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Merge pull request #5584 from SiliconLabs/feature/emlib-5.3.3 

Upgrade to Silicon Labs HAL
pull/5586/merge
Martin Kojtal 2017-11-30 18:09:04 +00:00 committed by GitHub
parent 969f8af386 1b0922e97b
commit 2b84a1742f
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
104 changed files with 12772 additions and 9196 deletions
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2
features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/inc/em_usb.h
View File

@ -45,8 +45,6 @@
#define EFM32_WEAK SL_WEAK
#define EFM32_ATTRIBUTE_SECTION(X) SL_ATTRIBUTE_SECTION(X)
#include "em_int.h"
#if defined( USB_USE_PRINTF )
#include <stdio.h>
#endif

87
features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/src/em_usbd.c
View File

@ -27,6 +27,7 @@
#if defined( USB_DEVICE )
#include "em_cmu.h"
#include "em_core.h"
#include "em_usbtypes.h"
#include "em_usbhal.h"
#include "em_usbd.h"
@ -69,9 +70,10 @@ static const char *stateNames[] =
******************************************************************************/
void USBD_AbortAllTransfers( void )
{
INT_Disable();
CORE_DECLARE_IRQ_STATE;
CORE_ENTER_CRITICAL();
USBDHAL_AbortAllTransfers( USB_STATUS_EP_ABORTED );
INT_Enable();
CORE_EXIT_CRITICAL();
}
/***************************************************************************//**
@ -85,6 +87,7 @@ int USBD_AbortTransfer( int epAddr )
{
USB_XferCompleteCb_TypeDef callback;
USBD_Ep_TypeDef *ep = USBD_GetEpFromAddr( epAddr );
CORE_DECLARE_IRQ_STATE;
if ( ep == NULL )
{
@ -100,10 +103,10 @@ int USBD_AbortTransfer( int epAddr )
return USB_STATUS_ILLEGAL;
}
INT_Disable();
CORE_ENTER_CRITICAL();
if ( ep->state == D_EP_IDLE )
{
INT_Enable();
CORE_EXIT_CRITICAL();
return USB_STATUS_OK;
}
@ -125,7 +128,7 @@ int USBD_AbortTransfer( int epAddr )
callback( USB_STATUS_EP_ABORTED, ep->xferred, ep->remaining );
}
INT_Enable();
CORE_EXIT_CRITICAL();
return USB_STATUS_OK;
}
@ -139,9 +142,10 @@ int USBD_AbortTransfer( int epAddr )
******************************************************************************/
void USBD_Connect( void )
{
INT_Disable();
CORE_DECLARE_IRQ_STATE;
CORE_ENTER_CRITICAL();
USBDHAL_Connect();
INT_Enable();
CORE_EXIT_CRITICAL();
}
/***************************************************************************//**
@ -154,9 +158,10 @@ void USBD_Connect( void )
******************************************************************************/
void USBD_Disconnect( void )
{
INT_Disable();
CORE_DECLARE_IRQ_STATE;
CORE_ENTER_CRITICAL();
USBDHAL_Disconnect();
INT_Enable();
CORE_EXIT_CRITICAL();
}
/***************************************************************************//**
@ -239,6 +244,7 @@ const char *USBD_GetUsbStateName( USBD_State_TypeDef state )
int USBD_Init( const USBD_Init_TypeDef *p )
{
USBD_Ep_TypeDef *ep;
CORE_DECLARE_IRQ_STATE;
#if !defined( USB_CORECLK_HFRCO ) || !defined( CMU_OSCENCMD_USHFRCOEN )
/* Devices supporting crystal-less USB can use HFRCO or HFXO as core clock. */
@ -308,7 +314,7 @@ int USBD_Init( const USBD_Init_TypeDef *p )
*/
totalRxFifoSize += 10 + 1 + ( 2 * (MAX_NUM_OUT_EPS + 1) );
INT_Disable();
CORE_ENTER_CRITICAL();
/* Enable USB clock */
CMU->HFCORECLKEN0 |= CMU_HFCORECLKEN0_USB | CMU_HFCORECLKEN0_USBC;
@ -339,7 +345,7 @@ int USBD_Init( const USBD_Init_TypeDef *p )
}
else
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Init(), FIFO setup error" );
EFM_ASSERT( false );
return USB_STATUS_ILLEGAL;
@ -356,7 +362,7 @@ int USBD_Init( const USBD_Init_TypeDef *p )
USBD_SetUsbState( USBD_STATE_NONE );
}
INT_Enable();
CORE_EXIT_CRITICAL();
return USB_STATUS_OK;
}
@ -389,6 +395,7 @@ int USBD_Init( const USBD_Init_TypeDef *p )
int USBD_Read( int epAddr, void *data, int byteCount,
USB_XferCompleteCb_TypeDef callback )
{
CORE_DECLARE_IRQ_STATE;
USBD_Ep_TypeDef *ep = USBD_GetEpFromAddr( epAddr );
USB_PRINTF("USBD: Read addr %x, data %p, size %d, cb 0x%lx\n",
@ -416,24 +423,25 @@ int USBD_Read( int epAddr, void *data, int byteCount,
return USB_STATUS_ILLEGAL;
}
INT_Disable();
CORE_ENTER_CRITICAL();
if ( USBDHAL_EpIsStalled( ep ) )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Read(), Endpoint is halted" );
return USB_STATUS_EP_STALLED;
}
if ( ep->state != D_EP_IDLE )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Read(), Endpoint is busy" );
return USB_STATUS_EP_BUSY;
}
if ( ( ep->num > 0 ) && ( USBD_GetUsbState() != USBD_STATE_CONFIGURED ) )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Read(), Device not configured" );
return USB_STATUS_DEVICE_UNCONFIGURED;
}
@ -448,7 +456,7 @@ int USBD_Read( int epAddr, void *data, int byteCount,
}
else if ( ep->in != false )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Read(), Illegal EP direction" );
EFM_ASSERT( false );
return USB_STATUS_ILLEGAL;
@ -458,7 +466,7 @@ int USBD_Read( int epAddr, void *data, int byteCount,
ep->xferCompleteCb = callback;
USBD_ArmEp( ep );
INT_Enable();
CORE_EXIT_CRITICAL();
return USB_STATUS_OK;
}
@ -477,22 +485,26 @@ int USBD_Read( int epAddr, void *data, int byteCount,
******************************************************************************/
int USBD_RemoteWakeup( void )
{
INT_Disable();
CORE_DECLARE_IRQ_STATE;
CORE_ENTER_CRITICAL();
if ( ( dev->state != USBD_STATE_SUSPENDED ) ||
( dev->remoteWakeupEnabled == false ) )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_RemoteWakeup(), Illegal remote wakeup" );
return USB_STATUS_ILLEGAL;
}
USBDHAL_SetRemoteWakeup();
INT_Enable();
CORE_EXIT_CRITICAL();
USBTIMER_DelayMs( 10 );
INT_Disable();
CORE_ENTER_CRITICAL();
USBDHAL_ClearRemoteWakeup();
INT_Enable();
CORE_EXIT_CRITICAL();
return USB_STATUS_OK;
}
@ -565,6 +577,7 @@ void USBD_SetUsbState( USBD_State_TypeDef newState )
int USBD_StallEp( int epAddr )
{
USB_Status_TypeDef retVal;
CORE_DECLARE_IRQ_STATE;
USBD_Ep_TypeDef *ep = USBD_GetEpFromAddr( epAddr );
if ( ep == NULL )
@ -581,9 +594,9 @@ int USBD_StallEp( int epAddr )
return USB_STATUS_ILLEGAL;
}
INT_Disable();
CORE_ENTER_CRITICAL();
retVal = USBDHAL_StallEp( ep );
INT_Enable();
CORE_EXIT_CRITICAL();
if ( retVal != USB_STATUS_OK )
{
@ -626,6 +639,7 @@ void USBD_Stop( void )
int USBD_UnStallEp( int epAddr )
{
USB_Status_TypeDef retVal;
CORE_DECLARE_IRQ_STATE;
USBD_Ep_TypeDef *ep = USBD_GetEpFromAddr( epAddr );
if ( ep == NULL )
@ -642,9 +656,9 @@ int USBD_UnStallEp( int epAddr )
return USB_STATUS_ILLEGAL;
}
INT_Disable();
CORE_ENTER_CRITICAL();
retVal = USBDHAL_UnStallEp( ep );
INT_Enable();
CORE_EXIT_CRITICAL();
if ( retVal != USB_STATUS_OK )
{
@ -678,6 +692,7 @@ int USBD_Write( int epAddr, void *data, int byteCount,
USB_XferCompleteCb_TypeDef callback )
{
USBD_Ep_TypeDef *ep = USBD_GetEpFromAddr( epAddr );
CORE_DECLARE_IRQ_STATE;
USB_PRINTF("USBD: Write addr %x, data %p, size %d, cb 0x%lx\n",
epAddr, data, byteCount, (uint32_t)callback);
@ -704,24 +719,25 @@ int USBD_Write( int epAddr, void *data, int byteCount,
return USB_STATUS_ILLEGAL;
}
INT_Disable();
CORE_ENTER_CRITICAL();
if ( USBDHAL_EpIsStalled( ep ) )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Write(), Endpoint is halted" );
return USB_STATUS_EP_STALLED;
}
if ( ep->state != D_EP_IDLE )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Write(), Endpoint is busy" );
return USB_STATUS_EP_BUSY;
}
if ( ( ep->num > 0 ) && ( USBD_GetUsbState() != USBD_STATE_CONFIGURED ) )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Write(), Device not configured" );
return USB_STATUS_DEVICE_UNCONFIGURED;
}
@ -736,7 +752,7 @@ int USBD_Write( int epAddr, void *data, int byteCount,
}
else if ( ep->in != true )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Write(), Illegal EP direction" );
EFM_ASSERT( false );
return USB_STATUS_ILLEGAL;
@ -746,7 +762,7 @@ int USBD_Write( int epAddr, void *data, int byteCount,
ep->xferCompleteCb = callback;
USBD_ArmEp( ep );
INT_Enable();
CORE_EXIT_CRITICAL();
return USB_STATUS_OK;
}
@ -841,6 +857,7 @@ static void USBD_ResetEndpoints(void)
int USBD_AddEndpoint(int epAddr, int transferType,
int maxPacketSize, int bufferMult)
{
CORE_DECLARE_IRQ_STATE;
USBD_Ep_TypeDef *ep;
numEps++;
@ -890,7 +907,7 @@ int USBD_AddEndpoint(int epAddr, int transferType,
ep->num, numEps, ep->in, ep->addr, ep->type, ep->packetSize, ep->fifoSize,
totalTxFifoSize, totalRxFifoSize);
INT_Disable();
CORE_ENTER_CRITICAL();
#if defined( CMU_OSCENCMD_USHFRCOEN )
/* Happy Gecko workaround: disable LEM GATE mode if using ISOC endpoints. */
if ( transferType == USB_EPTYPE_ISOC )
@ -900,7 +917,7 @@ int USBD_AddEndpoint(int epAddr, int transferType,
#endif
int ret = USBDHAL_ReconfigureFifos(totalRxFifoSize, totalTxFifoSize);
INT_Enable();
CORE_EXIT_CRITICAL();
if( ret != USB_STATUS_OK ) {
return ret;

8
features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/src/em_usbdint.c
View File

@ -27,6 +27,7 @@
#if defined( USB_DEVICE )
#include "em_cmu.h"
#include "em_core.h"
#include "em_usbtypes.h"
#include "em_usbhal.h"
#include "em_usbd.h"
@ -106,8 +107,9 @@ void USB_IRQHandler( void )
{
uint32_t status;
bool servedVbusInterrupt = false;
CORE_DECLARE_IRQ_STATE;
INT_Disable();
CORE_ENTER_CRITICAL();
#if ( USB_PWRSAVE_MODE )
if ( USBD_poweredDown )
@ -192,7 +194,7 @@ void USB_IRQHandler( void )
status = USBHAL_GetCoreInts();
if ( status == 0 )
{
INT_Enable();
CORE_EXIT_CRITICAL();
if ( !servedVbusInterrupt )
{
DEBUG_USB_INT_LO_PUTS( "\nSinT" );
@ -209,7 +211,7 @@ void USB_IRQHandler( void )
HANDLE_INT( USB_GINTSTS_IEPINT )
HANDLE_INT( USB_GINTSTS_OEPINT )
INT_Enable();
CORE_EXIT_CRITICAL();
if ( status != 0 )
{

4
features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/src/em_usbhal.c
View File

@ -199,9 +199,7 @@ USB_Status_TypeDef USBDHAL_CoreInit( uint32_t totalRxFifoSize,
USB_GUSBCFG_FORCEDEVMODE;
#endif
INT_Enable();
USBTIMER_DelayMs( 50 );
INT_Disable();
/* Set device speed */
USB->DCFG = ( USB->DCFG & ~_USB_DCFG_DEVSPD_MASK ) | 3; /* Full speed PHY */
@ -649,9 +647,7 @@ USB_Status_TypeDef USBHHAL_CoreInit( uint32_t rxFifoSize,
~(GUSBCFG_WO_BITMASK | USB_GUSBCFG_FORCEDEVMODE ) ) |
USB_GUSBCFG_FORCEHSTMODE;
INT_Enable();
USBTIMER_DelayMs( 100 );
INT_Disable();
/* Set 48 MHz PHY clock, FS/LS mode */
USB->HCFG = ( USB->HCFG & ~_USB_HCFG_FSLSPCLKSEL_MASK ) |

18
features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/src/em_usbtimer.c
View File

@ -25,6 +25,7 @@
#include "em_usb.h"
#if defined( USB_DEVICE ) || defined( USB_HOST )
#include "em_cmu.h"
#include "em_core.h"
#include "em_timer.h"
#include "em_usbtypes.h"
#include "em_usbhal.h"
@ -244,8 +245,9 @@ void USBTIMER_Start( uint32_t id, uint32_t timeout,
{
uint32_t accumulated;
USBTIMER_Timer_TypeDef *this, **last;
CORE_DECLARE_IRQ_STATE;
INT_Disable();
CORE_ENTER_CRITICAL();
if ( timers[ id ].running )
{
@ -255,7 +257,7 @@ void USBTIMER_Start( uint32_t id, uint32_t timeout,
if ( timeout == 0 )
{
callback();
INT_Enable();
CORE_EXIT_CRITICAL();
return;
}
@ -297,7 +299,7 @@ void USBTIMER_Start( uint32_t id, uint32_t timeout,
}
}
INT_Enable();
CORE_EXIT_CRITICAL();
}
/***************************************************************************//**
@ -310,8 +312,9 @@ void USBTIMER_Start( uint32_t id, uint32_t timeout,
void USBTIMER_Stop( uint32_t id )
{
USBTIMER_Timer_TypeDef *this, **last;
CORE_DECLARE_IRQ_STATE;
INT_Disable();
CORE_ENTER_CRITICAL();
if ( head ) /* Queue empty ? */
{
@ -335,7 +338,7 @@ void USBTIMER_Stop( uint32_t id )
}
}
INT_Enable();
CORE_EXIT_CRITICAL();
}
#endif /* ( NUM_QTIMERS > 0 ) */
@ -347,8 +350,9 @@ void USBTIMER_Stop( uint32_t id )
static void TimerTick( void )
{
USBTIMER_Callback_TypeDef cb;
CORE_DECLARE_IRQ_STATE;
INT_Disable();
CORE_ENTER_CRITICAL();
if ( head )
{
@ -372,7 +376,7 @@ static void TimerTick( void )
}
}
INT_Enable();
CORE_EXIT_CRITICAL();
}
/** @endcond */
#endif /* ( NUM_QTIMERS > 0 ) */

4
targets/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c
View File

@ -40,10 +40,10 @@ void analogin_init(analogin_t *obj, PinName pin)
/* Init structure */
obj->adc = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT((int) obj->adc != NC);
MBED_ASSERT((unsigned int) obj->adc != NC);
obj->channel = pin_location(pin, PinMap_ADC);
MBED_ASSERT((int) obj->channel != NC);
MBED_ASSERT((unsigned int) obj->channel != NC);
/* Only initialize the ADC once */
if (!adc_initialized) {

8
targets/TARGET_Silicon_Labs/TARGET_EFM32/analogout_api.c
View File

@ -41,11 +41,11 @@ void analogout_init(dac_t *obj, PinName pin)
{
/* init in-memory structure */
obj->dac = (DAC_TypeDef *) pinmap_peripheral(pin, PinMap_DAC);
MBED_ASSERT((int) obj->dac != NC);
MBED_ASSERT((unsigned int) obj->dac != NC);
obj->channel = pin_location(pin, PinMap_DAC);
MBED_ASSERT((int) obj->channel != NC);
MBED_ASSERT((unsigned int) obj->channel != NC);
pin_mode(pin, Disabled);
if (!dac_initialized) {
@ -78,7 +78,7 @@ void analogout_free(dac_t *obj)
DAC_InitChannel_TypeDef initChannel = DAC_INITCHANNEL_DEFAULT;
initChannel.enable = false;
DAC_InitChannel(obj->dac, &initChannel, obj->channel);
//Check all channels to see if we can disable the DAC completely
if((DAC0->CH0CTRL & DAC_CH0CTRL_EN) == 0 && (DAC0->CH1CTRL & DAC_CH1CTRL_EN) == 0) {
CMU_ClockEnable(cmuClock_DAC0, false);

2
targets/TARGET_Silicon_Labs/TARGET_EFM32/common/CommonPinNames.h
View File

@ -41,7 +41,7 @@
PI0 = 8 << 4, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, \
PJ0 = 9 << 4, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, \
PK0 = 10 << 4, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, \
NC = (int) 0xFFFFFFFF
NC = (unsigned int) 0xFFFFFFFFUL
#ifdef __cplusplus
extern "C" {

2
targets/TARGET_Silicon_Labs/TARGET_EFM32/dma_api_HAL.h
View File

@ -45,6 +45,7 @@ extern "C" {
#define DMA_CAP_2DCOPY (1 << 0)
#define DMA_CAP_NONE (0 << 0)
#ifdef DMA_PRESENT
#if ( DMA_CHAN_COUNT <= 4 )
#define DMACTRL_CH_CNT 4
#define DMACTRL_ALIGNMENT 256
@ -60,6 +61,7 @@ extern "C" {
#else
#error "Unsupported DMA channel count (dma_api.c)."
#endif
#endif
#ifdef LDMA_PRESENT
typedef void (*LDMAx_CBFunc_t)(unsigned int channel, bool primary, void *user);

63
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt
View File

@ -1,4 +1,67 @@
================ Revision history ============================================
5.3.3
- em_cmu: 48 MHz HFRCO band selectable for devices that support it.
- em_emu: Added macro guards for BU mode functionality for series 0 devices.
5.3.2
- No changes.
5.3.1
- em_opamp: Corrected reload of default calibration trims in OPAMP_Enable()
for Series 0.
- em_core: Fixed invalid parameter in CORE_YIELD_CRITICAL and
CORE_YIELD_ATOMIC macros.
5.3.0
- em_chip: Updated PLFRCO tuning values.
- em_can: Fixed ID filter mask bug.
- em_gpio: Doc updates.
- em_gpio: Fixed bug in GPIO pin validation to enable PD9 on BGM121 modules.
- em_ldma: Added missing signals for EFM32GG11.
5.2.2:
- em_emu: Fixed bug in EMU_EM4Init(), The BUBODRSTDIS field was not initialized
as specified in function input parameters.
5.2.1:
- em_emu: Fixed a problem with handling of DCDC bypass current limiter
that may cause brownout reset.
- em_chip: Added workaround for errata DCDC-E206 for EFR32xG1x devices.
- em_cmu: Fixed handling of HFCLKLE prescaling at frequencies above 64 MHz.
5.2.0:
- em_cmu: Added flash wait state handling for all devices that can scale down
the voltage.
- em_adc: Fixed bug where ADC SINGLECTRLX register fields VREFSEL, PRSSEL and
FIFOOFACT was not cleared when calling ADC_InitSingle().
- em_msc: Removed call to SystemCoreClockGet() in MSC_Init.
- em_msc: MSC_WriteWordFast() can now only be used when executing code from
RAM on parts that include a flash write buffer.
- em_emu: Using VMON calibration values to set voltage thresholds when
calling EMU_VmonInit() and EMU_VmonHystInit(). The DI page contains
calibration values for 1.86 V and 2.98 V for each VMON channel. Updated
VMON supported voltage range to 1.62V-3.4V.
- em_emu: Added EMU_Save() and changed EMU_EnterEM2() and EMU_EnterEM3()
to only save the state if the restore parameter is true.
- em_usart: Fixed USART async baudrate calculation for EFM32HG devices.
The extra fractional bits in the CLKDIV register was not used.
- Added support for EFM32GG11B devices. This includes new modules for
Quad SPI (em_qspi) and CAN (em_can). This also includes
changes to other emlib modules in order to support the changes in the
register interface of the new device.
- em_cmu: Added DPLL support. Added support for asynchronous clocks for
ADC, reference clocks for QSPI and SDIO and USB rate clock. Added
functions to support the USHFRCO and clock select for HFXOX2.
- em_gpio: Using single cycle set and clear of DOUT on platforms
where this is supported.
- em_lesense: Added configuration of DACCHnEN and DACSTARTUP bits in
LESENSE->PERCTRL in LESENSE_Init() and init struct. Also changed
default values for LESENSE_AltExDesc_TypeDef and
LESENSE_ChDesc_TypeDef to be disabled by default.
5.1.3:
- No changes.
5.1.2:
Misc. bugfixes and improvements.

231
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_acmp.h
* @brief Analog Comparator (ACMP) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -95,8 +95,7 @@ extern "C" {
/** Resistor values used for the internal capacative sense resistor. See the
* datasheet for your device for details on each resistor value. */
typedef enum
{
typedef enum {
acmpResistor0 = _ACMP_INPUTSEL_CSRESSEL_RES0, /**< Resistor value 0 */
acmpResistor1 = _ACMP_INPUTSEL_CSRESSEL_RES1, /**< Resistor value 1 */
acmpResistor2 = _ACMP_INPUTSEL_CSRESSEL_RES2, /**< Resistor value 2 */
@ -111,8 +110,7 @@ typedef enum
/** Hysteresis level. See datasheet for your device for details on each
* level. */
typedef enum
{
typedef enum {
#if defined(_ACMP_CTRL_HYSTSEL_MASK)
acmpHysteresisLevel0 = _ACMP_CTRL_HYSTSEL_HYST0, /**< Hysteresis level 0 */
acmpHysteresisLevel1 = _ACMP_CTRL_HYSTSEL_HYST1, /**< Hysteresis level 1 */
@ -146,8 +144,7 @@ typedef enum
#if defined(_ACMP_CTRL_WARMTIME_MASK)
/** ACMP warmup time. The delay is measured in HFPERCLK cycles and should
* be at least 10 us. */
typedef enum
{
typedef enum {
/** 4 HFPERCLK cycles warmup */
acmpWarmTime4 = _ACMP_CTRL_WARMTIME_4CYCLES,
/** 8 HFPERCLK cycles warmup */
@ -171,8 +168,7 @@ typedef enum
/**
* Adjust performance of the ACMP for a given input voltage range
*/
typedef enum
{
typedef enum {
acmpInputRangeFull = _ACMP_CTRL_INPUTRANGE_FULL, /**< Input can be from 0 to Vdd */
acmpInputRangeHigh = _ACMP_CTRL_INPUTRANGE_GTVDDDIV2, /**< Input will always be greater than Vdd/2 */
acmpInputRangeLow = _ACMP_CTRL_INPUTRANGE_LTVDDDIV2 /**< Input will always be less than Vdd/2 */
@ -183,12 +179,11 @@ typedef enum
/**
* ACMP Power source.
*/
typedef enum
{
acmpPowerSourceAvdd = _ACMP_CTRL_PWRSEL_AVDD, /**< Power the ACMP using the AVDD supply */
acmpPowerSourceVddVreg = _ACMP_CTRL_PWRSEL_VREGVDD, /**< Power the ACMP using the VREGVDD supply */
acmpPowerSourceIOVdd0 = _ACMP_CTRL_PWRSEL_IOVDD0, /**< Power the ACMP using the IOVDD/IOVDD0 supply */
acmpPowerSourceIOVdd1 = _ACMP_CTRL_PWRSEL_IOVDD1, /**< Power the ACMP using the IOVDD1 supply (if part has two I/O voltages) */
typedef enum {
acmpPowerSourceAvdd = _ACMP_CTRL_PWRSEL_AVDD, /**< Power the ACMP using the AVDD supply */
acmpPowerSourceVddVreg = _ACMP_CTRL_PWRSEL_VREGVDD, /**< Power the ACMP using the VREGVDD supply */
acmpPowerSourceIOVdd0 = _ACMP_CTRL_PWRSEL_IOVDD0, /**< Power the ACMP using the IOVDD/IOVDD0 supply */
acmpPowerSourceIOVdd1 = _ACMP_CTRL_PWRSEL_IOVDD1, /**< Power the ACMP using the IOVDD1 supply (if part has two I/O voltages) */
} ACMP_PowerSource_TypeDef;
#endif
@ -196,8 +191,7 @@ typedef enum
/**
* ACMP accuracy mode.
*/
typedef enum
{
typedef enum {
acmpAccuracyLow = _ACMP_CTRL_ACCURACY_LOW, /**< Low-accuracy mode but consume less current */
acmpAccuracyHigh = _ACMP_CTRL_ACCURACY_HIGH /**< High-accuracy mode but consume more current */
} ACMP_Accuracy_TypeDef;
@ -206,8 +200,7 @@ typedef enum
#if defined(_ACMP_INPUTSEL_VASEL_MASK)
/** ACMP Input to the VA divider. This enum is used to select the input for
* the VA Divider */
typedef enum
{
typedef enum {
acmpVAInputVDD = _ACMP_INPUTSEL_VASEL_VDD,
acmpVAInputAPORT2YCH0 = _ACMP_INPUTSEL_VASEL_APORT2YCH0,
acmpVAInputAPORT2YCH2 = _ACMP_INPUTSEL_VASEL_APORT2YCH2,
@ -265,8 +258,7 @@ typedef enum
* ACMP Input to the VB divider. This enum is used to select the input for
* the VB divider.
*/
typedef enum
{
typedef enum {
acmpVBInput1V25 = _ACMP_INPUTSEL_VBSEL_1V25,
acmpVBInput2V5 = _ACMP_INPUTSEL_VBSEL_2V5
} ACMP_VBInput_TypeDef;
@ -276,8 +268,7 @@ typedef enum
/**
* ACMP Low-Power Input Selection.
*/
typedef enum
{
typedef enum {
acmpVLPInputVADIV = _ACMP_INPUTSEL_VLPSEL_VADIV,
acmpVLPInputVBDIV = _ACMP_INPUTSEL_VLPSEL_VBDIV
} ACMP_VLPInput_Typedef;
@ -285,8 +276,7 @@ typedef enum
#if defined(_ACMP_INPUTSEL_POSSEL_APORT0XCH0)
/** ACMP Input Selection */
typedef enum
{
typedef enum {
acmpInputAPORT0XCH0 = _ACMP_INPUTSEL_POSSEL_APORT0XCH0,
acmpInputAPORT0XCH1 = _ACMP_INPUTSEL_POSSEL_APORT0XCH1,
acmpInputAPORT0XCH2 = _ACMP_INPUTSEL_POSSEL_APORT0XCH2,
@ -462,8 +452,7 @@ typedef enum
#else
/** ACMP inputs. Note that scaled VDD and bandgap references can only be used
* as negative inputs. */
typedef enum
{
typedef enum {
/** Channel 0 */
acmpChannel0 = _ACMP_INPUTSEL_NEGSEL_CH0,
/** Channel 1 */
@ -510,8 +499,7 @@ typedef enum
* used by an external module like LESENSE when it's taking control over
* the ACMP input.
*/
typedef enum
{
typedef enum {
acmpExternalInputAPORT0X = _ACMP_EXTIFCTRL_APORTSEL_APORT0X,
acmpExternalInputAPORT0Y = _ACMP_EXTIFCTRL_APORTSEL_APORT0Y,
acmpExternalInputAPORT1X = _ACMP_EXTIFCTRL_APORTSEL_APORT1X,
@ -534,8 +522,7 @@ typedef enum
******************************************************************************/
/** Capsense initialization structure. */
typedef struct
{
typedef struct {
/** Full bias current. See the ACMP chapter about bias and response time in
* the reference manual for details. */
bool fullBias;
@ -607,47 +594,46 @@ typedef struct
/** Default config for capacitive sense mode initialization. */
#if defined(_ACMP_HYSTERESIS0_HYST_MASK)
#define ACMP_CAPSENSE_INIT_DEFAULT \
{ \
false, /* Don't use fullBias to lower power consumption */ \
0x20, /* Using biasProg value of 0x20 (32) */ \
acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 0 */ \
acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 1 */ \
acmpResistor5, /* Use internal resistor value 5 */ \
0x30, /* VDD level high */ \
0x10, /* VDD level low */ \
true /* Enable after init. */ \
}
#define ACMP_CAPSENSE_INIT_DEFAULT \
{ \
false, /* Don't use fullBias to lower power consumption */ \
0x20, /* Using biasProg value of 0x20 (32) */ \
acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 0 */ \
acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 1 */ \
acmpResistor5, /* Use internal resistor value 5 */ \
0x30, /* VDD level high */ \
0x10, /* VDD level low */ \
true /* Enable after init. */ \
}
#elif defined(_ACMP_CTRL_WARMTIME_MASK)
#define ACMP_CAPSENSE_INIT_DEFAULT \
{ \
false, /* fullBias */ \
false, /* halfBias */ \
0x7, /* biasProg */ \
acmpWarmTime512, /* 512 cycle warmup to be safe */ \
acmpHysteresisLevel5, \
acmpResistor3, \
false, /* low power reference */ \
0x3D, /* VDD level */ \
true /* Enable after init. */ \
}
{ \
false, /* fullBias */ \
false, /* halfBias */ \
0x7, /* biasProg */ \
acmpWarmTime512, /* 512 cycle warmup to be safe */ \
acmpHysteresisLevel5, \
acmpResistor3, \
false, /* low power reference */ \
0x3D, /* VDD level */ \
true /* Enable after init. */ \
}
#else
#define ACMP_CAPSENSE_INIT_DEFAULT \
{ \
false, /* fullBias */ \
false, /* halfBias */ \
0x7, /* biasProg */ \
acmpHysteresisLevel5, \
acmpResistor3, \
false, /* low power reference */ \
0x3D, /* VDD level */ \
true /* Enable after init. */ \
}
#define ACMP_CAPSENSE_INIT_DEFAULT \
{ \
false, /* fullBias */ \
false, /* halfBias */ \
0x7, /* biasProg */ \
acmpHysteresisLevel5, \
acmpResistor3, \
false, /* low power reference */ \
0x3D, /* VDD level */ \
true /* Enable after init. */ \
}
#endif
/** ACMP initialization structure. */
typedef struct
{
typedef struct {
/** Full bias current. See the ACMP chapter about bias and response time in
* the reference manual for details. */
bool fullBias;
@ -731,56 +717,55 @@ typedef struct
/** Default config for ACMP regular initialization. */
#if defined(_ACMP_HYSTERESIS0_HYST_MASK)
#define ACMP_INIT_DEFAULT \
{ \
false, /* fullBias */ \
0x7, /* biasProg */ \
false, /* No interrupt on falling edge. */ \
false, /* No interrupt on rising edge. */ \
acmpInputRangeFull, /* Input range from 0 to Vdd. */ \
acmpAccuracyLow, /* Low accuracy, less current usage. */ \
acmpPowerSourceAvdd, /* Use the AVDD supply. */ \
acmpHysteresisLevel5, /* Use hysteresis level 5 when output is 0 */ \
acmpHysteresisLevel5, /* Use hysteresis level 5 when output is 1 */ \
acmpVLPInputVADIV, /* Use VADIV as the VLP input source. */ \
false, /* Output 0 when ACMP is inactive. */ \
true /* Enable after init. */ \
}
{ \
false, /* fullBias */ \
0x7, /* biasProg */ \
false, /* No interrupt on falling edge. */ \
false, /* No interrupt on rising edge. */ \
acmpInputRangeFull, /* Input range from 0 to Vdd. */ \
acmpAccuracyLow, /* Low accuracy, less current usage. */ \
acmpPowerSourceAvdd, /* Use the AVDD supply. */ \
acmpHysteresisLevel5, /* Use hysteresis level 5 when output is 0 */ \
acmpHysteresisLevel5, /* Use hysteresis level 5 when output is 1 */ \
acmpVLPInputVADIV, /* Use VADIV as the VLP input source. */ \
false, /* Output 0 when ACMP is inactive. */ \
true /* Enable after init. */ \
}
#elif defined(_ACMP_CTRL_WARMTIME_MASK)
#define ACMP_INIT_DEFAULT \
{ \
false, /* fullBias */ \
false, /* halfBias */ \
0x7, /* biasProg */ \
false, /* No interrupt on falling edge. */ \
false, /* No interrupt on rising edge. */ \
acmpWarmTime512, /* 512 cycle warmup to be safe */ \
acmpHysteresisLevel5, \
false, /* Disabled emitting inactive value during warmup. */ \
false, /* low power reference */ \
0x3D, /* VDD level */ \
true /* Enable after init. */ \
}
{ \
false, /* fullBias */ \
false, /* halfBias */ \
0x7, /* biasProg */ \
false, /* No interrupt on falling edge. */ \
false, /* No interrupt on rising edge. */ \
acmpWarmTime512, /* 512 cycle warmup to be safe */ \
acmpHysteresisLevel5, \
false, /* Disabled emitting inactive value during warmup. */ \
false, /* low power reference */ \
0x3D, /* VDD level */ \
true /* Enable after init. */ \
}
#else
#define ACMP_INIT_DEFAULT \
{ \
false, /* fullBias */ \
false, /* halfBias */ \
0x7, /* biasProg */ \
false, /* No interrupt on falling edge. */ \
false, /* No interrupt on rising edge. */ \
acmpHysteresisLevel5, \
false, /* Disabled emitting inactive value during warmup. */ \
false, /* low power reference */ \
0x3D, /* VDD level */ \
true /* Enable after init. */ \
}
{ \
false, /* fullBias */ \
false, /* halfBias */ \
0x7, /* biasProg */ \
false, /* No interrupt on falling edge. */ \
false, /* No interrupt on rising edge. */ \
acmpHysteresisLevel5, \
false, /* Disabled emitting inactive value during warmup. */ \
false, /* low power reference */ \
0x3D, /* VDD level */ \
true /* Enable after init. */ \
}
#endif
#if defined(_ACMP_INPUTSEL_VASEL_MASK)
/** VA Configuration structure. This struct is used to configure the
* VA voltage input source and it's dividers. */
typedef struct
{
typedef struct {
ACMP_VAInput_TypeDef input; /**< VA voltage input source */
/**
@ -802,19 +787,18 @@ typedef struct
uint32_t div1;
} ACMP_VAConfig_TypeDef;
#define ACMP_VACONFIG_DEFAULT \
{ \
acmpVAInputVDD, /* Use Vdd as VA voltage input source */ \
63, /* No division of the VA source when ACMP output is 0 */ \
63, /* No division of the VA source when ACMP output is 1 */ \
}
#define ACMP_VACONFIG_DEFAULT \
{ \
acmpVAInputVDD, /* Use Vdd as VA voltage input source */ \
63, /* No division of the VA source when ACMP output is 0 */ \
63, /* No division of the VA source when ACMP output is 1 */ \
}
#endif
#if defined(_ACMP_INPUTSEL_VBSEL_MASK)
/** VB Configuration structure. This struct is used to configure the
* VB voltage input source and it's dividers. */
typedef struct
{
typedef struct {
ACMP_VBInput_TypeDef input; /**< VB Voltage input source */
/**
@ -837,11 +821,11 @@ typedef struct
} ACMP_VBConfig_TypeDef;
#define ACMP_VBCONFIG_DEFAULT \
{ \
acmpVBInput1V25, /* Use 1.25 V as VB voltage input source */ \
63, /* No division of the VB source when ACMP output is 0 */ \
63, /* No division of the VB source when ACMP output is 1 */ \
}
{ \
acmpVBInput1V25, /* Use 1.25 V as VB voltage input source */ \
63, /* No division of the VB source when ACMP output is 0 */ \
63, /* No division of the VB source when ACMP output is 1 */ \
}
#endif
/*******************************************************************************
@ -883,7 +867,6 @@ __STATIC_INLINE void ACMP_IntClear(ACMP_TypeDef *acmp, uint32_t flags)
acmp->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more ACMP interrupts.
@ -901,7 +884,6 @@ __STATIC_INLINE void ACMP_IntDisable(ACMP_TypeDef *acmp, uint32_t flags)
acmp->IEN &= ~(flags);
}
/***************************************************************************//**
* @brief
* Enable one or more ACMP interrupts.
@ -924,7 +906,6 @@ __STATIC_INLINE void ACMP_IntEnable(ACMP_TypeDef *acmp, uint32_t flags)
acmp->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending ACMP interrupt flags.
@ -945,7 +926,6 @@ __STATIC_INLINE uint32_t ACMP_IntGet(ACMP_TypeDef *acmp)
return acmp->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending ACMP interrupt flags.
@ -977,7 +957,6 @@ __STATIC_INLINE uint32_t ACMP_IntGetEnabled(ACMP_TypeDef *acmp)
return acmp->IF & tmp;
}
/***************************************************************************//**
* @brief
* Set one or more pending ACMP interrupts from SW.

381
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_adc.h
* @brief Analog to Digital Converter (ADC) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -34,7 +34,7 @@
#define EM_ADC_H
#include "em_device.h"
#if defined( ADC_COUNT ) && ( ADC_COUNT > 0 )
#if defined(ADC_COUNT) && (ADC_COUNT > 0)
#include <stdbool.h>
@ -57,8 +57,7 @@ extern "C" {
******************************************************************************/
/** Acquisition time (in ADC clock cycles). */
typedef enum
{
typedef enum {
adcAcqTime1 = _ADC_SINGLECTRL_AT_1CYCLE, /**< 1 clock cycle. */
adcAcqTime2 = _ADC_SINGLECTRL_AT_2CYCLES, /**< 2 clock cycles. */
adcAcqTime4 = _ADC_SINGLECTRL_AT_4CYCLES, /**< 4 clock cycles. */
@ -70,10 +69,9 @@ typedef enum
adcAcqTime256 = _ADC_SINGLECTRL_AT_256CYCLES /**< 256 clock cycles. */
} ADC_AcqTime_TypeDef;
#if defined( _ADC_CTRL_LPFMODE_MASK )
#if defined(_ADC_CTRL_LPFMODE_MASK)
/** Lowpass filter mode. */
typedef enum
{
typedef enum {
/** No filter or decoupling capacitor. */
adcLPFilterBypass = _ADC_CTRL_LPFMODE_BYPASS,
@ -86,8 +84,7 @@ typedef enum
#endif
/** Oversample rate select. */
typedef enum
{
typedef enum {
/** 2 samples per conversion result. */
adcOvsRateSel2 = _ADC_CTRL_OVSRSEL_X2,
@ -125,37 +122,35 @@ typedef enum
adcOvsRateSel4096 = _ADC_CTRL_OVSRSEL_X4096
} ADC_OvsRateSel_TypeDef;
/** Peripheral Reflex System signal used to trigger single sample. */
typedef enum
{
#if defined( _ADC_SINGLECTRL_PRSSEL_MASK )
typedef enum {
#if defined(_ADC_SINGLECTRL_PRSSEL_MASK)
adcPRSSELCh0 = _ADC_SINGLECTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
adcPRSSELCh1 = _ADC_SINGLECTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
adcPRSSELCh2 = _ADC_SINGLECTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
adcPRSSELCh3 = _ADC_SINGLECTRL_PRSSEL_PRSCH3, /**< PRS channel 3. */
#if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH4 )
#if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH4)
adcPRSSELCh4 = _ADC_SINGLECTRL_PRSSEL_PRSCH4, /**< PRS channel 4. */
#endif
#if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH5 )
#if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH5)
adcPRSSELCh5 = _ADC_SINGLECTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */
#endif
#if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH6 )
#if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH6)
adcPRSSELCh6 = _ADC_SINGLECTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */
#endif
#if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH7 )
#if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH7)
adcPRSSELCh7 = _ADC_SINGLECTRL_PRSSEL_PRSCH7, /**< PRS channel 7. */
#endif
#if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH8 )
#if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH8)
adcPRSSELCh8 = _ADC_SINGLECTRL_PRSSEL_PRSCH8, /**< PRS channel 8. */
#endif
#if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH9 )
#if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH9)
adcPRSSELCh9 = _ADC_SINGLECTRL_PRSSEL_PRSCH9, /**< PRS channel 9. */
#endif
#if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH10 )
#if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH10)
adcPRSSELCh10 = _ADC_SINGLECTRL_PRSSEL_PRSCH10, /**< PRS channel 10. */
#endif
#if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH11 )
#if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH11)
adcPRSSELCh11 = _ADC_SINGLECTRL_PRSSEL_PRSCH11, /**< PRS channel 11. */
#endif
#elif defined(_ADC_SINGLECTRLX_PRSSEL_MASK)
@ -167,11 +162,19 @@ typedef enum
adcPRSSELCh5 = _ADC_SINGLECTRLX_PRSSEL_PRSCH5, /**< PRS channel 5. */
adcPRSSELCh6 = _ADC_SINGLECTRLX_PRSSEL_PRSCH6, /**< PRS channel 6. */
adcPRSSELCh7 = _ADC_SINGLECTRLX_PRSSEL_PRSCH7, /**< PRS channel 7. */
#if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH8)
adcPRSSELCh8 = _ADC_SINGLECTRLX_PRSSEL_PRSCH8, /**< PRS channel 8. */
#endif
#if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH9)
adcPRSSELCh9 = _ADC_SINGLECTRLX_PRSSEL_PRSCH9, /**< PRS channel 9. */
#endif
#if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH10)
adcPRSSELCh10 = _ADC_SINGLECTRLX_PRSSEL_PRSCH10, /**< PRS channel 10. */
#endif
#if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH11)
adcPRSSELCh11 = _ADC_SINGLECTRLX_PRSSEL_PRSCH11, /**< PRS channel 11. */
#if defined( _ADC_SINGLECTRLX_PRSSEL_PRSCH12 )
#endif
#if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH12)
adcPRSSELCh12 = _ADC_SINGLECTRLX_PRSSEL_PRSCH12, /**< PRS channel 12. */
adcPRSSELCh13 = _ADC_SINGLECTRLX_PRSSEL_PRSCH13, /**< PRS channel 13. */
adcPRSSELCh14 = _ADC_SINGLECTRLX_PRSSEL_PRSCH14, /**< PRS channel 14. */
@ -180,14 +183,12 @@ typedef enum
#endif
} ADC_PRSSEL_TypeDef;
/** Single and scan mode voltage references. Using unshifted enums and or
in ADC_CTRLX_VREFSEL_REG to select the extension register CTRLX_VREFSEL. */
#if defined( _ADC_SCANCTRLX_VREFSEL_MASK )
#if defined(_ADC_SCANCTRLX_VREFSEL_MASK)
#define ADC_CTRLX_VREFSEL_REG 0x80
#endif
typedef enum
{
typedef enum {
/** Internal 1.25V reference. */
adcRef1V25 = _ADC_SINGLECTRL_REF_1V25,
@ -197,12 +198,12 @@ typedef enum
/** Buffered VDD. */
adcRefVDD = _ADC_SINGLECTRL_REF_VDD,
#if defined( _ADC_SINGLECTRL_REF_5VDIFF )
#if defined(_ADC_SINGLECTRL_REF_5VDIFF)
/** Internal differential 5V reference. */
adcRef5VDIFF = _ADC_SINGLECTRL_REF_5VDIFF,
#endif
#if defined( _ADC_SINGLECTRL_REF_5V )
#if defined(_ADC_SINGLECTRL_REF_5V)
/** Internal 5V reference. */
adcRef5V = _ADC_SINGLECTRL_REF_5V,
#endif
@ -216,39 +217,39 @@ typedef enum
/** Unbuffered 2xVDD. */
adcRef2xVDD = _ADC_SINGLECTRL_REF_2XVDD,
#if defined( _ADC_SINGLECTRLX_VREFSEL_VBGR )
#if defined(_ADC_SINGLECTRLX_VREFSEL_VBGR)
/** Custom VFS: Internal Bandgap reference */
adcRefVBGR = _ADC_SINGLECTRLX_VREFSEL_VBGR | ADC_CTRLX_VREFSEL_REG,
#endif
#if defined( _ADC_SINGLECTRLX_VREFSEL_VDDXWATT )
#if defined(_ADC_SINGLECTRLX_VREFSEL_VDDXWATT)
/** Custom VFS: Scaled AVDD: AVDD * VREFATT */
adcRefVddxAtt = _ADC_SINGLECTRLX_VREFSEL_VDDXWATT | ADC_CTRLX_VREFSEL_REG,
#endif
#if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPWATT )
#if defined(_ADC_SINGLECTRLX_VREFSEL_VREFPWATT)
/** Custom VFS: Scaled singled ended external reference from pin 6:
VREFP * VREFATT */
adcRefVPxAtt = _ADC_SINGLECTRLX_VREFSEL_VREFPWATT | ADC_CTRLX_VREFSEL_REG,
#endif
#if defined( _ADC_SINGLECTRLX_VREFSEL_VREFP )
#if defined(_ADC_SINGLECTRLX_VREFSEL_VREFP)
/** Custom VFS: Raw single ended external reference from pin 6. */
adcRefP = _ADC_SINGLECTRLX_VREFSEL_VREFP | ADC_CTRLX_VREFSEL_REG,
#endif
#if defined( _ADC_SINGLECTRLX_VREFSEL_VENTROPY )
#if defined(_ADC_SINGLECTRLX_VREFSEL_VENTROPY)
/** Custom VFS: Special mode for entropy generation */
adcRefVEntropy = _ADC_SINGLECTRLX_VREFSEL_VENTROPY | ADC_CTRLX_VREFSEL_REG,
#endif
#if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT )
#if defined(_ADC_SINGLECTRLX_VREFSEL_VREFPNWATT)
/** Custom VFS: Scaled differential external Vref from pin 6 and 7:
(VREFP - VREFN) * VREFATT */
adcRefVPNxAtt = _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT | ADC_CTRLX_VREFSEL_REG,
#endif
#if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPN )
#if defined(_ADC_SINGLECTRLX_VREFSEL_VREFPN)
/** Custom VFS: Raw differential external Vref from pin 6 and 7:
VREFP - VREFN */
adcRefPN = _ADC_SINGLECTRLX_VREFSEL_VREFPN | ADC_CTRLX_VREFSEL_REG,
@ -257,26 +258,22 @@ typedef enum
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/* Deprecated enum names */
#if !defined( _ADC_SINGLECTRL_REF_5VDIFF )
#if !defined(_ADC_SINGLECTRL_REF_5VDIFF)
#define adcRef5VDIFF adcRef5V
#endif
/** @endcond */
/** Sample resolution. */
typedef enum
{
typedef enum {
adcRes12Bit = _ADC_SINGLECTRL_RES_12BIT, /**< 12 bit sampling. */
adcRes8Bit = _ADC_SINGLECTRL_RES_8BIT, /**< 8 bit sampling. */
adcRes6Bit = _ADC_SINGLECTRL_RES_6BIT, /**< 6 bit sampling. */
adcResOVS = _ADC_SINGLECTRL_RES_OVS /**< Oversampling. */
} ADC_Res_TypeDef;
#if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
#if defined(_ADC_SINGLECTRL_INPUTSEL_MASK)
/** Single sample input selection. */
typedef enum
{
typedef enum {
/* Differential mode disabled */
adcSingleInputCh0 = _ADC_SINGLECTRL_INPUTSEL_CH0, /**< Channel 0. */
adcSingleInputCh1 = _ADC_SINGLECTRL_INPUTSEL_CH1, /**< Channel 1. */
@ -329,10 +326,9 @@ typedef enum
/** @endcond */
#endif
#if defined( _ADC_SINGLECTRL_POSSEL_MASK )
#if defined(_ADC_SINGLECTRL_POSSEL_MASK)
/** Positive input selection for single and scan coversion. */
typedef enum
{
typedef enum {
adcPosSelAPORT0XCH0 = _ADC_SINGLECTRL_POSSEL_APORT0XCH0,
adcPosSelAPORT0XCH1 = _ADC_SINGLECTRL_POSSEL_APORT0XCH1,
adcPosSelAPORT0XCH2 = _ADC_SINGLECTRL_POSSEL_APORT0XCH2,
@ -494,6 +490,9 @@ typedef enum
adcPosSelAPORT4YCH30 = _ADC_SINGLECTRL_POSSEL_APORT4YCH30,
adcPosSelAPORT4XCH31 = _ADC_SINGLECTRL_POSSEL_APORT4XCH31,
adcPosSelAVDD = _ADC_SINGLECTRL_POSSEL_AVDD,
#if defined(_ADC_SINGLECTRL_POSSEL_BU)
adcPosSelBUVDD = _ADC_SINGLECTRL_POSSEL_BU,
#endif
adcPosSelDVDD = _ADC_SINGLECTRL_POSSEL_AREG,
adcPosSelPAVDD = _ADC_SINGLECTRL_POSSEL_VREGOUTPA,
adcPosSelDECOUPLE = _ADC_SINGLECTRL_POSSEL_PDBU,
@ -513,14 +512,11 @@ typedef enum
#define adcPosSelVREGOUTPA adcPosSelPAVDD
#define adcPosSelAREG adcPosSelDVDD
#define adcPosSelPDBU adcPosSelDECOUPLE
#endif
#if defined( _ADC_SINGLECTRL_NEGSEL_MASK )
#if defined(_ADC_SINGLECTRL_NEGSEL_MASK)
/** Negative input selection for single and scan coversion. */
typedef enum
{
typedef enum {
adcNegSelAPORT0XCH0 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH0,
adcNegSelAPORT0XCH1 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH1,
adcNegSelAPORT0XCH2 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH2,
@ -687,11 +683,9 @@ typedef enum
} ADC_NegSel_TypeDef;
#endif
#if defined( _ADC_SCANINPUTSEL_MASK )
/* ADC scan input groups */
typedef enum
{
#if defined(_ADC_SCANINPUTSEL_MASK)
/* ADC scan input groups */
typedef enum {
adcScanInputGroup0 = 0,
adcScanInputGroup1 = 1,
adcScanInputGroup2 = 2,
@ -700,18 +694,17 @@ typedef enum
/* Define none selected for ADC_SCANINPUTSEL */
#define ADC_SCANINPUTSEL_GROUP_NONE 0xFFU
#define ADC_SCANINPUTSEL_NONE ((ADC_SCANINPUTSEL_GROUP_NONE \
<< _ADC_SCANINPUTSEL_INPUT0TO7SEL_SHIFT) \
| (ADC_SCANINPUTSEL_GROUP_NONE \
<< _ADC_SCANINPUTSEL_INPUT8TO15SEL_SHIFT) \
| (ADC_SCANINPUTSEL_GROUP_NONE \
<< _ADC_SCANINPUTSEL_INPUT16TO23SEL_SHIFT) \
| (ADC_SCANINPUTSEL_GROUP_NONE \
#define ADC_SCANINPUTSEL_NONE ((ADC_SCANINPUTSEL_GROUP_NONE \
<< _ADC_SCANINPUTSEL_INPUT0TO7SEL_SHIFT) \
| (ADC_SCANINPUTSEL_GROUP_NONE \
<< _ADC_SCANINPUTSEL_INPUT8TO15SEL_SHIFT) \
| (ADC_SCANINPUTSEL_GROUP_NONE \
<< _ADC_SCANINPUTSEL_INPUT16TO23SEL_SHIFT) \
| (ADC_SCANINPUTSEL_GROUP_NONE \
<< _ADC_SCANINPUTSEL_INPUT24TO31SEL_SHIFT))
/* ADC scan alternative negative inputs */
typedef enum
{
/* ADC scan alternative negative inputs */
typedef enum {
adcScanNegInput1 = 1,
adcScanNegInput3 = 3,
adcScanNegInput5 = 5,
@ -724,10 +717,8 @@ typedef enum
} ADC_ScanNegInput_TypeDef;
#endif
/** ADC Start command. */
typedef enum
{
typedef enum {
/** Start single conversion. */
adcStartSingle = ADC_CMD_SINGLESTART,
@ -741,30 +732,28 @@ typedef enum
adcStartScanAndSingle = ADC_CMD_SCANSTART | ADC_CMD_SINGLESTART
} ADC_Start_TypeDef;
/** Warm-up mode. */
typedef enum
{
typedef enum {
/** ADC shutdown after each conversion. */
adcWarmupNormal = _ADC_CTRL_WARMUPMODE_NORMAL,
#if defined( _ADC_CTRL_WARMUPMODE_FASTBG )
#if defined(_ADC_CTRL_WARMUPMODE_FASTBG)
/** Do not warm-up bandgap references. */
adcWarmupFastBG = _ADC_CTRL_WARMUPMODE_FASTBG,
#endif
#if defined( _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM )
#if defined(_ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM)
/** Reference selected for scan mode kept warm.*/
adcWarmupKeepScanRefWarm = _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM,
#endif
#if defined( _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY )
#if defined(_ADC_CTRL_WARMUPMODE_KEEPINSTANDBY)
/** ADC is kept in standby mode between conversion. 1us warmup time needed
before next conversion. */
adcWarmupKeepInStandby = _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY,
#endif
#if defined( _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC )
#if defined(_ADC_CTRL_WARMUPMODE_KEEPINSLOWACC)
/** ADC is kept in slow acquisition mode between conversions. 1us warmup
time needed before next conversion. */
adcWarmupKeepInSlowAcq = _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC,
@ -773,35 +762,30 @@ typedef enum
/** ADC and reference selected for scan mode kept warmup, allowing
continuous conversion. */
adcWarmupKeepADCWarm = _ADC_CTRL_WARMUPMODE_KEEPADCWARM,
} ADC_Warmup_TypeDef;
#if defined( _ADC_CTRL_ADCCLKMODE_MASK )
/** ADC EM2 clock configuration */
typedef enum
{
#if defined(_ADC_CTRL_ADCCLKMODE_MASK)
/** ADC EM2 clock configuration */
typedef enum {
adcEm2Disabled = 0,
adcEm2ClockOnDemand = ADC_CTRL_ADCCLKMODE_ASYNC | ADC_CTRL_ASYNCCLKEN_ASNEEDED,
adcEm2ClockAlwaysOn = ADC_CTRL_ADCCLKMODE_ASYNC | ADC_CTRL_ASYNCCLKEN_ALWAYSON,
} ADC_EM2ClockConfig_TypeDef;
#endif
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** ADC init structure, common for single conversion and scan sequence. */
typedef struct
{
typedef struct {
/**
* Oversampling rate select. In order to have any effect, oversampling must
* be enabled for single/scan mode.
*/
ADC_OvsRateSel_TypeDef ovsRateSel;
#if defined( _ADC_CTRL_LPFMODE_MASK )
#if defined(_ADC_CTRL_LPFMODE_MASK)
/** Lowpass or decoupling capacitor filter to use. */
ADC_LPFilter_TypeDef lpfMode;
#endif
@ -825,48 +809,45 @@ typedef struct
bool tailgate;
/** ADC EM2 clock configuration */
#if defined( _ADC_CTRL_ADCCLKMODE_MASK )
#if defined(_ADC_CTRL_ADCCLKMODE_MASK)
ADC_EM2ClockConfig_TypeDef em2ClockConfig;
#endif
} ADC_Init_TypeDef;
/** Default config for ADC init structure. */
#if defined( _ADC_CTRL_LPFMODE_MASK ) && (!defined( _ADC_CTRL_ADCCLKMODE_MASK ))
#define ADC_INIT_DEFAULT \
{ \
adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
adcLPFilterBypass, /* No input filter selected. */ \
adcWarmupNormal, /* ADC shutdown after each conversion. */ \
_ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
_ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
false /* Do not use tailgate. */ \
}
#elif (!defined( _ADC_CTRL_LPFMODE_MASK )) && (!defined( _ADC_CTRL_ADCCLKMODE_MASK ))
#define ADC_INIT_DEFAULT \
{ \
adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
adcWarmupNormal, /* ADC shutdown after each conversion. */ \
_ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
_ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
false /* Do not use tailgate. */ \
}
#elif (!defined( _ADC_CTRL_LPFMODE_MASK )) && defined( _ADC_CTRL_ADCCLKMODE_MASK )
#define ADC_INIT_DEFAULT \
{ \
adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
adcWarmupNormal, /* ADC shutdown after each conversion. */ \
_ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
_ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
false, /* Do not use tailgate. */ \
adcEm2Disabled /* ADC disabled in EM2 */ \
}
#if defined(_ADC_CTRL_LPFMODE_MASK) && (!defined(_ADC_CTRL_ADCCLKMODE_MASK))
#define ADC_INIT_DEFAULT \
{ \
adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
adcLPFilterBypass, /* No input filter selected. */ \
adcWarmupNormal, /* ADC shutdown after each conversion. */ \
_ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
_ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
false /* Do not use tailgate. */ \
}
#elif (!defined(_ADC_CTRL_LPFMODE_MASK)) && (!defined(_ADC_CTRL_ADCCLKMODE_MASK))
#define ADC_INIT_DEFAULT \
{ \
adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
adcWarmupNormal, /* ADC shutdown after each conversion. */ \
_ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
_ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
false /* Do not use tailgate. */ \
}
#elif (!defined(_ADC_CTRL_LPFMODE_MASK)) && defined(_ADC_CTRL_ADCCLKMODE_MASK)
#define ADC_INIT_DEFAULT \
{ \
adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
adcWarmupNormal, /* ADC shutdown after each conversion. */ \
_ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
_ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
false, /* Do not use tailgate. */ \
adcEm2Disabled /* ADC disabled in EM2 */ \
}
#endif
/** Scan input configuration */
typedef struct
{
typedef struct {
/** Input range select to be applied to ADC_SCANINPUTSEL. */
uint32_t scanInputSel;
@ -877,10 +858,8 @@ typedef struct
uint32_t scanNegSel;
} ADC_InitScanInput_TypeDef;
/** Scan sequence init structure. */
typedef struct
{
typedef struct {
/**
* Peripheral reflex system trigger selection. Only applicable if @p prsEnable
* is enabled.
@ -899,7 +878,7 @@ typedef struct
/** Sample resolution. */
ADC_Res_TypeDef resolution;
#if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
#if defined(_ADC_SCANCTRL_INPUTMASK_MASK)
/**
* Scan input selection. If single ended (@p diff is false), use logical
* combination of ADC_SCANCTRL_INPUTMASK_CHx defines. If differential input
@ -909,7 +888,7 @@ typedef struct
uint32_t input;
#endif
#if defined( _ADC_SCANINPUTSEL_MASK )
#if defined(_ADC_SCANINPUTSEL_MASK)
/**
* Scan input configuration. @ref Use ADC_ScanInputClear(), @ref ADC_ScanSingleEndedInputAdd()
* or @ref ADC_ScanDifferentialInputAdd() to update this struct.
@ -930,11 +909,11 @@ typedef struct
bool rep;
/** When true, DMA is available in EM2 for scan conversion */
#if defined( _ADC_CTRL_SCANDMAWU_MASK )
#if defined(_ADC_CTRL_SCANDMAWU_MASK)
bool scanDmaEm2Wu;
#endif
#if defined( _ADC_SCANCTRLX_FIFOOFACT_MASK )
#if defined(_ADC_SCANCTRLX_FIFOOFACT_MASK)
/** When true, the FIFO overwrites old data when full. If false, then the FIFO discards new data.
The SINGLEOF IRQ is triggered in both cases. */
bool fifoOverwrite;
@ -942,47 +921,45 @@ typedef struct
} ADC_InitScan_TypeDef;
/** Default config for ADC scan init structure. */
#if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
#if defined(_ADC_SCANCTRL_INPUTMASK_MASK)
#define ADC_INITSCAN_DEFAULT \
{ \
adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
adcRef1V25, /* 1.25V internal reference. */ \
adcRes12Bit, /* 12 bit resolution. */ \
0, /* No input selected. */ \
false, /* Single-ended input. */ \
false, /* PRS disabled. */ \
false, /* Right adjust. */ \
false, /* Deactivate conversion after one scan sequence. */ \
}
#endif
#if defined( _ADC_SCANINPUTSEL_MASK )
#define ADC_INITSCAN_DEFAULT \
{ \
adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
adcRef1V25, /* 1.25V internal reference. */ \
adcRes12Bit, /* 12 bit resolution. */ \
{ \
/* Initialization should match values set by @ref ADC_ScanInputClear() */ \
ADC_SCANINPUTSEL_NONE, /* Default ADC inputs */ \
0, /* Default input mask (all off) */ \
_ADC_SCANNEGSEL_RESETVALUE,/* Default negative select for positive ternimal */\
}, \
false, /* Single-ended input. */ \
false, /* PRS disabled. */ \
false, /* Right adjust. */ \
false, /* Deactivate conversion after one scan sequence. */ \
false, /* No EM2 DMA wakeup from scan FIFO DVL */ \
false /* Discard new data on full FIFO. */ \
}
adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
adcRef1V25, /* 1.25V internal reference. */ \
adcRes12Bit, /* 12 bit resolution. */ \
0, /* No input selected. */ \
false, /* Single-ended input. */ \
false, /* PRS disabled. */ \
false, /* Right adjust. */ \
false, /* Deactivate conversion after one scan sequence. */ \
}
#endif
#if defined(_ADC_SCANINPUTSEL_MASK)
#define ADC_INITSCAN_DEFAULT \
{ \
adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
adcRef1V25, /* 1.25V internal reference. */ \
adcRes12Bit, /* 12 bit resolution. */ \
{ \
/* Initialization should match values set by @ref ADC_ScanInputClear() */ \
ADC_SCANINPUTSEL_NONE, /* Default ADC inputs */ \
0, /* Default input mask (all off) */ \
_ADC_SCANNEGSEL_RESETVALUE,/* Default negative select for positive ternimal */ \
}, \
false, /* Single-ended input. */ \
false, /* PRS disabled. */ \
false, /* Right adjust. */ \
false, /* Deactivate conversion after one scan sequence. */ \
false, /* No EM2 DMA wakeup from scan FIFO DVL */ \
false /* Discard new data on full FIFO. */ \
}
#endif
/** Single conversion init structure. */
typedef struct
{
typedef struct {
/**
* Peripheral reflex system trigger selection. Only applicable if @p prsEnable
* is enabled.
@ -1001,7 +978,7 @@ typedef struct
/** Sample resolution. */
ADC_Res_TypeDef resolution;
#if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
#if defined(_ADC_SINGLECTRL_INPUTSEL_MASK)
/**
* Sample input selection, use single ended or differential input according
* to setting of @p diff.
@ -1009,12 +986,12 @@ typedef struct
ADC_SingleInput_TypeDef input;
#endif
#if defined( _ADC_SINGLECTRL_POSSEL_MASK )
#if defined(_ADC_SINGLECTRL_POSSEL_MASK)
/** Select positive input for for single channel conversion mode. */
ADC_PosSel_TypeDef posSel;
#endif
#if defined( _ADC_SINGLECTRL_NEGSEL_MASK )
#if defined(_ADC_SINGLECTRL_NEGSEL_MASK)
/** Select negative input for single channel conversion mode. Negative input is grounded
for single ended (non-differential) converison. */
ADC_NegSel_TypeDef negSel;
@ -1032,12 +1009,12 @@ typedef struct
/** Select if continuous conversion until explicit stop. */
bool rep;
#if defined( _ADC_CTRL_SINGLEDMAWU_MASK )
#if defined(_ADC_CTRL_SINGLEDMAWU_MASK)
/** When true, DMA is available in EM2 for single conversion */
bool singleDmaEm2Wu;
#endif
#if defined( _ADC_SINGLECTRLX_FIFOOFACT_MASK )
#if defined(_ADC_SINGLECTRLX_FIFOOFACT_MASK)
/** When true, the FIFO overwrites old data when full. If false, then the FIFO discards new data.
The SCANOF IRQ is triggered in both cases. */
bool fifoOverwrite;
@ -1045,35 +1022,35 @@ typedef struct
} ADC_InitSingle_TypeDef;
/** Default config for ADC single conversion init structure. */
#if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
#if defined(_ADC_SINGLECTRL_INPUTSEL_MASK)
#define ADC_INITSINGLE_DEFAULT \
{ \
adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
adcRef1V25, /* 1.25V internal reference. */ \
adcRes12Bit, /* 12 bit resolution. */ \
adcSingleInpCh0, /* CH0 input selected. */ \
false, /* Single ended input. */ \
false, /* PRS disabled. */ \
false, /* Right adjust. */ \
false /* Deactivate conversion after one scan sequence. */ \
}
{ \
adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
adcRef1V25, /* 1.25V internal reference. */ \
adcRes12Bit, /* 12 bit resolution. */ \
adcSingleInpCh0, /* CH0 input selected. */ \
false, /* Single ended input. */ \
false, /* PRS disabled. */ \
false, /* Right adjust. */ \
false /* Deactivate conversion after one scan sequence. */ \
}
#else
#define ADC_INITSINGLE_DEFAULT \
{ \
adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
adcRef1V25, /* 1.25V internal reference. */ \
adcRes12Bit, /* 12 bit resolution. */ \
adcPosSelAPORT0XCH0, /* Select node BUS0XCH0 as posSel */ \
adcNegSelVSS, /* Select VSS as negSel */ \
false, /* Single ended input. */ \
false, /* PRS disabled. */ \
false, /* Right adjust. */ \
false, /* Deactivate conversion after one scan sequence. */ \
false, /* No EM2 DMA wakeup from single FIFO DVL */ \
false /* Discard new data on full FIFO. */ \
}
{ \
adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
adcRef1V25, /* 1.25V internal reference. */ \
adcRes12Bit, /* 12 bit resolution. */ \
adcPosSelAPORT0XCH0, /* Select node BUS0XCH0 as posSel */ \
adcNegSelVSS, /* Select VSS as negSel */ \
false, /* Single ended input. */ \
false, /* PRS disabled. */ \
false, /* Right adjust. */ \
false, /* Deactivate conversion after one scan sequence. */ \
false, /* No EM2 DMA wakeup from single FIFO DVL */ \
false /* Discard new data on full FIFO. */ \
}
#endif
/*******************************************************************************
@ -1098,7 +1075,6 @@ __STATIC_INLINE uint32_t ADC_DataSingleGet(ADC_TypeDef *adc)
return adc->SINGLEDATA;
}
/***************************************************************************//**
* @brief
* Peek single conversion result.
@ -1117,7 +1093,6 @@ __STATIC_INLINE uint32_t ADC_DataSinglePeek(ADC_TypeDef *adc)
return adc->SINGLEDATAP;
}
/***************************************************************************//**
* @brief
* Get scan result.
@ -1136,7 +1111,6 @@ __STATIC_INLINE uint32_t ADC_DataScanGet(ADC_TypeDef *adc)
return adc->SCANDATA;
}
/***************************************************************************//**
* @brief
* Peek scan result.
@ -1155,8 +1129,7 @@ __STATIC_INLINE uint32_t ADC_DataScanPeek(ADC_TypeDef *adc)
return adc->SCANDATAP;
}
#if defined( _ADC_SCANDATAX_MASK )
#if defined(_ADC_SCANDATAX_MASK)
uint32_t ADC_DataIdScanGet(ADC_TypeDef *adc, uint32_t *scanId);
#endif
@ -1164,7 +1137,7 @@ void ADC_Init(ADC_TypeDef *adc, const ADC_Init_TypeDef *init);
void ADC_Reset(ADC_TypeDef *adc);
void ADC_InitScan(ADC_TypeDef *adc, const ADC_InitScan_TypeDef *init);
#if defined( _ADC_SCANINPUTSEL_MASK )
#if defined(_ADC_SCANINPUTSEL_MASK)
void ADC_ScanInputClear(ADC_InitScan_TypeDef *scanInit);
uint32_t ADC_ScanSingleEndedInputAdd(ADC_InitScan_TypeDef *scanInit,
ADC_ScanInputGroup_TypeDef inputGroup,
@ -1179,7 +1152,6 @@ void ADC_InitSingle(ADC_TypeDef *adc, const ADC_InitSingle_TypeDef *init);
uint8_t ADC_TimebaseCalc(uint32_t hfperFreq);
uint8_t ADC_PrescaleCalc(uint32_t adcFreq, uint32_t hfperFreq);
/***************************************************************************//**
* @brief
* Clear one or more pending ADC interrupts.
@ -1196,7 +1168,6 @@ __STATIC_INLINE void ADC_IntClear(ADC_TypeDef *adc, uint32_t flags)
adc->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more ADC interrupts.
@ -1213,7 +1184,6 @@ __STATIC_INLINE void ADC_IntDisable(ADC_TypeDef *adc, uint32_t flags)
adc->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more ADC interrupts.
@ -1235,7 +1205,6 @@ __STATIC_INLINE void ADC_IntEnable(ADC_TypeDef *adc, uint32_t flags)
adc->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending ADC interrupt flags.
@ -1255,7 +1224,6 @@ __STATIC_INLINE uint32_t ADC_IntGet(ADC_TypeDef *adc)
return adc->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending ADC interrupt flags.
@ -1287,7 +1255,6 @@ __STATIC_INLINE uint32_t ADC_IntGetEnabled(ADC_TypeDef *adc)
return adc->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending ADC interrupts from SW.
@ -1304,7 +1271,6 @@ __STATIC_INLINE void ADC_IntSet(ADC_TypeDef *adc, uint32_t flags)
adc->IFS = flags;
}
/***************************************************************************//**
* @brief
* Start scan sequence and/or single conversion.
@ -1320,7 +1286,6 @@ __STATIC_INLINE void ADC_Start(ADC_TypeDef *adc, ADC_Start_TypeDef cmd)
adc->CMD = (uint32_t)cmd;
}
/** @} (end addtogroup ADC) */
/** @} (end addtogroup emlib) */

25
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_aes.h
* @brief Advanced encryption standard (AES) accelerator peripheral API.
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -126,7 +126,7 @@ void AES_CBC128(uint8_t *out,
const uint8_t *iv,
bool encrypt);
#if defined( AES_CTRL_AES256 )
#if defined(AES_CTRL_AES256)
void AES_CBC256(uint8_t *out,
const uint8_t *in,
unsigned int len,
@ -142,7 +142,7 @@ void AES_CFB128(uint8_t *out,
const uint8_t *iv,
bool encrypt);
#if defined( AES_CTRL_AES256 )
#if defined(AES_CTRL_AES256)
void AES_CFB256(uint8_t *out,
const uint8_t *in,
unsigned int len,
@ -158,7 +158,7 @@ void AES_CTR128(uint8_t *out,
uint8_t *ctr,
AES_CtrFuncPtr_TypeDef ctrFunc);
#if defined( AES_CTRL_AES256 )
#if defined(AES_CTRL_AES256)
void AES_CTR256(uint8_t *out,
const uint8_t *in,
unsigned int len,
@ -171,7 +171,7 @@ void AES_CTRUpdate32Bit(uint8_t *ctr);
void AES_DecryptKey128(uint8_t *out, const uint8_t *in);
#if defined( AES_CTRL_AES256 )
#if defined(AES_CTRL_AES256)
void AES_DecryptKey256(uint8_t *out, const uint8_t *in);
#endif
@ -181,7 +181,7 @@ void AES_ECB128(uint8_t *out,
const uint8_t *key,
bool encrypt);
#if defined( AES_CTRL_AES256 )
#if defined(AES_CTRL_AES256)
void AES_ECB256(uint8_t *out,
const uint8_t *in,
unsigned int len,
@ -202,7 +202,6 @@ __STATIC_INLINE void AES_IntClear(uint32_t flags)
AES->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more AES interrupts.
@ -216,7 +215,6 @@ __STATIC_INLINE void AES_IntDisable(uint32_t flags)
AES->IEN &= ~(flags);
}
/***************************************************************************//**
* @brief
* Enable one or more AES interrupts.
@ -235,7 +233,6 @@ __STATIC_INLINE void AES_IntEnable(uint32_t flags)
AES->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending AES interrupt flags.
@ -252,7 +249,6 @@ __STATIC_INLINE uint32_t AES_IntGet(void)
return AES->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending AES interrupt flags.
@ -275,7 +271,6 @@ __STATIC_INLINE uint32_t AES_IntGetEnabled(void)
return AES->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending AES interrupts from SW.
@ -289,14 +284,13 @@ __STATIC_INLINE void AES_IntSet(uint32_t flags)
AES->IFS = flags;
}
void AES_OFB128(uint8_t *out,
const uint8_t *in,
unsigned int len,
const uint8_t *key,
const uint8_t *iv);
#if defined( AES_CTRL_AES256 )
#if defined(AES_CTRL_AES256)
void AES_OFB256(uint8_t *out,
const uint8_t *in,
unsigned int len,
@ -304,7 +298,6 @@ void AES_OFB256(uint8_t *out,
const uint8_t *iv);
#endif
/** @} (end addtogroup AES) */
/** @} (end addtogroup emlib) */
@ -314,5 +307,3 @@ void AES_OFB256(uint8_t *out,
#endif /* defined(AES_COUNT) && (AES_COUNT > 0) */
#endif /* EM_AES_H */

8
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_assert.h
* @brief Emlib peripheral API "assert" implementation.
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -44,8 +44,8 @@ extern "C" {
#if defined(DOXY_DOC_ONLY)
/** @brief Included for documentation purposes only. This define is not present by default.
* @ref DEBUG_EFM should be defined from the compiler to enable the default internal
* assert handler. */
* @ref DEBUG_EFM should be defined from the compiler to enable the default internal
* assert handler. */
#define DEBUG_EFM
/** @endcond */
#endif

66
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_burtc.h
* @brief Backup Real Time Counter (BURTC) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -73,8 +73,7 @@ extern "C" {
******************************************************************************/
/** BURTC clock selection */
typedef enum
{
typedef enum {
/** Ultra low frequency (1 kHz) clock */
burtcClkSelULFRCO = BURTC_CTRL_CLKSEL_ULFRCO,
/** Low frequency RC oscillator */
@ -83,10 +82,8 @@ typedef enum
burtcClkSelLFXO = BURTC_CTRL_CLKSEL_LFXO
} BURTC_ClkSel_TypeDef;
/** BURTC mode of operation */
typedef enum
{
typedef enum {
/** Disable BURTC */
burtcModeDisable = BURTC_CTRL_MODE_DISABLE,
/** Enable and start BURTC counter in EM0 to EM2 */
@ -98,8 +95,7 @@ typedef enum
} BURTC_Mode_TypeDef;
/** BURTC low power mode */
typedef enum
{
typedef enum {
/** Low Power Mode is disabled */
burtcLPDisable = BURTC_LPMODE_LPMODE_DISABLE,
/** Low Power Mode is always enabled */
@ -113,8 +109,7 @@ typedef enum
******************************************************************************/
/** BURTC initialization structure. */
typedef struct
{
typedef struct {
bool enable; /**< Enable BURTC after initialization (starts counter) */
BURTC_Mode_TypeDef mode; /**< Configure energy mode operation */
@ -131,18 +126,18 @@ typedef struct
} BURTC_Init_TypeDef;
/** Default configuration for BURTC init structure */
#define BURTC_INIT_DEFAULT \
{ \
true, \
burtcModeEM2, \
false, \
burtcClkSelULFRCO, \
burtcClkDiv_1, \
0, \
true, \
false, \
burtcLPDisable, \
}
#define BURTC_INIT_DEFAULT \
{ \
true, \
burtcModeEM2, \
false, \
burtcClkSelULFRCO, \
burtcClkDiv_1, \
0, \
true, \
false, \
burtcLPDisable, \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************
@ -162,7 +157,6 @@ __STATIC_INLINE void BURTC_IntClear(uint32_t flags)
BURTC->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more BURTC interrupts.
@ -177,7 +171,6 @@ __STATIC_INLINE void BURTC_IntDisable(uint32_t flags)
BURTC->IEN &= ~(flags);
}
/***************************************************************************//**
* @brief
* Enable one or more BURTC interrupts.
@ -197,7 +190,6 @@ __STATIC_INLINE void BURTC_IntEnable(uint32_t flags)
BURTC->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending BURTC interrupt flags.
@ -214,7 +206,6 @@ __STATIC_INLINE uint32_t BURTC_IntGet(void)
return(BURTC->IF);
}
/***************************************************************************//**
* @brief
* Get enabled and pending BURTC interrupt flags.
@ -238,7 +229,6 @@ __STATIC_INLINE uint32_t BURTC_IntGetEnabled(void)
return BURTC->IF & tmp;
}
/***************************************************************************//**
* @brief
* Set one or more pending BURTC interrupts from SW.
@ -253,7 +243,6 @@ __STATIC_INLINE void BURTC_IntSet(uint32_t flags)
BURTC->IFS = flags;
}
/***************************************************************************//**
* @brief
* Status of BURTC RAM, timestamp and LP Mode
@ -265,7 +254,6 @@ __STATIC_INLINE uint32_t BURTC_Status(void)
return BURTC->STATUS;
}
/***************************************************************************//**
* @brief
* Clear and reset BURTC status register
@ -275,7 +263,6 @@ __STATIC_INLINE void BURTC_StatusClear(void)
BURTC->CMD = BURTC_CMD_CLRSTATUS;
}
/***************************************************************************//**
* @brief
* Enable or Disable BURTC peripheral reset and start counter
@ -289,17 +276,13 @@ __STATIC_INLINE void BURTC_Enable(bool enable)
&& ((BURTC->CTRL & _BURTC_CTRL_MODE_MASK)
!= BURTC_CTRL_MODE_DISABLE))
|| (enable == false));
if (enable)
{
if (enable) {
BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0);
}
else
{
} else {
BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1);
}
}
/***************************************************************************//**
* @brief Get BURTC counter
*
@ -311,7 +294,6 @@ __STATIC_INLINE uint32_t BURTC_CounterGet(void)
return BURTC->CNT;
}
/***************************************************************************//**
* @brief Get BURTC timestamp for entering BU
*
@ -323,7 +305,6 @@ __STATIC_INLINE uint32_t BURTC_TimestampGet(void)
return BURTC->TIMESTAMP;
}
/***************************************************************************//**
* @brief Freeze register updates until enabled
* @param[in] enable If true, registers are not updated until enabled again.
@ -333,7 +314,6 @@ __STATIC_INLINE void BURTC_FreezeEnable(bool enable)
BUS_RegBitWrite(&BURTC->FREEZE, _BURTC_FREEZE_REGFREEZE_SHIFT, enable);
}
/***************************************************************************//**
* @brief Shut down power to rentention register bank.
* @param[in] enable
@ -347,7 +327,6 @@ __STATIC_INLINE void BURTC_Powerdown(bool enable)
BUS_RegBitWrite(&BURTC->POWERDOWN, _BURTC_POWERDOWN_RAM_SHIFT, enable);
}
/***************************************************************************//**
* @brief
* Set a value in one of the retention registers
@ -364,7 +343,6 @@ __STATIC_INLINE void BURTC_RetRegSet(uint32_t num, uint32_t data)
BURTC->RET[num].REG = data;
}
/***************************************************************************//**
* @brief
* Read a value from one of the retention registers
@ -379,7 +357,6 @@ __STATIC_INLINE uint32_t BURTC_RetRegGet(uint32_t num)
return BURTC->RET[num].REG;
}
/***************************************************************************//**
* @brief
* Lock BURTC registers, will protect from writing new config settings
@ -389,7 +366,6 @@ __STATIC_INLINE void BURTC_Lock(void)
BURTC->LOCK = BURTC_LOCK_LOCKKEY_LOCK;
}
/***************************************************************************//**
* @brief
* Unlock BURTC registers, enable write access to change configuration
@ -399,7 +375,6 @@ __STATIC_INLINE void BURTC_Unlock(void)
BURTC->LOCK = BURTC_LOCK_LOCKKEY_UNLOCK;
}
void BURTC_Reset(void);
void BURTC_Init(const BURTC_Init_TypeDef *burtcInit);
void BURTC_CounterReset(void);
@ -407,7 +382,6 @@ void BURTC_CompareSet(unsigned int comp, uint32_t value);
uint32_t BURTC_CompareGet(unsigned int comp);
uint32_t BURTC_ClockFreqGet(void);
/** @} (end addtogroup BURTC) */
/** @} (end addtogroup emlib) */

26
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bus.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_bus.h
* @brief RAM and peripheral bit-field set and clear API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -76,7 +76,7 @@ __STATIC_INLINE void BUS_RamBitWrite(volatile uint32_t *addr,
unsigned int bit,
unsigned int val)
{
#if defined( BITBAND_RAM_BASE )
#if defined(BITBAND_RAM_BASE)
uint32_t aliasAddr =
BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * 32) + (bit * 4);
@ -89,7 +89,6 @@ __STATIC_INLINE void BUS_RamBitWrite(volatile uint32_t *addr,
#endif
}
/***************************************************************************//**
* @brief
* Perform a single-bit read operation on a 32-bit word in RAM
@ -114,7 +113,7 @@ __STATIC_INLINE void BUS_RamBitWrite(volatile uint32_t *addr,
__STATIC_INLINE unsigned int BUS_RamBitRead(volatile const uint32_t *addr,
unsigned int bit)
{
#if defined( BITBAND_RAM_BASE )
#if defined(BITBAND_RAM_BASE)
uint32_t aliasAddr =
BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * 32) + (bit * 4);
@ -124,7 +123,6 @@ __STATIC_INLINE unsigned int BUS_RamBitRead(volatile const uint32_t *addr,
#endif
}
/***************************************************************************//**
* @brief
* Perform a single-bit write operation on a peripheral register
@ -149,7 +147,7 @@ __STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr,
unsigned int bit,
unsigned int val)
{
#if defined( BITBAND_PER_BASE )
#if defined(BITBAND_PER_BASE)
uint32_t aliasAddr =
BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * 32) + (bit * 4);
@ -162,7 +160,6 @@ __STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr,
#endif
}
/***************************************************************************//**
* @brief
* Perform a single-bit read operation on a peripheral register
@ -187,7 +184,7 @@ __STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr,
__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr,
unsigned int bit)
{
#if defined( BITBAND_PER_BASE )
#if defined(BITBAND_PER_BASE)
uint32_t aliasAddr =
BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * 32) + (bit * 4);
@ -197,7 +194,6 @@ __STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr,
#endif
}
/***************************************************************************//**
* @brief
* Perform a masked set operation on peripheral register address.
@ -221,7 +217,7 @@ __STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr,
__STATIC_INLINE void BUS_RegMaskedSet(volatile uint32_t *addr,
uint32_t mask)
{
#if defined( PER_BITSET_MEM_BASE )
#if defined(PER_BITSET_MEM_BASE)
uint32_t aliasAddr = PER_BITSET_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE);
*(volatile uint32_t *)aliasAddr = mask;
#else
@ -229,7 +225,6 @@ __STATIC_INLINE void BUS_RegMaskedSet(volatile uint32_t *addr,
#endif
}
/***************************************************************************//**
* @brief
* Perform a masked clear operation on peripheral register address.
@ -253,7 +248,7 @@ __STATIC_INLINE void BUS_RegMaskedSet(volatile uint32_t *addr,
__STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr,
uint32_t mask)
{
#if defined( PER_BITCLR_MEM_BASE )
#if defined(PER_BITCLR_MEM_BASE)
uint32_t aliasAddr = PER_BITCLR_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE);
*(volatile uint32_t *)aliasAddr = mask;
#else
@ -261,7 +256,6 @@ __STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr,
#endif
}
/***************************************************************************//**
* @brief
* Perform peripheral register masked clear and value write.
@ -289,7 +283,7 @@ __STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr,
uint32_t mask,
uint32_t val)
{
#if defined( PER_BITCLR_MEM_BASE )
#if defined(PER_BITCLR_MEM_BASE)
BUS_RegMaskedClear(addr, mask);
BUS_RegMaskedSet(addr, val);
#else
@ -297,7 +291,6 @@ __STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr,
#endif
}
/***************************************************************************//**
* @brief
* Perform a peripheral register masked read
@ -321,7 +314,6 @@ __STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr,
return *addr & mask;
}
/** @} (end addtogroup BUS) */
/** @} (end addtogroup emlib) */

596
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_can.h Normal file
View File

@ -0,0 +1,596 @@
/***************************************************************************//**
* @file em_can.h
* @brief Controller Area Network API
* @version 5.3.3
*******************************************************************************
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
* obligation to support this Software. Silicon Labs is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Silicon Labs will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#ifndef EM_CAN_H
#define EM_CAN_H
#include "em_bus.h"
#include "em_device.h"
#include <stdbool.h>
#if defined(CAN_COUNT) && (CAN_COUNT > 0)
#ifdef __cplusplus
extern "C" {
#endif
/***************************************************************************//**
* @addtogroup emlib
* @{
******************************************************************************/
/***************************************************************************//**
* @addtogroup CAN
* @{
******************************************************************************/
/*******************************************************************************
******************************* DEFINES ***********************************
******************************************************************************/
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** CAN Status codes */
typedef enum {
/** No error occurred during last CAN bus event. */
canErrorNoError = CAN_STATUS_LEC_NONE,
/**
* More than 5 equal bits in a sequence have occurred in a part of a received
* message where this is not allowed.
*/
canErrorStuff = CAN_STATUS_LEC_STUFF,
/** A fixed format part of a received frame has the wrong format. */
canErrorForm = CAN_STATUS_LEC_FORM,
/** The message this CAN Core transmitted was not acknowledged by another node. */
canErrorAck = CAN_STATUS_LEC_ACK,
/** Wrong monitored bus value : dominant when the module wanted to send a recessive. */
canErrorBit1 = CAN_STATUS_LEC_BIT1,
/** Wrong monitored bus value : recessive when the module intended to send a dominant. */
canErrorBit0 = CAN_STATUS_LEC_BIT0,
/** CRC check sum incorrect. */
canErrorCrc = CAN_STATUS_LEC_CRC,
/** Unused. No new error since the cpu wrote this value */
canErrorUnused = CAN_STATUS_LEC_UNUSED
} CAN_ErrorCode_TypeDef;
/** CAN peripheral mode */
typedef enum {
/** CAN peripheral in Normal mode : ready to send and receive messages */
canModeNormal,
/** CAN peripheral in Basic mode : no use of the RAM */
canModeBasic,
/**
* CAN peripheral in Loopback mode : input from the CAN bus is disregarded
* and comes from TX instead
*/
canModeLoopBack,
/**
* CAN peripheral in SilentLoopback mode : input from the CAN bus is
* disregarded and comes from TX instead ; no output on the CAN bus
*/
canModeSilentLoopBack,
/** CAN peripheral in Silent mode : no output on the CAN bus. If required to
* send a dominant bit, it's rerouted internally so that the CAN module
* monitors it but the CAN bus stays recessive.
*/
canModeSilent
} CAN_Mode_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** CAN Message Object TypeDef structure. LSBs is used */
typedef struct {
/** Message number of this Message Object, [1 - 32] */
uint8_t msgNum;
/** Id extended if true, standard if false */
bool extended;
/**
* Id of the message, with 11 bits (standard) or 28 bits (extended).
* LSBs are used for both of them
*/
uint32_t id;
/** Data Length Code [0 - 8] */
uint8_t dlc;
/** Pointer to the data, [0 - 8] bytes */
uint8_t data[8];
/** Mask for id filtering */
uint32_t mask;
/** Enable the use of 'extended' value for filtering */
bool extendedMask;
/** Enable the use of 'direction' value for filtering */
bool directionMask;
} CAN_MessageObject_TypeDef;
/** CAN initialization structure. */
typedef struct {
/** true to set the CAN Device in normal mode after init */
bool enable;
/** True to reset messages during initialization */
bool resetMessages;
/** Default bitrate */
uint32_t bitrate;
/** Default Propagation Time Segment */
uint8_t propagationTimeSegment;
/** Default Phase Buffer Segment 1 */
uint8_t phaseBufferSegment1;
/** Default Phase Buffer Segment 2 */
uint8_t phaseBufferSegment2;
/** Default Synchronisation Jump Width */
uint8_t synchronisationJumpWidth;
} CAN_Init_TypeDef;
/**
* Default initialization of CAN_Init_TypeDef. The total duration of a bit with
* these default parameters is 10 tq (time quantum : tq = brp/fsys, brp being
* the baudrate prescaler and being set according to the wanted bitrate, fsys
* beeing the CAN Device frequency).
*/
#define CAN_INIT_DEFAULT \
{ \
true, /** Set the CAN Device in normal mode after init */ \
true, /** Reset messages during initialization */ \
100000, /** Set bitrate to 100 000 */ \
1, /** Set the Propagation Time Segment to 1 */ \
4, /** Set the Phase Buffer Segment 1 to 4 */ \
4, /** Set the Phase Buffer Segment 2 to 4 */ \
1 /** Set the Synchronization Jump Width to 1 */ \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
void CAN_Init(CAN_TypeDef *can, const CAN_Init_TypeDef *init);
uint32_t CAN_GetClockFrequency(CAN_TypeDef *can);
bool CAN_MessageLost(CAN_TypeDef *can, uint8_t interface, uint8_t msgNum);
void CAN_SetRoute(CAN_TypeDef *can,
bool active,
uint16_t pinRxLoc,
uint16_t pinTxLoc);
void CAN_SetBitTiming(CAN_TypeDef *can,
uint32_t bitrate,
uint16_t propagationTimeSegment,
uint16_t phaseBufferSegment1,
uint16_t phaseBufferSegment2,
uint16_t synchronisationJumpWidth);
void CAN_SetMode(CAN_TypeDef *can, CAN_Mode_TypeDef mode);
void CAN_SetIdAndFilter(CAN_TypeDef *can,
uint8_t interface,
bool useMask,
const CAN_MessageObject_TypeDef *message,
bool wait);
void CAN_ConfigureMessageObject(CAN_TypeDef *can,
uint8_t interface,
uint8_t msgNum,
bool valid,
bool tx,
bool remoteTransfer,
bool endOfBuffer,
bool wait);
void CAN_SendMessage(CAN_TypeDef *can,
uint8_t interface,
const CAN_MessageObject_TypeDef *message,
bool wait);
void CAN_ReadMessage(CAN_TypeDef *can,
uint8_t interface,
CAN_MessageObject_TypeDef *message);
void CAN_AbortSendMessage(CAN_TypeDef *can,
uint8_t interface,
uint8_t msgNum,
bool wait);
void CAN_ResetMessages(CAN_TypeDef *can, uint8_t interface);
void CAN_Reset(CAN_TypeDef *can);
void CAN_WriteData(CAN_TypeDef *can,
uint8_t interface,
const CAN_MessageObject_TypeDef *message);
void CAN_SendRequest(CAN_TypeDef *can,
uint8_t interface,
uint8_t msgNum,
bool wait);
/***************************************************************************//**
* @brief
* Enable the Host Controller to send messages.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] enable
* true to enable CAN device, false to disable it. If the CAN device is
* enabled, it goes in normal mode (the default working mode).
******************************************************************************/
__STATIC_INLINE void CAN_Enable(CAN_TypeDef *can, bool enable)
{
BUS_RegBitWrite(&can->CTRL, _CAN_CTRL_INIT_SHIFT, (enable ? 0 : 1));
}
/***************************************************************************//**
* @brief
* Gives the communication capabilities state.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* true if the Host Controller can send messages, false otherwise.
******************************************************************************/
__STATIC_INLINE bool CAN_IsEnabled(CAN_TypeDef *can)
{
return (can->CTRL & _CAN_CTRL_INIT_MASK) == 0;
}
/***************************************************************************//**
* @brief
* Waiting function.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
******************************************************************************/
__STATIC_INLINE void CAN_ReadyWait(CAN_TypeDef *can,
uint8_t interface)
{
while ((_CAN_MIR_CMDREQ_BUSY_MASK & can->MIR[interface].CMDREQ) != 0) {
}
}
/***************************************************************************//**
* @brief
* Get the last error code and clear its register.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* return Last error code.
******************************************************************************/
__STATIC_INLINE CAN_ErrorCode_TypeDef CAN_GetLastErrorCode(CAN_TypeDef *can)
{
CAN_ErrorCode_TypeDef errorCode = (CAN_ErrorCode_TypeDef)
(can->STATUS & _CAN_STATUS_LEC_MASK);
can->STATUS |= ~_CAN_STATUS_LEC_MASK;
return errorCode;
}
/***************************************************************************//**
* @brief
* Indicates which messages objects have received new data.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* State of MESSAGEDATA register indicating which messages objects have received
* new data.
******************************************************************************/
__STATIC_INLINE uint32_t CAN_HasNewdata(CAN_TypeDef *can)
{
return can->MESSAGEDATA;
}
/***************************************************************************//**
* @brief
* Clear one or more pending CAN status interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* Pending CAN status interrupt source(s) to clear.
******************************************************************************/
__STATIC_INLINE void CAN_StatusIntClear(CAN_TypeDef *can, uint32_t flags)
{
can->IF1IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable CAN status interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* CAN status interrupt source(s) to disable.
******************************************************************************/
__STATIC_INLINE void CAN_StatusIntDisable(CAN_TypeDef *can, uint32_t flags)
{
can->IF1IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable CAN status interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* CAN status interrupt source(s) to enable.
******************************************************************************/
__STATIC_INLINE void CAN_StatusIntEnable(CAN_TypeDef *can, uint32_t flags)
{
can->IF1IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending CAN status interrupt flags.
*
* @note
* The event bits are not cleared by the use of this function.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* CAN interrupt source(s) pending.
******************************************************************************/
__STATIC_INLINE uint32_t CAN_StatusIntGet(CAN_TypeDef *can)
{
return can->IF1IF;
}
/***************************************************************************//**
* @brief
* Get pending and enabled CAN status interrupt flags.
*
* @note
* The event bits are not cleared by the use of this function.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* CAN interrupt source(s) pending and enabled.
******************************************************************************/
__STATIC_INLINE uint32_t CAN_StatusIntGetEnabled(CAN_TypeDef *can)
{
uint32_t ien;
ien = can->IF1IEN;
return can->IF1IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more CAN status interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* CAN status interrupt source(s) to set to pending.
******************************************************************************/
__STATIC_INLINE void CAN_StatusIntSet(CAN_TypeDef *can, uint32_t flags)
{
can->IF1IFS = flags;
}
/***************************************************************************//**
* @brief
* Get CAN status.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* Value of CAN register STATUS.
******************************************************************************/
__STATIC_INLINE uint32_t CAN_StatusGet(CAN_TypeDef *can)
{
return can->STATUS & ~_CAN_STATUS_LEC_MASK;
}
/***************************************************************************//**
* @brief
* Clear CAN status.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* CAN status bits to clear.
******************************************************************************/
__STATIC_INLINE void CAN_StatusClear(CAN_TypeDef *can, uint32_t flags)
{
can->STATUS &= ~flags;
}
/***************************************************************************//**
* @brief
* Get the error count.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* Error count.
******************************************************************************/
__STATIC_INLINE uint32_t CAN_GetErrorCount(CAN_TypeDef *can)
{
return can->ERRCNT;
}
/***************************************************************************//**
* @brief
* Clear one or more pending CAN message interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* Pending CAN message interrupt source(s) to clear.
******************************************************************************/
__STATIC_INLINE void CAN_MessageIntClear(CAN_TypeDef *can, uint32_t flags)
{
can->IF0IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable CAN message interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* CAN message interrupt source(s) to disable.
******************************************************************************/
__STATIC_INLINE void CAN_MessageIntDisable(CAN_TypeDef *can, uint32_t flags)
{
can->IF0IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable CAN message interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* CAN message interrupt source(s) to enable.
******************************************************************************/
__STATIC_INLINE void CAN_MessageIntEnable(CAN_TypeDef *can, uint32_t flags)
{
can->IF0IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending CAN message interrupt flags.
*
* @note
* The event bits are not cleared by the use of this function.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* CAN message interrupt source(s) pending.
******************************************************************************/
__STATIC_INLINE uint32_t CAN_MessageIntGet(CAN_TypeDef *can)
{
return can->IF0IF;
}
/***************************************************************************//**
* @brief
* Get CAN message interrupt flags that are pending and enabled.
*
* @note
* The event bits are not cleared by the use of this function.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* CAN message interrupt source(s) pending and enabled.
******************************************************************************/
__STATIC_INLINE uint32_t CAN_MessageIntGetEnabled(CAN_TypeDef *can)
{
uint32_t ien;
ien = can->IF0IEN;
return can->IF0IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more CAN message interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* CAN message interrupt source(s) to set to pending.
******************************************************************************/
__STATIC_INLINE void CAN_MessageIntSet(CAN_TypeDef *can, uint32_t flags)
{
can->IF0IFS = flags;
}
/** @} (end addtogroup CAN) */
/** @} (end addtogroup emlib) */
#ifdef __cplusplus
}
#endif
#endif /* defined(CAN_COUNT) && (CAN_COUNT > 0) */
#endif /* EM_CAN_H */

95
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_chip.h
* @brief Chip Initialization API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -76,8 +76,7 @@ __STATIC_INLINE void CHIP_Init(void)
rev = *(volatile uint32_t *)(0x0FE081FC);
/* Engineering Sample calibration setup */
if ((rev >> 24) == 0)
{
if ((rev >> 24) == 0) {
reg = (volatile uint32_t *)0x400CA00C;
*reg &= ~(0x70UL);
/* DREG */
@ -85,8 +84,7 @@ __STATIC_INLINE void CHIP_Init(void)
*reg &= ~(0xE0000000UL);
*reg |= ~(7UL << 25);
}
if ((rev >> 24) <= 3)
{
if ((rev >> 24) <= 3) {
/* DREG */
reg = (volatile uint32_t *)0x400C6020;
*reg &= ~(0x00001F80UL);
@ -104,12 +102,10 @@ __STATIC_INLINE void CHIP_Init(void)
}
SYSTEM_ChipRevisionGet(&chipRev);
if (chipRev.major == 0x01)
{
if (chipRev.major == 0x01) {
/* Rev A errata handling for EM2/3. Must enable DMA clock in order for EM2/3 */
/* to work. This will be fixed in later chip revisions, so only do for rev A. */
if (chipRev.minor == 00)
{
if (chipRev.minor == 00) {
reg = (volatile uint32_t *)0x400C8040;
*reg |= 0x2;
}
@ -117,16 +113,14 @@ __STATIC_INLINE void CHIP_Init(void)
/* Rev A+B errata handling for I2C when using EM2/3. USART0 clock must be enabled */
/* after waking up from EM2/EM3 in order for I2C to work. This will be fixed in */
/* later chip revisions, so only do for rev A+B. */
if (chipRev.minor <= 0x01)
{
if (chipRev.minor <= 0x01) {
reg = (volatile uint32_t *)0x400C8044;
*reg |= 0x1;
}
}
/* Ensure correct ADC/DAC calibration value */
rev = *(volatile uint32_t *)0x0FE081F0;
if (rev < 0x4C8ABA00)
{
if (rev < 0x4C8ABA00) {
uint32_t cal;
/* Enable ADC/DAC clocks */
@ -134,17 +128,17 @@ __STATIC_INLINE void CHIP_Init(void)
*reg |= (1 << 14 | 1 << 11);
/* Retrive calibration values */
cal = ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) >>
8) << 24;
cal = ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL)
>> 8) << 24;
cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) >>
0) << 16;
cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL)
>> 0) << 16;
cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) >>
8) << 8;
cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL)
>> 8) << 8;
cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) >>
0) << 0;
cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL)
>> 0) << 0;
/* ADC0->CAL = 1.25 reference */
reg = (volatile uint32_t *)0x40002034UL;
@ -172,11 +166,10 @@ __STATIC_INLINE void CHIP_Init(void)
prodRev = SYSTEM_GetProdRev();
SYSTEM_ChipRevisionGet(&chipRev);
if ((prodRev >= 16) && (chipRev.minor >= 3))
{
if ((prodRev >= 16) && (chipRev.minor >= 3)) {
/* This fixes an issue with the LFXO on high temperatures. */
*(volatile uint32_t*)0x400C80C0 =
( *(volatile uint32_t*)0x400C80C0 & ~(1 << 6) ) | (1 << 4);
(*(volatile uint32_t*)0x400C80C0 & ~(1 << 6) ) | (1 << 4);
}
#endif
@ -185,8 +178,7 @@ __STATIC_INLINE void CHIP_Init(void)
uint8_t prodRev;
prodRev = SYSTEM_GetProdRev();
if (prodRev <= 129)
{
if (prodRev <= 129) {
/* This fixes a mistaken internal connection between PC0 and PC4 */
/* This disables an internal pulldown on PC4 */
*(volatile uint32_t*)(0x400C6018) = (1 << 26) | (5 << 0);
@ -198,14 +190,14 @@ __STATIC_INLINE void CHIP_Init(void)
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
/****************************
* Fixes for errata GPIO_E201 (slewrate) and
* HFXO high temperature oscillator startup robustness fix */
* Fixes for errata GPIO_E201 (slewrate) and
* HFXO high temperature oscillator startup robustness fix */
uint32_t port;
uint32_t clkEn;
uint8_t prodRev;
const uint32_t setVal = (0x5 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT)
| (0x5 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
| (0x5 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
const uint32_t resetVal = _GPIO_P_CTRL_RESETVALUE
& ~(_GPIO_P_CTRL_SLEWRATE_MASK
| _GPIO_P_CTRL_SLEWRATEALT_MASK);
@ -215,8 +207,7 @@ __STATIC_INLINE void CHIP_Init(void)
SYSTEM_ChipRevisionGet(&chipRev);
/* This errata is fixed in hardware from PRODREV 0x8F. */
if (prodRev < 0x8F)
{
if (prodRev < 0x8F) {
/* Fixes for errata GPIO_E201 (slewrate) */
/* Save HFBUSCLK enable state and enable GPIO clock. */
@ -224,8 +215,7 @@ __STATIC_INLINE void CHIP_Init(void)
CMU->HFBUSCLKEN0 = clkEn | CMU_HFBUSCLKEN0_GPIO;
/* Update slewrate */
for(port = 0; port <= GPIO_PORT_MAX; port++)
{
for (port = 0; port <= GPIO_PORT_MAX; port++) {
GPIO->P[port].CTRL = setVal | resetVal;
}
@ -234,19 +224,25 @@ __STATIC_INLINE void CHIP_Init(void)
}
/* This errata is fixed in hardware from PRODREV 0x90. */
if (prodRev < 0x90)
{
if (prodRev < 0x90) {
/* HFXO high temperature oscillator startup robustness fix */
CMU->HFXOSTARTUPCTRL =
(CMU->HFXOSTARTUPCTRL & ~_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK)
| (0x20 << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT);
(CMU->HFXOSTARTUPCTRL & ~_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK)
| (0x20 << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT);
}
if (chipRev.major == 0x01)
{
if (chipRev.major == 0x01) {
/* Fix for errata EMU_E210 - Potential Power-Down When Entering EM2 */
*(volatile uint32_t *)(EMU_BASE + 0x164) |= 0x4;
}
#if defined(_EFR_DEVICE)
/****************************
* Fix for errata DCDC_E206
* Disable bypass limit enabled temporarily in SystemInit() errata
* workaround. */
BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0);
#endif
#endif
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
@ -254,28 +250,33 @@ __STATIC_INLINE void CHIP_Init(void)
uint8_t prodRev = SYSTEM_GetProdRev();
/* EM2 current fixes for early samples */
if (prodRev == 0)
{
if (prodRev == 0) {
*(volatile uint32_t *)(EMU_BASE + 0x190) = 0x0000ADE8UL;
*(volatile uint32_t *)(EMU_BASE + 0x198) |= (0x1 << 2);
*(volatile uint32_t *)(EMU_BASE + 0x190) = 0x0;
}
if (prodRev < 2)
{
if (prodRev < 2) {
*(volatile uint32_t *)(EMU_BASE + 0x164) |= (0x1 << 13);
}
/* Set optimal LFRCOCTRL VREFUPDATE and enable duty cycling of vref */
CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~_CMU_LFRCOCTRL_VREFUPDATE_MASK)
| CMU_LFRCOCTRL_VREFUPDATE_64CYCLES
| CMU_LFRCOCTRL_ENVREF;
| CMU_LFRCOCTRL_VREFUPDATE_64CYCLES
| CMU_LFRCOCTRL_ENVREF;
#endif
#if defined(_EFR_DEVICE) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 84)
MSC->CTRL |= 0x1 << 8;
#endif
/* Set validated PLFRCO trims for production revision < 5. Overwriting registers
for all production revisions is safe. */
#if defined(_SILICON_LABS_32B_SERIES_1) && defined(_CMU_STATUS_PLFRCOENS_MASK)
*(volatile uint32_t *)(CMU_BASE + 0x28C) = 0x258;
*(volatile uint32_t *)(CMU_BASE + 0x290) = 0x55D4A;
*(volatile uint32_t *)(CMU_BASE + 0x2FC) = 0x16E228;
*(volatile uint32_t *)(CMU_BASE + 0x294) = 0x1E0;
#endif
}
/** @} (end addtogroup CHIP) */

907
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h
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File diff suppressed because it is too large Load Diff

61
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h
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@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_common.h
* @brief General purpose utilities.
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -116,7 +116,7 @@ extern "C" {
#if defined(__ICCARM__)
/** @brief IAR Embedded Workbench: Macros for handling aligned structs. */
#define SL_ALIGN(X) _Pragma(STRINGIZE(data_alignment=X))
#define SL_ALIGN(X) _Pragma(STRINGIZE(data_alignment = X))
/** @brief IAR Embedded Workbench: Macros for handling weak symbols. */
#define SL_WEAK __weak
@ -124,9 +124,11 @@ extern "C" {
/** @brief IAR Embedded Workbench: Macro for handling non-returning functions. */
#define SL_NORETURN __noreturn
/* *INDENT-OFF* */
/** IAR Embedded Workbench: Macro for handling section placement */
#define SL_ATTRIBUTE_SECTION(X) @ X
#endif
/* *INDENT-ON* */
#define SL_ATTRIBUTE_ALIGN(X)
@ -134,10 +136,10 @@ extern "C" {
/* GCC compilers */
/** @brief Macro for getting minimum value. No sideeffects, a and b are evaluated once only. */
#define SL_MIN(a, b) __extension__({__typeof__(a) _a = (a); __typeof__(b) _b = (b); _a < _b ? _a : _b;})
#define SL_MIN(a, b) __extension__({ __typeof__(a)_a = (a); __typeof__(b)_b = (b); _a < _b ? _a : _b; })
/** @brief Macro for getting maximum value. No sideeffects, a and b are evaluated once only. */
#define SL_MAX(a, b) __extension__({__typeof__(a) _a = (a); __typeof__(b) _b = (b); _a > _b ? _a : _b;})
#define SL_MAX(a, b) __extension__({ __typeof__(a)_a = (a); __typeof__(b)_b = (b); _a > _b ? _a : _b; })
/** @brief GCC style macro for handling packed structs. */
#define SL_ATTRIBUTE_PACKED __attribute__ ((packed))
@ -198,18 +200,63 @@ __STATIC_INLINE uint32_t SL_CTZ(uint32_t value)
#else
uint32_t zeros;
for(zeros=0; (zeros<32) && ((value&0x1) == 0); zeros++, value>>=1);
for (zeros = 0; (zeros < 32) && ((value & 0x1) == 0); zeros++, value >>= 1) {
;
}
return zeros;
#endif
}
/* Deprecated function. New code should use @ref SL_CTZ. */
__STATIC_INLINE uint32_t EFM32_CTZ(uint32_t value)
{
return SL_CTZ(value);
}
/***************************************************************************//**
* @brief
* Reverse the bits. Use the RBIT instruction if available, else process.
*
* @param[in] value
* Data value to reverse.
*
* @return
* Reversed value.
******************************************************************************/
__STATIC_INLINE uint32_t SL_RBIT(uint32_t value)
{
uint32_t result;
#if (__CORTEX_M >= 0x03U)
result = __RBIT(value);
#else
int32_t s = 4 * 8 - 1;
result = value;
for (value >>= 1U; value; value >>= 1U) {
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s;
#endif
return result;
}
/***************************************************************************//**
* @brief
* Reverse the bits. Use the RBIT instruction if available, else process.
*
* @param[in] value
* 16-bit data value to reverse.
*
* @return
* 16-bit reversed value.
******************************************************************************/
__STATIC_INLINE uint32_t SL_RBIT16(uint32_t value)
{
return SL_RBIT(value) >> 16;
}
/** @} (end addtogroup COMMON) */
/** @} (end addtogroup emlib) */

58
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_core.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_core.h
* @brief Core interrupt handling API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -92,14 +92,14 @@ extern "C" {
/** Convenience macro for implementing a CRITICAL section. */
#define CORE_CRITICAL_SECTION(yourcode) \
{ \
CORE_DECLARE_IRQ_STATE; \
CORE_ENTER_CRITICAL(); \
{ \
yourcode \
} \
CORE_EXIT_CRITICAL(); \
}
CORE_DECLARE_IRQ_STATE; \
CORE_ENTER_CRITICAL(); \
{ \
yourcode \
} \
CORE_EXIT_CRITICAL(); \
}
/** Enter CRITICAL section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in
* scope. */
@ -110,7 +110,7 @@ extern "C" {
#define CORE_EXIT_CRITICAL() CORE_ExitCritical(irqState)
/** CRITICAL style yield. */
#define CORE_YIELD_CRITICAL() CORE_YieldCritical(void)
#define CORE_YIELD_CRITICAL() CORE_YieldCritical()
//
// ATOMIC section macro API.
@ -124,14 +124,14 @@ extern "C" {
/** Convenience macro for implementing an ATOMIC section. */
#define CORE_ATOMIC_SECTION(yourcode) \
{ \
CORE_DECLARE_IRQ_STATE; \
CORE_ENTER_ATOMIC(); \
{ \
yourcode \
} \
CORE_EXIT_ATOMIC(); \
}
CORE_DECLARE_IRQ_STATE; \
CORE_ENTER_ATOMIC(); \
{ \
yourcode \
} \
CORE_EXIT_ATOMIC(); \
}
/** Enter ATOMIC section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in
* scope. */
@ -142,7 +142,7 @@ extern "C" {
#define CORE_EXIT_ATOMIC() CORE_ExitAtomic(irqState)
/** ATOMIC style yield. */
#define CORE_YIELD_ATOMIC() CORE_YieldAtomic(void)
#define CORE_YIELD_ATOMIC() CORE_YieldAtomic()
//
// NVIC mask section macro API.
@ -160,7 +160,7 @@ extern "C" {
/** Allocate storage for and zero initialize NVIC interrupt mask.
* @param[in] x
* The storage variable name to use.*/
#define CORE_DECLARE_NVIC_ZEROMASK(x) CORE_nvicMask_t x = {{0}}
#define CORE_DECLARE_NVIC_ZEROMASK(x) CORE_nvicMask_t x = { { 0 } }
/** NVIC mask style interrupt disable.
* @param[in] mask
@ -177,21 +177,21 @@ extern "C" {
* Mask specifying which NVIC interrupts to disable within the section.
* @param[in] yourcode
* The code for the section. */
#define CORE_NVIC_SECTION(mask, yourcode) \
{ \
CORE_DECLARE_NVIC_STATE; \
CORE_ENTER_NVIC(mask); \
{ \
yourcode \
} \
CORE_EXIT_NVIC(); \
}
#define CORE_NVIC_SECTION(mask, yourcode) \
{ \
CORE_DECLARE_NVIC_STATE; \
CORE_ENTER_NVIC(mask); \
{ \
yourcode \
} \
CORE_EXIT_NVIC(); \
}
/** Enter NVIC mask section. Assumes that a @ref CORE_DECLARE_NVIC_STATE exist
* in scope.
* @param[in] disable
* Mask specifying which NVIC interrupts to disable within the section. */
#define CORE_ENTER_NVIC(disable) CORE_EnterNvicMask(&nvicState,disable)
#define CORE_ENTER_NVIC(disable) CORE_EnterNvicMask(&nvicState, disable)
/** Exit NVIC mask section. Assumes that a @ref CORE_DECLARE_NVIC_STATE exist
* in scope. */

34
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cryotimer.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_cryotimer.h
* @brief Ultra Low Energy Timer/Counter (CRYOTIMER) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -116,8 +116,7 @@ extern "C" {
******************************************************************************/
/** Prescaler selection. */
typedef enum
{
typedef enum {
cryotimerPresc_1 = _CRYOTIMER_CTRL_PRESC_DIV1, /**< Divide clock by 1. */
cryotimerPresc_2 = _CRYOTIMER_CTRL_PRESC_DIV2, /**< Divide clock by 2. */
cryotimerPresc_4 = _CRYOTIMER_CTRL_PRESC_DIV4, /**< Divide clock by 4. */
@ -129,16 +128,14 @@ typedef enum
} CRYOTIMER_Presc_TypeDef;
/** Low frequency oscillator selection. */
typedef enum
{
typedef enum {
cryotimerOscLFRCO = _CRYOTIMER_CTRL_OSCSEL_LFRCO, /**< Select Low Frequency RC Oscillator. */
cryotimerOscLFXO = _CRYOTIMER_CTRL_OSCSEL_LFXO, /**< Select Low Frequency Crystal Oscillator. */
cryotimerOscULFRCO = _CRYOTIMER_CTRL_OSCSEL_ULFRCO, /**< Select Ultra Low Frequency RC Oscillator. */
} CRYOTIMER_Osc_TypeDef;
/** Period selection value */
typedef enum
{
typedef enum {
cryotimerPeriod_1 = 0, /**< Wakeup event after every Pre-scaled clock cycle. */
cryotimerPeriod_2 = 1, /**< Wakeup event after 2 Pre-scaled clock cycles. */
cryotimerPeriod_4 = 2, /**< Wakeup event after 4 Pre-scaled clock cycles. */
@ -179,8 +176,7 @@ typedef enum
******************************************************************************/
/** CRYOTIMER initialization structure. */
typedef struct
{
typedef struct {
/** Enable/disable counting when initialization is completed. */
bool enable;
@ -205,15 +201,15 @@ typedef struct
******************************************************************************/
/** Default CRYOTIMER init structure. */
#define CRYOTIMER_INIT_DEFAULT \
{ \
true, /* Start counting when init done. */ \
false, /* Disable CRYOTIMER during debug halt. */ \
false, /* Disable EM4 wakeup. */ \
cryotimerOscLFRCO, /* Select Low Frequency RC Oscillator. */ \
cryotimerPresc_1, /* LF Oscillator frequency undivided. */ \
cryotimerPeriod_4096m, /* Wakeup event after 4096M pre-scaled clock cycles. */ \
}
#define CRYOTIMER_INIT_DEFAULT \
{ \
true, /* Start counting when init done. */ \
false, /* Disable CRYOTIMER during debug halt. */ \
false, /* Disable EM4 wakeup. */ \
cryotimerOscLFRCO, /* Select Low Frequency RC Oscillator. */ \
cryotimerPresc_1, /* LF Oscillator frequency undivided. */ \
cryotimerPeriod_4096m, /* Wakeup event after 4096M pre-scaled clock cycles. */ \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************

443
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crypto.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_crypto.h
* @brief Cryptography accelerator peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -187,37 +187,46 @@ extern "C" {
* @{
******************************************************************************/
/*******************************************************************************
/*******************************************************************************
****************************** DEFINES ***********************************
******************************************************************************/
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** Default CRYPTO instance for deprecated AES functions. */
#if !defined(DEFAULT_CRYPTO)
#if defined(CRYPTO)
#define DEFAULT_CRYPTO CRYPTO
#elif defined(CRYPTO0)
#define DEFAULT_CRYPTO CRYPTO0
#endif
#endif
/** Data sizes used by CRYPTO operations. */
#define CRYPTO_DATA_SIZE_IN_BITS (128)
#define CRYPTO_DATA_SIZE_IN_BYTES (CRYPTO_DATA_SIZE_IN_BITS/8)
#define CRYPTO_DATA_SIZE_IN_32BIT_WORDS (CRYPTO_DATA_SIZE_IN_BYTES/sizeof(uint32_t))
#define CRYPTO_DATA_SIZE_IN_BYTES (CRYPTO_DATA_SIZE_IN_BITS / 8)
#define CRYPTO_DATA_SIZE_IN_32BIT_WORDS (CRYPTO_DATA_SIZE_IN_BYTES / sizeof(uint32_t))
#define CRYPTO_KEYBUF_SIZE_IN_BITS (256)
#define CRYPTO_KEYBUF_SIZE_IN_BYTES (CRYPTO_DDATA_SIZE_IN_BITS/8)
#define CRYPTO_KEYBUF_SIZE_IN_32BIT_WORDS (CRYPTO_DDATA_SIZE_IN_BYTES/sizeof(uint32_t))
#define CRYPTO_KEYBUF_SIZE_IN_BYTES (CRYPTO_DDATA_SIZE_IN_BITS / 8)
#define CRYPTO_KEYBUF_SIZE_IN_32BIT_WORDS (CRYPTO_DDATA_SIZE_IN_BYTES / sizeof(uint32_t))
#define CRYPTO_DDATA_SIZE_IN_BITS (256)
#define CRYPTO_DDATA_SIZE_IN_BYTES (CRYPTO_DDATA_SIZE_IN_BITS/8)
#define CRYPTO_DDATA_SIZE_IN_32BIT_WORDS (CRYPTO_DDATA_SIZE_IN_BYTES/sizeof(uint32_t))
#define CRYPTO_DDATA_SIZE_IN_BYTES (CRYPTO_DDATA_SIZE_IN_BITS / 8)
#define CRYPTO_DDATA_SIZE_IN_32BIT_WORDS (CRYPTO_DDATA_SIZE_IN_BYTES / sizeof(uint32_t))
#define CRYPTO_QDATA_SIZE_IN_BITS (512)
#define CRYPTO_QDATA_SIZE_IN_BYTES (CRYPTO_QDATA_SIZE_IN_BITS/8)
#define CRYPTO_QDATA_SIZE_IN_32BIT_WORDS (CRYPTO_QDATA_SIZE_IN_BYTES/sizeof(uint32_t))
#define CRYPTO_QDATA_SIZE_IN_BYTES (CRYPTO_QDATA_SIZE_IN_BITS / 8)
#define CRYPTO_QDATA_SIZE_IN_32BIT_WORDS (CRYPTO_QDATA_SIZE_IN_BYTES / sizeof(uint32_t))
#define CRYPTO_DATA260_SIZE_IN_32BIT_WORDS (9)
/** SHA-1 digest sizes */
#define CRYPTO_SHA1_DIGEST_SIZE_IN_BITS (160)
#define CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES (CRYPTO_SHA1_DIGEST_SIZE_IN_BITS/8)
#define CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES (CRYPTO_SHA1_DIGEST_SIZE_IN_BITS / 8)
/** SHA-256 digest sizes */
#define CRYPTO_SHA256_DIGEST_SIZE_IN_BITS (256)
#define CRYPTO_SHA256_DIGEST_SIZE_IN_BYTES (CRYPTO_SHA256_DIGEST_SIZE_IN_BITS/8)
#define CRYPTO_SHA256_DIGEST_SIZE_IN_BYTES (CRYPTO_SHA256_DIGEST_SIZE_IN_BITS / 8)
/**
* Read and write all 260 bits of DDATA0 when in 260 bit mode.
@ -233,89 +242,89 @@ extern "C" {
* Use these macros in order for faster execution than the function API.
*/
#define CRYPTO_SEQ_LOAD_1(crypto, a1) { \
crypto->SEQ0 = a1 | (CRYPTO_CMD_INSTR_END<<8);}
crypto->SEQ0 = a1 | (CRYPTO_CMD_INSTR_END << 8); }
#define CRYPTO_SEQ_LOAD_2(crypto, a1, a2) { \
crypto->SEQ0 = a1 | (a2<<8) | (CRYPTO_CMD_INSTR_END<<16);}
crypto->SEQ0 = a1 | (a2 << 8) | (CRYPTO_CMD_INSTR_END << 16); }
#define CRYPTO_SEQ_LOAD_3(crypto, a1, a2, a3) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (CRYPTO_CMD_INSTR_END<<24);}
#define CRYPTO_SEQ_LOAD_4(crypto, a1, a2, a3, a4) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = CRYPTO_CMD_INSTR_END;}
#define CRYPTO_SEQ_LOAD_5(crypto, a1, a2, a3, a4, a5) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (CRYPTO_CMD_INSTR_END<<8);}
#define CRYPTO_SEQ_LOAD_6(crypto, a1, a2, a3, a4, a5, a6) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (CRYPTO_CMD_INSTR_END<<16);}
#define CRYPTO_SEQ_LOAD_7(crypto, a1, a2, a3, a4, a5, a6, a7) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (CRYPTO_CMD_INSTR_END<<24);}
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (CRYPTO_CMD_INSTR_END << 24); }
#define CRYPTO_SEQ_LOAD_4(crypto, a1, a2, a3, a4) { \
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = CRYPTO_CMD_INSTR_END; }
#define CRYPTO_SEQ_LOAD_5(crypto, a1, a2, a3, a4, a5) { \
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (CRYPTO_CMD_INSTR_END << 8); }
#define CRYPTO_SEQ_LOAD_6(crypto, a1, a2, a3, a4, a5, a6) { \
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (CRYPTO_CMD_INSTR_END << 16); }
#define CRYPTO_SEQ_LOAD_7(crypto, a1, a2, a3, a4, a5, a6, a7) { \
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (CRYPTO_CMD_INSTR_END << 24); }
#define CRYPTO_SEQ_LOAD_8(crypto, a1, a2, a3, a4, a5, a6, a7, a8) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = CRYPTO_CMD_INSTR_END;}
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = CRYPTO_CMD_INSTR_END; }
#define CRYPTO_SEQ_LOAD_9(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (CRYPTO_CMD_INSTR_END<<8);}
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (CRYPTO_CMD_INSTR_END << 8); }
#define CRYPTO_SEQ_LOAD_10(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (CRYPTO_CMD_INSTR_END<<16);}
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (CRYPTO_CMD_INSTR_END << 16); }
#define CRYPTO_SEQ_LOAD_11(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (CRYPTO_CMD_INSTR_END<<24);}
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (CRYPTO_CMD_INSTR_END << 24); }
#define CRYPTO_SEQ_LOAD_12(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ3 = CRYPTO_CMD_INSTR_END;}
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = CRYPTO_CMD_INSTR_END; }
#define CRYPTO_SEQ_LOAD_13(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ3 = a13 | (CRYPTO_CMD_INSTR_END<<8);}
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = a13 | (CRYPTO_CMD_INSTR_END << 8); }
#define CRYPTO_SEQ_LOAD_14(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ3 = a13 | (a14<<8) | (CRYPTO_CMD_INSTR_END<<16);}
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = a13 | (a14 << 8) | (CRYPTO_CMD_INSTR_END << 16); }
#define CRYPTO_SEQ_LOAD_15(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (CRYPTO_CMD_INSTR_END<<24);}
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (CRYPTO_CMD_INSTR_END << 24); }
#define CRYPTO_SEQ_LOAD_16(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
crypto->SEQ4 = CRYPTO_CMD_INSTR_END;}
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
crypto->SEQ4 = CRYPTO_CMD_INSTR_END; }
#define CRYPTO_SEQ_LOAD_17(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
crypto->SEQ4 = a17 | (CRYPTO_CMD_INSTR_END<<8);}
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
crypto->SEQ4 = a17 | (CRYPTO_CMD_INSTR_END << 8); }
#define CRYPTO_SEQ_LOAD_18(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
crypto->SEQ4 = a17 | (a18<<8) | (CRYPTO_CMD_INSTR_END<<16);}
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
crypto->SEQ4 = a17 | (a18 << 8) | (CRYPTO_CMD_INSTR_END << 16); }
#define CRYPTO_SEQ_LOAD_19(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
crypto->SEQ4 = a17 | (a18<<8) | (a19<<16) | (CRYPTO_CMD_INSTR_END<<24);}
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
crypto->SEQ4 = a17 | (a18 << 8) | (a19 << 16) | (CRYPTO_CMD_INSTR_END << 24); }
#define CRYPTO_SEQ_LOAD_20(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
crypto->SEQ4 = a17 | (a18<<8) | (a19<<16) | (a20<<24);}
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
crypto->SEQ4 = a17 | (a18 << 8) | (a19 << 16) | (a20 << 24); }
/** @endcond */
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
@ -324,91 +333,91 @@ extern "C" {
* 1-20). E.g. @ref CRYPTO_EXECUTE_19.
* Use these macros in order for faster execution than the function API.
*/
#define CRYPTO_EXECUTE_1(crypto, a1) { \
crypto->SEQ0 = a1 | (CRYPTO_CMD_INSTR_EXEC<<8); }
#define CRYPTO_EXECUTE_2(crypto, a1, a2) { \
crypto->SEQ0 = a1 | (a2<<8) | (CRYPTO_CMD_INSTR_EXEC<<16); }
#define CRYPTO_EXECUTE_3(crypto, a1, a2, a3) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }
#define CRYPTO_EXECUTE_4(crypto, a1, a2, a3, a4) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
#define CRYPTO_EXECUTE_1(crypto, a1) { \
crypto->SEQ0 = a1 | (CRYPTO_CMD_INSTR_EXEC << 8); }
#define CRYPTO_EXECUTE_2(crypto, a1, a2) { \
crypto->SEQ0 = a1 | (a2 << 8) | (CRYPTO_CMD_INSTR_EXEC << 16); }
#define CRYPTO_EXECUTE_3(crypto, a1, a2, a3) { \
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (CRYPTO_CMD_INSTR_EXEC << 24); }
#define CRYPTO_EXECUTE_4(crypto, a1, a2, a3, a4) { \
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = CRYPTO_CMD_INSTR_EXEC; }
#define CRYPTO_EXECUTE_5(crypto, a1, a2, a3, a4, a5) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (CRYPTO_CMD_INSTR_EXEC<<8); }
#define CRYPTO_EXECUTE_6(crypto, a1, a2, a3, a4, a5, a6) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (CRYPTO_CMD_INSTR_EXEC<<16); }
#define CRYPTO_EXECUTE_7(crypto, a1, a2, a3, a4, a5, a6, a7) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }
#define CRYPTO_EXECUTE_8(crypto, a1, a2, a3, a4, a5, a6, a7, a8) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
#define CRYPTO_EXECUTE_5(crypto, a1, a2, a3, a4, a5) { \
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (CRYPTO_CMD_INSTR_EXEC << 8); }
#define CRYPTO_EXECUTE_6(crypto, a1, a2, a3, a4, a5, a6) { \
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (CRYPTO_CMD_INSTR_EXEC << 16); }
#define CRYPTO_EXECUTE_7(crypto, a1, a2, a3, a4, a5, a6, a7) { \
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (CRYPTO_CMD_INSTR_EXEC << 24); }
#define CRYPTO_EXECUTE_8(crypto, a1, a2, a3, a4, a5, a6, a7, a8) { \
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = CRYPTO_CMD_INSTR_EXEC; }
#define CRYPTO_EXECUTE_9(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (CRYPTO_CMD_INSTR_EXEC<<8); }
#define CRYPTO_EXECUTE_10(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (CRYPTO_CMD_INSTR_EXEC<<16); }
#define CRYPTO_EXECUTE_9(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9) { \
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (CRYPTO_CMD_INSTR_EXEC << 8); }
#define CRYPTO_EXECUTE_10(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10) { \
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (CRYPTO_CMD_INSTR_EXEC << 16); }
#define CRYPTO_EXECUTE_11(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (CRYPTO_CMD_INSTR_EXEC << 24); }
#define CRYPTO_EXECUTE_12(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = CRYPTO_CMD_INSTR_EXEC; }
#define CRYPTO_EXECUTE_13(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ3 = a13 | (CRYPTO_CMD_INSTR_EXEC<<8); }
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = a13 | (CRYPTO_CMD_INSTR_EXEC << 8); }
#define CRYPTO_EXECUTE_14(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ3 = a13 | (a14<<8) | (CRYPTO_CMD_INSTR_EXEC<<16); }
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = a13 | (a14 << 8) | (CRYPTO_CMD_INSTR_EXEC << 16); }
#define CRYPTO_EXECUTE_15(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (CRYPTO_CMD_INSTR_EXEC << 24); }
#define CRYPTO_EXECUTE_16(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
crypto->SEQ4 = CRYPTO_CMD_INSTR_EXEC; }
#define CRYPTO_EXECUTE_17(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
crypto->SEQ4 = a17 | (CRYPTO_CMD_INSTR_EXEC<<8); }
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
crypto->SEQ4 = a17 | (CRYPTO_CMD_INSTR_EXEC << 8); }
#define CRYPTO_EXECUTE_18(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
crypto->SEQ4 = a17 | (a18<<8) | (CRYPTO_CMD_INSTR_EXEC<<16); }
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
crypto->SEQ4 = a17 | (a18 << 8) | (CRYPTO_CMD_INSTR_EXEC << 16); }
#define CRYPTO_EXECUTE_19(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
crypto->SEQ4 = a17 | (a18<<8) | (a19<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
crypto->SEQ4 = a17 | (a18 << 8) | (a19 << 16) | (CRYPTO_CMD_INSTR_EXEC << 24); }
#define CRYPTO_EXECUTE_20(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20) { \
crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
crypto->SEQ4 = a17 | (a18<<8) | (a19<<16) | (a20<<24); \
CRYPTO_InstructionSequenceExecute();}
crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
crypto->SEQ4 = a17 | (a18 << 8) | (a19 << 16) | (a20 << 24); \
CRYPTO_InstructionSequenceExecute(); }
/** @endcond */
/*******************************************************************************
@ -478,8 +487,7 @@ typedef volatile uint32_t* CRYPTO_DDataReg_TypeDef;
typedef volatile uint32_t* CRYPTO_QDataReg_TypeDef;
/** CRYPTO modulus identifiers. */
typedef enum
{
typedef enum {
cryptoModulusBin256 = CRYPTO_WAC_MODULUS_BIN256, /**< Generic 256 bit modulus 2^256 */
cryptoModulusBin128 = CRYPTO_WAC_MODULUS_BIN128, /**< Generic 128 bit modulus 2^128 */
cryptoModulusGcmBin128 = CRYPTO_WAC_MODULUS_GCMBIN128, /**< GCM 128 bit modulus = 2^128 + 2^7 + 2^2 + 2 + 1 */
@ -498,8 +506,7 @@ typedef enum
} CRYPTO_ModulusId_TypeDef;
/** CRYPTO multiplication widths for wide arithmetic operations. */
typedef enum
{
typedef enum {
cryptoMulOperand256Bits = CRYPTO_WAC_MULWIDTH_MUL256, /**< 256 bits operands */
cryptoMulOperand128Bits = CRYPTO_WAC_MULWIDTH_MUL128, /**< 128 bits operands */
cryptoMulOperandModulusBits = CRYPTO_WAC_MULWIDTH_MULMOD /**< MUL operand width
@ -508,16 +515,14 @@ typedef enum
} CRYPTO_MulOperandWidth_TypeDef;
/** CRYPTO result widths for MUL operations. */
typedef enum
{
typedef enum {
cryptoResult128Bits = CRYPTO_WAC_RESULTWIDTH_128BIT, /**< Multiplication result width is 128 bits*/
cryptoResult256Bits = CRYPTO_WAC_RESULTWIDTH_256BIT, /**< Multiplication result width is 256 bits*/
cryptoResult260Bits = CRYPTO_WAC_RESULTWIDTH_260BIT /**< Multiplication result width is 260 bits*/
} CRYPTO_ResultWidth_TypeDef;
/** CRYPTO result widths for MUL operations. */
typedef enum
{
typedef enum {
cryptoInc1byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH1, /**< inc width is 1 byte*/
cryptoInc2byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH2, /**< inc width is 2 byte*/
cryptoInc3byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH3, /**< inc width is 3 byte*/
@ -525,8 +530,7 @@ typedef enum
} CRYPTO_IncWidth_TypeDef;
/** CRYPTO key width. */
typedef enum
{
typedef enum {
cryptoKey128Bits = 8, /**< Key width is 128 bits*/
cryptoKey256Bits = 16, /**< Key width is 256 bits*/
} CRYPTO_KeyWidth_TypeDef;
@ -549,14 +553,14 @@ typedef uint8_t CRYPTO_InstructionSequence_TypeDef[CRYPTO_MAX_SEQUENCE_INSTRUCTI
initialize the instruction sequence with this default value set, and fill
in the desired operations from step 1. The first END instruction marks
the end of the sequence. */
#define CRYPTO_INSTRUCTIONSEQUENSE_DEFAULT \
{CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END}
#define CRYPTO_INSTRUCTIONSEQUENSE_DEFAULT \
{ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END }
/** SHA-1 Digest type. */
typedef uint8_t CRYPTO_SHA1_Digest_TypeDef[CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES];
@ -861,15 +865,12 @@ __STATIC_INLINE void CRYPTO_KeyBufWrite(CRYPTO_TypeDef *crypto,
CRYPTO_KeyBuf_TypeDef val,
CRYPTO_KeyWidth_TypeDef keyWidth)
{
if (keyWidth == cryptoKey256Bits)
{
if (keyWidth == cryptoKey256Bits) {
/* Set AES-256 mode */
BUS_RegBitWrite(&crypto->CTRL, _CRYPTO_CTRL_AES_SHIFT, _CRYPTO_CTRL_AES_AES256);
/* Load key in KEYBUF register (= DDATA4) */
CRYPTO_DDataWrite(&crypto->DDATA4, (uint32_t *)val);
}
else
{
} else {
/* Set AES-128 mode */
BUS_RegBitWrite(&crypto->CTRL, _CRYPTO_CTRL_AES_SHIFT, _CRYPTO_CTRL_AES_AES128);
CRYPTO_BurstToCrypto(&crypto->KEYBUF, &val[0]);
@ -915,7 +916,7 @@ __STATIC_INLINE void CRYPTO_KeyBuf128Write(CRYPTO_TypeDef *crypto,
__STATIC_INLINE bool CRYPTO_CarryIsSet(CRYPTO_TypeDef *crypto)
{
return (crypto->DSTATUS & _CRYPTO_DSTATUS_CARRY_MASK)
>> _CRYPTO_DSTATUS_CARRY_SHIFT;
>> _CRYPTO_DSTATUS_CARRY_SHIFT;
}
/***************************************************************************//**
@ -935,7 +936,7 @@ __STATIC_INLINE bool CRYPTO_CarryIsSet(CRYPTO_TypeDef *crypto)
__STATIC_INLINE uint8_t CRYPTO_DData0_4LSBitsRead(CRYPTO_TypeDef *crypto)
{
return (crypto->DSTATUS & _CRYPTO_DSTATUS_DDATA0LSBS_MASK)
>> _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT;
>> _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT;
}
/***************************************************************************//**
@ -959,7 +960,7 @@ __STATIC_INLINE void CRYPTO_DData0Read260(CRYPTO_TypeDef *crypto,
{
CRYPTO_DDataRead(&crypto->DDATA0, val);
val[8] = (crypto->DSTATUS & _CRYPTO_DSTATUS_DDATA0MSBS_MASK)
>> _CRYPTO_DSTATUS_DDATA0MSBS_SHIFT;
>> _CRYPTO_DSTATUS_DDATA0MSBS_SHIFT;
}
/***************************************************************************//**
@ -1004,7 +1005,7 @@ __STATIC_INLINE void CRYPTO_DData0Write260(CRYPTO_TypeDef *crypto,
__STATIC_INLINE bool CRYPTO_DData1_MSBitRead(CRYPTO_TypeDef *crypto)
{
return (crypto->DSTATUS & _CRYPTO_DSTATUS_DDATA1MSB_MASK)
>> _CRYPTO_DSTATUS_DDATA1MSB_SHIFT;
>> _CRYPTO_DSTATUS_DDATA1MSB_SHIFT;
}
/***************************************************************************//**
@ -1336,13 +1337,13 @@ __STATIC_INLINE void CRYPTO_IntSet(CRYPTO_TypeDef *crypto, uint32_t flags)
* @ref CRYPTO_AES_CBC128 instead.
******************************************************************************/
__STATIC_INLINE void AES_CBC128(uint8_t * out,
const uint8_t * in,
unsigned int len,
const uint8_t * key,
const uint8_t * iv,
bool encrypt)
const uint8_t * in,
unsigned int len,
const uint8_t * key,
const uint8_t * iv,
bool encrypt)
{
CRYPTO_AES_CBC128(CRYPTO, out, in, len, key, iv, encrypt);
CRYPTO_AES_CBC128(DEFAULT_CRYPTO, out, in, len, key, iv, encrypt);
}
/***************************************************************************//**
@ -1355,13 +1356,13 @@ __STATIC_INLINE void AES_CBC128(uint8_t * out,
* @ref CRYPTO_AES_CBC256 instead.
******************************************************************************/
__STATIC_INLINE void AES_CBC256(uint8_t * out,
const uint8_t * in,
unsigned int len,
const uint8_t * key,
const uint8_t * iv,
bool encrypt)
const uint8_t * in,
unsigned int len,
const uint8_t * key,
const uint8_t * iv,
bool encrypt)
{
CRYPTO_AES_CBC256(CRYPTO, out, in, len, key, iv, encrypt);
CRYPTO_AES_CBC256(DEFAULT_CRYPTO, out, in, len, key, iv, encrypt);
}
/***************************************************************************//**
@ -1373,13 +1374,13 @@ __STATIC_INLINE void AES_CBC256(uint8_t * out,
* @ref CRYPTO_AES_CFB128 instead.
******************************************************************************/
__STATIC_INLINE void AES_CFB128(uint8_t * out,
const uint8_t * in,
unsigned int len,
const uint8_t * key,
const uint8_t * iv,
bool encrypt)
const uint8_t * in,
unsigned int len,
const uint8_t * key,
const uint8_t * iv,
bool encrypt)
{
CRYPTO_AES_CFB128(CRYPTO, out, in, len, key, iv, encrypt);
CRYPTO_AES_CFB128(DEFAULT_CRYPTO, out, in, len, key, iv, encrypt);
}
/***************************************************************************//**
@ -1391,13 +1392,13 @@ __STATIC_INLINE void AES_CFB128(uint8_t * out,
* @ref CRYPTO_AES_CFB256 instead.
******************************************************************************/
__STATIC_INLINE void AES_CFB256(uint8_t * out,
const uint8_t * in,
unsigned int len,
const uint8_t * key,
const uint8_t * iv,
bool encrypt)
const uint8_t * in,
unsigned int len,
const uint8_t * key,
const uint8_t * iv,
bool encrypt)
{
CRYPTO_AES_CFB256(CRYPTO, out, in, len, key, iv, encrypt);
CRYPTO_AES_CFB256(DEFAULT_CRYPTO, out, in, len, key, iv, encrypt);
}
/***************************************************************************//**
@ -1409,13 +1410,13 @@ __STATIC_INLINE void AES_CFB256(uint8_t * out,
* @ref CRYPTO_AES_CTR128 instead.
******************************************************************************/
__STATIC_INLINE void AES_CTR128(uint8_t * out,
const uint8_t * in,
unsigned int len,
const uint8_t * key,
uint8_t * ctr,
CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc)
const uint8_t * in,
unsigned int len,
const uint8_t * key,
uint8_t * ctr,
CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc)
{
CRYPTO_AES_CTR128(CRYPTO, out, in, len, key, ctr, ctrFunc);
CRYPTO_AES_CTR128(DEFAULT_CRYPTO, out, in, len, key, ctr, ctrFunc);
}
/***************************************************************************//**
@ -1427,13 +1428,13 @@ __STATIC_INLINE void AES_CTR128(uint8_t * out,
* @ref CRYPTO_AES_CTR256 instead.
******************************************************************************/
__STATIC_INLINE void AES_CTR256(uint8_t * out,
const uint8_t * in,
unsigned int len,
const uint8_t * key,
uint8_t * ctr,
CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc)
const uint8_t * in,
unsigned int len,
const uint8_t * key,
uint8_t * ctr,
CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc)
{
CRYPTO_AES_CTR256(CRYPTO, out, in, len, key, ctr, ctrFunc);
CRYPTO_AES_CTR256(DEFAULT_CRYPTO, out, in, len, key, ctr, ctrFunc);
}
/***************************************************************************//**
@ -1460,7 +1461,7 @@ __STATIC_INLINE void AES_CTRUpdate32Bit(uint8_t * ctr)
******************************************************************************/
__STATIC_INLINE void AES_DecryptKey128(uint8_t * out, const uint8_t * in)
{
CRYPTO_AES_DecryptKey128(CRYPTO, out, in);
CRYPTO_AES_DecryptKey128(DEFAULT_CRYPTO, out, in);
}
/***************************************************************************//**
@ -1474,7 +1475,7 @@ __STATIC_INLINE void AES_DecryptKey128(uint8_t * out, const uint8_t * in)
******************************************************************************/
__STATIC_INLINE void AES_DecryptKey256(uint8_t * out, const uint8_t * in)
{
CRYPTO_AES_DecryptKey256(CRYPTO, out, in);
CRYPTO_AES_DecryptKey256(DEFAULT_CRYPTO, out, in);
}
/***************************************************************************//**
@ -1492,7 +1493,7 @@ __STATIC_INLINE void AES_ECB128(uint8_t * out,
const uint8_t * key,
bool encrypt)
{
CRYPTO_AES_ECB128(CRYPTO, out, in, len, key, encrypt);
CRYPTO_AES_ECB128(DEFAULT_CRYPTO, out, in, len, key, encrypt);
}
/***************************************************************************//**
@ -1510,7 +1511,7 @@ __STATIC_INLINE void AES_ECB256(uint8_t * out,
const uint8_t * key,
bool encrypt)
{
CRYPTO_AES_ECB256(CRYPTO, out, in, len, key, encrypt);
CRYPTO_AES_ECB256(DEFAULT_CRYPTO, out, in, len, key, encrypt);
}
/***************************************************************************//**
@ -1527,7 +1528,7 @@ __STATIC_INLINE void AES_OFB128(uint8_t * out,
const uint8_t * key,
const uint8_t * iv)
{
CRYPTO_AES_OFB128(CRYPTO, out, in, len, key, iv);
CRYPTO_AES_OFB128(DEFAULT_CRYPTO, out, in, len, key, iv);
}
/***************************************************************************//**
@ -1544,7 +1545,7 @@ __STATIC_INLINE void AES_OFB256(uint8_t * out,
const uint8_t * key,
const uint8_t * iv)
{
CRYPTO_AES_OFB256(CRYPTO, out, in, len, key, iv);
CRYPTO_AES_OFB256(DEFAULT_CRYPTO, out, in, len, key, iv);
}
#ifdef __cplusplus

245
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_csen.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_csen.h
* @brief Capacitive Sense Module (CSEN) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -34,7 +34,7 @@
#define EM_CSEN_H
#include "em_device.h"
#if defined( CSEN_COUNT ) && ( CSEN_COUNT > 0 )
#if defined(CSEN_COUNT) && (CSEN_COUNT > 0)
#include <stdbool.h>
#include "em_bus.h"
@ -53,24 +53,24 @@ extern "C" {
* @brief Capacitive Sense (CSEN) Peripheral API
*
* @details
* This module provides functions for controlling the capacitive sense
* peripheral of Silicon Labs 32-bit MCUs and SoCs. The CSEN includes a
* capacitance-to-digital circuit that measures capacitance on selected
* inputs. Measurements are performed using either a successive approximation
* This module provides functions for controlling the capacitive sense
* peripheral of Silicon Labs 32-bit MCUs and SoCs. The CSEN includes a
* capacitance-to-digital circuit that measures capacitance on selected
* inputs. Measurements are performed using either a successive approximation
* register (SAR) or a delta modulator (DM) analog to digital converter.
*
* The CSEN can be configured to measure capacitance on a single port pin
* or to automatically measure multiple port pins in succession using scan
* mode. Also several port pins can be shorted together to measure the
* The CSEN can be configured to measure capacitance on a single port pin
* or to automatically measure multiple port pins in succession using scan
* mode. Also several port pins can be shorted together to measure the
* combined capacitance.
*
* The CSEN includes an accumulator which can be configured to average
* multiple conversions on the selected input. Additionally, an exponential
* moving average (EMA) calculator is included to provide data smoothing.
* A comparator is also included and can be used to terminate a continuous
* The CSEN includes an accumulator which can be configured to average
* multiple conversions on the selected input. Additionally, an exponential
* moving average (EMA) calculator is included to provide data smoothing.
* A comparator is also included and can be used to terminate a continuous
* conversion when the configured threshold condition is met.
*
* The following example shows how to intialize and start a single
* The following example shows how to intialize and start a single
* conversion on one input:
*
* @include em_csen_single.c
@ -83,8 +83,7 @@ extern "C" {
******************************************************************************/
/** Comparator Mode. Selects the operation of the digital comparator. */
typedef enum
{
typedef enum {
/** Comparator is disabled. */
csenCmpModeDisabled = 0,
@ -98,10 +97,8 @@ typedef enum
csenCmpModeEMAWindow = CSEN_CTRL_EMACMPEN,
} CSEN_CmpMode_TypeDef;
/** Converter Select. Determines the converter operational mode. */
typedef enum
{
typedef enum {
/** Successive Approximation (SAR) converter. */
csenConvSelSAR = CSEN_CTRL_CONVSEL_SAR,
@ -115,10 +112,8 @@ typedef enum
csenConvSelDMChop = CSEN_CTRL_CONVSEL_DM | CSEN_CTRL_CHOPEN_ENABLE,
} CSEN_ConvSel_TypeDef;
/** Sample Mode. Determines how inputs are sampled for a conversion. */
typedef enum
{
typedef enum {
/** Convert multiple inputs shorted together and stop. */
csenSampleModeBonded = CSEN_CTRL_CM_SGL | CSEN_CTRL_MCEN_ENABLE,
@ -138,19 +133,15 @@ typedef enum
csenSampleModeContScan = CSEN_CTRL_CM_CONTSCAN,
} CSEN_SampleMode_TypeDef;
/** Start Trigger Select. */
typedef enum
{
typedef enum {
csenTrigSelPRS = _CSEN_CTRL_STM_PRS, /**< PRS system. */
csenTrigSelTimer = _CSEN_CTRL_STM_TIMER, /**< CSEN PC timer. */
csenTrigSelStart = _CSEN_CTRL_STM_START, /**< Start bit. */
} CSEN_TrigSel_TypeDef;
/** Accumulator Mode Select. */
typedef enum
{
typedef enum {
csenAccMode1 = _CSEN_CTRL_ACU_ACC1, /**< Accumulate 1 sample. */
csenAccMode2 = _CSEN_CTRL_ACU_ACC2, /**< Accumulate 2 samples. */
csenAccMode4 = _CSEN_CTRL_ACU_ACC4, /**< Accumulate 4 samples. */
@ -160,31 +151,25 @@ typedef enum
csenAccMode64 = _CSEN_CTRL_ACU_ACC64, /**< Accumulate 64 samples. */
} CSEN_AccMode_TypeDef;
/** Successive Approximation (SAR) Conversion Resolution. */
typedef enum
{
typedef enum {
csenSARRes10 = _CSEN_CTRL_SARCR_CLK10, /**< 10-bit resolution. */
csenSARRes12 = _CSEN_CTRL_SARCR_CLK12, /**< 12-bit resolution. */
csenSARRes14 = _CSEN_CTRL_SARCR_CLK14, /**< 14-bit resolution. */
csenSARRes16 = _CSEN_CTRL_SARCR_CLK16, /**< 16-bit resolution. */
} CSEN_SARRes_TypeDef;
/** Delta Modulator (DM) Conversion Resolution. */
typedef enum
{
typedef enum {
csenDMRes10 = _CSEN_DMCFG_CRMODE_DM10, /**< 10-bit resolution. */
csenDMRes12 = _CSEN_DMCFG_CRMODE_DM12, /**< 12-bit resolution. */
csenDMRes14 = _CSEN_DMCFG_CRMODE_DM14, /**< 14-bit resolution. */
csenDMRes16 = _CSEN_DMCFG_CRMODE_DM16, /**< 16-bit resolution. */
} CSEN_DMRes_TypeDef;
/** Period counter clock pre-scaler. See the reference manual for source clock
/** Period counter clock pre-scaler. See the reference manual for source clock
* information. */
typedef enum
{
typedef enum {
csenPCPrescaleDiv1 = _CSEN_TIMCTRL_PCPRESC_DIV1, /**< Divide by 1. */
csenPCPrescaleDiv2 = _CSEN_TIMCTRL_PCPRESC_DIV2, /**< Divide by 2. */
csenPCPrescaleDiv4 = _CSEN_TIMCTRL_PCPRESC_DIV4, /**< Divide by 4. */
@ -195,10 +180,8 @@ typedef enum
csenPCPrescaleDiv128 = _CSEN_TIMCTRL_PCPRESC_DIV128, /**< Divide by 128. */
} CSEN_PCPrescale_TypeDef;
/** Exponential Moving Average sample weight. */
typedef enum
{
typedef enum {
csenEMASampleW1 = _CSEN_EMACTRL_EMASAMPLE_W1, /**< Weight 1. */
csenEMASampleW2 = _CSEN_EMACTRL_EMASAMPLE_W2, /**< Weight 2. */
csenEMASampleW4 = _CSEN_EMACTRL_EMASAMPLE_W4, /**< Weight 4. */
@ -208,10 +191,8 @@ typedef enum
csenEMASampleW64 = _CSEN_EMACTRL_EMASAMPLE_W64, /**< Weight 64. */
} CSEN_EMASample_TypeDef;
/** Reset Phase Timing Select (units are microseconds). */
typedef enum
{
typedef enum {
csenResetPhaseSel0 = 0, /**< Reset phase time = 0.75 usec. */
csenResetPhaseSel1 = 1, /**< Reset phase time = 1.00 usec. */
csenResetPhaseSel2 = 2, /**< Reset phase time = 1.20 usec. */
@ -222,10 +203,8 @@ typedef enum
csenResetPhaseSel7 = 7, /**< Reset phase time = 12.0 usec. */
} CSEN_ResetPhaseSel_TypeDef;
/** Drive Strength Select. Scales the output current. */
typedef enum
{
typedef enum {
csenDriveSelFull = 0, /**< Drive strength = fully on. */
csenDriveSel1 = 1, /**< Drive strength = 1/8 full scale. */
csenDriveSel2 = 2, /**< Drive strength = 1/4 full scale. */
@ -236,10 +215,8 @@ typedef enum
csenDriveSel7 = 7, /**< Drive strength = 7/8 full scale. */
} CSEN_DriveSel_TypeDef;
/** Gain Select. See reference manual for information on each setting. */
typedef enum
{
typedef enum {
csenGainSel1X = 0, /**< Gain = 1x. */
csenGainSel2X = 1, /**< Gain = 2x. */
csenGainSel3X = 2, /**< Gain = 3x. */
@ -250,10 +227,8 @@ typedef enum
csenGainSel8X = 7, /**< Gain = 8x. */
} CSEN_GainSel_TypeDef;
/** Peripheral Reflex System signal used to trigger conversion. */
typedef enum
{
typedef enum {
csenPRSSELCh0 = _CSEN_PRSSEL_PRSSEL_PRSCH0, /**< PRS channel 0. */
csenPRSSELCh1 = _CSEN_PRSSEL_PRSSEL_PRSCH1, /**< PRS channel 1. */
csenPRSSELCh2 = _CSEN_PRSSEL_PRSSEL_PRSCH2, /**< PRS channel 2. */
@ -262,16 +237,22 @@ typedef enum
csenPRSSELCh5 = _CSEN_PRSSEL_PRSSEL_PRSCH5, /**< PRS channel 5. */
csenPRSSELCh6 = _CSEN_PRSSEL_PRSSEL_PRSCH6, /**< PRS channel 6. */
csenPRSSELCh7 = _CSEN_PRSSEL_PRSSEL_PRSCH7, /**< PRS channel 7. */
#if defined(_CSEN_PRSSEL_PRSSEL_PRSCH8)
csenPRSSELCh8 = _CSEN_PRSSEL_PRSSEL_PRSCH8, /**< PRS channel 8. */
#endif
#if defined(_CSEN_PRSSEL_PRSSEL_PRSCH9)
csenPRSSELCh9 = _CSEN_PRSSEL_PRSSEL_PRSCH9, /**< PRS channel 9. */
#endif
#if defined(_CSEN_PRSSEL_PRSSEL_PRSCH10)
csenPRSSELCh10 = _CSEN_PRSSEL_PRSSEL_PRSCH10, /**< PRS channel 10. */
#endif
#if defined(_CSEN_PRSSEL_PRSSEL_PRSCH11)
csenPRSSELCh11 = _CSEN_PRSSEL_PRSSEL_PRSCH11, /**< PRS channel 11. */
#endif
} CSEN_PRSSel_TypeDef;
/** APORT channel to CSEN input selection. */
typedef enum
{
typedef enum {
csenInputSelDefault = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT,
csenInputSelAPORT1CH0TO7 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7,
csenInputSelAPORT1CH8TO15 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15,
@ -283,10 +264,8 @@ typedef enum
csenInputSelAPORT3CH24TO31 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31,
} CSEN_InputSel_TypeDef;
/** APORT channel to CSEN single input selection. */
typedef enum
{
typedef enum {
csenSingleSelDefault = _CSEN_SINGLECTRL_SINGLESEL_DEFAULT,
csenSingleSelAPORT1XCH0 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0,
csenSingleSelAPORT1YCH1 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1,
@ -354,14 +333,12 @@ typedef enum
csenSingleSelAPORT3YCH31 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31,
} CSEN_SingleSel_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** CSEN init structure, common for all measurement modes. */
typedef struct
{
typedef struct {
/** Requests system charge pump high accuracy mode. */
bool cpAccuracyHi;
@ -394,29 +371,27 @@ typedef struct
CSEN_InputSel_TypeDef input56To63;
} CSEN_Init_TypeDef;
#define CSEN_INIT_DEFAULT \
{ \
false, /* Charge pump low accuracy mode. */ \
false, /* Use external kelvin connection. */ \
false, /* Disable keep warm. */ \
0, /* 0+3 cycle warmup time. */ \
0, /* Period counter reload. */ \
csenPCPrescaleDiv1, /* Period counter prescale. */ \
csenPRSSELCh0, /* PRS channel 0. */ \
csenInputSelAPORT1CH0TO7, /* input0To7 -> aport1ch0to7 */ \
csenInputSelAPORT1CH8TO15, /* input8To15 -> aport1ch8to15 */ \
csenInputSelAPORT1CH16TO23, /* input16To23 -> aport1ch16to23 */ \
csenInputSelAPORT1CH24TO31, /* input24To31 -> aport1ch24to31 */ \
csenInputSelAPORT3CH0TO7, /* input32To39 -> aport3ch0to7 */ \
csenInputSelAPORT3CH8TO15, /* input40To47 -> aport3ch8to15 */ \
csenInputSelAPORT3CH16TO23, /* input48To55 -> aport3ch16to23 */ \
csenInputSelAPORT3CH24TO31, /* input56To63 -> aport3ch24to31 */ \
}
#define CSEN_INIT_DEFAULT \
{ \
false, /* Charge pump low accuracy mode. */ \
false, /* Use external kelvin connection. */ \
false, /* Disable keep warm. */ \
0, /* 0+3 cycle warmup time. */ \
0, /* Period counter reload. */ \
csenPCPrescaleDiv1, /* Period counter prescale. */ \
csenPRSSELCh0, /* PRS channel 0. */ \
csenInputSelAPORT1CH0TO7, /* input0To7 -> aport1ch0to7 */ \
csenInputSelAPORT1CH8TO15, /* input8To15 -> aport1ch8to15 */ \
csenInputSelAPORT1CH16TO23, /* input16To23 -> aport1ch16to23 */ \
csenInputSelAPORT1CH24TO31, /* input24To31 -> aport1ch24to31 */ \
csenInputSelAPORT3CH0TO7, /* input32To39 -> aport3ch0to7 */ \
csenInputSelAPORT3CH8TO15, /* input40To47 -> aport3ch8to15 */ \
csenInputSelAPORT3CH16TO23, /* input48To55 -> aport3ch16to23 */ \
csenInputSelAPORT3CH24TO31, /* input56To63 -> aport3ch24to31 */ \
}
/** Measurement mode init structure. */
typedef struct
{
typedef struct {
/** Selects the conversion sample mode. */
CSEN_SampleMode_TypeDef sampleMode;
@ -444,11 +419,11 @@ typedef struct
/** Selects an APORT channel for a single conversion. */
CSEN_SingleSel_TypeDef singleSel;
/**
* Mask selects inputs 0 to 31. Effect depends on @p sampleMode. If sample
* mode is bonded, then mask selects inputs to short together. If sample
* mode is scan, then mask selects which inputs will be scanned. If sample
* mode is single and auto-ground is on (@p autoGnd is true), mask selects
/**
* Mask selects inputs 0 to 31. Effect depends on @p sampleMode. If sample
* mode is bonded, then mask selects inputs to short together. If sample
* mode is scan, then mask selects which inputs will be scanned. If sample
* mode is single and auto-ground is on (@p autoGnd is true), mask selects
* which pins are grounded.
*/
uint32_t inputMask0;
@ -467,61 +442,60 @@ typedef struct
/** Selects the Delta Modulation (DM) converter resolution. */
CSEN_DMRes_TypeDef dmRes;
/** Sets the number of DM iterations (comparisons) per cycle. Only applies
* to the Delta Modulation converter. */
/** Sets the number of DM iterations (comparisons) per cycle. Only applies
* to the Delta Modulation converter. */
uint8_t dmIterPerCycle;
/** Sets number of DM converter cycles. Only applies to the
* Delta Modulation converter. */
/** Sets number of DM converter cycles. Only applies to the
* Delta Modulation converter. */
uint8_t dmCycles;
/** Sets the DM converter initial delta value. Only applies to the
* Delta Modulation converter. */
/** Sets the DM converter initial delta value. Only applies to the
* Delta Modulation converter. */
uint8_t dmDelta;
/** Disable DM automatic delta size reduction per cycle. Only applies to the
* Delta Modulation converter. */
/** Disable DM automatic delta size reduction per cycle. Only applies to the
* Delta Modulation converter. */
bool dmFixedDelta;
/** Selects the reset phase timing. Most measurements should use the default
* value. See reference manual for details on when to adjust. */
/** Selects the reset phase timing. Most measurements should use the default
* value. See reference manual for details on when to adjust. */
CSEN_ResetPhaseSel_TypeDef resetPhase;
/** Selects the output drive strength. Most measurements should use the
* default value. See reference manual for details on when to adjust. */
/** Selects the output drive strength. Most measurements should use the
* default value. See reference manual for details on when to adjust. */
CSEN_DriveSel_TypeDef driveSel;
/** Selects the converter gain. */
CSEN_GainSel_TypeDef gainSel;
} CSEN_InitMode_TypeDef;
#define CSEN_INITMODE_DEFAULT \
{ \
csenSampleModeSingle, /* Sample one input and stop. */ \
csenTrigSelStart, /* Use start bit to trigger. */ \
false, /* Disable DMA. */ \
false, /* Average the accumulated result. */ \
csenAccMode1, /* Accumulate 1 sample. */ \
csenEMASampleW1, /* Disable the EMA. */ \
csenCmpModeDisabled, /* Disable the comparator. */ \
0, /* Comparator threshold not used. */ \
csenSingleSelDefault, /* Disconnect the single input. */ \
0, /* Disable inputs 0 to 31. */ \
0, /* Disable inputs 32 to 63. */ \
false, /* Do not ground inactive inputs. */ \
csenConvSelSAR, /* Use the SAR converter. */ \
csenSARRes10, /* Set SAR resolution to 10 bits. */ \
csenDMRes10, /* Set DM resolution to 10 bits. */ \
0, /* Set DM conv/cycle to default. */ \
0, /* Set DM cycles to default. */ \
0, /* Set DM initial delta to default. */ \
false, /* Use DM auto delta reduction. */ \
csenResetPhaseSel0, /* Use shortest reset phase time. */ \
csenDriveSelFull, /* Use full output current. */ \
csenGainSel8X, /* Use highest converter gain. */ \
}
#define CSEN_INITMODE_DEFAULT \
{ \
csenSampleModeSingle, /* Sample one input and stop. */ \
csenTrigSelStart, /* Use start bit to trigger. */ \
false, /* Disable DMA. */ \
false, /* Average the accumulated result. */ \
csenAccMode1, /* Accumulate 1 sample. */ \
csenEMASampleW1, /* Disable the EMA. */ \
csenCmpModeDisabled, /* Disable the comparator. */ \
0, /* Comparator threshold not used. */ \
csenSingleSelDefault, /* Disconnect the single input. */ \
0, /* Disable inputs 0 to 31. */ \
0, /* Disable inputs 32 to 63. */ \
false, /* Do not ground inactive inputs. */ \
csenConvSelSAR, /* Use the SAR converter. */ \
csenSARRes10, /* Set SAR resolution to 10 bits. */ \
csenDMRes10, /* Set DM resolution to 10 bits. */ \
0, /* Set DM conv/cycle to default. */ \
0, /* Set DM cycles to default. */ \
0, /* Set DM initial delta to default. */ \
false, /* Use DM auto delta reduction. */ \
csenResetPhaseSel0, /* Use shortest reset phase time. */ \
csenDriveSelFull, /* Use full output current. */ \
csenGainSel8X, /* Use highest converter gain. */ \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************
@ -532,8 +506,8 @@ typedef struct
* Get last conversion result.
*
* @note
* Check conversion busy flag before calling this function. In addition,
* the result width and format depend on the parameters passed to the
* Check conversion busy flag before calling this function. In addition,
* the result width and format depend on the parameters passed to the
* @ref CSEN_InitMode() function.
*
* @param[in] csen
@ -612,7 +586,6 @@ void CSEN_Init(CSEN_TypeDef *csen, const CSEN_Init_TypeDef *init);
void CSEN_InitMode(CSEN_TypeDef *csen, const CSEN_InitMode_TypeDef *init);
void CSEN_Reset(CSEN_TypeDef *csen);
/***************************************************************************//**
* @brief
* Clear one or more pending CSEN interrupts.
@ -629,7 +602,6 @@ __STATIC_INLINE void CSEN_IntClear(CSEN_TypeDef *csen, uint32_t flags)
csen->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more CSEN interrupts.
@ -646,7 +618,6 @@ __STATIC_INLINE void CSEN_IntDisable(CSEN_TypeDef *csen, uint32_t flags)
csen->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more CSEN interrupts.
@ -668,7 +639,6 @@ __STATIC_INLINE void CSEN_IntEnable(CSEN_TypeDef *csen, uint32_t flags)
csen->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending CSEN interrupt flags.
@ -688,7 +658,6 @@ __STATIC_INLINE uint32_t CSEN_IntGet(CSEN_TypeDef *csen)
return csen->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending CSEN interrupt flags.
@ -720,7 +689,6 @@ __STATIC_INLINE uint32_t CSEN_IntGetEnabled(CSEN_TypeDef *csen)
return csen->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending CSEN interrupts from SW.
@ -737,7 +705,6 @@ __STATIC_INLINE void CSEN_IntSet(CSEN_TypeDef *csen, uint32_t flags)
csen->IFS = flags;
}
/***************************************************************************//**
* @brief
* Return CSEN conversion busy status.
@ -753,7 +720,6 @@ __STATIC_INLINE bool CSEN_IsBusy(CSEN_TypeDef *csen)
return (bool)(csen->STATUS & _CSEN_STATUS_CSENBUSY_MASK);
}
/***************************************************************************//**
* @brief
* Start scan sequence and/or single conversion.
@ -766,7 +732,6 @@ __STATIC_INLINE void CSEN_Start(CSEN_TypeDef *csen)
csen->CMD = CSEN_CMD_START;
}
/** @} (end addtogroup CSEN) */
/** @} (end addtogroup emlib) */

103
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_dac.h
* @brief Digital to Analog Converter (DAC) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -44,7 +44,6 @@
extern "C" {
#endif
/***************************************************************************//**
* @addtogroup emlib
* @{
@ -67,83 +66,73 @@ extern "C" {
******************************************************************************/
/** Conversion mode. */
typedef enum
{
typedef enum {
dacConvModeContinuous = _DAC_CTRL_CONVMODE_CONTINUOUS, /**< Continuous mode. */
dacConvModeSampleHold = _DAC_CTRL_CONVMODE_SAMPLEHOLD, /**< Sample/hold mode. */
dacConvModeSampleOff = _DAC_CTRL_CONVMODE_SAMPLEOFF /**< Sample/shut off mode. */
} DAC_ConvMode_TypeDef;
/** Output mode. */
typedef enum
{
typedef enum {
dacOutputDisable = _DAC_CTRL_OUTMODE_DISABLE, /**< Output to pin and ADC disabled. */
dacOutputPin = _DAC_CTRL_OUTMODE_PIN, /**< Output to pin only. */
dacOutputADC = _DAC_CTRL_OUTMODE_ADC, /**< Output to ADC only */
dacOutputPinADC = _DAC_CTRL_OUTMODE_PINADC /**< Output to pin and ADC. */
} DAC_Output_TypeDef;
/** Peripheral Reflex System signal used to trigger single sample. */
typedef enum
{
typedef enum {
dacPRSSELCh0 = _DAC_CH0CTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
dacPRSSELCh1 = _DAC_CH0CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
dacPRSSELCh2 = _DAC_CH0CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
dacPRSSELCh3 = _DAC_CH0CTRL_PRSSEL_PRSCH3, /**< PRS channel 3. */
#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH4 )
#if defined(_DAC_CH0CTRL_PRSSEL_PRSCH4)
dacPRSSELCh4 = _DAC_CH0CTRL_PRSSEL_PRSCH4, /**< PRS channel 4. */
#endif
#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH5 )
#if defined(_DAC_CH0CTRL_PRSSEL_PRSCH5)
dacPRSSELCh5 = _DAC_CH0CTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */
#endif
#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH6 )
#if defined(_DAC_CH0CTRL_PRSSEL_PRSCH6)
dacPRSSELCh6 = _DAC_CH0CTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */
#endif
#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH7 )
#if defined(_DAC_CH0CTRL_PRSSEL_PRSCH7)
dacPRSSELCh7 = _DAC_CH0CTRL_PRSSEL_PRSCH7, /**< PRS channel 7. */
#endif
#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH8 )
#if defined(_DAC_CH0CTRL_PRSSEL_PRSCH8)
dacPRSSELCh8 = _DAC_CH0CTRL_PRSSEL_PRSCH8, /**< PRS channel 8. */
#endif
#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH9 )
#if defined(_DAC_CH0CTRL_PRSSEL_PRSCH9)
dacPRSSELCh9 = _DAC_CH0CTRL_PRSSEL_PRSCH9, /**< PRS channel 9. */
#endif
#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH10 )
#if defined(_DAC_CH0CTRL_PRSSEL_PRSCH10)
dacPRSSELCh10 = _DAC_CH0CTRL_PRSSEL_PRSCH10, /**< PRS channel 10. */
#endif
#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH11 )
#if defined(_DAC_CH0CTRL_PRSSEL_PRSCH11)
dacPRSSELCh11 = _DAC_CH0CTRL_PRSSEL_PRSCH11, /**< PRS channel 11. */
#endif
} DAC_PRSSEL_TypeDef;
/** Reference voltage for DAC. */
typedef enum
{
typedef enum {
dacRef1V25 = _DAC_CTRL_REFSEL_1V25, /**< Internal 1.25V bandgap reference. */
dacRef2V5 = _DAC_CTRL_REFSEL_2V5, /**< Internal 2.5V bandgap reference. */
dacRefVDD = _DAC_CTRL_REFSEL_VDD /**< VDD reference. */
} DAC_Ref_TypeDef;
/** Refresh interval. */
typedef enum
{
typedef enum {
dacRefresh8 = _DAC_CTRL_REFRSEL_8CYCLES, /**< Refresh every 8 prescaled cycles. */
dacRefresh16 = _DAC_CTRL_REFRSEL_16CYCLES, /**< Refresh every 16 prescaled cycles. */
dacRefresh32 = _DAC_CTRL_REFRSEL_32CYCLES, /**< Refresh every 32 prescaled cycles. */
dacRefresh64 = _DAC_CTRL_REFRSEL_64CYCLES /**< Refresh every 64 prescaled cycles. */
} DAC_Refresh_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** DAC init structure, common for both channels. */
typedef struct
{
typedef struct {
/** Refresh interval. Only used if REFREN bit set for a DAC channel. */
DAC_Refresh_TypeDef refresh;
@ -180,23 +169,21 @@ typedef struct
/** Default config for DAC init structure. */
#define DAC_INIT_DEFAULT \
{ \
dacRefresh8, /* Refresh every 8 prescaled cycles. */ \
dacRef1V25, /* 1.25V internal reference. */ \
dacOutputPin, /* Output to pin only. */ \
dacConvModeContinuous, /* Continuous mode. */ \
0, /* No prescaling. */ \
false, /* Do not enable low pass filter. */ \
false, /* Do not reset prescaler on ch0 start. */ \
false, /* DAC output enable always on. */ \
false, /* Disable sine mode. */ \
false /* Single ended mode. */ \
}
{ \
dacRefresh8, /* Refresh every 8 prescaled cycles. */ \
dacRef1V25, /* 1.25V internal reference. */ \
dacOutputPin, /* Output to pin only. */ \
dacConvModeContinuous, /* Continuous mode. */ \
0, /* No prescaling. */ \
false, /* Do not enable low pass filter. */ \
false, /* Do not reset prescaler on ch0 start. */ \
false, /* DAC output enable always on. */ \
false, /* Disable sine mode. */ \
false /* Single ended mode. */ \
}
/** DAC channel init structure. */
typedef struct
{
typedef struct {
/** Enable channel. */
bool enable;
@ -221,13 +208,12 @@ typedef struct
/** Default config for DAC channel init structure. */
#define DAC_INITCHANNEL_DEFAULT \
{ \
false, /* Leave channel disabled when init done. */ \
false, /* Disable PRS triggering. */ \
false, /* Channel not refreshed automatically. */ \
dacPRSSELCh0 /* Select PRS ch0 (if PRS triggering enabled). */ \
}
{ \
false, /* Leave channel disabled when init done. */ \
false, /* Disable PRS triggering. */ \
false, /* Channel not refreshed automatically. */ \
dacPRSSELCh0 /* Select PRS ch0 (if PRS triggering enabled). */ \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************
@ -256,14 +242,13 @@ void DAC_ChannelOutputSet(DAC_TypeDef *dac,
* @param[in] value
* Value to write to the channel 0 output register CH0DATA.
******************************************************************************/
__STATIC_INLINE void DAC_Channel0OutputSet( DAC_TypeDef *dac,
uint32_t value )
__STATIC_INLINE void DAC_Channel0OutputSet(DAC_TypeDef *dac,
uint32_t value)
{
EFM_ASSERT(value<=_DAC_CH0DATA_MASK);
EFM_ASSERT(value <= _DAC_CH0DATA_MASK);
dac->CH0DATA = value;
}
/***************************************************************************//**
* @brief
* Set the output signal of DAC channel 1 to a given value.
@ -278,14 +263,13 @@ __STATIC_INLINE void DAC_Channel0OutputSet( DAC_TypeDef *dac,
* @param[in] value
* Value to write to the channel 1 output register CH1DATA.
******************************************************************************/
__STATIC_INLINE void DAC_Channel1OutputSet( DAC_TypeDef *dac,
uint32_t value )
__STATIC_INLINE void DAC_Channel1OutputSet(DAC_TypeDef *dac,
uint32_t value)
{
EFM_ASSERT(value<=_DAC_CH1DATA_MASK);
EFM_ASSERT(value <= _DAC_CH1DATA_MASK);
dac->CH1DATA = value;
}
/***************************************************************************//**
* @brief
* Clear one or more pending DAC interrupts.
@ -302,7 +286,6 @@ __STATIC_INLINE void DAC_IntClear(DAC_TypeDef *dac, uint32_t flags)
dac->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more DAC interrupts.
@ -319,7 +302,6 @@ __STATIC_INLINE void DAC_IntDisable(DAC_TypeDef *dac, uint32_t flags)
dac->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more DAC interrupts.
@ -341,7 +323,6 @@ __STATIC_INLINE void DAC_IntEnable(DAC_TypeDef *dac, uint32_t flags)
dac->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending DAC interrupt flags.
@ -361,7 +342,6 @@ __STATIC_INLINE uint32_t DAC_IntGet(DAC_TypeDef *dac)
return dac->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending DAC interrupt flags.
@ -393,7 +373,6 @@ __STATIC_INLINE uint32_t DAC_IntGetEnabled(DAC_TypeDef *dac)
return dac->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending DAC interrupts from SW.

12
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_dbg.h
* @brief Debug (DBG) API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -30,14 +30,13 @@
*
******************************************************************************/
#ifndef EM_DBG_H
#define EM_DBG_H
#include <stdbool.h>
#include "em_device.h"
#if defined( CoreDebug_DHCSR_C_DEBUGEN_Msk )
#if defined(CoreDebug_DHCSR_C_DEBUGEN_Msk)
#ifdef __cplusplus
extern "C" {
@ -57,7 +56,7 @@ extern "C" {
***************************** PROTOTYPES **********************************
******************************************************************************/
#if defined( GPIO_ROUTE_SWCLKPEN ) || defined( GPIO_ROUTEPEN_SWCLKTCKPEN )
#if defined(GPIO_ROUTE_SWCLKPEN) || defined(GPIO_ROUTEPEN_SWCLKTCKPEN)
/***************************************************************************//**
* @brief
* Check if a debugger is connected (and debug session activated)
@ -76,8 +75,7 @@ __STATIC_INLINE bool DBG_Connected(void)
}
#endif
#if defined( GPIO_ROUTE_SWOPEN ) || defined( GPIO_ROUTEPEN_SWVPEN )
#if defined(GPIO_ROUTE_SWOPEN) || defined(GPIO_ROUTEPEN_SWVPEN)
void DBG_SWOEnable(unsigned int location);
#endif

72
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_dma.h
* @brief Direct memory access (DMA) API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -34,7 +34,7 @@
#define EM_DMA_H
#include "em_device.h"
#if defined( DMA_PRESENT )
#if defined(DMA_PRESENT)
#include <stdio.h>
#include <stdbool.h>
@ -61,27 +61,22 @@ extern "C" {
* Amount source/destination address should be incremented for each data
* transfer.
*/
typedef enum
{
typedef enum {
dmaDataInc1 = _DMA_CTRL_SRC_INC_BYTE, /**< Increment address 1 byte. */
dmaDataInc2 = _DMA_CTRL_SRC_INC_HALFWORD, /**< Increment address 2 bytes. */
dmaDataInc4 = _DMA_CTRL_SRC_INC_WORD, /**< Increment address 4 bytes. */
dmaDataIncNone = _DMA_CTRL_SRC_INC_NONE /**< Do not increment address. */
} DMA_DataInc_TypeDef;
/** Data sizes (in number of bytes) to be read/written by DMA transfer. */
typedef enum
{
typedef enum {
dmaDataSize1 = _DMA_CTRL_SRC_SIZE_BYTE, /**< 1 byte DMA transfer size. */
dmaDataSize2 = _DMA_CTRL_SRC_SIZE_HALFWORD, /**< 2 byte DMA transfer size. */
dmaDataSize4 = _DMA_CTRL_SRC_SIZE_WORD /**< 4 byte DMA transfer size. */
} DMA_DataSize_TypeDef;
/** Type of DMA transfer. */
typedef enum
{
typedef enum {
/** Basic DMA cycle. */
dmaCycleCtrlBasic = _DMA_CTRL_CYCLE_CTRL_BASIC,
/** Auto-request DMA cycle. */
@ -94,10 +89,8 @@ typedef enum
dmaCycleCtrlPerScatterGather = _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER
} DMA_CycleCtrl_TypeDef;
/** Number of transfers before controller does new arbitration. */
typedef enum
{
typedef enum {
dmaArbitrate1 = _DMA_CTRL_R_POWER_1, /**< Arbitrate after 1 DMA transfer. */
dmaArbitrate2 = _DMA_CTRL_R_POWER_2, /**< Arbitrate after 2 DMA transfers. */
dmaArbitrate4 = _DMA_CTRL_R_POWER_4, /**< Arbitrate after 4 DMA transfers. */
@ -111,7 +104,6 @@ typedef enum
dmaArbitrate1024 = _DMA_CTRL_R_POWER_1024 /**< Arbitrate after 1024 DMA transfers. */
} DMA_ArbiterConfig_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
@ -134,7 +126,6 @@ typedef enum
*/
typedef void (*DMA_FuncPtr_TypeDef)(unsigned int channel, bool primary, void *user);
/**
* @brief
* Callback structure that can be used to define DMA complete actions.
@ -145,8 +136,7 @@ typedef void (*DMA_FuncPtr_TypeDef)(unsigned int channel, bool primary, void *us
* handled by one common callback, using the provided 'primary' parameter
* with the callback function.
*/
typedef struct
{
typedef struct {
/**
* Pointer to callback function to invoke when DMA transfer cycle done.
* Notice that this function is invoked in interrupt context, and therefore
@ -165,10 +155,8 @@ typedef struct
uint8_t primary;
} DMA_CB_TypeDef;
/** Configuration structure for a channel. */
typedef struct
{
typedef struct {
/**
* Select if channel priority is in the high or default priority group
* with respect to arbitration. Within a priority group, lower numbered
@ -208,13 +196,11 @@ typedef struct
DMA_CB_TypeDef *cb;
} DMA_CfgChannel_TypeDef;
/**
* Configuration structure for primary or alternate descriptor
* (not used for scatter-gather DMA cycles).
*/
typedef struct
{
typedef struct {
/** Destination increment size for each DMA transfer */
DMA_DataInc_TypeDef dstInc;
@ -242,13 +228,11 @@ typedef struct
uint8_t hprot;
} DMA_CfgDescr_TypeDef;
#if defined( _DMA_LOOP0_MASK ) && defined( _DMA_LOOP1_MASK )
#if defined(_DMA_LOOP0_MASK) && defined(_DMA_LOOP1_MASK)
/**
* Configuration structure for loop mode
*/
typedef struct
{
typedef struct {
/** Enable repeated loop */
bool enable;
/** Width of transfer, reload value for nMinus1 */
@ -256,13 +240,11 @@ typedef struct
} DMA_CfgLoop_TypeDef;
#endif
#if defined( _DMA_RECT0_MASK )
#if defined(_DMA_RECT0_MASK)
/**
* Configuration structure for rectangular copy
*/
typedef struct
{
typedef struct {
/** DMA channel destination stride (width of destination image, distance between lines) */
uint16_t dstStride;
/** DMA channel source stride (width of source image, distance between lines) */
@ -272,10 +254,8 @@ typedef struct
} DMA_CfgRect_TypeDef;
#endif
/** Configuration structure for alternate scatter-gather descriptor. */
typedef struct
{
typedef struct {
/** Pointer to location to transfer data from. */
void *src;
@ -320,10 +300,8 @@ typedef struct
bool peripheral;
} DMA_CfgDescrSGAlt_TypeDef;
/** DMA init structure */
typedef struct
{
typedef struct {
/**
* HPROT signal state when accessing the primary/alternate
* descriptors. Normally set to 0 if protection is not an issue.
@ -352,7 +330,6 @@ typedef struct
DMA_DESCRIPTOR_TypeDef *controlBlock;
} DMA_Init_TypeDef;
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
@ -384,15 +361,15 @@ void DMA_CfgChannel(unsigned int channel, DMA_CfgChannel_TypeDef *cfg);
void DMA_CfgDescr(unsigned int channel,
bool primary,
DMA_CfgDescr_TypeDef *cfg);
#if defined( _DMA_LOOP0_MASK ) && defined( _DMA_LOOP1_MASK )
#if defined(_DMA_LOOP0_MASK) && defined(_DMA_LOOP1_MASK)
void DMA_CfgLoop(unsigned int channel, DMA_CfgLoop_TypeDef *cfg);
#endif
#if defined( _DMA_RECT0_MASK )
#if defined(_DMA_RECT0_MASK)
void DMA_CfgRect(unsigned int channel, DMA_CfgRect_TypeDef *cfg);
#endif
#if defined( _DMA_LOOP0_MASK ) && defined( _DMA_LOOP1_MASK )
#if defined(_DMA_LOOP0_MASK) && defined(_DMA_LOOP1_MASK)
/***************************************************************************//**
* @brief
* Clear Loop configuration for channel
@ -403,8 +380,7 @@ void DMA_CfgRect(unsigned int channel, DMA_CfgRect_TypeDef *cfg);
__STATIC_INLINE void DMA_ResetLoop(unsigned int channel)
{
/* Clean loop copy operation */
switch(channel)
{
switch (channel) {
case 0:
DMA->LOOP0 = _DMA_LOOP0_RESETVALUE;
break;
@ -417,8 +393,7 @@ __STATIC_INLINE void DMA_ResetLoop(unsigned int channel)
}
#endif
#if defined( _DMA_RECT0_MASK )
#if defined(_DMA_RECT0_MASK)
/***************************************************************************//**
* @brief
* Clear Rect/2D DMA configuration for channel
@ -464,7 +439,6 @@ __STATIC_INLINE void DMA_IntClear(uint32_t flags)
DMA->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more DMA interrupts.
@ -478,7 +452,6 @@ __STATIC_INLINE void DMA_IntDisable(uint32_t flags)
DMA->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more DMA interrupts.
@ -497,7 +470,6 @@ __STATIC_INLINE void DMA_IntEnable(uint32_t flags)
DMA->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending DMA interrupt flags.
@ -514,7 +486,6 @@ __STATIC_INLINE uint32_t DMA_IntGet(void)
return DMA->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending DMA interrupt flags.
@ -537,7 +508,6 @@ __STATIC_INLINE uint32_t DMA_IntGetEnabled(void)
return DMA->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending DMA interrupts

455
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_ebi.h
* @brief External Bus Iterface (EBI) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -82,28 +82,88 @@ extern "C" {
#define EBI_CS2 (uint32_t)(1 << 3) /**< EBI chip select line 2 */
#define EBI_CS3 (uint32_t)(1 << 4) /**< EBI chip select line 3 */
#if defined(_EBI_ROUTE_MASK) && defined(_EBI_ROUTE_APEN_MASK)
#define EBI_GENERIC_ALB_A0 EBI_ROUTE_ALB_A0
#define EBI_GENERIC_ALB_A8 EBI_ROUTE_ALB_A8
#define EBI_GENERIC_ALB_A16 EBI_ROUTE_ALB_A16
#define EBI_GENERIC_ALB_A24 EBI_ROUTE_ALB_A24
#define EBI_GENERIC_APEN_A0 EBI_ROUTE_APEN_A0
#define EBI_GENERIC_APEN_A5 EBI_ROUTE_APEN_A5
#define EBI_GENERIC_APEN_A6 EBI_ROUTE_APEN_A6
#define EBI_GENERIC_APEN_A7 EBI_ROUTE_APEN_A7
#define EBI_GENERIC_APEN_A8 EBI_ROUTE_APEN_A8
#define EBI_GENERIC_APEN_A9 EBI_ROUTE_APEN_A9
#define EBI_GENERIC_APEN_A10 EBI_ROUTE_APEN_A10
#define EBI_GENERIC_APEN_A11 EBI_ROUTE_APEN_A11
#define EBI_GENERIC_APEN_A12 EBI_ROUTE_APEN_A12
#define EBI_GENERIC_APEN_A13 EBI_ROUTE_APEN_A13
#define EBI_GENERIC_APEN_A14 EBI_ROUTE_APEN_A14
#define EBI_GENERIC_APEN_A15 EBI_ROUTE_APEN_A15
#define EBI_GENERIC_APEN_A16 EBI_ROUTE_APEN_A16
#define EBI_GENERIC_APEN_A17 EBI_ROUTE_APEN_A17
#define EBI_GENERIC_APEN_A18 EBI_ROUTE_APEN_A18
#define EBI_GENERIC_APEN_A19 EBI_ROUTE_APEN_A19
#define EBI_GENERIC_APEN_A20 EBI_ROUTE_APEN_A20
#define EBI_GENERIC_APEN_A21 EBI_ROUTE_APEN_A21
#define EBI_GENERIC_APEN_A22 EBI_ROUTE_APEN_A22
#define EBI_GENERIC_APEN_A23 EBI_ROUTE_APEN_A23
#define EBI_GENERIC_APEN_A24 EBI_ROUTE_APEN_A24
#define EBI_GENERIC_APEN_A25 EBI_ROUTE_APEN_A25
#define EBI_GENERIC_APEN_A26 EBI_ROUTE_APEN_A26
#define EBI_GENERIC_APEN_A27 EBI_ROUTE_APEN_A27
#define EBI_GENERIC_APEN_A28 EBI_ROUTE_APEN_A28
#elif defined(_EBI_ROUTEPEN_MASK)
#define EBI_GENERIC_ALB_A0 EBI_ROUTEPEN_ALB_A0
#define EBI_GENERIC_ALB_A8 EBI_ROUTEPEN_ALB_A8
#define EBI_GENERIC_ALB_A16 EBI_ROUTEPEN_ALB_A16
#define EBI_GENERIC_ALB_A24 EBI_ROUTEPEN_ALB_A24
#define EBI_GENERIC_APEN_A0 EBI_ROUTEPEN_APEN_A0
#define EBI_GENERIC_APEN_A5 EBI_ROUTEPEN_APEN_A5
#define EBI_GENERIC_APEN_A6 EBI_ROUTEPEN_APEN_A6
#define EBI_GENERIC_APEN_A7 EBI_ROUTEPEN_APEN_A7
#define EBI_GENERIC_APEN_A8 EBI_ROUTEPEN_APEN_A8
#define EBI_GENERIC_APEN_A9 EBI_ROUTEPEN_APEN_A9
#define EBI_GENERIC_APEN_A10 EBI_ROUTEPEN_APEN_A10
#define EBI_GENERIC_APEN_A11 EBI_ROUTEPEN_APEN_A11
#define EBI_GENERIC_APEN_A12 EBI_ROUTEPEN_APEN_A12
#define EBI_GENERIC_APEN_A13 EBI_ROUTEPEN_APEN_A13
#define EBI_GENERIC_APEN_A14 EBI_ROUTEPEN_APEN_A14
#define EBI_GENERIC_APEN_A15 EBI_ROUTEPEN_APEN_A15
#define EBI_GENERIC_APEN_A16 EBI_ROUTEPEN_APEN_A16
#define EBI_GENERIC_APEN_A17 EBI_ROUTEPEN_APEN_A17
#define EBI_GENERIC_APEN_A18 EBI_ROUTEPEN_APEN_A18
#define EBI_GENERIC_APEN_A19 EBI_ROUTEPEN_APEN_A19
#define EBI_GENERIC_APEN_A20 EBI_ROUTEPEN_APEN_A20
#define EBI_GENERIC_APEN_A21 EBI_ROUTEPEN_APEN_A21
#define EBI_GENERIC_APEN_A22 EBI_ROUTEPEN_APEN_A22
#define EBI_GENERIC_APEN_A23 EBI_ROUTEPEN_APEN_A23
#define EBI_GENERIC_APEN_A24 EBI_ROUTEPEN_APEN_A24
#define EBI_GENERIC_APEN_A25 EBI_ROUTEPEN_APEN_A25
#define EBI_GENERIC_APEN_A26 EBI_ROUTEPEN_APEN_A26
#define EBI_GENERIC_APEN_A27 EBI_ROUTEPEN_APEN_A27
#define EBI_GENERIC_APEN_A28 EBI_ROUTEPEN_APEN_A28
#endif
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** EBI Mode of operation */
typedef enum
{
typedef enum {
/** 8 data bits, 8 address bits */
ebiModeD8A8 = EBI_CTRL_MODE_D8A8,
/** 16 data bits, 16 address bits, using address latch enable */
ebiModeD16A16ALE = EBI_CTRL_MODE_D16A16ALE,
/** 8 data bits, 24 address bits, using address latch enable */
ebiModeD8A24ALE = EBI_CTRL_MODE_D8A24ALE,
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if defined(EBI_CTRL_MODE_D16)
/** Mode D16 */
ebiModeD16 = EBI_CTRL_MODE_D16,
#endif
} EBI_Mode_TypeDef;
/** EBI Polarity configuration */
typedef enum
{
typedef enum {
/** Active Low */
ebiActiveLow = 0,
/** Active High */
@ -111,8 +171,7 @@ typedef enum
} EBI_Polarity_TypeDef;
/** EBI Pin Line types */
typedef enum
{
typedef enum {
/** Address Ready line */
ebiLineARDY,
/** Address Latch Enable line */
@ -123,11 +182,11 @@ typedef enum
ebiLineRE,
/** Chip Select line */
ebiLineCS,
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if defined(_EBI_POLARITY_BLPOL_MASK)
/** BL line */
ebiLineBL,
#endif
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if defined(_EBI_TFTPOLARITY_MASK)
/** TFT VSYNC line */
ebiLineTFTVSync,
/** TFT HSYNC line */
@ -141,75 +200,75 @@ typedef enum
#endif
} EBI_Line_TypeDef;
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if !defined(_EFM32_GECKO_FAMILY)
/** Address Pin Enable, lower limit - lower range of pins to enable */
typedef enum
{
typedef enum {
/** Adress lines EBI_A[0] and upwards are enabled by APEN */
ebiALowA0 = EBI_ROUTE_ALB_A0,
ebiALowA0 = EBI_GENERIC_ALB_A0,
/** Adress lines EBI_A[8] and upwards are enabled by APEN */
ebiALowA8 = EBI_ROUTE_ALB_A8,
ebiALowA8 = EBI_GENERIC_ALB_A8,
/** Adress lines EBI_A[16] and upwards are enabled by APEN */
ebiALowA16 = EBI_ROUTE_ALB_A16,
ebiALowA16 = EBI_GENERIC_ALB_A16,
/** Adress lines EBI_A[24] and upwards are enabled by APEN */
ebiALowA24 = EBI_ROUTE_ALB_A24,
ebiALowA24 = EBI_GENERIC_ALB_A24,
} EBI_ALow_TypeDef;
/** Adress Pin Enable, high limit - higher limit of pins to enable */
typedef enum
{
typedef enum {
/** All EBI_A pins are disabled */
ebiAHighA0 = EBI_ROUTE_APEN_A0,
ebiAHighA0 = EBI_GENERIC_APEN_A0,
/** All EBI_A[4:ALow] are enabled */
ebiAHighA5 = EBI_ROUTE_APEN_A5,
ebiAHighA5 = EBI_GENERIC_APEN_A5,
/** All EBI_A[5:ALow] are enabled */
ebiAHighA6 = EBI_ROUTE_APEN_A6,
ebiAHighA6 = EBI_GENERIC_APEN_A6,
/** All EBI_A[6:ALow] are enabled */
ebiAHighA7 = EBI_ROUTE_APEN_A7,
ebiAHighA7 = EBI_GENERIC_APEN_A7,
/** All EBI_A[7:ALow] are enabled */
ebiAHighA8 = EBI_ROUTE_APEN_A8,
ebiAHighA8 = EBI_GENERIC_APEN_A8,
/** All EBI_A[8:ALow] are enabled */
ebiAHighA9 = EBI_ROUTE_APEN_A9,
ebiAHighA9 = EBI_GENERIC_APEN_A9,
/** All EBI_A[9:ALow] are enabled */
ebiAHighA10 = EBI_ROUTE_APEN_A10,
ebiAHighA10 = EBI_GENERIC_APEN_A10,
/** All EBI_A[10:ALow] are enabled */
ebiAHighA11 = EBI_ROUTE_APEN_A11,
ebiAHighA11 = EBI_GENERIC_APEN_A11,
/** All EBI_A[11:ALow] are enabled */
ebiAHighA12 = EBI_ROUTE_APEN_A12,
ebiAHighA12 = EBI_GENERIC_APEN_A12,
/** All EBI_A[12:ALow] are enabled */
ebiAHighA13 = EBI_ROUTE_APEN_A13,
ebiAHighA13 = EBI_GENERIC_APEN_A13,
/** All EBI_A[13:ALow] are enabled */
ebiAHighA14 = EBI_ROUTE_APEN_A14,
ebiAHighA14 = EBI_GENERIC_APEN_A14,
/** All EBI_A[14:ALow] are enabled */
ebiAHighA15 = EBI_ROUTE_APEN_A15,
ebiAHighA15 = EBI_GENERIC_APEN_A15,
/** All EBI_A[15:ALow] are enabled */
ebiAHighA16 = EBI_ROUTE_APEN_A16,
ebiAHighA16 = EBI_GENERIC_APEN_A16,
/** All EBI_A[16:ALow] are enabled */
ebiAHighA17 = EBI_ROUTE_APEN_A17,
ebiAHighA17 = EBI_GENERIC_APEN_A17,
/** All EBI_A[17:ALow] are enabled */
ebiAHighA18 = EBI_ROUTE_APEN_A18,
ebiAHighA18 = EBI_GENERIC_APEN_A18,
/** All EBI_A[18:ALow] are enabled */
ebiAHighA19 = EBI_ROUTE_APEN_A19,
ebiAHighA19 = EBI_GENERIC_APEN_A19,
/** All EBI_A[19:ALow] are enabled */
ebiAHighA20 = EBI_ROUTE_APEN_A20,
ebiAHighA20 = EBI_GENERIC_APEN_A20,
/** All EBI_A[20:ALow] are enabled */
ebiAHighA21 = EBI_ROUTE_APEN_A21,
ebiAHighA21 = EBI_GENERIC_APEN_A21,
/** All EBI_A[21:ALow] are enabled */
ebiAHighA22 = EBI_ROUTE_APEN_A22,
ebiAHighA22 = EBI_GENERIC_APEN_A22,
/** All EBI_A[22:ALow] are enabled */
ebiAHighA23 = EBI_ROUTE_APEN_A23,
ebiAHighA23 = EBI_GENERIC_APEN_A23,
/** All EBI_A[23:ALow] are enabled */
ebiAHighA24 = EBI_ROUTE_APEN_A24,
ebiAHighA24 = EBI_GENERIC_APEN_A24,
/** All EBI_A[24:ALow] are enabled */
ebiAHighA25 = EBI_ROUTE_APEN_A25,
ebiAHighA25 = EBI_GENERIC_APEN_A25,
/** All EBI_A[25:ALow] are enabled */
ebiAHighA26 = EBI_ROUTE_APEN_A26,
ebiAHighA26 = EBI_GENERIC_APEN_A26,
/** All EBI_A[26:ALow] are enabled */
ebiAHighA27 = EBI_ROUTE_APEN_A27,
ebiAHighA27 = EBI_GENERIC_APEN_A27,
/** All EBI_A[27:ALow] are enabled */
ebiAHighA28 = EBI_ROUTE_APEN_A28,
ebiAHighA28 = EBI_GENERIC_APEN_A28,
} EBI_AHigh_TypeDef;
#endif
#if defined(_EBI_ROUTE_LOCATION_MASK)
/** EBI I/O Alternate Pin Location */
typedef enum {
/** EBI PIN I/O Location 0 */
@ -221,11 +280,11 @@ typedef enum {
} EBI_Location_TypeDef;
#endif
#if defined(_EBI_TFTCTRL_MASK)
/* TFT support */
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
/** EBI TFT Graphics Bank Select */
typedef enum
{
typedef enum {
/** Memory BANK0 contains frame buffer */
ebiTFTBank0 = EBI_TFTCTRL_BANKSEL_BANK0,
/** Memory BANK1 contains frame buffer */
@ -237,8 +296,7 @@ typedef enum
} EBI_TFTBank_TypeDef;
/** Masking and Alpha blending source color*/
typedef enum
{
typedef enum {
/** Use memory as source color for masking/alpha blending */
ebiTFTColorSrcMem = EBI_TFTCTRL_COLOR1SRC_MEM,
/** Use PIXEL1 register as source color for masking/alpha blending */
@ -246,8 +304,7 @@ typedef enum
} EBI_TFTColorSrc_TypeDef;
/** Bus Data Interleave Mode */
typedef enum
{
typedef enum {
/** Unlimited interleaved accesses per EBI_DCLK period. Can cause jitter */
ebiTFTInterleaveUnlimited = EBI_TFTCTRL_INTERLEAVE_UNLIMITED,
/** Allow 1 interleaved access per EBI_DCLK period */
@ -257,8 +314,7 @@ typedef enum
} EBI_TFTInterleave_TypeDef;
/** Control frame base pointer copy */
typedef enum
{
typedef enum {
/** Trigger update of frame buffer pointer on vertical sync */
ebiTFTFrameBufTriggerVSync = EBI_TFTCTRL_FBCTRIG_VSYNC,
/** Trigger update of frame buffer pointer on horizontal sync */
@ -266,8 +322,7 @@ typedef enum
} EBI_TFTFrameBufTrigger_TypeDef;
/** Control of mask and alpha blending mode */
typedef enum
{
typedef enum {
/** Masking and blending are disabled */
ebiTFTMBDisabled = EBI_TFTCTRL_MASKBLEND_DISABLED,
/** Internal masking */
@ -275,18 +330,30 @@ typedef enum
/** Internal alpha blending */
ebiTFTMBIAlpha = EBI_TFTCTRL_MASKBLEND_IALPHA,
/** Internal masking and alpha blending are enabled */
#if defined(EBI_TFTCTRL_MASKBLEND_IMASKIALPHA)
ebiTFTMBIMaskAlpha = EBI_TFTCTRL_MASKBLEND_IMASKIALPHA,
#else
ebiTFTMBIMaskAlpha = EBI_TFTCTRL_MASKBLEND_IMASKALPHA,
#endif
#if defined(EBI_TFTCTRL_MASKBLEND_EMASK)
/** External masking */
ebiTFTMBEMask = EBI_TFTCTRL_MASKBLEND_EMASK,
/** External alpha blending */
ebiTFTMBEAlpha = EBI_TFTCTRL_MASKBLEND_EALPHA,
/** External masking and alpha blending */
ebiTFTMBEMaskAlpha = EBI_TFTCTRL_MASKBLEND_EMASKEALPHA,
#else
/** External masking */
ebiTFTMBEMask = EBI_TFTCTRL_MASKBLEND_EFBMASK,
/** External alpha blending */
ebiTFTMBEAlpha = EBI_TFTCTRL_MASKBLEND_EFBALPHA,
/** External masking and alpha blending */
ebiTFTMBEMaskAlpha = EBI_TFTCTRL_MASKBLEND_EFBMASKALPHA,
#endif
} EBI_TFTMaskBlend_TypeDef;
/** TFT Direct Drive mode */
typedef enum
{
typedef enum {
/** Disabled */
ebiTFTDDModeDisabled = EBI_TFTCTRL_DD_DISABLED,
/** Direct Drive from internal memory */
@ -296,23 +363,21 @@ typedef enum
} EBI_TFTDDMode_TypeDef;
/** TFT Data Increment Width */
typedef enum
{
typedef enum {
/** Pixel increments are 1 byte at a time */
ebiTFTWidthByte = EBI_TFTCTRL_WIDTH_BYTE,
/** Pixel increments are 2 bytes (half word) */
ebiTFTWidthHalfWord = EBI_TFTCTRL_WIDTH_HALFWORD,
} EBI_TFTWidth_TypeDef;
#endif
#endif // _EBI_TFTCTRL_MASK
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** EBI Initialization structure */
typedef struct
{
typedef struct {
/** EBI operation mode, data and address limits */
EBI_Mode_TypeDef mode;
/** Address Ready pin polarity, active high or low */
@ -325,8 +390,8 @@ typedef struct
EBI_Polarity_TypeDef rePolarity;
/** Chip Select pin polarity, active high or low */
EBI_Polarity_TypeDef csPolarity;
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
/** Byte Lane pin polaritym, active high or low */
#if !defined(_EFM32_GECKO_FAMILY)
/** Byte Lane pin polarity, active high or low */
EBI_Polarity_TypeDef blPolarity;
/** Flag to enable or disable Byte Lane support */
bool blEnable;
@ -345,7 +410,7 @@ typedef struct
int addrSetupCycles;
/** Number of cycles address is driven onto the ADDRDAT bus before ALE is asserted */
int addrHoldCycles;
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if !defined(_EFM32_GECKO_FAMILY)
/** Enable or disables half cycle duration of the ALE strobe in the last address setup cycle */
bool addrHalfALE;
#endif
@ -355,7 +420,7 @@ typedef struct
int readStrobeCycles;
/** Number of cycles CSn is held active after REn is deasserted */
int readHoldCycles;
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if !defined(_EFM32_GECKO_FAMILY)
/** Enable or disable page mode reads */
bool readPageMode;
/** Enables or disable prefetching from sequential addresses */
@ -369,7 +434,7 @@ typedef struct
int writeStrobeCycles;
/** Number of cycles CSn is held active after WEn is deasserted */
int writeHoldCycles;
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if !defined(_EFM32_GECKO_FAMILY)
/** Enable or disable the write buffer */
bool writeBufferDisable;
/** Enables or disables half cycle duration of the WEn signal in the last strobe cycle */
@ -378,6 +443,8 @@ typedef struct
EBI_ALow_TypeDef aLow;
/** High address pin limit to enable */
EBI_AHigh_TypeDef aHigh;
#endif
#if defined(_EBI_ROUTE_LOCATION_MASK)
/** Pin Location */
EBI_Location_TypeDef location;
#endif
@ -386,71 +453,104 @@ typedef struct
} EBI_Init_TypeDef;
/** Default config for EBI init structures */
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if defined(_SILICON_LABS_32B_SERIES_1)
#define EBI_INIT_DEFAULT \
{ \
ebiModeD8A8, /* 8 bit address, 8 bit data */ \
ebiActiveLow, /* ARDY polarity */ \
ebiActiveLow, /* ALE polarity */ \
ebiActiveLow, /* WE polarity */ \
ebiActiveLow, /* RE polarity */ \
ebiActiveLow, /* CS polarity */ \
ebiActiveLow, /* BL polarity */ \
false, /* enable BL */ \
false, /* enable NOIDLE */ \
false, /* enable ARDY */ \
false, /* don't disable ARDY timeout */ \
EBI_BANK0, /* enable bank 0 */ \
EBI_CS0, /* enable chip select 0 */ \
0, /* addr setup cycles */ \
1, /* addr hold cycles */ \
false, /* do not enable half cycle ALE strobe */ \
0, /* read setup cycles */ \
0, /* read strobe cycles */ \
0, /* read hold cycles */ \
false, /* disable page mode */ \
false, /* disable prefetch */ \
false, /* do not enable half cycle REn strobe */ \
0, /* write setup cycles */ \
0, /* write strobe cycles */ \
1, /* write hold cycles */ \
false, /* do not disable the write buffer */ \
false, /* do not enable halc cycle WEn strobe */ \
ebiALowA0, /* ALB - Low bound, address lines */ \
ebiAHighA0, /* APEN - High bound, address lines */ \
ebiLocation0, /* Use Location 0 */ \
true, /* enable EBI */ \
}
{ \
ebiModeD8A8, /* 8 bit address, 8 bit data */ \
ebiActiveLow, /* ARDY polarity */ \
ebiActiveLow, /* ALE polarity */ \
ebiActiveLow, /* WE polarity */ \
ebiActiveLow, /* RE polarity */ \
ebiActiveLow, /* CS polarity */ \
ebiActiveLow, /* BL polarity */ \
false, /* enable BL */ \
false, /* enable NOIDLE */ \
false, /* enable ARDY */ \
false, /* don't disable ARDY timeout */ \
EBI_BANK0, /* enable bank 0 */ \
EBI_CS0, /* enable chip select 0 */ \
0, /* addr setup cycles */ \
1, /* addr hold cycles */ \
false, /* do not enable half cycle ALE strobe */ \
0, /* read setup cycles */ \
0, /* read strobe cycles */ \
0, /* read hold cycles */ \
false, /* disable page mode */ \
false, /* disable prefetch */ \
false, /* do not enable half cycle REn strobe */ \
0, /* write setup cycles */ \
0, /* write strobe cycles */ \
1, /* write hold cycles */ \
false, /* do not disable the write buffer */ \
false, /* do not enable halc cycle WEn strobe */ \
ebiALowA0, /* ALB - Low bound, address lines */ \
ebiAHighA0, /* APEN - High bound, address lines */ \
true, /* enable EBI */ \
}
#elif !defined(_EFM32_GECKO_FAMILY)
#define EBI_INIT_DEFAULT \
{ \
ebiModeD8A8, /* 8 bit address, 8 bit data */ \
ebiActiveLow, /* ARDY polarity */ \
ebiActiveLow, /* ALE polarity */ \
ebiActiveLow, /* WE polarity */ \
ebiActiveLow, /* RE polarity */ \
ebiActiveLow, /* CS polarity */ \
ebiActiveLow, /* BL polarity */ \
false, /* enable BL */ \
false, /* enable NOIDLE */ \
false, /* enable ARDY */ \
false, /* don't disable ARDY timeout */ \
EBI_BANK0, /* enable bank 0 */ \
EBI_CS0, /* enable chip select 0 */ \
0, /* addr setup cycles */ \
1, /* addr hold cycles */ \
false, /* do not enable half cycle ALE strobe */ \
0, /* read setup cycles */ \
0, /* read strobe cycles */ \
0, /* read hold cycles */ \
false, /* disable page mode */ \
false, /* disable prefetch */ \
false, /* do not enable half cycle REn strobe */ \
0, /* write setup cycles */ \
0, /* write strobe cycles */ \
1, /* write hold cycles */ \
false, /* do not disable the write buffer */ \
false, /* do not enable halc cycle WEn strobe */ \
ebiALowA0, /* ALB - Low bound, address lines */ \
ebiAHighA0, /* APEN - High bound, address lines */ \
ebiLocation0, /* Use Location 0 */ \
true, /* enable EBI */ \
}
#else
#define EBI_INIT_DEFAULT \
{ \
ebiModeD8A8, /* 8 bit address, 8 bit data */ \
ebiActiveLow, /* ARDY polarity */ \
ebiActiveLow, /* ALE polarity */ \
ebiActiveLow, /* WE polarity */ \
ebiActiveLow, /* RE polarity */ \
ebiActiveLow, /* CS polarity */ \
false, /* enable ARDY */ \
false, /* don't disable ARDY timeout */ \
EBI_BANK0, /* enable bank 0 */ \
EBI_CS0, /* enable chip select 0 */ \
0, /* addr setup cycles */ \
1, /* addr hold cycles */ \
0, /* read setup cycles */ \
0, /* read strobe cycles */ \
0, /* read hold cycles */ \
0, /* write setup cycles */ \
0, /* write strobe cycles */ \
1, /* write hold cycles */ \
true, /* enable EBI */ \
}
{ \
ebiModeD8A8, /* 8 bit address, 8 bit data */ \
ebiActiveLow, /* ARDY polarity */ \
ebiActiveLow, /* ALE polarity */ \
ebiActiveLow, /* WE polarity */ \
ebiActiveLow, /* RE polarity */ \
ebiActiveLow, /* CS polarity */ \
false, /* enable ARDY */ \
false, /* don't disable ARDY timeout */ \
EBI_BANK0, /* enable bank 0 */ \
EBI_CS0, /* enable chip select 0 */ \
0, /* addr setup cycles */ \
1, /* addr hold cycles */ \
0, /* read setup cycles */ \
0, /* read strobe cycles */ \
0, /* read hold cycles */ \
0, /* write setup cycles */ \
0, /* write strobe cycles */ \
1, /* write hold cycles */ \
true, /* enable EBI */ \
}
#endif
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if defined(_EBI_TFTCTRL_MASK)
/** TFT Initialization structure */
typedef struct
{
typedef struct {
/** External memory bank for driving display */
EBI_TFTBank_TypeDef bank;
/** Width */
@ -507,36 +607,36 @@ typedef struct
/** Default configuration for EBI TFT init structure */
#define EBI_TFTINIT_DEFAULT \
{ \
ebiTFTBank0, /* Select EBI Bank 0 */ \
ebiTFTWidthHalfWord, /* Select 2-byte increments */ \
ebiTFTColorSrcMem, /* Use memory as source for mask/blending */ \
ebiTFTInterleaveUnlimited, /* Unlimited interleaved accesses */ \
ebiTFTFrameBufTriggerVSync, /* VSYNC as frame buffer update trigger */ \
false, /* Drive DCLK from negative edge of internal clock */ \
ebiTFTMBDisabled, /* No masking and alpha blending enabled */ \
ebiTFTDDModeExternal, /* Drive from external memory */ \
ebiActiveLow, /* CS Active Low polarity */ \
ebiActiveLow, /* DCLK Active Low polarity */ \
ebiActiveLow, /* DATAEN Active Low polarity */ \
ebiActiveLow, /* HSYNC Active Low polarity */ \
ebiActiveLow, /* VSYNC Active Low polarity */ \
320, /* Horizontal size in pixels */ \
1, /* Horizontal Front Porch */ \
29, /* Horizontal Back Porch */ \
2, /* Horizontal Synchronization Pulse Width */ \
240, /* Vertical size in pixels */ \
1, /* Vertical Front Porch */ \
4, /* Vertical Back Porch */ \
2, /* Vertical Synchronization Pulse Width */ \
0x0000, /* Address offset to EBI memory base */ \
5, /* DCLK Period */ \
2, /* DCLK Start */ \
1, /* DCLK Setup cycles */ \
1, /* DCLK Hold cycles */ \
}
{ \
ebiTFTBank0, /* Select EBI Bank 0 */ \
ebiTFTWidthHalfWord, /* Select 2-byte increments */ \
ebiTFTColorSrcMem, /* Use memory as source for mask/blending */ \
ebiTFTInterleaveUnlimited, /* Unlimited interleaved accesses */ \
ebiTFTFrameBufTriggerVSync, /* VSYNC as frame buffer update trigger */ \
false, /* Drive DCLK from negative edge of internal clock */ \
ebiTFTMBDisabled, /* No masking and alpha blending enabled */ \
ebiTFTDDModeExternal, /* Drive from external memory */ \
ebiActiveLow, /* CS Active Low polarity */ \
ebiActiveLow, /* DCLK Active Low polarity */ \
ebiActiveLow, /* DATAEN Active Low polarity */ \
ebiActiveLow, /* HSYNC Active Low polarity */ \
ebiActiveLow, /* VSYNC Active Low polarity */ \
320, /* Horizontal size in pixels */ \
1, /* Horizontal Front Porch */ \
29, /* Horizontal Back Porch */ \
2, /* Horizontal Synchronization Pulse Width */ \
240, /* Vertical size in pixels */ \
1, /* Vertical Front Porch */ \
4, /* Vertical Back Porch */ \
2, /* Vertical Synchronization Pulse Width */ \
0x0000, /* Address offset to EBI memory base */ \
5, /* DCLK Period */ \
2, /* DCLK Start */ \
1, /* DCLK Setup cycles */ \
1, /* DCLK Hold cycles */ \
}
#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
@ -546,7 +646,7 @@ void EBI_Disable(void);
uint32_t EBI_BankAddress(uint32_t bank);
void EBI_BankEnable(uint32_t banks, bool enable);
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if defined(_EBI_TFTCTRL_MASK)
void EBI_TFTInit(const EBI_TFTInit_TypeDef *ebiTFTInit);
void EBI_TFTSizeSet(uint32_t horizontal, uint32_t vertical);
void EBI_TFTHPorchSet(int front, int back, int pulseWidth);
@ -554,7 +654,7 @@ void EBI_TFTVPorchSet(int front, int back, int pulseWidth);
void EBI_TFTTimingSet(int dclkPeriod, int start, int setup, int hold);
#endif
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if !defined(_EFM32_GECKO_FAMILY)
/* This functionality is only available on devices with independent timing support */
void EBI_BankReadTimingSet(uint32_t bank, int setupCycles, int strobeCycles, int holdCycles);
void EBI_BankReadTimingConfig(uint32_t bank, bool pageMode, bool prefetch, bool halfRE);
@ -568,7 +668,9 @@ void EBI_BankAddressTimingConfig(uint32_t bank, bool halfALE);
void EBI_BankPolaritySet(uint32_t bank, EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity);
void EBI_BankByteLaneEnable(uint32_t bank, bool enable);
void EBI_AltMapEnable(bool enable);
#endif
#if defined(_EBI_TFTCTRL_MASK)
/***************************************************************************//**
* @brief
* Enable or disable TFT Direct Drive
@ -581,7 +683,6 @@ __STATIC_INLINE void EBI_TFTEnable(EBI_TFTDDMode_TypeDef mode)
EBI->TFTCTRL = (EBI->TFTCTRL & ~(_EBI_TFTCTRL_DD_MASK)) | (uint32_t) mode;
}
/***************************************************************************//**
* @brief
* Configure frame buffer pointer
@ -594,7 +695,6 @@ __STATIC_INLINE void EBI_TFTFrameBaseSet(uint32_t address)
EBI->TFTFRAMEBASE = (uint32_t) address;
}
/***************************************************************************//**
* @brief Set TFT Pixel Color 0 or 1
*
@ -607,17 +707,14 @@ __STATIC_INLINE void EBI_TFTPixelSet(int pixel, uint32_t color)
{
EFM_ASSERT(pixel == 0 || pixel == 1);
if (pixel == 0)
{
if (pixel == 0) {
EBI->TFTPIXEL0 = color;
}
if (pixel == 1)
{
if (pixel == 1) {
EBI->TFTPIXEL1 = color;
}
}
/***************************************************************************//**
* @brief Masking and Blending Mode Set
*
@ -626,10 +723,9 @@ __STATIC_INLINE void EBI_TFTPixelSet(int pixel, uint32_t color)
******************************************************************************/
__STATIC_INLINE void EBI_TFTMaskBlendMode(EBI_TFTMaskBlend_TypeDef maskBlend)
{
EBI->TFTCTRL = (EBI->TFTCTRL & (~_EBI_TFTCTRL_MASKBLEND_MASK))|maskBlend;
EBI->TFTCTRL = (EBI->TFTCTRL & (~_EBI_TFTCTRL_MASKBLEND_MASK)) | maskBlend;
}
/***************************************************************************//**
* @brief Set TFT Alpha Blending Factor
*
@ -641,7 +737,6 @@ __STATIC_INLINE void EBI_TFTAlphaBlendSet(uint8_t alpha)
EBI->TFTALPHA = alpha;
}
/***************************************************************************//**
* @brief Set TFT mask value
* Data accesses that matches this value are suppressed
@ -652,7 +747,6 @@ __STATIC_INLINE void EBI_TFTMaskSet(uint32_t mask)
EBI->TFTMASK = mask;
}
/***************************************************************************//**
* @brief Get current vertical position counter
* @return
@ -663,7 +757,6 @@ __STATIC_INLINE uint32_t EBI_TFTVCount(void)
return((EBI->TFTSTATUS & _EBI_TFTSTATUS_VCNT_MASK) >> _EBI_TFTSTATUS_VCNT_SHIFT);
}
/***************************************************************************//**
* @brief Get current horizontal position counter
* @return
@ -674,7 +767,6 @@ __STATIC_INLINE uint32_t EBI_TFTHCount(void)
return((EBI->TFTSTATUS & _EBI_TFTSTATUS_HCNT_MASK) >> _EBI_TFTSTATUS_HCNT_SHIFT);
}
/***************************************************************************//**
* @brief Set Frame Buffer Trigger
*
@ -687,10 +779,9 @@ __STATIC_INLINE uint32_t EBI_TFTHCount(void)
******************************************************************************/
__STATIC_INLINE void EBI_TFTFBTriggerSet(EBI_TFTFrameBufTrigger_TypeDef sync)
{
EBI->TFTCTRL = ((EBI->TFTCTRL & ~_EBI_TFTCTRL_FBCTRIG_MASK)|sync);
EBI->TFTCTRL = ((EBI->TFTCTRL & ~_EBI_TFTCTRL_FBCTRIG_MASK) | sync);
}
/***************************************************************************//**
* @brief Set horizontal TFT stride value in number of bytes
*
@ -702,11 +793,12 @@ __STATIC_INLINE void EBI_TFTHStrideSet(uint32_t nbytes)
{
EFM_ASSERT(nbytes < 0x1000);
EBI->TFTSTRIDE = (EBI->TFTSTRIDE & ~(_EBI_TFTSTRIDE_HSTRIDE_MASK))|
(nbytes<<_EBI_TFTSTRIDE_HSTRIDE_SHIFT);
EBI->TFTSTRIDE = (EBI->TFTSTRIDE & ~(_EBI_TFTSTRIDE_HSTRIDE_MASK))
| (nbytes << _EBI_TFTSTRIDE_HSTRIDE_SHIFT);
}
#endif // _EBI_TFTCTRL_MASK
#if defined(_EBI_IF_MASK)
/***************************************************************************//**
* @brief
* Clear one or more pending EBI interrupts.
@ -719,7 +811,6 @@ __STATIC_INLINE void EBI_IntClear(uint32_t flags)
EBI->IFC = flags;
}
/***************************************************************************//**
* @brief
* Set one or more pending EBI interrupts.
@ -733,7 +824,6 @@ __STATIC_INLINE void EBI_IntSet(uint32_t flags)
EBI->IFS = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more EBI interrupts.
@ -747,7 +837,6 @@ __STATIC_INLINE void EBI_IntDisable(uint32_t flags)
EBI->IEN &= ~(flags);
}
/***************************************************************************//**
* @brief
* Enable one or more EBI interrupts.
@ -761,7 +850,6 @@ __STATIC_INLINE void EBI_IntEnable(uint32_t flags)
EBI->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending EBI interrupt flags.
@ -778,7 +866,6 @@ __STATIC_INLINE uint32_t EBI_IntGet(void)
return EBI->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending EBI interrupt flags.
@ -800,8 +887,9 @@ __STATIC_INLINE uint32_t EBI_IntGetEnabled(void)
ien = EBI->IEN;
return EBI->IF & ien;
}
#endif // _EBI_IF_MASK
#if defined(_EBI_CMD_MASK)
/***************************************************************************//**
* @brief
* Start ECC generator on NAND flash transfers.
@ -811,7 +899,6 @@ __STATIC_INLINE void EBI_StartNandEccGen(void)
EBI->CMD = EBI_CMD_ECCSTART | EBI_CMD_ECCCLEAR;
}
/***************************************************************************//**
* @brief
* Stop NAND flash ECC generator and return generated ECC.
@ -819,12 +906,12 @@ __STATIC_INLINE void EBI_StartNandEccGen(void)
* @return
* The generated ECC.
******************************************************************************/
__STATIC_INLINE uint32_t EBI_StopNandEccGen( void )
__STATIC_INLINE uint32_t EBI_StopNandEccGen(void)
{
EBI->CMD = EBI_CMD_ECCSTOP;
return EBI->ECCPARITY;
}
#endif
#endif // _EBI_CMD_MASK
void EBI_ChipSelectEnable(uint32_t banks, bool enable);
void EBI_ReadTimingSet(int setupCycles, int strobeCycles, int holdCycles);

593
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h
View File

File diff suppressed because it is too large Load Diff

27
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpcrc.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file
* @brief General Purpose Cyclic Redundancy Check (GPCRC) API.
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -99,8 +99,7 @@ extern "C" {
******************************************************************************/
/** CRC initialization structure. */
typedef struct
{
typedef struct {
/**
* CRC polynomial value. The GPCRC support either a fixed 32-bit polynomial
* or a user configurable 16 bit polynomial. The fixed 32-bit polynomial
@ -159,16 +158,16 @@ typedef struct
} GPCRC_Init_TypeDef;
/** Default configuration for GPCRC_Init_TypeDef structure. */
#define GPCRC_INIT_DEFAULT \
{ \
0x04C11DB7UL, /* CRC32 Polynomial value. */ \
0x00000000UL, /* Initialization value. */ \
false, /* Byte order is normal. */ \
false, /* Bit order is not reversed on output. */ \
false, /* Disable byte mode. */ \
false, /* Disable automatic init on data read. */ \
true, /* Enable GPCRC. */ \
}
#define GPCRC_INIT_DEFAULT \
{ \
0x04C11DB7UL, /* CRC32 Polynomial value. */ \
0x00000000UL, /* Initialization value. */ \
false, /* Byte order is normal. */ \
false, /* Bit order is not reversed on output. */ \
false, /* Disable byte mode. */ \
false, /* Disable automatic init on data read. */ \
true, /* Enable GPCRC. */ \
}
/*******************************************************************************
****************************** PROTOTYPES *********************************

331
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_gpio.h
* @brief General Purpose IO (GPIO) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -30,7 +30,6 @@
*
******************************************************************************/
#ifndef EM_GPIO_H
#define EM_GPIO_H
@ -60,7 +59,8 @@ extern "C" {
******************************************************************************/
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
#if defined( _EFM32_TINY_FAMILY ) || defined( _EFM32_ZERO_FAMILY )
#if defined(_SILICON_LABS_32B_SERIES_0) \
&& defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY)
#define _GPIO_PORT_A_PIN_COUNT 14
#define _GPIO_PORT_B_PIN_COUNT 10
@ -86,7 +86,7 @@ extern "C" {
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
#elif defined( _EFM32_HAPPY_FAMILY )
#elif defined(_EFM32_HAPPY_FAMILY)
#define _GPIO_PORT_A_PIN_COUNT 6
#define _GPIO_PORT_B_PIN_COUNT 5
@ -112,8 +112,8 @@ extern "C" {
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
#elif defined( _EFM32_GIANT_FAMILY ) \
|| defined( _EFM32_WONDER_FAMILY )
#elif defined(_SILICON_LABS_32B_SERIES_0) \
&& (defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY))
#define _GPIO_PORT_A_PIN_COUNT 16
#define _GPIO_PORT_B_PIN_COUNT 16
@ -139,7 +139,7 @@ extern "C" {
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
#elif defined( _EFM32_GECKO_FAMILY )
#elif defined(_EFM32_GECKO_FAMILY)
#define _GPIO_PORT_A_PIN_COUNT 16
#define _GPIO_PORT_B_PIN_COUNT 16
@ -165,33 +165,7 @@ extern "C" {
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) && defined( _EFR_DEVICE )
#define _GPIO_PORT_A_PIN_COUNT 6
#define _GPIO_PORT_B_PIN_COUNT 5
#define _GPIO_PORT_C_PIN_COUNT 6
#define _GPIO_PORT_D_PIN_COUNT 6
#define _GPIO_PORT_E_PIN_COUNT 0
#define _GPIO_PORT_F_PIN_COUNT 8
#define _GPIO_PORT_G_PIN_COUNT 0
#define _GPIO_PORT_H_PIN_COUNT 0
#define _GPIO_PORT_I_PIN_COUNT 0
#define _GPIO_PORT_J_PIN_COUNT 0
#define _GPIO_PORT_K_PIN_COUNT 0
#define _GPIO_PORT_A_PIN_MASK 0x003F
#define _GPIO_PORT_B_PIN_MASK 0xF800
#define _GPIO_PORT_C_PIN_MASK 0x0FC0
#define _GPIO_PORT_D_PIN_MASK 0xFC00
#define _GPIO_PORT_E_PIN_MASK 0x0000
#define _GPIO_PORT_F_PIN_MASK 0x00FF
#define _GPIO_PORT_G_PIN_MASK 0x0000
#define _GPIO_PORT_H_PIN_MASK 0x0000
#define _GPIO_PORT_I_PIN_MASK 0x0000
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) && defined( _EFM_DEVICE )
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE)
#define _GPIO_PORT_A_PIN_COUNT 6
#define _GPIO_PORT_B_PIN_COUNT 5
@ -217,7 +191,33 @@ extern "C" {
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_84 )
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFM_DEVICE)
#define _GPIO_PORT_A_PIN_COUNT 6
#define _GPIO_PORT_B_PIN_COUNT 5
#define _GPIO_PORT_C_PIN_COUNT 6
#define _GPIO_PORT_D_PIN_COUNT 7
#define _GPIO_PORT_E_PIN_COUNT 0
#define _GPIO_PORT_F_PIN_COUNT 8
#define _GPIO_PORT_G_PIN_COUNT 0
#define _GPIO_PORT_H_PIN_COUNT 0
#define _GPIO_PORT_I_PIN_COUNT 0
#define _GPIO_PORT_J_PIN_COUNT 0
#define _GPIO_PORT_K_PIN_COUNT 0
#define _GPIO_PORT_A_PIN_MASK 0x003F
#define _GPIO_PORT_B_PIN_MASK 0xF800
#define _GPIO_PORT_C_PIN_MASK 0x0FC0
#define _GPIO_PORT_D_PIN_MASK 0xFE00
#define _GPIO_PORT_E_PIN_MASK 0x0000
#define _GPIO_PORT_F_PIN_MASK 0x00FF
#define _GPIO_PORT_G_PIN_MASK 0x0000
#define _GPIO_PORT_H_PIN_MASK 0x0000
#define _GPIO_PORT_I_PIN_MASK 0x0000
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
#define _GPIO_PORT_A_PIN_COUNT 10
#define _GPIO_PORT_B_PIN_COUNT 10
@ -243,7 +243,7 @@ extern "C" {
#define _GPIO_PORT_J_PIN_MASK 0xC000
#define _GPIO_PORT_K_PIN_MASK 0x0007
#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_89 )
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
#define _GPIO_PORT_A_PIN_COUNT 6
#define _GPIO_PORT_B_PIN_COUNT 5
@ -269,46 +269,124 @@ extern "C" {
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
#elif defined(_SILICON_LABS_32B_SERIES_1) && defined(_EFM32_GIANT_FAMILY)
#define _GPIO_PORT_A_PIN_COUNT 16
#define _GPIO_PORT_B_PIN_COUNT 16
#define _GPIO_PORT_C_PIN_COUNT 16
#define _GPIO_PORT_D_PIN_COUNT 16
#define _GPIO_PORT_E_PIN_COUNT 16
#define _GPIO_PORT_F_PIN_COUNT 16
#define _GPIO_PORT_G_PIN_COUNT 16
#define _GPIO_PORT_H_PIN_COUNT 16
#define _GPIO_PORT_I_PIN_COUNT 16
#define _GPIO_PORT_J_PIN_COUNT 0
#define _GPIO_PORT_K_PIN_COUNT 0
#define _GPIO_PORT_A_PIN_MASK 0xFFFF
#define _GPIO_PORT_B_PIN_MASK 0xFFFF
#define _GPIO_PORT_C_PIN_MASK 0xFFFF
#define _GPIO_PORT_D_PIN_MASK 0xFFFF
#define _GPIO_PORT_E_PIN_MASK 0xFFFF
#define _GPIO_PORT_F_PIN_MASK 0xFFFF
#define _GPIO_PORT_G_PIN_MASK 0xFFFF
#define _GPIO_PORT_H_PIN_MASK 0xFFFF
#define _GPIO_PORT_I_PIN_MASK 0xFFFF
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
#define _GPIO_PORT_A_PIN_COUNT 6
#define _GPIO_PORT_B_PIN_COUNT 5
#define _GPIO_PORT_C_PIN_COUNT 6
#define _GPIO_PORT_D_PIN_COUNT 6
#define _GPIO_PORT_E_PIN_COUNT 0
#define _GPIO_PORT_F_PIN_COUNT 8
#define _GPIO_PORT_G_PIN_COUNT 0
#define _GPIO_PORT_H_PIN_COUNT 0
#define _GPIO_PORT_I_PIN_COUNT 0
#define _GPIO_PORT_J_PIN_COUNT 0
#define _GPIO_PORT_K_PIN_COUNT 0
#define _GPIO_PORT_A_PIN_MASK 0x003F
#define _GPIO_PORT_B_PIN_MASK 0xF800
#define _GPIO_PORT_C_PIN_MASK 0x0FC0
#define _GPIO_PORT_D_PIN_MASK 0xFC00
#define _GPIO_PORT_E_PIN_MASK 0x0000
#define _GPIO_PORT_F_PIN_MASK 0x00FF
#define _GPIO_PORT_G_PIN_MASK 0x0000
#define _GPIO_PORT_H_PIN_MASK 0x0000
#define _GPIO_PORT_I_PIN_MASK 0x0000
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
#define _GPIO_PORT_A_PIN_COUNT 14
#define _GPIO_PORT_B_PIN_COUNT 10
#define _GPIO_PORT_C_PIN_COUNT 16
#define _GPIO_PORT_D_PIN_COUNT 9
#define _GPIO_PORT_E_PIN_COUNT 12
#define _GPIO_PORT_F_PIN_COUNT 6
#define _GPIO_PORT_G_PIN_COUNT 0
#define _GPIO_PORT_H_PIN_COUNT 0
#define _GPIO_PORT_I_PIN_COUNT 0
#define _GPIO_PORT_J_PIN_COUNT 0
#define _GPIO_PORT_K_PIN_COUNT 0
#define _GPIO_PORT_A_PIN_MASK 0xF77F
#define _GPIO_PORT_B_PIN_MASK 0x79F8
#define _GPIO_PORT_C_PIN_MASK 0xFFFF
#define _GPIO_PORT_D_PIN_MASK 0x01FF
#define _GPIO_PORT_E_PIN_MASK 0xFFF0
#define _GPIO_PORT_F_PIN_MASK 0x003F
#define _GPIO_PORT_G_PIN_MASK 0x0000
#define _GPIO_PORT_H_PIN_MASK 0x0000
#define _GPIO_PORT_I_PIN_MASK 0x0000
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
#else
#warning "Port and pin masks are not defined for this family."
#endif
#define _GPIO_PORT_SIZE(port) ( \
(port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \
(port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \
(port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \
(port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \
(port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \
(port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \
(port) == 6 ? _GPIO_PORT_G_PIN_COUNT : \
(port) == 7 ? _GPIO_PORT_H_PIN_COUNT : \
(port) == 8 ? _GPIO_PORT_I_PIN_COUNT : \
(port) == 9 ? _GPIO_PORT_J_PIN_COUNT : \
(port) == 10 ? _GPIO_PORT_K_PIN_COUNT : \
0)
#define _GPIO_PORT_SIZE(port) ( \
(port) == 0 ? _GPIO_PORT_A_PIN_COUNT \
: (port) == 1 ? _GPIO_PORT_B_PIN_COUNT \
: (port) == 2 ? _GPIO_PORT_C_PIN_COUNT \
: (port) == 3 ? _GPIO_PORT_D_PIN_COUNT \
: (port) == 4 ? _GPIO_PORT_E_PIN_COUNT \
: (port) == 5 ? _GPIO_PORT_F_PIN_COUNT \
: (port) == 6 ? _GPIO_PORT_G_PIN_COUNT \
: (port) == 7 ? _GPIO_PORT_H_PIN_COUNT \
: (port) == 8 ? _GPIO_PORT_I_PIN_COUNT \
: (port) == 9 ? _GPIO_PORT_J_PIN_COUNT \
: (port) == 10 ? _GPIO_PORT_K_PIN_COUNT \
: 0)
#define _GPIO_PORT_MASK(port) ( \
(port) == 0 ? _GPIO_PORT_A_PIN_MASK : \
(port) == 1 ? _GPIO_PORT_B_PIN_MASK : \
(port) == 2 ? _GPIO_PORT_C_PIN_MASK : \
(port) == 3 ? _GPIO_PORT_D_PIN_MASK : \
(port) == 4 ? _GPIO_PORT_E_PIN_MASK : \
(port) == 5 ? _GPIO_PORT_F_PIN_MASK : \
(port) == 6 ? _GPIO_PORT_G_PIN_MASK : \
(port) == 7 ? _GPIO_PORT_H_PIN_MASK : \
(port) == 8 ? _GPIO_PORT_I_PIN_MASK : \
(port) == 9 ? _GPIO_PORT_J_PIN_MASK : \
(port) == 10 ? _GPIO_PORT_K_PIN_MASK : \
0)
#define _GPIO_PORT_MASK(port) ( \
(port) == 0 ? _GPIO_PORT_A_PIN_MASK \
: (port) == 1 ? _GPIO_PORT_B_PIN_MASK \
: (port) == 2 ? _GPIO_PORT_C_PIN_MASK \
: (port) == 3 ? _GPIO_PORT_D_PIN_MASK \
: (port) == 4 ? _GPIO_PORT_E_PIN_MASK \
: (port) == 5 ? _GPIO_PORT_F_PIN_MASK \
: (port) == 6 ? _GPIO_PORT_G_PIN_MASK \
: (port) == 7 ? _GPIO_PORT_H_PIN_MASK \
: (port) == 8 ? _GPIO_PORT_I_PIN_MASK \
: (port) == 9 ? _GPIO_PORT_J_PIN_MASK \
: (port) == 10 ? _GPIO_PORT_K_PIN_MASK \
: 0)
/** Validation of port and pin */
#define GPIO_PORT_VALID(port) ( _GPIO_PORT_MASK(port) )
#define GPIO_PORT_PIN_VALID(port, pin) ((( _GPIO_PORT_MASK(port)) >> (pin)) & 0x1 )
#define GPIO_PORT_VALID(port) (_GPIO_PORT_MASK(port) )
#define GPIO_PORT_PIN_VALID(port, pin) (((_GPIO_PORT_MASK(port)) >> (pin)) & 0x1)
#if defined(_GPIO_EXTIPINSELL_MASK)
/** Validation of interrupt number and pin */
#define GPIO_INTNO_PIN_VALID(intNo, pin) \
((intNo & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) \
#define GPIO_INTNO_PIN_VALID(intNo, pin) \
((intNo & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) \
== (pin & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK))
#endif
@ -316,17 +394,17 @@ extern "C" {
#define GPIO_PIN_MAX 15
/** Highest GPIO port number */
#if ( _GPIO_PORT_K_PIN_COUNT > 0 )
#if (_GPIO_PORT_K_PIN_COUNT > 0)
#define GPIO_PORT_MAX 10
#elif ( _GPIO_PORT_J_PIN_COUNT > 0 )
#elif (_GPIO_PORT_J_PIN_COUNT > 0)
#define GPIO_PORT_MAX 9
#elif ( _GPIO_PORT_I_PIN_COUNT > 0 )
#elif (_GPIO_PORT_I_PIN_COUNT > 0)
#define GPIO_PORT_MAX 8
#elif ( _GPIO_PORT_H_PIN_COUNT > 0 )
#elif (_GPIO_PORT_H_PIN_COUNT > 0)
#define GPIO_PORT_MAX 7
#elif ( _GPIO_PORT_G_PIN_COUNT > 0 )
#elif (_GPIO_PORT_G_PIN_COUNT > 0)
#define GPIO_PORT_MAX 6
#elif ( _GPIO_PORT_F_PIN_COUNT > 0 )
#elif (_GPIO_PORT_F_PIN_COUNT > 0)
#define GPIO_PORT_MAX 5
#else
#error "Max GPIO port number is undefined for this part."
@ -342,47 +420,45 @@ extern "C" {
******************************************************************************/
/** GPIO ports ids. */
typedef enum
{
#if ( _GPIO_PORT_A_PIN_COUNT > 0 )
typedef enum {
#if (_GPIO_PORT_A_PIN_COUNT > 0)
gpioPortA = 0,
#endif
#if ( _GPIO_PORT_B_PIN_COUNT > 0 )
#if (_GPIO_PORT_B_PIN_COUNT > 0)
gpioPortB = 1,
#endif
#if ( _GPIO_PORT_C_PIN_COUNT > 0 )
#if (_GPIO_PORT_C_PIN_COUNT > 0)
gpioPortC = 2,
#endif
#if ( _GPIO_PORT_D_PIN_COUNT > 0 )
#if (_GPIO_PORT_D_PIN_COUNT > 0)
gpioPortD = 3,
#endif
#if ( _GPIO_PORT_E_PIN_COUNT > 0 )
#if (_GPIO_PORT_E_PIN_COUNT > 0)
gpioPortE = 4,
#endif
#if ( _GPIO_PORT_F_PIN_COUNT > 0 )
#if (_GPIO_PORT_F_PIN_COUNT > 0)
gpioPortF = 5,
#endif
#if ( _GPIO_PORT_G_PIN_COUNT > 0 )
#if (_GPIO_PORT_G_PIN_COUNT > 0)
gpioPortG = 6,
#endif
#if ( _GPIO_PORT_H_PIN_COUNT > 0 )
#if (_GPIO_PORT_H_PIN_COUNT > 0)
gpioPortH = 7,
#endif
#if ( _GPIO_PORT_I_PIN_COUNT > 0 )
#if (_GPIO_PORT_I_PIN_COUNT > 0)
gpioPortI = 8,
#endif
#if ( _GPIO_PORT_J_PIN_COUNT > 0 )
#if (_GPIO_PORT_J_PIN_COUNT > 0)
gpioPortJ = 9,
#endif
#if ( _GPIO_PORT_K_PIN_COUNT > 0 )
#if (_GPIO_PORT_K_PIN_COUNT > 0)
gpioPortK = 10,
#endif
} GPIO_Port_TypeDef;
#if defined( _GPIO_P_CTRL_DRIVEMODE_MASK )
#if defined(_GPIO_P_CTRL_DRIVEMODE_MASK)
/** GPIO drive mode. */
typedef enum
{
typedef enum {
/** Default 6mA */
gpioDriveModeStandard = GPIO_P_CTRL_DRIVEMODE_STANDARD,
/** 0.5 mA */
@ -394,17 +470,16 @@ typedef enum
} GPIO_DriveMode_TypeDef;
#endif
#if defined( _GPIO_P_CTRL_DRIVESTRENGTH_MASK ) && defined( _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK )
#if defined(_GPIO_P_CTRL_DRIVESTRENGTH_MASK) && defined(_GPIO_P_CTRL_DRIVESTRENGTHALT_MASK)
/** GPIO drive strength. */
typedef enum
{
typedef enum {
/** GPIO weak 1mA and alternate function weak 1mA */
gpioDriveStrengthWeakAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK,
/** GPIO weak 1mA and alternate function strong 10mA */
gpioDriveStrengthWeakAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG,
/** GPIO strong 10mA and alternate function weak 1mA */
/** GPIO strong 10mA and alternate function weak 1mA */
gpioDriveStrengthStrongAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK,
/** GPIO strong 10mA and alternate function strong 10mA */
@ -418,8 +493,7 @@ typedef enum
/** Pin mode. For more details on each mode, please refer to the
* reference manual. */
typedef enum
{
typedef enum {
/** Input disabled. Pullup if DOUT is set. */
gpioModeDisabled = _GPIO_P_MODEL_MODE0_DISABLED,
/** Input enabled. Filter if DOUT is set */
@ -430,11 +504,11 @@ typedef enum
gpioModeInputPullFilter = _GPIO_P_MODEL_MODE0_INPUTPULLFILTER,
/** Push-pull output */
gpioModePushPull = _GPIO_P_MODEL_MODE0_PUSHPULL,
#if defined( _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE )
#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLDRIVE)
/** Push-pull output with drive-strength set by DRIVEMODE */
gpioModePushPullDrive = _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE,
#endif
#if defined( _GPIO_P_MODEL_MODE0_PUSHPULLALT )
#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLALT)
/** Push-pull using alternate control */
gpioModePushPullAlternate = _GPIO_P_MODEL_MODE0_PUSHPULLALT,
#endif
@ -450,7 +524,7 @@ typedef enum
gpioModeWiredAndPullUp = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP,
/** Open-drain output with filter and pullup */
gpioModeWiredAndPullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER,
#if defined( _GPIO_P_MODEL_MODE0_WIREDANDDRIVE )
#if defined(_GPIO_P_MODEL_MODE0_WIREDANDDRIVE)
/** Open-drain output with drive-strength set by DRIVEMODE */
gpioModeWiredAndDrive = _GPIO_P_MODEL_MODE0_WIREDANDDRIVE,
/** Open-drain output with filter and drive-strength set by DRIVEMODE */
@ -460,7 +534,7 @@ typedef enum
/** Open-drain output with filter, pullup and drive-strength set by DRIVEMODE */
gpioModeWiredAndDrivePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER
#endif
#if defined( _GPIO_P_MODEL_MODE0_WIREDANDALT )
#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALT)
/** Open-drain output using alternate control */
gpioModeWiredAndAlternate = _GPIO_P_MODEL_MODE0_WIREDANDALT,
/** Open-drain output using alternate control with filter */
@ -492,9 +566,9 @@ void GPIO_DbgLocationSet(unsigned int location);
******************************************************************************/
__STATIC_INLINE void GPIO_DbgSWDClkEnable(bool enable)
{
#if defined( _GPIO_ROUTE_SWCLKPEN_MASK )
#if defined(_GPIO_ROUTE_SWCLKPEN_MASK)
BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, enable);
#elif defined( _GPIO_ROUTEPEN_SWCLKTCKPEN_MASK )
#elif defined(_GPIO_ROUTEPEN_SWCLKTCKPEN_MASK)
BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT, enable);
#else
#warning "ROUTE enable for SWCLK pin is not defined."
@ -515,16 +589,16 @@ __STATIC_INLINE void GPIO_DbgSWDClkEnable(bool enable)
******************************************************************************/
__STATIC_INLINE void GPIO_DbgSWDIOEnable(bool enable)
{
#if defined( _GPIO_ROUTE_SWDIOPEN_MASK )
#if defined(_GPIO_ROUTE_SWDIOPEN_MASK)
BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, enable);
#elif defined( _GPIO_ROUTEPEN_SWDIOTMSPEN_MASK )
#elif defined(_GPIO_ROUTEPEN_SWDIOTMSPEN_MASK)
BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT, enable);
#else
#warning "ROUTE enable for SWDIO pin is not defined."
#endif
}
#if defined( _GPIO_ROUTE_SWOPEN_MASK ) || defined( _GPIO_ROUTEPEN_SWVPEN_MASK )
#if defined(_GPIO_ROUTE_SWOPEN_MASK) || defined(_GPIO_ROUTEPEN_SWVPEN_MASK)
/***************************************************************************//**
* @brief
* Enable/Disable serial wire output pin.
@ -532,7 +606,7 @@ __STATIC_INLINE void GPIO_DbgSWDIOEnable(bool enable)
* @note
* Enabling this pin is not sufficient to fully enable serial wire output
* which is also dependent on issues outside the GPIO module. Please refer to
* DBG_SWOEnable().
* @ref DBG_SWOEnable().
*
* @param[in] enable
* @li false - disable serial wire viewer pin (default after reset).
@ -540,9 +614,9 @@ __STATIC_INLINE void GPIO_DbgSWDIOEnable(bool enable)
******************************************************************************/
__STATIC_INLINE void GPIO_DbgSWOEnable(bool enable)
{
#if defined( _GPIO_ROUTE_SWOPEN_MASK )
#if defined(_GPIO_ROUTE_SWOPEN_MASK)
BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, enable);
#elif defined( _GPIO_ROUTEPEN_SWVPEN_MASK )
#elif defined(_GPIO_ROUTEPEN_SWVPEN_MASK)
BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWVPEN_SHIFT, enable);
#else
#warning "ROUTE enable for SWO/SWV pin is not defined."
@ -554,11 +628,11 @@ __STATIC_INLINE void GPIO_DbgSWOEnable(bool enable)
void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode);
#endif
#if defined( _GPIO_P_CTRL_DRIVESTRENGTH_MASK )
#if defined(_GPIO_P_CTRL_DRIVESTRENGTH_MASK)
void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, GPIO_DriveStrength_TypeDef strength);
#endif
# if defined( _GPIO_EM4WUEN_MASK )
# if defined(_GPIO_EM4WUEN_MASK)
/**************************************************************************//**
* @brief
* Disable GPIO pin wake-up from EM4.
@ -575,11 +649,11 @@ __STATIC_INLINE void GPIO_EM4DisablePinWakeup(uint32_t pinmask)
}
#endif
# if defined( _GPIO_EM4WUEN_MASK )
# if defined(_GPIO_EM4WUEN_MASK)
void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask);
#endif
#if defined( _GPIO_EM4WUCAUSE_MASK ) || defined( _GPIO_IF_EM4WU_MASK )
#if defined(_GPIO_EM4WUCAUSE_MASK) || defined(_GPIO_IF_EM4WU_MASK)
/**************************************************************************//**
* @brief
* Check which GPIO pin(s) that caused a wake-up from EM4.
@ -590,7 +664,7 @@ void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask);
*****************************************************************************/
__STATIC_INLINE uint32_t GPIO_EM4GetPinWakeupCause(void)
{
#if defined( _GPIO_EM4WUCAUSE_MASK )
#if defined(_GPIO_EM4WUCAUSE_MASK)
return GPIO->EM4WUCAUSE & _GPIO_EM4WUCAUSE_MASK;
#else
return GPIO->IF & _GPIO_IF_EM4WU_MASK;
@ -598,14 +672,14 @@ __STATIC_INLINE uint32_t GPIO_EM4GetPinWakeupCause(void)
}
#endif
#if defined( GPIO_CTRL_EM4RET ) || defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
#if defined(GPIO_CTRL_EM4RET) || defined(_EMU_EM4CTRL_EM4IORETMODE_MASK)
/**************************************************************************//**
* @brief
* Enable GPIO pin retention of output enable, output value, pull enable and
* pull direction in EM4.
*
* @note
* For platform 2 parts, EMU_EM4Init() and EMU_UnlatchPinRetention() offers
* For platform 2 parts, @ref EMU_EM4Init() and @ref EMU_UnlatchPinRetention() offers
* more pin retention features. This function implements the EM4EXIT retention
* mode on platform 2.
*
@ -615,18 +689,15 @@ __STATIC_INLINE uint32_t GPIO_EM4GetPinWakeupCause(void)
*****************************************************************************/
__STATIC_INLINE void GPIO_EM4SetPinRetention(bool enable)
{
if (enable)
{
#if defined( GPIO_CTRL_EM4RET )
if (enable) {
#if defined(GPIO_CTRL_EM4RET)
GPIO->CTRL |= GPIO_CTRL_EM4RET;
#else
EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK)
| EMU_EM4CTRL_EM4IORETMODE_EM4EXIT;
#endif
}
else
{
#if defined( GPIO_CTRL_EM4RET )
} else {
#if defined(GPIO_CTRL_EM4RET)
GPIO->CTRL &= ~GPIO_CTRL_EM4RET;
#else
EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK)
@ -694,7 +765,7 @@ __STATIC_INLINE void GPIO_IntDisable(uint32_t flags)
*
* @note
* Depending on the use, a pending interrupt may already be set prior to
* enabling the interrupt. Consider using GPIO_IntClear() prior to enabling
* enabling the interrupt. Consider using @ref GPIO_IntClear() prior to enabling
* if such a pending interrupt should be ignored.
*
* @param[in] flags
@ -811,10 +882,10 @@ void GPIO_PinModeSet(GPIO_Port_TypeDef port,
__STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin)
{
EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
#if defined( _GPIO_P_DOUTCLR_MASK )
#if defined(_GPIO_P_DOUTCLR_MASK)
GPIO->P[port].DOUTCLR = 1 << pin;
#else
BUS_RegBitWrite(&GPIO->P[port].DOUT, pin, 0);
BUS_RegMaskedClear(&GPIO->P[port].DOUT, 1 << pin);
#endif
}
@ -856,10 +927,10 @@ __STATIC_INLINE unsigned int GPIO_PinOutGet(GPIO_Port_TypeDef port,
__STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin)
{
EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
#if defined( _GPIO_P_DOUTSET_MASK )
#if defined(_GPIO_P_DOUTSET_MASK)
GPIO->P[port].DOUTSET = 1 << pin;
#else
BUS_RegBitWrite(&GPIO->P[port].DOUT, pin, 1);
BUS_RegMaskedSet(&GPIO->P[port].DOUT, 1 << pin);
#endif
}
@ -917,7 +988,7 @@ __STATIC_INLINE uint32_t GPIO_PortInGet(GPIO_Port_TypeDef port)
__STATIC_INLINE void GPIO_PortOutClear(GPIO_Port_TypeDef port, uint32_t pins)
{
EFM_ASSERT(GPIO_PORT_VALID(port));
#if defined( _GPIO_P_DOUTCLR_MASK )
#if defined(_GPIO_P_DOUTCLR_MASK)
GPIO->P[port].DOUTCLR = pins;
#else
BUS_RegMaskedClear(&GPIO->P[port].DOUT, pins);
@ -959,7 +1030,7 @@ __STATIC_INLINE uint32_t GPIO_PortOutGet(GPIO_Port_TypeDef port)
__STATIC_INLINE void GPIO_PortOutSet(GPIO_Port_TypeDef port, uint32_t pins)
{
EFM_ASSERT(GPIO_PORT_VALID(port));
#if defined( _GPIO_P_DOUTSET_MASK )
#if defined(_GPIO_P_DOUTSET_MASK)
GPIO->P[port].DOUTSET = pins;
#else
BUS_RegMaskedSet(&GPIO->P[port].DOUT, pins);
@ -1067,7 +1138,7 @@ __STATIC_INLINE void GPIO_Unlock(void)
*
* @details
* If reconfiguring a GPIO interrupt that is already enabled, it is generally
* recommended to disable it first, see GPIO_Disable().
* recommended to disable it first, see @ref GPIO_Disable().
*
* The actual GPIO interrupt handler must be in place before enabling the
* interrupt.
@ -1099,7 +1170,7 @@ __STATIC_INLINE void GPIO_Unlock(void)
*
* @param[in] enable
* Set to true if interrupt shall be enabled after configuration completed,
* false to leave disabled. See GPIO_IntDisable() and GPIO_IntEnable().
* false to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable().
******************************************************************************/
__STATIC_INLINE void GPIO_IntConfig(GPIO_Port_TypeDef port,
unsigned int pin,

67
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_i2c.h
* @brief Inter-intergrated circuit (I2C) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -68,15 +68,15 @@ extern "C" {
* @note
* Due to chip characteristics, the max value is somewhat reduced.
*/
#if defined(_SILICON_LABS_32B_SERIES_0) \
&& (defined(_EFM32_GECKO_FAMILY) \
|| defined(_EFM32_TINY_FAMILY) \
|| defined(_EFM32_ZERO_FAMILY) \
|| defined(_EFM32_HAPPY_FAMILY))
#if defined(_SILICON_LABS_32B_SERIES_0) \
&& (defined(_EFM32_GECKO_FAMILY) \
|| defined(_EFM32_TINY_FAMILY) \
|| defined(_EFM32_ZERO_FAMILY) \
|| defined(_EFM32_HAPPY_FAMILY))
#define I2C_FREQ_STANDARD_MAX 93000
#elif defined(_SILICON_LABS_32B_SERIES_0) \
&& (defined(_EFM32_GIANT_FAMILY) \
|| defined(_EFM32_WONDER_FAMILY))
#elif defined(_SILICON_LABS_32B_SERIES_0) \
&& (defined(_EFM32_GIANT_FAMILY) \
|| defined(_EFM32_WONDER_FAMILY))
#define I2C_FREQ_STANDARD_MAX 92000
#elif defined(_SILICON_LABS_32B_SERIES_1)
// None of the chips on this platform has been characterized on this parameter.
@ -98,7 +98,6 @@ extern "C" {
*/
#define I2C_FREQ_FAST_MAX 392157
/**
* @brief
* Fast mode+ max frequency assuming using 11:6 ratio for Nlow:Nhigh.
@ -111,7 +110,6 @@ extern "C" {
*/
#define I2C_FREQ_FASTPLUS_MAX 987167
/**
* @brief
* Indicate plain write sequence: S+ADDR(W)+DATA0+P.
@ -161,23 +159,19 @@ extern "C" {
/** Use 10 bit address. */
#define I2C_FLAG_10BIT_ADDR 0x0010
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** Clock low to high ratio settings. */
typedef enum
{
typedef enum {
i2cClockHLRStandard = _I2C_CTRL_CLHR_STANDARD, /**< Ratio is 4:4 */
i2cClockHLRAsymetric = _I2C_CTRL_CLHR_ASYMMETRIC, /**< Ratio is 6:3 */
i2cClockHLRFast = _I2C_CTRL_CLHR_FAST /**< Ratio is 11:3 */
} I2C_ClockHLR_TypeDef;
/** Return codes for single master mode transfer function. */
typedef enum
{
typedef enum {
/* In progress code (>0) */
i2cTransferInProgress = 1, /**< Transfer in progress. */
@ -192,14 +186,12 @@ typedef enum
i2cTransferSwFault = -5 /**< SW fault. */
} I2C_TransferReturn_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** I2C initialization structure. */
typedef struct
{
typedef struct {
/** Enable I2C peripheral when init completed. */
bool enable;
@ -225,15 +217,14 @@ typedef struct
/** Suggested default config for I2C init structure. */
#define I2C_INIT_DEFAULT \
{ \
true, /* Enable when init done */ \
true, /* Set to master mode */ \
0, /* Use currently configured reference clock */ \
I2C_FREQ_STANDARD_MAX, /* Set to standard rate assuring being */ \
/* within I2C spec */ \
i2cClockHLRStandard /* Set to use 4:4 low/high duty cycle */ \
}
{ \
true, /* Enable when init done */ \
true, /* Set to master mode */ \
0, /* Use currently configured reference clock */ \
I2C_FREQ_STANDARD_MAX, /* Set to standard rate assuring being */ \
/* within I2C spec */ \
i2cClockHLRStandard /* Set to use 4:4 low/high duty cycle */ \
}
/**
* @brief
@ -249,8 +240,7 @@ typedef struct
* @li #I2C_FLAG_WRITE_WRITE - data written from buf[0].data and
* buf[1].data
*/
typedef struct
{
typedef struct {
/**
* @brief
* Address to use after (repeated) start.
@ -268,8 +258,7 @@ typedef struct
* Buffers used to hold data to send from or receive into depending
* on sequence type.
*/
struct
{
struct {
/** Buffer used for data to transmit/receive, must be @p len long. */
uint8_t *data;
@ -284,7 +273,6 @@ typedef struct
} buf[2];
} I2C_TransferSeq_TypeDef;
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
@ -313,7 +301,6 @@ __STATIC_INLINE void I2C_IntClear(I2C_TypeDef *i2c, uint32_t flags)
i2c->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more I2C interrupts.
@ -330,7 +317,6 @@ __STATIC_INLINE void I2C_IntDisable(I2C_TypeDef *i2c, uint32_t flags)
i2c->IEN &= ~(flags);
}
/***************************************************************************//**
* @brief
* Enable one or more I2C interrupts.
@ -352,7 +338,6 @@ __STATIC_INLINE void I2C_IntEnable(I2C_TypeDef *i2c, uint32_t flags)
i2c->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending I2C interrupt flags.
@ -372,7 +357,6 @@ __STATIC_INLINE uint32_t I2C_IntGet(I2C_TypeDef *i2c)
return i2c->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending I2C interrupt flags.
@ -398,7 +382,6 @@ __STATIC_INLINE uint32_t I2C_IntGetEnabled(I2C_TypeDef *i2c)
return i2c->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending I2C interrupts from SW.
@ -439,7 +422,6 @@ __STATIC_INLINE uint8_t I2C_SlaveAddressGet(I2C_TypeDef *i2c)
return ((uint8_t)(i2c->SADDR));
}
/***************************************************************************//**
* @brief
* Set slave address to use for I2C peripheral (when operating in slave mode).
@ -462,7 +444,6 @@ __STATIC_INLINE void I2C_SlaveAddressSet(I2C_TypeDef *i2c, uint8_t addr)
i2c->SADDR = (uint32_t)addr & 0xfe;
}
/***************************************************************************//**
* @brief
* Get slave address mask used for I2C peripheral (when operating in slave
@ -491,7 +472,6 @@ __STATIC_INLINE uint8_t I2C_SlaveAddressMaskGet(I2C_TypeDef *i2c)
return ((uint8_t)(i2c->SADDRMASK));
}
/***************************************************************************//**
* @brief
* Set slave address mask used for I2C peripheral (when operating in slave
@ -520,7 +500,6 @@ __STATIC_INLINE void I2C_SlaveAddressMaskSet(I2C_TypeDef *i2c, uint8_t mask)
i2c->SADDRMASK = (uint32_t)mask & 0xfe;
}
I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c);
I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c,
I2C_TransferSeq_TypeDef *seq);

68
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_idac.h
* @brief Current Digital to Analog Converter (IDAC) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -90,9 +90,8 @@ extern "C" {
******************************************************************************/
/** Output mode. */
typedef enum
{
#if defined( _IDAC_CTRL_OUTMODE_MASK )
typedef enum {
#if defined(_IDAC_CTRL_OUTMODE_MASK)
idacOutputPin = IDAC_CTRL_OUTMODE_PIN, /**< Output to IDAC OUT pin */
idacOutputADC = IDAC_CTRL_OUTMODE_ADC /**< Output to ADC */
#elif ( _IDAC_CTRL_APORTOUTSEL_MASK )
@ -131,20 +130,18 @@ typedef enum
#endif
} IDAC_OutMode_TypeDef;
/** Selects which Peripheral Reflex System (PRS) signal to use when
PRS is set to control the IDAC output. */
typedef enum
{
typedef enum {
idacPRSSELCh0 = IDAC_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
idacPRSSELCh1 = IDAC_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
idacPRSSELCh2 = IDAC_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
idacPRSSELCh3 = IDAC_CTRL_PRSSEL_PRSCH3, /**< PRS channel 3. */
#if defined( IDAC_CTRL_PRSSEL_PRSCH4 )
#if defined(IDAC_CTRL_PRSSEL_PRSCH4)
idacPRSSELCh4 = IDAC_CTRL_PRSSEL_PRSCH4, /**< PRS channel 4. */
idacPRSSELCh5 = IDAC_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */
#endif
#if defined( IDAC_CTRL_PRSSEL_PRSCH6 )
#if defined(IDAC_CTRL_PRSSEL_PRSCH6)
idacPRSSELCh6 = IDAC_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */
idacPRSSELCh7 = IDAC_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7. */
idacPRSSELCh8 = IDAC_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8. */
@ -154,10 +151,8 @@ typedef enum
#endif
} IDAC_PRSSEL_TypeDef;
/** Selects which current range to use. */
typedef enum
{
typedef enum {
idacCurrentRange0 = IDAC_CURPROG_RANGESEL_RANGE0, /**< current range 0. */
idacCurrentRange1 = IDAC_CURPROG_RANGESEL_RANGE1, /**< current range 1. */
idacCurrentRange2 = IDAC_CURPROG_RANGESEL_RANGE2, /**< current range 2. */
@ -169,8 +164,7 @@ typedef enum
******************************************************************************/
/** IDAC init structure, common for both channels. */
typedef struct
{
typedef struct {
/** Enable IDAC. */
bool enable;
@ -192,36 +186,33 @@ typedef struct
/** Enable/disable current sink mode. */
bool sinkEnable;
} IDAC_Init_TypeDef;
/** Default config for IDAC init structure. */
#if defined( _IDAC_CTRL_OUTMODE_MASK )
#if defined(_IDAC_CTRL_OUTMODE_MASK)
#define IDAC_INIT_DEFAULT \
{ \
false, /**< Leave IDAC disabled when init done. */ \
idacOutputPin, /**< Output to IDAC output pin. */ \
false, /**< Disable PRS triggering. */ \
idacPRSSELCh0, /**< Select PRS ch0 (if PRS triggering enabled). */ \
false /**< Disable current sink mode. */ \
}
#elif ( _IDAC_CTRL_APORTOUTSEL_MASK )
{ \
false, /**< Leave IDAC disabled when init done. */ \
idacOutputPin, /**< Output to IDAC output pin. */ \
false, /**< Disable PRS triggering. */ \
idacPRSSELCh0, /**< Select PRS ch0 (if PRS triggering enabled). */ \
false /**< Disable current sink mode. */ \
}
#elif (_IDAC_CTRL_APORTOUTSEL_MASK)
#define IDAC_INIT_DEFAULT \
{ \
false, /**< Leave IDAC disabled when init done. */ \
idacOutputAPORT1XCH0, /**< Output to APORT. */ \
false, /**< Disable PRS triggering. */ \
idacPRSSELCh0, /**< Select PRS ch0 (if PRS triggering enabled). */ \
false /**< Disable current sink mode. */ \
}
{ \
false, /**< Leave IDAC disabled when init done. */ \
idacOutputAPORT1XCH0, /**< Output to APORT. */ \
false, /**< Disable PRS triggering. */ \
idacPRSSELCh0, /**< Select PRS ch0 (if PRS triggering enabled). */ \
false /**< Disable current sink mode. */ \
}
#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
void IDAC_Init(IDAC_TypeDef *idac, const IDAC_Init_TypeDef *init);
void IDAC_Enable(IDAC_TypeDef *idac, bool enable);
void IDAC_Reset(IDAC_TypeDef *idac);
@ -230,8 +221,7 @@ void IDAC_RangeSet(IDAC_TypeDef *idac, const IDAC_Range_TypeDef range);
void IDAC_StepSet(IDAC_TypeDef *idac, const uint32_t step);
void IDAC_OutEnable(IDAC_TypeDef *idac, bool enable);
#if defined( _IDAC_IEN_MASK )
#if defined(_IDAC_IEN_MASK)
/***************************************************************************//**
* @brief
* Clear one or more pending IDAC interrupts.
@ -248,7 +238,6 @@ __STATIC_INLINE void IDAC_IntClear(IDAC_TypeDef *idac, uint32_t flags)
idac->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more IDAC interrupts.
@ -265,7 +254,6 @@ __STATIC_INLINE void IDAC_IntDisable(IDAC_TypeDef *idac, uint32_t flags)
idac->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more IDAC interrupts.
@ -287,7 +275,6 @@ __STATIC_INLINE void IDAC_IntEnable(IDAC_TypeDef *idac, uint32_t flags)
idac->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending IDAC interrupt flags.
@ -307,7 +294,6 @@ __STATIC_INLINE uint32_t IDAC_IntGet(IDAC_TypeDef *idac)
return idac->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending IDAC interrupt flags.
@ -339,7 +325,6 @@ __STATIC_INLINE uint32_t IDAC_IntGetEnabled(IDAC_TypeDef *idac)
return idac->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending IDAC interrupts from SW.
@ -357,7 +342,6 @@ __STATIC_INLINE void IDAC_IntSet(IDAC_TypeDef *idac, uint32_t flags)
}
#endif
/** @} (end addtogroup IDAC) */
/** @} (end addtogroup emlib) */

132
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h
View File

@ -1,132 +0,0 @@
/***************************************************************************//**
* @file em_int.h
* @brief Interrupt enable/disable unit API
* @version 5.1.2
*******************************************************************************
* @section License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
* obligation to support this Software. Silicon Labs is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Silicon Labs will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#ifndef EM_INT_H
#define EM_INT_H
#include "em_device.h"
extern uint32_t INT_LockCnt;
#ifdef __cplusplus
extern "C" {
#endif
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
#ifndef UINT32_MAX
#define UINT32_MAX ((uint32_t)(0xFFFFFFFF))
#endif
#warning "The INT module is deprecated and marked for removal in a later release. Please use the new CORE module instead. See \"Porting from em_int\" in the CORE documentation for instructions."
/** @endcond */
/***************************************************************************//**
* @addtogroup emlib
* @{
******************************************************************************/
/***************************************************************************//**
* @addtogroup INT
* @{
******************************************************************************/
/***************************************************************************//**
* @brief
* Disable interrupts.
*
* @deprecated
* This function is deprecated and marked for removal in a later release.
* Please use the new CORE module instead.
*
* @details
* Disable interrupts and increment lock level counter.
*
* @return
* The resulting interrupt disable nesting level.
*
******************************************************************************/
__STATIC_INLINE uint32_t INT_Disable(void)
{
__disable_irq();
if (INT_LockCnt < UINT32_MAX)
{
INT_LockCnt++;
}
return INT_LockCnt;
}
/***************************************************************************//**
* @brief
* Enable interrupts.
*
* @deprecated
* This function is deprecated and marked for removal in a later release.
* Please use the new CORE module instead.
*
* @return
* The resulting interrupt disable nesting level.
*
* @details
* Decrement interrupt lock level counter and enable interrupts if counter
* reached zero.
*
******************************************************************************/
__STATIC_INLINE uint32_t INT_Enable(void)
{
uint32_t retVal;
if (INT_LockCnt > 0)
{
INT_LockCnt--;
retVal = INT_LockCnt;
if (retVal == 0)
{
__enable_irq();
}
return retVal;
}
else
{
return 0;
}
}
/** @} (end addtogroup INT) */
/** @} (end addtogroup emlib) */
#ifdef __cplusplus
}
#endif
#endif /* EM_INT_H */

208
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_lcd.h
* @brief Liquid Crystal Display (LCD) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -53,13 +53,19 @@ extern "C" {
* @{
******************************************************************************/
/*******************************************************************************
******************************** DEFINES **********************************
******************************************************************************/
#define LCD_DEFAULT_FRAME_RATE_DIV 4
#define LCD_DEFAULT_CONTRAST 15
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** MUX setting */
typedef enum
{
typedef enum {
/** Static (segments can be multiplexed with LCD_COM[0]) */
lcdMuxStatic = LCD_DISPCTRL_MUX_STATIC,
/** Duplex / 1/2 Duty cycle (segments can be multiplexed with LCD_COM[0:1]) */
@ -73,12 +79,24 @@ typedef enum
lcdMuxSextaplex = LCD_DISPCTRL_MUXE_MUXE | LCD_DISPCTRL_MUX_DUPLEX,
/** Octaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]) */
lcdMuxOctaplex = LCD_DISPCTRL_MUXE_MUXE | LCD_DISPCTRL_MUX_QUADRUPLEX
#elif defined(LCD_DISPCTRL_MUX_SEXTAPLEX)
/** Sextaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]) */
lcdMuxSextaplex = LCD_DISPCTRL_MUX_SEXTAPLEX,
/** Octaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]) */
lcdMuxOctaplex = LCD_DISPCTRL_MUX_OCTAPLEX,
#endif
} LCD_Mux_TypeDef;
/** Wave type */
typedef enum {
/** Low power optimized waveform output */
lcdWaveLowPower = LCD_DISPCTRL_WAVE_LOWPOWER,
/** Regular waveform output */
lcdWaveNormal = LCD_DISPCTRL_WAVE_NORMAL
} LCD_Wave_TypeDef;
/** Bias setting */
typedef enum
{
typedef enum {
/** Static (2 levels) */
lcdBiasStatic = LCD_DISPCTRL_BIAS_STATIC,
/** 1/2 Bias (3 levels) */
@ -91,36 +109,29 @@ typedef enum
#endif
} LCD_Bias_TypeDef;
/** Wave type */
typedef enum
{
/** Low power optimized waveform output */
lcdWaveLowPower = LCD_DISPCTRL_WAVE_LOWPOWER,
/** Regular waveform output */
lcdWaveNormal = LCD_DISPCTRL_WAVE_NORMAL
} LCD_Wave_TypeDef;
#if defined(_SILICON_LABS_32B_SERIES_0)
/** VLCD Voltage Source */
typedef enum
{
typedef enum {
/** VLCD Powered by VDD */
lcdVLCDSelVDD = LCD_DISPCTRL_VLCDSEL_VDD,
/** VLCD Powered by external VDD / Voltage Boost */
lcdVLCDSelVExtBoost = LCD_DISPCTRL_VLCDSEL_VEXTBOOST
} LCD_VLCDSel_TypeDef;
#endif
/** Contrast Configuration */
typedef enum
{
#if defined(_SILICON_LABS_32B_SERIES_0)
typedef enum {
/** Contrast is adjusted relative to VDD (VLCD) */
lcdConConfVLCD = LCD_DISPCTRL_CONCONF_VLCD,
/** Contrast is adjusted relative to Ground */
lcdConConfGND = LCD_DISPCTRL_CONCONF_GND
} LCD_ConConf_TypeDef;
#endif
#if defined(_SILICON_LABS_32B_SERIES_0)
/** Voltage Boost Level - Datasheets document setting for each part number */
typedef enum
{
typedef enum {
lcdVBoostLevel0 = LCD_DISPCTRL_VBLEV_LEVEL0, /**< Voltage boost LEVEL0 */
lcdVBoostLevel1 = LCD_DISPCTRL_VBLEV_LEVEL1, /**< Voltage boost LEVEL1 */
lcdVBoostLevel2 = LCD_DISPCTRL_VBLEV_LEVEL2, /**< Voltage boost LEVEL2 */
@ -130,10 +141,19 @@ typedef enum
lcdVBoostLevel6 = LCD_DISPCTRL_VBLEV_LEVEL6, /**< Voltage boost LEVEL6 */
lcdVBoostLevel7 = LCD_DISPCTRL_VBLEV_LEVEL7 /**< Voltage boost LEVEL7 */
} LCD_VBoostLevel_TypeDef;
#endif
#if defined(_SILICON_LABS_32B_SERIES_1)
/** Mode */
typedef enum {
lcdModeNoExtCap = LCD_DISPCTRL_MODE_NOEXTCAP, /**< No external capacitor */
lcdModeStepDown = LCD_DISPCTRL_MODE_STEPDOWN, /**< External cap with resistor string */
lcdModeCpIntOsc = LCD_DISPCTRL_MODE_CPINTOSC, /**< External cap and internal oscillator */
} LCD_Mode_Typedef;
#endif
/** Frame Counter Clock Prescaler, FC-CLK = FrameRate (Hz) / this factor */
typedef enum
{
typedef enum {
/** Prescale Div 1 */
lcdFCPrescDiv1 = LCD_BACTRL_FCPRESC_DIV1,
/** Prescale Div 2 */
@ -144,9 +164,9 @@ typedef enum
lcdFCPrescDiv8 = LCD_BACTRL_FCPRESC_DIV8
} LCD_FCPreScale_TypeDef;
#if defined(_SILICON_LABS_32B_SERIES_0)
/** Segment selection */
typedef enum
{
typedef enum {
/** Select segment lines 0 to 3 */
lcdSegment0_3 = (1 << 0),
/** Select segment lines 4 to 7 */
@ -175,10 +195,10 @@ typedef enum
lcdSegmentAll = (0x03ff)
#endif
} LCD_SegmentRange_TypeDef;
#endif
/** Update Data Control */
typedef enum
{
typedef enum {
/** Regular update, data transfer done immediately */
lcdUpdateCtrlRegular = LCD_CTRL_UDCTRL_REGULAR,
/** Data transfer done at Frame Counter event */
@ -188,8 +208,7 @@ typedef enum
} LCD_UpdateCtrl_TypeDef;
/** Animation Shift operation; none, left or right */
typedef enum
{
typedef enum {
/** No shift */
lcdAnimShiftNone = _LCD_BACTRL_AREGASC_NOSHIFT,
/** Shift segment bits left */
@ -199,22 +218,19 @@ typedef enum
} LCD_AnimShift_TypeDef;
/** Animation Logic Control, how AReg and BReg should be combined */
typedef enum
{
typedef enum {
/** Use bitwise logic AND to mix animation register A (AREGA) and B (AREGB) */
lcdAnimLogicAnd = LCD_BACTRL_ALOGSEL_AND,
/** Use bitwise logic OR to mix animation register A (AREGA) and B (AREGB) */
lcdAnimLogicOr = LCD_BACTRL_ALOGSEL_OR
} LCD_AnimLogic_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** LCD Animation Configuration */
typedef struct
{
typedef struct {
/** Enable Animation at end of initialization */
bool enable;
/** Initial Animation Register A Value */
@ -234,8 +250,7 @@ typedef struct
} LCD_AnimInit_TypeDef;
/** LCD Frame Control Initialization */
typedef struct
{
typedef struct {
/** Enable at end */
bool enable;
/** Frame Counter top value */
@ -245,8 +260,7 @@ typedef struct
} LCD_FrameCountInit_TypeDef;
/** LCD Controller Initialization structure */
typedef struct
{
typedef struct {
/** Enable controller at end of initialization */
bool enable;
/** Mux configuration */
@ -255,46 +269,81 @@ typedef struct
LCD_Bias_TypeDef bias;
/** Wave configuration */
LCD_Wave_TypeDef wave;
#if defined(_SILICON_LABS_32B_SERIES_0)
/** VLCD Select */
LCD_VLCDSel_TypeDef vlcd;
/** Contrast Configuration */
LCD_ConConf_TypeDef contrast;
#endif
#if defined(_SILICON_LABS_32B_SERIES_1)
/** Mode */
LCD_Mode_Typedef mode;
uint8_t chgrDst;
uint8_t frameRateDivider;
int contrastLevel;
#endif
} LCD_Init_TypeDef;
/** Default config for LCD init structure, enables 160 segments */
#if defined(_SILICON_LABS_32B_SERIES_0)
#define LCD_INIT_DEFAULT \
{ \
true, \
lcdMuxQuadruplex, \
lcdBiasOneThird, \
lcdWaveLowPower, \
lcdVLCDSelVDD, \
lcdConConfVLCD \
}
{ \
true, \
lcdMuxQuadruplex, \
lcdBiasOneThird, \
lcdWaveLowPower, \
lcdVLCDSelVDD, \
lcdConConfVLCD, \
}
#endif
#if defined(_SILICON_LABS_32B_SERIES_1)
#define LCD_INIT_DEFAULT \
{ \
true, \
lcdMuxQuadruplex, \
lcdBiasOneThird, \
lcdWaveLowPower, \
lcdModeNoExtCap, \
0, \
LCD_DEFAULT_FRAME_RATE_DIV, \
LCD_DEFAULT_CONTRAST \
}
#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
void LCD_Init(const LCD_Init_TypeDef *lcdInit);
#if defined(_SILICON_LABS_32B_SERIES_0)
void LCD_VLCDSelect(LCD_VLCDSel_TypeDef vlcd);
#endif
void LCD_UpdateCtrl(LCD_UpdateCtrl_TypeDef ud);
void LCD_FrameCountInit(const LCD_FrameCountInit_TypeDef *fcInit);
void LCD_AnimInit(const LCD_AnimInit_TypeDef *animInit);
#if defined(_SILICON_LABS_32B_SERIES_0)
void LCD_SegmentRangeEnable(LCD_SegmentRange_TypeDef segment, bool enable);
#endif
void LCD_SegmentSet(int com, int bit, bool enable);
void LCD_SegmentSetLow(int com, uint32_t mask, uint32_t bits);
#if defined(_LCD_SEGD0H_MASK)
void LCD_SegmentSetHigh(int com, uint32_t mask, uint32_t bits);
#endif
void LCD_ContrastSet(int level);
void LCD_BiasSet(LCD_Bias_TypeDef bias);
#if defined(_SILICON_LABS_32B_SERIES_0)
void LCD_VBoostSet(LCD_VBoostLevel_TypeDef vboost);
#endif
#if defined(LCD_CTRL_DSC)
void LCD_BiasSegmentSet(int segment, int biasLevel);
void LCD_BiasComSet(int com, int biasLevel);
#endif
#if defined(_SILICON_LABS_32B_SERIES_1)
void LCD_ModeSet(LCD_Mode_Typedef mode);
void LCD_ChargeRedistributionCyclesSet(uint8_t cycles);
#endif
/***************************************************************************//**
* @brief
@ -307,17 +356,13 @@ void LCD_BiasComSet(int com, int biasLevel);
******************************************************************************/
__STATIC_INLINE void LCD_Enable(bool enable)
{
if (enable)
{
if (enable) {
LCD->CTRL |= LCD_CTRL_EN;
}
else
{
} else {
LCD->CTRL &= ~LCD_CTRL_EN;
}
}
/***************************************************************************//**
* @brief
* Enables or disables LCD Animation feature
@ -327,17 +372,13 @@ __STATIC_INLINE void LCD_Enable(bool enable)
******************************************************************************/
__STATIC_INLINE void LCD_AnimEnable(bool enable)
{
if (enable)
{
if (enable) {
LCD->BACTRL |= LCD_BACTRL_AEN;
}
else
{
} else {
LCD->BACTRL &= ~LCD_BACTRL_AEN;
}
}
/***************************************************************************//**
* @brief
* Enables or disables LCD blink
@ -347,17 +388,13 @@ __STATIC_INLINE void LCD_AnimEnable(bool enable)
******************************************************************************/
__STATIC_INLINE void LCD_BlinkEnable(bool enable)
{
if (enable)
{
if (enable) {
LCD->BACTRL |= LCD_BACTRL_BLINKEN;
}
else
{
} else {
LCD->BACTRL &= ~LCD_BACTRL_BLINKEN;
}
}
/***************************************************************************//**
* @brief
* Disables all segments, while keeping segment state
@ -367,17 +404,13 @@ __STATIC_INLINE void LCD_BlinkEnable(bool enable)
******************************************************************************/
__STATIC_INLINE void LCD_BlankEnable(bool enable)
{
if (enable)
{
if (enable) {
LCD->BACTRL |= LCD_BACTRL_BLANK;
}
else
{
} else {
LCD->BACTRL &= ~LCD_BACTRL_BLANK;
}
}
/***************************************************************************//**
* @brief
* Enables or disables LCD Frame Control
@ -387,17 +420,13 @@ __STATIC_INLINE void LCD_BlankEnable(bool enable)
******************************************************************************/
__STATIC_INLINE void LCD_FrameCountEnable(bool enable)
{
if (enable)
{
if (enable) {
LCD->BACTRL |= LCD_BACTRL_FCEN;
}
else
{
} else {
LCD->BACTRL &= ~LCD_BACTRL_FCEN;
}
}
/***************************************************************************//**
* @brief
* Returns current animation state
@ -410,7 +439,6 @@ __STATIC_INLINE int LCD_AnimState(void)
return (int)(LCD->STATUS & _LCD_STATUS_ASTATE_MASK) >> _LCD_STATUS_ASTATE_SHIFT;
}
/***************************************************************************//**
* @brief
* Returns current blink state
@ -423,7 +451,6 @@ __STATIC_INLINE int LCD_BlinkState(void)
return (int)(LCD->STATUS & _LCD_STATUS_BLINK_MASK) >> _LCD_STATUS_BLINK_SHIFT;
}
/***************************************************************************//**
* @brief
* When set, LCD registers will not be updated until cleared,
@ -434,17 +461,13 @@ __STATIC_INLINE int LCD_BlinkState(void)
******************************************************************************/
__STATIC_INLINE void LCD_FreezeEnable(bool enable)
{
if (enable)
{
if (enable) {
LCD->FREEZE = LCD_FREEZE_REGFREEZE_FREEZE;
}
else
{
} else {
LCD->FREEZE = LCD_FREEZE_REGFREEZE_UPDATE;
}
}
/***************************************************************************//**
* @brief
* Returns SYNCBUSY bits, indicating which registers have pending updates
@ -457,7 +480,6 @@ __STATIC_INLINE uint32_t LCD_SyncBusyGet(void)
return LCD->SYNCBUSY;
}
/***************************************************************************//**
* @brief
* Polls LCD SYNCBUSY flags, until flag has been cleared
@ -471,7 +493,6 @@ __STATIC_INLINE void LCD_SyncBusyDelay(uint32_t flags)
;
}
/***************************************************************************//**
* @brief
* Get pending LCD interrupt flags
@ -485,7 +506,6 @@ __STATIC_INLINE uint32_t LCD_IntGet(void)
return LCD->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending LCD interrupt flags.
@ -516,7 +536,6 @@ __STATIC_INLINE uint32_t LCD_IntGetEnabled(void)
return LCD->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending LCD interrupts from SW.
@ -531,7 +550,6 @@ __STATIC_INLINE void LCD_IntSet(uint32_t flags)
LCD->IFS = flags;
}
/***************************************************************************//**
* @brief
* Enable LCD interrupts
@ -546,7 +564,6 @@ __STATIC_INLINE void LCD_IntEnable(uint32_t flags)
LCD->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Disable LCD interrupts
@ -561,7 +578,6 @@ __STATIC_INLINE void LCD_IntDisable(uint32_t flags)
LCD->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Clear one or more interrupt flags
@ -576,7 +592,6 @@ __STATIC_INLINE void LCD_IntClear(uint32_t flags)
LCD->IFC = flags;
}
#if defined(LCD_CTRL_DSC)
/***************************************************************************//**
* @brief
@ -589,12 +604,9 @@ __STATIC_INLINE void LCD_IntClear(uint32_t flags)
******************************************************************************/
__STATIC_INLINE void LCD_DSCEnable(bool enable)
{
if (enable)
{
if (enable) {
LCD->CTRL |= LCD_CTRL_DSC;
}
else
{
} else {
LCD->CTRL &= ~LCD_CTRL_DSC;
}
}

1336
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ldma.h
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File diff suppressed because it is too large Load Diff

711
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h
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File diff suppressed because it is too large Load Diff

73
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h
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@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_letimer.h
* @brief Low Energy Timer (LETIMER) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -56,8 +56,7 @@ extern "C" {
******************************************************************************/
/** Repeat mode. */
typedef enum
{
typedef enum {
/** Count until stopped by SW. */
letimerRepeatFree = _LETIMER_CTRL_REPMODE_FREE,
/** Count REP0 times. */
@ -74,10 +73,8 @@ typedef enum
letimerRepeatDouble = _LETIMER_CTRL_REPMODE_DOUBLE
} LETIMER_RepeatMode_TypeDef;
/** Underflow action on output. */
typedef enum
{
typedef enum {
/** No output action. */
letimerUFOANone = _LETIMER_CTRL_UFOA0_NONE,
/** Toggle output when counter underflows. */
@ -93,8 +90,7 @@ typedef enum
******************************************************************************/
/** LETIMER initialization structure. */
typedef struct
{
typedef struct {
bool enable; /**< Start counting when init completed. */
bool debugRun; /**< Counter shall keep running during debug halt. */
#if defined(LETIMER_CTRL_RTCC0TEN)
@ -113,32 +109,32 @@ typedef struct
/** Default config for LETIMER init structure. */
#if defined(LETIMER_CTRL_RTCC0TEN)
#define LETIMER_INIT_DEFAULT \
{ \
true, /* Enable timer when init complete. */ \
false, /* Stop counter during debug halt. */ \
false, /* Do not start counting on RTC COMP0 match. */ \
false, /* Do not start counting on RTC COMP1 match. */ \
false, /* Do not load COMP0 into CNT on underflow. */ \
false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \
0, /* Idle value 0 for output 0. */ \
0, /* Idle value 0 for output 1. */ \
letimerUFOANone, /* No action on underflow on output 0. */ \
letimerUFOANone, /* No action on underflow on output 1. */ \
letimerRepeatFree /* Count until stopped by SW. */ \
}
{ \
true, /* Enable timer when init complete. */ \
false, /* Stop counter during debug halt. */ \
false, /* Do not start counting on RTC COMP0 match. */ \
false, /* Do not start counting on RTC COMP1 match. */ \
false, /* Do not load COMP0 into CNT on underflow. */ \
false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \
0, /* Idle value 0 for output 0. */ \
0, /* Idle value 0 for output 1. */ \
letimerUFOANone, /* No action on underflow on output 0. */ \
letimerUFOANone, /* No action on underflow on output 1. */ \
letimerRepeatFree /* Count until stopped by SW. */ \
}
#else
#define LETIMER_INIT_DEFAULT \
{ \
true, /* Enable timer when init complete. */ \
false, /* Stop counter during debug halt. */ \
false, /* Do not load COMP0 into CNT on underflow. */ \
false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \
0, /* Idle value 0 for output 0. */ \
0, /* Idle value 0 for output 1. */ \
letimerUFOANone, /* No action on underflow on output 0. */ \
letimerUFOANone, /* No action on underflow on output 1. */ \
letimerRepeatFree /* Count until stopped by SW. */ \
}
{ \
true, /* Enable timer when init complete. */ \
false, /* Stop counter during debug halt. */ \
false, /* Do not load COMP0 into CNT on underflow. */ \
false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \
0, /* Idle value 0 for output 0. */ \
0, /* Idle value 0 for output 1. */ \
letimerUFOANone, /* No action on underflow on output 0. */ \
letimerUFOANone, /* No action on underflow on output 1. */ \
letimerRepeatFree /* Count until stopped by SW. */ \
}
#endif
/*******************************************************************************
@ -150,7 +146,6 @@ void LETIMER_CompareSet(LETIMER_TypeDef *letimer,
unsigned int comp,
uint32_t value);
/***************************************************************************//**
* @brief
* Get LETIMER counter value.
@ -166,14 +161,12 @@ __STATIC_INLINE uint32_t LETIMER_CounterGet(LETIMER_TypeDef *letimer)
return(letimer->CNT);
}
void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable);
#if defined(_LETIMER_FREEZE_MASK)
void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable);
#endif
void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init);
/***************************************************************************//**
* @brief
* Clear one or more pending LETIMER interrupts.
@ -191,7 +184,6 @@ __STATIC_INLINE void LETIMER_IntClear(LETIMER_TypeDef *letimer, uint32_t flags)
letimer->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more LETIMER interrupts.
@ -208,7 +200,6 @@ __STATIC_INLINE void LETIMER_IntDisable(LETIMER_TypeDef *letimer, uint32_t flags
letimer->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more LETIMER interrupts.
@ -230,7 +221,6 @@ __STATIC_INLINE void LETIMER_IntEnable(LETIMER_TypeDef *letimer, uint32_t flags)
letimer->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending LETIMER interrupt flags.
@ -250,7 +240,6 @@ __STATIC_INLINE uint32_t LETIMER_IntGet(LETIMER_TypeDef *letimer)
return letimer->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending LETIMER interrupt flags.
@ -276,7 +265,6 @@ __STATIC_INLINE uint32_t LETIMER_IntGetEnabled(LETIMER_TypeDef *letimer)
{
uint32_t ien;
/* Store flags in temporary variable in order to define explicit order
* of volatile accesses. */
ien = letimer->IEN;
@ -285,7 +273,6 @@ __STATIC_INLINE uint32_t LETIMER_IntGetEnabled(LETIMER_TypeDef *letimer)
return letimer->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending LETIMER interrupts from SW.
@ -302,14 +289,12 @@ __STATIC_INLINE void LETIMER_IntSet(LETIMER_TypeDef *letimer, uint32_t flags)
letimer->IFS = flags;
}
uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep);
void LETIMER_RepeatSet(LETIMER_TypeDef *letimer,
unsigned int rep,
uint32_t value);
void LETIMER_Reset(LETIMER_TypeDef *letimer);
/** @} (end addtogroup LETIMER) */
/** @} (end addtogroup emlib) */

49
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h
View File

@ -2,9 +2,9 @@
* @file em_leuart.h
* @brief Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
* peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -58,16 +58,13 @@ extern "C" {
******************************************************************************/
/** Databit selection. */
typedef enum
{
typedef enum {
leuartDatabits8 = LEUART_CTRL_DATABITS_EIGHT, /**< 8 databits. */
leuartDatabits9 = LEUART_CTRL_DATABITS_NINE /**< 9 databits. */
} LEUART_Databits_TypeDef;
/** Enable selection. */
typedef enum
{
typedef enum {
/** Disable both receiver and transmitter. */
leuartDisable = 0x0,
@ -81,31 +78,25 @@ typedef enum
leuartEnable = (LEUART_CMD_RXEN | LEUART_CMD_TXEN)
} LEUART_Enable_TypeDef;
/** Parity selection. */
typedef enum
{
typedef enum {
leuartNoParity = LEUART_CTRL_PARITY_NONE, /**< No parity. */
leuartEvenParity = LEUART_CTRL_PARITY_EVEN, /**< Even parity. */
leuartOddParity = LEUART_CTRL_PARITY_ODD /**< Odd parity. */
} LEUART_Parity_TypeDef;
/** Stopbits selection. */
typedef enum
{
typedef enum {
leuartStopbits1 = LEUART_CTRL_STOPBITS_ONE, /**< 1 stopbits. */
leuartStopbits2 = LEUART_CTRL_STOPBITS_TWO /**< 2 stopbits. */
} LEUART_Stopbits_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** Init structure. */
typedef struct
{
typedef struct {
/** Specifies whether TX and/or RX shall be enabled when init completed. */
LEUART_Enable_TypeDef enable;
@ -130,15 +121,14 @@ typedef struct
/** Default config for LEUART init structure. */
#define LEUART_INIT_DEFAULT \
{ \
leuartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
9600, /* 9600 bits/s. */ \
leuartDatabits8, /* 8 databits. */ \
leuartNoParity, /* No parity. */ \
leuartStopbits1 /* 1 stopbit. */ \
}
{ \
leuartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
9600, /* 9600 bits/s. */ \
leuartDatabits8, /* 8 databits. */ \
leuartNoParity, /* No parity. */ \
leuartStopbits1 /* 1 stopbit. */ \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************
@ -171,7 +161,6 @@ __STATIC_INLINE void LEUART_IntClear(LEUART_TypeDef *leuart, uint32_t flags)
leuart->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more LEUART interrupts.
@ -188,7 +177,6 @@ __STATIC_INLINE void LEUART_IntDisable(LEUART_TypeDef *leuart, uint32_t flags)
leuart->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more LEUART interrupts.
@ -210,7 +198,6 @@ __STATIC_INLINE void LEUART_IntEnable(LEUART_TypeDef *leuart, uint32_t flags)
leuart->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending LEUART interrupt flags.
@ -230,7 +217,6 @@ __STATIC_INLINE uint32_t LEUART_IntGet(LEUART_TypeDef *leuart)
return leuart->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending LEUART interrupt flags.
@ -262,7 +248,6 @@ __STATIC_INLINE uint32_t LEUART_IntGetEnabled(LEUART_TypeDef *leuart)
return leuart->IF & tmp;
}
/***************************************************************************//**
* @brief
* Set one or more pending LEUART interrupts from SW.
@ -279,7 +264,6 @@ __STATIC_INLINE void LEUART_IntSet(LEUART_TypeDef *leuart, uint32_t flags)
leuart->IFS = flags;
}
/***************************************************************************//**
* @brief
* Get LEUART STATUS register.
@ -302,7 +286,6 @@ uint16_t LEUART_RxExt(LEUART_TypeDef *leuart);
void LEUART_Tx(LEUART_TypeDef *leuart, uint8_t data);
void LEUART_TxExt(LEUART_TypeDef *leuart, uint16_t data);
/***************************************************************************//**
* @brief
* Receive one 8 bit frame, (or part of a 9 bit frame).
@ -336,7 +319,6 @@ __STATIC_INLINE uint8_t LEUART_RxDataGet(LEUART_TypeDef *leuart)
return (uint8_t)leuart->RXDATA;
}
/***************************************************************************//**
* @brief
* Receive one 8-9 bit frame, with extended information.
@ -370,7 +352,6 @@ __STATIC_INLINE uint16_t LEUART_RxDataXGet(LEUART_TypeDef *leuart)
return (uint16_t)leuart->RXDATAX;
}
/** @} (end addtogroup LEUART) */
/** @} (end addtogroup emlib) */

111
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_mpu.h
* @brief Memory protection unit (MPU) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -71,8 +71,7 @@ extern "C" {
/**
* Size of an MPU region.
*/
typedef enum
{
typedef enum {
mpuRegionSize32b = 4, /**< 32 byte region size. */
mpuRegionSize64b = 5, /**< 64 byte region size. */
mpuRegionSize128b = 6, /**< 128 byte region size. */
@ -106,8 +105,7 @@ typedef enum
/**
* MPU region access permission attributes.
*/
typedef enum
{
typedef enum {
mpuRegionNoAccess = 0, /**< No access what so ever. */
mpuRegionApPRw = 1, /**< Priviledged state R/W only. */
mpuRegionApPRwURo = 2, /**< Priviledged state R/W, User state R only. */
@ -116,19 +114,17 @@ typedef enum
mpuRegionApPRo_URo = 6 /**< R only in Priviledged and User state. */
} MPU_RegionAp_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** MPU Region init structure. */
typedef struct
{
typedef struct {
bool regionEnable; /**< MPU region enable. */
uint8_t regionNo; /**< MPU region number. */
uint32_t baseAddress; /**< Region baseaddress. */
MPU_RegionSize_TypeDef size; /**< Memory region size. */
MPU_RegionAp_TypeDef accessPermission; /**< Memory access permissions. */
MPU_RegionAp_TypeDef accessPermission; /**< Memory access permissions. */
bool disableExec; /**< Disable execution. */
bool shareable; /**< Memory shareable attribute. */
bool cacheable; /**< Memory cacheable attribute. */
@ -138,64 +134,59 @@ typedef struct
} MPU_RegionInit_TypeDef;
/** Default configuration of MPU region init structure for flash memory. */
#define MPU_INIT_FLASH_DEFAULT \
{ \
true, /* Enable MPU region. */ \
0, /* MPU Region number. */ \
FLASH_MEM_BASE, /* Flash base address. */ \
mpuRegionSize1Mb, /* Size - Set to max. */ \
mpuRegionApFullAccess, /* Access permissions. */ \
false, /* Execution allowed. */ \
false, /* Not shareable. */ \
true, /* Cacheable. */ \
false, /* Not bufferable. */ \
0, /* No subregions. */ \
0 /* No TEX attributes. */ \
}
#define MPU_INIT_FLASH_DEFAULT \
{ \
true, /* Enable MPU region. */ \
0, /* MPU Region number. */ \
FLASH_MEM_BASE, /* Flash base address. */ \
mpuRegionSize1Mb, /* Size - Set to max. */ \
mpuRegionApFullAccess, /* Access permissions. */ \
false, /* Execution allowed. */ \
false, /* Not shareable. */ \
true, /* Cacheable. */ \
false, /* Not bufferable. */ \
0, /* No subregions. */ \
0 /* No TEX attributes. */ \
}
/** Default configuration of MPU region init structure for sram memory. */
#define MPU_INIT_SRAM_DEFAULT \
{ \
true, /* Enable MPU region. */ \
1, /* MPU Region number. */ \
RAM_MEM_BASE, /* SRAM base address. */ \
mpuRegionSize128Kb, /* Size - Set to max. */ \
mpuRegionApFullAccess, /* Access permissions. */ \
false, /* Execution allowed. */ \
true, /* Shareable. */ \
true, /* Cacheable. */ \
false, /* Not bufferable. */ \
0, /* No subregions. */ \
0 /* No TEX attributes. */ \
}
#define MPU_INIT_SRAM_DEFAULT \
{ \
true, /* Enable MPU region. */ \
1, /* MPU Region number. */ \
RAM_MEM_BASE, /* SRAM base address. */ \
mpuRegionSize128Kb, /* Size - Set to max. */ \
mpuRegionApFullAccess, /* Access permissions. */ \
false, /* Execution allowed. */ \
true, /* Shareable. */ \
true, /* Cacheable. */ \
false, /* Not bufferable. */ \
0, /* No subregions. */ \
0 /* No TEX attributes. */ \
}
/** Default configuration of MPU region init structure for onchip peripherals.*/
#define MPU_INIT_PERIPHERAL_DEFAULT \
{ \
true, /* Enable MPU region. */ \
0, /* MPU Region number. */ \
0, /* Region base address. */ \
mpuRegionSize32b, /* Size - Set to minimum */ \
mpuRegionApFullAccess, /* Access permissions. */ \
true, /* Execution not allowed. */ \
true, /* Shareable. */ \
false, /* Not cacheable. */ \
true, /* Bufferable. */ \
0, /* No subregions. */ \
0 /* No TEX attributes. */ \
}
#define MPU_INIT_PERIPHERAL_DEFAULT \
{ \
true, /* Enable MPU region. */ \
0, /* MPU Region number. */ \
0, /* Region base address. */ \
mpuRegionSize32b, /* Size - Set to minimum */ \
mpuRegionApFullAccess, /* Access permissions. */ \
true, /* Execution not allowed. */ \
true, /* Shareable. */ \
false, /* Not cacheable. */ \
true, /* Bufferable. */ \
0, /* No subregions. */ \
0 /* No TEX attributes. */ \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
void MPU_ConfigureRegion(const MPU_RegionInit_TypeDef *init);
/***************************************************************************//**
* @brief
* Disable the MPU
@ -204,11 +195,12 @@ void MPU_ConfigureRegion(const MPU_RegionInit_TypeDef *init);
******************************************************************************/
__STATIC_INLINE void MPU_Disable(void)
{
#if defined(SCB_SHCSR_MEMFAULTENA_Msk)
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; /* Disable fault exceptions */
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; /* Disable the MPU */
}
/***************************************************************************//**
* @brief
* Enable the MPU
@ -225,10 +217,11 @@ __STATIC_INLINE void MPU_Enable(uint32_t flags)
| MPU_CTRL_ENABLE_Msk)));
MPU->CTRL = flags | MPU_CTRL_ENABLE_Msk; /* Enable the MPU */
#if defined(SCB_SHCSR_MEMFAULTENA_Msk)
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; /* Enable fault exceptions */
#endif
}
/** @} (end addtogroup MPU) */
/** @} (end addtogroup emlib) */

94
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_msc.h
* @brief Flash controller (MSC) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -130,8 +130,7 @@ extern "C" {
******************************************************************************/
/** Return codes for writing/erasing the flash */
typedef enum
{
typedef enum {
mscReturnOk = 0, /**< Flash write/erase successful. */
mscReturnInvalidAddr = -1, /**< Invalid address. Write to an address that is not flash. */
mscReturnLocked = -2, /**< Flash address is locked. */
@ -139,11 +138,9 @@ typedef enum
mscReturnUnaligned = -4 /**< Unaligned access to flash. */
} MSC_Status_TypeDef;
#if defined( _MSC_READCTRL_BUSSTRATEGY_MASK )
#if defined(_MSC_READCTRL_BUSSTRATEGY_MASK)
/** Strategy for prioritized bus access */
typedef enum
{
typedef enum {
mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU, /**< Prioritize CPU bus accesses */
mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA, /**< Prioritize DMA bus accesses */
mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1, /**< Prioritize DMAEM1 for bus accesses */
@ -152,8 +149,7 @@ typedef enum
#endif
/** Code execution configuration */
typedef struct
{
typedef struct {
bool scbtEn; /**< Enable Suppressed Conditional Branch Target Prefetch */
bool prefetchEn; /**< Enable MSC prefetching */
bool ifcDis; /**< Disable instruction cache */
@ -163,15 +159,15 @@ typedef struct
} MSC_ExecConfig_TypeDef;
/** Default MSC ExecConfig initialization */
#define MSC_EXECCONFIG_DEFAULT \
{ \
false, \
true, \
false, \
false, \
false, \
false, \
}
#define MSC_EXECCONFIG_DEFAULT \
{ \
false, \
true, \
false, \
false, \
false, \
false, \
}
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/* Deprecated type names */
@ -179,7 +175,6 @@ typedef struct
#define msc_Return_TypeDef MSC_Status_TypeDef
/** @endcond */
/***************************************************************************//**
* @brief
* Clear one or more pending MSC interrupts.
@ -206,7 +201,6 @@ __STATIC_INLINE void MSC_IntDisable(uint32_t flags)
MSC->IEN &= ~(flags);
}
/***************************************************************************//**
* @brief
* Enable one or more MSC interrupts.
@ -225,7 +219,6 @@ __STATIC_INLINE void MSC_IntEnable(uint32_t flags)
MSC->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending MSC interrupt flags.
@ -242,7 +235,6 @@ __STATIC_INLINE uint32_t MSC_IntGet(void)
return(MSC->IF);
}
/***************************************************************************//**
* @brief
* Get enabled and pending MSC interrupt flags.
@ -265,7 +257,6 @@ __STATIC_INLINE uint32_t MSC_IntGetEnabled(void)
return MSC->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending MSC interrupts from SW.
@ -279,8 +270,7 @@ __STATIC_INLINE void MSC_IntSet(uint32_t flags)
MSC->IFS = flags;
}
#if defined( MSC_IF_CHOF ) && defined( MSC_IF_CMOF )
#if defined(MSC_IF_CHOF) && defined(MSC_IF_CMOF)
/***************************************************************************//**
* @brief
* Starts measuring cache hit ratio.
@ -294,14 +284,13 @@ __STATIC_INLINE void MSC_StartCacheMeasurement(void)
MSC->IFC = MSC_IF_CHOF | MSC_IF_CMOF;
/* Start performance counters */
#if defined( _MSC_CACHECMD_MASK )
#if defined(_MSC_CACHECMD_MASK)
MSC->CACHECMD = MSC_CACHECMD_STARTPC;
#else
MSC->CMD = MSC_CMD_STARTPC;
#endif
}
/***************************************************************************//**
* @brief
* Stops measuring the hit rate.
@ -321,13 +310,11 @@ __STATIC_INLINE void MSC_StartCacheMeasurement(void)
* {
* uint32_t flags;
* flags = MSC->IF;
* if (flags & MSC_IF_CHOF)
* {
* if (flags & MSC_IF_CHOF) {
* MSC->IFC = MSC_IF_CHOF;
* hitOverflows++;
* }
* if (flags & MSC_IF_CMOF)
* {
* if (flags & MSC_IF_CMOF) {
* MSC->IFC = MSC_IF_CMOF;
* missOverflows++;
* }
@ -354,15 +341,14 @@ __STATIC_INLINE int32_t MSC_GetCacheMeasurement(void)
int32_t total;
int32_t hits;
/* Stop the counter before computing the hit-rate */
#if defined( _MSC_CACHECMD_MASK )
#if defined(_MSC_CACHECMD_MASK)
MSC->CACHECMD = MSC_CACHECMD_STOPPC;
#else
MSC->CMD = MSC_CMD_STOPPC;
#endif
/* Check for overflows in performance counters */
if (MSC->IF & (MSC_IF_CHOF | MSC_IF_CMOF))
{
if (MSC->IF & (MSC_IF_CHOF | MSC_IF_CMOF)) {
return -2;
}
@ -370,29 +356,26 @@ __STATIC_INLINE int32_t MSC_GetCacheMeasurement(void)
total = MSC->CACHEMISSES + hits;
/* To avoid a division by zero. */
if (total == 0)
{
if (total == 0) {
return -1;
}
return (hits * 100) / total;
}
/***************************************************************************//**
* @brief
* Flush the contents of the instruction cache.
******************************************************************************/
__STATIC_INLINE void MSC_FlushCache(void)
{
#if defined( _MSC_CACHECMD_MASK )
#if defined(_MSC_CACHECMD_MASK)
MSC->CACHECMD = MSC_CACHECMD_INVCACHE;
#else
MSC->CMD = MSC_CMD_INVCACHE;
#endif
}
/***************************************************************************//**
* @brief
* Enable or disable instruction cache functionality
@ -404,8 +387,7 @@ __STATIC_INLINE void MSC_EnableCache(bool enable)
BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, !enable);
}
#if defined( MSC_READCTRL_ICCDIS )
#if defined(MSC_READCTRL_ICCDIS)
/***************************************************************************//**
* @brief
* Enable or disable instruction cache functionality in IRQs
@ -418,7 +400,6 @@ __STATIC_INLINE void MSC_EnableCacheIRQs(bool enable)
}
#endif
/***************************************************************************//**
* @brief
* Enable or disable instruction cache flushing when writing to flash
@ -431,8 +412,7 @@ __STATIC_INLINE void MSC_EnableAutoCacheFlush(bool enable)
}
#endif /* defined( MSC_IF_CHOF ) && defined( MSC_IF_CMOF ) */
#if defined( _MSC_READCTRL_BUSSTRATEGY_MASK )
#if defined(_MSC_READCTRL_BUSSTRATEGY_MASK)
/***************************************************************************//**
* @brief
* Configure which unit should get priority on system bus.
@ -445,7 +425,6 @@ __STATIC_INLINE void MSC_BusStrategy(mscBusStrategy_Typedef mode)
}
#endif
/*******************************************************************************
************************* PROTOTYPES **************************************
******************************************************************************/
@ -468,24 +447,25 @@ void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig);
#endif
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef
MSC_WriteWord(uint32_t *address,
void const *data,
uint32_t numBytes);
MSC_WriteWord(uint32_t *address,
void const *data,
uint32_t numBytes);
#if !defined( _EFM32_GECKO_FAMILY )
#if !defined(_EFM32_GECKO_FAMILY)
#if !defined (EM_MSC_RUN_FROM_FLASH) || (_SILICON_LABS_GECKO_INTERNAL_SDID < 84)
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef
MSC_WriteWordFast(uint32_t *address,
void const *data,
uint32_t numBytes);
MSC_WriteWordFast(uint32_t *address,
void const *data,
uint32_t numBytes);
#endif
#endif
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef
MSC_ErasePage(uint32_t *startAddress);
MSC_ErasePage(uint32_t *startAddress);
#if defined( _MSC_MASSLOCK_MASK )
#if defined(_MSC_MASSLOCK_MASK)
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef
MSC_MassErase(void);
MSC_MassErase(void);
#endif
/** @} (end addtogroup MSC) */

1560
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h
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112
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h
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@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_pcnt.h
* @brief Pulse Counter (PCNT) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -72,14 +72,12 @@ extern "C" {
#define PCNT2_CNT_SIZE (8) /* PCNT2 counter is 8 bits. */
#endif
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** Mode selection. */
typedef enum
{
typedef enum {
/** Disable pulse counter. */
pcntModeDisable = _PCNT_CTRL_MODE_DISABLE,
@ -104,13 +102,11 @@ typedef enum
#endif
} PCNT_Mode_TypeDef;
#if defined(_PCNT_CTRL_CNTEV_MASK)
/** Counter event selection.
* Note: unshifted values are being used for enumeration because multiple
* configuration structure members use this type definition. */
typedef enum
{
typedef enum {
/** Counts up on up-count and down on down-count events. */
pcntCntEventBoth = _PCNT_CTRL_CNTEV_BOTH,
@ -125,11 +121,9 @@ typedef enum
} PCNT_CntEvent_TypeDef;
#endif
#if defined(_PCNT_INPUT_MASK)
/** PRS sources for @p s0PRS and @p s1PRS. */
typedef enum
{
typedef enum {
pcntPRSCh0 = 0, /**< PRS channel 0. */
pcntPRSCh1 = 1, /**< PRS channel 1. */
pcntPRSCh2 = 2, /**< PRS channel 2. */
@ -160,23 +154,19 @@ typedef enum
#endif
} PCNT_PRSSel_TypeDef;
/** PRS inputs of PCNT. */
typedef enum
{
typedef enum {
pcntPRSInputS0 = 0, /** PRS input 0. */
pcntPRSInputS1 = 1 /** PRS input 1. */
} PCNT_PRSInput_TypeDef;
#endif
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** Init structure. */
typedef struct
{
typedef struct {
/** Mode to operate in. */
PCNT_Mode_TypeDef mode;
@ -235,37 +225,36 @@ typedef struct
#if !defined(PCNT_CTRL_HYST)
/** Default config for PCNT init structure. */
#define PCNT_INIT_DEFAULT \
{ \
pcntModeDisable, /* Disabled by default. */ \
_PCNT_CNT_RESETVALUE, /* Default counter HW reset value. */ \
_PCNT_TOP_RESETVALUE, /* Default counter HW reset value. */ \
false, /* Use positive edge. */ \
false, /* Up-counting. */ \
false /* Filter disabled. */ \
}
{ \
pcntModeDisable, /* Disabled by default. */ \
_PCNT_CNT_RESETVALUE, /* Default counter HW reset value. */ \
_PCNT_TOP_RESETVALUE, /* Default counter HW reset value. */ \
false, /* Use positive edge. */ \
false, /* Up-counting. */ \
false /* Filter disabled. */ \
}
#else
/** Default config for PCNT init structure. */
#define PCNT_INIT_DEFAULT \
{ \
pcntModeDisable, /* Disabled by default. */ \
_PCNT_CNT_RESETVALUE, /* Default counter HW reset value. */ \
_PCNT_TOP_RESETVALUE, /* Default counter HW reset value. */ \
false, /* Use positive edge. */ \
false, /* Up-counting. */ \
false, /* Filter disabled. */ \
false, /* Hysteresis disabled. */ \
true, /* Counter direction is given by CNTDIR. */ \
pcntCntEventUp, /* Regular counter counts up on upcount events. */ \
pcntCntEventNone, /* Auxiliary counter doesn't respond to events. */ \
pcntPRSCh0, /* PRS channel 0 selected as S0IN. */ \
pcntPRSCh0 /* PRS channel 0 selected as S1IN. */ \
}
{ \
pcntModeDisable, /* Disabled by default. */ \
_PCNT_CNT_RESETVALUE, /* Default counter HW reset value. */ \
_PCNT_TOP_RESETVALUE, /* Default counter HW reset value. */ \
false, /* Use positive edge. */ \
false, /* Up-counting. */ \
false, /* Filter disabled. */ \
false, /* Hysteresis disabled. */ \
true, /* Counter direction is given by CNTDIR. */ \
pcntCntEventUp, /* Regular counter counts up on upcount events. */ \
pcntCntEventNone, /* Auxiliary counter doesn't respond to events. */ \
pcntPRSCh0, /* PRS channel 0 selected as S0IN. */ \
pcntPRSCh0 /* PRS channel 0 selected as S1IN. */ \
}
#endif
#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT)
/** Filter initialization structure */
typedef struct
{
typedef struct {
/** Used only in OVSINGLE and OVSQUAD1X-4X modes. To use this, enable the filter through
* setting filter to true during PCNT_Init(). Filter length = (filtLen + 5) LFACLK cycles. */
uint8_t filtLen;
@ -278,18 +267,17 @@ typedef struct
/** Default config for PCNT init structure. */
#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT)
#define PCNT_FILTER_DEFAULT \
{ \
0, /* Default length is 5 LFACLK cycles */ \
false /* No flutter removal */ \
}
#define PCNT_FILTER_DEFAULT \
{ \
0, /* Default length is 5 LFACLK cycles */ \
false /* No flutter removal */ \
}
#endif
#if defined(PCNT_CTRL_TCCMODE_DEFAULT)
/** Modes for Triggered Compare and Clear module */
typedef enum
{
typedef enum {
/** Triggered compare and clear not enabled. */
tccModeDisabled = _PCNT_CTRL_TCCMODE_DISABLED,
@ -301,8 +289,7 @@ typedef enum
} PCNT_TCCMode_TypeDef;
/** Prescaler values for LFA compare and clear events. Only has effect when TCC mode is LFA. */
typedef enum
{
typedef enum {
/** Compare and clear event each LFA cycle. */
tccPrescDiv1 = _PCNT_CTRL_TCCPRESC_DIV1,
@ -317,8 +304,7 @@ typedef enum
} PCNT_TCCPresc_Typedef;
/** Compare modes for TCC module */
typedef enum
{
typedef enum {
/** Compare match if PCNT_CNT is less than, or equal to PCNT_TOP. */
tccCompLTOE = _PCNT_CTRL_TCCCOMP_LTOE,
@ -331,8 +317,7 @@ typedef enum
} PCNT_TCCComp_Typedef;
/** TCC initialization structure */
typedef struct
{
typedef struct {
/** Mode to operate in. */
PCNT_TCCMode_TypeDef mode;
@ -355,15 +340,15 @@ typedef struct
bool prsGateEnable;
} PCNT_TCC_TypeDef;
#define PCNT_TCC_DEFAULT \
{ \
tccModeDisabled, /* Disabled by default */ \
tccPrescDiv1, /* Do not prescale LFA clock in LFA mode */ \
tccCompLTOE, /* Clear when CNT <= TOP */ \
pcntPRSCh0, /* Select PRS channel 0 as input to TCC */ \
false, /* PRS polarity is rising edge, and gate when 1 */ \
false /* Do not gate the PCNT counter input */ \
}
#define PCNT_TCC_DEFAULT \
{ \
tccModeDisabled, /* Disabled by default */ \
tccPrescDiv1, /* Do not prescale LFA clock in LFA mode */ \
tccCompLTOE, /* Clear when CNT <= TOP */ \
pcntPRSCh0, /* Select PRS channel 0 as input to TCC */ \
false, /* PRS polarity is rising edge, and gate when 1 */ \
false /* Do not gate the PCNT counter input */ \
}
#endif
/* defined(PCNT_CTRL_TCCMODE_DEFAULT) */
@ -547,7 +532,6 @@ __STATIC_INLINE uint32_t PCNT_IntGetEnabled(PCNT_TypeDef *pcnt)
{
uint32_t ien;
/* Store pcnt->IEN in temporary variable in order to define explicit order
* of volatile accesses. */
ien = pcnt->IEN;

10
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_prs.h
* @brief Peripheral Reflex System (PRS) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -55,8 +55,7 @@ extern "C" {
******************************************************************************/
/** Edge detection type. */
typedef enum
{
typedef enum {
prsEdgeOff = PRS_CH_CTRL_EDSEL_OFF, /**< Leave signal as is. */
prsEdgePos = PRS_CH_CTRL_EDSEL_POSEDGE, /**< Generate pules on positive edge. */
prsEdgeNeg = PRS_CH_CTRL_EDSEL_NEGEDGE, /**< Generate pules on negative edge. */
@ -88,7 +87,6 @@ __STATIC_INLINE void PRS_LevelSet(uint32_t level, uint32_t mask)
PRS->SWLEVEL = (PRS->SWLEVEL & ~mask) | (level & mask);
}
/***************************************************************************//**
* @brief
* Trigger a high pulse (one HFPERCLK) for one or more channels.
@ -113,7 +111,7 @@ void PRS_SourceSignalSet(unsigned int ch,
uint32_t signal,
PRS_Edge_TypeDef edge);
#if defined( PRS_CH_CTRL_ASYNC )
#if defined(PRS_CH_CTRL_ASYNC)
void PRS_SourceAsyncSignalSet(unsigned int ch,
uint32_t source,
uint32_t signal);

345
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_qspi.h Normal file
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@ -0,0 +1,345 @@
/***************************************************************************//**
* @file em_qspi.h
* @brief QSPI Octal-SPI Flash Controller API
* @version 5.3.3
*******************************************************************************
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
* obligation to support this Software. Silicon Labs is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Silicon Labs will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#ifndef EM_QSPI_H
#define EM_QSPI_H
#include "em_device.h"
#if defined(QSPI_COUNT) && (QSPI_COUNT > 0)
#ifdef __cplusplus
extern "C" {
#endif
#include "em_bus.h"
#include <stdbool.h>
/***************************************************************************//**
* @addtogroup emlib
* @{
******************************************************************************/
/***************************************************************************//**
* @addtogroup QSPI
* @{
******************************************************************************/
/*******************************************************************************
******************************* DEFINES ***********************************
******************************************************************************/
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** Transfer type. */
typedef enum {
/** Single IO mode. DQ0 used for output and DQ1 as input. */
qspiTransferSingle = 0,
/** Dual I/O transfer. DQ0 and DQ1 are used as both inputs and outputs. */
qspiTransferDual = 1,
/** Quad I/O transfer. DQ0, DQ1, DQ2 and DQ3 are used as both inputs and outputs. */
qspiTransferQuad = 2,
/** Octal I/O transfer. DQ[7:0] are used as both inputs and outputs. */
qspiTransferOctal = 3
} QSPI_TransferType_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** QSPI Device Read Instruction Configuration structure. */
typedef struct {
/** Read opcode in non-xip mode. */
uint8_t opCode;
/** Number of dummy read clock cycles. */
uint8_t dummyCycles;
/** Transfer type used for address. */
QSPI_TransferType_TypeDef addrTransfer;
/** Transfer type used for data. */
QSPI_TransferType_TypeDef dataTransfer;
/** Transfer type used for instruction. */
QSPI_TransferType_TypeDef instTransfer;
} QSPI_ReadConfig_TypeDef;
/** Default read configuration structure. */
#define QSPI_READCONFIG_DEFAULT \
{ \
0x03, /* 0x03 is the standard read opcode. */ \
0, /* 0 dummy cycles. */ \
qspiTransferSingle, /* Single I/O mode. */ \
qspiTransferSingle, /* Single I/O mode. */ \
qspiTransferSingle, /* Single I/O mode. */ \
}
/** QSPI Device Write Instruction Configuration structure. */
typedef struct {
/** Write opcode. */
uint8_t opCode;
/** Number of dummy read clock cycles. */
uint8_t dummyCycles;
/** Transfer type used for address. */
QSPI_TransferType_TypeDef addrTransfer;
/** Transfer type used for data. */
QSPI_TransferType_TypeDef dataTransfer;
/**
* @brief
* Enable/disable automatic issuing of WEL (Write Enable Latch)
* command before a write operation.
*
* @details
* When writing to a flash device the write enable latch (WEL)
* within the flash device itself must be high before a write sequence can be
* issued. The QSPI peripheral can automatically issue the write enable latch
* command before triggering a write sequence. The command used for enabling
* the write enable latch is WREN (0x06) and is common between devices. */
bool autoWEL;
} QSPI_WriteConfig_TypeDef;
/** Default write configuration structure. */
#define QSPI_WRITECONFIG_DEFAULT \
{ \
0x02, /* 0x02 is the standard write opcode. */ \
0, /* 0 dummy cycles. */ \
qspiTransferSingle, /* Single I/O mode. */ \
qspiTransferSingle, /* Single I/O mode. */ \
true, /* Send WEL command automatically. */ \
}
/** QSPI Device Delay Configuration structure. */
typedef struct {
/** The minimal delay to keep the chip select line de-asserted between
* two transactions. */
uint8_t deassert;
/** Delay between one chip select being de-activated and the
* activation of another. */
uint8_t deviceSwitch;
/** Delay between last bit and chip select de-assert. */
uint8_t lastBit;
/** Delay chip select assert and first bit in a transaction. */
uint8_t firstBit;
} QSPI_DelayConfig_TypeDef;
/** Defines command to be executed using STIG mechanism. */
typedef struct {
/** command op-code */
uint8_t cmdOpcode;
/** Number of Read Data Bytes */
uint16_t readDataSize;
/** Number of Address Bytes */
uint8_t addrSize;
/** Number of Write Data Bytes */
uint8_t writeDataSize;
/** Number of dummy cycles */
uint8_t dummyCycles;
/** Mode Bit Configuration register are sent following the address bytes. */
bool modeBitEnable;
/** flash command address */
uint32_t address;
/** buffer for read data */
void * readBuffer;
/** buffer with data to write */
void * writeBuffer;
} QSPI_StigCmd_TypeDef;
/** QSPI initialization structure. */
typedef struct {
/** Enable/disable Quad SPI when initialization is completed. */
bool enable;
/**
* Master mode baude rate divisor. Values can be even numbers in the range
* [2-32] inclusive. */
uint8_t divisor;
} QSPI_Init_TypeDef;
/** Default configuration for QSPI_Init_TypeDef structure. */
#define QSPI_INIT_DEFAULT \
{ \
true, /* Enable Quad SPI. */ \
32, /* Divide QSPI clock by 32. */ \
}
/*******************************************************************************
****************************** PROTOTYPES *********************************
******************************************************************************/
void QSPI_Init(QSPI_TypeDef * qspi, const QSPI_Init_TypeDef * init);
void QSPI_ReadConfig(QSPI_TypeDef * qspi, const QSPI_ReadConfig_TypeDef * config);
void QSPI_WriteConfig(QSPI_TypeDef * qspi, const QSPI_WriteConfig_TypeDef * config);
void QSPI_ExecStigCmd(QSPI_TypeDef * qspi, const QSPI_StigCmd_TypeDef * stigCmd);
/***************************************************************************//**
* @brief
* Wait for the QSPI to go into idle state.
*
* @param[in] qspi
* Pointer to QSPI peripheral register block.
******************************************************************************/
__STATIC_INLINE void QSPI_WaitForIdle(QSPI_TypeDef * qspi)
{
while ((qspi->CONFIG & _QSPI_CONFIG_IDLE_MASK) == 0)
;
}
/***************************************************************************//**
* @brief
* Get the fill level of the write partition of the QSPI internal SRAM.
*
* @param[in] qspi
* Pointer to QSPI peripheral register block.
*
* @return
* SRAM fill level of the write partition. The value is the number of 4 byte
* words in the write partition.
******************************************************************************/
__STATIC_INLINE uint16_t QSPI_GetWriteLevel(QSPI_TypeDef * qspi)
{
return (qspi->SRAMFILL & _QSPI_SRAMFILL_SRAMFILLINDACWRITE_MASK)
>> _QSPI_SRAMFILL_SRAMFILLINDACWRITE_SHIFT;
}
/***************************************************************************//**
* @brief
* Get the fill level of the read partition of the QSPI internal SRAM.
*
* @param[in] qspi
* Pointer to QSPI peripheral register block.
*
* @return
* SRAM fill level of the read partition. The value is the number of 4 byte
* words in the read partition.
******************************************************************************/
__STATIC_INLINE uint16_t QSPI_GetReadLevel(QSPI_TypeDef * qspi)
{
return (qspi->SRAMFILL & _QSPI_SRAMFILL_SRAMFILLINDACREAD_MASK)
>> _QSPI_SRAMFILL_SRAMFILLINDACREAD_SHIFT;
}
/***************************************************************************//**
* @brief
* Enable/disable Quad SPI.
*
* @param[in] qspi
* Pointer to QSPI peripheral register block.
*
* @param[in] enable
* true to enable quad spi, false to disable quad spi.
******************************************************************************/
__STATIC_INLINE void QSPI_Enable(QSPI_TypeDef * qspi, bool enable)
{
BUS_RegBitWrite(&qspi->CONFIG, _QSPI_CONFIG_ENBSPI_SHIFT, enable ? 1 : 0);
}
/***************************************************************************//**
* @brief
* Get the current interrupt flags.
*
* @param[in] qspi
* Pointer to QSPI peripheral register block.
*
* @return
* This functions returns the current interrupt flags that are set.
******************************************************************************/
__STATIC_INLINE uint32_t QSPI_IntGet(QSPI_TypeDef * qspi)
{
return qspi->IRQSTATUS;
}
/***************************************************************************//**
* @brief
* Clear interrupt flags
*
* @param[in] qspi
* Pointer to QSPI peripheral register block.
*
* @param[in] flags
* The interrupt flags to clear.
******************************************************************************/
__STATIC_INLINE void QSPI_IntClear(QSPI_TypeDef * qspi, uint32_t flags)
{
qspi->IRQSTATUS = flags;
}
/***************************************************************************//**
* @brief
* Enable interrupts.
*
* @param[in] qspi
* Pointer to QSPI peripheral register block.
*
* @param[in] flags
* The interrupt flags to enable.
******************************************************************************/
__STATIC_INLINE void QSPI_IntEnable(QSPI_TypeDef * qspi, uint32_t flags)
{
qspi->IRQMASK = flags & (~_QSPI_IRQMASK_MASK);
}
/***************************************************************************//**
* @brief
* Disable interrupts.
*
* @param[in] qspi
* Pointer to QSPI peripheral register block.
*
* @param[in] flags
* The interrupt flags to disable.
******************************************************************************/
__STATIC_INLINE void QSPI_IntDisable(QSPI_TypeDef * qspi, uint32_t flags)
{
qspi->IRQMASK = ~flags & (~_QSPI_IRQMASK_MASK);
}
/** @} (end addtogroup QSPI) */
/** @} (end addtogroup emlib) */
#ifdef __cplusplus
}
#endif
#endif /* defined(QSPI_COUNT) && (QSPI_COUNT > 0) */
#endif /* EM_QSPI_H */

14
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ramfunc.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_ramfunc.h
* @brief RAM code support.
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -37,6 +37,7 @@
extern "C" {
#endif
/* *INDENT-OFF* */
/***************************************************************************//**
* @addtogroup emlib
* @{
@ -61,6 +62,11 @@ extern "C" {
guarantee no calls to standard libraries with GCC.
Read more at https://gcc.gnu.org/onlinedocs/gcc-5.3.0/gcc/Standards.html
@warning
Keil/ARM uVision users must add a section named "ram_code" in their linker
scatter file. This section must be in RAM memory. Look in the MCU SDK for
example scatter files (ram_code.sct).
@n @section ramfunc_usage Usage
In your .h file:
@ -87,10 +93,10 @@ extern "C" {
SL_RAMFUNC_DEFINITION_END
@endverbatim
******************************************************************************/
/* *INDENT-ON* */
/*******************************************************************************
/*******************************************************************************
****************************** DEFINES ***********************************
******************************************************************************/

10
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_rmu.h
* @brief Reset Management Unit (RMU) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -58,8 +58,7 @@ extern "C" {
******************************************************************************/
/** RMU reset modes */
typedef enum
{
typedef enum {
#if defined(_RMU_CTRL_PINRMODE_MASK)
rmuResetModeDisabled = _RMU_CTRL_PINRMODE_DISABLED,
rmuResetModeLimited = _RMU_CTRL_PINRMODE_LIMITED,
@ -72,8 +71,7 @@ typedef enum
} RMU_ResetMode_TypeDef;
/** RMU controlled peripheral reset control and reset source control */
typedef enum
{
typedef enum {
#if defined(RMU_CTRL_BURSTEN)
rmuResetBU = _RMU_CTRL_BURSTEN_MASK, /**< Reset control over Backup Power domain select */
#endif

25
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_rtc.h
* @brief Real Time Counter (RTC) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -57,8 +57,7 @@ extern "C" {
******************************************************************************/
/** RTC initialization structure. */
typedef struct
{
typedef struct {
bool enable; /**< Start counting when init completed. */
bool debugRun; /**< Counter shall keep running during debug halt. */
bool comp0Top; /**< Use compare register 0 as max count value. */
@ -66,12 +65,11 @@ typedef struct
/** Suggested default config for RTC init structure. */
#define RTC_INIT_DEFAULT \
{ \
true, /* Start counting when init done */ \
false, /* Disable updating during debug halt */ \
true /* Restart counting from 0 when reaching COMP0 */ \
}
{ \
true, /* Start counting when init done */ \
false, /* Disable updating during debug halt */ \
true /* Restart counting from 0 when reaching COMP0 */ \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************
@ -108,7 +106,9 @@ __STATIC_INLINE void RTC_CounterSet(uint32_t value)
void RTC_CounterReset(void);
void RTC_Enable(bool enable);
#if defined(_RTC_FREEZE_MASK)
void RTC_FreezeEnable(bool enable);
#endif
void RTC_Init(const RTC_Init_TypeDef *init);
/***************************************************************************//**
@ -125,7 +125,6 @@ __STATIC_INLINE void RTC_IntClear(uint32_t flags)
RTC->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more RTC interrupts.
@ -140,7 +139,6 @@ __STATIC_INLINE void RTC_IntDisable(uint32_t flags)
RTC->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more RTC interrupts.
@ -160,7 +158,6 @@ __STATIC_INLINE void RTC_IntEnable(uint32_t flags)
RTC->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending RTC interrupt flags.
@ -177,7 +174,6 @@ __STATIC_INLINE uint32_t RTC_IntGet(void)
return RTC->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending RTC interrupt flags.
@ -200,7 +196,6 @@ __STATIC_INLINE uint32_t RTC_IntGetEnabled(void)
return RTC->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending RTC interrupts from SW.

260
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtcc.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file
* @brief Real Time Counter (RTCC) peripheral API.
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -34,7 +34,7 @@
#define EM_RTCC_H
#include "em_device.h"
#if defined( RTCC_COUNT ) && ( RTCC_COUNT == 1 )
#if defined(RTCC_COUNT) && (RTCC_COUNT == 1)
#include <stdbool.h>
#include "em_assert.h"
@ -54,8 +54,8 @@ extern "C" {
******************************************************************************/
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \
|| defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \
|| defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
/* Enable fix for errata "RTCC_E203 - Potential Stability Issue with RTCC
* Registers". */
#define ERRATA_FIX_RTCC_E203
@ -73,19 +73,17 @@ extern "C" {
******************************************************************************/
/** Operational mode of the counter. */
typedef enum
{
typedef enum {
/** Normal counter mode. The counter is incremented by 1 for each tick. */
rtccCntModeNormal = _RTCC_CTRL_CNTTICK_PRESC,
rtccCntModeNormal = _RTCC_CTRL_CNTMODE_NORMAL,
/** Calendar mode. Refer to the RTCC chapter of the Reference Manual for more
* details on the calendar mode. */
rtccCntModeCalendar = _RTCC_CTRL_CNTTICK_CCV0MATCH
rtccCntModeCalendar = _RTCC_CTRL_CNTMODE_CALENDAR
} RTCC_CntMode_TypeDef;
/** Counter prescaler selection. */
typedef enum
{
typedef enum {
rtccCntPresc_1 = _RTCC_CTRL_CNTPRESC_DIV1, /**< Divide clock by 1. */
rtccCntPresc_2 = _RTCC_CTRL_CNTPRESC_DIV2, /**< Divide clock by 2. */
rtccCntPresc_4 = _RTCC_CTRL_CNTPRESC_DIV4, /**< Divide clock by 4. */
@ -104,10 +102,8 @@ typedef enum
rtccCntPresc_32768 = _RTCC_CTRL_CNTPRESC_DIV32768 /**< Divide clock by 32768. */
} RTCC_CntPresc_TypeDef;
/** Prescaler mode of the RTCC counter. */
typedef enum
{
typedef enum {
/** CNT register ticks according to the prescaler value. */
rtccCntTickPresc = _RTCC_CTRL_CNTTICK_PRESC,
@ -116,28 +112,23 @@ typedef enum
rtccCntTickCCV0Match = _RTCC_CTRL_CNTTICK_CCV0MATCH
} RTCC_PrescMode_TypeDef;
/** Capture/Compare channel mode. */
typedef enum
{
typedef enum {
rtccCapComChModeOff = _RTCC_CC_CTRL_MODE_OFF, /**< Capture/Compare channel turned off. */
rtccCapComChModeCapture = _RTCC_CC_CTRL_MODE_INPUTCAPTURE, /**< Capture mode. */
rtccCapComChModeCompare = _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE, /**< Compare mode. */
} RTCC_CapComChMode_TypeDef;
/** Compare match output action mode. */
typedef enum
{
typedef enum {
rtccCompMatchOutActionPulse = _RTCC_CC_CTRL_CMOA_PULSE, /**< Generate a pulse. */
rtccCompMatchOutActionToggle = _RTCC_CC_CTRL_CMOA_TOGGLE, /**< Toggle output. */
rtccCompMatchOutActionClear = _RTCC_CC_CTRL_CMOA_CLEAR, /**< Clear output. */
rtccCompMatchOutActionSet = _RTCC_CC_CTRL_CMOA_SET /**< Set output. */
} RTCC_CompMatchOutAction_TypeDef;
/** PRS input sources. */
typedef enum
{
typedef enum {
rtccPRSCh0 = _RTCC_CC_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
rtccPRSCh1 = _RTCC_CC_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
rtccPRSCh2 = _RTCC_CC_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
@ -146,26 +137,30 @@ typedef enum
rtccPRSCh5 = _RTCC_CC_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */
rtccPRSCh6 = _RTCC_CC_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */
rtccPRSCh7 = _RTCC_CC_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7. */
#if defined(_RTCC_CC_CTRL_PRSSEL_PRSCH8)
rtccPRSCh8 = _RTCC_CC_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8. */
#endif
#if defined(_RTCC_CC_CTRL_PRSSEL_PRSCH9)
rtccPRSCh9 = _RTCC_CC_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9. */
#endif
#if defined(_RTCC_CC_CTRL_PRSSEL_PRSCH10)
rtccPRSCh10 = _RTCC_CC_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10. */
#endif
#if defined(_RTCC_CC_CTRL_PRSSEL_PRSCH11)
rtccPRSCh11 = _RTCC_CC_CTRL_PRSSEL_PRSCH11 /**< PRS channel 11. */
#endif
} RTCC_PRSSel_TypeDef;
/** Input edge select. */
typedef enum
{
typedef enum {
rtccInEdgeRising = _RTCC_CC_CTRL_ICEDGE_RISING, /**< Rising edges detected. */
rtccInEdgeFalling = _RTCC_CC_CTRL_ICEDGE_FALLING, /**< Falling edges detected. */
rtccInEdgeBoth = _RTCC_CC_CTRL_ICEDGE_BOTH, /**< Both edges detected. */
rtccInEdgeNone = _RTCC_CC_CTRL_ICEDGE_NONE /**< No edge detection, signal is left as is. */
} RTCC_InEdgeSel_TypeDef;
/** Capture/Compare channel compare mode. */
typedef enum
{
typedef enum {
/** CCVx is compared with the CNT register. */
rtccCompBaseCnt = _RTCC_CC_CTRL_COMPBASE_CNT,
@ -173,9 +168,8 @@ typedef enum
rtccCompBasePreCnt = _RTCC_CC_CTRL_COMPBASE_PRECNT
} RTCC_CompBase_TypeDef;
/** Day compare mode. */
typedef enum
{
/** Day compare mode. */
typedef enum {
rtccDayCompareModeMonth = _RTCC_CC_CTRL_DAYCC_MONTH, /**< Day of month is selected for Capture/Compare. */
rtccDayCompareModeWeek = _RTCC_CC_CTRL_DAYCC_WEEK /**< Day of week is selected for Capture/Compare. */
} RTCC_DayCompareMode_TypeDef;
@ -185,8 +179,7 @@ typedef enum
******************************************************************************/
/** RTCC initialization structure. */
typedef struct
{
typedef struct {
/** Enable/disable counting when initialization is completed. */
bool enable;
@ -224,10 +217,8 @@ typedef struct
bool disLeapYearCorr;
} RTCC_Init_TypeDef;
/** RTCC capture/compare channel configuration structure. */
typedef struct
{
typedef struct {
/** Select the mode of the Capture/Compare channel. */
RTCC_CapComChMode_TypeDef chMode;
@ -251,7 +242,6 @@ typedef struct
RTCC_DayCompareMode_TypeDef dayCompMode;
} RTCC_CCChConf_TypeDef;
/*******************************************************************************
******************************* DEFINES ***********************************
******************************************************************************/
@ -259,59 +249,59 @@ typedef struct
/** Default RTCC init structure. */
#if defined(_RTCC_CTRL_BUMODETSEN_MASK)
#define RTCC_INIT_DEFAULT \
{ \
true, /* Start counting when init done. */ \
false, /* Disable RTCC during debug halt. */ \
false, /* Disable precounter wrap on ch. 0 CCV value. */ \
false, /* Disable counter wrap on ch. 1 CCV value. */ \
rtccCntPresc_32, /* 977 us per tick. */ \
rtccCntTickPresc, /* Counter increments according to prescaler value. */ \
false, /* No RTCC storage on backup mode entry. */ \
false, /* No RTCC oscillator failure detection. */ \
rtccCntModeNormal, /* Normal RTCC mode. */ \
false, /* No leap year correction. */ \
}
{ \
true, /* Start counting when init done. */ \
false, /* Disable RTCC during debug halt. */ \
false, /* Disable precounter wrap on ch. 0 CCV value. */ \
false, /* Disable counter wrap on ch. 1 CCV value. */ \
rtccCntPresc_32, /* 977 us per tick. */ \
rtccCntTickPresc, /* Counter increments according to prescaler value.*/ \
false, /* No RTCC storage on backup mode entry. */ \
false, /* No RTCC oscillator failure detection. */ \
rtccCntModeNormal, /* Normal RTCC mode. */ \
false, /* No leap year correction. */ \
}
#else
#define RTCC_INIT_DEFAULT \
{ \
true, /* Start counting when init done. */ \
false, /* Disable RTCC during debug halt. */ \
false, /* Disable precounter wrap on ch. 0 CCV value. */ \
false, /* Disable counter wrap on ch. 1 CCV value. */ \
rtccCntPresc_32, /* 977 us per tick. */ \
rtccCntTickPresc, /* Counter increments according to prescaler value. */ \
false, /* No RTCC oscillator failure detection. */ \
rtccCntModeNormal, /* Normal RTCC mode. */ \
false, /* No leap year correction. */ \
}
{ \
true, /* Start counting when init done. */ \
false, /* Disable RTCC during debug halt. */ \
false, /* Disable precounter wrap on ch. 0 CCV value. */ \
false, /* Disable counter wrap on ch. 1 CCV value. */ \
rtccCntPresc_32, /* 977 us per tick. */ \
rtccCntTickPresc, /* Counter increments according to prescaler value.*/ \
false, /* No RTCC oscillator failure detection. */ \
rtccCntModeNormal, /* Normal RTCC mode. */ \
false, /* No leap year correction. */ \
}
#endif
/** Default RTCC channel output compare init structure. */
#define RTCC_CH_INIT_COMPARE_DEFAULT \
{ \
rtccCapComChModeCompare, /* Select output compare mode. */ \
rtccCompMatchOutActionPulse, /* Create pulse on compare match. */ \
rtccPRSCh0, /* PRS channel 0 (not used). */ \
rtccInEdgeNone, /* No edge detection. */ \
rtccCompBaseCnt, /* Counter comparison base. */ \
0, /* No compare mask bits set. */ \
rtccDayCompareModeMonth /* Don't care */ \
}
#define RTCC_CH_INIT_COMPARE_DEFAULT \
{ \
rtccCapComChModeCompare, /* Select output compare mode. */ \
rtccCompMatchOutActionPulse, /* Create pulse on compare match.*/ \
rtccPRSCh0, /* PRS channel 0 (not used). */ \
rtccInEdgeNone, /* No edge detection. */ \
rtccCompBaseCnt, /* Counter comparison base. */ \
0, /* No compare mask bits set. */ \
rtccDayCompareModeMonth /* Don't care */ \
}
/** Default RTCC channel input capture init structure. */
#define RTCC_CH_INIT_CAPTURE_DEFAULT \
{ \
rtccCapComChModeCapture, /* Select input capture mode. */ \
rtccCompMatchOutActionPulse, /* Create pulse on capture. */ \
rtccPRSCh0, /* PRS channel 0. */ \
rtccInEdgeRising, /* Rising edge detection. */ \
rtccCompBaseCnt, /* Don't care. */ \
0, /* Don't care. */ \
rtccDayCompareModeMonth /* Don't care */ \
}
#define RTCC_CH_INIT_CAPTURE_DEFAULT \
{ \
rtccCapComChModeCapture, /* Select input capture mode. */ \
rtccCompMatchOutActionPulse, /* Create pulse on capture. */ \
rtccPRSCh0, /* PRS channel 0. */ \
rtccInEdgeRising, /* Rising edge detection. */ \
rtccCompBaseCnt, /* Don't care. */ \
0, /* Don't care. */ \
rtccDayCompareModeMonth /* Don't care */ \
}
/** Validation of valid RTCC channel for assert statements. */
#define RTCC_CH_VALID( ch ) ( ( ch ) < 3 )
#define RTCC_CH_VALID(ch) ( (ch) < 3)
/*******************************************************************************
***************************** PROTOTYPES **********************************
@ -327,10 +317,10 @@ typedef struct
* @return
* Capture/compare register value.
******************************************************************************/
__STATIC_INLINE uint32_t RTCC_ChannelCCVGet( int ch )
__STATIC_INLINE uint32_t RTCC_ChannelCCVGet(int ch)
{
EFM_ASSERT( RTCC_CH_VALID( ch ) );
return RTCC->CC[ ch ].CCV;
EFM_ASSERT(RTCC_CH_VALID(ch) );
return RTCC->CC[ch].CCV;
}
/***************************************************************************//**
@ -343,10 +333,10 @@ __STATIC_INLINE uint32_t RTCC_ChannelCCVGet( int ch )
* @param[in] value
* CCV value.
******************************************************************************/
__STATIC_INLINE void RTCC_ChannelCCVSet( int ch, uint32_t value )
__STATIC_INLINE void RTCC_ChannelCCVSet(int ch, uint32_t value)
{
EFM_ASSERT( RTCC_CH_VALID( ch ) );
RTCC->CC[ ch ].CCV = value;
EFM_ASSERT(RTCC_CH_VALID(ch) );
RTCC->CC[ch].CCV = value;
}
/***************************************************************************//**
@ -359,10 +349,10 @@ __STATIC_INLINE void RTCC_ChannelCCVSet( int ch, uint32_t value )
* @return
* DATE register value.
******************************************************************************/
__STATIC_INLINE uint32_t RTCC_ChannelDateGet( int ch )
__STATIC_INLINE uint32_t RTCC_ChannelDateGet(int ch)
{
EFM_ASSERT( RTCC_CH_VALID( ch ) );
return RTCC->CC[ ch ].DATE;
EFM_ASSERT(RTCC_CH_VALID(ch) );
return RTCC->CC[ch].DATE;
}
/***************************************************************************//**
@ -375,13 +365,13 @@ __STATIC_INLINE uint32_t RTCC_ChannelDateGet( int ch )
* @param[in] date
* DATE value.
******************************************************************************/
__STATIC_INLINE void RTCC_ChannelDateSet( int ch, uint32_t date )
__STATIC_INLINE void RTCC_ChannelDateSet(int ch, uint32_t date)
{
EFM_ASSERT( RTCC_CH_VALID( ch ) );
RTCC->CC[ ch ].DATE = date;
EFM_ASSERT(RTCC_CH_VALID(ch) );
RTCC->CC[ch].DATE = date;
}
void RTCC_ChannelInit( int ch, RTCC_CCChConf_TypeDef const *confPtr );
void RTCC_ChannelInit(int ch, RTCC_CCChConf_TypeDef const *confPtr);
/***************************************************************************//**
* @brief
@ -393,10 +383,10 @@ void RTCC_ChannelInit( int ch, RTCC_CCChConf_TypeDef const *confPtr );
* @return
* TIME register value.
******************************************************************************/
__STATIC_INLINE uint32_t RTCC_ChannelTimeGet( int ch )
__STATIC_INLINE uint32_t RTCC_ChannelTimeGet(int ch)
{
EFM_ASSERT( RTCC_CH_VALID( ch ) );
return RTCC->CC[ ch ].TIME;
EFM_ASSERT(RTCC_CH_VALID(ch) );
return RTCC->CC[ch].TIME;
}
/***************************************************************************//**
@ -409,10 +399,10 @@ __STATIC_INLINE uint32_t RTCC_ChannelTimeGet( int ch )
* @param[in] time
* TIME value.
******************************************************************************/
__STATIC_INLINE void RTCC_ChannelTimeSet( int ch, uint32_t time )
__STATIC_INLINE void RTCC_ChannelTimeSet(int ch, uint32_t time)
{
EFM_ASSERT( RTCC_CH_VALID( ch ) );
RTCC->CC[ ch ].TIME = time;
EFM_ASSERT(RTCC_CH_VALID(ch) );
RTCC->CC[ch].TIME = time;
}
/***************************************************************************//**
@ -422,7 +412,7 @@ __STATIC_INLINE void RTCC_ChannelTimeSet( int ch, uint32_t time )
* @return
* CNT/PRECNT register value.
******************************************************************************/
__STATIC_INLINE uint32_t RTCC_CombinedCounterGet( void )
__STATIC_INLINE uint32_t RTCC_CombinedCounterGet(void)
{
return RTCC->COMBCNT;
}
@ -434,7 +424,7 @@ __STATIC_INLINE uint32_t RTCC_CombinedCounterGet( void )
* @return
* Current RTCC counter value.
******************************************************************************/
__STATIC_INLINE uint32_t RTCC_CounterGet( void )
__STATIC_INLINE uint32_t RTCC_CounterGet(void)
{
return RTCC->CNT;
}
@ -446,7 +436,7 @@ __STATIC_INLINE uint32_t RTCC_CounterGet( void )
* @param[in] value
* CNT value.
******************************************************************************/
__STATIC_INLINE void RTCC_CounterSet( uint32_t value )
__STATIC_INLINE void RTCC_CounterSet(uint32_t value)
{
RTCC->CNT = value;
}
@ -458,7 +448,7 @@ __STATIC_INLINE void RTCC_CounterSet( uint32_t value )
* @return
* Current DATE register value.
******************************************************************************/
__STATIC_INLINE uint32_t RTCC_DateGet( void )
__STATIC_INLINE uint32_t RTCC_DateGet(void)
{
return RTCC->DATE;
}
@ -470,7 +460,7 @@ __STATIC_INLINE uint32_t RTCC_DateGet( void )
* @param[in] date
* DATE value.
******************************************************************************/
__STATIC_INLINE void RTCC_DateSet( uint32_t date )
__STATIC_INLINE void RTCC_DateSet(uint32_t date)
{
RTCC->DATE = date;
}
@ -482,21 +472,18 @@ __STATIC_INLINE void RTCC_DateSet( uint32_t date )
* @param[in] enable
* True to enable EM4 wakeup, false to disable.
******************************************************************************/
__STATIC_INLINE void RTCC_EM4WakeupEnable( bool enable )
__STATIC_INLINE void RTCC_EM4WakeupEnable(bool enable)
{
if ( enable )
{
if ( enable ) {
RTCC->EM4WUEN = RTCC_EM4WUEN_EM4WU;
}
else
{
} else {
RTCC->EM4WUEN = 0;
}
}
void RTCC_Enable( bool enable );
void RTCC_Enable(bool enable);
void RTCC_Init( const RTCC_Init_TypeDef *init );
void RTCC_Init(const RTCC_Init_TypeDef *init);
/***************************************************************************//**
* @brief
@ -506,7 +493,7 @@ void RTCC_Init( const RTCC_Init_TypeDef *init );
* RTCC interrupt sources to clear. Use a set of interrupt flags OR-ed
* together to clear multiple interrupt sources.
******************************************************************************/
__STATIC_INLINE void RTCC_IntClear( uint32_t flags )
__STATIC_INLINE void RTCC_IntClear(uint32_t flags)
{
RTCC->IFC = flags;
}
@ -519,7 +506,7 @@ __STATIC_INLINE void RTCC_IntClear( uint32_t flags )
* RTCC interrupt sources to disable. Use a set of interrupt flags OR-ed
* together to disable multiple interrupt.
******************************************************************************/
__STATIC_INLINE void RTCC_IntDisable( uint32_t flags )
__STATIC_INLINE void RTCC_IntDisable(uint32_t flags)
{
RTCC->IEN &= ~flags;
}
@ -537,7 +524,7 @@ __STATIC_INLINE void RTCC_IntDisable( uint32_t flags )
* RTCC interrupt sources to enable. Use a set of interrupt flags OR-ed
* together to set multiple interrupt.
******************************************************************************/
__STATIC_INLINE void RTCC_IntEnable( uint32_t flags )
__STATIC_INLINE void RTCC_IntEnable(uint32_t flags)
{
RTCC->IEN |= flags;
}
@ -553,7 +540,7 @@ __STATIC_INLINE void RTCC_IntEnable( uint32_t flags )
* Pending RTCC interrupt sources. Returns a set of interrupt flags OR-ed
* together for the interrupt sources set.
******************************************************************************/
__STATIC_INLINE uint32_t RTCC_IntGet( void )
__STATIC_INLINE uint32_t RTCC_IntGet(void)
{
return RTCC->IF;
}
@ -569,7 +556,7 @@ __STATIC_INLINE uint32_t RTCC_IntGet( void )
* Pending and enabled RTCC interrupt sources. Returns a set of interrupt
* flags OR-ed together for the interrupt sources set.
******************************************************************************/
__STATIC_INLINE uint32_t RTCC_IntGetEnabled( void )
__STATIC_INLINE uint32_t RTCC_IntGetEnabled(void)
{
uint32_t tmp;
@ -587,7 +574,7 @@ __STATIC_INLINE uint32_t RTCC_IntGetEnabled( void )
* RTCC interrupt sources to set to pending. Use a set of interrupt flags
* (RTCC_IFS_nnn).
******************************************************************************/
__STATIC_INLINE void RTCC_IntSet( uint32_t flags )
__STATIC_INLINE void RTCC_IntSet(uint32_t flags)
{
RTCC->IFS = flags;
}
@ -601,15 +588,14 @@ __STATIC_INLINE void RTCC_IntSet( uint32_t flags )
* RTCC_TIME, RTCC_DATE, RTCC_IEN, RTCC_POWERDOWN and RTCC_CCx_XXX registers
* can not be written to.
******************************************************************************/
__STATIC_INLINE void RTCC_Lock( void )
__STATIC_INLINE void RTCC_Lock(void)
{
#if defined(ERRATA_FIX_RTCC_E203)
/* RTCC_E203 - Potential Stability Issue with RTCC Registers
* RTCC_LOCK register must be modified while RTCC clock is disabled. */
uint32_t lfeReg = CMU->LFECLKEN0;
bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED);
if (cmuLocked)
{
if (cmuLocked) {
CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
}
CMU->LFECLKEN0 = 0x0;
@ -618,8 +604,7 @@ __STATIC_INLINE void RTCC_Lock( void )
#if defined(ERRATA_FIX_RTCC_E203)
/* Restore clock state after RTCC_E203 fix. */
CMU->LFECLKEN0 = lfeReg;
if (cmuLocked)
{
if (cmuLocked) {
CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
}
#endif
@ -632,7 +617,7 @@ __STATIC_INLINE void RTCC_Lock( void )
* @return
* Current RTCC pre-counter value.
******************************************************************************/
__STATIC_INLINE uint32_t RTCC_PreCounterGet( void )
__STATIC_INLINE uint32_t RTCC_PreCounterGet(void)
{
return RTCC->PRECNT;
}
@ -644,12 +629,12 @@ __STATIC_INLINE uint32_t RTCC_PreCounterGet( void )
* @param[in] preCntVal
* RTCC pre-counter value to be set.
******************************************************************************/
__STATIC_INLINE void RTCC_PreCounterSet( uint32_t preCntVal )
__STATIC_INLINE void RTCC_PreCounterSet(uint32_t preCntVal)
{
RTCC->PRECNT = preCntVal;
}
void RTCC_Reset( void );
void RTCC_Reset(void);
/***************************************************************************//**
* @brief
@ -658,7 +643,7 @@ void RTCC_Reset( void );
* @note
* Once retention ram is powered down, it cannot be powered up again.
******************************************************************************/
__STATIC_INLINE void RTCC_RetentionRamPowerDown( void )
__STATIC_INLINE void RTCC_RetentionRamPowerDown(void)
{
#if !defined(ERRATA_FIX_RTCC_E204)
/* Devices that are affected by RTCC_E204 should always keep the RTCC
@ -667,7 +652,7 @@ __STATIC_INLINE void RTCC_RetentionRamPowerDown( void )
#endif
}
void RTCC_StatusClear( void );
void RTCC_StatusClear(void);
/***************************************************************************//**
* @brief
@ -676,10 +661,9 @@ void RTCC_StatusClear( void );
* @return
* Current STATUS register value.
******************************************************************************/
__STATIC_INLINE uint32_t RTCC_StatusGet( void )
__STATIC_INLINE uint32_t RTCC_StatusGet(void)
{
while ( RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD )
{
while ( RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD ) {
// Wait for syncronization.
}
return RTCC->STATUS;
@ -692,7 +676,7 @@ __STATIC_INLINE uint32_t RTCC_StatusGet( void )
* @return
* Current TIME register value.
******************************************************************************/
__STATIC_INLINE uint32_t RTCC_TimeGet( void )
__STATIC_INLINE uint32_t RTCC_TimeGet(void)
{
return RTCC->TIME;
}
@ -704,7 +688,7 @@ __STATIC_INLINE uint32_t RTCC_TimeGet( void )
* @param[in] time
* TIME value.
******************************************************************************/
__STATIC_INLINE void RTCC_TimeSet( uint32_t time )
__STATIC_INLINE void RTCC_TimeSet(uint32_t time)
{
RTCC->TIME = time;
}
@ -718,15 +702,14 @@ __STATIC_INLINE void RTCC_TimeSet( uint32_t time )
* RTCC_TIME, RTCC_DATE, RTCC_IEN, RTCC_POWERDOWN and RTCC_CCx_XXX registers
* can not be written to.
******************************************************************************/
__STATIC_INLINE void RTCC_Unlock( void )
__STATIC_INLINE void RTCC_Unlock(void)
{
#if defined(ERRATA_FIX_RTCC_E203)
/* RTCC_E203 - Potential Stability Issue with RTCC Registers
* RTCC_LOCK register must be modified while RTCC clock is disabled. */
uint32_t lfeReg = CMU->LFECLKEN0;
bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED);
if (cmuLocked)
{
if (cmuLocked) {
CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
}
CMU->LFECLKEN0 = 0x0;
@ -735,8 +718,7 @@ __STATIC_INLINE void RTCC_Unlock( void )
#if defined(ERRATA_FIX_RTCC_E203)
/* Restore clock state after RTCC_E203 fix. */
CMU->LFECLKEN0 = lfeReg;
if (cmuLocked)
{
if (cmuLocked) {
CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
}
#endif

329
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_smu.h
* @brief Security Management Unit (SMU) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -77,7 +77,6 @@ extern "C" {
/** SMU peripheral identifiers. */
typedef enum {
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
@ -127,8 +126,12 @@ typedef enum {
smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1 */
#if defined(_SMU_PPUPATD0_CSEN_SHIFT)
smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
#endif
#if defined(_SMU_PPUPATD0_VDAC0_SHIFT)
smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
#endif
smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
@ -136,7 +139,9 @@ typedef enum {
smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
#if defined(_SMU_PPUPATD0_IDAC0_SHIFT)
smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
#endif
smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */
smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
@ -156,6 +161,167 @@ typedef enum {
smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
#if defined(_SMU_PPUPATD0_ACMP0_SHIFT)
smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
#endif
#if defined(_SMU_PPUPATD0_ACMP1_SHIFT)
smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
#endif
smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
smuPeripheralCRYPTO = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
#if defined(_SMU_PPUPATD0_VDAC0_SHIFT)
smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
#endif
smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
#if defined(_SMU_PPUPATD0_IDAC0_SHIFT)
smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
#endif
smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */
smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
#if defined(_SMU_PPUPATD0_LESENSE_SHIFT)
smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
#endif
smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
smuPeripheralLEUART = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
#if defined(_SMU_PPUPATD0_PCNT0_SHIFT)
smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
#endif
smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */
smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100)
smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2 */
smuPeripheralACMP3 = _SMU_PPUPATD0_ACMP3_SHIFT, /**< SMU peripheral identifier for ACMP3 */
smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1 */
smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0 */
smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1 */
smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI */
smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
#if defined(_SMU_PPUPATD0_ETH_SHIFT)
smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH */
#endif
smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
smuPeripheralI2C2 = _SMU_PPUPATD0_I2C2_SHIFT, /**< SMU peripheral identifier for I2C2 */
smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC */
#if defined(_SMU_PPUPATD0_LCD_SHIFT)
smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD */
#endif
smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1 */
smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1 */
smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1 */
smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2 */
#if defined(_SMU_PPUPATD1_QSPI0_SHIFT)
smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0 */
#endif
smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC */
smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
#if defined(_SMU_PPUPATD1_SDIO_SHIFT)
smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO */
#endif
smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */
smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2 */
smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3 */
smuPeripheralTIMER4 = 32 + _SMU_PPUPATD1_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4 */
smuPeripheralTIMER5 = 32 + _SMU_PPUPATD1_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5 */
smuPeripheralTIMER6 = 32 + _SMU_PPUPATD1_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6 */
smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0 */
smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1 */
smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */
smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3 */
smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4 */
smuPeripheralUSART5 = 32 + _SMU_PPUPATD1_USART5_SHIFT, /**< SMU peripheral identifier for USART5 */
#if defined(_SMU_PPUPATD1_USB_SHIFT)
smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB */
#endif
smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1 */
smuPeripheralWTIMER2 = 32 + _SMU_PPUPATD1_WTIMER2_SHIFT, /**< SMU peripheral identifier for WTIMER2 */
smuPeripheralWTIMER3 = 32 + _SMU_PPUPATD1_WTIMER3_SHIFT, /**< SMU peripheral identifier for WTIMER3 */
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0 */
smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC */
#if defined(_SMU_PPUPATD0_LCD_SHIFT)
smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD */
#endif
smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER0 */
smuPeripheralTRNG0 = _SMU_PPUPATD0_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
smuPeripheralUART0 = _SMU_PPUPATD0_UART0_SHIFT, /**< SMU peripheral identifier for UART0 */
smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */
smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3 */
smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1 */
#else
#error "No peripherals defined for SMU for this device configuration."
#endif
@ -164,7 +330,6 @@ typedef enum {
/** SMU peripheral privileged access enablers. */
typedef struct {
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
@ -262,6 +427,154 @@ typedef struct {
bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
bool privilegedACMP0 : 1; /**< Privileged access enabler for */
bool privilegedACMP1 : 1; /**< Privileged access enabler for */
bool privilegedADC0 : 1; /**< Privileged access enabler for */
bool privilegedReserved0 : 1;
bool privilegedReserved1 : 1;
bool privilegedCMU : 1; /**< Privileged access enabler for */
bool privilegedReserved2 : 1;
bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for */
bool privilegedCRYPTO : 1; /**< Privileged access enabler for */
bool privilegedVDAC0 : 1; /**< Privileged access enabler for */
bool privilegedPRS : 1; /**< Privileged access enabler for */
bool privilegedEMU : 1; /**< Privileged access enabler for */
bool privilegedFPUEH : 1; /**< Privileged access enabler for */
bool privilegedReserved3 : 1;
bool privilegedGPCRC : 1; /**< Privileged access enabler for */
bool privilegedGPIO : 1; /**< Privileged access enabler for */
bool privilegedI2C0 : 1; /**< Privileged access enabler for */
bool privilegedIDAC0 : 1; /**< Privileged access enabler for */
bool privilegedMSC : 1; /**< Privileged access enabler for */
bool privilegedLDMA : 1; /**< Privileged access enabler for */
bool privilegedLESENSE : 1; /**< Privileged access enabler for */
bool privilegedLETIMER0 : 1; /**< Privileged access enabler for */
bool privilegedLEUART : 1; /**< Privileged access enabler for */
bool privilegedReserved4 : 1;
bool privilegedPCNT0 : 1; /**< Privileged access enabler for */
bool privilegedReserved5 : 1;
bool privilegedReserved6 : 1;
bool privilegedReserved7 : 1;
bool privilegedReserved8 : 1;
bool privilegedRMU : 1; /**< Privileged access enabler for */
bool privilegedRTCC : 1; /**< Privileged access enabler for */
bool privilegedSMU : 1; /**< Privileged access enabler for */
bool privilegedReserved9 : 1;
bool privilegedTIMER0 : 1; /**< Privileged access enabler for */
bool privilegedTIMER1 : 1; /**< Privileged access enabler for */
bool privilegedTRNG0 : 1; /**< Privileged access enabler for */
bool privilegedUSART0 : 1; /**< Privileged access enabler for */
bool privilegedUSART1 : 1; /**< Privileged access enabler for */
bool privilegedWDOG0 : 1; /**< Privileged access enabler for */
bool privilegedWDOG1 : 1; /**< Privileged access enabler for */
bool privilegedWTIMER0 : 1; /**< Privileged access enabler for */
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100)
bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2 */
bool privilegedACMP3 : 1; /**< Privileged access enabler for ACMP3 */
bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */
bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1 */
bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0 */
bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1 */
bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */
bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */
bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */
bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
bool privilegedPRS : 1; /**< Privileged access enabler for PRS */
bool privilegedEBI : 1; /**< Privileged access enabler for EBI */
bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
bool privilegedETH : 1; /**< Privileged access enabler for ETH */
bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH */
bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2 */
bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0 */
bool privilegedMSC : 1; /**< Privileged access enabler for MAC */
bool privilegedLCD : 1; /**< Privileged access enabler for LCD */
bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1 */
bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */
bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1 */
bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */
bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1 */
bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2 */
bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0 */
bool privilegedRMU : 1; /**< Privileged access enabler for RMU */
bool privilegedRTC : 1; /**< Privileged access enabler for RTC */
bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO */
bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */
bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */
bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */
bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5 */
bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6 */
bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */
bool privilegedUART0 : 1; /**< Privileged access enabler for UART0 */
bool privilegedUART1 : 1; /**< Privileged access enabler for UART1 */
bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */
bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3 */
bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4 */
bool privilegedUSART5 : 1; /**< Privileged access enabler for USART5 */
bool privilegedUSB : 1; /**< Privileged access enabler for USB */
bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1 */
bool privilegedWTIMER2 : 1; /**< Privileged access enabler for WTIMER2 */
bool privilegedWTIMER3 : 1; /**< Privileged access enabler for WTIMER3 */
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */
bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0 */
bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */
bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */
bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */
bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
bool privilegedPRS : 1; /**< Privileged access enabler for PRS */
bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
bool privilegedMSC : 1; /**< Privileged access enabler for MAC */
bool privilegedLCD : 1; /**< Privileged access enabler for LCD */
bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */
bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */
bool privilegedRMU : 1; /**< Privileged access enabler for RMU */
bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */
bool privilegedUART0 : 1; /**< Privileged access enabler for UART0 */
bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */
bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3 */
bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1 */
#else
#error "No peripherals defined for SMU for this device configuration"
#endif
@ -280,13 +593,11 @@ typedef struct {
bool enable; /**< SMU enable flag, when set SMU_Init() will enable SMU.*/
} SMU_Init_TypeDef;
#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID > 80)
/** Default SMU initialization struct settings. */
#define SMU_INIT_DEFAULT { \
{{0}}, /* No peripherals acsess protected. */ \
true /* Enable SMU.*/ \
#define SMU_INIT_DEFAULT { \
{ { 0 } }, /* No peripherals acsess protected. */ \
true /* Enable SMU.*/ \
}
#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************

88
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_system.h
* @brief System API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -61,18 +61,23 @@ extern "C" {
******************************************************************************/
/** Family identifiers. */
typedef enum
{
typedef enum {
/* New style family #defines */
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32G)
systemPartFamilyEfm32Gecko = _DEVINFO_PART_DEVICE_FAMILY_EFM32G, /**< EFM32 Gecko Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG)
systemPartFamilyEfm32Giant = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG, /**< EFM32 Giant Gecko Device Family */
systemPartFamilyEfm32Giant = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG, /**< EFM32 Giant Gecko Series 0 Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B)
systemPartFamilyEfm32Giant11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B, /**< EFM32 Giant Gecko Series 1 Config 1 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG)
systemPartFamilyEfm32Tiny = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG, /**< EFM32 Tiny Gecko Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B)
systemPartFamilyEfm32Tiny11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B, /**< EFM32 Tiny Gecko 11 Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32LG)
systemPartFamilyEfm32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EFM32LG, /**< EFM32 Leopard Gecko Device Family */
#endif
@ -92,16 +97,16 @@ typedef enum
systemPartFamilyEfm32Jade1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B, /**< EFM32 Jade Gecko Series 1 Config 1 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B)
systemPartFamilyEfm32Pearl12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B, /**< EFM32 Pearl Gecko Series 1 Config 2 Basic Device Family */
systemPartFamilyEfm32Pearl12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B, /**< EFM32 Pearl Gecko Series 1 Config 2 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B)
systemPartFamilyEfm32Jade12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B, /**< EFM32 Jade Gecko Series 1 Config 2 Basic Device Family */
systemPartFamilyEfm32Jade12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B, /**< EFM32 Jade Gecko Series 1 Config 2 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B)
systemPartFamilyEfm32Pearl13B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B, /**< EFM32 Pearl Gecko Series 1 Config 3 Basic Device Family */
systemPartFamilyEfm32Pearl13B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B, /**< EFM32 Pearl Gecko Series 1 Config 3 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B)
systemPartFamilyEfm32Jade13B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B, /**< EFM32 Jade Gecko Series 1 Config 3 Basic Device Family */
systemPartFamilyEfm32Jade13B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B, /**< EFM32 Jade Gecko Series 1 Config 3 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32WG)
systemPartFamilyEzr32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EZR32WG, /**< EZR32 Wonder Device Family */
@ -196,8 +201,33 @@ typedef enum
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V)
systemPartFamilyFlex13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V, /**< EFR32 Flex Gecko Series 1 Config 3 Value Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P)
systemPartFamilyMighty14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P, /**< EFR32 Mighty Gecko Series 1 Config 4 Premium Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B)
systemPartFamilyMighty14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B, /**< EFR32 Mighty Gecko Series 1 Config 4 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V)
systemPartFamilyMighty14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V, /**< EFR32 Mighty Gecko Series 1 Config 4 Value Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P)
systemPartFamilyBlue14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P, /**< EFR32 Blue Gecko Series 1 Config 4 Premium Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B)
systemPartFamilyBlue14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B, /**< EFR32 Blue Gecko Series 1 Config 4 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V)
systemPartFamilyBlue14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V, /**< EFR32 Blue Gecko Series 1 Config 4 Value Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P)
systemPartFamilyFlex14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P, /**< EFR32 Flex Gecko Series 1 Config 4 Premium Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B)
systemPartFamilyFlex14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B, /**< EFR32 Flex Gecko Series 1 Config 4 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V)
systemPartFamilyFlex14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V, /**< EFR32 Flex Gecko Series 1 Config 4 Value Device Family */
#endif
/* Deprecated family #defines */
#if defined(_DEVINFO_PART_DEVICE_FAMILY_G)
@ -226,14 +256,12 @@ typedef enum
on unprogrammed parts. */
} SYSTEM_PartFamily_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** Chip revision details */
typedef struct
{
typedef struct {
uint8_t minor; /**< Minor revision number */
uint8_t major; /**< Major revision number */
uint8_t family;/**< Device family number */
@ -241,8 +269,7 @@ typedef struct
#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1)
/** Floating point coprocessor access modes. */
typedef enum
{
typedef enum {
fpuAccessDenied = (0x0 << 20), /**< Access denied, any attempted access generates a NOCP UsageFault. */
fpuAccessPrivilegedOnly = (0x5 << 20), /**< Privileged access only, an unprivileged access generates a NOCP UsageFault. */
fpuAccessReserved = (0xA << 20), /**< Reserved. */
@ -251,8 +278,7 @@ typedef enum
#endif
/** DEVINFO calibration address/value pair */
typedef struct
{
typedef struct {
uint32_t address; /**< Peripheral calibration register address */
uint32_t calValue; /**< Calibration value for register at address */
}
@ -324,14 +350,13 @@ __STATIC_INLINE uint16_t SYSTEM_GetSRAMSize(void)
#if defined(_EFM32_GECKO_FAMILY)
/* Early Gecko devices had a bug where SRAM and Flash size were swapped. */
if (SYSTEM_GetProdRev() < 5)
{
if (SYSTEM_GetProdRev() < 5) {
sizekb = (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK)
>> _DEVINFO_MSIZE_FLASH_SHIFT;
>> _DEVINFO_MSIZE_FLASH_SHIFT;
}
#endif
sizekb = (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK)
>> _DEVINFO_MSIZE_SRAM_SHIFT;
>> _DEVINFO_MSIZE_SRAM_SHIFT;
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE)
/* Do not include EFR32xG1 RAMH */
@ -357,8 +382,7 @@ __STATIC_INLINE uint16_t SYSTEM_GetFlashSize(void)
{
#if defined(_EFM32_GECKO_FAMILY)
/* Early Gecko devices had a bug where SRAM and Flash size were swapped. */
if (SYSTEM_GetProdRev() < 5)
{
if (SYSTEM_GetProdRev() < 5) {
return (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK)
>> _DEVINFO_MSIZE_SRAM_SHIFT;
}
@ -367,7 +391,6 @@ __STATIC_INLINE uint16_t SYSTEM_GetFlashSize(void)
>> _DEVINFO_MSIZE_FLASH_SHIFT;
}
/***************************************************************************//**
* @brief
* Get the flash page size in bytes.
@ -384,18 +407,18 @@ __STATIC_INLINE uint32_t SYSTEM_GetFlashPageSize(void)
{
uint32_t tmp;
#if defined(_SILICON_LABS_32B_SERIES_0)
#if defined(_EFM32_GIANT_FAMILY)
if (SYSTEM_GetProdRev() < 18)
{
if (SYSTEM_GetProdRev() < 18) {
/* Early Giant/Leopard devices did not have MEMINFO in DEVINFO. */
return FLASH_PAGE_SIZE;
}
#elif defined(_EFM32_ZERO_FAMILY)
if (SYSTEM_GetProdRev() < 24)
{
if (SYSTEM_GetProdRev() < 24) {
/* Early Zero devices have an incorrect DEVINFO flash page size */
return FLASH_PAGE_SIZE;
}
#endif
#endif
tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK)
@ -404,8 +427,7 @@ __STATIC_INLINE uint32_t SYSTEM_GetFlashPageSize(void)
return 1 << ((tmp + 10) & 0xFF);
}
#if defined( _DEVINFO_DEVINFOREV_DEVINFOREV_MASK )
#if defined(_DEVINFO_DEVINFOREV_DEVINFOREV_MASK)
/***************************************************************************//**
* @brief
* Get DEVINFO revision.
@ -416,11 +438,10 @@ __STATIC_INLINE uint32_t SYSTEM_GetFlashPageSize(void)
__STATIC_INLINE uint8_t SYSTEM_GetDevinfoRev(void)
{
return (DEVINFO->DEVINFOREV & _DEVINFO_DEVINFOREV_DEVINFOREV_MASK)
>> _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT;
>> _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT;
}
#endif
/***************************************************************************//**
* @brief
* Get part number of the MCU.
@ -455,7 +476,6 @@ __STATIC_INLINE SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void)
>> _DEVINFO_PART_DEVICE_FAMILY_SHIFT);
}
/***************************************************************************//**
* @brief
* Get the calibration temperature (in degrees Celsius).

236
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_timer.h
* @brief Timer/counter (TIMER) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -78,18 +78,15 @@ extern "C" {
******************************************************************************/
/** Timer compare/capture mode. */
typedef enum
{
typedef enum {
timerCCModeOff = _TIMER_CC_CTRL_MODE_OFF, /**< Channel turned off. */
timerCCModeCapture = _TIMER_CC_CTRL_MODE_INPUTCAPTURE, /**< Input capture. */
timerCCModeCompare = _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE, /**< Output compare. */
timerCCModePWM = _TIMER_CC_CTRL_MODE_PWM /**< Pulse-Width modulation. */
} TIMER_CCMode_TypeDef;
/** Clock select. */
typedef enum
{
typedef enum {
/** Prescaled HFPER clock. */
timerClkSelHFPerClk = _TIMER_CTRL_CLKSEL_PRESCHFPERCLK,
@ -103,10 +100,8 @@ typedef enum
timerClkSelCascade = _TIMER_CTRL_CLKSEL_TIMEROUF
} TIMER_ClkSel_TypeDef;
/** Input capture edge select. */
typedef enum
{
typedef enum {
/** Rising edges detected. */
timerEdgeRising = _TIMER_CC_CTRL_ICEDGE_RISING,
@ -120,10 +115,8 @@ typedef enum
timerEdgeNone = _TIMER_CC_CTRL_ICEDGE_NONE
} TIMER_Edge_TypeDef;
/** Input capture event control. */
typedef enum
{
typedef enum {
/** PRS output pulse, interrupt flag and DMA request set on every capture. */
timerEventEveryEdge = _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE,
/** PRS output pulse, interrupt flag and DMA request set on every second capture. */
@ -140,10 +133,8 @@ typedef enum
timerEventFalling = _TIMER_CC_CTRL_ICEVCTRL_FALLING
} TIMER_Event_TypeDef;
/** Input edge action. */
typedef enum
{
typedef enum {
/** No action taken. */
timerInputActionNone = _TIMER_CTRL_FALLA_NONE,
@ -157,20 +148,16 @@ typedef enum
timerInputActionReloadStart = _TIMER_CTRL_FALLA_RELOADSTART
} TIMER_InputAction_TypeDef;
/** Timer mode. */
typedef enum
{
typedef enum {
timerModeUp = _TIMER_CTRL_MODE_UP, /**< Up-counting. */
timerModeDown = _TIMER_CTRL_MODE_DOWN, /**< Down-counting. */
timerModeUpDown = _TIMER_CTRL_MODE_UPDOWN, /**< Up/down-counting. */
timerModeQDec = _TIMER_CTRL_MODE_QDEC /**< Quadrature decoder. */
} TIMER_Mode_TypeDef;
/** Compare/capture output action. */
typedef enum
{
typedef enum {
/** No action. */
timerOutputActionNone = _TIMER_CC_CTRL_CUFOA_NONE,
@ -184,10 +171,8 @@ typedef enum
timerOutputActionSet = _TIMER_CC_CTRL_CUFOA_SET
} TIMER_OutputAction_TypeDef;
/** Prescaler. */
typedef enum
{
typedef enum {
timerPrescale1 = _TIMER_CTRL_PRESC_DIV1, /**< Divide by 1. */
timerPrescale2 = _TIMER_CTRL_PRESC_DIV2, /**< Divide by 2. */
timerPrescale4 = _TIMER_CTRL_PRESC_DIV4, /**< Divide by 4. */
@ -201,10 +186,8 @@ typedef enum
timerPrescale1024 = _TIMER_CTRL_PRESC_DIV1024 /**< Divide by 1024. */
} TIMER_Prescale_TypeDef;
/** Peripheral Reflex System signal. */
typedef enum
{
typedef enum {
timerPRSSELCh0 = _TIMER_CC_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
timerPRSSELCh1 = _TIMER_CC_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
timerPRSSELCh2 = _TIMER_CC_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
@ -237,8 +220,7 @@ typedef enum
#if defined(_TIMER_DTFC_DTFA_NONE)
/** DT (Dead Time) Fault Actions. */
typedef enum
{
typedef enum {
timerDtiFaultActionNone = _TIMER_DTFC_DTFA_NONE, /**< No action on fault. */
timerDtiFaultActionInactive = _TIMER_DTFC_DTFA_INACTIVE, /**< Set outputs inactive. */
timerDtiFaultActionClear = _TIMER_DTFC_DTFA_CLEAR, /**< Clear outputs. */
@ -251,8 +233,7 @@ typedef enum
******************************************************************************/
/** TIMER initialization structure. */
typedef struct
{
typedef struct {
/** Start counting when init completed. */
bool enable;
@ -299,41 +280,40 @@ typedef struct
/** Default config for TIMER init structure. */
#if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI)
#define TIMER_INIT_DEFAULT \
{ \
true, /* Enable timer when init complete. */ \
false, /* Stop counter during debug halt. */ \
timerPrescale1, /* No prescaling. */ \
timerClkSelHFPerClk, /* Select HFPER clock. */ \
false, /* Not 2x count mode. */ \
false, /* No ATI. */ \
timerInputActionNone, /* No action on falling input edge. */ \
timerInputActionNone, /* No action on rising input edge. */ \
timerModeUp, /* Up-counting. */ \
false, /* Do not clear DMA requests when DMA channel is active. */ \
false, /* Select X2 quadrature decode mode (if used). */ \
false, /* Disable one shot. */ \
false /* Not started/stopped/reloaded by other timers. */ \
}
{ \
true, /* Enable timer when init complete. */ \
false, /* Stop counter during debug halt. */ \
timerPrescale1, /* No prescaling. */ \
timerClkSelHFPerClk, /* Select HFPER clock. */ \
false, /* Not 2x count mode. */ \
false, /* No ATI. */ \
timerInputActionNone, /* No action on falling input edge. */ \
timerInputActionNone, /* No action on rising input edge. */ \
timerModeUp, /* Up-counting. */ \
false, /* Do not clear DMA requests when DMA channel is active. */ \
false, /* Select X2 quadrature decode mode (if used). */ \
false, /* Disable one shot. */ \
false /* Not started/stopped/reloaded by other timers. */ \
}
#else
#define TIMER_INIT_DEFAULT \
{ \
true, /* Enable timer when init complete. */ \
false, /* Stop counter during debug halt. */ \
timerPrescale1, /* No prescaling. */ \
timerClkSelHFPerClk, /* Select HFPER clock. */ \
timerInputActionNone, /* No action on falling input edge. */ \
timerInputActionNone, /* No action on rising input edge. */ \
timerModeUp, /* Up-counting. */ \
false, /* Do not clear DMA requests when DMA channel is active. */ \
false, /* Select X2 quadrature decode mode (if used). */ \
false, /* Disable one shot. */ \
false /* Not started/stopped/reloaded by other timers. */ \
}
{ \
true, /* Enable timer when init complete. */ \
false, /* Stop counter during debug halt. */ \
timerPrescale1, /* No prescaling. */ \
timerClkSelHFPerClk, /* Select HFPER clock. */ \
timerInputActionNone, /* No action on falling input edge. */ \
timerInputActionNone, /* No action on rising input edge. */ \
timerModeUp, /* Up-counting. */ \
false, /* Do not clear DMA requests when DMA channel is active. */ \
false, /* Select X2 quadrature decode mode (if used). */ \
false, /* Disable one shot. */ \
false /* Not started/stopped/reloaded by other timers. */ \
}
#endif
/** TIMER compare/capture initialization structure. */
typedef struct
{
typedef struct {
/** Input capture event control. */
TIMER_Event_TypeDef eventCtrl;
@ -379,24 +359,23 @@ typedef struct
/** Default config for TIMER compare/capture init structure. */
#define TIMER_INITCC_DEFAULT \
{ \
timerEventEveryEdge, /* Event on every capture. */ \
timerEdgeRising, /* Input capture edge on rising edge. */ \
timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
timerOutputActionNone, /* No action on underflow. */ \
timerOutputActionNone, /* No action on overflow. */ \
timerOutputActionNone, /* No action on match. */ \
timerCCModeOff, /* Disable compare/capture channel. */ \
false, /* Disable filter. */ \
false, /* Select TIMERnCCx input. */ \
false, /* Clear output when counter disabled. */ \
false /* Do not invert output. */ \
}
{ \
timerEventEveryEdge, /* Event on every capture. */ \
timerEdgeRising, /* Input capture edge on rising edge. */ \
timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
timerOutputActionNone, /* No action on underflow. */ \
timerOutputActionNone, /* No action on overflow. */ \
timerOutputActionNone, /* No action on match. */ \
timerCCModeOff, /* Disable compare/capture channel. */ \
false, /* Disable filter. */ \
false, /* Select TIMERnCCx input. */ \
false, /* Clear output when counter disabled. */ \
false /* Do not invert output. */ \
}
#if defined(_TIMER_DTCTRL_MASK)
/** TIMER Dead Time Insertion (DTI) initialization structure. */
typedef struct
{
typedef struct {
/** Enable DTI or leave it disabled until @ref TIMER_EnableDTI() is called */
bool enable;
@ -451,39 +430,35 @@ typedef struct
/** Fault Action */
TIMER_DtiFaultAction_TypeDef faultAction;
} TIMER_InitDTI_TypeDef;
/** Default config for TIMER DTI init structure. */
#define TIMER_INITDTI_DEFAULT \
{ \
true, /* Enable the DTI. */ \
false, /* CC[0|1|2] outputs are active high. */ \
false, /* CDTI[0|1|2] outputs are not inverted. */ \
false, /* No auto restart when debugger exits. */ \
false, /* No PRS source selected. */ \
timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
timerPrescale1, /* No prescaling. */ \
0, /* No rise time. */ \
0, /* No fall time. */ \
TIMER_DTOGEN_DTOGCC0EN|TIMER_DTOGEN_DTOGCDTI0EN, /* Enable CC0 and CDTI0 */\
true, /* Enable core lockup as fault source */ \
true, /* Enable debugger as fault source */ \
false, /* Disable PRS fault source 0 */ \
timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
false, /* Disable PRS fault source 1 */ \
timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
timerDtiFaultActionInactive, /* No fault action. */ \
}
/** Default config for TIMER DTI init structure. */
#define TIMER_INITDTI_DEFAULT \
{ \
true, /* Enable the DTI. */ \
false, /* CC[0|1|2] outputs are active high. */ \
false, /* CDTI[0|1|2] outputs are not inverted. */ \
false, /* No auto restart when debugger exits. */ \
false, /* No PRS source selected. */ \
timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
timerPrescale1, /* No prescaling. */ \
0, /* No rise time. */ \
0, /* No fall time. */ \
TIMER_DTOGEN_DTOGCC0EN | TIMER_DTOGEN_DTOGCDTI0EN, /* Enable CC0 and CDTI0 */ \
true, /* Enable core lockup as fault source */ \
true, /* Enable debugger as fault source */ \
false, /* Disable PRS fault source 0 */ \
timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
false, /* Disable PRS fault source 1 */ \
timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
timerDtiFaultActionInactive, /* No fault action. */ \
}
#endif /* _TIMER_DTCTRL_MASK */
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
/***************************************************************************//**
* @brief
* Validate the TIMER register block pointer
@ -506,13 +481,28 @@ __STATIC_INLINE bool TIMER_Valid(const TIMER_TypeDef *ref)
#if defined(TIMER3)
|| (ref == TIMER3)
#endif
#if defined(TIMER4)
|| (ref == TIMER4)
#endif
#if defined(TIMER5)
|| (ref == TIMER5)
#endif
#if defined(TIMER6)
|| (ref == TIMER6)
#endif
#if defined(WTIMER0)
|| (ref == WTIMER0)
#endif
#if defined(WTIMER1)
|| (ref == WTIMER1)
#endif
;
#if defined(WTIMER2)
|| (ref == WTIMER2)
#endif
#if defined(WTIMER3)
|| (ref == WTIMER3)
#endif
;
}
/***************************************************************************//**
@ -533,8 +523,13 @@ __STATIC_INLINE uint32_t TIMER_MaxCount(const TIMER_TypeDef *ref)
#if defined(WTIMER1)
|| (ref == WTIMER1)
#endif
)
{
#if defined(WTIMER2)
|| (ref == WTIMER2)
#endif
#if defined(WTIMER3)
|| (ref == WTIMER3)
#endif
) {
return 0xFFFFFFFFUL;
}
#else
@ -562,7 +557,6 @@ __STATIC_INLINE uint32_t TIMER_CaptureGet(TIMER_TypeDef *timer, unsigned int ch)
return timer->CC[ch].CCV;
}
/***************************************************************************//**
* @brief
* Set compare value buffer for compare/capture channel when operating in
@ -590,7 +584,6 @@ __STATIC_INLINE void TIMER_CompareBufSet(TIMER_TypeDef *timer,
timer->CC[ch].CCVB = val;
}
/***************************************************************************//**
* @brief
* Set compare value for compare/capture channel when operating in compare
@ -613,7 +606,6 @@ __STATIC_INLINE void TIMER_CompareSet(TIMER_TypeDef *timer,
timer->CC[ch].CCV = val;
}
/***************************************************************************//**
* @brief
* Get TIMER counter value.
@ -629,7 +621,6 @@ __STATIC_INLINE uint32_t TIMER_CounterGet(TIMER_TypeDef *timer)
return timer->CNT;
}
/***************************************************************************//**
* @brief
* Set TIMER counter value.
@ -646,7 +637,6 @@ __STATIC_INLINE void TIMER_CounterSet(TIMER_TypeDef *timer, uint32_t val)
timer->CNT = val;
}
/***************************************************************************//**
* @brief
* Start/stop TIMER.
@ -661,17 +651,13 @@ __STATIC_INLINE void TIMER_Enable(TIMER_TypeDef *timer, bool enable)
{
EFM_ASSERT(TIMER_REF_VALID(timer));
if (enable)
{
if (enable) {
timer->CMD = TIMER_CMD_START;
}
else
{
} else {
timer->CMD = TIMER_CMD_STOP;
}
}
void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init);
void TIMER_InitCC(TIMER_TypeDef *timer,
unsigned int ch,
@ -694,17 +680,13 @@ __STATIC_INLINE void TIMER_EnableDTI(TIMER_TypeDef *timer, bool enable)
{
EFM_ASSERT(TIMER0 == timer);
if (enable)
{
if (enable) {
timer->DTCTRL |= TIMER_DTCTRL_DTEN;
}
else
{
} else {
timer->DTCTRL &= ~TIMER_DTCTRL_DTEN;
}
}
/***************************************************************************//**
* @brief
* Get DTI fault source flags status.
@ -725,7 +707,6 @@ __STATIC_INLINE uint32_t TIMER_GetDTIFault(TIMER_TypeDef *timer)
return timer->DTFAULT;
}
/***************************************************************************//**
* @brief
* Clear DTI fault source flags.
@ -745,7 +726,6 @@ __STATIC_INLINE void TIMER_ClearDTIFault(TIMER_TypeDef *timer, uint32_t flags)
}
#endif /* _TIMER_DTCTRL_MASK */
/***************************************************************************//**
* @brief
* Clear one or more pending TIMER interrupts.
@ -762,7 +742,6 @@ __STATIC_INLINE void TIMER_IntClear(TIMER_TypeDef *timer, uint32_t flags)
timer->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more TIMER interrupts.
@ -779,7 +758,6 @@ __STATIC_INLINE void TIMER_IntDisable(TIMER_TypeDef *timer, uint32_t flags)
timer->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more TIMER interrupts.
@ -801,7 +779,6 @@ __STATIC_INLINE void TIMER_IntEnable(TIMER_TypeDef *timer, uint32_t flags)
timer->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending TIMER interrupt flags.
@ -821,7 +798,6 @@ __STATIC_INLINE uint32_t TIMER_IntGet(TIMER_TypeDef *timer)
return timer->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending TIMER interrupt flags.
@ -853,7 +829,6 @@ __STATIC_INLINE uint32_t TIMER_IntGetEnabled(TIMER_TypeDef *timer)
return timer->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending TIMER interrupts from SW.
@ -918,7 +893,6 @@ __STATIC_INLINE void TIMER_TopBufSet(TIMER_TypeDef *timer, uint32_t val)
timer->TOPB = val;
}
/***************************************************************************//**
* @brief
* Get top value setting for timer.
@ -934,7 +908,6 @@ __STATIC_INLINE uint32_t TIMER_TopGet(TIMER_TypeDef *timer)
return timer->TOP;
}
/***************************************************************************//**
* @brief
* Set top value for timer.
@ -951,7 +924,6 @@ __STATIC_INLINE void TIMER_TopSet(TIMER_TypeDef *timer, uint32_t val)
timer->TOP = val;
}
#if defined(TIMER_DTLOCK_LOCKKEY_UNLOCK)
/***************************************************************************//**
* @brief

580
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h
View File

@ -2,9 +2,9 @@
* @file em_usart.h
* @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART)
* peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -31,7 +31,6 @@
*
******************************************************************************/
#ifndef EM_USART_H
#define EM_USART_H
@ -102,8 +101,7 @@ extern "C" {
******************************************************************************/
/** Databit selection. */
typedef enum
{
typedef enum {
usartDatabits4 = USART_FRAME_DATABITS_FOUR, /**< 4 databits (not available for UART). */
usartDatabits5 = USART_FRAME_DATABITS_FIVE, /**< 5 databits (not available for UART). */
usartDatabits6 = USART_FRAME_DATABITS_SIX, /**< 6 databits (not available for UART). */
@ -119,10 +117,8 @@ typedef enum
usartDatabits16 = USART_FRAME_DATABITS_SIXTEEN /**< 16 databits (not available for UART). */
} USART_Databits_TypeDef;
/** Enable selection. */
typedef enum
{
typedef enum {
/** Disable both receiver and transmitter. */
usartDisable = 0x0,
@ -136,39 +132,40 @@ typedef enum
usartEnable = (USART_CMD_RXEN | USART_CMD_TXEN)
} USART_Enable_TypeDef;
/** Oversampling selection, used for asynchronous operation. */
typedef enum
{
typedef enum {
usartOVS16 = USART_CTRL_OVS_X16, /**< 16x oversampling (normal). */
usartOVS8 = USART_CTRL_OVS_X8, /**< 8x oversampling. */
usartOVS6 = USART_CTRL_OVS_X6, /**< 6x oversampling. */
usartOVS4 = USART_CTRL_OVS_X4 /**< 4x oversampling. */
} USART_OVS_TypeDef;
/** Parity selection, mainly used for asynchronous operation. */
typedef enum
{
typedef enum {
usartNoParity = USART_FRAME_PARITY_NONE, /**< No parity. */
usartEvenParity = USART_FRAME_PARITY_EVEN, /**< Even parity. */
usartOddParity = USART_FRAME_PARITY_ODD /**< Odd parity. */
} USART_Parity_TypeDef;
/** Stopbits selection, used for asynchronous operation. */
typedef enum
{
typedef enum {
usartStopbits0p5 = USART_FRAME_STOPBITS_HALF, /**< 0.5 stopbits. */
usartStopbits1 = USART_FRAME_STOPBITS_ONE, /**< 1 stopbits. */
usartStopbits1p5 = USART_FRAME_STOPBITS_ONEANDAHALF, /**< 1.5 stopbits. */
usartStopbits2 = USART_FRAME_STOPBITS_TWO /**< 2 stopbits. */
} USART_Stopbits_TypeDef;
#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
typedef enum {
usartHwFlowControlNone = 0,
usartHwFlowControlCts = USART_ROUTEPEN_CTSPEN,
usartHwFlowControlRts = USART_ROUTEPEN_RTSPEN,
usartHwFlowControlCtsAndRts = USART_ROUTEPEN_CTSPEN | USART_ROUTEPEN_RTSPEN,
} USART_HwFlowControl_TypeDef;
#endif
/** Clock polarity/phase mode. */
typedef enum
{
typedef enum {
/** Clock idle low, sample on rising edge. */
usartClockMode0 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLELEADING,
@ -182,10 +179,8 @@ typedef enum
usartClockMode3 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLETRAILING
} USART_ClockMode_TypeDef;
/** Pulse width selection for IrDA mode. */
typedef enum
{
typedef enum {
/** IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 */
usartIrDAPwONE = USART_IRCTRL_IRPW_ONE,
@ -199,10 +194,8 @@ typedef enum
usartIrDAPwFOUR = USART_IRCTRL_IRPW_FOUR
} USART_IrDAPw_Typedef;
/** PRS channel selection for IrDA mode. */
typedef enum
{
typedef enum {
usartIrDAPrsCh0 = USART_IRCTRL_IRPRSSEL_PRSCH0, /**< PRS channel 0 */
usartIrDAPrsCh1 = USART_IRCTRL_IRPRSSEL_PRSCH1, /**< PRS channel 1 */
usartIrDAPrsCh2 = USART_IRCTRL_IRPRSSEL_PRSCH2, /**< PRS channel 2 */
@ -223,8 +216,7 @@ typedef enum
#if defined(_USART_I2SCTRL_MASK)
/** I2S format selection. */
typedef enum
{
typedef enum {
usartI2sFormatW32D32 = USART_I2SCTRL_FORMAT_W32D32, /**< 32-bit word, 32-bit data */
usartI2sFormatW32D24M = USART_I2SCTRL_FORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked */
usartI2sFormatW32D24 = USART_I2SCTRL_FORMAT_W32D24, /**< 32-bit word, 24-bit data */
@ -236,8 +228,7 @@ typedef enum
} USART_I2sFormat_TypeDef;
/** I2S frame data justify. */
typedef enum
{
typedef enum {
usartI2sJustifyLeft = USART_I2SCTRL_JUSTIFY_LEFT, /**< Data is left-justified within the frame */
usartI2sJustifyRight = USART_I2SCTRL_JUSTIFY_RIGHT /**< Data is right-justified within the frame */
} USART_I2sJustify_TypeDef;
@ -245,8 +236,7 @@ typedef enum
#if defined(_USART_INPUT_MASK)
/** USART Rx input PRS selection. */
typedef enum
{
typedef enum {
usartPrsRxCh0 = USART_INPUT_RXPRSSEL_PRSCH0, /**< PRSCH0 selected as USART_INPUT */
usartPrsRxCh1 = USART_INPUT_RXPRSSEL_PRSCH1, /**< PRSCH1 selected as USART_INPUT */
usartPrsRxCh2 = USART_INPUT_RXPRSSEL_PRSCH2, /**< PRSCH2 selected as USART_INPUT */
@ -269,8 +259,7 @@ typedef enum
#endif
/** USART PRS Transmit Trigger Channels */
typedef enum
{
typedef enum {
usartPrsTriggerCh0 = USART_TRIGCTRL_TSEL_PRSCH0, /**< PRSCH0 selected as USART Trigger */
usartPrsTriggerCh1 = USART_TRIGCTRL_TSEL_PRSCH1, /**< PRSCH0 selected as USART Trigger */
usartPrsTriggerCh2 = USART_TRIGCTRL_TSEL_PRSCH2, /**< PRSCH0 selected as USART Trigger */
@ -289,8 +278,7 @@ typedef enum
******************************************************************************/
/** Asynchronous mode init structure. */
typedef struct
{
typedef struct {
/** Specifies whether TX and/or RX shall be enabled when init completed. */
USART_Enable_TypeDef enable;
@ -334,11 +322,13 @@ typedef struct
/** Auto CS setup time in baud cycles */
uint8_t autoCsSetup;
#endif
#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
USART_HwFlowControl_TypeDef hwFlowControl;
#endif
} USART_InitAsync_TypeDef;
/** USART PRS trigger enable */
typedef struct
{
typedef struct {
#if defined(USART_TRIGCTRL_AUTOTXTEN)
/** Enable AUTOTX */
bool autoTxTriggerEnable;
@ -352,71 +342,119 @@ typedef struct
} USART_PrsTriggerInit_TypeDef;
/** Default config for USART async init structure. */
#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
#define USART_INITASYNC_DEFAULT \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartNoParity, /* No parity. */ \
usartStopbits1, /* 1 stopbit. */ \
false, /* Do not disable majority vote. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0, /* PRS channel 0. */ \
false, /* Auto CS functionality enable/disable switch */ \
0, /* Auto CS Hold cycles */ \
0 /* Auto CS Setup cycles */ \
}
#define USART_INITASYNC_DEFAULT \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartNoParity, /* No parity. */ \
usartStopbits1, /* 1 stopbit. */ \
false, /* Do not disable majority vote. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0, /* PRS channel 0. */ \
false, /* Auto CS functionality enable/disable switch */ \
0, /* Auto CS Hold cycles */ \
0, /* Auto CS Setup cycles */ \
usartHwFlowControlNone /* No HW flow control */ \
}
#elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
#define USART_INITASYNC_DEFAULT \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartNoParity, /* No parity. */ \
usartStopbits1, /* 1 stopbit. */ \
false, /* Do not disable majority vote. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0 /* PRS channel 0. */ \
}
#define USART_INITASYNC_DEFAULT \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartNoParity, /* No parity. */ \
usartStopbits1, /* 1 stopbit. */ \
false, /* Do not disable majority vote. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0, /* PRS channel 0. */ \
usartHwFlowControlNone /* No HW flow control */ \
}
#else
#define USART_INITASYNC_DEFAULT \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartNoParity, /* No parity. */ \
usartStopbits1 /* 1 stopbit. */ \
}
#define USART_INITASYNC_DEFAULT \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartNoParity, /* No parity. */ \
usartStopbits1, /* 1 stopbit. */ \
usartHwFlowControlNone /* No HW flow control */ \
}
#endif
#else
#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
#define USART_INITASYNC_DEFAULT \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartNoParity, /* No parity. */ \
usartStopbits1, /* 1 stopbit. */ \
false, /* Do not disable majority vote. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0, /* PRS channel 0. */ \
false, /* Auto CS functionality enable/disable switch */ \
0, /* Auto CS Hold cycles */ \
0 /* Auto CS Setup cycles */ \
}
#elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
#define USART_INITASYNC_DEFAULT \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartNoParity, /* No parity. */ \
usartStopbits1, /* 1 stopbit. */ \
false, /* Do not disable majority vote. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0 /* PRS channel 0. */ \
}
#else
#define USART_INITASYNC_DEFAULT \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartNoParity, /* No parity. */ \
usartStopbits1 /* 1 stopbit. */ \
}
#endif
#endif
/** Default config for USART PRS triggering structure. */
#if defined(USART_TRIGCTRL_AUTOTXTEN)
#define USART_INITPRSTRIGGER_DEFAULT \
{ \
false, /* Do not enable autoTX triggering. */ \
false, /* Do not enable receive triggering. */ \
false, /* Do not enable transmit triggering. */ \
usartPrsTriggerCh0 /* Set default channel to zero. */ \
}
#define USART_INITPRSTRIGGER_DEFAULT \
{ \
false, /* Do not enable autoTX triggering. */ \
false, /* Do not enable receive triggering. */ \
false, /* Do not enable transmit triggering. */ \
usartPrsTriggerCh0 /* Set default channel to zero. */ \
}
#else
#define USART_INITPRSTRIGGER_DEFAULT \
{ \
false, /* Do not enable receive triggering. */ \
false, /* Do not enable transmit triggering. */ \
usartPrsTriggerCh0 /* Set default channel to zero. */ \
}
#define USART_INITPRSTRIGGER_DEFAULT \
{ \
false, /* Do not enable receive triggering. */ \
false, /* Do not enable transmit triggering. */ \
usartPrsTriggerCh0 /* Set default channel to zero. */ \
}
#endif
/** Synchronous mode init structure. */
typedef struct
{
typedef struct {
/** Specifies whether TX and/or RX shall be enabled when init completed. */
USART_Enable_TypeDef enable;
@ -465,52 +503,50 @@ typedef struct
/** Default config for USART sync init structure. */
#if defined(_USART_TIMING_CSHOLD_MASK)
#define USART_INITSYNC_DEFAULT \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
1000000, /* 1 Mbits/s. */ \
usartDatabits8, /* 8 databits. */ \
true, /* Master mode. */ \
false, /* Send least significant bit first. */ \
usartClockMode0, /* Clock idle low, sample on rising edge. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0, /* PRS channel 0. */ \
false, /* No AUTOTX mode. */ \
false, /* No AUTOCS mode */ \
0, /* Auto CS Hold cycles */ \
0 /* Auto CS Setup cycles */ \
}
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
1000000, /* 1 Mbits/s. */ \
usartDatabits8, /* 8 databits. */ \
true, /* Master mode. */ \
false, /* Send least significant bit first. */ \
usartClockMode0, /* Clock idle low, sample on rising edge. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0, /* PRS channel 0. */ \
false, /* No AUTOTX mode. */ \
false, /* No AUTOCS mode */ \
0, /* Auto CS Hold cycles */ \
0 /* Auto CS Setup cycles */ \
}
#elif defined(USART_INPUT_RXPRS) && defined(USART_TRIGCTRL_AUTOTXTEN)
#define USART_INITSYNC_DEFAULT \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
1000000, /* 1 Mbits/s. */ \
usartDatabits8, /* 8 databits. */ \
true, /* Master mode. */ \
false, /* Send least significant bit first. */ \
usartClockMode0, /* Clock idle low, sample on rising edge. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0, /* PRS channel 0. */ \
false /* No AUTOTX mode. */ \
}
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
1000000, /* 1 Mbits/s. */ \
usartDatabits8, /* 8 databits. */ \
true, /* Master mode. */ \
false, /* Send least significant bit first. */ \
usartClockMode0, /* Clock idle low, sample on rising edge. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0, /* PRS channel 0. */ \
false /* No AUTOTX mode. */ \
}
#else
#define USART_INITSYNC_DEFAULT \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
1000000, /* 1 Mbits/s. */ \
usartDatabits8, /* 8 databits. */ \
true, /* Master mode. */ \
false, /* Send least significant bit first. */ \
usartClockMode0 /* Clock idle low, sample on rising edge. */ \
}
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
1000000, /* 1 Mbits/s. */ \
usartDatabits8, /* 8 databits. */ \
true, /* Master mode. */ \
false, /* Send least significant bit first. */ \
usartClockMode0 /* Clock idle low, sample on rising edge. */ \
}
#endif
/** IrDA mode init structure. Inherited from asynchronous mode init structure */
typedef struct
{
typedef struct {
/** General Async initialization structure. */
USART_InitAsync_TypeDef async;
@ -533,77 +569,145 @@ typedef struct
USART_IrDAPrsSel_Typedef irPrsSel;
} USART_InitIrDA_TypeDef;
/** Default config for IrDA mode init structure. */
#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
#define USART_INITIRDA_DEFAULT \
{ \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartEvenParity, /* Even parity. */ \
usartStopbits1, /* 1 stopbit. */ \
false, /* Do not disable majority vote. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0, /* PRS channel 0. */ \
false, /* Auto CS functionality enable/disable switch */ \
0, /* Auto CS Hold cycles */ \
0 /* Auto CS Setup cycles */ \
}, \
false, /* Rx invert disabled. */ \
false, /* Filtering disabled. */ \
usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
false, /* Routing to PRS is disabled. */ \
usartIrDAPrsCh0 /* PRS channel 0. */ \
}
#define USART_INITIRDA_DEFAULT \
{ \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartEvenParity,/* Even parity. */ \
usartStopbits1, /* 1 stopbit. */ \
false, /* Do not disable majority vote. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0, /* PRS channel 0. */ \
false, /* Auto CS functionality enable/disable switch */ \
0, /* Auto CS Hold cycles */ \
0, /* Auto CS Setup cycles */ \
usartHwFlowControlNone /* No HW flow control */ \
}, \
false, /* Rx invert disabled. */ \
false, /* Filtering disabled. */ \
usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
false, /* Routing to PRS is disabled. */ \
usartIrDAPrsCh0 /* PRS channel 0. */ \
}
#elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
#define USART_INITIRDA_DEFAULT \
{ \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartEvenParity, /* Even parity. */ \
usartStopbits1, /* 1 stopbit. */ \
false, /* Do not disable majority vote. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0 /* PRS channel 0. */ \
}, \
false, /* Rx invert disabled. */ \
false, /* Filtering disabled. */ \
usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
false, /* Routing to PRS is disabled. */ \
usartIrDAPrsCh0 /* PRS channel 0. */ \
}
#define USART_INITIRDA_DEFAULT \
{ \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartEvenParity,/* Even parity. */ \
usartStopbits1, /* 1 stopbit. */ \
false, /* Do not disable majority vote. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0, /* PRS channel 0. */ \
usartHwFlowControlNone /* No HW flow control */ \
}, \
false, /* Rx invert disabled. */ \
false, /* Filtering disabled. */ \
usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
false, /* Routing to PRS is disabled. */ \
usartIrDAPrsCh0 /* PRS channel 0. */ \
}
#else
#define USART_INITIRDA_DEFAULT \
{ \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartEvenParity, /* Even parity. */ \
usartStopbits1 /* 1 stopbit. */ \
}, \
false, /* Rx invert disabled. */ \
false, /* Filtering disabled. */ \
usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
false, /* Routing to PRS is disabled. */ \
usartIrDAPrsCh0 /* PRS channel 0. */ \
}
#define USART_INITIRDA_DEFAULT \
{ \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartEvenParity,/* Even parity. */ \
usartStopbits1, /* 1 stopbit. */ \
usartHwFlowControlNone /* No HW flow control */ \
}, \
false, /* Rx invert disabled. */ \
false, /* Filtering disabled. */ \
usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
false, /* Routing to PRS is disabled. */ \
usartIrDAPrsCh0 /* PRS channel 0. */ \
}
#endif
#else
#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
#define USART_INITIRDA_DEFAULT \
{ \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartEvenParity,/* Even parity. */ \
usartStopbits1, /* 1 stopbit. */ \
false, /* Do not disable majority vote. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0, /* PRS channel 0. */ \
false, /* Auto CS functionality enable/disable switch */ \
0, /* Auto CS Hold cycles */ \
0 /* Auto CS Setup cycles */ \
}, \
false, /* Rx invert disabled. */ \
false, /* Filtering disabled. */ \
usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
false, /* Routing to PRS is disabled. */ \
usartIrDAPrsCh0 /* PRS channel 0. */ \
}
#elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
#define USART_INITIRDA_DEFAULT \
{ \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartEvenParity,/* Even parity. */ \
usartStopbits1, /* 1 stopbit. */ \
false, /* Do not disable majority vote. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0 /* PRS channel 0. */ \
}, \
false, /* Rx invert disabled. */ \
false, /* Filtering disabled. */ \
usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
false, /* Routing to PRS is disabled. */ \
usartIrDAPrsCh0 /* PRS channel 0. */ \
}
#else
#define USART_INITIRDA_DEFAULT \
{ \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartEvenParity,/* Even parity. */ \
usartStopbits1 /* 1 stopbit. */ \
}, \
false, /* Rx invert disabled. */ \
false, /* Filtering disabled. */ \
usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
false, /* Routing to PRS is disabled. */ \
usartIrDAPrsCh0 /* PRS channel 0. */ \
}
#endif
#endif
#if defined(_USART_I2SCTRL_MASK)
/** I2S mode init structure. Inherited from synchronous mode init structure */
typedef struct
{
typedef struct {
/** General Sync initialization structure. */
USART_InitSync_TypeDef sync;
@ -625,53 +729,52 @@ typedef struct
bool mono;
} USART_InitI2s_TypeDef;
/** Default config for I2S mode init structure. */
#if defined(_USART_TIMING_CSHOLD_MASK)
#define USART_INITI2S_DEFAULT \
{ \
{ \
usartEnableTx, /* Enable TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
1000000, /* Baudrate 1M bits/s. */ \
usartDatabits16, /* 16 databits. */ \
true, /* Operate as I2S master. */ \
true, /* Most significant bit first. */ \
usartClockMode0, /* Clock idle low, sample on rising edge. */ \
false, /* Don't enable USARTRx via PRS. */ \
usartPrsRxCh0, /* PRS channel selection (dummy). */ \
false, /* Disable AUTOTX mode. */ \
false, /* No AUTOCS mode */ \
0, /* Auto CS Hold cycles */ \
0 /* Auto CS Setup cycles */ \
}, \
usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \
true, /* Delay on I2S data. */ \
false, /* No DMA split. */ \
usartI2sJustifyLeft, /* Data is left-justified within the frame */ \
false /* Stereo mode. */ \
}
{ \
usartEnableTx, /* Enable TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
1000000, /* Baudrate 1M bits/s. */ \
usartDatabits16, /* 16 databits. */ \
true, /* Operate as I2S master. */ \
true, /* Most significant bit first. */ \
usartClockMode0, /* Clock idle low, sample on rising edge. */ \
false, /* Don't enable USARTRx via PRS. */ \
usartPrsRxCh0, /* PRS channel selection (dummy). */ \
false, /* Disable AUTOTX mode. */ \
false, /* No AUTOCS mode */ \
0, /* Auto CS Hold cycles */ \
0 /* Auto CS Setup cycles */ \
}, \
usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \
true, /* Delay on I2S data. */ \
false, /* No DMA split. */ \
usartI2sJustifyLeft,/* Data is left-justified within the frame */ \
false /* Stereo mode. */ \
}
#else
#define USART_INITI2S_DEFAULT \
{ \
{ \
usartEnableTx, /* Enable TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
1000000, /* Baudrate 1M bits/s. */ \
usartDatabits16, /* 16 databits. */ \
true, /* Operate as I2S master. */ \
true, /* Most significant bit first. */ \
usartClockMode0, /* Clock idle low, sample on rising edge. */ \
false, /* Don't enable USARTRx via PRS. */ \
usartPrsRxCh0, /* PRS channel selection (dummy). */ \
false /* Disable AUTOTX mode. */ \
}, \
usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \
true, /* Delay on I2S data. */ \
false, /* No DMA split. */ \
usartI2sJustifyLeft, /* Data is left-justified within the frame */ \
false /* Stereo mode. */ \
}
{ \
usartEnableTx, /* Enable TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
1000000, /* Baudrate 1M bits/s. */ \
usartDatabits16, /* 16 databits. */ \
true, /* Operate as I2S master. */ \
true, /* Most significant bit first. */ \
usartClockMode0, /* Clock idle low, sample on rising edge. */ \
false, /* Don't enable USARTRx via PRS. */ \
usartPrsRxCh0, /* PRS channel selection (dummy). */ \
false /* Disable AUTOTX mode. */ \
}, \
usartI2sFormatW16D16,/* 16-bit word, 16-bit data */ \
true, /* Delay on I2S data. */ \
false, /* No DMA split. */ \
usartI2sJustifyLeft,/* Data is left-justified within the frame */ \
false /* Stereo mode. */ \
}
#endif
#endif
@ -759,7 +862,6 @@ __STATIC_INLINE void USART_IntClear(USART_TypeDef *usart, uint32_t flags)
usart->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more USART interrupts.
@ -776,7 +878,6 @@ __STATIC_INLINE void USART_IntDisable(USART_TypeDef *usart, uint32_t flags)
usart->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more USART interrupts.
@ -798,7 +899,6 @@ __STATIC_INLINE void USART_IntEnable(USART_TypeDef *usart, uint32_t flags)
usart->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending USART interrupt flags.
@ -818,7 +918,6 @@ __STATIC_INLINE uint32_t USART_IntGet(USART_TypeDef *usart)
return usart->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending USART interrupt flags.
@ -850,7 +949,6 @@ __STATIC_INLINE uint32_t USART_IntGetEnabled(USART_TypeDef *usart)
return usart->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending USART interrupts from SW.
@ -867,7 +965,6 @@ __STATIC_INLINE void USART_IntSet(USART_TypeDef *usart, uint32_t flags)
usart->IFS = flags;
}
/***************************************************************************//**
* @brief
* Get USART STATUS register.
@ -890,7 +987,6 @@ uint16_t USART_RxDouble(USART_TypeDef *usart);
uint32_t USART_RxDoubleExt(USART_TypeDef *usart);
uint16_t USART_RxExt(USART_TypeDef *usart);
/***************************************************************************//**
* @brief
* Receive one 4-8 bit frame, (or part of 10-16 bit frame).
@ -924,7 +1020,6 @@ __STATIC_INLINE uint8_t USART_RxDataGet(USART_TypeDef *usart)
return (uint8_t)usart->RXDATA;
}
/***************************************************************************//**
* @brief
* Receive two 4-8 bit frames, or one 10-16 bit frame.
@ -962,7 +1057,6 @@ __STATIC_INLINE uint16_t USART_RxDoubleGet(USART_TypeDef *usart)
return (uint16_t)usart->RXDOUBLE;
}
/***************************************************************************//**
* @brief
* Receive two 4-9 bit frames, or one 10-16 bit frame with extended
@ -998,7 +1092,6 @@ __STATIC_INLINE uint32_t USART_RxDoubleXGet(USART_TypeDef *usart)
return usart->RXDOUBLEX;
}
/***************************************************************************//**
* @brief
* Receive one 4-9 bit frame, (or part of 10-16 bit frame) with extended
@ -1039,7 +1132,6 @@ void USART_TxDouble(USART_TypeDef *usart, uint16_t data);
void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data);
void USART_TxExt(USART_TypeDef *usart, uint16_t data);
/** @} (end addtogroup USART) */
/** @} (end addtogroup emlib) */

69
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_vcmp.h
* @brief Voltage Comparator (VCMP) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -58,8 +58,7 @@ extern "C" {
******************************************************************************/
/** Warm-up Time in High Frequency Peripheral Clock cycles */
typedef enum
{
typedef enum {
/** 4 cycles */
vcmpWarmTime4Cycles = _VCMP_CTRL_WARMTIME_4CYCLES,
/** 8 cycles */
@ -79,8 +78,7 @@ typedef enum
} VCMP_WarmTime_TypeDef;
/** Hyseresis configuration */
typedef enum
{
typedef enum {
/** Normal operation, no hysteresis */
vcmpHystNone,
/** Digital output will not toggle until positive edge is at least
@ -93,8 +91,7 @@ typedef enum
******************************************************************************/
/** VCMP Initialization structure */
typedef struct
{
typedef struct {
/** If set to true, will reduce by half the bias current */
bool halfBias;
/** BIAS current configuration, depends on halfBias setting,
@ -121,18 +118,18 @@ typedef struct
/** Default VCMP initialization structure */
#define VCMP_INIT_DEFAULT \
{ \
true, /** Half Bias enabled */ \
0x7, /** Bias curernt 0.7 uA when half bias enabled */ \
false, /** Falling edge sense not enabled */ \
false, /** Rising edge sense not enabled */ \
vcmpWarmTime4Cycles, /** 4 clock cycles warm-up time */ \
vcmpHystNone, /** No hysteresis */ \
0, /** 0 in digital ouput when inactive */ \
true, /** Do not use low power reference */ \
39, /** Trigger level just below 3V */ \
true, /** Enable after init */ \
}
{ \
true, /** Half Bias enabled */ \
0x7, /** Bias curernt 0.7 uA when half bias enabled */ \
false, /** Falling edge sense not enabled */ \
false, /** Rising edge sense not enabled */ \
vcmpWarmTime4Cycles, /** 4 clock cycles warm-up time */ \
vcmpHystNone, /** No hysteresis */ \
0, /** 0 in digital ouput when inactive */ \
true, /** Do not use low power reference */ \
39, /** Trigger level just below 3V */ \
true, /** Enable after init */ \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************
@ -151,7 +148,6 @@ __STATIC_INLINE void VCMP_Enable(void)
VCMP->CTRL |= VCMP_CTRL_EN;
}
/***************************************************************************//**
* @brief
* Disable Voltage Comparator
@ -161,7 +157,6 @@ __STATIC_INLINE void VCMP_Disable(void)
VCMP->CTRL &= ~VCMP_CTRL_EN;
}
/***************************************************************************//**
* @brief
* Calculate voltage to trigger level
@ -177,7 +172,6 @@ __STATIC_INLINE uint32_t VCMP_VoltageToLevel(float v)
return (uint32_t)((v - (float)1.667) / (float)0.034);
}
/***************************************************************************//**
* @brief
* Returns true, if Voltage Comparator indicated VDD < trigger level, else
@ -185,17 +179,13 @@ __STATIC_INLINE uint32_t VCMP_VoltageToLevel(float v)
******************************************************************************/
__STATIC_INLINE bool VCMP_VDDLower(void)
{
if (VCMP->STATUS & VCMP_STATUS_VCMPOUT)
{
if (VCMP->STATUS & VCMP_STATUS_VCMPOUT) {
return false;
}
else
{
} else {
return true;
}
}
/***************************************************************************//**
* @brief
* Returns true, if Voltage Comparator indicated VDD > trigger level, else
@ -203,34 +193,26 @@ __STATIC_INLINE bool VCMP_VDDLower(void)
******************************************************************************/
__STATIC_INLINE bool VCMP_VDDHigher(void)
{
if (VCMP->STATUS & VCMP_STATUS_VCMPOUT)
{
if (VCMP->STATUS & VCMP_STATUS_VCMPOUT) {
return true;
}
else
{
} else {
return false;
}
}
/***************************************************************************//**
* @brief
* VCMP output is ready
******************************************************************************/
__STATIC_INLINE bool VCMP_Ready(void)
{
if (VCMP->STATUS & VCMP_STATUS_VCMPACT)
{
if (VCMP->STATUS & VCMP_STATUS_VCMPACT) {
return true;
}
else
{
} else {
return false;
}
}
/***************************************************************************//**
* @brief
* Clear one or more pending VCMP interrupts.
@ -245,7 +227,6 @@ __STATIC_INLINE void VCMP_IntClear(uint32_t flags)
VCMP->IFC = flags;
}
/***************************************************************************//**
* @brief
* Set one or more pending VCMP interrupts from SW.
@ -260,7 +241,6 @@ __STATIC_INLINE void VCMP_IntSet(uint32_t flags)
VCMP->IFS = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more VCMP interrupts
@ -275,7 +255,6 @@ __STATIC_INLINE void VCMP_IntDisable(uint32_t flags)
VCMP->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more VCMP interrupts
@ -290,7 +269,6 @@ __STATIC_INLINE void VCMP_IntEnable(uint32_t flags)
VCMP->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending VCMP interrupt flags
@ -307,7 +285,6 @@ __STATIC_INLINE uint32_t VCMP_IntGet(void)
return VCMP->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending VCMP interrupt flags.

97
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vdac.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_vdac.h
* @brief Digital to Analog Converter (VDAC) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -44,7 +44,6 @@
extern "C" {
#endif
/***************************************************************************//**
* @addtogroup emlib
* @{
@ -103,8 +102,7 @@ extern "C" {
******************************************************************************/
/** Channel refresh period. */
typedef enum
{
typedef enum {
vdacRefresh8 = _VDAC_CTRL_REFRESHPERIOD_8CYCLES, /**< Refresh every 8 clock cycles. */
vdacRefresh16 = _VDAC_CTRL_REFRESHPERIOD_16CYCLES, /**< Refresh every 16 clock cycles. */
vdacRefresh32 = _VDAC_CTRL_REFRESHPERIOD_32CYCLES, /**< Refresh every 32 clock cycles. */
@ -112,8 +110,7 @@ typedef enum
} VDAC_Refresh_TypeDef;
/** Reference voltage for VDAC. */
typedef enum
{
typedef enum {
vdacRef1V25Ln = _VDAC_CTRL_REFSEL_1V25LN, /**< Internal low noise 1.25 V bandgap reference. */
vdacRef2V5Ln = _VDAC_CTRL_REFSEL_2V5LN, /**< Internal low noise 2.5 V bandgap reference. */
vdacRef1V25 = _VDAC_CTRL_REFSEL_1V25, /**< Internal 1.25 V bandgap reference. */
@ -123,25 +120,31 @@ typedef enum
} VDAC_Ref_TypeDef;
/** Peripheral Reflex System signal used to trig VDAC channel conversion. */
typedef enum
{
vdacPrsSelCh0 = _VDAC_CH0CTRL_PRSSEL_PRSCH0 , /**< PRS ch 0 triggers conversion. */
vdacPrsSelCh1 = _VDAC_CH0CTRL_PRSSEL_PRSCH1 , /**< PRS ch 1 triggers conversion. */
vdacPrsSelCh2 = _VDAC_CH0CTRL_PRSSEL_PRSCH2 , /**< PRS ch 2 triggers conversion. */
vdacPrsSelCh3 = _VDAC_CH0CTRL_PRSSEL_PRSCH3 , /**< PRS ch 3 triggers conversion. */
vdacPrsSelCh4 = _VDAC_CH0CTRL_PRSSEL_PRSCH4 , /**< PRS ch 4 triggers conversion. */
vdacPrsSelCh5 = _VDAC_CH0CTRL_PRSSEL_PRSCH5 , /**< PRS ch 5 triggers conversion. */
vdacPrsSelCh6 = _VDAC_CH0CTRL_PRSSEL_PRSCH6 , /**< PRS ch 6 triggers conversion. */
vdacPrsSelCh7 = _VDAC_CH0CTRL_PRSSEL_PRSCH7 , /**< PRS ch 7 triggers conversion. */
vdacPrsSelCh8 = _VDAC_CH0CTRL_PRSSEL_PRSCH8 , /**< PRS ch 8 triggers conversion. */
vdacPrsSelCh9 = _VDAC_CH0CTRL_PRSSEL_PRSCH9 , /**< PRS ch 9 triggers conversion. */
typedef enum {
vdacPrsSelCh0 = _VDAC_CH0CTRL_PRSSEL_PRSCH0, /**< PRS ch 0 triggers conversion. */
vdacPrsSelCh1 = _VDAC_CH0CTRL_PRSSEL_PRSCH1, /**< PRS ch 1 triggers conversion. */
vdacPrsSelCh2 = _VDAC_CH0CTRL_PRSSEL_PRSCH2, /**< PRS ch 2 triggers conversion. */
vdacPrsSelCh3 = _VDAC_CH0CTRL_PRSSEL_PRSCH3, /**< PRS ch 3 triggers conversion. */
vdacPrsSelCh4 = _VDAC_CH0CTRL_PRSSEL_PRSCH4, /**< PRS ch 4 triggers conversion. */
vdacPrsSelCh5 = _VDAC_CH0CTRL_PRSSEL_PRSCH5, /**< PRS ch 5 triggers conversion. */
vdacPrsSelCh6 = _VDAC_CH0CTRL_PRSSEL_PRSCH6, /**< PRS ch 6 triggers conversion. */
vdacPrsSelCh7 = _VDAC_CH0CTRL_PRSSEL_PRSCH7, /**< PRS ch 7 triggers conversion. */
#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH8)
vdacPrsSelCh8 = _VDAC_CH0CTRL_PRSSEL_PRSCH8, /**< PRS ch 8 triggers conversion. */
#endif
#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH9)
vdacPrsSelCh9 = _VDAC_CH0CTRL_PRSSEL_PRSCH9, /**< PRS ch 9 triggers conversion. */
#endif
#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH10)
vdacPrsSelCh10 = _VDAC_CH0CTRL_PRSSEL_PRSCH10, /**< PRS ch 10 triggers conversion. */
#endif
#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH11)
vdacPrsSelCh11 = _VDAC_CH0CTRL_PRSSEL_PRSCH11, /**< PRS ch 11 triggers conversion. */
#endif
} VDAC_PrsSel_TypeDef;
/** Channel conversion trigger mode. */
typedef enum
{
typedef enum {
vdacTrigModeSw = _VDAC_CH0CTRL_TRIGMODE_SW, /**< Channel is triggered by CHnDATA or COMBDATA write. */
vdacTrigModePrs = _VDAC_CH0CTRL_TRIGMODE_PRS, /**< Channel is triggered by PRS input. */
vdacTrigModeRefresh = _VDAC_CH0CTRL_TRIGMODE_REFRESH, /**< Channel is triggered by Refresh timer. */
@ -155,8 +158,7 @@ typedef enum
******************************************************************************/
/** VDAC init structure, common for both channels. */
typedef struct
{
typedef struct {
/** Select between main and alternate output path calibration values. */
bool mainCalibration;
@ -190,23 +192,22 @@ typedef struct
} VDAC_Init_TypeDef;
/** Default config for VDAC init structure. */
#define VDAC_INIT_DEFAULT \
{ \
true, /* Use main output path calibration values. */ \
false, /* Use synchronous clock mode. */ \
false, /* Turn off between sample off conversions.*/ \
vdacRefresh8, /* Refresh every 8th cycle. */ \
0, /* No prescaling. */ \
vdacRef1V25Ln, /* 1.25V internal low noise reference. */ \
false, /* Do not reset prescaler on CH 0 start. */ \
false, /* VDAC output enable always on. */ \
false, /* Disable sine mode. */ \
false /* Single ended mode. */ \
}
#define VDAC_INIT_DEFAULT \
{ \
true, /* Use main output path calibration values. */ \
false, /* Use synchronous clock mode. */ \
false, /* Turn off between sample off conversions.*/ \
vdacRefresh8, /* Refresh every 8th cycle. */ \
0, /* No prescaling. */ \
vdacRef1V25Ln, /* 1.25V internal low noise reference. */ \
false, /* Do not reset prescaler on CH 0 start. */ \
false, /* VDAC output enable always on. */ \
false, /* Disable sine mode. */ \
false /* Single ended mode. */ \
}
/** VDAC channel init structure. */
typedef struct
{
typedef struct {
/** Enable channel. */
bool enable;
@ -227,14 +228,14 @@ typedef struct
} VDAC_InitChannel_TypeDef;
/** Default config for VDAC channel init structure. */
#define VDAC_INITCHANNEL_DEFAULT \
{ \
false, /* Leave channel disabled when init done. */ \
vdacPrsSelCh0, /* PRS CH 0 triggers conversion. */ \
false, /* Treat PRS channel as a synchronous signal. */ \
vdacTrigModeSw, /* Conversion trigged by CH0DATA or COMBDATA write. */ \
false, /* Channel conversion set to continous. */ \
}
#define VDAC_INITCHANNEL_DEFAULT \
{ \
false, /* Leave channel disabled when init done. */ \
vdacPrsSelCh0, /* PRS CH 0 triggers conversion. */ \
false, /* Treat PRS channel as a synchronous signal. */ \
vdacTrigModeSw, /* Conversion trigged by CH0DATA or COMBDATA write. */ \
false, /* Channel conversion set to continous. */ \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************
@ -266,7 +267,7 @@ void VDAC_InitChannel(VDAC_TypeDef *vdac,
__STATIC_INLINE void VDAC_Channel0OutputSet(VDAC_TypeDef *vdac,
uint32_t value)
{
EFM_ASSERT(value<=_VDAC_CH0DATA_MASK);
EFM_ASSERT(value <= _VDAC_CH0DATA_MASK);
vdac->CH0DATA = value;
}
@ -287,7 +288,7 @@ __STATIC_INLINE void VDAC_Channel0OutputSet(VDAC_TypeDef *vdac,
__STATIC_INLINE void VDAC_Channel1OutputSet(VDAC_TypeDef *vdac,
uint32_t value)
{
EFM_ASSERT(value<=_VDAC_CH1DATA_MASK);
EFM_ASSERT(value <= _VDAC_CH1DATA_MASK);
vdac->CH1DATA = value;
}

15
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_version.h
* @brief Assign correct part number for include file
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -52,23 +52,26 @@ extern "C" {
* @{
******************************************************************************/
/* *INDENT-OFF* */
/** Version number of emlib peripheral API. */
#define _EMLIB_VERSION 5.1.2
#define _EMLIB_VERSION 5.3.3
/* *INDENT-ON* */
/** Major version of emlib. Bumped when incompatible API changes introduced. */
#define _EMLIB_VERSION_MAJOR 5
/** Minor version of emlib. Bumped when functionality is added in a backwards-
compatible manner. */
#define _EMLIB_VERSION_MINOR 1
#define _EMLIB_VERSION_MINOR 3
/** Patch revision of emlib. Bumped when adding backwards-compatible bug
fixes.*/
#define _EMLIB_VERSION_PATCH 2
#define _EMLIB_VERSION_PATCH 3
/* *INDENT-OFF* */
/** Version number of targeted CMSIS package. */
#define _CMSIS_VERSION 4.5.0
/* *INDENT-ON* */
/** Major version of CMSIS. */
#define _CMSIS_VERSION_MAJOR 4

105
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_wdog.h
* @brief Watchdog (WDOG) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -30,7 +30,6 @@
*
******************************************************************************/
#ifndef EM_WDOG_H
#define EM_WDOG_H
@ -58,16 +57,14 @@ extern "C" {
******************************************************************************/
/** Watchdog clock selection. */
typedef enum
{
typedef enum {
wdogClkSelULFRCO = _WDOG_CTRL_CLKSEL_ULFRCO, /**< Ultra low frequency (1 kHz) clock */
wdogClkSelLFRCO = _WDOG_CTRL_CLKSEL_LFRCO, /**< Low frequency RC oscillator */
wdogClkSelLFXO = _WDOG_CTRL_CLKSEL_LFXO /**< Low frequency crystal oscillator */
} WDOG_ClkSel_TypeDef;
/** Watchdog period selection. */
typedef enum
{
typedef enum {
wdogPeriod_9 = 0x0, /**< 9 clock periods */
wdogPeriod_17 = 0x1, /**< 17 clock periods */
wdogPeriod_33 = 0x2, /**< 33 clock periods */
@ -86,11 +83,9 @@ typedef enum
wdogPeriod_256k = 0xF /**< 262145 clock periods */
} WDOG_PeriodSel_TypeDef;
#if defined( _WDOG_CTRL_WARNSEL_MASK )
#if defined(_WDOG_CTRL_WARNSEL_MASK)
/** Select watchdog warning timeout period as percentage of timeout. */
typedef enum
{
typedef enum {
wdogWarnDisable = 0,
wdogWarnTime25pct = 1,
wdogWarnTime50pct = 2,
@ -98,10 +93,9 @@ typedef enum
} WDOG_WarnSel_TypeDef;
#endif
#if defined( _WDOG_CTRL_WINSEL_MASK )
#if defined(_WDOG_CTRL_WINSEL_MASK)
/** Select watchdog illegal window limit. */
typedef enum
{
typedef enum {
wdogIllegalWindowDisable = 0,
wdogIllegalWindowTime12_5pct = 1,
wdogIllegalWindowTime25_0pct = 2,
@ -118,8 +112,7 @@ typedef enum
******************************************************************************/
/** Watchdog initialization structure. */
typedef struct
{
typedef struct {
/** Enable watchdog when init completed. */
bool enable;
@ -147,60 +140,58 @@ typedef struct
/** Watchdog timeout period. */
WDOG_PeriodSel_TypeDef perSel;
#if defined( _WDOG_CTRL_WARNSEL_MASK )
#if defined(_WDOG_CTRL_WARNSEL_MASK)
/** Select warning time as % of the watchdog timeout */
WDOG_WarnSel_TypeDef warnSel;
#endif
#if defined( _WDOG_CTRL_WINSEL_MASK )
#if defined(_WDOG_CTRL_WINSEL_MASK)
/** Select illegal window time as % of the watchdog timeout */
WDOG_WinSel_TypeDef winSel;
#endif
#if defined( _WDOG_CTRL_WDOGRSTDIS_MASK )
#if defined(_WDOG_CTRL_WDOGRSTDIS_MASK)
/** Disable watchdog reset output if true */
bool resetDisable;
#endif
} WDOG_Init_TypeDef;
/** Suggested default config for WDOG init structure. */
#if defined( _WDOG_CTRL_WARNSEL_MASK ) \
&& defined( _WDOG_CTRL_WDOGRSTDIS_MASK ) \
&& defined( _WDOG_CTRL_WINSEL_MASK )
#define WDOG_INIT_DEFAULT \
{ \
true, /* Start watchdog when init done */ \
false, /* WDOG not counting during debug halt */ \
false, /* WDOG not counting when in EM2 */ \
false, /* WDOG not counting when in EM3 */ \
false, /* EM4 can be entered */ \
false, /* Do not block disabling LFRCO/LFXO in CMU */ \
false, /* Do not lock WDOG configuration (if locked,
reset needed to unlock) */ \
wdogClkSelULFRCO, /* Select 1kHZ WDOG oscillator */ \
wdogPeriod_256k, /* Set longest possible timeout period */ \
wdogWarnDisable, /* Disable warning interrupt */ \
wdogIllegalWindowDisable, /* Disable illegal window interrupt */ \
false /* Do not disable reset */ \
}
#if defined(_WDOG_CTRL_WARNSEL_MASK) \
&& defined(_WDOG_CTRL_WDOGRSTDIS_MASK) \
&& defined(_WDOG_CTRL_WINSEL_MASK)
#define WDOG_INIT_DEFAULT \
{ \
true, /* Start watchdog when init done */ \
false, /* WDOG not counting during debug halt */ \
false, /* WDOG not counting when in EM2 */ \
false, /* WDOG not counting when in EM3 */ \
false, /* EM4 can be entered */ \
false, /* Do not block disabling LFRCO/LFXO in CMU */ \
false, /* Do not lock WDOG configuration (if locked,
reset needed to unlock) */ \
wdogClkSelULFRCO, /* Select 1kHZ WDOG oscillator */ \
wdogPeriod_256k, /* Set longest possible timeout period */ \
wdogWarnDisable, /* Disable warning interrupt */ \
wdogIllegalWindowDisable, /* Disable illegal window interrupt */ \
false /* Do not disable reset */ \
}
#else
#define WDOG_INIT_DEFAULT \
{ \
true, /* Start watchdog when init done */ \
false, /* WDOG not counting during debug halt */ \
false, /* WDOG not counting when in EM2 */ \
false, /* WDOG not counting when in EM3 */ \
false, /* EM4 can be entered */ \
false, /* Do not block disabling LFRCO/LFXO in CMU */ \
false, /* Do not lock WDOG configuration (if locked,
reset needed to unlock) */ \
wdogClkSelULFRCO, /* Select 1kHZ WDOG oscillator */ \
wdogPeriod_256k /* Set longest possible timeout period */ \
}
#define WDOG_INIT_DEFAULT \
{ \
true, /* Start watchdog when init done */ \
false, /* WDOG not counting during debug halt */ \
false, /* WDOG not counting when in EM2 */ \
false, /* WDOG not counting when in EM3 */ \
false, /* EM4 can be entered */ \
false, /* Do not block disabling LFRCO/LFXO in CMU */ \
false, /* Do not lock WDOG configuration (if locked,
reset needed to unlock) */ \
wdogClkSelULFRCO, /* Select 1kHZ WDOG oscillator */ \
wdogPeriod_256k /* Set longest possible timeout period */ \
}
#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
@ -210,8 +201,7 @@ void WDOGn_Feed(WDOG_TypeDef *wdog);
void WDOGn_Init(WDOG_TypeDef *wdog, const WDOG_Init_TypeDef *init);
void WDOGn_Lock(WDOG_TypeDef *wdog);
#if defined( _WDOG_IF_MASK )
#if defined(_WDOG_IF_MASK)
/***************************************************************************//**
* @brief
* Clear one or more pending WDOG interrupts.
@ -325,7 +315,6 @@ __STATIC_INLINE void WDOGn_IntSet(WDOG_TypeDef *wdog, uint32_t flags)
}
#endif
/** Default WDOG instance for deprecated functions. */
#if !defined(DEFAULT_WDOG)
#if defined(WDOG)
@ -352,7 +341,6 @@ __STATIC_INLINE void WDOG_Enable(bool enable)
WDOGn_Enable(DEFAULT_WDOG, enable);
}
/***************************************************************************//**
* @brief
* Feed the watchdog.
@ -366,7 +354,6 @@ __STATIC_INLINE void WDOG_Feed(void)
WDOGn_Feed(DEFAULT_WDOG);
}
/***************************************************************************//**
* @brief
* Initialize watchdog (assuming the watchdog configuration has not been
@ -385,7 +372,6 @@ __STATIC_INLINE void WDOG_Init(const WDOG_Init_TypeDef *init)
WDOGn_Init(DEFAULT_WDOG, init);
}
/***************************************************************************//**
* @brief
* Lock the watchdog configuration.
@ -399,7 +385,6 @@ __STATIC_INLINE void WDOG_Lock(void)
WDOGn_Lock(DEFAULT_WDOG);
}
/** @} (end addtogroup WDOG) */
/** @} (end addtogroup emlib) */

49
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_acmp.c
* @brief Analog Comparator (ACMP) Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -30,7 +30,6 @@
*
******************************************************************************/
#include "em_acmp.h"
#if defined(ACMP_COUNT) && (ACMP_COUNT > 0)
@ -54,13 +53,17 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** Validation of ACMP register block pointer reference
* for assert statements. */
#if (ACMP_COUNT == 1)
#define ACMP_REF_VALID(ref) ((ref) == ACMP0)
#elif (ACMP_COUNT == 2)
#define ACMP_REF_VALID(ref) (((ref) == ACMP0) || ((ref) == ACMP1))
#elif (ACMP_COUNT == 4)
#define ACMP_REF_VALID(ref) (((ref) == ACMP0) \
|| ((ref) == ACMP1) \
|| ((ref) == ACMP2) \
|| ((ref) == ACMP3))
#else
#error Undefined number of analog comparators (ACMP).
#endif
@ -75,6 +78,8 @@
#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTE_LOCATION_LOC1
#elif defined(_ACMP_ROUTELOC0_OUTLOC_LOC31)
#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTELOC0_OUTLOC_LOC31
#elif defined(_ACMP_ROUTELOC0_OUTLOC_MASK)
#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTELOC0_OUTLOC_MASK
#else
#error Undefined max route locations
#endif
@ -120,8 +125,8 @@ void ACMP_CapsenseInit(ACMP_TypeDef *acmp, const ACMP_CapsenseInit_TypeDef *init
#endif
/* Make sure biasprog is within bounds */
EFM_ASSERT(init->biasProg <=
(_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT));
EFM_ASSERT(init->biasProg
<= (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT));
/* Set control register. No need to set interrupt modes */
acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT)
@ -138,7 +143,7 @@ void ACMP_CapsenseInit(ACMP_TypeDef *acmp, const ACMP_CapsenseInit_TypeDef *init
#if defined(_ACMP_CTRL_ACCURACY_MASK)
| ACMP_CTRL_ACCURACY_HIGH
#endif
;
;
#if defined(_ACMP_HYSTERESIS0_MASK)
acmp->HYSTERESIS0 = (init->vddLevelHigh << _ACMP_HYSTERESIS0_DIVVA_SHIFT)
@ -162,7 +167,7 @@ void ACMP_CapsenseInit(ACMP_TypeDef *acmp, const ACMP_CapsenseInit_TypeDef *init
| ACMP_INPUTSEL_VASEL_VDD
| ACMP_INPUTSEL_NEGSEL_VADIV
#endif
;
;
/* Enable ACMP if requested. */
BUS_RegBitWrite(&(acmp->CTRL), _ACMP_CTRL_EN_SHIFT, init->enable);
@ -197,7 +202,7 @@ void ACMP_CapsenseChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef channel)
/* Set channel as positive channel in ACMP */
BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_POSSEL_MASK,
channel << _ACMP_INPUTSEL_POSSEL_SHIFT);
channel << _ACMP_INPUTSEL_POSSEL_SHIFT);
}
/***************************************************************************//**
@ -312,7 +317,7 @@ void ACMP_GPIOSetup(ACMP_TypeDef *acmp, uint32_t location, bool enable, bool inv
/* Set GPIO inversion */
BUS_RegMaskedWrite(&acmp->CTRL, _ACMP_CTRL_GPIOINV_MASK,
invert << _ACMP_CTRL_GPIOINV_SHIFT);
invert << _ACMP_CTRL_GPIOINV_SHIFT);
#if defined(_ACMP_ROUTE_MASK)
acmp->ROUTE = (location << _ACMP_ROUTE_LOCATION_SHIFT)
@ -377,8 +382,8 @@ void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init)
EFM_ASSERT(ACMP_REF_VALID(acmp));
/* Make sure biasprog is within bounds */
EFM_ASSERT(init->biasProg <=
(_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT));
EFM_ASSERT(init->biasProg
<= (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT));
/* Make sure the ACMP is disable since we might be changing the
* ACMP power source */
@ -411,15 +416,15 @@ void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init)
acmp->INPUTSEL = (0)
#if defined(_ACMP_INPUTSEL_VLPSEL_MASK)
| (init->vlpInput << _ACMP_INPUTSEL_VLPSEL_SHIFT)
| (init->vlpInput << _ACMP_INPUTSEL_VLPSEL_SHIFT)
#endif
#if defined(_ACMP_INPUTSEL_LPREF_MASK)
| (init->lowPowerReferenceEnabled << _ACMP_INPUTSEL_LPREF_SHIFT)
| (init->lowPowerReferenceEnabled << _ACMP_INPUTSEL_LPREF_SHIFT)
#endif
#if defined(_ACMP_INPUTSEL_VDDLEVEL_MASK)
| (init->vddLevel << _ACMP_INPUTSEL_VDDLEVEL_SHIFT)
| (init->vddLevel << _ACMP_INPUTSEL_VDDLEVEL_SHIFT)
#endif
;
;
/* Enable ACMP if requested. */
BUS_RegBitWrite(&(acmp->CTRL), _ACMP_CTRL_EN_SHIFT, init->enable);
@ -443,11 +448,11 @@ void ACMP_VASetup(ACMP_TypeDef *acmp, const ACMP_VAConfig_TypeDef *vaconfig)
EFM_ASSERT(vaconfig->div1 < 64);
BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_VASEL_MASK,
vaconfig->input << _ACMP_INPUTSEL_VASEL_SHIFT);
vaconfig->input << _ACMP_INPUTSEL_VASEL_SHIFT);
BUS_RegMaskedWrite(&acmp->HYSTERESIS0, _ACMP_HYSTERESIS0_DIVVA_MASK,
vaconfig->div0 << _ACMP_HYSTERESIS0_DIVVA_SHIFT);
vaconfig->div0 << _ACMP_HYSTERESIS0_DIVVA_SHIFT);
BUS_RegMaskedWrite(&acmp->HYSTERESIS1, _ACMP_HYSTERESIS1_DIVVA_MASK,
vaconfig->div1 << _ACMP_HYSTERESIS1_DIVVA_SHIFT);
vaconfig->div1 << _ACMP_HYSTERESIS1_DIVVA_SHIFT);
}
#endif
@ -469,11 +474,11 @@ void ACMP_VBSetup(ACMP_TypeDef *acmp, const ACMP_VBConfig_TypeDef *vbconfig)
EFM_ASSERT(vbconfig->div1 < 64);
BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_VBSEL_MASK,
vbconfig->input << _ACMP_INPUTSEL_VBSEL_SHIFT);
vbconfig->input << _ACMP_INPUTSEL_VBSEL_SHIFT);
BUS_RegMaskedWrite(&acmp->HYSTERESIS0, _ACMP_HYSTERESIS0_DIVVB_MASK,
vbconfig->div0 << _ACMP_HYSTERESIS0_DIVVB_SHIFT);
vbconfig->div0 << _ACMP_HYSTERESIS0_DIVVB_SHIFT);
BUS_RegMaskedWrite(&acmp->HYSTERESIS1, _ACMP_HYSTERESIS1_DIVVB_MASK,
vbconfig->div1 << _ACMP_HYSTERESIS1_DIVVB_SHIFT);
vbconfig->div1 << _ACMP_HYSTERESIS1_DIVVB_SHIFT);
}
#endif

415
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_adc.c
* @brief Analog to Digital Converter (ADC) Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -31,7 +31,7 @@
******************************************************************************/
#include "em_adc.h"
#if defined( ADC_COUNT ) && ( ADC_COUNT > 0 )
#if defined(ADC_COUNT) && (ADC_COUNT > 0)
#include "em_assert.h"
#include "em_cmu.h"
@ -59,10 +59,14 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** Validation of ADC register block pointer reference for assert statements. */
#if (ADC_COUNT == 1)
#define ADC_REF_VALID(ref) ((ref) == ADC0)
#elif (ADC_COUNT == 2)
#define ADC_REF_VALID(ref) (((ref) == ADC0) || ((ref) == ADC1))
#endif
/** Max ADC clock */
#if defined( _SILICON_LABS_32B_SERIES_0 )
#if defined(_SILICON_LABS_32B_SERIES_0)
#define ADC_MAX_CLOCK 13000000
#else
#define ADC_MAX_CLOCK 16000000
@ -72,119 +76,119 @@
#define ADC_MIN_CLOCK 32000
/** Helper defines for selecting ADC calibration and DEVINFO register fields. */
#if defined( _DEVINFO_ADC0CAL0_1V25_GAIN_MASK )
#if defined(_DEVINFO_ADC0CAL0_1V25_GAIN_MASK)
#define DEVINFO_ADC0_GAIN1V25_MASK _DEVINFO_ADC0CAL0_1V25_GAIN_MASK
#elif defined( _DEVINFO_ADC0CAL0_GAIN1V25_MASK )
#elif defined(_DEVINFO_ADC0CAL0_GAIN1V25_MASK)
#define DEVINFO_ADC0_GAIN1V25_MASK _DEVINFO_ADC0CAL0_GAIN1V25_MASK
#endif
#if defined( _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT )
#if defined(_DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT)
#define DEVINFO_ADC0_GAIN1V25_SHIFT _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT
#elif defined( _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT )
#elif defined(_DEVINFO_ADC0CAL0_GAIN1V25_SHIFT)
#define DEVINFO_ADC0_GAIN1V25_SHIFT _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT
#endif
#if defined( _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK )
#if defined(_DEVINFO_ADC0CAL0_1V25_OFFSET_MASK)
#define DEVINFO_ADC0_OFFSET1V25_MASK _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK
#elif defined( _DEVINFO_ADC0CAL0_OFFSET1V25_MASK )
#elif defined(_DEVINFO_ADC0CAL0_OFFSET1V25_MASK)
#define DEVINFO_ADC0_OFFSET1V25_MASK _DEVINFO_ADC0CAL0_OFFSET1V25_MASK
#endif
#if defined( _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT )
#if defined(_DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT)
#define DEVINFO_ADC0_OFFSET1V25_SHIFT _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT
#elif defined( _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT )
#elif defined(_DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT)
#define DEVINFO_ADC0_OFFSET1V25_SHIFT _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT
#endif
#if defined( _DEVINFO_ADC0CAL0_2V5_GAIN_MASK )
#if defined(_DEVINFO_ADC0CAL0_2V5_GAIN_MASK)
#define DEVINFO_ADC0_GAIN2V5_MASK _DEVINFO_ADC0CAL0_2V5_GAIN_MASK
#elif defined( _DEVINFO_ADC0CAL0_GAIN2V5_MASK )
#elif defined(_DEVINFO_ADC0CAL0_GAIN2V5_MASK)
#define DEVINFO_ADC0_GAIN2V5_MASK _DEVINFO_ADC0CAL0_GAIN2V5_MASK
#endif
#if defined( _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT )
#if defined(_DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT)
#define DEVINFO_ADC0_GAIN2V5_SHIFT _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT
#elif defined( _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT )
#elif defined(_DEVINFO_ADC0CAL0_GAIN2V5_SHIFT)
#define DEVINFO_ADC0_GAIN2V5_SHIFT _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT
#endif
#if defined( _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK )
#if defined(_DEVINFO_ADC0CAL0_2V5_OFFSET_MASK)
#define DEVINFO_ADC0_OFFSET2V5_MASK _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK
#elif defined( _DEVINFO_ADC0CAL0_OFFSET2V5_MASK )
#elif defined(_DEVINFO_ADC0CAL0_OFFSET2V5_MASK)
#define DEVINFO_ADC0_OFFSET2V5_MASK _DEVINFO_ADC0CAL0_OFFSET2V5_MASK
#endif
#if defined( _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT )
#if defined(_DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT)
#define DEVINFO_ADC0_OFFSET2V5_SHIFT _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT
#elif defined( _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT )
#elif defined(_DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT)
#define DEVINFO_ADC0_OFFSET2V5_SHIFT _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT
#endif
#if defined( _DEVINFO_ADC0CAL1_VDD_GAIN_MASK )
#if defined(_DEVINFO_ADC0CAL1_VDD_GAIN_MASK)
#define DEVINFO_ADC0_GAINVDD_MASK _DEVINFO_ADC0CAL1_VDD_GAIN_MASK
#elif defined( _DEVINFO_ADC0CAL1_GAINVDD_MASK )
#elif defined(_DEVINFO_ADC0CAL1_GAINVDD_MASK)
#define DEVINFO_ADC0_GAINVDD_MASK _DEVINFO_ADC0CAL1_GAINVDD_MASK
#endif
#if defined( _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT )
#if defined(_DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT)
#define DEVINFO_ADC0_GAINVDD_SHIFT _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT
#elif defined( _DEVINFO_ADC0CAL1_GAINVDD_SHIFT )
#elif defined(_DEVINFO_ADC0CAL1_GAINVDD_SHIFT)
#define DEVINFO_ADC0_GAINVDD_SHIFT _DEVINFO_ADC0CAL1_GAINVDD_SHIFT
#endif
#if defined( _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK )
#if defined(_DEVINFO_ADC0CAL1_VDD_OFFSET_MASK)
#define DEVINFO_ADC0_OFFSETVDD_MASK _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK
#elif defined( _DEVINFO_ADC0CAL1_OFFSETVDD_MASK )
#elif defined(_DEVINFO_ADC0CAL1_OFFSETVDD_MASK)
#define DEVINFO_ADC0_OFFSETVDD_MASK _DEVINFO_ADC0CAL1_OFFSETVDD_MASK
#endif
#if defined( _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT )
#if defined(_DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT)
#define DEVINFO_ADC0_OFFSETVDD_SHIFT _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT
#elif defined( _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT )
#elif defined(_DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT)
#define DEVINFO_ADC0_OFFSETVDD_SHIFT _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT
#endif
#if defined( _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK )
#if defined(_DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK)
#define DEVINFO_ADC0_GAIN5VDIFF_MASK _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK
#elif defined( _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK )
#elif defined(_DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK)
#define DEVINFO_ADC0_GAIN5VDIFF_MASK _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK
#endif
#if defined( _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT )
#if defined(_DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT)
#define DEVINFO_ADC0_GAIN5VDIFF_SHIFT _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT
#elif defined( _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT )
#elif defined(_DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT)
#define DEVINFO_ADC0_GAIN5VDIFF_SHIFT _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT
#endif
#if defined( _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK )
#if defined(_DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK)
#define DEVINFO_ADC0_OFFSET5VDIFF_MASK _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK
#elif defined( _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK )
#elif defined(_DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK)
#define DEVINFO_ADC0_OFFSET5VDIFF_MASK _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK
#endif
#if defined( _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT )
#if defined(_DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT)
#define DEVINFO_ADC0_OFFSET5VDIFF_SHIFT _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT
#elif defined( _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT )
#elif defined(_DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT)
#define DEVINFO_ADC0_OFFSET5VDIFF_SHIFT _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT
#endif
#if defined( _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK )
#if defined(_DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK)
#define DEVINFO_ADC0_OFFSET2XVDD_MASK _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK
#elif defined( _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK )
#elif defined(_DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK)
#define DEVINFO_ADC0_OFFSET2XVDD_MASK _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK
#endif
#if defined( _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT )
#if defined(_DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT)
#define DEVINFO_ADC0_OFFSET2XVDD_SHIFT _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT
#elif defined( _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT )
#elif defined(_DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT)
#define DEVINFO_ADC0_OFFSET2XVDD_SHIFT _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT
#endif
#if defined( _SILICON_LABS_32B_SERIES_1 )
#if defined(_SILICON_LABS_32B_SERIES_1)
#define FIX_ADC_TEMP_BIAS_EN
#endif
/** @endcond */
/** @endcond */
/*******************************************************************************
*************************** LOCAL FUNCTIONS *******************************
@ -220,21 +224,19 @@ static void ADC_LoadDevinfoCal(ADC_TypeDef *adc,
uint32_t newCal;
uint32_t mask;
uint32_t shift;
__IM uint32_t * diCalReg;
if (setScanCal)
{
if (setScanCal) {
shift = _ADC_CAL_SCANOFFSET_SHIFT;
mask = ~(_ADC_CAL_SCANOFFSET_MASK
#if defined( _ADC_CAL_SCANOFFSETINV_MASK )
#if defined(_ADC_CAL_SCANOFFSETINV_MASK)
| _ADC_CAL_SCANOFFSETINV_MASK
#endif
| _ADC_CAL_SCANGAIN_MASK);
}
else
{
} else {
shift = _ADC_CAL_SINGLEOFFSET_SHIFT;
mask = ~(_ADC_CAL_SINGLEOFFSET_MASK
#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
#if defined(_ADC_CAL_SINGLEOFFSETINV_MASK)
| _ADC_CAL_SINGLEOFFSETINV_MASK
#endif
| _ADC_CAL_SINGLEGAIN_MASK);
@ -243,59 +245,70 @@ static void ADC_LoadDevinfoCal(ADC_TypeDef *adc,
calReg = adc->CAL & mask;
newCal = 0;
switch (ref)
{
if (adc == ADC0) {
diCalReg = &DEVINFO->ADC0CAL0;
}
#if defined(ADC1)
else if (adc == ADC1) {
diCalReg = &DEVINFO->ADC1CAL0;
}
#endif
else {
return;
}
switch (ref) {
case adcRef1V25:
newCal |= ((DEVINFO->ADC0CAL0 & DEVINFO_ADC0_GAIN1V25_MASK)
newCal |= ((diCalReg[0] & DEVINFO_ADC0_GAIN1V25_MASK)
>> DEVINFO_ADC0_GAIN1V25_SHIFT)
<< _ADC_CAL_SINGLEGAIN_SHIFT;
newCal |= ((DEVINFO->ADC0CAL0 & DEVINFO_ADC0_OFFSET1V25_MASK)
newCal |= ((diCalReg[0] & DEVINFO_ADC0_OFFSET1V25_MASK)
>> DEVINFO_ADC0_OFFSET1V25_SHIFT)
<< _ADC_CAL_SINGLEOFFSET_SHIFT;
#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
newCal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK)
#if defined(_ADC_CAL_SINGLEOFFSETINV_MASK)
newCal |= ((diCalReg[0] & _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK)
>> _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT)
<< _ADC_CAL_SINGLEOFFSETINV_SHIFT;
#endif
break;
case adcRef2V5:
newCal |= ((DEVINFO->ADC0CAL0 & DEVINFO_ADC0_GAIN2V5_MASK)
newCal |= ((diCalReg[0] & DEVINFO_ADC0_GAIN2V5_MASK)
>> DEVINFO_ADC0_GAIN2V5_SHIFT)
<< _ADC_CAL_SINGLEGAIN_SHIFT;
newCal |= ((DEVINFO->ADC0CAL0 & DEVINFO_ADC0_OFFSET2V5_MASK)
newCal |= ((diCalReg[0] & DEVINFO_ADC0_OFFSET2V5_MASK)
>> DEVINFO_ADC0_OFFSET2V5_SHIFT)
<< _ADC_CAL_SINGLEOFFSET_SHIFT;
#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
newCal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK)
#if defined(_ADC_CAL_SINGLEOFFSETINV_MASK)
newCal |= ((diCalReg[0] & _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK)
>> _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT)
<< _ADC_CAL_SINGLEOFFSETINV_SHIFT;
#endif
break;
case adcRefVDD:
newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_GAINVDD_MASK)
newCal |= ((diCalReg[1] & DEVINFO_ADC0_GAINVDD_MASK)
>> DEVINFO_ADC0_GAINVDD_SHIFT)
<< _ADC_CAL_SINGLEGAIN_SHIFT;
newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_OFFSETVDD_MASK)
newCal |= ((diCalReg[1] & DEVINFO_ADC0_OFFSETVDD_MASK)
>> DEVINFO_ADC0_OFFSETVDD_SHIFT)
<< _ADC_CAL_SINGLEOFFSET_SHIFT;
#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
newCal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK)
<< _ADC_CAL_SINGLEOFFSET_SHIFT;
#if defined(_ADC_CAL_SINGLEOFFSETINV_MASK)
newCal |= ((diCalReg[1] & _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK)
>> _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT)
<< _ADC_CAL_SINGLEOFFSETINV_SHIFT;
#endif
break;
case adcRef5VDIFF:
newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_GAIN5VDIFF_MASK)
newCal |= ((diCalReg[1] & DEVINFO_ADC0_GAIN5VDIFF_MASK)
>> DEVINFO_ADC0_GAIN5VDIFF_SHIFT)
<< _ADC_CAL_SINGLEGAIN_SHIFT;
newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_OFFSET5VDIFF_MASK)
newCal |= ((diCalReg[1] & DEVINFO_ADC0_OFFSET5VDIFF_MASK)
>> DEVINFO_ADC0_OFFSET5VDIFF_SHIFT)
<< _ADC_CAL_SINGLEOFFSET_SHIFT;
#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
newCal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK)
#if defined(_ADC_CAL_SINGLEOFFSETINV_MASK)
newCal |= ((diCalReg[1] & _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK)
>> _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT)
<< _ADC_CAL_SINGLEOFFSETINV_SHIFT;
#endif
@ -303,25 +316,25 @@ static void ADC_LoadDevinfoCal(ADC_TypeDef *adc,
case adcRef2xVDD:
/* There is no gain calibration for this reference */
newCal |= ((DEVINFO->ADC0CAL2 & DEVINFO_ADC0_OFFSET2XVDD_MASK)
newCal |= ((diCalReg[2] & DEVINFO_ADC0_OFFSET2XVDD_MASK)
>> DEVINFO_ADC0_OFFSET2XVDD_SHIFT)
<< _ADC_CAL_SINGLEOFFSET_SHIFT;
#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
newCal |= ((DEVINFO->ADC0CAL2 & _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK)
#if defined(_ADC_CAL_SINGLEOFFSETINV_MASK)
newCal |= ((diCalReg[2] & _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK)
>> _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT)
<< _ADC_CAL_SINGLEOFFSETINV_SHIFT;
#endif
break;
#if defined( _ADC_SINGLECTRLX_VREFSEL_VDDXWATT )
#if defined(_ADC_SINGLECTRLX_VREFSEL_VDDXWATT)
case adcRefVddxAtt:
newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_GAINVDD_MASK)
newCal |= ((diCalReg[1] & DEVINFO_ADC0_GAINVDD_MASK)
>> DEVINFO_ADC0_GAINVDD_SHIFT)
<< _ADC_CAL_SINGLEGAIN_SHIFT;
newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_OFFSETVDD_MASK)
newCal |= ((diCalReg[1] & DEVINFO_ADC0_OFFSETVDD_MASK)
>> DEVINFO_ADC0_OFFSETVDD_SHIFT)
<< _ADC_CAL_SINGLEOFFSET_SHIFT;
newCal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK)
newCal |= ((diCalReg[1] & _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK)
>> _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT)
<< _ADC_CAL_SINGLEOFFSETINV_SHIFT;
break;
@ -375,13 +388,10 @@ void ADC_Init(ADC_TypeDef *adc, const ADC_Init_TypeDef *init)
EFM_ASSERT(ADC_REF_VALID(adc));
if (presc == 0)
{
if (presc == 0) {
/* Assume maximum ADC clock for prescaler 0 */
presc = ADC_PrescaleCalc(ADC_MAX_CLOCK, 0);
}
else
{
} else {
/* Check prescaler bounds against ADC_MAX_CLOCK and ADC_MIN_CLOCK */
#if defined(_ADC_CTRL_ADCCLKMODE_MASK)
if (ADC0->CTRL & ADC_CTRL_ADCCLKMODE_SYNC)
@ -397,35 +407,33 @@ void ADC_Init(ADC_TypeDef *adc, const ADC_Init_TypeDef *init)
tmp = ((uint32_t)(init->ovsRateSel) << _ADC_CTRL_OVSRSEL_SHIFT)
| (((uint32_t)(init->timebase) << _ADC_CTRL_TIMEBASE_SHIFT)
& _ADC_CTRL_TIMEBASE_MASK)
& _ADC_CTRL_TIMEBASE_MASK)
| (((uint32_t)(presc) << _ADC_CTRL_PRESC_SHIFT)
& _ADC_CTRL_PRESC_MASK)
#if defined ( _ADC_CTRL_LPFMODE_MASK )
& _ADC_CTRL_PRESC_MASK)
#if defined (_ADC_CTRL_LPFMODE_MASK)
| ((uint32_t)(init->lpfMode) << _ADC_CTRL_LPFMODE_SHIFT)
#endif
| ((uint32_t)(init->warmUpMode) << _ADC_CTRL_WARMUPMODE_SHIFT);
if (init->tailgate)
{
if (init->tailgate) {
tmp |= ADC_CTRL_TAILGATE;
}
adc->CTRL = tmp;
/* Set ADC EM2 clock configuration */
#if defined( _ADC_CTRL_ADCCLKMODE_MASK )
#if defined(_ADC_CTRL_ADCCLKMODE_MASK)
BUS_RegMaskedWrite(&ADC0->CTRL,
_ADC_CTRL_ADCCLKMODE_MASK | _ADC_CTRL_ASYNCCLKEN_MASK,
init->em2ClockConfig);
#endif
#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
/* A debugger can trigger the SCANUF interrupt on EFM32xG1 or EFR32xG1 */
ADC_IntClear(adc, ADC_IFC_SCANUF);
#endif
}
#if defined( _ADC_SCANINPUTSEL_MASK )
#if defined(_ADC_SCANINPUTSEL_MASK)
/***************************************************************************//**
* @brief
* Clear ADC scan input configuration.
@ -445,7 +453,6 @@ void ADC_ScanInputClear(ADC_InitScan_TypeDef *scanInit)
scanInit->scanInputConfig.scanNegSel = _ADC_SCANNEGSEL_RESETVALUE;
}
/***************************************************************************//**
* @brief
* Initialize ADC scan single-ended input configuration.
@ -487,17 +494,12 @@ uint32_t ADC_ScanSingleEndedInputAdd(ADC_InitScan_TypeDef *scanInit,
currentSel = (scanInit->scanInputConfig.scanInputSel >> (inputGroup * 8)) & 0xFF;
/* If none selected */
if (currentSel == ADC_SCANINPUTSEL_GROUP_NONE)
{
if (currentSel == ADC_SCANINPUTSEL_GROUP_NONE) {
scanInit->scanInputConfig.scanInputSel &= ~(0xFF << (inputGroup * 8));
scanInit->scanInputConfig.scanInputSel |= (newSel << (inputGroup * 8));
}
else if (currentSel == newSel)
{
} else if (currentSel == newSel) {
/* Ok, but do nothing. */
}
else
{
} else {
/* Invalid channel range. A range is already selected for this group. */
EFM_ASSERT(false);
}
@ -509,7 +511,6 @@ uint32_t ADC_ScanSingleEndedInputAdd(ADC_InitScan_TypeDef *scanInit,
return scanId;
}
/***************************************************************************//**
* @brief
* Initialize ADC scan differential input configuration.
@ -557,67 +558,47 @@ uint32_t ADC_ScanDifferentialInputAdd(ADC_InitScan_TypeDef *scanInit,
scanInit->diff = true;
/* Set negative ADC input, unless the default is selected. */
if (negInput != adcScanNegInputDefault)
{
if (scanId == 0)
{
if (negInput != adcScanNegInputDefault) {
if (scanId == 0) {
negInputRegMask = _ADC_SCANNEGSEL_INPUT0NEGSEL_MASK;
negInputRegShift = _ADC_SCANNEGSEL_INPUT0NEGSEL_SHIFT;
EFM_ASSERT(inputGroup == 0);
}
else if (scanId == 2)
{
} else if (scanId == 2) {
negInputRegMask = _ADC_SCANNEGSEL_INPUT2NEGSEL_MASK;
negInputRegShift = _ADC_SCANNEGSEL_INPUT2NEGSEL_SHIFT;
EFM_ASSERT(inputGroup == 0);
}
else if (scanId == 4)
{
} else if (scanId == 4) {
negInputRegMask = _ADC_SCANNEGSEL_INPUT4NEGSEL_MASK;
negInputRegShift = _ADC_SCANNEGSEL_INPUT4NEGSEL_SHIFT;
EFM_ASSERT(inputGroup == 0);
}
else if (scanId == 6)
{
} else if (scanId == 6) {
negInputRegMask = _ADC_SCANNEGSEL_INPUT6NEGSEL_MASK;
negInputRegShift = _ADC_SCANNEGSEL_INPUT6NEGSEL_SHIFT;
EFM_ASSERT(inputGroup == 0);
}
else if (scanId == 9)
{
} else if (scanId == 9) {
negInputRegMask = _ADC_SCANNEGSEL_INPUT9NEGSEL_MASK;
negInputRegShift = _ADC_SCANNEGSEL_INPUT9NEGSEL_SHIFT;
EFM_ASSERT(inputGroup == 1);
}
else if (scanId == 11)
{
} else if (scanId == 11) {
negInputRegMask = _ADC_SCANNEGSEL_INPUT11NEGSEL_MASK;
negInputRegShift = _ADC_SCANNEGSEL_INPUT11NEGSEL_SHIFT;
EFM_ASSERT(inputGroup == 1);
}
else if (scanId == 13)
{
} else if (scanId == 13) {
negInputRegMask = _ADC_SCANNEGSEL_INPUT13NEGSEL_MASK;
negInputRegShift = _ADC_SCANNEGSEL_INPUT13NEGSEL_SHIFT;
EFM_ASSERT(inputGroup == 1);
}
else if (scanId == 15)
{
} else if (scanId == 15) {
negInputRegMask = _ADC_SCANNEGSEL_INPUT15NEGSEL_MASK;
negInputRegShift = _ADC_SCANNEGSEL_INPUT15NEGSEL_SHIFT;
EFM_ASSERT(inputGroup == 1);
}
else
{
} else {
/* There is not negative input option for this positive input (negInput is posInput + 1). */
EFM_ASSERT(false);
}
/* Find ADC_SCANNEGSEL_CHxNSEL value for positive input 0, 2, 4 and 6 */
if (inputGroup == 0)
{
switch (negInput)
{
if (inputGroup == 0) {
switch (negInput) {
case adcScanNegInput1:
negInputRegVal = _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1;
break;
@ -639,12 +620,9 @@ uint32_t ADC_ScanDifferentialInputAdd(ADC_InitScan_TypeDef *scanInit,
EFM_ASSERT(false);
break;
}
}
else if (inputGroup == 1)
{
} else if (inputGroup == 1) {
/* Find ADC_SCANNEGSEL_CHxNSEL value for positive input 9, 11, 13 and 15 */
switch (negInput)
{
switch (negInput) {
case adcScanNegInput8:
negInputRegVal = _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8;
break;
@ -666,9 +644,7 @@ uint32_t ADC_ScanDifferentialInputAdd(ADC_InitScan_TypeDef *scanInit,
EFM_ASSERT(false);
break;
}
}
else
{
} else {
/* No alternative negative input for input group > 1 */
EFM_ASSERT(false);
}
@ -681,7 +657,6 @@ uint32_t ADC_ScanDifferentialInputAdd(ADC_InitScan_TypeDef *scanInit,
}
#endif
/***************************************************************************//**
* @brief
* Initialize ADC scan sequence.
@ -720,37 +695,34 @@ void ADC_InitScan(ADC_TypeDef *adc, const ADC_InitScan_TypeDef *init)
ADC_LoadDevinfoCal(adc, init->reference, true);
tmp = 0
#if defined ( _ADC_SCANCTRL_PRSSEL_MASK )
#if defined (_ADC_SCANCTRL_PRSSEL_MASK)
| (init->prsSel << _ADC_SCANCTRL_PRSSEL_SHIFT)
#endif
| (init->acqTime << _ADC_SCANCTRL_AT_SHIFT)
#if defined ( _ADC_SCANCTRL_INPUTMASK_MASK )
#if defined (_ADC_SCANCTRL_INPUTMASK_MASK)
| init->input
#endif
| (init->resolution << _ADC_SCANCTRL_RES_SHIFT);
if (init->prsEnable)
{
if (init->prsEnable) {
tmp |= ADC_SCANCTRL_PRSEN;
}
if (init->leftAdjust)
{
if (init->leftAdjust) {
tmp |= ADC_SCANCTRL_ADJ_LEFT;
}
#if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
#if defined(_ADC_SCANCTRL_INPUTMASK_MASK)
if (init->diff)
#elif defined( _ADC_SCANINPUTSEL_MASK )
#elif defined(_ADC_SCANINPUTSEL_MASK)
if (init->diff)
#endif
{
tmp |= ADC_SCANCTRL_DIFF;
}
if (init->rep)
{
#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
if (init->rep) {
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
/* Scan repeat mode does not work on EFM32JG1, EFM32PG1 or EFR32xG1x devices.
* The errata is called ADC_E211 in the errata document. */
EFM_ASSERT(false);
@ -759,52 +731,47 @@ void ADC_InitScan(ADC_TypeDef *adc, const ADC_InitScan_TypeDef *init)
}
/* Set scan reference. Check if reference configuraion is extended to SCANCTRLX. */
#if defined ( _ADC_SCANCTRLX_VREFSEL_MASK )
if (init->reference & ADC_CTRLX_VREFSEL_REG)
{
#if defined (_ADC_SCANCTRLX_VREFSEL_MASK)
if (init->reference & ADC_CTRLX_VREFSEL_REG) {
/* Select extension register */
tmp |= ADC_SCANCTRL_REF_CONF;
}
else
{
} else {
tmp |= init->reference << _ADC_SCANCTRL_REF_SHIFT;
}
#else
tmp |= init->reference << _ADC_SCANCTRL_REF_SHIFT;
#endif
#if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
#if defined(_ADC_SCANCTRL_INPUTMASK_MASK)
tmp |= init->input;
#endif
adc->SCANCTRL = tmp;
/* Update SINGLECTRLX for reference select and PRS select */
#if defined ( _ADC_SCANCTRLX_MASK )
#if defined (_ADC_SCANCTRLX_MASK)
tmp = adc->SCANCTRLX & ~(_ADC_SCANCTRLX_VREFSEL_MASK
| _ADC_SCANCTRLX_PRSSEL_MASK
| _ADC_SCANCTRLX_FIFOOFACT_MASK);
if (init->reference & ADC_CTRLX_VREFSEL_REG)
{
| _ADC_SCANCTRLX_PRSSEL_MASK
| _ADC_SCANCTRLX_FIFOOFACT_MASK);
if (init->reference & ADC_CTRLX_VREFSEL_REG) {
tmp |= (init->reference & ~ADC_CTRLX_VREFSEL_REG) << _ADC_SCANCTRLX_VREFSEL_SHIFT;
}
tmp |= init->prsSel << _ADC_SCANCTRLX_PRSSEL_SHIFT;
if (init->fifoOverwrite)
{
if (init->fifoOverwrite) {
tmp |= ADC_SCANCTRLX_FIFOOFACT_OVERWRITE;
}
adc->SCANCTRLX = tmp;
#endif
#if defined( _ADC_CTRL_SCANDMAWU_MASK )
#if defined(_ADC_CTRL_SCANDMAWU_MASK)
BUS_RegBitWrite(&adc->CTRL, _ADC_CTRL_SCANDMAWU_SHIFT, init->scanDmaEm2Wu);
#endif
/* Write scan input configuration */
#if defined( _ADC_SCANINPUTSEL_MASK )
#if defined(_ADC_SCANINPUTSEL_MASK)
/* Check for valid scan input configuration. Use @ref ADC_ScanInputClear()
@ref ADC_ScanSingleEndedInputAdd() and @ref ADC_ScanDifferentialInputAdd() to set
scan input configuration. */
@ -815,14 +782,13 @@ void ADC_InitScan(ADC_TypeDef *adc, const ADC_InitScan_TypeDef *init)
#endif
/* Assert for any APORT bus conflicts programming errors */
#if defined( _ADC_BUSCONFLICT_MASK )
#if defined(_ADC_BUSCONFLICT_MASK)
tmp = adc->BUSREQ;
EFM_ASSERT(!(tmp & adc->BUSCONFLICT));
EFM_ASSERT(!(adc->STATUS & _ADC_STATUS_PROGERR_MASK));
#endif
}
/***************************************************************************//**
* @brief
* Initialize single ADC sample conversion.
@ -864,62 +830,54 @@ void ADC_InitSingle(ADC_TypeDef *adc, const ADC_InitSingle_TypeDef *init)
ADC_LoadDevinfoCal(adc, init->reference, false);
tmp = 0
#if defined( _ADC_SINGLECTRL_PRSSEL_MASK )
#if defined(_ADC_SINGLECTRL_PRSSEL_MASK)
| (init->prsSel << _ADC_SINGLECTRL_PRSSEL_SHIFT)
#endif
| (init->acqTime << _ADC_SINGLECTRL_AT_SHIFT)
#if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
#if defined(_ADC_SINGLECTRL_INPUTSEL_MASK)
| (init->input << _ADC_SINGLECTRL_INPUTSEL_SHIFT)
#endif
#if defined( _ADC_SINGLECTRL_POSSEL_MASK )
#if defined(_ADC_SINGLECTRL_POSSEL_MASK)
| (init->posSel << _ADC_SINGLECTRL_POSSEL_SHIFT)
#endif
#if defined( _ADC_SINGLECTRL_NEGSEL_MASK )
#if defined(_ADC_SINGLECTRL_NEGSEL_MASK)
| (init->negSel << _ADC_SINGLECTRL_NEGSEL_SHIFT)
#endif
| ((uint32_t)(init->resolution) << _ADC_SINGLECTRL_RES_SHIFT);
if (init->prsEnable)
{
if (init->prsEnable) {
tmp |= ADC_SINGLECTRL_PRSEN;
}
if (init->leftAdjust)
{
if (init->leftAdjust) {
tmp |= ADC_SINGLECTRL_ADJ_LEFT;
}
if (init->diff)
{
if (init->diff) {
tmp |= ADC_SINGLECTRL_DIFF;
}
if (init->rep)
{
if (init->rep) {
tmp |= ADC_SINGLECTRL_REP;
}
#if defined( _ADC_SINGLECTRL_POSSEL_TEMP )
#if defined(_ADC_SINGLECTRL_POSSEL_TEMP)
/* Force at least 8 cycle acquisition time when reading internal temperature
* sensor with 1.25V reference */
if ((init->posSel == adcPosSelTEMP)
&& (init->reference == adcRef1V25)
&& (init->acqTime < adcAcqTime8))
{
&& (init->reference == adcRef1V25)
&& (init->acqTime < adcAcqTime8)) {
tmp = (tmp & ~_ADC_SINGLECTRL_AT_MASK)
| (adcAcqTime8 << _ADC_SINGLECTRL_AT_SHIFT);
| (adcAcqTime8 << _ADC_SINGLECTRL_AT_SHIFT);
}
#endif
/* Set single reference. Check if reference configuraion is extended to SINGLECTRLX. */
#if defined ( _ADC_SINGLECTRLX_MASK )
if (init->reference & ADC_CTRLX_VREFSEL_REG)
{
#if defined (_ADC_SINGLECTRLX_MASK)
if (init->reference & ADC_CTRLX_VREFSEL_REG) {
/* Select extension register */
tmp |= ADC_SINGLECTRL_REF_CONF;
}
else
{
} else {
tmp |= (init->reference << _ADC_SINGLECTRL_REF_SHIFT);
}
#else
@ -928,19 +886,17 @@ void ADC_InitSingle(ADC_TypeDef *adc, const ADC_InitSingle_TypeDef *init)
adc->SINGLECTRL = tmp;
/* Update SINGLECTRLX for reference select and PRS select */
#if defined ( _ADC_SINGLECTRLX_VREFSEL_MASK )
tmp = adc->SINGLECTRLX & (_ADC_SINGLECTRLX_VREFSEL_MASK
| _ADC_SINGLECTRLX_PRSSEL_MASK
| _ADC_SINGLECTRLX_FIFOOFACT_MASK);
if (init->reference & ADC_CTRLX_VREFSEL_REG)
{
#if defined (_ADC_SINGLECTRLX_VREFSEL_MASK)
tmp = adc->SINGLECTRLX & ~(_ADC_SINGLECTRLX_VREFSEL_MASK
| _ADC_SINGLECTRLX_PRSSEL_MASK
| _ADC_SINGLECTRLX_FIFOOFACT_MASK);
if (init->reference & ADC_CTRLX_VREFSEL_REG) {
tmp |= ((init->reference & ~ADC_CTRLX_VREFSEL_REG) << _ADC_SINGLECTRLX_VREFSEL_SHIFT);
}
tmp |= ((init->prsSel << _ADC_SINGLECTRLX_PRSSEL_SHIFT));
if (init->fifoOverwrite)
{
if (init->fifoOverwrite) {
tmp |= ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE;
}
@ -948,34 +904,30 @@ void ADC_InitSingle(ADC_TypeDef *adc, const ADC_InitSingle_TypeDef *init)
#endif
/* Set DMA availability in EM2 */
#if defined( _ADC_CTRL_SINGLEDMAWU_MASK )
#if defined(_ADC_CTRL_SINGLEDMAWU_MASK)
BUS_RegBitWrite(&adc->CTRL, _ADC_CTRL_SINGLEDMAWU_SHIFT, init->singleDmaEm2Wu);
#endif
#if defined( _ADC_BIASPROG_GPBIASACC_MASK ) && defined( FIX_ADC_TEMP_BIAS_EN )
if (init->posSel == adcPosSelTEMP)
{
#if defined(_ADC_BIASPROG_GPBIASACC_MASK) && defined(FIX_ADC_TEMP_BIAS_EN)
if (init->posSel == adcPosSelTEMP) {
/* ADC should always use low accuracy setting when reading the internal
* temperature sensor on platform 2 generation 1 devices. Using high
* accuracy setting can introduce a glitch. */
BUS_RegBitWrite(&adc->BIASPROG, _ADC_BIASPROG_GPBIASACC_SHIFT, 1);
}
else
{
} else {
BUS_RegBitWrite(&adc->BIASPROG, _ADC_BIASPROG_GPBIASACC_SHIFT, 0);
}
#endif
/* Assert for any APORT bus conflicts programming errors */
#if defined( _ADC_BUSCONFLICT_MASK )
#if defined(_ADC_BUSCONFLICT_MASK)
tmp = adc->BUSREQ;
EFM_ASSERT(!(tmp & adc->BUSCONFLICT));
EFM_ASSERT(!(adc->STATUS & _ADC_STATUS_PROGERR_MASK));
#endif
}
#if defined( _ADC_SCANDATAX_MASK )
#if defined(_ADC_SCANDATAX_MASK)
/***************************************************************************//**
* @brief
* Get scan result and scan select ID.
@ -1004,7 +956,6 @@ uint32_t ADC_DataIdScanGet(ADC_TypeDef *adc, uint32_t *scanId)
}
#endif
/***************************************************************************//**
* @brief
* Calculate prescaler value used to determine ADC clock.
@ -1027,31 +978,25 @@ uint8_t ADC_PrescaleCalc(uint32_t adcFreq, uint32_t hfperFreq)
uint32_t ret;
/* Make sure selected ADC clock is within valid range */
if (adcFreq > ADC_MAX_CLOCK)
{
if (adcFreq > ADC_MAX_CLOCK) {
adcFreq = ADC_MAX_CLOCK;
}
else if (adcFreq < ADC_MIN_CLOCK)
{
} else if (adcFreq < ADC_MIN_CLOCK) {
adcFreq = ADC_MIN_CLOCK;
}
/* Use current HFPER frequency? */
if (!hfperFreq)
{
if (!hfperFreq) {
hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER);
}
ret = (hfperFreq + adcFreq - 1) / adcFreq;
if (ret)
{
if (ret) {
ret--;
}
return (uint8_t)ret;
}
/***************************************************************************//**
* @brief
* Reset ADC to same state as after a HW reset.
@ -1068,29 +1013,29 @@ void ADC_Reset(ADC_TypeDef *adc)
/* Stop conversions, before resetting other registers. */
adc->CMD = ADC_CMD_SINGLESTOP | ADC_CMD_SCANSTOP;
adc->SINGLECTRL = _ADC_SINGLECTRL_RESETVALUE;
#if defined( _ADC_SINGLECTRLX_MASK )
#if defined(_ADC_SINGLECTRLX_MASK)
adc->SINGLECTRLX = _ADC_SINGLECTRLX_RESETVALUE;
#endif
adc->SCANCTRL = _ADC_SCANCTRL_RESETVALUE;
#if defined( _ADC_SCANCTRLX_MASK )
#if defined(_ADC_SCANCTRLX_MASK)
adc->SCANCTRLX = _ADC_SCANCTRLX_RESETVALUE;
#endif
adc->CTRL = _ADC_CTRL_RESETVALUE;
adc->IEN = _ADC_IEN_RESETVALUE;
adc->IFC = _ADC_IFC_MASK;
adc->BIASPROG = _ADC_BIASPROG_RESETVALUE;
#if defined( _ADC_SCANMASK_MASK )
#if defined(_ADC_SCANMASK_MASK)
adc->SCANMASK = _ADC_SCANMASK_RESETVALUE;
#endif
#if defined( _ADC_SCANINPUTSEL_MASK )
#if defined(_ADC_SCANINPUTSEL_MASK)
adc->SCANINPUTSEL = _ADC_SCANINPUTSEL_RESETVALUE;
#endif
#if defined( _ADC_SCANNEGSEL_MASK )
#if defined(_ADC_SCANNEGSEL_MASK)
adc->SCANNEGSEL = _ADC_SCANNEGSEL_RESETVALUE;
#endif
/* Clear data FIFOs */
#if defined( _ADC_SINGLEFIFOCLEAR_MASK )
#if defined(_ADC_SINGLEFIFOCLEAR_MASK)
adc->SINGLEFIFOCLEAR |= ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR;
adc->SCANFIFOCLEAR |= ADC_SCANFIFOCLEAR_SCANFIFOCLEAR;
#endif
@ -1099,12 +1044,11 @@ void ADC_Reset(ADC_TypeDef *adc)
ADC_LoadDevinfoCal(adc, adcRef1V25, false);
ADC_LoadDevinfoCal(adc, adcRef1V25, true);
#if defined( _ADC_SCANINPUTSEL_MASK )
#if defined(_ADC_SCANINPUTSEL_MASK)
/* Do not reset route register, setting should be done independently */
#endif
}
/***************************************************************************//**
* @brief
* Calculate timebase value in order to get a timebase providing at least 1us.
@ -1117,24 +1061,22 @@ void ADC_Reset(ADC_TypeDef *adc)
******************************************************************************/
uint8_t ADC_TimebaseCalc(uint32_t hfperFreq)
{
if (!hfperFreq)
{
if (!hfperFreq) {
hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER);
/* Just in case, make sure we get non-zero freq for below calculation */
if (!hfperFreq)
{
if (!hfperFreq) {
hfperFreq = 1;
}
}
#if defined( _EFM32_GIANT_FAMILY ) || defined( _EFM32_WONDER_FAMILY )
#if defined(_SILICON_LABS_32B_SERIES_0) \
&& (defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY))
/* Handle errata on Giant Gecko, max TIMEBASE is 5 bits wide or max 0x1F */
/* cycles. This will give a warmp up time of e.g. 0.645us, not the */
/* required 1us when operating at 48MHz. One must also increase acqTime */
/* to compensate for the missing clock cycles, adding up to 1us in total.*/
/* See reference manual for details. */
if ( hfperFreq > 32000000 )
{
if ( hfperFreq > 32000000 ) {
hfperFreq = 32000000;
}
#endif
@ -1146,7 +1088,6 @@ uint8_t ADC_TimebaseCalc(uint32_t hfperFreq)
return (uint8_t)(hfperFreq - 1);
}
/** @} (end addtogroup ADC) */
/** @} (end addtogroup emlib) */
#endif /* defined(ADC_COUNT) && (ADC_COUNT > 0) */

290
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_aes.c
* @brief Advanced Encryption Standard (AES) accelerator peripheral API.
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -141,21 +141,18 @@ void AES_CBC128(uint8_t *out,
/* Number of blocks to process */
len /= AES_BLOCKSIZE;
#if defined( AES_CTRL_KEYBUFEN )
if (key)
{
#if defined(AES_CTRL_KEYBUFEN)
if (key) {
/* Load key into high key for key buffer usage */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->KEYHA = __REV(_key[i]);
}
}
#endif
if (encrypt)
{
if (encrypt) {
/* Enable encryption with auto start using XOR */
#if defined( AES_CTRL_KEYBUFEN )
#if defined(AES_CTRL_KEYBUFEN)
AES->CTRL = AES_CTRL_KEYBUFEN | AES_CTRL_XORSTART;
#else
AES->CTRL = AES_CTRL_XORSTART;
@ -163,25 +160,21 @@ void AES_CBC128(uint8_t *out,
/* Load initialization vector, since writing to DATA, it will */
/* not trigger encryption. */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->DATA = __REV(_iv[i]);
}
/* Encrypt data */
while (len--)
{
#if !defined( AES_CTRL_KEYBUFEN )
while (len--) {
#if !defined(AES_CTRL_KEYBUFEN)
/* Load key */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->KEYLA = __REV(_key[i]);
}
#endif
/* Load data and trigger encryption */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->XORDATA = __REV(_in[i]);
}
_in += 4;
@ -191,42 +184,35 @@ void AES_CBC128(uint8_t *out,
;
/* Save encrypted data */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA);
}
_out += 4;
}
}
else
{
} else {
/* Select decryption mode */
#if defined( AES_CTRL_KEYBUFEN )
#if defined(AES_CTRL_KEYBUFEN)
AES->CTRL = AES_CTRL_DECRYPT | AES_CTRL_KEYBUFEN | AES_CTRL_DATASTART;
#else
AES->CTRL = AES_CTRL_DECRYPT | AES_CTRL_DATASTART;
#endif
/* Copy init vector to previous buffer to avoid special handling */
for (i = 0; i < 4; i++)
{
for (i = 0; i < 4; i++) {
prev[i] = _iv[i];
}
/* Decrypt data */
while (len--)
{
#if !defined( AES_CTRL_KEYBUFEN )
while (len--) {
#if !defined(AES_CTRL_KEYBUFEN)
/* Load key */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->KEYLA = __REV(_key[i]);
}
#endif
/* Load data and trigger decryption */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->DATA = __REV(_in[i]);
}
@ -236,8 +222,7 @@ void AES_CBC128(uint8_t *out,
/* In order to avoid additional buffer, we use HW directly for XOR and buffer */
/* (Writing to XORDATA will not trigger encoding, triggering enabled on DATA.) */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->XORDATA = __REV(prev[i]);
prev[i] = _in[i];
}
@ -245,8 +230,7 @@ void AES_CBC128(uint8_t *out,
/* Then fetch decrypted data, we have to do it in a separate loop */
/* due to internal auto-shifting of words */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA);
}
_out += 4;
@ -254,8 +238,7 @@ void AES_CBC128(uint8_t *out,
}
}
#if defined( AES_CTRL_AES256 )
#if defined(AES_CTRL_AES256)
/***************************************************************************//**
* @brief
* Cipher-block chaining (CBC) cipher mode encryption/decryption, 256 bit key.
@ -307,24 +290,20 @@ void AES_CBC256(uint8_t *out,
/* Number of blocks to process */
len /= AES_BLOCKSIZE;
if (encrypt)
{
if (encrypt) {
/* Enable encryption with auto start using XOR */
AES->CTRL = AES_CTRL_AES256 | AES_CTRL_XORSTART;
/* Load initialization vector, since writing to DATA, it will */
/* not trigger encryption. */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->DATA = __REV(_iv[i]);
}
/* Encrypt data */
while (len--)
{
while (len--) {
/* Load key and data and trigger encryption */
for (i = 3, j = 7; i >= 0; i--, j--)
{
for (i = 3, j = 7; i >= 0; i--, j--) {
AES->KEYLA = __REV(_key[j]);
AES->KEYHA = __REV(_key[i]);
/* Write data last, since will trigger encryption on last iteration */
@ -337,30 +316,24 @@ void AES_CBC256(uint8_t *out,
;
/* Save encrypted data */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA);
}
_out += 4;
}
}
else
{
} else {
/* Select decryption mode */
AES->CTRL = AES_CTRL_AES256 | AES_CTRL_DECRYPT | AES_CTRL_DATASTART;
/* Copy init vector to previous buffer to avoid special handling */
for (i = 0; i < 4; i++)
{
for (i = 0; i < 4; i++) {
prev[i] = _iv[i];
}
/* Decrypt data */
while (len--)
{
while (len--) {
/* Load key and data and trigger decryption */
for (i = 3, j = 7; i >= 0; i--, j--)
{
for (i = 3, j = 7; i >= 0; i--, j--) {
AES->KEYLA = __REV(_key[j]);
AES->KEYHA = __REV(_key[i]);
/* Write data last, since will trigger encryption on last iteration */
@ -372,8 +345,7 @@ void AES_CBC256(uint8_t *out,
;
/* In order to avoid additional buffer, we use HW directly for XOR and buffer */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->XORDATA = __REV(prev[i]);
prev[i] = _in[i];
}
@ -381,8 +353,7 @@ void AES_CBC256(uint8_t *out,
/* Then fetch decrypted data, we have to do it in a separate loop */
/* due to internal auto-shifting of words */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA);
}
_out += 4;
@ -391,7 +362,6 @@ void AES_CBC256(uint8_t *out,
}
#endif
/***************************************************************************//**
* @brief
* Cipher feedback (CFB) cipher mode encryption/decryption, 128 bit key.
@ -467,16 +437,15 @@ void AES_CFB128(uint8_t *out,
EFM_ASSERT(!(len % AES_BLOCKSIZE));
#if defined( AES_CTRL_KEYBUFEN )
#if defined(AES_CTRL_KEYBUFEN)
AES->CTRL = AES_CTRL_KEYBUFEN | AES_CTRL_DATASTART;
#else
AES->CTRL = AES_CTRL_DATASTART;
#endif
#if defined( AES_CTRL_KEYBUFEN )
#if defined(AES_CTRL_KEYBUFEN)
/* Load key into high key for key buffer usage */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->KEYHA = __REV(_key[i]);
}
#endif
@ -484,32 +453,25 @@ void AES_CFB128(uint8_t *out,
/* Encrypt/decrypt data */
data = _iv;
len /= AES_BLOCKSIZE;
while (len--)
{
#if !defined( AES_CTRL_KEYBUFEN )
while (len--) {
#if !defined(AES_CTRL_KEYBUFEN)
/* Load key */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->KEYLA = __REV(_key[i]);
}
#endif
/* Load data and trigger encryption */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->DATA = __REV(data[i]);
}
/* Do some required processing before waiting for completion */
if (encrypt)
{
if (encrypt) {
data = _out;
}
else
{
} else {
/* Must copy current ciphertext block since it may be overwritten */
for (i = 0; i < 4; i++)
{
for (i = 0; i < 4; i++) {
tmp[i] = _in[i];
}
data = tmp;
@ -520,8 +482,7 @@ void AES_CFB128(uint8_t *out,
;
/* Save encrypted/decrypted data */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA) ^ _in[i];
}
_out += 4;
@ -529,8 +490,7 @@ void AES_CFB128(uint8_t *out,
}
}
#if defined( AES_CTRL_AES256 )
#if defined(AES_CTRL_AES256)
/***************************************************************************//**
* @brief
* Cipher feedback (CFB) cipher mode encryption/decryption, 256 bit key.
@ -583,11 +543,9 @@ void AES_CFB256(uint8_t *out,
/* Encrypt/decrypt data */
data = _iv;
len /= AES_BLOCKSIZE;
while (len--)
{
while (len--) {
/* Load key and block to be encrypted/decrypted */
for (i = 3, j = 7; i >= 0; i--, j--)
{
for (i = 3, j = 7; i >= 0; i--, j--) {
AES->KEYLA = __REV(_key[j]);
AES->KEYHA = __REV(_key[i]);
/* Write data last, since will trigger encryption on last iteration */
@ -595,15 +553,11 @@ void AES_CFB256(uint8_t *out,
}
/* Do some required processing before waiting for completion */
if (encrypt)
{
if (encrypt) {
data = _out;
}
else
{
} else {
/* Must copy current ciphertext block since it may be overwritten */
for (i = 0; i < 4; i++)
{
for (i = 0; i < 4; i++) {
tmp[i] = _in[i];
}
data = tmp;
@ -613,8 +567,7 @@ void AES_CFB256(uint8_t *out,
;
/* Save encrypted/decrypted data */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA) ^ _in[i];
}
_out += 4;
@ -623,7 +576,6 @@ void AES_CFB256(uint8_t *out,
}
#endif
/***************************************************************************//**
* @brief
* Counter (CTR) cipher mode encryption/decryption, 128 bit key.
@ -700,18 +652,16 @@ void AES_CTR128(uint8_t *out,
EFM_ASSERT(!(len % AES_BLOCKSIZE));
EFM_ASSERT(ctrFunc);
#if defined( AES_CTRL_KEYBUFEN )
#if defined(AES_CTRL_KEYBUFEN)
AES->CTRL = AES_CTRL_KEYBUFEN | AES_CTRL_DATASTART;
#else
AES->CTRL = AES_CTRL_DATASTART;
#endif
#if defined( AES_CTRL_KEYBUFEN )
if (key)
{
#if defined(AES_CTRL_KEYBUFEN)
if (key) {
/* Load key into high key for key buffer usage */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->KEYHA = __REV(_key[i]);
}
}
@ -719,19 +669,16 @@ void AES_CTR128(uint8_t *out,
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
while (len--)
{
#if !defined( AES_CTRL_KEYBUFEN )
while (len--) {
#if !defined(AES_CTRL_KEYBUFEN)
/* Load key */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->KEYLA = __REV(_key[i]);
}
#endif
/* Load ctr to be encrypted/decrypted */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->DATA = __REV(_ctr[i]);
}
/* Increment ctr for next use */
@ -742,8 +689,7 @@ void AES_CTR128(uint8_t *out,
;
/* Save encrypted/decrypted data */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA) ^ _in[i];
}
_out += 4;
@ -751,8 +697,7 @@ void AES_CTR128(uint8_t *out,
}
}
#if defined( AES_CTRL_AES256 )
#if defined(AES_CTRL_AES256)
/***************************************************************************//**
* @brief
* Counter (CTR) cipher mode encryption/decryption, 256 bit key.
@ -804,11 +749,9 @@ void AES_CTR256(uint8_t *out,
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
while (len--)
{
while (len--) {
/* Load key and block to be encrypted/decrypted */
for (i = 3, j = 7; i >= 0; i--, j--)
{
for (i = 3, j = 7; i >= 0; i--, j--) {
AES->KEYLA = __REV(_key[j]);
AES->KEYHA = __REV(_key[i]);
/* Write data last, since will trigger encryption on last iteration */
@ -822,8 +765,7 @@ void AES_CTR256(uint8_t *out,
;
/* Save encrypted/decrypted data */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA) ^ _in[i];
}
_out += 4;
@ -832,7 +774,6 @@ void AES_CTR256(uint8_t *out,
}
#endif
/***************************************************************************//**
* @brief
* Update last 32 bits of 128 bit counter, by incrementing with 1.
@ -854,7 +795,6 @@ void AES_CTRUpdate32Bit(uint8_t *ctr)
_ctr[3] = __REV(__REV(_ctr[3]) + 1);
}
/***************************************************************************//**
* @brief
* Generate 128 bit decryption key from 128 bit encryption key. The decryption
@ -877,8 +817,7 @@ void AES_DecryptKey128(uint8_t *out, const uint8_t *in)
const uint32_t *_in = (const uint32_t *)in;
/* Load key */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->KEYLA = __REV(_in[i]);
}
@ -892,14 +831,12 @@ void AES_DecryptKey128(uint8_t *out, const uint8_t *in)
;
/* Save decryption key */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->KEYLA);
}
}
#if defined( AES_CTRL_AES256 )
#if defined(AES_CTRL_AES256)
/***************************************************************************//**
* @brief
* Generate 256 bit decryption key from 256 bit encryption key. The decryption
@ -923,8 +860,7 @@ void AES_DecryptKey256(uint8_t *out, const uint8_t *in)
const uint32_t *_in = (const uint32_t *)in;
/* Load key */
for (i = 3, j = 7; i >= 0; i--, j--)
{
for (i = 3, j = 7; i >= 0; i--, j--) {
AES->KEYLA = __REV(_in[j]);
AES->KEYHA = __REV(_in[i]);
}
@ -938,15 +874,13 @@ void AES_DecryptKey256(uint8_t *out, const uint8_t *in)
;
/* Save decryption key */
for (i = 3, j = 7; i >= 0; i--, j--)
{
for (i = 3, j = 7; i >= 0; i--, j--) {
_out[j] = __REV(AES->KEYLA);
_out[i] = __REV(AES->KEYHA);
}
}
#endif
/***************************************************************************//**
* @brief
* Electronic Codebook (ECB) cipher mode encryption/decryption, 128 bit key.
@ -1011,27 +945,23 @@ void AES_ECB128(uint8_t *out,
EFM_ASSERT(!(len % AES_BLOCKSIZE));
#if defined( AES_CTRL_KEYBUFEN )
#if defined(AES_CTRL_KEYBUFEN)
/* Load key into high key for key buffer usage */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->KEYHA = __REV(_key[i]);
}
#endif
if (encrypt)
{
if (encrypt) {
/* Select encryption mode */
#if defined( AES_CTRL_KEYBUFEN )
#if defined(AES_CTRL_KEYBUFEN)
AES->CTRL = AES_CTRL_KEYBUFEN | AES_CTRL_DATASTART;
#else
AES->CTRL = AES_CTRL_DATASTART;
#endif
}
else
{
} else {
/* Select decryption mode */
#if defined( AES_CTRL_KEYBUFEN )
#if defined(AES_CTRL_KEYBUFEN)
AES->CTRL = AES_CTRL_DECRYPT | AES_CTRL_KEYBUFEN | AES_CTRL_DATASTART;
#else
AES->CTRL = AES_CTRL_DECRYPT | AES_CTRL_DATASTART;
@ -1040,19 +970,16 @@ void AES_ECB128(uint8_t *out,
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
while (len--)
{
#if !defined( AES_CTRL_KEYBUFEN )
while (len--) {
#if !defined(AES_CTRL_KEYBUFEN)
/* Load key */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->KEYLA = __REV(_key[i]);
}
#endif
/* Load block to be encrypted/decrypted */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->DATA = __REV(_in[i]);
}
_in += 4;
@ -1062,16 +989,14 @@ void AES_ECB128(uint8_t *out,
;
/* Save encrypted/decrypted data */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA);
}
_out += 4;
}
}
#if defined( AES_CTRL_AES256 )
#if defined(AES_CTRL_AES256)
/***************************************************************************//**
* @brief
* Electronic Codebook (ECB) cipher mode encryption/decryption, 256 bit key.
@ -1113,24 +1038,19 @@ void AES_ECB256(uint8_t *out,
EFM_ASSERT(!(len % AES_BLOCKSIZE));
if (encrypt)
{
if (encrypt) {
/* Select encryption mode */
AES->CTRL = AES_CTRL_AES256 | AES_CTRL_DATASTART;
}
else
{
} else {
/* Select decryption mode */
AES->CTRL = AES_CTRL_DECRYPT | AES_CTRL_AES256 | AES_CTRL_DATASTART;
}
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
while (len--)
{
while (len--) {
/* Load key and block to be encrypted/decrypted */
for (i = 3, j = 7; i >= 0; i--, j--)
{
for (i = 3, j = 7; i >= 0; i--, j--) {
AES->KEYLA = __REV(_key[j]);
AES->KEYHA = __REV(_key[i]);
/* Write data last, since will trigger encryption on last iteration */
@ -1143,8 +1063,7 @@ void AES_ECB256(uint8_t *out,
;
/* Save encrypted/decrypted data */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA);
}
_out += 4;
@ -1152,7 +1071,6 @@ void AES_ECB256(uint8_t *out,
}
#endif
/***************************************************************************//**
* @brief
* Output feedback (OFB) cipher mode encryption/decryption, 128 bit key.
@ -1225,7 +1143,7 @@ void AES_OFB128(uint8_t *out,
EFM_ASSERT(!(len % AES_BLOCKSIZE));
/* Select encryption mode, trigger explicitly by command */
#if defined( AES_CTRL_KEYBUFEN )
#if defined(AES_CTRL_KEYBUFEN)
AES->CTRL = AES_CTRL_KEYBUFEN;
#else
AES->CTRL = 0;
@ -1233,9 +1151,8 @@ void AES_OFB128(uint8_t *out,
/* Load key into high key for key buffer usage */
/* Load initialization vector */
for (i = 3; i >= 0; i--)
{
#if defined( AES_CTRL_KEYBUFEN )
for (i = 3; i >= 0; i--) {
#if defined(AES_CTRL_KEYBUFEN)
AES->KEYHA = __REV(_key[i]);
#endif
AES->DATA = __REV(_iv[i]);
@ -1243,12 +1160,10 @@ void AES_OFB128(uint8_t *out,
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
while (len--)
{
#if !defined( AES_CTRL_KEYBUFEN )
while (len--) {
#if !defined(AES_CTRL_KEYBUFEN)
/* Load key */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->KEYLA = __REV(_key[i]);
}
#endif
@ -1260,8 +1175,7 @@ void AES_OFB128(uint8_t *out,
;
/* Save encrypted/decrypted data */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA) ^ _in[i];
}
_out += 4;
@ -1269,8 +1183,7 @@ void AES_OFB128(uint8_t *out,
}
}
#if defined( AES_CTRL_AES256 )
#if defined(AES_CTRL_AES256)
/***************************************************************************//**
* @brief
* Output feedback (OFB) cipher mode encryption/decryption, 256 bit key.
@ -1315,18 +1228,15 @@ void AES_OFB256(uint8_t *out,
AES->CTRL = AES_CTRL_AES256;
/* Load initialization vector */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
AES->DATA = __REV(_iv[i]);
}
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
while (len--)
{
while (len--) {
/* Load key */
for (i = 3, j = 7; i >= 0; i--, j--)
{
for (i = 3, j = 7; i >= 0; i--, j--) {
AES->KEYLA = __REV(_key[j]);
AES->KEYHA = __REV(_key[i]);
}
@ -1338,8 +1248,7 @@ void AES_OFB256(uint8_t *out,
;
/* Save encrypted/decrypted data */
for (i = 3; i >= 0; i--)
{
for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA) ^ _in[i];
}
_out += 4;
@ -1348,7 +1257,6 @@ void AES_OFB256(uint8_t *out,
}
#endif
/** @} (end addtogroup AES) */
/** @} (end addtogroup emlib) */
#endif /* defined(AES_COUNT) && (AES_COUNT > 0) */

7
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_assert.c
* @brief Assert API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -72,8 +72,7 @@ void assertEFM(const char *file, int line)
(void)file; /* Unused parameter */
(void)line; /* Unused parameter */
while (true)
{
while (true) {
}
}
#endif /* DEBUG_EFM */

40
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_burtc.c
* @brief Backup Real Time Counter (BURTC) Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -30,7 +30,6 @@
*
******************************************************************************/
#include "em_burtc.h"
#if defined(BURTC_PRESENT)
@ -78,7 +77,6 @@ __STATIC_INLINE uint32_t divToLog2(uint32_t div)
return log2;
}
/***************************************************************************//**
* @brief
* Wait for ongoing sync of register(s) to low frequency domain to complete.
@ -93,8 +91,7 @@ __STATIC_INLINE void regSync(uint32_t mask)
activated, or when no clock is selected for the BURTC. If no clock is
selected, then the sync is done once the clock source is set. */
if ((BURTC->FREEZE & BURTC_FREEZE_REGFREEZE)
|| ((BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK) == BURTC_CTRL_CLKSEL_NONE))
{
|| ((BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK) == BURTC_CTRL_CLKSEL_NONE)) {
return;
}
/* Wait for any pending previous write operation to have been completed */
@ -104,7 +101,6 @@ __STATIC_INLINE void regSync(uint32_t mask)
}
/** @endcond */
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
@ -140,13 +136,13 @@ void BURTC_Init(const BURTC_Init_TypeDef *burtcInit)
/* Note! Giant Gecko revision C errata, do NOT use LPCOMP=7 */
EFM_ASSERT(burtcInit->lowPowerComp <= 6);
/* You cannot enable the BURTC if mode is set to disabled */
EFM_ASSERT((burtcInit->enable == false) ||
((burtcInit->enable == true)
&& (burtcInit->mode != burtcModeDisable)));
EFM_ASSERT((burtcInit->enable == false)
|| ((burtcInit->enable == true)
&& (burtcInit->mode != burtcModeDisable)));
/* Low power mode is only available with LFRCO or LFXO as clock source */
EFM_ASSERT((burtcInit->clkSel != burtcClkSelULFRCO)
|| ((burtcInit->clkSel == burtcClkSelULFRCO)
&& (burtcInit->lowPowerMode == burtcLPDisable)));
&& (burtcInit->lowPowerMode == burtcLPDisable)));
/* Calculate prescaler value from clock divider input */
/* Note! If clock select (clkSel) is ULFRCO, a clock divisor (clkDiv) of
@ -155,8 +151,7 @@ void BURTC_Init(const BURTC_Init_TypeDef *burtcInit)
presc = divToLog2(burtcInit->clkDiv);
/* Make sure all registers are updated simultaneously */
if (burtcInit->enable)
{
if (burtcInit->enable) {
BURTC_FreezeEnable(true);
}
@ -184,8 +179,7 @@ void BURTC_Init(const BURTC_Init_TypeDef *burtcInit)
BURTC->CTRL = ctrl;
/* Enable BURTC and counter */
if (burtcInit->enable)
{
if (burtcInit->enable) {
/* To enable BURTC counter, we need to disable reset */
BURTC_Enable(true);
@ -194,7 +188,6 @@ void BURTC_Init(const BURTC_Init_TypeDef *burtcInit)
}
}
/***************************************************************************//**
* @brief Set BURTC compare channel
*
@ -216,7 +209,6 @@ void BURTC_CompareSet(unsigned int comp, uint32_t value)
BURTC->COMP0 = value;
}
/***************************************************************************//**
* @brief Get BURTC compare value
*
@ -233,7 +225,6 @@ uint32_t BURTC_CompareGet(unsigned int comp)
return BURTC->COMP0;
}
/***************************************************************************//**
* @brief Reset counter
******************************************************************************/
@ -244,7 +235,6 @@ void BURTC_CounterReset(void)
BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0);
}
/***************************************************************************//**
* @brief
* Restore BURTC to reset state
@ -263,7 +253,6 @@ void BURTC_Reset(void)
BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState);
}
/***************************************************************************//**
* @brief
* Get clock frequency of the BURTC.
@ -280,16 +269,12 @@ uint32_t BURTC_ClockFreqGet(void)
clkSel = BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK;
clkDiv = (BURTC->CTRL & _BURTC_CTRL_PRESC_MASK) >> _BURTC_CTRL_PRESC_SHIFT;
switch (clkSel)
{
switch (clkSel) {
/** Ultra low frequency (1 kHz) clock */
case BURTC_CTRL_CLKSEL_ULFRCO:
if (_BURTC_CTRL_PRESC_DIV1 == clkDiv)
{
if (_BURTC_CTRL_PRESC_DIV1 == clkDiv) {
frequency = 2000; /* 2KHz when clock divisor is 1. */
}
else
{
} else {
frequency = SystemULFRCOClockGet(); /* 1KHz when divisor is different
from 1. */
}
@ -312,7 +297,6 @@ uint32_t BURTC_ClockFreqGet(void)
return frequency;
}
/** @} (end addtogroup BURTC) */
/** @} (end addtogroup emlib) */

912
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_can.c Normal file
View File

@ -0,0 +1,912 @@
/***************************************************************************//**
* @file em_can.c
* @brief Controller Area Network API
* @version 5.3.3
*******************************************************************************
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
* obligation to support this Software. Silicon Labs is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Silicon Labs will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#include "em_can.h"
#include "em_common.h"
#include "em_assert.h"
#include "em_cmu.h"
#include <stddef.h>
#if defined(CAN_COUNT) && (CAN_COUNT > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/* Macros to use the ID field in the CANn_MIRx_ARB register as a 11 bit
* standard id. The register field can be used for both an 11 bit standard
* id and a 29 bit extended id. */
#define _CAN_MIR_ARB_STD_ID_SHIFT 18
#define _CAN_MIR_MASK_STD_SHIFT 18
#define _CAN_MIR_ARB_STD_ID_MASK 0x1FFC0000UL
#define _CAN_MIR_ARB_STD_ID_MAX 0x7FFUL // = 2^11 - 1
#if (CAN_COUNT == 2)
#define CAN_VALID(can) ((can == CAN0) || (can == CAN1))
#elif (CAN_COUNT == 1)
#define CAN_VALID(can) (can == CAN0)
#else
#error "The actual number of CAN busses is not supported."
#endif
/** @endcond */
/***************************************************************************//**
* @addtogroup emlib
* @{
******************************************************************************/
/***************************************************************************//**
* @addtogroup CAN
* @brief Controller Area Network API
*
* @details The Controller Area Network Interface Bus (CAN) implements a
* multi-master serial bus for connecting microcontrollers and devices, also
* known as nodes, to communicate with each other in applications without a host
* computer. CAN is a message-based protocol, designed originally for automotive
* applications, but meanwhile used also in many other surroundings.
* The complexity of the node can range from a simple I/O device up to an
* embedded computer with a CAN interface and sophisticated software. The node
* may also be a gateway allowing a standard computer to communicate over a USB
* or Ethernet port to the devices on a CAN network. Devices are connected to
* the bus through a host processor, a CAN controller, and a CAN transceiver.
*
* @include em_can_send_example.c
*
* @{
******************************************************************************/
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
/***************************************************************************//**
* @brief
* Initialize CAN.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] init
* Pointer to CAN initialization structure.
******************************************************************************/
void CAN_Init(CAN_TypeDef *can, const CAN_Init_TypeDef *init)
{
EFM_ASSERT(CAN_VALID(can));
CAN_Enable(can, false);
can->CTRL = _CAN_CTRL_TEST_MASK;
can->TEST = _CAN_TEST_RESETVALUE;
if (init->resetMessages) {
CAN_ResetMessages(can, 0);
}
can->CTRL = CAN_CTRL_INIT;
CAN_SetBitTiming(can,
init->bitrate,
init->propagationTimeSegment,
init->phaseBufferSegment1,
init->phaseBufferSegment2,
init->synchronisationJumpWidth);
CAN_Enable(can, init->enable);
}
/***************************************************************************//**
* @brief
* Get the CAN module frequency.
*
* @details
* There is an internal prescaler of 2 inside the CAN module.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* Clock value
******************************************************************************/
uint32_t CAN_GetClockFrequency(CAN_TypeDef *can)
{
#if defined CAN0
if (can == CAN0) {
return CMU_ClockFreqGet(cmuClock_CAN0) / 2;
}
#endif
#if defined CAN1
if (can == CAN1) {
return CMU_ClockFreqGet(cmuClock_CAN1) / 2;
}
#endif
EFM_ASSERT(false);
return 0;
}
/***************************************************************************//**
* @brief
* Read a Message Object to find if a message was lost ; reset the
* 'Message Lost' flag.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
* @param[in] msgNum
* Message number of the Message Object, [1 - 32].
*
* @return
* true if a message was lost, false otherwise.
******************************************************************************/
bool CAN_MessageLost(CAN_TypeDef *can, uint8_t interface, uint8_t msgNum)
{
CAN_MIR_TypeDef * mir = &can->MIR[interface];
bool messageLost;
/* Make sure msgNum is in the correct range */
EFM_ASSERT((msgNum > 0) && (msgNum <= 32));
CAN_ReadyWait(can, interface);
/* Set which registers to read from the RAM */
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD_READ
| CAN_MIR_CMDMASK_CONTROL
| CAN_MIR_CMDMASK_CLRINTPND;
/* Send reading request and wait (3 to 6 cpu cycle) */
CAN_SendRequest(can, interface, msgNum, true);
messageLost = mir->CTRL & _CAN_MIR_CTRL_MESSAGEOF_MASK;
if (messageLost) {
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD | CAN_MIR_CMDMASK_CONTROL;
/* Reset the 'MessageLost' bit */
mir->CTRL &= ~_CAN_MIR_CTRL_MESSAGEOF_MASK;
/* Send reading request and wait (3 to 6 cpu cycle) */
CAN_SendRequest(can, interface, msgNum, true);
}
/* Return the state of the MESSAGEOF bit */
return messageLost;
}
/***************************************************************************//**
* @brief
* Set the ROUTE registers.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] active
* Boolean to activate or not the ROUTE registers.
*
* @param[in] pinRxLoc
* Location of the rx pin.
*
* @param[in] pinTxLoc
* Location of the tx pin.
******************************************************************************/
void CAN_SetRoute(CAN_TypeDef *can,
bool active,
uint16_t pinRxLoc,
uint16_t pinTxLoc)
{
if (active) {
/* Set the ROUTE register */
can->ROUTE = CAN_ROUTE_TXPEN
| (pinRxLoc << _CAN_ROUTE_RXLOC_SHIFT)
| (pinTxLoc << _CAN_ROUTE_TXLOC_SHIFT);
} else {
/* Deactivate the ROUTE register */
can->ROUTE = 0x0;
}
}
/***************************************************************************//**
* @brief
* Set the bitrate and its parameters
*
* @details
* There are multiple parameters which need to be properly configured.
* Please refer to the reference manual for a detailed description.
* Careful : the BRP (Baud Rate Prescaler) is calculated by:
* 'brp = freq / (period * bitrate);'. freq is the frequency of the CAN
* device, period the time of transmission of a bit. The result is an uint32_t
* hence it's truncated, causing an approximation error. This error is non
* negligeable when period is high, bitrate is high and freq is low.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] bitrate
* Wanted bitrate on the CAN bus.
*
* @param[in] propagationTimeSegment
* Value for the Propagation Time Segment.
*
* @param[in] phaseBufferSegment1
* Value for the Phase Buffer Segment 1.
*
* @param[in] phaseBufferSegment2
* Value for the Phase Buffer Segment 2.
*
* @param[in] synchronisationJumpWidth
* Value for the Synchronisation Jump Width.
******************************************************************************/
void CAN_SetBitTiming(CAN_TypeDef *can,
uint32_t bitrate,
uint16_t propagationTimeSegment,
uint16_t phaseBufferSegment1,
uint16_t phaseBufferSegment2,
uint16_t synchronisationJumpWidth)
{
uint32_t sum, brp, period, freq, brpHigh, brpLow;
/* Verification that the parameters are within range */
EFM_ASSERT((propagationTimeSegment <= 8) && (propagationTimeSegment > 0));
EFM_ASSERT((phaseBufferSegment1 <= 8) && (phaseBufferSegment1 > 0));
EFM_ASSERT((phaseBufferSegment2 <= 8) && (phaseBufferSegment2 > 0));
EFM_ASSERT(bitrate > 0);
EFM_ASSERT((synchronisationJumpWidth <= phaseBufferSegment1)
&& (synchronisationJumpWidth <= phaseBufferSegment2)
&& (synchronisationJumpWidth > 0));
/* propagationTimeSegment is counted as part of phaseBufferSegment1 in the
BITTIMING register */
sum = phaseBufferSegment1 + propagationTimeSegment;
/* period is the total length of one CAN bit. 1 is the Sync_seg */
period = 1 + sum + phaseBufferSegment2;
freq = CAN_GetClockFrequency(can);
brp = freq / (period * bitrate);
EFM_ASSERT(brp != 0);
/* -1 because the hardware reads 'written value + 1' */
brp = brp - 1;
/* brp is divided between two registers */
brpHigh = brp / 64;
brpLow = brp % 64;
/* Checking register limit */
EFM_ASSERT(brpHigh <= 15);
bool enabled = CAN_IsEnabled(can);
/* Enable access to the bittiming registers */
can->CTRL |= CAN_CTRL_CCE | CAN_CTRL_INIT;
can->BITTIMING = (brpLow << _CAN_BITTIMING_BRP_SHIFT)
| ((synchronisationJumpWidth - 1) << _CAN_BITTIMING_SJW_SHIFT)
| ((sum - 1) << _CAN_BITTIMING_TSEG1_SHIFT)
| ((phaseBufferSegment2 - 1) << _CAN_BITTIMING_TSEG2_SHIFT);
can->BRPE = brpHigh;
if (enabled) {
can->CTRL &= ~(_CAN_CTRL_CCE_MASK | _CAN_CTRL_INIT_MASK);
} else {
can->CTRL &= ~_CAN_CTRL_CCE_MASK;
}
}
/***************************************************************************//**
* @brief
* Set the CAN operation mode.
*
* @details
* In Init mode, the CAN module is deactivated. Reset of the Messages in all
* the other modes to be sure that there are no leftover data and that they
* need to be configured before being of use.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] mode
* Mode of operation : Init, Normal, Loopback, SilentLoopback, Silent, Basic.
******************************************************************************/
void CAN_SetMode(CAN_TypeDef *can, CAN_Mode_TypeDef mode)
{
switch (mode) {
case canModeNormal:
can->CTRL |= _CAN_CTRL_TEST_MASK;
can->TEST = _CAN_TEST_RESETVALUE;
can->CTRL &= ~_CAN_CTRL_TEST_MASK;
can->CTRL = _CAN_CTRL_EIE_MASK
| _CAN_CTRL_SIE_MASK
| _CAN_CTRL_IE_MASK;
break;
case canModeBasic:
can->CTRL = _CAN_CTRL_EIE_MASK
| _CAN_CTRL_SIE_MASK
| _CAN_CTRL_IE_MASK
| CAN_CTRL_TEST;
can->TEST = CAN_TEST_BASIC;
break;
case canModeLoopBack:
can->CTRL = _CAN_CTRL_EIE_MASK
| _CAN_CTRL_SIE_MASK
| _CAN_CTRL_IE_MASK
| CAN_CTRL_TEST;
can->TEST = CAN_TEST_LBACK;
break;
case canModeSilentLoopBack:
can->CTRL = _CAN_CTRL_EIE_MASK
| _CAN_CTRL_SIE_MASK
| _CAN_CTRL_IE_MASK
| CAN_CTRL_TEST;
can->TEST = CAN_TEST_LBACK | CAN_TEST_SILENT;
break;
case canModeSilent:
can->CTRL = _CAN_CTRL_EIE_MASK
| _CAN_CTRL_SIE_MASK
| _CAN_CTRL_IE_MASK
| CAN_CTRL_TEST;
can->TEST = CAN_TEST_SILENT;
break;
default:
break;
}
}
/***************************************************************************//**
* @brief
* Set the Id and the filter for a specific Message Object.
*
* @details
* The Init bit have to be 0 to use this function.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
* @param[in] useMask
* Boolean to choose whether or not to use the masks.
*
* @param[in] message
* Message Object
*
* @param[in] wait
* If true, wait for the end of the transfer between the MIRx registers and
* the RAM to exit. If false, exit immediately, the transfer can still be
* in progress.
******************************************************************************/
void CAN_SetIdAndFilter(CAN_TypeDef *can,
uint8_t interface,
bool useMask,
const CAN_MessageObject_TypeDef *message,
bool wait)
{
/* Make sure msgNum is in the correct range */
EFM_ASSERT((message->msgNum > 0) && (message->msgNum <= 32));
CAN_MIR_TypeDef * mir = &can->MIR[interface];
CAN_ReadyWait(can, interface);
/* Set which registers to read from the RAM */
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD_READ
| CAN_MIR_CMDMASK_ARBACC
| CAN_MIR_CMDMASK_CONTROL;
/* Send reading request and wait (3 to 6 cpu cycle) */
CAN_SendRequest(can, interface, message->msgNum, true);
/* Reset MSGVAL */
mir->CMDMASK |= CAN_MIR_CMDMASK_WRRD;
mir->ARB &= ~(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT);
CAN_SendRequest(can, interface, message->msgNum, true);
/* Set which registers to write to the RAM */
mir->CMDMASK |= CAN_MIR_CMDMASK_MASKACC;
/* Set UMASK bit */
BUS_RegBitWrite(&mir->CTRL, _CAN_MIR_CTRL_UMASK_SHIFT, useMask);
/* Configure the id */
if (message->extended) {
EFM_ASSERT(message->id <= _CAN_MIR_ARB_ID_MASK);
mir->ARB = (mir->ARB & ~_CAN_MIR_ARB_ID_MASK)
| (message->id << _CAN_MIR_ARB_ID_SHIFT)
| (uint32_t)(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT)
| CAN_MIR_ARB_XTD_EXT;
} else {
EFM_ASSERT(message->id <= _CAN_MIR_ARB_STD_ID_MAX);
mir->ARB = (mir->ARB & ~(_CAN_MIR_ARB_ID_MASK | CAN_MIR_ARB_XTD_STD))
| (message->id << _CAN_MIR_ARB_STD_ID_SHIFT)
| (uint32_t)(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT);
}
if (message->extendedMask) {
mir->MASK = (message->mask << _CAN_MIR_MASK_MASK_SHIFT);
} else {
mir->MASK = (message->mask << _CAN_MIR_MASK_STD_SHIFT)
& _CAN_MIR_ARB_STD_ID_MASK;
}
/* Configure the masks */
mir->MASK |= (message->extendedMask << _CAN_MIR_MASK_MXTD_SHIFT)
| (message->directionMask << _CAN_MIR_MASK_MDIR_SHIFT);
/* Send writing request */
CAN_SendRequest(can, interface, message->msgNum, wait);
}
/***************************************************************************//**
* @brief
* Configure valid, tx/rx, remoteTransfer for a specific Message Object.
*
* @details
* The Init bit have to be 0 to use this function.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
* @param[in] msgNum
* Message number of this Message Object, [1 - 32].
*
* @param[in] valid
* true if Message Object is valid, false otherwise.
*
* @param[in] tx
* true if Message Object is used for transmission, false if used for
* reception.
*
* @param[in] remoteTransfer
* true if Message Object is used for remote transmission, false otherwise.
*
* @param[in] endOfBuffer
* true if it is for a single Message Object or the end of a fifo buffer,
* false if the Message Object is part of a fifo buffer and not the last.
*
* @param[in] wait
* If true, wait for the end of the transfer between the MIRx registers and
* the RAM to exit. If false, exit immediately, the transfer can still be
* in progress.
******************************************************************************/
void CAN_ConfigureMessageObject(CAN_TypeDef *can,
uint8_t interface,
uint8_t msgNum,
bool valid,
bool tx,
bool remoteTransfer,
bool endOfBuffer,
bool wait)
{
CAN_MIR_TypeDef * mir = &can->MIR[interface];
/* Make sure msgNum is in the correct range */
EFM_ASSERT((msgNum > 0) && (msgNum <= 32));
CAN_ReadyWait(can, interface);
/* Set which registers to read from the RAM */
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD_READ
| CAN_MIR_CMDMASK_ARBACC
| CAN_MIR_CMDMASK_CONTROL;
/* Send reading request and wait (3 to 6 cpu cycle) */
CAN_SendRequest(can, interface, msgNum, true);
/* Set which registers to write to the RAM */
mir->CMDMASK |= CAN_MIR_CMDMASK_WRRD;
/* Configure valid message and direction */
mir->ARB = (mir->ARB & ~(_CAN_MIR_ARB_DIR_MASK | _CAN_MIR_ARB_MSGVAL_MASK))
| (valid << _CAN_MIR_ARB_MSGVAL_SHIFT)
| (tx << _CAN_MIR_ARB_DIR_SHIFT);
/* Set eob bit, rx and tx interrupts */
mir->CTRL = (endOfBuffer << _CAN_MIR_CTRL_EOB_SHIFT)
| _CAN_MIR_CTRL_TXIE_MASK
| _CAN_MIR_CTRL_RXIE_MASK
| (remoteTransfer << _CAN_MIR_CTRL_RMTEN_SHIFT);
/* Send writing request */
CAN_SendRequest(can, interface, msgNum, wait);
}
/***************************************************************************//**
* @brief
* Send the data from the Message Object message.
*
* @details
* If message is configured as tx and remoteTransfer = 0, calling this function
* will send the data of this Message Object if its parameters are correct.
* If message is tx and remoteTransfer = 1, this function will set the data of
* message to the RAM and exit, the data will be automatically sent after
* reception of a remote frame.
* If message is rx and remoteTransfer = 1, this function will send a remote
* frame to the corresponding id.
* If message is rx and remoteTransfer = 0, the user shouldn't call this
* function. It will also send a remote frame.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
* @param[in] message
* Message Object
*
* @param[in] wait
* If true, wait for the end of the transfer between the MIRx registers and
* the RAM to exit. If false, exit immediately, the transfer can still be
* in progress.
******************************************************************************/
void CAN_SendMessage(CAN_TypeDef *can,
uint8_t interface,
const CAN_MessageObject_TypeDef *message,
bool wait)
{
CAN_MIR_TypeDef * mir = &can->MIR[interface];
/* Make sure msgNum is in the correct range */
EFM_ASSERT((message->msgNum > 0) && (message->msgNum <= 32));
/* Make sure dlc is in the correct range */
EFM_ASSERT(message->dlc <= _CAN_MIR_CTRL_DLC_MASK);
CAN_ReadyWait(can, interface);
/* Set LEC to unused value to be sure it is reset to 0 after sending */
BUS_RegMaskedWrite(&can->STATUS, _CAN_STATUS_LEC_MASK, 0x7);
/* Set which registers to read from the RAM */
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD_READ
| CAN_MIR_CMDMASK_ARBACC
| CAN_MIR_CMDMASK_CONTROL;
/* Send reading request and wait (3 to 6 cpu cycle) */
CAN_SendRequest(can, interface, message->msgNum, true);
/* Reset MSGVAL */
mir->CMDMASK |= CAN_MIR_CMDMASK_WRRD;
mir->ARB &= ~(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT);
CAN_SendRequest(can, interface, message->msgNum, true);
/* Set which registers to write to the RAM */
mir->CMDMASK |= CAN_MIR_CMDMASK_DATAA
| CAN_MIR_CMDMASK_DATAB;
/* If tx = 1 and remoteTransfer = 1, nothing is sent */
if ( ((mir->CTRL & _CAN_MIR_CTRL_RMTEN_MASK) == 0)
|| ((mir->ARB & _CAN_MIR_ARB_DIR_MASK) == _CAN_MIR_ARB_DIR_RX)) {
mir->CTRL |= CAN_MIR_CTRL_TXRQST;
/* DATAVALID is set only if it is not sending a remote message */
if ((mir->CTRL & _CAN_MIR_CTRL_RMTEN_MASK) == 0) {
mir->CTRL |= CAN_MIR_CTRL_DATAVALID;
}
}
/* Set the Data length Code */
mir->CTRL = (mir->CTRL & ~_CAN_MIR_CTRL_DLC_MASK)
| message->dlc;
/* Configure the id */
if (message->extended) {
EFM_ASSERT(message->id <= _CAN_MIR_ARB_ID_MASK);
mir->ARB = (mir->ARB & ~_CAN_MIR_ARB_ID_MASK)
| (message->id << _CAN_MIR_ARB_ID_SHIFT)
| (uint32_t)(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT)
| CAN_MIR_ARB_XTD_EXT;
} else {
EFM_ASSERT(message->id <= _CAN_MIR_ARB_STD_ID_MAX);
mir->ARB = (mir->ARB & ~(_CAN_MIR_ARB_ID_MASK | _CAN_MIR_ARB_XTD_MASK))
| (uint32_t)(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT)
| (message->id << _CAN_MIR_ARB_STD_ID_SHIFT)
| CAN_MIR_ARB_XTD_STD;
}
/* Set the data */
CAN_WriteData(can, interface, message);
/* Send writing request */
CAN_SendRequest(can, interface, message->msgNum, wait);
}
/***************************************************************************//**
* @brief
* Read the data from a Message Object in the RAM and store it in message.
*
* @details
* Read all the information from the RAM on this Message Object : the data but
* also the configuration of the other registers.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
* @param[in] message
* Message Object
******************************************************************************/
void CAN_ReadMessage(CAN_TypeDef *can,
uint8_t interface,
CAN_MessageObject_TypeDef *message)
{
CAN_MIR_TypeDef * mir = &can->MIR[interface];
uint32_t buffer;
uint32_t i;
/* Make sure msgNum is in the correct range */
EFM_ASSERT((message->msgNum > 0) && (message->msgNum <= 32));
CAN_ReadyWait(can, interface);
/* Set which registers to read from the RAM */
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD_READ
| CAN_MIR_CMDMASK_MASKACC
| CAN_MIR_CMDMASK_ARBACC
| CAN_MIR_CMDMASK_CONTROL
| CAN_MIR_CMDMASK_CLRINTPND
| CAN_MIR_CMDMASK_TXRQSTNEWDAT
| CAN_MIR_CMDMASK_DATAA
| CAN_MIR_CMDMASK_DATAB;
/* Send reading request and wait (3 to 6 cpu cycle) */
CAN_SendRequest(can, interface, message->msgNum, true);
/* Get dlc from the control register */
message->dlc = ((mir->CTRL & _CAN_MIR_CTRL_DLC_MASK) >> _CAN_MIR_CTRL_DLC_SHIFT);
/* Make sure dlc is in the correct range */
EFM_ASSERT(message->dlc <= 8);
/* Copy the data from the MIR registers to the Message Object message */
buffer = mir->DATAL;
for (i = 0; i < SL_MIN(message->dlc, 4U); ++i) {
message->data[i] = buffer & 0xFF;
buffer = buffer >> 8;
}
if (message->dlc > 3) {
buffer = mir->DATAH;
for (i = 0; i < message->dlc - 4U; ++i) {
message->data[i + 4] = buffer & 0xFF;
buffer = buffer >> 8;
}
}
}
/***************************************************************************//**
* @brief
* Abort the sending of a message
*
* @details
* Set the TXRQST of the CTRL register to 0. Doesn't touch the data ot the
* others parameters. The user can reuse CAN_SendMessage() to send the object
* after using CAN_AbortSendMessage().
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
* @param[in] msgNum
* Message number of this Message Object, [1 - 32].
*
* @param[in] wait
* If true, wait for the end of the transfer between the MIRx registers and
* the RAM to exit. If false, exit immediately, the transfer can still be
* in progress.
******************************************************************************/
void CAN_AbortSendMessage(CAN_TypeDef *can,
uint8_t interface,
uint8_t msgNum,
bool wait)
{
/* Make sure msgNum is in the correct range */
EFM_ASSERT((msgNum > 0) && (msgNum <= 32));
CAN_MIR_TypeDef * mir = &can->MIR[interface];
CAN_ReadyWait(can, interface);
/* Set which registers to write to the RAM */
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD
| CAN_MIR_CMDMASK_ARBACC;
/* Set TXRQST bit to 0 */
mir->ARB &= ~_CAN_MIR_CTRL_TXRQST_MASK;
/* Send writing request */
CAN_SendRequest(can, interface, msgNum, wait);
}
/***************************************************************************//**
* @brief
* Reset all the Message Objects and set their data to 0.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
******************************************************************************/
void CAN_ResetMessages(CAN_TypeDef *can, uint8_t interface)
{
CAN_MIR_TypeDef * mir = &can->MIR[interface];
CAN_ReadyWait(can, interface);
/* Set which registers to read from the RAM */
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD
| CAN_MIR_CMDMASK_MASKACC
| CAN_MIR_CMDMASK_ARBACC
| CAN_MIR_CMDMASK_CONTROL
| CAN_MIR_CMDMASK_DATAA
| CAN_MIR_CMDMASK_DATAB;
mir->MASK = _CAN_MIR_MASK_RESETVALUE;
mir->ARB = _CAN_MIR_ARB_RESETVALUE;
mir->CTRL = _CAN_MIR_CTRL_RESETVALUE;
mir->DATAL = 0x00000000;
mir->DATAH = 0x00000000;
/* Write each reset Message Object to the RAM */
for (int i = 1; i <= 32; ++i) {
CAN_SendRequest(can, interface, i, true);
}
}
/***************************************************************************//**
* @brief
* Set all the CAN registers to RESETVALUE. Leave the CAN Device disabled.
*
* @param[in] can
* Pointer to CAN peripheral register block.
******************************************************************************/
void CAN_Reset(CAN_TypeDef *can)
{
CAN_ReadyWait(can, 0);
CAN_ReadyWait(can, 1);
CAN_Enable(can, false);
can->STATUS = _CAN_STATUS_RESETVALUE;
can->CTRL |= _CAN_CTRL_CCE_MASK;
can->BITTIMING = _CAN_BITTIMING_RESETVALUE;
can->CTRL &= ~_CAN_CTRL_CCE_MASK;
can->CTRL |= _CAN_CTRL_TEST_MASK;
can->TEST = _CAN_TEST_RESETVALUE;
can->CTRL &= ~_CAN_CTRL_TEST_MASK;
can->BRPE = _CAN_BRPE_RESETVALUE;
can->CONFIG = _CAN_CONFIG_RESETVALUE;
can->IF0IFS = _CAN_IF0IFS_RESETVALUE;
can->IF0IFC = _CAN_IF0IFC_RESETVALUE;
can->IF0IEN = _CAN_IF0IEN_RESETVALUE;
can->IF1IFS = _CAN_IF1IF_RESETVALUE;
can->IF1IFC = _CAN_IF1IFC_RESETVALUE;
can->IF1IEN = _CAN_IF1IEN_RESETVALUE;
can->ROUTE = _CAN_ROUTE_RESETVALUE;
for (int i = 0; i < 2; i++) {
can->MIR[i].CMDMASK = _CAN_MIR_CMDMASK_RESETVALUE;
can->MIR[i].MASK = _CAN_MIR_MASK_RESETVALUE;
can->MIR[i].ARB = _CAN_MIR_ARB_RESETVALUE;
can->MIR[i].CTRL = _CAN_MIR_CTRL_RESETVALUE;
can->MIR[i].DATAL = _CAN_MIR_DATAL_RESETVALUE;
can->MIR[i].DATAH = _CAN_MIR_DATAH_RESETVALUE;
can->MIR[i].CMDREQ = _CAN_MIR_CMDREQ_RESETVALUE;
}
}
/***************************************************************************//**
* @brief
* Write the data from message to the MIRx registers
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
* @param[in] message
* Message Object
******************************************************************************/
void CAN_WriteData(CAN_TypeDef *can,
uint8_t interface,
const CAN_MessageObject_TypeDef *message)
{
CAN_MIR_TypeDef * mir = &can->MIR[interface];
uint8_t data[8] = { 0 };
size_t length = SL_MIN(8, message->dlc);
for (size_t i = 0; i < length; i++) {
data[i] = message->data[i];
}
CAN_ReadyWait(can, interface);
mir->DATAL = (data[3] << 24)
| (data[2] << 16)
| (data[1] << 8)
| (data[0] << 0);
mir->DATAH = (data[7] << 24)
| (data[6] << 16)
| (data[5] << 8)
| (data[4] << 0);
}
/***************************************************************************//**
* @brief
* Send request for writing or reading the RAM of Message Object msgNum.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
* @param[in] msgNum
* Message number of the Message Object, [1 - 32].
*
* @param[in] wait
* If true, wait for the end of the transfer between the MIRx registers and
* the RAM to exit. If false, exit immediately, the transfer can still be
* in progress.
******************************************************************************/
void CAN_SendRequest(CAN_TypeDef *can,
uint8_t interface,
uint8_t msgNum,
bool wait)
{
CAN_MIR_TypeDef * mir = &can->MIR[interface];
/* Make sure msgNum is in the correct range */
EFM_ASSERT((msgNum > 0) && (msgNum <= 32));
/* Make sure the MIRx registers aren't busy */
CAN_ReadyWait(can, interface);
/* Write msgNum to the CMDREQ register */
mir->CMDREQ = msgNum << _CAN_MIR_CMDREQ_MSGNUM_SHIFT;
if (wait) {
CAN_ReadyWait(can, interface);
}
}
/** @} (end addtogroup CAN) */
/** @} (end addtogroup emlib) */
#endif /* defined(CAN_COUNT) && (CAN_COUNT > 0) */

2737
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c
View File

File diff suppressed because it is too large Load Diff

47
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_core.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_core.c
* @brief Core interrupt handling API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -41,6 +41,7 @@
* @{
******************************************************************************/
/* *INDENT-OFF* */
/***************************************************************************//**
@addtogroup CORE
@brief Core interrupt handling API
@ -65,17 +66,16 @@
@li <b>CRITICAL</b> section: Inside a critical sections all interrupts are
disabled (except for fault handlers). The PRIMASK register is always used for
interrupt disable/enable.
@li <b>ATOMIC</b> section: This type of section is configurable and the default
method is to use PRIMASK. With BASEPRI configuration, interrupts with priority
equal to or lower than a given configurable level are disabled. The interrupt
disable priority level is defined at compile time. The BASEPRI register is not
@li <b>ATOMIC</b> section: This type of section is configurable and the default
method is to use PRIMASK. With BASEPRI configuration, interrupts with priority
equal to or lower than a given configurable level are disabled. The interrupt
disable priority level is defined at compile time. The BASEPRI register is not
available for all architectures.
@li <b>NVIC mask</b> section: Disable NVIC (external interrupts) on an
individual manner.
em_core also has an API for manipulating RAM based interrupt vector tables.
@n @section core_conf Compile time configuration
The following @htmlonly #defines @endhtmlonly are used to configure em_core:
@ -101,7 +101,6 @@
devices ATOMIC section helper macros are available but they are
implemented as CRITICAL sections using PRIMASK register.
@n @section core_macro_api The macro API
The primary em_core API is the macro API. The macro API will map to correct
@ -152,7 +151,6 @@
Refer to @em Macros or <em>Macro Definition Documentation</em> below for a
full list of macros.
@n @section core_reimplementation API reimplementation
Most of the functions in the API are implemented as weak functions. This means
@ -187,7 +185,6 @@
#define CORE_INTERRUPT_EXIT() OSIntExit()
@endverbatim
@n @section core_vector_tables Interrupt vector tables
When using RAM based interrupt vector tables it is the users responsibility
@ -227,7 +224,7 @@
@endverbatim
@n @section core_porting Porting from em_int
Existing code using INT_Enable() and INT_Disable() must be ported to the
em_core API. While em_int used a global counter to store the interrupt state,
em_core uses a local variable. Any usage of INT_Disable() therefore needs to
@ -259,6 +256,7 @@
@endverbatim
* @{
******************************************************************************/
/* *INDENT-ON* */
/*******************************************************************************
******************************* DEFINES ***********************************
@ -295,7 +293,7 @@
// Compile time sanity check.
#if (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_PRIMASK) \
&& (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_BASEPRI)
&& (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_BASEPRI)
#error "em_core: Undefined ATOMIC IRQ handling strategy."
#endif
@ -518,7 +516,7 @@ void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState,
CORE_CRITICAL_SECTION(
*nvicState = *(CORE_nvicMask_t*)&NVIC->ICER[0];
*(CORE_nvicMask_t*)&NVIC->ICER[0] = *disable;
)
)
}
/***************************************************************************//**
@ -532,7 +530,7 @@ void CORE_NvicDisableMask(const CORE_nvicMask_t *disable)
{
CORE_CRITICAL_SECTION(
*(CORE_nvicMask_t*)&NVIC->ICER[0] = *disable;
)
)
}
/***************************************************************************//**
@ -546,7 +544,7 @@ void CORE_NvicEnableMask(const CORE_nvicMask_t *enable)
{
CORE_CRITICAL_SECTION(
*(CORE_nvicMask_t*)&NVIC->ISER[0] = *enable;
)
)
}
/***************************************************************************//**
@ -567,7 +565,7 @@ void CORE_YieldNvicMask(const CORE_nvicMask_t *enable)
// Get current NVIC enable mask.
CORE_CRITICAL_SECTION(
nvicMask = *(CORE_nvicMask_t*)&NVIC->ISER[0];
)
)
// Make a mask with bits set for those interrupts that are currently
// disabled but are set in the enable mask.
@ -576,7 +574,6 @@ void CORE_YieldNvicMask(const CORE_nvicMask_t *enable)
nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0];
if (nvicMask.a[0] != 0) {
#elif (CORE_NVIC_REG_WORDS == 2)
nvicMask.a[0] &= enable->a[0];
nvicMask.a[1] &= enable->a[1];
@ -584,7 +581,6 @@ void CORE_YieldNvicMask(const CORE_nvicMask_t *enable)
nvicMask.a[1] = ~nvicMask.a[1] & enable->a[1];
if ((nvicMask.a[0] != 0) || (nvicMask.a[1] != 0)) {
#elif (CORE_NVIC_REG_WORDS == 3)
nvicMask.a[0] &= enable->a[0];
nvicMask.a[1] &= enable->a[1];
@ -729,7 +725,7 @@ void CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask)
{
CORE_CRITICAL_SECTION(
*mask = *(CORE_nvicMask_t*)&NVIC->ISER[0];
)
)
}
/***************************************************************************//**
@ -748,8 +744,7 @@ bool CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask)
CORE_CRITICAL_SECTION(
nvicMask = *(CORE_nvicMask_t*)&NVIC->ISER[0];
)
)
#if (CORE_NVIC_REG_WORDS == 1)
return (mask->a[0] & nvicMask.a[0]) == 0;
@ -800,7 +795,7 @@ bool CORE_NvicIRQDisabled(IRQn_Type irqN)
void *CORE_GetNvicRamTableHandler(IRQn_Type irqN)
{
EFM_ASSERT((irqN >= -16) && (irqN < EXT_IRQ_COUNT));
return (void*)(((uint32_t*)SCB->VTOR)[irqN+16]);
return (void*)(((uint32_t*)SCB->VTOR)[irqN + 16]);
}
/***************************************************************************//**
@ -819,7 +814,7 @@ void *CORE_GetNvicRamTableHandler(IRQn_Type irqN)
void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler)
{
EFM_ASSERT((irqN >= -16) && (irqN < EXT_IRQ_COUNT));
((uint32_t*)SCB->VTOR)[irqN+16] = (uint32_t)handler;
((uint32_t*)SCB->VTOR)[irqN + 16] = (uint32_t)handler;
}
/***************************************************************************//**
@ -879,15 +874,15 @@ void CORE_InitNvicVectorTable(uint32_t *sourceTable,
EFM_ASSERT(((uint32_t)targetTable
& ((1 << (32 - __CLZ((targetSize * 4) - 1))) - 1)) == 0);
for (i=0; i<targetSize; i++) {
for (i = 0; i < targetSize; i++) {
if (overwriteActive) { // Overwrite target entries ?
if (i<sourceSize) { // targetSize <= sourceSize
if (i < sourceSize) { // targetSize <= sourceSize
targetTable[i] = sourceTable[i];
} else { // targetSize > sourceSize
targetTable[i] = (uint32_t)defaultHandler;
}
} else { // Overwrite target entries which are 0
if (i<sourceSize) { // targetSize <= sourceSize
if (i < sourceSize) { // targetSize <= sourceSize
if (targetTable[i] == 0) {
targetTable[i] = sourceTable[i];
}

10
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cryotimer.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_cryotimer.c
* @brief Ultra Low Energy Timer/Counter (CRYOTIMER) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -52,9 +52,9 @@ void CRYOTIMER_Init(const CRYOTIMER_Init_TypeDef *init)
{
CRYOTIMER->PERIODSEL = (uint32_t)init->period & _CRYOTIMER_PERIODSEL_MASK;
CRYOTIMER->CTRL = ((uint32_t)init->enable << _CRYOTIMER_CTRL_EN_SHIFT)
| ((uint32_t)init->debugRun << _CRYOTIMER_CTRL_DEBUGRUN_SHIFT)
| ((uint32_t)init->osc << _CRYOTIMER_CTRL_OSCSEL_SHIFT)
| ((uint32_t)init->presc << _CRYOTIMER_CTRL_PRESC_SHIFT);
| ((uint32_t)init->debugRun << _CRYOTIMER_CTRL_DEBUGRUN_SHIFT)
| ((uint32_t)init->osc << _CRYOTIMER_CTRL_OSCSEL_SHIFT)
| ((uint32_t)init->presc << _CRYOTIMER_CTRL_PRESC_SHIFT);
CRYOTIMER_EM4WakeupEnable(init->em4Wakeup);
}

270
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_crypto.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_crypto.c
* @brief Cryptography accelerator peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -54,24 +54,24 @@
#define CRYPTO_INSTRUCTIONS_PER_REG (4)
#define CRYPTO_INSTRUCTIONS_MAX (12)
#define CRYPTO_INSTRUCTION_REGS (CRYPTO_INSTRUCTIONS_MAX/CRYPTO_INSTRUCTIONS_PER_REG)
#define CRYPTO_INSTRUCTION_REGS (CRYPTO_INSTRUCTIONS_MAX / CRYPTO_INSTRUCTIONS_PER_REG)
#define CRYPTO_SHA1_BLOCK_SIZE_IN_BITS (512)
#define CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES (CRYPTO_SHA1_BLOCK_SIZE_IN_BITS/8)
#define CRYPTO_SHA1_BLOCK_SIZE_IN_32BIT_WORDS (CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES/sizeof(uint32_t))
#define CRYPTO_SHA1_DIGEST_SIZE_IN_32BIT_WORDS (CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES/sizeof(uint32_t))
#define CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES (CRYPTO_SHA1_BLOCK_SIZE_IN_BITS / 8)
#define CRYPTO_SHA1_BLOCK_SIZE_IN_32BIT_WORDS (CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES / sizeof(uint32_t))
#define CRYPTO_SHA1_DIGEST_SIZE_IN_32BIT_WORDS (CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES / sizeof(uint32_t))
#define CRYPTO_SHA256_BLOCK_SIZE_IN_BITS (512)
#define CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES (CRYPTO_SHA256_BLOCK_SIZE_IN_BITS/8)
#define CRYPTO_SHA256_BLOCK_SIZE_IN_32BIT_WORDS (CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES/sizeof(uint32_t))
#define CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES (CRYPTO_SHA256_BLOCK_SIZE_IN_BITS / 8)
#define CRYPTO_SHA256_BLOCK_SIZE_IN_32BIT_WORDS (CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES / sizeof(uint32_t))
#define CRYPTO_SHA256_DIGEST_SIZE_IN_32BIT_WORDS (CRYPTO_SHA256_DIGEST_SIZE_IN_BYTES/sizeof(uint32_t))
#define CRYPTO_SHA256_DIGEST_SIZE_IN_32BIT_WORDS (CRYPTO_SHA256_DIGEST_SIZE_IN_BYTES / sizeof(uint32_t))
#define PARTIAL_OPERAND_WIDTH_LOG2 (7) /* 2^7 = 128 */
#define PARTIAL_OPERAND_WIDTH (1<<PARTIAL_OPERAND_WIDTH_LOG2)
#define PARTIAL_OPERAND_WIDTH_MASK (PARTIAL_OPERAND_WIDTH-1)
#define PARTIAL_OPERAND_WIDTH_IN_BYTES (PARTIAL_OPERAND_WIDTH/8)
#define PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS (PARTIAL_OPERAND_WIDTH_IN_BYTES/sizeof(uint32_t))
#define PARTIAL_OPERAND_WIDTH (1 << PARTIAL_OPERAND_WIDTH_LOG2)
#define PARTIAL_OPERAND_WIDTH_MASK (PARTIAL_OPERAND_WIDTH - 1)
#define PARTIAL_OPERAND_WIDTH_IN_BYTES (PARTIAL_OPERAND_WIDTH / 8)
#define PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS (PARTIAL_OPERAND_WIDTH_IN_BYTES / sizeof(uint32_t))
#define SWAP32(x) (__REV(x))
@ -152,16 +152,15 @@ void CRYPTO_DataWriteVariableSize(CRYPTO_DataReg_TypeDef dataReg,
int i;
volatile uint32_t * reg = (volatile uint32_t *) dataReg;
if (valSize < 4)
{
if (valSize < 4) {
/* Non optimal write of data. */
for (i = 0; i < valSize; i++)
for (i = 0; i < valSize; i++) {
*reg = *val++;
for (; i < 4; i++)
}
for (; i < 4; i++) {
*reg = 0;
}
else
{
}
} else {
CRYPTO_BurstToCrypto(reg, &val[0]);
}
}
@ -192,8 +191,7 @@ void CRYPTO_ModulusSet(CRYPTO_TypeDef * crypto,
{
uint32_t temp = crypto->WAC & (~(_CRYPTO_WAC_MODULUS_MASK | _CRYPTO_WAC_MODOP_MASK));
switch (modulusId)
{
switch (modulusId) {
case cryptoModulusBin256:
case cryptoModulusBin128:
case cryptoModulusGcmBin128:
@ -248,8 +246,7 @@ void CRYPTO_KeyRead(CRYPTO_TypeDef * crypto,
EFM_ASSERT(val);
CRYPTO_BurstFromCrypto(&crypto->KEY, &val[0]);
if (keyWidth == cryptoKey256Bits)
{
if (keyWidth == cryptoKey256Bits) {
CRYPTO_BurstFromCrypto(&crypto->KEY, &val[4]);
}
}
@ -282,7 +279,7 @@ void CRYPTO_SHA_1(CRYPTO_TypeDef * crypto,
uint32_t temp;
uint32_t len;
int blockLen;
uint32_t shaBlock[CRYPTO_SHA1_BLOCK_SIZE_IN_32BIT_WORDS]=
uint32_t shaBlock[CRYPTO_SHA1_BLOCK_SIZE_IN_32BIT_WORDS] =
{
/* Initial value */
0x67452301, 0xefcdab89, 0x98badcfe, 0x10325476, 0xc3d2e1f0
@ -307,8 +304,7 @@ void CRYPTO_SHA_1(CRYPTO_TypeDef * crypto,
len = msgLen;
while (len >= CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES)
{
while (len >= CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES) {
/* Write block to QDATA1. */
CRYPTO_QDataWrite(&crypto->QDATA1BIG, (uint32_t *) msg);
@ -325,8 +321,9 @@ void CRYPTO_SHA_1(CRYPTO_TypeDef * crypto,
blockLen = 0;
/* Build the last (or second to last) block */
for (; len; len--)
for (; len; len--) {
p8ShaBlock[blockLen++] = *msg++;
}
/* append the '1' bit */
p8ShaBlock[blockLen++] = 0x80;
@ -335,8 +332,7 @@ void CRYPTO_SHA_1(CRYPTO_TypeDef * crypto,
* then compress. Then we can fall back to padding zeros and length
* encoding like normal.
*/
if (blockLen > 56)
{
if (blockLen > 56) {
while (blockLen < 64)
p8ShaBlock[blockLen++] = 0;
@ -412,7 +408,7 @@ void CRYPTO_SHA_256(CRYPTO_TypeDef * crypto,
uint32_t temp;
uint32_t len;
int blockLen;
uint32_t shaBlock[CRYPTO_SHA256_BLOCK_SIZE_IN_32BIT_WORDS]=
uint32_t shaBlock[CRYPTO_SHA256_BLOCK_SIZE_IN_32BIT_WORDS] =
{
/* Initial value */
0x6a09e667, 0xbb67ae85, 0x3c6ef372, 0xa54ff53a,
@ -437,8 +433,7 @@ void CRYPTO_SHA_256(CRYPTO_TypeDef * crypto,
CRYPTO_CMD_INSTR_SELDDATA0DDATA1);
len = msgLen;
while (len >= CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES)
{
while (len >= CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES) {
/* Write block to QDATA1BIG. */
CRYPTO_QDataWrite(&crypto->QDATA1BIG, (uint32_t *) msg);
@ -455,8 +450,9 @@ void CRYPTO_SHA_256(CRYPTO_TypeDef * crypto,
blockLen = 0;
/* Build the last (or second to last) block */
for (; len; len--)
for (; len; len--) {
p8ShaBlock[blockLen++] = *msg++;
}
/* append the '1' bit */
p8ShaBlock[blockLen++] = 0x80;
@ -465,8 +461,7 @@ void CRYPTO_SHA_256(CRYPTO_TypeDef * crypto,
* then compress. Then we can fall back to padding zeros and length
* encoding like normal.
*/
if (blockLen > 56)
{
if (blockLen > 56) {
while (blockLen < 64)
p8ShaBlock[blockLen++] = 0;
@ -532,9 +527,11 @@ __STATIC_INLINE void cryptoBigintIncrement(uint32_t * words32bits,
int num32bitWords)
{
int i;
for (i=0; i<num32bitWords; i++)
if (++words32bits[i] != 0)
for (i = 0; i < num32bitWords; i++) {
if (++words32bits[i] != 0) {
break;
}
}
return;
}
@ -565,18 +562,18 @@ void CRYPTO_Mul(CRYPTO_TypeDef * crypto,
/**************** Initializations ******************/
#ifdef USE_VARIABLE_SIZED_DATA_LOADS
int numWordsLastOperandA = (aSize&PARTIAL_OPERAND_WIDTH_MASK)>>5;
int numPartialOperandsA = numWordsLastOperandA ?
(aSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1 :
aSize >> PARTIAL_OPERAND_WIDTH_LOG2;
int numWordsLastOperandB = (bSize&PARTIAL_OPERAND_WIDTH_MASK)>>5;
int numPartialOperandsB = numWordsLastOperandB ?
(bSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1 :
bSize >> PARTIAL_OPERAND_WIDTH_LOG2;
int numWordsLastOperandR = (rSize&PARTIAL_OPERAND_WIDTH_MASK)>>5;
int numPartialOperandsR = numWordsLastOperandR ?
(rSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1 :
rSize >> PARTIAL_OPERAND_WIDTH_LOG2;
int numWordsLastOperandA = (aSize & PARTIAL_OPERAND_WIDTH_MASK) >> 5;
int numPartialOperandsA = numWordsLastOperandA
? (aSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1
: aSize >> PARTIAL_OPERAND_WIDTH_LOG2;
int numWordsLastOperandB = (bSize & PARTIAL_OPERAND_WIDTH_MASK) >> 5;
int numPartialOperandsB = numWordsLastOperandB
? (bSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1
: bSize >> PARTIAL_OPERAND_WIDTH_LOG2;
int numWordsLastOperandR = (rSize & PARTIAL_OPERAND_WIDTH_MASK) >> 5;
int numPartialOperandsR = numWordsLastOperandR
? (rSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1
: rSize >> PARTIAL_OPERAND_WIDTH_LOG2;
EFM_ASSERT(numPartialOperandsA + numPartialOperandsB <= numPartialOperandsR);
#else
int numPartialOperandsA = aSize >> PARTIAL_OPERAND_WIDTH_LOG2;
@ -597,8 +594,8 @@ void CRYPTO_Mul(CRYPTO_TypeDef * crypto,
can take place immediately when CRYPTO is ready inside the instruction
sequence. */
crypto->CTRL =
CRYPTO_CTRL_DMA0RSEL_DATA0 | CRYPTO_CTRL_DMA0MODE_FULL |
CRYPTO_CTRL_DMA1RSEL_DATA1 | CRYPTO_CTRL_DMA1MODE_FULL;
CRYPTO_CTRL_DMA0RSEL_DATA0 | CRYPTO_CTRL_DMA0MODE_FULL
| CRYPTO_CTRL_DMA1RSEL_DATA1 | CRYPTO_CTRL_DMA1MODE_FULL;
CRYPTO_EXECUTE_4(crypto,
CRYPTO_CMD_INSTR_CCLR, /* Carry = 0 */
@ -607,12 +604,12 @@ void CRYPTO_Mul(CRYPTO_TypeDef * crypto,
CRYPTO_CMD_INSTR_DDATA0TODDATA2,
CRYPTO_CMD_INSTR_SELDDATA1DDATA3);
/*
register map:
DDATA0: working register
DDATA1: B(j)
DDATA2: R(i+j+1) and R(i+j), combined with DMA entry for B(j)
DDATA3: A(i)
*/
register map:
DDATA0: working register
DDATA1: B(j)
DDATA2: R(i+j+1) and R(i+j), combined with DMA entry for B(j)
DDATA3: A(i)
*/
CRYPTO_SEQ_LOAD_10(crypto,
/* Temporarily load partial operand B(j) to DATA0. */
@ -645,30 +642,31 @@ void CRYPTO_Mul(CRYPTO_TypeDef * crypto,
/**************** End Initializations ******************/
for(i=0; i<numPartialOperandsA; i++)
{
for (i = 0; i < numPartialOperandsA; i++) {
/* Load partial operand #1 A>>(i*PARTIAL_OPERAND_WIDTH) to DDATA1. */
#ifdef USE_VARIABLE_SIZED_DATA_LOADS
if ( (numWordsLastOperandA != 0) && ( i == numPartialOperandsA-1 ) )
if ( (numWordsLastOperandA != 0) && (i == numPartialOperandsA - 1) ) {
CRYPTO_DataWriteVariableSize(&crypto->DATA2,
&A[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
&A[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
numWordsLastOperandA);
else
CRYPTO_DataWrite(&crypto->DATA2, &A[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
} else {
CRYPTO_DataWrite(&crypto->DATA2, &A[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
}
#else
CRYPTO_DataWrite(&crypto->DATA2, &A[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
CRYPTO_DataWrite(&crypto->DATA2, &A[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
#endif
/* Load partial result in R>>(i*PARTIAL_OPERAND_WIDTH) to DATA1. */
#ifdef USE_VARIABLE_SIZED_DATA_LOADS
if ( (numWordsLastOperandR != 0) && ( i == numPartialOperandsR-1 ) )
if ( (numWordsLastOperandR != 0) && (i == numPartialOperandsR - 1) ) {
CRYPTO_DataWriteVariableSize(&crypto->DATA1,
&R[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
&R[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
numWordsLastOperandR);
else
CRYPTO_DataWrite(&crypto->DATA1, &R[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
} else {
CRYPTO_DataWrite(&crypto->DATA1, &R[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
}
#else
CRYPTO_DataWrite(&crypto->DATA1, &R[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
CRYPTO_DataWrite(&crypto->DATA1, &R[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
#endif
/* Clear carry */
@ -676,59 +674,59 @@ void CRYPTO_Mul(CRYPTO_TypeDef * crypto,
/* Setup number of sequence iterations and block size. */
crypto->SEQCTRL = CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES
| (PARTIAL_OPERAND_WIDTH_IN_BYTES * numPartialOperandsB);
| (PARTIAL_OPERAND_WIDTH_IN_BYTES * numPartialOperandsB);
/* Execute the MULtiply instruction sequence. */
CRYPTO_InstructionSequenceExecute(crypto);
for (j=0; j<numPartialOperandsB; j++)
{
for (j = 0; j < numPartialOperandsB; j++) {
/* Load partial operand 2 B>>(j*`PARTIAL_OPERAND_WIDTH) to DDATA2
(via DATA0). */
#ifdef USE_VARIABLE_SIZED_DATA_LOADS
if ( (numWordsLastOperandB != 0) && ( j == numPartialOperandsB-1 ) )
if ( (numWordsLastOperandB != 0) && (j == numPartialOperandsB - 1) ) {
CRYPTO_DataWriteVariableSize(&crypto->DATA0,
&B[j*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
&B[j * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
numWordsLastOperandB);
else
} else {
CRYPTO_DataWrite(&crypto->DATA0,
&B[j*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
&B[j * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
}
#else
CRYPTO_DataWrite(&crypto->DATA0,
&B[j*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
&B[j * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
#endif
/* Load most significant partial result
R>>((i+j+1)*`PARTIAL_OPERAND_WIDTH) into DATA1. */
#ifdef USE_VARIABLE_SIZED_DATA_LOADS
if ( (numWordsLastOperandR != 0) && ( (i+j+1) == numPartialOperandsR-1 ) )
if ( (numWordsLastOperandR != 0) && ( (i + j + 1) == numPartialOperandsR - 1) ) {
CRYPTO_DataWriteVariableSize(&crypto->DATA1,
&R[(i+j+1)*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
&R[(i + j + 1) * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
numWordsLastOperandR);
else
} else {
CRYPTO_DataWrite(&crypto->DATA1,
&R[(i+j+1)*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
&R[(i + j + 1) * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
}
#else
CRYPTO_DataWrite(&crypto->DATA1,
&R[(i+j+1)*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
&R[(i + j + 1) * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
#endif
/* Store least significant partial result */
CRYPTO_DataRead(&crypto->DATA0,
&R[(i+j)*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
&R[(i + j) * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
} /* for (j=0; j<numPartialOperandsB; j++) */
/* Handle carry at the end of the inner loop. */
if (CRYPTO_CarryIsSet(crypto))
cryptoBigintIncrement(&R[(i+numPartialOperandsB+1)
*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
(numPartialOperandsA-i-1)
*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS);
if (CRYPTO_CarryIsSet(crypto)) {
cryptoBigintIncrement(&R[(i + numPartialOperandsB + 1)
* PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
(numPartialOperandsA - i - 1)
* PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS);
}
CRYPTO_DataRead(&crypto->DATA1,
&R[(i+numPartialOperandsB)
&R[(i + numPartialOperandsB)
* PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
} /* for (i=0; i<numPartialOperandsA; i++) */
}
@ -1141,7 +1139,7 @@ void CRYPTO_AES_DecryptKey128(CRYPTO_TypeDef * crypto,
/* Setup CRYPTO in AES-128 mode. */
crypto->CTRL = CRYPTO_CTRL_AES_AES128;
/* Load key */
CRYPTO_BurstToCrypto(&crypto->KEYBUF, &_in[0]);
@ -1179,7 +1177,7 @@ void CRYPTO_AES_DecryptKey256(CRYPTO_TypeDef * crypto,
/* Setup CRYPTO in AES-256 mode. */
crypto->CTRL = CRYPTO_CTRL_AES_AES256;
/* Load key */
CRYPTO_BurstToCrypto(&crypto->KEYBUF, &_in[0]);
CRYPTO_BurstToCrypto(&crypto->KEYBUF, &_in[4]);
@ -1466,27 +1464,22 @@ static void CRYPTO_AES_CBCx(CRYPTO_TypeDef * crypto,
CRYPTO_KeyBufWrite(crypto, (uint32_t *)key, keyWidth);
if (encrypt)
{
if (encrypt) {
CRYPTO_DataWrite(&crypto->DATA0, (uint32_t *)iv);
crypto->SEQ0 =
CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR0_SHIFT |
CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR1_SHIFT;
crypto->SEQ0 = CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR0_SHIFT
| CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR1_SHIFT;
CRYPTO_AES_ProcessLoop(crypto, len,
&crypto->DATA1, (uint32_t *) in,
&crypto->DATA0, (uint32_t *) out);
}
else
{
} else {
CRYPTO_DataWrite(&crypto->DATA2, (uint32_t *) iv);
crypto->SEQ0 =
CRYPTO_CMD_INSTR_DATA1TODATA0 << _CRYPTO_SEQ0_INSTR0_SHIFT |
CRYPTO_CMD_INSTR_AESDEC << _CRYPTO_SEQ0_INSTR1_SHIFT |
CRYPTO_CMD_INSTR_DATA2TODATA0XOR << _CRYPTO_SEQ0_INSTR2_SHIFT |
CRYPTO_CMD_INSTR_DATA1TODATA2 << _CRYPTO_SEQ0_INSTR3_SHIFT;
crypto->SEQ0 = CRYPTO_CMD_INSTR_DATA1TODATA0 << _CRYPTO_SEQ0_INSTR0_SHIFT
| CRYPTO_CMD_INSTR_AESDEC << _CRYPTO_SEQ0_INSTR1_SHIFT
| CRYPTO_CMD_INSTR_DATA2TODATA0XOR << _CRYPTO_SEQ0_INSTR2_SHIFT
| CRYPTO_CMD_INSTR_DATA1TODATA2 << _CRYPTO_SEQ0_INSTR3_SHIFT;
crypto->SEQ1 = 0;
@ -1552,30 +1545,25 @@ static void CRYPTO_AES_CFBx(CRYPTO_TypeDef * crypto,
CRYPTO_KeyBufWrite(crypto, (uint32_t *)key, keyWidth);
/* Load instructions to CRYPTO sequencer. */
if (encrypt)
{
if (encrypt) {
/* Load IV */
CRYPTO_DataWrite(&crypto->DATA0, (uint32_t *)iv);
crypto->SEQ0 =
CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR0_SHIFT |
CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR1_SHIFT;
crypto->SEQ0 = CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR0_SHIFT
| CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR1_SHIFT;
CRYPTO_AES_ProcessLoop(crypto, len,
&crypto->DATA1, (uint32_t *)in,
&crypto->DATA0, (uint32_t *)out
);
}
else
{
} else {
/* Load IV */
CRYPTO_DataWrite(&crypto->DATA2, (uint32_t *)iv);
crypto->SEQ0 =
CRYPTO_CMD_INSTR_DATA2TODATA0 << _CRYPTO_SEQ0_INSTR0_SHIFT |
CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR1_SHIFT |
CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR2_SHIFT |
CRYPTO_CMD_INSTR_DATA1TODATA2 << _CRYPTO_SEQ0_INSTR3_SHIFT;
crypto->SEQ0 = CRYPTO_CMD_INSTR_DATA2TODATA0 << _CRYPTO_SEQ0_INSTR0_SHIFT
| CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR1_SHIFT
| CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR2_SHIFT
| CRYPTO_CMD_INSTR_DATA1TODATA2 << _CRYPTO_SEQ0_INSTR3_SHIFT;
crypto->SEQ1 = 0;
CRYPTO_AES_ProcessLoop(crypto, len,
@ -1643,10 +1631,10 @@ static void CRYPTO_AES_CTRx(CRYPTO_TypeDef * crypto,
CRYPTO_DataWrite(&crypto->DATA1, (uint32_t *) ctr);
crypto->SEQ0 = CRYPTO_CMD_INSTR_DATA1TODATA0 << _CRYPTO_SEQ0_INSTR0_SHIFT |
CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR1_SHIFT |
CRYPTO_CMD_INSTR_DATA0TODATA3 << _CRYPTO_SEQ0_INSTR2_SHIFT |
CRYPTO_CMD_INSTR_DATA1INC << _CRYPTO_SEQ0_INSTR3_SHIFT;
crypto->SEQ0 = CRYPTO_CMD_INSTR_DATA1TODATA0 << _CRYPTO_SEQ0_INSTR0_SHIFT
| CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR1_SHIFT
| CRYPTO_CMD_INSTR_DATA0TODATA3 << _CRYPTO_SEQ0_INSTR2_SHIFT
| CRYPTO_CMD_INSTR_DATA1INC << _CRYPTO_SEQ0_INSTR3_SHIFT;
crypto->SEQ1 = CRYPTO_CMD_INSTR_DATA2TODATA0XOR << _CRYPTO_SEQ1_INSTR4_SHIFT;
@ -1704,17 +1692,12 @@ static void CRYPTO_AES_ECBx(CRYPTO_TypeDef * crypto,
CRYPTO_KeyBufWrite(crypto, (uint32_t *)key, keyWidth);
if (encrypt)
{
crypto->SEQ0 =
(CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR0_SHIFT |
CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ0_INSTR1_SHIFT);
}
else
{
crypto->SEQ0 =
(CRYPTO_CMD_INSTR_AESDEC << _CRYPTO_SEQ0_INSTR0_SHIFT |
CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ0_INSTR1_SHIFT);
if (encrypt) {
crypto->SEQ0 = CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR0_SHIFT
| CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ0_INSTR1_SHIFT;
} else {
crypto->SEQ0 = CRYPTO_CMD_INSTR_AESDEC << _CRYPTO_SEQ0_INSTR0_SHIFT
| CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ0_INSTR1_SHIFT;
}
CRYPTO_AES_ProcessLoop(crypto, len,
@ -1769,14 +1752,12 @@ static void CRYPTO_AES_OFBx(CRYPTO_TypeDef * crypto,
CRYPTO_DataWrite(&crypto->DATA2, (uint32_t *)iv);
crypto->SEQ0 =
CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ0_INSTR0_SHIFT |
CRYPTO_CMD_INSTR_DATA2TODATA0 << _CRYPTO_SEQ0_INSTR1_SHIFT |
CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR2_SHIFT |
CRYPTO_CMD_INSTR_DATA0TODATA2 << _CRYPTO_SEQ0_INSTR3_SHIFT;
crypto->SEQ1 =
CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ1_INSTR4_SHIFT |
CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ1_INSTR5_SHIFT;
crypto->SEQ0 = CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ0_INSTR0_SHIFT
| CRYPTO_CMD_INSTR_DATA2TODATA0 << _CRYPTO_SEQ0_INSTR1_SHIFT
| CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR2_SHIFT
| CRYPTO_CMD_INSTR_DATA0TODATA2 << _CRYPTO_SEQ0_INSTR3_SHIFT;
crypto->SEQ1 = CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ1_INSTR4_SHIFT
| CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ1_INSTR5_SHIFT;
CRYPTO_AES_ProcessLoop(crypto, len,
&crypto->DATA0, (uint32_t *) in,
@ -1821,8 +1802,7 @@ static inline void CRYPTO_AES_ProcessLoop(CRYPTO_TypeDef * crypto,
len /= CRYPTO_AES_BLOCKSIZE;
crypto->SEQCTRL = 16 << _CRYPTO_SEQCTRL_LENGTHA_SHIFT;
while (len--)
{
while (len--) {
/* Load data and trigger encryption */
CRYPTO_DataWrite(inReg, (uint32_t *)in);

59
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_csen.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_csen.c
* @brief Capacitive Sense Module (CSEN) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -31,7 +31,7 @@
******************************************************************************/
#include "em_csen.h"
#if defined( CSEN_COUNT ) && ( CSEN_COUNT > 0 )
#if defined(CSEN_COUNT) && (CSEN_COUNT > 0)
#include "em_assert.h"
#include "em_cmu.h"
@ -68,8 +68,8 @@
*
* @details
* Sets the initial value of the integrator(s) for the Delta Modulation (DM)
* converter. The initial value for the ramp-down integrator has no effect
* if low frequency attenuation was not selected by the mode initialization
* converter. The initial value for the ramp-down integrator has no effect
* if low frequency attenuation was not selected by the mode initialization
* function @ref CSEN_InitMode().
*
* @note
@ -82,7 +82,7 @@
* Initial value for the ramp-up integrator.
*
* @param[in] down
* Initial value for the ramp-down integrator. Has no effect if low frequency
* Initial value for the ramp-down integrator. Has no effect if low frequency
* attenuation is not configured.
******************************************************************************/
void CSEN_DMBaselineSet(CSEN_TypeDef *csen, uint32_t up, uint32_t down)
@ -94,7 +94,6 @@ void CSEN_DMBaselineSet(CSEN_TypeDef *csen, uint32_t up, uint32_t down)
| (down << _CSEN_DMBASELINE_BASELINEDN_SHIFT);
}
/***************************************************************************//**
* @brief
* Initialize CSEN.
@ -122,18 +121,15 @@ void CSEN_Init(CSEN_TypeDef *csen, const CSEN_Init_TypeDef *init)
/* Initialize CTRL. This will stop any conversion in progress. */
tmp = CSEN_CTRL_STM_DEFAULT;
if (init->cpAccuracyHi)
{
if (init->cpAccuracyHi) {
tmp |= CSEN_CTRL_CPACCURACY_HI;
}
if (init->localSense)
{
if (init->localSense) {
tmp |= _CSEN_CTRL_LOCALSENS_MASK;
}
if (init->keepWarm)
{
if (init->keepWarm) {
tmp |= CSEN_CTRL_WARMUPMODE_KEEPCSENWARM;
}
@ -160,18 +156,17 @@ void CSEN_Init(CSEN_TypeDef *csen, const CSEN_Init_TypeDef *init)
| (init->input56To63 << _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_SHIFT);
}
/***************************************************************************//**
* @brief
* Initialize a CSEN measurement mode.
*
* @details
* Used to configure any type of measurement mode. After the measurement
* has been configured, calling @ref CSEN_Enable() will enable CSEN and
* allow it to start a conversion from the selected trigger source. To
* manually start a conversion use @ref CSEN_Start(). To check if a
* Used to configure any type of measurement mode. After the measurement
* has been configured, calling @ref CSEN_Enable() will enable CSEN and
* allow it to start a conversion from the selected trigger source. To
* manually start a conversion use @ref CSEN_Start(). To check if a
* conversion is in progress use @ref CSEN_IsBusy(), or alternatively
* use the interrupt flags returned by @ref CSEN_IntGet() to detect when
* use the interrupt flags returned by @ref CSEN_IntGet() to detect when
* a conversion is completed.
*
* @note
@ -191,36 +186,33 @@ void CSEN_InitMode(CSEN_TypeDef *csen, const CSEN_InitMode_TypeDef *init)
EFM_ASSERT(init->dmIterPerCycle < 0x10);
EFM_ASSERT(init->dmCycles < 0x10);
/* Initialize CTRL. This will stop any conversion in progress.
* These composite inputs set multiple fields. They do not need
/* Initialize CTRL. This will stop any conversion in progress.
* These composite inputs set multiple fields. They do not need
* to be shifted. */
tmp = ((uint32_t)init->sampleMode
| (uint32_t)init->convSel
| (uint32_t)init->cmpMode);
| (uint32_t)init->convSel
| (uint32_t)init->cmpMode);
tmp |= (init->trigSel << _CSEN_CTRL_STM_SHIFT)
| (init->accMode << _CSEN_CTRL_ACU_SHIFT)
| (init->sarRes << _CSEN_CTRL_SARCR_SHIFT);
if (init->enableDma)
{
if (init->enableDma) {
tmp |= CSEN_CTRL_DMAEN_ENABLE;
}
if (init->sumOnly)
{
if (init->sumOnly) {
tmp |= CSEN_CTRL_DRSF_ENABLE;
}
if (init->autoGnd)
{
if (init->autoGnd) {
tmp |= CSEN_CTRL_AUTOGND_ENABLE;
}
/* Preserve the fields that were initialized by CSEN_Init(). */
tmp |= csen->CTRL & (_CSEN_CTRL_CPACCURACY_MASK
| _CSEN_CTRL_LOCALSENS_MASK
| _CSEN_CTRL_WARMUPMODE_MASK);
| _CSEN_CTRL_LOCALSENS_MASK
| _CSEN_CTRL_WARMUPMODE_MASK);
csen->CTRL = tmp;
@ -243,8 +235,7 @@ void CSEN_InitMode(CSEN_TypeDef *csen, const CSEN_InitMode_TypeDef *init)
| (init->dmIterPerCycle << _CSEN_DMCFG_DMR_SHIFT)
| (init->dmDelta << _CSEN_DMCFG_DMG_SHIFT);
if (init->dmFixedDelta)
{
if (init->dmFixedDelta) {
tmp |= CSEN_DMCFG_DMGRDIS;
}
@ -256,7 +247,6 @@ void CSEN_InitMode(CSEN_TypeDef *csen, const CSEN_InitMode_TypeDef *init)
| (init->gainSel << _CSEN_ANACTRL_IREFPROG_SHIFT);
}
/***************************************************************************//**
* @brief
* Reset CSEN to same state as after a HW reset.
@ -288,7 +278,6 @@ void CSEN_Reset(CSEN_TypeDef *csen)
csen->IFC = _CSEN_IF_MASK;
}
/** @} (end addtogroup CSEN) */
/** @} (end addtogroup emlib) */
#endif /* defined(CSEN_COUNT) && (CSEN_COUNT > 0) */

72
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_dac.c
* @brief Digital to Analog Converter (DAC) Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -90,19 +90,15 @@ void DAC_Enable(DAC_TypeDef *dac, unsigned int ch, bool enable)
EFM_ASSERT(DAC_REF_VALID(dac));
EFM_ASSERT(DAC_CH_VALID(ch));
if (!ch)
{
if (!ch) {
reg = &(dac->CH0CTRL);
}
else
{
} else {
reg = &(dac->CH1CTRL);
}
BUS_RegBitWrite(reg, _DAC_CH0CTRL_EN_SHIFT, enable);
}
/***************************************************************************//**
* @brief
* Initialize DAC.
@ -131,8 +127,7 @@ void DAC_Init(DAC_TypeDef *dac, const DAC_Init_TypeDef *init)
BUS_RegBitWrite(&(dac->CH1CTRL), _DAC_CH0CTRL_EN_SHIFT, 0);
/* Load proper calibration data depending on selected reference */
switch (init->reference)
{
switch (init->reference) {
case dacRef2V5:
dac->CAL = DEVINFO->DAC0CAL1;
break;
@ -153,30 +148,25 @@ void DAC_Init(DAC_TypeDef *dac, const DAC_Init_TypeDef *init)
| ((uint32_t)(init->outMode) << _DAC_CTRL_OUTMODE_SHIFT)
| ((uint32_t)(init->convMode) << _DAC_CTRL_CONVMODE_SHIFT);
if (init->ch0ResetPre)
{
if (init->ch0ResetPre) {
tmp |= DAC_CTRL_CH0PRESCRST;
}
if (init->outEnablePRS)
{
if (init->outEnablePRS) {
tmp |= DAC_CTRL_OUTENPRS;
}
if (init->sineEnable)
{
if (init->sineEnable) {
tmp |= DAC_CTRL_SINEMODE;
}
if (init->diff)
{
if (init->diff) {
tmp |= DAC_CTRL_DIFF;
}
dac->CTRL = tmp;
}
/***************************************************************************//**
* @brief
* Initialize DAC channel.
@ -201,32 +191,25 @@ void DAC_InitChannel(DAC_TypeDef *dac,
tmp = (uint32_t)(init->prsSel) << _DAC_CH0CTRL_PRSSEL_SHIFT;
if (init->enable)
{
if (init->enable) {
tmp |= DAC_CH0CTRL_EN;
}
if (init->prsEnable)
{
if (init->prsEnable) {
tmp |= DAC_CH0CTRL_PRSEN;
}
if (init->refreshEnable)
{
if (init->refreshEnable) {
tmp |= DAC_CH0CTRL_REFREN;
}
if (ch)
{
if (ch) {
dac->CH1CTRL = tmp;
}
else
{
} else {
dac->CH0CTRL = tmp;
}
}
/***************************************************************************//**
* @brief
* Set the output signal of a DAC channel to a given value.
@ -244,12 +227,11 @@ void DAC_InitChannel(DAC_TypeDef *dac,
* @param[in] value
* Value to write to the channel output register CHnDATA.
******************************************************************************/
void DAC_ChannelOutputSet( DAC_TypeDef *dac,
unsigned int channel,
uint32_t value )
void DAC_ChannelOutputSet(DAC_TypeDef *dac,
unsigned int channel,
uint32_t value)
{
switch(channel)
{
switch (channel) {
case 0:
DAC_Channel0OutputSet(dac, value);
break;
@ -262,7 +244,6 @@ void DAC_ChannelOutputSet( DAC_TypeDef *dac,
}
}
/***************************************************************************//**
* @brief
* Calculate prescaler value used to determine DAC clock.
@ -289,37 +270,33 @@ uint8_t DAC_PrescaleCalc(uint32_t dacFreq, uint32_t hfperFreq)
uint32_t ret;
/* Make sure selected DAC clock is below max value */
if (dacFreq > DAC_MAX_CLOCK)
{
if (dacFreq > DAC_MAX_CLOCK) {
dacFreq = DAC_MAX_CLOCK;
}
/* Use current HFPER frequency? */
if (!hfperFreq)
{
if (!hfperFreq) {
hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER);
}
/* Iterate in order to determine best prescale value. Only a few possible */
/* values. We start with lowest prescaler value in order to get first */
/* equal or below wanted DAC frequency value. */
for (ret = 0; ret <= (_DAC_CTRL_PRESC_MASK >> _DAC_CTRL_PRESC_SHIFT); ret++)
{
if ((hfperFreq >> ret) <= dacFreq)
for (ret = 0; ret <= (_DAC_CTRL_PRESC_MASK >> _DAC_CTRL_PRESC_SHIFT); ret++) {
if ((hfperFreq >> ret) <= dacFreq) {
break;
}
}
/* If ret is higher than the max prescaler value, make sure to return
the max value. */
if (ret > (_DAC_CTRL_PRESC_MASK >> _DAC_CTRL_PRESC_SHIFT))
{
if (ret > (_DAC_CTRL_PRESC_MASK >> _DAC_CTRL_PRESC_SHIFT)) {
ret = _DAC_CTRL_PRESC_MASK >> _DAC_CTRL_PRESC_SHIFT;
}
return (uint8_t)ret;
}
/***************************************************************************//**
* @brief
* Reset DAC to same state as after a HW reset.
@ -340,7 +317,6 @@ void DAC_Reset(DAC_TypeDef *dac)
/* Do not reset route register, setting should be done independently */
}
/** @} (end addtogroup DAC) */
/** @} (end addtogroup emlib) */
#endif /* defined(DAC_COUNT) && (DAC_COUNT > 0) */

15
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_dbg.c
* @brief Debug (DBG) Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -32,7 +32,7 @@
#include "em_dbg.h"
#if defined( CoreDebug_DHCSR_C_DEBUGEN_Msk )
#if defined(CoreDebug_DHCSR_C_DEBUGEN_Msk)
#include "em_assert.h"
#include "em_cmu.h"
@ -57,7 +57,7 @@
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
#if defined( GPIO_ROUTE_SWOPEN ) || defined( GPIO_ROUTEPEN_SWVPEN )
#if defined(GPIO_ROUTE_SWOPEN) || defined(GPIO_ROUTEPEN_SWVPEN)
/***************************************************************************//**
* @brief
* Enable Serial Wire Output (SWO) pin.
@ -96,10 +96,10 @@ void DBG_SWOEnable(unsigned int location)
EFM_ASSERT(location < AFCHANLOC_MAX);
#if defined ( AF_DBG_SWO_PORT )
#if defined (AF_DBG_SWO_PORT)
port = AF_DBG_SWO_PORT(location);
pin = AF_DBG_SWO_PIN(location);
#elif defined (AF_DBG_SWV_PORT )
#elif defined (AF_DBG_SWV_PORT)
port = AF_DBG_SWV_PORT(location);
pin = AF_DBG_SWV_PIN(location);
#else
@ -107,8 +107,7 @@ void DBG_SWOEnable(unsigned int location)
#endif
/* Port/pin location not defined for device? */
if ((pin < 0) || (port < 0))
{
if ((pin < 0) || (port < 0)) {
EFM_ASSERT(0);
return;
}

281
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_dma.c
* @brief Direct memory access (DMA) module peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -31,7 +31,7 @@
******************************************************************************/
#include "em_dma.h"
#if defined( DMA_PRESENT )
#if defined(DMA_PRESENT)
#include "em_cmu.h"
#include "em_assert.h"
@ -186,12 +186,9 @@ static void DMA_Prepare(unsigned int channel,
primDescr = ((DMA_DESCRIPTOR_TypeDef *)(DMA->CTRLBASE)) + channel;
/* Find descriptor to configure */
if (primary)
{
if (primary) {
descr = primDescr;
}
else
{
} else {
descr = ((DMA_DESCRIPTOR_TypeDef *)(DMA->ALTCTRLBASE)) + channel;
}
@ -199,53 +196,38 @@ static void DMA_Prepare(unsigned int channel,
/* for primary or alternate descriptor. Mainly needed for ping-pong */
/* cycles. */
cb = (DMA_CB_TypeDef *)(primDescr->USER);
if (cb)
{
if (cb) {
cb->primary = (uint8_t)primary;
}
if (src)
{
if (src) {
inc = (descr->CTRL & _DMA_CTRL_SRC_INC_MASK) >> _DMA_CTRL_SRC_INC_SHIFT;
if (inc == _DMA_CTRL_SRC_INC_NONE)
{
if (inc == _DMA_CTRL_SRC_INC_NONE) {
descr->SRCEND = (volatile void*)src;
}
else
{
} else {
descr->SRCEND = (void *)((uint32_t)src + (nMinus1 << inc));
}
}
if (dst)
{
if (dst) {
inc = (descr->CTRL & _DMA_CTRL_DST_INC_MASK) >> _DMA_CTRL_DST_INC_SHIFT;
if (inc == _DMA_CTRL_DST_INC_NONE)
{
if (inc == _DMA_CTRL_DST_INC_NONE) {
descr->DSTEND = dst;
}
else
{
} else {
descr->DSTEND = (void *)((uint32_t)dst + (nMinus1 << inc));
}
}
chBit = 1 << channel;
if (useBurst)
{
if (useBurst) {
DMA->CHUSEBURSTS = chBit;
}
else
{
} else {
DMA->CHUSEBURSTC = chBit;
}
if (primary)
{
if (primary) {
DMA->CHALTC = chBit;
}
else
{
} else {
DMA->CHALTS = chBit;
}
@ -302,15 +284,12 @@ void DMA_IRQHandler(void)
/* defined with high priority, then those with default priority. */
prio = DMA->CHPRIS;
pendingPrio = pending & prio;
for (i = 0; i < 2; i++)
{
for (i = 0; i < 2; i++) {
channel = 0;
/* Process pending interrupts within high/default priority group */
/* honouring priority within group. */
while (pendingPrio)
{
if (pendingPrio & 1)
{
while (pendingPrio) {
if (pendingPrio & 1) {
DMA_DESCRIPTOR_TypeDef *descr = (DMA_DESCRIPTOR_TypeDef *)(DMA->CTRLBASE);
uint32_t chmask = 1 << channel;
@ -322,14 +301,12 @@ void DMA_IRQHandler(void)
/* check if callback is defined anyway. Callback info is always */
/* located in primary descriptor. */
cb = (DMA_CB_TypeDef *)(descr[channel].USER);
if (cb)
{
if (cb) {
/* Toggle next-descriptor indicator always prior to invoking */
/* callback (in case callback reconfigurs something) */
primaryCpy = cb->primary;
cb->primary ^= 1;
if (cb->cbFunc)
{
if (cb->cbFunc) {
cb->cbFunc(channel, (bool)primaryCpy, cb->userPtr);
}
}
@ -346,7 +323,6 @@ void DMA_IRQHandler(void)
#endif /* EXCLUDE_DEFAULT_DMA_IRQ_HANDLER */
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
@ -407,7 +383,6 @@ void DMA_ActivateAuto(unsigned int channel,
DMA->CHSWREQ = chBit; /* Activate with SW request */
}
/***************************************************************************//**
* @brief
* Activate DMA basic cycle (used for memory-peripheral transfers).
@ -468,7 +443,6 @@ void DMA_ActivateBasic(unsigned int channel,
DMA->CHENS = 1 << channel;
}
/***************************************************************************//**
* @brief
* Activate DMA ping-pong cycle (used for memory-peripheral transfers).
@ -553,7 +527,6 @@ void DMA_ActivatePingPong(unsigned int channel,
DMA->CHENS = 1 << channel;
}
/***************************************************************************//**
* @brief
* Activate DMA scatter-gather cycle (used for either memory-peripheral
@ -612,8 +585,8 @@ void DMA_ActivateScatterGather(unsigned int channel,
/* The destination end address in the primary descriptor MUST point */
/* to the corresponding alternate descriptor in scatter-gather mode. */
descr->DSTEND = (uint32_t *)((DMA_DESCRIPTOR_TypeDef *)(DMA->ALTCTRLBASE) +
channel + 1) - 1;
descr->DSTEND = (uint32_t *)((DMA_DESCRIPTOR_TypeDef *)(DMA->ALTCTRLBASE)
+ channel + 1) - 1;
/* The user field of the descriptor is used for callback configuration, */
/* and already configured when channel is configured. Do not modify it. */
@ -630,13 +603,10 @@ void DMA_ActivateScatterGather(unsigned int channel,
/* order to have dma_done signal asserted when complete. Otherwise interrupt */
/* will not be triggered when done. */
altDescr[count - 1].CTRL &= ~_DMA_CTRL_CYCLE_CTRL_MASK;
if (cycleCtrl == dmaCycleCtrlMemScatterGather)
{
if (cycleCtrl == dmaCycleCtrlMemScatterGather) {
altDescr[count - 1].CTRL |= (uint32_t)dmaCycleCtrlAuto
<< _DMA_CTRL_CYCLE_CTRL_SHIFT;
}
else
{
} else {
altDescr[count - 1].CTRL |= (uint32_t)dmaCycleCtrlBasic
<< _DMA_CTRL_CYCLE_CTRL_SHIFT;
}
@ -646,22 +616,21 @@ void DMA_ActivateScatterGather(unsigned int channel,
/* but do for consistency. Always set to alternate, since that is the last */
/* descriptor actually used. */
cb = (DMA_CB_TypeDef *)(descr->USER);
if (cb)
{
if (cb) {
cb->primary = false;
}
/* Configure primary descriptor control word */
descr->CTRL =((uint32_t)dmaDataInc4 << _DMA_CTRL_DST_INC_SHIFT)
| ((uint32_t)dmaDataSize4 << _DMA_CTRL_DST_SIZE_SHIFT)
| ((uint32_t)dmaDataInc4 << _DMA_CTRL_SRC_INC_SHIFT)
| ((uint32_t)dmaDataSize4 << _DMA_CTRL_SRC_SIZE_SHIFT)
/* Use same protection scheme as for alternate descriptors */
| (altDescr->CTRL & _DMA_CTRL_SRC_PROT_CTRL_MASK)
| ((uint32_t)dmaArbitrate4 << _DMA_CTRL_R_POWER_SHIFT)
| (((count * 4) - 1) << _DMA_CTRL_N_MINUS_1_SHIFT)
| (((uint32_t)useBurst & 1) << _DMA_CTRL_NEXT_USEBURST_SHIFT)
| cycleCtrl;
descr->CTRL = ((uint32_t)dmaDataInc4 << _DMA_CTRL_DST_INC_SHIFT)
| ((uint32_t)dmaDataSize4 << _DMA_CTRL_DST_SIZE_SHIFT)
| ((uint32_t)dmaDataInc4 << _DMA_CTRL_SRC_INC_SHIFT)
| ((uint32_t)dmaDataSize4 << _DMA_CTRL_SRC_SIZE_SHIFT)
/* Use same protection scheme as for alternate descriptors */
| (altDescr->CTRL & _DMA_CTRL_SRC_PROT_CTRL_MASK)
| ((uint32_t)dmaArbitrate4 << _DMA_CTRL_R_POWER_SHIFT)
| (((count * 4) - 1) << _DMA_CTRL_N_MINUS_1_SHIFT)
| (((uint32_t)useBurst & 1) << _DMA_CTRL_NEXT_USEBURST_SHIFT)
| cycleCtrl;
chBit = 1 << channel;
@ -673,13 +642,11 @@ void DMA_ActivateScatterGather(unsigned int channel,
/* Send request if memory scatter-gather, otherwise request signal is */
/* provided by peripheral. */
if (cycleCtrl == dmaCycleCtrlMemScatterGather)
{
if (cycleCtrl == dmaCycleCtrlMemScatterGather) {
DMA->CHSWREQ = chBit;
}
}
/***************************************************************************//**
* @brief
* Configure a DMA channel.
@ -710,12 +677,9 @@ void DMA_CfgChannel(unsigned int channel, DMA_CfgChannel_TypeDef *cfg)
descr[channel].USER = (uint32_t)(cfg->cb);
/* Set to specified priority for channel */
if (cfg->highPri)
{
if (cfg->highPri) {
DMA->CHPRIS = 1 << channel;
}
else
{
} else {
DMA->CHPRIC = 1 << channel;
}
@ -723,18 +687,14 @@ void DMA_CfgChannel(unsigned int channel, DMA_CfgChannel_TypeDef *cfg)
DMA->CH[channel].CTRL = cfg->select;
/* Enable/disable interrupt as specified */
if (cfg->enableInt)
{
if (cfg->enableInt) {
DMA->IFC = (1 << channel);
BUS_RegBitWrite(&(DMA->IEN), channel, 1);
}
else
{
} else {
BUS_RegBitWrite(&(DMA->IEN), channel, 0);
}
}
/***************************************************************************//**
* @brief
* Configure DMA descriptor for auto-request, basic or ping-pong DMA cycles.
@ -783,12 +743,9 @@ void DMA_CfgDescr(unsigned int channel,
EFM_ASSERT(cfg);
/* Find descriptor to configure */
if (primary)
{
if (primary) {
descr = (DMA_DESCRIPTOR_TypeDef *)DMA->CTRLBASE;
}
else
{
} else {
descr = (DMA_DESCRIPTOR_TypeDef *)DMA->ALTCTRLBASE;
}
descr += channel;
@ -806,8 +763,7 @@ void DMA_CfgDescr(unsigned int channel,
| DMA_CTRL_CYCLE_CTRL_INVALID; /* Set when activated */
}
#if defined( _DMA_LOOP0_MASK ) && defined( _DMA_LOOP1_MASK )
#if defined(_DMA_LOOP0_MASK) && defined(_DMA_LOOP1_MASK)
/***************************************************************************//**
* @brief Configure DMA channel for Loop mode or 2D transfer.
*
@ -827,22 +783,20 @@ void DMA_CfgLoop(unsigned int channel, DMA_CfgLoop_TypeDef *cfg)
EFM_ASSERT(cfg->nMinus1 <= 1023);
/* Configure LOOP setting */
switch( channel )
{
case 0:
DMA->LOOP0 = (cfg->enable << _DMA_LOOP0_EN_SHIFT)
| (cfg->nMinus1 << _DMA_LOOP0_WIDTH_SHIFT);
break;
case 1:
DMA->LOOP1 = (cfg->enable << _DMA_LOOP1_EN_SHIFT)
| (cfg->nMinus1 << _DMA_LOOP1_WIDTH_SHIFT);
break;
switch ( channel ) {
case 0:
DMA->LOOP0 = (cfg->enable << _DMA_LOOP0_EN_SHIFT)
| (cfg->nMinus1 << _DMA_LOOP0_WIDTH_SHIFT);
break;
case 1:
DMA->LOOP1 = (cfg->enable << _DMA_LOOP1_EN_SHIFT)
| (cfg->nMinus1 << _DMA_LOOP1_WIDTH_SHIFT);
break;
}
}
#endif
#if defined( _DMA_RECT0_MASK )
#if defined(_DMA_RECT0_MASK)
/***************************************************************************//**
* @brief Configure DMA channel 2D transfer properties.
*
@ -862,13 +816,12 @@ void DMA_CfgRect(unsigned int channel, DMA_CfgRect_TypeDef *cfg)
EFM_ASSERT(cfg->height <= 1023);
/* Configure rectangular/2D copy */
DMA->RECT0 = (cfg->dstStride << _DMA_RECT0_DSTSTRIDE_SHIFT)
| (cfg->srcStride << _DMA_RECT0_SRCSTRIDE_SHIFT)
| (cfg->height << _DMA_RECT0_HEIGHT_SHIFT);
DMA->RECT0 = (cfg->dstStride << _DMA_RECT0_DSTSTRIDE_SHIFT)
| (cfg->srcStride << _DMA_RECT0_SRCSTRIDE_SHIFT)
| (cfg->height << _DMA_RECT0_HEIGHT_SHIFT);
}
#endif
/***************************************************************************//**
* @brief
* Configure an alternate DMA descriptor for use with scatter-gather DMA
@ -907,22 +860,16 @@ void DMA_CfgDescrScatterGather(DMA_DESCRIPTOR_TypeDef *descr,
/* Point to selected entry in alternate descriptor table */
descr += indx;
if (cfg->srcInc == dmaDataIncNone)
{
if (cfg->srcInc == dmaDataIncNone) {
descr->SRCEND = cfg->src;
}
else
{
} else {
descr->SRCEND = (void *)((uint32_t)(cfg->src)
+ ((uint32_t)(cfg->nMinus1) << cfg->srcInc));
}
if (cfg->dstInc == dmaDataIncNone)
{
if (cfg->dstInc == dmaDataIncNone) {
descr->DSTEND = cfg->dst;
}
else
{
} else {
descr->DSTEND = (void *)((uint32_t)(cfg->dst)
+ ((uint32_t)(cfg->nMinus1) << cfg->dstInc));
}
@ -930,31 +877,27 @@ void DMA_CfgDescrScatterGather(DMA_DESCRIPTOR_TypeDef *descr,
/* User definable part not used */
descr->USER = 0;
if (cfg->peripheral)
{
if (cfg->peripheral) {
cycleCtrl = (uint32_t)dmaCycleCtrlPerScatterGather + 1;
}
else
{
} else {
cycleCtrl = (uint32_t)dmaCycleCtrlMemScatterGather + 1;
}
descr->CTRL =(cfg->dstInc << _DMA_CTRL_DST_INC_SHIFT)
| (cfg->size << _DMA_CTRL_DST_SIZE_SHIFT)
| (cfg->srcInc << _DMA_CTRL_SRC_INC_SHIFT)
| (cfg->size << _DMA_CTRL_SRC_SIZE_SHIFT)
| ((uint32_t)(cfg->hprot) << _DMA_CTRL_SRC_PROT_CTRL_SHIFT)
| (cfg->arbRate << _DMA_CTRL_R_POWER_SHIFT)
| ((uint32_t)(cfg->nMinus1) << _DMA_CTRL_N_MINUS_1_SHIFT)
/* Never set next useburst bit, since the descriptor used after the */
/* alternate descriptor is the primary descriptor which operates on */
/* memory. If the alternate descriptors need to have useBurst set, this */
/* done when setting up the primary descriptor, ie when activating. */
| (0 << _DMA_CTRL_NEXT_USEBURST_SHIFT)
| (cycleCtrl << _DMA_CTRL_CYCLE_CTRL_SHIFT);
descr->CTRL = (cfg->dstInc << _DMA_CTRL_DST_INC_SHIFT)
| (cfg->size << _DMA_CTRL_DST_SIZE_SHIFT)
| (cfg->srcInc << _DMA_CTRL_SRC_INC_SHIFT)
| (cfg->size << _DMA_CTRL_SRC_SIZE_SHIFT)
| ((uint32_t)(cfg->hprot) << _DMA_CTRL_SRC_PROT_CTRL_SHIFT)
| (cfg->arbRate << _DMA_CTRL_R_POWER_SHIFT)
| ((uint32_t)(cfg->nMinus1) << _DMA_CTRL_N_MINUS_1_SHIFT)
/* Never set next useburst bit, since the descriptor used after the */
/* alternate descriptor is the primary descriptor which operates on */
/* memory. If the alternate descriptors need to have useBurst set, this */
/* done when setting up the primary descriptor, ie when activating. */
| (0 << _DMA_CTRL_NEXT_USEBURST_SHIFT)
| (cycleCtrl << _DMA_CTRL_CYCLE_CTRL_SHIFT);
}
/***************************************************************************//**
* @brief
* Enable or disable a DMA channel.
@ -975,17 +918,13 @@ void DMA_ChannelEnable(unsigned int channel, bool enable)
{
EFM_ASSERT(channel < DMA_CHAN_COUNT);
if (enable)
{
DMA->CHENS = 1<<channel;
}
else
{
DMA->CHENC = 1<<channel;
if (enable) {
DMA->CHENS = 1 << channel;
} else {
DMA->CHENC = 1 << channel;
}
}
/***************************************************************************//**
* @brief
* Check if DMA channel is enabled.
@ -1007,7 +946,6 @@ bool DMA_ChannelEnabled(unsigned int channel)
return (bool)((DMA->CHENS >> channel) & 1);
}
/***************************************************************************//**
* @brief
* Enable or disable a DMA channel request.
@ -1026,17 +964,13 @@ void DMA_ChannelRequestEnable(unsigned int channel, bool enable)
{
EFM_ASSERT(channel < DMA_CHAN_COUNT);
if (enable)
{
BUS_RegBitWrite (&DMA->CHREQMASKC, channel, 1);
}
else
{
BUS_RegBitWrite (&DMA->CHREQMASKS, channel, 1);
if (enable) {
BUS_RegBitWrite(&DMA->CHREQMASKC, channel, 1);
} else {
BUS_RegBitWrite(&DMA->CHREQMASKS, channel, 1);
}
}
/***************************************************************************//**
* @brief
* Initializes DMA controller.
@ -1090,7 +1024,6 @@ void DMA_Init(DMA_Init_TypeDef *init)
| DMA_CONFIG_EN;
}
/***************************************************************************//**
* @brief
* Refresh a descriptor used in a DMA ping-pong cycle.
@ -1150,58 +1083,41 @@ void DMA_RefreshPingPong(unsigned int channel,
EFM_ASSERT(nMinus1 <= (_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT));
/* The ping-pong DMA cycle may be stopped by issuing a basic cycle type */
if (stop)
{
if (stop) {
cycleCtrl = dmaCycleCtrlBasic;
}
else
{
} else {
cycleCtrl = dmaCycleCtrlPingPong;
}
/* Find descriptor to configure */
if (primary)
{
if (primary) {
descr = ((DMA_DESCRIPTOR_TypeDef *)(DMA->CTRLBASE)) + channel;
}
else
{
} else {
descr = ((DMA_DESCRIPTOR_TypeDef *)(DMA->ALTCTRLBASE)) + channel;
}
if (src)
{
if (src) {
inc = (descr->CTRL & _DMA_CTRL_SRC_INC_MASK) >> _DMA_CTRL_SRC_INC_SHIFT;
if (inc == _DMA_CTRL_SRC_INC_NONE)
{
if (inc == _DMA_CTRL_SRC_INC_NONE) {
descr->SRCEND = (volatile void*)src;
}
else
{
} else {
descr->SRCEND = (void *)((uint32_t)src + (nMinus1 << inc));
}
}
if (dst)
{
if (dst) {
inc = (descr->CTRL & _DMA_CTRL_DST_INC_MASK) >> _DMA_CTRL_DST_INC_SHIFT;
if (inc == _DMA_CTRL_DST_INC_NONE)
{
if (inc == _DMA_CTRL_DST_INC_NONE) {
descr->DSTEND = dst;
}
else
{
} else {
descr->DSTEND = (void *)((uint32_t)dst + (nMinus1 << inc));
}
}
chBit = 1 << channel;
if (useBurst)
{
if (useBurst) {
DMA->CHUSEBURSTS = chBit;
}
else
{
} else {
DMA->CHUSEBURSTC = chBit;
}
@ -1212,7 +1128,6 @@ void DMA_RefreshPingPong(unsigned int channel,
descr->CTRL = tmp;
}
/***************************************************************************//**
* @brief
* Reset the DMA controller.
@ -1243,13 +1158,11 @@ void DMA_Reset(void)
DMA->IFC = _DMA_IFC_MASK;
/* Clear channel control flags */
for (i = 0; i < DMA_CHAN_COUNT; i++)
{
for (i = 0; i < DMA_CHAN_COUNT; i++) {
DMA->CH[i].CTRL = _DMA_CH_CTRL_RESETVALUE;
}
}
/** @} (end addtogroup DMA) */
/** @} (end addtogroup emlib) */
#endif /* defined( DMA_PRESENT ) */

453
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_ebi.c
* @brief External Bus Interface (EBI) Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -50,6 +50,55 @@
* @{
******************************************************************************/
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/* The ROUTE register has been renamed in the newest platform so these register
* field names have been created in order to make it easier to work with both
* the new and the old names in a generic way. */
#if defined(_EBI_ROUTE_MASK)
#define _EBI_GENERIC_ALEPEN_SHIFT _EBI_ROUTE_ALEPEN_SHIFT
#define _EBI_GENERIC_BLPEN_SHIFT _EBI_ROUTE_BLPEN_SHIFT
#define _EBI_GENERIC_EBIPEN_SHIFT _EBI_ROUTE_EBIPEN_SHIFT
#define _EBI_GENERIC_CS0PEN_SHIFT _EBI_ROUTE_CS0PEN_SHIFT
#define _EBI_GENERIC_CS1PEN_SHIFT _EBI_ROUTE_CS1PEN_SHIFT
#define _EBI_GENERIC_CS2PEN_SHIFT _EBI_ROUTE_CS2PEN_SHIFT
#define _EBI_GENERIC_CS3PEN_SHIFT _EBI_ROUTE_CS3PEN_SHIFT
#define _EBI_GENERIC_RESETVALUE _EBI_ROUTE_RESETVALUE
#define EBI_GENERIC_ROUTE_REG EBI->ROUTE
#define _EBI_GENERIC_ALB_MASK _EBI_ROUTE_ALB_MASK
#define _EBI_GENERIC_APEN_MASK _EBI_ROUTE_APEN_MASK
#define EBI_GENERIC_TFTPEN EBI_ROUTE_TFTPEN
#else
#define _EBI_GENERIC_ALEPEN_SHIFT _EBI_ROUTEPEN_ALEPEN_SHIFT
#define _EBI_GENERIC_BLPEN_SHIFT _EBI_ROUTEPEN_BLPEN_SHIFT
#define _EBI_GENERIC_EBIPEN_SHIFT _EBI_ROUTEPEN_EBIPEN_SHIFT
#define _EBI_GENERIC_CS0PEN_SHIFT _EBI_ROUTEPEN_CS0PEN_SHIFT
#define _EBI_GENERIC_CS1PEN_SHIFT _EBI_ROUTEPEN_CS1PEN_SHIFT
#define _EBI_GENERIC_CS2PEN_SHIFT _EBI_ROUTEPEN_CS2PEN_SHIFT
#define _EBI_GENERIC_CS3PEN_SHIFT _EBI_ROUTEPEN_CS3PEN_SHIFT
#define _EBI_GENERIC_RESETVALUE _EBI_ROUTEPEN_RESETVALUE
#define EBI_GENERIC_ROUTE_REG EBI->ROUTEPEN
#define _EBI_GENERIC_ALB_MASK _EBI_ROUTEPEN_ALB_MASK
#define _EBI_GENERIC_APEN_MASK _EBI_ROUTEPEN_APEN_MASK
#define EBI_GENERIC_TFTPEN EBI_ROUTEPEN_TFTPEN
#endif
/***************************************************************************//**
* @brief
* Perform a single-bit write operation on a EBI route register
*
* @param[in] bit
* bit Bit position to write, 0-31
*
* @param[in] val
* 0 to clear bit and 1 to set bit
******************************************************************************/
__STATIC_INLINE void EBI_RouteBitWrite(uint32_t bit, uint32_t val)
{
BUS_RegBitWrite(&(EBI_GENERIC_ROUTE_REG), bit, val);
}
/** @endcond */
/***************************************************************************//**
* @brief
* Configure and enable External Bus Interface
@ -65,7 +114,18 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
{
uint32_t ctrl = EBI->CTRL;
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if defined(_EFM32_GECKO_FAMILY)
/* Set polarity of address ready */
EBI_PolaritySet(ebiLineARDY, ebiInit->ardyPolarity);
/* Set polarity of address latch enable */
EBI_PolaritySet(ebiLineALE, ebiInit->alePolarity);
/* Set polarity of write enable */
EBI_PolaritySet(ebiLineWE, ebiInit->wePolarity);
/* Set polarity of read enable */
EBI_PolaritySet(ebiLineRE, ebiInit->rePolarity);
/* Set polarity of chip select lines */
EBI_PolaritySet(ebiLineCS, ebiInit->csPolarity);
#else
/* Enable Independent Timing for devices that supports it */
ctrl |= EBI_CTRL_ITS;
@ -81,23 +141,36 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
EBI_BankPolaritySet(ebiInit->banks, ebiLineCS, ebiInit->csPolarity);
/* Set polarity of byte lane line */
EBI_BankPolaritySet(ebiInit->banks, ebiLineBL, ebiInit->blPolarity);
#else
/* Set polarity of address ready */
EBI_PolaritySet(ebiLineARDY, ebiInit->ardyPolarity);
/* Set polarity of address latch enable */
EBI_PolaritySet(ebiLineALE, ebiInit->alePolarity);
/* Set polarity of write enable */
EBI_PolaritySet(ebiLineWE, ebiInit->wePolarity);
/* Set polarity of read enable */
EBI_PolaritySet(ebiLineRE, ebiInit->rePolarity);
/* Set polarity of chip select lines */
EBI_PolaritySet(ebiLineCS, ebiInit->csPolarity);
#endif
/* Configure EBI mode and control settings */
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
if (ebiInit->banks & EBI_BANK0)
{
#if defined(_EFM32_GECKO_FAMILY)
ctrl &= ~(_EBI_CTRL_MODE_MASK
| _EBI_CTRL_ARDYEN_MASK
| _EBI_CTRL_ARDYTODIS_MASK
| _EBI_CTRL_BANK0EN_MASK
| _EBI_CTRL_BANK1EN_MASK
| _EBI_CTRL_BANK2EN_MASK
| _EBI_CTRL_BANK3EN_MASK);
if ( ebiInit->enable) {
if ( ebiInit->banks & EBI_BANK0 ) {
ctrl |= EBI_CTRL_BANK0EN;
}
if ( ebiInit->banks & EBI_BANK1 ) {
ctrl |= EBI_CTRL_BANK1EN;
}
if ( ebiInit->banks & EBI_BANK2 ) {
ctrl |= EBI_CTRL_BANK2EN;
}
if ( ebiInit->banks & EBI_BANK3 ) {
ctrl |= EBI_CTRL_BANK3EN;
}
}
ctrl |= ebiInit->mode;
ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
#else
if (ebiInit->banks & EBI_BANK0) {
ctrl &= ~(_EBI_CTRL_MODE_MASK
| _EBI_CTRL_ARDYEN_MASK
| _EBI_CTRL_ARDYTODIS_MASK
@ -109,13 +182,11 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL_SHIFT);
ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE_SHIFT);
if ( ebiInit->enable)
{
if ( ebiInit->enable) {
ctrl |= EBI_CTRL_BANK0EN;
}
}
if (ebiInit->banks & EBI_BANK1)
{
if (ebiInit->banks & EBI_BANK1) {
ctrl &= ~(_EBI_CTRL_BL1_MASK
| _EBI_CTRL_MODE1_MASK
| _EBI_CTRL_ARDY1EN_MASK
@ -127,13 +198,11 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO1DIS_SHIFT);
ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL1_SHIFT);
ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE1_SHIFT);
if ( ebiInit->enable)
{
if ( ebiInit->enable) {
ctrl |= EBI_CTRL_BANK1EN;
}
}
if (ebiInit->banks & EBI_BANK2)
{
if (ebiInit->banks & EBI_BANK2) {
ctrl &= ~(_EBI_CTRL_BL2_MASK
| _EBI_CTRL_MODE2_MASK
| _EBI_CTRL_ARDY2EN_MASK
@ -145,13 +214,11 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO2DIS_SHIFT);
ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL2_SHIFT);
ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE2_SHIFT);
if ( ebiInit->enable)
{
if ( ebiInit->enable) {
ctrl |= EBI_CTRL_BANK2EN;
}
}
if (ebiInit->banks & EBI_BANK3)
{
if (ebiInit->banks & EBI_BANK3) {
ctrl &= ~(_EBI_CTRL_BL3_MASK
| _EBI_CTRL_MODE3_MASK
| _EBI_CTRL_ARDY3EN_MASK
@ -163,45 +230,23 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO3DIS_SHIFT);
ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL3_SHIFT);
ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE3_SHIFT);
if ( ebiInit->enable)
{
if ( ebiInit->enable) {
ctrl |= EBI_CTRL_BANK3EN;
}
}
#else
ctrl &= ~(_EBI_CTRL_MODE_MASK
| _EBI_CTRL_ARDYEN_MASK
| _EBI_CTRL_ARDYTODIS_MASK
| _EBI_CTRL_BANK0EN_MASK
| _EBI_CTRL_BANK1EN_MASK
| _EBI_CTRL_BANK2EN_MASK
| _EBI_CTRL_BANK3EN_MASK);
if ( ebiInit->enable)
{
if ( ebiInit->banks & EBI_BANK0 )
{
ctrl |= EBI_CTRL_BANK0EN;
}
if ( ebiInit->banks & EBI_BANK1 )
{
ctrl |= EBI_CTRL_BANK1EN;
}
if ( ebiInit->banks & EBI_BANK2 )
{
ctrl |= EBI_CTRL_BANK2EN;
}
if ( ebiInit->banks & EBI_BANK3 )
{
ctrl |= EBI_CTRL_BANK3EN;
}
}
ctrl |= ebiInit->mode;
ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
#endif
/* Configure timing */
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if defined(_EFM32_GECKO_FAMILY)
EBI_ReadTimingSet(ebiInit->readSetupCycles,
ebiInit->readStrobeCycles,
ebiInit->readHoldCycles);
EBI_WriteTimingSet(ebiInit->writeSetupCycles,
ebiInit->writeStrobeCycles,
ebiInit->writeHoldCycles);
EBI_AddressTimingSet(ebiInit->addrSetupCycles,
ebiInit->addrHoldCycles);
#else
EBI_BankReadTimingSet(ebiInit->banks,
ebiInit->readSetupCycles,
ebiInit->readStrobeCycles,
@ -222,57 +267,49 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
ebiInit->addrHoldCycles);
EBI_BankAddressTimingConfig(ebiInit->banks,
ebiInit->addrHalfALE);
#else
EBI_ReadTimingSet(ebiInit->readSetupCycles,
ebiInit->readStrobeCycles,
ebiInit->readHoldCycles);
EBI_WriteTimingSet(ebiInit->writeSetupCycles,
ebiInit->writeStrobeCycles,
ebiInit->writeHoldCycles);
EBI_AddressTimingSet(ebiInit->addrSetupCycles,
ebiInit->addrHoldCycles);
#endif
/* Activate new configuration */
EBI->CTRL = ctrl;
/* Configure Adress Latch Enable */
switch (ebiInit->mode)
{
switch (ebiInit->mode) {
case ebiModeD16A16ALE:
case ebiModeD8A24ALE:
/* Address Latch Enable */
BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 1);
EBI_RouteBitWrite(_EBI_GENERIC_ALEPEN_SHIFT, 1);
break;
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if defined(EBI_CTRL_MODE_D16)
case ebiModeD16:
#endif
case ebiModeD8A8:
/* Make sure Address Latch is disabled */
BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 0);
EBI_RouteBitWrite(_EBI_GENERIC_ALEPEN_SHIFT, 0);
break;
}
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if !defined(_EFM32_GECKO_FAMILY)
/* Limit pin enable */
EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_ALB_MASK) | ebiInit->aLow;
EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_APEN_MASK) | ebiInit->aHigh;
EBI_GENERIC_ROUTE_REG = (EBI_GENERIC_ROUTE_REG & ~_EBI_GENERIC_ALB_MASK) | ebiInit->aLow;
EBI_GENERIC_ROUTE_REG = (EBI_GENERIC_ROUTE_REG & ~_EBI_GENERIC_APEN_MASK) | ebiInit->aHigh;
#if defined(_EBI_ROUTE_LOCATION_MASK)
/* Location */
EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_LOCATION_MASK) | ebiInit->location;
#endif
/* Enable EBI BL pin if necessary */
if(ctrl & (_EBI_CTRL_BL_MASK|_EBI_CTRL_BL1_MASK|_EBI_CTRL_BL2_MASK|_EBI_CTRL_BL3_MASK))
{
BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_BLPEN_SHIFT, ebiInit->blEnable);
if (ctrl & (_EBI_CTRL_BL_MASK | _EBI_CTRL_BL1_MASK | _EBI_CTRL_BL2_MASK | _EBI_CTRL_BL3_MASK)) {
EBI_RouteBitWrite(_EBI_GENERIC_BLPEN_SHIFT, ebiInit->blEnable);
}
#endif
/* Enable EBI pins EBI_WEn and EBI_REn */
BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_EBIPEN_SHIFT, 1);
EBI_RouteBitWrite(_EBI_GENERIC_EBIPEN_SHIFT, 1);
/* Enable chip select lines */
EBI_ChipSelectEnable(ebiInit->csLines, true);
}
/***************************************************************************//**
* @brief
* Disable External Bus Interface
@ -280,12 +317,11 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
void EBI_Disable(void)
{
/* Disable pins */
EBI->ROUTE = _EBI_ROUTE_RESETVALUE;
EBI_GENERIC_ROUTE_REG = _EBI_GENERIC_RESETVALUE;
/* Disable banks */
EBI->CTRL = _EBI_CTRL_RESETVALUE;
}
/***************************************************************************//**
* @brief
* Enable or disable EBI Bank
@ -298,25 +334,20 @@ void EBI_Disable(void)
******************************************************************************/
void EBI_BankEnable(uint32_t banks, bool enable)
{
if (banks & EBI_BANK0)
{
if (banks & EBI_BANK0) {
BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK0EN_SHIFT, enable);
}
if (banks & EBI_BANK1)
{
if (banks & EBI_BANK1) {
BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK1EN_SHIFT, enable);
}
if (banks & EBI_BANK2)
{
if (banks & EBI_BANK2) {
BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK2EN_SHIFT, enable);
}
if (banks & EBI_BANK3)
{
if (banks & EBI_BANK3) {
BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK3EN_SHIFT, enable);
}
}
/***************************************************************************//**
* @brief
* Return base address of EBI bank
@ -329,22 +360,20 @@ void EBI_BankEnable(uint32_t banks, bool enable)
******************************************************************************/
uint32_t EBI_BankAddress(uint32_t bank)
{
#if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
if(EBI->CTRL & EBI_CTRL_ALTMAP)
{
switch (bank)
{
#if defined (EBI_CTRL_ALTMAP)
if (EBI->CTRL & EBI_CTRL_ALTMAP) {
switch (bank) {
case EBI_BANK0:
return(EBI_MEM_BASE);
return EBI_MEM_BASE;
case EBI_BANK1:
return(EBI_MEM_BASE + 0x10000000UL);
return EBI_MEM_BASE + 0x10000000UL;
case EBI_BANK2:
return(EBI_MEM_BASE + 0x20000000UL);
return EBI_MEM_BASE + 0x20000000UL;
case EBI_BANK3:
return(EBI_MEM_BASE + 0x30000000UL);
return EBI_MEM_BASE + 0x30000000UL;
default:
EFM_ASSERT(0);
@ -352,19 +381,18 @@ uint32_t EBI_BankAddress(uint32_t bank)
}
}
#endif
switch (bank)
{
switch (bank) {
case EBI_BANK0:
return(EBI_MEM_BASE);
return EBI_MEM_BASE;
case EBI_BANK1:
return(EBI_MEM_BASE + 0x04000000UL);
return EBI_MEM_BASE + 0x04000000UL;
case EBI_BANK2:
return(EBI_MEM_BASE + 0x08000000UL);
return EBI_MEM_BASE + 0x08000000UL;
case EBI_BANK3:
return(EBI_MEM_BASE + 0x0C000000UL);
return EBI_MEM_BASE + 0x0C000000UL;
default:
EFM_ASSERT(0);
@ -373,7 +401,6 @@ uint32_t EBI_BankAddress(uint32_t bank)
return 0;
}
/***************************************************************************//**
* @brief
* Enable or disable EBI Chip Select
@ -386,25 +413,20 @@ uint32_t EBI_BankAddress(uint32_t bank)
******************************************************************************/
void EBI_ChipSelectEnable(uint32_t cs, bool enable)
{
if (cs & EBI_CS0)
{
BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS0PEN_SHIFT, enable);
if (cs & EBI_CS0) {
EBI_RouteBitWrite(_EBI_GENERIC_CS0PEN_SHIFT, enable);
}
if (cs & EBI_CS1)
{
BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS1PEN_SHIFT, enable);
if (cs & EBI_CS1) {
EBI_RouteBitWrite(_EBI_GENERIC_CS1PEN_SHIFT, enable);
}
if (cs & EBI_CS2)
{
BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS2PEN_SHIFT, enable);
if (cs & EBI_CS2) {
EBI_RouteBitWrite(_EBI_GENERIC_CS2PEN_SHIFT, enable);
}
if (cs & EBI_CS3)
{
BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS3PEN_SHIFT, enable);
if (cs & EBI_CS3) {
EBI_RouteBitWrite(_EBI_GENERIC_CS3PEN_SHIFT, enable);
}
}
/***************************************************************************//**
* @brief
* Configure EBI pin polarity
@ -417,41 +439,42 @@ void EBI_ChipSelectEnable(uint32_t cs, bool enable)
******************************************************************************/
void EBI_PolaritySet(EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
{
switch (line)
{
switch (line) {
case ebiLineARDY:
BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
break;
case ebiLineALE:
BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ALEPOL_SHIFT, polarity);
BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_ALEPOL_SHIFT, polarity);
break;
case ebiLineWE:
BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_WEPOL_SHIFT, polarity);
BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_WEPOL_SHIFT, polarity);
break;
case ebiLineRE:
BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_REPOL_SHIFT, polarity);
BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_REPOL_SHIFT, polarity);
break;
case ebiLineCS:
BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_CSPOL_SHIFT, polarity);
BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_CSPOL_SHIFT, polarity);
break;
#if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if defined(_EBI_POLARITY_BLPOL_MASK)
case ebiLineBL:
BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_BLPOL_SHIFT, polarity);
BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_BLPOL_SHIFT, polarity);
break;
#endif
#if defined (_EBI_TFTPOLARITY_MASK)
case ebiLineTFTVSync:
BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
BUS_RegBitWrite(&EBI->TFTPOLARITY, _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
break;
case ebiLineTFTHSync:
BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
BUS_RegBitWrite(&EBI->TFTPOLARITY, _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
break;
case ebiLineTFTDataEn:
BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
BUS_RegBitWrite(&EBI->TFTPOLARITY, _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
break;
case ebiLineTFTDClk:
BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
BUS_RegBitWrite(&EBI->TFTPOLARITY, _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
break;
case ebiLineTFTCS:
BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
BUS_RegBitWrite(&EBI->TFTPOLARITY, _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
break;
#endif
default:
@ -460,7 +483,6 @@ void EBI_PolaritySet(EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
}
}
/***************************************************************************//**
* @brief
* Configure timing values of read bus accesses
@ -489,7 +511,6 @@ void EBI_ReadTimingSet(int setupCycles, int strobeCycles, int holdCycles)
| (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
| (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
EBI->RDTIMING = (EBI->RDTIMING
& ~(_EBI_RDTIMING_RDSETUP_MASK
| _EBI_RDTIMING_RDSTRB_MASK
@ -497,7 +518,6 @@ void EBI_ReadTimingSet(int setupCycles, int strobeCycles, int holdCycles)
| readTiming;
}
/***************************************************************************//**
* @brief
* Configure timing values of write bus accesses
@ -532,7 +552,6 @@ void EBI_WriteTimingSet(int setupCycles, int strobeCycles, int holdCycles)
| writeTiming;
}
/***************************************************************************//**
* @brief
* Configure timing values of address latch bus accesses
@ -562,7 +581,7 @@ void EBI_AddressTimingSet(int setupCycles, int holdCycles)
| addressLatchTiming;
}
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if defined(_EBI_TFTCTRL_MASK)
/***************************************************************************//**
* @brief
* Configure and initialize TFT Direct Drive
@ -614,13 +633,11 @@ void EBI_TFTInit(const EBI_TFTInit_TypeDef *ebiTFTInit)
EBI->TFTCTRL = ctrl;
/* Enable TFT pins */
if (ebiTFTInit->driveMode != ebiTFTDDModeDisabled)
{
EBI->ROUTE |= EBI_ROUTE_TFTPEN;
if (ebiTFTInit->driveMode != ebiTFTDDModeDisabled) {
EBI_GENERIC_ROUTE_REG |= EBI_GENERIC_TFTPEN;
}
}
/***************************************************************************//**
* @brief
* Configure and initialize TFT size settings
@ -632,11 +649,11 @@ void EBI_TFTInit(const EBI_TFTInit_TypeDef *ebiTFTInit)
******************************************************************************/
void EBI_TFTSizeSet(uint32_t horizontal, uint32_t vertical)
{
EFM_ASSERT((horizontal-1) < 1024);
EFM_ASSERT((vertical-1) < 1024);
EFM_ASSERT((horizontal - 1) < 1024);
EFM_ASSERT((vertical - 1) < 1024);
EBI->TFTSIZE = ((horizontal-1) << _EBI_TFTSIZE_HSZ_SHIFT)
| ((vertical-1) << _EBI_TFTSIZE_VSZ_SHIFT);
EBI->TFTSIZE = ((horizontal - 1) << _EBI_TFTSIZE_HSZ_SHIFT)
| ((vertical - 1) << _EBI_TFTSIZE_VSZ_SHIFT);
}
/***************************************************************************//**
@ -654,14 +671,13 @@ void EBI_TFTHPorchSet(int front, int back, int pulseWidth)
{
EFM_ASSERT(front < 256);
EFM_ASSERT(back < 256);
EFM_ASSERT((pulseWidth-1) < 128);
EFM_ASSERT((pulseWidth - 1) < 128);
EBI->TFTHPORCH = (front << _EBI_TFTHPORCH_HFPORCH_SHIFT)
| (back << _EBI_TFTHPORCH_HBPORCH_SHIFT)
| ((pulseWidth-1) << _EBI_TFTHPORCH_HSYNC_SHIFT);
| ((pulseWidth - 1) << _EBI_TFTHPORCH_HSYNC_SHIFT);
}
/***************************************************************************//**
* @brief
* Configure Vertical Porch Settings
@ -677,14 +693,13 @@ void EBI_TFTVPorchSet(int front, int back, int pulseWidth)
{
EFM_ASSERT(front < 256);
EFM_ASSERT(back < 256);
EFM_ASSERT((pulseWidth-1) < 128);
EFM_ASSERT((pulseWidth - 1) < 128);
EBI->TFTVPORCH = (front << _EBI_TFTVPORCH_VFPORCH_SHIFT)
| (back << _EBI_TFTVPORCH_VBPORCH_SHIFT)
| ((pulseWidth-1) << _EBI_TFTVPORCH_VSYNC_SHIFT);
| ((pulseWidth - 1) << _EBI_TFTVPORCH_VSYNC_SHIFT);
}
/***************************************************************************//**
* @brief
* Configure TFT Direct Drive Timing Settings
@ -715,7 +730,7 @@ void EBI_TFTTimingSet(int dclkPeriod, int start, int setup, int hold)
}
#endif
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if !defined(_EFM32_GECKO_FAMILY)
/***************************************************************************//**
* @brief
* Configure read operation parameters for selected bank
@ -734,30 +749,26 @@ void EBI_TFTTimingSet(int dclkPeriod, int start, int setup, int hold)
******************************************************************************/
void EBI_BankReadTimingConfig(uint32_t banks, bool pageMode, bool prefetch, bool halfRE)
{
/* Verify only valid banks are used */
/* Verify only valid banks are used */
EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
/* Configure read operation parameters */
if( banks & EBI_BANK0 )
{
if ( banks & EBI_BANK0 ) {
BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
}
if( banks & EBI_BANK1 )
{
if ( banks & EBI_BANK1 ) {
BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
}
if( banks & EBI_BANK2 )
{
if ( banks & EBI_BANK2 ) {
BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
}
if( banks & EBI_BANK3 )
{
if ( banks & EBI_BANK3 ) {
BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
@ -798,32 +809,28 @@ void EBI_BankReadTimingSet(uint32_t banks, int setupCycles, int strobeCycles, in
| (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
| (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
if (banks & EBI_BANK0)
{
if (banks & EBI_BANK0) {
EBI->RDTIMING = (EBI->RDTIMING
& ~(_EBI_RDTIMING_RDSETUP_MASK
| _EBI_RDTIMING_RDSTRB_MASK
| _EBI_RDTIMING_RDHOLD_MASK))
| readTiming;
}
if (banks & EBI_BANK1)
{
if (banks & EBI_BANK1) {
EBI->RDTIMING1 = (EBI->RDTIMING1
& ~(_EBI_RDTIMING1_RDSETUP_MASK
| _EBI_RDTIMING1_RDSTRB_MASK
| _EBI_RDTIMING1_RDHOLD_MASK))
| _EBI_RDTIMING1_RDSTRB_MASK
| _EBI_RDTIMING1_RDHOLD_MASK))
| readTiming;
}
if (banks & EBI_BANK2)
{
if (banks & EBI_BANK2) {
EBI->RDTIMING2 = (EBI->RDTIMING2
& ~(_EBI_RDTIMING2_RDSETUP_MASK
| _EBI_RDTIMING2_RDSTRB_MASK
| _EBI_RDTIMING2_RDHOLD_MASK))
| readTiming;
}
if (banks & EBI_BANK3)
{
if (banks & EBI_BANK3) {
EBI->RDTIMING3 = (EBI->RDTIMING3
& ~(_EBI_RDTIMING3_RDSETUP_MASK
| _EBI_RDTIMING3_RDSTRB_MASK
@ -832,7 +839,6 @@ void EBI_BankReadTimingSet(uint32_t banks, int setupCycles, int strobeCycles, in
}
}
/***************************************************************************//**
* @brief
* Configure write operation parameters for selected bank
@ -852,29 +858,24 @@ void EBI_BankWriteTimingConfig(uint32_t banks, bool writeBufDisable, bool halfWE
EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
/* Configure write operation parameters */
if( banks & EBI_BANK0 )
{
if ( banks & EBI_BANK0 ) {
BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
}
if( banks & EBI_BANK1 )
{
if ( banks & EBI_BANK1 ) {
BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
}
if( banks & EBI_BANK2 )
{
if ( banks & EBI_BANK2 ) {
BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
}
if( banks & EBI_BANK3 )
{
if ( banks & EBI_BANK3 ) {
BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
}
}
/***************************************************************************//**
* @brief
* Configure timing values of write bus accesses
@ -908,32 +909,28 @@ void EBI_BankWriteTimingSet(uint32_t banks, int setupCycles, int strobeCycles, i
| (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT)
| (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
if (banks & EBI_BANK0)
{
if (banks & EBI_BANK0) {
EBI->WRTIMING = (EBI->WRTIMING
& ~(_EBI_WRTIMING_WRSETUP_MASK
| _EBI_WRTIMING_WRSTRB_MASK
| _EBI_WRTIMING_WRHOLD_MASK))
| writeTiming;
}
if (banks & EBI_BANK1)
{
if (banks & EBI_BANK1) {
EBI->WRTIMING1 = (EBI->WRTIMING1
& ~(_EBI_WRTIMING1_WRSETUP_MASK
| _EBI_WRTIMING1_WRSTRB_MASK
| _EBI_WRTIMING1_WRHOLD_MASK))
| writeTiming;
}
if (banks & EBI_BANK2)
{
if (banks & EBI_BANK2) {
EBI->WRTIMING2 = (EBI->WRTIMING2
& ~(_EBI_WRTIMING2_WRSETUP_MASK
| _EBI_WRTIMING2_WRSTRB_MASK
| _EBI_WRTIMING2_WRHOLD_MASK))
| writeTiming;
}
if (banks & EBI_BANK3)
{
if (banks & EBI_BANK3) {
EBI->WRTIMING3 = (EBI->WRTIMING3
& ~(_EBI_WRTIMING3_WRSETUP_MASK
| _EBI_WRTIMING3_WRSTRB_MASK
@ -942,7 +939,6 @@ void EBI_BankWriteTimingSet(uint32_t banks, int setupCycles, int strobeCycles, i
}
}
/***************************************************************************//**
* @brief
* Configure address operation parameters for selected bank
@ -958,25 +954,20 @@ void EBI_BankAddressTimingConfig(uint32_t banks, bool halfALE)
/* Verify only valid banks are used */
EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
if( banks & EBI_BANK0 )
{
if ( banks & EBI_BANK0 ) {
BUS_RegBitWrite(&EBI->ADDRTIMING, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
}
if( banks & EBI_BANK1 )
{
if ( banks & EBI_BANK1 ) {
BUS_RegBitWrite(&EBI->ADDRTIMING1, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
}
if( banks & EBI_BANK2 )
{
if ( banks & EBI_BANK2 ) {
BUS_RegBitWrite(&EBI->ADDRTIMING2, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
}
if( banks & EBI_BANK3 )
{
if ( banks & EBI_BANK3 ) {
BUS_RegBitWrite(&EBI->ADDRTIMING3, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
}
}
/***************************************************************************//**
* @brief
* Configure timing values of address latch bus accesses
@ -1006,29 +997,25 @@ void EBI_BankAddressTimingSet(uint32_t banks, int setupCycles, int holdCycles)
addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT)
| (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
if (banks & EBI_BANK0)
{
if (banks & EBI_BANK0) {
EBI->ADDRTIMING = (EBI->ADDRTIMING
& ~(_EBI_ADDRTIMING_ADDRSETUP_MASK
| _EBI_ADDRTIMING_ADDRHOLD_MASK))
| addressLatchTiming;
}
if (banks & EBI_BANK1)
{
if (banks & EBI_BANK1) {
EBI->ADDRTIMING1 = (EBI->ADDRTIMING1
& ~(_EBI_ADDRTIMING1_ADDRSETUP_MASK
| _EBI_ADDRTIMING1_ADDRHOLD_MASK))
| addressLatchTiming;
}
if (banks & EBI_BANK2)
{
if (banks & EBI_BANK2) {
EBI->ADDRTIMING2 = (EBI->ADDRTIMING2
& ~(_EBI_ADDRTIMING2_ADDRSETUP_MASK
| _EBI_ADDRTIMING2_ADDRHOLD_MASK))
| addressLatchTiming;
}
if (banks & EBI_BANK3)
{
if (banks & EBI_BANK3) {
EBI->ADDRTIMING3 = (EBI->ADDRTIMING3
& ~(_EBI_ADDRTIMING3_ADDRSETUP_MASK
| _EBI_ADDRTIMING3_ADDRHOLD_MASK))
@ -1036,7 +1023,6 @@ void EBI_BankAddressTimingSet(uint32_t banks, int setupCycles, int holdCycles)
}
}
/***************************************************************************//**
* @brief
* Configure EBI pin polarity for selected bank(s) for devices with individual
@ -1059,37 +1045,26 @@ void EBI_BankPolaritySet(uint32_t banks, EBI_Line_TypeDef line, EBI_Polarity_Typ
/* Verify only valid banks are used */
EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
while (banks)
{
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
if (banks & EBI_BANK0)
{
while (banks) {
if (banks & EBI_BANK0) {
polRegister = &EBI->POLARITY;
bankSet = EBI_BANK0;
}
if (banks & EBI_BANK1)
{
if (banks & EBI_BANK1) {
polRegister = &EBI->POLARITY1;
bankSet = EBI_BANK1;
}
if (banks & EBI_BANK2)
{
if (banks & EBI_BANK2) {
polRegister = &EBI->POLARITY2;
bankSet = EBI_BANK2;
}
if (banks & EBI_BANK3)
{
if (banks & EBI_BANK3) {
polRegister = &EBI->POLARITY3;
bankSet = EBI_BANK3;
}
#else
polRegister = &EBI->POLARITY;
banks = 0;
#endif
/* What line to configure */
switch (line)
{
switch (line) {
case ebiLineARDY:
BUS_RegBitWrite(polRegister, _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
break;
@ -1105,7 +1080,6 @@ void EBI_BankPolaritySet(uint32_t banks, EBI_Line_TypeDef line, EBI_Polarity_Typ
case ebiLineCS:
BUS_RegBitWrite(polRegister, _EBI_POLARITY_CSPOL_SHIFT, polarity);
break;
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
case ebiLineBL:
BUS_RegBitWrite(polRegister, _EBI_POLARITY_BLPOL_SHIFT, polarity);
break;
@ -1124,7 +1098,6 @@ void EBI_BankPolaritySet(uint32_t banks, EBI_Line_TypeDef line, EBI_Polarity_Typ
case ebiLineTFTCS:
BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
break;
#endif
default:
EFM_ASSERT(0);
break;
@ -1133,7 +1106,6 @@ void EBI_BankPolaritySet(uint32_t banks, EBI_Line_TypeDef line, EBI_Polarity_Typ
}
}
/***************************************************************************//**
* @brief
* Configure Byte Lane Enable for select banks
@ -1151,25 +1123,20 @@ void EBI_BankByteLaneEnable(uint32_t banks, bool enable)
EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
/* Configure byte lane support for each selected bank */
if (banks & EBI_BANK0)
{
if (banks & EBI_BANK0) {
BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL_SHIFT, enable);
}
if (banks & EBI_BANK1)
{
if (banks & EBI_BANK1) {
BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL1_SHIFT, enable);
}
if (banks & EBI_BANK2)
{
if (banks & EBI_BANK2) {
BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL2_SHIFT, enable);
}
if (banks & EBI_BANK3)
{
if (banks & EBI_BANK3) {
BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL3_SHIFT, enable);
}
}
/***************************************************************************//**
* @brief
* Configure Alternate Address Map support

1332
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c
View File

File diff suppressed because it is too large Load Diff

28
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpcrc.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file
* @brief General Purpose Cyclic Redundancy Check (GPCRC) API.
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -30,6 +30,7 @@
*
******************************************************************************/
#include "em_common.h"
#include "em_gpcrc.h"
#include "em_assert.h"
@ -73,29 +74,26 @@
void GPCRC_Init(GPCRC_TypeDef * gpcrc, const GPCRC_Init_TypeDef * init)
{
uint32_t polySelect;
uint32_t revPoly = 0;
if (init->crcPoly == 0x04C11DB7)
{
if (init->crcPoly == 0x04C11DB7) {
polySelect = GPCRC_CTRL_POLYSEL_CRC32;
}
else
{
} else {
// If not using the fixed CRC-32 polynomial then we must be using 16-bit
EFM_ASSERT((init->crcPoly & 0xFFFF0000) == 0);
polySelect = GPCRC_CTRL_POLYSEL_16;
revPoly = SL_RBIT16(init->crcPoly);
}
gpcrc->CTRL = (((uint32_t)init->autoInit << _GPCRC_CTRL_AUTOINIT_SHIFT)
| ((uint32_t)init->reverseByteOrder << _GPCRC_CTRL_BYTEREVERSE_SHIFT)
| ((uint32_t)init->reverseBits << _GPCRC_CTRL_BITREVERSE_SHIFT)
| ((uint32_t)init->enableByteMode << _GPCRC_CTRL_BYTEMODE_SHIFT)
| polySelect
| ((uint32_t)init->enable << _GPCRC_CTRL_EN_SHIFT));
| ((uint32_t)init->reverseByteOrder << _GPCRC_CTRL_BYTEREVERSE_SHIFT)
| ((uint32_t)init->reverseBits << _GPCRC_CTRL_BITREVERSE_SHIFT)
| ((uint32_t)init->enableByteMode << _GPCRC_CTRL_BYTEMODE_SHIFT)
| polySelect
| ((uint32_t)init->enable << _GPCRC_CTRL_EN_SHIFT));
if (polySelect == GPCRC_CTRL_POLYSEL_16)
{
if (polySelect == GPCRC_CTRL_POLYSEL_16) {
// Set CRC polynomial value
uint32_t revPoly = __RBIT(init->crcPoly) >> 16;
gpcrc->POLY = revPoly & _GPCRC_POLY_POLY_MASK;
}

90
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c
View File

@ -2,9 +2,9 @@
* @file em_gpio.c
* @brief General Purpose IO (GPIO) peripheral API
* devices.
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -31,7 +31,6 @@
*
******************************************************************************/
#include "em_gpio.h"
#if defined(GPIO_COUNT) && (GPIO_COUNT > 0)
@ -60,12 +59,11 @@
/** Validation of pin typically usable in assert statements. */
#define GPIO_DRIVEMODE_VALID(mode) ((mode) <= 3)
#define GPIO_STRENGHT_VALID(strenght) (!((strenght) & \
~(_GPIO_P_CTRL_DRIVESTRENGTH_MASK \
| _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK)))
#define GPIO_STRENGHT_VALID(strenght) (!((strenght) \
& ~(_GPIO_P_CTRL_DRIVESTRENGTH_MASK \
| _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK)))
/** @endcond */
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
@ -82,11 +80,11 @@
******************************************************************************/
void GPIO_DbgLocationSet(unsigned int location)
{
#if defined ( _GPIO_ROUTE_SWLOCATION_MASK )
#if defined (_GPIO_ROUTE_SWLOCATION_MASK)
EFM_ASSERT(location < AFCHANLOC_MAX);
GPIO->ROUTE = (GPIO->ROUTE & ~_GPIO_ROUTE_SWLOCATION_MASK) |
(location << _GPIO_ROUTE_SWLOCATION_SHIFT);
GPIO->ROUTE = (GPIO->ROUTE & ~_GPIO_ROUTE_SWLOCATION_MASK)
| (location << _GPIO_ROUTE_SWLOCATION_SHIFT);
#else
(void)location;
#endif
@ -138,8 +136,8 @@ void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port,
* Configure GPIO external pin interrupt.
*
* @details
* If reconfiguring a GPIO interrupt that is already enabled, it is generally
* recommended to disable it first, see GPIO_Disable().
* It is recommended to disable interrupts before configuring a GPIO pin interrupt.
* See @ref GPIO_IntDisable() for more information.
*
* The actual GPIO interrupt handler must be in place before enabling the
* interrupt.
@ -154,10 +152,10 @@ void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port,
* On series 1 devices, pin number can be selected freely within a group.
* Interrupt numbers are divided into 4 groups (intNo / 4) and valid pin
* number within the interrupt groups are:
* 0: pins 0-3
* 1: pins 4-7
* 2: pins 8-11
* 3: pins 12-15
* 0: pins 0-3 (interrupt number 0-3)
* 1: pins 4-7 (interrupt number 4-7)
* 2: pins 8-11 (interrupt number 8-11)
* 3: pins 12-15 (interrupt number 12-15)
*
* @param[in] port
* The port to associate with @p pin.
@ -176,7 +174,7 @@ void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port,
*
* @param[in] enable
* Set to true if interrupt shall be enabled after configuration completed,
* false to leave disabled. See GPIO_IntDisable() and GPIO_IntEnable().
* false to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable().
******************************************************************************/
void GPIO_ExtIntConfig(GPIO_Port_TypeDef port,
unsigned int pin,
@ -198,15 +196,12 @@ void GPIO_ExtIntConfig(GPIO_Port_TypeDef port,
/* There are two registers controlling the interrupt configuration:
* The EXTIPSELL register controls pins 0-7 and EXTIPSELH controls
* pins 8-15. */
if (intNo < 8)
{
if (intNo < 8) {
BUS_RegMaskedWrite(&GPIO->EXTIPSELL,
_GPIO_EXTIPSELL_EXTIPSEL0_MASK
<< (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo),
port << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo));
}
else
{
} else {
tmp = intNo - 8;
BUS_RegMaskedWrite(&GPIO->EXTIPSELH,
_GPIO_EXTIPSELH_EXTIPSEL8_MASK
@ -218,16 +213,13 @@ void GPIO_ExtIntConfig(GPIO_Port_TypeDef port,
/* There are two registers controlling the interrupt/pin number mapping:
* The EXTIPINSELL register controls interrupt 0-7 and EXTIPINSELH controls
* interrupt 8-15. */
if (intNo < 8)
{
if (intNo < 8) {
BUS_RegMaskedWrite(&GPIO->EXTIPINSELL,
_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK
<< (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo),
((pin % 4) & _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK)
<< (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo));
}
else
{
} else {
BUS_RegMaskedWrite(&GPIO->EXTIPINSELH,
_GPIO_EXTIPINSELH_EXTIPINSEL8_MASK
<< (_GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT * tmp),
@ -275,39 +267,28 @@ void GPIO_PinModeSet(GPIO_Port_TypeDef port,
/* If disabling pin, do not modify DOUT in order to reduce chance for */
/* glitch/spike (may not be sufficient precaution in all use cases) */
if (mode != gpioModeDisabled)
{
if (out)
{
if (mode != gpioModeDisabled) {
if (out) {
GPIO_PinOutSet(port, pin);
}
else
{
} else {
GPIO_PinOutClear(port, pin);
}
}
/* There are two registers controlling the pins for each port. The MODEL
* register controls pins 0-7 and MODEH controls pins 8-15. */
if (pin < 8)
{
if (pin < 8) {
GPIO->P[port].MODEL = (GPIO->P[port].MODEL & ~(0xFu << (pin * 4)))
| (mode << (pin * 4));
}
else
{
} else {
GPIO->P[port].MODEH = (GPIO->P[port].MODEH & ~(0xFu << ((pin - 8) * 4)))
| (mode << ((pin - 8) * 4));
}
if (mode == gpioModeDisabled)
{
if (out)
{
if (mode == gpioModeDisabled) {
if (out) {
GPIO_PinOutSet(port, pin);
}
else
{
} else {
GPIO_PinOutClear(port, pin);
}
}
@ -331,17 +312,14 @@ GPIO_Mode_TypeDef GPIO_PinModeGet(GPIO_Port_TypeDef port,
{
EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
if (pin < 8)
{
if (pin < 8) {
return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEL >> (pin * 4)) & 0xF);
}
else
{
} else {
return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEH >> ((pin - 8) * 4)) & 0xF);
}
}
#if defined( _GPIO_EM4WUEN_MASK )
#if defined(_GPIO_EM4WUEN_MASK)
/**************************************************************************//**
* @brief
* Enable GPIO pin wake-up from EM4. When the function exits,
@ -362,11 +340,11 @@ void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask)
{
EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0);
#if defined( _GPIO_EM4WUPOL_MASK )
#if defined(_GPIO_EM4WUPOL_MASK)
EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0);
GPIO->EM4WUPOL &= ~pinmask; /* Set wakeup polarity */
GPIO->EM4WUPOL |= pinmask & polaritymask;
#elif defined( _GPIO_EXTILEVEL_MASK )
#elif defined(_GPIO_EXTILEVEL_MASK)
EFM_ASSERT((polaritymask & ~_GPIO_EXTILEVEL_MASK) == 0);
GPIO->EXTILEVEL &= ~pinmask;
GPIO->EXTILEVEL |= pinmask & polaritymask;
@ -375,9 +353,9 @@ void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask)
GPIO_EM4SetPinRetention(true); /* Enable pin retention */
#if defined( _GPIO_CMD_EM4WUCLR_MASK )
#if defined(_GPIO_CMD_EM4WUCLR_MASK)
GPIO->CMD = GPIO_CMD_EM4WUCLR; /* Clear wake-up logic */
#elif defined( _GPIO_IFC_EM4WU_MASK )
#elif defined(_GPIO_IFC_EM4WU_MASK)
GPIO_IntClear(pinmask);
#endif
}

569
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_i2c.c
* @brief Inter-integrated Circuit (I2C) Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -66,7 +66,7 @@
#elif (I2C_COUNT == 2)
#define I2C_REF_VALID(ref) ((ref == I2C0) || (ref == I2C1))
#elif (I2C_COUNT == 3)
#define I2C_REF_VALID(ref) ((ref == I2C0) || (ref == I2C1)|| (ref == I2C2))
#define I2C_REF_VALID(ref) ((ref == I2C0) || (ref == I2C1) || (ref == I2C2))
#endif
/** Error flags indicating I2C transfer has failed somehow. */
@ -77,9 +77,9 @@
#define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST)
/* Max I2C transmission rate constant */
#if defined( _SILICON_LABS_32B_SERIES_0 )
#if defined(_SILICON_LABS_32B_SERIES_0)
#define I2C_CR_MAX 4
#elif defined( _SILICON_LABS_32B_SERIES_1 )
#elif defined(_SILICON_LABS_32B_SERIES_1)
#define I2C_CR_MAX 8
#else
#warning "Max I2C transmission rate constant is not defined"
@ -94,8 +94,7 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** Master mode transfer states. */
typedef enum
{
typedef enum {
i2cStateStartAddrSend, /**< Send start + (first part of) address. */
i2cStateAddrWFAckNack, /**< Wait for ACK/NACK on (first part of) address. */
i2cStateAddrWF2ndAckNack, /**< Wait for ACK/NACK on second part of 10 bit address. */
@ -117,8 +116,7 @@ typedef enum
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** Structure used to store state information on an ongoing master mode transfer. */
typedef struct
{
typedef struct {
/** Current state. */
I2C_TransferState_TypeDef state;
@ -186,7 +184,6 @@ uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c)
return (freqHfper / ((n * (i2c->CLKDIV + 1)) + I2C_CR_MAX));
}
/***************************************************************************//**
* @brief
* Set I2C bus frequency.
@ -234,8 +231,7 @@ void I2C_BusFreqSet(I2C_TypeDef *i2c,
/* Avoid divide by 0 */
EFM_ASSERT(freqScl);
if (!freqScl)
{
if (!freqScl) {
return;
}
@ -243,45 +239,39 @@ void I2C_BusFreqSet(I2C_TypeDef *i2c,
i2c->CTRL &= ~_I2C_CTRL_CLHR_MASK;
BUS_RegMaskedWrite(&i2c->CTRL,
_I2C_CTRL_CLHR_MASK,
i2cMode <<_I2C_CTRL_CLHR_SHIFT);
i2cMode << _I2C_CTRL_CLHR_SHIFT);
if (!freqRef)
{
if (!freqRef) {
freqRef = CMU_ClockFreqGet(cmuClock_HFPER);
}
/* Check minumum HF peripheral clock */
/* Check minumum HF peripheral clock */
minFreq = UINT_MAX;
if (i2c->CTRL & I2C_CTRL_SLAVE)
{
switch(i2cMode)
{
if (i2c->CTRL & I2C_CTRL_SLAVE) {
switch (i2cMode) {
case i2cClockHLRStandard:
#if defined( _SILICON_LABS_32B_SERIES_0 )
#if defined(_SILICON_LABS_32B_SERIES_0)
minFreq = 4200000; break;
#elif defined( _SILICON_LABS_32B_SERIES_1 )
#elif defined(_SILICON_LABS_32B_SERIES_1)
minFreq = 2000000; break;
#endif
case i2cClockHLRAsymetric:
#if defined( _SILICON_LABS_32B_SERIES_0 )
#if defined(_SILICON_LABS_32B_SERIES_0)
minFreq = 11000000; break;
#elif defined( _SILICON_LABS_32B_SERIES_1 )
#elif defined(_SILICON_LABS_32B_SERIES_1)
minFreq = 5000000; break;
#endif
case i2cClockHLRFast:
#if defined( _SILICON_LABS_32B_SERIES_0 )
#if defined(_SILICON_LABS_32B_SERIES_0)
minFreq = 24400000; break;
#elif defined( _SILICON_LABS_32B_SERIES_1 )
#elif defined(_SILICON_LABS_32B_SERIES_1)
minFreq = 14000000; break;
#endif
}
}
else
{
} else {
/* For master mode, platform 1 and 2 share the same
min frequencies */
switch(i2cMode)
{
switch (i2cMode) {
case i2cClockHLRStandard:
minFreq = 2000000; break;
case i2cClockHLRAsymetric:
@ -311,14 +301,12 @@ void I2C_BusFreqSet(I2C_TypeDef *i2c,
/* Clock divisor must be at least 1 in slave mode according to reference */
/* manual (in which case there is normally no need to set bus frequency). */
if ((i2c->CTRL & I2C_CTRL_SLAVE) && !div)
{
if ((i2c->CTRL & I2C_CTRL_SLAVE) && !div) {
div = 1;
}
i2c->CLKDIV = (uint32_t)div;
}
/***************************************************************************//**
* @brief
* Enable/disable I2C.
@ -339,7 +327,6 @@ void I2C_Enable(I2C_TypeDef *i2c, bool enable)
BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, enable);
}
/***************************************************************************//**
* @brief
* Initialize I2C.
@ -365,7 +352,6 @@ void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init)
BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, init->enable);
}
/***************************************************************************//**
* @brief
* Reset I2C to same state as after a HW reset.
@ -388,7 +374,6 @@ void I2C_Reset(I2C_TypeDef *i2c)
/* Do not reset route register, setting should be done independently */
}
/***************************************************************************//**
* @brief
* Continue an initiated I2C transfer (single master mode only).
@ -435,38 +420,35 @@ I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c)
EFM_ASSERT(I2C_REF_VALID(i2c));
/* Support up to 2 I2C buses */
if (i2c == I2C0)
{
if (i2c == I2C0) {
transfer = i2cTransfer;
}
#if (I2C_COUNT > 1)
else if (i2c == I2C1)
{
else if (i2c == I2C1) {
transfer = i2cTransfer + 1;
}
#endif
else
{
#if (I2C_COUNT > 2)
else if (i2c == I2C2) {
transfer = i2cTransfer + 2;
}
#endif
else {
return i2cTransferUsageFault;
}
seq = transfer->seq;
for (;; )
{
for (;; ) {
pending = i2c->IF;
/* If some sort of fault, abort transfer. */
if (pending & I2C_IF_ERRORS)
{
if (pending & I2C_IF_ARBLOST)
{
if (pending & I2C_IF_ERRORS) {
if (pending & I2C_IF_ARBLOST) {
/* If arbitration fault, it indicates either a slave device */
/* not responding as expected, or other master which is not */
/* supported by this SW. */
transfer->result = i2cTransferArbLost;
}
else if (pending & I2C_IF_BUSERR)
{
} else if (pending & I2C_IF_BUSERR) {
/* A bus error indicates a misplaced start or stop, which should */
/* not occur in master mode controlled by this SW. */
transfer->result = i2cTransferBusErr;
@ -479,306 +461,258 @@ I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c)
goto done;
}
switch (transfer->state)
{
/***************************************************/
/* Send first start+address (first byte if 10 bit) */
/***************************************************/
case i2cStateStartAddrSend:
if (seq->flags & I2C_FLAG_10BIT_ADDR)
{
tmp = (((uint32_t)(seq->addr) >> 8) & 0x06) | 0xf0;
switch (transfer->state) {
/***************************************************/
/* Send first start+address (first byte if 10 bit) */
/***************************************************/
case i2cStateStartAddrSend:
if (seq->flags & I2C_FLAG_10BIT_ADDR) {
tmp = (((uint32_t)(seq->addr) >> 8) & 0x06) | 0xf0;
/* In 10 bit address mode, the address following the first */
/* start always indicate write. */
}
else
{
tmp = (uint32_t)(seq->addr) & 0xfe;
/* In 10 bit address mode, the address following the first */
/* start always indicate write. */
} else {
tmp = (uint32_t)(seq->addr) & 0xfe;
if (seq->flags & I2C_FLAG_READ)
{
if (seq->flags & I2C_FLAG_READ) {
/* Indicate read request */
tmp |= 1;
}
}
transfer->state = i2cStateAddrWFAckNack;
i2c->TXDATA = tmp;/* Data not transmitted until START sent */
i2c->CMD = I2C_CMD_START;
goto done;
/*******************************************************/
/* Wait for ACK/NACK on address (first byte if 10 bit) */
/*******************************************************/
case i2cStateAddrWFAckNack:
if (pending & I2C_IF_NACK) {
i2c->IFC = I2C_IFC_NACK;
transfer->result = i2cTransferNack;
transfer->state = i2cStateWFStopSent;
i2c->CMD = I2C_CMD_STOP;
} else if (pending & I2C_IF_ACK) {
i2c->IFC = I2C_IFC_ACK;
/* If 10 bit address, send 2nd byte of address. */
if (seq->flags & I2C_FLAG_10BIT_ADDR) {
transfer->state = i2cStateAddrWF2ndAckNack;
i2c->TXDATA = (uint32_t)(seq->addr) & 0xff;
} else {
/* Determine whether receiving or sending data */
if (seq->flags & I2C_FLAG_READ) {
transfer->state = i2cStateWFData;
if (seq->buf[transfer->bufIndx].len == 1) {
i2c->CMD = I2C_CMD_NACK;
}
} else {
transfer->state = i2cStateDataSend;
continue;
}
}
}
goto done;
/******************************************************/
/* Wait for ACK/NACK on second byte of 10 bit address */
/******************************************************/
case i2cStateAddrWF2ndAckNack:
if (pending & I2C_IF_NACK) {
i2c->IFC = I2C_IFC_NACK;
transfer->result = i2cTransferNack;
transfer->state = i2cStateWFStopSent;
i2c->CMD = I2C_CMD_STOP;
} else if (pending & I2C_IF_ACK) {
i2c->IFC = I2C_IFC_ACK;
/* If using plain read sequence with 10 bit address, switch to send */
/* repeated start. */
if (seq->flags & I2C_FLAG_READ) {
transfer->state = i2cStateRStartAddrSend;
}
/* Otherwise expected to write 0 or more bytes */
else {
transfer->state = i2cStateDataSend;
}
continue;
}
goto done;
/*******************************/
/* Send repeated start+address */
/*******************************/
case i2cStateRStartAddrSend:
if (seq->flags & I2C_FLAG_10BIT_ADDR) {
tmp = ((seq->addr >> 8) & 0x06) | 0xf0;
} else {
tmp = seq->addr & 0xfe;
}
/* If this is a write+read combined sequence, then read is about to start */
if (seq->flags & I2C_FLAG_WRITE_READ) {
/* Indicate read request */
tmp |= 1;
}
}
transfer->state = i2cStateAddrWFAckNack;
i2c->TXDATA = tmp; /* Data not transmitted until START sent */
i2c->CMD = I2C_CMD_START;
goto done;
transfer->state = i2cStateRAddrWFAckNack;
/* We have to write START cmd first since repeated start, otherwise */
/* data would be sent first. */
i2c->CMD = I2C_CMD_START;
i2c->TXDATA = tmp;
goto done;
/*******************************************************/
/* Wait for ACK/NACK on address (first byte if 10 bit) */
/*******************************************************/
case i2cStateAddrWFAckNack:
if (pending & I2C_IF_NACK)
{
i2c->IFC = I2C_IFC_NACK;
transfer->result = i2cTransferNack;
transfer->state = i2cStateWFStopSent;
i2c->CMD = I2C_CMD_STOP;
}
else if (pending & I2C_IF_ACK)
{
i2c->IFC = I2C_IFC_ACK;
/**********************************************************************/
/* Wait for ACK/NACK on repeated start+address (first byte if 10 bit) */
/**********************************************************************/
case i2cStateRAddrWFAckNack:
if (pending & I2C_IF_NACK) {
i2c->IFC = I2C_IFC_NACK;
transfer->result = i2cTransferNack;
transfer->state = i2cStateWFStopSent;
i2c->CMD = I2C_CMD_STOP;
} else if (pending & I2C_IF_ACK) {
i2c->IFC = I2C_IFC_ACK;
/* If 10 bit address, send 2nd byte of address. */
if (seq->flags & I2C_FLAG_10BIT_ADDR)
{
transfer->state = i2cStateAddrWF2ndAckNack;
i2c->TXDATA = (uint32_t)(seq->addr) & 0xff;
}
else
{
/* Determine whether receiving or sending data */
if (seq->flags & I2C_FLAG_READ)
{
if (seq->flags & I2C_FLAG_WRITE_READ) {
transfer->state = i2cStateWFData;
if(seq->buf[transfer->bufIndx].len==1)
{
i2c->CMD = I2C_CMD_NACK;
}
}
else
{
} else {
transfer->state = i2cStateDataSend;
continue;
}
}
}
goto done;
goto done;
/******************************************************/
/* Wait for ACK/NACK on second byte of 10 bit address */
/******************************************************/
case i2cStateAddrWF2ndAckNack:
if (pending & I2C_IF_NACK)
{
i2c->IFC = I2C_IFC_NACK;
transfer->result = i2cTransferNack;
transfer->state = i2cStateWFStopSent;
i2c->CMD = I2C_CMD_STOP;
}
else if (pending & I2C_IF_ACK)
{
i2c->IFC = I2C_IFC_ACK;
/*****************************/
/* Send a data byte to slave */
/*****************************/
case i2cStateDataSend:
/* Reached end of data buffer? */
if (transfer->offset >= seq->buf[transfer->bufIndx].len) {
/* Move to next message part */
transfer->offset = 0;
transfer->bufIndx++;
/* If using plain read sequence with 10 bit address, switch to send */
/* repeated start. */
if (seq->flags & I2C_FLAG_READ)
{
transfer->state = i2cStateRStartAddrSend;
}
/* Otherwise expected to write 0 or more bytes */
else
{
transfer->state = i2cStateDataSend;
}
continue;
}
goto done;
/* Send repeated start when switching to read mode on 2nd buffer */
if (seq->flags & I2C_FLAG_WRITE_READ) {
transfer->state = i2cStateRStartAddrSend;
continue;
}
/*******************************/
/* Send repeated start+address */
/*******************************/
case i2cStateRStartAddrSend:
if (seq->flags & I2C_FLAG_10BIT_ADDR)
{
tmp = ((seq->addr >> 8) & 0x06) | 0xf0;
}
else
{
tmp = seq->addr & 0xfe;
}
/* Only writing from one buffer, or finished both buffers */
if ((seq->flags & I2C_FLAG_WRITE) || (transfer->bufIndx > 1)) {
transfer->state = i2cStateWFStopSent;
i2c->CMD = I2C_CMD_STOP;
goto done;
}
/* If this is a write+read combined sequence, then read is about to start */
if (seq->flags & I2C_FLAG_WRITE_READ)
{
/* Indicate read request */
tmp |= 1;
}
transfer->state = i2cStateRAddrWFAckNack;
/* We have to write START cmd first since repeated start, otherwise */
/* data would be sent first. */
i2c->CMD = I2C_CMD_START;
i2c->TXDATA = tmp;
goto done;
/**********************************************************************/
/* Wait for ACK/NACK on repeated start+address (first byte if 10 bit) */
/**********************************************************************/
case i2cStateRAddrWFAckNack:
if (pending & I2C_IF_NACK)
{
i2c->IFC = I2C_IFC_NACK;
transfer->result = i2cTransferNack;
transfer->state = i2cStateWFStopSent;
i2c->CMD = I2C_CMD_STOP;
}
else if (pending & I2C_IF_ACK)
{
i2c->IFC = I2C_IFC_ACK;
/* Determine whether receiving or sending data */
if (seq->flags & I2C_FLAG_WRITE_READ)
{
transfer->state = i2cStateWFData;
}
else
{
transfer->state = i2cStateDataSend;
continue;
}
}
goto done;
/*****************************/
/* Send a data byte to slave */
/*****************************/
case i2cStateDataSend:
/* Reached end of data buffer? */
if (transfer->offset >= seq->buf[transfer->bufIndx].len)
{
/* Move to next message part */
transfer->offset = 0;
transfer->bufIndx++;
/* Send repeated start when switching to read mode on 2nd buffer */
if (seq->flags & I2C_FLAG_WRITE_READ)
{
transfer->state = i2cStateRStartAddrSend;
/* Reprocess in case next buffer is empty */
continue;
}
/* Only writing from one buffer, or finished both buffers */
if ((seq->flags & I2C_FLAG_WRITE) || (transfer->bufIndx > 1))
{
transfer->state = i2cStateWFStopSent;
i2c->CMD = I2C_CMD_STOP;
goto done;
/* Send byte */
i2c->TXDATA = (uint32_t)(seq->buf[transfer->bufIndx].data[transfer->offset++]);
transfer->state = i2cStateDataWFAckNack;
goto done;
/*********************************************************/
/* Wait for ACK/NACK from slave after sending data to it */
/*********************************************************/
case i2cStateDataWFAckNack:
if (pending & I2C_IF_NACK) {
i2c->IFC = I2C_IFC_NACK;
transfer->result = i2cTransferNack;
transfer->state = i2cStateWFStopSent;
i2c->CMD = I2C_CMD_STOP;
} else if (pending & I2C_IF_ACK) {
i2c->IFC = I2C_IFC_ACK;
transfer->state = i2cStateDataSend;
continue;
}
goto done;
/* Reprocess in case next buffer is empty */
continue;
}
/****************************/
/* Wait for data from slave */
/****************************/
case i2cStateWFData:
if (pending & I2C_IF_RXDATAV) {
uint8_t data;
unsigned int rxLen = seq->buf[transfer->bufIndx].len;
/* Send byte */
i2c->TXDATA = (uint32_t)(seq->buf[transfer->bufIndx].data[transfer->offset++]);
transfer->state = i2cStateDataWFAckNack;
goto done;
/* Must read out data in order to not block further progress */
data = (uint8_t)(i2c->RXDATA);
/*********************************************************/
/* Wait for ACK/NACK from slave after sending data to it */
/*********************************************************/
case i2cStateDataWFAckNack:
if (pending & I2C_IF_NACK)
{
i2c->IFC = I2C_IFC_NACK;
transfer->result = i2cTransferNack;
transfer->state = i2cStateWFStopSent;
i2c->CMD = I2C_CMD_STOP;
}
else if (pending & I2C_IF_ACK)
{
i2c->IFC = I2C_IFC_ACK;
transfer->state = i2cStateDataSend;
continue;
}
goto done;
/****************************/
/* Wait for data from slave */
/****************************/
case i2cStateWFData:
if (pending & I2C_IF_RXDATAV)
{
uint8_t data;
unsigned int rxLen = seq->buf[transfer->bufIndx].len;
/* Must read out data in order to not block further progress */
data = (uint8_t)(i2c->RXDATA);
/* Make sure not storing beyond end of buffer just in case */
if (transfer->offset < rxLen)
{
seq->buf[transfer->bufIndx].data[transfer->offset++] = data;
}
/* If we have read all requested data, then the sequence should end */
if (transfer->offset >= rxLen)
{
/* If there is only one byte to receive we need to transmit the
NACK now, before the stop. */
if (1 == rxLen)
{
i2c->CMD = I2C_CMD_NACK;
/* Make sure not storing beyond end of buffer just in case */
if (transfer->offset < rxLen) {
seq->buf[transfer->bufIndx].data[transfer->offset++] = data;
}
transfer->state = i2cStateWFStopSent;
i2c->CMD = I2C_CMD_STOP;
}
else
{
/* Send ACK and wait for next byte */
i2c->CMD = I2C_CMD_ACK;
/* If we have read all requested data, then the sequence should end */
if (transfer->offset >= rxLen) {
/* If there is only one byte to receive we need to transmit the
NACK now, before the stop. */
if (1 == rxLen) {
i2c->CMD = I2C_CMD_NACK;
}
if ( (1<rxLen) && (transfer->offset == (rxLen-1)) )
{
/* If there is more than one byte to receive and this is the next
to last byte we need to transmit the NACK now, before receiving
the last byte. */
i2c->CMD = I2C_CMD_NACK;
transfer->state = i2cStateWFStopSent;
i2c->CMD = I2C_CMD_STOP;
} else {
/* Send ACK and wait for next byte */
i2c->CMD = I2C_CMD_ACK;
if ( (1 < rxLen) && (transfer->offset == (rxLen - 1)) ) {
/* If there is more than one byte to receive and this is the next
to last byte we need to transmit the NACK now, before receiving
the last byte. */
i2c->CMD = I2C_CMD_NACK;
}
}
}
}
goto done;
goto done;
/***********************************/
/* Wait for STOP to have been sent */
/***********************************/
case i2cStateWFStopSent:
if (pending & I2C_IF_MSTOP)
{
i2c->IFC = I2C_IFC_MSTOP;
transfer->state = i2cStateDone;
}
goto done;
/***********************************/
/* Wait for STOP to have been sent */
/***********************************/
case i2cStateWFStopSent:
if (pending & I2C_IF_MSTOP) {
i2c->IFC = I2C_IFC_MSTOP;
transfer->state = i2cStateDone;
}
goto done;
/******************************/
/* Unexpected state, SW fault */
/******************************/
default:
transfer->result = i2cTransferSwFault;
transfer->state = i2cStateDone;
goto done;
/******************************/
/* Unexpected state, SW fault */
/******************************/
default:
transfer->result = i2cTransferSwFault;
transfer->state = i2cStateDone;
goto done;
}
}
done:
done:
if (transfer->state == i2cStateDone)
{
if (transfer->state == i2cStateDone) {
/* Disable interrupt sources when done */
i2c->IEN = 0;
/* Update result unless some fault already occurred */
if (transfer->result == i2cTransferInProgress)
{
if (transfer->result == i2cTransferInProgress) {
transfer->result = i2cTransferDone;
}
}
/* Until transfer is done keep returning i2cTransferInProgress */
else
{
else {
return i2cTransferInProgress;
}
return transfer->result;
}
/***************************************************************************//**
* @brief
* Prepare and start an I2C transfer (single master mode only).
@ -813,25 +747,26 @@ I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c,
EFM_ASSERT(seq);
/* Support up to 2 I2C buses */
if (i2c == I2C0)
{
if (i2c == I2C0) {
transfer = i2cTransfer;
}
#if (I2C_COUNT > 1)
else if (i2c == I2C1)
{
else if (i2c == I2C1) {
transfer = i2cTransfer + 1;
}
#endif
else
{
#if (I2C_COUNT > 2)
else if (i2c == I2C2) {
transfer = i2cTransfer + 2;
}
#endif
else {
return i2cTransferUsageFault;
}
/* Check if in busy state. Since this SW assumes single master, we can */
/* just issue an abort. The BUSY state is normal after a reset. */
if (i2c->STATE & I2C_STATE_BUSY)
{
if (i2c->STATE & I2C_STATE_BUSY) {
i2c->CMD = I2C_CMD_ABORT;
}
@ -839,10 +774,9 @@ I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c,
/* possible according to I2C spec, since slave will always start */
/* sending first byte ACK on address. The read operation can */
/* only be stopped by NACKing a received byte, ie minimum 1 byte. */
if (((seq->flags & I2C_FLAG_READ) && !(seq->buf[0].len)) ||
((seq->flags & I2C_FLAG_WRITE_READ) && !(seq->buf[1].len))
)
{
if (((seq->flags & I2C_FLAG_READ) && !(seq->buf[0].len))
|| ((seq->flags & I2C_FLAG_WRITE_READ) && !(seq->buf[1].len))
) {
return i2cTransferUsageFault;
}
@ -855,8 +789,7 @@ I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c,
/* Ensure buffers are empty */
i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX;
if (i2c->IF & I2C_IF_RXDATAV)
{
if (i2c->IF & I2C_IF_RXDATAV) {
(void)i2c->RXDATA;
}
@ -866,8 +799,8 @@ I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c,
/* Enable those interrupts we are interested in throughout transfer. */
/* Notice that the I2C interrupt must also be enabled in the NVIC, but */
/* that is left for an additional driver wrapper. */
i2c->IEN |= I2C_IF_NACK | I2C_IF_ACK | I2C_IF_MSTOP |
I2C_IF_RXDATAV | I2C_IF_ERRORS;
i2c->IEN |= I2C_IF_NACK | I2C_IF_ACK | I2C_IF_MSTOP
| I2C_IF_RXDATAV | I2C_IF_ERRORS;
/* Start transfer */
return I2C_Transfer(i2c);

53
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_idac.c
* @brief Current Digital to Analog Converter (IDAC) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -48,8 +48,8 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/* Fix for errata IDAC_E101 - IDAC output current degradation */
#if defined(_SILICON_LABS_32B_SERIES_0) \
&& (defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY))
#if defined(_SILICON_LABS_32B_SERIES_0) \
&& (defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY))
#define ERRATA_FIX_IDAC_E101_EN
#endif
/** @endcond */
@ -58,7 +58,6 @@
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
/***************************************************************************//**
* @brief
* Initialize IDAC.
@ -86,27 +85,23 @@ void IDAC_Init(IDAC_TypeDef *idac, const IDAC_Init_TypeDef *init)
tmp |= init->outMode;
if (init->enable)
{
if (init->enable) {
tmp |= IDAC_CTRL_EN;
}
if (init->prsEnable)
{
if (init->prsEnable) {
#if defined(_IDAC_CTRL_OUTENPRS_MASK)
tmp |= IDAC_CTRL_OUTENPRS;
#else
tmp |= IDAC_CTRL_APORTOUTENPRS;
#endif
}
if (init->sinkEnable)
{
if (init->sinkEnable) {
tmp |= IDAC_CTRL_CURSINK;
}
idac->CTRL = tmp;
}
/***************************************************************************//**
* @brief
* Enable/disable IDAC.
@ -123,7 +118,6 @@ void IDAC_Enable(IDAC_TypeDef *idac, bool enable)
BUS_RegBitWrite(&idac->CTRL, _IDAC_CTRL_EN_SHIFT, enable);
}
/***************************************************************************//**
* @brief
* Reset IDAC to same state as after a HW reset.
@ -144,8 +138,8 @@ void IDAC_Reset(IDAC_TypeDef *idac)
idac->CTRL = _IDAC_CTRL_RESETVALUE | IDAC_CTRL_EN;
/* Set lowest current (50 nA) */
idac->CURPROG = IDAC_CURPROG_RANGESEL_RANGE0 |
(0x0 << _IDAC_CURPROG_STEPSEL_SHIFT);
idac->CURPROG = IDAC_CURPROG_RANGESEL_RANGE0
| (0x0 << _IDAC_CURPROG_STEPSEL_SHIFT);
/* Enable duty-cycling for all energy modes */
idac->DUTYCONFIG = IDAC_DUTYCONFIG_DUTYCYCLEEN;
@ -154,12 +148,11 @@ void IDAC_Reset(IDAC_TypeDef *idac)
idac->CURPROG = _IDAC_CURPROG_RESETVALUE;
idac->DUTYCONFIG = _IDAC_DUTYCONFIG_RESETVALUE;
#endif
#if defined ( _IDAC_CAL_MASK )
#if defined (_IDAC_CAL_MASK)
idac->CAL = _IDAC_CAL_RESETVALUE;
#endif
}
/***************************************************************************//**
* @brief
* Enable/disable Minimal Output Transition mode.
@ -176,7 +169,6 @@ void IDAC_MinimalOutputTransitionMode(IDAC_TypeDef *idac, bool enable)
BUS_RegBitWrite(&idac->CTRL, _IDAC_CTRL_MINOUTTRANS_SHIFT, enable);
}
/***************************************************************************//**
* @brief
* Set the current range of the IDAC output.
@ -196,7 +188,7 @@ void IDAC_MinimalOutputTransitionMode(IDAC_TypeDef *idac, bool enable)
void IDAC_RangeSet(IDAC_TypeDef *idac, const IDAC_Range_TypeDef range)
{
uint32_t tmp;
#if defined( _IDAC_CURPROG_TUNING_MASK )
#if defined(_IDAC_CURPROG_TUNING_MASK)
uint32_t diCal0;
uint32_t diCal1;
#endif
@ -205,11 +197,10 @@ void IDAC_RangeSet(IDAC_TypeDef *idac, const IDAC_Range_TypeDef range)
EFM_ASSERT(((uint32_t)range >> _IDAC_CURPROG_RANGESEL_SHIFT)
<= (_IDAC_CURPROG_RANGESEL_MASK >> _IDAC_CURPROG_RANGESEL_SHIFT));
#if defined ( _IDAC_CAL_MASK )
#if defined (_IDAC_CAL_MASK)
/* Load proper calibration data depending on selected range */
switch ((IDAC_Range_TypeDef)range)
{
switch ((IDAC_Range_TypeDef)range) {
case idacCurrentRange0:
idac->CAL = (DEVINFO->IDAC0CAL0 & _DEVINFO_IDAC0CAL0_RANGE0_MASK)
>> _DEVINFO_IDAC0CAL0_RANGE0_SHIFT;
@ -231,7 +222,7 @@ void IDAC_RangeSet(IDAC_TypeDef *idac, const IDAC_Range_TypeDef range)
tmp = idac->CURPROG & ~_IDAC_CURPROG_RANGESEL_MASK;
tmp |= (uint32_t)range;
#elif defined( _IDAC_CURPROG_TUNING_MASK )
#elif defined(_IDAC_CURPROG_TUNING_MASK)
/* Load calibration data depending on selected range and sink/source mode */
/* TUNING (calibration) field in CURPROG register. */
@ -241,10 +232,8 @@ void IDAC_RangeSet(IDAC_TypeDef *idac, const IDAC_Range_TypeDef range)
tmp = idac->CURPROG & ~(_IDAC_CURPROG_TUNING_MASK
| _IDAC_CURPROG_RANGESEL_MASK);
if (idac->CTRL & IDAC_CTRL_CURSINK)
{
switch (range)
{
if (idac->CTRL & IDAC_CTRL_CURSINK) {
switch (range) {
case idacCurrentRange0:
tmp |= ((diCal1 & _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK)
>> _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT)
@ -269,11 +258,8 @@ void IDAC_RangeSet(IDAC_TypeDef *idac, const IDAC_Range_TypeDef range)
<< _IDAC_CURPROG_TUNING_SHIFT;
break;
}
}
else
{
switch (range)
{
} else {
switch (range) {
case idacCurrentRange0:
tmp |= ((diCal0 & _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK)
>> _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT)
@ -309,7 +295,6 @@ void IDAC_RangeSet(IDAC_TypeDef *idac, const IDAC_Range_TypeDef range)
idac->CURPROG = tmp;
}
/***************************************************************************//**
* @brief
* Set the current step of the IDAC output.
@ -333,7 +318,6 @@ void IDAC_StepSet(IDAC_TypeDef *idac, const uint32_t step)
idac->CURPROG = tmp;
}
/***************************************************************************//**
* @brief
* Enable/disable the IDAC OUT pin.
@ -354,7 +338,6 @@ void IDAC_OutEnable(IDAC_TypeDef *idac, bool enable)
#endif
}
/** @} (end addtogroup IDAC) */
/** @} (end addtogroup emlib) */

78
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_int.c
View File

@ -1,78 +0,0 @@
/**************************************************************************//**
* @file em_int.c
* @brief Interrupt enable/disable unit API
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
* obligation to support this Software. Silicon Labs is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Silicon Labs will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#include <stdint.h>
#include "em_int.h"
/***************************************************************************//**
* @addtogroup emlib
* @{
******************************************************************************/
/***************************************************************************//**
* @addtogroup INT
* @brief Safe nesting of interrupt disable/enable API
* @{
* @deprecated
* These functions are deprecated and marked for removal in a later release.
* Please use the @ref CORE module instead. See @ref core_porting for
* information on how to convert existing code bases to use @ref CORE.
*
* @details
* This module contains functions to safely disable and enable interrupts
* at CPU level. INT_Disable() disables interrupts globally and increments a lock
* level counter (counting semaphore). INT_Enable() decrements the lock level
* counter and enable interrupts if the counter reaches zero.
*
* These functions would normally be used to secure critical regions, and
* to make sure that a critical section that calls into another critical
* section does not unintentionally terminate the callee critical section.
*
* These functions should also be used inside interrupt handlers:
* @verbatim
* void SysTick_Handler(void)
* {
* INT_Disable();
* .
* .
* .
* INT_Enable();
* }
* @endverbatim
******************************************************************************/
/** Interrupt lock level counter. Set to zero initially as we normally enter
* main with interrupts enabled */
uint32_t INT_LockCnt = 0;
/** @} (end addtogroup INT) */
/** @} (end addtogroup emlib) */

214
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_lcd.c
* @brief Liquid Crystal Display (LCD) Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -81,27 +81,48 @@ void LCD_Init(const LCD_Init_TypeDef *lcdInit)
| _LCD_DISPCTRL_MUX_MASK
| _LCD_DISPCTRL_BIAS_MASK
| _LCD_DISPCTRL_WAVE_MASK
#if defined(_LCD_DISPCTRL_VLCDSEL_MASK)
| _LCD_DISPCTRL_VLCDSEL_MASK
| _LCD_DISPCTRL_CONCONF_MASK);
#endif
#if defined(_LCD_DISPCTRL_CONCONF_MASK)
| _LCD_DISPCTRL_CONCONF_MASK
#endif
#if defined(_LCD_DISPCTRL_MODE_MASK)
| _LCD_DISPCTRL_MODE_MASK
#endif
#if defined(_LCD_DISPCTRL_CHGRDST_MASK)
| _LCD_DISPCTRL_CHGRDST_MASK
#endif
);
/* Configure controller according to initialization structure */
dispCtrl |= lcdInit->mux; /* also configures MUXE */
dispCtrl |= lcdInit->bias;
dispCtrl |= lcdInit->wave;
#if defined(_SILICON_LABS_32B_SERIES_0)
dispCtrl |= lcdInit->vlcd;
dispCtrl |= lcdInit->contrast;
#endif
#if defined(_SILICON_LABS_32B_SERIES_1)
dispCtrl |= lcdInit->mode;
dispCtrl |= (lcdInit->chgrDst << _LCD_DISPCTRL_CHGRDST_SHIFT);
#endif
/* Update display controller */
LCD->DISPCTRL = dispCtrl;
#if defined(_SILICON_LABS_32B_SERIES_1)
LCD->FRAMERATE = lcdInit->frameRateDivider;
LCD_ContrastSet(lcdInit->contrastLevel);
#endif
/* Enable controller if wanted */
if (lcdInit->enable)
{
if (lcdInit->enable) {
LCD_Enable(true);
}
}
#if defined(_SILICON_LABS_32B_SERIES_0)
/***************************************************************************//**
* @brief
* Select source for VLCD
@ -115,8 +136,7 @@ void LCD_VLCDSelect(LCD_VLCDSel_TypeDef vlcd)
/* Select VEXT or VDD */
dispctrl &= ~_LCD_DISPCTRL_VLCDSEL_MASK;
switch (vlcd)
{
switch (vlcd) {
case lcdVLCDSelVExtBoost:
dispctrl |= LCD_DISPCTRL_VLCDSEL_VEXTBOOST;
break;
@ -129,7 +149,7 @@ void LCD_VLCDSelect(LCD_VLCDSel_TypeDef vlcd)
LCD->DISPCTRL = dispctrl;
}
#endif
/***************************************************************************//**
* @brief
@ -143,7 +163,6 @@ void LCD_UpdateCtrl(LCD_UpdateCtrl_TypeDef ud)
LCD->CTRL = (LCD->CTRL & ~_LCD_CTRL_UDCTRL_MASK) | ud;
}
/***************************************************************************//**
* @brief
* Initialize LCD Frame Counter
@ -172,7 +191,6 @@ void LCD_FrameCountInit(const LCD_FrameCountInit_TypeDef *fcInit)
LCD_FrameCountEnable(fcInit->enable);
}
/***************************************************************************//**
* @brief
* Configures LCD controller Animation feature
@ -202,12 +220,9 @@ void LCD_AnimInit(const LCD_AnimInit_TypeDef *animInit)
#if defined(LCD_BACTRL_ALOC)
bactrl &= ~(_LCD_BACTRL_ALOC_MASK);
if(animInit->startSeg == 0)
{
if (animInit->startSeg == 0) {
bactrl |= LCD_BACTRL_ALOC_SEG0TO7;
}
else if(animInit->startSeg == 8)
{
} else if (animInit->startSeg == 8) {
bactrl |= LCD_BACTRL_ALOC_SEG8TO15;
}
#endif
@ -219,7 +234,6 @@ void LCD_AnimInit(const LCD_AnimInit_TypeDef *animInit)
LCD_AnimEnable(animInit->enable);
}
/***************************************************************************//**
* @brief
* Enables update of this range of LCD segment lines
@ -231,18 +245,16 @@ void LCD_AnimInit(const LCD_AnimInit_TypeDef *animInit)
* @param[in] enable
* Bool true to enable segment updates, false to disable updates
******************************************************************************/
#if defined(_SILICON_LABS_32B_SERIES_0)
void LCD_SegmentRangeEnable(LCD_SegmentRange_TypeDef segmentRange, bool enable)
{
if (enable)
{
if (enable) {
LCD->SEGEN |= segmentRange;
}
else
{
} else {
LCD->SEGEN &= ~((uint32_t)segmentRange);
}
}
#endif
/***************************************************************************//**
* @brief
@ -280,55 +292,46 @@ void LCD_SegmentSet(int com, int bit, bool enable)
#endif
/* Use bitband access for atomic bit set/clear of segment */
switch (com)
{
switch (com) {
case 0:
if (bit < 32)
{
if (bit < 32) {
BUS_RegBitWrite(&(LCD->SEGD0L), bit, enable);
}
#if defined(_LCD_SEGD0H_MASK)
else
{
else {
bit -= 32;
BUS_RegBitWrite(&(LCD->SEGD0H), bit, enable);
}
#endif
break;
case 1:
if (bit < 32)
{
if (bit < 32) {
BUS_RegBitWrite(&(LCD->SEGD1L), bit, enable);
}
#if defined(_LCD_SEGD1H_MASK)
else
{
else {
bit -= 32;
BUS_RegBitWrite(&(LCD->SEGD1H), bit, enable);
}
#endif
break;
case 2:
if (bit < 32)
{
if (bit < 32) {
BUS_RegBitWrite(&(LCD->SEGD2L), bit, enable);
}
#if defined(_LCD_SEGD2H_MASK)
else
{
else {
bit -= 32;
BUS_RegBitWrite(&(LCD->SEGD2H), bit, enable);
}
#endif
break;
case 3:
if (bit < 32)
{
if (bit < 32) {
BUS_RegBitWrite(&(LCD->SEGD3L), bit, enable);
}
#if defined(_LCD_SEGD3H_MASK)
else
{
else {
bit -= 32;
BUS_RegBitWrite(&(LCD->SEGD3H), bit, enable);
}
@ -336,13 +339,11 @@ void LCD_SegmentSet(int com, int bit, bool enable)
break;
#if defined(_LCD_SEGD4L_MASK)
case 4:
if (bit < 32)
{
if (bit < 32) {
BUS_RegBitWrite(&(LCD->SEGD4L), bit, enable);
}
#if defined(_LCD_SEGD4H_MASK)
else
{
else {
bit -= 32;
BUS_RegBitWrite(&(LCD->SEGD4H), bit, enable);
}
@ -351,13 +352,11 @@ void LCD_SegmentSet(int com, int bit, bool enable)
#endif
#if defined(_LCD_SEGD5L_MASK)
case 5:
if (bit < 32)
{
if (bit < 32) {
BUS_RegBitWrite(&(LCD->SEGD5L), bit, enable);
}
#if defined(_LCD_SEGD5H_MASK)
else
{
else {
bit -= 32;
BUS_RegBitWrite(&(LCD->SEGD5H), bit, enable);
}
@ -366,13 +365,11 @@ void LCD_SegmentSet(int com, int bit, bool enable)
#endif
case 6:
#if defined(_LCD_SEGD6L_MASK)
if (bit < 32)
{
if (bit < 32) {
BUS_RegBitWrite(&(LCD->SEGD6L), bit, enable);
}
#if defined(_LCD_SEGD6H_MASK)
else
{
else {
bit -= 32;
BUS_RegBitWrite(&(LCD->SEGD6H), bit, enable);
}
@ -381,13 +378,11 @@ void LCD_SegmentSet(int com, int bit, bool enable)
#endif
#if defined(_LCD_SEGD7L_MASK)
case 7:
if (bit < 32)
{
if (bit < 32) {
BUS_RegBitWrite(&(LCD->SEGD7L), bit, enable);
}
#if defined(_LCD_SEGD7H_MASK)
else
{
else {
bit -= 32;
BUS_RegBitWrite(&(LCD->SEGD7H), bit, enable);
}
@ -401,7 +396,6 @@ void LCD_SegmentSet(int com, int bit, bool enable)
}
}
/***************************************************************************//**
* @brief
* Updates the 0-31 lowest segments on a given COM-line in one operation,
@ -428,8 +422,7 @@ void LCD_SegmentSetLow(int com, uint32_t mask, uint32_t bits)
EFM_ASSERT(com < 4);
#endif
switch (com)
{
switch (com) {
case 0:
segData = LCD->SEGD0L;
segData &= ~(mask);
@ -492,7 +485,6 @@ void LCD_SegmentSetLow(int com, uint32_t mask, uint32_t bits)
}
}
#if defined(_LCD_SEGD0H_MASK)
/***************************************************************************//**
* @brief
@ -518,8 +510,7 @@ void LCD_SegmentSetHigh(int com, uint32_t mask, uint32_t bits)
#endif
/* Maximum number of com lines */
switch (com)
{
switch (com) {
case 0:
segData = LCD->SEGD0H;
segData &= ~(mask);
@ -582,6 +573,7 @@ void LCD_SegmentSetHigh(int com, uint32_t mask, uint32_t bits)
}
#endif
#if defined(_SILICON_LABS_32B_SERIES_0)
/***************************************************************************//**
* @brief
* Configure contrast level on LCD panel
@ -596,8 +588,38 @@ void LCD_ContrastSet(int level)
LCD->DISPCTRL = (LCD->DISPCTRL & ~_LCD_DISPCTRL_CONLEV_MASK)
| (level << _LCD_DISPCTRL_CONLEV_SHIFT);
}
#endif
#if defined(_SILICON_LABS_32B_SERIES_1)
/***************************************************************************//**
* @brief
* Configure contrast level on LCD panel
*
* @param[in] level
* Contrast level in the range 0-63
******************************************************************************/
void LCD_ContrastSet(int level)
{
EFM_ASSERT(level < 64);
LCD->DISPCTRL = (LCD->DISPCTRL & ~_LCD_DISPCTRL_CONTRAST_MASK)
| (level << _LCD_DISPCTRL_CONTRAST_SHIFT);
}
#endif
/***************************************************************************//**
* @brief
* Configure bias level on LCD panel
*
* @param[in] bias
* Bias level
******************************************************************************/
void LCD_BiasSet(LCD_Bias_TypeDef bias)
{
LCD->DISPCTRL = (LCD->DISPCTRL & ~_LCD_DISPCTRL_BIAS_MASK) | bias;
}
#if defined(_SILICON_LABS_32B_SERIES_0)
/***************************************************************************//**
* @brief
* Configure voltage booster
@ -612,7 +634,7 @@ void LCD_VBoostSet(LCD_VBoostLevel_TypeDef vboost)
/* Reconfigure Voltage Boost */
LCD->DISPCTRL = (LCD->DISPCTRL & ~_LCD_DISPCTRL_VBLEV_MASK) | vboost;
}
#endif
#if defined(LCD_CTRL_DSC)
/***************************************************************************//**
@ -647,8 +669,7 @@ void LCD_BiasSegmentSet(int segmentLine, int biasLevel)
biasRegister = segmentLine / 8;
bitShift = (segmentLine % 8) * 4;
switch (biasRegister)
{
switch (biasRegister) {
case 0:
segmentRegister = &LCD->SEGD0L;
break;
@ -673,48 +694,35 @@ void LCD_BiasSegmentSet(int segmentLine, int biasLevel)
biasRegister = segmentLine / 10;
bitShift = (segmentLine % 10) * 4;
switch (biasRegister)
{
switch (biasRegister) {
case 0:
if (bitShift < 32)
{
if (bitShift < 32) {
segmentRegister = &LCD->SEGD0L;
}
else
{
} else {
segmentRegister = &LCD->SEGD0H;
bitShift -= 32;
}
break;
case 1:
if (bitShift < 32)
{
if (bitShift < 32) {
segmentRegister = &LCD->SEGD1L;
}
else
{
} else {
segmentRegister = &LCD->SEGD1H;
bitShift -= 32;
}
break;
case 2:
if (bitShift < 32)
{
if (bitShift < 32) {
segmentRegister = &LCD->SEGD2L;
}
else
{
} else {
segmentRegister = &LCD->SEGD1H;
bitShift -= 32;
}
break;
case 3:
if (bitShift < 32)
{
if (bitShift < 32) {
segmentRegister = &LCD->SEGD3L;
}
else
{
} else {
segmentRegister = &LCD->SEGD3H;
bitShift -= 32;
}
@ -731,7 +739,6 @@ void LCD_BiasSegmentSet(int segmentLine, int biasLevel)
}
#endif
#if defined(LCD_CTRL_DSC)
/***************************************************************************//**
* @brief
@ -762,6 +769,35 @@ void LCD_BiasComSet(int comLine, int biasLevel)
}
#endif
#if defined(_SILICON_LABS_32B_SERIES_1)
/***************************************************************************//**
* @brief
* Configure the mode for the LCD panel
*
* @param[in] mode
* Mode
******************************************************************************/
void LCD_ModeSet(LCD_Mode_Typedef mode)
{
LCD->DISPCTRL = (LCD->DISPCTRL & ~_LCD_DISPCTRL_MODE_MASK) | mode;
}
/***************************************************************************//**
* @brief
* Configure the charge redistribution cycles for the LCD panel
*
* @param[in] chgrDst
* Charge redistribution cycles, range 0-4
******************************************************************************/
void LCD_ChargeRedistributionCyclesSet(uint8_t cycles)
{
EFM_ASSERT(cycles <= 4);
LCD->DISPCTRL = (LCD->DISPCTRL & ~_LCD_DISPCTRL_CHGRDST_MASK)
| (cycles << _LCD_DISPCTRL_CHGRDST_SHIFT);
}
#endif
/** @} (end addtogroup LCD) */
/** @} (end addtogroup emlib) */

53
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ldma.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_ldma.c
* @brief Direct memory access (LDMA) module peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -32,7 +32,7 @@
#include "em_ldma.h"
#if defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 )
#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1)
#include <stddef.h>
#include "em_assert.h"
@ -50,7 +50,7 @@
* @{
******************************************************************************/
#if defined( LDMA_IRQ_HANDLER_TEMPLATE )
#if defined(LDMA_IRQ_HANDLER_TEMPLATE)
/***************************************************************************//**
* @brief
* Template for an LDMA IRQ handler.
@ -62,16 +62,13 @@ void LDMA_IRQHandler(void)
uint32_t pending = LDMA_IntGetEnabled();
/* Loop here on an LDMA error to enable debugging. */
while (pending & LDMA_IF_ERROR)
{
while (pending & LDMA_IF_ERROR) {
}
/* Iterate over all LDMA channels. */
for (ch = 0; ch < DMA_CHAN_COUNT; ch++)
{
for (ch = 0; ch < DMA_CHAN_COUNT; ch++) {
uint32_t mask = 0x1 << ch;
if (pending & mask)
{
if (pending & mask) {
/* Clear interrupt flag. */
LDMA->IFC = mask;
@ -204,7 +201,7 @@ void LDMA_StartTransfer(int ch,
EFM_ASSERT(!((transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT)
& ~_LDMA_CH_CFG_ARBSLOTS_MASK));
EFM_ASSERT(!((transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT)
& ~_LDMA_CH_CFG_SRCINCSIGN_MASK ) );
& ~_LDMA_CH_CFG_SRCINCSIGN_MASK) );
EFM_ASSERT(!((transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT)
& ~_LDMA_CH_CFG_DSTINCSIGN_MASK));
EFM_ASSERT(!((transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT)
@ -228,37 +225,31 @@ void LDMA_StartTransfer(int ch,
/* Enable channel interrupt. */
LDMA->IEN |= chMask;
if (transfer->ldmaReqDis)
{
if (transfer->ldmaReqDis) {
LDMA->REQDIS |= chMask;
}
if (transfer->ldmaDbgHalt)
{
if (transfer->ldmaDbgHalt) {
LDMA->DBGHALT |= chMask;
}
tmp = LDMA->CTRL;
if (transfer->ldmaCtrlSyncPrsClrOff)
{
if (transfer->ldmaCtrlSyncPrsClrOff) {
tmp &= ~_LDMA_CTRL_SYNCPRSCLREN_MASK
| (~transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT);
}
if (transfer->ldmaCtrlSyncPrsClrOn)
{
if (transfer->ldmaCtrlSyncPrsClrOn) {
tmp |= transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT;
}
if (transfer->ldmaCtrlSyncPrsSetOff)
{
if (transfer->ldmaCtrlSyncPrsSetOff) {
tmp &= ~_LDMA_CTRL_SYNCPRSSETEN_MASK
| (~transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT);
}
if (transfer->ldmaCtrlSyncPrsSetOn)
{
if (transfer->ldmaCtrlSyncPrsSetOn) {
tmp |= transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT;
}
@ -290,7 +281,7 @@ void LDMA_StopTransfer(int ch)
CORE_ATOMIC_SECTION(
LDMA->IEN &= ~chMask;
BUS_RegMaskedClear(&LDMA->CHEN, chMask);
)
)
}
/***************************************************************************//**
@ -312,11 +303,10 @@ bool LDMA_TransferDone(int ch)
CORE_ATOMIC_SECTION(
if (((LDMA->CHEN & chMask) == 0)
&& ((LDMA->CHDONE & chMask) == chMask))
{
retVal = true;
}
)
&& ((LDMA->CHDONE & chMask) == chMask)) {
retVal = true;
}
)
return retVal;
}
@ -346,15 +336,14 @@ uint32_t LDMA_TransferRemainingCount(int ch)
iflag = LDMA->IF;
done = LDMA->CHDONE;
remaining = LDMA->CH[ch].CTRL;
)
)
iflag &= chMask;
done &= chMask;
remaining = (remaining & _LDMA_CH_CTRL_XFERCNT_MASK)
>> _LDMA_CH_CTRL_XFERCNT_SHIFT;
if (done || ((remaining == 0) && iflag))
{
if (done || ((remaining == 0) && iflag)) {
return 0;
}

141
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_lesense.c
* @brief Low Energy Sensor (LESENSE) Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -79,7 +79,6 @@
************************** LOCAL FUNCTIONS ********************************
******************************************************************************/
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
@ -124,8 +123,7 @@ void LESENSE_Init(const LESENSE_Init_TypeDef * init, bool reqReset)
#endif
/* Reset LESENSE registers if requested. */
if (reqReset)
{
if (reqReset) {
LESENSE_Reset();
}
@ -166,27 +164,32 @@ void LESENSE_Init(const LESENSE_Init_TypeDef * init, bool reqReset)
* Set DAC0 and DAC1 data source, conversion mode, output mode. Set DAC
* prescaler and reference. Set ACMP0 and ACMP1 control mode. Set ACMP and DAC
* duty cycle (warm up) mode. */
LESENSE->PERCTRL =
((uint32_t)init->perCtrl.dacCh0Data << _LESENSE_PERCTRL_DACCH0DATA_SHIFT)
| ((uint32_t)init->perCtrl.dacCh1Data << _LESENSE_PERCTRL_DACCH1DATA_SHIFT)
#if defined(_LESENSE_PERCTRL_DACCH0CONV_MASK)
| ((uint32_t)init->perCtrl.dacCh0ConvMode << _LESENSE_PERCTRL_DACCH0CONV_SHIFT)
| ((uint32_t)init->perCtrl.dacCh0OutMode << _LESENSE_PERCTRL_DACCH0OUT_SHIFT)
| ((uint32_t)init->perCtrl.dacCh1ConvMode << _LESENSE_PERCTRL_DACCH1CONV_SHIFT)
| ((uint32_t)init->perCtrl.dacCh1OutMode << _LESENSE_PERCTRL_DACCH1OUT_SHIFT)
| ((uint32_t)init->perCtrl.dacPresc << _LESENSE_PERCTRL_DACPRESC_SHIFT)
| (uint32_t)init->perCtrl.dacRef
LESENSE->PERCTRL = 0
#if defined(_LESENSE_PERCTRL_DACCH0EN_MASK)
| ((uint32_t)init->perCtrl.dacCh0En << _LESENSE_PERCTRL_DACCH0EN_SHIFT)
| ((uint32_t)init->perCtrl.dacCh1En << _LESENSE_PERCTRL_DACCH1EN_SHIFT)
#endif
| ((uint32_t)init->perCtrl.acmp0Mode << _LESENSE_PERCTRL_ACMP0MODE_SHIFT)
| ((uint32_t)init->perCtrl.acmp1Mode << _LESENSE_PERCTRL_ACMP1MODE_SHIFT)
#if defined(_LESENSE_PERCTRL_ACMP0INV_MASK)
| ((uint32_t)init->coreCtrl.invACMP0 << _LESENSE_PERCTRL_ACMP0INV_SHIFT)
| ((uint32_t)init->coreCtrl.invACMP1 << _LESENSE_PERCTRL_ACMP1INV_SHIFT)
| ((uint32_t)init->perCtrl.dacCh0Data << _LESENSE_PERCTRL_DACCH0DATA_SHIFT)
| ((uint32_t)init->perCtrl.dacCh1Data << _LESENSE_PERCTRL_DACCH1DATA_SHIFT)
#if defined(_LESENSE_PERCTRL_DACCH0CONV_MASK)
| ((uint32_t)init->perCtrl.dacCh0ConvMode << _LESENSE_PERCTRL_DACCH0CONV_SHIFT)
| ((uint32_t)init->perCtrl.dacCh0OutMode << _LESENSE_PERCTRL_DACCH0OUT_SHIFT)
| ((uint32_t)init->perCtrl.dacCh1ConvMode << _LESENSE_PERCTRL_DACCH1CONV_SHIFT)
| ((uint32_t)init->perCtrl.dacCh1OutMode << _LESENSE_PERCTRL_DACCH1OUT_SHIFT)
| ((uint32_t)init->perCtrl.dacPresc << _LESENSE_PERCTRL_DACPRESC_SHIFT)
| (uint32_t)init->perCtrl.dacRef
#endif
#if defined(_LESENSE_PERCTRL_DACCONVTRIG_MASK)
| ((uint32_t)init->perCtrl.dacScan << _LESENSE_PERCTRL_DACCONVTRIG_SHIFT)
| ((uint32_t)init->perCtrl.dacStartupHalf << _LESENSE_PERCTRL_DACSTARTUP_SHIFT)
| ((uint32_t)init->perCtrl.dacScan << _LESENSE_PERCTRL_DACCONVTRIG_SHIFT)
#endif
| (uint32_t)init->perCtrl.warmupMode;
| ((uint32_t)init->perCtrl.acmp0Mode << _LESENSE_PERCTRL_ACMP0MODE_SHIFT)
| ((uint32_t)init->perCtrl.acmp1Mode << _LESENSE_PERCTRL_ACMP1MODE_SHIFT)
#if defined(_LESENSE_PERCTRL_ACMP0INV_MASK)
| ((uint32_t)init->coreCtrl.invACMP0 << _LESENSE_PERCTRL_ACMP0INV_SHIFT)
| ((uint32_t)init->coreCtrl.invACMP1 << _LESENSE_PERCTRL_ACMP1INV_SHIFT)
#endif
| (uint32_t)init->perCtrl.warmupMode;
/* LESENSE decoder general control configuration.
* Set decoder input source, select PRS input for decoder bits.
@ -217,7 +220,6 @@ void LESENSE_Init(const LESENSE_Init_TypeDef * init, bool reqReset)
LESENSE->BIASCTRL = (uint32_t)init->coreCtrl.biasMode;
}
/***************************************************************************//**
* @brief
* Set scan frequency for periodic scanning.
@ -252,11 +254,9 @@ uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t scanFreq)
uint32_t pcTop = 63UL; /* Period counter top value (max. 63). */
uint32_t calcScanFreq; /* Variable for testing the calculation algorithm. */
/* If refFreq is set to 0, the currently configured reference clock is
* assumed. */
if (!refFreq)
{
if (!refFreq) {
refFreq = CMU_ClockFreqGet(cmuClock_LESENSE);
}
@ -272,8 +272,7 @@ uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t scanFreq)
* biggest possible resolution for setting scan frequency.
* Maximum number of calculation cycles is 7 (value of lesenseClkDiv_128). */
while ((refFreq / ((uint32_t)scanFreq * clkDiv) > (pcTop + 1UL))
&& (pcPresc < lesenseClkDiv_128))
{
&& (pcPresc < lesenseClkDiv_128)) {
++pcPresc;
clkDiv = (uint32_t)1UL << pcPresc;
}
@ -299,7 +298,6 @@ uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t scanFreq)
return calcScanFreq;
}
/***************************************************************************//**
* @brief
* Set scan mode of the LESENSE channels.
@ -331,7 +329,6 @@ void LESENSE_ScanModeSet(LESENSE_ScanMode_TypeDef scanMode,
{
uint32_t tmp; /* temporary storage of the CTRL register value */
/* Save the CTRL register value to tmp.
* Please be aware the effects of the non-atomic Read-Modify-Write cycle! */
tmp = LESENSE->CTRL & ~(_LESENSE_CTRL_SCANMODE_MASK);
@ -343,13 +340,11 @@ void LESENSE_ScanModeSet(LESENSE_ScanMode_TypeDef scanMode,
LESENSE->CTRL = tmp;
/* Start sensor scanning if requested. */
if (start)
{
if (start) {
LESENSE_ScanStart();
}
}
/***************************************************************************//**
* @brief
* Set start delay of sensor interaction on each channel.
@ -372,7 +367,6 @@ void LESENSE_StartDelaySet(uint8_t startDelay)
{
uint32_t tmp; /* temporary storage of the TIMCTRL register value */
/* Sanity check of startDelay. */
EFM_ASSERT(startDelay < 4U);
@ -386,7 +380,6 @@ void LESENSE_StartDelaySet(uint8_t startDelay)
LESENSE->TIMCTRL = tmp;
}
/***************************************************************************//**
* @brief
* Set clock division for LESENSE timers.
@ -416,10 +409,8 @@ void LESENSE_ClkDivSet(LESENSE_ChClk_TypeDef clk,
{
uint32_t tmp;
/* Select clock to prescale */
switch (clk)
{
switch (clk) {
case lesenseClkHF:
/* Sanity check of clock divisor for HF clock. */
EFM_ASSERT((uint32_t)clkDiv <= lesenseClkDiv_8);
@ -451,7 +442,6 @@ void LESENSE_ClkDivSet(LESENSE_ChClk_TypeDef clk,
}
}
/***************************************************************************//**
* @brief
* Configure all (16) LESENSE sensor channels.
@ -478,14 +468,12 @@ void LESENSE_ChannelAllConfig(const LESENSE_ChAll_TypeDef * confChAll)
uint32_t i;
/* Iterate through all the 16 channels */
for (i = 0U; i < LESENSE_NUM_CHANNELS; ++i)
{
for (i = 0U; i < LESENSE_NUM_CHANNELS; ++i) {
/* Configure scan channels. */
LESENSE_ChannelConfig(&confChAll->Ch[i], i);
}
}
/***************************************************************************//**
* @brief
* Configure a single LESENSE sensor channel.
@ -513,7 +501,6 @@ void LESENSE_ChannelConfig(const LESENSE_ChDesc_TypeDef * confCh,
{
uint32_t tmp; /* Service variable. */
/* Sanity check of configuration parameters */
EFM_ASSERT(chIdx < LESENSE_NUM_CHANNELS);
EFM_ASSERT(confCh->exTime <= (_LESENSE_CH_TIMING_EXTIME_MASK >> _LESENSE_CH_TIMING_EXTIME_SHIFT));
@ -527,8 +514,7 @@ void LESENSE_ChannelConfig(const LESENSE_ChDesc_TypeDef * confCh,
* configuration parameters, check the parameter description of acmpThres for
* for more details! */
EFM_ASSERT(confCh->acmpThres < 4096U);
if (confCh->chPinExMode == lesenseChPinExDACOut)
{
if (confCh->chPinExMode == lesenseChPinExDACOut) {
EFM_ASSERT((0x1 << chIdx) & DACOUT_SUPPORT);
}
@ -563,25 +549,25 @@ void LESENSE_ChannelConfig(const LESENSE_ChDesc_TypeDef * confCh,
* alternate excitation usage and interrupt mode on scan channel chIdx in
* LESENSE_CHchIdx_INTERACT. */
LESENSE->CH[chIdx].INTERACT =
((uint32_t)confCh->exClk << _LESENSE_CH_INTERACT_EXCLK_SHIFT)
| ((uint32_t)confCh->sampleClk << _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT)
| (uint32_t)confCh->sampleMode
| (uint32_t)confCh->intMode
| (uint32_t)confCh->chPinExMode
| ((uint32_t)confCh->useAltEx << _LESENSE_CH_INTERACT_ALTEX_SHIFT);
((uint32_t)confCh->exClk << _LESENSE_CH_INTERACT_EXCLK_SHIFT)
| ((uint32_t)confCh->sampleClk << _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT)
| (uint32_t)confCh->sampleMode
| (uint32_t)confCh->intMode
| (uint32_t)confCh->chPinExMode
| ((uint32_t)confCh->useAltEx << _LESENSE_CH_INTERACT_ALTEX_SHIFT);
/* Configure channel specific counter comparison mode, optional result
* forwarding to decoder, optional counter value storing and optional result
* inverting on scan channel chIdx in LESENSE_CHchIdx_EVAL. */
LESENSE->CH[chIdx].EVAL =
(uint32_t)confCh->compMode
| ((uint32_t)confCh->shiftRes << _LESENSE_CH_EVAL_DECODE_SHIFT)
| ((uint32_t)confCh->storeCntRes << _LESENSE_CH_EVAL_STRSAMPLE_SHIFT)
| ((uint32_t)confCh->invRes << _LESENSE_CH_EVAL_SCANRESINV_SHIFT)
(uint32_t)confCh->compMode
| ((uint32_t)confCh->shiftRes << _LESENSE_CH_EVAL_DECODE_SHIFT)
| ((uint32_t)confCh->storeCntRes << _LESENSE_CH_EVAL_STRSAMPLE_SHIFT)
| ((uint32_t)confCh->invRes << _LESENSE_CH_EVAL_SCANRESINV_SHIFT)
#if defined(_LESENSE_CH_EVAL_MODE_MASK)
| ((uint32_t)confCh->evalMode << _LESENSE_CH_EVAL_MODE_SHIFT)
| ((uint32_t)confCh->evalMode << _LESENSE_CH_EVAL_MODE_SHIFT)
#endif
;
;
/* Configure analog comparator (ACMP) threshold and decision threshold for
* counter separately with the function provided for that. */
@ -599,7 +585,6 @@ void LESENSE_ChannelConfig(const LESENSE_ChDesc_TypeDef * confCh,
BUS_RegBitWrite(&LESENSE->CHEN, chIdx, confCh->enaScanCh);
}
/***************************************************************************//**
* @brief
* Configure the LESENSE alternate excitation modes.
@ -622,7 +607,6 @@ void LESENSE_AltExConfig(const LESENSE_ConfAltEx_TypeDef * confAltEx)
uint32_t i;
uint32_t tmp;
/* Configure alternate excitation mapping.
* Atomic read-modify-write using BUS_RegBitWrite function in order to
* support reconfiguration during LESENSE operation. */
@ -630,12 +614,10 @@ void LESENSE_AltExConfig(const LESENSE_ConfAltEx_TypeDef * confAltEx)
_LESENSE_CTRL_ALTEXMAP_SHIFT,
confAltEx->altExMap);
switch (confAltEx->altExMap)
{
switch (confAltEx->altExMap) {
case lesenseAltExMapALTEX:
/* Iterate through the 8 possible alternate excitation pin descriptors. */
for (i = 0U; i < 8U; ++i)
{
for (i = 0U; i < 8U; ++i) {
/* Enable/disable alternate excitation pin i.
* Atomic read-modify-write using BUS_RegBitWrite function in order to
* support reconfiguration during LESENSE operation. */
@ -663,8 +645,7 @@ void LESENSE_AltExConfig(const LESENSE_ConfAltEx_TypeDef * confAltEx)
case lesenseAltExMapCH:
#endif
/* Iterate through all the 16 alternate excitation channels */
for (i = 0U; i < 16U; ++i)
{
for (i = 0U; i < 16U; ++i) {
/* Enable/disable alternate ACMP excitation channel pin i. */
/* Atomic read-modify-write using BUS_RegBitWrite function in order to
* support reconfiguration during LESENSE operation. */
@ -680,7 +661,6 @@ void LESENSE_AltExConfig(const LESENSE_ConfAltEx_TypeDef * confAltEx)
}
}
/***************************************************************************//**
* @brief
* Enable/disable LESENSE scan channel and the pin assigned to it.
@ -719,7 +699,6 @@ void LESENSE_ChannelEnable(uint8_t chIdx,
BUS_RegBitWrite(&LESENSE->CHEN, chIdx, enaScanCh);
}
/***************************************************************************//**
* @brief
* Enable/disable LESENSE scan channel and the pin assigned to it.
@ -750,7 +729,6 @@ void LESENSE_ChannelEnableMask(uint16_t chMask, uint16_t pinMask)
GENERIC_LESENSE_ROUTE = pinMask;
}
/***************************************************************************//**
* @brief
* Set LESENSE channel timing parameters.
@ -795,12 +773,11 @@ void LESENSE_ChannelTimingSet(uint8_t chIdx,
/* Channel specific timing configuration on scan channel chIdx.
* Setting excitation time, sampling delay, measurement delay. */
LESENSE->CH[chIdx].TIMING =
((uint32_t)exTime << _LESENSE_CH_TIMING_EXTIME_SHIFT)
| ((uint32_t)sampleDelay << _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT)
| ((uint32_t)measDelay << _LESENSE_CH_TIMING_MEASUREDLY_SHIFT);
((uint32_t)exTime << _LESENSE_CH_TIMING_EXTIME_SHIFT)
| ((uint32_t)sampleDelay << _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT)
| ((uint32_t)measDelay << _LESENSE_CH_TIMING_MEASUREDLY_SHIFT);
}
/***************************************************************************//**
* @brief
* Set LESENSE channel threshold parameters.
@ -840,7 +817,6 @@ void LESENSE_ChannelThresSet(uint8_t chIdx,
{
uint32_t tmp; /* temporary storage */
/* Sanity check for acmpThres only, cntThres is 16bit value. */
EFM_ASSERT(acmpThres < 4096U);
/* Sanity check for LESENSE channel id. */
@ -1001,14 +977,12 @@ void LESENSE_DecoderStateAllConfig(const LESENSE_DecStAll_TypeDef * confDecStAll
uint32_t i;
/* Iterate through all the 16 or 32 decoder states. */
for (i = 0U; i < LESENSE_NUM_DECODER_STATES; ++i)
{
for (i = 0U; i < LESENSE_NUM_DECODER_STATES; ++i) {
/* Configure decoder state i. */
LESENSE_DecoderStateConfig(&confDecStAll->St[i], i);
}
}
/***************************************************************************//**
* @brief
* Configure a single LESENSE decoder state.
@ -1052,14 +1026,13 @@ void LESENSE_DecoderStateConfig(const LESENSE_DecStDesc_TypeDef * confDecSt,
* Setting sensor compare value, sensor mask, next state index, transition
* action and interrupt flag option configurations. */
LESENSE->ST[decSt].TCONFB =
(uint32_t)confDecSt->confB.prsAct
(uint32_t)confDecSt->confB.prsAct
| ((uint32_t)confDecSt->confB.compMask << _LESENSE_ST_TCONFB_MASK_SHIFT)
| ((uint32_t)confDecSt->confB.compVal << _LESENSE_ST_TCONFB_COMP_SHIFT)
| ((uint32_t)confDecSt->confB.nextState << _LESENSE_ST_TCONFB_NEXTSTATE_SHIFT)
| ((uint32_t)confDecSt->confB.setInt << _LESENSE_ST_TCONFB_SETIF_SHIFT);
}
/***************************************************************************//**
* @brief
* Set LESENSE decoder state.
@ -1083,7 +1056,6 @@ void LESENSE_DecoderStateSet(uint32_t decSt)
LESENSE->DECSTATE = decSt & _LESENSE_DECSTATE_DECSTATE_MASK;
}
/***************************************************************************//**
* @brief
* Get the current state of the LESENSE decoder.
@ -1149,7 +1121,6 @@ void LESENSE_ScanStart(void)
;
}
/***************************************************************************//**
* @brief
* Stop scanning of sensors.
@ -1182,7 +1153,6 @@ void LESENSE_ScanStop(void)
;
}
/***************************************************************************//**
* @brief
* Start LESENSE decoder.
@ -1212,7 +1182,6 @@ void LESENSE_DecoderStart(void)
;
}
/***************************************************************************//**
* @brief
* Clear result buffer.
@ -1241,7 +1210,6 @@ void LESENSE_ResultBufferClear(void)
;
}
/***************************************************************************//**
* @brief
* Reset the LESENSE module.
@ -1297,16 +1265,14 @@ void LESENSE_Reset(void)
#endif
/* Reset all channel configuration registers */
for (i = 0U; i < LESENSE_NUM_CHANNELS; ++i)
{
for (i = 0U; i < LESENSE_NUM_CHANNELS; ++i) {
LESENSE->CH[i].TIMING = _LESENSE_CH_TIMING_RESETVALUE;
LESENSE->CH[i].INTERACT = _LESENSE_CH_INTERACT_RESETVALUE;
LESENSE->CH[i].EVAL = _LESENSE_CH_EVAL_RESETVALUE;
}
/* Reset all decoder state configuration registers */
for (i = 0U; i < LESENSE_NUM_DECODER_STATES; ++i)
{
for (i = 0U; i < LESENSE_NUM_DECODER_STATES; ++i) {
LESENSE->ST[i].TCONFA = _LESENSE_ST_TCONFA_RESETVALUE;
LESENSE->ST[i].TCONFB = _LESENSE_ST_TCONFB_RESETVALUE;
}
@ -1317,7 +1283,6 @@ void LESENSE_Reset(void)
;
}
/** @} (end addtogroup LESENSE) */
/** @} (end addtogroup emlib) */

73
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_letimer.c
* @brief Low Energy Timer (LETIMER) Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -60,14 +60,19 @@
#define LETIMER_COMP_REG_VALID(reg) (((reg) <= 1))
/** Validation of LETIMER register block pointer reference for assert statements. */
#if (LETIMER_COUNT == 1)
#define LETIMER_REF_VALID(ref) ((ref) == LETIMER0)
#elif (LETIMER_COUNT == 2)
#define LETIMER_REF_VALID(ref) (((ref) == LETIMER0) || ((ref) == LETIMER1))
#else
#error Undefined number of analog comparators (ACMP).
#endif
/** Validation of valid repeat counter register for assert statements. */
#define LETIMER_REP_REG_VALID(reg) (((reg) <= 1))
/** @endcond */
/*******************************************************************************
************************** LOCAL FUNCTIONS ********************************
******************************************************************************/
@ -96,8 +101,9 @@ __STATIC_INLINE void regSync(LETIMER_TypeDef *letimer, uint32_t mask)
#if defined(_LETIMER_FREEZE_MASK)
/* Avoid deadlock if modifying the same register twice when freeze mode is */
/* activated. */
if (letimer->FREEZE & LETIMER_FREEZE_REGFREEZE)
if (letimer->FREEZE & LETIMER_FREEZE_REGFREEZE) {
return;
}
#endif
/* Wait for any pending previous write operation to have been completed */
@ -133,8 +139,7 @@ uint32_t LETIMER_CompareGet(LETIMER_TypeDef *letimer, unsigned int comp)
EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_COMP_REG_VALID(comp));
/* Initialize selected compare value */
switch (comp)
{
switch (comp) {
case 0:
ret = letimer->COMP0;
break;
@ -152,7 +157,6 @@ uint32_t LETIMER_CompareGet(LETIMER_TypeDef *letimer, unsigned int comp)
return(ret);
}
/***************************************************************************//**
* @brief
* Set LETIMER compare register value.
@ -186,8 +190,7 @@ void LETIMER_CompareSet(LETIMER_TypeDef *letimer,
== 0));
/* Initialize selected compare value */
switch (comp)
{
switch (comp) {
case 0:
compReg = &(letimer->COMP0);
break;
@ -209,7 +212,6 @@ void LETIMER_CompareSet(LETIMER_TypeDef *letimer,
*compReg = value;
}
/***************************************************************************//**
* @brief
* Start/stop LETIMER.
@ -237,12 +239,9 @@ void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable)
regSync(letimer, LETIMER_SYNCBUSY_CMD);
#endif
if (enable)
{
if (enable) {
letimer->CMD = LETIMER_CMD_START;
}
else
{
} else {
letimer->CMD = LETIMER_CMD_STOP;
}
}
@ -277,8 +276,7 @@ void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable)
******************************************************************************/
void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable)
{
if (enable)
{
if (enable) {
/*
* Wait for any ongoing LF synchronization to complete. This is just to
* protect against the rare case when a user
@ -292,9 +290,7 @@ void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable)
;
letimer->FREEZE = LETIMER_FREEZE_REGFREEZE;
}
else
{
} else {
letimer->FREEZE = 0;
}
}
@ -331,8 +327,7 @@ void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init)
EFM_ASSERT(LETIMER_REF_VALID(letimer));
/* Stop timer if specified to be disabled and running */
if (!(init->enable) && (letimer->STATUS & LETIMER_STATUS_RUNNING))
{
if (!(init->enable) && (letimer->STATUS & LETIMER_STATUS_RUNNING)) {
#if defined(_EFM32_GECKO_FAMILY)
/* LF register about to be modified require sync. busy check */
regSync(letimer, LETIMER_SYNCBUSY_CMD);
@ -342,40 +337,33 @@ void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init)
/* Configure DEBUGRUN flag, sets whether or not counter should be
* updated when debugger is active */
if (init->debugRun)
{
if (init->debugRun) {
tmp |= LETIMER_CTRL_DEBUGRUN;
}
#if defined(LETIMER_CTRL_RTCC0TEN)
if (init->rtcComp0Enable)
{
if (init->rtcComp0Enable) {
tmp |= LETIMER_CTRL_RTCC0TEN;
}
if (init->rtcComp1Enable)
{
if (init->rtcComp1Enable) {
tmp |= LETIMER_CTRL_RTCC1TEN;
}
#endif
if (init->comp0Top)
{
if (init->comp0Top) {
tmp |= LETIMER_CTRL_COMP0TOP;
}
if (init->bufTop)
{
if (init->bufTop) {
tmp |= LETIMER_CTRL_BUFTOP;
}
if (init->out0Pol)
{
if (init->out0Pol) {
tmp |= LETIMER_CTRL_OPOL0;
}
if (init->out1Pol)
{
if (init->out1Pol) {
tmp |= LETIMER_CTRL_OPOL1;
}
@ -390,8 +378,7 @@ void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init)
letimer->CTRL = tmp;
/* Start timer if specified to be enabled and not already running */
if (init->enable && !(letimer->STATUS & LETIMER_STATUS_RUNNING))
{
if (init->enable && !(letimer->STATUS & LETIMER_STATUS_RUNNING)) {
#if defined(_EFM32_GECKO_FAMILY)
/* LF register about to be modified require sync. busy check */
regSync(letimer, LETIMER_SYNCBUSY_CMD);
@ -400,7 +387,6 @@ void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init)
}
}
/***************************************************************************//**
* @brief
* Get LETIMER repeat register value.
@ -421,8 +407,7 @@ uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep)
EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_REP_REG_VALID(rep));
/* Initialize selected compare value */
switch (rep)
{
switch (rep) {
case 0:
ret = letimer->REP0;
break;
@ -440,7 +425,6 @@ uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep)
return(ret);
}
/***************************************************************************//**
* @brief
* Set LETIMER repeat counter register value.
@ -476,8 +460,7 @@ void LETIMER_RepeatSet(LETIMER_TypeDef *letimer,
== 0));
/* Initialize selected compare value */
switch (rep)
{
switch (rep) {
case 0:
repReg = &(letimer->REP0);
#if defined(_EFM32_GECKO_FAMILY)
@ -505,7 +488,6 @@ void LETIMER_RepeatSet(LETIMER_TypeDef *letimer,
*repReg = value;
}
/***************************************************************************//**
* @brief
* Reset LETIMER to same state as after a HW reset.
@ -542,7 +524,6 @@ void LETIMER_Reset(LETIMER_TypeDef *letimer)
#endif
}
/** @} (end addtogroup LETIMER) */
/** @} (end addtogroup emlib) */
#endif /* defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) */

61
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c
View File

@ -2,9 +2,9 @@
* @file em_leuart.c
* @brief Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
* Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -60,7 +60,6 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** Validation of LEUART register block pointer reference
* for assert statements. */
#if (LEUART_COUNT == 1)
@ -94,8 +93,7 @@ __STATIC_INLINE void LEUART_Sync(LEUART_TypeDef *leuart, uint32_t mask)
{
/* Avoid deadlock if modifying the same register twice when freeze mode is */
/* activated. */
if (leuart->FREEZE & LEUART_FREEZE_REGFREEZE)
{
if (leuart->FREEZE & LEUART_FREEZE_REGFREEZE) {
return;
}
@ -194,7 +192,6 @@ uint32_t LEUART_BaudrateCalc(uint32_t refFreq, uint32_t clkdiv)
return br;
}
/***************************************************************************//**
* @brief
* Get current baudrate for LEUART.
@ -215,18 +212,15 @@ uint32_t LEUART_BaudrateGet(LEUART_TypeDef *leuart)
CMU_Clock_TypeDef clock;
/* Get current frequency */
if (leuart == LEUART0)
{
if (leuart == LEUART0) {
clock = cmuClock_LEUART0;
}
#if (LEUART_COUNT > 1)
else if (leuart == LEUART1)
{
else if (leuart == LEUART1) {
clock = cmuClock_LEUART1;
}
#endif
else
{
else {
EFM_ASSERT(0);
return 0;
}
@ -236,7 +230,6 @@ uint32_t LEUART_BaudrateGet(LEUART_TypeDef *leuart)
return LEUART_BaudrateCalc(freq, leuart->CLKDIV);
}
/***************************************************************************//**
* @brief
* Configure baudrate (or as close as possible to specified baudrate).
@ -295,20 +288,16 @@ void LEUART_BaudrateSet(LEUART_TypeDef *leuart,
*/
/* Get current frequency? */
if (!refFreq)
{
if (leuart == LEUART0)
{
if (!refFreq) {
if (leuart == LEUART0) {
clock = cmuClock_LEUART0;
}
#if (LEUART_COUNT > 1)
else if (leuart == LEUART1)
{
else if (leuart == LEUART1) {
clock = cmuClock_LEUART1;
}
#endif
else
{
else {
EFM_ASSERT(0);
return;
}
@ -333,7 +322,6 @@ void LEUART_BaudrateSet(LEUART_TypeDef *leuart,
leuart->CLKDIV = clkdiv;
}
/***************************************************************************//**
* @brief
* Enable/disable LEUART receiver and/or transmitter.
@ -374,7 +362,6 @@ void LEUART_Enable(LEUART_TypeDef *leuart, LEUART_Enable_TypeDef enable)
leuart->CMD = tmp;
}
/***************************************************************************//**
* @brief
* LEUART register synchronization freeze control.
@ -404,8 +391,7 @@ void LEUART_Enable(LEUART_TypeDef *leuart, LEUART_Enable_TypeDef enable)
******************************************************************************/
void LEUART_FreezeEnable(LEUART_TypeDef *leuart, bool enable)
{
if (enable)
{
if (enable) {
/*
* Wait for any ongoing LF synchronization to complete. This is just to
* protect against the rare case when a user
@ -419,14 +405,11 @@ void LEUART_FreezeEnable(LEUART_TypeDef *leuart, bool enable)
;
leuart->FREEZE = LEUART_FREEZE_REGFREEZE;
}
else
{
} else {
leuart->FREEZE = 0;
}
}
/***************************************************************************//**
* @brief
* Init LEUART.
@ -489,7 +472,6 @@ void LEUART_Init(LEUART_TypeDef *leuart, LEUART_Init_TypeDef const *init)
LEUART_FreezeEnable(leuart, false);
}
/***************************************************************************//**
* @brief
* Reset LEUART to same state as after a HW reset.
@ -526,7 +508,6 @@ void LEUART_Reset(LEUART_TypeDef *leuart)
LEUART_FreezeEnable(leuart, false);
}
/***************************************************************************//**
* @brief
* Receive one 8 bit frame, (or part of 9 bit frame).
@ -556,7 +537,6 @@ uint8_t LEUART_Rx(LEUART_TypeDef *leuart)
return (uint8_t)leuart->RXDATA;
}
/***************************************************************************//**
* @brief
* Receive one 8-9 bit frame, with extended information.
@ -582,7 +562,6 @@ uint16_t LEUART_RxExt(LEUART_TypeDef *leuart)
return (uint16_t)leuart->RXDATAX;
}
/***************************************************************************//**
* @brief
* Transmit one frame.
@ -618,7 +597,6 @@ void LEUART_Tx(LEUART_TypeDef *leuart, uint8_t data)
leuart->TXDATA = (uint32_t)data;
}
/***************************************************************************//**
* @brief
* Transmit one 8-9 bit frame with extended control.
@ -667,12 +645,9 @@ void LEUART_TxDmaInEM2Enable(LEUART_TypeDef *leuart, bool enable)
/* LF register about to be modified require sync. busy check */
LEUART_Sync(leuart, LEUART_SYNCBUSY_CTRL);
if (enable)
{
if (enable) {
leuart->CTRL |= LEUART_CTRL_TXDMAWU;
}
else
{
} else {
leuart->CTRL &= ~LEUART_CTRL_TXDMAWU;
}
}
@ -694,17 +669,13 @@ void LEUART_RxDmaInEM2Enable(LEUART_TypeDef *leuart, bool enable)
/* LF register about to be modified require sync. busy check */
LEUART_Sync(leuart, LEUART_SYNCBUSY_CTRL);
if (enable)
{
if (enable) {
leuart->CTRL |= LEUART_CTRL_RXDMAWU;
}
else
{
} else {
leuart->CTRL &= ~LEUART_CTRL_RXDMAWU;
}
}
/** @} (end addtogroup LEUART) */
/** @} (end addtogroup emlib) */
#endif /* defined(LEUART_COUNT) && (LEUART_COUNT > 0) */

20
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_mpu.c
* @brief Memory Protection Unit (MPU) Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -34,13 +34,11 @@
#if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1)
#include "em_assert.h"
/***************************************************************************//**
* @addtogroup emlib
* @{
******************************************************************************/
/***************************************************************************//**
* @addtogroup MPU
* @brief Memory Protection Unit (MPU) Peripheral API
@ -69,12 +67,10 @@
* @{
******************************************************************************/
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
/***************************************************************************//**
* @brief
* Configure an MPU region.
@ -90,13 +86,12 @@
******************************************************************************/
void MPU_ConfigureRegion(const MPU_RegionInit_TypeDef *init)
{
EFM_ASSERT(init->regionNo < ((MPU->TYPE & MPU_TYPE_DREGION_Msk) >>
MPU_TYPE_DREGION_Pos));
EFM_ASSERT(init->regionNo < ((MPU->TYPE & MPU_TYPE_DREGION_Msk)
>> MPU_TYPE_DREGION_Pos));
MPU->RNR = init->regionNo;
if (init->regionEnable)
{
if (init->regionEnable) {
EFM_ASSERT(!(init->baseAddress & ~MPU_RBAR_ADDR_Msk));
EFM_ASSERT(init->tex <= 0x7);
@ -110,15 +105,12 @@ void MPU_ConfigureRegion(const MPU_RegionInit_TypeDef *init)
| (init->srd << MPU_RASR_SRD_Pos)
| (init->size << MPU_RASR_SIZE_Pos)
| (1 << MPU_RASR_ENABLE_Pos);
}
else
{
} else {
MPU->RBAR = 0;
MPU->RASR = 0;
}
}
/** @} (end addtogroup CMU) */
/** @} (end addtogroup emlib) */
#endif /* defined(__MPU_PRESENT) && (__MPU_PRESENT == 1) */

305
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_msc.c
* @brief Flash controller (MSC) Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -31,10 +31,10 @@
******************************************************************************/
#include "em_msc.h"
#if defined( MSC_COUNT ) && ( MSC_COUNT > 0 )
#if defined(MSC_COUNT) && (MSC_COUNT > 0)
#include "em_system.h"
#if defined( _MSC_TIMEBASE_MASK )
#if defined(_MSC_TIMEBASE_MASK)
#include "em_cmu.h"
#endif
#include "em_assert.h"
@ -51,13 +51,13 @@
#error "Running Flash write/erase operations from Flash is not supported on EFM32G."
#endif
#if defined( MSC_WRITECTRL_WDOUBLE )
#if defined(MSC_WRITECTRL_WDOUBLE)
#define WORDS_PER_DATA_PHASE (FLASH_SIZE < (512 * 1024) ? 1 : 2)
#else
#define WORDS_PER_DATA_PHASE (1)
#endif
#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
/* Fix for errata FLASH_E201 - Potential program failure after Power On */
#define ERRATA_FIX_FLASH_E201_EN
#endif
@ -68,18 +68,18 @@ typedef enum {
} MSC_WriteStrategy_Typedef;
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef
MSC_WriteWordI(uint32_t *address,
void const *data,
uint32_t numBytes,
MSC_WriteStrategy_Typedef writeStrategy);
MSC_WriteWordI(uint32_t *address,
void const *data,
uint32_t numBytes,
MSC_WriteStrategy_Typedef writeStrategy);
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef
MSC_LoadWriteData(uint32_t* data,
uint32_t numWords,
MSC_WriteStrategy_Typedef writeStrategy);
MSC_LoadWriteData(uint32_t* data,
uint32_t numWords,
MSC_WriteStrategy_Typedef writeStrategy);
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef
MSC_LoadVerifyAddress(uint32_t* address);
MSC_LoadVerifyAddress(uint32_t* address);
#if !defined(EM_MSC_RUN_FROM_FLASH)
@ -108,8 +108,7 @@ void mscRfAssertEFM(const char *file, int line)
(void)file; /* Unused parameter */
(void)line; /* Unused parameter */
while (true)
{
while (true) {
}
}
MSC_RAMFUNC_DEFINITION_END
@ -146,21 +145,14 @@ MSC_RAMFUNC_DEFINITION_END
* @note
* This function must be called before flash operations when
* AUXHFRCO clock has been changed from default band.
* @note
* This function calls SystemCoreClockGet in order to set the global variable
* SystemCoreClock which is used in subseqent calls of MSC_WriteWord to make
* sure the frequency is sufficiently high for flash operations. If the clock
* frequency is changed then software is responsible for calling MSC_Init or
* SystemCoreClockGet in order to set the SystemCoreClock variable to the
* correct value.
******************************************************************************/
void MSC_Init(void)
{
#if defined( _MSC_TIMEBASE_MASK )
#if defined(_MSC_TIMEBASE_MASK)
uint32_t freq, cycles;
#endif
#if defined( _EMU_STATUS_VSCALE_MASK )
#if defined(_EMU_STATUS_VSCALE_MASK)
/* VSCALE must be done and flash erase and write requires VSCALE2 */
EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK));
EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2);
@ -171,21 +163,13 @@ void MSC_Init(void)
/* Disable writing to the flash */
MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN;
/* Call SystemCoreClockGet in order to set the global variable SystemCoreClock
which is used in MSC_LoadWriteData to make sure the frequency is
sufficiently high. If the clock frequency is changed then software is
responsible for calling MSC_Init or SystemCoreClockGet in order to set the
SystemCoreClock variable to the correct value. */
SystemCoreClockGet();
#if defined( _MSC_TIMEBASE_MASK )
#if defined(_MSC_TIMEBASE_MASK)
/* Configure MSC->TIMEBASE according to selected frequency */
freq = CMU_ClockFreqGet(cmuClock_AUX);
/* Timebase 5us is used for the 1/1.2MHz band only. Note that the 1MHz band
is tuned to 1.2MHz on newer revisions. */
if (freq > 1200000)
{
if (freq > 1200000) {
/* Calculate number of clock cycles for 1us as base period */
freq = (freq * 11) / 10;
cycles = (freq / 1000000) + 1;
@ -195,9 +179,7 @@ void MSC_Init(void)
| _MSC_TIMEBASE_PERIOD_MASK))
| MSC_TIMEBASE_PERIOD_1US
| (cycles << _MSC_TIMEBASE_BASE_SHIFT);
}
else
{
} else {
/* Calculate number of clock cycles for 5us as base period */
freq = (freq * 5 * 11) / 10;
cycles = (freq / 1000000) + 1;
@ -223,7 +205,6 @@ void MSC_Deinit(void)
MSC->LOCK = 0;
}
/***************************************************************************//**
* @brief
* Set MSC code execution configuration
@ -235,77 +216,65 @@ void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig)
{
uint32_t mscReadCtrl;
#if defined( MSC_READCTRL_MODE_WS0SCBTP )
#if defined(MSC_READCTRL_MODE_WS0SCBTP)
mscReadCtrl = MSC->READCTRL & _MSC_READCTRL_MODE_MASK;
if ((mscReadCtrl == MSC_READCTRL_MODE_WS0) && (execConfig->scbtEn))
{
if ((mscReadCtrl == MSC_READCTRL_MODE_WS0) && (execConfig->scbtEn)) {
mscReadCtrl |= MSC_READCTRL_MODE_WS0SCBTP;
}
else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1) && (execConfig->scbtEn))
{
} else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1) && (execConfig->scbtEn)) {
mscReadCtrl |= MSC_READCTRL_MODE_WS1SCBTP;
}
else if ((mscReadCtrl == MSC_READCTRL_MODE_WS0SCBTP) && (!execConfig->scbtEn))
{
} else if ((mscReadCtrl == MSC_READCTRL_MODE_WS0SCBTP) && (!execConfig->scbtEn)) {
mscReadCtrl |= MSC_READCTRL_MODE_WS0;
}
else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1SCBTP) && (!execConfig->scbtEn))
{
} else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1SCBTP) && (!execConfig->scbtEn)) {
mscReadCtrl |= MSC_READCTRL_MODE_WS1;
}
else
{
} else {
/* No change needed */
}
#endif
mscReadCtrl = MSC->READCTRL & ~(0
#if defined( MSC_READCTRL_SCBTP )
#if defined(MSC_READCTRL_SCBTP)
| MSC_READCTRL_SCBTP
#endif
#if defined( MSC_READCTRL_USEHPROT )
#if defined(MSC_READCTRL_USEHPROT)
| MSC_READCTRL_USEHPROT
#endif
#if defined( MSC_READCTRL_PREFETCH )
#if defined(MSC_READCTRL_PREFETCH)
| MSC_READCTRL_PREFETCH
#endif
#if defined( MSC_READCTRL_ICCDIS )
#if defined(MSC_READCTRL_ICCDIS)
| MSC_READCTRL_ICCDIS
#endif
#if defined( MSC_READCTRL_AIDIS )
#if defined(MSC_READCTRL_AIDIS)
| MSC_READCTRL_AIDIS
#endif
#if defined( MSC_READCTRL_IFCDIS )
#if defined(MSC_READCTRL_IFCDIS)
| MSC_READCTRL_IFCDIS
#endif
);
mscReadCtrl |= (0
#if defined( MSC_READCTRL_SCBTP )
| (execConfig->scbtEn ? MSC_READCTRL_SCBTP : 0)
#if defined(MSC_READCTRL_SCBTP)
| (execConfig->scbtEn ? MSC_READCTRL_SCBTP : 0)
#endif
#if defined( MSC_READCTRL_USEHPROT )
| (execConfig->useHprot ? MSC_READCTRL_USEHPROT : 0)
#if defined(MSC_READCTRL_USEHPROT)
| (execConfig->useHprot ? MSC_READCTRL_USEHPROT : 0)
#endif
#if defined( MSC_READCTRL_PREFETCH )
| (execConfig->prefetchEn ? MSC_READCTRL_PREFETCH : 0)
#if defined(MSC_READCTRL_PREFETCH)
| (execConfig->prefetchEn ? MSC_READCTRL_PREFETCH : 0)
#endif
#if defined( MSC_READCTRL_ICCDIS )
| (execConfig->iccDis ? MSC_READCTRL_ICCDIS : 0)
#if defined(MSC_READCTRL_ICCDIS)
| (execConfig->iccDis ? MSC_READCTRL_ICCDIS : 0)
#endif
#if defined( MSC_READCTRL_AIDIS )
| (execConfig->aiDis ? MSC_READCTRL_AIDIS : 0)
#if defined(MSC_READCTRL_AIDIS)
| (execConfig->aiDis ? MSC_READCTRL_AIDIS : 0)
#endif
#if defined( MSC_READCTRL_IFCDIS )
| (execConfig->ifcDis ? MSC_READCTRL_IFCDIS : 0)
#if defined(MSC_READCTRL_IFCDIS)
| (execConfig->ifcDis ? MSC_READCTRL_IFCDIS : 0)
#endif
);
);
MSC->READCTRL = mscReadCtrl;
}
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/***************************************************************************//**
@ -333,14 +302,12 @@ MSC_Status_TypeDef MSC_LoadVerifyAddress(uint32_t* address)
/* Wait for the MSC to become ready. */
timeOut = MSC_PROGRAM_TIMEOUT;
while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0))
{
while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) {
timeOut--;
}
/* Check for timeout */
if (timeOut == 0)
{
if (timeOut == 0) {
return mscReturnTimeOut;
}
/* Load address */
@ -348,20 +315,20 @@ MSC_Status_TypeDef MSC_LoadVerifyAddress(uint32_t* address)
MSC->WRITECMD = MSC_WRITECMD_LADDRIM;
status = MSC->STATUS;
if (status & (MSC_STATUS_INVADDR | MSC_STATUS_LOCKED))
{
if (status & (MSC_STATUS_INVADDR | MSC_STATUS_LOCKED)) {
/* Check for invalid address */
if (status & MSC_STATUS_INVADDR)
if (status & MSC_STATUS_INVADDR) {
return mscReturnInvalidAddr;
}
/* Check for write protected page */
if (status & MSC_STATUS_LOCKED)
if (status & MSC_STATUS_LOCKED) {
return mscReturnLocked;
}
}
return mscReturnOk;
}
MSC_RAMFUNC_DEFINITION_END
/***************************************************************************//**
* @brief
* Perform a Flash data write phase.
@ -391,28 +358,24 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data,
uint32_t wordIndex;
bool useWDouble = false;
MSC_Status_TypeDef retval = mscReturnOk;
#if !defined( _EFM32_GECKO_FAMILY )
#if !defined(_EFM32_GECKO_FAMILY)
uint32_t irqState;
#endif
#if defined(_MSC_WRITECTRL_LPWRITE_MASK) && defined(_MSC_WRITECTRL_WDOUBLE_MASK)
/* If LPWRITE (Low Power Write) is NOT enabled, set WDOUBLE (Write Double word) */
if (!(MSC->WRITECTRL & MSC_WRITECTRL_LPWRITE))
{
if (!(MSC->WRITECTRL & MSC_WRITECTRL_LPWRITE)) {
#if defined(_SILICON_LABS_32B_SERIES_0)
/* If the number of words to be written are odd, we need to align by writing
a single word first, before setting the WDOUBLE bit. */
if (numWords & 0x1)
{
if (numWords & 0x1) {
/* Wait for the MSC to become ready for the next word. */
timeOut = MSC_PROGRAM_TIMEOUT;
while ((!(MSC->STATUS & MSC_STATUS_WDATAREADY)) && (timeOut != 0))
{
while ((!(MSC->STATUS & MSC_STATUS_WDATAREADY)) && (timeOut != 0)) {
timeOut--;
}
/* Check for timeout */
if (timeOut == 0)
{
if (timeOut == 0) {
return mscReturnTimeOut;
}
/* Clear double word option, in order to write the initial single word. */
@ -424,13 +387,11 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data,
/* Wait for the operation to finish. It may be required to change the WDOUBLE
config after the initial write. It should not be changed while BUSY. */
timeOut = MSC_PROGRAM_TIMEOUT;
while((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0))
{
while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) {
timeOut--;
}
/* Check for timeout */
if (timeOut == 0)
{
if (timeOut == 0) {
return mscReturnTimeOut;
}
/* Subtract this initial odd word for the write loop below */
@ -446,37 +407,29 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data,
#endif /* defined( _MSC_WRITECTRL_LPWRITE_MASK ) && defined( _MSC_WRITECTRL_WDOUBLE_MASK ) */
/* Write the rest as double word write if wordsPerDataPhase == 2 */
if (numWords > 0)
{
if (numWords > 0) {
/**** Write strategy: mscWriteIntSafe ****/
if (writeStrategy == mscWriteIntSafe)
{
if (writeStrategy == mscWriteIntSafe) {
/* Requires a system core clock at 1MHz or higher */
EFM_ASSERT(SystemCoreClock >= 1000000);
wordIndex = 0;
while(wordIndex < numWords)
{
if (!useWDouble)
{
while (wordIndex < numWords) {
if (!useWDouble) {
MSC->WDATA = *data++;
wordIndex++;
MSC->WRITECMD = MSC_WRITECMD_WRITEONCE;
}
else // useWDouble == true
{
/* Trigger double write according to flash properties. */
#if defined(_SILICON_LABS_32B_SERIES_0)
} else { // useWDouble == true
/* Trigger double write according to flash properties. */
#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_MSC_WRITECTRL_WDOUBLE_MASK)
MSC->WDATA = *data++;
while (!(MSC->STATUS & MSC_STATUS_WDATAREADY));
while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)) ;
MSC->WDATA = *data++;
wordIndex += 2;
MSC->WRITECMD = MSC_WRITECMD_WRITEONCE;
#elif (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2)
while (!(MSC->STATUS & MSC_STATUS_WDATAREADY));
do
{
#elif defined(_SILICON_LABS_32B_SERIES_1) && defined(_MSC_WRITECTRL_WDOUBLE_MASK)
while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)) ;
do {
MSC->WDATA = *data++;
wordIndex++;
} while ((MSC->STATUS & MSC_STATUS_WDATAREADY)
@ -487,27 +440,23 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data,
/* Wait for the transaction to finish. */
timeOut = MSC_PROGRAM_TIMEOUT;
while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0))
{
while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) {
timeOut--;
}
/* Check for timeout */
if (timeOut == 0)
{
if (timeOut == 0) {
retval = mscReturnTimeOut;
break;
}
#if defined( _EFM32_GECKO_FAMILY )
#if defined(_EFM32_GECKO_FAMILY)
MSC->ADDRB += 4;
MSC->WRITECMD = MSC_WRITECMD_LADDRIM;
#endif
}
}
/**** Write strategy: mscWriteFast ****/
else
{
#if defined( _EFM32_GECKO_FAMILY )
else {
#if defined(_EFM32_GECKO_FAMILY)
/* Gecko does not have auto-increment of ADDR. */
EFM_ASSERT(false);
#else
@ -522,11 +471,9 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data,
__disable_irq();
wordIndex = 0;
while(wordIndex < numWords)
{
while (wordIndex < numWords) {
/* Wait for the MSC to be ready for the next word. */
while (!(MSC->STATUS & MSC_STATUS_WDATAREADY))
{
while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)) {
/* If the write to MSC->WDATA below missed the 30us timeout and the
following MSC_WRITECMD_WRITETRIG command arrived while
MSC_STATUS_BUSY is 1, then the MSC_WRITECMD_WRITETRIG could be ignored by
@ -535,39 +482,32 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data,
complete write of data in MSC->WDATA.
If WDATAREADY became high since entry into this loop, exit and continue
to the next WDATA write.
*/
*/
if ((MSC->STATUS & (MSC_STATUS_WORDTIMEOUT
| MSC_STATUS_BUSY
| MSC_STATUS_WDATAREADY))
== MSC_STATUS_WORDTIMEOUT)
{
== MSC_STATUS_WORDTIMEOUT) {
MSC->WRITECMD = MSC_WRITECMD_WRITETRIG;
}
}
if (!useWDouble)
{
if (!useWDouble) {
MSC->WDATA = *data;
MSC->WRITECMD = MSC_WRITECMD_WRITETRIG;
data++;
wordIndex++;
}
else // useWDouble == true
{
/* Trigger double write according to flash properties. */
} else { // useWDouble == true
/* Trigger double write according to flash properties. */
#if defined(_SILICON_LABS_32B_SERIES_0)
MSC->WDATA = *data;
if (wordIndex & 0x1)
{
if (wordIndex & 0x1) {
MSC->WRITECMD = MSC_WRITECMD_WRITETRIG;
}
data++;
wordIndex++;
#elif (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2)
do
{
do {
MSC->WDATA = *data++;
wordIndex++;
} while ((MSC->STATUS & MSC_STATUS_WDATAREADY)
@ -577,28 +517,25 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data,
}
}
if (irqState == 0)
{
if (irqState == 0) {
/* Restore previous interrupt state. */
__enable_irq();
}
/* Wait for the transaction to finish. */
timeOut = MSC_PROGRAM_TIMEOUT;
while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0))
{
while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) {
timeOut--;
}
/* Check for timeout */
if (timeOut == 0)
{
if (timeOut == 0) {
retval = mscReturnTimeOut;
}
#endif
} /* writeStrategy */
}
#if defined( _MSC_WRITECTRL_WDOUBLE_MASK )
#if defined(_MSC_WRITECTRL_WDOUBLE_MASK)
/* Clear double word option, which should not be left on when returning. */
MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE;
#endif
@ -607,7 +544,6 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data,
}
MSC_RAMFUNC_DEFINITION_END
/***************************************************************************//**
* @brief
* Internal flash write function with select write strategy parameter
@ -640,7 +576,7 @@ MSC_Status_TypeDef MSC_WriteWordI(uint32_t *address,
/* Check number of bytes. Must be divisable by four */
EFM_ASSERT((numBytes & 0x3) == 0);
#if defined( _EMU_STATUS_VSCALE_MASK )
#if defined(_EMU_STATUS_VSCALE_MASK)
/* VSCALE must be done and flash write requires VSCALE2 */
EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK));
EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2);
@ -656,35 +592,31 @@ MSC_Status_TypeDef MSC_WriteWordI(uint32_t *address,
/* The following loop splits the data into chunks corresponding to flash pages.
The address is loaded only once per page, because the hardware automatically
increments the address internally for each data load inside a page. */
for (wordCount = 0, pData = (uint32_t *)data; wordCount < numWords; )
{
for (wordCount = 0, pData = (uint32_t *)data; wordCount < numWords; ) {
/* First we load address. The address is auto-incremented within a page.
Therefore the address phase is only needed once for each page. */
retval = MSC_LoadVerifyAddress(address + wordCount);
if (mscReturnOk != retval)
{
if (mscReturnOk != retval) {
return retval;
}
/* Compute the number of words to write to the current page. */
pageWords =
(FLASH_PAGE_SIZE -
(((uint32_t) (address + wordCount)) & (FLASH_PAGE_SIZE - 1)))
(FLASH_PAGE_SIZE
- (((uint32_t) (address + wordCount)) & (FLASH_PAGE_SIZE - 1)))
/ sizeof(uint32_t);
if (pageWords > numWords - wordCount)
{
if (pageWords > numWords - wordCount) {
pageWords = numWords - wordCount;
}
/* Now write the data in the current page. */
retval = MSC_LoadWriteData(pData, pageWords, writeStrategy);
if (mscReturnOk != retval)
{
if (mscReturnOk != retval) {
break;
}
wordCount += pageWords;
pData += pageWords;
}
#if defined( ERRATA_FIX_FLASH_E201_EN )
#if defined(ERRATA_FIX_FLASH_E201_EN)
/* Fix for errata FLASH_E201 - Potential program failure after Power On.
*
* Check if the first word was programmed correctly. If a failure is detected
@ -692,11 +624,9 @@ MSC_Status_TypeDef MSC_WriteWordI(uint32_t *address,
*
* Full description of errata can be found in the errata document */
pData = (uint32_t *) data;
if (*address != *pData)
{
if (*address != *pData) {
retval = MSC_LoadVerifyAddress(address);
if (mscReturnOk == retval)
{
if (mscReturnOk == retval) {
retval = MSC_LoadWriteData(pData, 1, writeStrategy);
}
}
@ -705,8 +635,8 @@ MSC_Status_TypeDef MSC_WriteWordI(uint32_t *address,
/* Disable writing to the MSC */
MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN;
#if defined( _MSC_WRITECTRL_WDOUBLE_MASK )
#if ( WORDS_PER_DATA_PHASE == 2 )
#if defined(_MSC_WRITECTRL_WDOUBLE_MASK)
#if (WORDS_PER_DATA_PHASE == 2)
/* Turn off double word write cycle support. */
MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE;
#endif
@ -718,7 +648,6 @@ MSC_RAMFUNC_DEFINITION_END
/** @endcond */
/***************************************************************************//**
* @brief
* Erases a page in flash memory.
@ -751,7 +680,7 @@ MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress)
/* Address must be aligned to pages */
EFM_ASSERT((((uint32_t) startAddress) & (FLASH_PAGE_SIZE - 1)) == 0);
#if defined( _EMU_STATUS_VSCALE_MASK )
#if defined(_EMU_STATUS_VSCALE_MASK)
/* VSCALE must be done and flash erase requires VSCALE2 */
EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK));
EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2);
@ -765,15 +694,13 @@ MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress)
MSC->WRITECMD = MSC_WRITECMD_LADDRIM;
/* Check for invalid address */
if (MSC->STATUS & MSC_STATUS_INVADDR)
{
if (MSC->STATUS & MSC_STATUS_INVADDR) {
/* Disable writing to the MSC */
MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN;
return mscReturnInvalidAddr;
}
/* Check for write protected page */
if (MSC->STATUS & MSC_STATUS_LOCKED)
{
if (MSC->STATUS & MSC_STATUS_LOCKED) {
/* Disable writing to the MSC */
MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN;
return mscReturnLocked;
@ -782,12 +709,10 @@ MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress)
MSC->WRITECMD = MSC_WRITECMD_ERASEPAGE;
/* Wait for the erase to complete */
while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0))
{
while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) {
timeOut--;
}
if (timeOut == 0)
{
if (timeOut == 0) {
/* Disable writing to the MSC */
MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN;
return mscReturnTimeOut;
@ -798,7 +723,6 @@ MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress)
}
MSC_RAMFUNC_DEFINITION_END
/***************************************************************************//**
* @brief
* Writes data to flash memory. This function is interrupt safe, but slower than
@ -844,8 +768,7 @@ MSC_Status_TypeDef MSC_WriteWord(uint32_t *address,
}
MSC_RAMFUNC_DEFINITION_END
#if !defined( _EFM32_GECKO_FAMILY )
#if !defined(_EFM32_GECKO_FAMILY)
/***************************************************************************//**
* @brief
* Writes data to flash memory. This function is faster than MSC_WriteWord(),
@ -853,9 +776,8 @@ MSC_RAMFUNC_DEFINITION_END
* a number of bytes that is divisable by four.
* @note
* It is recommended to erase the flash page before performing a write.
* It is recommended to run this code from RAM. On the Gecko family, it is required
* to run this function from RAM.
* It is required to run this function from RAM on parts that include a
* flash write buffer.
*
* For IAR, Rowley, SimplicityStudio, Atollic and armgcc this will be achieved
* automatically by using attributes in the function proctype. For Keil uVision you
@ -879,6 +801,7 @@ MSC_RAMFUNC_DEFINITION_END
* the next word into the DWORD register.
* @endverbatim
******************************************************************************/
#if !defined (EM_MSC_RUN_FROM_FLASH) || (_SILICON_LABS_GECKO_INTERNAL_SDID < 84)
MSC_RAMFUNC_DEFINITION_BEGIN
MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address,
void const *data,
@ -888,10 +811,10 @@ MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address,
}
MSC_RAMFUNC_DEFINITION_END
#endif
#endif
#if defined( _MSC_MASSLOCK_MASK )
#if defined(_MSC_MASSLOCK_MASK)
/***************************************************************************//**
* @brief
* Erase entire flash in one operation
@ -915,14 +838,14 @@ MSC_Status_TypeDef MSC_MassErase(void)
MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN0;
/* Waiting for erase to complete */
while ((MSC->STATUS & MSC_STATUS_BUSY));
while ((MSC->STATUS & MSC_STATUS_BUSY)) ;
#if ((FLASH_SIZE >= (512 * 1024)) && defined( _MSC_WRITECMD_ERASEMAIN1_MASK ))
#if ((FLASH_SIZE >= (512 * 1024)) && defined(_MSC_WRITECMD_ERASEMAIN1_MASK))
/* Erase second 512K block */
MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN1;
/* Waiting for erase to complete */
while ((MSC->STATUS & MSC_STATUS_BUSY));
while ((MSC->STATUS & MSC_STATUS_BUSY)) ;
#endif
/* Restore mass erase lock */

169
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c
View File

@ -1,9 +1,9 @@
/**************************************************************************//**
/***************************************************************************//**
* @file em_opamp.c
* @brief Operational Amplifier (OPAMP) peripheral API
* @version 5.1.2
* @version 5.3.3
******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -32,7 +32,7 @@
#include "em_opamp.h"
#if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \
|| (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0)))
|| (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0)))
#include "em_system.h"
#include "em_assert.h"
@ -42,7 +42,7 @@
* @{
******************************************************************************/
/* *INDENT-OFF* */
/***************************************************************************//**
* @addtogroup OPAMP
* @brief Operational Amplifier (OPAMP) peripheral API
@ -206,7 +206,7 @@
* @if DOXYDOC_P2_DEVICE
* \n<b>Instrumentation amplifier.</b>\n
* Use predefined macros @ref OPA_INIT_INSTR_AMP_OPA0 and
* @ref OPA_INIT_INSTR_AMP_OPA0.
* @ref OPA_INIT_INSTR_AMP_OPA1.
* @verbatim
|\
@ -235,6 +235,7 @@
*
* @{
******************************************************************************/
/* *INDENT-ON* */
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
@ -268,18 +269,13 @@ void OPAMP_Disable(
EFM_ASSERT(DAC_REF_VALID(dac));
EFM_ASSERT(DAC_OPA_VALID(opa));
if (opa == OPA0)
{
if (opa == OPA0) {
dac->CH0CTRL &= ~DAC_CH0CTRL_EN;
dac->OPACTRL &= ~DAC_OPACTRL_OPA0EN;
}
else if (opa == OPA1)
{
} else if (opa == OPA1) {
dac->CH1CTRL &= ~DAC_CH1CTRL_EN;
dac->OPACTRL &= ~DAC_OPACTRL_OPA1EN;
}
else /* OPA2 */
{
} else { /* OPA2 */
dac->OPACTRL &= ~DAC_OPACTRL_OPA2EN;
}
@ -287,31 +283,28 @@ void OPAMP_Disable(
EFM_ASSERT(VDAC_REF_VALID(dac));
EFM_ASSERT(VDAC_OPA_VALID(opa));
if (opa == OPA0)
{
if (opa == OPA0) {
#if defined(VDAC_STATUS_OPA0ENS)
dac->CMD |= VDAC_CMD_OPA0DIS;
while (dac->STATUS & VDAC_STATUS_OPA0ENS)
{
while (dac->STATUS & VDAC_STATUS_OPA0ENS) {
}
}
else if (opa == OPA1)
{
#endif
} else if (opa == OPA1) {
#if defined(VDAC_STATUS_OPA1ENS)
dac->CMD |= VDAC_CMD_OPA1DIS;
while (dac->STATUS & VDAC_STATUS_OPA1ENS)
{
while (dac->STATUS & VDAC_STATUS_OPA1ENS) {
}
}
else /* OPA2 */
{
#endif
} else { /* OPA2 */
#if defined(VDAC_STATUS_OPA2ENS)
dac->CMD |= VDAC_CMD_OPA2DIS;
while (dac->STATUS & VDAC_STATUS_OPA2ENS)
{
while (dac->STATUS & VDAC_STATUS_OPA2ENS) {
}
#endif
}
#endif
}
/***************************************************************************//**
* @brief
* Configure and enable an Operational Amplifier.
@ -379,15 +372,14 @@ void OPAMP_Enable(
const OPAMP_Init_TypeDef *init)
{
#if defined(_SILICON_LABS_32B_SERIES_0)
uint32_t offset;
uint32_t gain;
EFM_ASSERT(DAC_REF_VALID(dac));
EFM_ASSERT(DAC_OPA_VALID(opa));
EFM_ASSERT(init->bias <= (_DAC_BIASPROG_BIASPROG_MASK
>> _DAC_BIASPROG_BIASPROG_SHIFT));
>> _DAC_BIASPROG_BIASPROG_SHIFT));
if (opa == OPA0)
{
if (opa == OPA0) {
EFM_ASSERT((init->outPen & ~_DAC_OPA0MUX_OUTPEN_MASK) == 0);
dac->BIASPROG = (dac->BIASPROG
@ -396,14 +388,11 @@ void OPAMP_Enable(
| (init->bias << _DAC_BIASPROG_BIASPROG_SHIFT)
| (init->halfBias ? DAC_BIASPROG_HALFBIAS : 0);
if (init->defaultOffset)
{
offset = SYSTEM_GetCalibrationValue(&dac->CAL);
dac->CAL = (dac->CAL & ~_DAC_CAL_CH0OFFSET_MASK)
| (offset & _DAC_CAL_CH0OFFSET_MASK);
}
else
{
if (init->defaultOffset) {
gain = dac->CAL & _DAC_CAL_GAIN_MASK;
SYSTEM_GetCalibrationValue(&dac->CAL);
dac->CAL = (dac->CAL & ~_DAC_CAL_GAIN_MASK) | gain;
} else {
EFM_ASSERT(init->offset <= (_DAC_CAL_CH0OFFSET_MASK
>> _DAC_CAL_CH0OFFSET_SHIFT));
@ -417,9 +406,9 @@ void OPAMP_Enable(
| (uint32_t)init->resInMux
| (uint32_t)init->negSel
| (uint32_t)init->posSel
| ( init->nextOut ? DAC_OPA0MUX_NEXTOUT : 0)
| ( init->npEn ? DAC_OPA0MUX_NPEN : 0)
| ( init->ppEn ? DAC_OPA0MUX_PPEN : 0);
| (init->nextOut ? DAC_OPA0MUX_NEXTOUT : 0)
| (init->npEn ? DAC_OPA0MUX_NPEN : 0)
| (init->ppEn ? DAC_OPA0MUX_PPEN : 0);
dac->CH0CTRL |= DAC_CH0CTRL_EN;
dac->OPACTRL = (dac->OPACTRL
@ -433,25 +422,20 @@ void OPAMP_Enable(
? DAC_OPACTRL_OPA0LPFDIS_NLPFDIS : 0)
| (init->hcmDisable ? DAC_OPACTRL_OPA0HCMDIS : 0)
| DAC_OPACTRL_OPA0EN;
}
else if ( opa == OPA1 )
{
} else if ( opa == OPA1 ) {
EFM_ASSERT((init->outPen & ~_DAC_OPA1MUX_OUTPEN_MASK) == 0);
dac->BIASPROG = (dac->BIASPROG
& ~(_DAC_BIASPROG_BIASPROG_MASK
| DAC_BIASPROG_HALFBIAS))
| (init->bias << _DAC_BIASPROG_BIASPROG_SHIFT)
| (init->halfBias ? DAC_BIASPROG_HALFBIAS : 0 );
| (init->halfBias ? DAC_BIASPROG_HALFBIAS : 0);
if (init->defaultOffset)
{
offset = SYSTEM_GetCalibrationValue(&dac->CAL);
dac->CAL = (dac->CAL & ~_DAC_CAL_CH1OFFSET_MASK)
| (offset & _DAC_CAL_CH1OFFSET_MASK);
}
else
{
if (init->defaultOffset) {
gain = dac->CAL & _DAC_CAL_GAIN_MASK;
SYSTEM_GetCalibrationValue(&dac->CAL);
dac->CAL = (dac->CAL & ~_DAC_CAL_GAIN_MASK) | gain;
} else {
EFM_ASSERT(init->offset <= (_DAC_CAL_CH1OFFSET_MASK
>> _DAC_CAL_CH1OFFSET_SHIFT));
@ -481,9 +465,7 @@ void OPAMP_Enable(
? DAC_OPACTRL_OPA1LPFDIS_NLPFDIS : 0)
| (init->hcmDisable ? DAC_OPACTRL_OPA1HCMDIS : 0)
| DAC_OPACTRL_OPA1EN;
}
else /* OPA2 */
{
} else { /* OPA2 */
EFM_ASSERT((init->posSel == DAC_OPA2MUX_POSSEL_DISABLE)
|| (init->posSel == DAC_OPA2MUX_POSSEL_POSPAD)
|| (init->posSel == DAC_OPA2MUX_POSSEL_OPA1INP)
@ -499,14 +481,9 @@ void OPAMP_Enable(
| (init->bias << _DAC_BIASPROG_OPA2BIASPROG_SHIFT)
| (init->halfBias ? DAC_BIASPROG_OPA2HALFBIAS : 0);
if (init->defaultOffset)
{
offset = SYSTEM_GetCalibrationValue(&dac->OPAOFFSET);
dac->OPAOFFSET = (dac->OPAOFFSET & ~_DAC_OPAOFFSET_OPA2OFFSET_MASK)
| (offset & _DAC_OPAOFFSET_OPA2OFFSET_MASK);
}
else
{
if (init->defaultOffset) {
SYSTEM_GetCalibrationValue(&dac->OPAOFFSET);
} else {
EFM_ASSERT(init->offset <= (_DAC_OPAOFFSET_OPA2OFFSET_MASK
>> _DAC_OPAOFFSET_OPA2OFFSET_SHIFT));
dac->OPAOFFSET = (dac->OPAOFFSET & ~_DAC_OPAOFFSET_OPA2OFFSET_MASK)
@ -519,9 +496,9 @@ void OPAMP_Enable(
| (uint32_t)init->resInMux
| (uint32_t)init->negSel
| (uint32_t)init->posSel
| ( init->nextOut ? DAC_OPA2MUX_NEXTOUT : 0 )
| ( init->npEn ? DAC_OPA2MUX_NPEN : 0 )
| ( init->ppEn ? DAC_OPA2MUX_PPEN : 0 );
| (init->nextOut ? DAC_OPA2MUX_NEXTOUT : 0)
| (init->npEn ? DAC_OPA2MUX_NPEN : 0)
| (init->ppEn ? DAC_OPA2MUX_PPEN : 0);
dac->OPACTRL = (dac->OPACTRL
& ~(DAC_OPACTRL_OPA2SHORT
@ -548,8 +525,8 @@ void OPAMP_Enable(
>> _VDAC_OPA_TIMER_STARTUPDLY_SHIFT));
EFM_ASSERT((init->outPen & ~_VDAC_OPA_OUT_ALTOUTPADEN_MASK) == 0);
EFM_ASSERT(!((init->gain3xEn == true)
&& ((init->negSel == opaNegSelResTap)
|| (init->posSel == opaPosSelResTap))));
&& ((init->negSel == opaNegSelResTap)
|| (init->posSel == opaPosSelResTap))));
EFM_ASSERT((init->drvStr == opaDrvStrLowerAccLowStr)
|| (init->drvStr == opaDrvStrLowAccLowStr)
|| (init->drvStr == opaDrvStrHighAccHighStr)
@ -559,11 +536,10 @@ void OPAMP_Enable(
OPAMP_Disable(dac, opa);
/* Get the calibration value based on OPAMP, Drive Strength, and INCBW. */
switch (opa)
{
switch (opa) {
#if defined(VDAC_STATUS_OPA0ENS)
case OPA0:
switch (init->drvStr)
{
switch (init->drvStr) {
case opaDrvStrLowerAccLowStr:
calData = (init->ugBwScale ? DEVINFO->OPA0CAL0 : DEVINFO->OPA0CAL4);
break;
@ -578,10 +554,11 @@ void OPAMP_Enable(
break;
}
break;
#endif
#if defined(VDAC_STATUS_OPA1ENS)
case OPA1:
switch (init->drvStr)
{
switch (init->drvStr) {
case opaDrvStrLowerAccLowStr:
calData = (init->ugBwScale ? DEVINFO->OPA1CAL0 : DEVINFO->OPA1CAL4);
break;
@ -596,10 +573,11 @@ void OPAMP_Enable(
break;
}
break;
#endif
#if defined(VDAC_STATUS_OPA2ENS)
case OPA2:
switch (init->drvStr)
{
switch (init->drvStr) {
case opaDrvStrLowerAccLowStr:
calData = (init->ugBwScale ? DEVINFO->OPA2CAL0 : DEVINFO->OPA2CAL4);
break;
@ -614,16 +592,15 @@ void OPAMP_Enable(
break;
}
break;
#endif
}
if (!init->defaultOffsetN)
{
if (!init->defaultOffsetN) {
EFM_ASSERT(init->offsetN <= (_VDAC_OPA_CAL_OFFSETN_MASK
>> _VDAC_OPA_CAL_OFFSETN_SHIFT));
calData = (calData & ~_VDAC_OPA_CAL_OFFSETN_MASK)
| (init->offsetN << _VDAC_OPA_CAL_OFFSETN_SHIFT);
}
if (!init->defaultOffsetP)
{
if (!init->defaultOffsetP) {
EFM_ASSERT(init->offsetP <= (_VDAC_OPA_CAL_OFFSETP_MASK
>> _VDAC_OPA_CAL_OFFSETP_SHIFT));
calData = (calData & ~_VDAC_OPA_CAL_OFFSETP_MASK)
@ -641,8 +618,7 @@ void OPAMP_Enable(
dac->OPA[opa].OUT = (uint32_t)init->outMode
| (uint32_t)init->outPen;
switch (init->drvStr)
{
switch (init->drvStr) {
case opaDrvStrHigherAccHighStr:
warmupTime = 6;
break;
@ -678,22 +654,23 @@ void OPAMP_Enable(
| (init->prsEn ? VDAC_OPA_CTRL_PRSEN : 0)
| (init->halfDrvStr
? VDAC_OPA_CTRL_OUTSCALE_HALF
: VDAC_OPA_CTRL_OUTSCALE_FULL)
: VDAC_OPA_CTRL_OUTSCALE_FULL)
| (init->hcmDisable ? VDAC_OPA_CTRL_HCMDIS : 0)
| (init->ugBwScale ? VDAC_OPA_CTRL_INCBW : 0)
| (uint32_t)init->drvStr;
if (opa == OPA0)
{
if (opa == OPA0) {
#if defined(VDAC_STATUS_OPA0ENS)
dac->CMD |= VDAC_CMD_OPA0EN;
}
else if (opa == OPA1)
{
#endif
} else if (opa == OPA1) {
#if defined(VDAC_STATUS_OPA1ENS)
dac->CMD |= VDAC_CMD_OPA1EN;
}
else /* OPA2 */
{
#endif
} else { /* OPA2 */
#if defined(VDAC_STATUS_OPA2ENS)
dac->CMD |= VDAC_CMD_OPA2EN;
#endif
}
#endif
@ -703,4 +680,4 @@ void OPAMP_Enable(
/** @} (end addtogroup emlib) */
#endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)
|| defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */
|| defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */

157
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_pcnt.c
* @brief Pulse Counter (PCNT) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -59,22 +59,20 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** Validation of PCNT register block pointer reference for assert statements. */
#if (PCNT_COUNT == 1)
#define PCNT_REF_VALID(ref) ((ref) == PCNT0)
#elif (PCNT_COUNT == 2)
#define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1))
#elif (PCNT_COUNT == 3)
#define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1) || \
((ref) == PCNT2))
#define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1) \
|| ((ref) == PCNT2))
#else
#error "Undefined number of pulse counters (PCNT)."
#endif
/** @endcond */
/*******************************************************************************
************************** LOCAL FUNCTIONS ********************************
******************************************************************************/
@ -96,7 +94,6 @@ __STATIC_INLINE unsigned int PCNT_Map(PCNT_TypeDef *pcnt)
return ((uint32_t)pcnt - PCNT0_BASE) / 0x400;
}
/***************************************************************************//**
* @brief
* Wait for ongoing sync of register(s) to low frequency domain to complete.
@ -112,8 +109,7 @@ __STATIC_INLINE void PCNT_Sync(PCNT_TypeDef *pcnt, uint32_t mask)
{
/* Avoid deadlock if modifying the same register twice when freeze mode is
* activated. */
if (pcnt->FREEZE & PCNT_FREEZE_REGFREEZE)
{
if (pcnt->FREEZE & PCNT_FREEZE_REGFREEZE) {
return;
}
@ -154,7 +150,6 @@ void PCNT_CounterReset(PCNT_TypeDef *pcnt)
BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0);
}
/***************************************************************************//**
* @brief
* Set counter and top values.
@ -186,26 +181,23 @@ void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top)
EFM_ASSERT(PCNT_REF_VALID(pcnt));
#ifdef PCNT0
if (PCNT0 == pcnt)
{
EFM_ASSERT((1<<PCNT0_CNT_SIZE) > count);
EFM_ASSERT((1<<PCNT0_CNT_SIZE) > top);
if (PCNT0 == pcnt) {
EFM_ASSERT((1 << PCNT0_CNT_SIZE) > count);
EFM_ASSERT((1 << PCNT0_CNT_SIZE) > top);
}
#endif
#ifdef PCNT1
if (PCNT1 == pcnt)
{
EFM_ASSERT((1<<PCNT1_CNT_SIZE) > count);
EFM_ASSERT((1<<PCNT1_CNT_SIZE) > top);
if (PCNT1 == pcnt) {
EFM_ASSERT((1 << PCNT1_CNT_SIZE) > count);
EFM_ASSERT((1 << PCNT1_CNT_SIZE) > top);
}
#endif
#ifdef PCNT2
if (PCNT2 == pcnt)
{
EFM_ASSERT((1<<PCNT2_CNT_SIZE) > count);
EFM_ASSERT((1<<PCNT2_CNT_SIZE) > top);
if (PCNT2 == pcnt) {
EFM_ASSERT((1 << PCNT2_CNT_SIZE) > count);
EFM_ASSERT((1 << PCNT2_CNT_SIZE) > top);
}
#endif
@ -213,8 +205,7 @@ void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top)
ctrl = pcnt->CTRL;
/* If enabled, disable pulse counter before changing values */
if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE)
{
if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE) {
PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
pcnt->CTRL = (ctrl & ~_PCNT_CTRL_MODE_MASK) | PCNT_CTRL_MODE_DISABLE;
}
@ -236,8 +227,7 @@ void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top)
/* Restore TOP? ('count' setting has been loaded into pcnt->TOP, better
* to use 'top' than pcnt->TOP in compare, since latter may in theory not
* be visible yet.) */
if (top != count)
{
if (top != count) {
/* Wait for command to sync LCNTIM before setting TOPB */
PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD);
@ -251,14 +241,12 @@ void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top)
}
/* Reenable if it was enabled */
if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE)
{
if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE) {
PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL | PCNT_SYNCBUSY_CMD);
pcnt->CTRL = ctrl;
}
}
/***************************************************************************//**
* @brief
* Set PCNT operational mode.
@ -320,8 +308,7 @@ void PCNT_PRSInputEnable(PCNT_TypeDef *pcnt,
EFM_ASSERT(PCNT_REF_VALID(pcnt));
/* Enable/disable the selected PRS input on the selected PCNT module. */
switch (prsInput)
{
switch (prsInput) {
/* Enable/disable PRS input S0. */
case pcntPRSInputS0:
BUS_RegBitWrite(&(pcnt->INPUT), _PCNT_INPUT_S0PRSEN_SHIFT, enable);
@ -335,12 +322,11 @@ void PCNT_PRSInputEnable(PCNT_TypeDef *pcnt,
/* Invalid parameter, asserted. */
default:
EFM_ASSERT(0);
break;
break;
}
}
#endif
/***************************************************************************//**
* @brief
* PCNT register synchronization freeze control.
@ -372,8 +358,7 @@ void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable)
{
EFM_ASSERT(PCNT_REF_VALID(pcnt));
if (enable)
{
if (enable) {
/* Wait for any ongoing LF synchronization to complete. This is just to
* protect against the rare case when a user:
* - modifies a register requiring LF sync
@ -385,14 +370,11 @@ void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable)
;
pcnt->FREEZE = PCNT_FREEZE_REGFREEZE;
}
else
{
} else {
pcnt->FREEZE = 0;
}
}
/***************************************************************************//**
* @brief
* Init pulse counter.
@ -440,26 +422,23 @@ void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init)
EFM_ASSERT(PCNT_REF_VALID(pcnt));
#ifdef PCNT0
if (PCNT0 == pcnt)
{
EFM_ASSERT((1<<PCNT0_CNT_SIZE) > init->counter);
EFM_ASSERT((1<<PCNT0_CNT_SIZE) > init->top);
if (PCNT0 == pcnt) {
EFM_ASSERT((1 << PCNT0_CNT_SIZE) > init->counter);
EFM_ASSERT((1 << PCNT0_CNT_SIZE) > init->top);
}
#endif
#ifdef PCNT1
if (PCNT1 == pcnt)
{
EFM_ASSERT((1<<PCNT1_CNT_SIZE) > init->counter);
EFM_ASSERT((1<<PCNT1_CNT_SIZE) > init->top);
if (PCNT1 == pcnt) {
EFM_ASSERT((1 << PCNT1_CNT_SIZE) > init->counter);
EFM_ASSERT((1 << PCNT1_CNT_SIZE) > init->top);
}
#endif
#ifdef PCNT2
if (PCNT2 == pcnt)
{
EFM_ASSERT((1<<PCNT2_CNT_SIZE) > init->counter);
EFM_ASSERT((1<<PCNT2_CNT_SIZE) > init->top);
if (PCNT2 == pcnt) {
EFM_ASSERT((1 << PCNT2_CNT_SIZE) > init->counter);
EFM_ASSERT((1 << PCNT2_CNT_SIZE) > init->top);
}
#endif
@ -471,38 +450,33 @@ void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init)
* written with a Read-Modify-Write sequence in order to keep the value of the
* input enable bits which can be modified using PCNT_PRSInputEnable(). */
tmp = pcnt->INPUT & ~(_PCNT_INPUT_S0PRSSEL_MASK | _PCNT_INPUT_S1PRSSEL_MASK);
tmp |= ((uint32_t)init->s0PRS << _PCNT_INPUT_S0PRSSEL_SHIFT) |
((uint32_t)init->s1PRS << _PCNT_INPUT_S1PRSSEL_SHIFT);
tmp |= ((uint32_t)init->s0PRS << _PCNT_INPUT_S0PRSSEL_SHIFT)
| ((uint32_t)init->s1PRS << _PCNT_INPUT_S1PRSSEL_SHIFT);
pcnt->INPUT = tmp;
#endif
/* Build CTRL setting, except for mode */
tmp = 0;
if (init->negEdge)
{
if (init->negEdge) {
tmp |= PCNT_CTRL_EDGE_NEG;
}
if (init->countDown)
{
if (init->countDown) {
tmp |= PCNT_CTRL_CNTDIR_DOWN;
}
if (init->filter)
{
if (init->filter) {
tmp |= PCNT_CTRL_FILT;
}
#if defined(PCNT_CTRL_HYST)
if (init->hyst)
{
if (init->hyst) {
tmp |= PCNT_CTRL_HYST;
}
#endif
#if defined(PCNT_CTRL_S1CDIR)
if (init->s1CntDir)
{
if (init->s1CntDir) {
tmp |= PCNT_CTRL_S1CDIR;
}
#endif
@ -518,10 +492,9 @@ void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init)
the CTRL register because the AUXCNTEV field values are different from
the CNTEV field values, and cntEvent and auxCntEvent are of the same type
PCNT_CntEvent_TypeDef.
*/
*/
uint32_t auxCntEventField = 0; /* Get rid of compiler warning. */
switch (init->auxCntEvent)
{
switch (init->auxCntEvent) {
case pcntCntEventBoth:
auxCntEventField = pcntCntEventNone;
break;
@ -549,8 +522,7 @@ void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init)
CMU_PCNTClockExternalSet(inst, false);
/* Handling depends on whether using external clock or not. */
switch (init->mode)
{
switch (init->mode) {
case pcntModeExtSingle:
case pcntModeExtQuad:
tmp |= init->mode << _PCNT_CTRL_MODE_SHIFT;
@ -596,8 +568,7 @@ void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init)
/* pcntModeOvsSingle */
default:
/* No need to set disabled mode if already disabled. */
if ((pcnt->CTRL & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE)
{
if ((pcnt->CTRL & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE) {
/* Set control to disabled mode, leave reset on until ensured disabled.
* We don't need to wait for CTRL SYNCBUSY completion here, it was
* triggered by reset bit above, which is asynchronous. */
@ -615,8 +586,7 @@ void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init)
PCNT_CounterTopSet(pcnt, init->counter, init->top);
/* Enter oversampling mode if selected. */
if (init->mode == pcntModeOvsSingle)
{
if (init->mode == pcntModeOvsSingle) {
PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
pcnt->CTRL = tmp | (init->mode << _PCNT_CTRL_MODE_SHIFT);
}
@ -624,7 +594,6 @@ void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init)
}
}
/***************************************************************************//**
* @brief
* Reset PCNT to same state as after a HW reset.
@ -695,7 +664,8 @@ void PCNT_Reset(PCNT_TypeDef *pcnt)
* @param[in] enable
* Whether to enable or disable filtering
******************************************************************************/
void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *config, bool enable) {
void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *config, bool enable)
{
uint32_t ovscfg = 0;
EFM_ASSERT(PCNT_REF_VALID(pcnt));
@ -708,15 +678,11 @@ void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *con
PCNT_Sync(pcnt, PCNT_SYNCBUSY_OVSCFG);
pcnt->OVSCFG = ovscfg;
/* Set new state of filter. LF register requires sync check before writing. */
PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
if(enable)
{
if (enable) {
pcnt->CTRL |= PCNT_CTRL_FILT;
}
else
{
} else {
pcnt->CTRL &= ~PCNT_CTRL_FILT;
}
}
@ -744,7 +710,8 @@ void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *con
* @param[in] config
* Pointer to configuration structure to be applied.
******************************************************************************/
void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config){
void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config)
{
uint32_t ctrl = 0;
uint32_t mask = _PCNT_CTRL_TCCMODE_MASK
| _PCNT_CTRL_TCCPRESC_MASK
@ -756,12 +723,12 @@ void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config){
EFM_ASSERT(PCNT_REF_VALID(pcnt));
/* construct TCC part of configuration register */
ctrl |= (config->mode << _PCNT_CTRL_TCCMODE_SHIFT ) & _PCNT_CTRL_TCCMODE_MASK;
ctrl |= (config->prescaler << _PCNT_CTRL_TCCPRESC_SHIFT ) & _PCNT_CTRL_TCCPRESC_MASK;
ctrl |= (config->compare << _PCNT_CTRL_TCCCOMP_SHIFT ) & _PCNT_CTRL_TCCCOMP_MASK;
ctrl |= (config->tccPRS << _PCNT_CTRL_TCCPRSSEL_SHIFT ) & _PCNT_CTRL_TCCPRSSEL_MASK;
ctrl |= (config->prsPolarity << _PCNT_CTRL_TCCPRSPOL_SHIFT ) & _PCNT_CTRL_TCCPRSPOL_MASK;
ctrl |= (config->prsGateEnable << _PCNT_CTRL_PRSGATEEN_SHIFT ) & _PCNT_CTRL_PRSGATEEN_MASK;
ctrl |= (config->mode << _PCNT_CTRL_TCCMODE_SHIFT) & _PCNT_CTRL_TCCMODE_MASK;
ctrl |= (config->prescaler << _PCNT_CTRL_TCCPRESC_SHIFT) & _PCNT_CTRL_TCCPRESC_MASK;
ctrl |= (config->compare << _PCNT_CTRL_TCCCOMP_SHIFT) & _PCNT_CTRL_TCCCOMP_MASK;
ctrl |= (config->tccPRS << _PCNT_CTRL_TCCPRSSEL_SHIFT) & _PCNT_CTRL_TCCPRSSEL_MASK;
ctrl |= (config->prsPolarity << _PCNT_CTRL_TCCPRSPOL_SHIFT) & _PCNT_CTRL_TCCPRSPOL_MASK;
ctrl |= (config->prsGateEnable << _PCNT_CTRL_PRSGATEEN_SHIFT) & _PCNT_CTRL_PRSGATEEN_MASK;
/* Load new TCC config to PCNT. LF register requires sync check before write. */
PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
@ -794,7 +761,6 @@ void PCNT_TopBufferSet(PCNT_TypeDef *pcnt, uint32_t val)
pcnt->TOPB = val;
}
/***************************************************************************//**
* @brief
* Set top value.
@ -816,23 +782,20 @@ void PCNT_TopSet(PCNT_TypeDef *pcnt, uint32_t val)
EFM_ASSERT(PCNT_REF_VALID(pcnt));
#ifdef PCNT0
if (PCNT0 == pcnt)
{
EFM_ASSERT((1<<PCNT0_CNT_SIZE) > val);
if (PCNT0 == pcnt) {
EFM_ASSERT((1 << PCNT0_CNT_SIZE) > val);
}
#endif
#ifdef PCNT1
if (PCNT1 == pcnt)
{
EFM_ASSERT((1<<PCNT1_CNT_SIZE) > val);
if (PCNT1 == pcnt) {
EFM_ASSERT((1 << PCNT1_CNT_SIZE) > val);
}
#endif
#ifdef PCNT2
if (PCNT2 == pcnt)
{
EFM_ASSERT((1<<PCNT2_CNT_SIZE) > val);
if (PCNT2 == pcnt) {
EFM_ASSERT((1 << PCNT2_CNT_SIZE) > val);
}
#endif

6
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_prs.c
* @brief Peripheral Reflex System (PRS) Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -83,7 +83,7 @@ void PRS_SourceSignalSet(unsigned int ch,
| (uint32_t)edge;
}
#if defined( PRS_CH_CTRL_ASYNC )
#if defined(PRS_CH_CTRL_ASYNC)
/***************************************************************************//**
* @brief
* Set source and asynchronous signal to be used for a channel.

287
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_qspi.c Normal file
View File

@ -0,0 +1,287 @@
/***************************************************************************//**
* @file em_qspi.c
* @brief QSPI Octal-SPI Flash Controller API
* @version 5.3.3
*******************************************************************************
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
* obligation to support this Software. Silicon Labs is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Silicon Labs will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#include "em_qspi.h"
#if defined(QSPI_COUNT) && (QSPI_COUNT > 0)
#include "em_assert.h"
/***************************************************************************//**
* @addtogroup emlib
* @{
******************************************************************************/
/* *INDENT-OFF* */
/***************************************************************************//**
* @addtogroup QSPI
* @brief QSPI Octal-SPI Controller API
* @details
* These QSPI functions provide basic support for using the QSPI peripheral
* in the following configurations:
* @li @b Direct Read/Write, used for memory mapped access to external
* memory.
* @li @b STIG Command, used for configuring and executing commands on the
* external memory device.
*
* Indirect read/write, PHY configuration and Execute-In-Place (XIP)
* configuration is not supported.
*
* The example below shows how to set up the QSPI for direct read and write
* operation:
* @code
CMU_ClockEnable(cmuClock_GPIO, true);
CMU_ClockEnable(cmuClock_QSPI0, true);
QSPI_Init_TypeDef initQspi = QSPI_INIT_DEFAULT;
QSPI_Init(QSPI0, &initQspi);
// Configure QSPI pins
GPIO_PinModeSet(EXTFLASH_PORT_CS, EXTFLASH_PIN_CS, gpioModePushPull, 0);
GPIO_PinModeSet(EXTFLASH_PORT_SCLK, EXTFLASH_PIN_SCLK, gpioModePushPull, 0);
GPIO_PinModeSet(EXTFLASH_PORT_DQ0, EXTFLASH_PIN_DQ0, gpioModePushPull, 0);
GPIO_PinModeSet(EXTFLASH_PORT_DQ1, EXTFLASH_PIN_DQ1, gpioModePushPull, 0);
GPIO_PinModeSet(EXTFLASH_PORT_DQ2, EXTFLASH_PIN_DQ2, gpioModePushPull, 0);
GPIO_PinModeSet(EXTFLASH_PORT_DQ3, EXTFLASH_PIN_DQ3, gpioModePushPull, 0);
// Configure QSPI routing to GPIO
QSPI0->ROUTELOC0 = EXTFLASH_QSPI_LOC;
QSPI0->ROUTEPEN = QSPI_ROUTEPEN_SCLKPEN
| EXTFLASH_QSPI_CSPEN
| QSPI_ROUTEPEN_DQ0PEN
| QSPI_ROUTEPEN_DQ1PEN
| QSPI_ROUTEPEN_DQ2PEN
| QSPI_ROUTEPEN_DQ3PEN;
// Configure direct read
QSPI_ReadConfig_TypeDef readConfig = QSPI_READCONFIG_DEFAULT;
readConfig.dummyCycles = 8;
readConfig.opCode = 0x6B;
readConfig.instTransfer = qspiTransferSingle;
readConfig.addrTransfer = qspiTransferSingle;
readConfig.dataTransfer = qspiTransferQuad;
QSPI_ReadConfig(QSPI0, &readConfig);
// Configure direct write
QSPI_WriteConfig_TypeDef writeConfig = QSPI_WRITECONFIG_DEFAULT;
writeConfig.dummyCycles = 0;
writeConfig.opCode = 0x38;
writeConfig.addrTransfer = qspiTransferQuad;
writeConfig.dataTransfer = qspiTransferQuad;
writeConfig.autoWEL = true;
QSPI_WriteConfig(QSPI0, &writeConfig);@endcode
*
* To configure an external flash, commands can set up and executed using the
* Software Triggered Instruction Generator (STIG) function of the QSPI, as
* shown in the example below:
* @code
uint8_t status;
QSPI_StigCmd_TypeDef stigCmd = {0};
stigCmd.cmdOpcode = EXTFLASH_OPCODE_READ_STATUS;
stigCmd.readDataSize = 1;
stigCmd.readBuffer = &status;
QSPI_ExecStigCmd(QSPI0, &stigCmd);@endcode
* @{
******************************************************************************/
/* *INDENT-OFF* */
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
/***************************************************************************//**
* @brief
* Initialize QSPI.
*
* @param[in] qspi
* Pointer to the QSPI peripheral register block.
*
* @param[in] init
* Pointer to initialization structure used to configure QSPI.
******************************************************************************/
void QSPI_Init(QSPI_TypeDef * qspi, const QSPI_Init_TypeDef * init)
{
uint32_t divisor;
EFM_ASSERT((init->divisor >= 2) && (init->divisor <= 32));
divisor = init->divisor / 2 - 1;
qspi->CONFIG = (qspi->CONFIG & ~_QSPI_CONFIG_MSTRBAUDDIV_MASK)
| (divisor << _QSPI_CONFIG_MSTRBAUDDIV_SHIFT);
QSPI_Enable(qspi, init->enable);
}
/***************************************************************************//**
* @brief
* Configure Read Operations.
*
* @param[in] qspi
* Pointer to the QSPI peripheral register block.
*
* @param[in] config
* Pointer to configuration structure for QSPI read operations.
******************************************************************************/
void QSPI_ReadConfig(QSPI_TypeDef * qspi, const QSPI_ReadConfig_TypeDef * config)
{
EFM_ASSERT(config->dummyCycles < 31);
QSPI_WaitForIdle(qspi);
qspi->DEVINSTRRDCONFIG = (config->opCode << _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_SHIFT)
| (config->dummyCycles << _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_SHIFT)
| (config->addrTransfer << _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_SHIFT)
| (config->dataTransfer << _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_SHIFT)
| (config->instTransfer << _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_SHIFT);
}
/***************************************************************************//**
* @brief
* Configure Write Operations.
*
* @param[in] qspi
* Pointer to the QSPI peripheral register block.
*
* @param[in] config
* Pointer to configuration structure for QSPI write operations.
******************************************************************************/
void QSPI_WriteConfig(QSPI_TypeDef * qspi, const QSPI_WriteConfig_TypeDef * config)
{
EFM_ASSERT(config->dummyCycles < 31);
QSPI_WaitForIdle(qspi);
qspi->DEVINSTRWRCONFIG = (config->opCode << _QSPI_DEVINSTRWRCONFIG_WROPCODE_SHIFT)
| (config->dummyCycles << _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_SHIFT)
| (config->addrTransfer << _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_SHIFT)
| (config->dataTransfer << _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_SHIFT)
| ((config->autoWEL ? 0 : 1) << _QSPI_DEVINSTRWRCONFIG_WELDIS_SHIFT);
}
/***************************************************************************//**
* @brief
* Execute a STIG command.
*
* @details
* STIG means "software triggered instruction generator" and is used when the
* application needs to access status registers, configuration registers or
* perform erase functions. The STIG commands can be used to perform any
* instruction that the flash device supports.
*
* @param[in] qspi
* Pointer to the QSPI peripheral register block.
*
* @param[in] stigCmd
* Pointer to a structure that describes the STIG command.
******************************************************************************/
void QSPI_ExecStigCmd(QSPI_TypeDef * qspi, const QSPI_StigCmd_TypeDef * stigCmd)
{
uint32_t i;
EFM_ASSERT(stigCmd->addrSize <= 4);
EFM_ASSERT(stigCmd->writeDataSize <= 8);
EFM_ASSERT(stigCmd->readDataSize <= 8);
EFM_ASSERT(stigCmd->dummyCycles < 32);
if (stigCmd->writeDataSize) {
EFM_ASSERT(stigCmd->writeBuffer);
}
if (stigCmd->readDataSize) {
EFM_ASSERT(stigCmd->readBuffer);
}
QSPI_WaitForIdle(qspi);
qspi->FLASHCMDCTRL = (stigCmd->cmdOpcode << _QSPI_FLASHCMDCTRL_CMDOPCODE_SHIFT)
| (stigCmd->dummyCycles << _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_SHIFT);
if (stigCmd->writeDataSize) {
uint32_t buffer[2] = { 0, 0 };
uint8_t * dst = (uint8_t *) buffer;
uint8_t * src = stigCmd->writeBuffer;
qspi->FLASHCMDCTRL |= QSPI_FLASHCMDCTRL_ENBWRITEDATA
| ((stigCmd->writeDataSize - 1)
<< _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_SHIFT);
for (i = 0; i < stigCmd->writeDataSize; i++) {
dst[i] = src[i];
}
qspi->FLASHWRDATALOWER = buffer[0];
qspi->FLASHWRDATAUPPER = buffer[1];
}
if (stigCmd->addrSize) {
qspi->FLASHCMDCTRL |= QSPI_FLASHCMDCTRL_ENBCOMDADDR
| ((stigCmd->addrSize - 1)
<< _QSPI_FLASHCMDCTRL_NUMADDRBYTES_SHIFT);
qspi->FLASHCMDADDR = stigCmd->address;
}
if (stigCmd->modeBitEnable) {
qspi->FLASHCMDCTRL |= QSPI_FLASHCMDCTRL_ENBMODEBIT;
}
if (stigCmd->readDataSize) {
qspi->FLASHCMDCTRL |= QSPI_FLASHCMDCTRL_ENBREADDATA
| ((stigCmd->readDataSize - 1)
<< _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_SHIFT);
}
// Start command execution
qspi->FLASHCMDCTRL |= QSPI_FLASHCMDCTRL_CMDEXEC;
while (qspi->FLASHCMDCTRL & QSPI_FLASHCMDCTRL_CMDEXECSTATUS)
;
// Read data if any
if (stigCmd->readDataSize) {
uint32_t buffer[2] = { 0, 0 };
const uint8_t * src = (const uint8_t *)buffer;
uint8_t * dst = stigCmd->readBuffer;
buffer[0] = qspi->FLASHRDDATALOWER;
buffer[1] = qspi->FLASHRDDATAUPPER;
for (i = 0; i < stigCmd->readDataSize; i++) {
dst[i] = src[i];
}
}
}
/** @} (end addtogroup QSPI) */
/** @} (end addtogroup emlib) */
#endif /* defined(QSPI_COUNT) && (QSPI_COUNT > 0) */

116
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c
View File

@ -2,9 +2,9 @@
* @file em_rmu.c
* @brief Reset Management Unit (RMU) peripheral module peripheral API
*
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -124,11 +124,25 @@
#define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */
#define NUM_RSTCAUSES 9
/* EFM32GG11 */
#elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00011F1DUL)
#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */
#define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */
#define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL /** 0000000000000001 < DVDD BOD Reset */
#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL /** 0000000000000001 < Regulated Domain (DEC) BOD Reset */
#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */
#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL /** 0000000000011101 < LOCKUP Reset */
#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL /** 0000000000011101 < System Request Reset */
#define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL /** 0000000000011101 < Watchdog Reset */
#define RMU_RSTCAUSE_BUMODERST_XMASK 0x0000001DUL /** 0000000000011101 < Backup mode reset */
#define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */
#define NUM_RSTCAUSES 10
#else
#error "RMU_RSTCAUSE XMASKs are not defined for this family."
#endif
#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
/* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H */
#define ERRATA_FIX_EMU_E208_EN
#endif
@ -138,63 +152,62 @@
******************************************************************************/
/** Reset cause mask type. */
typedef struct
{
typedef struct {
/** Reset-cause 1 bits */
uint32_t resetCauseMask;
/** Reset-cause 0 and "don't care" bits */
uint32_t resetCauseZeroXMask;
} RMU_ResetCauseMasks_Typedef;
/*******************************************************************************
******************************* TYPEDEFS **********************************
******************************************************************************/
/** Reset cause mask table. */
static const RMU_ResetCauseMasks_Typedef resetCauseMasks[NUM_RSTCAUSES] =
{
{ RMU_RSTCAUSE_PORST, RMU_RSTCAUSE_PORST_XMASK },
{
{ RMU_RSTCAUSE_PORST, RMU_RSTCAUSE_PORST_XMASK },
#if defined(RMU_RSTCAUSE_BODUNREGRST)
{ RMU_RSTCAUSE_BODUNREGRST, RMU_RSTCAUSE_BODUNREGRST_XMASK },
{ RMU_RSTCAUSE_BODUNREGRST, RMU_RSTCAUSE_BODUNREGRST_XMASK },
#endif
#if defined(RMU_RSTCAUSE_BODREGRST)
{ RMU_RSTCAUSE_BODREGRST, RMU_RSTCAUSE_BODREGRST_XMASK },
{ RMU_RSTCAUSE_BODREGRST, RMU_RSTCAUSE_BODREGRST_XMASK },
#endif
#if defined(RMU_RSTCAUSE_AVDDBOD)
{ RMU_RSTCAUSE_AVDDBOD, RMU_RSTCAUSE_BODAVDD_XMASK },
{ RMU_RSTCAUSE_AVDDBOD, RMU_RSTCAUSE_BODAVDD_XMASK },
#endif
#if defined(RMU_RSTCAUSE_DVDDBOD)
{ RMU_RSTCAUSE_DVDDBOD, RMU_RSTCAUSE_BODDVDD_XMASK },
{ RMU_RSTCAUSE_DVDDBOD, RMU_RSTCAUSE_BODDVDD_XMASK },
#endif
#if defined(RMU_RSTCAUSE_DECBOD)
{ RMU_RSTCAUSE_DECBOD, RMU_RSTCAUSE_BODREGRST_XMASK },
{ RMU_RSTCAUSE_DECBOD, RMU_RSTCAUSE_BODREGRST_XMASK },
#endif
{ RMU_RSTCAUSE_EXTRST, RMU_RSTCAUSE_EXTRST_XMASK },
{ RMU_RSTCAUSE_WDOGRST, RMU_RSTCAUSE_WDOGRST_XMASK },
{ RMU_RSTCAUSE_LOCKUPRST, RMU_RSTCAUSE_LOCKUPRST_XMASK },
{ RMU_RSTCAUSE_SYSREQRST, RMU_RSTCAUSE_SYSREQRST_XMASK },
{ RMU_RSTCAUSE_EXTRST, RMU_RSTCAUSE_EXTRST_XMASK },
{ RMU_RSTCAUSE_WDOGRST, RMU_RSTCAUSE_WDOGRST_XMASK },
{ RMU_RSTCAUSE_LOCKUPRST, RMU_RSTCAUSE_LOCKUPRST_XMASK },
{ RMU_RSTCAUSE_SYSREQRST, RMU_RSTCAUSE_SYSREQRST_XMASK },
#if defined(RMU_RSTCAUSE_EM4RST)
{ RMU_RSTCAUSE_EM4RST, RMU_RSTCAUSE_EM4RST_XMASK },
{ RMU_RSTCAUSE_EM4RST, RMU_RSTCAUSE_EM4RST_XMASK },
#endif
#if defined(RMU_RSTCAUSE_EM4WURST)
{ RMU_RSTCAUSE_EM4WURST, RMU_RSTCAUSE_EM4WURST_XMASK },
{ RMU_RSTCAUSE_EM4WURST, RMU_RSTCAUSE_EM4WURST_XMASK },
#endif
#if defined(RMU_RSTCAUSE_BODAVDD0)
{ RMU_RSTCAUSE_BODAVDD0, RMU_RSTCAUSE_BODAVDD0_XMASK },
{ RMU_RSTCAUSE_BODAVDD0, RMU_RSTCAUSE_BODAVDD0_XMASK },
#endif
#if defined(RMU_RSTCAUSE_BODAVDD1)
{ RMU_RSTCAUSE_BODAVDD1, RMU_RSTCAUSE_BODAVDD1_XMASK },
{ RMU_RSTCAUSE_BODAVDD1, RMU_RSTCAUSE_BODAVDD1_XMASK },
#endif
#if defined(BU_PRESENT)
{ RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK },
{ RMU_RSTCAUSE_BUBODBUVIN, RMU_RSTCAUSE_BUBODBUVIN_XMASK },
{ RMU_RSTCAUSE_BUBODUNREG, RMU_RSTCAUSE_BUBODUNREG_XMASK },
{ RMU_RSTCAUSE_BUBODREG, RMU_RSTCAUSE_BUBODREG_XMASK },
{ RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK },
#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
{ RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK },
{ RMU_RSTCAUSE_BUBODBUVIN, RMU_RSTCAUSE_BUBODBUVIN_XMASK },
{ RMU_RSTCAUSE_BUBODUNREG, RMU_RSTCAUSE_BUBODUNREG_XMASK },
{ RMU_RSTCAUSE_BUBODREG, RMU_RSTCAUSE_BUBODREG_XMASK },
{ RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK },
#elif defined(RMU_RSTCAUSE_BUMODERST)
{ RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK },
#endif
};
};
/*******************************************************************************
******************************** TEST ********************************
@ -236,7 +249,6 @@ void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode)
#endif
}
/***************************************************************************//**
* @brief
* Clear the reset cause register.
@ -257,23 +269,20 @@ void RMU_ResetCauseClear(void)
/* Clear some reset causes not cleared with RMU CMD register */
/* (If EMU registers locked, they must be unlocked first) */
locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED;
if (locked)
{
if (locked) {
EMU_Unlock();
}
BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1);
BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0);
if (locked)
{
if (locked) {
EMU_Lock();
}
}
#endif
}
/***************************************************************************//**
* @brief
* Get the cause of the last reset.
@ -290,7 +299,7 @@ void RMU_ResetCauseClear(void)
******************************************************************************/
uint32_t RMU_ResetCauseGet(void)
{
#define LB_CLW0 (* ((volatile uint32_t *)(LOCKBITS_BASE) + 122))
#define LB_CLW0 (*((volatile uint32_t *)(LOCKBITS_BASE) +122))
#define LB_CLW0_PINRESETSOFT (1 << 2)
#if !defined(EMLIB_REGRESSION_TEST)
@ -300,22 +309,19 @@ uint32_t RMU_ResetCauseGet(void)
uint32_t zeroXMask;
uint32_t i;
for (i = 0; i < NUM_RSTCAUSES; i++)
{
for (i = 0; i < NUM_RSTCAUSES; i++) {
zeroXMask = resetCauseMasks[i].resetCauseZeroXMask;
#if defined( _SILICON_LABS_32B_SERIES_1 )
#if defined(_SILICON_LABS_32B_SERIES_1)
/* Handle soft/hard pin reset */
if (!(LB_CLW0 & LB_CLW0_PINRESETSOFT))
{
if (!(LB_CLW0 & LB_CLW0_PINRESETSOFT)) {
/* RSTCAUSE_EXTRST must be 0 if pin reset is configured as hard reset */
switch (resetCauseMasks[i].resetCauseMask)
{
switch (resetCauseMasks[i].resetCauseMask) {
case RMU_RSTCAUSE_LOCKUPRST:
/* Fallthrough */
/* Fallthrough */
case RMU_RSTCAUSE_SYSREQRST:
/* Fallthrough */
/* Fallthrough */
case RMU_RSTCAUSE_WDOGRST:
/* Fallthrough */
/* Fallthrough */
case RMU_RSTCAUSE_EM4RST:
zeroXMask |= RMU_RSTCAUSE_EXTRST;
break;
@ -323,10 +329,9 @@ uint32_t RMU_ResetCauseGet(void)
}
#endif
#if defined( _EMU_EM4CTRL_MASK ) && defined( ERRATA_FIX_EMU_E208_EN )
#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN)
/* Ignore BOD flags impacted by EMU_E208 */
if (*(volatile uint32_t *)(EMU_BASE + 0x88) & (0x1 << 8))
{
if (*(volatile uint32_t *)(EMU_BASE + 0x88) & (0x1 << 8)) {
zeroXMask &= ~(RMU_RSTCAUSE_DECBOD
| RMU_RSTCAUSE_DVDDBOD
| RMU_RSTCAUSE_AVDDBOD);
@ -336,25 +341,22 @@ uint32_t RMU_ResetCauseGet(void)
/* Check reset cause requirements. Note that a bit is "don't care" if 0 in
both resetCauseMask and resetCauseZeroXMask. */
if ((rstCause & resetCauseMasks[i].resetCauseMask)
&& !(rstCause & zeroXMask))
{
&& !(rstCause & zeroXMask)) {
/* Add this reset-cause to the mask of qualified reset-causes */
validRstCause |= resetCauseMasks[i].resetCauseMask;
}
}
#if defined( _EMU_EM4CTRL_MASK ) && defined( ERRATA_FIX_EMU_E208_EN )
#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN)
/* Clear BOD flags impacted by EMU_E208 */
if (validRstCause & RMU_RSTCAUSE_EM4RST)
{
if (validRstCause & RMU_RSTCAUSE_EM4RST) {
validRstCause &= ~(RMU_RSTCAUSE_DECBOD
| RMU_RSTCAUSE_DVDDBOD
| RMU_RSTCAUSE_AVDDBOD);
| RMU_RSTCAUSE_DVDDBOD
| RMU_RSTCAUSE_AVDDBOD);
}
#endif
return validRstCause;
}
/** @} (end addtogroup RMU) */
/** @} (end addtogroup emlib) */
#endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */

72
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_rtc.c
* @brief Real Time Counter (RTC) Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -61,7 +61,6 @@
/** @endcond */
/*******************************************************************************
************************** LOCAL FUNCTIONS ********************************
******************************************************************************/
@ -88,8 +87,9 @@ __STATIC_INLINE void regSync(uint32_t mask)
{
/* Avoid deadlock if modifying the same register twice when freeze mode is */
/* activated. */
if (RTC->FREEZE & RTC_FREEZE_REGFREEZE)
if (RTC->FREEZE & RTC_FREEZE_REGFREEZE) {
return;
}
/* Wait for any pending previous write operation to have been completed */
/* in low frequency domain. This is only required for the Gecko Family */
@ -120,9 +120,11 @@ uint32_t RTC_CompareGet(unsigned int comp)
EFM_ASSERT(RTC_COMP_REG_VALID(comp));
#if defined(_RTC_COMP_COMP_MASK)
ret = RTC->COMP[comp].COMP;
#elif defined(_RTC_COMP0_MASK)
/* Initialize selected compare value */
switch (comp)
{
switch (comp) {
case 0:
ret = RTC->COMP0;
break;
@ -136,11 +138,10 @@ uint32_t RTC_CompareGet(unsigned int comp)
ret = 0;
break;
}
#endif
return ret;
}
/***************************************************************************//**
* @brief
* Set RTC compare register value.
@ -165,13 +166,19 @@ void RTC_CompareSet(unsigned int comp, uint32_t value)
uint32_t syncbusy;
#endif
EFM_ASSERT(RTC_COMP_REG_VALID(comp)
&& ((value & ~(_RTC_COMP0_COMP0_MASK
>> _RTC_COMP0_COMP0_SHIFT)) == 0));
EFM_ASSERT(RTC_COMP_REG_VALID(comp));
#if defined(_RTC_COMP_COMP_COMP_MASK)
EFM_ASSERT((value & ~(_RTC_COMP_COMP_COMP_MASK >> _RTC_COMP_COMP_COMP_SHIFT)) == 0);
#elif defined(_RTC_COMP0_COMP0_MASK)
EFM_ASSERT((value & ~(_RTC_COMP0_COMP0_MASK >> _RTC_COMP0_COMP0_SHIFT)) == 0);
#endif
#if defined(_RTC_COMP_COMP_MASK)
compReg = &(RTC->COMP[comp].COMP);
#elif defined(_RTC_COMP0_MASK)
/* Initialize selected compare value */
switch (comp)
{
switch (comp) {
case 0:
compReg = &(RTC->COMP0);
#if defined(_EFM32_GECKO_FAMILY)
@ -190,6 +197,8 @@ void RTC_CompareSet(unsigned int comp, uint32_t value)
/* Unknown compare register selected, abort */
return;
}
#endif
#if defined(_EFM32_GECKO_FAMILY)
/* LF register about to be modified require sync. busy check */
regSync(syncbusy);
@ -198,7 +207,6 @@ void RTC_CompareSet(unsigned int comp, uint32_t value)
*compReg = value;
}
/***************************************************************************//**
* @brief
* Enable/disable RTC.
@ -231,7 +239,7 @@ void RTC_Enable(bool enable)
#endif
}
#if defined(_RTC_FREEZE_MASK)
/***************************************************************************//**
* @brief
* RTC register synchronization freeze control.
@ -260,8 +268,7 @@ void RTC_Enable(bool enable)
******************************************************************************/
void RTC_FreezeEnable(bool enable)
{
if (enable)
{
if (enable) {
#if defined(_EFM32_GECKO_FAMILY)
/* Wait for any ongoing LF synchronization to complete. This is just to */
/* protect against the rare case when a user */
@ -274,13 +281,11 @@ void RTC_FreezeEnable(bool enable)
;
#endif
RTC->FREEZE = RTC_FREEZE_REGFREEZE;
}
else
{
} else {
RTC->FREEZE = 0;
}
}
#endif
/***************************************************************************//**
* @brief
@ -306,26 +311,21 @@ void RTC_Init(const RTC_Init_TypeDef *init)
{
uint32_t tmp;
if (init->enable)
{
if (init->enable) {
tmp = RTC_CTRL_EN;
}
else
{
} else {
tmp = 0;
}
/* Configure DEBUGRUN flag, sets whether or not counter should be
* updated when debugger is active */
if (init->debugRun)
{
if (init->debugRun) {
tmp |= RTC_CTRL_DEBUGRUN;
}
/* Configure COMP0TOP, this will use the COMP0 compare value as an
* overflow value, instead of default 24-bit 0x00ffffff */
if (init->comp0Top)
{
if (init->comp0Top) {
tmp |= RTC_CTRL_COMP0TOP;
}
@ -337,8 +337,6 @@ void RTC_Init(const RTC_Init_TypeDef *init)
RTC->CTRL = tmp;
}
/***************************************************************************//**
* @brief
* Restore RTC to reset state
@ -346,10 +344,17 @@ void RTC_Init(const RTC_Init_TypeDef *init)
void RTC_Reset(void)
{
/* Restore all essential RTC register to default config */
#if defined(_RTC_FREEZE_MASK)
RTC->FREEZE = _RTC_FREEZE_RESETVALUE;
#endif
RTC->CTRL = _RTC_CTRL_RESETVALUE;
#if defined(_RTC_COMP_COMP_MASK)
RTC->COMP[0].COMP = _RTC_COMP_COMP_RESETVALUE;
RTC->COMP[1].COMP = _RTC_COMP_COMP_RESETVALUE;
#elif defined(_RTC_COMP0_MASK)
RTC->COMP0 = _RTC_COMP0_RESETVALUE;
RTC->COMP1 = _RTC_COMP1_RESETVALUE;
#endif
RTC->IEN = _RTC_IEN_RESETVALUE;
RTC->IFC = _RTC_IFC_RESETVALUE;
@ -361,8 +366,6 @@ void RTC_Reset(void)
#endif
}
/***************************************************************************//**
* @brief
* Restart RTC counter from zero
@ -374,7 +377,6 @@ void RTC_CounterReset(void)
RTC_Enable(true);
}
/** @} (end addtogroup RTC) */
/** @} (end addtogroup emlib) */
#endif /* defined(RTC_COUNT) && (RTC_COUNT > 0) */

62
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtcc.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file
* @brief Real Time Counter with Calendar (RTCC) Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -31,7 +31,7 @@
******************************************************************************/
#include "em_rtcc.h"
#if defined( RTCC_COUNT ) && ( RTCC_COUNT == 1 )
#if defined(RTCC_COUNT) && (RTCC_COUNT == 1)
#include "em_bus.h"
/***************************************************************************//**
@ -78,21 +78,21 @@
* @param[in] confPtr
* Pointer to configuration structure.
******************************************************************************/
void RTCC_ChannelInit( int ch, RTCC_CCChConf_TypeDef const *confPtr )
void RTCC_ChannelInit(int ch, RTCC_CCChConf_TypeDef const *confPtr)
{
EFM_ASSERT( RTCC_CH_VALID( ch ) );
EFM_ASSERT(RTCC_CH_VALID(ch) );
EFM_ASSERT( (uint32_t)confPtr->compMask
< ( _RTCC_CC_CTRL_COMPMASK_MASK >> _RTCC_CC_CTRL_COMPMASK_SHIFT )
+ 1 );
< (_RTCC_CC_CTRL_COMPMASK_MASK >> _RTCC_CC_CTRL_COMPMASK_SHIFT)
+ 1);
/** Configure the selected capture/compare channel. */
RTCC->CC[ch].CTRL = ( (uint32_t)confPtr->chMode << _RTCC_CC_CTRL_MODE_SHIFT )
| ( (uint32_t)confPtr->compMatchOutAction << _RTCC_CC_CTRL_CMOA_SHIFT )
| ( (uint32_t)confPtr->prsSel << _RTCC_CC_CTRL_PRSSEL_SHIFT )
| ( (uint32_t)confPtr->inputEdgeSel << _RTCC_CC_CTRL_ICEDGE_SHIFT )
| ( (uint32_t)confPtr->compBase << _RTCC_CC_CTRL_COMPBASE_SHIFT )
| ( (uint32_t)confPtr->compMask << _RTCC_CC_CTRL_COMPMASK_SHIFT )
| ( (uint32_t)confPtr->dayCompMode << _RTCC_CC_CTRL_DAYCC_SHIFT );
RTCC->CC[ch].CTRL = ( (uint32_t)confPtr->chMode << _RTCC_CC_CTRL_MODE_SHIFT)
| ( (uint32_t)confPtr->compMatchOutAction << _RTCC_CC_CTRL_CMOA_SHIFT)
| ( (uint32_t)confPtr->prsSel << _RTCC_CC_CTRL_PRSSEL_SHIFT)
| ( (uint32_t)confPtr->inputEdgeSel << _RTCC_CC_CTRL_ICEDGE_SHIFT)
| ( (uint32_t)confPtr->compBase << _RTCC_CC_CTRL_COMPBASE_SHIFT)
| ( (uint32_t)confPtr->compMask << _RTCC_CC_CTRL_COMPMASK_SHIFT)
| ( (uint32_t)confPtr->dayCompMode << _RTCC_CC_CTRL_DAYCC_SHIFT);
}
/***************************************************************************//**
@ -102,7 +102,7 @@ void RTCC_ChannelInit( int ch, RTCC_CCChConf_TypeDef const *confPtr )
* @param[in] enable
* True to enable RTCC, false to disable.
******************************************************************************/
void RTCC_Enable( bool enable )
void RTCC_Enable(bool enable)
{
/* Bitbanding the enable bit in the CTRL register (atomic). */
BUS_RegBitWrite((&RTCC->CTRL), _RTCC_CTRL_ENABLE_SHIFT, enable);
@ -120,27 +120,27 @@ void RTCC_Enable( bool enable )
* @param[in] init
* Pointer to RTCC initialization structure.
******************************************************************************/
void RTCC_Init( const RTCC_Init_TypeDef *init )
void RTCC_Init(const RTCC_Init_TypeDef *init)
{
RTCC->CTRL = ( (uint32_t)init->enable << _RTCC_CTRL_ENABLE_SHIFT )
| ( (uint32_t)init->debugRun << _RTCC_CTRL_DEBUGRUN_SHIFT )
| ( (uint32_t)init->precntWrapOnCCV0 << _RTCC_CTRL_PRECCV0TOP_SHIFT )
| ( (uint32_t)init->cntWrapOnCCV1 << _RTCC_CTRL_CCV1TOP_SHIFT )
| ( (uint32_t)init->presc << _RTCC_CTRL_CNTPRESC_SHIFT )
| ( (uint32_t)init->prescMode << _RTCC_CTRL_CNTTICK_SHIFT )
RTCC->CTRL = ( (uint32_t)init->enable << _RTCC_CTRL_ENABLE_SHIFT)
| ( (uint32_t)init->debugRun << _RTCC_CTRL_DEBUGRUN_SHIFT)
| ( (uint32_t)init->precntWrapOnCCV0 << _RTCC_CTRL_PRECCV0TOP_SHIFT)
| ( (uint32_t)init->cntWrapOnCCV1 << _RTCC_CTRL_CCV1TOP_SHIFT)
| ( (uint32_t)init->presc << _RTCC_CTRL_CNTPRESC_SHIFT)
| ( (uint32_t)init->prescMode << _RTCC_CTRL_CNTTICK_SHIFT)
#if defined(_RTCC_CTRL_BUMODETSEN_MASK)
| ( (uint32_t)init->enaBackupModeSet << _RTCC_CTRL_BUMODETSEN_SHIFT )
| ( (uint32_t)init->enaBackupModeSet << _RTCC_CTRL_BUMODETSEN_SHIFT)
#endif
| ( (uint32_t)init->enaOSCFailDetect << _RTCC_CTRL_OSCFDETEN_SHIFT )
| ( (uint32_t)init->cntMode << _RTCC_CTRL_CNTMODE_SHIFT )
| ( (uint32_t)init->disLeapYearCorr << _RTCC_CTRL_LYEARCORRDIS_SHIFT );
| ( (uint32_t)init->enaOSCFailDetect << _RTCC_CTRL_OSCFDETEN_SHIFT)
| ( (uint32_t)init->cntMode << _RTCC_CTRL_CNTMODE_SHIFT)
| ( (uint32_t)init->disLeapYearCorr << _RTCC_CTRL_LYEARCORRDIS_SHIFT);
}
/***************************************************************************//**
* @brief
* Restore RTCC to its reset state.
******************************************************************************/
void RTCC_Reset( void )
void RTCC_Reset(void)
{
int i;
@ -156,8 +156,7 @@ void RTCC_Reset( void )
RTCC_StatusClear();
RTCC->EM4WUEN = _RTCC_EM4WUEN_RESETVALUE;
for (i = 0; i < 3; i++)
{
for (i = 0; i < 3; i++) {
RTCC->CC[i].CTRL = _RTCC_CC_CTRL_RESETVALUE;
RTCC->CC[i].CCV = _RTCC_CC_CCV_RESETVALUE;
RTCC->CC[i].TIME = _RTCC_CC_TIME_RESETVALUE;
@ -169,10 +168,9 @@ void RTCC_Reset( void )
* @brief
* Clear STATUS register.
******************************************************************************/
void RTCC_StatusClear( void )
void RTCC_StatusClear(void)
{
while ( RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD )
{
while ( RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD ) {
// Wait for syncronization.
}
RTCC->CMD = RTCC_CMD_CLRSTATUS;

24
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_system.c
* @brief System Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -61,10 +61,10 @@ void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev)
uint8_t tmp;
EFM_ASSERT(rev);
uint32_t pid0 = SECURE_READ(&(ROMTABLE->PID0));
uint32_t pid1 = SECURE_READ(&(ROMTABLE->PID1));
uint32_t pid2 = SECURE_READ(&(ROMTABLE->PID2));
uint32_t pid0 = SECURE_READ(&(ROMTABLE->PID0));
uint32_t pid1 = SECURE_READ(&(ROMTABLE->PID1));
uint32_t pid2 = SECURE_READ(&(ROMTABLE->PID2));
uint32_t pid3 = SECURE_READ(&(ROMTABLE->PID3));
/* CHIP FAMILY bit [5:2] */
@ -83,7 +83,6 @@ void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev)
rev->minor = tmp;
}
/***************************************************************************//**
* @brief
* Get factory calibration value for a given peripheral register.
@ -103,15 +102,8 @@ bool SYSTEM_GetCalibrationValue(volatile uint32_t *regAddress)
p = (SYSTEM_CalAddrVal_TypeDef *)(DEVINFO_BASE & 0xFFFFF000);
end = (SYSTEM_CalAddrVal_TypeDef *)DEVINFO_BASE;
for ( ; p < end; p++)
{
if (p->address == 0xFFFFFFFF)
{
/* Found table terminator */
return false;
}
if (p->address == (uint32_t)regAddress)
{
for (; p < end; p++) {
if (p->address == (uint32_t)regAddress) {
*regAddress = p->calValue;
return true;
}

22
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_timer.c
* @brief Timer/counter (TIMER) Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -51,7 +51,6 @@
* @{
******************************************************************************/
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
@ -78,8 +77,7 @@ void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init)
EFM_ASSERT(TIMER_REF_VALID(timer));
/* Stop timer if specified to be disabled (dosn't hurt if already stopped) */
if (!(init->enable))
{
if (!(init->enable)) {
timer->CMD = TIMER_CMD_STOP;
}
@ -103,13 +101,11 @@ void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init)
| (init->sync ? TIMER_CTRL_SYNC : 0);
/* Start timer if specified to be enabled (dosn't hurt if already started) */
if (init->enable)
{
if (init->enable) {
timer->CMD = TIMER_CMD_START;
}
}
/***************************************************************************//**
* @brief
* Initialize TIMER compare/capture channel.
@ -148,7 +144,6 @@ void TIMER_InitCC(TIMER_TypeDef *timer,
| (init->outInvert ? TIMER_CC_CTRL_OUTINV : 0);
}
#if defined(_TIMER_DTCTRL_MASK)
/***************************************************************************//**
* @brief
@ -165,7 +160,7 @@ void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init)
EFM_ASSERT(TIMER0 == timer);
/* Make sure the DTI unit is disabled while initializing. */
TIMER_EnableDTI (timer, false);
TIMER_EnableDTI(timer, false);
/* Setup the DTCTRL register.
The enable bit will be set at the end of the function if specified. */
@ -199,11 +194,10 @@ void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init)
TIMER_ClearDTIFault(timer, TIMER_GetDTIFault(timer));
/* Enable/disable before returning. */
TIMER_EnableDTI (timer, init->enable);
TIMER_EnableDTI(timer, init->enable);
}
#endif
/***************************************************************************//**
* @brief
* Reset TIMER to same state as after a HW reset.
@ -234,8 +228,7 @@ void TIMER_Reset(TIMER_TypeDef *timer)
/* Do not reset route register, setting should be done independently */
/* (Note: ROUTE register may be locked by DTLOCK register.) */
for (i = 0; TIMER_CH_VALID(i); i++)
{
for (i = 0; TIMER_CH_VALID(i); i++) {
timer->CC[i].CTRL = _TIMER_CC_CTRL_RESETVALUE;
timer->CC[i].CCV = _TIMER_CC_CCV_RESETVALUE;
timer->CC[i].CCVB = _TIMER_CC_CCVB_RESETVALUE;
@ -255,7 +248,6 @@ void TIMER_Reset(TIMER_TypeDef *timer)
#endif
}
/** @} (end addtogroup TIMER) */
/** @} (end addtogroup emlib) */
#endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */

217
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c
View File

@ -2,9 +2,9 @@
* @file em_usart.c
* @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART)
* Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -54,7 +54,6 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** Validation of USART register block pointer reference for assert statements. */
#if (USART_COUNT == 1) && defined(USART0)
#define USART_REF_VALID(ref) ((ref) == USART0)
@ -69,19 +68,19 @@
#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1))
#elif (USART_COUNT == 3)
#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || \
((ref) == USART2))
#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \
|| ((ref) == USART2))
#elif (USART_COUNT == 4)
#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || \
((ref) == USART2) || ((ref) == USART3))
#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \
|| ((ref) == USART2) || ((ref) == USART3))
#elif (USART_COUNT == 5)
#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || \
((ref) == USART2) || ((ref) == USART3) || \
((ref) == USART4))
#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \
|| ((ref) == USART2) || ((ref) == USART3) \
|| ((ref) == USART4))
#elif (USART_COUNT == 6)
#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || \
((ref) == USART2) || ((ref) == USART3) || \
((ref) == USART4) || ((ref) == USART5))
#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \
|| ((ref) == USART2) || ((ref) == USART3) \
|| ((ref) == USART4) || ((ref) == USART5))
#else
#error "Undefined number of USARTs."
#endif
@ -98,6 +97,18 @@
#define USARTRF_REF_VALID(ref) (0)
#endif
#if defined(_SILICON_LABS_32B_SERIES_1)
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
// If GG11 or TG11
#define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART2))
#elif defined(USART3)
#define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || ((ref) == USART2) || ((ref) == USART3))
#elif defined(USART2)
#define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || ((ref) == USART2))
#else
#define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1))
#endif
#elif defined(_SILICON_LABS_32B_SERIES_0)
#if defined(_EZR32_HAPPY_FAMILY)
#define USART_IRDA_VALID(ref) ((ref) == USART0)
#elif defined(_EFM32_HAPPY_FAMILY)
@ -106,21 +117,30 @@
#define USART_IRDA_VALID(ref) ((ref) == USART0)
#elif (USART_COUNT == 1) && defined(USART1)
#define USART_IRDA_VALID(ref) ((ref) == USART1)
#elif defined(USARTRF0)
#define USART_IRDA_VALID(ref) ((ref) == USARTRF0)
#else
#define USART_IRDA_VALID(ref) (0)
#endif
#endif
#if defined(_SILICON_LABS_32B_SERIES_1)
#define USART_I2S_VALID(ref) ((ref) == USART1)
#if defined(USART4)
#define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART3) || ((ref) == USART4))
#elif defined(USART3)
#define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART3))
#else
#define USART_I2S_VALID(ref) ((ref) == USART1)
#endif
#elif defined(_SILICON_LABS_32B_SERIES_0)
#if defined(_EZR32_HAPPY_FAMILY)
#define USART_I2S_VALID(ref) ((ref) == USART0)
#elif defined(_EFM32_HAPPY_FAMILY)
#define USART_I2S_VALID(ref) (((ref) == USART0) || ((ref) == USART1))
#elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY)
#define USART_I2S_VALID(ref) ((ref) == USART1)
#elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART2))
#if defined(_EZR32_HAPPY_FAMILY)
#define USART_I2S_VALID(ref) ((ref) == USART0)
#elif defined(_EFM32_HAPPY_FAMILY)
#define USART_I2S_VALID(ref) (((ref) == USART0) || ((ref) == USART1))
#elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY)
#define USART_I2S_VALID(ref) ((ref) == USART1)
#elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART2))
#endif
#endif
@ -132,8 +152,13 @@
#define UART_REF_VALID(ref) (0)
#endif
/** @endcond */
#if defined(_USART_CLKDIV_DIVEXT_MASK)
#define CLKDIV_MASK (_USART_CLKDIV_DIV_MASK | _USART_CLKDIV_DIVEXT_MASK)
#else
#define CLKDIV_MASK _USART_CLKDIV_DIV_MASK
#endif
/** @endcond */
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
@ -201,14 +226,12 @@ void USART_BaudrateAsyncSet(USART_TypeDef *usart,
*/
/* HFPERCLK used to clock all USART/UART peripheral modules */
if (!refFreq)
{
if (!refFreq) {
refFreq = CMU_ClockFreqGet(cmuClock_HFPER);
}
/* Map oversampling */
switch (ovs)
{
switch (ovs) {
case usartOVS16:
EFM_ASSERT(baudrate <= (refFreq / 16));
oversample = 16;
@ -236,34 +259,33 @@ void USART_BaudrateAsyncSet(USART_TypeDef *usart,
}
/* Calculate and set CLKDIV with fractional bits.
* The addend (oversample*baudrate)/2 in the first line is to round the
* divisor up by half the divisor before the division in order to reduce the
* integer division error, which consequently results in a higher baudrate
* than desired. */
#if defined(_USART_CLKDIV_DIV_MASK) && (_USART_CLKDIV_DIV_MASK >= 0x7FFFF8UL)
clkdiv = 32 * refFreq + (oversample * baudrate) / 2;
clkdiv /= (oversample * baudrate);
clkdiv -= 32;
clkdiv *= 8;
#else
* The added (oversample*baudrate)/2 in the first line is to round the
* divisor to the nearest fractional divisor. */
#if defined(_SILICON_LABS_32B_SERIES_0) && !defined(_EFM32_HAPPY_FAMILY)
/* Devices with 2 fractional bits. CLKDIV[7:6] */
clkdiv = 4 * refFreq + (oversample * baudrate) / 2;
clkdiv /= (oversample * baudrate);
clkdiv -= 4;
clkdiv *= 64;
#else
/* Devices with 5 fractional bits. CLKDIV[7:3] */
clkdiv = 32 * refFreq + (oversample * baudrate) / 2;
clkdiv /= (oversample * baudrate);
clkdiv -= 32;
clkdiv *= 8;
#endif
/* Verify that resulting clock divider is within limits */
EFM_ASSERT(clkdiv <= _USART_CLKDIV_DIV_MASK);
EFM_ASSERT(clkdiv <= CLKDIV_MASK);
/* If EFM_ASSERT is not enabled, make sure we don't write to reserved bits */
clkdiv &= _USART_CLKDIV_DIV_MASK;
/* Make sure we don't write to reserved bits */
clkdiv &= CLKDIV_MASK;
usart->CTRL &= ~_USART_CTRL_OVS_MASK;
usart->CTRL |= ovs;
usart->CLKDIV = clkdiv;
}
/***************************************************************************//**
* @brief
* Calculate baudrate for USART/UART given reference frequency, clock division
@ -305,17 +327,16 @@ uint32_t USART_BaudrateCalc(uint32_t refFreq,
uint32_t br;
/* Out of bound clkdiv ? */
EFM_ASSERT(clkdiv <= _USART_CLKDIV_DIV_MASK);
EFM_ASSERT(clkdiv <= CLKDIV_MASK);
/* Mask out unused bits */
clkdiv &= _USART_CLKDIV_DIV_MASK;
clkdiv &= CLKDIV_MASK;
/* We want to use integer division to avoid forcing in float division */
/* utils, and yet keep rounding effect errors to a minimum. */
/* Baudrate calculation depends on if synchronous or asynchronous mode */
if (syncmode)
{
if (syncmode) {
/*
* Baudrate is given by:
*
@ -327,9 +348,7 @@ uint32_t USART_BaudrateCalc(uint32_t refFreq,
*/
oversample = 1; /* Not used in sync mode, ie 1 */
factor = 128;
}
else
{
} else {
/*
* Baudrate in asynchronous mode is given by:
*
@ -343,8 +362,7 @@ uint32_t USART_BaudrateCalc(uint32_t refFreq,
* (part of) oversample part of the divisor.
*/
switch (ovs)
{
switch (ovs) {
case usartOVS16:
oversample = 1;
factor = 256 / 16;
@ -413,7 +431,6 @@ uint32_t USART_BaudrateCalc(uint32_t refFreq,
return br;
}
/***************************************************************************//**
* @brief
* Get current baudrate for USART/UART.
@ -434,12 +451,9 @@ uint32_t USART_BaudrateGet(USART_TypeDef *usart)
USART_OVS_TypeDef ovs;
bool syncmode;
if (usart->CTRL & USART_CTRL_SYNC)
{
if (usart->CTRL & USART_CTRL_SYNC) {
syncmode = true;
}
else
{
} else {
syncmode = false;
}
@ -449,7 +463,6 @@ uint32_t USART_BaudrateGet(USART_TypeDef *usart)
return USART_BaudrateCalc(freq, usart->CLKDIV, syncmode, ovs);
}
/***************************************************************************//**
* @brief
* Configure USART operating in synchronous mode to use a given baudrate
@ -491,8 +504,7 @@ void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baud
*/
/* HFPERCLK used to clock all USART/UART peripheral modules */
if (!refFreq)
{
if (!refFreq) {
refFreq = CMU_ClockFreqGet(cmuClock_HFPER);
}
@ -500,15 +512,11 @@ void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baud
clkdiv = clkdiv << 8;
/* Verify that resulting clock divider is within limits */
EFM_ASSERT(!(clkdiv & ~_USART_CLKDIV_DIV_MASK));
EFM_ASSERT(!(clkdiv & ~CLKDIV_MASK));
/* If EFM_ASSERT is not enabled, make sure we don't write to reserved bits */
clkdiv &= _USART_CLKDIV_DIV_MASK;
BUS_RegMaskedWrite(&usart->CLKDIV, _USART_CLKDIV_DIV_MASK, clkdiv);
usart->CLKDIV = clkdiv;
}
/***************************************************************************//**
* @brief
* Enable/disable USART/UART receiver and/or transmitter.
@ -529,9 +537,9 @@ void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable)
uint32_t tmp;
/* Make sure the module exists on the selected chip */
EFM_ASSERT( USART_REF_VALID(usart)
|| USARTRF_REF_VALID(usart)
|| UART_REF_VALID(usart) );
EFM_ASSERT(USART_REF_VALID(usart)
|| USARTRF_REF_VALID(usart)
|| UART_REF_VALID(usart) );
/* Disable as specified */
tmp = ~((uint32_t) (enable));
@ -542,7 +550,6 @@ void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable)
usart->CMD = (uint32_t) (enable);
}
/***************************************************************************//**
* @brief
* Init USART/UART for normal asynchronous mode.
@ -569,23 +576,21 @@ void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable)
void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init)
{
/* Make sure the module exists on the selected chip */
EFM_ASSERT( USART_REF_VALID(usart)
|| USARTRF_REF_VALID(usart)
|| UART_REF_VALID(usart) );
EFM_ASSERT(USART_REF_VALID(usart)
|| USARTRF_REF_VALID(usart)
|| UART_REF_VALID(usart) );
/* Init USART registers to HW reset state. */
USART_Reset(usart);
#if defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
/* Disable majority vote if specified. */
if (init->mvdis)
{
if (init->mvdis) {
usart->CTRL |= USART_CTRL_MVDIS;
}
/* Configure PRS input mode. */
if (init->prsRxEnable)
{
if (init->prsRxEnable) {
usart->INPUT = (uint32_t) init->prsRxCh | USART_INPUT_RXPRS;
}
#endif
@ -603,16 +608,20 @@ void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init)
& _USART_TIMING_CSHOLD_MASK)
| ((init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT)
& _USART_TIMING_CSSETUP_MASK);
if (init->autoCsEnable)
{
if (init->autoCsEnable) {
usart->CTRL |= USART_CTRL_AUTOCS;
}
#endif
#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
usart->ROUTEPEN &= ~(_USART_ROUTEPEN_RTSPEN_MASK | _USART_ROUTEPEN_CTSPEN_MASK);
usart->ROUTEPEN |= init->hwFlowControl;
#endif
/* Finally enable (as specified) */
usart->CMD = (uint32_t)init->enable;
}
/***************************************************************************//**
* @brief
* Init USART for synchronous mode.
@ -640,7 +649,7 @@ void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init)
void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init)
{
/* Make sure the module exists on the selected chip */
EFM_ASSERT( USART_REF_VALID(usart) || USARTRF_REF_VALID(usart) );
EFM_ASSERT(USART_REF_VALID(usart) || USARTRF_REF_VALID(usart) );
/* Init USART registers to HW reset state. */
USART_Reset(usart);
@ -656,8 +665,7 @@ void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init)
#if defined(_USART_INPUT_RXPRS_MASK)
/* Configure PRS input mode. */
if (init->prsRxEnable)
{
if (init->prsRxEnable) {
usart->INPUT = (uint32_t)init->prsRxCh | USART_INPUT_RXPRS;
}
#endif
@ -671,8 +679,7 @@ void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init)
USART_BaudrateSyncSet(usart, init->refFreq, init->baudrate);
/* Finally enable (as specified) */
if (init->master)
{
if (init->master) {
usart->CMD = USART_CMD_MASTEREN;
}
@ -681,8 +688,7 @@ void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init)
& _USART_TIMING_CSHOLD_MASK)
| ((init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT)
& _USART_TIMING_CSSETUP_MASK);
if (init->autoCsEnable)
{
if (init->autoCsEnable) {
usart->CTRL |= USART_CTRL_AUTOCS;
}
#endif
@ -729,8 +735,7 @@ void USARTn_InitIrDA(USART_TypeDef *usart, const USART_InitIrDA_TypeDef *init)
usart->CTRL |= USART_CTRL_TXINV;
/* Invert Rx signal before demodulator if enabled */
if (init->irRxInv)
{
if (init->irRxInv) {
usart->CTRL |= USART_CTRL_RXINV;
}
@ -796,14 +801,12 @@ void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init)
| (init->mono ? USART_I2SCTRL_MONO : 0)
| USART_I2SCTRL_EN;
if (enable != usartDisable)
{
if (enable != usartDisable) {
USART_Enable(usart, enable);
}
}
#endif
/***************************************************************************//**
* @brief
* Initialize automatic transmissions using PRS channel as trigger
@ -826,17 +829,14 @@ void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeD
| _USART_TRIGCTRL_TSEL_MASK);
#if defined(USART_TRIGCTRL_AUTOTXTEN)
if (init->autoTxTriggerEnable)
{
if (init->autoTxTriggerEnable) {
trigctrl |= USART_TRIGCTRL_AUTOTXTEN;
}
#endif
if (init->txTriggerEnable)
{
if (init->txTriggerEnable) {
trigctrl |= USART_TRIGCTRL_TXTEN;
}
if (init->rxTriggerEnable)
{
if (init->rxTriggerEnable) {
trigctrl |= USART_TRIGCTRL_RXTEN;
}
trigctrl |= init->prsTriggerChannel;
@ -845,7 +845,6 @@ void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeD
usart->TRIGCTRL = trigctrl;
}
/***************************************************************************//**
* @brief
* Reset USART/UART to same state as after a HW reset.
@ -856,9 +855,9 @@ void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeD
void USART_Reset(USART_TypeDef *usart)
{
/* Make sure the module exists on the selected chip */
EFM_ASSERT( USART_REF_VALID(usart)
|| USARTRF_REF_VALID(usart)
|| UART_REF_VALID(usart) );
EFM_ASSERT(USART_REF_VALID(usart)
|| USARTRF_REF_VALID(usart)
|| UART_REF_VALID(usart) );
/* Make sure disabled first, before resetting other registers */
usart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS
@ -878,8 +877,7 @@ void USART_Reset(USART_TypeDef *usart)
usart->ROUTE = _USART_ROUTE_RESETVALUE;
#endif
if (USART_IRDA_VALID(usart))
{
if (USART_IRDA_VALID(usart)) {
usart->IRCTRL = _USART_IRCTRL_RESETVALUE;
}
@ -888,14 +886,12 @@ void USART_Reset(USART_TypeDef *usart)
#endif
#if defined(_USART_I2SCTRL_RESETVALUE)
if (USART_I2S_VALID(usart))
{
if (USART_I2S_VALID(usart)) {
usart->I2SCTRL = _USART_I2SCTRL_RESETVALUE;
}
#endif
}
/***************************************************************************//**
* @brief
* Receive one 4-8 bit frame, (or part of 10-16 bit frame).
@ -928,7 +924,6 @@ uint8_t USART_Rx(USART_TypeDef *usart)
return (uint8_t)usart->RXDATA;
}
/***************************************************************************//**
* @brief
* Receive two 4-8 bit frames, or one 10-16 bit frame.
@ -961,7 +956,6 @@ uint16_t USART_RxDouble(USART_TypeDef *usart)
return (uint16_t)usart->RXDOUBLE;
}
/***************************************************************************//**
* @brief
* Receive two 4-9 bit frames, or one 10-16 bit frame with extended
@ -994,7 +988,6 @@ uint32_t USART_RxDoubleExt(USART_TypeDef *usart)
return usart->RXDOUBLEX;
}
/***************************************************************************//**
* @brief
* Receive one 4-9 bit frame, (or part of 10-16 bit frame) with extended
@ -1027,7 +1020,6 @@ uint16_t USART_RxExt(USART_TypeDef *usart)
return (uint16_t)usart->RXDATAX;
}
/***************************************************************************//**
* @brief
* Perform one 8 bit frame SPI transfer.
@ -1057,7 +1049,6 @@ uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data)
return (uint8_t)usart->RXDATA;
}
/***************************************************************************//**
* @brief
* Transmit one 4-9 bit frame.
@ -1089,7 +1080,6 @@ void USART_Tx(USART_TypeDef *usart, uint8_t data)
usart->TXDATA = (uint32_t)data;
}
/***************************************************************************//**
* @brief
* Transmit two 4-9 bit frames, or one 10-16 bit frame.
@ -1125,7 +1115,6 @@ void USART_TxDouble(USART_TypeDef *usart, uint16_t data)
usart->TXDOUBLE = (uint32_t)data;
}
/***************************************************************************//**
* @brief
* Transmit two 4-9 bit frames, or one 10-16 bit frame with extended control.
@ -1161,7 +1150,6 @@ void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data)
usart->TXDOUBLEX = data;
}
/***************************************************************************//**
* @brief
* Transmit one 4-9 bit frame with extended control.
@ -1189,7 +1177,6 @@ void USART_TxExt(USART_TypeDef *usart, uint16_t data)
usart->TXDATAX = (uint32_t)data;
}
/** @} (end addtogroup USART) */
/** @} (end addtogroup emlib) */
#endif /* defined(USART_COUNT) && (USART_COUNT > 0) */

50
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_vcmp.c
* @brief Voltage Comparator (VCMP) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -64,12 +64,9 @@ void VCMP_Init(const VCMP_Init_TypeDef *vcmpInit)
EFM_ASSERT((vcmpInit->biasProg >= 0) && (vcmpInit->biasProg < 16));
/* Configure Half Bias setting */
if (vcmpInit->halfBias)
{
if (vcmpInit->halfBias) {
VCMP->CTRL |= VCMP_CTRL_HALFBIAS;
}
else
{
} else {
VCMP->CTRL &= ~(VCMP_CTRL_HALFBIAS);
}
@ -78,22 +75,16 @@ void VCMP_Init(const VCMP_Init_TypeDef *vcmpInit)
VCMP->CTRL |= (vcmpInit->biasProg << _VCMP_CTRL_BIASPROG_SHIFT);
/* Configure sense for falling edge */
if (vcmpInit->irqFalling)
{
if (vcmpInit->irqFalling) {
VCMP->CTRL |= VCMP_CTRL_IFALL;
}
else
{
} else {
VCMP->CTRL &= ~(VCMP_CTRL_IFALL);
}
/* Configure sense for rising edge */
if (vcmpInit->irqRising)
{
if (vcmpInit->irqRising) {
VCMP->CTRL |= VCMP_CTRL_IRISE;
}
else
{
} else {
VCMP->CTRL &= ~(VCMP_CTRL_IRISE);
}
@ -102,8 +93,7 @@ void VCMP_Init(const VCMP_Init_TypeDef *vcmpInit)
VCMP->CTRL |= (vcmpInit->warmup << _VCMP_CTRL_WARMTIME_SHIFT);
/* Configure hysteresis */
switch (vcmpInit->hyst)
{
switch (vcmpInit->hyst) {
case vcmpHyst20mV:
VCMP->CTRL |= VCMP_CTRL_HYSTEN;
break;
@ -121,22 +111,18 @@ void VCMP_Init(const VCMP_Init_TypeDef *vcmpInit)
VCMP_TriggerSet(vcmpInit->triggerLevel);
/* Enable or disable VCMP */
if (vcmpInit->enable)
{
if (vcmpInit->enable) {
VCMP->CTRL |= VCMP_CTRL_EN;
}
else
{
} else {
VCMP->CTRL &= ~(VCMP_CTRL_EN);
}
/* If Low Power Reference is enabled, wait until VCMP is ready */
/* before enabling it, see reference manual for deatils */
/* Configuring Low Power Ref without enable has no effect */
if(vcmpInit->lowPowerRef && vcmpInit->enable)
{
if (vcmpInit->lowPowerRef && vcmpInit->enable) {
/* Poll for VCMP ready */
while(!VCMP_Ready());
while (!VCMP_Ready()) ;
VCMP_LowPowerRefSet(vcmpInit->lowPowerRef);
}
@ -144,7 +130,6 @@ void VCMP_Init(const VCMP_Init_TypeDef *vcmpInit)
VCMP_IntClear(VCMP_IF_EDGE);
}
/***************************************************************************//**
* @brief
* Enable or disable Low Power Reference setting
@ -154,17 +139,13 @@ void VCMP_Init(const VCMP_Init_TypeDef *vcmpInit)
******************************************************************************/
void VCMP_LowPowerRefSet(bool enable)
{
if (enable)
{
if (enable) {
VCMP->INPUTSEL |= VCMP_INPUTSEL_LPREF;
}
else
{
} else {
VCMP->INPUTSEL &= ~VCMP_INPUTSEL_LPREF;
}
}
/***************************************************************************//**
* @brief
* Configure trigger level of voltage comparator
@ -182,7 +163,6 @@ void VCMP_TriggerSet(int level)
| (level << _VCMP_INPUTSEL_TRIGLEVEL_SHIFT);
}
/** @} (end addtogroup VCMP) */
/** @} (end addtogroup emlib) */
#endif /* defined(VCMP_COUNT) && (VCMP_COUNT > 0) */

107
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vdac.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_vdac.c
* @brief Digital to Analog Converter (VDAC) Peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -83,28 +83,19 @@ void VDAC_Enable(VDAC_TypeDef *vdac, unsigned int ch, bool enable)
EFM_ASSERT(VDAC_REF_VALID(vdac));
EFM_ASSERT(VDAC_CH_VALID(ch));
if (ch == 0)
{
if (enable)
{
if (ch == 0) {
if (enable) {
vdac->CMD = VDAC_CMD_CH0EN;
}
else
{
} else {
vdac->CMD = VDAC_CMD_CH0DIS;
while (vdac->STATUS & VDAC_STATUS_CH0ENS);
while (vdac->STATUS & VDAC_STATUS_CH0ENS) ;
}
}
else
{
if (enable)
{
} else {
if (enable) {
vdac->CMD = VDAC_CMD_CH1EN;
}
else
{
} else {
vdac->CMD = VDAC_CMD_CH1DIS;
while (vdac->STATUS & VDAC_STATUS_CH1ENS);
while (vdac->STATUS & VDAC_STATUS_CH1ENS) ;
}
}
}
@ -138,25 +129,21 @@ void VDAC_Init(VDAC_TypeDef *vdac, const VDAC_Init_TypeDef *init)
/* Make sure both channels are disabled. */
vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS;
while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS));
while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)) ;
/* Get OFFSETTRIM calibration value. */
cal = ((DEVINFO->VDAC0CH1CAL & _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK)
>> _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT)
<< _VDAC_CAL_OFFSETTRIM_SHIFT;
if (init->mainCalibration)
{
if (init->mainCalibration) {
calData = &DEVINFO->VDAC0MAINCAL;
}
else
{
} else {
calData = &DEVINFO->VDAC0ALTCAL;
}
/* Get correct GAINERRTRIM calibration value. */
switch (init->reference)
{
switch (init->reference) {
case vdacRef1V25Ln:
tmp = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK)
>> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT;
@ -188,8 +175,7 @@ void VDAC_Init(VDAC_TypeDef *vdac, const VDAC_Init_TypeDef *init)
cal |= tmp << _VDAC_CAL_GAINERRTRIM_SHIFT;
/* Get GAINERRTRIMCH1 calibration value. */
switch (init->reference)
{
switch (init->reference) {
case vdacRef1V25Ln:
case vdacRef1V25:
case vdacRefAvdd:
@ -249,48 +235,36 @@ void VDAC_InitChannel(VDAC_TypeDef *vdac,
/* Make sure both channels are disabled. */
vdacStatus = vdac->STATUS;
vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS;
while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS));
while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)) ;
vdacChCtrl = ((uint32_t)init->prsSel << _VDAC_CH0CTRL_PRSSEL_SHIFT)
| ((uint32_t)init->prsAsync << _VDAC_CH0CTRL_PRSASYNC_SHIFT)
| ((uint32_t)init->trigMode << _VDAC_CH0CTRL_TRIGMODE_SHIFT)
| ((uint32_t)init->sampleOffMode << _VDAC_CH0CTRL_CONVMODE_SHIFT);
if (ch == 0)
{
if (ch == 0) {
vdac->CH0CTRL = vdacChCtrl;
}
else
{
} else {
vdac->CH1CTRL = vdacChCtrl;
}
/* Check if the channel must be enabled. */
if (init->enable)
{
if (ch == 0)
{
if (init->enable) {
if (ch == 0) {
vdac->CMD = VDAC_CMD_CH0EN;
}
else
{
} else {
vdac->CMD = VDAC_CMD_CH1EN;
}
}
/* Check if the other channel had to be turned off above
* and needs to be turned on again. */
if (ch == 0)
{
if (vdacStatus & VDAC_STATUS_CH1ENS)
{
if (ch == 0) {
if (vdacStatus & VDAC_STATUS_CH1ENS) {
vdac->CMD = VDAC_CMD_CH1EN;
}
}
else
{
if (vdacStatus & VDAC_STATUS_CH0ENS)
{
} else {
if (vdacStatus & VDAC_STATUS_CH0ENS) {
vdac->CMD = VDAC_CMD_CH0EN;
}
}
@ -317,8 +291,7 @@ void VDAC_ChannelOutputSet(VDAC_TypeDef *vdac,
unsigned int channel,
uint32_t value)
{
switch(channel)
{
switch (channel) {
case 0:
VDAC_Channel0OutputSet(vdac, value);
break;
@ -368,23 +341,16 @@ uint32_t VDAC_PrescaleCalc(uint32_t vdacFreq, bool syncMode, uint32_t hfperFreq)
uint32_t ret, refFreq;
/* Make sure selected VDAC clock is below max value */
if (vdacFreq > VDAC_MAX_CLOCK)
{
if (vdacFreq > VDAC_MAX_CLOCK) {
vdacFreq = VDAC_MAX_CLOCK;
}
if (!syncMode)
{
if (!syncMode) {
refFreq = VDAC_INTERNAL_CLOCK_FREQ;
}
else
{
if (hfperFreq)
{
} else {
if (hfperFreq) {
refFreq = hfperFreq;
}
else
{
} else {
refFreq = CMU_ClockFreqGet(cmuClock_HFPER);
}
}
@ -392,18 +358,15 @@ uint32_t VDAC_PrescaleCalc(uint32_t vdacFreq, bool syncMode, uint32_t hfperFreq)
/* Iterate in order to determine best prescale value. Start with lowest */
/* prescaler value in order to get the first equal or less VDAC */
/* frequency value. */
for (ret = 0; ret <= _VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT; ret++)
{
if ((refFreq / (ret + 1)) <= vdacFreq)
{
for (ret = 0; ret <= _VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT; ret++) {
if ((refFreq / (ret + 1)) <= vdacFreq) {
break;
}
}
/* If ret is higher than the max prescaler value, make sure to return
the max value. */
if (ret > (_VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT))
{
if (ret > (_VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT)) {
ret = _VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT;
}
@ -421,7 +384,7 @@ void VDAC_Reset(VDAC_TypeDef *vdac)
{
/* Disable channels, before resetting other registers. */
vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS;
while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS));
while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)) ;
vdac->CH0CTRL = _VDAC_CH0CTRL_RESETVALUE;
vdac->CH1CTRL = _VDAC_CH1CTRL_RESETVALUE;
vdac->CH0DATA = _VDAC_CH0DATA_RESETVALUE;

63
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c
View File

@ -2,9 +2,9 @@
* @file em_wdog.c
* @brief Watchdog (WDOG) peripheral API
* devices.
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -75,16 +75,13 @@
void WDOGn_Enable(WDOG_TypeDef *wdog, bool enable)
{
/* SYNCBUSY may stall when locked. */
if (wdog->CTRL & WDOG_CTRL_LOCK)
{
if (wdog->CTRL & WDOG_CTRL_LOCK) {
return;
}
if (!enable)
{
if (!enable) {
/* If the user intends to disable and the WDOG is enabled */
if (BUS_RegBitRead(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT))
{
if (BUS_RegBitRead(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT)) {
/* Wait for any pending previous write operation to have been completed in */
/* low frequency domain */
while (wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL)
@ -92,14 +89,11 @@ void WDOGn_Enable(WDOG_TypeDef *wdog, bool enable)
BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT, 0);
}
}
else
{
} else {
BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT, 1);
}
}
/***************************************************************************//**
* @brief
* Feed the watchdog.
@ -108,15 +102,14 @@ void WDOGn_Enable(WDOG_TypeDef *wdog, bool enable)
* When the watchdog is activated, it must be fed (ie clearing the counter)
* before it reaches the defined timeout period. Otherwise, the watchdog
* will generate a reset.
*
*
* @param[in] wdog
* Pointer to WDOG peripheral register block.
******************************************************************************/
void WDOGn_Feed(WDOG_TypeDef *wdog)
{
/* The watchdog should not be fed while it is disabled */
if (!(wdog->CTRL & WDOG_CTRL_EN))
{
if (!(wdog->CTRL & WDOG_CTRL_EN)) {
return;
}
@ -124,8 +117,7 @@ void WDOGn_Feed(WDOG_TypeDef *wdog)
/* is no point in waiting for it to complete before clearing over again. */
/* This avoids stalling the core in the typical use case where some idle loop */
/* keeps clearing the watchdog. */
if (wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD)
{
if (wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD) {
return;
}
/* Before writing to the WDOG_CMD register we also need to make sure that
@ -136,7 +128,6 @@ void WDOGn_Feed(WDOG_TypeDef *wdog)
wdog->CMD = WDOG_CMD_CLEAR;
}
/***************************************************************************//**
* @brief
* Initialize watchdog (assuming the watchdog configuration has not been
@ -159,53 +150,43 @@ void WDOGn_Init(WDOG_TypeDef *wdog, const WDOG_Init_TypeDef *init)
{
uint32_t setting;
if (init->enable)
{
if (init->enable) {
setting = WDOG_CTRL_EN;
}
else
{
} else {
setting = 0;
}
if (init->debugRun)
{
if (init->debugRun) {
setting |= WDOG_CTRL_DEBUGRUN;
}
if (init->em2Run)
{
if (init->em2Run) {
setting |= WDOG_CTRL_EM2RUN;
}
if (init->em3Run)
{
if (init->em3Run) {
setting |= WDOG_CTRL_EM3RUN;
}
if (init->em4Block)
{
if (init->em4Block) {
setting |= WDOG_CTRL_EM4BLOCK;
}
if (init->swoscBlock)
{
if (init->swoscBlock) {
setting |= WDOG_CTRL_SWOSCBLOCK;
}
if (init->lock)
{
if (init->lock) {
setting |= WDOG_CTRL_LOCK;
}
#if defined( _WDOG_CTRL_WDOGRSTDIS_MASK )
if (init->resetDisable)
{
#if defined(_WDOG_CTRL_WDOGRSTDIS_MASK)
if (init->resetDisable) {
setting |= WDOG_CTRL_WDOGRSTDIS;
}
#endif
setting |= ((uint32_t)(init->clkSel) << _WDOG_CTRL_CLKSEL_SHIFT)
#if defined( _WDOG_CTRL_WARNSEL_MASK )
#if defined(_WDOG_CTRL_WARNSEL_MASK)
| ((uint32_t)(init->warnSel) << _WDOG_CTRL_WARNSEL_SHIFT)
#endif
#if defined( _WDOG_CTRL_WINSEL_MASK )
#if defined(_WDOG_CTRL_WINSEL_MASK)
| ((uint32_t)(init->winSel) << _WDOG_CTRL_WINSEL_SHIFT)
#endif
| ((uint32_t)(init->perSel) << _WDOG_CTRL_PERSEL_SHIFT);
@ -218,7 +199,6 @@ void WDOGn_Init(WDOG_TypeDef *wdog, const WDOG_Init_TypeDef *init)
wdog->CTRL = setting;
}
/***************************************************************************//**
* @brief
* Lock the watchdog configuration.
@ -251,7 +231,6 @@ void WDOGn_Lock(WDOG_TypeDef *wdog)
BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_LOCK_SHIFT, 1);
}
/** @} (end addtogroup WDOG) */
/** @} (end addtogroup emlib) */
#endif /* defined(WDOG_COUNT) && (WDOG_COUNT > 0) */

7
targets/TARGET_Silicon_Labs/TARGET_EFM32/flash_api.c
View File

@ -93,10 +93,17 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
(void)obj;
(void)address;
#if FLASH_BASE > 0
if (address < FLASH_BASE || address >= FLASH_BASE + FLASH_SIZE) {
// Address outside of flash -- invalid sector
return MBED_FLASH_INVALID_SIZE;
}
#else
if (address >= FLASH_BASE + FLASH_SIZE) {
// Address outside of flash -- invalid sector
return MBED_FLASH_INVALID_SIZE;
}
#endif
return FLASH_PAGE_SIZE;
}

1
targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c
View File

@ -29,7 +29,6 @@
#include "pinmap.h"
#include "em_gpio.h"
#include "em_int.h"
#include "em_cmu.h"
#include "sleep_api.h"
#include "sleepmodes.h"

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