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Added TMPM4NR Platform 

New Platform for Toshiba Added
pull/15330/head
Deepak V. Shreshti 2022-09-08 18:54:26 +05:30
parent 807fd79651
commit 2a72a7079b
67 changed files with 41460 additions and 4 deletions
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476
targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_adc.h Normal file
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/**
*******************************************************************************
* @file txz_adc.h
* @brief This file provides all the functions prototypes for ADC driver.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __ADC_H
#define __ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_driver_def.h"
#include "txz_adc_ch.h"
/**
* @addtogroup Periph_Driver Peripheral Driver
* @{
*/
/**
* @defgroup ADC ADC
* @brief ADC Driver.
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Exported_define ADC Exported Define
* @{
*/
/**
* @defgroup ADC_ChannelMax Channel Num Max
* @brief Max Num of channel.
* @{
*/
#define ADC_NUM_MAX ((uint32_t)24) /*!< Max Num of conversion. */
/**
* @}
*/ /* End of group ADC_ChannelMax */
/**
* @}
*/ /* End of group ADC_Exported_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
@defgroup ADC_Exported_define ADC Exported Define
@{
*/
/** @enum adc_sampling_period0_t
@brief Outside AIN sampling period.
*/
typedef enum {
ADC_SAMPLING_PERIOD0_XN = 0x00, /*!< SCLK Period (1/SCLK)xN */
ADC_SAMPLING_PERIOD0_X2N = 0x08, /*!< SCLK Period (1/SCLK)x2N */
ADC_SAMPLING_PERIOD0_X3N = 0x10, /*!< SCLK Period (1/SCLK)x3N */
ADC_SAMPLING_PERIOD0_X4N = 0x18, /*!< SCLK Period (1/SCLK)x4N */
} adc_sampling_period0_t;
/** @enum adc_sampling_period1_t
@brief Outside AIN sampling period.
*/
typedef enum {
ADC_SAMPLING_PERIOD1_XN = 0x000, /*!< SCLK Period (1/SCLK)xN */
ADC_SAMPLING_PERIOD1_X2N = 0x100, /*!< SCLK Period (1/SCLK)x2N */
ADC_SAMPLING_PERIOD1_X3N = 0x200, /*!< SCLK Period (1/SCLK)x3N */
ADC_SAMPLING_PERIOD1_X4N = 0x300, /*!< SCLK Period (1/SCLK)x4N */
} adc_sampling_period1_t;
/*! @enum adc_sclk_t
@brief Select AD prescaler output (SCLK).
*/
typedef enum {
ADC_SCLK_2 = (0x00000000U), /*!< ADCLK/2 */
ADC_SCLK_4 = (0x00000001U), /*!< ADCLK/4 */
ADC_SCLK_8 = (0x00000002U), /*!< ADCLK/8 */
ADC_SCLK_16 = (0x00000003U), /*!< ADCLK/16 */
ADC_SCLK_3 = (0x00000004U), /*!< ADCLK/3 */
ADC_SCLK_5 = (0x00000005U), /*!< ADCLK/5 */
ADC_SCLK_6 = (0x00000006U), /*!< ADCLK/6 */
ADC_SCLK_10 = (0x00000007U), /*!< ADCLK/10 */
} adc_sclk_t;
/*! @enum adc_mod1_t
@brief Select SCLK Frequency Band (MOD1).
*/
typedef enum {
ADC_MOD1_SCLK_1 = (0x00001000U), /*!< SCLK =< 20MHz > */
ADC_MOD1_SCLK_2 = (0x00003000U), /*!< 20MHz < SCLK =< 25MHz > */
ADC_MOD1_SCLK_3 = (0x00004000U), /*!< 25MHz < SCLK =< 30MHz > */
ADC_MOD1_SCLK_4 = (0x00006011U), /*!< 30MHz < SCLK =< 40MHz > */
} adc_mod1_t;
/*! @enum adc_mod2_t
@brief Select ADC Product Setting Value (MOD2).
*/
typedef enum {
ADC_MOD2_SET = (0x00000000U), /*!< SET Value */
ADC_MOD2_CLEAR = (0x00000000U), /*!< Reset Value */
} adc_mod2_t;
/*! @enum adc_int_t
@brief Select Interrupt Enable/Disable.
*/
typedef enum {
ADC_INT_DISABLE = (0x00000000U), /*!< Disable. */
ADC_INT_ENABLE = (0x00000080U), /*!< Enable. */
} adc_int_t;
/*! @enum adc_conversion_t
@brief Select conversion method.
*/
typedef enum {
ADC_CONVERSION_DISABLE = (0x00000000U), /*!< Disable. */
ADC_CONVERSION_CNT = (0x00000100U), /*!< Continuation. */
ADC_CONVERSION_SGL = (0x00000200U), /*!< Single. */
ADC_CONVERSION_TRG = (0x00000300U), /*!< Universal Trigger. */
ADC_CONVERSION_HPTG = (0x00000400U), /*!< High Priority Trigger. */
} adc_conversion_t;
/*! @enum adc_dma_int_t
@brief Select DMA interrupt method.
*/
typedef enum {
ADC_DMA_INT_SGL_DISABLE = (0x00000000U), /*!< Disable. */
ADC_DMA_INT_SGL_ENABLE = (0x00000020U), /*!< DMA Single interrupt Enable. */
ADC_DMA_INT_CNT_DISABLE = (0x00000000U), /*!< Disable. */
ADC_DMA_INT_CNT_ENABLE = (0x00000040U), /*!< DMA Continuation interrupt Enable. */
ADC_DMA_INT_TRG_DISABLE = (0x00000000U), /*!< Disable. */
ADC_DMA_INT_TRG_ENABLE = (0x00000010U), /*!< DMA Universal Trigger interrupt Enable. */
ADC_TRG_DISABLE = (0x00000000U), /*!< Universal Trigger Disable. */
ADC_TRG_ENABLE = (0x00000001U), /*!< Universal Trigger Enable. */
ADC_HPTG_DISABLE = (0x00000000U), /*!< High Priority Trigger Disable. */
ADC_HPTG_ENABLE = (0x00000002U), /*!< High Priority Trigger Enable. */
} adc_dma_int_t;
/*! @enum adc_ain_range_t
@brief Range of AIN Macro Definition.
Range of AIN be set "(ADC_AIN_RANGE_MIN <= Value <= ADC_AIN_RANGE_MAX)".
*/
typedef enum {
ADC_AIN_RANGE_MIN = (0x00000000U), /*!< Minimum Value :AINx00 */
ADC_AIN_RANGE_MAX = (0x00000017U), /*!< Maximum Value :AINx23 */
} adc_ain_range_t;
/*! @enum adc_status_t
@brief AD Running Status.
*/
typedef enum {
ADC_STATUS_MASK = (0x00000080U), /*!< for Mask. */
ADC_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */
ADC_STATUS_RUNNING = (0x00000080U), /*!< Running. */
} adc_status_t;
/*! @enum adc_cnt_status_t
@brief Continuity Conversion Running Status.
*/
typedef enum {
ADC_CNT_STATUS_MASK = (0x00000008U), /*!< for Mask. */
ADC_CNT_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */
ADC_CNT_STATUS_RUNNING = (0x00000008U), /*!< Running. */
} adc_cnt_status_t;
/*! @enum adc_sgl_status_t
@brief Single Conversion Running Status.
*/
typedef enum {
ADC_SGL_STATUS_MASK = (0x00000004U), /*!< for Mask. */
ADC_SGL_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */
ADC_SGL_STATUS_RUNNING = (0x00000004U), /*!< Running. */
} adc_sgl_status_t;
/*! @enum adc_trg_status_t
@brief Trigger Conversion Running Status.
*/
typedef enum {
ADC_TRG_STATUS_MASK = (0x00000002U), /*!< for Mask. */
ADC_TRG_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */
ADC_TRG_STATUS_RUNNING = (0x00000002U), /*!< Running. */
} adc_trg_status_t;
/*! @enum adc_hpri_status_t
@brief Trigger Conversion Running Status.
*/
typedef enum {
ADC_HPTG_STATUS_MASK = (0x00000001U), /*!< for Mask. */
ADC_HPTG_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */
ADC_HPTG_STATUS_RUNNING = (0x00000001U), /*!< Running. */
} adc_hpri_status_t;
/*! @enum adcmpxen_t
@brief Select Enable, Disable setting(ADxCMPEN).
*/
typedef enum {
ADCMP1EN_DISABLE = (0x00000000U), /*!< Disable. */
ADCMP1EN_ENABLE = (0x00000002U), /*!< Enable. */
ADCMP0EN_DISABLE = (0x00000000U), /*!< Disable. */
ADCMP0EN_ENABLE = (0x00000001U), /*!< Enable. */
} adcmpxen_t;
/*! @enum adcmpcnt_t
@brief Select Compare count num.
*/
typedef enum {
ADCMPCNT_1 = (0x00000000U), /*!< 1 time */
ADCMPCNT_2 = (0x00000100U), /*!< 2 times */
ADCMPCNT_3 = (0x00000200U), /*!< 3 times */
ADCMPCNT_4 = (0x00000300U), /*!< 4 times */
ADCMPCNT_5 = (0x00000400U), /*!< 5 times */
ADCMPCNT_6 = (0x00000500U), /*!< 6 times */
ADCMPCNT_7 = (0x00000600U), /*!< 7 times */
ADCMPCNT_8 = (0x00000700U), /*!< 8 times */
ADCMPCNT_9 = (0x00000800U), /*!< 9 times */
ADCMPCNT_10 = (0x00000900U), /*!< 10 times */
ADCMPCNT_11 = (0x00000a00U), /*!< 11 times */
ADCMPCNT_12 = (0x00000b00U), /*!< 12 times */
ADCMPCNT_13 = (0x00000c00U), /*!< 13 times */
ADCMPCNT_14 = (0x00000d00U), /*!< 14 times */
ADCMPCNT_15 = (0x00000e00U), /*!< 15 times */
ADCMPCNT_16 = (0x00000f00U), /*!< 16 times */
} adcmpcnt_t;
/*! @enum adcmpcond_t
@brief Compare condition
*/
typedef enum {
ADCMPCond_CNT = (0x00000000U), /*!< Continuous */
ADCMPCond_ACC = (0x00000040U), /*!< Accumulation */
} adcmpcond_t;
/*! @enum adcmpbigsml_t
@brief Compare Big, Small condition
*/
typedef enum {
ADCMPBigSml_Big = (0x00000000U), /*!< Big */
ADCMPBigSml_Sml = (0x00000020U), /*!< Small */
} adcmpbigsml_t;
/*! @enum adcmpstr_t
@brief Select Compare Store register
*/
typedef enum {
ADCMPStr_Reg0 = (0x00000000U), /*!< ADxREG0 */
ADCMPStr_Reg1 = (0x00000001U), /*!< ADxREG1 */
ADCMPStr_Reg2 = (0x00000002U), /*!< ADxREG2 */
ADCMPStr_Reg3 = (0x00000003U), /*!< ADxREG3 */
ADCMPStr_Reg4 = (0x00000004U), /*!< ADxREG4 */
ADCMPStr_Reg5 = (0x00000005U), /*!< ADxREG5 */
ADCMPStr_Reg6 = (0x00000006U), /*!< ADxREG6 */
ADCMPStr_Reg7 = (0x00000007U), /*!< ADxREG7 */
ADCMPStr_Reg8 = (0x00000008U), /*!< ADxREG8 */
ADCMPStr_Reg9 = (0x00000009U), /*!< ADxREG9 */
ADCMPStr_Reg10 = (0x0000000aU), /*!< ADxREG10 */
ADCMPStr_Reg11 = (0x0000000bU), /*!< ADxREG11 */
ADCMPStr_Reg12 = (0x0000000cU), /*!< ADxREG12 */
ADCMPStr_Reg13 = (0x0000000dU), /*!< ADxREG13 */
ADCMPStr_Reg14 = (0x0000000eU), /*!< ADxREG14 */
ADCMPStr_Reg15 = (0x0000000fU), /*!< ADxREG15 */
ADCMPStr_Reg16 = (0x00000010U), /*!< ADxREG16 */
ADCMPStr_Reg17 = (0x00000011U), /*!< ADxREG17 */
ADCMPStr_Reg18 = (0x00000012U), /*!< ADxREG18 */
ADCMPStr_Reg19 = (0x00000013U), /*!< ADxREG19 */
ADCMPStr_Reg20 = (0x00000014U), /*!< ADxREG20 */
ADCMPStr_Reg21 = (0x00000015U), /*!< ADxREG21 */
ADCMPStr_Reg22 = (0x00000016U), /*!< ADxREG22 */
ADCMPStr_Reg23 = (0x00000017U), /*!< ADxREG23 */
} adcmpstr_t;
/*! @enum adcexazain_t
@brief Select AIN no.
*/
typedef enum {
ADCEXAZSEL_AIN0 = 0, /*!< AIN0 */
ADCEXAZSEL_AIN1, /*!< AIN1 */
ADCEXAZSEL_AIN2, /*!< AIN2 */
ADCEXAZSEL_AIN3, /*!< AIN3 */
ADCEXAZSEL_AIN4, /*!< AIN4 */
ADCEXAZSEL_AIN5, /*!< AIN5 */
ADCEXAZSEL_AIN6, /*!< AIN6 */
ADCEXAZSEL_AIN7, /*!< AIN7 */
ADCEXAZSEL_AIN8, /*!< AIN8 */
ADCEXAZSEL_AIN9, /*!< AIN9 */
ADCEXAZSEL_AIN10, /*!< AIN10 */
ADCEXAZSEL_AIN11, /*!< AIN11 */
ADCEXAZSEL_AIN12, /*!< AIN12 */
ADCEXAZSEL_AIN13, /*!< AIN13 */
ADCEXAZSEL_AIN14, /*!< AIN14 */
ADCEXAZSEL_AIN15, /*!< AIN15 */
ADCEXAZSEL_AIN16, /*!< AIN16 */
ADCEXAZSEL_AIN17, /*!< AIN17 */
ADCEXAZSEL_AIN18, /*!< AIN18 */
ADCEXAZSEL_AIN19, /*!< AIN19 */
ADCEXAZSEL_AIN20, /*!< AIN20 */
ADCEXAZSEL_AIN21, /*!< AIN21 */
ADCEXAZSEL_AIN22, /*!< AIN22 */
ADCEXAZSEL_AIN23, /*!< AIN23 */
} adcexazain_t;
/*! @enum adcexazsel_t
@brief Select sampling period, EXAS0 or EXAS1.
*/
typedef enum {
ADCEXAZSEL_EXAZ0 = (0x00000000), /*< EXAZ0 */
ADCEXAZSEL_EXAZ1 = (0x00000001), /*< EXAZ1 */
} adcexazsel_t;
/*!
@}
*/ /* End of group ADC_Exported_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/*!
@defgroup ADC_Exported_typedef ADC Exported Typedef
@{
*/
/*----------------------------------*/
/*! @struct adc_clock_t
@brief Clock information structure definition.
*/
/*----------------------------------*/
typedef struct {
adc_sampling_period0_t exaz0; /*!< Outside AIN0 Sampling period.
: Use @ref adc_sampling_period0_t. */
adc_sampling_period1_t exaz1; /*!< Outside AIN1 Sampling period.
: Use @ref adc_sampling_period1_t. */
adc_sclk_t vadcld; /*!< Select AD prescaler output (SCLK).
: Use @ref adc_sclk_t. */
uint32_t sampling_select; /*!< Sampling period select. : bit0-bit23 */
} adc_clock_t;
/*----------------------------------*/
/*! @struct adc_cmpx_t
@brief Clock information structure definition.
*/
/*----------------------------------*/
typedef struct {
uint32_t CMPEN; /*!< Enable Register status */
uint32_t CMPCNT; /*!< Compare count num. */
uint32_t CMPCond; /*!< Compare condition */
uint32_t CMPBigSml; /*!< Compare Big/Small condition */
uint32_t StrReg; /*!< Compare Store register */
uint32_t ADComp; /*!< ADxCMP0 register data */
void (*handle)(uint32_t id, TXZ_Result result); /*!< Notify Compare Done. */
} adc_cmpx_t;
/*----------------------------------*/
/*! @struct adc_initial_setting_t
@brief Initial setting structure definition.
*/
/*----------------------------------*/
typedef struct {
uint32_t id; /*!< ID: User value. */
adc_clock_t clk; /*!< Clock setting.
: Use @ref adc_clock_t. */
uint32_t mod1; /*!< AVDD3 voltage band setting.
: Use @ref adc_mod1_t. */
uint32_t mod2; /*!< Product info setting.
: Use @ref adc_mod2_t. */
adc_cmpx_t CMPxEN[4]; /*!< adc_cmpx_t. */
} adc_initial_setting_t;
/*----------------------------------*/
/*! @struct adc_channel_setting_t
@brief Channel Setting. \n
*/
/*----------------------------------*/
typedef struct {
uint32_t interrupt; /*!< Interrupt Enable/Disable.
: Use @ref adc_dma_int_t. */
uint32_t type; /*!< Conversion Type.
: Use @ref adc_conversion_t. */
uint32_t ain; /*!< AIN. */
} adc_channel_setting_t;
/*----------------------------------*/
/*! @struct adc_internal_info_t
@brief Driver internal information structure definition.
*/
/*----------------------------------*/
typedef struct {
adc_ch_t ch[ADC_NUM_MAX]; /*!< Channel Instance. */
} adc_internal_info_t;
/*----------------------------------*/
/*! @struct adc_t
@brief ADC handle structure definition.
*/
/*----------------------------------*/
typedef struct {
TSB_AD_TypeDef *p_instance; /*!< Registers base address. */
adc_initial_setting_t init; /*!< Initial setting. */
adc_internal_info_t info; /*!< Driver internal information. */
struct {
void (*single)(uint32_t id, TXZ_Result result); /*!< Notify Single Conversion Done. */
void (*continuity)(uint32_t id, TXZ_Result result); /*!< Notify Continuity Conversion Done. */
void (*trigger)(uint32_t id, TXZ_Result result); /*!< Notify Trigger Conversion Done. */
void (*highpriority)(uint32_t id, TXZ_Result result); /*!< Notify HighPriority Conversion Done. */
} handler; /*!< Handler structure. */
} adc_t;
/**
* @}
*/ /* End of group ADC_Exported_typedef */
/*------------------------------------------------------------------------------*/
/* Functions */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Exported_functions ADC Exported Functions
* @{
*/
TXZ_Result adc_init(adc_t *p_obj);
TXZ_Result adc_deinit(adc_t *p_obj);
TXZ_Result adc_mode1_setting(void);
TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting);
TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch);
TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t);
TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t);
TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value);
TXZ_Result adc_start(adc_t *p_obj);
TXZ_Result adc_stop(adc_t *p_obj);
TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status);
TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout);
void adc_compa_irq_handler(void);
void adc_compb_irq_handler(void);
void adc_single_irq_handler(void);
void adc_continuity_irq_handler(void);
void adc_trigger_irq_handler(void);
/**
* @}
*/ /* End of group ADC_Exported_functions */
/**
* @}
*/ /* End of group ADC */
/**
* @}
*/ /* End of group Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ADC_H */

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targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_adc_ch.h Normal file
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/**
*******************************************************************************
* @file txz_adc_ch.h
* @brief This file provides all the functions prototypes for ADC driver. \n
* Channel Class.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __ADC_CH_H
#define __ADC_CH_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_driver_def.h"
/**
* @addtogroup Periph_Driver Peripheral Driver
* @{
*/
/**
* @defgroup ADC ADC
* @brief ADC Driver.
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Exported_define ADC Exported Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Exported_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Exported_define ADC Exported Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Exported_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Exported_typedef ADC Exported Typedef
* @{
*/
/*----------------------------------*/
/*! @struct adc_ch_initial_setting_t
* @brief Initialize Setting.
*/
/*----------------------------------*/
typedef struct {
uint32_t interrupt; /*!< Interrupt Enable/Disable.
: Use @ref adc_dma_int_t. */
uint32_t type; /*!< Conversion Type.
: Use @ref adc_conversion_t. */
uint32_t ain; /*!< AIN. */
} adc_ch_initial_setting_t;
/*----------------------------------*/
/*! @struct adc_ch_t
* @brief ADC handle structure definition.
*/
/*----------------------------------*/
typedef struct {
__IO uint32_t *p_tset; /*!< ADxTSETn Address. */
__I uint32_t *p_reg; /*!< ADxREGx Address. */
adc_ch_initial_setting_t init; /*!< Initial setting. */
} adc_ch_t;
/**
* @}
*/ /* End of group ADC_Exported_typedef */
/*------------------------------------------------------------------------------*/
/* Functions */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Exported_functions ADC Exported Functions
* @{
*/
uint32_t get_conversion_data(uint32_t reg);
TXZ_Result adc_ch_init(adc_ch_t *p_obj);
TXZ_Result adc_ch_deinit(adc_ch_t *p_obj);
TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj);
TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj);
TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value);
/**
* @}
*/ /* End of group ADC_Exported_functions */
/**
* @}
*/ /* End of group ADC */
/**
* @}
*/ /* End of group Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ADC_CH_H */

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/**
*******************************************************************************
* @file txz_adc_include.h
* @brief This file provides internal common definition.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __ADC_INCLUDE_H
#define __ADC_INCLUDE_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_driver_def.h"
#include "txz_hal.h"
/**
* @addtogroup Periph_Driver Peripheral Driver
* @{
*/
/**
* @defgroup ADC ADC
* @brief ADC Driver.
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_define ADC Private Define
* @{
*/
/**
* @defgroup NULL_Pointer NULL Pointer
* @brief NULL Pointer.
* @{
*/
#define ADC_NULL ((void *)0) /*!< NULL Pointer. */
/**
* @}
*/ /* End of group NULL_Pointer */
/**
* @defgroup Parameter_Result Parameter Result
* @brief Whether the parameter is specified or not.
* @{
*/
#define ADC_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */
#define ADC_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */
/**
* @}
*/ /* End of group Parameter_Result */
/**
* @defgroup ADxCR0 ADxCR0
* @brief ADxCR0 Register.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-8 | - |
* | 7 | ADEN |
* | 6-3 | - |
* | 2 | HPSGL |
* | 1 | SGL |
* | 0 | CNT |
* @{
*/
/* ADEN */
#define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000) /*!< ADEN :Disable */
#define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080) /*!< ADEN :Enable */
/* HPSGL */
#define ADxCR0_HPSGL_ENABLE ((uint32_t)0x00000004) /*!< HPSGL :Enable */
/* SGL */
#define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002) /*!< SGL :Enable */
/* CNT */
#define ADxCR0_CNT_MASK ((uint32_t)0x00000001) /*!< CNT :Mask */
#define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000) /*!< CNT :Disable */
#define ADxCR0_CNT_ENABLE ((uint32_t)0x00000001) /*!< CNT :Enable */
/**
* @}
*/ /* End of group ADxCR0 */
/**
* @defgroup ADxCR1 ADxCR1
* @brief ADxCR1 Register.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-8 | - |
* | 7 | HPDMEN |
* | 6 | CNTDMEN |
* | 5 | SGLDMEN |
* | 4 | TRGDMEN |
* | 3:2 | - |
* | 1 | HPTRGEN |
* | 0 | TRGEN |
* @{
*/
/* HPDMEN */
#define ADxCR1_HPDMEN_DISABLE ((uint32_t)0x00000000) /*!< HPDMEN :Disable */
#define ADxCR1_HPDMEN_ENABLE ((uint32_t)0x00000080) /*!< HPDMEN :Enable */
/* CNTDMEN */
#define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000) /*!< CNTDMEN :Disable */
#define ADxCR1_CNTDMEN_ENABLE ((uint32_t)0x00000040) /*!< CNTDMEN :Enable */
/* SGLDMEN */
#define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000) /*!< SGLDMEN :Disable */
#define ADxCR1_SGLDMEN_ENABLE ((uint32_t)0x00000020) /*!< SGLDMEN :Enable */
/* TRGDMEN */
#define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000) /*!< TRGDMEN :Disable */
#define ADxCR1_TRGDMEN_ENABLE ((uint32_t)0x00000010) /*!< TRGDMEN :Enable */
/* HPTRGEN */
#define ADxCR1_HPTRGEN_DISABLE ((uint32_t)0x00000000) /*!< HPTRGEN :Disable */
#define ADxCR1_HPTRGEN_ENABLE ((uint32_t)0x00000002) /*!< HPTRGEN :Enable */
/* TRGEN */
#define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< TRGEN :Disable */
#define ADxCR1_TRGEN_ENABLE ((uint32_t)0x00000001) /*!< TRGEN :Enable */
/**
* @}
*/ /* End of group ADxCR1 */
/**
* @defgroup ADxST ADxST
* @brief ADxST Register.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-8 | - |
* | 7 | ADBF |
* | 6-4 | - |
* | 3 | CNTF |
* | 2 | SNGF |
* | 1 | TRGF |
* | 0 | HPF |
* @{
*/
/* ADBF */
#define ADxST_ADBF_MASK ((uint32_t)0x00000080) /*!< ADBF :Mask. */
#define ADxST_ADBF_IDLE ((uint32_t)0x00000000) /*!< ADBF :Idle. Can stop ADCLK. */
#define ADxST_ADBF_RUN ((uint32_t)0x00000080) /*!< ADBF :Running. Can't stop ADCLK. */
/* CNTF */
#define ADxST_CNTF_MASK ((uint32_t)0x00000008) /*!< CNTF :Mask. */
#define ADxST_CNTF_IDLE ((uint32_t)0x00000000) /*!< CNTF :Idle. */
#define ADxST_CNTF_RUN ((uint32_t)0x00000008) /*!< CNTF :Running. */
/* SNGF */
#define ADxST_SNGF_MASK ((uint32_t)0x00000004) /*!< SNGF :Mask. */
#define ADxST_SNGF_IDLE ((uint32_t)0x00000000) /*!< SNGF :Idle. */
#define ADxST_SNGF_RUN ((uint32_t)0x00000004) /*!< SNGF :Running. */
/* TRGF */
#define ADxST_TRGF_MASK ((uint32_t)0x00000002) /*!< TRGF :Mask. */
#define ADxST_TRGF_IDLE ((uint32_t)0x00000000) /*!< TRGF :Idle. */
#define ADxST_TRGF_RUN ((uint32_t)0x00000002) /*!< TRGF :Running. */
/* PMDF */
#define ADxST_HPF_MASK ((uint32_t)0x00000001) /*!< HPF :Mask. */
#define ADxST_HPF_IDLE ((uint32_t)0x00000000) /*!< HPF :Idle. */
#define ADxST_HPF_RUN ((uint32_t)0x00000001) /*!< HPF :Running. */
/**
* @}
*/ /* End of group ADxST */
/**
* @defgroup ADxMOD0 ADxMOD0.
* @brief ADxMOD0 Register.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-2 | - |
* | 1 | RCUT |
* | 0 | DACON |
* @{
*/
/* RCUT */
#define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000) /*!< RCUT :Normal */
#define ADxMOD0_RCUT_IREF_CUT ((uint32_t)0x00000002) /*!< RCUT :Iref cut */
/* DACON */
#define ADxMOD0_DACON_OFF ((uint32_t)0x00000000) /*!< DACON :DAC off */
#define ADxMOD0_DACON_ON ((uint32_t)0x00000001) /*!< DACON :DAC on */
/**
* @}
*/ /* End of group ADxMOD0 */
/**
* @name ADxCMPEN Macro Definition.
* @brief ADxCMPEN Register Macro Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-4 | - |
* | 3 | CMP3EN |
* | 2 | CMP2EN |
* | 1 | CMP1EN |
* | 0 | CMP0EN |
* @{
*/
/* CMP3EN */
#define ADxCMPEN_CMP3EN_DISABLE ((uint32_t)0x00000000) /*!< CMP3EN :Disable */
#define ADxCMPEN_CMP3EN_ENABLE ((uint32_t)0x00000008) /*!< CMP3EN :Enable */
/* CMP2EN */
#define ADxCMPEN_CMP2EN_DISABLE ((uint32_t)0x00000000) /*!< CMP2EN :Disable */
#define ADxCMPEN_CMP2EN_ENABLE ((uint32_t)0x00000004) /*!< CMP2EN :Enable */
/* CMP1EN */
#define ADxCMPEN_CMP1EN_DISABLE ((uint32_t)0x00000000) /*!< CMP1EN :Disable */
#define ADxCMPEN_CMP1EN_ENABLE ((uint32_t)0x00000002) /*!< CMP1EN :Enable */
/* CMP0EN */
#define ADxCMPEN_CMP0EN_DISABLE ((uint32_t)0x00000000) /*!< CMP0EN :Disable */
#define ADxCMPEN_CMP0EN_ENABLE ((uint32_t)0x00000001) /*!< CMP0EN :Enable */
/**
* @}
*/ /* End of name ADxCMPEN Macro Definition */
/**
* @name ADxTSETn Macro Definition.
* @brief ADxTSETn Register Macro Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-8 | - |
* | 7 | ENINT0 |
* | 6-5 | TRGS0[1:0] |
* | 4-0 | AINST0[4:0]|
* @{
*/
/* ENINT0 */
#define ADxTSETn_ENINT_MASK ((uint32_t)0x00000080) /*!< ENINT :Mask */
#define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000) /*!< ENINT :Disable */
#define ADxTSETn_ENINT_ENABLE ((uint32_t)0x00000080) /*!< ENINT :Enable */
/* TRGS0[1:0] */
#define ADxTSETn_TRGS_DISABLE ((uint32_t)0x00000000) /*!< TRGS :Disable */
#define ADxTSETn_TRGS_CNT ((uint32_t)0x00000100) /*!< TRGS :Continuation */
#define ADxTSETn_TRGS_SGL ((uint32_t)0x00000200) /*!< TRGS :Single */
#define ADxTSETn_TRGS_TRG ((uint32_t)0x00000300) /*!< TRGS :Universal Trigger */
#define ADxTSETn_TRGS_PRI ((uint32_t)0x00000400) /*!< TRGS :Priority Trigger */
/**
* @}
*/ /* End of name ADxTSETn Macro Definition */
/**
* @name ADxREGn Macro Definition.
* @brief ADxREGn Register Macro Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-30 | - |
* | 29 | ADOVRF_Mn |
* | 28 | ADRF_Mn |
* | 27-16 | ADR_Mn[11:0] |
* | 15-4 | ADRn[11:0] |
* | 3-2 | - |
* | 1 | ADOVRFn |
* | 0 | ADRFn |
* @{
*/
/* ADOVRF_Mn */
#define ADxREGn_ADOVRF_Mn_MASK ((uint32_t)0x20000000) /*!< ADOVRF_Mn :Mask */
#define ADxREGn_ADOVRF_Mn_OFF ((uint32_t)0x00000000) /*!< ADOVRF_Mn :Flag off. */
#define ADxREGn_ADOVRF_Mn_ON ((uint32_t)0x20000000) /*!< ADOVRF_Mn :Flag on */
/* ADRF_Mn */
#define ADxREGn_ADRF_Mn_MASK ((uint32_t)0x10000000) /*!< ADRF_Mn :Mask */
#define ADxREGn_ADRF_Mn_OFF ((uint32_t)0x00000000) /*!< ADRF_Mn :Flag off. */
#define ADxREGn_ADRF_Mn_ON ((uint32_t)0x10000000) /*!< ADRF_Mn :Flag on */
/* ADR_Mn */
#define ADxREGn_ADR_Mn_MASK ((uint32_t)0x0FFF0000) /*!< ADR_Mn :Mask */
/* ADRn */
#define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0) /*!< ADRn :Mask */
/* ADOVRFn */
#define ADxREGn_ADOVRFn_MASK ((uint32_t)0x00000002) /*!< ADOVRF_Mn :Mask */
#define ADxREGn_ADOVRFn_OFF ((uint32_t)0x00000000) /*!< ADOVRF_Mn :Flag off. */
#define ADxREGn_ADOVRFn_ON ((uint32_t)0x00000002) /*!< ADOVRF_Mn :Flag on */
/* ADRFn */
#define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001) /*!< ADRFn :Mask */
#define ADxREGn_ADRFn_OFF ((uint32_t)0x00000000) /*!< ADRFn :Flag off. */
#define ADxREGn_ADRFn_ON ((uint32_t)0x00000001) /*!< ADRFn :Flag on */
/**
* @}
*/ /* End of name ADxREGn Macro Definition */
/**
* @}
*/ /* End of group ADC_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_define ADC Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Private_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_typedef ADC Private Typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Inline Functions */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_functions ADC Private Functions
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Private_functions */
/**
* @}
*/ /* End of group ADC */
/**
* @}
*/ /* End of group Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ADC_INCLUDE_H */

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/**
*******************************************************************************
* @file txz_cg.h
* @brief This file provides all the functions prototypes for CG driver.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __CG_H
#define __CG_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_driver_def.h"
/**
* @addtogroup Periph_Driver
* @{
*/
/**
* @defgroup CG CG
* @brief CG Driver.
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Exported_define CG Exported Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group CG_Exported_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Exported_define CG Exported Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group CG_Exported_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Exported_typedef CG Exported Typedef
* @{
*/
/**
* @brief CG member.
*/
/*----------------------------------*/
typedef struct {
TSB_CG_TypeDef *p_instance; /*!< Registers base address. */
} cg_t;
/**
* @}
*/ /* End of group CG_Exported_typedef */
/*------------------------------------------------------------------------------*/
/* Functions */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Exported_functions CG Exported Functions
* @{
*/
uint32_t cg_get_fsysm(cg_t *p_obj);
uint32_t cg_get_phyt0(cg_t *p_obj);
uint32_t cg_get_mphyt0(cg_t *p_obj);
TXZ_Result cg_ihosc_enable(cg_t *p_obj);
TXZ_Result cg_ihosc_disable(cg_t *p_obj);
/**
* @}
*/ /* End of group CG_Exported_functions */
/**
* @}
*/ /* End of group CG */
/**
* @}
*/ /* End of group Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __CG_H */

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/**
*******************************************************************************
* @file txz_driver_def.h
* @brief All common macro and definition for TXZ peripheral drivers
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TXZ_DRIVER_DEF_H
#define __TXZ_DRIVER_DEF_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup Periph_Driver Peripheral Driver
* @{
*/
/** @defgroup TXZ_DRIVER_DEF TXZ DRIVER DEF
* @brief All common macro and definition for TXZ peripheral drivers
* @{
*/
/** @defgroup Device_Header_Included Device Header Included
* @brief Include the Device header file of a Target.
* @{
*/
#if (defined(TMPM4NR) || defined(TMPM4NQ) || defined(TMPM4NN))
#include "TMPM4Nx.h" /*!< TMPM4Nx Group Header file. */
#else
#error "target device is non-select."
#endif
/**
* @}
*/ /* End of group Device_Header */
/** @defgroup TXZ_Exported_typedef TXZ Exported typedef
* @{
*/
typedef enum {
TXZ_SUCCESS = 0U,
TXZ_ERROR = 1U
} TXZ_Result;
typedef enum {
TXZ_BUSY = 0U,
TXZ_DONE = 1U
} TXZ_WorkState;
typedef enum {
TXZ_DISABLE = 0U,
TXZ_ENABLE = 1U
} TXZ_FunctionalState;
/**
* @}
*/ /* End of group TXZ_Exported_typedef */
/** @defgroup TXZ_Exported_macro TXZ Exported macro
* @{
*/
#define IS_TXZ_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
#define IS_POINTER_NOT_NULL(param) ((void*)(param)!=(void*)0)
/**
* @brief To report the name of the source file and source line number where the
* assert_param error has occurred, "__DEBUG__" must be defined. And detailed
* definition of assert_failed() is needed to be implemented, which can be
* done, for example, in the main.c file.
*/
#ifdef __DEBUG__
void assert_failed(char *file, int32_t line);
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__))
#else
#define assert_param(expr)
#endif /* __DEBUG__ */
/**
* @}
*/ /* End of group TXZ_Exported_macro */
/**
* @}
*/ /* End of group Periph_Driver */
/**
* @}
*/ /* End of group TXZ_DRIVER_DEF */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __TXZ_DRIVER_DEF_H */

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/**
*******************************************************************************
* @file txz_fc.h
* @brief This file provides all the functions prototypes for FLASH.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __FC_H
#define __FC_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "txz_driver_def.h"
#if defined(__FC_H)
/** @addtogroup Periph driver
* @{
*/
/** @defgroup fc
* @brief fc
* @{
*/
/** @defgroup FlashApi_Exported_Types
* @{
*/
/**
* @enum fc_sr0_t
* @brief Enumerated type definition of the FCSR0 register.
*/
typedef enum {
FC_SR0_RDYBSY = (0x00000001UL) /*!< 0:Busy, 1:Ready all flash */
} fc_sr0_t;
/*----------------------------------*/
/**
* @enum fc_erase_kind_t
* @brief FC Erase Flash Kind structure definenition.
*/
/*----------------------------------*/
typedef enum {
FC_ERASE_KIND_PAGE = (0x00000040UL), /*!< Page Erase */
FC_ERASE_KIND_BLOCK = (0x00000030UL) /*!< Block Erase */
} fc_erase_kind_t;
typedef enum {
FC_CODE_FLASH_PAGE0 = 0, /*!< (0x5E000000UL), CODE FLASH Page0 */
FC_CODE_FLASH_PAGE1, /*!< (0x5E001000UL), CODE FLASH Page1 */
FC_CODE_FLASH_PAGE2, /*!< (0x5E002000UL), CODE FLASH Page2 */
FC_CODE_FLASH_PAGE3, /*!< (0x5E003000UL), CODE FLASH Page3 */
FC_CODE_FLASH_PAGE4, /*!< (0x5E004000UL), CODE FLASH Page4 */
FC_CODE_FLASH_PAGE5, /*!< (0x5E005000UL), CODE FLASH Page5 */
FC_CODE_FLASH_PAGE6, /*!< (0x5E006000UL), CODE FLASH Page6 */
FC_CODE_FLASH_PAGE7, /*!< (0x5E007000UL), CODE FLASH Page7 */
FC_CODE_FLASH_PAGE8, /*!< (0x5E008000UL), CODE FLASH Page8 */
FC_CODE_FLASH_PAGE9, /*!< (0x5E009000UL), CODE FLASH Page9 */
FC_CODE_FLASH_PAGE10, /*!< (0x5E00A000UL), CODE FLASH Page10 */
FC_CODE_FLASH_PAGE11, /*!< (0x5E00B000UL), CODE FLASH Page11 */
FC_CODE_FLASH_PAGE12, /*!< (0x5E00C000UL), CODE FLASH Page12 */
FC_CODE_FLASH_PAGE13, /*!< (0x5E00D000UL), CODE FLASH Page13 */
FC_CODE_FLASH_PAGE14, /*!< (0x5E00E000UL), CODE FLASH Page14 */
FC_CODE_FLASH_PAGE15, /*!< (0x5E00F000UL), CODE FLASH Page15 */
FC_CODE_FLASH_PAGE16, /*!< (0x5E010000UL), CODE FLASH Page16 */
FC_CODE_FLASH_PAGE17, /*!< (0x5E011000UL), CODE FLASH Page17 */
FC_CODE_FLASH_PAGE18, /*!< (0x5E012000UL), CODE FLASH Page18 */
FC_CODE_FLASH_PAGE19, /*!< (0x5E013000UL), CODE FLASH Page19 */
FC_CODE_FLASH_PAGE20, /*!< (0x5E014000UL), CODE FLASH Page20 */
FC_CODE_FLASH_PAGE21, /*!< (0x5E015000UL), CODE FLASH Page21 */
FC_CODE_FLASH_PAGE22, /*!< (0x5E016000UL), CODE FLASH Page22 */
FC_CODE_FLASH_PAGE23, /*!< (0x5E017000UL), CODE FLASH Page23 */
FC_CODE_FLASH_PAGE24, /*!< (0x5E018000UL), CODE FLASH Page24 */
FC_CODE_FLASH_PAGE25, /*!< (0x5E019000UL), CODE FLASH Page25 */
FC_CODE_FLASH_PAGE26, /*!< (0x5E01A000UL), CODE FLASH Page26 */
FC_CODE_FLASH_PAGE27, /*!< (0x5E01B000UL), CODE FLASH Page27 */
FC_CODE_FLASH_PAGE28, /*!< (0x5E01C000UL), CODE FLASH Page28 */
FC_CODE_FLASH_PAGE29, /*!< (0x5E01D000UL), CODE FLASH Page29 */
FC_CODE_FLASH_PAGE30, /*!< (0x5E01E000UL), CODE FLASH Page30 */
FC_CODE_FLASH_PAGE31 /*!< (0x5E01F000UL), CODE FLASH Page31 */
} fc_code_flash_page_number_t;
/** @} */
/* End of group FlashApi_Exported_Types */
/** @defgroup FlashApi_Exported_Constants
* @{
*/
//#define FC_RAMADDRESSTOP (0x20000000UL) /*!< RAM Address Top */
//#define FC_RAMADDRESSEND (0x20003fffUL) /*!< RAM Address End */
#define FC_CODE_FLASH_ADDRESS_TOP (0x5E000000UL) /*!< CODE FLASH Address Top */
//#define FC_CODEFLASHADDRESSEND (0x5E01FFFFUL) /*!< CODE FLASH Address End */
#define FC_PAGE_SIZE (0x1000) /*!< The number of bytes in a page. */
//#define FC_CODEFLASHPAGESIZE (0x1000) /*!< CODE FLASH PAGE SIZE */
#define FC_CODE_FLASH_WRITE_SIZE (sizeof(uint32_t)*4) /*!< CODE FLASH WRITE SIZE */
/** @} */
/* End of group FlashApi_Exported_Constants */
/** @weakgroup FlashApi_Exported_FunctionPrototypes
* @{
*/
TXZ_WorkState fc_get_status(fc_sr0_t status);
TXZ_Result fc_write_code_flash(uint32_t *src_address, uint32_t *dst_address, uint32_t size);
TXZ_Result fc_erase_page_code_flash(fc_code_flash_page_number_t first_page, uint8_t num_of_pages);
TXZ_Result fc_blank_check_page_code_flash(fc_code_flash_page_number_t first_page, fc_code_flash_page_number_t lasr_page);
TXZ_Result fc_erase_block_code_flash(uint32_t *top_addr, uint32_t *blk_addr);
/** @} */
/* End of group FlashApi_Exported_FunctionPrototypes */
/** @} */
/* End of group fc */
/** @} */
/* End of group Periph_driver */
#endif /* defined(__FC_H) */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __FC_H */

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/**
*******************************************************************************
* @file txz_flash.h
* @brief This file provides all the functions prototypes for driver common part.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __FLASH_H
#define __FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_driver_def.h"
/**
* @addtogroup Periph_Driver
* @{
*/
/**
* @defgroup FLASH FLASH
* @brief FLASH Driver.
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup FLASH_Exported_macro FLASH Exported Macro
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FLASH_Exported_macro */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup FLASH_Exported_define FLASH Exported Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FLASH_Exported_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup FLASH_Exported_define FLASH Exported Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FLASH_Exported_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup FLASH_Exported_typedef FLASH Exported Typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FLASH_Exported_typedef */
/*------------------------------------------------------------------------------*/
/* Functions */
/*------------------------------------------------------------------------------*/
/**
* @defgroup FLASH_Exported_functions FLASH Exported Functions
* @{
*/
void fc_read_clock_set(uint32_t sysclock);
/**
* @}
*/ /* End of group FLASH_Exported_functions */
/**
* @}
*/ /* End of group FLASH */
/**
* @}
*/ /* End of group Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __FLASH_H */

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/**
*******************************************************************************
* @file txz_fuart.h
* @brief This file provides all the functions prototypes for FUART driver.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __FUART_H
#define __FUART_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_driver_def.h"
/**
* @addtogroup Periph_Driver
* @{
*/
/**
* @defgroup FUART FUART
* @brief FUART Driver.
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup FUART_Exported_define FUART Exported Define
* @{
*/
/**
* @defgroup FUART_FifoMax Max Num of FIFO
* @brief Max Num of Tx/Rx Fifo.
* @{
*/
#define FUART_TX_FIFO_MAX ((uint32_t)0x00000020) /*!< TX FIFO Max. */
#define FUART_RX_FIFO_MAX ((uint32_t)0x00000020) /*!< RX FIFO Max. */
/**
* @}
*/ /* End of group UART_FifoMax */
/**
* @defgroup FUART_CTSHandshake CTS Handshake
* @brief Available CTS Handshake Macro Definition.
* @{
*/
#define FUART_CTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
#define FUART_CTS_ENABLE ((uint32_t)0x00008000) /*!< Available. */
/**
* @}
*/ /* End of group FUART_CTSHandshake */
/**
* @defgroup FUART_RTSHandshake RTS Handshake
* @brief Available RTS Handshake Macro Definition.
* @{
*/
#define FUART_RTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
#define FUART_RTS_ENABLE ((uint32_t)0x00004000) /*!< Available. */
/**
* @}
*/ /* End of group FUART_RTSHandshake */
/**
* @defgroup FUART_FIFO FIFO Enable
* @brief FIFO Enable Bit Macro Definition.
* @{
*/
#define FUART_FIFO_DISABLE ((uint32_t)0x00000000) /*!< Disable. */
#define FUART_FIFO_ENABLE ((uint32_t)0x00000010) /*!< Enable. */
/**
* @}
*/ /* End of group FUART_FIFO */
/**
* @defgroup FUART_StopBit Stop Bit
* @brief Stop Bit Macro Definition.
* @{
*/
#define FUART_STOP_BIT_1 ((uint32_t)0x00000000) /*!< 1 bit */
#define FUART_STOP_BIT_2 ((uint32_t)0x00000008) /*!< 2 bit */
/**
* @}
*/ /* End of group FUART_StopBit */
/**
* @defgroup FUART_ParityBit Parity Bit
* @brief Parity Bit Macro Definition.
* @{
*/
#define FUART_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */
#define FUART_PARITY_BIT_EVEN ((uint32_t)0x00000004) /*!< Even Parity */
/**
* @}
*/ /* End of group FUART_ParityBit */
/**
* @defgroup FUART_ParityEnable Parity Enable
* @brief Enable/Disable Parity Macro Definition.
* @{
*/
#define FUART_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */
#define FUART_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */
/**
* @}
*/ /* End of group FUART_ParityEnable */
/**
* @defgroup FUART_StaticParityEnable Static Parity Enable
* @brief Enable/Disable Static Parity Macro Definition.
* @{
*/
#define FUART_STATIC_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */
#define FUART_STATIC_PARITY_ENABLE ((uint32_t)0x00000080) /*!< Enable */
/**
* @}
*/ /* End of group FUART_ParityEnable */
/**
* @defgroup FUART_DataLength Data Length
* @brief Data Length Macro Definition.
* @{
*/
#define FUART_DATA_LENGTH_5 ((uint32_t)0x00000000) /*!< 5 bit */
#define FUART_DATA_LENGTH_6 ((uint32_t)0x00000020) /*!< 6 bit */
#define FUART_DATA_LENGTH_7 ((uint32_t)0x00000040) /*!< 7 bit */
#define FUART_DATA_LENGTH_8 ((uint32_t)0x00000060) /*!< 8 bit */
/**
* @}
*/ /* End of group FUART_DataLength */
/**
* @defgroup FUART_FIFO_Level FIFO Level
* @brief FIFO Level Macro Definition.
* @{
*/
#define FUART_FIFO_LEVEL_4 ((uint32_t)0x00000000) /*!< 4 level */
#define FUART_FIFO_LEVEL_8 ((uint32_t)0x00000001) /*!< 8 level */
#define FUART_FIFO_LEVEL_16 ((uint32_t)0x00000002) /*!< 16 level */
#define FUART_FIFO_LEVEL_24 ((uint32_t)0x00000003) /*!< 24 level */
#define FUART_FIFO_LEVEL_28 ((uint32_t)0x00000004) /*!< 28 level */
/**
* @}
*/ /* End of group FUART_DataLength */
/**
* @defgroup FUART_TxInterrupt Tx Interrupt
* @brief Available Transmit Interrupt Macro Definition.
* @{
*/
#define FUART_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
#define FUART_TX_INT_ENABLE ((uint32_t)0x00000020) /*!< Available. */
/**
* @}
*/ /* End of group FUART_TxInterrupt */
/**
* @defgroup FUART_RxInterrupt Rx Interrupt
* @brief Available Receive Interrupt Macro Definition.
* @{
*/
#define FUART_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
#define FUART_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Available. */
/**
* @}
*/ /* End of group FUART_RxInterrupt */
/**
* @defgroup FUART_ErrorInterrupt Error Interrupt
* @brief Enable/Disable Error Interrupt Macro Definition.
* @{
*/
/**
* @defgroup FUART_OVER_RUN_ErrorInterrupt Over Run Error Interrupt
* @brief Enable/Disable Error Interrupt Macro Definition.
* @{
*/
#define FUART_OV_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
#define FUART_OV_ERR_INT_ENABLE ((uint32_t)0x00000400) /*!< Enable */
/**
* @}
*/ /* End of group FUART_OVER_RUN_ErrorInterrupt */
/**
* @defgroup FUART_BREAK_ErrorInterrupt Break Error Interrupt
* @brief Enable/Disable Error Interrupt Macro Definition.
* @{
*/
#define FUART_BK_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
#define FUART_BK_ERR_INT_ENABLE ((uint32_t)0x00000200) /*!< Enable */
/**
* @}
*/ /* End of group FUART_BREAK_ErrorInterrupt */
/**
* @defgroup FUART_PARITY_ErrorInterrupt Parity Error Interrupt
* @brief Enable/Disable Error Interrupt Macro Definition.
* @{
*/
#define FUART_PA_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
#define FUART_PA_ERR_INT_ENABLE ((uint32_t)0x00000100) /*!< Enable */
/**
* @}
*/ /* End of group FUART_PARITY_ErrorInterrupt */
/**
* @defgroup FUART_FRAMING_ErrorInterrupt Framing Error Interrupt
* @brief Enable/Disable Error Interrupt Macro Definition.
* @{
*/
#define FUART_FR_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
#define FUART_FR_ERR_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */
/**
* @}
*/ /* End of group FUART_FRAMING_ErrorInterrupt */
/**
* @defgroup FUART_RX_TIMEOUT_ErrorInterrupt Rx Timeout Error Interrupt
* @brief Enable/Disable Error Interrupt Macro Definition.
* @{
*/
#define FUART_TO_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
#define FUART_TO_ERR_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */
/**
* @}
*/ /* End of group FUART_RX_TIMEOUT_RUN_ErrorInterrupt */
/**
* @}
*/ /* End of group FUART_ErrorInterrupt */
/**
* @defgroup FUART_RangeK Range K
* @brief Range of K Macro Definition.
* @brief Range of K be set "(UART_RANGE_K_MIN <= Value <= FUART_RANGE_K_MAX)".
* @{
*/
#define FUART_RANGE_K_MIN ((uint32_t)0x00000000) /*!< Minimum Value :K=0 */
#define FUART_RANGE_K_MAX ((uint32_t)0x0000003F) /*!< Maximum Value :K=63 */
/**
* @}
*/ /* End of group FUART_RangeK */
/**
* @defgroup FUART_RangeN Range N
* @brief Range of N Macro Definition.
* @brief Range of N be set "(UART_RANGE_N_MIN <= Value <= FUART_RANGE_N_MAX)".
* @{
*/
#define FUART_RANGE_N_MIN ((uint32_t)0x00000002) /*!< Minimum Value :N=2 */
#define FUART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /*!< Maximum Value :N=65535 */
/**
* @}
*/ /* End of group FUART_RangeN */
/**
* @defgroup FUART_OverrunErr Overrun Error
* @brief Overrun Error Macro Definition.
* @{
*/
#define FUART_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
#define FUART_OVERRUN_ERR ((uint32_t)0x00000008) /*!< Error */
/**
* @}
*/ /* End of group FUART_OverrunErr */
/**
* @defgroup FUART_BreakErr Break Error
* @brief Break Error Macro Definition.
* @{
*/
#define FUART_BREAK_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
#define FUART_BREAK_ERR ((uint32_t)0x00000004) /*!< Error */
/**
* @}
*/ /* End of group FUART_BreakErr */
/**
* @defgroup FUART_ParityErr Parity Error
* @brief Parity Error Macro Definition.
* @{
*/
#define FUART_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
#define FUART_PARITY_ERR ((uint32_t)0x00000002) /*!< Error */
/**
* @}
*/ /* End of group FUART_ParityErr */
/**
* @defgroup FUART_FramingErr Framing Error
* @brief Framing Error Macro Definition.
* @{
*/
#define FUART_FRAMING_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
#define FUART_FRAMING_ERR ((uint32_t)0x00000001) /*!< Error */
/**
* @}
*/ /* End of group FUART_FramingErr */
/**
* @defgroup FUARTxFR FUARTxFR Register
* @brief FUARTxFR Register Definition.
* @{
*/
/* FR */
#define FUARTxFR_TXFE_MASK ((uint32_t)0x00000080) /*!< TXFE :Mask */
#define FUARTxFR_RXFF_MASK ((uint32_t)0x00000040) /*!< RXFF :Mask */
#define FUARTxFR_TXFF_MASK ((uint32_t)0x00000020) /*!< TXFF :Mask */
#define FUARTxFR_RXFE_MASK ((uint32_t)0x00000010) /*!< RXFE :Mask */
#define FUARTxFR_BUSY_MASK ((uint32_t)0x00000008) /*!< BUSY :Mask */
#define FUARTxFR_CTS_MASK ((uint32_t)0x00000001) /*!< CTS :Mask */
#define FUARTxFR_TXFE_FLAG_SET ((uint32_t)0x00000080) /*!< TXFE :Flag Set */
#define FUARTxFR_RXFF_FLAG_SET ((uint32_t)0x00000040) /*!< RXFF :Flag Set */
#define FUARTxFR_TXFF_FLAG_SET ((uint32_t)0x00000020) /*!< TXFF :Flag Set */
#define FUARTxFR_RXFE_FLAG_SET ((uint32_t)0x00000010) /*!< RXFE :Flag Set */
#define FUARTxFR_BUSY_FLAG_SET ((uint32_t)0x00000008) /*!< BUSY :Flag Set */
#define FUARTxFR_CTS_FLAG_SET ((uint32_t)0x00000001) /*!< CTS :Flag Set */
#define FUARTxFR_TXFE_FLAG_CLR ((uint32_t)0x00000000) /*!< TXFE :Flag Clear */
#define FUARTxFR_RXFF_FLAG_CLR ((uint32_t)0x00000000) /*!< RXFF :Flag Clear */
#define FUARTxFR_TXFF_FLAG_CLR ((uint32_t)0x00000000) /*!< TXFF :Flag Clear */
#define FUARTxFR_RXFE_FLAG_CLR ((uint32_t)0x00000000) /*!< RXFE :Flag Clear */
#define FUARTxFR_BUSY_FLAG_CLR ((uint32_t)0x00000000) /*!< BUSY :Flag Clear */
#define FUARTxFR_CTS_FLAG_CLR ((uint32_t)0x00000000) /*!< CTS :Flag Clear */
/**
* @}
*/ /* End of group FUARTxFR */
/**
* @}
*/ /* End of group FUART_Exported_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup FUART_Exported_define FUART Exported Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FUART_Exported_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup FUART_Exported_typedef FUART Exported Typedef
* @{
*/
/*----------------------------------*/
/**
* @brief Receive event information structure definition.
*/
/*----------------------------------*/
typedef struct {
uint8_t *p_data; /*!< The buffer to receive data. */
uint32_t num; /*!< The number of receive data. */
} fuart_receive_t;
/*----------------------------------*/
/**
* @brief Transmit data information structure definition.
*/
/*----------------------------------*/
typedef struct {
uint8_t *p_data; /*!< The buffer to transmit data. */
uint32_t num; /*!< The number of transmit data. */
} fuart_transmit_t;
/*----------------------------------*/
/**
* @brief Boudrate setting structure definition.
*/
/*----------------------------------*/
typedef struct {
uint32_t brk; /*!< Division Value K.
: K Range ( FUART_RANGE_K_MIN <= K =< FUART_RANGE_K_MAX ) @ref FUART_RangeK */
uint32_t brn; /*!< Division Value N.
: N Range ( FUART_RANGE_N_MIN <= N =< FUART_RANGE_N_MAX ) @ref FUART_RangeN */
} fuart_boudrate_t;
/*----------------------------------*/
/**
* @brief Transmit FIFO setting.
*/
/*----------------------------------*/
typedef struct {
uint32_t inttx; /*!< Available Transmit Interrupt.
: Use @ref FUART_TxInterrupt */
uint32_t level; /*!< Transmit Fill Level.
: Use @ref FUART_FIFO_Level */
} fuart_tx_int_t;
/*----------------------------------*/
/**
* @brief Receive FIFO setting.
*/
/*----------------------------------*/
typedef struct {
uint32_t intrx; /*!< Available Receive Interrupt.
: Use @ref FUART_RxInterrupt */
uint32_t level; /*!< Receive Fill Level.
: Use @ref FUART_FIFO_Level */
} fuart_rx_int_t;
/*----------------------------------*/
/**
* @brief Initial setting structure definition.
*/
/*----------------------------------*/
typedef struct {
uint32_t id; /*!< ID: User value. */
fuart_boudrate_t boudrate; /*!< Boudrate setting.
: Use @ref fuart_boudrate_t */
uint32_t interr; /*!< Available Error Interrupt.
: Use @ref FUART_ErrorInterrupt */
fuart_tx_int_t tx_int; /*!< Transmit Interrupt setting.
: Use @ref fuart_tx_int_t */
fuart_rx_int_t rx_int; /*!< Receive Interrupt setting.
: Use @ref fuart_rx_int_t */
uint32_t ctse; /*!< Available CTS Handshake.
: Use @ref FUART_CTSHandshake */
uint32_t rtse; /*!< Available RTS Handshake.
: Use @ref FUART_RTSHandshake */
uint32_t stpa; /*!< Enable/Disable Static Parity.
: Use @ref FUART_StaticParityEnable */
uint32_t sm; /*!< Data Length.
: Use @ref FUART_DataLength */
uint32_t fifo; /*!< Available FIFO.
: Use @ref FUART_FIFO */
uint32_t sblen; /*!< Stop Bit.
: Use @ref FUART_StopBit */
uint32_t even; /*!< Odd/Even Parity Bit.
: Use @ref FUART_ParityBit */
uint32_t pe; /*!< Enable/Disable Parity Bit.
: Use @ref FUART_ParityEnable */
} fuart_initial_setting_t;
/*----------------------------------*/
/**
* @brief FUART handle structure definition.
*/
/*----------------------------------*/
typedef struct {
TSB_FURT_TypeDef *p_instance; /*!< Registers base address. */
fuart_initial_setting_t init; /*!< Initial setting. */
/*------------------------------------------*/
/*!
@brief Transmit Information.
*/
/*------------------------------------------*/
struct {
uint32_t rp; /*!< Num of transmitted data. */
fuart_transmit_t info; /*!< Transmit Data Information. */
void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */
} transmit;
/*------------------------------------------*/
/*!
@brief Receive Information.
*/
/*------------------------------------------*/
struct {
uint32_t wp; /*!< Num of received data. */
fuart_receive_t info; /*!< Receive Data Information. */
void (*handler)(uint32_t id, TXZ_Result result, fuart_receive_t *p_info); /*!< Receive Event handler. */
} receive;
} fuart_t;
/**
* @}
*/ /* End of group FUART_Exported_typedef */
/*------------------------------------------------------------------------------*/
/* Functions */
/*------------------------------------------------------------------------------*/
/**
* @defgroup FUART_Exported_functions FUART Exported Functions
* @{
*/
TXZ_Result fuart_init(fuart_t *p_obj);
TXZ_Result fuart_deinit(fuart_t *p_obj);
TXZ_Result fuart_discard_transmit(fuart_t *p_obj);
TXZ_Result fuart_discard_receive(fuart_t *p_obj);
TXZ_Result fuart_transmitIt(fuart_t *p_obj, fuart_transmit_t *p_info);
TXZ_Result fuart_receiveIt(fuart_t *p_obj, fuart_receive_t *p_info);
void fuart_transmit_irq_handler(fuart_t *p_obj);
void fuart_receive_irq_handler(fuart_t *p_obj);
void fuart_error_irq_handler(fuart_t *p_obj);
void fuart_irq_handler(fuart_t *p_obj);
TXZ_Result fuart_get_status(fuart_t *p_obj, uint32_t *p_status);
TXZ_Result fuart_get_error(fuart_t *p_obj, uint32_t *p_error);
TXZ_Result fuart_get_boudrate_setting(uint32_t clock, uint32_t boudrate, fuart_boudrate_t *p_setting);
/**
* @}
*/ /* End of group FUART_Exported_functions */
/**
* @}
*/ /* End of group FUART */
/**
* @}
*/ /* End of group Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __UART_H */

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/**
*******************************************************************************
* @file txz_fuart_ex.h
* @brief This file provides all the functions prototypes for FUART driver.
* @brief Extended functionality.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __FUART_EX_H
#define __FUART_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_driver_def.h"
#include "txz_fuart.h"
/**
* @addtogroup Periph_Driver
* @{
*/
/**
* @addtogroup FUART
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup FUART_Exported_define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FUART_Exported_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup FUART_Exported_define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FUART_Exported_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup FUART_Exported_typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FUART_Exported_typedef */
/*------------------------------------------------------------------------------*/
/* Functions */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup FUART_Exported_functions
* @{
*/
TXZ_Result fuart_send_break(fuart_t *p_obj);
TXZ_Result fuart_stop_break(fuart_t *p_obj);
/**
* @}
*/ /* End of group FUART_Exported_functions */
/**
* @}
*/ /* End of group FUART */
/**
* @}
*/ /* End of group Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __FUART_EX_H */

398
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/**
*******************************************************************************
* @file txz_fuart_include.h
* @brief This file provides internal common definition.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __FUART_INCLUDE_H
#define __FUART_INCLUDE_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_driver_def.h"
/**
* @addtogroup Periph_Driver
* @{
*/
/**
* @addtogroup FUART
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup FUART_Private_define
* @{
*/
/**
* @defgroup FUART_NullPointer Null Pointer
* @brief Null Pointer.
* @{
*/
#define FUART_NULL ((void *)0) /*!< Null Pointer. */
/**
* @}
*/ /* End of group FUART_NullPointer */
/**
* @defgroup FUART_ParameterResult Parameter Check Result
* @brief Whether the parameter is specified or not.
* @{
*/
#define FUART_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */
#define FUART_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */
/**
* @}
*/ /* End of group FUART_ParameterResult */
/**
* @defgroup FUARTxDR FUARTxDR Register
* @brief FUARTxDR Register Definition.
* @{
*/
/* DR */
#define FUARTxDR_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */
/**
* @}
*/ /* End of group FUARTxDR */
/**
* @defgroup FUARTxCR FUARTxCR Register
* @brief FUARTxCR Register Definition.
* @{
*/
#define FUARTxCR_CTSEN_MASK ((uint32_t)0x00008000) /*!< CTSEN :MASK. */
#define FUARTxCR_RTSEN_MASK ((uint32_t)0x00004000) /*!< RTSEN :MASK. */
#define FUARTxCR_RXE_MASK ((uint32_t)0x00000200) /*!< RXE :MASK. */
#define FUARTxCR_TXE_MASK ((uint32_t)0x00000100) /*!< TXE :MASK. */
#define FUARTxCR_UARTEN_MSK ((uint32_t)0x00000001) /*!< UARTEN :MASK. */
#define FUARTxCR_CTSEN_DISABLE ((uint32_t)0x00000000) /*!< CTSEN :Not Available. */
#define FUARTxCR_RTSEN_DISABLE ((uint32_t)0x00000000) /*!< RTSEN :Not Available. */
#define FUARTxCR_RXE_DISABLE ((uint32_t)0x00000000) /*!< RXE :Disable. */
#define FUARTxCR_TXE_DISABLE ((uint32_t)0x00000000) /*!< TXE :Disable. */
#define FUARTxCR_UARTEN_DISABLE ((uint32_t)0x00000000) /*!< UARTEN :Disable. */
#define FUARTxCR_CTSEN_ENABLE ((uint32_t)0x00008000) /*!< CTSEN :Available. */
#define FUARTxCR_RTSEN_ENABLE ((uint32_t)0x00004000) /*!< RTSEN :Available. */
#define FUARTxCR_RXE_ENABLE ((uint32_t)0x00000200) /*!< RXE :Enable. */
#define FUARTxCR_TXE_ENABLE ((uint32_t)0x00000100) /*!< TXE :Enable. */
#define FUARTxCR_UARTEN_ENABLE ((uint32_t)0x00000001) /*!< UARTEN :Enable. */
/**
* @}
*/ /* End of group FUARTxRSR */
/**
* @defgroup FUARTxRSR FUARTxRSR Register
* @brief FUARTxRSR Register Definition.
* @{
*/
#define FUARTxRSR_OE_MASK ((uint32_t)0x00000008) /*!< OE :Mask */
#define FUARTxRSR_BE_MASK ((uint32_t)0x00000004) /*!< BE :Mask */
#define FUARTxRSR_PE_MASK ((uint32_t)0x00000002) /*!< PE :Mask */
#define FUARTxRSR_FE_MASK ((uint32_t)0x00000001) /*!< FE :Mask */
#define FUARTxRSR_OE_ERR ((uint32_t)0x00000008) /*!< OE :Error */
#define FUARTxRSR_BE_ERR ((uint32_t)0x00000004) /*!< BE :Error */
#define FUARTxRSR_PE_ERR ((uint32_t)0x00000002) /*!< PE :Error */
#define FUARTxRSR_FE_ERR ((uint32_t)0x00000001) /*!< FE :Error */
/**
* @}
*/ /* End of group FUARTxRSR */
/**
* @defgroup FUARTxECR FUARTxECR Register
* @brief FUARTxECR Register Definition.
* @{
*/
/* ECR */
#define FUARTxECR_OE_MASK ((uint32_t)0x00000008) /*!< OE :Mask */
#define FUARTxECR_BE_MASK ((uint32_t)0x00000004) /*!< BE :Mask */
#define FUARTxECR_PE_MASK ((uint32_t)0x00000002) /*!< PE :Mask */
#define FUARTxECR_FE_MASK ((uint32_t)0x00000001) /*!< FE :Mask */
#define FUARTxECR_OE_CLR ((uint32_t)0x00000008) /*!< OE :Clear */
#define FUARTxECR_BE_CLR ((uint32_t)0x00000004) /*!< BE :Clear */
#define FUARTxECR_PE_CLR ((uint32_t)0x00000002) /*!< PE :Clear */
#define FUARTxECR_FE_CLR ((uint32_t)0x00000001) /*!< FE :Clear */
/**
* @}
*/ /* End of group FUARTxECR */
/**
* @defgroup FUARTxLCR_H FUARTxRSR Register
* @brief FUARTxLCR_H Register Definition.
* @{
*/
#define FUARTxLCR_H_BRK_MASK ((uint32_t)0x00000001) /*!< BRK :Mask */
#define FUARTxLCR_H_BRK_SEND ((uint32_t)0x00000001) /*!< BRK :Send */
#define FUARTxLCR_H_BRK_STOP ((uint32_t)0x00000000) /*!< BRK :Stop */
/**
* @}
*/ /* End of group FUARTxLCR_H */
/**
* @defgroup FUARTxRIS FUARTxRIS Register
* @brief FUARTxRIS Register Definition.
* @{
*/
#define FUARTxRIS_OERIS_MASK ((uint32_t)0x00000400) /*!< OERIS :Mask */
#define FUARTxRIS_BERIS_MASK ((uint32_t)0x00000200) /*!< BERIS :Mask */
#define FUARTxRIS_PERIS_MASK ((uint32_t)0x00000100) /*!< PRRIS :Mask */
#define FUARTxRIS_FERIS_MASK ((uint32_t)0x00000080) /*!< FERIS :Mask */
#define FUARTxRIS_RTRIS_MASK ((uint32_t)0x00000040) /*!< RTRIS :Mask */
#define FUARTxRIS_TXRIS_MASK ((uint32_t)0x00000020) /*!< TXRIS :Mask */
#define FUARTxRIS_RXRIS_MASK ((uint32_t)0x00000010) /*!< RXRIS :Mask */
#define FUARTxRIS_OERIS_REQ ((uint32_t)0x00000400) /*!< OERIS :Request */
#define FUARTxRIS_BERIS_REQ ((uint32_t)0x00000200) /*!< BERIS :Request */
#define FUARTxRIS_PERIS_REQ ((uint32_t)0x00000100) /*!< PRRIS :Request */
#define FUARTxRIS_FERIS_REQ ((uint32_t)0x00000080) /*!< FERIS :Request */
#define FUARTxRIS_RTRIS_REQ ((uint32_t)0x00000040) /*!< RTRIS :Request */
#define FUARTxRIS_TXRIS_REQ ((uint32_t)0x00000020) /*!< TXRIS :Request */
#define FUARTxRIS_RXRIS_REQ ((uint32_t)0x00000010) /*!< RXRIS :Request */
/**
* @}
*/ /* End of group FUARTxRIS */
/**
* @defgroup FUARTxMIS FUARTxMIS Register
* @brief FUARTxMIS Register Definition.
* @{
*/
#define FUARTxMIS_OEMIS_MASK ((uint32_t)0x00000400) /*!< OEMIS :Mask */
#define FUARTxMIS_BEMIS_MASK ((uint32_t)0x00000200) /*!< BEMIS :Mask */
#define FUARTxMIS_PEMIS_MASK ((uint32_t)0x00000100) /*!< PRMIS :Mask */
#define FUARTxMIS_FEMIS_MASK ((uint32_t)0x00000080) /*!< FEMIS :Mask */
#define FUARTxMIS_RTMIS_MASK ((uint32_t)0x00000040) /*!< RTMIS :Mask */
#define FUARTxMIS_TXMIS_MASK ((uint32_t)0x00000020) /*!< TXMIS :Mask */
#define FUARTxMIS_RXMIS_MASK ((uint32_t)0x00000010) /*!< RXMIS :Mask */
#define FUARTxMIS_OEMIS_REQ ((uint32_t)0x00000400) /*!< OEMIS :Request */
#define FUARTxMIS_BEMIS_REQ ((uint32_t)0x00000200) /*!< BEMIS :Request */
#define FUARTxMIS_PEMIS_REQ ((uint32_t)0x00000100) /*!< PRMIS :Request */
#define FUARTxMIS_FEMIS_REQ ((uint32_t)0x00000080) /*!< FEMIS :Request */
#define FUARTxMIS_RTMIS_REQ ((uint32_t)0x00000040) /*!< RTMIS :Request */
#define FUARTxMIS_TXMIS_REQ ((uint32_t)0x00000020) /*!< TXMIS :Request */
#define FUARTxMIS_RXMIS_REQ ((uint32_t)0x00000010) /*!< RXMIS :Request */
/**
* @}
*/ /* End of group FUARTxMIS */
/**
* @defgroup FUARTxICR FUARTxICR Register
* @brief FUARTxICR Register Definition.
* @{
*/
#define FUARTxICR_OEIC_MASK ((uint32_t)0x00000400) /*!< OEIC :Mask */
#define FUARTxICR_BEIC_MASK ((uint32_t)0x00000200) /*!< BEIC :Mask */
#define FUARTxICR_PEIC_MASK ((uint32_t)0x00000100) /*!< PRIC :Mask */
#define FUARTxICR_FEIC_MASK ((uint32_t)0x00000080) /*!< FEIC :Mask */
#define FUARTxICR_RTIC_MASK ((uint32_t)0x00000040) /*!< RTIC :Mask */
#define FUARTxICR_TXIC_MASK ((uint32_t)0x00000020) /*!< TXIC :Mask */
#define FUARTxICR_RXIC_MASK ((uint32_t)0x00000010) /*!< RXIC :Mask */
#define FUARTxICR_OEIC_CLR ((uint32_t)0x00000400) /*!< OEIC :Request */
#define FUARTxICR_BEIC_CLR ((uint32_t)0x00000200) /*!< BEIC :Request */
#define FUARTxICR_PEIC_CLR ((uint32_t)0x00000100) /*!< PRIC :Request */
#define FUARTxICR_FEIC_CLR ((uint32_t)0x00000080) /*!< FEIC :Request */
#define FUARTxICR_RTIC_CLR ((uint32_t)0x00000040) /*!< RTIC :Request */
#define FUARTxICR_TXIC_CLR ((uint32_t)0x00000020) /*!< TXIC :Request */
#define FUARTxICR_RXIC_CLR ((uint32_t)0x00000010) /*!< RXIC :Request */
/**
* @}
*/ /* End of group FUARTxICR */
/**
* @defgroup FUARTxDMACR FUARTxDMACR Register
* @brief FUARTxDMACR Register Definition.
* @{
*/
#define FUARTxDMACR_RXDMAE_MASK ((uint32_t)0x00000001) /*!< RXDMAE :Mask */
#define FUARTxDMACR_TXDMAE_MASK ((uint32_t)0x00000002) /*!< TXDMAE :Mask */
#define FUARTxDMACR_RXDMAE_ENABLE ((uint32_t)0x00000001) /*!< RXDMAE :Enable */
#define FUARTxDMACR_TXDMAE_ENABLE ((uint32_t)0x00000002) /*!< TXDMAE :Enable */
#define FUARTxDMACR_RXDMAE_DISABLE ((uint32_t)0x00000000) /*!< RXDMAE :Disable */
#define FUARTxDMACR_TXDMAE_DISABLE ((uint32_t)0x00000000) /*!< TXDMAE :Disable */
/**
* @}
*/ /* End of group FUARTxDMACR */
/**
* @}
*/ /* End of group FUART_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup FUART_Private_define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FUART_Private_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup FUART_Private_typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FUART_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Inline Functions */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup FUART_Private_functions
* @{
*/
__STATIC_INLINE void disable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance);
__STATIC_INLINE void enable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance);
__STATIC_INLINE void disable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance);
__STATIC_INLINE void enable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance);
/*--------------------------------------------------*/
/**
* @brief Disable FUARTxCR TXE.
* @param p_instance: Instance address.
* @retval -
* @note Bitband Access
*/
/*--------------------------------------------------*/
__STATIC_INLINE void disable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance)
{
#ifdef __DEBUG__
if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) {
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 8))) = 0;
}
#else
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 8))) = 0;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Enable FUARTxCR TXE.
* @param p_instance: Instance address.
* @retval -
* @note Bitband Access
*/
/*--------------------------------------------------*/
__STATIC_INLINE void enable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance)
{
#ifdef __DEBUG__
if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) {
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 8))) = 1;
}
#else
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 8))) = 1;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Disable FUARTxCR RXE.
* @param p_instance: Instance address.
* @retval -
* @note Bitband Access
*/
/*--------------------------------------------------*/
__STATIC_INLINE void disable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance)
{
#ifdef __DEBUG__
if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) {
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 9))) = 0;
}
#else
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 9))) = 0;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Enable FUARTxCR RXE.
* @param p_instance: Instance address.
* @retval -
* @note Bitband Access
*/
/*--------------------------------------------------*/
__STATIC_INLINE void enable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance)
{
#ifdef __DEBUG__
if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) {
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 9))) = 1;
}
#else
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 9))) = 1;
#endif
}
/**
* @}
*/ /* End of group FUART_Private_functions */
/**
* @}
*/ /* End of group FUART */
/**
* @}
*/ /* End of group Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __UART_EX_H */

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/**
*******************************************************************************
* @file txz_gpio.h
* @brief This file provides all the functions prototypes for GPIO driver.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __GPIO_H
#define __GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
/** @defgroup Device_Included Device Included
* @{
*/
#if defined(TMPM4NR)
#include "txz_gpio_M4NR.h"
#elif defined(TMPM4NQ)
#include "txz_gpio_M4NQ.h"
#elif defined(TMPM4NN)
#include "txz_gpio_M4NN.h"
#else
#error "target device is non-select."
#endif
/**
* @}
*/ /* End of group Device_Included */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup GPIO_Exported_define GPIO Exported Define
* @{
*/
#define CHECK_MASK(mode, mask) ((1 << ((mode)/4)) & (mask))
#define WRITE_PORT(mode, addr, val, mask) \
do { \
if(CHECK_MASK(mode, mask)) *((uint32_t*)(addr) + (mode)/4) = (val); \
}while(0)
#define READ_PORT(mode, addr, val, mask) \
do { \
if(CHECK_MASK(mode, mask)) (*(val)) = (*((uint32_t*)(addr) + (mode)/4)); \
}while(0)
/**
* @defgroup GPIO_Result Result
* @brief GPIO Result Macro Definition.
* @{
*/
#define GPIO_RESULT_SUCCESS (0) /*!< Success */
#define GPIO_RESULT_FAILURE (-1) /*!< Failure */
#define GPIO_READ_FAILURE (0xFFFFFFFF) /*!< Failure */
/**
* @}
*/ /* End of group GPIO_Result */
/**
* @}
*/ /* End of group GPIO_Exported_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Typedef GPIO Exported Typedef
* @{
*/
/**
* @enum gpio_pinstate_t
* @brief Pin State Reset/Set Enumerated Type Definition.
*/
typedef enum {
GPIO_PIN_RESET = 0, /*!< 0: Clear */
GPIO_PIN_SET, /*!< 1: Set */
} gpio_pinstate_t;
/**
* @enum gpio_pininout_t
* @brief Pin Input/Output Enumerated Type Definition.
*/
typedef enum {
GPIO_PIN_INPUT = 0, /*!< 0: Input */
GPIO_PIN_OUTPUT, /*!< 1: Output */
GPIO_PIN_INOUT, /*!< 2: Input/Output */
GPIO_PIN_NOTINOUT, /*!< 3: Not Input/Output */
} gpio_pininout_t;
/**
* @enum gpio_mode_t
* @brief Port Mode Enumerated Type Definition.
*/
typedef enum {
GPIO_Mode_DATA = 0x0, /*!< 0x0: PxDATA */
GPIO_Mode_CR = 0x4, /*!< 0x4: PxCR */
GPIO_Mode_FR1 = 0x8, /*!< 0x8: PxFR1 */
GPIO_Mode_FR2 = 0xC, /*!< 0xC: PxFR2 */
GPIO_Mode_FR3 = 0x10, /*!< 0x10: PxFR3 */
GPIO_Mode_FR4 = 0x14, /*!< 0x14: PxFR4 */
GPIO_Mode_FR5 = 0x18, /*!< 0x18: PxFR5 */
GPIO_Mode_FR6 = 0x1C, /*!< 0x1C: PxFR6 */
GPIO_Mode_FR7 = 0x20, /*!< 0x20: PxFR7 */
GPIO_Mode_FR8 = 0x24, /*!< 0x24: PxFR8 */
GPIO_Mode_OD = 0x28, /*!< 0x28: PxOD */
GPIO_Mode_PUP = 0x2C, /*!< 0x2C: PxPUP */
GPIO_Mode_PDN = 0x30, /*!< 0x30: PxPDN */
GPIO_Mode_IE = 0x38 /*!< 0x38: PxIE */
} gpio_mode_t;
/**
* @enum gpio_mode_num
* @brief Port Mode Enumerated Num(bit num).
*/
typedef enum {
GPIO_ModeNum_DATA = 0, /*!< 0: PxDATA */
GPIO_ModeNum_CR, /*!< 1: PxCR */
GPIO_ModeNum_FR1, /*!< 2: PxFR1 */
GPIO_ModeNum_FR2, /*!< 3: PxFR2 */
GPIO_ModeNum_FR3, /*!< 4: PxFR3 */
GPIO_ModeNum_FR4, /*!< 5: PxFR4 */
GPIO_ModeNum_FR5, /*!< 6: PxFR5 */
GPIO_ModeNum_FR6, /*!< 7: PxFR6 */
GPIO_ModeNum_FR7, /*!< 8: PxFR7 */
GPIO_ModeNum_FR8, /*!< 9: PxFR8 */
GPIO_ModeNum_OD, /*!< 10: PxOD */
GPIO_ModeNum_PUP, /*!< 11: PxPUP */
GPIO_ModeNum_PDN, /*!< 12: PxPDN */
GPIO_ModeNum_IE, /*!< 13: PxIE */
GPIO_ModeNum_Max, /*!< 14: Max */
} gpio_mode_num;
/**
* @}
*/ /* End of group GPIO_Exported_Typedef */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup GPIO_Exported_Typedef GPIO Exported Typedef
* @{
*/
/**
* @}
*/ /* End of group GPIO_Exported_Typedef */
/*------------------------------------------------------------------------------*/
/* Functions */
/*------------------------------------------------------------------------------*/
/**
* @defgroup GPIO_Exported_functions GPIO Exported Functions
* @{
*/
TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group);
TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group);
TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val);
TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val);
TXZ_Result gpio_func(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, uint32_t func, gpio_pininout_t inout);
TXZ_Result gpio_SetPullUp(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val);
TXZ_Result gpio_SetPullDown(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val);
TXZ_Result gpio_SetOpenDrain(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val);
TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val);
TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate);
/**
* @}
*/ /* End of group GPIO_Exported_functions */
/**
* @}
*/ /* End of group GPIO */
#ifdef __cplusplus
}
#endif
#endif /* __GPIO_H */

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/**
*******************************************************************************
* @file txz_hal.h
* @brief This file provides all the functions prototypes for driver common part.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __HAL_H
#define __HAL_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_driver_def.h"
/**
* @addtogroup Periph_Driver
* @{
*/
/**
* @defgroup HAL HAL
* @brief HAL Driver.
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup HAL_Exported_macro HAL Exported Macro
* @{
*/
/* no define */
/**
* @}
*/ /* End of group HAL_Exported_macro */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup HAL_Exported_define HAL Exported Define
* @{
*/
#if defined ( __CC_ARM ) /* RealView Compiler */
extern uint32_t Load$$FLASH_CODE_RAM$$Base;
extern uint32_t Image$$FLASH_CODE_RAM$$Base;
extern uint32_t Load$$FLASH_CODE_RAM$$Length;
#elif defined ( __ICCARM__ ) /* IAR Compiler */
#pragma section = "FLASH_CODE_RAM"
#pragma section = "FLASH_CODE_ROM"
#endif
#if defined ( __CC_ARM ) /* RealView Compiler */
#define FLASH_API_ROM (uint32_t *)&Load$$FLASH_CODE_RAM$$Base
#define FLASH_API_RAM (uint32_t *)&Image$$FLASH_CODE_RAM$$Base
#define SIZE_FLASH_API (uint32_t)&Load$$FLASH_CODE_RAM$$Length
#elif defined ( __ICCARM__ ) /* IAR Compiler */
#define FLASH_API_ROM ((uint32_t *)__section_begin("FLASH_CODE_ROM"))
#define FLASH_API_RAM ((uint32_t *)__section_begin("FLASH_CODE_RAM"))
#define SIZE_FLASH_API ((uint32_t)__section_size("FLASH_CODE_ROM"))
#endif
/* no define */
/**
* @}
*/ /* End of group HAL_Exported_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup HAL_Exported_define HAL Exported Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group HAL_Exported_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup HAL_Exported_typedef HAL Exported Typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group HAL_Exported_typedef */
/*------------------------------------------------------------------------------*/
/* Functions */
/*------------------------------------------------------------------------------*/
/**
* @defgroup HAL_Exported_functions HAL Exported Functions
* @{
*/
void hal_inc_tick(void);
uint32_t hal_get_tick(void);
void wait(uint32_t count);
void Copy_Routine(uint32_t *dest, uint32_t *source, uint32_t size);
void fc_ram_con_reg_set(uint32_t sysclock);
/**
* @}
*/ /* End of group HAL_Exported_functions */
/**
* @}
*/ /* End of group HAL */
/**
* @}
*/ /* End of group Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __HAL_H */

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/**
*******************************************************************************
* @file txz_i2c.h
* @brief This file provides all the functions prototypes for I2C Class.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __I2C_H
#define __I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_driver_def.h"
/**
* @addtogroup Example
* @{
*/
/**
* @addtogroup UTILITIES
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Function */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_macro
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_macro */
/*------------------------------------------------------------------------------*/
/* Configuration */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_define */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_define
* @{
*/
#ifdef __DEBUG__
/**
* @name I2C_NULL Pointer
* @brief NULL Pointer.
* @{
*/
#define I2C_NULL ((void *)0)
/**
* @}
*/ /* End of name I2C_NULL Pointer */
#endif
/**
* @name I2CxST Macro Definition.
* @brief I2CxST Register Macro Definition.
* @{
*/
#define I2CxST_NACK ((uint32_t)0x00000008) /*!< NACK Interrupt Status. */
#define I2CxST_I2CBF ((uint32_t)0x00000004) /*!< I2CBF Interrupt Status. */
#define I2CxST_I2CAL ((uint32_t)0x00000002) /*!< I2CAL Interrupt Status. */
#define I2CxST_I2C ((uint32_t)0x00000001) /*!< I2C Interrupt Status. */
#define I2CxST_CLEAR ((uint32_t)0x0000000F) /*!< All Bits Clear. */
/**
* @}
*/ /* End of name I2CxST Macro Definition */
/**
* @name I2CxCR1 Macro Definition.
* @brief I2CxCR1 Register Macro Definition.
* @{
*/
#define I2CxCR1_ACK ((uint32_t)0x00000010) /*!< ACK */
#define I2CxCR1_NOACK ((uint32_t)0x00000008) /*!< NOACK */
#define I2CxCR1_BC ((uint32_t)0x000000E0) /*!< BC */
/**
* @}
*/ /* End of name I2CxCR1 Macro Definition */
/**
* @name I2CxDBR Macro Definition.
* @brief I2CxDBR Register Macro Definition.
* @{
*/
#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) /* !< DB 7-0 bits mask. */
/**
* @}
*/ /* End of name I2CxDBR Macro Definition */
/**
* @name I2CxCR2 Macro Definition.
* @brief I2CxCR2 Register Macro Definition.
* @{
*/
#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) /*!< PIN=1 */
#define I2CxCR2_I2CM_DISABLE ((uint32_t)0x00000000) /*!< I2CM=0 */
#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000008) /*!< I2CM=1 */
#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) /*!< SWRES=10 */
#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) /*!< SWRES=01 */
#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) /*!< MST=1,TRX=1,BB=1,PIN=1,I2CM=1 */
#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) /*!< MST=1,TRX=1,BB=0,PIN=1,I2CM=1 */
#define I2CxCR2_INIT ((uint32_t)0x00000008) /*!< MST=0,TRX=0,BB=0,PIN=0,I2CM=1,SWRES=00 */
/**
* @}
*/ /* End of name I2CxCR2 Macro Definition */
/**
* @name I2CxSR Macro Definition.
* @brief I2CxSR Register Macro Definition.
* @{
*/
#define I2CxSR_MST ((uint32_t)0x00000080) /*!< MST */
#define I2CxSR_TRX ((uint32_t)0x00000040) /*!< TRX */
#define I2CxSR_BB ((uint32_t)0x00000020) /*!< BB */
#define I2CxSR_PIN ((uint32_t)0x00000010) /*!< PIN */
#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */
#define I2CxSR_AAS ((uint32_t)0x00000004) /*!< AAS */
#define I2CxSR_AD0 ((uint32_t)0x00000002) /*!< AD0 */
#define I2CxSR_LRB ((uint32_t)0x00000001) /*!< LRB */
/**
* @}
*/ /* End of name I2CxSR Macro Definition */
/**
* @name I2CxPRS Macro Definition.
* @brief I2CxPRS Register Macro Definition.
* @{
*/
#define I2CxPRS_PRCK ((uint32_t)0x0000001F) /*!< PRCK */
/**
* @}
*/ /* End of name I2CxPRS Macro Definition */
/**
* @name I2CxIE Macro Definition.
* @brief I2CxIE Register Macro Definition.
* @{
*/
#define I2CxIE_SELPINCD ((uint32_t)0x00000040) /*!< SELPINCD */
#define I2CxIE_DMARI2CTX ((uint32_t)0x00000020) /*!< DMARI2CTX */
#define I2CxIE_DMARI2CRX ((uint32_t)0x00000010) /*!< DMARI2CRX */
#define I2CxIE_I2C ((uint32_t)0x00000001) /*!< INTI2C */
#define I2CxIE_CLEAR ((uint32_t)0x00000000) /*!< All Clear Setting */
/**
* @}
*/ /* End of name I2CxIE Macro Definition */
/**
* @name I2CxOP Macro Definition.
* @brief I2CxOP Register Macro Definition.
* @{
*/
#define I2CxOP_DISAL ((uint32_t)0x00000080) /*!< DISAL */
#define I2CxOP_SA2ST ((uint32_t)0x00000040) /*!< SA2ST */
#define I2CxOP_SAST ((uint32_t)0x00000020) /*!< SAST */
#define I2CxOP_RSTA ((uint32_t)0x00000008) /*!< RSTA */
#define I2CxOP_GCDI ((uint32_t)0x00000004) /*!< GDDI */
#define I2CxOP_SREN ((uint32_t)0x00000002) /*!< SREN */
#define I2CxOP_MFACK ((uint32_t)0x00000001) /*!< MFACK */
#ifndef I2C_MULTI_MASTER
#define I2CxOP_INIT ((uint32_t)0x00000084) /*!< Initial Settings. */
#else
#define I2CxOP_INIT ((uint32_t)0x00000004) /*!< Initial Settings. */
#endif
#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) /*!< Slave Initial Settings. */
/**
* @}
*/ /* End of name I2CxOP Macro Definition */
/**
* @name I2CxAR Macro Definition.
* @brief I2CxAR Register Macro Definition.
* @{
*/
#define I2CxAR_ALS ((uint32_t)0x00000001) /*!< ALS. */
#define I2CxAR_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */
#define I2CxAR2_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */
/**
* @}
*/ /* End of name I2CxAR Macro Definition */
/**
* @name I2CxPM Macro Definition.
* @brief I2CxPM Register Macro Definition.
* @{
*/
#define I2CxPM_SDA_SCL ((uint32_t)0x00000003) /* SDA and SCL level. */
/**
* @}
*/ /* End of name I2CxPM Macro Definition */
/**
* @name I2CxWUPCR_INT Macro Definition.
* @brief I2CxWUPCR_INT Register Macro Definition.
* @{
*/
#define I2CxWUPCR_INT_RELESE ((uint32_t)0x00000001) /* Interrupt Release. */
#define I2CxWUPCR_INT_HOLD ((uint32_t)0x00000000) /* Interrupt setting keep it. */
/**
* @}
*/ /* End of name I2CxWUPCR_INT Macro Definition */
/**
* @name I2CxWUPCR_RST Macro Definition.
* @brief I2CxWUPCR_RST Register Macro Definition.
* @{
*/
#define I2CxWUPCR_RST_RESET ((uint32_t)0x00000010) /* I2C BUS Reset. */
#define I2CxWUPCR_RST_RELEASE ((uint32_t)0x00000000) /* I2C BUS Reset Release. */
/**
* @}
*/ /* End of name I2CxWUPCR_RST Macro Definition */
/**
* @name I2CxWUPCR_ACK Macro Definition.
* @brief I2CxWUPCR_ACK Register Macro Definition.
* @{
*/
#define I2CxWUPCR_ACK ((uint32_t)0x00000020) /* ACK Output. Output "0" */
#define I2CxWUPCR_NACK ((uint32_t)0x00000000) /* ACL No Output. Output "1" NACK Output */
/**
* @}
*/ /* End of name I2CxWUPCR_RST Macro Definition */
/**
* @}
*/ /* End of group UTILITIES_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_typedef
* @{
*/
/*----------------------------------*/
/**
* @brief Clock setting structure definition.
*/
/*----------------------------------*/
typedef struct {
uint32_t sck; /*!< Select internal SCL output clock frequency. */
uint32_t prsck; /*!< Prescaler clock frequency for generating the Serial clock. */
} I2C_clock_setting_t;
/*----------------------------------*/
/**
* @brief Wakeup Control setting structure definition.
*/
/*----------------------------------*/
typedef struct {
uint32_t sgcdi; /*!< Select general call detect ON/OFF. */
uint32_t ack; /*!< Select ACK output. */
uint32_t reset; /*!< I2C BUS Rest. */
uint32_t intend; /*!< Interrupt release. */
} I2CS_wup_setting_t;
/*----------------------------------*/
/**
* @brief Initial setting structure definition.
*/
/*----------------------------------*/
typedef struct {
I2C_clock_setting_t clock; /*!< Serial clock setting. */
} I2C_initial_setting_t;
/*----------------------------------*/
/**
* @brief Initial setting structure definition.
*/
/*----------------------------------*/
typedef struct {
I2CS_wup_setting_t wup; /*!< Wakeup Control setting. */
} I2CS_initial_setting_t;
/*----------------------------------*/
/**
* @brief I2C handle structure definition.
*/
/*----------------------------------*/
typedef struct {
TSB_I2C_TypeDef *p_instance; /*!< Registers base address. */
I2C_initial_setting_t init; /*!< Initial setting. */
} I2C_t;
#if defined(I2CSxWUP_EN)
/*----------------------------------*/
/**
* @brief I2CS handle structure definition.
*/
/*----------------------------------*/
typedef struct {
TSB_I2CS_TypeDef *p_instance; /*!< Registers base address. */
I2CS_initial_setting_t init; /*!< Initial setting. */
} I2CS_t;
#endif
/**
* @}
*/ /* End of group UTILITIES_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Inline Functions */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_functions
* @{
*/
__STATIC_INLINE void I2C_reset(I2C_t *p_obj);
__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj);
__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj);
__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj);
__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data);
__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj);
__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack);
__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj);
__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj);
__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj);
__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj);
__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj);
__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj);
__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj);
__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx);
__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj);
__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr);
__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj);
/*--------------------------------------------------*/
/**
* @brief I2C software reset.
* @param p_obj :I2C object.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_reset(I2C_t *p_obj)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
p_obj->p_instance->CR2 = I2CxCR2_SWRES_10;
p_obj->p_instance->CR2 = I2CxCR2_SWRES_01;
}
#else
p_obj->p_instance->CR2 = I2CxCR2_SWRES_10;
p_obj->p_instance->CR2 = I2CxCR2_SWRES_01;
#endif
}
/*--------------------------------------------------*/
/**
* @brief I2C bus port high
* @param p_obj :I2C object.
* @retval true :SDA and SCL Port High.
* @retval false :Bus Error.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL));
}
return (0);
#else
return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL));
#endif
}
/*--------------------------------------------------*/
/**
* @brief Generate stop condition.
* @param p_obj :I2C object.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION;
}
#else
p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Read from Data buffer
* @param p_obj :I2C object.
* @retval result :Read data.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK);
}
return (0);
#else
return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK);
#endif
}
/*--------------------------------------------------*/
/**
* @brief Write to Data buffer.
* @param p_obj :I2C object.
* @param data :Write data.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK);
}
#else
p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK);
#endif
}
/*--------------------------------------------------*/
/**
* @brief Return restart condition
* @param p_obj :I2C object.
* @retval true :Restart Detected.
* @retval false :Restart Non-Detected.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
__IO uint32_t opreg = p_obj->p_instance->OP;
p_obj->p_instance->OP &= ~I2CxOP_RSTA;
return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA);
}
return (0);
#else
__IO uint32_t opreg = p_obj->p_instance->OP;
p_obj->p_instance->OP &= ~I2CxOP_RSTA;
return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA);
#endif
}
/*--------------------------------------------------*/
/**
* @brief Set Ack condition
* @param p_obj :I2C object.
* @param nack :1 NACK, 0 ACK.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
if (nack) {
p_obj->p_instance->OP |= I2CxOP_MFACK;
} else {
p_obj->p_instance->OP &= ~I2CxOP_MFACK;
}
}
#else
if (nack) {
p_obj->p_instance->OP |= I2CxOP_MFACK;
} else {
p_obj->p_instance->OP &= ~I2CxOP_MFACK;
}
#endif
}
/*--------------------------------------------------*/
/**
* @brief Return received Ack condition
* @param p_obj :I2C object.
* @retval true :NACK Received.
* @retval false :ACK Received.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB);
}
return (0);
#else
return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB);
#endif
}
/*--------------------------------------------------*/
/**
* @brief Return Busy condition
* @param p_obj :I2C object.
* @retval true :I2C bus busy.
* @retval false :I2C bus free.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB);
}
return (0);
#else
return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB);
#endif
}
/*--------------------------------------------------*/
/**
* @brief Return The Master status
* @param p_obj :I2C object.
* @retval true :Master mode.
* @retval false :Slave mode.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST);
}
return (0);
#else
return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST);
#endif
}
/*--------------------------------------------------*/
/**
* @brief Return The Transmitter
* @param p_obj :I2C object.
* @retval true :Transmitter.
* @retval false :Receiver.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX);
}
return (0);
#else
return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX);
#endif
}
/*--------------------------------------------------*/
/**
* @brief Interrupt Status
* @param p_obj :I2C object.
* @retval true :Interrupt Occurred.
* @retval false :No Interrupt Occurred.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C);
}
return (0);
#else
return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C);
#endif
}
/*--------------------------------------------------*/
/**
* @brief Interrupt Status Clear
* @param p_obj :I2C object.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
p_obj->p_instance->ST = I2CxST_CLEAR;
}
#else
p_obj->p_instance->ST = I2CxST_CLEAR;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Enable Interrupt setting.
* @param p_obj :I2C object.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
p_obj->p_instance->IE = I2CxIE_I2C;
}
#else
p_obj->p_instance->IE = I2CxIE_I2C;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Enable Interrupt setting.
* @param p_obj :I2C object.
* @param tx :Direction of transfer(1=tx 0=rx).
* @retval -
* @note For DMA transfer.
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
if (tx) {
p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX);
} else {
p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX);
}
}
#else
if (tx) {
p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX);
} else {
p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX);
}
#endif
}
/*--------------------------------------------------*/
/**
* @brief Disable Interrupt setting.
* @param p_obj :I2C object.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
p_obj->p_instance->IE = I2CxIE_CLEAR;
}
#else
p_obj->p_instance->IE = I2CxIE_CLEAR;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Set slave address.
* @param p_obj :I2C object.
* @param addr :slave address.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
p_obj->p_instance->AR = (addr & ~I2CxAR_ALS);
p_obj->p_instance->AR2 = I2CxAR2_INIT;
}
#else
p_obj->p_instance->AR = (addr & ~I2CxAR_ALS);
p_obj->p_instance->AR2 = I2CxAR2_INIT;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Detecting Slave Address
* @param p_obj :I2C object.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj)
{
#ifdef __DEBUG__
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS)
&& ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST));
}
return (0);
#else
return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS)
&& ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST));
#endif
}
/**
* @}
*/ /* End of group UTILITIES_Private_functions */
/*------------------------------------------------------------------------------*/
/* Functions */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_functions
* @{
*/
void I2C_init(I2C_t *p_obj);
void I2C_start_condition(I2C_t *p_obj, uint32_t data);
uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting);
void I2C_slave_init(I2C_t *p_obj);
#if defined(I2CSxWUP_EN)
void I2CS_init(I2CS_t *p_obj);
void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr);
void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr);
#endif
/**
* @}
*/ /* End of group UTILITIES_Private_functions */
/**
* @}
*/ /* End of group UTILITIES */
/**
* @}
*/ /* End of group Example */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __I2C_H */

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/**
*******************************************************************************
* @file i2c_api.h
* @brief This file provides all the functions prototypes for I2C Driver.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __BSP_I2C_H
#define __BSP_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_i2c.h"
/**
* @addtogroup Example
* @{
*/
/**
* @addtogroup UTILITIES
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Function */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Exported_macro
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Exported_macro */
/*------------------------------------------------------------------------------*/
/* Configuration */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Exported_define
* @{
*/
/**
* @defgroup I2C_NullPointer Null Pointer
* @brief I2C NULL Pointer.
* @{
*/
#define I2C_NULL ((void *)0)
/**
* @}
*/ /* End of group I2C_NullPointer */
/**
* @}
*/ /* End of group UTILITIES_Exported_define */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Exported_define
* @{
*/
/**
* @defgroup I2C_ACK I2C ACK Macros
* @brief I2C Type of Acknowledge.
* @{
*/
#define I2C_NACK (0) /*!< NACK Received. */
#define I2C_ACK (1) /*!< ACK Received. */
/**
* @}
*/ /* End of group I2C_ACK */
/**
* @defgroup I2C_ERROR I2C ERROR Macros
* @brief I2C Error definitions.
* @{
*/
#define I2C_ERROR_NO_ERROR (0) /*!< No Error. */
#if 0
#define I2C_ERROR_NO_SLAVE (-1) /*!< No Slave Error. */
#define I2C_ERROR_BUS_BUSY (-2) /*!< Bus Busy Error.(now, not support) */
#endif
#define I2C_ERROR_PARAM (-3) /*!< Parameter Error. */
#define I2C_ERROR_OTHERS (-4) /*!< Others Error. */
#define I2C_ERROR_ARBITRATION (-5) /*!< Arbitration Error. */
/**
* @}
*/ /* End of group I2C_ERROR */
/**
* @defgroup I2C_Events I2C Events Macros
* @brief I2C Asynch Events.
* @{
*/
#define I2C_EVENT_ERROR (1 << 1) /*!< Error. */
#define I2C_EVENT_ERROR_NO_SLAVE (1 << 2) /*!< No Slave. */
#define I2C_EVENT_TRANSFER_COMPLETE (1 << 3) /*!< Transfer Complete. */
#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4) /*!< End of Transfer. */
#define I2C_EVENT_ALL (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK)
/**
* @}
*/ /* End of group I2C_Events */
/**
* @defgroup I2C_SlaveReceive I2C Slave Receive Return Macros
* @brief I2C Received Contents of Slave.
* @{
*/
#define I2C_NO_DATA (0) /*!< the slave has not been addressed. */
#define I2C_READ_ADDRESSED (1) /*!< the master has requested a read from this slave. */
#define I2C_WRITE_GENERAL (2) /*!< the master is writing to all slave.(now, not support) */
#define I2C_WRITE_ADDRESSED (3) /*!< the master is writing to this slave. */
/**
* @}
*/ /* End of group I2C_SlaveReceive */
/**
* @}
*/ /* End of group UTILITIES_Exported_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Exported_define
* @{
*/
/*----------------------------------*/
/**
* @brief i2c Port Enumerated Type Definition.
*/
/*----------------------------------*/
typedef enum {
I2C_PORT_PG2 = 0, /*!< 0: PG2 I2C0 */
I2C_PORT_PG3, /*!< 1: PG3 I2C0 */
I2C_PORT_PF2, /*!< 2: PF2 I2C1 */
I2C_PORT_PF3, /*!< 3: PF3 I2C1 */
I2C_PORT_PG4, /*!< 4: PG4 I2C2 */
I2C_PORT_PG5, /*!< 5: PG5 I2C2 */
I2C_PORT_PJ6, /*!< 6: PJ6 I2C3 */
I2C_PORT_PJ7, /*!< 7: PJ7 I2C3 */
I2C_PORT_PJ2, /*!< 8: PJ2 I2C4 */
I2C_PORT_PJ3, /*!< 9: PJ3 I2C4 */
}
i2c_port_t;
/*----------------------*/
/* I2C Setting */
/*----------------------*/
/* #define I2C_CHANNEL0 */
#define I2C_CHANNEL3
/* #define I2C_CHANNEL2 */
/* #define I2C_CHANNEL3 */
/* #define I2C_CHANNEL4 */
#if defined(I2C_CHANNEL0)
#define I2Cx_TEXT "I2C0"
#define I2C_CFG_PORT_SCL (I2C_PORT_PG3) /*!< SCL Port. */
#define I2C_CFG_PORT_SDA (I2C_PORT_PG2) /*!< SDA Port. */
#elif defined(I2C_CHANNEL1)
#define I2Cx_TEXT "I2C1"
#define I2C_CFG_PORT_SCL (I2C_PORT_PF3) /*!< SCL Port. */
#define I2C_CFG_PORT_SDA (I2C_PORT_PF2) /*!< SDA Port. */
#elif defined(I2C_CHANNEL2)
#define I2Cx_TEXT "I2C2"
#define I2C_CFG_PORT_SCL (I2C_PORT_PG5) /*!< SCL Port. */
#define I2C_CFG_PORT_SDA (I2C_PORT_PG4) /*!< SDA Port. */
#elif defined(I2C_CHANNEL3)
#define I2Cx_TEXT "I2C3"
#define I2C_CFG_PORT_SCL (I2C_PORT_PJ7) /*!< SCL Port. */
#define I2C_CFG_PORT_SDA (I2C_PORT_PJ6) /*!< SDA Port. */
#elif defined(I2C_CHANNEL4)
#define I2Cx_TEXT "I2C4"
#define I2C_CFG_PORT_SCL (I2C_PORT_PJ3) /*!< SCL Port. */
#define I2C_CFG_PORT_SDA (I2C_PORT_PJ2) /*!< SDA Port. */
#else
#error "target channel is non-select."
#endif
/**
* @}
*/ /* End of group UTILITIES_Exported_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Exported_typedef
* @{
*/
/*----------------------------------*/
/**
* @brief I2C internal information structure definenition.
*/
/*----------------------------------*/
typedef struct {
uint8_t bus_free; /*!< Bus free information. */
uint8_t start; /*!< Start condition information. */
uint32_t irqn; /*!< IRQ number table pointer. */
struct {
uint32_t address; /*!< Slave address. */
uint32_t stop; /*!< Stop control */
uint32_t event; /*!< I2C Event information. */
uint32_t state; /*!< Transfer State. */
} asynch;
} i2c_internal_info_t;
/*----------------------------------*/
/**
* @brief I2C buffer structure definenition.
*/
/*----------------------------------*/
typedef struct {
uint8_t *p_buffer; /*!< Buffer address. */
uint32_t length; /*!< Buffer length. */
uint32_t pos; /*!< Buffer pointer. */
} i2c_buffer_t;
/*----------------------------------*/
/**
* @brief I2C handle structure definenition.
*/
/*----------------------------------*/
typedef struct {
I2C_t i2c; /*!< I2C class structure. */
i2c_internal_info_t info; /*!< Internal Information. */
i2c_buffer_t tx_buff; /*!< Tx buffer structure. */
i2c_buffer_t rx_buff; /*!< Rx buffer structure. */
} _i2c_t;
/**
* @}
*/ /* End of group UTILITIES_Exported_typedef */
/*------------------------------------------------------------------------------*/
/* Functions */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Exported_functions
* @{
*/
TXZ_Result i2c_init_t(_i2c_t *p_obj, i2c_port_t sda, i2c_port_t scl);
TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz);
void i2c_reset_t(_i2c_t *p_obj);
TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj);
TXZ_Result i2c_start_t(_i2c_t *p_obj);
TXZ_Result i2c_stop_t(_i2c_t *p_obj);
int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop);
int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop);
int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last);
int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data);
uint8_t i2c_active_t(_i2c_t *p_obj);
TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop);
uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj);
void i2c_abort_asynch_t(_i2c_t *p_obj);
uint32_t set_i2c(uint8_t ch, uint32_t *p_irqn);
/* For slave */
void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave);
int32_t i2c_slave_receive_t(_i2c_t *p_obj);
int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length);
int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length);
void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address);
TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length);
uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj);
void i2c_slave_abort_asynch_t(_i2c_t *p_obj);
/**
* @}
*/ /* End of group UTILITIES_Exported_functions */
/**
* @}
*/ /* End of group UTILITIES */
/**
* @}
*/ /* End of group Example */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __BSP_I2C_H */

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/**
*******************************************************************************
* @file txz_uart.h
* @brief This file provides all the functions prototypes for UART driver.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __UART_H
#define __UART_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_driver_def.h"
/**
* @addtogroup Periph_Driver
* @{
*/
/**
* @defgroup UART UART
* @brief UART Driver.
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup UART_Exported_define UART Exported Define
* @{
*/
/**
* @defgroup UART_FifoMax Max Num of FIFO
* @brief Max Num of Tx/Rx Fifo.
* @{
*/
#define UART_TX_FIFO_MAX ((uint32_t)0x00000008) /*!< TX FIFO Max. */
#define UART_RX_FIFO_MAX ((uint32_t)0x00000008) /*!< RX FIFO Max. */
/**
* @}
*/ /* End of group UART_FifoMax */
/**
* @defgroup UART_HalfClockSelect Half Clock Select
* @brief Output Terminal Select
* @{
*/
#define UART_HALF_CLOCK_UTxTXDA ((uint32_t)0x00000000) /*!< Half Clock output terminal select UTxTXDA. */
#define UART_HALF_CLOCK_UTxTXDB ((uint32_t)0x00040000) /*!< Half Clock output terminal select UTxTXDB. */
/**
* @}
*/ /* End of group UART_HalfClockSelect */
/**
* @defgroup UART_HalfClockMode Half Clock Mode
* @brief Half Clock Mode Setting.
* @{
*/
#define UART_HALF_CLOCK_MODE_1 ((uint32_t)0x00000000) /*!< Half Clock 1 terminal Mode. */
#define UART_HALF_CLOCK_MODE_2 ((uint32_t)0x00020000) /*!< Half Clock 2 terminal Mode. */
/**
* @}
*/ /* End of group UART_HalfClockMode */
/**
* @defgroup UART_HalfClockCTR Half Clock Mode Control
* @brief Half Clock Control.
* @{
*/
#define UART_HALF_CLOCK_DISABLE ((uint32_t)0x00000000) /*!< Half Clock Mode Disable. */
#define UART_HALF_CLOCK_ENABLE ((uint32_t)0x00010000) /*!< Half Clock Mode Enable. */
/**
* @}
*/ /* End of group UART_HalfClockCTR */
/**
* @defgroup UART_LoopBack Loop Back Function
* @brief Half Clock Control.
* @{
*/
#define UART_LOOPBACK_DISABLE ((uint32_t)0x00000000) /*!< Loop Back Function Disable. */
#define UART_LOOPBACK_ENABLE ((uint32_t)0x00008000) /*!< Loop Back Function Enable. */
/**
* @}
*/ /* End of group UART_LoopBack */
/**
* @defgroup UART_NoiseFilter Noise Filter
* @brief Noise Filter Setting.
* @{
*/
#define UART_NOISE_FILTER_NON ((uint32_t)0x00000000) /*!< No Filetering. */
#define UART_NOISE_FILTER_2_T0 ((uint32_t)0x00001000) /*!< A signal below the 2/T0 is filtering as noise. */
#define UART_NOISE_FILTER_4_T0 ((uint32_t)0x00002000) /*!< A signal below the 4/T0 is filtering as noise. */
#define UART_NOISE_FILTER_8_T0 ((uint32_t)0x00003000) /*!< A signal below the 8/T0 is filtering as noise. */
#define UART_NOISE_FILTER_2_CLOCK ((uint32_t)0x00004000) /*!< A signal below the 2/Clock is filtering as noise. */
#define UART_NOISE_FILTER_3_CLOCK ((uint32_t)0x00005000) /*!< A signal below the 3/Clock is filtering as noise. */
#define UART_NOISE_FILTER_4_CLOCK ((uint32_t)0x00006000) /*!< A signal below the 4/Clock is filtering as noise. */
#define UART_NOISE_FILTER_5_CLOCK ((uint32_t)0x00007000) /*!< A signal below the 5/Clock is filtering as noise */
/**
* @}
*/ /* End of group UART_NoiseFilter */
/**
* @defgroup UART_CTSHandshake CTS Handshake
* @brief Available CTS Handshake Macro Definition.
* @{
*/
#define UART_CTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
#define UART_CTS_ENABLE ((uint32_t)0x00000400) /*!< Available. */
/**
* @}
*/ /* End of group UART_CTSHandshake */
/**
* @defgroup UART_RTSHandshake RTS Handshake
* @brief Available RTS Handshake Macro Definition.
* @{
*/
#define UART_RTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
#define UART_RTS_ENABLE ((uint32_t)0x00000200) /*!< Available. */
/**
* @}
*/ /* End of group UART_RTSHandshake */
/**
* @defgroup UART_DataComplementation Data Complementation
* @brief Enable/Disable Data Signal Complementation Macro Definition.
* @{
*/
#define UART_DATA_COMPLEMENTION_DISABLE ((uint32_t)0x00000000) /*!< Disable */
#define UART_DATA_COMPLEMENTION_ENABLE ((uint32_t)0x00000040) /*!< Enable */
/**
* @}
*/ /* End of group UART_DataComplementation */
/**
* @defgroup UART_DataDirection Data Direction
* @brief Data Direction Macro Definition.
* @{
*/
#define UART_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */
#define UART_DATA_DIRECTION_MSB ((uint32_t)0x00000020) /*!< MSB first */
/*!
* @}
*/ /* End of group UART_DataDirection */
/**
* @defgroup UART_StopBit Stop Bit
* @brief Stop Bit Macro Definition.
* @{
*/
#define UART_STOP_BIT_1 ((uint32_t)0x00000000) /*!< 1 bit */
#define UART_STOP_BIT_2 ((uint32_t)0x00000010) /*!< 2 bit */
/**
* @}
*/ /* End of group UART_StopBit */
/**
* @defgroup UART_ParityBit Parity Bit
* @brief Parity Bit Macro Definition.
* @{
*/
#define UART_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */
#define UART_PARITY_BIT_EVEN ((uint32_t)0x00000008) /*!< Even Parity */
/**
* @}
*/ /* End of group UART_ParityBit */
/**
* @defgroup UART_ParityEnable Parity Enable
* @brief Enable/Disable Parity Macro Definition.
* @{
*/
#define UART_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */
#define UART_PARITY_ENABLE ((uint32_t)0x00000004) /*!< Enable */
/**
* @}
*/ /* End of group UART_ParityEnable */
/**
* @defgroup UART_DataLength Data Length
* @brief Data Length Macro Definition.
* @{
*/
#define UART_DATA_LENGTH_7 ((uint32_t)0x00000000) /*!< 7 bit */
#define UART_DATA_LENGTH_8 ((uint32_t)0x00000001) /*!< 8 bit */
#define UART_DATA_LENGTH_9 ((uint32_t)0x00000002) /*!< 9 bit */
/**
* @}
*/ /* End of group UART_DataLength */
/**
* @defgroup UART_TxFillLevelRange Tx Fill Level Range
* @brief Transmit Fill Level Range Macro Definition.
* @brief Range of Value be set "(UART_TX_FILL_LEVEL_MIN <= Value <= UART_TX_FILL_LEVEL_MAX)".
* @{
*/
#define UART_TX_FILL_RANGE_MIN ((uint32_t)0x00000000) /*!< Minimum Value :1 */
#define UART_TX_FILL_RANGE_MAX ((uint32_t)0x00000007) /*!< Maximum Value :7 */
/*!
* @}
*/ /* End of group UART_TxFillLevelRange */
/**
* @defgroup UART_RxFillLevelRange Rx Fill Level Range
* @brief Receive Fill Level Range Macro Definition.
* @brief Range of Value be set "(UART_RX_FILL_LEVEL_MIN <= Value <= UART_RX_FILL_LEVEL_MAX)".
* @{
*/
#define UART_RX_FILL_RANGE_MIN ((uint32_t)0x00000001) /*!< Minimum Value :1 */
#define UART_RX_FILL_RANGE_MAX ((uint32_t)0x00000008) /*!< Maximum Value :8 */
/**
* @}
*/ /* End of group UART_RxFillLevelRange */
/**
* @defgroup UART_TxFIFOInterrupt Tx FIFO Interrupt
* @brief Available Transmit FIFO Interrupt Macro Definition.
* @{
*/
#define UART_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
#define UART_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Available. */
/**
* @}
*/ /* End of group UART_TxFIFOInterrupt */
/**
* @defgroup UART_TxInterrupt Tx Interrupt
* @brief Available Transmit Interrupt Macro Definition.
* @{
*/
#define UART_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
#define UART_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Available. */
/**
* @}
*/ /* End of group UART_TxInterrupt */
/**
* @defgroup UART_RxFIFOInterrupt Rx FIFO Interrupt
* @brief Available Receive FIFO Interrupt Macro Definition.
* @{
*/
#define UART_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
#define UART_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Available. */
/**
* @}
*/ /* End of group UART_RxFIFOInterrupt */
/**
* @defgroup UART_RxInterrupt Rx Interrupt
* @brief Available Receive Interrupt Macro Definition.
* @{
*/
#define UART_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
#define UART_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Available. */
/**
* @}
*/ /* End of group UART_RxInterrupt */
/**
* @defgroup UART_ErrorInterrupt Error Interrupt
* @brief Enable/Disable Error Interrupt Macro Definition.
* @{
*/
#define UART_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
#define UART_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */
/**
* @}
*/ /* End of group UART_ErrorInterrupt */
/**
* @defgroup UART_Prescaler Prescaler
* @brief Prescaler Macro Definition.
* @{
*/
#define UART_PLESCALER_1 ((uint32_t)0x00000000) /*!< 1/1 */
#define UART_PLESCALER_2 ((uint32_t)0x00000010) /*!< 1/2 */
#define UART_PLESCALER_4 ((uint32_t)0x00000020) /*!< 1/4 */
#define UART_PLESCALER_8 ((uint32_t)0x00000030) /*!< 1/8 */
#define UART_PLESCALER_16 ((uint32_t)0x00000040) /*!< 1/16 */
#define UART_PLESCALER_32 ((uint32_t)0x00000050) /*!< 1/32 */
#define UART_PLESCALER_64 ((uint32_t)0x00000060) /*!< 1/64 */
#define UART_PLESCALER_128 ((uint32_t)0x00000070) /*!< 1/128 */
#define UART_PLESCALER_256 ((uint32_t)0x00000080) /*!< 1/256 */
#define UART_PLESCALER_512 ((uint32_t)0x00000090) /*!< 1/512 */
/**
* @}
*/ /* End of group UART_Prescaler */
/**
* @defgroup UART_Clock_Mask Clock Mask
* @brief Clock Mask Macro Definition.
* @{
*/
#define UART_UARTxCLK_MASK ((uint32_t)0x00000000) /*!< [1:0] is always 0 */
/**
* @}
*/ /* End of group UART_Clock_Mask */
/**
* @defgroup UART_Division Division
* @brief Enable/Disable Division Macro Definition.
* @{
*/
#define UART_DIVISION_DISABLE ((uint32_t)0x00000000) /*!< Disable */
#define UART_DIVISION_ENABLE ((uint32_t)0x00800000) /*!< Enable */
/**
* @}
*/ /* End of group UART_Division */
/**
* @defgroup UART_RangeK Range K
* @brief Range of K Macro Definition.
* @brief Range of K be set "(UART_RANGE_K_MIN <= Value <= UART_RANGE_K_MAX)".
* @{
*/
#define UART_RANGE_K_MIN ((uint32_t)0x00000000) /*!< Minimum Value :K=0 */
#define UART_RANGE_K_MAX ((uint32_t)0x0000003F) /*!< Maximum Value :K=63 */
/**
* @}
*/ /* End of group UART_RangeK */
/**
* @defgroup UART_RangeN Range N
* @brief Range of N Macro Definition.
* @brief Range of N be set "(UART_RANGE_N_MIN <= Value <= UART_RANGE_N_MAX)".
* @{
*/
#define UART_RANGE_N_MIN ((uint32_t)0x00000001) /*!< Minimum Value :N=1 */
#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /*!< Maximum Value :N=65535 */
/**
* @}
*/ /* End of group UART_RangeN */
/**
* @defgroup UART_SettingEnable Setting Enable
* @brief Enable/Disable Setting Macro Definition.
* @{
*/
#define UART_SETTING_MASK ((uint32_t)0x80000000) /*!< for Mask */
#define UART_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */
#define UART_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */
/**
* @}
*/ /* End of group UART_SettingEnable */
/**
* @defgroup UART_TxState Tx State
* @brief Transmitting State Macro Definition.
* @{
*/
#define UART_TX_STATE_MASK ((uint32_t)0x00008000) /*!< for Mask */
#define UART_TX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */
#define UART_TX_STATE_RUN ((uint32_t)0x00008000) /*!< Run */
/**
* @}
*/ /* End of group UART_TxState */
/**
* @defgroup UART_TxDone Transmitting Done
* @brief Transmitting Done Macro Definition.
* @{
*/
#define UART_TX_MASK ((uint32_t)0x00004000) /*!< for Mask */
#define UART_TX_DONE ((uint32_t)0x00004000) /*!< Transmitting Done */
/**
* @}
*/ /* End of group UART_TxDone */
/**
* @defgroup UART_TxReachFillLevel Tx Reach Fill Level
* @brief Reach Transmitting Fill Level Macro Definition.
* @{
*/
#define UART_TX_REACH_FILL_MASK ((uint32_t)0x00002000) /*!< for Mask */
#define UART_TX_REACH_FILL_LEVEL ((uint32_t)0x00002000) /*!< Reach Transmitting Fill Level */
/**
* @}
*/ /* End of group UART_TxReachFillLevel */
/**
* @defgroup UART_TxFifoLevel Tx FIFO Fill Level
* @brief Transmitting FIFO Fill Level Macro Definition.
* @{
*/
#define UART_TX_FIFO_LEVEL_MASK ((uint32_t)0x00000F00) /*!< for Mask */
/**
* @}
*/ /* End of group UART_TxFifoLevel */
/**
* @defgroup UART_RxState Rx State
* @brief Receive State Macro Definition.
* @{
*/
#define UART_RX_STATE_MASK ((uint32_t)0x00000080) /*!< for Mask */
#define UART_RX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */
#define UART_RX_STATE_RUN ((uint32_t)0x00000080) /*!< Run */
/**
* @}
*/ /* End of group UART_RxState */
/**
* @defgroup UART_RxDone Rx Done
* @brief Receive Done Macro Definition.
* @{
*/
#define UART_RX_MASK ((uint32_t)0x00000040) /*!< for Mask */
#define UART_RX_DONE ((uint32_t)0x00000040) /*!< Receive Done */
/**
* @}
*/ /* End of group UART_RxDone */
/**
* @defgroup UART_RxReachFillLevel Rx Reach Fill Level
* @brief Reach Receive Fill Level Macro Definition.
* @{
*/
#define UART_RX_REACH_FILL_MASK ((uint32_t)0x00000020) /*!< for Mask */
#define UART_RX_REACH_FILL_LEVEL ((uint32_t)0x00000020) /*!< Reach Receive Fill Level */
/**
* @}
*/ /* End of group UART_RxReachFillLevel */
/**
* @defgroup UART_RxFifoLevel Rx FIFO Fill Level
* @brief Receive FIFO Fill Level Macro Definition.
* @{
*/
#define UART_RX_FIFO_LEVEL_MASK ((uint32_t)0x0000000F) /*!< for Mask */
/**
* @}
*/ /* End of group UART_RxFifoLevel */
/**
* @defgroup UART_TriggerErr Trigger Error
* @brief Trigger Error Macro Definition.
* @{
*/
#define UART_TRIGGER_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
#define UART_TRIGGER_ERR ((uint32_t)0x00000010) /*!< Error */
/**
* @}
*/ /* End of group UART_TxTriggerErr */
/**
* @defgroup UART_OverrunErr Overrun Error
* @brief Overrun Error Macro Definition.
* @{
*/
#define UART_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
#define UART_OVERRUN_ERR ((uint32_t)0x00000008) /*!< Error */
/**
* @}
*/ /* End of group UART_OverrunErr */
/**
* @defgroup UART_ParityErr Parity Error
* @brief Parity Error Macro Definition.
* @{
*/
#define UART_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
#define UART_PARITY_ERR ((uint32_t)0x00000004) /*!< Error */
/**
* @}
*/ /* End of group UART_ParityErr */
/**
* @defgroup UART_FramingErr Framing Error
* @brief Framing Error Macro Definition.
* @{
*/
#define UART_FRAMING_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
#define UART_FRAMING_ERR ((uint32_t)0x00000002) /*!< Error */
/**
* @}
*/ /* End of group UART_FramingErr */
/**
* @defgroup UART_BreakErr Break Error
* @brief Break Error Macro Definition.
* @{
*/
#define UART_BREAK_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
#define UART_BREAK_ERR ((uint32_t)0x00000001) /*!< Error */
/**
* @}
*/ /* End of group UART_BreakErr */
/**
* @}
*/ /* End of group UART_Exported_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup UART_Exported_define UART Exported Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UART_Exported_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup UART_Exported_typedef UART Exported Typedef
* @{
*/
/*----------------------------------*/
/**
* @brief Receive event information structure definition.
* @brief When data length definition is "7 or 8bit"( @ref UART_DataLength ), use this.
* @attention "num" must be over FIFO max num.
*/
/*----------------------------------*/
typedef struct {
uint8_t *p_data; /*!< The buffer to receive data. */
uint32_t num; /*!< The number of receive data. */
} uart_receive8_t;
/*----------------------------------*/
/**
* @brief Receive event information structure definition.
* @brief When data length definition is "9bit"( @ref UART_DataLength ), use this.
*/
/*----------------------------------*/
typedef struct {
uint16_t *p_data; /*!< The buffer to receive data. */
uint32_t num; /*!< The number of receive data. */
} uart_receive16_t;
/*----------------------------------*/
/**
* @brief Receive event information structure definition.
*/
/*----------------------------------*/
typedef union {
uart_receive8_t rx8; /*!< @ref uart_receive8_t */
uart_receive16_t rx16; /*!< @ref uart_receive16_t */
} uart_receive_t;
/*----------------------------------*/
/**
* @brief Transmit data information structure definition.
* @brief When data length definition is "7 or 8bit"( @ref UART_DataLength ), use this.
*/
/*----------------------------------*/
typedef struct {
uint8_t *p_data; /*!< The buffer to transmit data. */
uint32_t num; /*!< The number of transmit data. */
} uart_transmit8_t;
/*----------------------------------*/
/**
* @brief Transmit data information structure definition.
* @brief When data length definition is "9bit"( @ref UART_DataLength ), use this.
*/
/*----------------------------------*/
typedef struct {
uint16_t *p_data; /*!< The buffer to transmit data.
Rransmit data valid range is ( 0x0000 <= range <= 0x01FF ) */
uint32_t num; /*!< The number of transmit data. */
} uart_transmit16_t;
/*----------------------------------*/
/**
* @brief Transmit data information structure definition.
*/
/*----------------------------------*/
typedef union {
uart_transmit8_t tx8; /*!< @ref uart_transmit8_t */
uart_transmit16_t tx16; /*!< @ref uart_transmit16_t */
} uart_transmit_t;
/*----------------------------------*/
/**
* @brief Clock setting structure definition.
*/
/*----------------------------------*/
typedef struct {
uint32_t prsel; /*!< Prescaler.
: Use @ref UART_Prescaler */
} uart_clock_t;
/*----------------------------------*/
/**
* @brief Boudrate setting structure definition.
*/
/*----------------------------------*/
typedef struct {
uint32_t ken; /*!< Enable/Disable Division Definition.
: Use @ref UART_Division */
uint32_t brk; /*!< Division Value K.
: K Range ( UART_RANGE_K_MIN <= K =< UART_RANGE_K_MAX ) @ref UART_RangeK */
uint32_t brn; /*!< Division Value N.
: N Range ( UART_RANGE_N_MIN <= N =< UART_RANGE_N_MAX ) @ref UART_RangeN */
} uart_boudrate_t;
/*----------------------------------*/
/**
* @brief Transmit FIFO setting.
*/
/*----------------------------------*/
typedef struct {
uint32_t inttx; /*!< Available Transmit FIFO Interrupt.
: Use @ref UART_TxFIFOInterrupt */
uint32_t level; /*!< Transmit Fill Level.
: Range ( UART_TX_FILL_RANGE_MIN <= K =< UART_TX_FILL_RANGE_MAX ) @ref UART_TxFillLevelRange */
} uart_tx_fifo_t;
/*----------------------------------*/
/**
* @brief Receive FIFO setting.
*/
/*----------------------------------*/
typedef struct {
uint32_t intrx; /*!< Available Receive FIFO Interrupt.
: Use @ref UART_RxFIFOInterrupt */
uint32_t level; /*!< Receive Fill Level.
: Range ( UART_RX_FILL_RANGE_MIN <= K =< UART_RX_FILL_RANGE_MAX ) @ref UART_RxFillLevelRange */
} uart_rx_fifo_t;
/*----------------------------------*/
/**
* @brief Initial setting structure definition.
*/
/*----------------------------------*/
typedef struct {
uint32_t id; /*!< ID: User value. */
uart_clock_t clock; /*!< Clock setting.
: Use @ref uart_clock_t */
uart_boudrate_t boudrate; /*!< Boudrate setting.
: Use @ref uart_boudrate_t */
uint32_t inttx; /*!< Available Transmit Interrupt.
: Use @ref UART_TxInterrupt */
uint32_t intrx; /*!< Available Receive Interrupt.
: Use @ref UART_RxInterrupt */
uint32_t interr; /*!< Available Error Interrupt.
: Use @ref UART_ErrorInterrupt */
uart_tx_fifo_t txfifo; /*!< Transmit FIFO setting.
: Use @ref uart_tx_fifo_t */
uart_rx_fifo_t rxfifo; /*!< Receive FIFO setting.
: Use @ref uart_rx_fifo_t */
uint32_t hct; /*!< Half Clock Terminal Select.
: Use @ref UART_HalfClockSelect */
uint32_t hcm; /*!< Half Clock Mode Select.
: Use @ref UART_HalfClockMode */
uint32_t hcc; /*!< Half Clock Control.
: Use @ref UART_HalfClockCTR */
uint32_t lbc; /*!< Loop Back Control.
: Use @ref UART_LoopBack */
uint32_t nf; /*!< UTxRXD Noise Filter.
: Use @ref UART_NoiseFilter */
uint32_t ctse; /*!< Available CTS Handshake.
: Use @ref UART_CTSHandshake */
uint32_t rtse; /*!< Available RTS Handshake.
: Use @ref UART_RTSHandshake */
uint32_t iv; /*!< Data Signal Complementation.
: Use @ref UART_DataComplementation */
uint32_t dir; /*!< Data Direction.
: Use @ref UART_DataDirection */
uint32_t sblen; /*!< Stop Bit.
: Use @ref UART_StopBit */
uint32_t even; /*!< Odd/Even Parity Bit.
: Use @ref UART_ParityBit */
uint32_t pe; /*!< Enable/Disable Parity Bit.
: Use @ref UART_ParityEnable */
uint32_t sm; /*!< Data Length.
: Use @ref UART_DataLength */
} uart_initial_setting_t;
/*----------------------------------*/
/**
* @brief UART handle structure definition.
*/
/*----------------------------------*/
typedef struct {
TSB_UART_TypeDef *p_instance; /*!< Registers base address. */
uart_initial_setting_t init; /*!< Initial setting. */
/*------------------------------------------*/
/*!
@brief Transmit Information.
*/
/*------------------------------------------*/
struct {
uint32_t rp; /*!< Num of transmitted data. */
uart_transmit_t info; /*!< Transmit Data Information. */
void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */
} transmit;
/*------------------------------------------*/
/*!
@brief Receive Information.
*/
/*------------------------------------------*/
struct {
uart_receive_t info; /*!< Receive Data Information. */
void (*handler)(uint32_t id, TXZ_Result result, uart_receive_t *p_info); /*!< Receive Event handler. */
} receive;
} uart_t;
/**
* @}
*/ /* End of group UART_Exported_typedef */
/*------------------------------------------------------------------------------*/
/* Functions */
/*------------------------------------------------------------------------------*/
/**
* @defgroup UART_Exported_functions UART Exported Functions
* @{
*/
TXZ_Result uart_init(uart_t *p_obj);
TXZ_Result uart_deinit(uart_t *p_obj);
TXZ_Result uart_discard_transmit(uart_t *p_obj);
TXZ_Result uart_discard_receive(uart_t *p_obj);
TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info);
TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info);
void uart_transmit_irq_handler(uart_t *p_obj);
void uart_receive_irq_handler(uart_t *p_obj);
void uart_error_irq_handler(uart_t *p_obj);
TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status);
TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error);
TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_setting);
/**
* @}
*/ /* End of group UART_Exported_functions */
/**
* @}
*/ /* End of group UART */
/**
* @}
*/ /* End of group Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __UART_H */

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targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_uart_include.h Normal file
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@ -0,0 +1,484 @@
/**
*******************************************************************************
* @file txz_uart_include.h
* @brief This file provides internal common definition.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __UART_INCLUDE_H
#define __UART_INCLUDE_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_driver_def.h"
/**
* @addtogroup Periph_Driver
* @{
*/
/**
* @addtogroup UART
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UART_Private_define
* @{
*/
/**
* @defgroup UART_NullPointer Null Pointer
* @brief Null Pointer.
* @{
*/
#define UART_NULL ((void *)0)
/**
* @}
*/ /* End of group UART_NullPointer */
/**
* @defgroup UART_ParameterResult Parameter Check Result
* @brief Whether the parameter is specified or not.
* @{
*/
#define UART_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */
#define UART_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */
/**
* @}
*/ /* End of group UART_ParameterResult */
/**
* @defgroup UARTxSWRST UARTxSWRST Register
* @brief UARTxSWRST Register Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-8 | - |
* | 7 | SWRSTF |
* | 6:2 | - |
* | 1:0 | SWRST |
* @{
*/
/* SWRSTF */
#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) /*!< SWRSTF :Mask. */
#define UARTxSWRST_SWRSTF_IDLE ((uint32_t)0x00000000) /*!< SWRSTF :Not be "Software Reset". */
#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) /*!< SWRSTF :During "Software Reset". */
/* SWRST */
#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) /*!< SWRST :"10" */
#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) /*!< SWRST :"01" */
/**
* @}
*/ /* End of group UARTxSWRST */
/**
* @defgroup UARTxCR0 UARTxCR0 Register
* @brief UARTxCR0 Register Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-19 | - |
* | 18 | HBSST |
* | 17 | HBSMD |
* | 16 | HBSEN |
* | 15 | LPB |
* | 14-12 | NF[2:0] |
* | 11 | - |
* | 10 | CTSE |
* | 9 | RTSE |
* | 8 | WU |
* | 7 | - |
* | 6 | IV |
* | 5 | DIR |
* | 4 | SBLEN |
* | 3 | EVEN |
* | 2 | PE |
* | 1-0 | SM[1:0] |
* @{
*/
/* HBSST */
#define UARTxCR0_HBSST_MASK ((uint32_t)0x00040000) /*!< HBSST :Mask. */
/* HBSMD */
#define UARTxCR0_HBSMD_MASK ((uint32_t)0x00020000) /*!< HBSMD :Mask. */
/* HBSEN */
#define UARTxCR0_HBSEN_MASK ((uint32_t)0x00010000) /*!< HBSEN :Mask. */
#define UARTxCR0_HBSEN_DISABLE ((uint32_t)0x00000000) /*!< HBSEN :Disable. */
#define UARTxCR0_HBSEN_ENABLE ((uint32_t)0x00010000) /*!< HBSEN :Enable. */
/* LPB */
#define UARTxCR0_LPB_MASK ((uint32_t)0x00008000) /*!< LPB :Mask. */
#define UARTxCR0_LPB_DISABLE ((uint32_t)0x00000000) /*!< LPB :Disable. */
#define UARTxCR0_LPB_ENABLE ((uint32_t)0x00008000) /*!< LPB :Enable. */
/* WU */
#define UARTxCR0_WU_MASK ((uint32_t)0x00000100) /*!< WU :Mask. */
#define UARTxCR0_WU_DISABLE ((uint32_t)0x00000000) /*!< WU :Disable. */
#define UARTxCR0_WU_ENABLE ((uint32_t)0x00000100) /*!< WU :Enable. */
/**
* @}
*/ /* End of group UARTxCR0 */
/**
* @defgroup UARTxCR1 UARTxCR1 Register
* @brief UARTxCR1 Register Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-15 | - |
* | 14-12 | TIL[2:0] |
* | 11 | - |
* | 10-8 | RIL[2:0] |
* | 7 | INTTXFE |
* | 6 | INTTXWE |
* | 5 | INTRXFE |
* | 4 | INTRXWE |
* | 3 | - |
* | 2 | INTERR |
* | 1 | DMATE |
* | 0 | DMARE |
* @{
*/
/* RIL */
#define UARTxCR1_RIL_MASK ((uint32_t)0x00000700) /*!< RIL :Mask. */
/* DMATE */
#define UARTxCR1_DMATE_MASK ((uint32_t)0x00000002) /*!< DMATE :Mask. */
#define UARTxCR1_DMATE_DISABLE ((uint32_t)0x00000000) /*!< DMATE :Disable. */
#define UARTxCR1_DMATE_ENABLE ((uint32_t)0x00000002) /*!< DMATE :Enable. */
/* DMARE */
#define UARTxCR1_DMARE_MASK ((uint32_t)0x00000001) /*!< DMARE :Mask. */
#define UARTxCR1_DMARE_DISABLE ((uint32_t)0x00000000) /*!< DMARE :Disable. */
#define UARTxCR1_DMARE_ENABLE ((uint32_t)0x00000001) /*!< DMARE :Enable. */
/**
* @}
*/ /* End of group UARTxCR1 */
/**
* @defgroup UARTxTRANS UARTxTRANS Register
* @brief UARTxTRANS Register Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-4 | - |
* | 3 | BK |
* | 2 | TXTRG |
* | 1 | TXE |
* | 0 | RXE |
* @{
*/
/* BK */
#define UARTxTRANS_BK_MASK ((uint32_t)0x00000008) /*!< BK :Mask */
#define UARTxTRANS_BK_STOP ((uint32_t)0x00000000) /*!< BK :Stop */
#define UARTxTRANS_BK_SEND ((uint32_t)0x00000008) /*!< BK :Send */
/* TXTRG */
#define UARTxTRANS_TXTRG_MASK ((uint32_t)0x00000004) /*!< TXTRG :Mask */
#define UARTxTRANS_TXTRG_DISABLE ((uint32_t)0x00000000) /*!< TXTRG :Disable */
#define UARTxTRANS_TXTRG_ENABLE ((uint32_t)0x00000004) /*!< TXTRG :Enable */
/* TXE */
#define UARTxTRANS_TXE_MASK ((uint32_t)0x00000002) /*!< TXE :Mask */
#define UARTxTRANS_TXE_DISABLE ((uint32_t)0x00000000) /*!< TXE :Disable */
#define UARTxTRANS_TXE_ENABLE ((uint32_t)0x00000002) /*!< TXE :Enable */
/* RXE */
#define UARTxTRANS_RXE_MASK ((uint32_t)0x00000001) /*!< RXE :Mask */
#define UARTxTRANS_RXE_DISABLE ((uint32_t)0x00000000) /*!< RXE :Disable */
#define UARTxTRANS_RXE_ENABLE ((uint32_t)0x00000001) /*!< RXE :Enable */
/* TXE,RXE */
#define UARTxTRANS_TXE_RXE_MASK ((uint32_t)0x00000003) /*!< TXE/RXE:Mask */
/**
* @}
*/ /* End of group UARTxTRANS */
/**
* @defgroup UARTxDR UARTxDR Register
* @brief UARTxDR Register Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-19 | - |
* | 18 | PERR |
* | 17 | FERR |
* | 16 | BERR |
* | 15:9 | - |
* | 8:0 | DR |
* @{
*/
/* DR */
#define UARTxDR_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 9bit */
#define UARTxDR_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */
#define UARTxDR_DR_7BIT_MASK ((uint32_t)0x0000007F) /*!< DR :Mask for 7bit */
/**
* @}
*/ /* End of group UARTxDR */
/**
* @defgroup UARTxSR UARTxSR Register
* @brief UARTxSR Register Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31 | SUE |
* | 30:16 | - |
* | 15 | TXRUN |
* | 14 | TXEND |
* | 13 | TXFF |
* | 12 | - |
* | 11:8 | TLVL |
* | 7 | RXRUN |
* | 6 | RXEND |
* | 5 | RXFF |
* | 4 | - |
* | 3:0 | RLVL |
* @{
*/
/* SUE */
#define UARTxSR_SUE_MASK ((uint32_t)0x80000000) /*!< SUE :Mask. */
/* TXEND */
#define UARTxSR_TXEND_MASK ((uint32_t)0x00004000) /*!< TEXND :Mask. */
#define UARTxSR_TXEND_R_END ((uint32_t)0x00004000) /*!< TXEND :[read] Transfer done. */
#define UARTxSR_TXEND_W_CLEAR ((uint32_t)0x00004000) /*!< TXEND :[write] Clear Flag. */
/* TXFF */
#define UARTxSR_TXFF_MASK ((uint32_t)0x00002000) /*!< TXFF :Mask. */
#define UARTxSR_TXFF_R_REACHED ((uint32_t)0x00002000) /*!< TXFF :[read] Reached the transfer level. */
#define UARTxSR_TXFF_W_CLEAR ((uint32_t)0x00002000) /*!< TXFF :[write] Clear Flag. */
/* TLVL */
#define UARTxSR_TLVL_MASK ((uint32_t)0x00000F00) /*!< TLVL :Mask. */
/* RXEND */
#define UARTxSR_RXEND_MASK ((uint32_t)0x00000040) /*!< RXEND :Mask. */
#define UARTxSR_RXEND_R_END ((uint32_t)0x00000040) /*!< RXEND :[read] Receive done. */
#define UARTxSR_RXEND_W_CLEAR ((uint32_t)0x00000040) /*!< RXEND :[write] Clear Flag. */
/* RXFF */
#define UARTxSR_RXFF_MASK ((uint32_t)0x00000020) /*!< RXFF :Mask. */
#define UARTxSR_RXFF_R_REACHED ((uint32_t)0x00000020) /*!< RXFF :[read] Receive done. */
#define UARTxSR_RXFF_W_CLEAR ((uint32_t)0x00000020) /*!< RXFF :[write] Clear Flag. */
/* RLVL */
#define UARTxSR_RLVL_MASK ((uint32_t)0x0000000F) /*!< RLVL :Mask. */
/**
* @}
*/ /* End of group UARTxSR */
/**
* @defgroup UARTxFIFOCLR UARTxFIFOCLR Register
* @brief UARTxFIFOCLR Register Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-2 | - |
* | 1 | TFCLR |
* | 0 | RFCLR |
* @{
*/
/* TFCLR */
#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) /*!< TFCLR :Clear the transmit buff. */
/* RFCLR */
#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) /*!< RFCLR :Clear the receive buff. */
/**
* @}
*/ /* End of group UARTxFIFOCLR */
/**
* @defgroup UARTxERR UARTxERR Register
* @brief UARTxERR Register Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-5 | - |
* | 4 | TRGERR |
* | 3 | OVRERR |
* | 2 | PERR |
* | 1 | FERR |
* | 0 | BERR |
* @{
*/
/* TRGERR */
#define UARTxERR_TRGERR_MASK ((uint32_t)0x00000010) /*!< TRGERR :Mask. */
#define UARTxERR_TRGERR_R_NO_ERR ((uint32_t)0x00000000) /*!< TRGERR :[read] No Error. */
#define UARTxERR_TRGERR_R_ERR ((uint32_t)0x00000010) /*!< TRGERR :[read] Error. */
#define UARTxERR_TRGERR_W_CLEAR ((uint32_t)0x00000010) /*!< TRGERR :[write] Clear Flag. */
/* OVRERR */
#define UARTxERR_OVRERR_MASK ((uint32_t)0x00000008) /*!< OVRERR :Mask. */
#define UARTxERR_OVRERR_R_NO_ERR ((uint32_t)0x00000000) /*!< OVRERR :[read] No Error. */
#define UARTxERR_OVRERR_R_ERR ((uint32_t)0x00000008) /*!< OVRERR :[read] Error. */
#define UARTxERR_OVRERR_W_CLEAR ((uint32_t)0x00000008) /*!< OVRERR :[write] Clear Flag. */
/* PERR */
#define UARTxERR_PERR_MASK ((uint32_t)0x00000004) /*!< PERR :Mask. */
#define UARTxERR_PERR_R_NO_ERR ((uint32_t)0x00000000) /*!< PERR :[read] No Error. */
#define UARTxERR_PERR_R_ERR ((uint32_t)0x00000004) /*!< PERR :[read] Error. */
#define UARTxERR_PERR_W_CLEAR ((uint32_t)0x00000004) /*!< PERR :[write] Clear Flag. */
/* FERR */
#define UARTxERR_FERR_MASK ((uint32_t)0x00000002) /*!< FERR :Mask. */
#define UARTxERR_FERR_R_NO_ERR ((uint32_t)0x00000000) /*!< FERR :[read] No Error. */
#define UARTxERR_FERR_R_ERR ((uint32_t)0x00000002) /*!< FERR :[read] Error. */
#define UARTxERR_FERR_W_CLEAR ((uint32_t)0x00000002) /*!< FERR :[write] Clear Flag. */
/* BERR */
#define UARTxERR_BERR_MASK ((uint32_t)0x00000001) /*!< BERR :Mask. */
#define UARTxERR_BERR_R_NO_ERR ((uint32_t)0x00000000) /*!< BERR :[read] No Error. */
#define UARTxERR_BERR_R_ERR ((uint32_t)0x00000001) /*!< BERR :[read] Error. */
#define UARTxERR_BERR_W_CLEAR ((uint32_t)0x00000001) /*!< BERR :[write] Clear Flag. */
/**
* @}
*/ /* End of group UARTxERR */
/**
* @}
*/ /* End of group UART_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UART_Private_define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UART_Private_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UART_Private_typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UART_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Inline Functions */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UART_Private_functions
* @{
*/
__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance);
__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance);
__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance);
__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance);
/*--------------------------------------------------*/
/**
* @brief Disable UARTxTRANS TXE.
* @param p_instance: Instance address.
* @retval -
* @note Bitband Access
*/
/*--------------------------------------------------*/
__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance)
{
#ifdef __DEBUG__
if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) {
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 0;
}
#else
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 0;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Enable UARTxTRANS TXE.
* @param p_instance: Instance address.
* @retval -
* @note Bitband Access
*/
/*--------------------------------------------------*/
__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance)
{
#ifdef __DEBUG__
if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) {
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 1;
}
#else
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 1;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Disable UARTxTRANS RXE.
* @param p_instance: Instance address.
* @retval -
* @note Bitband Access
*/
/*--------------------------------------------------*/
__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance)
{
#ifdef __DEBUG__
if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) {
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 0;
}
#else
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 0;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Enable UARTxTRANS RXE.
* @param p_instance: Instance address.
* @retval -
* @note Bitband Access
*/
/*--------------------------------------------------*/
__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance)
{
#ifdef __DEBUG__
if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) {
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 1;
}
#else
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 1;
#endif
}
/**
* @}
*/ /* End of group UART_Private_functions */
/**
* @}
*/ /* End of group UART */
/**
* @}
*/ /* End of group Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __UART_EX_H */

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/**
*******************************************************************************
* @file txz_adc_ch.c
* @brief This file provides API functions for ADC driver. \n
* Channel Class.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_adc_include.h"
#include "txz_adc_ch.h"
#if defined(__ADC_CH_H)
/**
* @addtogroup Periph_Driver Peripheral Driver
* @{
*/
/**
* @addtogroup ADC
* @{
*/
/*------------------------------------------------------------------------------*/
/* Configuration */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_define ADC Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Private_define */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_define ADC Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_define ADC Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Private_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_typedef ADC Private Typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Private Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_fuctions ADC Private Fuctions
* @{
*/
#ifdef __DEBUG__
/* no define */
#endif
/**
* @}
*/ /* End of group ADC_Private_functions */
/*------------------------------------------------------------------------------*/
/* Public Function */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup ADC_Exported_functions
* @{
*/
/*--------------------------------------------------*/
/*!
* @fn static uint32_t get_conversion_data(uint32_t reg)
* @brief Get convertion data from ADxREGn.
* @param[in] reg :ADxREGn data.
* @retval Convertion data.
* @note -
*/
/*--------------------------------------------------*/
uint32_t get_conversion_data(uint32_t reg)
{
uint32_t result = (uint32_t)((reg & ADxREGn_ADRn_MASK) >> 4);
return (result);
}
/*--------------------------------------------------*/
/*!
* @fn TXZ_Result adc_ch_init(adc_ch_t *p_obj)
* @brief Initialize the ADC Channel object.
* @param[in][out] p_obj :ADC Channel object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @pre Conversion has stoped.
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
TXZ_Result adc_ch_init(adc_ch_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
if (((void *)(p_obj) == (void *)0) ||
((volatile void *)(p_obj->p_tset) == (volatile void *)0) ||
((const volatile void *)(p_obj->p_reg) == (const volatile void *)0)) {
result = TXZ_ERROR;
} else {
/*------------------------------*/
/* Register Setting */
/*------------------------------*/
/*--- ADxREGx ---*/
/* Read is needed before the next convertion. */
{
volatile uint32_t reg;
reg = *p_obj->p_reg;
}
/*--- ADxTSET ---*/
*p_obj->p_tset = (p_obj->init.interrupt | p_obj->init.type | p_obj->init.ain);
}
return (result);
}
/*--------------------------------------------------*/
/*!
* @fn TXZ_Result adc_ch_deinit(adc_ch_t *p_obj)
* @brief Release the ADC Channel object.
* @param[in][out] p_obj :ADC Channel object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
TXZ_Result adc_ch_deinit(adc_ch_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
if ((void *)(p_obj) == (void *)0) {
result = TXZ_ERROR;
} else {
/*------------------------------*/
/* Register Setting */
/*------------------------------*/
/*--- ADxTSET ---*/
*p_obj->p_tset = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_DISABLE | 0);
/*--- ADxREGx ---*/
/* Read is needed before the next convertion. */
{
volatile uint32_t reg;
reg = *p_obj->p_reg;
}
}
return (result);
}
/*--------------------------------------------------*/
/*!
* @fn TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj)
* @brief Enable Interrupt.
* @param[in][out] p_obj :ADC Channel object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @pre Conversion has stoped.
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
if (((void *)(p_obj) == (void *)0) ||
((volatile void *)(p_obj->p_tset) == (volatile void *)0) ||
((const volatile void *)(p_obj->p_reg) == (const volatile void *)0)) {
result = TXZ_ERROR;
} else {
/*------------------------------*/
/* Register Setting */
/*------------------------------*/
/*--- ADxTSET ---*/
{
uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK);
*p_obj->p_tset = (tset | ADxTSETn_ENINT_ENABLE);
}
}
return (result);
}
/*--------------------------------------------------*/
/*!
* @fn TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj)
* @brief Disable Interrupt.
* @param[in][out] p_obj :ADC Channel object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @pre Conversion has stoped.
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
if (((void *)(p_obj) == (void *)0) ||
((volatile void *)(p_obj->p_tset) == (volatile void *)0) ||
((const volatile void *)(p_obj->p_reg) == (const volatile void *)0)) {
result = TXZ_ERROR;
} else {
/*------------------------------*/
/* Register Setting */
/*------------------------------*/
/*--- ADxTSET ---*/
{
uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK);
*p_obj->p_tset = (tset | ADxTSETn_ENINT_DISABLE);
}
}
return (result);
}
/*--------------------------------------------------*/
/*!
* @fn TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value)
* @brief Get conversion value.
* @param p_obj :ADC Channel object.
* @param p_value :AD value. Destination address.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @pre Conversion has done.
*/
/*--------------------------------------------------*/
TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value)
{
TXZ_Result result = TXZ_ERROR;
uint32_t reg;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
if ((void *)(p_obj) == (void *)0) {
result = TXZ_ERROR;
} else {
reg = *p_obj->p_reg;
/*------------------------------*/
/* Check Result */
/*------------------------------*/
if ((reg & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) {
*p_value = get_conversion_data(reg);
result = TXZ_SUCCESS;
}
}
return (result);
}
/**
* @}
*/ /* End of group ADC_Exported_functions */
/**
* @}
*/ /* End of group ADC */
/**
* @}
*/ /* End of group Periph_Driver */
#endif /* defined(__ADC_H) */
#ifdef __cplusplus
}
#endif /* __cplusplus */

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/**
*******************************************************************************
* @file txz_cg.c
* @brief This file provides API functions for CG driver.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_cg.h"
#if defined(__CG_H)
/**
* @addtogroup Periph_Driver
* @{
*/
/**
* @addtogroup CG
* @{
*/
/*------------------------------------------------------------------------------*/
/* Configuration */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Private_define CG Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group CG_Private_define */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Private_define CG Private Define
* @{
*/
#define CG_FSYS_MASK ((uint32_t)0x00070000) /*!< CG FSYS mask */
#define CG_FSYS_1 ((uint32_t)0x00000000) /*!< CG fc register value */
#define CG_FSYS_2 ((uint32_t)0x00010000) /*!< CG fc/2 register value */
#define CG_FSYS_4 ((uint32_t)0x00020000) /*!< CG fc/4 register value */
#define CG_FSYS_8 ((uint32_t)0x00030000) /*!< CG fc/8 register value */
#define CG_FSYS_16 ((uint32_t)0x00040000) /*!< CG fc/16 register value */
#define CG_FSYS_1_MUL ((uint32_t)0x00000001) /*!< CG fc multiplication value */
#define CG_FSYS_2_MUL ((uint32_t)0x00000002) /*!< CG fc/2 multiplication value */
#define CG_FSYS_4_MUL ((uint32_t)0x00000004) /*!< CG fc/4 multiplication value */
#define CG_FSYS_8_MUL ((uint32_t)0x00000008) /*!< CG fc/8 multiplication value */
#define CG_FSYS_16_MUL ((uint32_t)0x00000010) /*!< CG fc/16 multiplication value */
#define CG_PRCK_MASK ((uint32_t)0x00000F00) /*!< CG PRCK mask */
#define CG_PRCK_1 ((uint32_t)0x00000000) /*!< CG ƒÓT0 fc register value */
#define CG_PRCK_2 ((uint32_t)0x00000100) /*!< CG ƒÓT0 fc/2 register value */
#define CG_PRCK_4 ((uint32_t)0x00000200) /*!< CG ƒÓT0 fc/4 register value */
#define CG_PRCK_8 ((uint32_t)0x00000300) /*!< CG ƒÓT0 fc/8 register value */
#define CG_PRCK_16 ((uint32_t)0x00000400) /*!< CG ƒÓT0 fc/16 register value */
#define CG_PRCK_32 ((uint32_t)0x00000500) /*!< CG ƒÓT0 fc/32 register value */
#define CG_PRCK_64 ((uint32_t)0x00000600) /*!< CG ƒÓT0 fc/64 register value */
#define CG_PRCK_128 ((uint32_t)0x00000700) /*!< CG ƒÓT0 fc/128 register value */
#define CG_PRCK_256 ((uint32_t)0x00000800) /*!< CG ƒÓT0 fc/256 register value */
#define CG_PRCK_512 ((uint32_t)0x00000900) /*!< CG ƒÓT0 fc/512 register value */
#define CG_PRCKST_MASK ((uint32_t)0x0F000000) /*!< CG PRCKST mask */
#define CG_PRCKST_1 ((uint32_t)0x00000000) /*!< CG ƒÓT0 fc register status */
#define CG_PRCKST_2 ((uint32_t)0x01000000) /*!< CG ƒÓT0 fc/2 register status */
#define CG_PRCKST_4 ((uint32_t)0x02000000) /*!< CG ƒÓT0 fc/4 register status */
#define CG_PRCKST_8 ((uint32_t)0x03000000) /*!< CG ƒÓT0 fc/8 register status */
#define CG_PRCKST_16 ((uint32_t)0x04000000) /*!< CG ƒÓT0 fc/16 register status */
#define CG_PRCKST_32 ((uint32_t)0x05000000) /*!< CG ƒÓT0 fc/32 register status */
#define CG_PRCKST_64 ((uint32_t)0x06000000) /*!< CG ƒÓT0 fc/64 register status */
#define CG_PRCKST_128 ((uint32_t)0x07000000) /*!< CG ƒÓT0 fc/128 register status */
#define CG_PRCKST_256 ((uint32_t)0x08000000) /*!< CG ƒÓT0 fc/256 register status */
#define CG_PRCKST_512 ((uint32_t)0x09000000) /*!< CG ƒÓT0 fc/512 register status */
#define CG_PRCK_1_DIV ((uint32_t)0x00000001) /*!< CG ƒÓT0 fc division value */
#define CG_PRCK_2_DIV ((uint32_t)0x00000002) /*!< CG ƒÓT0 fc/2 division value */
#define CG_PRCK_4_DIV ((uint32_t)0x00000004) /*!< CG ƒÓT0 fc/4 division value */
#define CG_PRCK_8_DIV ((uint32_t)0x00000008) /*!< CG ƒÓT0 fc/8 division value */
#define CG_PRCK_16_DIV ((uint32_t)0x00000010) /*!< CG ƒÓT0 fc/16 division value */
#define CG_PRCK_32_DIV ((uint32_t)0x00000020) /*!< CG ƒÓT0 fc/32 division value */
#define CG_PRCK_64_DIV ((uint32_t)0x00000040) /*!< CG ƒÓT0 fc/64 division value */
#define CG_PRCK_128_DIV ((uint32_t)0x00000080) /*!< CG ƒÓT0 fc/128 division value */
#define CG_PRCK_256_DIV ((uint32_t)0x00000100) /*!< CG ƒÓT0 fc/256 division value */
#define CG_PRCK_512_DIV ((uint32_t)0x00000200) /*!< CG ƒÓT0 fc/512 division value */
#define CG_MCKSELPST_MASK ((uint32_t)0xC0000000) /*!< CG MCKSEL mask */
#define CG_MCKSELPST_1 ((uint32_t)0x00000000) /*!< CG ƒÓT0 fc/PRCK value */
#define CG_MCKSELPST_2 ((uint32_t)0x40000000) /*!< CG ƒÓT0 fc/PRCK/2 value */
#define CG_MCKSELPST_4 ((uint32_t)0x80000000) /*!< CG ƒÓT0 fc/PRCK/4 value */
#define CG_FSYSM_1_DIV ((uint32_t)0x00000001) /*!< CG fsysm ƒÓT0 division value */
#define CG_FSYSM_2_DIV ((uint32_t)0x00000002) /*!< CG fsysm ƒÓT0/2 division value */
#define CG_FSYSM_4_DIV ((uint32_t)0x00000004) /*!< CG fsysm ƒÓT0/4 division value */
#define CG_IHOSC_DISABLE ((uint32_t)0x00000000) /*!< Internal high-speed oscillator disable */
#define CG_IHOSC_ENABLE ((uint32_t)0x00000001) /*!< Internal high-speed oscillator enable */
#define CG_IHOSC1EN ((uint32_t)0x00000000) /*!< CG OSCCR bit0 */
#define CG_MCKSELGST_MASK ((uint32_t)0x00C00000) /*!< CG MCKSELGST mask */
#define CG_MCKSELGST_1 ((uint32_t)0x00000000) /*!< CG fsysm fc/PRCK value */
#define CG_MCKSELGST_2 ((uint32_t)0x00400000) /*!< CG fsysm fc/PRCK/2 value */
#define CG_MCKSELGST_4 ((uint32_t)0x00800000) /*!< CG fsysm fc/PRCK/4 value */
/**
* @}
*/ /* End of group CG_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Private_define CG Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group CG_Private_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Private_typedef CG Private Typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group CG_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Private Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Private_fuctions CG Private Fuctions
* @{
*/
/* no define */
/**
* @}
*/ /* End of group CG_Private_functions */
/*------------------------------------------------------------------------------*/
/* Public Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Exported_functions CG Exported Functions
* @{
*/
/*--------------------------------------------------*/
/**
* @brief Update Middle PrescalerClock according register values.
* @param p_obj :CG object.
* @retval Middle PrescalerClock Frequency.
* @note -
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
uint32_t cg_get_fsysm(cg_t *p_obj)
{
uint32_t result = 0U;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef __DEBUG__
/* Check the CG_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef __DEBUG__ */
/* System core clock update */
SystemCoreClockUpdate();
switch (p_obj->p_instance->SYSCR & CG_MCKSELGST_MASK) {
case CG_MCKSELGST_1: /* fsysm -> fc/PRCK */
result = SystemCoreClock / CG_FSYSM_1_DIV;
break;
case CG_MCKSELGST_2: /* fsysm -> fc/PRCK/2 */
result = SystemCoreClock / CG_FSYSM_2_DIV;
break;
case CG_MCKSELGST_4: /* fsysm -> fc/PRCK/4 */
result = SystemCoreClock / CG_FSYSM_4_DIV;
break;
default:
result = 0U;
break;
}
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Update PrescalerClock according register values.
* @param p_obj :CG object.
* @retval PrescalerClock Frequency.
* @note -
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
uint32_t cg_get_phyt0(cg_t *p_obj)
{
uint32_t result = 0U;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef __DEBUG__
/* Check the CG_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef __DEBUG__ */
/* System core clock update */
SystemCoreClockUpdate();
/* Get Gear status. */
switch (p_obj->p_instance->SYSCR & CG_FSYS_MASK) {
case CG_FSYS_1: /* Gear -> fc */
result = SystemCoreClock * CG_FSYS_1_MUL;
break;
case CG_FSYS_2: /* Gear -> fc/2 */
result = SystemCoreClock * CG_FSYS_2_MUL;
break;
case CG_FSYS_4: /* Gear -> fc/4 */
result = SystemCoreClock * CG_FSYS_4_MUL;
break;
case CG_FSYS_8: /* Gear -> fc/8 */
result = SystemCoreClock * CG_FSYS_8_MUL;
break;
case CG_FSYS_16: /* Gear -> fc/16 */
result = SystemCoreClock * CG_FSYS_16_MUL;
break;
default:
result = 0U;
break;
}
switch (p_obj->p_instance->SYSCR & CG_PRCKST_MASK) {
case CG_PRCKST_1: /* ƒÓT0 -> fc */
result /= CG_PRCK_1_DIV;
break;
case CG_PRCKST_2: /* ƒÓT0 -> fc/2 */
result /= CG_PRCK_2_DIV;
break;
case CG_PRCKST_4: /* ƒÓT0 -> fc/4 */
result /= CG_PRCK_4_DIV;
break;
case CG_PRCKST_8: /* ƒÓT0 -> fc/8 */
result /= CG_PRCK_8_DIV;
break;
case CG_PRCKST_16: /* ƒÓT0 -> fc/16 */
result /= CG_PRCK_16_DIV;
break;
case CG_PRCKST_32: /* ƒÓT0 -> fc/32 */
result /= CG_PRCK_32_DIV;
break;
case CG_PRCKST_64: /* ƒÓT0 -> fc/64 */
result /= CG_PRCK_64_DIV;
break;
case CG_PRCKST_128: /* ƒÓT0 -> fc/128 */
result /= CG_PRCK_128_DIV;
break;
case CG_PRCKST_256: /* ƒÓT0 -> fc/256 */
result /= CG_PRCK_256_DIV;
break;
case CG_PRCKST_512: /* ƒÓT0 -> fc/512 */
result /= CG_PRCK_512_DIV;
break;
default:
result = 0U;
break;
}
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Update Middle PrescalerClock according register values.
* @param p_obj :CG object.
* @retval Middle PrescalerClock Frequency.
* @note -
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
uint32_t cg_get_mphyt0(cg_t *p_obj)
{
uint32_t result = 0U;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef __DEBUG__
/* Check the CG_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef __DEBUG__ */
/* System core clock update */
SystemCoreClockUpdate();
/* Get Gear status. */
switch (p_obj->p_instance->SYSCR & CG_FSYS_MASK) {
case CG_FSYS_1: /* Gear -> fc */
result = SystemCoreClock * CG_FSYS_1_MUL;
break;
case CG_FSYS_2: /* Gear -> fc/2 */
result = SystemCoreClock * CG_FSYS_2_MUL;
break;
case CG_FSYS_4: /* Gear -> fc/4 */
result = SystemCoreClock * CG_FSYS_4_MUL;
break;
case CG_FSYS_8: /* Gear -> fc/8 */
result = SystemCoreClock * CG_FSYS_8_MUL;
break;
case CG_FSYS_16: /* Gear -> fc/16 */
result = SystemCoreClock * CG_FSYS_16_MUL;
break;
default:
result = 0U;
break;
}
switch (p_obj->p_instance->SYSCR & CG_PRCKST_MASK) {
case CG_PRCKST_1: /* ƒÓT0 -> fc */
result /= CG_PRCK_1_DIV;
break;
case CG_PRCKST_2: /* ƒÓT0 -> fc/2 */
result /= CG_PRCK_2_DIV;
break;
case CG_PRCKST_4: /* ƒÓT0 -> fc/4 */
result /= CG_PRCK_4_DIV;
break;
case CG_PRCKST_8: /* ƒÓT0 -> fc/8 */
result /= CG_PRCK_8_DIV;
break;
case CG_PRCKST_16: /* ƒÓT0 -> fc/16 */
result /= CG_PRCK_16_DIV;
break;
case CG_PRCKST_32: /* ƒÓT0 -> fc/32 */
result /= CG_PRCK_32_DIV;
break;
case CG_PRCKST_64: /* ƒÓT0 -> fc/64 */
result /= CG_PRCK_64_DIV;
break;
case CG_PRCKST_128: /* ƒÓT0 -> fc/128 */
result /= CG_PRCK_128_DIV;
break;
case CG_PRCKST_256: /* ƒÓT0 -> fc/256 */
result /= CG_PRCK_256_DIV;
break;
case CG_PRCKST_512: /* ƒÓT0 -> fc/512 */
result /= CG_PRCK_512_DIV;
break;
default:
result = 0U;
break;
}
switch (p_obj->p_instance->SYSCR & CG_MCKSELPST_MASK) {
case CG_MCKSELPST_1: /* ƒÓT0 -> fc/PRCK */
result /= CG_FSYSM_1_DIV;
break;
case CG_MCKSELPST_2: /* ƒÓT0 -> fc/PRCK/2 */
result /= CG_FSYSM_2_DIV;
break;
case CG_MCKSELPST_4: /* ƒÓT0 -> fc/PRCK/4 */
result /= CG_FSYSM_4_DIV;
break;
default:
result = 0U;
break;
}
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Set Internal high-speed oscillator enable.
* @param p_obj :CG object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
TXZ_Result cg_ihosc_enable(cg_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef __DEBUG__
/* Check the CG_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef __DEBUG__ */
/* Internal high-speed oscillator is enable. */
(*((__IO uint32_t *)BITBAND_PERI(&p_obj->p_instance->OSCCR, CG_IHOSC1EN))) = CG_IHOSC_ENABLE;
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Set Internal high-speed oscillator disable.
* @param p_obj :CG object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
TXZ_Result cg_ihosc_disable(cg_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef __DEBUG__
/* Check the CG_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef __DEBUG__ */
/* Internal high-speed oscillator is disable. */
(*((__IO uint32_t *)BITBAND_PERI(&p_obj->p_instance->OSCCR, CG_IHOSC1EN))) = CG_IHOSC_DISABLE;
return (result);
}
/**
* @}
*/ /* End of group CG_Exported_functions */
/**
* @}
*/ /* End of group CG */
/**
* @}
*/ /* End of group Periph_Driver */
#endif /* defined(__CG_H) */
#ifdef __cplusplus
}
#endif /* __cplusplus */

695
targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_fc.c Normal file
View File

@ -0,0 +1,695 @@
/**
*******************************************************************************
* @file flash512ud32_b.c
* @brief This file provides API functions for FLASH.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include <string.h>
#include "txz_fc.h"
//#include "txz_sample_def.h"
/**
* @addtogroup Example
* @{
*/
/**
* @defgroup Flash_Userboot Flash_Userboot Sample Appli
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup Flash_Userboot_Private_macro Flash_Userboot Private Macro
* @{
*/
/* no define */
/**
* @}
*/ /* End of group Flash_Userboot_Private_macro */
/*------------------------------------------------------------------------------*/
/* Configuration */
/*------------------------------------------------------------------------------*/
/**
* @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define
* @{
*/
/**
* @}
*/ /* End of group Flash_Userboot_Private_define */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define
* @{
*/
#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */
#define FC_BRANK_VALUE (uint32_t)(0xFFFFFFFFUL) /*!< Brank value */
#define FC_MAX_PAGES (uint8_t)(0x20) /*!< Maxmum pages */
#define FC_MAX_BLOCKS (uint8_t)(0x16) /*!< Maxmum blocks */
#define FC_MAX_AREAS (uint8_t)(0x1) /*!< Maxmum areas */
#define FC_CMD_ADDRESS_MASK (uint32_t)(0xFFFF0000UL) /*!< Upper address mask of the upper address */
#define FC_CMD_BC1_ADDR (0x00000550UL) /*!< The lower address of the first bus cycle when uses commans */
#define FC_CMD_BC2_ADDR (0x00000AA0UL) /*!< The lower address of the second bus cycle when uses commans */
/****************** Changed by TSIP *************************************/
///* Area Selection All */
#define FC_AREASEL_EXPECT_AREA0 (uint32_t)(0x00000000UL)
#define FC_AREASEL_EXPECT_AREA1 (uint32_t)(0x00000000UL) /*!< RW, Selects expect area1 */
#define FC_AREASEL_AREA0 (uint32_t)(0x00000007UL) //select Area 0
#define FC_AREASEL_AREA1 (uint32_t)(0x00000070UL) /*!< RW, Selects area1 */
#define FC_AREASEL_MASK_AREA0 (uint32_t)(0xFF8F0FF8UL) //mask Area 0
#define FC_AREASEL_MASK_AREA1 (uint32_t)(0xFF8F0F8FUL) /*!< RW, Selects area1 */
#define FC_AREASEL_WRITEA0_MODE (uint32_t)(0x04000000UL) /*!< R, Write Mode(area0) */
#define FC_AREASEL_WRITEA1_MODE (uint32_t)(0x08000000UL) /*!< R, Write Mode(area1) */
static uint32_t fc_const_code_flash_address[FC_MAX_PAGES] = {
(0x5E000000UL), /*!< CODE FLASH Page0 */
(0x5E001000UL), /*!< CODE FLASH Page1 */
(0x5E002000UL), /*!< CODE FLASH Page2 */
(0x5E003000UL), /*!< CODE FLASH Page3 */
(0x5E004000UL), /*!< CODE FLASH Page4 */
(0x5E005000UL), /*!< CODE FLASH Page5 */
(0x5E006000UL), /*!< CODE FLASH Page6 */
(0x5E007000UL), /*!< CODE FLASH Page7 */
(0x5E008000UL), /*!< CODE FLASH Page8 */
(0x5E009000UL), /*!< CODE FLASH Page9 */
(0x5E00A000UL), /*!< CODE FLASH Page10 */
(0x5E00B000UL), /*!< CODE FLASH Page11 */
(0x5E00C000UL), /*!< CODE FLASH Page12 */
(0x5E00D000UL), /*!< CODE FLASH Page13 */
(0x5E00E000UL), /*!< CODE FLASH Page14 */
(0x5E00F000UL), /*!< CODE FLASH Page15 */
(0x5E010000UL), /*!< CODE FLASH Page16 */
(0x5E011000UL), /*!< CODE FLASH Page17 */
(0x5E012000UL), /*!< CODE FLASH Page18 */
(0x5E013000UL), /*!< CODE FLASH Page19 */
(0x5E014000UL), /*!< CODE FLASH Page20 */
(0x5E015000UL), /*!< CODE FLASH Page21 */
(0x5E016000UL), /*!< CODE FLASH Page22 */
(0x5E017000UL), /*!< CODE FLASH Page23 */
(0x5E018000UL), /*!< CODE FLASH Page24 */
(0x5E019000UL), /*!< CODE FLASH Page25 */
(0x5E01A000UL), /*!< CODE FLASH Page26 */
(0x5E01B000UL), /*!< CODE FLASH Page27 */
(0x5E01C000UL), /*!< CODE FLASH Page28 */
(0x5E01D000UL), /*!< CODE FLASH Page29 */
(0x5E01E000UL), /*!< CODE FLASH Page30 */
(0x5E01F000UL) /*!< CODE FLASH Page31 */
};
/**
* @}
*/ /* End of group Flash_Userboot_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define
* @{
*/
/**
* @defgroup Flash_Userboot_Private_typedef Flash_Userboot Private Typedef
* @{
*/
/**
* @}
*/ /* End of group Flash_Userboot_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Private Member */
/*------------------------------------------------------------------------------*/
/**
* @defgroup Flash_Userboot_Private_variables Flash_Userboot Private Variables
* @{
*/
/**
* @}
*/ /* End of group Flash_Userboot_Private_variables */
/*------------------------------------------------------------------------------*/
/* Private Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup Flash_Userboot_Private_fuctions Flash_Userboot Private Fuctions
* @{
*/
__STATIC_INLINE TXZ_Result fc_enable_areasel0(void);
__STATIC_INLINE TXZ_Result fc_disable_areasel0(void);
__STATIC_INLINE TXZ_Result fc_enable_areasel1(void);
__STATIC_INLINE TXZ_Result fc_disable_areasel1(void);
static void fc_write_command(uint32_t *src_address, uint32_t *dst_address, uint32_t size);
static TXZ_Result fc_verify_check(uint32_t *src_address, uint32_t *dst_address, uint32_t size);
static TXZ_Result fc_erase_command(uint32_t *flash_top_address, uint32_t *erase_top_address, fc_erase_kind_t kind);
static TXZ_Result fc_blank_check(uint32_t *address, uint32_t size);
/*--------------------------------------------------*/
/**
* @brief Enables the AREA0.
* @param -
* @return Result.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note It works in the inner RAM.
* This function write the FCAREASEL regiset.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
__STATIC_INLINE TXZ_Result fc_enable_areasel0(void)
{
TXZ_Result retval = TXZ_ERROR;
uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0;
reg |= FC_AREASEL_AREA0;
/* Writes the FCKER register the KEYCODE. */
TSB_FC->KCR = FC_KCR_KEYCODE;
/* Selects the area0 */
TSB_FC->AREASEL = reg;
/* Confirms the FCAREASEL register the SSF0 was set. */
while (1) {
uint32_t i = TSB_FC->AREASEL;
if ((i & FC_AREASEL_WRITEA0_MODE) == FC_AREASEL_WRITEA0_MODE) {
retval = TXZ_SUCCESS;
break;
}
}
return (retval);
}
/*--------------------------------------------------*/
/**
* @brief Disables the AREA0.
* @param -
* @return Result.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note It works in the inner RAM.
* This function write the FCAREASEL regiset.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
__STATIC_INLINE TXZ_Result fc_disable_areasel0(void)
{
TXZ_Result retval = TXZ_ERROR;
uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0;
reg |= FC_AREASEL_EXPECT_AREA0;
/* Writes the FCKER register the KEYCODE. */
TSB_FC->KCR = FC_KCR_KEYCODE;
/* Selects the area0 */
TSB_FC->AREASEL = reg;
/* Confirms the SSF0 of the FCAREASEL register is not set. */
while (1) {
uint32_t i = TSB_FC->AREASEL;
if ((i & FC_AREASEL_WRITEA0_MODE) != FC_AREASEL_WRITEA0_MODE) {
retval = TXZ_SUCCESS;
break;
}
}
return (retval);
}
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
__STATIC_INLINE TXZ_Result fc_enable_areasel1(void)
{
TXZ_Result retval = TXZ_ERROR;
uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA1;
reg |= FC_AREASEL_AREA1;
TSB_FC->KCR = FC_KCR_KEYCODE;
TSB_FC->AREASEL = reg;
while (1) {
uint32_t i = TSB_FC->AREASEL;
if ((i & FC_AREASEL_WRITEA1_MODE) == FC_AREASEL_WRITEA1_MODE) {
retval = TXZ_SUCCESS;
break;
}
}
return (retval);
}
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
__STATIC_INLINE TXZ_Result fc_disable_areasel1(void)
{
TXZ_Result retval = TXZ_ERROR;
uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA1;
reg |= FC_AREASEL_EXPECT_AREA1;
TSB_FC->KCR = FC_KCR_KEYCODE;
TSB_FC->AREASEL = reg;
while (1) {
uint32_t i = TSB_FC->AREASEL;
if ((i & FC_AREASEL_WRITEA1_MODE) != FC_AREASEL_WRITEA1_MODE) {
retval = TXZ_SUCCESS;
break;
}
}
return (retval);
}
/*--------------------------------------------------*/
/**
* @brief Writes data of the Flash ROM.
* @param uint32_t* : src_address
* @param uint32_t* : dst_address
* @param uint32_t : size
* @return -
* @note It works in the inner RAM.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
static void fc_write_command(uint32_t *src_address, uint32_t *dst_address, uint32_t size)
{
uint32_t retval1;
uint32_t retval0;
volatile uint32_t *addr1;
volatile uint32_t *addr2;
volatile uint32_t *addr3;
uint32_t *source = (uint32_t *) src_address;
addr1 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR);
addr2 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR);
addr3 = (uint32_t *)((uint32_t)dst_address + FC_CODE_FLASH_ADDRESS_TOP);
/* Enables the AREA0. Write Mode. */
retval0 = fc_enable_areasel0();
retval1 = fc_enable_areasel1();
if ((retval0 == TXZ_SUCCESS)
&& (retval1 == TXZ_SUCCESS)) {
uint32_t i;
*addr1 = (0x000000AAUL); /* bus cycle 1 */
*addr2 = (0x00000055UL); /* bus cycle 2 */
*addr1 = (0x000000A0UL); /* bus cycle 3 */
for (i = (0UL); i < size; i += (0x4UL)) {
*addr3 = *source;
source++;
}
/* Confirmation of the works start of ROM. */
while (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) {
};
/* Waits for a finish of the works in the code Flash ROM. */
while (fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY) {
};
}
/* Disables the AREA0. Read Mode. */
retval0 = fc_disable_areasel0();
retval1 = fc_disable_areasel1();
}
/*--------------------------------------------------*/
/**
* @brief Verifies data of the Flash ROM.
* @param uint32_t* : src_address
* @param uint32_t* : dst_address
* @param uint32_t : size
* @return Result.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note It works in the inner RAM.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
static TXZ_Result fc_verify_check(uint32_t *src_address, uint32_t *dst_address, uint32_t size)
{
TXZ_Result retval = TXZ_ERROR;
int res = memcmp(src_address, dst_address, size);
if (res == 0) {
retval = TXZ_SUCCESS;
}
return (retval);
}
/*--------------------------------------------------*/
/**
* @brief Auro page erase command of the flash ROM.
* @param uint32_t* flash_top_address : flash top address
* @param uint32_t* erase_top_address : erase top address
* @param fc_erase_kind_t kind : Chip, Area, Block, Page, etc.
* @return -
* @note This function erases specified place of the flash ROM.
*/
/*--------------------------------------------------*/
//TXZ_Result fc_erase_pages_flash(uint32_t* top_address, uint32_t* erase_top_address)
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
static TXZ_Result fc_erase_command(uint32_t *flash_top_address, uint32_t *erase_top_address, fc_erase_kind_t kind)
{
TXZ_Result retval0;
TXZ_Result retval1;
volatile uint32_t *addr1 = (uint32_t *)((uint32_t)flash_top_address + FC_CMD_BC1_ADDR);
volatile uint32_t *addr2 = (uint32_t *)((uint32_t)flash_top_address + FC_CMD_BC2_ADDR);
volatile uint32_t *addr3 = (uint32_t *) erase_top_address;
/* Enables the AREA0. Write Mode. */
retval0 = fc_enable_areasel0();
retval1 = fc_enable_areasel1();
if ((retval0 == TXZ_SUCCESS)
&& (retval1 == TXZ_SUCCESS)) {
*addr1 = (0x000000AAUL);
*addr2 = (0x00000055UL);
*addr1 = (0x00000080UL);
*addr1 = (0x000000AAUL);
*addr2 = (0x00000055UL);
*addr3 = kind;
/* Confirmation of the works start of ROM. */
while (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) {
};
/* Waits for a finish of the works in the code Flash ROM. */
while (fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY) {
};
}
/* Disables the AREA0. Read Mode. */
retval0 = fc_disable_areasel0();
retval1 = fc_disable_areasel1();
}
/*--------------------------------------------------*/
/**
* @brief Checks a blank of the Flash ROM every 4bytes.
* @param uint32_t* : addrress
* @param uint32_t : size
* @return Result.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note It works in the inner RAM.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
static TXZ_Result fc_blank_check(uint32_t *address, uint32_t size)
{
TXZ_Result retval = TXZ_SUCCESS;
uint32_t i;
for (i = 0; i < (size / sizeof(uint32_t)); i++) {
uint32_t *addr = &address[i];
if (*addr != FC_BRANK_VALUE) {
retval = TXZ_ERROR;
break;
}
}
return (retval);
}
/**
* @}
*/ /* End of group Flash_Userboot_Private_fuctions */
/*------------------------------------------------------------------------------*/
/* Public Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup Flash_Userboot_Exported_functions Flash_Userboot Exported Functions
* @{
*/
/*--------------------------------------------------*/
/**
* @brief Get the status of the flash auto operation.
* @param fc_sr0_t : status
* @return Result.
* @retval TXZ_BUSY : Busy.
* @retval TXZ_DONE : Done.
* @note It works in the inner RAM.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
TXZ_WorkState fc_get_status(fc_sr0_t status)
{
TXZ_WorkState retval = TXZ_BUSY;
uint32_t work32;
/* Reads the FCSR0. Masks the other specfic status */
work32 = TSB_FC->SR0 & (uint32_t)status;
/* Confirms the specific status of the flash ROM */
if (work32 == (uint32_t)status) {
retval = TXZ_DONE;
}
return (retval);
}
/*--------------------------------------------------*/
/**
* @brief Auto write command of the code flash ROM.
* @param uint32_t* : src_address
* @param uint32_t* : dst_address
* @param uint32_t : size
* @return Result.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note It works in the inner RAM.
* This function writes 16bytes data to the code Flash ROM.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
TXZ_Result fc_write_code_flash(uint32_t *src_address, uint32_t *dst_address, uint32_t size)
{
TXZ_Result retval = TXZ_SUCCESS;
/* Checks the code Flash ROM status */
if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) {
uint32_t i;
/* Checks the code Flash ROM status */
for (i = 0; i < size; i += (uint32_t)(0x10UL)) {
/* Writes 16bytes data. */
fc_write_command((uint32_t *)((uint32_t)src_address + i), (uint32_t *)((uint32_t)dst_address + i), (uint32_t)(0x10UL));
}
/* Verifies user data and data of the Flash ROM. */
retval = fc_verify_check(src_address, dst_address, size);
}
return (retval);
}
/*--------------------------------------------------*/
/**
* @brief Auro page erase command of the code flash ROM.
* @param first_page : The first page to erase
* @param num_of_pages : The number of pages to erase.
* @return Result.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note It works in the inner RAM.
* This function erases specified page of the code Flash ROM and checks a blank.
*/
/*--------------------------------------------------*/
TXZ_Result fc_erase_page_code_flash(fc_code_flash_page_number_t first_page, uint8_t num_of_pages)
{
TXZ_Result retval = TXZ_SUCCESS;
/* Checks the code Flash ROM status */
if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) {
/* Checks the number of maximum pages. */
if ((first_page + num_of_pages) <= FC_MAX_PAGES) {
uint8_t i;
for (i = 0; i < num_of_pages ; i++) {
/* Erases the specific page. */
fc_erase_command((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP,
(uint32_t *)fc_const_code_flash_address[first_page + i],
FC_ERASE_KIND_PAGE);
}
/* Checks a blank of the specific page. */
if (fc_blank_check((uint32_t *)fc_const_code_flash_address[first_page], FC_PAGE_SIZE * (uint32_t)num_of_pages) == TXZ_ERROR) {
retval = TXZ_ERROR;
}
} else {
retval = TXZ_ERROR;
}
} else {
retval = TXZ_ERROR;
}
return (retval);
}
/*--------------------------------------------------*/
/**
* @brief Checks a blank of the code Flash ROM of specified pages.
* @param first_page : The first page which checks a blank.
* @param last_page : The last page which checks a blank..
* @return Result.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note It works in the inner RAM.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
TXZ_Result fc_blank_check_page_code_flash(fc_code_flash_page_number_t first_page, fc_code_flash_page_number_t last_page)
{
TXZ_Result retval;
uint32_t *address = (uint32_t *)fc_const_code_flash_address[first_page];
uint32_t size = ((uint32_t)(last_page - first_page + 1) * (uint32_t)FC_PAGE_SIZE);
retval = fc_blank_check(address, size);
return (retval);
}
/*--------------------------------------------------*/
/*************** written by TSIP ******************/
/**
* @brief Erases the entire block of code Flash ROM of specified address.
* @param uint32_t *top_addr : top address of Flash ROM.
* @param uint32_t *blk_addr : start address of block to be erased.
* @return Result.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note It works in the inner RAM.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
TXZ_Result fc_erase_block_code_flash(uint32_t *top_addr, uint32_t *blk_addr)
{
TXZ_Result retval = TXZ_SUCCESS;
/* Checks the code Flash ROM status */
if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) {
/* Erases the specific block. */
fc_erase_command((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP, blk_addr, FC_ERASE_KIND_BLOCK);
/* Checks a blank of the specific block. */
if (fc_blank_check(blk_addr, (uint32_t)0x8000) == TXZ_ERROR) {
retval = TXZ_ERROR;
} else {
// do nothing
}
} else {
retval = TXZ_ERROR;
}
return (retval);
}
/**
* @}
*/ /* End of group Flash_Userboot_Exported_functions */
/**
* @}
*/ /* End of group Flash_Userboot */
/**
* @}
*/ /* End of group Example */
#ifdef __cplusplus
}
#endif /* __cplusplus */

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/**
*******************************************************************************
* @file txz_flash.c
* @brief This file provides API functions for driver common part.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_flash.h"
#if defined(__FLASH_H)
/**
* @addtogroup Periph_Driver
* @{
*/
/**
* @addtogroup FLASH
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup FLASH_Private_macro FLASH Private Macro
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FLASH_Private_macro */
/*------------------------------------------------------------------------------*/
/* Configuration */
/*------------------------------------------------------------------------------*/
/**
* @defgroup FLASH_Private_define FLASH Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FLASH_Private_define */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup FLASH_Private_define FLASH Private Define
* @{
*/
/**
* @defgroup wait Configuration
* @brief wait Configuration.
* @{
*/
/* FC ACCR setting configration */
#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */
#define FC_ACCR_CODE_7CLK (0x00000006UL) /*!< 7clock(less than 200MHZ). */
#define FC_ACCR_CODE_6CLK (0x00000005UL) /*!< 6clock(less than 160MHZ). */
#define FC_ACCR_CODE_5CLK (0x00000004UL) /*!< 5clock(less than 120MHZ). */
#define FC_ACCR_CODE_4CLK (0x00000003UL) /*!< 4clock(less than 100MHZ). */
#define FC_ACCR_CODE_3CLK (0x00000002UL) /*!< 3clock(less than 80MHZ). */
#define FC_ACCR_200MHZ (200000000UL) /*!< 200MHZ */
#define FC_ACCR_160MHZ (160000000UL) /*!< 160MHZ */
#define FC_ACCR_120MHZ (120000000UL) /*!< 120MHZ */
#define FC_ACCR_100MHZ (100000000UL) /*!< 100MHZ */
#define FC_ACCR_80MHZ ( 80000000UL) /*!< 80MHZ */
#define FC_ACCR_DATA (FC_ACCR_DATA_7CLK)
#define FC_ACCR_DATA_7CLK (0x00000600UL) /*!< 7clock(Must). */
/**
* @}
*/ /* End of group waitConfiguration */
/* no define */
/**
* @}
*/ /* End of group FLASH_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup FLASH_Private_define FLASH Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FLASH_Private_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup FLASH_Private_typedef FLASH Private Typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FLASH_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Private Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup FLASH_Private_fuctions FLASH Private Fuctions
* @{
*/
/**
* @}
*/ /* End of group FLASH_Private_functions */
/*------------------------------------------------------------------------------*/
/* Public Function */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup FLASH_Exported_functions
* @{
*/
/*--------------------------------------------------*/
/**
* @brief Raed clock set.
* @param none.
* @retval none.
* @note It works in the inner RAM.
*/
/*--------------------------------------------------*/
void fc_read_clock_set(uint32_t sysclock)
{
uint32_t regval = 0;
if (sysclock <= FC_ACCR_80MHZ) { /* less than 80MHZ */
regval = (uint32_t)(FC_ACCR_CODE_3CLK | FC_ACCR_DATA);
TSB_FC->KCR = FC_KCR_KEYCODE;
TSB_FC->ACCR = regval;
while (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_3CLK | FC_ACCR_DATA)) {
}
} else if (sysclock <= FC_ACCR_100MHZ) { /* less than 100MHZ */
regval = (uint32_t)(FC_ACCR_CODE_4CLK | FC_ACCR_DATA);
TSB_FC->KCR = FC_KCR_KEYCODE;
TSB_FC->ACCR = regval;
while (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_4CLK | FC_ACCR_DATA)) {
}
} else if (sysclock <= FC_ACCR_120MHZ) { /* less than 120MHZ */
regval = (uint32_t)(FC_ACCR_CODE_5CLK | FC_ACCR_DATA);
TSB_FC->KCR = FC_KCR_KEYCODE;
TSB_FC->ACCR = regval;
while (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_5CLK | FC_ACCR_DATA)) {
}
} else if (sysclock <= FC_ACCR_160MHZ) { /* less than 160MHZ */
regval = (uint32_t)(FC_ACCR_CODE_6CLK | FC_ACCR_DATA);
TSB_FC->KCR = FC_KCR_KEYCODE;
TSB_FC->ACCR = regval;
while (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_6CLK | FC_ACCR_DATA)) {
}
} else if (sysclock <= FC_ACCR_200MHZ) { /* less than 200MHZ */
regval = (uint32_t)(FC_ACCR_CODE_7CLK | FC_ACCR_DATA);
TSB_FC->KCR = FC_KCR_KEYCODE;
TSB_FC->ACCR = regval;
while (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_7CLK | FC_ACCR_DATA)) {
/* no processing */
}
} else {
/* no processing */
}
}
/**
* @}
*/ /* End of group FLASH_Exported_functions */
/**
* @}
*/ /* End of group FLASH */
/**
* @}
*/ /* End of group Periph_Driver */
#endif /* defined(__FLASH_H) */
#ifdef __cplusplus
}
#endif /* __cplusplus */

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/**
*******************************************************************************
* @file txz_fuart_ex.c
* @brief This file provides API functions for FUART driver.
* @brief Extended functionality.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_fuart_include.h"
#include "txz_fuart_ex.h"
#if defined(__FUART_EX_H)
/**
* @addtogroup Periph_Driver
* @{
*/
/**
* @addtogroup UART
* @{
*/
/*------------------------------------------------------------------------------*/
/* Configuration */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup FUART_Private_define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FUART_Private_define */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup FUART_Private_define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FUART_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup FUART_Private_define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FUART_Private_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup FUART_Private_typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group FUART_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Private Function */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup FUART_Private_fuctions
* @{
*/
/**
* @}
*/ /* End of group FUART_Private_functions */
/*------------------------------------------------------------------------------*/
/* Public Function */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup FUART_Exported_functions
* @{
*/
/*--------------------------------------------------*/
/**
* @brief Send Break.
* @param p_obj :UART object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @attention This function is not available in interrupt.
* @attention Use after interrupt is disabled.
*/
/*--------------------------------------------------*/
TXZ_Result fuart_send_break(fuart_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef __DEBUG__
/* Check the FUART_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
#endif /* #ifdef __DEBUG__ */
/*------------------------------*/
/* Set Break */
/*------------------------------*/
{
uint32_t trans = p_obj->p_instance->LCR_H;
trans &= ~FUARTxLCR_H_BRK_MASK;
trans |= FUARTxLCR_H_BRK_SEND;
p_obj->p_instance->LCR_H = trans;
}
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Stop Break.
* @param p_obj :UART object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @attention This function is not available in interrupt.
* @attention Use after interrupt is disabled.
*/
/*--------------------------------------------------*/
TXZ_Result fuart_stop_break(fuart_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef __DEBUG__
/* Check the FUART_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
#endif /* #ifdef __DEBUG__ */
/*------------------------------*/
/* Set Break */
/*------------------------------*/
{
uint32_t trans = p_obj->p_instance->LCR_H;
trans &= ~FUARTxLCR_H_BRK_MASK;
trans |= FUARTxLCR_H_BRK_STOP;
p_obj->p_instance->LCR_H = trans;
}
return (result);
}
/**
* @}
*/ /* End of group FUART_Exported_functions */
/**
* @}
*/ /* End of group FUART */
/**
* @}
*/ /* End of group Periph_Driver */
#endif /* defined(__UART_EX_H) */
#ifdef __cplusplus
}
#endif /* __cplusplus */

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/**
*******************************************************************************
* @file txz_hal.c
* @brief This file provides API functions for driver common part.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_hal.h"
#if defined(__HAL_H)
/**
* @addtogroup Periph_Driver
* @{
*/
/**
* @addtogroup HAL
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup HAL_Private_macro HAL Private Macro
* @{
*/
/* no define */
/**
* @}
*/ /* End of group HAL_Private_macro */
/*------------------------------------------------------------------------------*/
/* Configuration */
/*------------------------------------------------------------------------------*/
/**
* @defgroup HAL_Private_define HAL Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group HAL_Private_define */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup HAL_Private_define HAL Private Define
* @{
*/
/**
* @defgroup wait Configuration
* @brief wait Configuration.
* @{
*/
#define WAIT_UNIT_1US ((uint32_t)(1000000)) /*!< 1S-1us transfor unit. */
#define WAIT_FORLOOP_STEPS ((uint32_t)(5)) /*!< for loop steps. */
#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */
#define FC_ACCR_200MHZ (200000000UL) /*!< 200MHZ */
#define FC_ACCR_160MHZ (160000000UL) /*!< 160MHZ */
#define FC_ACCR_120MHZ (120000000UL) /*!< 120MHZ */
#define FC_ACCR_100MHZ (100000000UL) /*!< 100MHZ */
#define FC_ACCR_80MHZ ( 80000000UL) /*!< 80MHZ */
/* FC RACCR setting configration */
#define FC_RACCR_RAMLC_1CLK (0x00000000UL) /*!< 1clock(less than 160MHZ). */
#define FC_RACCR_RAMLC_2CLK (0x00000010UL) /*!< 2clock(more than 160MHZ). */
/**
* @}
*/ /* End of group waitConfiguration */
/* no define */
/**
* @}
*/ /* End of group HAL_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup HAL_Private_define HAL Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group HAL_Private_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup HAL_Private_typedef HAL Private Typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group HAL_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Private Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup HAL_Private_fuctions HAL Private Fuctions
* @{
*/
static uint32_t tick;
/**
* @}
*/ /* End of group HAL_Private_functions */
/*------------------------------------------------------------------------------*/
/* Public Function */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup HAL_Exported_functions
* @{
*/
/*--------------------------------------------------*/
/**
* @brief Increment a tick value.
* @param -
* @retval -
* @note Please call by user.
* @note In the sample, this variable is incremented each 1ms timer interrupt.
*/
/*--------------------------------------------------*/
void hal_inc_tick(void)
{
tick++;
}
/*--------------------------------------------------*/
/**
* @brief Provides a tick value.
* @param -
* @return Tick value.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
uint32_t hal_get_tick(void)
{
return (tick);
}
/*--------------------------------------------------*/
/**
* @brief wait Function(us)
* @param uint32_t :count(unit:us).
* @return void
* @retval -
* @note -
*/
/*--------------------------------------------------*/
void wait(uint32_t count)
{
uint32_t i, steps;
/*-----------------------------------------*/
/* step : 1000000us = fsys :1 */
/* step = EOSC_SYS_CLOCK/1000000 */
/*-----------------------------------------*/
/* system core clock update */
SystemCoreClockUpdate();
steps = count * (SystemCoreClock / WAIT_UNIT_1US) / WAIT_FORLOOP_STEPS;
for (i = 0; i < steps; ++i) {
__NOP();
}
}
/*--------------------------------------------------*/
/**
* @brief copy 32-bit data from source to dest
* @param the address of source and dast, the data size
* @retval None.
* @note -
*/
/*--------------------------------------------------*/
void Copy_Routine(uint32_t *dest, uint32_t *source, uint32_t size)
{
uint32_t *dest_addr, *source_addr, tmpsize;
uint32_t i, tmps, tmpd, mask;
dest_addr = dest;
source_addr = source;
tmpsize = size >> 2U;
for (i = 0U; i < tmpsize; i++) { /* 32bits copy */
*dest_addr = *source_addr;
dest_addr++;
source_addr++;
}
if (size & 0x00000003U) { /* if the last data size is not 0(maybe 1,2 or 3), copy the last data */
mask = 0xFFFFFF00U;
i = size & 0x00000003U;
tmps = *source_addr;
tmpd = *dest_addr;
while (i - 1U) {
mask = mask << 8U;
i--;
}
tmps = tmps & (~mask);
tmpd = tmpd & (mask);
*dest_addr = tmps + tmpd; /* 32bits copy, but only change the bytes need to be changed */
} else {
/* Do nothing */
}
}
/*--------------------------------------------------*/
/**
* @brief RAM register set.
* @param none.
* @retval none.
* @note -
*/
/*--------------------------------------------------*/
void fc_ram_con_reg_set(uint32_t sysclock)
{
uint32_t regval = 0;
if (sysclock <= FC_ACCR_160MHZ) { /* less than 160MHZ */
regval = (uint32_t)FC_RACCR_RAMLC_1CLK;
TSB_FC->KCR = FC_KCR_KEYCODE;
TSB_FC->RACCR = regval;
while (TSB_FC->RACCR != (uint32_t)FC_RACCR_RAMLC_1CLK) {
}
} else { /* more than 160MHZ */
regval = (uint32_t)FC_RACCR_RAMLC_2CLK;
TSB_FC->KCR = FC_KCR_KEYCODE;
TSB_FC->RACCR = regval;
while (TSB_FC->RACCR != (uint32_t)FC_RACCR_RAMLC_2CLK) {
/* no processing */
}
}
}
/**
* @}
*/ /* End of group HAL_Exported_functions */
/**
* @}
*/ /* End of group HAL */
/**
* @}
*/ /* End of group Periph_Driver */
#endif /* defined(__HAL_H) */
#ifdef __cplusplus
}
#endif /* __cplusplus */

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/**
*******************************************************************************
* @file txz_i2c.c
* @brief This file provides API functions for I2C Class.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txz_i2c.h"
#if defined(__I2C_H)
/**
* @addtogroup Example
* @{
*/
/**
* @addtogroup UTILITIES
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Function */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_macro
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_macro */
/*------------------------------------------------------------------------------*/
/* Configuration */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_define */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_define
* @{
*/
/**
* @}
*/ /* End of group UTILITIES_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Private Member */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_variables
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_variables */
/*------------------------------------------------------------------------------*/
/* Const Table */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_const
* @{
*/
/*----------------------------------*/
/**
* @brief SCK Divider value table.
* @details SCK = b000 - b111.
* @note NFSEL=0 (Digital Setting) Divider value.
*/
/*----------------------------------*/
static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { 20, 24, 32, 48, 80, 144, 272, 528 };
static const uint32_t I2C_SCK_LOW_MUL_TBL[8] = { 12, 14, 18, 26, 42, 74, 138, 266 };
/**
* @}
*/ /* End of group UTILITIES_Private_const */
/*------------------------------------------------------------------------------*/
/* Private Function */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_functions
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_functions */
/*------------------------------------------------------------------------------*/
/* Public Function */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_functions
* @{
*/
/*--------------------------------------------------*/
/**
* @brief Initializing I2C Regester
* @param p_obj :I2C object.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
void I2C_init(I2C_t *p_obj)
{
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef __DEBUG__
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef __DEBUG__ */
p_obj->p_instance->CR2 = I2CxCR2_I2CM_ENABLE;
p_obj->p_instance->OP = I2CxOP_INIT;
p_obj->p_instance->CR1 = (I2CxCR1_ACK | I2CxCR1_NOACK | p_obj->init.clock.sck);
p_obj->p_instance->AR = I2CxAR_INIT;
p_obj->p_instance->AR2 = I2CxAR2_INIT;
p_obj->p_instance->CR2 = I2CxCR2_INIT;
p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck);
p_obj->p_instance->IE = I2CxIE_CLEAR;
}
/*--------------------------------------------------*/
/**
* @brief Generate start condition
* @param p_obj :I2C object.
* @param data :Slave address.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
void I2C_start_condition(I2C_t *p_obj, uint32_t data)
{
__IO uint32_t opreg;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef __DEBUG__
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef __DEBUG__ */
opreg = p_obj->p_instance->OP;
opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN);
if (I2C_master(p_obj)) {
if ((p_obj->p_instance->SR & I2CxSR_BB)) {
opreg |= I2CxOP_SREN;
}
}
p_obj->p_instance->CR1 = (I2CxCR1_ACK | I2CxCR1_NOACK | p_obj->init.clock.sck);
p_obj->p_instance->OP = opreg;
p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK);
p_obj->p_instance->CR2 = I2CxCR2_START_CONDITION;
}
/*--------------------------------------------------*/
/**
* @brief Return the I2c clock setting
* @param p_obj :I2C object.
* @param frequency :Maximum frequency.
* @param fsys :SystemCoreClock.
* @param p_setting :Clock data pointer.
* @retval Non-zero :Scl frequency.
* @retval 0 :Error.
* @note -
*/
/*--------------------------------------------------*/
uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting)
{
uint32_t result = 0;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef __DEBUG__
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
assert_param(IS_POINTER_NOT_NULL(p_setting));
#endif /* #ifdef __DEBUG__ */
if (frequency <= 1000000) {
uint64_t sck, tmp_sck;
uint64_t prsck, tmp_prsck;
uint64_t fscl, tmp_fscl;
uint64_t fx;
uint64_t max_fx, min_fx;
uint64_t low_width, low_width_min;
sck = tmp_sck = 0;
prsck = tmp_prsck = 1;
fscl = tmp_fscl = 0;
if (frequency <= 400000) {
max_fx = 11428572U; /* Tpresck: 87.5ns 1/87.5 = 0.0114285714 */
min_fx = 6666666U; /* Tpresck:150.0ns 1/150 = 0.0066666667 */
low_width_min = 1600;
} else {
max_fx = 26666667U; /* Tpresck:37.5ns 1/37.5 = 0.0266666667 */
min_fx = 15384615U; /* Tpresck:65.0ns 1/65 = 0.0153846154 */
low_width_min = 675;
}
for (prsck = 1; prsck <= 32; prsck++) {
fx = ((uint64_t)fsys / prsck);
if ((fx < max_fx) && (fx >= min_fx)) {
for (sck = 0; sck <= 7; sck++) {
low_width = (uint64_t)(1000000000 * prsck * I2C_SCK_LOW_MUL_TBL[sck]) / fsys;
if (low_width < low_width_min) {
continue;
}
fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]);
if ((fscl <= frequency) && (fscl > tmp_fscl)) {
tmp_fscl = fscl;
tmp_sck = sck;
tmp_prsck = (prsck < 32) ? prsck : 0;
}
}
}
}
result = (uint32_t)tmp_fscl;
p_setting->sck = (uint32_t)tmp_sck;
p_setting->prsck = (tmp_prsck < 32) ? (uint32_t)tmp_prsck : 0;
} else {
result = 0;
}
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Slave mode setting.
* @param p_obj :I2C object.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
void I2C_slave_init(I2C_t *p_obj)
{
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef __DEBUG__
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef __DEBUG__ */
p_obj->p_instance->OP = I2CxOP_SLAVE_INIT;
p_obj->p_instance->CR1 = (I2CxCR1_ACK | p_obj->init.clock.sck);
p_obj->p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR);
p_obj->p_instance->CR2 = I2CxCR2_INIT;
p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck);
}
#if defined(I2CSxWUP_EN)
/*--------------------------------------------------*/
/**
* @brief I2C Wakeup Control setting.
* @param p_obj :I2CS object.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
void I2CS_init(I2CS_t *p_obj)
{
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef __DEBUG__
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef __DEBUG__ */
p_obj->p_instance->WUPCR1 = (p_obj->init.wup.sgcdi | p_obj->init.wup.ack | p_obj->init.wup.reset | p_obj->init.wup.intend);
}
/*--------------------------------------------------*/
/**
* @brief Primary Slave Address setting.
* @param p_obj :I2CS object.
* @param addr :Primary Slave Address.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr)
{
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef __DEBUG__
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef __DEBUG__ */
p_obj->p_instance->WUPCR2 = (0x0000000E & adr);
}
/*--------------------------------------------------*/
/**
* @brief Secondary Slave Address setting.
* @param p_obj :I2CS object.
* @param addr :Secondary Slave Address.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr)
{
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef __DEBUG__
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef __DEBUG__ */
p_obj->p_instance->WUPCR3 = (0x0000000E & adr);
p_obj->p_instance->WUPCR3 |= 0x00000001; /* WUPSA2EN: Secondary Slave Address Use Setting */
}
#endif
/**
* @}
*/ /* End of group UTILITIES_Private_functions */
/**
* @}
*/ /* End of group UTILITIES */
/**
* @}
*/ /* End of group Example */
#endif /* defined(__I2C_H) */
#ifdef __cplusplus
}
#endif /* __cplusplus */

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SERIAL_0 = 0,
SERIAL_1,
SERIAL_2,
SERIAL_3,
SERIAL_4,
SERIAL_5,
INVALID_SERIAL = (int)NC
} UARTName;
typedef enum {
DAC_0 = 0,
DAC_1,
INVALID_DAC = (int)NC
} DACName;
typedef enum {
PWM_0 = 0,
PWM_1,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
PWM_8,
PWM_9,
PWM_10,
PWM_11,
PWM_12,
INVALID_PWM = (int)NC
} PWMName;
typedef enum {
ADC_A0 = 0,
ADC_A1,
ADC_A2,
ADC_A3,
ADC_A4,
ADC_A5,
ADC_A6,
ADC_A7,
ADC_A9 = 9,
ADC_A14 = 14,
ADC_A17 = 17,
ADC_A18,
ADC_A19,
ADC_A20,
ADC_A21,
ADC_A22,
ADC_A23,
INVALID_ADC = (int)NC
} ADCName;
typedef enum {
I2C_0 = 0,
I2C_1,
I2C_2,
I2C_3,
INVALID_I2C = (int)NC
} I2CName;
typedef enum {
SPI_0 = 0,
SPI_1,
INVALID_SPI = (int)NC
} SPIName;
typedef enum {
GPIO_IRQ_0 = 0,
GPIO_IRQ_1,
GPIO_IRQ_2,
GPIO_IRQ_3,
GPIO_IRQ_4,
GPIO_IRQ_5,
GPIO_IRQ_6,
GPIO_IRQ_7,
GPIO_IRQ_8,
GPIO_IRQ_9,
GPIO_IRQ_A,
GPIO_IRQ_B,
GPIO_IRQ_C,
GPIO_IRQ_D,
GPIO_IRQ_E,
GPIO_IRQ_F,
INVALID_GPIO_IRQ = (int)NC
} GPIO_IRQName;
// DAP UART
#if defined(MBED_CONF_TARGET_STDIO_UART_TX)
#define STDIO_UART_TX MBED_CONF_TARGET_STDIO_UART_TX
#else
#define STDIO_UART_TX CONSOLE_TX
#endif
#if defined(MBED_CONF_TARGET_STDIO_UART_RX)
#define STDIO_UART_RX MBED_CONF_TARGET_STDIO_UART_RX
#else
#define STDIO_UART_RX CONSOLE_RX
#endif
#define SERIAL_TX PV1
#define SERIAL_RX PV0
#define STDIO_UART SERIAL_2
// TxD RxD
#define MBED_UART0 PE3, PE2
#define MBED_UART1 PV5, PV4
#define MBED_UART2 PV1, PV0
#define MBED_UART3 PJ1, PJ0
#define MBED_UART4 PJ4, PJ5
#define MBED_UART5 PJ6, PJ7
#define MBED_UARTUSB CONSOLE_TX, CONSOLE_RX
// SDA SCK
#define MBED_I2C0 PF2, PF3
#define MBED_I2C1 PV5, PV4
#define MBED_I2C2 PJ6, PJ7
#define MBED_I2C3 PJ3, PJ2
// MOSI, MISO, SCLK SS
#define MBED_SPI0 PA3, PA2, PA1, PA0
#define MBED_SPI1 PA4, PA5, PA6, PA7
#define MBED_ANALOGIN0 A0
#define MBED_ANALOGIN1 A1
#define MBED_ANALOGIN2 A2
#define MBED_ANALOGIN3 A3
#define MBED_ANALOGIN4 A4
#define MBED_ANALOGIN5 A5
#define MBED_PWMOUT0 PW1
#define MBED_PWMOUT1 PW2
#define MBED_PWMOUT2 PT3
#define MBED_PWMOUT3 PD2
#define MBED_PWMOUT4 PD4
#define MBED_PWMOUT5 PE1
#define MBED_PWMOUT6 PE6
#define MBED_PWMOUT7 PL4
#define MBED_PWMOUT8 PL6
#define MBED_PWMOUT9 PC4
#define MBED_PWMOUT10 PW6
#define MBED_PWMOUT11 PU0
#define MBED_PWMOUT12 PU6
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xFF)
#define PIN_POS(X) ((uint32_t)(X) & 0x7)
// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction
#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16) | ((DIR) << 0))
#define PIN_FUNC(X) (((X) & 0xffff0000) >> 16)
#define PIN_DIR(X) ((X) & 0xffff)
// Other mbed Pin Names
#define LED1 PW4
#define LED2 PW5
#define LED3 PW6
#define LED4 PW7
#define I2C_SDA SDA
#define I2C_SCL SCL
typedef enum {
PIN_INPUT,
PIN_OUTPUT,
PIN_INOUT
} PinDirection;
typedef enum {
// TMPM4NR Pin Names
PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
PB0 = 1 << 3, PB1, PB2, PB3,
PC4 = (2 << 3) | 4, PC5, PC6, PC7,
PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7,
PG0 = 6 << 3, PG1, PG2, PG3, PG4, PG5, PG6, PG7,
PH0 = 7 << 3, PH1, PH2, PH3, PH4, PH5, PH6, PH7,
PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7,
PK0 = 9 << 3, PK1, PK2, PK3, PK4, PK5, PK6, PK7,
PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, PL7,
PM0 = 11 << 3, PM1, PM2, PM3, PM4, PM5, PM6, PM7,
PN0 = 12 << 3, PN1, PN2, PN3, PN4, PN5, PN6, PN7,
PP0 = 13 << 3, PP1, PP2, PP3, PP4, PP5, PP6, PP7,
PR0 = 14 << 3, PR1, PR2, PR3, PR4, PR5, PR6, PR7,
PT0 = 15 << 3, PT1, PT2, PT3, PT4, PT5,
PU0 = 16 << 3,
PU2 = (16 << 3) | 2, PU3, PU4, PU5, PU6, PU7,
PV0 = 17 << 3, PV1, PV2, PV3, PV4, PV5, PV6, PV7,
PW0 = 18 << 3, PW1, PW2, PW3, PW4, PW5, PW6, PW7,
PY0 = 19 << 3, PY1, PY2, PY3, PY4,
// External data bus Pin Names
D0 = PJ1,
D1 = PJ0,
D2 = PM7,
D3 = PT5,
D4 = PM6,
D5 = PW3,
D6 = PW2,
D7 = PM5,
D8 = PM4,
D9 = PW1,
D10 = PA7,
D11 = PA4,
D12 = PA5,
D13 = PA6,
D14 = PF2,
D15 = PF3,
// Analogue in pins
A0 = PN0,
A1 = PN1,
A2 = PN2,
A3 = PN3,
A4 = PN4,
A5 = PN5,
// USB2_UART
CONSOLE_TX = PV1,
CONSOLE_RX = PV0,
MBEDIF_TXD = CONSOLE_TX,
MBEDIF_RXD = CONSOLE_RX,
MBED_CONF_APP_UART0_TX = PE3,
MBED_CONF_APP_UART0_RX = PE2,
// Switches
SW1 = PL5,
SW2 = PV2,
//SW3 = PV0,
//SW4 = PV1,
// I2C pins
SDA = PF2,
SCL = PF3,
// Analogue out
DAC0 = PT0,
DAC1 = PT1,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullUp = 0,
PullDown,
PullNone,
OpenDrain,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB,
PortC,
PortD,
PortE,
PortF,
PortG,
PortH,
PortJ,
PortK,
PortL,
PortM,
PortN,
PortP,
PortR,
PortT,
PortU,
PortV,
PortW,
PortY
} PortName;
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "analogin_api.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "mbed_wait_api.h"
#include "mbed_error.h"
#include "txz_adc_include.h"
#define ADC_12BIT_RANGE 0xFFF
#define CONVERSION_FLAG 0x4
static const PinMap PinMap_ADC[] = {
{PN0, ADC_A0, PIN_DATA(0, 0)},
{PN1, ADC_A1, PIN_DATA(0, 0)},
{PN2, ADC_A2, PIN_DATA(0, 0)},
{PN3, ADC_A3, PIN_DATA(0, 0)},
{PN4, ADC_A4, PIN_DATA(0, 0)},
{PN5, ADC_A5, PIN_DATA(0, 0)},
{PN6, ADC_A6, PIN_DATA(0, 0)},
{PN7, ADC_A7, PIN_DATA(0, 0)},
{PP1, ADC_A9, PIN_DATA(0, 0)},
{PP6, ADC_A14, PIN_DATA(0, 0)},
{PR1, ADC_A17, PIN_DATA(0, 0)},
{PR2, ADC_A18, PIN_DATA(0, 0)},
{PR3, ADC_A19, PIN_DATA(0, 0)},
{PR4, ADC_A20, PIN_DATA(0, 0)},
{PR5, ADC_A21, PIN_DATA(0, 0)},
{PR6, ADC_A22, PIN_DATA(0, 0)},
{PR7, ADC_A23, PIN_DATA(0, 0)},
{NC, NC, 0}
};
void analogin_init(analogin_t *obj, PinName pin)
{
// Check that pin belong to ADC module
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
// Enable ADC clock supply
TSB_CG_FSYSMENA_IPMENA03 = TXZ_ENABLE;
TSB_CG_SPCLKEN_ADCKEN = TXZ_ENABLE;
TSB_CG_SPCLKEN_TRCKEN = TXZ_ENABLE;
// Enable clock for GPIO
if (obj->adc <= ADC_A7) {
TSB_CG_FSYSMENB_IPMENB14 = TXZ_ENABLE;
} else if (obj->adc <= ADC_A14) {
TSB_CG_FSYSMENB_IPMENB15 = TXZ_ENABLE;
} else {
TSB_CG_FSYSMENB_IPMENB16 = TXZ_ENABLE;
}
// Set pin function as ADC
pinmap_pinout(pin, PinMap_ADC);
// Initialize
obj->p_adc.p_instance = TSB_ADA;
obj->p_adc.init.clk.exaz0 = ADC_SAMPLING_PERIOD0_XN;
obj->p_adc.init.clk.exaz1 = ADC_SAMPLING_PERIOD1_XN;
obj->p_adc.init.clk.vadcld = ADC_SCLK_5; /*less than 40MHz*/
obj->p_adc.init.clk.sampling_select = 0;
obj->p_adc.init.mod1 = ADC_MOD1_SCLK_4;
obj->p_adc.init.mod2 = ADC_MOD2_SET;
obj->p_adc.handler.single = NULL;
obj->p_adc.handler.continuity = NULL;
obj->p_adc.handler.trigger = NULL;
obj->p_adc.handler.highpriority = NULL;
if (adc_init(&obj->p_adc) != TXZ_SUCCESS) {
error("Failed : ADC Initialization");
}
// ADC channel setting
obj->param.interrupt = ADC_INT_DISABLE;
obj->param.type = ADC_CONVERSION_SGL;
obj->param.ain = obj->adc;
if (adc_channel_setting(&obj->p_adc, obj->param.ain, &obj->param) != TXZ_SUCCESS) {
error("Failed : ADC channel setting");
}
}
uint16_t analogin_read_u16(analogin_t *obj)
{
uint32_t adc_result = 0;
// Assert that ADC channel is valid
MBED_ASSERT(obj->adc != (ADCName)NC);
wait_us(7000); // Wait at least 7ms to ensure the voltage is stable
if (adc_start(&obj->p_adc) == TXZ_SUCCESS) {
// adc started
}
// Wait for Continuous conversion program flag clear.
while ((obj->p_adc.p_instance->ST & CONVERSION_FLAG)) {
// Do nothing
}
if (adc_channel_get_value(&obj->p_adc, obj->param.ain, &adc_result) != TXZ_SUCCESS) {
error("Failed : To read ADC converted result");
}
if (adc_stop(&obj->p_adc) != TXZ_SUCCESS) {
error("Failed : To Stop ADC Conversion");
}
return (uint16_t)adc_result;
}
float analogin_read(analogin_t *obj)
{
uint16_t value = 0;
value = analogin_read_u16(obj);
return (float)(value * (1.0f / (float)ADC_12BIT_RANGE));
}
const PinMap *analogin_pinmap()
{
return PinMap_ADC;
}

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "cmsis.h"
#include "analogout_api.h"
#include "pinmap.h"
#define REG_DAC_DAxCR_REN_DISABLE ((uint32_t)0x00000000) // DAC Control Disable.
#define REG_DAC_DAxCR_REN_ENABLE ((uint32_t)0x00000001) // DAC Control Enable.
#define DAC0_CLR_IN_CLR_OUT (1) // As per TRM DAC pin inout mode should be neither in nor out
#define DAC1_CLR_IN_CLR_OUT (2)
#define MAX_ANALOG_VAL (1.0f)
#define MIN_ANALOG_VAL (0.0f)
static const PinMap PinMap_DAC[] = {
{PT0, DAC_0, PIN_DATA(0, 1)},
{PT1, DAC_1, PIN_DATA(0, 1)},
{NC, NC, 0}
};
void analogout_init(dac_t *obj, PinName pin)
{
DACName dac_name = (DACName)pinmap_peripheral(pin, PinMap_DAC);
MBED_ASSERT(dac_name != (DACName)NC);
obj->dac = dac_name;
switch (dac_name) {
case DAC_0:
obj->DACx = TSB_DA0;
// Enable clock for DAC0 and Port T
TSB_CG_FSYSMENA_IPMENA04 = TXZ_ENABLE;
TSB_CG_FSYSMENB_IPMENB17 = TXZ_ENABLE;
break;
case DAC_1:
obj->DACx = TSB_DA1;
// Enable clock for DAC1 and Port T
TSB_CG_FSYSMENA_IPMENA05 = TXZ_ENABLE;
TSB_CG_FSYSMENB_IPMENB17 = TXZ_ENABLE;
break;
default:
break;
}
pinmap_pinout(pin, PinMap_DAC);
// DAC pins as neither input and nor output
if (dac_name == DAC_0) {
TSB_PT->CR &= ~(DAC0_CLR_IN_CLR_OUT);
TSB_PT->IE &= ~(DAC0_CLR_IN_CLR_OUT);
} else if (dac_name == DAC_1) {
TSB_PT->CR &= ~(DAC1_CLR_IN_CLR_OUT);
TSB_PT->IE &= ~(DAC1_CLR_IN_CLR_OUT);
} else {
return;
}
obj->DACx->CR = REG_DAC_DAxCR_REN_DISABLE;
}
void analogout_free(dac_t *obj)
{
obj->DACx->CR = REG_DAC_DAxCR_REN_DISABLE;
obj->dac = (DACName)NC;
}
void analogout_write(dac_t *obj, float value)
{
uint8_t outputcode = 0;
obj->DACx->CR = REG_DAC_DAxCR_REN_ENABLE;
if (value < 0.0f) {
value = 0.0f;
} else {
if (value >= 1.0f) {
value = 1.0f;
}
}
outputcode = (uint8_t)(value * 255.0f);
obj->DACx->REG = outputcode;
}
void analogout_write_u16(dac_t *obj, uint16_t value)
{
// Writing higher 8-bits to Data Register
obj->DACx->CR = REG_DAC_DAxCR_REN_ENABLE;
obj->DACx->REG = (uint8_t)(value & 0xFF);
}
float analogout_read(dac_t *obj)
{
float result = 0.0;
uint32_t value = 0;
value = ((obj->DACx->REG) & (0xFF));
result = ((float)value / 255.0f);
return result;
}
uint16_t analogout_read_u16(dac_t *obj)
{
uint16_t value = 0;
value = (uint16_t)((obj->DACx->REG) & (0xFF));
return value;
// Upper and lower byte stored with read value
}
const PinMap *analogout_pinmap()
{
return PinMap_DAC;
}

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define TRANSACTION_QUEUE_SIZE_SPI 4
#define DEVICE_ID_LENGTH 32
#include <stddef.h>
#include "objects.h"
#endif

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targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TMPM4NR.h Normal file
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targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TMPM4Nx.h Normal file
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/**
*******************************************************************************
* @file TMPM4Nx.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for the
* TOSHIBA 'TMPM4Nx' Group
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef __TMPM4Nx_H__
#define __TMPM4Nx_H__
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup TOSHIBA_TXZ_MICROCONTROLLER TOSHIBA TXZ MICROCONTROLLER
* @{
*/
/** @addtogroup TMPM4NR TMPM4NQ TMPM4NN
* @{
*/
#if !defined(TMPM4NR) && !defined(TMPM4NQ)&& !defined(TMPM4NN)
/**
* @brief Remove a comment of target device.
*/
#define TMPM4NR /*!< TMPM4NR device */
/*#define TMPM4NQ*/ /*!< TMPM4NQ device */
/*#define TMPM4NN*/ /*!< TMPM4NN device */
#endif
/** @defgroup Device_Included Device Included
* @{
*/
#if defined(TMPM4NR)
#include "TMPM4NR.h"
#elif defined(TMPM4NQ)
#include "TMPM4NQ.h"
#elif defined(TMPM4NN)
#include "TMPM4NN.h"
#else
#error "target device is non-select."
#endif
/**
* @}
*/ /* End of group Device_Included */
#ifdef __cplusplus
}
#endif
#endif /* __TMPM4Nx_H__ */
/**
* @}
*/ /* End of group TMPM4Nx */
/**
* @}
*/ /* End of group TOSHIBA_TXZ_MICROCONTROLLER */

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;/**
; *******************************************************************************
; * @file startup_TMPM4NR.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for the
; * TOSHIBA 'TMPM4NR' Device Series
; * @version V1.0.0
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
; *
; * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
; *******************************************************************************
; */
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD INT00_IRQHandler ; 0: Interrupt pin 00a/00b
DCD INT01_IRQHandler ; 1: Interrupt pin 01a/00b
DCD INT02_IRQHandler ; 2: Interrupt pin 02a/00b
DCD INT03_IRQHandler ; 3: Interrupt pin 03a/03b
DCD INT04_IRQHandler ; 4: Interrupt pin 04a/04b
DCD INT05_IRQHandler ; 5: Interrupt pin 05a/05b
DCD INT06_IRQHandler ; 6: Interrupt pin 06a/06b
DCD INT07_IRQHandler ; 7: Interrupt pin 07a/07b
DCD INT08_IRQHandler ; 8: Interrupt pin 08a/08b
DCD INT09_IRQHandler ; 9: Interrupt pin 09a/09b
DCD INT10_IRQHandler ; 10: Interrupt pin 10a/10b
DCD INT11_IRQHandler ; 11: Interrupt pin 11a/11b
DCD INT12_IRQHandler ; 12: Interrupt pin 12a/12b
DCD INT13_IRQHandler ; 13: Interrupt pin 13a/13b
DCD INT14_IRQHandler ; 14: Interrupt pin 14a/14b
DCD INT15_IRQHandler ; 15: Interrupt pin 15a/15b
DCD INTRTC_IRQHandler ; 16: Real time clock(XHz) interrupt
DCD INTCEC0RX_IRQHandler ; 17: CEC reception interrupt (channel 0)
DCD INTCEC0TX_IRQHandler ; 18: CEC transmission interrupt (channel 0)
DCD INTISDA_IRQHandler ; 19: Interval Sensing Detector interrupt (Unit A)
DCD INTISDB_IRQHandler ; 20: Interval Sensing Detector interrupt (Unit B)
DCD INTISDC_IRQHandler ; 21: Interval Sensing Detector interrupt (Unit C)
DCD INTRMC0_IRQHandler ; 22: Remote control reception interrupt 0
DCD INTRMC1_IRQHandler ; 23: Remote control reception interrupt 1
DCD INTLTTMR0_IRQHandler ; 24: Long Term Timer Interrupt(channel 0)
DCD INTHDMAATC_IRQHandler ; 25: HDMA complete of transfer(Unit A)
DCD INTHDMAAERR_IRQHandler ; 26: HDMA transfer error(Unit A)
DCD INTHDMABTC_IRQHandler ; 27: HDMA end of transfer(Unit B)
DCD INTHDMABERR_IRQHandler ; 28: HDMA transfer error(Unit B)
DCD INTMDMAATC_IRQHandler ; 29: MDMA complete of transfer(Unit A)
DCD INTT32A00_A_CT_IRQHandler ; 30: T32A00 TimerA all interrupt /TimerC match, overflow, and underflow
DCD INTT32A00_B_C01_CPC_IRQHandler; 31: T32A00 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
DCD INTT32A01_A_CT_IRQHandler ; 32: T32A01 TimerA all interrupt /TimerC match, overflow, and underflow
DCD INTT32A01_B_C01_CPC_IRQHandler; 33: T32A01 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
DCD INTT32A02_A_CT_IRQHandler ; 34: T32A02 TimerA all interrupt /TimerC match, overflow, and underflow
DCD INTT32A02_B_C01_CPC_IRQHandler; 35: T32A02 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
DCD INTT32A03_A_CT_IRQHandler ; 36: T32A03 TimerA all interrupt /TimerC match, overflow, and underflow
DCD INTT32A03_B_C01_CPC_IRQHandler; 37: T32A03 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
DCD INTT32A04_A_CT_IRQHandler ; 38: T32A04 TimerA all interrupt /TimerC match, overflow, and underflow
DCD INTT32A04_B_C01_CPC_IRQHandler; 39: T32A04 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
DCD INTT32A05_A_CT_IRQHandler ; 40: T32A05 TimerA all interrupt /TimerC match, overflow, and underflow
DCD INTT32A05_B_C01_CPC_IRQHandler; 41: T32A05 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
DCD INTT32A06_A_CT_IRQHandler ; 42: T32A06 TimerA all interrupt /TimerC match, overflow, and underflow
DCD INTT32A06_B_C01_CPC_IRQHandler; 43: T32A06 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
DCD INTT32A07_A_CT_IRQHandler ; 44: T32A07 TimerA all interrupt /TimerC match, overflow, and underflow
DCD INTT32A07_B_C01_CPC_IRQHandler; 45: T32A07 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
DCD INTT32A08_A_CT_IRQHandler ; 46: T32A08 TimerA all interrupt /TimerC match, overflow, and underflow
DCD INTT32A08_B_C01_CPC_IRQHandler; 47: T32A08 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
DCD INTT32A09_A_CT_IRQHandler ; 48: T32A09 TimerA all interrupt /TimerC match, overflow, and underflow
DCD INTT32A09_B_C01_CPC_IRQHandler; 49: T32A09 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
DCD INTT32A10_A_CT_IRQHandler ; 50: T32A10 TimerA all interrupt /TimerC match, overflow, and underflow
DCD INTT32A10_B_C01_CPC_IRQHandler; 51: T32A10 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
DCD INTT32A11_A_CT_IRQHandler ; 52: T32A11 TimerA all interrupt /TimerC match, overflow, and underflow
DCD INTT32A11_B_C01_CPC_IRQHandler; 53: T32A11 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
DCD INTT32A12_A_CT_IRQHandler ; 54: T32A12 TimerA all interrupt /TimerC match, overflow, and underflow
DCD INTT32A12_B_C01_CPC_IRQHandler; 55: T32A12 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
DCD INTT32A13_A_CT_IRQHandler ; 56: T32A13 TimerA all interrupt /TimerC match, overflow, and underflow
DCD INTT32A13_B_C01_CPC_IRQHandler; 57: T32A13 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
DCD INTEMG0_IRQHandler ; 58: PMD0 EMG interrupt
DCD INTOVV0_IRQHandler ; 59: PMD0 OVV interrupt
DCD INTPWM0_IRQHandler ; 60: PMD0 interrupt
DCD INTT0RX_IRQHandler ; 61: TSPI/SIO reception (channel 0) interrupt
DCD INTT0TX_IRQHandler ; 62: TSPI/SIO transmit (channel 0) interrupt
DCD INTT0ERR_IRQHandler ; 63: TSPI/SIO error (channel 0) interrupt
DCD INTT1RX_IRQHandler ; 64: TSPI/SIO reception (channel 1) interrupt
DCD INTT1TX_IRQHandler ; 65: TSPI/SIO transmit (channel 1) interrupt
DCD INTT1ERR_IRQHandler ; 66: TSPI/SIO error (channel 1) interrupt
DCD INTT2RX_IRQHandler ; 67: TSPI/SIO reception (channel 2) interrupt
DCD INTT2TX_IRQHandler ; 68: TSPI/SIO transmit (channel 2) interrupt
DCD INTT2ERR_IRQHandler ; 69: TSPI/SIO error (channel 2) interrupt
DCD INTT3RX_IRQHandler ; 70: TSPI/SIO reception (channel 3) interrupt
DCD INTT3TX_IRQHandler ; 71: TSPI/SIO transmit (channel 3) interrupt
DCD INTT3ERR_IRQHandler ; 72: TSPI/SIO error (channel 3) interrupt
DCD INTT4RX_IRQHandler ; 73: TSPI/SIO reception (channel 4) interrupt
DCD INTT4TX_IRQHandler ; 74: TSPI/SIO transmit (channel 4) interrupt
DCD INTT4ERR_IRQHandler ; 75: TSPI/SIO error (channel 4) interrupt
DCD INTT5RX_IRQHandler ; 76: TSPI/SIO reception (channel 5) interrupt
DCD INTT5TX_IRQHandler ; 77: TSPI/SIO transmit (channel 5) interrupt
DCD INTT5ERR_IRQHandler ; 78: TSPI/SIO error (channel 5) interrupt
DCD INTT6RX_IRQHandler ; 79: TSPI/SIO reception (channel 6) interrupt
DCD INTT6TX_IRQHandler ; 80: TSPI/SIO transmit (channel 6) interrupt
DCD INTT6ERR_IRQHandler ; 81: TSPI/SIO error (channel 6) interrupt
DCD INTT7RX_IRQHandler ; 82: TSPI/SIO reception (channel 7) interrupt
DCD INTT7TX_IRQHandler ; 83: TSPI/SIO transmit (channel 7) interrupt
DCD INTT7ERR_IRQHandler ; 84: TSPI/SIO error (channel 7) interrupt
DCD INTT8RX_IRQHandler ; 85: TSPI/SIO reception (channel 8) interrupt
DCD INTT8TX_IRQHandler ; 86: TSPI/SIO transmit (channel 8) interrupt
DCD INTT8ERR_IRQHandler ; 87: TSPI/SIO error (channel 8) interrupt
DCD INTSMI0_IRQHandler ; 88: Serial Memory Interface interrupt
DCD INTUART0RX_IRQHandler ; 89: UART reception (channel 0) interrupt
DCD INTUART0TX_IRQHandler ; 90: UART transmit (channel 0) interrupt
DCD INTUART0ERR_IRQHandler ; 91: UART error (channel 0) interrupt
DCD INTUART1RX_IRQHandler ; 92: UART reception (channel 1) interrupt
DCD INTUART1TX_IRQHandler ; 93: UART transmit (channel 1) interrupt
DCD INTUART1ERR_IRQHandler ; 94: UART error (channel 1) interrupt
DCD INTUART2RX_IRQHandler ; 95: UART reception (channel 2) interrupt
DCD INTUART2TX_IRQHandler ; 96: UART transmit (channel 2) interrupt
DCD INTUART2ERR_IRQHandler ; 97: UART error (channel 2) interrupt
DCD INTUART3RX_IRQHandler ; 98: UART reception (channel 3) interrupt
DCD INTUART3TX_IRQHandler ; 99: UART transmit (channel 3) interrupt
DCD INTUART3ERR_IRQHandler ; 100: UART error (channel 3) interrupt
DCD INTUART4RX_IRQHandler ; 101: UART reception (channel 4) interrupt
DCD INTUART4TX_IRQHandler ; 102: UART transmit (channel 4) interrupt
DCD INTUART4ERR_IRQHandler ; 103: UART error (channel 4) interrupt
DCD INTUART5RX_IRQHandler ; 104: UART reception (channel 5) interrupt
DCD INTUART5TX_IRQHandler ; 105: UART transmit (channel 5) interrupt
DCD INTUART5ERR_IRQHandler ; 106: UART error (channel 5) interrupt
DCD INTFUART0_IRQHandler ; 107: FUART interrupt(channel 0)
DCD INTFUART1_IRQHandler ; 108: FUART interrupt(channel 1)
DCD INTI2C0NST_IRQHandler ; 109: I2C0 interrupt / EI2C0 status interrupt
DCD INTI2C0ATX_IRQHandler ; 110: I2C0 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt
DCD INTI2C0BRX_IRQHandler ; 111: I2C0 bus free detection interrupt / EI2C0receive buffer empty interrupt
DCD INTI2C0NA_IRQHandler ; 112: I2C0 NACK detection interrupt
DCD INTI2C1NST_IRQHandler ; 113: I2C1 interrupt / EI2C0 status interrupt
DCD INTI2C1ATX_IRQHandler ; 114: I2C1 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt
DCD INTI2C1BRX_IRQHandler ; 115: I2C1 bus free detection interrupt / EI2C0receive buffer empty interrupt
DCD INTI2C1NA_IRQHandler ; 116: I2C1 NACK detection interrupt
DCD INTI2C2NST_IRQHandler ; 117: I2C2 interrupt / EI2C0 status interrupt
DCD INTI2C2ATX_IRQHandler ; 118: I2C2 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt
DCD INTI2C2BRX_IRQHandler ; 119: I2C2 bus free detection interrupt / EI2C0receive buffer empty interrupt
DCD INTI2C2NA_IRQHandler ; 120: I2C2 NACK detection interrupt
DCD INTI2C3NST_IRQHandler ; 121: I2C3 interrupt / EI2C0 status interrupt
DCD INTI2C3ATX_IRQHandler ; 122: I2C3 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt
DCD INTI2C3BRX_IRQHandler ; 123: I2C3 bus free detection interrupt / EI2C0receive buffer empty interrupt
DCD INTI2C3NA_IRQHandler ; 124: I2C3 NACK detection interrupt
DCD INTI2C4NST_IRQHandler ; 125: I2C4 interrupt / EI2C0 status interrupt
DCD INTI2C4ATX_IRQHandler ; 126: I2C4 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt
DCD INTI2C4BRX_IRQHandler ; 127: I2C4 bus free detection interrupt / EI2C0receive buffer empty interrupt
DCD INTI2C4NA_IRQHandler ; 128: I2C4 NACK detection interrupt
DCD INTADACP0_IRQHandler ; 129: ADC conversion monitoring function interrupt 0
DCD INTADACP1_IRQHandler ; 130: ADC conversion monitoring function interrupt 1
DCD INTADATRG_IRQHandler ; 131: ADC conversion triggered by General purpose is finished
DCD INTADASGL_IRQHandler ; 132: ADC conversion triggered by Single program is finished
DCD INTADACNT_IRQHandler ; 133: ADC conversion triggered by Continuity program is finished
DCD INTADAHP_IRQHandler ; 134: ADC high priority AD conversion interrupt
DCD INTFLDRDY_IRQHandler ; 135: Data FLASH Ready interrupt
DCD INTFLCRDY_IRQHandler ; 136: Code FLASH Area0/1 Ready interrupt
DCD 0 ; 137: Reserved
DCD 0 ; 138: Reserved
DCD INTMDMAABERR_IRQHandler ; 139: MDMA bus error(Unit A) interrupt
DCD INTMDMAADERR_IRQHandler ; 140: MDMA descriptor error(Unit A) interrupt
DCD INTI2S0SI_IRQHandler ; 141: I2S ch0 SI transfer end interrupt
DCD INTI2S0SIERR_IRQHandler ; 142: I2S ch0 SI error interrupt
DCD INTI2S0SO_IRQHandler ; 143: I2S ch0 SO transfer end interrupt
DCD INTI2S0SOERR_IRQHandler ; 144: I2S ch0 SO error interrupt
DCD INTI2S1SI_IRQHandler ; 145: I2S ch1 SI transfer end interrupt
DCD INTI2S1SIERR_IRQHandler ; 146: I2S ch1 SI error interrupt
DCD INTI2S1SO_IRQHandler ; 147: I2S ch1 SO transfer end interrupt
DCD INTI2S1SOERR_IRQHandler ; 148: I2S ch1 SO error interrupt
DCD INTFIR0_IRQHandler ; 149: FIR ch0 interrupt
DCD INTTSSI0RX_IRQHandler ; 150: TSSI ch0 RX interrupt
DCD INTTSSI0TX_IRQHandler ; 151: TSSI ch0 TX interrupt
DCD INTTSSI0ERR_IRQHandler ; 152: TSSI ch0 error interrupt
DCD INTTSSI1RX_IRQHandler ; 153: TSSI ch1 RX interrupt
DCD INTTSSI1TX_IRQHandler ; 154: TSSI ch1 TX interrupt
DCD INTTSSI1ERR_IRQHandler ; 155: TSSI ch1 error interrupt
DCD INTEMA_IRQHandler ; 156: Ether MAC interrupt
DCD INTEMAMP_IRQHandler ; 157: Ether MAC magic packet detection interrupt
DCD INTCAN0RX_IRQHandler ; 158: CAN ch0 receive interrupt
DCD INTCAN0TX_IRQHandler ; 159: CAN ch0 transmission interrupt
DCD INTCAN0GLB_IRQHandler ; 160: CAN ch0 Global interrupt
DCD INTCAN1RX_IRQHandler ; 161: CAN ch1 receive interrupt
DCD INTCAN1TX_IRQHandler ; 162: CAN ch1 transmission interrupt
DCD INTCAN1GLB_IRQHandler ; 163: CAN ch1 Global interrupt
DCD INTUSBOTGA_IRQHandler ; 164: USB OTG unit A interrupt
DCD INTUSBOTGAWK_IRQHandler ; 165: USB OTG unit A Wakeup interrupt
DCD INTUSBOTGB_IRQHandler ; 166: USB OTG unit B interrupt
DCD INTUSBOTGBWK_IRQHandler ; 167: USB OTG unit B Wakeup interrupt
DCD INTT32A14_A_IRQHandler ; 168: T32A14 TimerA all interrupt
DCD INTT32A14_B_IRQHandler ; 169: T32A14 TimerB all interrupt
DCD INTT32A14_CT_IRQHandler ; 170: T32A14 TimerC match, overflow, and underflow Interrupt
DCD INTT32A15_A_IRQHandler ; 171: T32A15 TimerA all interrupt
DCD INTT32A15_B_IRQHandler ; 172: T32A15 TimerB all interrupt
DCD INTT32A15_C_IRQHandler ; 173: T32A15 TimerC all interrupt
DCD INTMDMAADISR_IRQHandler ; 174: MDMAC unit A Descriptor interrupt
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT INT00_IRQHandler [WEAK]
EXPORT INT01_IRQHandler [WEAK]
EXPORT INT02_IRQHandler [WEAK]
EXPORT INT03_IRQHandler [WEAK]
EXPORT INT04_IRQHandler [WEAK]
EXPORT INT05_IRQHandler [WEAK]
EXPORT INT06_IRQHandler [WEAK]
EXPORT INT07_IRQHandler [WEAK]
EXPORT INT08_IRQHandler [WEAK]
EXPORT INT09_IRQHandler [WEAK]
EXPORT INT10_IRQHandler [WEAK]
EXPORT INT11_IRQHandler [WEAK]
EXPORT INT12_IRQHandler [WEAK]
EXPORT INT13_IRQHandler [WEAK]
EXPORT INT14_IRQHandler [WEAK]
EXPORT INT15_IRQHandler [WEAK]
EXPORT INTRTC_IRQHandler [WEAK]
EXPORT INTCEC0RX_IRQHandler [WEAK]
EXPORT INTCEC0TX_IRQHandler [WEAK]
EXPORT INTISDA_IRQHandler [WEAK]
EXPORT INTISDB_IRQHandler [WEAK]
EXPORT INTISDC_IRQHandler [WEAK]
EXPORT INTRMC0_IRQHandler [WEAK]
EXPORT INTRMC1_IRQHandler [WEAK]
EXPORT INTLTTMR0_IRQHandler [WEAK]
EXPORT INTHDMAATC_IRQHandler [WEAK]
EXPORT INTHDMAAERR_IRQHandler [WEAK]
EXPORT INTHDMABTC_IRQHandler [WEAK]
EXPORT INTHDMABERR_IRQHandler [WEAK]
EXPORT INTMDMAATC_IRQHandler [WEAK]
EXPORT INTT32A00_A_CT_IRQHandler [WEAK]
EXPORT INTT32A00_B_C01_CPC_IRQHandler[WEAK]
EXPORT INTT32A01_A_CT_IRQHandler [WEAK]
EXPORT INTT32A01_B_C01_CPC_IRQHandler[WEAK]
EXPORT INTT32A02_A_CT_IRQHandler [WEAK]
EXPORT INTT32A02_B_C01_CPC_IRQHandler[WEAK]
EXPORT INTT32A03_A_CT_IRQHandler [WEAK]
EXPORT INTT32A03_B_C01_CPC_IRQHandler[WEAK]
EXPORT INTT32A04_A_CT_IRQHandler [WEAK]
EXPORT INTT32A04_B_C01_CPC_IRQHandler[WEAK]
EXPORT INTT32A05_A_CT_IRQHandler [WEAK]
EXPORT INTT32A05_B_C01_CPC_IRQHandler[WEAK]
EXPORT INTT32A06_A_CT_IRQHandler [WEAK]
EXPORT INTT32A06_B_C01_CPC_IRQHandler[WEAK]
EXPORT INTT32A07_A_CT_IRQHandler [WEAK]
EXPORT INTT32A07_B_C01_CPC_IRQHandler[WEAK]
EXPORT INTT32A08_A_CT_IRQHandler [WEAK]
EXPORT INTT32A08_B_C01_CPC_IRQHandler[WEAK]
EXPORT INTT32A09_A_CT_IRQHandler [WEAK]
EXPORT INTT32A09_B_C01_CPC_IRQHandler[WEAK]
EXPORT INTT32A10_A_CT_IRQHandler [WEAK]
EXPORT INTT32A10_B_C01_CPC_IRQHandler[WEAK]
EXPORT INTT32A11_A_CT_IRQHandler [WEAK]
EXPORT INTT32A11_B_C01_CPC_IRQHandler[WEAK]
EXPORT INTT32A12_A_CT_IRQHandler [WEAK]
EXPORT INTT32A12_B_C01_CPC_IRQHandler[WEAK]
EXPORT INTT32A13_A_CT_IRQHandler [WEAK]
EXPORT INTT32A13_B_C01_CPC_IRQHandler[WEAK]
EXPORT INTEMG0_IRQHandler [WEAK]
EXPORT INTOVV0_IRQHandler [WEAK]
EXPORT INTPWM0_IRQHandler [WEAK]
EXPORT INTT0RX_IRQHandler [WEAK]
EXPORT INTT0TX_IRQHandler [WEAK]
EXPORT INTT0ERR_IRQHandler [WEAK]
EXPORT INTT1RX_IRQHandler [WEAK]
EXPORT INTT1TX_IRQHandler [WEAK]
EXPORT INTT1ERR_IRQHandler [WEAK]
EXPORT INTT2RX_IRQHandler [WEAK]
EXPORT INTT2TX_IRQHandler [WEAK]
EXPORT INTT2ERR_IRQHandler [WEAK]
EXPORT INTT3RX_IRQHandler [WEAK]
EXPORT INTT3TX_IRQHandler [WEAK]
EXPORT INTT3ERR_IRQHandler [WEAK]
EXPORT INTT4RX_IRQHandler [WEAK]
EXPORT INTT4TX_IRQHandler [WEAK]
EXPORT INTT4ERR_IRQHandler [WEAK]
EXPORT INTT5RX_IRQHandler [WEAK]
EXPORT INTT5TX_IRQHandler [WEAK]
EXPORT INTT5ERR_IRQHandler [WEAK]
EXPORT INTT6RX_IRQHandler [WEAK]
EXPORT INTT6TX_IRQHandler [WEAK]
EXPORT INTT6ERR_IRQHandler [WEAK]
EXPORT INTT7RX_IRQHandler [WEAK]
EXPORT INTT7TX_IRQHandler [WEAK]
EXPORT INTT7ERR_IRQHandler [WEAK]
EXPORT INTT8RX_IRQHandler [WEAK]
EXPORT INTT8TX_IRQHandler [WEAK]
EXPORT INTT8ERR_IRQHandler [WEAK]
EXPORT INTSMI0_IRQHandler [WEAK]
EXPORT INTUART0RX_IRQHandler [WEAK]
EXPORT INTUART0TX_IRQHandler [WEAK]
EXPORT INTUART0ERR_IRQHandler [WEAK]
EXPORT INTUART1RX_IRQHandler [WEAK]
EXPORT INTUART1TX_IRQHandler [WEAK]
EXPORT INTUART1ERR_IRQHandler [WEAK]
EXPORT INTUART2RX_IRQHandler [WEAK]
EXPORT INTUART2TX_IRQHandler [WEAK]
EXPORT INTUART2ERR_IRQHandler [WEAK]
EXPORT INTUART3RX_IRQHandler [WEAK]
EXPORT INTUART3TX_IRQHandler [WEAK]
EXPORT INTUART3ERR_IRQHandler [WEAK]
EXPORT INTUART4RX_IRQHandler [WEAK]
EXPORT INTUART4TX_IRQHandler [WEAK]
EXPORT INTUART4ERR_IRQHandler [WEAK]
EXPORT INTUART5RX_IRQHandler [WEAK]
EXPORT INTUART5TX_IRQHandler [WEAK]
EXPORT INTUART5ERR_IRQHandler [WEAK]
EXPORT INTFUART0_IRQHandler [WEAK]
EXPORT INTFUART1_IRQHandler [WEAK]
EXPORT INTI2C0NST_IRQHandler [WEAK]
EXPORT INTI2C0ATX_IRQHandler [WEAK]
EXPORT INTI2C0BRX_IRQHandler [WEAK]
EXPORT INTI2C0NA_IRQHandler [WEAK]
EXPORT INTI2C1NST_IRQHandler [WEAK]
EXPORT INTI2C1ATX_IRQHandler [WEAK]
EXPORT INTI2C1BRX_IRQHandler [WEAK]
EXPORT INTI2C1NA_IRQHandler [WEAK]
EXPORT INTI2C2NST_IRQHandler [WEAK]
EXPORT INTI2C2ATX_IRQHandler [WEAK]
EXPORT INTI2C2BRX_IRQHandler [WEAK]
EXPORT INTI2C2NA_IRQHandler [WEAK]
EXPORT INTI2C3NST_IRQHandler [WEAK]
EXPORT INTI2C3ATX_IRQHandler [WEAK]
EXPORT INTI2C3BRX_IRQHandler [WEAK]
EXPORT INTI2C3NA_IRQHandler [WEAK]
EXPORT INTI2C4NST_IRQHandler [WEAK]
EXPORT INTI2C4ATX_IRQHandler [WEAK]
EXPORT INTI2C4BRX_IRQHandler [WEAK]
EXPORT INTI2C4NA_IRQHandler [WEAK]
EXPORT INTADACP0_IRQHandler [WEAK]
EXPORT INTADACP1_IRQHandler [WEAK]
EXPORT INTADATRG_IRQHandler [WEAK]
EXPORT INTADASGL_IRQHandler [WEAK]
EXPORT INTADACNT_IRQHandler [WEAK]
EXPORT INTADAHP_IRQHandler [WEAK]
EXPORT INTFLDRDY_IRQHandler [WEAK]
EXPORT INTFLCRDY_IRQHandler [WEAK]
EXPORT INTMDMAABERR_IRQHandler [WEAK]
EXPORT INTMDMAADERR_IRQHandler [WEAK]
EXPORT INTI2S0SI_IRQHandler [WEAK]
EXPORT INTI2S0SIERR_IRQHandler [WEAK]
EXPORT INTI2S0SO_IRQHandler [WEAK]
EXPORT INTI2S0SOERR_IRQHandler [WEAK]
EXPORT INTI2S1SI_IRQHandler [WEAK]
EXPORT INTI2S1SIERR_IRQHandler [WEAK]
EXPORT INTI2S1SO_IRQHandler [WEAK]
EXPORT INTI2S1SOERR_IRQHandler [WEAK]
EXPORT INTFIR0_IRQHandler [WEAK]
EXPORT INTTSSI0RX_IRQHandler [WEAK]
EXPORT INTTSSI0TX_IRQHandler [WEAK]
EXPORT INTTSSI0ERR_IRQHandler [WEAK]
EXPORT INTTSSI1RX_IRQHandler [WEAK]
EXPORT INTTSSI1TX_IRQHandler [WEAK]
EXPORT INTTSSI1ERR_IRQHandler [WEAK]
EXPORT INTEMA_IRQHandler [WEAK]
EXPORT INTEMAMP_IRQHandler [WEAK]
EXPORT INTCAN0RX_IRQHandler [WEAK]
EXPORT INTCAN0TX_IRQHandler [WEAK]
EXPORT INTCAN0GLB_IRQHandler [WEAK]
EXPORT INTCAN1RX_IRQHandler [WEAK]
EXPORT INTCAN1TX_IRQHandler [WEAK]
EXPORT INTCAN1GLB_IRQHandler [WEAK]
EXPORT INTUSBOTGA_IRQHandler [WEAK]
EXPORT INTUSBOTGAWK_IRQHandler [WEAK]
EXPORT INTUSBOTGB_IRQHandler [WEAK]
EXPORT INTUSBOTGBWK_IRQHandler [WEAK]
EXPORT INTT32A14_A_IRQHandler [WEAK]
EXPORT INTT32A14_B_IRQHandler [WEAK]
EXPORT INTT32A14_CT_IRQHandler [WEAK]
EXPORT INTT32A15_A_IRQHandler [WEAK]
EXPORT INTT32A15_B_IRQHandler [WEAK]
EXPORT INTT32A15_C_IRQHandler [WEAK]
EXPORT INTMDMAADISR_IRQHandler [WEAK]
INT00_IRQHandler
INT01_IRQHandler
INT02_IRQHandler
INT03_IRQHandler
INT04_IRQHandler
INT05_IRQHandler
INT06_IRQHandler
INT07_IRQHandler
INT08_IRQHandler
INT09_IRQHandler
INT10_IRQHandler
INT11_IRQHandler
INT12_IRQHandler
INT13_IRQHandler
INT14_IRQHandler
INT15_IRQHandler
INTRTC_IRQHandler
INTCEC0RX_IRQHandler
INTCEC0TX_IRQHandler
INTISDA_IRQHandler
INTISDB_IRQHandler
INTISDC_IRQHandler
INTRMC0_IRQHandler
INTRMC1_IRQHandler
INTLTTMR0_IRQHandler
INTHDMAATC_IRQHandler
INTHDMAAERR_IRQHandler
INTHDMABTC_IRQHandler
INTHDMABERR_IRQHandler
INTMDMAATC_IRQHandler
INTT32A00_A_CT_IRQHandler
INTT32A00_B_C01_CPC_IRQHandler
INTT32A01_A_CT_IRQHandler
INTT32A01_B_C01_CPC_IRQHandler
INTT32A02_A_CT_IRQHandler
INTT32A02_B_C01_CPC_IRQHandler
INTT32A03_A_CT_IRQHandler
INTT32A03_B_C01_CPC_IRQHandler
INTT32A04_A_CT_IRQHandler
INTT32A04_B_C01_CPC_IRQHandler
INTT32A05_A_CT_IRQHandler
INTT32A05_B_C01_CPC_IRQHandler
INTT32A06_A_CT_IRQHandler
INTT32A06_B_C01_CPC_IRQHandler
INTT32A07_A_CT_IRQHandler
INTT32A07_B_C01_CPC_IRQHandler
INTT32A08_A_CT_IRQHandler
INTT32A08_B_C01_CPC_IRQHandler
INTT32A09_A_CT_IRQHandler
INTT32A09_B_C01_CPC_IRQHandler
INTT32A10_A_CT_IRQHandler
INTT32A10_B_C01_CPC_IRQHandler
INTT32A11_A_CT_IRQHandler
INTT32A11_B_C01_CPC_IRQHandler
INTT32A12_A_CT_IRQHandler
INTT32A12_B_C01_CPC_IRQHandler
INTT32A13_A_CT_IRQHandler
INTT32A13_B_C01_CPC_IRQHandler
INTEMG0_IRQHandler
INTOVV0_IRQHandler
INTPWM0_IRQHandler
INTT0RX_IRQHandler
INTT0TX_IRQHandler
INTT0ERR_IRQHandler
INTT1RX_IRQHandler
INTT1TX_IRQHandler
INTT1ERR_IRQHandler
INTT2RX_IRQHandler
INTT2TX_IRQHandler
INTT2ERR_IRQHandler
INTT3RX_IRQHandler
INTT3TX_IRQHandler
INTT3ERR_IRQHandler
INTT4RX_IRQHandler
INTT4TX_IRQHandler
INTT4ERR_IRQHandler
INTT5RX_IRQHandler
INTT5TX_IRQHandler
INTT5ERR_IRQHandler
INTT6RX_IRQHandler
INTT6TX_IRQHandler
INTT6ERR_IRQHandler
INTT7RX_IRQHandler
INTT7TX_IRQHandler
INTT7ERR_IRQHandler
INTT8RX_IRQHandler
INTT8TX_IRQHandler
INTT8ERR_IRQHandler
INTSMI0_IRQHandler
INTUART0RX_IRQHandler
INTUART0TX_IRQHandler
INTUART0ERR_IRQHandler
INTUART1RX_IRQHandler
INTUART1TX_IRQHandler
INTUART1ERR_IRQHandler
INTUART2RX_IRQHandler
INTUART2TX_IRQHandler
INTUART2ERR_IRQHandler
INTUART3RX_IRQHandler
INTUART3TX_IRQHandler
INTUART3ERR_IRQHandler
INTUART4RX_IRQHandler
INTUART4TX_IRQHandler
INTUART4ERR_IRQHandler
INTUART5RX_IRQHandler
INTUART5TX_IRQHandler
INTUART5ERR_IRQHandler
INTFUART0_IRQHandler
INTFUART1_IRQHandler
INTI2C0NST_IRQHandler
INTI2C0ATX_IRQHandler
INTI2C0BRX_IRQHandler
INTI2C0NA_IRQHandler
INTI2C1NST_IRQHandler
INTI2C1ATX_IRQHandler
INTI2C1BRX_IRQHandler
INTI2C1NA_IRQHandler
INTI2C2NST_IRQHandler
INTI2C2ATX_IRQHandler
INTI2C2BRX_IRQHandler
INTI2C2NA_IRQHandler
INTI2C3NST_IRQHandler
INTI2C3ATX_IRQHandler
INTI2C3BRX_IRQHandler
INTI2C3NA_IRQHandler
INTI2C4NST_IRQHandler
INTI2C4ATX_IRQHandler
INTI2C4BRX_IRQHandler
INTI2C4NA_IRQHandler
INTADACP0_IRQHandler
INTADACP1_IRQHandler
INTADATRG_IRQHandler
INTADASGL_IRQHandler
INTADACNT_IRQHandler
INTADAHP_IRQHandler
INTFLDRDY_IRQHandler
INTFLCRDY_IRQHandler
INTMDMAABERR_IRQHandler
INTMDMAADERR_IRQHandler
INTI2S0SI_IRQHandler
INTI2S0SIERR_IRQHandler
INTI2S0SO_IRQHandler
INTI2S0SOERR_IRQHandler
INTI2S1SI_IRQHandler
INTI2S1SIERR_IRQHandler
INTI2S1SO_IRQHandler
INTI2S1SOERR_IRQHandler
INTFIR0_IRQHandler
INTTSSI0RX_IRQHandler
INTTSSI0TX_IRQHandler
INTTSSI0ERR_IRQHandler
INTTSSI1RX_IRQHandler
INTTSSI1TX_IRQHandler
INTTSSI1ERR_IRQHandler
INTEMA_IRQHandler
INTEMAMP_IRQHandler
INTCAN0RX_IRQHandler
INTCAN0TX_IRQHandler
INTCAN0GLB_IRQHandler
INTCAN1RX_IRQHandler
INTCAN1TX_IRQHandler
INTCAN1GLB_IRQHandler
INTUSBOTGA_IRQHandler
INTUSBOTGAWK_IRQHandler
INTUSBOTGB_IRQHandler
INTUSBOTGBWK_IRQHandler
INTT32A14_A_IRQHandler
INTT32A14_B_IRQHandler
INTT32A14_CT_IRQHandler
INTT32A15_A_IRQHandler
INTT32A15_B_IRQHandler
INTT32A15_C_IRQHandler
INTMDMAADISR_IRQHandler
B .
ENDP
ALIGN
END

84
targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TOOLCHAIN_ARM_STD/tmpm4nrf20fg.sct Normal file
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@ -0,0 +1,84 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
/*
* Copyright(C) 2021, Toshiba Electronic Device Solutions Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
;; TMPM4NRF20FG scatter file
;; Vector table starts at 0
;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model)
;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model)
;; Initial PC == &__main (with LSB set to indicate Thumb)
;; These two values are provided by the library
;; Other vectors must be provided by the user
;; Code starts after the last possible vector
;; Data starts at 0x20000000
;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries)
;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above)
;; Compatible with ISSM model
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x000200000
#endif
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
# else
# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
# endif
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x40000
#endif
#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE
#define VECTOR_SIZE 0x300
; TMPM4NR: 2048 KB FLASH (0x200000) + 256 KB SRAM (0x40000)
LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region
{
ER_IROM1 MBED_APP_START MBED_APP_SIZE
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 MBED_RAM_START + VECTOR_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - Stack_Size)
{
txz_fc.o (+RO)
.ANY (+RW, +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
}
ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -Stack_Size { ; stack
}
}

599
targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TOOLCHAIN_GCC_ARM/startup_TMPM4NR.S Normal file
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@ -0,0 +1,599 @@
;/**
; *******************************************************************************
; * @file startup_TMPM4NR.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for the
; * TOSHIBA 'TMPM4NR' Device Series
; * @version V1.0.0
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
; *
; * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
; *******************************************************************************
; */
.syntax unified
.arch armv7-m
.section .stack
.align 3
/*
// <h> Stack Configuration
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
/*
// <h> Heap Configuration
// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long INT00_IRQHandler // 0: Interrupt pin 00a/00b
.long INT01_IRQHandler // 1: Interrupt pin 01a/00b
.long INT02_IRQHandler // 2: Interrupt pin 02a/00b
.long INT03_IRQHandler // 3: Interrupt pin 03a/03b
.long INT04_IRQHandler // 4: Interrupt pin 04a/04b
.long INT05_IRQHandler // 5: Interrupt pin 05a/05b
.long INT06_IRQHandler // 6: Interrupt pin 06a/06b
.long INT07_IRQHandler // 7: Interrupt pin 07a/07b
.long INT08_IRQHandler // 8: Interrupt pin 08a/08b
.long INT09_IRQHandler // 9: Interrupt pin 09a/09b
.long INT10_IRQHandler // 10: Interrupt pin 10a/10b
.long INT11_IRQHandler // 11: Interrupt pin 11a/11b
.long INT12_IRQHandler // 12: Interrupt pin 12a/12b
.long INT13_IRQHandler // 13: Interrupt pin 13a/13b
.long INT14_IRQHandler // 14: Interrupt pin 14a/14b
.long INT15_IRQHandler // 15: Interrupt pin 15a/15b
.long INTRTC_IRQHandler // 16: Real time clock(XHz) interrupt
.long INTCEC0RX_IRQHandler // 17: CEC reception interrupt (channel 0)
.long INTCEC0TX_IRQHandler // 18: CEC transmission interrupt (channel 0)
.long INTISDA_IRQHandler // 19: Interval Sensing Detector interrupt (Unit A)
.long INTISDB_IRQHandler // 20: Interval Sensing Detector interrupt (Unit B)
.long INTISDC_IRQHandler // 21: Interval Sensing Detector interrupt (Unit C)
.long INTRMC0_IRQHandler // 22: Remote control reception interrupt 0
.long INTRMC1_IRQHandler // 23: Remote control reception interrupt 1
.long INTLTTMR0_IRQHandler // 24: Long Term Timer Interrupt(channel 0)
.long INTHDMAATC_IRQHandler // 25: HDMA complete of transfer(Unit A)
.long INTHDMAAERR_IRQHandler // 26: HDMA transfer error(Unit A)
.long INTHDMABTC_IRQHandler // 27: HDMA end of transfer(Unit B)
.long INTHDMABERR_IRQHandler // 28: HDMA transfer error(Unit B)
.long INTMDMAATC_IRQHandler // 29: MDMA complete of transfer(Unit A)
.long INTT32A00_A_CT_IRQHandler // 30: T32A00 TimerA all interrupt /TimerC match, overflow, and underflow
.long INTT32A00_B_C01_CPC_IRQHandler// 31: T32A00 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
.long INTT32A01_A_CT_IRQHandler // 32: T32A01 TimerA all interrupt /TimerC match, overflow, and underflow
.long INTT32A01_B_C01_CPC_IRQHandler// 33: T32A01 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
.long INTT32A02_A_CT_IRQHandler // 34: T32A02 TimerA all interrupt /TimerC match, overflow, and underflow
.long INTT32A02_B_C01_CPC_IRQHandler// 35: T32A02 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
.long INTT32A03_A_CT_IRQHandler // 36: T32A03 TimerA all interrupt /TimerC match, overflow, and underflow
.long INTT32A03_B_C01_CPC_IRQHandler// 37: T32A03 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
.long INTT32A04_A_CT_IRQHandler // 38: T32A04 TimerA all interrupt /TimerC match, overflow, and underflow
.long INTT32A04_B_C01_CPC_IRQHandler// 39: T32A04 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
.long INTT32A05_A_CT_IRQHandler // 40: T32A05 TimerA all interrupt /TimerC match, overflow, and underflow
.long INTT32A05_B_C01_CPC_IRQHandler// 41: T32A05 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
.long INTT32A06_A_CT_IRQHandler // 42: T32A06 TimerA all interrupt /TimerC match, overflow, and underflow
.long INTT32A06_B_C01_CPC_IRQHandler// 43: T32A06 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
.long INTT32A07_A_CT_IRQHandler // 44: T32A07 TimerA all interrupt /TimerC match, overflow, and underflow
.long INTT32A07_B_C01_CPC_IRQHandler// 45: T32A07 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
.long INTT32A08_A_CT_IRQHandler // 46: T32A08 TimerA all interrupt /TimerC match, overflow, and underflow
.long INTT32A08_B_C01_CPC_IRQHandler// 47: T32A08 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
.long INTT32A09_A_CT_IRQHandler // 48: T32A09 TimerA all interrupt /TimerC match, overflow, and underflow
.long INTT32A09_B_C01_CPC_IRQHandler// 49: T32A09 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
.long INTT32A10_A_CT_IRQHandler // 50: T32A10 TimerA all interrupt /TimerC match, overflow, and underflow
.long INTT32A10_B_C01_CPC_IRQHandler// 51: T32A10 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
.long INTT32A11_A_CT_IRQHandler // 52: T32A11 TimerA all interrupt /TimerC match, overflow, and underflow
.long INTT32A11_B_C01_CPC_IRQHandler// 53: T32A11 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
.long INTT32A12_A_CT_IRQHandler // 54: T32A12 TimerA all interrupt /TimerC match, overflow, and underflow
.long INTT32A12_B_C01_CPC_IRQHandler// 55: T32A12 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
.long INTT32A13_A_CT_IRQHandler // 56: T32A13 TimerA all interrupt /TimerC match, overflow, and underflow
.long INTT32A13_B_C01_CPC_IRQHandler// 57: T32A13 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt
.long INTEMG0_IRQHandler // 58: PMD0 EMG interrupt
.long INTOVV0_IRQHandler // 59: PMD0 OVV interrupt
.long INTPWM0_IRQHandler // 60: PMD0 interrupt
.long INTT0RX_IRQHandler // 61: TSPI/SIO reception (channel 0) interrupt
.long INTT0TX_IRQHandler // 62: TSPI/SIO transmit (channel 0) interrupt
.long INTT0ERR_IRQHandler // 63: TSPI/SIO error (channel 0) interrupt
.long INTT1RX_IRQHandler // 64: TSPI/SIO reception (channel 1) interrupt
.long INTT1TX_IRQHandler // 65: TSPI/SIO transmit (channel 1) interrupt
.long INTT1ERR_IRQHandler // 66: TSPI/SIO error (channel 1) interrupt
.long INTT2RX_IRQHandler // 67: TSPI/SIO reception (channel 2) interrupt
.long INTT2TX_IRQHandler // 68: TSPI/SIO transmit (channel 2) interrupt
.long INTT2ERR_IRQHandler // 69: TSPI/SIO error (channel 2) interrupt
.long INTT3RX_IRQHandler // 70: TSPI/SIO reception (channel 3) interrupt
.long INTT3TX_IRQHandler // 71: TSPI/SIO transmit (channel 3) interrupt
.long INTT3ERR_IRQHandler // 72: TSPI/SIO error (channel 3) interrupt
.long INTT4RX_IRQHandler // 73: TSPI/SIO reception (channel 4) interrupt
.long INTT4TX_IRQHandler // 74: TSPI/SIO transmit (channel 4) interrupt
.long INTT4ERR_IRQHandler // 75: TSPI/SIO error (channel 4) interrupt
.long INTT5RX_IRQHandler // 76: TSPI/SIO reception (channel 5) interrupt
.long INTT5TX_IRQHandler // 77: TSPI/SIO transmit (channel 5) interrupt
.long INTT5ERR_IRQHandler // 78: TSPI/SIO error (channel 5) interrupt
.long INTT6RX_IRQHandler // 79: TSPI/SIO reception (channel 6) interrupt
.long INTT6TX_IRQHandler // 80: TSPI/SIO transmit (channel 6) interrupt
.long INTT6ERR_IRQHandler // 81: TSPI/SIO error (channel 6) interrupt
.long INTT7RX_IRQHandler // 82: TSPI/SIO reception (channel 7) interrupt
.long INTT7TX_IRQHandler // 83: TSPI/SIO transmit (channel 7) interrupt
.long INTT7ERR_IRQHandler // 84: TSPI/SIO error (channel 7) interrupt
.long INTT8RX_IRQHandler // 85: TSPI/SIO reception (channel 8) interrupt
.long INTT8TX_IRQHandler // 86: TSPI/SIO transmit (channel 8) interrupt
.long INTT8ERR_IRQHandler // 87: TSPI/SIO error (channel 8) interrupt
.long INTSMI0_IRQHandler // 88: Serial Memory Interface interrupt
.long INTUART0RX_IRQHandler // 89: UART reception (channel 0) interrupt
.long INTUART0TX_IRQHandler // 90: UART transmit (channel 0) interrupt
.long INTUART0ERR_IRQHandler // 91: UART error (channel 0) interrupt
.long INTUART1RX_IRQHandler // 92: UART reception (channel 1) interrupt
.long INTUART1TX_IRQHandler // 93: UART transmit (channel 1) interrupt
.long INTUART1ERR_IRQHandler // 94: UART error (channel 1) interrupt
.long INTUART2RX_IRQHandler // 95: UART reception (channel 2) interrupt
.long INTUART2TX_IRQHandler // 96: UART transmit (channel 2) interrupt
.long INTUART2ERR_IRQHandler // 97: UART error (channel 2) interrupt
.long INTUART3RX_IRQHandler // 98: UART reception (channel 3) interrupt
.long INTUART3TX_IRQHandler // 99: UART transmit (channel 3) interrupt
.long INTUART3ERR_IRQHandler // 100: UART error (channel 3) interrupt
.long INTUART4RX_IRQHandler // 101: UART reception (channel 4) interrupt
.long INTUART4TX_IRQHandler // 102: UART transmit (channel 4) interrupt
.long INTUART4ERR_IRQHandler // 103: UART error (channel 4) interrupt
.long INTUART5RX_IRQHandler // 104: UART reception (channel 5) interrupt
.long INTUART5TX_IRQHandler // 105: UART transmit (channel 5) interrupt
.long INTUART5ERR_IRQHandler // 106: UART error (channel 5) interrupt
.long INTFUART0_IRQHandler // 107: FUART interrupt(channel 0)
.long INTFUART1_IRQHandler // 108: FUART interrupt(channel 1)
.long INTI2C0NST_IRQHandler // 109: I2C0 interrupt / EI2C0 status interrupt
.long INTI2C0ATX_IRQHandler // 110: I2C0 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt
.long INTI2C0BRX_IRQHandler // 111: I2C0 bus free detection interrupt / EI2C0receive buffer empty interrupt
.long INTI2C0NA_IRQHandler // 112: I2C0 NACK detection interrupt
.long INTI2C1NST_IRQHandler // 113: I2C1 interrupt / EI2C0 status interrupt
.long INTI2C1ATX_IRQHandler // 114: I2C1 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt
.long INTI2C1BRX_IRQHandler // 115: I2C1 bus free detection interrupt / EI2C0receive buffer empty interrupt
.long INTI2C1NA_IRQHandler // 116: I2C1 NACK detection interrupt
.long INTI2C2NST_IRQHandler // 117: I2C2 interrupt / EI2C0 status interrupt
.long INTI2C2ATX_IRQHandler // 118: I2C2 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt
.long INTI2C2BRX_IRQHandler // 119: I2C2 bus free detection interrupt / EI2C0receive buffer empty interrupt
.long INTI2C2NA_IRQHandler // 120: I2C2 NACK detection interrupt
.long INTI2C3NST_IRQHandler // 121: I2C3 interrupt / EI2C0 status interrupt
.long INTI2C3ATX_IRQHandler // 122: I2C3 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt
.long INTI2C3BRX_IRQHandler // 123: I2C3 bus free detection interrupt / EI2C0receive buffer empty interrupt
.long INTI2C3NA_IRQHandler // 124: I2C3 NACK detection interrupt
.long INTI2C4NST_IRQHandler // 125: I2C4 interrupt / EI2C0 status interrupt
.long INTI2C4ATX_IRQHandler // 126: I2C4 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt
.long INTI2C4BRX_IRQHandler // 127: I2C4 bus free detection interrupt / EI2C0receive buffer empty interrupt
.long INTI2C4NA_IRQHandler // 128: I2C4 NACK detection interrupt
.long INTADACP0_IRQHandler // 129: ADC conversion monitoring function interrupt 0
.long INTADACP1_IRQHandler // 130: ADC conversion monitoring function interrupt 1
.long INTADATRG_IRQHandler // 131: ADC conversion triggered by General purpose is finished
.long INTADASGL_IRQHandler // 132: ADC conversion triggered by Single program is finished
.long INTADACNT_IRQHandler // 133: ADC conversion triggered by Continuity program is finished
.long INTADAHP_IRQHandler // 134: ADC high priority AD conversion interrupt
.long INTFLDRDY_IRQHandler // 135: Data FLASH Ready interrupt
.long INTFLCRDY_IRQHandler // 136: Code FLASH Area0/1 Ready interrupt
.long 0 // 137: Reserved
.long 0 // 138: Reserved
.long INTMDMAABERR_IRQHandler // 139: MDMA bus error(Unit A) interrupt
.long INTMDMAADERR_IRQHandler // 140: MDMA descriptor error(Unit A) interrupt
.long INTI2S0SI_IRQHandler // 141: I2S ch0 SI transfer end interrupt
.long INTI2S0SIERR_IRQHandler // 142: I2S ch0 SI error interrupt
.long INTI2S0SO_IRQHandler // 143: I2S ch0 SO transfer end interrupt
.long INTI2S0SOERR_IRQHandler // 144: I2S ch0 SO error interrupt
.long INTI2S1SI_IRQHandler // 145: I2S ch1 SI transfer end interrupt
.long INTI2S1SIERR_IRQHandler // 146: I2S ch1 SI error interrupt
.long INTI2S1SO_IRQHandler // 147: I2S ch1 SO transfer end interrupt
.long INTI2S1SOERR_IRQHandler // 148: I2S ch1 SO error interrupt
.long INTFIR0_IRQHandler // 149: FIR ch0 interrupt
.long INTTSSI0RX_IRQHandler // 150: TSSI ch0 RX interrupt
.long INTTSSI0TX_IRQHandler // 151: TSSI ch0 TX interrupt
.long INTTSSI0ERR_IRQHandler // 152: TSSI ch0 error interrupt
.long INTTSSI1RX_IRQHandler // 153: TSSI ch1 RX interrupt
.long INTTSSI1TX_IRQHandler // 154: TSSI ch1 TX interrupt
.long INTTSSI1ERR_IRQHandler // 155: TSSI ch1 error interrupt
.long INTEMA_IRQHandler // 156: Ether MAC interrupt
.long INTEMAMP_IRQHandler // 157: Ether MAC magic packet detection interrupt
.long INTCAN0RX_IRQHandler // 158: CAN ch0 receive interrupt
.long INTCAN0TX_IRQHandler // 159: CAN ch0 transmission interrupt
.long INTCAN0GLB_IRQHandler // 160: CAN ch0 Global interrupt
.long INTCAN1RX_IRQHandler // 161: CAN ch1 receive interrupt
.long INTCAN1TX_IRQHandler // 162: CAN ch1 transmission interrupt
.long INTCAN1GLB_IRQHandler // 163: CAN ch1 Global interrupt
.long INTUSBOTGA_IRQHandler // 164: USB OTG unit A interrupt
.long INTUSBOTGAWK_IRQHandler // 165: USB OTG unit A Wakeup interrupt
.long INTUSBOTGB_IRQHandler // 166: USB OTG unit B interrupt
.long INTUSBOTGBWK_IRQHandler // 167: USB OTG unit B Wakeup interrupt
.long INTT32A14_A_IRQHandler // 168: T32A14 TimerA all interrupt
.long INTT32A14_B_IRQHandler // 169: T32A14 TimerB all interrupt
.long INTT32A14_CT_IRQHandler // 170: T32A14 TimerC match, overflow, and underflow Interrupt
.long INTT32A15_A_IRQHandler // 171: T32A15 TimerA all interrupt
.long INTT32A15_B_IRQHandler // 172: T32A15 TimerB all interrupt
.long INTT32A15_C_IRQHandler // 173: T32A15 TimerC all interrupt
.long INTMDMAADISR_IRQHandler // 174: MDMAC unit A Descriptor interrupt
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler INT00_IRQHandler
def_irq_handler INT01_IRQHandler
def_irq_handler INT02_IRQHandler
def_irq_handler INT03_IRQHandler
def_irq_handler INT04_IRQHandler
def_irq_handler INT05_IRQHandler
def_irq_handler INT06_IRQHandler
def_irq_handler INT07_IRQHandler
def_irq_handler INT08_IRQHandler
def_irq_handler INT09_IRQHandler
def_irq_handler INT10_IRQHandler
def_irq_handler INT11_IRQHandler
def_irq_handler INT12_IRQHandler
def_irq_handler INT13_IRQHandler
def_irq_handler INT14_IRQHandler
def_irq_handler INT15_IRQHandler
def_irq_handler INTRTC_IRQHandler
def_irq_handler INTCEC0RX_IRQHandler
def_irq_handler INTCEC0TX_IRQHandler
def_irq_handler INTISDA_IRQHandler
def_irq_handler INTISDB_IRQHandler
def_irq_handler INTISDC_IRQHandler
def_irq_handler INTRMC0_IRQHandler
def_irq_handler INTRMC1_IRQHandler
def_irq_handler INTLTTMR0_IRQHandler
def_irq_handler INTHDMAATC_IRQHandler
def_irq_handler INTHDMAAERR_IRQHandler
def_irq_handler INTHDMABTC_IRQHandler
def_irq_handler INTHDMABERR_IRQHandler
def_irq_handler INTMDMAATC_IRQHandler
def_irq_handler INTT32A00_A_CT_IRQHandler
def_irq_handler INTT32A00_B_C01_CPC_IRQHandler
def_irq_handler INTT32A01_A_CT_IRQHandler
def_irq_handler INTT32A01_B_C01_CPC_IRQHandler
def_irq_handler INTT32A02_A_CT_IRQHandler
def_irq_handler INTT32A02_B_C01_CPC_IRQHandler
def_irq_handler INTT32A03_A_CT_IRQHandler
def_irq_handler INTT32A03_B_C01_CPC_IRQHandler
def_irq_handler INTT32A04_A_CT_IRQHandler
def_irq_handler INTT32A04_B_C01_CPC_IRQHandler
def_irq_handler INTT32A05_A_CT_IRQHandler
def_irq_handler INTT32A05_B_C01_CPC_IRQHandler
def_irq_handler INTT32A06_A_CT_IRQHandler
def_irq_handler INTT32A06_B_C01_CPC_IRQHandler
def_irq_handler INTT32A07_A_CT_IRQHandler
def_irq_handler INTT32A07_B_C01_CPC_IRQHandler
def_irq_handler INTT32A08_A_CT_IRQHandler
def_irq_handler INTT32A08_B_C01_CPC_IRQHandler
def_irq_handler INTT32A09_A_CT_IRQHandler
def_irq_handler INTT32A09_B_C01_CPC_IRQHandler
def_irq_handler INTT32A10_A_CT_IRQHandler
def_irq_handler INTT32A10_B_C01_CPC_IRQHandler
def_irq_handler INTT32A11_A_CT_IRQHandler
def_irq_handler INTT32A11_B_C01_CPC_IRQHandler
def_irq_handler INTT32A12_A_CT_IRQHandler
def_irq_handler INTT32A12_B_C01_CPC_IRQHandler
def_irq_handler INTT32A13_A_CT_IRQHandler
def_irq_handler INTT32A13_B_C01_CPC_IRQHandler
def_irq_handler INTEMG0_IRQHandler
def_irq_handler INTOVV0_IRQHandler
def_irq_handler INTPWM0_IRQHandler
def_irq_handler INTT0RX_IRQHandler
def_irq_handler INTT0TX_IRQHandler
def_irq_handler INTT0ERR_IRQHandler
def_irq_handler INTT1RX_IRQHandler
def_irq_handler INTT1TX_IRQHandler
def_irq_handler INTT1ERR_IRQHandler
def_irq_handler INTT2RX_IRQHandler
def_irq_handler INTT2TX_IRQHandler
def_irq_handler INTT2ERR_IRQHandler
def_irq_handler INTT3RX_IRQHandler
def_irq_handler INTT3TX_IRQHandler
def_irq_handler INTT3ERR_IRQHandler
def_irq_handler INTT4RX_IRQHandler
def_irq_handler INTT4TX_IRQHandler
def_irq_handler INTT4ERR_IRQHandler
def_irq_handler INTT5RX_IRQHandler
def_irq_handler INTT5TX_IRQHandler
def_irq_handler INTT5ERR_IRQHandler
def_irq_handler INTT6RX_IRQHandler
def_irq_handler INTT6TX_IRQHandler
def_irq_handler INTT6ERR_IRQHandler
def_irq_handler INTT7RX_IRQHandler
def_irq_handler INTT7TX_IRQHandler
def_irq_handler INTT7ERR_IRQHandler
def_irq_handler INTT8RX_IRQHandler
def_irq_handler INTT8TX_IRQHandler
def_irq_handler INTT8ERR_IRQHandler
def_irq_handler INTSMI0_IRQHandler
def_irq_handler INTUART0RX_IRQHandler
def_irq_handler INTUART0TX_IRQHandler
def_irq_handler INTUART0ERR_IRQHandler
def_irq_handler INTUART1RX_IRQHandler
def_irq_handler INTUART1TX_IRQHandler
def_irq_handler INTUART1ERR_IRQHandler
def_irq_handler INTUART2RX_IRQHandler
def_irq_handler INTUART2TX_IRQHandler
def_irq_handler INTUART2ERR_IRQHandler
def_irq_handler INTUART3RX_IRQHandler
def_irq_handler INTUART3TX_IRQHandler
def_irq_handler INTUART3ERR_IRQHandler
def_irq_handler INTUART4RX_IRQHandler
def_irq_handler INTUART4TX_IRQHandler
def_irq_handler INTUART4ERR_IRQHandler
def_irq_handler INTUART5RX_IRQHandler
def_irq_handler INTUART5TX_IRQHandler
def_irq_handler INTUART5ERR_IRQHandler
def_irq_handler INTFUART0_IRQHandler
def_irq_handler INTFUART1_IRQHandler
def_irq_handler INTI2C0NST_IRQHandler
def_irq_handler INTI2C0ATX_IRQHandler
def_irq_handler INTI2C0BRX_IRQHandler
def_irq_handler INTI2C0NA_IRQHandler
def_irq_handler INTI2C1NST_IRQHandler
def_irq_handler INTI2C1ATX_IRQHandler
def_irq_handler INTI2C1BRX_IRQHandler
def_irq_handler INTI2C1NA_IRQHandler
def_irq_handler INTI2C2NST_IRQHandler
def_irq_handler INTI2C2ATX_IRQHandler
def_irq_handler INTI2C2BRX_IRQHandler
def_irq_handler INTI2C2NA_IRQHandler
def_irq_handler INTI2C3NST_IRQHandler
def_irq_handler INTI2C3ATX_IRQHandler
def_irq_handler INTI2C3BRX_IRQHandler
def_irq_handler INTI2C3NA_IRQHandler
def_irq_handler INTI2C4NST_IRQHandler
def_irq_handler INTI2C4ATX_IRQHandler
def_irq_handler INTI2C4BRX_IRQHandler
def_irq_handler INTI2C4NA_IRQHandler
def_irq_handler INTADACP0_IRQHandler
def_irq_handler INTADACP1_IRQHandler
def_irq_handler INTADATRG_IRQHandler
def_irq_handler INTADASGL_IRQHandler
def_irq_handler INTADACNT_IRQHandler
def_irq_handler INTADAHP_IRQHandler
def_irq_handler INTFLDRDY_IRQHandler
def_irq_handler INTFLCRDY_IRQHandler
def_irq_handler INTMDMAABERR_IRQHandler
def_irq_handler INTMDMAADERR_IRQHandler
def_irq_handler INTI2S0SI_IRQHandler
def_irq_handler INTI2S0SIERR_IRQHandler
def_irq_handler INTI2S0SO_IRQHandler
def_irq_handler INTI2S0SOERR_IRQHandler
def_irq_handler INTI2S1SI_IRQHandler
def_irq_handler INTI2S1SIERR_IRQHandler
def_irq_handler INTI2S1SO_IRQHandler
def_irq_handler INTI2S1SOERR_IRQHandler
def_irq_handler INTFIR0_IRQHandler
def_irq_handler INTTSSI0RX_IRQHandler
def_irq_handler INTTSSI0TX_IRQHandler
def_irq_handler INTTSSI0ERR_IRQHandler
def_irq_handler INTTSSI1RX_IRQHandler
def_irq_handler INTTSSI1TX_IRQHandler
def_irq_handler INTTSSI1ERR_IRQHandler
def_irq_handler INTEMA_IRQHandler
def_irq_handler INTEMAMP_IRQHandler
def_irq_handler INTCAN0RX_IRQHandler
def_irq_handler INTCAN0TX_IRQHandler
def_irq_handler INTCAN0GLB_IRQHandler
def_irq_handler INTCAN1RX_IRQHandler
def_irq_handler INTCAN1TX_IRQHandler
def_irq_handler INTCAN1GLB_IRQHandler
def_irq_handler INTUSBOTGA_IRQHandler
def_irq_handler INTUSBOTGAWK_IRQHandler
def_irq_handler INTUSBOTGB_IRQHandler
def_irq_handler INTUSBOTGBWK_IRQHandler
def_irq_handler INTT32A14_A_IRQHandler
def_irq_handler INTT32A14_B_IRQHandler
def_irq_handler INTT32A14_CT_IRQHandler
def_irq_handler INTT32A15_A_IRQHandler
def_irq_handler INTT32A15_B_IRQHandler
def_irq_handler INTT32A15_C_IRQHandler
def_irq_handler INTMDMAADISR_IRQHandler
.end

197
targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TOOLCHAIN_GCC_ARM/tmpm4nrf20fg.ld Normal file
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@ -0,0 +1,197 @@
/*
* Copyright(C) 2021, Toshiba Electronic Device Solutions Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Linker script for Toshiba TMPM4NR */
/* Linker script to configure memory regions. */
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x200000
#endif
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE;
MEMORY
{
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
/* 8_byte_aligned((175 + 16) vect * 4 bytes) = 8_byte_aligned(0x2FC) = 0x300 */
RAM (rwx) : ORIGIN = (0x20000000 + 0x300), LENGTH = (256K - 0x300)
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapBase
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.vectors))
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
*(.ram_func*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
KEEP(*(.stack*))
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

24
targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/cmsis.h Normal file
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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "TMPM4NR.h"
#include "cmsis_nvic.h"
#endif

40
targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/cmsis_nvic.h Normal file
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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#if defined(__ICCARM__)
#pragma section=".intvec"
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec"))
#elif defined(__CC_ARM)
extern uint32_t Load$$LR$$LR_IROM1$$Base[];
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
#elif defined(__GNUC__)
extern uint32_t vectors[];
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)vectors)
#else
#error "Flash vector address not set for this toolchain"
#endif
#define NVIC_NUM_VECTORS (191)
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
#endif

342
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/**
*******************************************************************************
* @file system_TMPM4Nx.c
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for the
* TOSHIBA 'TMPM4Nx' Device Series
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include "TMPM4Nx.h"
#include "txz_flash.h"
#include "txz_hal.h"
/*-------- <<< Start of configuration section >>> ----------------------------*/
/* Semi-Independent Watchdog Timer (SIWDT) Configuration */
#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */
#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */
#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */
/* Clock Generator (CG) Configuration */
#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */
#define SYSCR_GEAR_Val (0x00000000UL) /* GEAR = fc */
#define SYSCR_MCKSEL_Val (0x00000001UL) /* fsysm(phiT0m) = fsysh(phiT0h) / 2 */
#define STBYCR_Val (0x00000000UL)
#define CG_8M_MUL_24_FPLL (0x00245030UL<<8U) /* fPLL = 8MHz * 24 */
#define CG_10M_MUL_19_1875_FPLL (0x002E9626UL<<8U) /* fPLL = 10MHz * 19.1875 */
#define CG_12M_MUL_16_FPLL (0x0036D020UL<<8U) /* fPLL = 12MHz * 16 */
#define CG_16M_MUL_12_FPLL (0x00495018UL<<8U) /* fPLL = 16MHz * 12 */
#define CG_24M_MUL_8_FPLL (0x006D9010UL<<8U) /* fPLL = 24MHz * 8 */
#define CG_PLL0SEL_PLL0ON_SET (0x00000001UL)
#define CG_PLL0SEL_PLL0ON_CLEAR (0xFFFFFFFEUL)
#define CG_PLL0SEL_PLL0SEL_SET (0x00000002UL)
#define CG_PLL0SEL_PLL0SEL_CLEAR (0xFFFFFFFDUL)
#define CG_SYSCR_MCKSEL_SET (SYSCR_MCKSEL_Val << 6U)
#define CG_SYSCR_MCKSELGST_Val (SYSCR_MCKSEL_Val << 22U)
#define CG_SYSCR_MCKSELPST_Val (SYSCR_MCKSEL_Val << 30U)
#define CG_OSCCR_IHOSC1EN_CLEAR (0xFFFFFFFEUL)
#define CG_OSCCR_EOSCEN_SET (0x00000002UL)
#define CG_OSCCR_OSCSEL_SET (0x00000100UL)
#define CG_WUPHCR_WUON_START_SET (0x00000001UL)
#define EXT_CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for External HOSC select the IHOSC1 */
#if (CLOCK_SETUP)
#define CG_WUPHCR_WUCLK_SET (0x00000100UL) /* WUCLK for Inital/Lockup time */
#define PLL0SEL_Ready CG_12M_MUL_16_FPLL
#else
#define CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for Inital/Lockup time */
#define PLL0SEL_Ready CG_10M_MUL_19_1875_FPLL
#endif
#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL)
#define PLL0SEL_MASK (0xFFFFFF00UL)
/*-------- <<< End of configuration section >>> ------------------------------*/
/*-------- DEFINES -----------------------------------------------------------*/
/* Define clocks */
#define EOSC_8M (8000000UL)
#define EOSC_12M (12000000UL)
#define EOSC_16M (16000000UL)
#define EOSC_24M (24000000UL)
#define IOSC_10M (10000000UL)
#define EXTALH EOSC_12M /* External high-speed oscillator freq */
#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */
#define EOSC_8M_DIV2_PLLON (192000000UL) /* 8.00MHz * 48.0000 / 2 */
#define EOSC_12M_DIV2_PLLON (192000000UL) /* 12.00MHz * 32.0000 / 2 */
#define EOSC_16M_DIV2_PLLON (192000000UL) /* 16.00MHz * 24.0000 / 2 */
#define EOSC_24M_DIV2_PLLON (192000000UL) /* 24.00MHz * 16.0000 / 2 */
#define IOSC_10M_DIV2_PLLON (191875000UL) /* 10.00MHz * 38.3750 / 2 */
/* Configure Warm-up time */
#define HZ_1M (1000000UL)
#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */
#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */
#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */
#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR<WUPT11:0> = (warm-up time(us) * IXTALH - 16) / 16 */
#if (CLOCK_SETUP)
#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#else
#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#endif
/* Determine core clock frequency according to settings */
/* System clock is high-speed clock*/
#if (CLOCK_SETUP)
#define CORE_TALH (EXTALH)
#else
#define CORE_TALH (IXTALH)
#endif
#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */
#if (CORE_TALH == EOSC_8M) /* If input is 8MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_24_FPLL))
#define __CORE_CLK EOSC_8M_DIV2_PLLON /* output clock is 192MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 8MHz */
#elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_16_FPLL)
#define __CORE_CLK EOSC_12M_DIV2_PLLON /* output clock is 192MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 12MHz */
#elif (CORE_TALH == EOSC_16M) /* If input is 16MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_16M_MUL_12_FPLL)
#define __CORE_CLK EOSC_16M_DIV2_PLLON /* output clock is 192MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 16MHz */
#elif (CORE_TALH == EOSC_24M) /* If input is 24MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_24M_MUL_8_FPLL)
#define __CORE_CLK EOSC_24M_DIV2_PLLON /* output clock is 192MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 24MHz */
#elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_19_1875_FPLL)
#define __CORE_CLK IOSC_10M_DIV2_PLLON /* output clock is 191.875MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 10MHz */
#else /* input clock not known */
#define __CORE_CLK (0U)
#error "Core Oscillator Frequency invalid!"
#endif /* End switch input clock */
#else
#define __CORE_CLK (CORE_TALH)
#endif
#if ((SYSCR_GEAR_Val & 7U) == 0U) /* Gear -> fc */
#define __CORE_SYS (__CORE_CLK)
#elif ((SYSCR_GEAR_Val & 7U) == 1U) /* Gear -> fc/2 */
#define __CORE_SYS (__CORE_CLK / 2U)
#elif ((SYSCR_GEAR_Val & 7U) == 2U) /* Gear -> fc/4 */
#define __CORE_SYS (__CORE_CLK / 4U )
#elif ((SYSCR_GEAR_Val & 7U) == 3U) /* Gear -> fc/8 */
#define __CORE_SYS (__CORE_CLK / 8U)
#elif ((SYSCR_GEAR_Val & 7U) == 4U) /* Gear -> fc/16 */
#define __CORE_SYS (__CORE_CLK / 16U)
#else /* Gear -> reserved */
#define __CORE_SYS (0U)
#endif
/* Clock Variable definitions */
uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */
uint32_t CoreClockInput = 0U;
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Update SystemCoreClock according register values.
*/
void SystemCoreClockUpdate(void)
{
/* Get Core Clock Frequency */
uint32_t CoreClock = 0U;
uint32_t regval = 0U;
uint32_t oscsel = 0U;
uint32_t pll0sel = 0U;
uint32_t pll0on = 0U;
CoreClockInput = 0U;
/* Determine clock frequency according to clock register values */
/* System clock is high-speed clock */
regval = TSB_CG->OSCCR;
oscsel = regval & CG_OSCCR_OSCSEL_SET;
if (oscsel) { /* If system clock is External high-speed oscillator freq */
CoreClock = EXTALH;
} else { /* If system clock is Internal high-speed oscillator freq */
CoreClock = IXTALH;
}
regval = TSB_CG->PLL0SEL;
pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET;
pll0on = regval & CG_PLL0SEL_PLL0ON_SET;
if (pll0sel && pll0on) { /* If PLL enabled */
if (CoreClock == EOSC_8M) { /* If input is 8MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_24_FPLL) {
CoreClockInput = EOSC_8M_DIV2_PLLON; /* output clock is 192MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == EOSC_12M) { /* If input is 12MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_16_FPLL) {
CoreClockInput = EOSC_12M_DIV2_PLLON; /* output clock is 192MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == EOSC_16M) { /* If input is 16MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_16M_MUL_12_FPLL) {
CoreClockInput = EOSC_16M_DIV2_PLLON; /* output clock is 192MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == EOSC_24M) { /* If input is 24MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_24M_MUL_8_FPLL) {
CoreClockInput = EOSC_24M_DIV2_PLLON; /* output clock is 192MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == IOSC_10M) { /* If input is 10MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_19_1875_FPLL) {
CoreClockInput = IOSC_10M_DIV2_PLLON; /* output clock is 191.875MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else {
CoreClockInput = 0U;
}
} else { /* If PLL not used */
CoreClockInput = CoreClock;
}
switch (TSB_CG->SYSCR & 7U) {
case 0U: /* Gear -> fc */
SystemCoreClock = CoreClockInput;
break;
case 1U: /* Gear -> fc/2 */
SystemCoreClock = CoreClockInput / 2U;
break;
case 2U: /* Gear -> fc/4 */
SystemCoreClock = CoreClockInput / 4U;
break;
case 3U: /* Gear -> fc/8 */
SystemCoreClock = CoreClockInput / 8U;
break;
case 4U: /* Gear -> fc/16 */
SystemCoreClock = CoreClockInput / 16U;
break;
case 5U:
case 6U:
case 7U:
SystemCoreClock = 0U;
break;
default:
SystemCoreClock = 0U;
break;
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit(void)
{
#if (SIWD_SETUP) /* Watchdog Setup */
/* SIWD Disable */
TSB_SIWD0->EN = SIWDEN_Val;
TSB_SIWD0->CR = SIWDCR_Val;
#else
/* SIWD Enable (Setting after a Reset) */
#endif
#if defined ( __CC_ARM )
/* set Flash Access Control Register */
Copy_Routine(FLASH_API_RAM, FLASH_API_ROM, SIZE_FLASH_API); /* copy flash API to RAM */
#endif
fc_read_clock_set(__CORE_SYS);
fc_ram_con_reg_set(__CORE_SYS);
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) /* FPU setting */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
#if (CLOCK_SETUP) /* Clock(external) Setup */
TSB_CG->SYSCR = SYSCR_GEAR_Val;
TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | EXT_CG_WUPHCR_WUCLK_SET);
TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET;
TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | EXT_CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
while (TSB_CG_WUPHCR_WUEF) {
;
} /* Warm-up */
TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
while (!TSB_CG_OSCCR_OSCF) {
;
} /* Confirm CGOSCCR<OSCF>="1" */
TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ;
#else
/* Internal HOSC Enable (Setting after a Reset) */
#endif
TSB_CG->SYSCR = (SYSCR_GEAR_Val | CG_SYSCR_MCKSEL_SET); /* set <MCKSEL> */
while ((TSB_CG->SYSCR & (CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val))
!= ((CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val))) {
;
}
TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET);
TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */
TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR;
TSB_CG->PLL0SEL = PLL0SEL_Ready;
TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
while (TSB_CG_WUPHCR_WUEF) {
;
} /* Warm-up */
TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET);
TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */
TSB_CG->STBYCR = STBYCR_Val;
TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
while (TSB_CG_WUPHCR_WUEF) {
;
} /* Lockup */
TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET;
while (!TSB_CG_PLL0SEL_PLL0ST) {
;
} /*Confirm CGPLL0SEL<PLL0ST> = "1" */
}

66
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/**
*****************************************************************************
* @file system_TMPM4Nx.h
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the
* TOSHIBA 'TMPM4Nx' Device Series
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*****************************************************************************
*/
#include <stdint.h>
#ifndef __SYSTEM_TMPM4Nx_H
#define __SYSTEM_TMPM4Nx_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t CoreClockInput; /*!< High speed Clock Frequency */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit(void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "flash_api.h"
#include "mbed_critical.h"
#include "txz_fc.h"
#define PROGRAM_WRITE_MAX (16U) // Page program could be written 16 bytes/4 words once
#define SECTOR_SIZE (0x8000) // 32KB each sectors or block
#define FLASH_CHIP_SIZE (0x00200000) // Flash chip size is 2048 KByte
#define MASK_CHIP_ID_FROM_ADD (0x00FFFFFFUL)
#define SUCCESS (0U)
#define FAIL (-1)
// IHOSC1EN
#define CGOSCCR_IHOSC1EN_MASK ((uint32_t)0x00000001) // IHOSC1EN :Mask
#define CGOSCCR_IHOSC1EN_RW_DISABLE ((uint32_t)0x00000000) // IHOSC1EN :[R/W] :Disable
#define CGOSCCR_IHOSC1EN_RW_ENABLE ((uint32_t)0x00000001) // IHOSC1EN :[R/W] :Enable
static void internal_hosc_enable(void);
int32_t flash_init(flash_t *obj)
{
obj->flash_inited = 0;
obj->flash_inited = 1;
internal_hosc_enable(); // Internal HOSC enable
return 0;
}
int32_t flash_free(flash_t *obj)
{
obj->flash_inited = 0;
return 0;
}
int32_t flash_erase_sector(flash_t *obj, uint32_t address)
{
int status = FAIL;
if (obj->flash_inited == 0) {
flash_init(obj);
}
// We need to prevent flash accesses during erase operation
core_util_critical_section_enter();
if (TXZ_SUCCESS == fc_erase_block_code_flash((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP, (uint32_t *)address)) {
status = SUCCESS;
} else {
// Do nothing
}
core_util_critical_section_exit();
return status;
}
int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
{
int status = SUCCESS;
address &= MASK_CHIP_ID_FROM_ADD;
// We need to prevent flash accesses during program operation
core_util_critical_section_enter();
if (TXZ_SUCCESS == fc_write_code_flash((uint32_t *)data, (uint32_t *)address, size)) {
// Do nothing
} else {
status = FAIL;
}
core_util_critical_section_exit();
return status;
}
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
{
if ((address >= FC_CODE_FLASH_ADDRESS_TOP) && (address < (FC_CODE_FLASH_ADDRESS_TOP + FLASH_CHIP_SIZE))) {
return SECTOR_SIZE;
} else {
// Do nothing
}
return MBED_FLASH_INVALID_SIZE;
}
uint32_t flash_get_page_size(const flash_t *obj)
{
return PROGRAM_WRITE_MAX;
}
uint32_t flash_get_start_address(const flash_t *obj)
{
return FC_CODE_FLASH_ADDRESS_TOP;
}
uint32_t flash_get_size(const flash_t *obj)
{
return FLASH_CHIP_SIZE;
}
static void internal_hosc_enable(void)
{
uint32_t work;
work = (uint32_t)(TSB_CG->OSCCR & ~CGOSCCR_IHOSC1EN_MASK);
TSB_CG->OSCCR = (uint32_t)(work | CGOSCCR_IHOSC1EN_RW_ENABLE);
}
uint8_t flash_get_erase_value(const flash_t *obj)
{
(void)obj;
return 0xFF;
}

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "txz_gpio.h"
#define GPIO_DATA PIN_DATA(0, 2)
#define ALT_FUNC_GPIO 0
_gpio_t gpio_port_add = {
.p_pa_instance = TSB_PA,
.p_pb_instance = TSB_PB,
.p_pc_instance = TSB_PC,
.p_pd_instance = TSB_PD,
.p_pe_instance = TSB_PE,
.p_pf_instance = TSB_PF,
.p_pg_instance = TSB_PG,
.p_ph_instance = TSB_PH,
.p_pj_instance = TSB_PJ,
.p_pk_instance = TSB_PK,
.p_pl_instance = TSB_PL,
.p_pm_instance = TSB_PM,
.p_pn_instance = TSB_PN,
.p_pp_instance = TSB_PP,
.p_pr_instance = TSB_PR,
.p_pt_instance = TSB_PT,
.p_pu_instance = TSB_PU,
.p_pv_instance = TSB_PV,
.p_pw_instance = TSB_PW,
.p_py_instance = TSB_PY
};
uint32_t gpio_set(PinName pin)
{
// Check that pin is valid
MBED_ASSERT(pin != (PinName)NC);
// Set pin function as GPIO pin
pin_function(pin, GPIO_DATA);
// Return pin mask
return (1 << (pin & 0x07));
}
void gpio_init(gpio_t *obj, PinName pin)
{
// Store above pin mask, pin name into GPIO object
obj->pin = pin;
if (pin == (PinName)NC) {
return;
}
obj->pin_num = PIN_POS(pin);
obj->mask = gpio_set(pin);
obj->port = (PortName) PIN_PORT(pin);
// Enable clock for particular port
TSB_CG->FSYSMENB |= (1 << ((obj->port) + 2));
}
void gpio_mode(gpio_t *obj, PinMode mode)
{
// Set pin mode
pin_mode(obj->pin, mode);
}
// Set gpio object pin direction
void gpio_dir(gpio_t *obj, PinDirection direction)
{
// Set direction
switch (direction) {
case PIN_INPUT:
// Set pin input
gpio_func(&gpio_port_add,
(gpio_gr_t)obj->port,
(gpio_num_t)obj->pin_num,
(uint32_t)ALT_FUNC_GPIO,
GPIO_PIN_INPUT);
break;
case PIN_OUTPUT:
// Set pin output
gpio_func(&gpio_port_add,
(gpio_gr_t)obj->port,
(gpio_num_t)obj->pin_num,
(uint32_t)ALT_FUNC_GPIO,
GPIO_PIN_OUTPUT);
break;
case PIN_INOUT:
// Set pin both input and output
gpio_func(&gpio_port_add,
(gpio_gr_t)obj->port,
(gpio_num_t)obj->pin_num,
(uint32_t)ALT_FUNC_GPIO,
GPIO_PIN_INOUT);
break;
default:
break;
}
}
void gpio_write(gpio_t *obj, int value)
{
// Write gpio object pin data
gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, value);
}
int gpio_read(gpio_t *obj)
{
// Read gpio object pin data
gpio_pinstate_t val = GPIO_PIN_SET; // To initialize local variable
gpio_read_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, &val);
return val;
}

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_irq_api.h"
#include "mbed_error.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "mbed_critical.h"
#include "txz_gpio.h"
#define CHANNEL_NUM (16)
#define DISABLE (0)
#define ENABLE (1)
#define CLR_INT_FLAG (0xC0)
const PinMap PinMap_GPIO_IRQ[] = {
{PT3, GPIO_IRQ_0, PIN_DATA(0, 0)},
{PL0, GPIO_IRQ_1, PIN_DATA(0, 0)},
{PA0, GPIO_IRQ_2, PIN_DATA(0, 0)},
{PL6, GPIO_IRQ_3, PIN_DATA(0, 0)},
{PF0, GPIO_IRQ_4, PIN_DATA(0, 0)},
{PF7, GPIO_IRQ_5, PIN_DATA(0, 0)},
{PU2, GPIO_IRQ_6, PIN_DATA(0, 0)},
{PU3, GPIO_IRQ_7, PIN_DATA(0, 0)},
{PU4, GPIO_IRQ_8, PIN_DATA(0, 0)},
{PU5, GPIO_IRQ_9, PIN_DATA(0, 0)},
{PP6, GPIO_IRQ_A, PIN_DATA(0, 0)},
{PK1, GPIO_IRQ_B, PIN_DATA(0, 0)},
{PL4, GPIO_IRQ_C, PIN_DATA(0, 0)},
{PL5, GPIO_IRQ_D, PIN_DATA(0, 0)},
{PC6, GPIO_IRQ_E, PIN_DATA(0, 0)},
{PM4, GPIO_IRQ_F, PIN_DATA(0, 0)},
{NC, NC, 0}
};
extern _gpio_t gpio_port_add;
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL};
static CG_INTActiveState CurrentState;
static void CG_SetSTBYReleaseINTSrc(CG_INTSrc, CG_INTActiveState, uint8_t);
static void INT_IRQHandler(PinName, uint32_t);
void INT00_IRQHandler(void)
{
INT_IRQHandler(PT3, 0);
}
void INT01_IRQHandler(void)
{
INT_IRQHandler(PL0, 1);
}
void INT02_IRQHandler(void)
{
INT_IRQHandler(PA0, 2);
}
void INT03_IRQHandler(void)
{
INT_IRQHandler(PL6, 3);
}
void INT04_IRQHandler(void)
{
INT_IRQHandler(PF0, 4);
}
void INT05_IRQHandler(void)
{
INT_IRQHandler(PF7, 5);
}
void INT06_IRQHandler(void)
{
INT_IRQHandler(PU2, 6);
}
void INT07_IRQHandler(void)
{
INT_IRQHandler(PU3, 7);
}
void INT08_IRQHandler(void)
{
INT_IRQHandler(PU4, 8);
}
void INT09_IRQHandler(void)
{
INT_IRQHandler(PU5, 9);
}
void INT10_IRQHandler(void)
{
INT_IRQHandler(PP6, 10);
}
void INT11_IRQHandler(void)
{
INT_IRQHandler(PK1, 11);
}
void INT12_IRQHandler(void)
{
INT_IRQHandler(PL4, 12);
}
void INT13_IRQHandler(void)
{
INT_IRQHandler(PL5, 13);
}
void INT14_IRQHandler(void)
{
INT_IRQHandler(PC6, 14);
}
void INT15_IRQHandler(void)
{
INT_IRQHandler(PM4, 15);
}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t id)
{
// Get gpio interrupt ID
obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ);
core_util_critical_section_enter();
// Get GPIO port and pin num
obj->port = (PortName)PIN_PORT(pin);
obj->pin_num = PIN_POS(pin);
// Set pin level as LOW
gpio_write_bit(&gpio_port_add, obj->port, obj->pin_num, GPIO_Mode_DATA, 0);
// Enable gpio interrupt function
pinmap_pinout(pin, PinMap_GPIO_IRQ);
// Get GPIO irq source
obj->irq_src = (CG_INTSrc)obj->irq_id;
// Save irq handler
hal_irq_handler[obj->irq_src] = handler;
// Save irq id
channel_ids[obj->irq_src] = id;
// Initialize interrupt event as both edges detection
obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
// Clear gpio pending interrupt
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
// Set interrupt event and enable INTx clear
CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE);
core_util_critical_section_exit();
return 0;
}
void gpio_irq_free(gpio_irq_t *obj)
{
// Clear gpio_irq
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
// Reset interrupt handler
hal_irq_handler[obj->irq_src] = NULL;
// Reset interrupt id
channel_ids[obj->irq_src] = 0;
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
{
// Disable GPIO interrupt on obj
gpio_irq_disable(obj);
if (enable) {
// Get gpio interrupt event
if (event == IRQ_RISE) {
if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) ||
(obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) {
obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
} else {
obj->event = CG_INT_ACTIVE_STATE_RISING;
}
} else if (event == IRQ_FALL) {
if ((obj->event == CG_INT_ACTIVE_STATE_RISING) ||
(obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) {
obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
} else {
obj->event = CG_INT_ACTIVE_STATE_FALLING;
}
} else {
error("Not supported event\n");
}
} else {
// Get gpio interrupt event
if (event == IRQ_RISE) {
if ((obj->event == CG_INT_ACTIVE_STATE_RISING) ||
(obj->event == CG_INT_ACTIVE_STATE_INVALID)) {
obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
} else {
obj->event = CG_INT_ACTIVE_STATE_FALLING;
}
} else if (event == IRQ_FALL) {
if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) ||
(obj->event == CG_INT_ACTIVE_STATE_INVALID)) {
obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
} else {
obj->event = CG_INT_ACTIVE_STATE_RISING;
}
} else {
error("Not supported event\n");
}
}
CurrentState = obj->event;
if (obj->event != CG_INT_ACTIVE_STATE_INVALID) {
// Set interrupt event and enable INTx clear
CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE);
gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 0);
} else {
gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 1);
}
// Clear interrupt request
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
// Enable GPIO interrupt on obj
gpio_irq_enable(obj);
}
void gpio_irq_enable(gpio_irq_t *obj)
{
// Clear and Enable gpio_irq object
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
NVIC_EnableIRQ((IRQn_Type)obj->irq_id);
}
void gpio_irq_disable(gpio_irq_t *obj)
{
// Disable gpio_irq object
NVIC_DisableIRQ((IRQn_Type)obj->irq_id);
}
static void INT_IRQHandler(PinName pin, uint32_t index)
{
PortName port;
uint8_t pin_num;
gpio_pinstate_t data = GPIO_PIN_RESET;
pin_num = PIN_POS(pin);
port = (PortName)PIN_PORT(pin);
// Clear interrupt request
CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, DISABLE);
// Get pin value
gpio_read_bit(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)pin_num, GPIO_Mode_DATA, &data);
switch (data) {
// Falling edge detection
case 0:
hal_irq_handler[index](channel_ids[index], IRQ_FALL);
break;
// Rising edge detection
case 1:
hal_irq_handler[index](channel_ids[index], IRQ_RISE);
break;
default:
break;
}
// Clear gpio pending interrupt
NVIC_ClearPendingIRQ((IRQn_Type)(CG_INT_SRC_0 + index));
// Enable interrupt request
CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, ENABLE);
}
static void CG_SetSTBYReleaseINTSrc(CG_INTSrc INTSource, CG_INTActiveState ActiveState, uint8_t NewState)
{
uint8_t *ptr;
if (((INTSource == CG_INT_SRC_1) || (INTSource == CG_INT_SRC_2)
|| (INTSource == CG_INT_SRC_B) || (INTSource == CG_INT_SRC_E))) {
ptr = ((uint8_t *)(&(TSB_IA->IMC00)) + (INTSource * 2));
} else {
ptr = ((uint8_t *)(&(TSB_IA->IMC00)) + (INTSource * 2) + 1);
}
// Clear pending falling and rising edge bit
*ptr = CLR_INT_FLAG;
*ptr = (ActiveState | NewState);
{
uint8_t regval = *ptr;
(void)regval;
}
}

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#include "mbed_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
uint32_t pin_num;
uint32_t mask;
PinName pin;
PortName port;
} gpio_t;
typedef enum {
CG_INT_SRC_0 = 0U,
CG_INT_SRC_1,
CG_INT_SRC_2,
CG_INT_SRC_3,
CG_INT_SRC_4,
CG_INT_SRC_5,
CG_INT_SRC_6,
CG_INT_SRC_7,
CG_INT_SRC_8,
CG_INT_SRC_9,
CG_INT_SRC_A,
CG_INT_SRC_B,
CG_INT_SRC_C,
CG_INT_SRC_D,
CG_INT_SRC_E,
CG_INT_SRC_F
} CG_INTSrc;
typedef enum {
CG_INT_ACTIVE_STATE_L = 0x00U,
CG_INT_ACTIVE_STATE_H = 0x02U,
CG_INT_ACTIVE_STATE_FALLING = 0x04U,
CG_INT_ACTIVE_STATE_RISING = 0x06U,
CG_INT_ACTIVE_STATE_BOTH_EDGES = 0x08U,
CG_INT_ACTIVE_STATE_INVALID = 0x0AU
} CG_INTActiveState;
static inline int gpio_is_connected(const gpio_t *obj)
{
return (obj->pin != (PinName)NC);
}
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "i2c_api.h"
#if DEVICE_I2C
#include <stdlib.h>
#include <string.h>
#include "mbed_error.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "txz_i2c_api.h"
#define MAX_I2C_FREQ 1000000
#define I2C_TRANSFER_STATE_IDLE (0x0U)
#if DEVICE_I2C_ASYNCH
#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c))
#else
#define I2C_S(obj) (struct i2c_s *) (obj)
#endif
static const PinMap PinMap_I2C_SDA[] = {
{PF2, I2C_0, PIN_DATA(7, 2)},
{PV5, I2C_1, PIN_DATA(6, 2)},
{PJ6, I2C_2, PIN_DATA(7, 2)},
{PJ3, I2C_3, PIN_DATA(7, 2)},
{NC, NC, 0}
};
static const PinMap PinMap_I2C_SCL[] = {
{PF3, I2C_0, PIN_DATA(7, 2)},
{PV4, I2C_1, PIN_DATA(6, 2)},
{PJ7, I2C_2, PIN_DATA(7, 2)},
{PJ2, I2C_3, PIN_DATA(7, 2)},
{NC, NC, 0}
};
// Initialize the I2C peripheral. It sets the default parameters for I2C
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
struct i2c_s *obj_s = I2C_S(obj);
MBED_ASSERT(obj_s != NULL);
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
MBED_ASSERT((int)i2c_name != NC);
obj_s->index = i2c_name;
obj_s->is_master = 1;
switch (i2c_name) {
case I2C_0:
TSB_CG_FSYSMENA_IPMENA30 = TXZ_ENABLE; // Enable clock for I2C_1
TSB_CG_FSYSMENB_IPMENB07 = TXZ_ENABLE; // Enable clock for GPIO F
obj_s->my_i2c.i2c.p_instance = TSB_I2C1;
obj_s->irqn = INTI2C1NST_IRQn;
break;
case I2C_1:
TSB_CG_FSYSMENA_IPMENA31 = TXZ_ENABLE; // Enable clock for I2C_2
TSB_CG_FSYSMENB_IPMENB19 = TXZ_ENABLE; // Enable clock for GPIO V
obj_s->my_i2c.i2c.p_instance = TSB_I2C2;
obj_s->irqn = INTI2C1NST_IRQn;
break;
case I2C_2:
TSB_CG_FSYSMENB_IPMENB00 = TXZ_ENABLE; // Enable clock for I2C_3
TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; // Enable clock for GPIO J
obj_s->my_i2c.i2c.p_instance = TSB_I2C3;
obj_s->irqn = INTI2C3NST_IRQn;
break;
case I2C_3:
TSB_CG_FSYSMENB_IPMENB01 = TXZ_ENABLE; // Enable clock for I2C_4
TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; // Enable clock for GPIO J
obj_s->my_i2c.i2c.p_instance = TSB_I2C4;
obj_s->irqn = INTI2C4NST_IRQn;
break;
default:
error("I2C is not available");
break;
}
pinmap_pinout(sda, PinMap_I2C_SDA);
pin_mode(sda, OpenDrain);
pin_mode(sda, PullUp);
pinmap_pinout(scl, PinMap_I2C_SCL);
pin_mode(scl, OpenDrain);
pin_mode(scl, PullUp);
i2c_reset(obj);
i2c_frequency(obj, 100000);
I2C_init(&obj_s->my_i2c.i2c);
}
// Configure the I2C frequency
void i2c_frequency(i2c_t *obj, int hz)
{
struct i2c_s *obj_s = I2C_S(obj);
if (hz > MAX_I2C_FREQ) {
error("Failed : Max I2C frequency is 1000000");
}
i2c_frequency_t(&obj_s->my_i2c, hz);
if (obj_s->is_master) {
I2C_init(&obj_s->my_i2c.i2c);
} else {
I2C_slave_init(&obj_s->my_i2c.i2c);
}
}
int i2c_start(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
i2c_start_t(&obj_s->my_i2c);
return TXZ_SUCCESS;
}
int i2c_stop(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
i2c_stop_t(&obj_s->my_i2c);
return TXZ_SUCCESS;
}
void i2c_reset(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
// Software reset
i2c_reset_t(&obj_s->my_i2c);
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{
int32_t count = 0;
struct i2c_s *obj_s = I2C_S(obj);
count = i2c_read_t(&obj_s->my_i2c, address, (uint8_t *)data, length, stop);
return count;
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
{
int32_t count = 0;
struct i2c_s *obj_s = I2C_S(obj);
count = i2c_write_t(&obj_s->my_i2c, address, (uint8_t *)data, length, stop);
return count;
}
int i2c_byte_read(i2c_t *obj, int last)
{
int32_t data = 0;
struct i2c_s *obj_s = I2C_S(obj);
data = i2c_byte_read_t(&obj_s->my_i2c, last);
return data;
}
int i2c_byte_write(i2c_t *obj, int data)
{
int32_t result = 0;
struct i2c_s *obj_s = I2C_S(obj);
result = i2c_byte_write_t(&obj_s->my_i2c, data);
return result;
}
void i2c_slave_mode(i2c_t *obj, int enable_slave)
{
struct i2c_s *obj_s = I2C_S(obj);
obj_s->is_master = 0;
i2c_slave_mode_t(&obj_s->my_i2c, enable_slave);
}
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
{
struct i2c_s *obj_s = I2C_S(obj);
i2c_slave_address_t(&obj_s->my_i2c, address);
}
int i2c_slave_receive(i2c_t *obj)
{
int32_t result = 0;
struct i2c_s *obj_s = I2C_S(obj);
result = i2c_slave_receive_t(&obj_s->my_i2c);
return result;
}
int i2c_slave_read(i2c_t *obj, char *data, int length)
{
int32_t count = 0;
struct i2c_s *obj_s = I2C_S(obj);
count = i2c_slave_read_t(&obj_s->my_i2c, (uint8_t *)data, length);
return count;
}
int i2c_slave_write(i2c_t *obj, const char *data, int length)
{
int32_t count = 0;
struct i2c_s *obj_s = I2C_S(obj);
count = i2c_slave_write_t(&obj_s->my_i2c, (uint8_t *)data, length);
return count;
}
const PinMap *i2c_master_sda_pinmap()
{
return PinMap_I2C_SDA;
}
const PinMap *i2c_master_scl_pinmap()
{
return PinMap_I2C_SCL;
}
const PinMap *i2c_slave_sda_pinmap()
{
return PinMap_I2C_SDA;
}
const PinMap *i2c_slave_scl_pinmap()
{
return PinMap_I2C_SCL;
}
#if DEVICE_I2C_ASYNCH
void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address,
uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
{
struct i2c_s *obj_s = I2C_S(obj);
obj_s->event_mask = event;
//Set irqn table for future use
set_i2c(obj_s->index, &obj_s->my_i2c.info.irqn);
NVIC_SetVector(obj_s->irqn, handler);
i2c_transfer_asynch_t(&obj_s->my_i2c, (uint8_t *)tx, tx_length, (uint8_t *)rx, rx_length, address, stop);
}
uint32_t i2c_irq_handler_asynch(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
uint32_t event = 0;
event = i2c_irq_handler_asynch_t(&obj_s->my_i2c);
return (event & obj_s->event_mask);
}
uint8_t i2c_active(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
uint8_t ret = (obj_s->my_i2c.info.asynch.state != I2C_TRANSFER_STATE_IDLE);
return ret;
}
void i2c_abort_asynch(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
i2c_abort_asynch_t(&obj_s->my_i2c);
}
#endif // #if DEVICE_I2C_ASYNCH
#endif // #if DEVICE_I2C

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include <stdbool.h>
#include "PortNames.h"
#include "PeripheralNames.h"
#include "gpio_object.h"
#include "txz_uart.h"
#include "txz_fuart.h"
#include "txz_tspi.h"
#include "txz_t32a.h"
#include "txz_cg.h"
#include "txz_driver_def.h"
#include "txz_adc.h"
#include "txz_i2c_api.h"
#include "txz_i2c.h"
#include "txz_fuart_include.h"
#ifdef __cplusplus
extern "C" {
#endif
struct port_s {
uint32_t mask;
PortName port;
};
struct dac_s {
DACName dac;
TSB_DA_TypeDef *DACx;
};
typedef struct {
uint32_t BaudRate;
uint32_t DataBits;
uint32_t StopBits;
uint32_t Parity;
uint32_t Mode;
uint32_t FlowCtrl;
} FUART_InitTypeDef;
struct serial_s {
uint32_t index;
uint32_t mode;
uint8_t is_using_fuart;
TSB_UART_TypeDef *UARTx;
TSB_FURT_TypeDef *FUARTx;
uart_boudrate_t boud_obj;
fuart_boudrate_t boudrate;
FUART_InitTypeDef fuart_config;
};
struct pwmout_s {
uint32_t divisor;
uint32_t type;
uint32_t trailing_timing;
uint32_t leading_timing;
float period;
t32a_t p_t32a;
PinName pin;
};
struct spi_s {
tspi_t p_obj;
SPIName module;
uint8_t bits;
PinName Slave_SCK;
#if DEVICE_SPI_ASYNCH
uint32_t irqn;
uint32_t event;
uint32_t max_size;
uint32_t state;
#endif
};
struct gpio_irq_s {
PortName port;
uint8_t pin_num;
uint32_t irq_id;
CG_INTSrc irq_src;
CG_INTActiveState event;
};
struct flash_s {
int flash_inited;
};
struct analogin_s {
adc_t p_adc;
PinName pin;
ADCName adc;
adc_channel_setting_t param;
};
struct i2c_s {
uint8_t is_master;
uint32_t index;
IRQn_Type irqn;
_i2c_t my_i2c;
#if DEVICE_I2C_ASYNCH
uint32_t event_mask;
#endif
};
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "mbed_error.h"
#include "pinmap.h"
#include "txz_gpio.h"
#define PIN_FUNC_MAX 8
extern _gpio_t gpio_port_add;
void pin_function(PinName pin, int function)
{
uint32_t port = 0;
uint8_t bit = 0;
uint8_t func = 0;
uint8_t dir = 0;
// Assert that pin is valid
MBED_ASSERT(pin != NC);
// Calculate pin function and pin direction
func = PIN_FUNC(function);
dir = PIN_DIR(function);
// Calculate port and pin position
port = PIN_PORT(pin);
bit = PIN_POS(pin);
// Find function is in range or not
if (func <= PIN_FUNC_MAX) {
// Set pin function and direction if direction is in range
switch (dir) {
case PIN_INPUT:
// Set pin input
gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INPUT);
break;
case PIN_OUTPUT:
// Set pin output
gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_OUTPUT);
break;
case PIN_INOUT:
// Set pin both input and output
gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INOUT);
break;
default:
break;
}
} else {
// Do nothing
}
}
void pin_mode(PinName pin, PinMode mode)
{
uint32_t port = 0;
uint8_t bit = 0;
// Assert that pin is valid
MBED_ASSERT(pin != NC);
// Check if function is in range
if (mode > OpenDrain) {
return;
}
// Calculate port and pin position
port = PIN_PORT(pin);
bit = PIN_POS(pin);
// Set pin mode
switch (mode) {
case PullNone:
gpio_SetPullUp(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET);
gpio_SetPullDown(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET);
gpio_SetOpenDrain(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET);
break;
case PullUp:
gpio_SetPullUp(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET);
break;
case PullDown:
gpio_SetPullDown(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET);
break;
case OpenDrain:
gpio_SetOpenDrain(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET);
break;
default:
break;
}
}

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "port_api.h"
#include "mbed_assert.h"
#include "mbed_error.h"
#include "txz_gpio.h"
#include "pinmap.h"
#define PORT_PIN_NUM (8)
#define ALT_FUNC_GPIO (0)
extern _gpio_t gpio_port_add;
static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num);
PinName port_pin(PortName port, int pin_n)
{
PinName pin = NC;
pin = (PinName)((port << 3) | pin_n);
return pin;
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
{
uint8_t i = 0;
// Assert that port is valid
MBED_ASSERT(port <= PortY);
// Store port and port mask for future use
obj->port = port;
obj->mask = mask;
// Enable the clock for particular port
_gpio_init(&gpio_port_add, obj->port);
// Set port function and port direction
for (i = 0; i < PORT_PIN_NUM; i++) {
// If the pin is used
if (obj->mask & (1 << i)) {
pin_function(port_pin(obj->port, i), dir);
}
}
}
void port_mode(port_t *obj, PinMode mode)
{
uint8_t i = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortY);
// Set mode for masked pins
for (i = 0; i < PORT_PIN_NUM; i++) {
// If the pin is used
if (obj->mask & (1 << i)) {
pin_mode(port_pin(obj->port, i), mode);
}
}
}
void port_dir(port_t *obj, PinDirection dir)
{
uint8_t i = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortY);
for (i = 0; i < PORT_PIN_NUM; i++) {
// Set direction for masked pins
if (obj->mask & (1 << i)) {
gpio_pin_dir(obj, dir, i);
}
}
}
void port_write(port_t *obj, int value)
{
uint32_t port_data = 0;
uint32_t data = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortY);
// Get current data of port
gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data);
// Calculate data to write to masked pins
data = (port_data & ~obj->mask) | (value & obj->mask);
// Write data to masked pins of the port
gpio_write_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, data);
}
int port_read(port_t *obj)
{
uint32_t port_data = 0;
uint32_t data = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortY);
// Get current data of port
gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data);
// Calculate data of masked pins
data = port_data & obj->mask;
return data;
}
static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num)
{
switch (dir) {
case PIN_INPUT:
// Set pin input
gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INPUT);
break;
case PIN_OUTPUT:
// Set pin output
gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_OUTPUT);
break;
case PIN_INOUT:
// Set pin both input and output
gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INOUT);
break;
default:
// error("Invalid direction\n");
break;
}
}

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "pwmout_api.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#define GPIO_CLK_OFFSET 2
// Because Timer operating frequency is 3.0 MhZ
#define CALCULATE_RGC1_VAL 2.95
static const PinMap PinMap_PWM[] = {
{PW1, PWM_0, PIN_DATA(7, 1)},
{PW2, PWM_1, PIN_DATA(7, 1)},
{PT3, PWM_2, PIN_DATA(3, 1)},
{PD2, PWM_3, PIN_DATA(5, 1)},
{PD4, PWM_4, PIN_DATA(5, 1)},
{PE1, PWM_5, PIN_DATA(5, 1)},
{PE6, PWM_6, PIN_DATA(5, 1)},
{PL4, PWM_7, PIN_DATA(3, 1)},
{PL6, PWM_8, PIN_DATA(3, 1)},
{PC4, PWM_9, PIN_DATA(5, 1)},
{PW6, PWM_10, PIN_DATA(7, 1)},
{PU0, PWM_11, PIN_DATA(3, 1)},
{PU6, PWM_12, PIN_DATA(3, 1)},
{NC, NC, 0}
};
void pwmout_init(pwmout_t *obj, PinName pin)
{
// Determine the pwm channel
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
// Assert input is valid
MBED_ASSERT(pwm != (PWMName)NC);
switch (pwm) {
case PWM_0:
obj->p_t32a.p_instance = TSB_T32A0;
// Clock enable of T32A ch00
TSB_CG_FSYSMENA_IPMENA06 = TXZ_ENABLE;
break;
case PWM_1:
obj->p_t32a.p_instance = TSB_T32A1;
// Clock enable of T32A ch01
TSB_CG_FSYSMENA_IPMENA07 = TXZ_ENABLE;
break;
case PWM_2:
obj->p_t32a.p_instance = TSB_T32A3;
// Clock enable of T32A ch03
TSB_CG_FSYSMENA_IPMENA09 = TXZ_ENABLE;
break;
case PWM_3:
obj->p_t32a.p_instance = TSB_T32A4;
// Clock enable of T32A ch04
TSB_CG_FSYSMENA_IPMENA10 = TXZ_ENABLE;
break;
case PWM_4:
obj->p_t32a.p_instance = TSB_T32A5;
// Clock enable of T32A ch05
TSB_CG_FSYSMENA_IPMENA11 = TXZ_ENABLE;
break;
case PWM_5:
obj->p_t32a.p_instance = TSB_T32A6;
// Clock enable of T32A ch06
TSB_CG_FSYSMENA_IPMENA12 = TXZ_ENABLE;
break;
case PWM_6:
obj->p_t32a.p_instance = TSB_T32A7;
// Clock enable of T32A ch07
TSB_CG_FSYSMENA_IPMENA13 = TXZ_ENABLE;
break;
case PWM_7:
obj->p_t32a.p_instance = TSB_T32A8;
// Clock enable of T32A ch08
TSB_CG_FSYSMENA_IPMENA14 = TXZ_ENABLE;
break;
case PWM_8:
obj->p_t32a.p_instance = TSB_T32A9;
// Clock enable of T32A ch09
TSB_CG_FSYSMENA_IPMENA15 = TXZ_ENABLE;
break;
case PWM_9:
obj->p_t32a.p_instance = TSB_T32A10;
// Clock enable of T32A ch10
TSB_CG_FSYSMENA_IPMENA16 = TXZ_ENABLE;
break;
case PWM_10:
obj->p_t32a.p_instance = TSB_T32A11;
// Clock enable of T32A ch11
TSB_CG_FSYSMENA_IPMENA17 = TXZ_ENABLE;
break;
case PWM_11:
obj->p_t32a.p_instance = TSB_T32A12;
// Clock enable of T32A ch12
TSB_CG_FSYSMENA_IPMENA18 = TXZ_ENABLE;
break;
case PWM_12:
obj->p_t32a.p_instance = TSB_T32A13;
// Clock enable of T32A ch13
TSB_CG_FSYSMENA_IPMENA19 = TXZ_ENABLE;
break;
default:
obj->p_t32a.p_instance = NULL;
break;
}
if (obj->p_t32a.p_instance == NULL) {
return;
}
// Enable clock for GPIO port.
TSB_CG->FSYSMENB |= (TXZ_ENABLE << ((PIN_PORT(pin)) + GPIO_CLK_OFFSET));
// Set pin function as PWM
pinmap_pinout(pin, PinMap_PWM);
// Default to 20ms, 0% duty cycle
pwmout_period_ms(obj, 20);
}
void pwmout_free(pwmout_t *obj)
{
// Stop PWM
obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
obj->trailing_timing = TXZ_DISABLE;
obj->leading_timing = TXZ_DISABLE;
obj->p_t32a.p_instance = NULL;
}
void pwmout_write(pwmout_t *obj, float value)
{
// Stop PWM
obj->p_t32a.p_instance->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP);
if (value <= 0.0f) {
value = TXZ_DISABLE;
} else if (value >= 1.0f) {
value = TXZ_ENABLE;
}
// Store the new leading_timing value
obj->leading_timing = obj->trailing_timing - (obj->trailing_timing * value);
// Setting T32A_RGA0 register
obj->p_t32a.p_instance->RGC0 = obj->leading_timing;
// Start PWM
obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
}
float pwmout_read(pwmout_t *obj)
{
float duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing);
return duty_cycle;
}
void pwmout_period(pwmout_t *obj, float seconds)
{
pwmout_period_us(obj, (int)(seconds * 1000000.0f));
}
void pwmout_period_ms(pwmout_t *obj, int ms)
{
pwmout_period_us(obj, (ms * 1000));
}
// Set the PWM period, keeping the duty cycle the same.
void pwmout_period_us(pwmout_t *obj, int us)
{
uint32_t prscl = 0;
float duty_cycle = 0;
float seconds = (float)((us) / 1000000.0f);
obj->period = seconds;
// Restore the duty-cycle
duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing);
prscl = T32A_PRSCLx_32;
obj->trailing_timing = (us * CALCULATE_RGC1_VAL);
obj->leading_timing = ((obj->trailing_timing) - (obj->trailing_timing * duty_cycle));
obj->p_t32a.p_instance->MOD = T32A_MODE_32;
obj->p_t32a.p_instance->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP);
obj->p_t32a.p_instance->CRC = (prscl | T32A_RELOAD_TREGx);
obj->p_t32a.p_instance->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ |
T32A_IMx1_MASK_REQ | T32A_IMx0_MASK_REQ);
obj->p_t32a.p_instance->RGC0 = obj->leading_timing;
obj->p_t32a.p_instance->RGC1 = obj->trailing_timing;
obj->p_t32a.p_instance->OUTCRC0 = T32A_OCR_DISABLE;
obj->p_t32a.p_instance->OUTCRC1 = (T32A_OCRCMPx1_CLR | T32A_OCRCMPx0_SET);
obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
}
int pwmout_read_period_us(pwmout_t *obj)
{
return obj->trailing_timing;
}
void pwmout_pulsewidth(pwmout_t *obj, float seconds)
{
pwmout_pulsewidth_us(obj, (seconds * 1000000.0f));
}
void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
{
pwmout_pulsewidth_us(obj, (ms * 1000));
}
void pwmout_pulsewidth_us(pwmout_t *obj, int us)
{
float seconds = 0;
float value = 0;
seconds = (float)(us / 1000000.0f);
value = (((seconds / obj->period) * 100.0f) / 100.0f);
pwmout_write(obj, value);
}
int pwmout_read_pulsewidth_us(pwmout_t *obj)
{
return obj->trailing_timing - obj->leading_timing;
}
const PinMap *pwmout_pinmap()
{
return PinMap_PWM;
}

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "reset_reason_api.h"
#ifdef DEVICE_RESET_REASON
#include "TMPM4NR.h"
#include <stdbool.h>
static uint8_t set_bit_count(uint32_t reg);
typedef enum {
POWER_ON_BIT_POS = 1 << 0,
PIN_RESET_BIT_POS = 1 << 3,
LOW_POWER_BIT_POS = 1 << 4,
BROWN_OUT_BIT_POS = 1 << 5,
} reason_flag0;
typedef enum {
SOFTWARE_BIT_POS = 1 << 0,
LOCK_BIT_POS = 1 << 1,
WATCHDOG_BIT_POS = 1 << 2,
PLATFORM_BIT_POS = 1 << 3,
} reason_flag1;
void hal_reset_reason_clear(void)
{
TSB_RLM->RSTFLG0 = 0;
TSB_RLM->RSTFLG1 = 0;
}
uint32_t hal_reset_reason_get_raw(void)
{
uint32_t ret = 0;
ret = (((TSB_RLM->RSTFLG1 & 0xFF) << 8) | (TSB_RLM->RSTFLG0 & 0xFF));
return ret;
}
reset_reason_t hal_reset_reason_get(void)
{
reset_reason_t ret;
uint8_t NoOfSetBitCountReg1 = set_bit_count(TSB_RLM->RSTFLG0);
uint8_t NoOfSetBitCountReg2 = set_bit_count(TSB_RLM->RSTFLG1);
if (NoOfSetBitCountReg1 != 0x00) {
if (NoOfSetBitCountReg1 > 0x01) {
ret = RESET_REASON_MULTIPLE;
} else {
if (TSB_RLM->RSTFLG0 & POWER_ON_BIT_POS) {
ret = RESET_REASON_POWER_ON;
} else if (TSB_RLM->RSTFLG0 & PIN_RESET_BIT_POS) {
ret = RESET_REASON_PIN_RESET;
} else if (TSB_RLM->RSTFLG0 & LOW_POWER_BIT_POS) {
ret = RESET_REASON_WAKE_LOW_POWER;
} else if (TSB_RLM->RSTFLG0 & BROWN_OUT_BIT_POS) {
ret = RESET_REASON_BROWN_OUT;
} else {
ret = RESET_REASON_UNKNOWN;
}
}
} else if (NoOfSetBitCountReg2 != 0x00) {
if (NoOfSetBitCountReg2 > 0x01) {
ret = RESET_REASON_MULTIPLE;
} else {
if (TSB_RLM->RSTFLG1 & SOFTWARE_BIT_POS) {
ret = RESET_REASON_SOFTWARE;
} else if (TSB_RLM->RSTFLG1 & LOCK_BIT_POS) {
ret = RESET_REASON_LOCKUP;
} else if (TSB_RLM->RSTFLG1 & WATCHDOG_BIT_POS) {
ret = RESET_REASON_WATCHDOG;
} else if (TSB_RLM->RSTFLG1 & PLATFORM_BIT_POS) {
ret = RESET_REASON_PLATFORM;
} else {
ret = RESET_REASON_UNKNOWN;
}
}
} else {
ret = RESET_REASON_UNKNOWN;
}
return ret;
}
void hal_reset_reason_get_capabilities(reset_reason_capabilities_t *cap)
{
cap->reasons = 1 << RESET_REASON_UNKNOWN;
cap->reasons |= 1 << RESET_REASON_POWER_ON;
cap->reasons |= 1 << RESET_REASON_PIN_RESET;
cap->reasons |= 1 << RESET_REASON_WAKE_LOW_POWER;
cap->reasons |= 1 << RESET_REASON_BROWN_OUT;
cap->reasons |= 1 << RESET_REASON_SOFTWARE;
cap->reasons |= 1 << RESET_REASON_LOCKUP;
cap->reasons |= 1 << RESET_REASON_WATCHDOG;
cap->reasons |= 1 << RESET_REASON_PLATFORM;
cap->reasons |= 1 << RESET_REASON_MULTIPLE;
}
static uint8_t set_bit_count(uint32_t reg)
{
uint8_t count = 0;
uint8_t index = 0;
for (index = 0; index < (sizeof(uint32_t) * 8); index++) {
if (reg & (1 << index)) {
count++;
if (count > 0x01) {
break;
}
}
}
return count;
}
#endif // DEVICE_RESET_REASON

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "rtc_api.h"
#include "mbed_mktime.h"
#define RTC_24_HOUR_MODE ((uint8_t)0x01)
#define PAGER_PAGE_ONE ((uint8_t)0x01)
#define PAGER_PAGE_ZERO ((uint8_t)0xEE)
#define RTC_CLK_ENABLE ((uint8_t)0x08)
#define RTC_CLK_DISABLE ((uint8_t)0xE7)
#define RTCRESTR_RSTTMR_MASK ((uint8_t)0x20)
#define RTCRESTR_RSTTMR_R_RUN ((uint8_t)0x20)
#define CGWUPLCR_WUPTL_HIGH_MASK ((uint32_t)0x07FFF000)
#define CGWUPLCR_WULEF_MASK ((uint32_t)0x00000002)
#define CGWUPLCR_WULEF_R_DONE ((uint32_t)0x00000000)
#define CGWUPLCR_WULON_W_ENABLE ((uint32_t)0x00000001)
#define RLMLOSCCR_XTEN_RW_ENABLE ((uint32_t)0x00000001)
#define RLMLOSCCR_DRCOSCL_RW_ENABLE ((uint32_t)0x00000004)
#define ELOSC_CFG_WARM_UP_TIME ((uint64_t)(5000))
#define ELOSC_CFG_CLOCK ((uint64_t)(32768))
#define HEX2DEC(val) ((val >> 4U) * 10U + val % 16U) // Hex to Dec conversion macro
#define DEC2HEX(val) ((val / 10U) * 16U + val % 10U) // Dec to Hex conversion macro
static int rtc_inited = 0;
static int diff_year = 100; //our RTC register only support 2000~2099
static void external_losc_enable(void);
void rtc_init(void)
{
if (!rtc_inited) {
external_losc_enable(); // Enable low-speed oscillator
TSB_RTC->PAGER = 0x00; // Disable clock and alarm
while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) {
// Reset RTC sec counter
}
TSB_RTC->RESTR = 0xE7;
while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) {
// Reset RTC sec counter
}
TSB_RTC->PAGER |= PAGER_PAGE_ONE;
TSB_RTC->YEARR = 0x03; // Set leap year state
TSB_RTC->MONTHR = RTC_24_HOUR_MODE; // Set hour mode
TSB_RTC->PAGER &= PAGER_PAGE_ZERO; // Set hour mode
TSB_RTC->YEARR = 0x01; // Set year value
TSB_RTC->MONTHR = (uint8_t)0x01; // Set month value
TSB_RTC->DATER = (uint8_t)0x01; // Set date value
TSB_RTC->DAYR = (uint8_t)0x0; // Set day value
TSB_RTC->HOURR = (uint8_t)0x01; // Set hour value
TSB_RTC->MINR = (uint8_t)0x02; // Set minute value
TSB_RTC->SECR = (uint8_t)0x22; // Set second value
TSB_RTC->PAGER |= RTC_CLK_ENABLE; // Enable Clock
rtc_inited = 1; // Enable RTC initialzed status
}
}
void rtc_free(void)
{
rtc_inited = 0; // Set status of RTC peripheral driver as DISABLE
}
int rtc_isenabled(void)
{
return rtc_inited; // Return status of RTC peripheral driver
}
time_t rtc_read(void)
{
if (!rtc_inited) {
// Return invalid time for now!
return 0;
}
struct tm timeinfo;
uint8_t read_1 = 0U;
uint8_t read_2 = 0U;
timeinfo.tm_isdst = 0; //no summer time
TSB_RTC->PAGER &= PAGER_PAGE_ZERO;
read_1 = TSB_RTC->SECR; // Get sec value
timeinfo.tm_sec = HEX2DEC(read_1);
// Get minute value
do {
read_1 = TSB_RTC->MINR;
read_2 = TSB_RTC->MINR;
} while (read_1 != read_2);
timeinfo.tm_min = HEX2DEC(read_1);
// Get hour value
do {
read_1 = TSB_RTC->HOURR;
read_2 = TSB_RTC->HOURR;
} while (read_1 != read_2);
timeinfo.tm_hour = HEX2DEC(read_1);
// Get Month date value
do {
read_1 = TSB_RTC->DATER;
read_2 = TSB_RTC->DATER;
} while (read_1 != read_2);
timeinfo.tm_mday = HEX2DEC(read_1);
// Get Month value
do {
read_1 = TSB_RTC->MONTHR;
read_2 = TSB_RTC->MONTHR;
} while (read_1 != read_2);
timeinfo.tm_mon = HEX2DEC(read_1) - 1;
// Get weekday value
do {
read_1 = TSB_RTC->DAYR;
read_2 = TSB_RTC->DAYR;
} while (read_1 != read_2);
timeinfo.tm_wday = HEX2DEC(read_1);
// Get year value
do {
read_1 = TSB_RTC->YEARR;
read_2 = TSB_RTC->YEARR;
} while (read_1 != read_2);
timeinfo.tm_year = (HEX2DEC(read_1) + diff_year);
time_t t;
if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
return 0;
}
return t;
}
void rtc_write(time_t t)
{
if (!rtc_inited) {
// Initialize the RTC as not yet initialized
rtc_init();
}
struct tm timeinfo;
if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
return;
}
diff_year = timeinfo.tm_year - (timeinfo.tm_year % 100);
TSB_RTC->PAGER &= RTC_CLK_DISABLE; // Disable clock
// Check current year is leap year or not
if (((timeinfo.tm_year % 4) == 0 && (timeinfo.tm_year % 100) != 0) ||
(timeinfo.tm_year % 400) == 0) {
TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is a leap year
TSB_RTC->YEARR = 0x00;
} else if ((timeinfo.tm_year % 4) == 1) {
TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is the year following a leap year
TSB_RTC->YEARR = 0x01;
} else if ((timeinfo.tm_year % 4) == 2) {
TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is two years after a leap year
TSB_RTC->YEARR = 0x02;
} else {
TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is three years after a leap year
TSB_RTC->YEARR = 0x03;
}
TSB_RTC->PAGER &= PAGER_PAGE_ZERO; // Select PAGE 0
TSB_RTC->YEARR = (uint8_t)DEC2HEX((timeinfo.tm_year - diff_year)); // Set year value
// Set month value, tm_mon=0 means Jan while 1 is Jan
TSB_RTC->MONTHR = (uint8_t)DEC2HEX((timeinfo.tm_mon + 1));
TSB_RTC->DATER = (uint8_t)DEC2HEX(timeinfo.tm_mday); // Set date value
TSB_RTC->DAYR = (uint8_t)(timeinfo.tm_wday); // Set week day value
TSB_RTC->HOURR = (uint8_t)DEC2HEX(timeinfo.tm_hour); // Set hour value
TSB_RTC->MINR = (uint8_t)DEC2HEX(timeinfo.tm_min); // Set minute value
TSB_RTC->SECR = (uint8_t)DEC2HEX(timeinfo.tm_sec); // Set second value
// Setting Wait
// When stop mode is selected, CaseA or CaseB is need.
// CaseA: Wait for RTC 1Hz interrupt.
// CaseB: Check the clock register setting.
{
uint8_t flag = 1;
time_t time_read = {0};
while (flag) {
time_read = rtc_read();
if (time_read == t) { // Wait for setting successfully
flag = 0;
}
}
}
TSB_RTC->PAGER |= RTC_CLK_ENABLE; // Enable Clock
}
static void external_losc_enable(void)
{
uint32_t work;
// [CGWUPLCR]<WUPTL> :Warm up time
//--------------------------------------
// "1"counter (s) = 1 / ELOSC
// "1"counter (us) = (10^6) / ELOSC
// "x"counter (us) = time
//--------------------------------------
// x : time = 1 : (10^6) / ELOSC
//--------------------------------------
{
uint64_t x = (uint64_t)((uint64_t)(ELOSC_CFG_WARM_UP_TIME) * (uint64_t)(ELOSC_CFG_CLOCK));
x = (uint64_t)(x / (uint64_t)(1000000));
if (x > (uint64_t)(0x7FFFF)) {
/* invalid value */
}
work = (uint32_t)x;
}
work &= (uint32_t)(0xFFFFFFF0);
work <<= 8;
TSB_CG->WUPLCR = work;
// [RLMLOSCCR]<XTEN> :LOSC Enable
TSB_RLM->LOSCCR = RLMLOSCCR_DRCOSCL_RW_ENABLE | RLMLOSCCR_XTEN_RW_ENABLE;
// [CGWUPLCR]<WULON> :Enable
work = (uint32_t)(TSB_CG->WUPLCR & CGWUPLCR_WUPTL_HIGH_MASK);
TSB_CG->WUPLCR = (uint32_t)(work | CGWUPLCR_WULON_W_ENABLE);
// [CGWUPLCR]<WULEF> :Read(wait for warm-up)
while ((TSB_CG->WUPLCR & CGWUPLCR_WULEF_MASK) != CGWUPLCR_WULEF_R_DONE) {
// no processing
}
}

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <string.h>
#include "mbed_error.h"
#include "serial_api.h"
#include "pinmap.h"
#define UART_NUM 8
#define UART_ENABLE_RX ((uint32_t)0x00000001)
#define UART_ENABLE_TX ((uint32_t)0x00000002)
#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002)
#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001)
#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080)
#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080)
#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002)
#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001)
#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100)
#define LCR_H_WLEN_MASK ((uint32_t)0xFFFFFF9F)
#define LCR_H_STP2_MASK ((uint32_t)0xFFFFFFF7)
#define LCR_H_PARITY_MASK ((uint32_t)0xFFFFFF79)
#define CR_FLOW_CTRL_MASK ((uint32_t)0x00000F07)
#define CR_MODE_MASK ((uint32_t)0x0000CC07)
#define FUARTxCR_UARTEN_ENABLE_CLEAR ((uint32_t)0xFFFFFF7E)
#define FUART_CTS_RTS_DISABLE_MASK ((uint32_t)0XFFFF3FFF)
#define BAUDRATE_DEFAULT (9600)
#define CLR_REGISTER (0x00)
#define IMSC_TXIM_RXIM_MASK ((uint32_t)0X000007C0)
#define IMSC_RXIM_CLEAR ((uint32_t)0X000007E0)
#define IMSC_TXIM_CLEAR ((uint32_t)0X000007D0)
static const PinMap PinMap_UART_TX[] = {
{PE3, SERIAL_0, PIN_DATA(7, 1)},
{PV5, SERIAL_1, PIN_DATA(7, 1)},
{PV1, SERIAL_2, PIN_DATA(6, 1)},
{PJ1, SERIAL_3, PIN_DATA(3, 1)},
{PJ4, SERIAL_4, PIN_DATA(5, 1)},
{PJ6, SERIAL_5, PIN_DATA(5, 1)},
{NC, NC, 0}
};
static const PinMap PinMap_UART_RX[] = {
{PE2, SERIAL_0, PIN_DATA(7, 0)},
{PV4, SERIAL_1, PIN_DATA(7, 0)},
{PV0, SERIAL_2, PIN_DATA(6, 0)},
{PJ0, SERIAL_3, PIN_DATA(3, 0)},
{PJ5, SERIAL_4, PIN_DATA(5, 0)},
{PJ7, SERIAL_5, PIN_DATA(5, 0)},
{NC, NC, 0}
};
static const PinMap PinMap_UART_RTS[] = {
{PE0, SERIAL_0, PIN_DATA(7, 1)},
{PV7, SERIAL_1, PIN_DATA(7, 1)},
{PV2, SERIAL_2, PIN_DATA(7, 1)},
{PJ2, SERIAL_3, PIN_DATA(3, 1)},
{NC, NC, 0}
};
static const PinMap PinMap_UART_CTS[] = {
{PE1, SERIAL_0, PIN_DATA(7, 0)},
{PV6, SERIAL_1, PIN_DATA(7, 0)},
{PV3, SERIAL_2, PIN_DATA(7, 0)},
{PJ3, SERIAL_3, PIN_DATA(3, 0)},
{NC, NC, 0}
};
static int serial_irq_ids[UART_NUM] = {0};
static uart_irq_handler irq_handler;
int stdio_uart_inited = 0;
serial_t stdio_uart;
static void uart_swreset(TSB_UART_TypeDef *UARTx);
static void fuart_init_config(serial_t *obj, FUART_InitTypeDef *InitStruct);
void serial_init(serial_t *obj, PinName tx, PinName rx)
{
int is_stdio_uart = 0;
obj->mode = 0;
cg_t paramCG;
paramCG.p_instance = TSB_CG;
uart_clock_t prescal = {0};
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT((int)uart_name != NC);
obj->is_using_fuart = 0;
obj->index = uart_name;
// Initialize UART instance
switch (uart_name) {
case SERIAL_0:
obj->UARTx = TSB_UART0;
// Enable clock for UART0 and Port E
TSB_CG_FSYSMENA_IPMENA23 = TXZ_ENABLE;
TSB_CG_FSYSMENB_IPMENB06 = TXZ_ENABLE;
break;
case SERIAL_1:
obj->UARTx = TSB_UART1;
// Enable clock for UART1 and Port V
TSB_CG_FSYSMENA_IPMENA24 = TXZ_ENABLE;
TSB_CG_FSYSMENB_IPMENB19 = TXZ_ENABLE;
break;
case SERIAL_2:
obj->UARTx = TSB_UART3;
// Enable clock for UART3 and Port V
TSB_CG_FSYSMENA_IPMENA26 = TXZ_ENABLE;
TSB_CG_FSYSMENB_IPMENB19 = TXZ_ENABLE;
break;
case SERIAL_3:
obj->UARTx = TSB_UART5;
// Enable clock for UART5 and Port J
TSB_CG_FSYSMENA_IPMENA28 = TXZ_ENABLE;
TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE;
break;
case SERIAL_4:
obj->FUARTx = TSB_FURT0;
//Enable clock for UART6 and Port J
TSB_CG_FSYSMENA_IPMENA01 = TXZ_ENABLE;
TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE;
obj->is_using_fuart = 1;
break;
case SERIAL_5:
obj->FUARTx = TSB_FURT1;
//Enable clock for UART7 and Port J
TSB_CG_FSYSMENA_IPMENA02 = TXZ_ENABLE;
TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE;
obj->is_using_fuart = 1;
break;
default:
break;
}
// Set alternate function
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
if (!(obj->is_using_fuart)) {
if (tx != NC && rx != NC) {
obj->mode = UART_ENABLE_RX | UART_ENABLE_TX;
} else {
if (tx != NC) {
obj->mode = UART_ENABLE_TX;
} else {
if (rx != NC) {
obj->mode = UART_ENABLE_RX;
}
}
}
//software reset
uart_swreset(obj->UARTx);
//mbed default configurations
obj->UARTx->CR0 |= (1U); // data lengh 8 bit No parity one stop bit
prescal.prsel = UART_PLESCALER_1;
uart_get_boudrate_setting(cg_get_mphyt0(&paramCG), &prescal, BAUDRATE_DEFAULT, &obj->boud_obj);
obj->UARTx->BRD |= ((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn));
obj->UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); // Clear FIFO
obj->UARTx->TRANS |= obj->mode; // Enable TX RX block.
obj->UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL | UART_TX_INT_ENABLE | UART_RX_INT_ENABLE);
} else {
if (tx != NC && rx != NC) {
obj->fuart_config.Mode = FUARTxCR_TXE_ENABLE | FUARTxCR_RXE_ENABLE;
} else if (tx != NC) {
obj->fuart_config.Mode = FUARTxCR_TXE_ENABLE;
} else if (rx != NC) {
obj->fuart_config.Mode = FUARTxCR_RXE_ENABLE;
}
obj->fuart_config.BaudRate = BAUDRATE_DEFAULT;
obj->fuart_config.DataBits = FUART_DATA_LENGTH_8;
obj->fuart_config.StopBits = FUART_STOP_BIT_1;
obj->fuart_config.Parity = FUART_PARITY_DISABLE;
obj->fuart_config.FlowCtrl = FUART_CTS_DISABLE | FUART_RTS_DISABLE;
fuart_get_boudrate_setting(cg_get_mphyt0(&paramCG), obj->fuart_config.BaudRate, &obj->boudrate);
fuart_init_config(obj, &obj->fuart_config);
//Enable FUART
obj->FUARTx->CR |= FUARTxCR_UARTEN_ENABLE;
}
is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0);
if (is_stdio_uart) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj)
{
if (!(obj->is_using_fuart)) {
obj->UARTx->TRANS = CLR_REGISTER;
obj->UARTx->CR0 = CLR_REGISTER;
obj->UARTx->CR1 = CLR_REGISTER;
obj->UARTx = CLR_REGISTER;
uart_swreset(obj->UARTx);
} else {
obj->FUARTx->CR = CLR_REGISTER;
obj->FUARTx->IMSC = CLR_REGISTER;
obj->FUARTx->ICR = CLR_REGISTER;
obj->FUARTx->LCR_H = CLR_REGISTER;
obj->FUARTx = CLR_REGISTER;
}
obj->index = (uint32_t)NC;
}
void serial_baud(serial_t *obj, int baudrate)
{
cg_t paramCG;
paramCG.p_instance = TSB_CG;
uart_clock_t prescal;
if (!(obj->is_using_fuart)) {
prescal.prsel = UART_PLESCALER_1;
uart_get_boudrate_setting(cg_get_mphyt0(&paramCG), &prescal, baudrate, &obj->boud_obj);
obj->UARTx->BRD = CLR_REGISTER; //clear BRD register
obj->UARTx->BRD |= ((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn));
} else {
obj->FUARTx->CR &= FUARTxCR_UARTEN_ENABLE_CLEAR;
obj->fuart_config.BaudRate = baudrate;
fuart_get_boudrate_setting(cg_get_mphyt0(&paramCG), obj->fuart_config.BaudRate, &obj->boudrate);
fuart_init_config(obj, &obj->fuart_config);
obj->FUARTx->CR |= FUARTxCR_UARTEN_ENABLE;
}
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
uint32_t parity_check = 0;
uint32_t data_length = 0;
uint32_t tmp = 0;
uint32_t sblen = 0;
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven));
if (!(obj->is_using_fuart)) {
MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits
parity_check = ((parity == ParityOdd) ? 1 : ((parity == ParityEven) ? 3 : 0));
data_length = (data_bits == 8 ? 1 : ((data_bits == 7) ? 0 : 2));
sblen = (stop_bits == 1) ? 0 : 1; // 0: 1 stop bits, 1: 2 stop bits
tmp = ((sblen << 4) | (parity_check << 2) | data_length);
obj->UARTx->CR0 = tmp;
} else {
MBED_ASSERT((data_bits > 6) && (data_bits < 9)); // 0: 5 data bits ... 2: 8 data bits
obj->FUARTx->CR &= FUARTxCR_UARTEN_ENABLE_CLEAR;
// Parity bit update
if (parity == ParityOdd) {
obj->fuart_config.Parity = FUART_PARITY_BIT_ODD | FUART_PARITY_ENABLE;
} else if (parity == ParityEven) {
obj->fuart_config.Parity = FUART_PARITY_BIT_EVEN | FUART_PARITY_ENABLE;
} else {
obj->fuart_config.Parity = FUART_PARITY_DISABLE;
}
// Stop bit update
obj->fuart_config.StopBits = (stop_bits == 1) ? FUART_STOP_BIT_1 : FUART_STOP_BIT_2;
// Data length update
obj->fuart_config.DataBits = (data_bits == 7) ? FUART_DATA_LENGTH_7 : FUART_DATA_LENGTH_8;
fuart_init_config(obj, &obj->fuart_config);
obj->FUARTx->CR |= FUARTxCR_UARTEN_ENABLE;
}
}
// INTERRUPT HANDLING
void INTUART0RX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_0], RxIrq);
}
void INTUART0TX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_0], TxIrq);
}
void INTUART1RX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_1], RxIrq);
}
void INTUART1TX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_1], TxIrq);
}
void INTUART3RX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_2], RxIrq);
}
void INTUART3TX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_2], TxIrq);
}
void INTUART5RX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_3], RxIrq);
}
void INTUART5TX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_3], TxIrq);
}
void INTFUART0_IRQHandler(void)
{
uint32_t int_status;
int_status = TSB_FURT0->MIS;
if (int_status & (1 << 4U)) {
TSB_FURT0->ICR = int_status & FUARTxMIS_RXMIS_MASK;
irq_handler(serial_irq_ids[SERIAL_4], RxIrq);
} else if (int_status & (1 << 5U)) {
TSB_FURT0->ICR = int_status & FUARTxMIS_TXMIS_MASK;
irq_handler(serial_irq_ids[SERIAL_4], TxIrq);
} else {
return;
}
}
void INTFUART1_IRQHandler(void)
{
uint32_t int_status;
int_status = TSB_FURT1->MIS;
if (int_status & (1 << 4U)) {
irq_handler(serial_irq_ids[SERIAL_5], RxIrq);
} else if (int_status & (1 << 5U)) {
irq_handler(serial_irq_ids[SERIAL_5], TxIrq);
} else {
return;
}
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
uint32_t tmp = 0U;
IRQn_Type irq_n = (IRQn_Type)0;
switch (obj->index) {
case SERIAL_0:
if (irq == RxIrq) {
irq_n = INTUART0RX_IRQn;
} else {
irq_n = INTUART0TX_IRQn;
}
break;
case SERIAL_1:
if (irq == RxIrq) {
irq_n = INTUART1RX_IRQn;
} else {
irq_n = INTUART1TX_IRQn;
}
break;
case SERIAL_2:
if (irq == RxIrq) {
irq_n = INTUART3RX_IRQn;
} else {
irq_n = INTUART3TX_IRQn;
}
break;
case SERIAL_3:
if (irq == RxIrq) {
irq_n = INTUART5RX_IRQn;
} else {
irq_n = INTUART5TX_IRQn;
}
break;
case SERIAL_4:
irq_n = INTFUART0_IRQn;
break;
case SERIAL_5:
irq_n = INTFUART1_IRQn;
break;
default:
break;
}
if (obj->is_using_fuart) {
// Set interrupt mask
if (enable) {
if (irq == RxIrq) {
obj->FUARTx->IMSC |= (1 << 4U);
} else {
obj->FUARTx->IMSC |= (1 << 5U);
}
} else {
if (irq == RxIrq) {
tmp = obj->FUARTx->IMSC;
tmp &= IMSC_RXIM_CLEAR; /* Disable Receive interrupt */
obj->FUARTx->IMSC = tmp;
} else {
tmp = obj->FUARTx->IMSC;
tmp &= IMSC_TXIM_CLEAR; /* Disable Transmit interrupt */
obj->FUARTx->IMSC = tmp;
}
}
}
NVIC_ClearPendingIRQ(irq_n);
if (enable) {
NVIC_EnableIRQ(irq_n);
} else {
if (!obj->is_using_fuart) {
NVIC_DisableIRQ(irq_n);
}
}
}
int serial_getc(serial_t *obj)
{
int data = 0;
while (!serial_readable(obj)) { // Wait until Rx buffer is full
// Do nothing
}
if (!(obj->is_using_fuart)) {
//Read Data Register
data = (obj->UARTx->DR & 0xFFU);
obj->UARTx->SR |= (1U << 6); // clear RXEND flag
} else {
data = (obj->FUARTx->DR & 0xFFU);
}
return data;
}
void serial_putc(serial_t *obj, int c)
{
while (!serial_writable(obj)) {
// Do nothing
}
// Write Data Register
if (!(obj->is_using_fuart)) {
obj->UARTx->DR = (c & 0xFF);
while ((obj->UARTx->SR & (1U << 14)) == 0) {
}
obj->UARTx->SR |= (1U << 14); // clear TXEND flag
} else {
obj->FUARTx->DR = (c & 0xFF);
}
}
int serial_readable(serial_t *obj)
{
int ret = 0;
if (!(obj->is_using_fuart)) {
if ((obj->UARTx->SR & 0x000F) != 0) {
ret = 1;
}
} else {
if (obj->FUARTx->FR & (1 << 6U)) {
ret = 1;
}
}
return ret;
}
int serial_writable(serial_t *obj)
{
int ret = 0;
if (!(obj->is_using_fuart)) {
if ((obj->UARTx->SR & 0x8000) == 0) {
ret = 1;
}
} else {
if (obj->FUARTx->FR & (1 << 7U)) {
ret = 1;
}
}
return ret;
}
void serial_clear(serial_t *obj)
{
uint32_t dummy;
if (!(obj->is_using_fuart)) {
obj->UARTx->FIFOCLR = 0x03;
} else {
{
dummy = obj->FUARTx->DR; //dummy read
(void)dummy;
}
}
}
void serial_pinout_tx(PinName tx)
{
pinmap_pinout(tx, PinMap_UART_TX);
}
// Set flow control
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
{
UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
UARTName uart_name = (UARTName)pinmap_merge(uart_cts, uart_rts);
if (!(obj->is_using_fuart)) {
if (type == FlowControlCTS) {
MBED_ASSERT(uart_cts != (UARTName) NC);
pinmap_pinout(txflow, PinMap_UART_CTS); // Enable the pin for CTS function
pin_mode(txflow, PullUp); // initial state of CTS preferably high
obj->UARTx->CR0 |= (1 << 10); // Enable CTS hardware control
} else if (type == FlowControlRTS) {
MBED_ASSERT(uart_rts != (UARTName) NC);
pinmap_pinout(rxflow, PinMap_UART_RTS); // Enable the pin for RTS function
obj->UARTx->CR0 |= (1 << 9); // Enable RTS hardware control
} else if (type == FlowControlRTSCTS) {
MBED_ASSERT(uart_name != (UARTName) NC);
obj->UARTx->CR0 |= (3 << 9); // Enable CTS and RTS hardware flow control
pinmap_pinout(txflow, PinMap_UART_CTS); // Enable the pin for CTS function
pinmap_pinout(rxflow, PinMap_UART_RTS); // Enable the pin for RTS function
pin_mode(txflow, PullUp);
} else {
obj->UARTx->CR0 &= (~(3 << 9)); // Disable CTS and RTS hardware flow control
}
} else {
obj->FUARTx->CR &= FUARTxCR_UARTEN_ENABLE_CLEAR; // Disable FUART
if (type == FlowControlCTS) {
MBED_ASSERT(uart_cts != (UARTName) NC);
obj->FUARTx->CR |= FUART_CTS_ENABLE; // Enable CTS hardware flow control
pinmap_pinout(txflow, PinMap_UART_CTS); // Enable the pin for CTS and RTS function
pin_mode(txflow, PullUp);
} else if (type == FlowControlRTS) {
MBED_ASSERT(uart_rts != (UARTName) NC);
obj->FUARTx->CR |= FUART_RTS_ENABLE; // Enable RTS hardware flow control
pinmap_pinout(rxflow, PinMap_UART_RTS); // Enable the pin for RTS function
} else if (type == FlowControlRTSCTS) {
MBED_ASSERT(uart_name != (UARTName) NC);
obj->FUARTx->CR |= (FUART_CTS_ENABLE | FUART_RTS_ENABLE); // Enable CTS and RTS hardware flow control
pinmap_pinout(txflow, PinMap_UART_CTS); // Enable the pin for CTS function
pinmap_pinout(rxflow, PinMap_UART_RTS); // Enable the pin for RTS function
pin_mode(txflow, PullUp);
} else {
obj->FUARTx->CR &= FUART_CTS_RTS_DISABLE_MASK; // Disable CTS and RTS hardware flow control
}
obj->FUARTx->CR |= FUARTxCR_UARTEN_ENABLE;
}
}
// Pause transmission
void serial_break_set(serial_t *obj)
{
if (!(obj->is_using_fuart)) {
obj->UARTx->TRANS |= 0x08;
} else {
obj->FUARTx->LCR_H |= FUARTxLCR_H_BRK_SEND;
}
}
// Switch to normal transmission
void serial_break_clear(serial_t *obj)
{
if (!(obj->is_using_fuart)) {
obj->UARTx->TRANS &= ~(0x08);
} else {
obj->FUARTx->LCR_H &= ~(FUARTxLCR_H_BRK_SEND);
}
}
static void uart_swreset(TSB_UART_TypeDef *UARTx)
{
while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) {
// No process
}
UARTx->SWRST = UARTxSWRST_SWRST_10;
UARTx->SWRST = UARTxSWRST_SWRST_01;
while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) {
// No process
}
}
static void fuart_init_config(serial_t *obj, FUART_InitTypeDef *InitStruct)
{
uint32_t tmp = 0U;
obj->FUARTx->BRD = obj->boudrate.brn;
obj->FUARTx->FBRD = obj->boudrate.brk;
tmp = obj->FUARTx->LCR_H;
tmp &= LCR_H_WLEN_MASK;
tmp |= InitStruct->DataBits;
tmp &= LCR_H_STP2_MASK;
tmp |= InitStruct->StopBits;
tmp &= LCR_H_PARITY_MASK;
tmp |= InitStruct->Parity;
obj->FUARTx->LCR_H = tmp; //Set DataBits, StopBits, Parity
tmp = obj->FUARTx->IMSC;
tmp &= IMSC_TXIM_RXIM_MASK;
tmp |= (FUART_TX_INT_ENABLE | FUART_RX_INT_ENABLE);
obj->FUARTx->IMSC = tmp;
tmp = obj->FUARTx->CR;
tmp &= CR_FLOW_CTRL_MASK;
tmp |= InitStruct->FlowCtrl;
tmp &= CR_MODE_MASK;
tmp |= InitStruct->Mode;
obj->FUARTx->CR = tmp;
}
const PinMap *serial_tx_pinmap()
{
return PinMap_UART_TX;
}
const PinMap *serial_rx_pinmap()
{
return PinMap_UART_RX;
}
const PinMap *serial_cts_pinmap()
{
return PinMap_UART_CTS;
}
const PinMap *serial_rts_pinmap()
{
return PinMap_UART_RTS;
}

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targets/TARGET_TOSHIBA/TARGET_TMPM4NR/sleep.c Normal file
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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "sleep_api.h"
// Number of warm-up cycle = (warming up time (s) / clock period (s)) - 16
#define CG_WUODR_INT_5MS ((uint16_t)0x0C34)
#define CG_STBY_MODE_IDLE 0x0
#define CG_STBY_MODE_STOP1 0x1
#define EXTERNEL_OSC_MASK 0xFFFFFFF1
#define SIWDT_DISABLE 0xB1
#define WUPT_LOWER_MASK 0x000F
#define WUPT_UPPER_MASK 0xFFF0
static void external_losc_enable(void);
void hal_sleep(void)
{
// Set low power consumption mode IDLE
TSB_CG->STBYCR = CG_STBY_MODE_IDLE;
// Enter idle mode
__DSB();
__WFI();
}
void hal_deepsleep(void)
{
uint32_t wupt_lower = 0;
uint32_t wupt_upper = 0;
uint32_t tmp = 0;
TSB_CG_FSYSMENB_IPMENB31 = TXZ_ENABLE;
TSB_SIWD0->EN = TXZ_DISABLE;
TSB_SIWD0->CR = SIWDT_DISABLE;
while ((TSB_FC->SR0 & TXZ_DONE) != TXZ_DONE) {
// Flash wait
}
while (TSB_CG_WUPHCR_WUEF) {
// Wait for end of Warming-up for IHOSC1
}
TSB_CG_WUPHCR_WUCLK = TXZ_DISABLE;
wupt_lower = ((CG_WUODR_INT_5MS & WUPT_LOWER_MASK) << 16U);
wupt_upper = ((CG_WUODR_INT_5MS & WUPT_UPPER_MASK) << 16U);
TSB_CG->WUPHCR |= (wupt_lower | wupt_upper);
TSB_CG->STBYCR = CG_STBY_MODE_STOP1;
TSB_CG_PLL0SEL_PLL0SEL = TXZ_DISABLE;
while (TSB_CG_PLL0SEL_PLL0ST) {
// Wait for PLL status of fsys until off state(fosc=0)
}
// Stop PLL of fsys
TSB_CG_PLL0SEL_PLL0ON = TXZ_DISABLE;
TSB_CG_OSCCR_IHOSC1EN = TXZ_ENABLE;
TSB_CG_OSCCR_OSCSEL = TXZ_DISABLE;
while (TSB_CG_OSCCR_OSCF) {
// Wait for fosc status until IHOSC1 = 0
}
tmp = TSB_CG->OSCCR;
tmp &= EXTERNEL_OSC_MASK;
TSB_CG->OSCCR = tmp;
// Enter stop1 mode
__DSB();
__WFI();
// Switch over from IHOSC to EHOSC
// After coming out off sleep mode, Restore the clock setting to EHOSC.
external_losc_enable();
}
static void external_losc_enable(void)
{
uint32_t wupt_lower = 0;
uint32_t wupt_upper = 0;
// Enable high-speed oscillator
TSB_CG->OSCCR |= (TXZ_ENABLE << 1);
// Select internal(fIHOSC) as warm-up clock
wupt_lower = ((CG_WUODR_INT_5MS & WUPT_LOWER_MASK) << 16U);
wupt_upper = ((CG_WUODR_INT_5MS & WUPT_UPPER_MASK) << 16U);
TSB_CG->WUPHCR |= (wupt_lower | wupt_upper);
// Start warm-up
TSB_CG->WUPHCR |= TXZ_ENABLE;
// Wait until EHOSC become stable
while ((TSB_CG->WUPHCR & 0x0002)) {
// Do nothing
}
// Set fosc source
TSB_CG->OSCCR |= (1 << 8);
// Wait for <OSCSEL> to become "1"
while (!((TSB_CG->OSCCR & 0x200) >> 9)) {
// Do nothing
}
// Stop IHOSC
TSB_CG->OSCCR &= ~TXZ_ENABLE;
}

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "spi_api.h"
#include "mbed_error.h"
#include "txz_tspi.h"
#include "pinmap.h"
#define TIMEOUT 5000
#define INITIAL_SPI_FREQ 1000000
#if DEVICE_SPI_ASYNCH
#define SPI_S(obj) (struct spi_s *) (&((obj)->spi))
#else
#define SPI_S(obj) (struct spi_s *) (obj)
#endif
#if DEVICE_SPI_ASYNCH
static void spi_irq_handler(spi_t *obj);
static void disable_irq(uint32_t irqn);
static void clear_irq(uint32_t irqn);
enum {
SPI_TRANSFER_STATE_IDLE = 0U,
SPI_TRANSFER_STATE_BUSY
} SPI_TransferState;
typedef struct {
IRQn_Type Tx;
IRQn_Type Rx;
IRQn_Type Error;
} spi_irq_t;
static const spi_irq_t SPI_CH0_IRQN_TBL[1] = {
{ INTT0RX_IRQn, INTT0TX_IRQn, INTT0ERR_IRQn }
};
static const spi_irq_t SPI_CH2_IRQN_TBL[1] = {
{ INTT2RX_IRQn, INTT2TX_IRQn, INTT2ERR_IRQn }
};
#endif
static const PinMap PinMap_SPI_SCLK[] = {
{PA1, SPI_0, PIN_DATA(7, 1)},
{PA6, SPI_1, PIN_DATA(7, 1)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_SLAVE_SCLK[] = {
{PA1, SPI_0, PIN_DATA(7, 0)},
{PA6, SPI_1, PIN_DATA(7, 0)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_MOSI[] = {
{PA3, SPI_0, PIN_DATA(7, 1)},
{PA4, SPI_1, PIN_DATA(7, 1)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{PA2, SPI_0, PIN_DATA(7, 0)},
{PA5, SPI_1, PIN_DATA(7, 0)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
{PA0, SPI_0, PIN_DATA(7, 2)},
{PA7, SPI_1, PIN_DATA(7, 2)},
{NC, NC, 0}
};
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
struct spi_s *obj_s = SPI_S(obj);
// Check pin parameters
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj_s->module = (SPIName)pinmap_merge(spi_data, spi_sclk);
obj_s->module = (SPIName)pinmap_merge(spi_data, spi_cntl);
MBED_ASSERT((int)obj_s->module != NC);
// Identify SPI module to use
switch ((int)obj_s->module) {
case SPI_0:
obj_s->p_obj.p_instance = TSB_TSPI0;
// Enable clock for particular Port and SPI
TSB_CG_FSYSENA_IPENA04 = TXZ_ENABLE;
TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE;
#if DEVICE_SPI_ASYNCH
obj_s->irqn = (uint32_t)&SPI_CH0_IRQN_TBL;
#endif
break;
case SPI_1:
obj_s->p_obj.p_instance = TSB_TSPI2;
// Enable clock for particular Port and SPI
TSB_CG_FSYSENA_IPENA06 = TXZ_ENABLE;
TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE;
#if DEVICE_SPI_ASYNCH
obj_s->irqn = (uint32_t)&SPI_CH2_IRQN_TBL;
#endif
break;
default:
obj_s->p_obj.p_instance = NULL;
obj_s->module = (SPIName)NC;
error("Cannot found SPI module corresponding with input pins.");
break;
}
// Pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
obj_s->Slave_SCK = sclk;
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
// Default configurations 8 bit, 1Mhz frequency
// Control 1 configurations
obj_s->p_obj.init.id = (uint32_t)obj_s->module;
obj_s->p_obj.init.cnt1.inf = TSPI_INF_DISABLE; // Infinite Transfer Control disabled
obj_s->p_obj.init.cnt1.trgen = TSPI_TRGEN_DISABLE; // Trigger disabled
obj_s->p_obj.init.cnt1.trxe = TSPI_TRXE_DISABLE; // Enable Communication
obj_s->p_obj.init.cnt1.tspims = TSPI_SPI_MODE; // SPI mode
obj_s->p_obj.init.cnt1.mstr = TSPI_MASTER_OPERATION; // master mode operation
obj_s->p_obj.init.cnt1.tmmd = TSPI_TWO_WAY; // Full-duplex mode (Transmit/receive)
obj_s->p_obj.init.cnt1.cssel = TSPI_TSPIxCS0_ENABLE; // Chip select of pin CS0 is valid
obj_s->p_obj.init.cnt1.fc = TSPI_TRANS_RANGE_CONTINUE;// transfer single frame at a time continuously
//Control 2 configurations
obj_s->p_obj.init.cnt2.tidle = TSPI_TIDLE_HI;
obj_s->p_obj.init.cnt2.txdemp = TSPI_TXDEMP_HI; // when slave underruns TxD fixed to low
obj_s->p_obj.init.cnt2.rxdly = TSPI_RXDLY_8CLK;
obj_s->p_obj.init.cnt2.til = TSPI_TX_FILL_LEVEL_0; // transmit FIFO Level
obj_s->p_obj.init.cnt2.ril = TSPI_RX_FILL_LEVEL_1; // receive FIFO Level
obj_s->p_obj.init.cnt2.inttxwe = TSPI_TX_INT_DISABLE;
obj_s->p_obj.init.cnt2.intrxwe = TSPI_RX_INT_DISABLE;
obj_s->p_obj.init.cnt2.inttxfe = TSPI_TX_FIFO_INT_DISABLE;
obj_s->p_obj.init.cnt2.intrxfe = TSPI_RX_FIFO_INT_DISABLE;
obj_s->p_obj.init.cnt2.interr = TSPI_ERR_INT_DISABLE;
obj_s->p_obj.init.cnt2.dmate = TSPI_TX_DMA_INT_DISABLE;
obj_s->p_obj.init.cnt2.dmare = TSPI_RX_DMA_INT_DISABLE;
//Control 3 configurations
obj_s->p_obj.init.cnt3.tfempclr = TSPI_TX_BUFF_CLR_DONE; // transmit buffer clear
obj_s->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // receive buffer clear
//baudrate settings - 1Mhz default
spi_frequency(obj, (int)INITIAL_SPI_FREQ);
//Format Control 0 settings
obj_s->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first
obj_s->p_obj.init.fmr0.fl = TSPI_DATA_LENGTH_8;
obj_s->p_obj.init.fmr0.fint = TSPI_INTERVAL_TIME_0;
//Special control on polarity of signal and generation timing
obj_s->p_obj.init.fmr0.cs3pol = TSPI_TSPIxCS3_NEGATIVE;
obj_s->p_obj.init.fmr0.cs2pol = TSPI_TSPIxCS2_NEGATIVE;
obj_s->p_obj.init.fmr0.cs1pol = TSPI_TSPIxCS1_NEGATIVE;
obj_s->p_obj.init.fmr0.cs0pol = TSPI_TSPIxCS0_NEGATIVE;
obj_s->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE;
obj_s->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW;
obj_s->p_obj.init.fmr0.csint = TSPI_MIN_IDLE_TIME_1;
obj_s->p_obj.init.fmr0.cssckdl = TSPI_SERIAL_CK_DELAY_1;
obj_s->p_obj.init.fmr0.sckcsdl = TSPI_NEGATE_1;
//Format Control 1 settings tspi_fmtr1_t
obj_s->p_obj.init.fmr1.vpe = TSPI_PARITY_DISABLE;
obj_s->p_obj.init.fmr1.vpm = TSPI_PARITY_BIT_ODD;
obj_s->p_obj.init.scr0.sect = TSPI_SECT_MODE_FRAME;
obj_s->bits = (uint8_t)TSPI_DATA_LENGTH_8;
//initialize SPI
tspi_init(&obj_s->p_obj);
}
void spi_free(spi_t *obj)
{
struct spi_s *obj_s = SPI_S(obj);
tspi_deinit(&obj_s->p_obj);
obj_s->module = (SPIName)NC;
}
void spi_format(spi_t *obj, int bits, int mode, int slave)
{
struct spi_s *obj_s = SPI_S(obj);
MBED_ASSERT((slave == 0U) || (slave == 1U)); // 0: master mode, 1: slave mode
MBED_ASSERT((bits >= 8) && (bits <= 32));
obj_s->bits = bits;
obj_s->p_obj.init.fmr0.fl = (bits << 24);
if ((mode >> 1) & 0x1) {
obj_s->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_HI;
} else {
obj_s->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW;
}
if (mode & 0x1) {
obj_s->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_2ND_EDGE;
} else {
obj_s->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE;
}
if (slave) {
pinmap_pinout(obj_s->Slave_SCK, PinMap_SPI_SLAVE_SCLK);
obj_s->p_obj.init.cnt1.mstr = TSPI_SLAVE_OPERATION; // Slave mode operation
}
tspi_init(&obj_s->p_obj);
}
void spi_frequency(spi_t *obj, int hz)
{
struct spi_s *obj_s = SPI_S(obj);
uint8_t brs = 0;
uint8_t brck = 0;
uint16_t prsck = 1;
uint64_t fscl = 0;
uint64_t tmp_fscl = 0;
uint64_t fx = 0;
uint64_t tmpvar = SystemCoreClock;
SystemCoreClockUpdate();
tmpvar = tmpvar / 2;
for (prsck = 1; prsck <= 512; prsck *= 2) {
fx = ((uint64_t)tmpvar / prsck);
for (brs = 1; brs <= 16; brs++) {
fscl = fx / brs;
if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) {
tmp_fscl = fscl;
obj_s->p_obj.init.brd.brck = (brck << 4);
if (brs == 16) {
obj_s->p_obj.init.brd.brs = 0;
} else {
obj_s->p_obj.init.brd.brs = brs;
}
}
}
brck ++;
}
tspi_init(&obj_s->p_obj);
}
int spi_master_write(spi_t *obj, int value)
{
struct spi_s *obj_s = SPI_S(obj);
uint8_t ret_value = 0;
tspi_transmit_t send_obj;
tspi_receive_t rec_obj;
// Transmit data
send_obj.tx8.p_data = (uint8_t *)&value;
send_obj.tx8.num = 1;
tspi_master_write(&obj_s->p_obj, &send_obj, TIMEOUT);
// Read received data
rec_obj.rx8.p_data = &ret_value;
rec_obj.rx8.num = 1;
tspi_master_read(&obj_s->p_obj, &rec_obj, TIMEOUT);
return ret_value;
}
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
char *rx_buffer, int rx_length, char write_fill)
{
int total = (tx_length > rx_length) ? tx_length : rx_length;
for (int i = 0; i < total; i++) {
char out = (i < tx_length) ? tx_buffer[i] : write_fill;
char in = spi_master_write(obj, out);
if (i < rx_length) {
rx_buffer[i] = in;
}
}
return total;
}
int spi_busy(spi_t *t_obj)
{
struct spi_s *obj = SPI_S(t_obj);
int ret = 1;
uint32_t status = 0;
tspi_get_status(&obj->p_obj, &status);
if ((status & (TSPI_TX_FLAG_ACTIVE | TSPI_RX_FLAG_ACTIVE)) == 0) {
ret = 0;
}
return ret;
}
int spi_slave_receive(spi_t *t_obj)
{
struct spi_s *obj = SPI_S(t_obj);
int ret = 1;
uint32_t status;
tspi_get_status(&obj->p_obj, &status);
if ((status & (TSPI_RX_REACH_FILL_LEVEL_MASK)) == 0) {
ret = 0;
}
return ret;
}
int spi_slave_read(spi_t *t_obj)
{
struct spi_s *obj = SPI_S(t_obj);
uint8_t ret_value = 0;
ret_value = obj->p_obj.p_instance->DR & 0xFF;
obj->p_obj.p_instance->SR |= TSPI_RX_DONE_CLR;
obj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
return ret_value;
}
void spi_slave_write(spi_t *t_obj, int value)
{
struct spi_s *obj = SPI_S(t_obj);
// Enable TSPI Transmission Control.
obj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE;
obj->p_obj.p_instance->DR = value & 0xFF;
}
uint8_t spi_get_module(spi_t *t_obj)
{
struct spi_s *obj = SPI_S(t_obj);
return (uint8_t)(obj->module);
}
const PinMap *spi_master_mosi_pinmap()
{
return PinMap_SPI_MOSI;
}
const PinMap *spi_master_miso_pinmap()
{
return PinMap_SPI_MISO;
}
const PinMap *spi_master_clk_pinmap()
{
return PinMap_SPI_SCLK;
}
const PinMap *spi_master_cs_pinmap()
{
return PinMap_SPI_SSEL;
}
const PinMap *spi_slave_mosi_pinmap()
{
return PinMap_SPI_MOSI;
}
const PinMap *spi_slave_miso_pinmap()
{
return PinMap_SPI_MISO;
}
const PinMap *spi_slave_clk_pinmap()
{
return PinMap_SPI_SLAVE_SCLK;
}
const PinMap *spi_slave_cs_pinmap()
{
return PinMap_SPI_SSEL;
}
#if DEVICE_SPI_ASYNCH
void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width,
uint32_t handler, uint32_t event, DMAUsage hint)
{
struct spi_s *spiobj = SPI_S(obj);
spi_irq_t *p_irqn = (spi_irq_t *)spiobj->irqn;
// check which use-case we have
bool use_tx = (tx != NULL && tx_length > 0);
bool use_rx = (rx != NULL && rx_length > 0);
// don't do anything, if the buffers aren't valid
if (!use_tx && !use_rx) {
return;
}
disable_irq(spiobj->irqn);
spiobj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR);
spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE);
clear_irq(spiobj->irqn);
obj->tx_buff.buffer = (void *) tx;
obj->tx_buff.length = tx_length;
obj->tx_buff.pos = 0;
obj->rx_buff.buffer = (void *)rx;
obj->rx_buff.length = rx_length;
obj->rx_buff.pos = 0;
spiobj->event = 0;
spiobj->state = SPI_TRANSFER_STATE_IDLE;
NVIC_SetVector(p_irqn->Error, (uint32_t)handler);
NVIC_SetVector(p_irqn->Tx, (uint32_t)handler);
NVIC_SetVector(p_irqn->Rx, (uint32_t)handler);
// Enable Error Interrupt, Receive complete interrupt and Transmit complete interrupt
spiobj->p_obj.p_instance->CR2 |= (TSPI_TX_INT_ENABLE | TSPI_RX_INT_ENABLE | TSPI_ERR_INT_ENABLE);
if (use_tx && use_rx) {
spiobj->max_size = tx_length < rx_length ? rx_length : tx_length;
spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE;
spiobj->p_obj.p_instance->DR = ((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF;
} else if (use_tx) {
spiobj->max_size = tx_length;
spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE;
spiobj->p_obj.p_instance->DR = ((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF;
// Enable Interrupt bit in SPI peripheral - Enabled in init()
} else if (use_rx) {
spiobj->max_size = rx_length;
spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE;
spiobj->p_obj.p_instance->DR = 0xFF;
}
spiobj->state = SPI_TRANSFER_STATE_BUSY;
NVIC_EnableIRQ(p_irqn->Error);
NVIC_EnableIRQ(p_irqn->Tx);
NVIC_EnableIRQ(p_irqn->Rx);
}
uint32_t spi_irq_handler_asynch(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
spi_irq_handler(obj);
return ((spiobj->event & SPI_EVENT_ALL) | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE) ;
}
uint8_t spi_active(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
uint8_t ret_val = 0;
if (spiobj->state != SPI_TRANSFER_STATE_IDLE) {
ret_val = 1;
}
return ret_val;
}
void spi_abort_asynch(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
disable_irq(spiobj->irqn);
clear_irq(spiobj->irqn);
tspi_init(&spiobj->p_obj);
}
static void spi_irq_handler(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
if ((spiobj->p_obj.p_instance->SR & TSPI_RX_DONE) &&
(spiobj->p_obj.p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK)) {
uint8_t rlvl = spiobj->p_obj.p_instance->SR & 0xF;
while ((rlvl != 0) && (obj->rx_buff.pos < obj->rx_buff.length)) {
((uint8_t *)obj->rx_buff.buffer)[obj->rx_buff.pos++] = spiobj->p_obj.p_instance->DR & 0xFF;
rlvl--;
// transmit complete but receive pending - dummy write
}
if (obj->rx_buff.pos == spiobj->max_size) {
spiobj->state = SPI_TRANSFER_STATE_IDLE;
}
spiobj->p_obj.p_instance->CR3 |= TSPI_RX_BUFF_CLR_DONE;
}
if (spiobj->p_obj.p_instance->SR & TSPI_TX_DONE) {
obj->tx_buff.pos++;
spiobj->p_obj.p_instance->SR |= TSPI_RX_DONE_CLR;
if (obj->tx_buff.pos == (spiobj->max_size)) {
spiobj->state = SPI_TRANSFER_STATE_IDLE;
}
if ((obj->tx_buff.pos < obj->tx_buff.length) && (obj->tx_buff.pos < spiobj->max_size)) {
spiobj->p_obj.p_instance->DR = (((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF);
} else if (obj->tx_buff.pos < spiobj->max_size) {
spiobj->p_obj.p_instance->DR = 0xFF;
}
}
if (spiobj->p_obj.p_instance->ERR) {
spiobj->event = SPI_EVENT_ERROR;
spiobj->state = SPI_TRANSFER_STATE_IDLE;
disable_irq(spiobj->irqn);
spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR);
spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE);
clear_irq(spiobj->irqn);
return;
}
if (spiobj->state == SPI_TRANSFER_STATE_IDLE) {
spiobj->event = SPI_EVENT_COMPLETE;
disable_irq(spiobj->irqn);
spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR);
spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE);
clear_irq(spiobj->irqn);
}
}
static void disable_irq(uint32_t irqn)
{
spi_irq_t *p_irqn = (spi_irq_t *)irqn;
NVIC_DisableIRQ(p_irqn->Tx);
NVIC_DisableIRQ(p_irqn->Rx);
NVIC_DisableIRQ(p_irqn->Error);
}
static void clear_irq(uint32_t irqn)
{
spi_irq_t *p_irqn = (spi_irq_t *)irqn;
NVIC_ClearPendingIRQ(p_irqn->Tx);
NVIC_ClearPendingIRQ(p_irqn->Rx);
NVIC_ClearPendingIRQ(p_irqn->Error);
//clean-up
}
#endif //DEVICE_SPI_ASYNCH

108
targets/TARGET_TOSHIBA/TARGET_TMPM4NR/us_ticker.c Normal file
View File

@ -0,0 +1,108 @@
/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "us_ticker_api.h"
#include "TMPM4NR.h"
#include "txz_t32a.h"
#define CLR_TIMER_INT_FLAG (uint8_t)0x41
static uint8_t us_ticker_inited = 0; // Is ticker initialized yet?
const ticker_info_t *us_ticker_get_info()
{
static const ticker_info_t info = {
3000000,
32
};
return &info;
}
// Initialize us_ticker
void us_ticker_init(void)
{
if (us_ticker_inited) {
us_ticker_disable_interrupt();
return;
}
us_ticker_inited = 1;
// Enable clock for T32A0
TSB_CG_FSYSMENA_IPMENA08 = TXZ_ENABLE;
// T32A ch0 TimerC Reg Match/Over Flow/Under Flow
TSB_IB->IMC026 = TXZ_ENABLE;
// Configure Timer T32A0
TSB_T32A2->MOD = T32A_MODE_32;
TSB_T32A2->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
TSB_T32A2->CRC = T32A_PRSCLx_32;
TSB_T32A2->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ);
TSB_T32A2->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
NVIC_SetVector(INTT32A02_A_CT_IRQn, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(INTT32A02_A_CT_IRQn);
}
uint32_t us_ticker_read(void)
{
uint32_t ret_val = 0;
if (!us_ticker_inited) {
us_ticker_init();
}
ret_val = (TSB_T32A2->TMRC);
return ret_val;
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
NVIC_DisableIRQ(INTT32A02_A_CT_IRQn);
TSB_T32A2->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
TSB_T32A2->RGC1 = timestamp ;
NVIC_EnableIRQ(INTT32A02_A_CT_IRQn);
TSB_T32A2->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
}
void us_ticker_fire_interrupt(void)
{
NVIC_SetPendingIRQ(INTT32A02_A_CT_IRQn);
NVIC_EnableIRQ(INTT32A02_A_CT_IRQn);
}
void us_ticker_disable_interrupt(void)
{
// Disable interrupts in NVIC
TSB_IB->IMC026 = CLR_TIMER_INT_FLAG;
NVIC_ClearPendingIRQ(INTT32A02_A_CT_IRQn);
NVIC_DisableIRQ(INTT32A02_A_CT_IRQn);
}
void us_ticker_clear_interrupt(void)
{
TSB_IB->IMC026 = CLR_TIMER_INT_FLAG;
NVIC_ClearPendingIRQ(INTT32A02_A_CT_IRQn);
}
void us_ticker_free(void)
{
TSB_T32A2->RUNC = T32A_RUN_DISABLE;
TSB_IB->IMC026 = CLR_TIMER_INT_FLAG;
NVIC_ClearPendingIRQ(INTT32A02_A_CT_IRQn);
NVIC_DisableIRQ(INTT32A02_A_CT_IRQn);
TSB_CG_FSYSMENA_IPMENA08 = TXZ_DISABLE;
}

8
targets/TARGET_TOSHIBA/mbed_rtx.h
View File

@ -44,4 +44,12 @@
#endif
#if defined(TARGET_TMPM4NR)
#ifndef INITIAL_SP
#define INITIAL_SP (0x20040000UL)
#endif
#endif
#endif // MBED_MBED_RTX_H

62
targets/targets.json
View File

@ -9176,5 +9176,65 @@
"std"
]
}
}
},
"TMPM4NR": {
"inherits": [
"Target"
],
"core": "Cortex-M4F",
"is_disk_virtual": true,
"extra_labels": [
"TOSHIBA"
],
"macros": [
"TMPM4NR"
],
"supported_toolchains": [
"GCC_ARM",
"ARM"
],
"device_has": [
"ANALOGIN",
"ANALOGOUT",
"INTERRUPTIN",
"PORTIN",
"PORTINOUT",
"PORTOUT",
"PWMOUT",
"RESET_REASON",
"SERIAL",
"SERIAL_FC",
"SPI",
"SPISLAVE",
"SPI_ASYNCH",
"I2C",
"I2CSLAVE",
"I2C_ASYNCH",
"RTC",
"STDIO_MESSAGES",
"FLASH",
"SLEEP",
"USTICKER",
"MPU"
],
"device_name": "TMPM4NRF20FG",
"detect_code": [
"7022"
],
"release_versions": [
"5"
],
"bootloader_supported": true,
"supported_c_libs": {
"arm": [
"std",
"small"
],
"gcc_arm": [
"std",
"small"
]
}
}
}

90
tools/arm_pack_manager/index.json
View File

@ -504412,14 +504412,98 @@
},
"sectors": [
[
0,
32768
0,
4096
],
[
805306368,
4096
]
],
],
"vendor": "Toshiba:92",
"family": "TXZ4A+ Series",
"sub_family": "M4K(2)"
},
"TMPM4NRF20FG": {
"name": "TMPM4NRF20FG",
"memories": {
"IROM1": {
"access": {
"read": true,
"write": false,
"execute": true,
"peripheral": false,
"secure": false,
"non_secure": false,
"non_secure_callable": false
},
"start": 0,
"size": 2097152,
"startup": true,
"default": true
},
"IRAM1": {
"access": {
"read": true,
"write": true,
"execute": false,
"peripheral": false,
"secure": false,
"non_secure": false,
"non_secure_callable": false
},
"start": 536870912,
"size": 262144,
"startup": false,
"default": true
}
},
"algorithms": [
{
"file_name": "Flash/TMPM4Nx_code_2048.FLM",
"start": 0,
"size": 2097152,
"default": true,
"ram_start": 536870912,
"ram_size": 8192
},
{
"file_name": "Flash/TMPM4Nx_data_32.FLM",
"start": 805306368,
"size": 32768,
"default": true,
"ram_start": 536870912,
"ram_size": 8192
}
],
"processor": {
"Symmetric": {
"units": 1,
"core": "CortexM4",
"fpu": "SinglePrecision",
"mpu": "Present"
}
},
"from_pack": {
"vendor": "Toshiba",
"pack": "TXZ4Aplus-M4N1_DFP",
"version": "1.0.1",
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{