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Merge pull request #14359 from harmut01/baremetal_nxp 

Add bare metal support to NXP targets
pull/14540/head
Martin Kojtal 2021-04-13 10:58:46 +02:00 committed by GitHub
parent 38796d0a88 9c73e09b06
commit 291beda749
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 44 additions and 347 deletions
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52
targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11XX/LPC1114.sct
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@ -1,52 +0,0 @@
#! armcc -E
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
; 32K flash
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x8000
#endif
; 4KB
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x10000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x00001000
#endif
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
# else
# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
# endif
#endif
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
#define VECTOR_SIZE 0xC0
#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE+VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; stack
}
}

287
targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11XX/startup_LPC11xx.S
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@ -1,287 +0,0 @@
;/*****************************************************************************
; * @file: startup_LPC11xx.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File
; * for the NXP LPC11xx Device Series
; * @version: V1.0
; * @date: 25. Nov. 2008
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2008 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
DCD SLWU_INT0_IRQHandler ; Start logic wake-up interrupt 0
DCD SLWU_INT1_IRQHandler ; Start logic wake-up interrupt 1
DCD SLWU_INT2_IRQHandler ; Start logic wake-up interrupt 2
DCD SLWU_INT3_IRQHandler ; Start logic wake-up interrupt 3
DCD SLWU_INT4_IRQHandler ; Start logic wake-up interrupt 4
DCD SLWU_INT5_IRQHandler ; Start logic wake-up interrupt 5
DCD SLWU_INT6_IRQHandler ; Start logic wake-up interrupt 6
DCD SLWU_INT7_IRQHandler ; Start logic wake-up interrupt 7
DCD SLWU_INT8_IRQHandler ; Start logic wake-up interrupt 8
DCD SLWU_INT9_IRQHandler ; Start logic wake-up interrupt 9
DCD SLWU_INT10_IRQHandler ; Start logic wake-up interrupt 10
DCD SLWU_INT11_IRQHandler ; Start logic wake-up interrupt 11
DCD SLWU_INT12_IRQHandler ; Start logic wake-up interrupt 12
DCD C_CAN_IRQHandler ; C_CAN
DCD SSP1_IRQHandler ; SSP1
DCD I2C_IRQHandler ; I2C
DCD TIMER16_0_IRQHandler ; 16-bit Timer0
DCD TIMER16_1_IRQHandler ; 16-bit Timer1
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
DCD TIMER32_1_IRQHandler ; 32-bit Timer1
DCD SSP0_IRQHandler ; SSP0
DCD UART_IRQHandler ; UART
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler ; Reserved
DCD ADC_IRQHandler ; A/D Converter
DCD WDT_IRQHandler ; Watchdog timer
DCD BOD_IRQHandler ; Brown Out Detect
DCD Reserved_IRQHandler ; Reserved
DCD PIO_3_IRQHandler ; GPIO interrupt status of port 3
DCD PIO_2_IRQHandler ; GPIO interrupt status of port 2
DCD PIO_1_IRQHandler ; GPIO interrupt status of port 1
DCD PIO_0_IRQHandler ; GPIO interrupt status of port 0
;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
; for particular peripheral.
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Reserved_IRQHandler PROC
EXPORT Reserved_IRQHandler [WEAK]
B .
ENDP
Default_Handler PROC
; for LPC1114
EXPORT NMI_Handler [WEAK]
EXPORT SLWU_INT0_IRQHandler [WEAK]
EXPORT SLWU_INT1_IRQHandler [WEAK]
EXPORT SLWU_INT2_IRQHandler [WEAK]
EXPORT SLWU_INT3_IRQHandler [WEAK]
EXPORT SLWU_INT4_IRQHandler [WEAK]
EXPORT SLWU_INT5_IRQHandler [WEAK]
EXPORT SLWU_INT6_IRQHandler [WEAK]
EXPORT SLWU_INT7_IRQHandler [WEAK]
EXPORT SLWU_INT8_IRQHandler [WEAK]
EXPORT SLWU_INT9_IRQHandler [WEAK]
EXPORT SLWU_INT10_IRQHandler [WEAK]
EXPORT SLWU_INT11_IRQHandler [WEAK]
EXPORT SLWU_INT12_IRQHandler [WEAK]
EXPORT C_CAN_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT TIMER16_0_IRQHandler [WEAK]
EXPORT TIMER16_1_IRQHandler [WEAK]
EXPORT TIMER32_0_IRQHandler [WEAK]
EXPORT TIMER32_1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT UART_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT PIO_3_IRQHandler [WEAK]
EXPORT PIO_2_IRQHandler [WEAK]
EXPORT PIO_1_IRQHandler [WEAK]
EXPORT PIO_0_IRQHandler [WEAK]
NMI_Handler
SLWU_INT0_IRQHandler
SLWU_INT1_IRQHandler
SLWU_INT2_IRQHandler
SLWU_INT3_IRQHandler
SLWU_INT4_IRQHandler
SLWU_INT5_IRQHandler
SLWU_INT6_IRQHandler
SLWU_INT7_IRQHandler
SLWU_INT8_IRQHandler
SLWU_INT9_IRQHandler
SLWU_INT10_IRQHandler
SLWU_INT11_IRQHandler
SLWU_INT12_IRQHandler
C_CAN_IRQHandler
SSP1_IRQHandler
I2C_IRQHandler
TIMER16_0_IRQHandler
TIMER16_1_IRQHandler
TIMER32_0_IRQHandler
TIMER32_1_IRQHandler
SSP0_IRQHandler
UART_IRQHandler
ADC_IRQHandler
WDT_IRQHandler
BOD_IRQHandler
PIO_3_IRQHandler
PIO_2_IRQHandler
PIO_1_IRQHandler
PIO_0_IRQHandler
B .
ENDP
ALIGN
END

2
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/TOOLCHAIN_ARM_STD/LPC54114J256_cm4.sct
View File

@ -121,6 +121,8 @@ LR_IROM1 m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load
}
RW_IRAM1 ((ImageLimit(RW_m_data) == m_data_start) ? ImageLimit(RW_m_data) : +0) EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY Heap_Size{ ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}

2
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/TOOLCHAIN_ARM_STD/LPC54628J512.sct
View File

@ -109,6 +109,8 @@ LR_IROM1 m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load
}
RW_IRAM1 +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY Heap_Size{ ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
}

48
targets/targets.json
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@ -295,9 +295,7 @@
],
"supported_toolchains": [
"ARM",
"uARM",
"GCC_ARM",
"IAR"
"GCC_ARM"
],
"detect_code": [
"1010"
@ -345,7 +343,18 @@
},
"overrides": {
"network-default-interface-type": "ETHERNET"
}
},
"supported_c_libs": {
"arm": [
"std", "small"
],
"gcc_arm": [
"std", "small"
]
},
"supported_application_profiles": [
"full", "bare-metal"
]
},
"ARCH_PRO": {
"supported_form_factors": [
@ -356,6 +365,9 @@
"ARM",
"GCC_ARM",
"IAR"
],
"supported_application_profiles": [
"full", "bare-metal"
],
"supported_c_libs": {
"arm": [
@ -4365,7 +4377,6 @@
"core": "Cortex-M4F",
"supported_toolchains": [
"ARM",
"IAR",
"GCC_ARM"
],
"extra_labels": [
@ -4415,13 +4426,23 @@
"post_binary_hook": {
"function": "LPCTargetCode.lpc_patch"
},
"device_name": "LPC54114J256BD64"
"device_name": "LPC54114J256BD64",
"supported_c_libs": {
"arm": [
"std", "small"
],
"gcc_arm": [
"std", "small"
]
},
"supported_application_profiles": [
"full", "bare-metal"
]
},
"MCU_LPC546XX": {
"core": "Cortex-M4F",
"supported_toolchains": [
"ARM",
"IAR",
"GCC_ARM"
],
"extra_labels": [
@ -4469,7 +4490,18 @@
"device_name": "LPC54628J512ET180",
"post_binary_hook": {
"function": "LPCTargetCode.lpc_patch"
}
},
"supported_c_libs": {
"arm": [
"std", "small"
],
"gcc_arm": [
"std", "small"
]
},
"supported_application_profiles": [
"full", "bare-metal"
]
},
"LPC546XX": {
"supported_form_factors": [