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Deleted uncommented code. 

Deleted checking interrupt status code.
pull/1229/head
hjjeon0608 2015-07-14 08:27:31 +09:00
parent cf868024b2
commit 28c307665f
1 changed files with 2 additions and 44 deletions
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42
libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c
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@ -54,28 +54,8 @@ void DUALTIMER0_Handler(void)
DUALTIMER_IntClear(DUALTIMER0_0); DUALTIMER_IntClear(DUALTIMER0_0);
us_ticker_irq_handler(); us_ticker_irq_handler();
} }
if(DUALTIMER_GetIntStatus(DUALTIMER0_1))
{
DUALTIMER_IntClear(DUALTIMER0_1);
}
} }
//void PWM2_Handler(void)
//{
// uint32_t IntFlag = 0;
// IntFlag = PWM_CHn_GetIntFlagStatus(PWM_CH2);
// /* If overflow interrupt is occurred */
// if( (IntFlag & PWM_CHn_IER_OI_Msk) != 0 )
// {
// /* Clear overflow interrupt */
// PWM_CH2_ClearOverflowInt();
// us_ticker_irq_handler();
// }
//}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
@ -139,22 +119,6 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
DUALTIMER_Start(TIMER_0); DUALTIMER_Start(TIMER_0);
// PWM_CHn_Stop(PWM_CH2);
// SystemCoreClockUpdate();
// TimMasterHandle_CH2.PWM_CHn_PR = (GetSystemClock() / 1000000) -1;
// TimMasterHandle_CH2.PWM_CHn_LR = dev;
// TimMasterHandle_CH2.PWM_CHn_UDMR = 0;
// TimMasterHandle_CH2.PWM_CHn_PDMR = 0;
// NVIC_EnableIRQ(PWM2_IRQn);
// PWM_CHn_IntConfig(PWM_CH2, PWM_CHn_IER_OIE, ENABLE);
// PWM_IntConfig(PWM_CH2, ENABLE);
// PWM_TimerModeInit(PWM_CH2, &TimMasterHandle_CH2);
// PWM_CHn_Start(PWM_CH2);
} }
void us_ticker_disable_interrupt(void) void us_ticker_disable_interrupt(void)
@ -162,15 +126,9 @@ void us_ticker_disable_interrupt(void)
NVIC_DisableIRQ(TIMER_IRQn); NVIC_DisableIRQ(TIMER_IRQn);
DUALTIMER_IntConfig(TIMER_0, DISABLE); DUALTIMER_IntConfig(TIMER_0, DISABLE);
//NVIC_DisableIRQ(PWM2_IRQn);
// PWM_CHn_IntConfig(PWM_CH2, PWM_CHn_IER_OIE, DISABLE);
// PWM_IntConfig(PWM_CH2, DISABLE);
} }
void us_ticker_clear_interrupt(void) void us_ticker_clear_interrupt(void)
{ {
DUALTIMER_IntClear(TIMER_0); DUALTIMER_IntClear(TIMER_0);
//PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_IER_OIE);
} }