diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct
index 542ebce868..b2d1ee2e36 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct
@@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cyb06xx7_cm4_dual.sct
-;* \version 2.50
+;* \version 2.60
;*
;* Linker file for the ARMCC.
;*
@@ -78,6 +78,7 @@
#define MBED_BOOT_STACK_SIZE 0x400
#endif
+; Size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target.
@@ -133,12 +134,9 @@
#define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000
-; Size and start address of the Cortex-M4 application image
-#define FLASH_CM4_SIZE FLASH_SIZE
-#define FLASH_CM4_START FLASH_START
-; Cortex-M4 application image
-LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
{
ER_FLASH_VECTORS +0
{
@@ -159,7 +157,7 @@ LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
RW_RAM_DATA +0
{
* (.cy_ramfunc)
- .ANY (+RW, +ZI)
+ * (+RW, +ZI)
}
; Place variables in the section that should not be initialized during the
@@ -275,7 +273,7 @@ CYMETA 0x90500000
/* The following symbols used by the cymcuelftool. */
/* Flash */
#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00100000
+#define __cy_memory_0_length 0x000D0000
#define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld
index ebb6f76525..0a81d0b541 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld
@@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cyb06xx7_cm4_dual.ld
-* \version 2.50
+* \version 2.60
*
* Linker file for the GNU C compiler.
*
@@ -76,6 +76,7 @@ ENTRY(Reset_Handler)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
+/* Size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
@@ -118,10 +119,6 @@ MEMORY
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
}
-/* Size and start address of the Cortex-M4 application image */
-FLASH_CM4_SIZE = LENGTH(flash);
-FLASH_CM4_START = ORIGIN(flash);
-
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
@@ -161,8 +158,8 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS
{
- /* Cortex-M4 application image */
- .text FLASH_CM4_START :
+ /* Cortex-M4 application flash area */
+ .text ORIGIN(flash) :
{
. = ALIGN(4);
__Vectors = . ;
@@ -278,7 +275,6 @@ SECTIONS
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
-
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
@@ -339,7 +335,7 @@ SECTIONS
__HeapLimit = .;
} > ram
-
+
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
@@ -392,7 +388,7 @@ SECTIONS
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
-
+
/* Supervisory Flash: Table of Content # 2 Copy */
.cy_rtoc_part2 :
{
@@ -426,7 +422,7 @@ SECTIONS
/* The following symbols used by the cymcuelftool. */
/* Flash */
__cy_memory_0_start = 0x10000000;
-__cy_memory_0_length = 0x00100000;
+__cy_memory_0_length = 0x000D0000;
__cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf
index 67556454eb..f6322dc7bc 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf
@@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cyb06xx7_cm4_dual.icf
-* \version 2.50
+* \version 2.60
*
* Linker file for the IAR compiler.
*
@@ -156,7 +156,7 @@ if (!isdefinedsymbol(__STACK_SIZE)) {
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
- define symbol __ICFEDIT_size_heap__ = 0x400;
+ define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
@@ -191,8 +191,10 @@ do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
-/* Flash - Cortex-M4 application image */
-place in IROM1_region { block RO };
+/* Flash - Cortex-M4 application */
+place at start of IROM1_region { block RO };
+
+/* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */
@@ -245,7 +247,7 @@ keep { section .cy_app_signature,
/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
-define exported symbol __cy_memory_0_length = 0x00100000;
+define exported symbol __cy_memory_0_length = 0x000D0000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S
index 75747c4fac..f4ca47b457 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S
@@ -310,10 +310,6 @@ intvec_copy
STR r0, [r1]
dsb
- ; Enable the FPU if used
- LDR R0, =Cy_SystemInitFpuEnable
- BLX R0
-
; Initialize data sections
LDR R0, =__iar_data_init3
BLX R0
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h
index 53bc71262c..423361f58a 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h
@@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
-* \version 2.50
+* \version 2.60
*
* \brief Device system header file.
*
@@ -320,6 +320,11 @@
* | Reason for Change |
*
*
+* | 2.60 |
+* Updated linker scripts. |
+* Provided support for new devices, updated usage of CM0p prebuilt image. |
+*
+*
* | 2.50 |
* Updated assembler files, C files, linker scripts. |
* Dynamic allocated HEAP size for Arm Compiler 6, IAR 8. |
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6_cm4.c
index a5408385ee..0a18f50a4d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6_cm4.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6_cm4.c
@@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
-* \version 2.50
+* \version 2.60
*
* The device system-source file.
*