mirror of https://github.com/ARMmbed/mbed-os.git
Merge branch 'master' of https://github.com/mbedmicro/mbed
bcostm
commit
27918745cd
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,13 @@
|
|||
|
||||
LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
|
||||
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
; 8_byte_aligned(16+47 vect * 4 bytes) = 0x100
|
||||
; 32kB (0x8000) - 0x100 = 0x7F00
|
||||
RW_IRAM1 (0x10000000+0x100) (0x8000-0x100) {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,244 @@
|
|||
;/**************************************************************************//**
|
||||
; * @file startup_LPC11U6x.s
|
||||
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
|
||||
; * NXP LPC11U6x Device Series
|
||||
; * @version V1.00
|
||||
; * @date 22. October 2013
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2013 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * @par
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * @par
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
|
||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
EXPORT __initial_sp
|
||||
|
||||
__initial_sp EQU 0x10008000 ; Top of RAM from LPC1U68
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD PIN_INT0_IRQHandler ; 16+ 0 GPIO pin interrupt 0
|
||||
DCD PIN_INT1_IRQHandler ; 16+ 1 GPIO pin interrupt 1
|
||||
DCD PIN_INT2_IRQHandler ; 16+ 2 GPIO pin interrupt 2
|
||||
DCD PIN_INT3_IRQHandler ; 16+ 3 GPIO pin interrupt 3
|
||||
DCD PIN_INT4_IRQHandler ; 16+ 4 GPIO pin interrupt 4
|
||||
DCD PIN_INT5_IRQHandler ; 16+ 5 GPIO pin interrupt 5
|
||||
DCD PIN_INT6_IRQHandler ; 16+ 6 GPIO pin interrupt 6
|
||||
DCD PIN_INT7_IRQHandler ; 16+ 7 GPIO pin interrupt 7
|
||||
DCD GINT0_IRQHandler ; 16+ 8 GPIO GROUP0 interrupt
|
||||
DCD GINT1_IRQHandler ; 16+ 9 GPIO GROUP1 interrupt
|
||||
DCD I2C1_IRQHandler ; 16+10 I2C1 interrupt
|
||||
DCD USART1_4_IRQHandler ; 16+11 Combined USART1 and USART4 interrupts
|
||||
DCD USART2_3_IRQHandler ; 16+12 Combined USART2 and USART3 interrupts
|
||||
DCD SCT0_1_IRQHandler ; 16+13 Combined SCT0 and SCT1 interrupts
|
||||
DCD SSP1_IRQHandler ; 16+14 SSP1 interrupt
|
||||
DCD I2C0_IRQHandler ; 16+15 I2C0 interrupt
|
||||
DCD CT16B0_IRQHandler ; 16+16 CT16B0 interrupt
|
||||
DCD CT16B1_IRQHandler ; 16+17 CT16B1 interrupt
|
||||
DCD CT32B0_IRQHandler ; 16+18 CT32B0 interrupt
|
||||
DCD CT32B1_IRQHandler ; 16+19 CT32B1 interrupt
|
||||
DCD SSP0_IRQHandler ; 16+20 SSP0 interrupt
|
||||
DCD USART0_IRQHandler ; 16+21 USART0 interrupt
|
||||
DCD USB_IRQHandler ; 16+22 USB interrupt
|
||||
DCD USB_FIQ_IRQHandler ; 16+23 USB_FIQ interrupt
|
||||
DCD ADC_A_IRQHandler ; 16+24 Combined ADC_A end-of-sequence A and threshold crossing interrupts
|
||||
DCD RTC_IRQHandler ; 16+25 RTC interrupt
|
||||
DCD BOD_WDT_IRQHandler ; 16+26 Combined BOD and WWDT interrupt
|
||||
DCD FLASH_IRQHandler ; 16+27 Combined flash and EEPROM controller interrupts
|
||||
DCD DMA_IRQHandler ; 16+28 DMA interrupt
|
||||
DCD ADC_B_IRQHandler ; 16+29 Combined ADC_A end-of-sequence A and threshold crossing interrupts
|
||||
DCD USBWAKEUP_IRQHandler ; 16+30 USB_WAKEUP interrupt
|
||||
DCD 0 ; 16+31 Reserved
|
||||
|
||||
; <h> Code Read Protection
|
||||
; <o> Code Read Protection <0xFFFFFFFF=>CRP Disabled
|
||||
; <0x12345678=>CRP Level 1
|
||||
; <0x87654321=>CRP Level 2
|
||||
; <0x43218765=>CRP Level 3 (ARE YOU SURE?)
|
||||
; <0x4E697370=>NO ISP (ARE YOU SURE?)
|
||||
; </h>
|
||||
IF :LNOT::DEF:NO_CRP
|
||||
AREA |.ARM.__at_0x02FC|, CODE, READONLY
|
||||
DCD 0xFFFFFFFF
|
||||
ENDIF
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
Reserved_IRQHandler PROC
|
||||
EXPORT Reserved_IRQHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT PIN_INT0_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT1_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT2_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT3_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT4_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT5_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT6_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT7_IRQHandler [WEAK]
|
||||
EXPORT GINT0_IRQHandler [WEAK]
|
||||
EXPORT GINT1_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT USART1_4_IRQHandler [WEAK]
|
||||
EXPORT USART2_3_IRQHandler [WEAK]
|
||||
EXPORT SCT0_1_IRQHandler [WEAK]
|
||||
EXPORT SSP1_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT CT16B0_IRQHandler [WEAK]
|
||||
EXPORT CT16B1_IRQHandler [WEAK]
|
||||
EXPORT CT32B0_IRQHandler [WEAK]
|
||||
EXPORT CT32B1_IRQHandler [WEAK]
|
||||
EXPORT SSP0_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USB_IRQHandler [WEAK]
|
||||
EXPORT USB_FIQ_IRQHandler [WEAK]
|
||||
EXPORT ADC_A_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT BOD_WDT_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT DMA_IRQHandler [WEAK]
|
||||
EXPORT ADC_B_IRQHandler [WEAK]
|
||||
EXPORT USBWAKEUP_IRQHandler [WEAK]
|
||||
|
||||
PIN_INT0_IRQHandler
|
||||
PIN_INT1_IRQHandler
|
||||
PIN_INT2_IRQHandler
|
||||
PIN_INT3_IRQHandler
|
||||
PIN_INT4_IRQHandler
|
||||
PIN_INT5_IRQHandler
|
||||
PIN_INT6_IRQHandler
|
||||
PIN_INT7_IRQHandler
|
||||
GINT0_IRQHandler
|
||||
GINT1_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
USART1_4_IRQHandler
|
||||
USART2_3_IRQHandler
|
||||
SCT0_1_IRQHandler
|
||||
SSP1_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
CT16B0_IRQHandler
|
||||
CT16B1_IRQHandler
|
||||
CT32B0_IRQHandler
|
||||
CT32B1_IRQHandler
|
||||
SSP0_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USB_IRQHandler
|
||||
USB_FIQ_IRQHandler
|
||||
ADC_A_IRQHandler
|
||||
RTC_IRQHandler
|
||||
BOD_WDT_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
DMA_IRQHandler
|
||||
ADC_B_IRQHandler
|
||||
USBWAKEUP_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
/* mbed Microcontroller Library - CMSIS
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* A generic CMSIS include header, pulling in LPC8xx specifics
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_H
|
||||
#define MBED_CMSIS_H
|
||||
|
||||
#include "LPC11U6x.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
|
||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*/
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
||||
uint32_t i;
|
||||
|
||||
// Copy and switch to dynamic vectors if the first time called
|
||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
||||
uint32_t *old_vectors = vectors;
|
||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
||||
vectors[i] = old_vectors[i];
|
||||
}
|
||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
||||
}
|
||||
vectors[IRQn + 16] = vector;
|
||||
}
|
||||
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
||||
return vectors[IRQn + 16];
|
||||
}
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/* mbed Microcontroller Library - cmsis_nvic
|
||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,555 @@
|
|||
/**************************************************************************//**
|
||||
* @file system_LPC11U6x.c
|
||||
* @brief CMSIS Cortex-M3 Device System Source File for
|
||||
* NXP LPC11U6x Device Series
|
||||
* @version V1.00
|
||||
* @date 19. July 2013
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2013 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include "LPC11U6x.h"
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
/*- SystemCoreClock Configuration -------------------------------------------*/
|
||||
// <e0> SystemCoreClock Configuration
|
||||
#define CLOCK_SETUP 1
|
||||
//
|
||||
// <h> System Oscillator Control (SYSOSCCTRL)
|
||||
// <o.0> BYPASS: System Oscillator Bypass Enable
|
||||
// <i> If enabled then PLL input (sys_osc_clk) is fed
|
||||
// <i> directly from XTALIN and XTALOUT pins.
|
||||
// <o.1> FREQRANGE: System Oscillator Frequency Range
|
||||
// <i> Determines frequency range for Low-power oscillator.
|
||||
// <0=> 1 - 20 MHz
|
||||
// <1=> 15 - 25 MHz
|
||||
// </h>
|
||||
#define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000
|
||||
//
|
||||
// <o.0..1> System PLL Clock Source Select (SYSPLLCLKSEL)
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> Crystal Oscillator (SYSOSC)
|
||||
// <3=> RTC Oscillator (32 kHz)
|
||||
#define SYSPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
|
||||
//
|
||||
// <e> Clock Configuration (Manual)
|
||||
#define CLOCK_SETUP_REG 1
|
||||
//
|
||||
// <h> WD Oscillator Setting (WDTOSCCTRL)
|
||||
// <o.0..4> DIVSEL: Select Divider for Fclkana
|
||||
// <i> wd_osc_clk = Fclkana / (2 × (1 + DIVSEL))
|
||||
// <0-31>
|
||||
// <o.5..8> FREQSEL: Select WD Oscillator Analog Output Frequency (Fclkana)
|
||||
// <1=> 0.5 MHz
|
||||
// <2=> 0.8 MHz
|
||||
// <3=> 1.1 MHz
|
||||
// <4=> 1.4 MHz
|
||||
// <5=> 1.6 MHz
|
||||
// <6=> 1.8 MHz
|
||||
// <7=> 2.0 MHz
|
||||
// <8=> 2.2 MHz
|
||||
// <9=> 2.4 MHz
|
||||
// <10=> 2.6 MHz
|
||||
// <11=> 2.7 MHz
|
||||
// <12=> 2.9 MHz
|
||||
// <13=> 3.1 MHz
|
||||
// <14=> 3.2 MHz
|
||||
// <15=> 3.4 MHz
|
||||
// </h>
|
||||
#define WDTOSCCTRL_Val 0x000000A0 // Reset value: 0x0A0
|
||||
//
|
||||
// <h> System PLL Setting (SYSPLLCTRL)
|
||||
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
|
||||
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
|
||||
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
|
||||
// <o.0..4> MSEL: Feedback Divider Selection
|
||||
// <i> M = MSEL + 1
|
||||
// <0-31>
|
||||
// <o.5..6> PSEL: Post Divider Selection
|
||||
// <i> Post divider ratio P. Division ratio is 2 * P
|
||||
// <0=> P = 1
|
||||
// <1=> P = 2
|
||||
// <2=> P = 4
|
||||
// <3=> P = 8
|
||||
// </h>
|
||||
#define SYSPLLCTRL_Val 0x00000003 // Reset value: 0x000
|
||||
//
|
||||
// <o.0..1> Main Clock Source Select (MAINCLKSEL)
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> PLL Input
|
||||
// <2=> WD Oscillator
|
||||
// <3=> PLL Output
|
||||
#define MAINCLKSEL_Val 0x00000003 // Reset value: 0x000
|
||||
//
|
||||
// <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV)
|
||||
// <i> Divides main clock to provide system clock to core, memories, and peripherals.
|
||||
// <i> 0 = is disabled
|
||||
// <0-255>
|
||||
#define SYSAHBCLKDIV_Val 0x00000001 // Reset value: 0x001
|
||||
// </e>
|
||||
//
|
||||
// <e> Clock Configuration (via ROM PLL API)
|
||||
#define CLOCK_SETUP_API 0
|
||||
//
|
||||
// <o> PLL API Mode Select
|
||||
// <0=> Exact
|
||||
// <1=> Less than or equal
|
||||
// <2=> Greater than or equal
|
||||
// <3=> As close as possible
|
||||
#define PLL_API_MODE_Val 0
|
||||
//
|
||||
// <o> CPU Frequency [Hz] <1000000-50000000:1000>
|
||||
#define PLL_API_FREQ_Val 48000000
|
||||
// </e>
|
||||
//
|
||||
// <e> USB Clock Configuration
|
||||
#define USB_CLOCK_SETUP 1
|
||||
// <h> USB PLL Control (USBPLLCTRL)
|
||||
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
|
||||
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
|
||||
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
|
||||
// <o.0..4> MSEL: Feedback Divider Selection
|
||||
// <i> M = MSEL + 1
|
||||
// <0-31>
|
||||
// <o.5..6> PSEL: Post Divider Selection
|
||||
// <i> Post divider ratio P. Division ratio is 2 * P
|
||||
// <0=> P = 1
|
||||
// <1=> P = 2
|
||||
// <2=> P = 4
|
||||
// <3=> P = 8
|
||||
// </h>
|
||||
#define USBPLLCTRL_Val 0x00000023 // Reset value: 0x000
|
||||
//
|
||||
// <o.0..1> USB PLL Clock Source Select (USBPLLCLKSEL.SEL)
|
||||
// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
#define USBPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
|
||||
//
|
||||
// <o.0..1> USB Clock Source Select (USBCLKSEL.SEL)
|
||||
// <0=> USB PLL out
|
||||
// <1=> Main clock
|
||||
#define USBCLKSEL_Val 0x00000000 // Reset value: 0x000
|
||||
//
|
||||
// <o.0..7> USB Clock Divider (USBCLKDIV.DIV)
|
||||
// <i> Divides USB clock to 48 MHz.
|
||||
// <i> 0 = is disabled
|
||||
// <0-255>
|
||||
#define USBCLKDIV_Val 0x00000001 // Reset Value: 0x001
|
||||
// </e>
|
||||
//
|
||||
// </e>
|
||||
//
|
||||
// <o0>System Oscillator (XTAL) Frequency [Hz] <1000000-25000000>
|
||||
// <i> XTAL frequency must be in the range of 1 MHz to 25 MHz
|
||||
//
|
||||
#define XTAL_CLK_Val 12000000
|
||||
|
||||
/*
|
||||
//-------- <<< end of configuration section >>> ------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */
|
||||
#define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */
|
||||
#define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */
|
||||
#define __RTC_OSC_CLK ( 32768UL) /* RTC oscillator freq */
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Check the register settings
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
||||
#define CHECK_RSVD(val, mask) (val & mask)
|
||||
|
||||
#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
|
||||
#error "SYSOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
|
||||
#error "WDTOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
|
||||
#error "SYSPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (SYSPLLCLKSEL_Val == 3) // RTC Oscillator used as PLL input
|
||||
#if (CLOCK_SETUP_API == 1)
|
||||
#error "SYSPLLCLKSEL: RTC oscillator not allowed as PLL clock source!"
|
||||
#endif
|
||||
#if (CLOCK_SETUP_REG == 1) && (MAINCLKSEL_Val == 3) // RTC Oscillator used as PLL input
|
||||
#error "SYSPLLCLKSEL: RTC oscillator not allowed as PLL clock source!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x0000007F))
|
||||
#error "SYSPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
|
||||
#error "MAINCLKSEL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
|
||||
#error "SYSAHBCLKDIV: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if ( CLOCK_SETUP_REG == CLOCK_SETUP_API )
|
||||
#error "You must select either manual or API based Clock Configuration!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
|
||||
#error "USBPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000007F))
|
||||
#error "USBPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
|
||||
#error "USBCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
|
||||
#error "USBCLKDIV: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000))
|
||||
#error "XTAL frequency is out of bounds"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3))
|
||||
#error "PLL API Mode Select not valid"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 50000000))
|
||||
#error "CPU Frequency (API mode) not valid"
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Calculate system core clock
|
||||
*----------------------------------------------------------------------------*/
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
|
||||
/* sys_pllclkin calculation */
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
|
||||
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
|
||||
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
|
||||
#elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
|
||||
#define __SYS_PLLCLKIN (__RTC_OSC_CLK)
|
||||
#else
|
||||
#error "Oops"
|
||||
#endif
|
||||
|
||||
#if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
|
||||
|
||||
#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
|
||||
#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
|
||||
|
||||
#if (__FREQSEL == 0)
|
||||
#error "WDTOSCCTRL.FREQSEL undefined!"
|
||||
#elif (__FREQSEL == 1)
|
||||
#define __OSC_CLK ( 500000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 2)
|
||||
#define __OSC_CLK ( 800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 3)
|
||||
#define __OSC_CLK (1100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 4)
|
||||
#define __OSC_CLK (1400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 5)
|
||||
#define __OSC_CLK (1600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 6)
|
||||
#define __OSC_CLK (1800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 7)
|
||||
#define __OSC_CLK (2000000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 8)
|
||||
#define __OSC_CLK (2200000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 9)
|
||||
#define __OSC_CLK (2400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 10)
|
||||
#define __OSC_CLK (2600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 11)
|
||||
#define __OSC_CLK (2700000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 12)
|
||||
#define __OSC_CLK (2900000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 13)
|
||||
#define __OSC_CLK (3100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 14)
|
||||
#define __OSC_CLK (3200000 / __DIVSEL)
|
||||
#else
|
||||
#define __OSC_CLK (3400000 / __DIVSEL)
|
||||
#endif
|
||||
|
||||
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
|
||||
|
||||
/* main clock calculation */
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 0)
|
||||
#define __MAIN_CLOCK (__IRC_OSC_CLK)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 1)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKIN)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 2)
|
||||
#define __MAIN_CLOCK (__OSC_CLK)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 3)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
|
||||
#else
|
||||
#error "Oops"
|
||||
#endif
|
||||
|
||||
#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
|
||||
#endif /* Clock Setup via Register */
|
||||
|
||||
#if (CLOCK_SETUP_API == 1) /* Clock Setup via ROM API */
|
||||
#define __SYSTEM_CLOCK (PLL_API_FREQ_Val)
|
||||
#endif /* Clock Setup via PLL API */
|
||||
|
||||
#else
|
||||
#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
|
||||
#endif /* CLOCK_SETUP */
|
||||
|
||||
|
||||
|
||||
#if ((CLOCK_SETUP == 1) && (CLOCK_SETUP_API == 1)) /* PLL Setup via PLL API */
|
||||
#include "power_api.h"
|
||||
|
||||
typedef struct _ROM {
|
||||
const unsigned p_dev0;
|
||||
const unsigned p_dev1;
|
||||
const unsigned p_dev2;
|
||||
const PWRD * pPWRD; /* ROM Power Management API */
|
||||
const unsigned p_dev4;
|
||||
const unsigned p_dev5;
|
||||
const unsigned p_dev6;
|
||||
const unsigned p_dev7;
|
||||
} ROM;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
PLL API Function
|
||||
*----------------------------------------------------------------------------*/
|
||||
static void setPLL(const uint32_t pllMode, const uint32_t pllInFreq, const uint32_t reqCpuFreq)
|
||||
{
|
||||
uint32_t cmd[5], res[5];
|
||||
ROM ** rom = (ROM **) 0x1FFF1FF8; /* pointer to power API calls */
|
||||
|
||||
cmd[0] = pllInFreq; /* PLL's input freq in KHz */
|
||||
cmd[1] = reqCpuFreq; /* requested CPU freq in KHz */
|
||||
cmd[2] = pllMode;
|
||||
cmd[3] = 0; /* no timeout for PLL to lock */
|
||||
|
||||
/* Execute API call */
|
||||
(*rom)->pPWRD->set_pll(cmd, res); /* call API function */
|
||||
if ((res[0] != PLL_CMD_SUCCESS)){ /* in case of an error ... */
|
||||
while(1); /* ... stay here */
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /* System Clock Frequency */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
uint32_t oscClk = 0;
|
||||
|
||||
/* Determine clock frequency according to clock register values */
|
||||
switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
|
||||
case 0: oscClk = 0; break;
|
||||
case 1: oscClk = 500000; break;
|
||||
case 2: oscClk = 800000; break;
|
||||
case 3: oscClk = 1100000; break;
|
||||
case 4: oscClk = 1400000; break;
|
||||
case 5: oscClk = 1600000; break;
|
||||
case 6: oscClk = 1800000; break;
|
||||
case 7: oscClk = 2000000; break;
|
||||
case 8: oscClk = 2200000; break;
|
||||
case 9: oscClk = 2400000; break;
|
||||
case 10: oscClk = 2600000; break;
|
||||
case 11: oscClk = 2700000; break;
|
||||
case 12: oscClk = 2900000; break;
|
||||
case 13: oscClk = 3100000; break;
|
||||
case 14: oscClk = 3200000; break;
|
||||
case 15: oscClk = 3400000; break;
|
||||
}
|
||||
oscClk /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
|
||||
|
||||
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* Input Clock to System PLL */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 2: /* WDT Oscillator */
|
||||
SystemCoreClock = oscClk;
|
||||
break;
|
||||
case 3: /* System PLL Clock Out */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
*/
|
||||
void SystemInit (void) {
|
||||
#if (CLOCK_SETUP)
|
||||
volatile uint32_t i;
|
||||
#endif
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
|
||||
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
|
||||
|
||||
#warning "should not return here, need to fix an issue with PLL lock"
|
||||
return;
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up sysosc */
|
||||
for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
|
||||
#endif
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 3)
|
||||
LPC_SYSCON->RTCOSCCTRL = (1 << 0); /* Enable 32 kHz output */
|
||||
for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
|
||||
//LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
|
||||
LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
|
||||
LPC_SYSCON->SYSPLLCLKUEN = 0x01;
|
||||
while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
|
||||
|
||||
#if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
|
||||
|
||||
#if (((MAINCLKSEL_Val & 0x03) == 2) )
|
||||
LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
|
||||
for (i = 0; i < 2000; i++) __NOP(); /* Wait for osc to stabilize */
|
||||
#endif
|
||||
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 7); /* Power-down SYSPLL */
|
||||
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
|
||||
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select Clock Source */
|
||||
LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
|
||||
LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
|
||||
LPC_SYSCON->MAINCLKUEN = 0x01;
|
||||
while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
|
||||
|
||||
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
|
||||
#endif /* Clock Setup via Register */
|
||||
|
||||
#if (CLOCK_SETUP_API == 1) /* Clock Setup via PLL API */
|
||||
// LPC_SYSCON->SYSPLLCLKSEL = 0x00; /* Use IRC */
|
||||
// LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
|
||||
// LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
|
||||
// LPC_SYSCON->SYSPLLCLKUEN = 0x01;
|
||||
// while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
|
||||
|
||||
LPC_SYSCON->MAINCLKSEL = SYSPLLCLKSEL_Val; /* Select same as SYSPLL */
|
||||
LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
|
||||
LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
|
||||
LPC_SYSCON->MAINCLKUEN = 0x01;
|
||||
while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
|
||||
|
||||
LPC_SYSCON->SYSAHBCLKDIV = 1;
|
||||
|
||||
setPLL(PLL_API_MODE_Val, __SYS_PLLCLKIN / 1000, PLL_API_FREQ_Val / 1000);
|
||||
#endif /* Clock Setup via PLL API */
|
||||
|
||||
#if (USB_CLOCK_SETUP == 1) /* USB clock is used */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
|
||||
|
||||
#if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
|
||||
LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
|
||||
LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */
|
||||
LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */
|
||||
LPC_SYSCON->USBPLLCLKUEN = 0x01;
|
||||
while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */
|
||||
|
||||
LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
|
||||
while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
|
||||
LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
|
||||
LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
|
||||
|
||||
#else /* USB clock is not used */
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
|
||||
#endif
|
||||
|
||||
#endif /* Clock Setup */
|
||||
|
||||
/* System clock to the IOCON needs to be enabled or
|
||||
most of the I/O related peripherals won't work. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
|
||||
}
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
/**************************************************************************//**
|
||||
* @file system_LPC11U6x.h
|
||||
* @brief CMSIS Cortex-M3 Device System Header File for
|
||||
* NXP LPC11U6x Device Series
|
||||
* @version V1.00
|
||||
* @date 19. July 2013
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2013 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_LPC11U6x_H
|
||||
#define __SYSTEM_LPC11U6x_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_LPC11U6x_H */
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PERIPHERALNAMES_H
|
||||
#define MBED_PERIPHERALNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
UART_0 = (int)LPC_USART0_BASE,
|
||||
UART_1 = (int)LPC_USART1_BASE,
|
||||
UART_2 = (int)LPC_USART2_BASE,
|
||||
UART_3 = (int)LPC_USART3_BASE,
|
||||
UART_4 = (int)LPC_USART4_BASE,
|
||||
} UARTName;
|
||||
|
||||
typedef enum {
|
||||
ADC0_0 = 0,
|
||||
ADC0_1,
|
||||
ADC0_2,
|
||||
ADC0_3,
|
||||
ADC0_4,
|
||||
ADC0_5,
|
||||
ADC0_6,
|
||||
ADC0_7,
|
||||
ADC0_8,
|
||||
ADC0_9,
|
||||
ADC0_10,
|
||||
ADC0_11,
|
||||
ADC1_0,
|
||||
ADC1_1,
|
||||
ADC1_2,
|
||||
ADC1_3,
|
||||
ADC1_4,
|
||||
ADC1_5,
|
||||
ADC1_6,
|
||||
ADC1_7,
|
||||
ADC1_8,
|
||||
ADC1_9,
|
||||
ADC1_10,
|
||||
ADC1_11,
|
||||
} ADCName;
|
||||
|
||||
typedef enum {
|
||||
SPI_0 = (int)LPC_SSP0_BASE,
|
||||
SPI_1 = (int)LPC_SSP1_BASE
|
||||
} SPIName;
|
||||
|
||||
typedef enum {
|
||||
I2C_0 = (int)LPC_I2C0_BASE,
|
||||
I2C_1 = (int)LPC_I2C1_BASE
|
||||
} I2CName;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2014 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 16
|
||||
#define PIN_SHIFT 9
|
||||
|
||||
typedef enum {
|
||||
// LPC11U68 Pin Names (PORT[19:16] + PIN[15:9] + IOCON offset[8:0])
|
||||
|
||||
P0_0 = (0 << PORT_SHIFT) | (0 << PIN_SHIFT) | 0x000,
|
||||
P0_1 = (0 << PORT_SHIFT) | (1 << PIN_SHIFT) | 0x004,
|
||||
P0_2 = (0 << PORT_SHIFT) | (2 << PIN_SHIFT) | 0x008,
|
||||
P0_3 = (0 << PORT_SHIFT) | (3 << PIN_SHIFT) | 0x00C,
|
||||
P0_4 = (0 << PORT_SHIFT) | (4 << PIN_SHIFT) | 0x010,
|
||||
P0_5 = (0 << PORT_SHIFT) | (5 << PIN_SHIFT) | 0x014,
|
||||
P0_6 = (0 << PORT_SHIFT) | (6 << PIN_SHIFT) | 0x018,
|
||||
P0_7 = (0 << PORT_SHIFT) | (7 << PIN_SHIFT) | 0x01C,
|
||||
P0_8 = (0 << PORT_SHIFT) | (8 << PIN_SHIFT) | 0x020,
|
||||
P0_9 = (0 << PORT_SHIFT) | (9 << PIN_SHIFT) | 0x024,
|
||||
P0_10= (0 << PORT_SHIFT) | (10<< PIN_SHIFT) | 0x028,
|
||||
P0_11= (0 << PORT_SHIFT) | (11<< PIN_SHIFT) | 0x02C,
|
||||
P0_12= (0 << PORT_SHIFT) | (12<< PIN_SHIFT) | 0x030,
|
||||
P0_13= (0 << PORT_SHIFT) | (13<< PIN_SHIFT) | 0x034,
|
||||
P0_14= (0 << PORT_SHIFT) | (14<< PIN_SHIFT) | 0x038,
|
||||
P0_15= (0 << PORT_SHIFT) | (15<< PIN_SHIFT) | 0x03C,
|
||||
P0_16= (0 << PORT_SHIFT) | (16<< PIN_SHIFT) | 0x040,
|
||||
P0_17= (0 << PORT_SHIFT) | (17<< PIN_SHIFT) | 0x044,
|
||||
P0_18= (0 << PORT_SHIFT) | (18<< PIN_SHIFT) | 0x048,
|
||||
P0_19= (0 << PORT_SHIFT) | (19<< PIN_SHIFT) | 0x04C,
|
||||
P0_20= (0 << PORT_SHIFT) | (20<< PIN_SHIFT) | 0x050,
|
||||
P0_21= (0 << PORT_SHIFT) | (21<< PIN_SHIFT) | 0x054,
|
||||
P0_22= (0 << PORT_SHIFT) | (22<< PIN_SHIFT) | 0x058,
|
||||
P0_23= (0 << PORT_SHIFT) | (23<< PIN_SHIFT) | 0x05C,
|
||||
|
||||
P1_0 = (1 << PORT_SHIFT) | (0 << PIN_SHIFT) | 0x060,
|
||||
P1_1 = (1 << PORT_SHIFT) | (1 << PIN_SHIFT) | 0x064,
|
||||
P1_2 = (1 << PORT_SHIFT) | (2 << PIN_SHIFT) | 0x068,
|
||||
P1_3 = (1 << PORT_SHIFT) | (3 << PIN_SHIFT) | 0x06C,
|
||||
P1_4 = (1 << PORT_SHIFT) | (4 << PIN_SHIFT) | 0x070,
|
||||
P1_5 = (1 << PORT_SHIFT) | (5 << PIN_SHIFT) | 0x074,
|
||||
P1_6 = (1 << PORT_SHIFT) | (6 << PIN_SHIFT) | 0x078,
|
||||
P1_7 = (1 << PORT_SHIFT) | (7 << PIN_SHIFT) | 0x07C,
|
||||
P1_8 = (1 << PORT_SHIFT) | (8 << PIN_SHIFT) | 0x080,
|
||||
P1_9 = (1 << PORT_SHIFT) | (9 << PIN_SHIFT) | 0x084,
|
||||
P1_10= (1 << PORT_SHIFT) | (10<< PIN_SHIFT) | 0x088,
|
||||
P1_11= (1 << PORT_SHIFT) | (11<< PIN_SHIFT) | 0x08C,
|
||||
P1_12= (1 << PORT_SHIFT) | (12<< PIN_SHIFT) | 0x090,
|
||||
P1_13= (1 << PORT_SHIFT) | (13<< PIN_SHIFT) | 0x094,
|
||||
P1_14= (1 << PORT_SHIFT) | (14<< PIN_SHIFT) | 0x098,
|
||||
P1_15= (1 << PORT_SHIFT) | (15<< PIN_SHIFT) | 0x09C,
|
||||
P1_16= (1 << PORT_SHIFT) | (16<< PIN_SHIFT) | 0x0A0,
|
||||
P1_17= (1 << PORT_SHIFT) | (17<< PIN_SHIFT) | 0x0A4,
|
||||
P1_18= (1 << PORT_SHIFT) | (18<< PIN_SHIFT) | 0x0A8,
|
||||
P1_19= (1 << PORT_SHIFT) | (19<< PIN_SHIFT) | 0x0AC,
|
||||
P1_20= (1 << PORT_SHIFT) | (20<< PIN_SHIFT) | 0x0B0,
|
||||
P1_21= (1 << PORT_SHIFT) | (21<< PIN_SHIFT) | 0x0B4,
|
||||
P1_22= (1 << PORT_SHIFT) | (22<< PIN_SHIFT) | 0x0B8,
|
||||
P1_23= (1 << PORT_SHIFT) | (23<< PIN_SHIFT) | 0x0BC,
|
||||
P1_24= (1 << PORT_SHIFT) | (24<< PIN_SHIFT) | 0x0C0,
|
||||
P1_25= (1 << PORT_SHIFT) | (25<< PIN_SHIFT) | 0x0C4,
|
||||
P1_26= (1 << PORT_SHIFT) | (26<< PIN_SHIFT) | 0x0C8,
|
||||
P1_27= (1 << PORT_SHIFT) | (27<< PIN_SHIFT) | 0x0CC,
|
||||
P1_28= (1 << PORT_SHIFT) | (28<< PIN_SHIFT) | 0x0D0,
|
||||
P1_29= (1 << PORT_SHIFT) | (29<< PIN_SHIFT) | 0x0D4,
|
||||
P1_30= (1 << PORT_SHIFT) | (30<< PIN_SHIFT) | 0x0D8,
|
||||
P1_31= (1 << PORT_SHIFT) | (31<< PIN_SHIFT) | 0x0DC,
|
||||
|
||||
P2_0 = (2 << PORT_SHIFT) | (0 << PIN_SHIFT) | 0x0F0,
|
||||
P2_1 = (2 << PORT_SHIFT) | (1 << PIN_SHIFT) | 0x0F4,
|
||||
P2_2 = (2 << PORT_SHIFT) | (2 << PIN_SHIFT) | 0x0FC,
|
||||
P2_3 = (2 << PORT_SHIFT) | (3 << PIN_SHIFT) | 0x100,
|
||||
P2_4 = (2 << PORT_SHIFT) | (4 << PIN_SHIFT) | 0x104,
|
||||
P2_5 = (2 << PORT_SHIFT) | (5 << PIN_SHIFT) | 0x108,
|
||||
P2_6 = (2 << PORT_SHIFT) | (6 << PIN_SHIFT) | 0x10C,
|
||||
P2_7 = (2 << PORT_SHIFT) | (7 << PIN_SHIFT) | 0x110,
|
||||
P2_8 = (2 << PORT_SHIFT) | (8 << PIN_SHIFT) | 0x114,
|
||||
P2_9 = (2 << PORT_SHIFT) | (9 << PIN_SHIFT) | 0x118,
|
||||
P2_10= (2 << PORT_SHIFT) | (10<< PIN_SHIFT) | 0x11C,
|
||||
P2_11= (2 << PORT_SHIFT) | (11<< PIN_SHIFT) | 0x120,
|
||||
P2_12= (2 << PORT_SHIFT) | (12<< PIN_SHIFT) | 0x124,
|
||||
P2_13= (2 << PORT_SHIFT) | (13<< PIN_SHIFT) | 0x128,
|
||||
P2_14= (2 << PORT_SHIFT) | (14<< PIN_SHIFT) | 0x12C,
|
||||
P2_15= (2 << PORT_SHIFT) | (15<< PIN_SHIFT) | 0x130,
|
||||
P2_16= (2 << PORT_SHIFT) | (16<< PIN_SHIFT) | 0x134,
|
||||
P2_17= (2 << PORT_SHIFT) | (17<< PIN_SHIFT) | 0x138,
|
||||
P2_18= (2 << PORT_SHIFT) | (18<< PIN_SHIFT) | 0x13C,
|
||||
P2_19= (2 << PORT_SHIFT) | (19<< PIN_SHIFT) | 0x140,
|
||||
P2_20= (2 << PORT_SHIFT) | (20<< PIN_SHIFT) | 0x144,
|
||||
P2_21= (2 << PORT_SHIFT) | (21<< PIN_SHIFT) | 0x148,
|
||||
P2_22= (2 << PORT_SHIFT) | (22<< PIN_SHIFT) | 0x14C,
|
||||
P2_23= (2 << PORT_SHIFT) | (23<< PIN_SHIFT) | 0x150,
|
||||
|
||||
LED_RED = P2_17,
|
||||
LED_GREEN = P2_16,
|
||||
LED_BLUE = P2_18,
|
||||
|
||||
// mbed original LED naming
|
||||
LED1 = LED_BLUE,
|
||||
LED2 = LED_GREEN,
|
||||
LED3 = LED_RED,
|
||||
LED4 = LED_RED,
|
||||
|
||||
// Serial to USB pins
|
||||
USBTX = P0_19,
|
||||
USBRX = P0_18,
|
||||
|
||||
// Arduino Shield Receptacles Names
|
||||
D0 = P0_18,
|
||||
D1 = P0_19,
|
||||
D2 = P1_18,
|
||||
D3 = P1_24,
|
||||
D4 = P1_19,
|
||||
D5 = P1_26,
|
||||
D6 = P1_27,
|
||||
D7 = P1_25,
|
||||
D8 = P1_28,
|
||||
D9 = P2_3,
|
||||
D10= P0_2,
|
||||
D11= P0_9,
|
||||
D12= P0_8,
|
||||
D13= P1_29,
|
||||
D14= P0_5,
|
||||
D15= P0_4,
|
||||
|
||||
A0 = P1_9,
|
||||
A1 = P0_14,
|
||||
A2 = P0_13,
|
||||
A3 = P0_12,
|
||||
A4 = P0_5, // same port as SDA
|
||||
A5 = P0_4, // same port as SCL
|
||||
SDA= P0_5, // same port as A4
|
||||
SCL= P0_4, // same port as A5
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF,
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullUp = 2,
|
||||
PullDown = 1,
|
||||
PullNone = 0,
|
||||
Repeater = 3,
|
||||
OpenDrain = 4,
|
||||
PullDefault = PullDown
|
||||
} PinMode;
|
||||
|
||||
#define STDIO_UART_TX USBTX
|
||||
#define STDIO_UART_RX USBRX
|
||||
#define STDIO_UART UART_0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2014 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PORTNAMES_H
|
||||
#define MBED_PORTNAMES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
Port0 = 0,
|
||||
Port1 = 1,
|
||||
Port2 = 2
|
||||
} PortName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2014 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
#define DEVICE_PORTIN 0
|
||||
#define DEVICE_PORTOUT 0
|
||||
#define DEVICE_PORTINOUT 0
|
||||
|
||||
#define DEVICE_INTERRUPTIN 1
|
||||
|
||||
#define DEVICE_ANALOGIN 0
|
||||
#define DEVICE_ANALOGOUT 0
|
||||
|
||||
#define DEVICE_SERIAL 1
|
||||
#define DEVICE_SERIAL_FC 1
|
||||
|
||||
#define DEVICE_I2C 1
|
||||
#define DEVICE_I2CSLAVE 0
|
||||
|
||||
#define DEVICE_SPI 1
|
||||
#define DEVICE_SPISLAVE 0
|
||||
|
||||
#define DEVICE_CAN 0
|
||||
|
||||
#define DEVICE_RTC 0
|
||||
|
||||
#define DEVICE_ETHERNET 0
|
||||
|
||||
#define DEVICE_PWMOUT 0
|
||||
|
||||
#define DEVICE_SEMIHOST 0
|
||||
#define DEVICE_LOCALFILESYSTEM 0
|
||||
|
||||
#define DEVICE_SLEEP 0
|
||||
|
||||
#define DEVICE_DEBUG_AWARENESS 0
|
||||
|
||||
#define DEVICE_STDIO_MESSAGES 0
|
||||
|
||||
#define DEVICE_ERROR_RED 1
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2014 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "gpio_api.h"
|
||||
#include "pinmap.h"
|
||||
|
||||
static int gpio_enabled = 0;
|
||||
|
||||
static void gpio_enable(void) {
|
||||
gpio_enabled = 1;
|
||||
|
||||
/* Enable AHB clock to the GPIO and IOCON domain. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= ((1 << 16) | (1 << 6));
|
||||
}
|
||||
|
||||
uint32_t gpio_set(PinName pin) {
|
||||
|
||||
if (!gpio_enabled)
|
||||
gpio_enable();
|
||||
|
||||
return (1UL << ((int)pin >> PIN_SHIFT & 0x1F));
|
||||
}
|
||||
|
||||
void gpio_init(gpio_t *obj, PinName pin) {
|
||||
if(pin == NC) return;
|
||||
|
||||
obj->pin = pin;
|
||||
obj->mask = gpio_set(pin);
|
||||
|
||||
unsigned int port = (unsigned int)(pin >> PORT_SHIFT);
|
||||
|
||||
obj->reg_set = &LPC_GPIO_PORT->SET[port];
|
||||
obj->reg_clr = &LPC_GPIO_PORT->CLR[port];
|
||||
obj->reg_in = &LPC_GPIO_PORT->PIN[port];
|
||||
obj->reg_dir = &LPC_GPIO_PORT->DIR[port];
|
||||
}
|
||||
|
||||
void gpio_mode(gpio_t *obj, PinMode mode) {
|
||||
pin_mode(obj->pin, mode);
|
||||
}
|
||||
|
||||
void gpio_dir(gpio_t *obj, PinDirection direction) {
|
||||
switch (direction) {
|
||||
case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
|
||||
case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <stddef.h>
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "gpio_irq_api.h"
|
||||
#include "error.h"
|
||||
|
||||
#if DEVICE_INTERRUPTIN
|
||||
|
||||
#define CHANNEL_NUM 8
|
||||
#define LPC_GPIO_X LPC_PINT
|
||||
#define PININT_IRQ PIN_INT0_IRQn
|
||||
|
||||
static uint32_t channel_ids[CHANNEL_NUM] = {0};
|
||||
static gpio_irq_handler irq_handler;
|
||||
|
||||
static inline void handle_interrupt_in(uint32_t channel) {
|
||||
uint32_t ch_bit = (1 << channel);
|
||||
// Return immediately if:
|
||||
// * The interrupt was already served
|
||||
// * There is no user handler
|
||||
// * It is a level interrupt, not an edge interrupt
|
||||
if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
|
||||
(channel_ids[channel] == 0 ) ||
|
||||
(LPC_GPIO_X->ISEL & ch_bit ) ) return;
|
||||
|
||||
if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
|
||||
irq_handler(channel_ids[channel], IRQ_RISE);
|
||||
LPC_GPIO_X->RISE = ch_bit;
|
||||
}
|
||||
if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
|
||||
irq_handler(channel_ids[channel], IRQ_FALL);
|
||||
LPC_GPIO_X->FALL = ch_bit;
|
||||
}
|
||||
LPC_GPIO_X->IST = ch_bit;
|
||||
}
|
||||
|
||||
void gpio_irq0(void) {handle_interrupt_in(0);}
|
||||
void gpio_irq1(void) {handle_interrupt_in(1);}
|
||||
void gpio_irq2(void) {handle_interrupt_in(2);}
|
||||
void gpio_irq3(void) {handle_interrupt_in(3);}
|
||||
void gpio_irq4(void) {handle_interrupt_in(4);}
|
||||
void gpio_irq5(void) {handle_interrupt_in(5);}
|
||||
void gpio_irq6(void) {handle_interrupt_in(6);}
|
||||
void gpio_irq7(void) {handle_interrupt_in(7);}
|
||||
|
||||
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
|
||||
// PINT only supprt PIO0_*, PIO1_* and from PIO2_0 to PIO0_7 interrupt
|
||||
if (pin >= P2_8) return -1;
|
||||
|
||||
irq_handler = handler;
|
||||
|
||||
int found_free_channel = 0;
|
||||
int i = 0;
|
||||
for (i=0; i<CHANNEL_NUM; i++) {
|
||||
if (channel_ids[i] == 0) {
|
||||
channel_ids[i] = id;
|
||||
obj->ch = i;
|
||||
found_free_channel = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!found_free_channel) return -1;
|
||||
|
||||
/* Enable AHB clock to the PIN, GPIO and IOCON domain. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= ((1 << 19) | (1 << 16) | (1 << 7));
|
||||
|
||||
LPC_SYSCON->PINTSEL[obj->ch] = ((((pin >> PORT_SHIFT) & 0x3) * 24) + ((pin >> PIN_SHIFT) & 0x1F));
|
||||
|
||||
// Interrupt Wake-Up Enable
|
||||
LPC_SYSCON->STARTERP0 |= (1 << obj->ch);
|
||||
|
||||
LPC_GPIO_PORT->DIR[(pin >> PORT_SHIFT) & 0x3] &= ~(1 << ((pin >> PIN_SHIFT) & 0x1F));
|
||||
|
||||
void (*channels_irq)(void) = NULL;
|
||||
switch (obj->ch) {
|
||||
case 0: channels_irq = &gpio_irq0; break;
|
||||
case 1: channels_irq = &gpio_irq1; break;
|
||||
case 2: channels_irq = &gpio_irq2; break;
|
||||
case 3: channels_irq = &gpio_irq3; break;
|
||||
case 4: channels_irq = &gpio_irq4; break;
|
||||
case 5: channels_irq = &gpio_irq5; break;
|
||||
case 6: channels_irq = &gpio_irq6; break;
|
||||
case 7: channels_irq = &gpio_irq7; break;
|
||||
}
|
||||
NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
|
||||
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void gpio_irq_free(gpio_irq_t *obj) {
|
||||
channel_ids[obj->ch] = 0;
|
||||
LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
|
||||
}
|
||||
|
||||
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
|
||||
unsigned int ch_bit = (1 << obj->ch);
|
||||
|
||||
// Clear interrupt
|
||||
if (!(LPC_GPIO_X->ISEL & ch_bit))
|
||||
LPC_GPIO_X->IST = ch_bit;
|
||||
|
||||
// Edge trigger
|
||||
LPC_GPIO_X->ISEL &= ~ch_bit;
|
||||
if (event == IRQ_RISE) {
|
||||
if (enable) {
|
||||
LPC_GPIO_X->IENR |= ch_bit;
|
||||
} else {
|
||||
LPC_GPIO_X->IENR &= ~ch_bit;
|
||||
}
|
||||
} else {
|
||||
if (enable) {
|
||||
LPC_GPIO_X->IENF |= ch_bit;
|
||||
} else {
|
||||
LPC_GPIO_X->IENF &= ~ch_bit;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void gpio_irq_enable(gpio_irq_t *obj) {
|
||||
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
|
||||
}
|
||||
|
||||
void gpio_irq_disable(gpio_irq_t *obj) {
|
||||
NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_GPIO_OBJECT_H
|
||||
#define MBED_GPIO_OBJECT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
PinName pin;
|
||||
uint32_t mask;
|
||||
|
||||
__IO uint32_t *reg_dir;
|
||||
__IO uint32_t *reg_set;
|
||||
__IO uint32_t *reg_clr;
|
||||
__I uint32_t *reg_in;
|
||||
} gpio_t;
|
||||
|
||||
static inline void gpio_write(gpio_t *obj, int value) {
|
||||
if (value)
|
||||
*obj->reg_set = obj->mask;
|
||||
else
|
||||
*obj->reg_clr = obj->mask;
|
||||
}
|
||||
|
||||
static inline int gpio_read(gpio_t *obj) {
|
||||
return ((*obj->reg_in & obj->mask) ? 1 : 0);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,400 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "i2c_api.h"
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
#include "error.h"
|
||||
|
||||
#if DEVICE_I2C
|
||||
|
||||
static const PinMap PinMap_I2C_SDA[] = {
|
||||
{P0_5 , I2C_0, 1},
|
||||
{P1_3 , I2C_1, 3},
|
||||
{P1_14, I2C_1, 1},
|
||||
{P1_24, I2C_1, 2},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_I2C_SCL[] = {
|
||||
{P0_4 , I2C_0, 1},
|
||||
{P0_7 , I2C_1, 3},
|
||||
{P1_11, I2C_1, 1},
|
||||
{P1_30, I2C_1, 1},
|
||||
{NC , NC, 0}
|
||||
};
|
||||
|
||||
#define I2C_CONSET(x) (x->i2c->CONSET)
|
||||
#define I2C_CONCLR(x) (x->i2c->CONCLR)
|
||||
#define I2C_STAT(x) (x->i2c->STAT)
|
||||
#define I2C_DAT(x) (x->i2c->DAT)
|
||||
#define I2C_SCLL(x, val) (x->i2c->SCLL = val)
|
||||
#define I2C_SCLH(x, val) (x->i2c->SCLH = val)
|
||||
|
||||
#warning [TODO] just copied from LPC11UXX code, need to check
|
||||
static const uint32_t I2C_addr_offset[2][4] = {
|
||||
{0x0C, 0x20, 0x24, 0x28},
|
||||
{0x30, 0x34, 0x38, 0x3C}
|
||||
};
|
||||
|
||||
static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
|
||||
I2C_CONCLR(obj) = (start << 5)
|
||||
| (stop << 4)
|
||||
| (interrupt << 3)
|
||||
| (acknowledge << 2);
|
||||
}
|
||||
|
||||
static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
|
||||
I2C_CONSET(obj) = (start << 5)
|
||||
| (stop << 4)
|
||||
| (interrupt << 3)
|
||||
| (acknowledge << 2);
|
||||
}
|
||||
|
||||
// Clear the Serial Interrupt (SI)
|
||||
static inline void i2c_clear_SI(i2c_t *obj) {
|
||||
i2c_conclr(obj, 0, 0, 1, 0);
|
||||
}
|
||||
|
||||
static inline int i2c_status(i2c_t *obj) {
|
||||
return I2C_STAT(obj);
|
||||
}
|
||||
|
||||
// Wait until the Serial Interrupt (SI) is set
|
||||
static int i2c_wait_SI(i2c_t *obj) {
|
||||
volatile int timeout = 0;
|
||||
while (!(I2C_CONSET(obj) & (1 << 3))) {
|
||||
timeout++;
|
||||
if (timeout > 100000) return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void i2c_interface_enable(i2c_t *obj) {
|
||||
I2C_CONSET(obj) = 0x40;
|
||||
}
|
||||
|
||||
static inline void i2c_power_enable(i2c_t *obj) {
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= ((1 << 5) | (1 << 25));
|
||||
LPC_SYSCON->PRESETCTRL |= ((1 << 1) | (1 << 3));
|
||||
}
|
||||
|
||||
void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
|
||||
// determine the SPI to use
|
||||
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
|
||||
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
|
||||
obj->i2c = (LPC_I2C0_Type *)pinmap_merge(i2c_sda, i2c_scl);
|
||||
|
||||
if ((int)obj->i2c == NC) {
|
||||
error("I2C pin mapping failed");
|
||||
}
|
||||
|
||||
// enable power
|
||||
i2c_power_enable(obj);
|
||||
|
||||
// set default frequency at 100k
|
||||
i2c_frequency(obj, 100000);
|
||||
i2c_conclr(obj, 1, 1, 1, 1);
|
||||
i2c_interface_enable(obj);
|
||||
|
||||
pinmap_pinout(sda, PinMap_I2C_SDA);
|
||||
pinmap_pinout(scl, PinMap_I2C_SCL);
|
||||
}
|
||||
|
||||
inline int i2c_start(i2c_t *obj) {
|
||||
int status = 0;
|
||||
// 8.1 Before master mode can be entered, I2CON must be initialised to:
|
||||
// - I2EN STA STO SI AA - -
|
||||
// - 1 0 0 0 x - -
|
||||
// if AA = 0, it can't enter slave mode
|
||||
i2c_conclr(obj, 1, 1, 1, 1);
|
||||
|
||||
// The master mode may now be entered by setting the STA bit
|
||||
// this will generate a start condition when the bus becomes free
|
||||
i2c_conset(obj, 1, 0, 0, 1);
|
||||
|
||||
i2c_wait_SI(obj);
|
||||
status = i2c_status(obj);
|
||||
|
||||
// Clear start bit now transmitted, and interrupt bit
|
||||
i2c_conclr(obj, 1, 0, 0, 0);
|
||||
return status;
|
||||
}
|
||||
|
||||
inline int i2c_stop(i2c_t *obj) {
|
||||
int timeout = 0;
|
||||
|
||||
// write the stop bit
|
||||
i2c_conset(obj, 0, 1, 0, 0);
|
||||
i2c_clear_SI(obj);
|
||||
|
||||
// wait for STO bit to reset
|
||||
while(I2C_CONSET(obj) & (1 << 4)) {
|
||||
timeout ++;
|
||||
if (timeout > 100000) return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
|
||||
// write the data
|
||||
I2C_DAT(obj) = value;
|
||||
|
||||
// clear SI to init a send
|
||||
i2c_clear_SI(obj);
|
||||
|
||||
// wait and return status
|
||||
i2c_wait_SI(obj);
|
||||
return i2c_status(obj);
|
||||
}
|
||||
|
||||
static inline int i2c_do_read(i2c_t *obj, int last) {
|
||||
// we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
|
||||
if (last) {
|
||||
i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
|
||||
} else {
|
||||
i2c_conset(obj, 0, 0, 0, 1); // send a ACK
|
||||
}
|
||||
|
||||
// accept byte
|
||||
i2c_clear_SI(obj);
|
||||
|
||||
// wait for it to arrive
|
||||
i2c_wait_SI(obj);
|
||||
|
||||
// return the data
|
||||
return (I2C_DAT(obj) & 0xFF);
|
||||
}
|
||||
|
||||
void i2c_frequency(i2c_t *obj, int hz) {
|
||||
// No peripheral clock divider on the M0
|
||||
#warning "[TODO] This should be fixed to handle system core clock correctly."
|
||||
uint32_t PCLK = 12000000; //SystemCoreClock;
|
||||
|
||||
uint32_t pulse = PCLK / (hz * 2);
|
||||
|
||||
// I2C Rate
|
||||
I2C_SCLL(obj, pulse);
|
||||
I2C_SCLH(obj, pulse);
|
||||
}
|
||||
|
||||
// The I2C does a read or a write as a whole operation
|
||||
// There are two types of error conditions it can encounter
|
||||
// 1) it can not obtain the bus
|
||||
// 2) it gets error responses at part of the transmission
|
||||
//
|
||||
// We tackle them as follows:
|
||||
// 1) we retry until we get the bus. we could have a "timeout" if we can not get it
|
||||
// which basically turns it in to a 2)
|
||||
// 2) on error, we use the standard error mechanisms to report/debug
|
||||
//
|
||||
// Therefore an I2C transaction should always complete. If it doesn't it is usually
|
||||
// because something is setup wrong (e.g. wiring), and we don't need to programatically
|
||||
// check for that
|
||||
|
||||
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
|
||||
int count, status;
|
||||
|
||||
status = i2c_start(obj);
|
||||
|
||||
if ((status != 0x10) && (status != 0x08)) {
|
||||
i2c_stop(obj);
|
||||
return I2C_ERROR_BUS_BUSY;
|
||||
}
|
||||
|
||||
status = i2c_do_write(obj, (address | 0x01), 1);
|
||||
if (status != 0x40) {
|
||||
i2c_stop(obj);
|
||||
return I2C_ERROR_NO_SLAVE;
|
||||
}
|
||||
|
||||
// Read in all except last byte
|
||||
for (count = 0; count < (length - 1); count++) {
|
||||
int value = i2c_do_read(obj, 0);
|
||||
status = i2c_status(obj);
|
||||
if (status != 0x50) {
|
||||
i2c_stop(obj);
|
||||
return count;
|
||||
}
|
||||
data[count] = (char) value;
|
||||
}
|
||||
|
||||
// read in last byte
|
||||
int value = i2c_do_read(obj, 1);
|
||||
status = i2c_status(obj);
|
||||
if (status != 0x58) {
|
||||
i2c_stop(obj);
|
||||
return length - 1;
|
||||
}
|
||||
|
||||
data[count] = (char) value;
|
||||
|
||||
// If not repeated start, send stop.
|
||||
if (stop) {
|
||||
i2c_stop(obj);
|
||||
}
|
||||
|
||||
return length;
|
||||
}
|
||||
|
||||
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
|
||||
int i, status;
|
||||
|
||||
status = i2c_start(obj);
|
||||
|
||||
if ((status != 0x10) && (status != 0x08)) {
|
||||
i2c_stop(obj);
|
||||
return I2C_ERROR_BUS_BUSY;
|
||||
}
|
||||
|
||||
status = i2c_do_write(obj, (address & 0xFE), 1);
|
||||
if (status != 0x18) {
|
||||
i2c_stop(obj);
|
||||
return I2C_ERROR_NO_SLAVE;
|
||||
}
|
||||
|
||||
for (i=0; i<length; i++) {
|
||||
status = i2c_do_write(obj, data[i], 0);
|
||||
if(status != 0x28) {
|
||||
i2c_stop(obj);
|
||||
return i;
|
||||
}
|
||||
}
|
||||
|
||||
// clearing the serial interrupt here might cause an unintended rewrite of the last byte
|
||||
// see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
|
||||
// i2c_clear_SI(obj);
|
||||
|
||||
// If not repeated start, send stop.
|
||||
if (stop) {
|
||||
i2c_stop(obj);
|
||||
}
|
||||
|
||||
return length;
|
||||
}
|
||||
|
||||
void i2c_reset(i2c_t *obj) {
|
||||
i2c_stop(obj);
|
||||
}
|
||||
|
||||
int i2c_byte_read(i2c_t *obj, int last) {
|
||||
return (i2c_do_read(obj, last) & 0xFF);
|
||||
}
|
||||
|
||||
int i2c_byte_write(i2c_t *obj, int data) {
|
||||
int ack;
|
||||
int status = i2c_do_write(obj, (data & 0xFF), 0);
|
||||
|
||||
switch(status) {
|
||||
case 0x18: case 0x28: // Master transmit ACKs
|
||||
ack = 1;
|
||||
break;
|
||||
case 0x40: // Master receive address transmitted ACK
|
||||
ack = 1;
|
||||
break;
|
||||
case 0xB8: // Slave transmit ACK
|
||||
ack = 1;
|
||||
break;
|
||||
default:
|
||||
ack = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
return ack;
|
||||
}
|
||||
|
||||
void i2c_slave_mode(i2c_t *obj, int enable_slave) {
|
||||
if (enable_slave != 0) {
|
||||
i2c_conclr(obj, 1, 1, 1, 0);
|
||||
i2c_conset(obj, 0, 0, 0, 1);
|
||||
} else {
|
||||
i2c_conclr(obj, 1, 1, 1, 1);
|
||||
}
|
||||
}
|
||||
|
||||
int i2c_slave_receive(i2c_t *obj) {
|
||||
int status;
|
||||
int retval;
|
||||
|
||||
status = i2c_status(obj);
|
||||
switch(status) {
|
||||
case 0x60: retval = 3; break;
|
||||
case 0x70: retval = 2; break;
|
||||
case 0xA8: retval = 1; break;
|
||||
default : retval = 0; break;
|
||||
}
|
||||
|
||||
return(retval);
|
||||
}
|
||||
|
||||
int i2c_slave_read(i2c_t *obj, char *data, int length) {
|
||||
int count = 0;
|
||||
int status;
|
||||
|
||||
do {
|
||||
i2c_clear_SI(obj);
|
||||
i2c_wait_SI(obj);
|
||||
status = i2c_status(obj);
|
||||
if((status == 0x80) || (status == 0x90)) {
|
||||
data[count] = I2C_DAT(obj) & 0xFF;
|
||||
}
|
||||
count++;
|
||||
} while (((status == 0x80) || (status == 0x90) ||
|
||||
(status == 0x060) || (status == 0x70)) && (count < length));
|
||||
|
||||
if(status != 0xA0) {
|
||||
i2c_stop(obj);
|
||||
}
|
||||
|
||||
i2c_clear_SI(obj);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
int i2c_slave_write(i2c_t *obj, const char *data, int length) {
|
||||
int count = 0;
|
||||
int status;
|
||||
|
||||
if(length <= 0) {
|
||||
return(0);
|
||||
}
|
||||
|
||||
do {
|
||||
status = i2c_do_write(obj, data[count], 0);
|
||||
count++;
|
||||
} while ((count < length) && (status == 0xB8));
|
||||
|
||||
if((status != 0xC0) && (status != 0xC8)) {
|
||||
i2c_stop(obj);
|
||||
}
|
||||
|
||||
i2c_clear_SI(obj);
|
||||
|
||||
return(count);
|
||||
}
|
||||
|
||||
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
|
||||
uint32_t addr;
|
||||
|
||||
if ((idx >= 0) && (idx <= 3)) {
|
||||
addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
|
||||
*((uint32_t *) addr) = address & 0xFF;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_OBJECTS_H
|
||||
#define MBED_OBJECTS_H
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "PortNames.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "PinNames.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if DEVICE_INTERRUPTIN
|
||||
struct gpio_irq_s {
|
||||
uint32_t ch;
|
||||
};
|
||||
#endif
|
||||
|
||||
#if DEVICE_PWMOUT
|
||||
struct pwmout_s {
|
||||
LPC_SCT0_Type* pwm;
|
||||
uint32_t pwm_ch;
|
||||
};
|
||||
#endif
|
||||
|
||||
#if DEVICE_SERIAL
|
||||
struct serial_s {
|
||||
LPC_USART0_Type *uart;
|
||||
unsigned char index;
|
||||
};
|
||||
#endif
|
||||
|
||||
#if DEVICE_ANALOGIN
|
||||
struct analogin_s {
|
||||
ADCName adc;
|
||||
};
|
||||
#endif
|
||||
|
||||
#if DEVICE_ANALOGOUT
|
||||
struct dac_s {
|
||||
DACName dac;
|
||||
};
|
||||
#endif
|
||||
|
||||
#if DEVICE_I2C
|
||||
struct i2c_s {
|
||||
LPC_I2C0_Type *i2c;
|
||||
};
|
||||
#endif
|
||||
|
||||
#if DEVICE_SPI
|
||||
struct spi_s {
|
||||
LPC_SSP0_Type *spi;
|
||||
unsigned char spi_n;
|
||||
};
|
||||
#endif
|
||||
|
||||
#include "gpio_object.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "pinmap.h"
|
||||
#include "error.h"
|
||||
|
||||
void pin_function(PinName pin, int function) {
|
||||
if (pin == (uint32_t)NC)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
__IO uint32_t *reg = (__IO uint32_t*)(LPC_IOCON_BASE + (pin & 0x1FF));
|
||||
|
||||
// pin function bits: [2:0] -> 111 = (0x7)
|
||||
*reg = (*reg & ~0x7) | (function & 0x7);
|
||||
}
|
||||
|
||||
void pin_mode(PinName pin, PinMode mode) {
|
||||
if (pin == (uint32_t)NC)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
if ((pin == P0_4) || (pin == P0_5)) {
|
||||
// The true open-drain pins PIO0_4 and PIO0_5 can be configured for different I2C-bus speeds.
|
||||
return;
|
||||
}
|
||||
|
||||
__IO uint32_t *reg = (__IO uint32_t*)(LPC_IOCON_BASE + (pin & 0x1FF));
|
||||
|
||||
if (mode == OpenDrain) {
|
||||
*reg |= (1 << 10);
|
||||
} else {
|
||||
uint32_t tmp = *reg;
|
||||
tmp &= ~(0x3 << 3);
|
||||
tmp |= (mode & 0x3) << 3;
|
||||
*reg = tmp;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,352 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
// math.h required for floating point operations for baud rate calculation
|
||||
#include <math.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include "serial_api.h"
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
#include "error.h"
|
||||
|
||||
#if DEVICE_SERIAL
|
||||
#warning "[TODO] support from UART_1 to UART_4"
|
||||
/******************************************************************************
|
||||
* INITIALIZATION
|
||||
******************************************************************************/
|
||||
|
||||
#define UART_NUM 5
|
||||
|
||||
static const PinMap PinMap_UART_TX[] = {
|
||||
{P0_19, UART_0, 1},
|
||||
{P1_18, UART_0, 2},
|
||||
{P1_27, UART_0, 2},
|
||||
{P1_18, UART_1, 2},
|
||||
{P1_0 , UART_2, 3},
|
||||
{P1_23, UART_2, 3},
|
||||
{P2_4 , UART_3, 1},
|
||||
{P2_12, UART_4, 1},
|
||||
{ NC , NC , 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_UART_RX[] = {
|
||||
{P0_18, UART_0, 1},
|
||||
{P1_17, UART_0, 2},
|
||||
{P1_26, UART_0, 2},
|
||||
{P1_2 , UART_1, 3},
|
||||
{P0_20, UART_2, 2},
|
||||
{P1_6 , UART_2, 2},
|
||||
{P2_3 , UART_3, 1},
|
||||
{P2_11, UART_4, 1},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
static uint32_t serial_irq_ids[UART_NUM] = {0};
|
||||
static uart_irq_handler irq_handler;
|
||||
|
||||
int stdio_uart_inited = 0;
|
||||
serial_t stdio_uart;
|
||||
|
||||
void serial_init(serial_t *obj, PinName tx, PinName rx) {
|
||||
int is_stdio_uart = 0;
|
||||
|
||||
// determine the UART to use
|
||||
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
|
||||
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
|
||||
UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
|
||||
if ((int)uart == NC) {
|
||||
error("Serial pinout mapping failed");
|
||||
}
|
||||
|
||||
obj->uart = (LPC_USART0_Type *)uart;
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<12) | (1<<20) | (1<<21) | (1<<22));
|
||||
|
||||
// [TODO] Consider more elegant approach
|
||||
// disconnect USBTX/RX mapping mux, for case when switching ports
|
||||
#ifdef USBTX
|
||||
pin_function(USBTX, 0);
|
||||
pin_function(USBRX, 0);
|
||||
#endif
|
||||
|
||||
// enable fifos and default rx trigger level
|
||||
obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
|
||||
| 0 << 1 // Rx Fifo Clear
|
||||
| 0 << 2 // Tx Fifo Clear
|
||||
| 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
|
||||
|
||||
// disable irqs
|
||||
obj->uart->IER = 0 << 0 // Rx Data available irq enable
|
||||
| 0 << 1 // Tx Fifo empty irq enable
|
||||
| 0 << 2; // Rx Line Status irq enable
|
||||
|
||||
// set default baud rate and format
|
||||
serial_baud (obj, 9600);
|
||||
serial_format(obj, 8, ParityNone, 1);
|
||||
|
||||
// pinout the chosen uart
|
||||
pinmap_pinout(tx, PinMap_UART_TX);
|
||||
pinmap_pinout(rx, PinMap_UART_RX);
|
||||
|
||||
// set rx/tx pins in PullUp mode
|
||||
pin_mode(tx, PullUp);
|
||||
pin_mode(rx, PullUp);
|
||||
|
||||
switch (uart) {
|
||||
case UART_0: obj->index = 0; break;
|
||||
case UART_1: obj->index = 1; break;
|
||||
case UART_2: obj->index = 2; break;
|
||||
case UART_3: obj->index = 3; break;
|
||||
case UART_4: obj->index = 4; break;
|
||||
}
|
||||
|
||||
is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
|
||||
|
||||
if (is_stdio_uart) {
|
||||
stdio_uart_inited = 1;
|
||||
memcpy(&stdio_uart, obj, sizeof(serial_t));
|
||||
}
|
||||
}
|
||||
|
||||
void serial_free(serial_t *obj) {
|
||||
serial_irq_ids[obj->index] = 0;
|
||||
}
|
||||
|
||||
// serial_baud
|
||||
// set the baud rate, taking in to account the current SystemFrequency
|
||||
void serial_baud(serial_t *obj, int baudrate) {
|
||||
LPC_SYSCON->USART0CLKDIV = 0x1;
|
||||
#warning "[TODO] This should be fixed to handle system core clock correctly."
|
||||
uint32_t PCLK = 12000000; //SystemCoreClock;
|
||||
// First we check to see if the basic divide with no DivAddVal/MulVal
|
||||
// ratio gives us an integer result. If it does, we set DivAddVal = 0,
|
||||
// MulVal = 1. Otherwise, we search the valid ratio value range to find
|
||||
// the closest match. This could be more elegant, using search methods
|
||||
// and/or lookup tables, but the brute force method is not that much
|
||||
// slower, and is more maintainable.
|
||||
uint16_t DL = PCLK / (16 * baudrate);
|
||||
|
||||
uint8_t DivAddVal = 0;
|
||||
uint8_t MulVal = 1;
|
||||
int hit = 0;
|
||||
uint16_t dlv;
|
||||
uint8_t mv, dav;
|
||||
if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder
|
||||
int err_best = baudrate, b;
|
||||
for (mv = 1; mv < 16 && !hit; mv++)
|
||||
{
|
||||
for (dav = 0; dav < mv; dav++)
|
||||
{
|
||||
// baudrate = PCLK / (16 * dlv * (1 + (DivAdd / Mul))
|
||||
// solving for dlv, we get dlv = mul * PCLK / (16 * baudrate * (divadd + mul))
|
||||
// mul has 4 bits, PCLK has 27 so we have 1 bit headroom which can be used for rounding
|
||||
// for many values of mul and PCLK we have 2 or more bits of headroom which can be used to improve precision
|
||||
// note: X / 32 doesn't round correctly. Instead, we use ((X / 16) + 1) / 2 for correct rounding
|
||||
|
||||
if ((mv * PCLK * 2) & 0x80000000) // 1 bit headroom
|
||||
dlv = ((((2 * mv * PCLK) / (baudrate * (dav + mv))) / 16) + 1) / 2;
|
||||
else // 2 bits headroom, use more precision
|
||||
dlv = ((((4 * mv * PCLK) / (baudrate * (dav + mv))) / 32) + 1) / 2;
|
||||
|
||||
// datasheet says if DLL==DLM==0, then 1 is used instead since divide by zero is ungood
|
||||
if (dlv == 0)
|
||||
dlv = 1;
|
||||
|
||||
// datasheet says if dav > 0 then DL must be >= 2
|
||||
if ((dav > 0) && (dlv < 2))
|
||||
dlv = 2;
|
||||
|
||||
// integer rearrangement of the baudrate equation (with rounding)
|
||||
b = ((PCLK * mv / (dlv * (dav + mv) * 8)) + 1) / 2;
|
||||
|
||||
// check to see how we went
|
||||
b = abs(b - baudrate);
|
||||
if (b < err_best)
|
||||
{
|
||||
err_best = b;
|
||||
|
||||
DL = dlv;
|
||||
MulVal = mv;
|
||||
DivAddVal = dav;
|
||||
|
||||
if (b == baudrate)
|
||||
{
|
||||
hit = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// set LCR[DLAB] to enable writing to divider registers
|
||||
obj->uart->LCR |= (1 << 7);
|
||||
|
||||
// set divider values
|
||||
obj->uart->DLM = (DL >> 8) & 0xFF;
|
||||
obj->uart->DLL = (DL >> 0) & 0xFF;
|
||||
obj->uart->FDR = (uint32_t) DivAddVal << 0
|
||||
| (uint32_t) MulVal << 4;
|
||||
|
||||
// clear LCR[DLAB]
|
||||
obj->uart->LCR &= ~(1 << 7);
|
||||
}
|
||||
|
||||
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
|
||||
// 0: 1 stop bits, 1: 2 stop bits
|
||||
if (stop_bits != 1 && stop_bits != 2) {
|
||||
error("Invalid stop bits specified");
|
||||
}
|
||||
stop_bits -= 1;
|
||||
|
||||
// 0: 5 data bits ... 3: 8 data bits
|
||||
if (data_bits < 5 || data_bits > 8) {
|
||||
error("Invalid number of bits (%d) in serial format, should be 5..8", data_bits);
|
||||
}
|
||||
data_bits -= 5;
|
||||
|
||||
int parity_enable, parity_select;
|
||||
switch (parity) {
|
||||
case ParityNone: parity_enable = 0; parity_select = 0; break;
|
||||
case ParityOdd : parity_enable = 1; parity_select = 0; break;
|
||||
case ParityEven: parity_enable = 1; parity_select = 1; break;
|
||||
case ParityForced1: parity_enable = 1; parity_select = 2; break;
|
||||
case ParityForced0: parity_enable = 1; parity_select = 3; break;
|
||||
default:
|
||||
error("Invalid serial parity setting");
|
||||
return;
|
||||
}
|
||||
|
||||
obj->uart->LCR = data_bits << 0
|
||||
| stop_bits << 2
|
||||
| parity_enable << 3
|
||||
| parity_select << 4;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* INTERRUPTS HANDLING
|
||||
******************************************************************************/
|
||||
static inline void uart_irq(uint32_t iir, uint32_t index) {
|
||||
// [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
|
||||
SerialIrq irq_type;
|
||||
switch (iir) {
|
||||
case 1: irq_type = TxIrq; break;
|
||||
case 2: irq_type = RxIrq; break;
|
||||
default: return;
|
||||
}
|
||||
|
||||
if (serial_irq_ids[index] != 0)
|
||||
irq_handler(serial_irq_ids[index], irq_type);
|
||||
}
|
||||
|
||||
void uart0_irq()
|
||||
{
|
||||
uart_irq((LPC_USART0->IIR >> 1) & 0x7, 0);
|
||||
}
|
||||
|
||||
void uart1_irq()
|
||||
{
|
||||
//uart_irq((LPC_USART4->IIR >> 1) & 0x7, 1);
|
||||
}
|
||||
|
||||
void uart2_irq()
|
||||
{
|
||||
//uart_irq((LPC_USART4->IIR >> 1) & 0x7, 2);
|
||||
}
|
||||
|
||||
void uart3_irq()
|
||||
{
|
||||
//uart_irq((LPC_USART4->IIR >> 1) & 0x7, 3);
|
||||
}
|
||||
|
||||
void uart4_irq()
|
||||
{
|
||||
//uart_irq((LPC_USART4->IIR >> 1) & 0x7, 4);
|
||||
}
|
||||
|
||||
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
|
||||
irq_handler = handler;
|
||||
serial_irq_ids[obj->index] = id;
|
||||
}
|
||||
|
||||
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
|
||||
IRQn_Type irq_n = (IRQn_Type)0;
|
||||
uint32_t vector = 0;
|
||||
switch ((int)obj->uart) {
|
||||
case UART_0: irq_n = USART0_IRQn; vector = (uint32_t)&uart0_irq; break;
|
||||
case UART_1: irq_n = USART1_4_IRQn; vector = (uint32_t)&uart1_irq; break;
|
||||
case UART_2: irq_n = USART2_3_IRQn; vector = (uint32_t)&uart2_irq; break;
|
||||
case UART_3: irq_n = USART2_3_IRQn; vector = (uint32_t)&uart3_irq; break;
|
||||
case UART_4: irq_n = USART1_4_IRQn; vector = (uint32_t)&uart4_irq; break;
|
||||
}
|
||||
|
||||
if (enable) {
|
||||
obj->uart->IER |= (1 << irq);
|
||||
NVIC_SetVector(irq_n, vector);
|
||||
NVIC_EnableIRQ(irq_n);
|
||||
} else { // disable
|
||||
int all_disabled = 0;
|
||||
SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
|
||||
|
||||
obj->uart->IER &= ~(1 << irq);
|
||||
all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
|
||||
|
||||
if (all_disabled)
|
||||
NVIC_DisableIRQ(irq_n);
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* READ/WRITE
|
||||
******************************************************************************/
|
||||
int serial_getc(serial_t *obj) {
|
||||
while (!serial_readable(obj));
|
||||
return obj->uart->RBR;
|
||||
}
|
||||
|
||||
void serial_putc(serial_t *obj, int c) {
|
||||
while (!serial_writable(obj));
|
||||
obj->uart->THR = c;
|
||||
}
|
||||
|
||||
int serial_readable(serial_t *obj) {
|
||||
return obj->uart->LSR & 0x01;
|
||||
}
|
||||
|
||||
int serial_writable(serial_t *obj) {
|
||||
return obj->uart->LSR & 0x20;
|
||||
}
|
||||
|
||||
void serial_clear(serial_t *obj) {
|
||||
obj->uart->FCR = 1 << 1 // rx FIFO reset
|
||||
| 1 << 2 // tx FIFO reset
|
||||
| 0 << 6; // interrupt depth
|
||||
}
|
||||
|
||||
void serial_pinout_tx(PinName tx) {
|
||||
pinmap_pinout(tx, PinMap_UART_TX);
|
||||
}
|
||||
|
||||
void serial_break_set(serial_t *obj) {
|
||||
obj->uart->LCR |= (1 << 6);
|
||||
}
|
||||
|
||||
void serial_break_clear(serial_t *obj) {
|
||||
obj->uart->LCR &= ~(1 << 6);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,226 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <math.h>
|
||||
|
||||
#include "spi_api.h"
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
#include "error.h"
|
||||
|
||||
#if DEVICE_SPI
|
||||
|
||||
static const PinMap PinMap_SPI_SCLK[] = {
|
||||
{P0_6 , SPI_0, 0x02},
|
||||
{P1_29, SPI_0, 0x01},
|
||||
{P2_7 , SPI_0, 0x01},
|
||||
{P1_20, SPI_1, 0x02},
|
||||
{P1_27, SPI_1, 0x04},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_SPI_MOSI[] = {
|
||||
{P0_9 , SPI_0, 0x01},
|
||||
{P1_12, SPI_0, 0x01},
|
||||
{P0_21, SPI_1, 0x02},
|
||||
{P1_22, SPI_1, 0x01},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_SPI_MISO[] = {
|
||||
{P0_8 , SPI_0, 0x01},
|
||||
{P1_16, SPI_0, 0x01},
|
||||
{P0_22, SPI_1, 0x03},
|
||||
{P1_21, SPI_1, 0x02},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_SPI_SSEL[] = {
|
||||
{P0_2 , SPI_0, 0x01},
|
||||
{P1_15, SPI_0, 0x01},
|
||||
{P0_23, SPI_1, 0x04},
|
||||
{P1_23, SPI_1, 0x02},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
static inline int ssp_disable(spi_t *obj);
|
||||
static inline int ssp_enable(spi_t *obj);
|
||||
|
||||
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
|
||||
// determine the SPI to use
|
||||
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
|
||||
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
|
||||
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
|
||||
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
|
||||
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
|
||||
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
|
||||
|
||||
obj->spi = (LPC_SSP0_Type*)pinmap_merge(spi_data, spi_cntl);
|
||||
|
||||
if ((int)obj->spi == NC) {
|
||||
error("SPI pinout mapping failed");
|
||||
}
|
||||
|
||||
// enable power and clocking
|
||||
switch ((int)obj->spi) {
|
||||
case SPI_0:
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11;
|
||||
LPC_SYSCON->SSP0CLKDIV = 0x01;
|
||||
LPC_SYSCON->PRESETCTRL |= 1 << 0;
|
||||
break;
|
||||
case SPI_1:
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18;
|
||||
LPC_SYSCON->SSP1CLKDIV = 0x01;
|
||||
LPC_SYSCON->PRESETCTRL |= 1 << 2;
|
||||
break;
|
||||
}
|
||||
|
||||
// set default format and frequency
|
||||
if (ssel == NC) {
|
||||
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
|
||||
} else {
|
||||
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
|
||||
}
|
||||
spi_frequency(obj, 1000000);
|
||||
|
||||
// enable the ssp channel
|
||||
ssp_enable(obj);
|
||||
|
||||
// pin out the spi pins
|
||||
pinmap_pinout(mosi, PinMap_SPI_MOSI);
|
||||
pinmap_pinout(miso, PinMap_SPI_MISO);
|
||||
pinmap_pinout(sclk, PinMap_SPI_SCLK);
|
||||
if (ssel != NC) {
|
||||
pinmap_pinout(ssel, PinMap_SPI_SSEL);
|
||||
}
|
||||
}
|
||||
|
||||
void spi_free(spi_t *obj) {}
|
||||
|
||||
void spi_format(spi_t *obj, int bits, int mode, int slave) {
|
||||
ssp_disable(obj);
|
||||
|
||||
if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
|
||||
error("SPI format error");
|
||||
}
|
||||
|
||||
int polarity = (mode & 0x2) ? 1 : 0;
|
||||
int phase = (mode & 0x1) ? 1 : 0;
|
||||
|
||||
// set it up
|
||||
int DSS = bits - 1; // DSS (data select size)
|
||||
int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
|
||||
int SPH = (phase) ? 1 : 0; // SPH - clock out phase
|
||||
|
||||
int FRF = 0; // FRF (frame format) = SPI
|
||||
uint32_t tmp = obj->spi->CR0;
|
||||
tmp &= ~(0xFFFF);
|
||||
tmp |= DSS << 0
|
||||
| FRF << 4
|
||||
| SPO << 6
|
||||
| SPH << 7;
|
||||
obj->spi->CR0 = tmp;
|
||||
|
||||
tmp = obj->spi->CR1;
|
||||
tmp &= ~(0xD);
|
||||
tmp |= 0 << 0 // LBM - loop back mode - off
|
||||
| ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
|
||||
| 0 << 3; // SOD - slave output disable - na
|
||||
obj->spi->CR1 = tmp;
|
||||
|
||||
ssp_enable(obj);
|
||||
}
|
||||
|
||||
void spi_frequency(spi_t *obj, int hz) {
|
||||
ssp_disable(obj);
|
||||
|
||||
uint32_t PCLK = SystemCoreClock;
|
||||
|
||||
int prescaler;
|
||||
|
||||
for (prescaler = 2; prescaler <= 254; prescaler += 2) {
|
||||
int prescale_hz = PCLK / prescaler;
|
||||
|
||||
// calculate the divider
|
||||
int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
|
||||
|
||||
// check we can support the divider
|
||||
if (divider < 256) {
|
||||
// prescaler
|
||||
obj->spi->CPSR = prescaler;
|
||||
|
||||
// divider
|
||||
obj->spi->CR0 &= ~(0xFFFF << 8);
|
||||
obj->spi->CR0 |= (divider - 1) << 8;
|
||||
ssp_enable(obj);
|
||||
return;
|
||||
}
|
||||
}
|
||||
error("Couldn't setup requested SPI frequency");
|
||||
}
|
||||
|
||||
static inline int ssp_disable(spi_t *obj) {
|
||||
return obj->spi->CR1 &= ~(1 << 1);
|
||||
}
|
||||
|
||||
static inline int ssp_enable(spi_t *obj) {
|
||||
return obj->spi->CR1 |= (1 << 1);
|
||||
}
|
||||
|
||||
static inline int ssp_readable(spi_t *obj) {
|
||||
return obj->spi->SR & (1 << 2);
|
||||
}
|
||||
|
||||
static inline int ssp_writeable(spi_t *obj) {
|
||||
return obj->spi->SR & (1 << 1);
|
||||
}
|
||||
|
||||
static inline void ssp_write(spi_t *obj, int value) {
|
||||
while (!ssp_writeable(obj));
|
||||
obj->spi->DR = value;
|
||||
}
|
||||
|
||||
static inline int ssp_read(spi_t *obj) {
|
||||
while (!ssp_readable(obj));
|
||||
return obj->spi->DR;
|
||||
}
|
||||
|
||||
static inline int ssp_busy(spi_t *obj) {
|
||||
return (obj->spi->SR & (1 << 4)) ? (1) : (0);
|
||||
}
|
||||
|
||||
int spi_master_write(spi_t *obj, int value) {
|
||||
ssp_write(obj, value);
|
||||
return ssp_read(obj);
|
||||
}
|
||||
|
||||
int spi_slave_receive(spi_t *obj) {
|
||||
return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
|
||||
}
|
||||
|
||||
int spi_slave_read(spi_t *obj) {
|
||||
return obj->spi->DR;
|
||||
}
|
||||
|
||||
void spi_slave_write(spi_t *obj, int value) {
|
||||
while (ssp_writeable(obj) == 0) ;
|
||||
obj->spi->DR = value;
|
||||
}
|
||||
|
||||
int spi_busy(spi_t *obj) {
|
||||
return ssp_busy(obj);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <stddef.h>
|
||||
#include "us_ticker_api.h"
|
||||
#include "PeripheralNames.h"
|
||||
|
||||
#define US_TICKER_TIMER ((LPC_CT32B0_Type *)LPC_CT32B1_BASE)
|
||||
#define US_TICKER_TIMER_IRQn CT32B1_IRQn
|
||||
|
||||
int us_ticker_inited = 0;
|
||||
|
||||
void us_ticker_init(void) {
|
||||
if (us_ticker_inited) return;
|
||||
us_ticker_inited = 1;
|
||||
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10); // Clock CT32B1
|
||||
#warning "[TODO] this should read from SystemCoreClock grobal variable."
|
||||
uint32_t PCLK = 12000000;//SystemCoreClock;
|
||||
|
||||
US_TICKER_TIMER->TCR = 0x2; // reset
|
||||
|
||||
uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks)
|
||||
US_TICKER_TIMER->PR = prescale - 1;
|
||||
US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0
|
||||
|
||||
NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
|
||||
NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
|
||||
}
|
||||
|
||||
uint32_t us_ticker_read() {
|
||||
if (!us_ticker_inited)
|
||||
us_ticker_init();
|
||||
|
||||
return US_TICKER_TIMER->TC;
|
||||
}
|
||||
|
||||
void us_ticker_set_interrupt(unsigned int timestamp) {
|
||||
// set match value
|
||||
US_TICKER_TIMER->MR0 = timestamp;
|
||||
// enable match interrupt
|
||||
US_TICKER_TIMER->MCR |= 1;
|
||||
}
|
||||
|
||||
void us_ticker_disable_interrupt(void) {
|
||||
US_TICKER_TIMER->MCR &= ~1;
|
||||
}
|
||||
|
||||
void us_ticker_clear_interrupt(void) {
|
||||
US_TICKER_TIMER->IR = 1;
|
||||
}
|
||||
|
|
@ -144,8 +144,8 @@ void pwmout_period_us(pwmout_t* obj, int us) {
|
|||
uint32_t old_period_ticks = timer->MR3;
|
||||
|
||||
// for 16bit timer, set prescaler to avoid overflow
|
||||
uint16_t high_period_ticks = period_ticks >> 16;
|
||||
if ((high_period_ticks) && (timer == LPC_CT16B0 || timer == LPC_CT16B1)) {
|
||||
if (timer == LPC_CT16B0 || timer == LPC_CT16B1) {
|
||||
uint16_t high_period_ticks = period_ticks >> 16;
|
||||
timer->PR = high_period_ticks;
|
||||
period_ticks /= (high_period_ticks + 1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -42,10 +42,10 @@
|
|||
#define DEVICE_SERIAL 1
|
||||
|
||||
#define DEVICE_I2C 1
|
||||
#define DEVICE_I2CSLAVE 0
|
||||
#define DEVICE_I2CSLAVE 1
|
||||
|
||||
#define DEVICE_SPI 1
|
||||
#define DEVICE_SPISLAVE 0
|
||||
#define DEVICE_SPISLAVE 1
|
||||
|
||||
#define DEVICE_RTC 1
|
||||
|
||||
|
|
|
|||
|
|
@ -69,6 +69,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
|
|||
// Enable I2C clock
|
||||
if (obj->i2c == I2C_1) {
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
|
||||
RCC_I2CCLKConfig(RCC_I2C1CLK_SYSCLK);
|
||||
}
|
||||
if (obj->i2c == I2C_2) {
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE);
|
||||
|
|
@ -103,7 +104,7 @@ void i2c_frequency(i2c_t *obj, int hz) {
|
|||
* Fast Mode (up to 400 kHz)
|
||||
* Fast Mode Plus (up to 1 MHz)
|
||||
Below values obtained with:
|
||||
- I2C clock source = 8 MHz (HSI clock per default)
|
||||
- I2C clock source = 48 MHz (System Clock)
|
||||
- Analog filter delay = ON
|
||||
- Digital filter coefficient = 0
|
||||
- Rise time = 100 ns
|
||||
|
|
@ -111,16 +112,16 @@ void i2c_frequency(i2c_t *obj, int hz) {
|
|||
*/
|
||||
switch (hz) {
|
||||
case 100000:
|
||||
tim = 0x00201D2B; // Standard mode
|
||||
tim = 0x10805E89; // Standard mode
|
||||
break;
|
||||
case 200000:
|
||||
tim = 0x0010021E; // Fast Mode
|
||||
tim = 0x00905E82; // Fast Mode
|
||||
break;
|
||||
case 400000:
|
||||
tim = 0x0010020A; // Fast Mode
|
||||
tim = 0x00901850; // Fast Mode
|
||||
break;
|
||||
case 1000000:
|
||||
tim = 0x00100001; // Fast Mode Plus
|
||||
tim = 0x00700818; // Fast Mode Plus
|
||||
// Enable the Fast Mode Plus capability
|
||||
if (obj->i2c == I2C_1) {
|
||||
SYSCFG_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus_I2C1, ENABLE);
|
||||
|
|
@ -299,25 +300,19 @@ void i2c_slave_mode(i2c_t *obj, int enable_slave) {
|
|||
|
||||
int i2c_slave_receive(i2c_t *obj) {
|
||||
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
|
||||
int event = 0;
|
||||
int timeout;
|
||||
int event = NoData;
|
||||
|
||||
// Wait until address match
|
||||
timeout = FLAG_TIMEOUT;
|
||||
while (I2C_GetFlagStatus(i2c, I2C_ISR_ADDR) == RESET) {
|
||||
timeout--;
|
||||
if (timeout == 0) {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
if(I2C_GetFlagStatus(i2c, I2C_ISR_BUSY) == SET) {
|
||||
if(I2C_GetFlagStatus(i2c, I2C_ISR_ADDR) == SET) {
|
||||
// Check direction
|
||||
if (i2c->ISR & I2C_ISR_DIR) {
|
||||
if (I2C_GetFlagStatus(i2c, I2C_ISR_DIR) == SET) {
|
||||
event = ReadAddressed;
|
||||
}
|
||||
else event = WriteAddressed;
|
||||
// Clear adress match flag to generate an acknowledge
|
||||
i2c->ICR |= I2C_ICR_ADDRCF;
|
||||
|
||||
}
|
||||
}
|
||||
return event;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -238,6 +238,12 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL}
|
|||
#elif defined(TARGET_STM32F407) || defined(TARGET_F407VG)
|
||||
#define INITIAL_SP (0x20020000UL)
|
||||
|
||||
#elif defined(TARGET_LPC1549)
|
||||
#define INITIAL_SP (0x02009000UL)
|
||||
|
||||
#elif defined(TARGET_LPC11U68)
|
||||
#define INITIAL_SP (0x10004000UL)
|
||||
|
||||
#else
|
||||
#error "no target defined"
|
||||
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@
|
|||
// <i> Default: 6
|
||||
#ifndef OS_TASKCNT
|
||||
# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC1347) || defined(TARGET_K64F) \
|
||||
|| defined(TARGET_KL46Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC)
|
||||
|| defined(TARGET_KL46Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68)
|
||||
# define OS_TASKCNT 14
|
||||
# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPC1114) \
|
||||
|| defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8)
|
||||
|
|
@ -63,7 +63,7 @@
|
|||
// <o>Scheduler (+ interrupts) stack size [bytes] <64-4096:8><#/4>
|
||||
#ifndef OS_SCHEDULERSTKSIZE
|
||||
# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC1347) || defined(TARGET_K64F) \
|
||||
|| defined(TARGET_KL46Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC)
|
||||
|| defined(TARGET_KL46Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68)
|
||||
# define OS_SCHEDULERSTKSIZE 256
|
||||
# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPC1114) \
|
||||
|| defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8)
|
||||
|
|
@ -112,10 +112,10 @@
|
|||
# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
|
||||
# define OS_CLOCK 96000000
|
||||
|
||||
# elif defined(TARGET_LPC1347) || defined(TARGET_STM32F303VC)
|
||||
# elif defined(TARGET_LPC1347) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549)
|
||||
# define OS_CLOCK 72000000
|
||||
|
||||
# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPC1114) || defined(TARGET_KL25Z) || defined(TARGET_KL46Z) || defined(TARGET_STM32F051R8)
|
||||
# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPC1114) || defined(TARGET_KL25Z) || defined(TARGET_KL46Z) || defined(TARGET_STM32F051R8) || defined(TARGET_LPC11U68)
|
||||
# define OS_CLOCK 48000000
|
||||
|
||||
# elif defined(TARGET_LPC812)
|
||||
|
|
|
|||
|
|
@ -526,7 +526,20 @@ class LPC1549(Target):
|
|||
|
||||
self.supported_form_factors = ["ARDUINO"]
|
||||
|
||||
|
||||
class LPC11U68(Target):
|
||||
ONLINE_TOOLCHAIN = "uARM"
|
||||
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
self.core = "Cortex-M0+"
|
||||
|
||||
self.extra_labels = ['NXP', 'LPC11U6X']
|
||||
|
||||
self.supported_toolchains = ["uARM"]
|
||||
|
||||
|
||||
class DISCO_F100RB(Target):
|
||||
ONLINE_TOOLCHAIN = "uARM"
|
||||
OUTPUT_NAMING = "8.3"
|
||||
|
|
@ -611,6 +624,7 @@ TARGETS = [
|
|||
NRF51822(),
|
||||
UBLOX_C027(),
|
||||
LPC1549(),
|
||||
LPC11U68(),
|
||||
DISCO_F100RB(),
|
||||
DISCO_F051R8(),
|
||||
DISCO_F407VG(),
|
||||
|
|
|
|||
Loading…
Reference in New Issue