From e270779ae1b5fccf20a36125dfd2fb5368664b14 Mon Sep 17 00:00:00 2001 From: Wim Date: Wed, 11 Feb 2015 19:35:44 +0100 Subject: [PATCH 01/36] Update us_ticker.c Using MRT instead of SCT, needed to free up SCT for PWM Code ported from LPC824 libs --- .../hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c | 120 ++++++++++-------- 1 file changed, 66 insertions(+), 54 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c index c1d1a1c10e..b4fb2001e2 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c @@ -17,77 +17,89 @@ #include "us_ticker_api.h" #include "PeripheralNames.h" -#define US_TICKER_TIMER_IRQn SCT_IRQn +//New, using MRT instead of SCT, needed to free up SCT for PWM +//Ported from LPC824 libs +static int us_ticker_inited = 0; +static int ticker_expired = 0; +int MRT_Clock_MHz; -int us_ticker_inited = 0; +#define US_TICKER_TIMER_IRQn MRT_IRQn void us_ticker_init(void) { - if (us_ticker_inited) return; + + if (us_ticker_inited) + return; + us_ticker_inited = 1; + + // Calculate MRT clock value (MRT has no prescaler) + MRT_Clock_MHz = (SystemCoreClock / 1000000); + + // Enable the MRT clock + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); + + // Clear peripheral reset the MRT + LPC_SYSCON->PRESETCTRL |= (1 << 7); + + // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit) + LPC_MRT->INTVAL0 = 0xFFFFFFFFUL; + // Enable Ch0 interrupt, Mode 0 is Repeat Interrupt + LPC_MRT->CTRL0 = (0x0 << 1) | (0x1 << 0); + + // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit) + LPC_MRT->INTVAL1 = 0x80000000UL; + // Disable ch1 interrupt, Mode 0 is Repeat Interrupt + LPC_MRT->CTRL1 = (0x0 << 1) | (0x0 << 0); - // Enable the SCT clock - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); - - // Clear peripheral reset the SCT: - LPC_SYSCON->PRESETCTRL |= (1 << 8); - - // Unified counter (32 bits) - LPC_SCT->CONFIG |= 1; - - // halt and clear the counter - LPC_SCT->CTRL_L |= (1 << 2) | (1 << 3); - - // System Clock (12)MHz -> us_ticker (1)MHz - LPC_SCT->CTRL_L |= ((SystemCoreClock/1000000 - 1) << 5); - - // unhalt the counter: - // - clearing bit 2 of the CTRL register - LPC_SCT->CTRL_L &= ~(1 << 2); - + // Set MRT interrupt vector NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); } +//TIMER0 is used for us ticker and timers (Timer, wait(), wait_us() etc) uint32_t us_ticker_read() { + if (!us_ticker_inited) us_ticker_init(); - - return LPC_SCT->COUNT_U; + + // Generate ticker value + // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer + // Calculate expected value using number of expired times to mimic a 32bit timer @ 1 MHz + return (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_Clock_MHz + (ticker_expired * (0x80000000UL/MRT_Clock_MHz)); } +//TIMER1 is used for Timestamped interrupts (Ticker(), Timeout()) void us_ticker_set_interrupt(timestamp_t timestamp) { - // halt the counter: - // - setting bit 2 of the CTRL register - LPC_SCT->CTRL_L |= (1 << 2); - // set timestamp in compare register - LPC_SCT->MATCH[0].U = (uint32_t)timestamp; + // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer + // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit) + // Note: The MRT has less counter headroom available than the typical mbed 32bit timer @ 1 MHz. + // The calculated counter interval until the next timestamp will be truncated and an + // 'early' interrupt will be generated in case the max required count interval exceeds + // the available 31 bits space. However, the mbed us_ticker interrupt handler will + // check current time against the next scheduled timestamp and simply re-issue the + // same interrupt again when needed. The calculated counter interval will now be smaller. + LPC_MRT->INTVAL1 = (((timestamp - us_ticker_read()) * MRT_Clock_MHz) | 0x80000000UL); - // unhalt the counter: - // - clearing bit 2 of the CTRL register - LPC_SCT->CTRL_L &= ~(1 << 2); + // Enable interrupt + LPC_MRT->CTRL1 |= 1; +} + +//Disable Timestamped interrupts triggered by TIMER1 +void us_ticker_disable_interrupt() { + //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock) + LPC_MRT->CTRL1 &= ~1; +} + +void us_ticker_clear_interrupt() { - // if events are not enabled, enable them - if (!(LPC_SCT->EVEN & 0x01)) { - - // comb mode = match only - LPC_SCT->EVENT[0].CTRL = (1 << 12); - - // ref manual: - // In simple applications that do not - // use states, write 0x01 to this - // register to enable an event - LPC_SCT->EVENT[0].STATE |= 0x1; - - // enable events - LPC_SCT->EVEN |= 0x1; + //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock) + if (LPC_MRT->STAT1 & 1) + LPC_MRT->STAT1 = 1; + + //Timer0 for us counter (31 bits downcounter @ SystemCoreClock) + if (LPC_MRT->STAT0 & 1) { + LPC_MRT->STAT0 = 1; + ticker_expired++; } } - -void us_ticker_disable_interrupt(void) { - LPC_SCT->EVEN &= ~1; -} - -void us_ticker_clear_interrupt(void) { - LPC_SCT->EVFLAG = 1; -} From d9bd50c37e8b0c62bd50c49b04ce2927f78f2d24 Mon Sep 17 00:00:00 2001 From: Wim Date: Wed, 11 Feb 2015 19:47:04 +0100 Subject: [PATCH 02/36] Create pwmout_api.c Added PWM support for the LPC812 using the SCT. Code was ported from LPC824 libs. First needed to modify us_ticker() to free up the SCT and use the MRT instead. PWM can support a maximum of 4 channels using any portpin. All channels will use the same period. --- .../hal/TARGET_NXP/TARGET_LPC81X/pwmout_api.c | 226 ++++++++++++++++++ 1 file changed, 226 insertions(+) create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/pwmout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/pwmout_api.c new file mode 100644 index 0000000000..7866df5629 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/pwmout_api.c @@ -0,0 +1,226 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pwmout_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" + +// Ported from LPC824 and adapted. + +#if DEVICE_PWMOUT + +#define PWM_IRQn SCT_IRQn + +// Bit flags for used SCT Outputs +static unsigned char sct_used = 0; +static int sct_inited = 0; + +// Find available output channel +// Max number of PWM outputs is 4 on LPC812 +static int get_available_sct() { + int i; + +// Find available output channel 0..3 +// Also need one Match register per channel + for (i = 0; i < CONFIG_SCT_nOU; i++) { +// for (i = 0; i < 4; i++) { + if ((sct_used & (1 << i)) == 0) + return i; + } + return -1; +} + +// Any Port pin may be used for PWM. +// Max number of PWM outputs is 4 +void pwmout_init(pwmout_t* obj, PinName pin) { + MBED_ASSERT(pin != (uint32_t)NC); + + int sct_n = get_available_sct(); + if (sct_n == -1) { + error("No available SCT Output"); + } + + sct_used |= (1 << sct_n); + + obj->pwm = (LPC_SCT_TypeDef*)LPC_SCT; + obj->pwm_ch = sct_n; + + LPC_SCT_TypeDef* pwm = obj->pwm; + + // Init SCT on first use + if (! sct_inited) { + sct_inited = 1; + + // Enable the SCT clock + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); + + // Clear peripheral reset the SCT: + LPC_SYSCON->PRESETCTRL |= (1 << 8); + + // Two 16-bit counters, autolimit (ie reset on Match_0) + pwm->CONFIG &= ~(0x1); + pwm->CONFIG |= (1 << 17); + + // halt and clear the counter + pwm->CTRL_L |= (1 << 2) | (1 << 3); + + // System Clock (30 Mhz) -> Prescaler -> us_ticker (1 MHz) + pwm->CTRL_L &= ~(0x7F << 5); + pwm->CTRL_L |= (((SystemCoreClock/1000000 - 1) & 0x7F) << 5); + + pwm->EVENT[0].CTRL = (1 << 12) | 0; // Event_0 on Match_0 + pwm->EVENT[0].STATE = 0xFFFFFFFF; // All states + + // unhalt the counter: + // - clearing bit 2 of the CTRL register + pwm->CTRL_L &= ~(1 << 2); + + // Not using IRQs + //NVIC_SetVector(PWM_IRQn, (uint32_t)pwm_irq_handler); + //NVIC_EnableIRQ(PWM_IRQn); + } + + // LPC81x has only one SCT and 4 Outputs + // LPC82x has only one SCT and 6 Outputs + // LPC1549 has 4 SCTs and 16 Outputs + switch(sct_n) { + case 0: + // SCTx_OUT0 + LPC_SWM->PINASSIGN[6] &= ~0xFF000000; + LPC_SWM->PINASSIGN[6] |= (pin << 24); + break; + case 1: + // SCTx_OUT1 + LPC_SWM->PINASSIGN[7] &= ~0x000000FF; + LPC_SWM->PINASSIGN[7] |= (pin); + break; + case 2: + // SCTx_OUT2 + LPC_SWM->PINASSIGN[7] &= ~0x0000FF00; + LPC_SWM->PINASSIGN[7] |= (pin << 8); + break; + case 3: + // SCTx_OUT3 + LPC_SWM->PINASSIGN[7] &= ~0x00FF0000; + LPC_SWM->PINASSIGN[7] |= (pin << 16); + break; + default: + break; + } + + pwm->EVENT[sct_n + 1].CTRL = (1 << 12) | (sct_n + 1); // Event_n on Match_n + pwm->EVENT[sct_n + 1].STATE = 0xFFFFFFFF; // All states + + pwm->OUT[sct_n].SET = (1 << 0); // All PWM channels are SET on Event_0 + pwm->OUT[sct_n].CLR = (1 << (sct_n + 1)); // PWM ch is CLRed on Event_(ch+1) + + // default to 20ms: standard for servos, and fine for e.g. brightness control + pwmout_period_ms(obj, 20); // 20ms period + pwmout_write (obj, 0.0); // 0ms pulsewidth, dutycycle 0 +} + +void pwmout_free(pwmout_t* obj) { + // PWM channel is now free + sct_used &= ~(1 << obj->pwm_ch); + + // Disable the SCT clock when all channels free + if (sct_used == 0) { + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8); + sct_inited = 0; + }; +} + +// Set new dutycycle (0.0 .. 1.0) +void pwmout_write(pwmout_t* obj, float value) { + //value is new dutycycle + if (value < 0.0f) { + value = 0.0; + } else if (value > 1.0f) { + value = 1.0; + } + + // Match_0 is PWM period. Compute new endtime of pulse for current channel + uint32_t t_off = (uint32_t)((float)(obj->pwm->MATCHREL[0].L) * value); + obj->pwm->MATCHREL[(obj->pwm_ch) + 1].L = t_off; // New endtime +} + +// Get dutycycle (0.0 .. 1.0) +float pwmout_read(pwmout_t* obj) { + uint32_t t_period = obj->pwm->MATCHREL[0].L; + + //Sanity check + if (t_period == 0) { + return 0.0; + }; + + uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch) + 1].L; + float v = (float)t_off/(float)t_period; + //Sanity check + return (v > 1.0f) ? (1.0f) : (v); +} + +// Set the PWM period, keeping the duty cycle the same (for this channel only!). +void pwmout_period(pwmout_t* obj, float seconds){ + pwmout_period_us(obj, seconds * 1000000.0f); +} + +// Set the PWM period, keeping the duty cycle the same (for this channel only!). +void pwmout_period_ms(pwmout_t* obj, int ms) { + pwmout_period_us(obj, ms * 1000); +} + +// Set the PWM period, keeping the duty cycle the same (for this channel only!). +void pwmout_period_us(pwmout_t* obj, int us) { + + uint32_t t_period = obj->pwm->MATCHREL[0].L; // Current PWM period + obj->pwm->MATCHREL[0].L = (uint64_t)us; // New PWM period + + //Keep the dutycycle for the new PWM period + //Should really do this for all active channels!! + //This problem exists in all mbed libs. + + //Sanity check + if (t_period == 0) { + return; +// obj->pwm->MATCHREL[(obj->pwm_ch) + 1].L = 0; // New endtime for this channel + } + else { + uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch) + 1].L; + float v = (float)t_off/(float)t_period; + obj->pwm->MATCHREL[(obj->pwm_ch) + 1].L = (uint64_t)((float)us * (float)v); // New endtime for this channel + } +} + + +//Set pulsewidth +void pwmout_pulsewidth(pwmout_t* obj, float seconds) { + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +//Set pulsewidth +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms){ + pwmout_pulsewidth_us(obj, ms * 1000); +} + +//Set pulsewidth +void pwmout_pulsewidth_us(pwmout_t* obj, int us) { + +//Should add Sanity check to make sure pulsewidth < period! + obj->pwm->MATCHREL[(obj->pwm_ch) + 1].L = (uint64_t)us; // New endtime for this channel +} + +#endif From 81e67758fac9c3029729ea5b2a20b9efbf34f107 Mon Sep 17 00:00:00 2001 From: Wim Date: Wed, 11 Feb 2015 19:52:20 +0100 Subject: [PATCH 03/36] Update device.h Activated the I2CSlave functions. Slave block read/write operations are fully supported. The slave byte read and writes need general modification to I2CSlave.cpp. See pending Issue. Activated the PWM functions. They are supported now using the SCT after updating us_ticker() to use the MRT instead of the SCT. --- libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/device.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/device.h index 4ee3403e37..491694096b 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/device.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/device.h @@ -29,7 +29,7 @@ #define DEVICE_SERIAL_FC 1 #define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 0 +#define DEVICE_I2CSLAVE 1 #define DEVICE_SPI 1 #define DEVICE_SPISLAVE 1 @@ -40,7 +40,7 @@ #define DEVICE_ETHERNET 0 -#define DEVICE_PWMOUT 0 +#define DEVICE_PWMOUT 1 #define DEVICE_SEMIHOST 0 #define DEVICE_LOCALFILESYSTEM 0 From 7bd12f26f759c2cbc9d97f9027d7bc98d8ba36ed Mon Sep 17 00:00:00 2001 From: Wim Date: Wed, 11 Feb 2015 22:37:15 +0100 Subject: [PATCH 04/36] Update LPC8xx.h Updated LPC_MRT_TypeDef for new us_ticker implementation on LPC812. --- .../cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h | 51 ++++++++++++++----- 1 file changed, 37 insertions(+), 14 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h index 4dcffe4496..a6df8ea120 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h @@ -368,23 +368,46 @@ typedef struct { /*!< (@ 0x40028000) WKT Structure } LPC_WKT_TypeDef; /*@}*/ /* end of group LPC8xx_WKT */ - /*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/ -typedef struct { -__IO uint32_t INTVAL; -__IO uint32_t TIMER; -__IO uint32_t CTRL; -__IO uint32_t STAT; -} MRT_Channel_cfg_Type; - -typedef struct { - MRT_Channel_cfg_Type Channel[4]; - uint32_t Reserved0[1]; - __IO uint32_t IDLE_CH; - __IO uint32_t IRQ_FLAG; +//New, Copied from lpc824 +/** + * @brief Multi-Rate Timer (MRT) (MRT) + */ +typedef struct { /*!< (@ 0x40004000) MRT Structure */ + __IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value + is loaded into the TIMER0 register. */ + __I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the + value of the down-counter. */ + __IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls + the MRT0 modes. */ + __IO uint32_t STAT0; /*!< (@ 0x4000400C) MRT0 Status register. */ + __IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value + is loaded into the TIMER0 register. */ + __I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the + value of the down-counter. */ + __IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls + the MRT0 modes. */ + __IO uint32_t STAT1; /*!< (@ 0x4000401C) MRT0 Status register. */ + __IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value + is loaded into the TIMER0 register. */ + __I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the + value of the down-counter. */ + __IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls + the MRT0 modes. */ + __IO uint32_t STAT2; /*!< (@ 0x4000402C) MRT0 Status register. */ + __IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value + is loaded into the TIMER0 register. */ + __I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the + value of the down-counter. */ + __IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls + the MRT0 modes. */ + __IO uint32_t STAT3; /*!< (@ 0x4000403C) MRT0 Status register. */ + __I uint32_t RESERVED0[45]; + __I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns + the number of the first idle channel. */ + __IO uint32_t IRQ_FLAG; /*!< (@ 0x400040F8) Global interrupt flag register */ } LPC_MRT_TypeDef; - /*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/ /** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter @{ From 2f2f4d67bcef076446bebe2d9258d8ac00d7a00b Mon Sep 17 00:00:00 2001 From: Wim Date: Wed, 11 Feb 2015 22:42:35 +0100 Subject: [PATCH 05/36] Update objects.h Added PWM object. --- .../mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/objects.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/objects.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/objects.h index 98c8053574..819420f9a5 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/objects.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/objects.h @@ -43,6 +43,11 @@ struct spi_s { unsigned char spi_n; }; +struct pwmout_s { + LPC_SCT_TypeDef* pwm; + uint32_t pwm_ch; +}; + #include "gpio_object.h" #ifdef __cplusplus From 9241e5eabadfbe2f47a02310135b7ba43da4a173 Mon Sep 17 00:00:00 2001 From: Wim Date: Thu, 19 Feb 2015 15:09:18 +0100 Subject: [PATCH 06/36] Update us_ticker.c Used precomputed variables to replace runtime mult and div in us_ticker_read(). --- .../hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c | 26 +++++++++++++++---- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c index b4fb2001e2..838b614be1 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c @@ -20,7 +20,8 @@ //New, using MRT instead of SCT, needed to free up SCT for PWM //Ported from LPC824 libs static int us_ticker_inited = 0; -static int ticker_expired = 0; +unsigned int ticker_fullcount_us; +unsigned long int ticker_expired_count_us = 0; int MRT_Clock_MHz; #define US_TICKER_TIMER_IRQn MRT_IRQn @@ -31,9 +32,11 @@ void us_ticker_init(void) { return; us_ticker_inited = 1; - + // Calculate MRT clock value (MRT has no prescaler) MRT_Clock_MHz = (SystemCoreClock / 1000000); + // Calculate fullcounter value in us (MRT has 31 bits and clock is 30 MHz) + ticker_fullcount_us = 0x80000000UL/MRT_Clock_MHz; // Enable the MRT clock LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); @@ -64,8 +67,18 @@ uint32_t us_ticker_read() { // Generate ticker value // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer - // Calculate expected value using number of expired times to mimic a 32bit timer @ 1 MHz - return (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_Clock_MHz + (ticker_expired * (0x80000000UL/MRT_Clock_MHz)); + // Calculate expected value using current count and number of expired times to mimic a 32bit timer @ 1 MHz + // + // ticker_expired_count_us + // The variable ticker_expired_count_us keeps track of the number of 31bits overflows (counted by TIMER0) and + // corrects that back to us counts. + // + // (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_Clock_MHz + // The counter is a 31bit downcounter from 7FFFFFFF so correct to actual count-up value and correct + // for 30 counts per us. + // + // Added up these 2 parts result in current us time returned as 32 bits. + return (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_Clock_MHz + ticker_expired_count_us; } //TIMER1 is used for Timestamped interrupts (Ticker(), Timeout()) @@ -100,6 +113,9 @@ void us_ticker_clear_interrupt() { //Timer0 for us counter (31 bits downcounter @ SystemCoreClock) if (LPC_MRT->STAT0 & 1) { LPC_MRT->STAT0 = 1; - ticker_expired++; + // ticker_expired_count_us = (ticker_expired * 0x80000000UL) / MRT_Clock_MHz + // The variable ticker_expired_count_us keeps track of the number of 31bits overflows (counted by TIMER0) and + // the multiplication/division corrects that back to us counts. + ticker_expired_count_us += ticker_fullcount_us; } } From 02cba63476938179d9f01db854f0bf591d163eb9 Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Fri, 20 Feb 2015 17:36:11 +0900 Subject: [PATCH 07/36] Increase private thread num. --- libraries/rtos/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c b/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c index adc5fae609..40482bf5e9 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c @@ -68,7 +68,7 @@ // Defines the number of threads with user-provided stack size. // Default: 0 #ifndef OS_PRIVCNT - #define OS_PRIVCNT 8 + #define OS_PRIVCNT 10 #endif // Total stack size [bytes] for threads with user-provided stack size <0-4096:8><#/4> From 1641dd7e8d32192c322872dfd265e5998771c7c3 Mon Sep 17 00:00:00 2001 From: mazgch Date: Fri, 20 Feb 2015 13:38:11 +0100 Subject: [PATCH 08/36] enable the additional uart 7&8 of the STM32F439 --- .../TARGET_UBLOX_C029/PeripheralNames.h | 4 +- .../TARGET_UBLOX_C029/PeripheralPins.c | 2 + .../TARGET_STM/TARGET_STM32F4/serial_api.c | 56 ++++++++++++++++++- 3 files changed, 59 insertions(+), 3 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h index c2de03ab09..47f03095d0 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h @@ -53,7 +53,9 @@ typedef enum { UART_3 = (int)USART3_BASE, UART_4 = (int)UART4_BASE, UART_5 = (int)UART5_BASE, - UART_6 = (int)USART6_BASE + UART_6 = (int)USART6_BASE, + UART_7 = (int)UART7_BASE, + UART_8 = (int)UART8_BASE } UARTName; #define STDIO_UART_TX PD_8 diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralPins.c index b139dafcc6..63720ea40b 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralPins.c @@ -133,12 +133,14 @@ const PinMap PinMap_PWM[] = { const PinMap PinMap_UART_TX[] = { {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, {NC, NC, 0} }; const PinMap PinMap_UART_RX[] = { {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, {NC, NC, 0} }; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/serial_api.c index 3a8535bf5f..c89d1e5302 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/serial_api.c @@ -37,9 +37,9 @@ #include #include "PeripheralPins.h" -#define UART_NUM (6) +#define UART_NUM (8) -static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0, 0, 0, 0}; +static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0, 0, 0, 0, 0, 0}; static uart_irq_handler irq_handler; @@ -111,6 +111,18 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) __USART6_CLK_ENABLE(); obj->index = 5; break; +#if defined(UART7_BASE) + case UART_7: + __UART7_CLK_ENABLE(); + obj->index = 6; + break; +#endif +#if defined(UART8_BASE) + case UART_8: + __UART8_CLK_ENABLE(); + obj->index = 7; + break; +#endif } // Configure the UART pins @@ -181,6 +193,20 @@ void serial_free(serial_t *obj) __USART6_RELEASE_RESET(); __USART6_CLK_DISABLE(); break; +#if defined(UART7_BASE) + case UART_7: + __UART7_FORCE_RESET(); + __UART7_RELEASE_RESET(); + __UART7_CLK_DISABLE(); + break; +#endif +#if defined(UART8_BASE) + case UART_8: + __UART8_FORCE_RESET(); + __UART8_RELEASE_RESET(); + __UART8_CLK_DISABLE(); + break; +#endif } // Configure GPIOs pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); @@ -281,6 +307,20 @@ static void uart6_irq(void) uart_irq(UART_6, 5); } +#if defined(UART7_BASE) +static void uart7_irq(void) +{ + uart_irq(UART_7, 6); +} +#endif + +#if defined(UART8_BASE) +static void uart8_irq(void) +{ + uart_irq(UART_8, 7); +} +#endif + void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { irq_handler = handler; @@ -326,6 +366,18 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) irq_n = USART6_IRQn; vector = (uint32_t)&uart6_irq; break; +#if defined(UART7_BASE) + case UART_7: + irq_n = UART7_IRQn; + vector = (uint32_t)&uart7_irq; + break; +#endif +#if defined(UART8_BASE) + case UART_8: + irq_n = UART8_IRQn; + vector = (uint32_t)&uart8_irq; + break; +#endif } if (enable) { From 5c5bf71e1d98fa22c8e5ee41c81b0276eefe8560 Mon Sep 17 00:00:00 2001 From: GustavWi Date: Fri, 20 Feb 2015 15:59:16 +0100 Subject: [PATCH 09/36] Issue #910. Added debug file with predefined hardware debug settings. When user exports to IAR the project has all the necessary settings so the user can immediately flash the program --- workspace_tools/export/iar.py | 6 +- workspace_tools/export/iar_arch_pro.ewd.tmpl | 2733 +++++++++++++++++ workspace_tools/export/iar_k20d50m.ewd.tmpl | 1370 +++++++++ workspace_tools/export/iar_k22f.ewd.tmpl | 1370 +++++++++ workspace_tools/export/iar_k64f.ewd.tmpl | 1370 +++++++++ workspace_tools/export/iar_kl05z.ewd.tmpl | 1370 +++++++++ workspace_tools/export/iar_kl25z.ewd.tmpl | 1370 +++++++++ workspace_tools/export/iar_kl46z.ewd.tmpl | 1370 +++++++++ workspace_tools/export/iar_lpc1114.ewd.tmpl | 1370 +++++++++ workspace_tools/export/iar_lpc11u24.ewd.tmpl | 1370 +++++++++ .../export/iar_lpc11u35_401.ewd.tmpl | 1370 +++++++++ .../export/iar_lpc11u35_501.ewd.tmpl | 1370 +++++++++ workspace_tools/export/iar_lpc1347.ewd.tmpl | 1370 +++++++++ workspace_tools/export/iar_lpc1549.ewd.tmpl | 1370 +++++++++ workspace_tools/export/iar_lpc1768.ewd.tmpl | 2733 +++++++++++++++++ workspace_tools/export/iar_lpc4088.ewd.tmpl | 1370 +++++++++ .../export/iar_lpc4088_dm.ewd.tmpl | 1370 +++++++++ workspace_tools/export/iar_lpc812.ewd.tmpl | 1370 +++++++++ .../export/iar_mts_dragonfly_f411re.ewd.tmpl | 2733 +++++++++++++++++ .../export/iar_mts_dragonfly_f411re.ewp.tmpl | 8 +- .../export/iar_mts_mdot_f405re.ewd.tmpl | 2733 +++++++++++++++++ .../export/iar_mts_mdot_f411re.ewd.tmpl | 2733 +++++++++++++++++ workspace_tools/export/iar_nrf51822.ewd.tmpl | 1370 +++++++++ .../export/iar_nucleo_f030r8.ewd.tmpl | 2733 +++++++++++++++++ .../export/iar_nucleo_f070rb.ewd.tmpl | 2733 +++++++++++++++++ .../export/iar_nucleo_f072rb.ewd.tmpl | 2733 +++++++++++++++++ .../export/iar_nucleo_f091rc.ewd.tmpl | 2733 +++++++++++++++++ .../export/iar_nucleo_f103rb.ewd.tmpl | 1370 +++++++++ .../export/iar_nucleo_f302r8.ewd.tmpl | 2733 +++++++++++++++++ .../export/iar_nucleo_f303re.ewd.tmpl | 2733 +++++++++++++++++ .../export/iar_nucleo_f303re.ewp.tmpl | 4 +- .../export/iar_nucleo_f334r8.ewd.tmpl | 2733 +++++++++++++++++ .../export/iar_nucleo_f401re.ewd.tmpl | 2733 +++++++++++++++++ .../export/iar_nucleo_f401re.ewp.tmpl | 8 +- .../export/iar_nucleo_f411re.ewd.tmpl | 2733 +++++++++++++++++ .../export/iar_nucleo_l053r8.ewd.tmpl | 2733 +++++++++++++++++ .../export/iar_nucleo_l152re.ewd.tmpl | 2733 +++++++++++++++++ .../export/iar_ublox_c027.ewd.tmpl | 2733 +++++++++++++++++ 38 files changed, 69765 insertions(+), 12 deletions(-) create mode 100644 workspace_tools/export/iar_arch_pro.ewd.tmpl create mode 100644 workspace_tools/export/iar_k20d50m.ewd.tmpl create mode 100644 workspace_tools/export/iar_k22f.ewd.tmpl create mode 100644 workspace_tools/export/iar_k64f.ewd.tmpl create mode 100644 workspace_tools/export/iar_kl05z.ewd.tmpl create mode 100644 workspace_tools/export/iar_kl25z.ewd.tmpl create mode 100644 workspace_tools/export/iar_kl46z.ewd.tmpl create mode 100644 workspace_tools/export/iar_lpc1114.ewd.tmpl create mode 100644 workspace_tools/export/iar_lpc11u24.ewd.tmpl create mode 100644 workspace_tools/export/iar_lpc11u35_401.ewd.tmpl create mode 100644 workspace_tools/export/iar_lpc11u35_501.ewd.tmpl create mode 100644 workspace_tools/export/iar_lpc1347.ewd.tmpl create mode 100644 workspace_tools/export/iar_lpc1549.ewd.tmpl create mode 100644 workspace_tools/export/iar_lpc1768.ewd.tmpl create mode 100644 workspace_tools/export/iar_lpc4088.ewd.tmpl create mode 100644 workspace_tools/export/iar_lpc4088_dm.ewd.tmpl create mode 100644 workspace_tools/export/iar_lpc812.ewd.tmpl create mode 100644 workspace_tools/export/iar_mts_dragonfly_f411re.ewd.tmpl create mode 100644 workspace_tools/export/iar_mts_mdot_f405re.ewd.tmpl create mode 100644 workspace_tools/export/iar_mts_mdot_f411re.ewd.tmpl create mode 100644 workspace_tools/export/iar_nrf51822.ewd.tmpl create mode 100644 workspace_tools/export/iar_nucleo_f030r8.ewd.tmpl create mode 100644 workspace_tools/export/iar_nucleo_f070rb.ewd.tmpl create mode 100644 workspace_tools/export/iar_nucleo_f072rb.ewd.tmpl create mode 100644 workspace_tools/export/iar_nucleo_f091rc.ewd.tmpl create mode 100644 workspace_tools/export/iar_nucleo_f103rb.ewd.tmpl create mode 100644 workspace_tools/export/iar_nucleo_f302r8.ewd.tmpl create mode 100644 workspace_tools/export/iar_nucleo_f303re.ewd.tmpl create mode 100644 workspace_tools/export/iar_nucleo_f334r8.ewd.tmpl create mode 100644 workspace_tools/export/iar_nucleo_f401re.ewd.tmpl create mode 100644 workspace_tools/export/iar_nucleo_f411re.ewd.tmpl create mode 100644 workspace_tools/export/iar_nucleo_l053r8.ewd.tmpl create mode 100644 workspace_tools/export/iar_nucleo_l152re.ewd.tmpl create mode 100644 workspace_tools/export/iar_ublox_c027.ewd.tmpl diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py index 37abf2ecf3..ba96e80746 100644 --- a/workspace_tools/export/iar.py +++ b/workspace_tools/export/iar.py @@ -27,7 +27,8 @@ class IAREmbeddedWorkbench(Exporter): 'LPC11U24', 'LPC11U35_401', 'LPC11U35_501', - 'LPCCAPPUCCINO', + #Removed LPCCAPPUCCINO linker file and startup file missing + #'LPCCAPPUCCINO', 'LPC1114', 'LPC1549', 'LPC812', @@ -53,7 +54,7 @@ class IAREmbeddedWorkbench(Exporter): 'NUCLEO_F411RE', 'NUCLEO_L053R8', 'NUCLEO_L152RE', - 'STM32F407', + #'STM32F407', Fails to build same for GCC 'MTS_MDOT_F405RG', 'MTS_MDOT_F411RE', 'MTS_DRAGONFLY_F411RE', @@ -78,3 +79,4 @@ class IAREmbeddedWorkbench(Exporter): } self.gen_file('iar_%s.ewp.tmpl' % self.target.lower(), ctx, '%s.ewp' % self.program_name) self.gen_file('iar.eww.tmpl', ctx, '%s.eww' % self.program_name) + self.gen_file('iar_%s.ewd.tmpl' % self.target.lower(), ctx, '%s.ewd' % self.program_name) diff --git a/workspace_tools/export/iar_arch_pro.ewd.tmpl b/workspace_tools/export/iar_arch_pro.ewd.tmpl new file mode 100644 index 0000000000..baa751f071 --- /dev/null +++ b/workspace_tools/export/iar_arch_pro.ewd.tmpl @@ -0,0 +1,2733 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 26 + 1 + 1 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