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Merge pull request #4438 from 0xc0170/dev_realtek 

Add REALTEK_RTL8195AM to mbed-os
pull/2224/merge
Sam Grove 2017-06-04 08:34:26 -05:00 committed by GitHub
parent ebeb776de9 1fa30b7403
commit 273f653921
140 changed files with 39221 additions and 9 deletions
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38
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_Realtek/lwipopts_conf.h Normal file
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@ -0,0 +1,38 @@
/* Copyright (C) 2012 mbed.org, MIT License
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef LWIPOPTS_CONF_H
#define LWIPOPTS_CONF_H
#define LWIP_TRANSPORT_ETHERNET 1
#define ETHMEM_SECTIO
//#define TCPIP_THREAD_STACKSIZE 2048
/* ---------- Pbuf options ---------- */
#define MEM_SIZE (10*1600)
#define TCP_SND_QUEUELEN 60
#define MEMP_NUM_TCP_SEG TCP_SND_QUEUELEN
#define TCP_MSS 1460
#define TCP_SND_BUF (10 * TCP_MSS)
#define TCP_WND (6 * TCP_MSS)
#define PBUF_POOL_SIZE 10
#endif

16
features/filesystem/bd/MBRBlockDevice.cpp
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@ -38,16 +38,16 @@ MBED_PACKED(struct) mbr_table {
static inline uint32_t tole32(uint32_t a)
{
union {
uint32_t u32;
uint8_t u8[4];
} w;
uint32_t w;
uint8_t b[4];
} s;
w.u8[0] = a >> 0;
w.u8[1] = a >> 8;
w.u8[2] = a >> 16;
w.u8[3] = a >> 24;
s.b[0] = a >> 0;
s.b[1] = a >> 8;
s.b[2] = a >> 16;
s.b[3] = a >> 24;
return w.u32;
return s.w;
}
static inline uint32_t fromle32(uint32_t a)

284
targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp Normal file
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/* Ameba implementation of NetworkInterfaceAPI
* Copyright (c) 2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed.h"
#include "rtos.h"
#include "RTWInterface.h"
#include "mbed_interface.h"
#include "rtw_emac.h"
#include "wifi_constants.h"
#include "wifi_conf.h"
#include "lwip_stack.h"
#include "osdep_service.h"
typedef struct _wifi_scan_hdl {
void *scan_sema;
nsapi_size_t ap_num;
nsapi_size_t scan_num;
WiFiAccessPoint *ap_details;
} wifi_scan_hdl;
#define MAX_SCAN_TIMEOUT (15000)
static rtw_result_t scan_result_handler( rtw_scan_handler_result_t* malloced_scan_result )
{
wifi_scan_hdl *scan_handler = (wifi_scan_hdl *)malloced_scan_result->user_data;
if (malloced_scan_result->scan_complete != RTW_TRUE) {
if(scan_handler->ap_details && scan_handler->scan_num > scan_handler->ap_num){
nsapi_wifi_ap_t ap;
rtw_scan_result_t* record = &malloced_scan_result->ap_details;
record->SSID.val[record->SSID.len] = 0; /* Ensure the SSID is null terminated */
memset((void*)&ap, 0x00, sizeof(nsapi_wifi_ap_t));
memcpy(ap.ssid, record->SSID.val, record->SSID.len);
memcpy(ap.bssid, record->BSSID.octet, 6);
switch (record->security){
case RTW_SECURITY_OPEN:
ap.security = NSAPI_SECURITY_NONE;
break;
case RTW_SECURITY_WEP_PSK:
case RTW_SECURITY_WEP_SHARED:
ap.security = NSAPI_SECURITY_WEP;
break;
case RTW_SECURITY_WPA_TKIP_PSK:
case RTW_SECURITY_WPA_AES_PSK:
ap.security = NSAPI_SECURITY_WPA;
break;
case RTW_SECURITY_WPA2_AES_PSK:
case RTW_SECURITY_WPA2_TKIP_PSK:
case RTW_SECURITY_WPA2_MIXED_PSK:
ap.security = NSAPI_SECURITY_WPA2;
break;
case RTW_SECURITY_WPA_WPA2_MIXED:
ap.security = NSAPI_SECURITY_WPA_WPA2;
break;
default:
ap.security = NSAPI_SECURITY_UNKNOWN;
break;
}
ap.rssi = record->signal_strength;
ap.channel = record->channel;
WiFiAccessPoint *accesspoint = new WiFiAccessPoint(ap);
memcpy(&scan_handler->ap_details[scan_handler->ap_num], accesspoint, sizeof(WiFiAccessPoint));
delete[] accesspoint;
}
scan_handler->ap_num++;
} else{
// scan done
rtw_up_sema(&scan_handler->scan_sema);
}
return RTW_SUCCESS;
}
RTWInterface::RTWInterface()
: _dhcp(true), _ip_address(), _netmask(), _gateway()
{
emac_interface_t *emac;
int ret;
emac = wlan_emac_init_interface();
if (!emac) {
printf("Error init RTWInterface!\r\n");
return;
}
emac->ops.power_up(emac);
ret = mbed_lwip_init(emac);
if (ret != 0) {
printf("Error init RTWInterface!(%d)\r\n", ret);
return;
}
}
RTWInterface::~RTWInterface()
{
wlan_emac_link_change(false);
mbed_lwip_bringdown();
}
nsapi_error_t RTWInterface::set_network(const char *ip_address, const char *netmask, const char *gateway)
{
_dhcp = false;
strncpy(_ip_address, ip_address ? ip_address : "", sizeof(_ip_address));
strncpy(_netmask, netmask ? netmask : "", sizeof(_netmask));
strncpy(_gateway, gateway ? gateway : "", sizeof(_gateway));
return NSAPI_ERROR_OK;
}
nsapi_error_t RTWInterface::set_dhcp(bool dhcp)
{
_dhcp = dhcp;
return NSAPI_ERROR_OK;
}
/*
* we may call connect multiple times
*/
nsapi_error_t RTWInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security)
{
strncpy(_ssid, ssid, 255);
strncpy(_pass, pass, 255);
_security = security;
return NSAPI_ERROR_OK;
}
nsapi_error_t RTWInterface::connect()
{
int ret;
rtw_security_t sec;
if (!_ssid || (!_pass && _security != NSAPI_SECURITY_NONE)) {
printf("Invalid credentials\r\n");
return NSAPI_ERROR_PARAMETER;
}
switch (_security) {
case NSAPI_SECURITY_WPA:
case NSAPI_SECURITY_WPA2:
case NSAPI_SECURITY_WPA_WPA2:
sec = RTW_SECURITY_WPA_WPA2_MIXED;
break;
case NSAPI_SECURITY_WEP:
sec = RTW_SECURITY_WEP_PSK;
break;
case NSAPI_SECURITY_NONE:
sec = RTW_SECURITY_OPEN;
break;
default:
return NSAPI_ERROR_PARAMETER;
}
if(_channel > 0 && _channel < 14){
uint8_t pscan_config = PSCAN_ENABLE;
wifi_set_pscan_chan(&_channel, &pscan_config, 1);
}
ret = wifi_connect(_ssid, sec, _pass, strlen(_ssid), strlen(_pass), 0, (void *)NULL);
if (ret != RTW_SUCCESS) {
printf("failed: %d\r\n", ret);
return NSAPI_ERROR_NO_CONNECTION;
}
wlan_emac_link_change(true);
return mbed_lwip_bringup(_dhcp,
_ip_address[0] ? _ip_address : 0,
_netmask[0] ? _netmask : 0,
_gateway[0] ? _gateway : 0);
}
nsapi_error_t RTWInterface::scan(WiFiAccessPoint *res, unsigned count)
{
static wifi_scan_hdl scan_handler;
scan_handler.ap_num = 0;
if(!scan_handler.scan_sema)
rtw_init_sema(&scan_handler.scan_sema, 0);
scan_handler.scan_num = count;
scan_handler.ap_details = res;
if(wifi_scan_networks(scan_result_handler, (void *)&scan_handler) != RTW_SUCCESS){
printf("wifi scan failed\n\r");
return NSAPI_ERROR_DEVICE_ERROR;
}
if(rtw_down_timeout_sema( &scan_handler.scan_sema, MAX_SCAN_TIMEOUT ) == RTW_FALSE) {
printf("wifi scan timeout\r\n");
return NSAPI_ERROR_DEVICE_ERROR;
}
if(count <= 0 || count > scan_handler.ap_num)
count = scan_handler.ap_num;
return count;
}
nsapi_error_t RTWInterface::set_channel(uint8_t channel)
{
_channel = channel;
return NSAPI_ERROR_OK;
}
int8_t RTWInterface::get_rssi()
{
int rssi = 0;
if(wifi_get_rssi(&rssi) == 0)
return (int8_t)rssi;
return NSAPI_ERROR_OK;
}
nsapi_error_t RTWInterface::connect(const char *ssid, const char *pass,
nsapi_security_t security, uint8_t channel)
{
set_credentials(ssid, pass, security);
set_channel(channel);
return connect();
}
nsapi_error_t RTWInterface::disconnect()
{
char essid[33];
wlan_emac_link_change(false);
if(wifi_is_connected_to_ap() != RTW_SUCCESS)
return NSAPI_ERROR_NO_CONNECTION;
if(wifi_disconnect()<0){
return NSAPI_ERROR_DEVICE_ERROR;
}
while(1){
if(wext_get_ssid(WLAN0_NAME, (unsigned char *) essid) < 0) {
break;
}
}
return NSAPI_ERROR_OK;
}
int RTWInterface::is_connected()
{
// wifi_is_connected_to_ap return 0 on connected
return !wifi_is_connected_to_ap();
}
const char *RTWInterface::get_mac_address()
{
return mbed_lwip_get_mac_address();
}
const char *RTWInterface::get_ip_address()
{
if (mbed_lwip_get_ip_address(_ip_address, sizeof _ip_address)) {
return _ip_address;
}
return 0;
}
const char *RTWInterface::get_netmask()
{
if (mbed_lwip_get_netmask(_netmask, sizeof _netmask)) {
return _netmask;
}
return 0;
}
const char *RTWInterface::get_gateway()
{
if (mbed_lwip_get_gateway(_gateway, sizeof _gateway)) {
return _gateway;
}
return 0;
}
NetworkStack *RTWInterface::get_stack()
{
return nsapi_create_stack(&lwip_stack);
}

163
targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h Normal file
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/* Ameba implementation of NetworkInterfaceAPI
* Copyright (c) 2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef RTW_INTERFACE_H
#define RTW_INTERFACE_H
#include "netsocket/NetworkInterface.h"
#include "netsocket/WiFiInterface.h"
#include "nsapi.h"
#include "rtos.h"
#include "lwip/netif.h"
// Forward declaration
class NetworkStack;
/** Realtek Wlan (RTW) interface class
* Implementation of the NetworkStack for Ameba
*/
class RTWInterface: public WiFiInterface
{
public:
/** RTWWlanInterface lifetime
*/
RTWInterface();
~RTWInterface();
/** Set a static IP address
*
* Configures this network interface to use a static IP address.
* Implicitly disables DHCP, which can be enabled in set_dhcp.
* Requires that the network is disconnected.
*
* @param address Null-terminated representation of the local IP address
* @param netmask Null-terminated representation of the local network mask
* @param gateway Null-terminated representation of the local gateway
* @return 0 on success, negative error code on failure
*/
virtual nsapi_error_t set_network(const char *ip_address, const char *netmask, const char *gateway);
/** Enable or disable DHCP on the network
*
* Requires that the network is disconnected
*
* @param dhcp False to disable dhcp (defaults to enabled)
* @return 0 on success, negative error code on failure
*/
virtual nsapi_error_t set_dhcp(bool dhcp);
/** Set the WiFi network credentials
*
* @param ssid Name of the network to connect to
* @param pass Security passphrase to connect to the network
* @param security Type of encryption for connection
* (defaults to NSAPI_SECURITY_NONE)
* @return 0 on success, or error code on failure
*/
virtual nsapi_error_t set_credentials(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE);
/** Start the interface
*
* Attempts to connect to a WiFi network.
*
* @param ssid Name of the network to connect to
* @param pass Security passphrase to connect to the network
* @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE)
* @param channel Channel on which the connection is to be made, or 0 for any (Default: 0)
* @return 0 on success, or error code on failure
*/
virtual nsapi_error_t connect(const char *ssid, const char *pass,
nsapi_security_t security = NSAPI_SECURITY_NONE,
uint8_t channel = 0);
/** Start the interface
* @return 0 on success, negative on failure
*/
virtual nsapi_error_t connect();
/** Stop the interface
* @return 0 on success, negative on failure
*/
virtual nsapi_error_t disconnect();
virtual int is_connected();
/** Scan for available networks
*
* The scan will
* If the network interface is set to non-blocking mode, scan will attempt to scan
* for WiFi networks asynchronously and return NSAPI_ERROR_WOULD_BLOCK. If a callback
* is attached, the callback will be called when the operation has completed.
* @param ap Pointer to allocated array to store discovered AP
* @param count Size of allocated @a res array, or 0 to only count available AP
* @param timeout Timeout in milliseconds; 0 for no timeout (Default: 0)
* @return Number of entries in @a, or if @a count was 0 number of available networks, negative on error
* see @a nsapi_error
*/
virtual nsapi_size_or_error_t scan(WiFiAccessPoint *res, unsigned count);
virtual nsapi_error_t set_channel(uint8_t channel);
virtual int8_t get_rssi();
/** Get the local MAC address
*
* Provided MAC address is intended for info or debug purposes and
* may not be provided if the underlying network interface does not
* provide a MAC address
*
* @return Null-terminated representation of the local MAC address
* or null if no MAC address is available
*/
virtual const char *get_mac_address();
/** Get the local IP address
*
* @return Null-terminated representation of the local IP address
* or null if no IP address has been recieved
*/
virtual const char *get_ip_address();
/** Get the local network mask
*
* @return Null-terminated representation of the local network mask
* or null if no network mask has been recieved
*/
virtual const char *get_netmask();
/** Get the local gateways
*
* @return Null-terminated representation of the local gateway
* or null if no network mask has been recieved
*/
virtual const char *get_gateway();
protected:
/** Provide access to the underlying stack
*
* @return The underlying network stack
*/
virtual NetworkStack *get_stack();
bool _dhcp;
char _ssid[256];
char _pass[256];
nsapi_security_t _security;
uint8_t _channel;
char _ip_address[IPADDR_STRLEN_MAX];
char _netmask[NSAPI_IPv4_SIZE];
char _gateway[NSAPI_IPv4_SIZE];
};
#endif

42
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PeripheralNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
#define UART_3 3
#define STDIO_UART_TX PB_0
#define STDIO_UART_RX PB_1
#define STDIO_UART UART_3
typedef enum {
DAC_0 = 0,
DAC_1
} DACName;
#ifdef __cplusplus
}
#endif
#endif

235
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PinNames.h Normal file
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@ -0,0 +1,235 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _PINNAMES_H_
#define _PINNAMES_H_
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PORT_A = 0,
PORT_B = 1,
PORT_C = 2,
PORT_D = 3,
PORT_E = 4,
PORT_F = 5,
PORT_G = 6,
PORT_H = 7,
PORT_I = 8,
PORT_J = 9,
PORT_K = 10,
PORT_V = 11,
PORT_U = 12,
PORT_MAX
} GPIO_PORT;
#define RTL_PIN_PERI(FUN, IDX, SEL) ((int)(((FUN) << 8) | ((IDX)<<4) | (SEL)))
#define RTL_PIN_FUNC(FUN, SEL) ((int)(((FUN) << 7) | (SEL)))
#define RTL_GET_PERI_SEL(peri) ((int)((peri)&0x0F))
#define RTL_GET_PERI_IDX(peri) ((int)(((peri) >> 4)&0x0F))
typedef enum {
PIN_INPUT=0,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = (PORT_A<<4|0),
PA_1 = (PORT_A<<4|1),
PA_2 = (PORT_A<<4|2),
PA_3 = (PORT_A<<4|3),
PA_4 = (PORT_A<<4|4),
PA_5 = (PORT_A<<4|5),
PA_6 = (PORT_A<<4|6),
PA_7 = (PORT_A<<4|7),
PB_0 = (PORT_B<<4|0),
PB_1 = (PORT_B<<4|1),
PB_2 = (PORT_B<<4|2),
PB_3 = (PORT_B<<4|3),
PB_4 = (PORT_B<<4|4),
PB_5 = (PORT_B<<4|5),
PB_6 = (PORT_B<<4|6),
PB_7 = (PORT_B<<4|7),
PC_0 = (PORT_C<<4|0),
PC_1 = (PORT_C<<4|1),
PC_2 = (PORT_C<<4|2),
PC_3 = (PORT_C<<4|3),
PC_4 = (PORT_C<<4|4),
PC_5 = (PORT_C<<4|5),
PC_6 = (PORT_C<<4|6),
PC_7 = (PORT_C<<4|7),
PC_8 = (PORT_C<<4|8),
PC_9 = (PORT_C<<4|9),
PD_0 = (PORT_D<<4|0),
PD_1 = (PORT_D<<4|1),
PD_2 = (PORT_D<<4|2),
PD_3 = (PORT_D<<4|3),
PD_4 = (PORT_D<<4|4),
PD_5 = (PORT_D<<4|5),
PD_6 = (PORT_D<<4|6),
PD_7 = (PORT_D<<4|7),
PD_8 = (PORT_D<<4|8),
PD_9 = (PORT_D<<4|9),
PE_0 = (PORT_E<<4|0),
PE_1 = (PORT_E<<4|1),
PE_2 = (PORT_E<<4|2),
PE_3 = (PORT_E<<4|3),
PE_4 = (PORT_E<<4|4),
PE_5 = (PORT_E<<4|5),
PE_6 = (PORT_E<<4|6),
PE_7 = (PORT_E<<4|7),
PE_8 = (PORT_E<<4|8),
PE_9 = (PORT_E<<4|9),
PE_A = (PORT_E<<4|10),
PF_0 = (PORT_F<<4|0),
PF_1 = (PORT_F<<4|1),
PF_2 = (PORT_F<<4|2),
PF_3 = (PORT_F<<4|3),
PF_4 = (PORT_F<<4|4),
PF_5 = (PORT_F<<4|5),
/* unavailable pins */
// PF_6 = (PORT_F<<4|6),
// PF_7 = (PORT_F<<4|7),
PG_0 = (PORT_G<<4|0),
PG_1 = (PORT_G<<4|1),
PG_2 = (PORT_G<<4|2),
PG_3 = (PORT_G<<4|3),
PG_4 = (PORT_G<<4|4),
PG_5 = (PORT_G<<4|5),
PG_6 = (PORT_G<<4|6),
PG_7 = (PORT_G<<4|7),
PH_0 = (PORT_H<<4|0),
PH_1 = (PORT_H<<4|1),
PH_2 = (PORT_H<<4|2),
PH_3 = (PORT_H<<4|3),
PH_4 = (PORT_H<<4|4),
PH_5 = (PORT_H<<4|5),
PH_6 = (PORT_H<<4|6),
PH_7 = (PORT_H<<4|7),
PI_0 = (PORT_I<<4|0),
PI_1 = (PORT_I<<4|1),
PI_2 = (PORT_I<<4|2),
PI_3 = (PORT_I<<4|3),
PI_4 = (PORT_I<<4|4),
PI_5 = (PORT_I<<4|5),
PI_6 = (PORT_I<<4|6),
PI_7 = (PORT_I<<4|7),
PJ_0 = (PORT_J<<4|0),
PJ_1 = (PORT_J<<4|1),
PJ_2 = (PORT_J<<4|2),
PJ_3 = (PORT_J<<4|3),
PJ_4 = (PORT_J<<4|4),
PJ_5 = (PORT_J<<4|5),
PJ_6 = (PORT_J<<4|6),
/* unavailable pins */
// PJ_7 = (PORT_J<<4|7),
PK_0 = (PORT_K<<4|0),
PK_1 = (PORT_K<<4|1),
PK_2 = (PORT_K<<4|2),
PK_3 = (PORT_K<<4|3),
PK_4 = (PORT_K<<4|4),
PK_5 = (PORT_K<<4|5),
PK_6 = (PORT_K<<4|6),
/* unavailable pins */
// PK_7 = (PORT_K<<4|7),
AD_1 = (PORT_V<<4|1),
AD_2 = (PORT_V<<4|2),
AD_3 = (PORT_V<<4|3),
DA_0 = (PORT_U<<4|0),
DA_1 = (PORT_U<<4|1),
// Arduino connector namings
A0 = AD_2,//A0 and A1 are connected
A1 = AD_2,
A2 = AD_3,
D0 = PA_6,
D1 = PA_7,
D2 = PA_5,
D3 = PD_4,
D4 = PD_5,
D5 = PA_4,
D6 = PA_3,
D7 = PA_2,
D8 = PB_4,
D9 = PB_5,
D10 = PC_0,
D11 = PC_2,
D12 = PC_3,
D13 = PC_1,
D14 = PB_3,
D15 = PB_2,
D16 = PA_1,
D17 = PA_0,
D18 = PE_5,
// Generic signals namings
/* LED1~4 are defined as alias of GPIO pins, they are not the LEDs on board*/
LED1 = PB_4,
LED2 = PB_5,
LED3 = PB_6,
LED4 = PB_7,
SERIAL_TX = PA_7,
SERIAL_RX = PA_6,
USBTX = PB_0,
USBRX = PB_1,
I2C_SCL = PC_5,
I2C_SDA = PC_4,
SPI_MOSI = PC_2,
SPI_MISO = PC_3,
SPI_SCK = PC_1,
SPI_CS = PC_0,
PWM_OUT = PD_4,
// Not connected
NC = (uint32_t)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#define PORT_NUM(pin) (((uint32_t)(pin) >> 4) & 0xF)
#define PIN_NUM(pin) ((uint32_t)(pin) & 0xF)
#ifdef __cplusplus
}
#endif
#endif

38
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PortNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortE = 4,
PortF = 5,
PortG = 6,
PortH = 7,
PortI = 8
} PortName;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

BIN
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar Normal file
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BIN
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar Normal file
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45
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct Normal file
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; *************************************************************
; *** Scatter-Loading Description File for RTL8195A ***
; *************************************************************
LR_ROM 0x00000000 0x00030000{
_ROM_CODE 0x00000000 0x00030000 {
;*.o (RESET, +First)
;*(InRoot$$Sections)
}
}
LR_RAM 0x10006000 0x6FFFF {
;LR_RAM 0x10000000 0x6FFFF {
;ROM_BSS 0x10000000 0x0005FFF{
;rtl_console.o(.mon.ram.bss*)
;}
.image2.table 0x10006000 FIXED {
rtl8195a_init.o(.image2.ram.data*)
rtl8195a_init.o(.image2.validate.rodata*)
}
.text +0 FIXED{
rtl8195a_init.o(.infra.ram.start)
;*.o(.mon.ram.text*)
;*.o(.hal.flash.text*)
;*.o(.hal.sdrc.text*)
;*.o(.hal.gpio.text*)
;*.o(.text*)
;*.o(.rodata*)
.ANY (+RO)
}
.data +0 FIXED{
.ANY (+RW)
}
RW_IRAM1 +0 UNINIT FIXED {
.ANY (+ZI)
}
}
LR_DRAM 0x30000000 0x1FFFFF{
_DRAM_CODE 0x30000000 0x1FFFFF{
}
}

648
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a_rom.o Normal file
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#<SYMDEFS># ARM Linker, RVCT3.1 [Build num]: Last Updated: Date ;
0x00000000 D __vectors_table
0x00000101 T Reset_Handler
0x00000109 T NMI_Handler
0x0000010d T HardFault_Handler
0x00000121 T MemManage_Handler
0x00000125 T BusFault_Handler
0x00000129 T UsageFault_Handler
0x00000201 T HalLogUartInit
0x00000309 T HalSerialGetcRtl8195a
0x00000329 T HalSerialGetIsrEnRegRtl8195a
0x00000335 T HalSerialSetIrqEnRegRtl8195a
0x00000341 T HalCpuClkConfig
0x00000355 T HalGetCpuClk
0x0000039d T HalRomInfo
0x000003b5 T HalGetRomInfo
0x000003c5 T HalResetVsr
0x00000899 T HalDelayUs
0x000008e1 T HalNMIHandler
0x00000911 T HalHardFaultHandler
0x00000c09 T HalMemManageHandler
0x00000c39 T HalBusFaultHandler
0x00000c69 T HalUsageFaultHandler
0x00000cfd T HalUart0PinCtrlRtl8195A
0x00000dc9 T HalUart1PinCtrlRtl8195A
0x00000e9d T HalUart2PinCtrlRtl8195A
0x00000f75 T HalSPI0PinCtrlRtl8195A
0x00001015 T HalSPI1PinCtrlRtl8195A
0x000010e5 T HalSPI2PinCtrlRtl8195A
0x000011b5 T HalSPI0MCSPinCtrlRtl8195A
0x00001275 T HalI2C0PinCtrlRtl8195A
0x00001381 T HalI2C1PinCtrlRtl8195A
0x00001459 T HalI2C2PinCtrlRtl8195A
0x00001529 T HalI2C3PinCtrlRtl8195A
0x00001639 T HalI2S0PinCtrlRtl8195A
0x0000176d T HalI2S1PinCtrlRtl8195A
0x00001845 T HalPCM0PinCtrlRtl8195A
0x00001949 T HalPCM1PinCtrlRtl8195A
0x00001a1d T HalSDIODPinCtrlRtl8195A
0x00001a6d T HalSDIOHPinCtrlRtl8195A
0x00001ab9 T HalMIIPinCtrlRtl8195A
0x00001b51 T HalWLLEDPinCtrlRtl8195A
0x00001c0d T HalWLANT0PinCtrlRtl8195A
0x00001c61 T HalWLANT1PinCtrlRtl8195A
0x00001cb5 T HalWLBTCOEXPinCtrlRtl8195A
0x00001d05 T HalWLBTCMDPinCtrlRtl8195A
0x00001d59 T HalNFCPinCtrlRtl8195A
0x00001da9 T HalPWM0PinCtrlRtl8195A
0x00001ead T HalPWM1PinCtrlRtl8195A
0x00001fb5 T HalPWM2PinCtrlRtl8195A
0x000020b1 T HalPWM3PinCtrlRtl8195A
0x000021b9 T HalETE0PinCtrlRtl8195A
0x000022c1 T HalETE1PinCtrlRtl8195A
0x000023c9 T HalETE2PinCtrlRtl8195A
0x000024d1 T HalETE3PinCtrlRtl8195A
0x000025d9 T HalEGTIMPinCtrlRtl8195A
0x00002679 T HalSPIFlashPinCtrlRtl8195A
0x00002725 T HalSDRPinCtrlRtl8195A
0x0000280d T HalJTAGPinCtrlRtl8195A
0x00002861 T HalTRACEPinCtrlRtl8195A
0x000028b9 T HalLOGUartPinCtrlRtl8195A
0x0000291d T HalLOGUartIRPinCtrlRtl8195A
0x00002981 T HalSICPinCtrlRtl8195A
0x000029d9 T HalEEPROMPinCtrlRtl8195A
0x00002a31 T HalDEBUGPinCtrlRtl8195A
0x00002b39 T HalPinCtrlRtl8195A
0x00002e5d T SpicRxCmdRtl8195A
0x00002ea5 T SpicWaitBusyDoneRtl8195A
0x00002eb5 T SpicGetFlashStatusRtl8195A
0x00002f55 T SpicWaitWipDoneRtl8195A
0x00002f6d T SpicTxCmdRtl8195A
0x00002fc1 T SpicSetFlashStatusRtl8195A
0x00003049 T SpicCmpDataForCalibrationRtl8195A
0x00003081 T SpicLoadInitParaFromClockRtl8195A
0x000030e5 T SpicInitRtl8195A
0x000031bd T SpicEraseFlashRtl8195A
0x00003279 T SpiFlashApp
0x000033b5 T HalPeripheralIntrHandle
0x00003439 T HalSysOnIntrHandle
0x00003485 T HalWdgIntrHandle
0x000034d5 T HalTimer0IntrHandle
0x00003525 T HalTimer1IntrHandle
0x00003575 T HalI2C3IntrHandle
0x000035c5 T HalTimer2To7IntrHandle
0x00003615 T HalSpi0IntrHandle
0x00003665 T HalGpioIntrHandle
0x000036b5 T HalUart0IntrHandle
0x00003705 T HalSpiFlashIntrHandle
0x00003755 T HalUsbOtgIntrHandle
0x000037a5 T HalSdioHostIntrHandle
0x000037f5 T HalI2s0OrPcm0IntrHandle
0x00003845 T HalI2s1OrPcm1IntrHandle
0x00003895 T HalWlDmaIntrHandle
0x000038e5 T HalWlProtocolIntrHandle
0x00003935 T HalCryptoIntrHandle
0x00003985 T HalGmacIntrHandle
0x000039d5 T HalGdma0Ch0IntrHandle
0x00003a25 T HalGdma0Ch1IntrHandle
0x00003a75 T HalGdma0Ch2IntrHandle;
0x00003ac5 T HalGdma0Ch3IntrHandle
0x00003b15 T HalGdma0Ch4IntrHandle
0x00003b65 T HalGdma0Ch5IntrHandle
0x00003bb5 T HalGdma1Ch0IntrHandle
0x00003c05 T HalGdma1Ch1IntrHandle
0x00003c55 T HalGdma1Ch2IntrHandle
0x00003ca5 T HalGdma1Ch3IntrHandle
0x00003cf5 T HalGdma1Ch4IntrHandle
0x00003d45 T HalGdma1Ch5IntrHandle
0x00003d95 T HalSdioDeviceIntrHandle
0x00003de5 T VectorTableInitRtl8195A
0x00004019 T VectorTableInitForOSRtl8195A
0x00004029 T VectorIrqRegisterRtl8195A
0x00004091 T VectorIrqUnRegisterRtl8195A
0x000040f1 T VectorIrqEnRtl8195A
0x0000418d T VectorIrqDisRtl8195A
0x0000422d T _UartRxDmaIrqHandle
0x00004281 T HalRuartPutCRtl8195a
0x0000429d T HalRuartGetCRtl8195a
0x000042bd T HalRuartRTSCtrlRtl8195a
0x000042e1 T HalRuartGetDebugValueRtl8195a
0x000043e1 T HalRuartGetIMRRtl8195a
0x0000442d T HalRuartSetIMRRtl8195a
0x00004465 T _UartIrqHandle
0x00004681 T HalRuartDmaInitRtl8195a
0x00004845 T HalRuartIntDisableRtl8195a
0x00004855 T HalRuartDeInitRtl8195a
0x00004985 T HalRuartIntEnableRtl8195a
0x00004995 T _UartTxDmaIrqHandle
0x000049d1 T HalRuartRegIrqRtl8195a
0x00004a4d T HalRuartAdapterLoadDefRtl8195a
0x00004add T HalRuartTxGdmaLoadDefRtl8195a
0x00004bc9 T HalRuartRxGdmaLoadDefRtl8195a
0x00004cc9 T RuartLock
0x00004ced T RuartUnLock
0x00004d09 T HalRuartIntSendRtl8195a
0x00004e35 T HalRuartDmaSendRtl8195a
0x00004f89 T HalRuartStopSendRtl8195a
0x0000504d T HalRuartIntRecvRtl8195a
0x000051ad T HalRuartDmaRecvRtl8195a
0x000052cd T HalRuartStopRecvRtl8195a
0x00005385 T RuartIsTimeout
0x000053b1 T HalRuartSendRtl8195a
0x00005599 T HalRuartRecvRtl8195a
0x00005751 T RuartResetRxFifoRtl8195a
0x00005775 T HalRuartResetRxFifoRtl8195a
0x00005829 T HalRuartInitRtl8195a
0x00005df1 T HalGdmaOnOffRtl8195a
0x00005e0d T HalGdmaChIsrEnAndDisRtl8195a
0x00005e51 T HalGdmaChEnRtl8195a
0x00005e6d T HalGdmaChDisRtl8195a
0x00005e91 T HalGdamChInitRtl8195a
0x00005ebd T HalGdmaChSetingRtl8195a
0x000060dd T HalGdmaChBlockSetingRtl8195a
0x00006419 T HalGdmaChIsrCleanRtl8195a
0x000064a1 T HalGdmaChCleanAutoSrcRtl8195a
0x00006501 T HalGdmaChCleanAutoDstRtl8195a
0x00006561 T HalEFUSEPowerSwitch8195AROM
0x000065f9 T HALEFUSEOneByteReadROM
0x00006699 T HALEFUSEOneByteWriteROM
0x0000681d T __rtl_memcmpb_v1_00
0x00006861 T __rtl_random_v1_00
0x00006881 T __rtl_align_to_be32_v1_00
0x00006899 T __rtl_memsetw_v1_00
0x000068ad T __rtl_memsetb_v1_00
0x000068bd T __rtl_memcpyw_v1_00
0x000068dd T __rtl_memcpyb_v1_00
0x000068f5 T __rtl_memDump_v1_00
0x00006901 T __rtl_AES_set_encrypt_key
0x00006c11 T __rtl_cryptoEngine_AES_set_decrypt_key
0x00006c95 T __rtl_cryptoEngine_set_security_mode_v1_00
0x00006ea9 T __rtl_cryptoEngine_init_v1_00
0x00007055 T __rtl_cryptoEngine_exit_v1_00
0x000070b1 T __rtl_cryptoEngine_reset_v1_00
0x000070ed T __rtl_cryptoEngine_v1_00
0x00007c69 T __rtl_crypto_cipher_init_v1_00
0x00007c89 T __rtl_crypto_cipher_encrypt_v1_00
0x00007cad T __rtl_crypto_cipher_decrypt_v1_00
0x00007cd5 T HalSsiPinmuxEnableRtl8195a
0x00007e45 T HalSsiEnableRtl8195a
0x00007ef9 T HalSsiDisableRtl8195a
0x00007fad T HalSsiLoadSettingRtl8195a
0x00008521 T HalSsiSetInterruptMaskRtl8195a
0x000085c9 T HalSsiGetInterruptMaskRtl8195a
0x0000863d T HalSsiSetSclkPolarityRtl8195a
0x00008715 T HalSsiSetSclkPhaseRtl8195a
0x000087e9 T HalSsiWriteRtl8195a
0x00008861 T HalSsiSetDeviceRoleRtl8195a
0x000088c9 T HalSsiSetRxFifoThresholdLevelRtl8195a
0x00008941 T HalSsiSetTxFifoThresholdLevelRtl8195a
0x000089b9 T HalSsiReadRtl8195a
0x00008a2d T HalSsiGetRxFifoLevelRtl8195a
0x00008aa5 T HalSsiGetTxFifoLevelRtl8195a
0x00008b1d T HalSsiGetStatusRtl8195a
0x00008b91 T HalSsiWriteableRtl8195a
0x00008c09 T HalSsiReadableRtl8195a
0x00008c81 T HalSsiBusyRtl8195a
0x00008cf9 T HalSsiReadInterruptRtl8195a
0x00008efd T HalSsiWriteInterruptRtl8195a
0x00009009 T HalSsiSetSlaveEnableRegisterRtl8195a
0x000090d9 T HalSsiGetInterruptStatusRtl8195a
0x0000914d T HalSsiInterruptEnableRtl8195a
0x00009299 T HalSsiInterruptDisableRtl8195a
0x000093e9 T HalSsiGetRawInterruptStatusRtl8195a
0x0000945d T HalSsiGetSlaveEnableRegisterRtl8195a
0x000094d1 T HalSsiInitRtl8195a
0x00009ba5 T _SsiReadInterrupt
0x00009db1 T _SsiWriteInterrupt
0x00009eb1 T _SsiIrqHandle
0x0000a061 T HalI2CWrite32
0x0000a09d T HalI2CRead32
0x0000a0dd T HalI2CDeInit8195a
0x0000a1f1 T HalI2CSendRtl8195a
0x0000a25d T HalI2CReceiveRtl8195a
0x0000a271 T HalI2CEnableRtl8195a
0x0000a389 T HalI2CIntrCtrl8195a
0x0000a3a1 T HalI2CReadRegRtl8195a
0x0000a3b1 T HalI2CWriteRegRtl8195a
0x0000a3c5 T HalI2CSetCLKRtl8195a
0x0000a6e9 T HalI2CMassSendRtl8195a
0x0000a749 T HalI2CClrIntrRtl8195a
0x0000a761 T HalI2CClrAllIntrRtl8195a
0x0000a775 T HalI2CInit8195a
0x0000aa31 T HalI2CDMACtrl8195a
0x0000aa61 T RtkI2CIoCtrl
0x0000aa65 T RtkI2CPowerCtrl
0x0000aa69 T HalI2COpInit
0x0000ac65 T I2CIsTimeout
0x0000b435 T I2CTXGDMAISRHandle
0x0000b4c1 T I2CRXGDMAISRHandle
0x0000b54d T RtkI2CIrqInit
0x0000b611 T RtkI2CIrqDeInit
0x0000b675 T RtkI2CPinMuxInit
0x0000b7c9 T RtkI2CPinMuxDeInit
0x0000b955 T RtkI2CDMAInit
0x0000bc95 T RtkI2CInit
0x0000bdad T RtkI2CDMADeInit
0x0000be4d T RtkI2CDeInit
0x0000bee5 T RtkI2CSendUserAddr
0x0000c07d T RtkI2CSend
0x0000ce51 T RtkI2CLoadDefault
0x0000cf21 T RtkSalI2COpInit
0x0000cf65 T HalI2SWrite32
0x0000cf85 T HalI2SRead32
0x0000cfa9 T HalI2SDeInitRtl8195a
0x0000cfc9 T HalI2STxRtl8195a
0x0000d011 T HalI2SRxRtl8195a
0x0000d05d T HalI2SEnableRtl8195a
0x0000d0b1 T HalI2SIntrCtrlRtl8195a
0x0000d0d1 T HalI2SReadRegRtl8195a
0x0000d0dd T HalI2SClrIntrRtl8195a
0x0000d0fd T HalI2SClrAllIntrRtl8195a
0x0000d11d T HalI2SInitRtl8195a
0x0000d2e5 T GPIO_GetIPPinName_8195a
0x0000d331 T GPIO_GetChipPinName_8195a
0x0000d39d T GPIO_PullCtrl_8195a
0x0000d421 T GPIO_FuncOn_8195a
0x0000d481 T GPIO_FuncOff_8195a
0x0000d4e9 T GPIO_Int_Mask_8195a
0x0000d511 T GPIO_Int_SetType_8195a
0x0000d5fd T HAL_GPIO_IrqHandler_8195a
0x0000d645 T HAL_GPIO_MbedIrqHandler_8195a
0x0000d6a1 T HAL_GPIO_UserIrqHandler_8195a
0x0000d6cd T HAL_GPIO_IntCtrl_8195a
0x0000d805 T HAL_GPIO_Init_8195a
0x0000dac1 T HAL_GPIO_DeInit_8195a
0x0000dbd1 T HAL_GPIO_ReadPin_8195a
0x0000dc91 T HAL_GPIO_WritePin_8195a
0x0000ddad T HAL_GPIO_RegIrq_8195a
0x0000ddf5 T HAL_GPIO_UnRegIrq_8195a
0x0000de15 T HAL_GPIO_UserRegIrq_8195a
0x0000def9 T HAL_GPIO_UserUnRegIrq_8195a
0x0000dfc1 T HAL_GPIO_MaskIrq_8195a
0x0000e061 T HAL_GPIO_UnMaskIrq_8195a
0x0000e101 T HAL_GPIO_IntDebounce_8195a
0x0000e1c1 T HAL_GPIO_GetIPPinName_8195a
0x0000e1c9 T HAL_GPIO_PullCtrl_8195a
0x0000e259 T DumpForOneBytes
0x0000e419 T CmdRomHelp
0x0000e491 T CmdWriteWord
0x0000e505 T CmdDumpHelfWord
0x0000e5f1 T CmdDumpWord
0x0000e6f5 T CmdDumpByte
0x0000e751 T CmdSpiFlashTool
0x0000e7a9 T GetRomCmdNum
0x0000e7ad T CmdWriteByte
0x0000e7ed T Isspace
0x0000e801 T Strtoul
0x0000e8b1 T ArrayInitialize
0x0000e8c9 T GetArgc
0x0000e8f9 T GetArgv
0x0000e95d T UartLogCmdExecute
0x0000e9fd T UartLogShowBackSpace
0x0000ea39 T UartLogRecallOldCmd
0x0000ea71 T UartLogHistoryCmd
0x0000eadd T UartLogCmdChk
0x0000ebf5 T UartLogIrqHandle
0x0000ecc5 T RtlConsolInit
0x0000ed49 T RtlConsolTaskRom
0x0000ed79 T RtlExitConsol
0x0000edcd T RtlConsolRom
0x0000ee0d T HalTimerOpInit
0x0000ee59 T HalTimerIrq2To7Handle
0x0000ef09 T HalGetTimerIdRtl8195a
0x0000ef3d T HalTimerInitRtl8195a
0x0000f069 T HalTimerDisRtl8195a
0x0000f089 T HalTimerEnRtl8195a
0x0000f0a9 T HalTimerReadCountRtl8195a
0x0000f0bd T HalTimerIrqClearRtl8195a
0x0000f0d1 T HalTimerDumpRegRtl8195a
0x0000f129 T VSprintf
0x0000f39d T DiagPrintf
0x0000f3b9 T DiagSPrintf
0x0000f3d1 T DiagSnPrintf
0x0000f3ed T prvDiagPrintf
0x0000f40d T prvDiagSPrintf
0x0000f429 T _memcmp
0x0000f465 T _memcpy
#0x0000f511 T _memset
0x0000f585 T Rand
0x0000f60d T _strncpy
0x0000f629 T _strcpy
0x0000f639 T prvStrCpy
0x0000f651 T _strlen
0x0000f669 T _strnlen
0x0000f699 T prvStrLen
0x0000f6b1 T _strcmp
0x0000f6d1 T _strncmp
0x0000f719 T prvStrCmp
0x0000f749 T StrUpr
0x0000f769 T prvAtoi
0x0000f7bd T prvStrStr
0x0000f7d5 T _strsep
0x0000f815 T skip_spaces
0x0000f831 T skip_atoi
0x0000f869 T _parse_integer_fixup_radix
0x0000f8bd T _parse_integer
0x0000f915 T simple_strtoull
0x0000f945 T simple_strtoll
0x0000f965 T simple_strtoul
0x0000f96d T simple_strtol
0x0000f985 T _vsscanf
0x0000ff71 T _sscanf
0x0000ff91 T div_u64
0x0000ff99 T div_s64
0x0000ffa1 T div_u64_rem
0x0000ffb1 T div_s64_rem
0x0000ffc1 T _strpbrk
0x0000ffed T _strchr
0x00010005 T aes_set_key
0x000103d1 T aes_encrypt
0x000114a5 T aes_decrypt
0x000125c9 T AES_WRAP
0x00012701 T AES_UnWRAP
0x00012861 T crc32_get
0x00012895 T arc4_byte
0x000128bd T rt_arc4_init
0x00012901 T rt_arc4_crypt
0x000131c1 T rt_md5_init
0x000131f5 T rt_md5_append
0x0001327d T rt_md5_final
0x000132d5 T rt_md5_hmac
0x00013449 T rtw_get_bit_value_from_ieee_value
0x00013475 T rtw_is_cckrates_included
0x000134b5 T rtw_is_cckratesonly_included
0x000134dd T rtw_check_network_type
0x0001350d T rtw_set_fixed_ie
0x0001352d T rtw_set_ie
0x0001355d T rtw_get_ie
0x00013591 T rtw_set_supported_rate
0x00013611 T rtw_get_rateset_len
0x0001362d T rtw_get_wpa_ie
0x000136c9 T rtw_get_wpa2_ie
0x00013701 T rtw_get_wpa_cipher_suite
0x00013769 T rtw_get_wpa2_cipher_suite
0x000137d1 T rtw_parse_wpa_ie
0x000138ad T rtw_parse_wpa2_ie
0x00013965 T rtw_get_sec_ie
0x00013a15 T rtw_get_wps_ie
0x00013a99 T rtw_get_wps_attr
0x00013b49 T rtw_get_wps_attr_content
0x00013b91 T rtw_ieee802_11_parse_elems
0x00013d9d T str_2char2num
0x00013db9 T key_2char2num
0x00013dd1 T convert_ip_addr
0x00013e9d T rom_psk_PasswordHash
0x00013ed5 T rom_psk_CalcGTK
0x00013f69 T rom_psk_CalcPTK
0x00014295 T wep_80211_encrypt
0x000142f5 T wep_80211_decrypt
0x00014389 T tkip_micappendbyte
0x000143d9 T rtw_secmicsetkey
0x00014419 T rtw_secmicappend
0x00014435 T rtw_secgetmic
0x0001449d T rtw_seccalctkipmic
0x000145a5 T tkip_phase1
0x00014725 T tkip_phase2
0x00014941 T tkip_80211_encrypt
0x000149d5 T tkip_80211_decrypt
0x00014a8d T aes1_encrypt
0x00014c65 T aesccmp_construct_mic_iv
0x00014ccd T aesccmp_construct_mic_header1
0x00014d21 T aesccmp_construct_mic_header2
0x00014db5 T aesccmp_construct_ctr_preload
0x00014e29 T aes_80211_encrypt
0x000151ad T aes_80211_decrypt
0x000155b9 T _sha1_process_message_block
0x00015749 T _sha1_pad_message
0x000157e5 T rt_sha1_init
0x00015831 T rt_sha1_update
0x000158a9 T rt_sha1_finish
0x00015909 T rt_hmac_sha1
0x00015a65 T rom_aes_128_cbc_encrypt
0x00015ae1 T rom_aes_128_cbc_decrypt
0x00015b5d T rom_rijndaelKeySetupEnc
0x00015c39 T rom_aes_decrypt_init
0x00015d15 T rom_aes_internal_decrypt
0x00016071 T rom_aes_decrypt_deinit
0x00016085 T rom_aes_encrypt_init
0x0001609d T rom_aes_internal_encrypt
0x00016451 T rom_aes_encrypt_deinit
0x00017b35 T bignum_init
0x00017b61 T bignum_deinit
0x00017b81 T bignum_get_unsigned_bin_len
0x00017b85 T bignum_get_unsigned_bin
0x00017c21 T bignum_set_unsigned_bi
0x00017cd1 T bignum_cmp
0x00017cd5 T bignum_cmp_d
0x00017cfd T bignum_add
0x00017d0d T bignum_sub
0x00017d1d T bignum_mul
0x00017d2d T bignum_exptmod
0x00017d51 T WPS_realloc
0x00017d99 T os_zalloc
0x00017dc1 T rom_hmac_sha256_vector
0x00017ebd T rom_hmac_sha256
0x00018009 T rom_sha256_vector
0x00018221 T phy_CalculateBitShift
0x00018239 T PHY_SetBBReg_8195A
0x00018279 T PHY_QueryBBReg_8195A
0x0001829d T ROM_odm_QueryRxPwrPercentage
0x000182bd T ROM_odm_EVMdbToPercentage
0x000182e5 T ROM_odm_SignalScaleMapping_8195A
0x000183cd T ROM_odm_FalseAlarmCounterStatistics
0x00018721 T ROM_odm_SetEDCCAThreshold
0x00018749 T ROM_odm_SetTRxMux
0x00018771 T ROM_odm_SetCrystalCap
0x000187d5 T ROM_odm_GetDefaultCrytaltalCap
0x000187e9 T ROM_ODM_CfoTrackingReset
0x00018811 T ROM_odm_CfoTrackingFlow
0x0001965d T curve25519_donna
0x0001a391 T aes_test_alignment_detection
0x0001a3ed T aes_mode_reset
0x0001a3f9 T aes_ecb_encrypt
0x0001a431 T aes_ecb_decrypt
0x0001a469 T aes_cbc_encrypt
0x0001a579 T aes_cbc_decrypt
0x0001a701 T aes_cfb_encrypt
0x0001a9e5 T aes_cfb_decrypt
0x0001acc9 T aes_ofb_crypt
0x0001af7d T aes_ctr_crypt
0x0001b289 T aes_encrypt_key128
0x0001b2a5 T aes_encrypt_key192
0x0001b2c1 T aes_encrypt_key256
0x0001b2e1 T aes_encrypt_key
0x0001b351 T aes_decrypt_key128
0x0001b36d T aes_decrypt_key192
0x0001b389 T aes_decrypt_key256
0x0001b3a9 T aes_decrypt_key
0x0001b419 T aes_init
0x0001b41d T CRYPTO_chacha_20
0x0001bc25 T CRYPTO_poly1305_init
0x0001bd09 T CRYPTO_poly1305_update
0x0001bd8d T CRYPTO_poly1305_finish
0x0001ceb5 T rom_sha512_starts
0x0001d009 T rom_sha512_update
0x0001d011 T rom_sha512_finish
0x0001d261 T rom_sha512
0x0001d299 T rom_sha512_hmac_starts
0x0001d35d T rom_sha512_hmac_update
0x0001d365 T rom_sha512_hmac_finish
0x0001d3b5 T rom_sha512_hmac_reset
0x0001d3d1 T rom_sha512_hmac
0x0001d40d T rom_sha512_hkdf
0x0001d501 T rom_ed25519_gen_keypair
0x0001d505 T rom_ed25519_gen_signature
0x0001d51d T rom_ed25519_verify_signature
0x0001d521 T rom_ed25519_crypto_sign_seed_keypair
0x0001d579 T rom_ed25519_crypto_sign_detached
0x0001d655 T rom_ed25519_crypto_sign_verify_detached
0x0001f86d T rom_ed25519_ge_double_scalarmult_vartime
0x0001fc35 T rom_ed25519_ge_frombytes_negate_vartime
0x000207d5 T rom_ed25519_ge_p3_tobytes
0x00020821 T rom_ed25519_ge_scalarmult_base
0x000209e1 T rom_ed25519_ge_tobytes
0x00020a2d T rom_ed25519_sc_muladd
0x0002603d T rom_ed25519_sc_reduce
0x00028a4d T __rtl_memchr_v1_00
0x00028ae1 T __rtl_memcmp_v1_00
0x00028b49 T __rtl_memcpy_v1_00
0x00028bed T __rtl_memmove_v1_00
0x00028cb5 T __rtl_memset_v1_00
0x00028d49 T __rtl_strcat_v1_00
0x00028d91 T __rtl_strchr_v1_00
0x00028e55 T __rtl_strcmp_v1_00
0x00028ec9 T __rtl_strcpy_v1_00
0x00028f15 T __rtl_strlen_v1_00
0x00028f69 T __rtl_strncat_v1_00
0x00028fc5 T __rtl_strncmp_v1_00
0x0002907d T __rtl_strncpy_v1_00
0x000293cd T __rtl_strstr_v1_00
0x0002960d T __rtl_strsep_v1_00
0x00029619 T __rtl_strtok_v1_00
0x0002962d T __rtl__strtok_r_v1_00
0x00029691 T __rtl_strtok_r_v1_00
0x00029699 T __rtl_close_v1_00
0x000296ad T __rtl_fstat_v1_00
0x000296c1 T __rtl_isatty_v1_00
0x000296d5 T __rtl_lseek_v1_00
0x000296e9 T __rtl_open_v1_00
0x000296fd T __rtl_read_v1_00
0x00029711 T __rtl_write_v1_00
0x00029725 T __rtl_sbrk_v1_00
0x000297bd T __rtl_ltoa_v1_00
0x00029855 T __rtl_ultoa_v1_00
0x000298c5 T __rtl_dtoi_v1_00
0x00029945 T __rtl_dtoi64_v1_00
0x000299dd T __rtl_dtoui_v1_00
0x000299e5 T __rtl_ftol_v1_00
0x00029a51 T __rtl_itof_v1_00
0x00029ae9 T __rtl_itod_v1_00
0x00029b79 T __rtl_i64tod_v1_00
0x00029c55 T __rtl_uitod_v1_00
0x00029d2d T __rtl_ftod_v1_00
0x00029de9 T __rtl_dtof_v1_00
0x00029e89 T __rtl_uitof_v1_00
0x00029f65 T __rtl_fadd_v1_00
0x0002a261 T __rtl_fsub_v1_00
0x0002a559 T __rtl_fmul_v1_00
0x0002a695 T __rtl_fdiv_v1_00
0x0002a825 T __rtl_dadd_v1_00
0x0002aed9 T __rtl_dsub_v1_00
0x0002b555 T __rtl_dmul_v1_00
0x0002b8ad T __rtl_ddiv_v1_00
0x0002be4d T __rtl_dcmpeq_v1_00
0x0002bebd T __rtl_dcmplt_v1_00
0x0002bf51 T __rtl_dcmpgt_v1_00
0x0002c049 T __rtl_dcmple_v1_00
0x0002c139 T __rtl_fcmplt_v1_00
0x0002c195 T __rtl_fcmpgt_v1_00
0x0002c229 T __rtl_cos_f32_v1_00
0x0002c435 T __rtl_sin_f32_v1_00
0x0002c639 T __rtl_fabs_v1_00
0x0002c641 T __rtl_fabsf_v1_00
0x0002c77d T __rtl_dtoa_r_v1_00
0x0002d7d1 T __rom_mallocr_init_v1_00
0x0002d841 T __rtl_free_r_v1_00
0x0002da31 T __rtl_malloc_r_v1_00
0x0002df55 T __rtl_realloc_r_v1_00
0x0002e331 T __rtl_memalign_r_v1_00
0x0002e421 T __rtl_valloc_r_v1_00
0x0002e42d T __rtl_pvalloc_r_v1_00
0x0002e441 T __rtl_calloc_r_v1_00
0x0002e4a9 T __rtl_cfree_r_v1_00
0x0002e515 T __rtl_Balloc_v1_00
0x0002e571 T __rtl_Bfree_v1_00
0x0002e585 T __rtl_i2b_v1_00
0x0002e599 T __rtl_multadd_v1_00
0x0002e629 T __rtl_mult_v1_00
0x0002e769 T __rtl_pow5mult_v1_00
0x0002e809 T __rtl_hi0bits_v1_00
0x0002e845 T __rtl_d2b_v1_00
0x0002e901 T __rtl_lshift_v1_00
0x0002e9bd T __rtl_cmp_v1_00
0x0002ea01 T __rtl_diff_v1_00
0x0002eae9 T __rtl_sread_v1_00
0x0002eb39 T __rtl_seofread_v1_00
0x0002eb3d T __rtl_swrite_v1_00
0x0002ebc1 T __rtl_sseek_v1_00
0x0002ec11 T __rtl_sclose_v1_00
0x0002ec41 T __rtl_sbrk_r_v1_00
0x0002ef8d T __rtl_fflush_r_v1_00
0x0002f661 T __rtl_vfprintf_r_v1_00
0x00030c15 T __rtl_fpclassifyd
0x00030c68 D CpkClkTbl
0x00030c80 D ROM_IMG1_VALID_PATTEN
0x00030c88 D SpicCalibrationPattern
0x00030c98 D SpicInitCPUCLK
0x00030ca8 D BAUDRATE
0x00030d1c D OVSR
0x00030d90 D DIV
0x00030e04 D OVSR_ADJ
0x00030e78 D __AES_rcon
0x00030ea0 D __AES_Te4
0x000312a0 D I2CDmaChNo
0x000316a0 D UartLogRomCmdTable
0x00031700 D _HalRuartOp
0x00031760 D _HalGdmaOp
0x0003540c D RTW_WPA_OUI_TYPE
0x00035410 D WPA_CIPHER_SUITE_NONE
0x00035414 D WPA_CIPHER_SUITE_WEP40
0x00035418 D WPA_CIPHER_SUITE_TKIP
0x0003541c D WPA_CIPHER_SUITE_CCMP
0x00035420 D WPA_CIPHER_SUITE_WEP104
0x00035424 D RSN_CIPHER_SUITE_NONE
0x00035428 D RSN_CIPHER_SUITE_WEP40
0x0003542c D RSN_CIPHER_SUITE_TKIP
0x00035430 D RSN_CIPHER_SUITE_CCMP
0x00035434 D RSN_CIPHER_SUITE_WEP104
0x00035444 D RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X
0x00035448 D RSN_AUTH_KEY_MGMT_UNSPEC_802_1X
0x0003544c D RSN_VERSION_BSD
0x00035988 D rom_wps_Te0
0x00035d88 D rom_wps_rcons
0x00035d94 D rom_wps_Td4s
0x00035e94 D rom_wps_Td0
0x10000000 D NewVectorTable
0x10000100 D UserIrqFunTable
0x10000200 D UserIrqDataTable
0x10000300 D __rom_bss_start__
0x10000300 D CfgSysDebugWarn
0x10000304 D CfgSysDebugInfo
0x10000308 D CfgSysDebugErr
0x1000030c D ConfigDebugWarn
0x10000310 D ConfigDebugInfo
0x10000314 D ConfigDebugErr
0x10000318 D HalTimerOp
0x10000334 D GPIOState
0x1000034c D gTimerRecord
0x10000350 D SSI_DBG_CONFIG
0x10000354 D _pHAL_Gpio_Adapter
0x10000358 D Timer2To7VectorTable
#0x10000384 D pUartLogCtl
#0x10000388 D UartLogBuf
#0x10000408 D UartLogCtl
#0x10000430 D UartLogHistoryBuf
#0x100006ac D ArgvArray
0x100006d4 D rom_wlan_ram_map
0x100006e0 D FalseAlmCnt
0x10000720 D ROMInfo
0x10000738 D DM_CfoTrack
0x10000760 D rom_libgloss_ram_map
0x10000bc4 D __rtl_errno
0x10000bc8 D __ram_table_start__
0x10000bc8 D __rom_bss_end__
0x10001c60 D _rtl_impure_ptr
0X10006000 D __image2_entry_func__
0x10006000 D __image2_start__
0x30000000 D __image3_start__

52
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/sys.cpp Normal file
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/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
* mbed Microcontroller Library - stackheap
* Setup a fixed single stack/heap memory model,
* between the top of the RW/ZI region and the stackpointer
******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
//push down stack pointer to recycle some of the stack space that are not use in future
__asm volatile
(
"MRS IP, MSP \n"
"ADD IP, #64 \n"
"BIC IP, IP, #7 \n"
"MSR MSP, IP \n"
);
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

BIN
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a Normal file
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BIN
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a Normal file
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851
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rlx8195A-symbol-v02-img2.ld Normal file
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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
ENTRY(Reset_Handler)
/*INCLUDE "mbed-os/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/export-rom_v02.txt"*/
SECTIONS
{
__vectors_table = 0x0;
Reset_Handler = 0x101;
NMI_Handler = 0x109;
HardFault_Handler = 0x10d;
MemManage_Handler = 0x121;
BusFault_Handler = 0x125;
UsageFault_Handler = 0x129;
HalLogUartInit = 0x201;
HalSerialGetcRtl8195a = 0x309;
HalSerialGetIsrEnRegRtl8195a = 0x329;
HalSerialSetIrqEnRegRtl8195a = 0x335;
HalCpuClkConfig = 0x341;
HalGetCpuClk = 0x355;
HalRomInfo = 0x39d;
HalGetRomInfo = 0x3b5;
HalResetVsr = 0x3c5;
HalDelayUs = 0x899;
HalNMIHandler = 0x8e1;
HalHardFaultHandler = 0x911;
HalMemManageHandler = 0xc09;
HalBusFaultHandler = 0xc39;
HalUsageFaultHandler = 0xc69;
HalUart0PinCtrlRtl8195A = 0xcfd;
HalUart1PinCtrlRtl8195A = 0xdc9;
HalUart2PinCtrlRtl8195A = 0xe9d;
HalSPI0PinCtrlRtl8195A = 0xf75;
HalSPI1PinCtrlRtl8195A = 0x1015;
HalSPI2PinCtrlRtl8195A = 0x10e5;
HalSPI0MCSPinCtrlRtl8195A = 0x11b5;
HalI2C0PinCtrlRtl8195A = 0x1275;
HalI2C1PinCtrlRtl8195A = 0x1381;
HalI2C2PinCtrlRtl8195A = 0x1459;
HalI2C3PinCtrlRtl8195A = 0x1529;
HalI2S0PinCtrlRtl8195A = 0x1639;
HalI2S1PinCtrlRtl8195A = 0x176d;
HalPCM0PinCtrlRtl8195A = 0x1845;
HalPCM1PinCtrlRtl8195A = 0x1949;
HalSDIODPinCtrlRtl8195A = 0x1a1d;
HalSDIOHPinCtrlRtl8195A = 0x1a6d;
HalMIIPinCtrlRtl8195A = 0x1ab9;
HalWLLEDPinCtrlRtl8195A = 0x1b51;
HalWLANT0PinCtrlRtl8195A = 0x1c0d;
HalWLANT1PinCtrlRtl8195A = 0x1c61;
HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5;
HalWLBTCMDPinCtrlRtl8195A = 0x1d05;
HalNFCPinCtrlRtl8195A = 0x1d59;
HalPWM0PinCtrlRtl8195A = 0x1da9;
HalPWM1PinCtrlRtl8195A = 0x1ead;
HalPWM2PinCtrlRtl8195A = 0x1fb5;
HalPWM3PinCtrlRtl8195A = 0x20b1;
HalETE0PinCtrlRtl8195A = 0x21b9;
HalETE1PinCtrlRtl8195A = 0x22c1;
HalETE2PinCtrlRtl8195A = 0x23c9;
HalETE3PinCtrlRtl8195A = 0x24d1;
HalEGTIMPinCtrlRtl8195A = 0x25d9;
HalSPIFlashPinCtrlRtl8195A = 0x2679;
HalSDRPinCtrlRtl8195A = 0x2725;
HalJTAGPinCtrlRtl8195A = 0x280d;
HalTRACEPinCtrlRtl8195A = 0x2861;
HalLOGUartPinCtrlRtl8195A = 0x28b9;
HalLOGUartIRPinCtrlRtl8195A = 0x291d;
HalSICPinCtrlRtl8195A = 0x2981;
HalEEPROMPinCtrlRtl8195A = 0x29d9;
HalDEBUGPinCtrlRtl8195A = 0x2a31;
HalPinCtrlRtl8195A = 0x2b39;
SpicRxCmdRtl8195A = 0x2e5d;
SpicWaitBusyDoneRtl8195A = 0x2ea5;
SpicGetFlashStatusRtl8195A = 0x2eb5;
SpicWaitWipDoneRtl8195A = 0x2f55;
SpicTxCmdRtl8195A = 0x2f6d;
SpicSetFlashStatusRtl8195A = 0x2fc1;
SpicCmpDataForCalibrationRtl8195A = 0x3049;
SpicLoadInitParaFromClockRtl8195A = 0x3081;
SpicInitRtl8195A = 0x30e5;
SpicEraseFlashRtl8195A = 0x31bd;
SpiFlashApp = 0x3279;
HalPeripheralIntrHandle = 0x33b5;
HalSysOnIntrHandle = 0x3439;
HalWdgIntrHandle = 0x3485;
HalTimer0IntrHandle = 0x34d5;
HalTimer1IntrHandle = 0x3525;
HalI2C3IntrHandle = 0x3575;
HalTimer2To7IntrHandle = 0x35c5;
HalSpi0IntrHandle = 0x3615;
HalGpioIntrHandle = 0x3665;
HalUart0IntrHandle = 0x36b5;
HalSpiFlashIntrHandle = 0x3705;
HalUsbOtgIntrHandle = 0x3755;
HalSdioHostIntrHandle = 0x37a5;
HalI2s0OrPcm0IntrHandle = 0x37f5;
HalI2s1OrPcm1IntrHandle = 0x3845;
HalWlDmaIntrHandle = 0x3895;
HalWlProtocolIntrHandle = 0x38e5;
HalCryptoIntrHandle = 0x3935;
HalGmacIntrHandle = 0x3985;
HalGdma0Ch0IntrHandle = 0x39d5;
HalGdma0Ch1IntrHandle = 0x3a25;
HalGdma0Ch2IntrHandle = 0x3a75;
HalGdma0Ch3IntrHandle = 0x3ac5;
HalGdma0Ch4IntrHandle = 0x3b15;
HalGdma0Ch5IntrHandle = 0x3b65;
HalGdma1Ch0IntrHandle = 0x3bb5;
HalGdma1Ch1IntrHandle = 0x3c05;
HalGdma1Ch2IntrHandle = 0x3c55;
HalGdma1Ch3IntrHandle = 0x3ca5;
HalGdma1Ch4IntrHandle = 0x3cf5;
HalGdma1Ch5IntrHandle = 0x3d45;
HalSdioDeviceIntrHandle = 0x3d95;
VectorTableInitRtl8195A = 0x3de5;
VectorTableInitForOSRtl8195A = 0x4019;
VectorIrqRegisterRtl8195A = 0x4029;
VectorIrqUnRegisterRtl8195A = 0x4091;
VectorIrqEnRtl8195A = 0x40f1;
VectorIrqDisRtl8195A = 0x418d;
_UartRxDmaIrqHandle = 0x422d;
HalRuartPutCRtl8195a = 0x4281;
HalRuartGetCRtl8195a = 0x429d;
HalRuartRTSCtrlRtl8195a = 0x42bd;
HalRuartGetDebugValueRtl8195a = 0x42e1;
HalRuartGetIMRRtl8195a = 0x43e1;
HalRuartSetIMRRtl8195a = 0x442d;
_UartIrqHandle = 0x4465;
HalRuartDmaInitRtl8195a = 0x4681;
HalRuartIntDisableRtl8195a = 0x4845;
HalRuartDeInitRtl8195a = 0x4855;
HalRuartIntEnableRtl8195a = 0x4985;
_UartTxDmaIrqHandle = 0x4995;
HalRuartRegIrqRtl8195a = 0x49d1;
HalRuartAdapterLoadDefRtl8195a = 0x4a4d;
HalRuartTxGdmaLoadDefRtl8195a = 0x4add;
HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9;
RuartLock = 0x4cc9;
RuartUnLock = 0x4ced;
HalRuartIntSendRtl8195a = 0x4d09;
HalRuartDmaSendRtl8195a = 0x4e35;
HalRuartStopSendRtl8195a = 0x4f89;
HalRuartIntRecvRtl8195a = 0x504d;
HalRuartDmaRecvRtl8195a = 0x51ad;
HalRuartStopRecvRtl8195a = 0x52cd;
RuartIsTimeout = 0x5385;
HalRuartSendRtl8195a = 0x53b1;
HalRuartRecvRtl8195a = 0x5599;
RuartResetRxFifoRtl8195a = 0x5751;
HalRuartResetRxFifoRtl8195a = 0x5775;
HalRuartInitRtl8195a = 0x5829;
HalGdmaOnOffRtl8195a = 0x5df1;
HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d;
HalGdmaChEnRtl8195a = 0x5e51;
HalGdmaChDisRtl8195a = 0x5e6d;
HalGdamChInitRtl8195a = 0x5e91;
HalGdmaChSetingRtl8195a = 0x5ebd;
HalGdmaChBlockSetingRtl8195a = 0x000060dd;
HalGdmaChIsrCleanRtl8195a = 0x6419;
HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
HalGdmaChCleanAutoDstRtl8195a = 0x6501;
HalEFUSEPowerSwitch8195AROM = 0x6561;
HALEFUSEOneByteReadROM = 0x65f9;
HALEFUSEOneByteWriteROM = 0x6699;
__rtl_memcmpb_v1_00 = 0x681d;
__rtl_random_v1_00 = 0x6861;
__rtl_align_to_be32_v1_00 = 0x6881;
__rtl_memsetw_v1_00 = 0x6899;
__rtl_memsetb_v1_00 = 0x68ad;
__rtl_memcpyw_v1_00 = 0x68bd;
__rtl_memcpyb_v1_00 = 0x68dd;
__rtl_memDump_v1_00 = 0x68f5;
__rtl_AES_set_encrypt_key = 0x6901;
__rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11;
__rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95;
__rtl_cryptoEngine_init_v1_00 = 0x6ea9;
__rtl_cryptoEngine_exit_v1_00 = 0x7055;
__rtl_cryptoEngine_reset_v1_00 = 0x70b1;
__rtl_cryptoEngine_v1_00 = 0x70ed;
__rtl_crypto_cipher_init_v1_00 = 0x7c69;
__rtl_crypto_cipher_encrypt_v1_00 = 0x7c89;
__rtl_crypto_cipher_decrypt_v1_00 = 0x7cad;
HalSsiPinmuxEnableRtl8195a = 0x7cd5;
HalSsiEnableRtl8195a = 0x7e45;
HalSsiDisableRtl8195a = 0x7ef9;
HalSsiLoadSettingRtl8195a = 0x7fad;
HalSsiSetInterruptMaskRtl8195a = 0x8521;
HalSsiGetInterruptMaskRtl8195a = 0x85c9;
HalSsiSetSclkPolarityRtl8195a = 0x863d;
HalSsiSetSclkPhaseRtl8195a = 0x8715;
HalSsiWriteRtl8195a = 0x87e9;
HalSsiSetDeviceRoleRtl8195a = 0x8861;
HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9;
HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941;
HalSsiReadRtl8195a = 0x89b9;
HalSsiGetRxFifoLevelRtl8195a = 0x8a2d;
HalSsiGetTxFifoLevelRtl8195a = 0x8aa5;
HalSsiGetStatusRtl8195a = 0x8b1d;
HalSsiWriteableRtl8195a = 0x8b91;
HalSsiReadableRtl8195a = 0x8c09;
HalSsiBusyRtl8195a = 0x8c81;
HalSsiReadInterruptRtl8195a = 0x8cf9;
HalSsiWriteInterruptRtl8195a = 0x8efd;
HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009;
HalSsiGetInterruptStatusRtl8195a = 0x90d9;
HalSsiInterruptEnableRtl8195a = 0x914d;
HalSsiInterruptDisableRtl8195a = 0x9299;
HalSsiGetRawInterruptStatusRtl8195a = 0x93e9;
HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d;
HalSsiInitRtl8195a = 0x94d1;
_SsiReadInterrupt = 0x9ba5;
_SsiWriteInterrupt = 0x9db1;
_SsiIrqHandle = 0x9eb1;
HalI2CWrite32 = 0xa061;
HalI2CRead32 = 0xa09d;
HalI2CDeInit8195a = 0xa0dd;
HalI2CSendRtl8195a = 0xa1f1;
HalI2CReceiveRtl8195a = 0xa25d;
HalI2CEnableRtl8195a = 0xa271;
HalI2CIntrCtrl8195a = 0xa389;
HalI2CReadRegRtl8195a = 0xa3a1;
HalI2CWriteRegRtl8195a = 0xa3b1;
HalI2CSetCLKRtl8195a = 0xa3c5;
HalI2CMassSendRtl8195a = 0xa6e9;
HalI2CClrIntrRtl8195a = 0xa749;
HalI2CClrAllIntrRtl8195a = 0xa761;
HalI2CInit8195a = 0xa775;
HalI2CDMACtrl8195a = 0xaa31;
RtkI2CIoCtrl = 0xaa61;
RtkI2CPowerCtrl = 0xaa65;
HalI2COpInit = 0xaa69;
I2CIsTimeout = 0xac65;
I2CTXGDMAISRHandle = 0xb435;
I2CRXGDMAISRHandle = 0xb4c1;
RtkI2CIrqInit = 0xb54d;
RtkI2CIrqDeInit = 0xb611;
RtkI2CPinMuxInit = 0xb675;
RtkI2CPinMuxDeInit = 0xb7c9;
RtkI2CDMAInit = 0xb955;
RtkI2CInit = 0xbc95;
RtkI2CDMADeInit = 0xbdad;
RtkI2CDeInit = 0xbe4d;
RtkI2CSendUserAddr = 0xbee5;
RtkI2CSend = 0xc07d;
RtkI2CLoadDefault = 0xce51;
RtkSalI2COpInit = 0xcf21;
HalI2SWrite32 = 0xcf65;
HalI2SRead32 = 0xcf85;
HalI2SDeInitRtl8195a = 0xcfa9;
HalI2STxRtl8195a = 0xcfc9;
HalI2SRxRtl8195a = 0xd011;
HalI2SEnableRtl8195a = 0xd05d;
HalI2SIntrCtrlRtl8195a = 0xd0b1;
HalI2SReadRegRtl8195a = 0xd0d1;
HalI2SClrIntrRtl8195a = 0xd0dd;
HalI2SClrAllIntrRtl8195a = 0xd0fd;
HalI2SInitRtl8195a = 0xd11d;
GPIO_GetIPPinName_8195a = 0xd2e5;
GPIO_GetChipPinName_8195a = 0xd331;
GPIO_PullCtrl_8195a = 0xd39d;
GPIO_FuncOn_8195a = 0xd421;
GPIO_FuncOff_8195a = 0xd481;
GPIO_Int_Mask_8195a = 0xd4e9;
GPIO_Int_SetType_8195a = 0xd511;
HAL_GPIO_IrqHandler_8195a = 0xd5fd;
HAL_GPIO_MbedIrqHandler_8195a = 0xd645;
HAL_GPIO_UserIrqHandler_8195a = 0xd6a1;
HAL_GPIO_IntCtrl_8195a = 0xd6cd;
HAL_GPIO_Init_8195a = 0xd805;
HAL_GPIO_DeInit_8195a = 0xdac1;
HAL_GPIO_ReadPin_8195a = 0xdbd1;
HAL_GPIO_WritePin_8195a = 0xdc91;
HAL_GPIO_RegIrq_8195a = 0xddad;
HAL_GPIO_UnRegIrq_8195a = 0xddf5;
HAL_GPIO_UserRegIrq_8195a = 0xde15;
HAL_GPIO_UserUnRegIrq_8195a = 0xdef9;
HAL_GPIO_MaskIrq_8195a = 0xdfc1;
HAL_GPIO_UnMaskIrq_8195a = 0xe061;
HAL_GPIO_IntDebounce_8195a = 0xe101;
HAL_GPIO_GetIPPinName_8195a = 0xe1c1;
HAL_GPIO_PullCtrl_8195a = 0xe1c9;
DumpForOneBytes = 0xe259;
CmdRomHelp = 0xe419;
CmdWriteWord = 0xe491;
CmdDumpHelfWord = 0xe505;
CmdDumpWord = 0xe5f1;
CmdDumpByte = 0xe6f5;
CmdSpiFlashTool = 0xe751;
GetRomCmdNum = 0xe7a9;
CmdWriteByte = 0xe7ad;
Isspace = 0xe7ed;
Strtoul = 0xe801;
ArrayInitialize = 0xe8b1;
GetArgc = 0xe8c9;
GetArgv = 0xe8f9;
UartLogCmdExecute = 0xe95d;
UartLogShowBackSpace = 0xe9fd;
UartLogRecallOldCmd = 0xea39;
UartLogHistoryCmd = 0xea71;
UartLogCmdChk = 0xeadd;
UartLogIrqHandle = 0xebf5;
RtlConsolInit = 0xecc5;
RtlConsolTaskRom = 0xed49;
RtlExitConsol = 0xed79;
RtlConsolRom = 0xedcd;
HalTimerOpInit = 0xee0d;
HalTimerIrq2To7Handle = 0xee59;
HalGetTimerIdRtl8195a = 0xef09;
HalTimerInitRtl8195a = 0xef3d;
HalTimerDisRtl8195a = 0xf069;
HalTimerEnRtl8195a = 0xf089;
HalTimerReadCountRtl8195a = 0xf0a9;
HalTimerIrqClearRtl8195a = 0xf0bd;
HalTimerDumpRegRtl8195a = 0xf0d1;
VSprintf = 0xf129;
DiagPrintf = 0xf39d;
DiagSPrintf = 0xf3b9;
DiagSnPrintf = 0xf3d1;
prvDiagPrintf = 0xf3ed;
prvDiagSPrintf = 0xf40d;
_memcmp = 0xf429;
_memcpy = 0xf465;
_memset = 0xf511;
Rand = 0xf585;
_strncpy = 0xf60d;
_strcpy = 0xf629;
prvStrCpy = 0xf639;
_strlen = 0xf651;
_strnlen = 0xf669;
prvStrLen = 0xf699;
_strcmp = 0xf6b1;
_strncmp = 0xf6d1;
prvStrCmp = 0xf719;
StrUpr = 0xf749;
prvAtoi = 0xf769;
prvStrStr = 0xf7bd;
_strsep = 0xf7d5;
skip_spaces = 0xf815;
skip_atoi = 0xf831;
_parse_integer_fixup_radix = 0xf869;
_parse_integer = 0xf8bd;
simple_strtoull = 0xf915;
simple_strtoll = 0xf945;
simple_strtoul = 0xf965;
simple_strtol = 0xf96d;
_vsscanf = 0xf985;
_sscanf = 0xff71;
div_u64 = 0xff91;
div_s64 = 0xff99;
div_u64_rem = 0xffa1;
div_s64_rem = 0xffb1;
_strpbrk = 0xffc1;
_strchr = 0xffed;
aes_set_key = 0x10005;
aes_encrypt = 0x103d1;
aes_decrypt = 0x114a5;
AES_WRAP = 0x125c9;
AES_UnWRAP = 0x12701;
crc32_get = 0x12861;
arc4_byte = 0x12895;
rt_arc4_init = 0x128bd;
rt_arc4_crypt = 0x12901;
rt_md5_init = 0x131c1;
rt_md5_append = 0x131f5;
rt_md5_final = 0x1327d;
rt_md5_hmac = 0x132d5;
rtw_get_bit_value_from_ieee_value = 0x13449;
rtw_is_cckrates_included = 0x13475;
rtw_is_cckratesonly_included = 0x134b5;
rtw_check_network_type = 0x134dd;
rtw_set_fixed_ie = 0x1350d;
rtw_set_ie = 0x1352d;
rtw_get_ie = 0x1355d;
rtw_set_supported_rate = 0x13591;
rtw_get_rateset_len = 0x13611;
rtw_get_wpa_ie = 0x1362d;
rtw_get_wpa2_ie = 0x136c9;
rtw_get_wpa_cipher_suite = 0x13701;
rtw_get_wpa2_cipher_suite = 0x13769;
rtw_parse_wpa_ie = 0x137d1;
rtw_parse_wpa2_ie = 0x138ad;
rtw_get_sec_ie = 0x13965;
rtw_get_wps_ie = 0x13a15;
rtw_get_wps_attr = 0x13a99;
rtw_get_wps_attr_content = 0x13b49;
rtw_ieee802_11_parse_elems = 0x13b91;
str_2char2num = 0x13d9d;
key_2char2num = 0x13db9;
convert_ip_addr = 0x13dd1;
rom_psk_PasswordHash = 0x13e9d;
rom_psk_CalcGTK = 0x13ed5;
rom_psk_CalcPTK = 0x13f69;
wep_80211_encrypt = 0x14295;
wep_80211_decrypt = 0x142f5;
tkip_micappendbyte = 0x14389;
rtw_secmicsetkey = 0x143d9;
rtw_secmicappend = 0x14419;
rtw_secgetmic = 0x14435;
rtw_seccalctkipmic = 0x1449d;
tkip_phase1 = 0x145a5;
tkip_phase2 = 0x14725;
tkip_80211_encrypt = 0x14941;
tkip_80211_decrypt = 0x149d5;
aes1_encrypt = 0x14a8d;
aesccmp_construct_mic_iv = 0x14c65;
aesccmp_construct_mic_header1 = 0x14ccd;
aesccmp_construct_mic_header2 = 0x14d21;
aesccmp_construct_ctr_preload = 0x14db5;
aes_80211_encrypt = 0x14e29;
aes_80211_decrypt = 0x151ad;
_sha1_process_message_block = 0x155b9;
_sha1_pad_message = 0x15749;
rt_sha1_init = 0x157e5;
rt_sha1_update = 0x15831;
rt_sha1_finish = 0x158a9;
rt_hmac_sha1 = 0x15909;
rom_aes_128_cbc_encrypt = 0x15a65;
rom_aes_128_cbc_decrypt = 0x15ae1;
rom_rijndaelKeySetupEnc = 0x15b5d;
rom_aes_decrypt_init = 0x15c39;
rom_aes_internal_decrypt = 0x15d15;
rom_aes_decrypt_deinit = 0x16071;
rom_aes_encrypt_init = 0x16085;
rom_aes_internal_encrypt = 0x1609d;
rom_aes_encrypt_deinit = 0x16451;
bignum_init = 0x17b35;
bignum_deinit = 0x17b61;
bignum_get_unsigned_bin_len = 0x17b81;
bignum_get_unsigned_bin = 0x17b85;
bignum_set_unsigned_bin = 0x17c21;
bignum_cmp = 0x17cd1;
bignum_cmp_d = 0x17cd5;
bignum_add = 0x17cfd;
bignum_sub = 0x17d0d;
bignum_mul = 0x17d1d;
bignum_exptmod = 0x17d2d;
WPS_realloc = 0x17d51;
os_zalloc = 0x17d99;
rom_hmac_sha256_vector = 0x17dc1;
rom_hmac_sha256 = 0x17ebd;
rom_sha256_vector = 0x18009;
phy_CalculateBitShift = 0x18221;
PHY_SetBBReg_8195A = 0x18239;
PHY_QueryBBReg_8195A = 0x18279;
ROM_odm_QueryRxPwrPercentage = 0x1829d;
ROM_odm_EVMdbToPercentage = 0x182bd;
ROM_odm_SignalScaleMapping_8195A = 0x182e5;
ROM_odm_FalseAlarmCounterStatistics = 0x183cd;
ROM_odm_SetEDCCAThreshold = 0x18721;
ROM_odm_SetTRxMux = 0x18749;
ROM_odm_SetCrystalCap = 0x18771;
ROM_odm_GetDefaultCrytaltalCap = 0x187d5;
ROM_ODM_CfoTrackingReset = 0x187e9;
ROM_odm_CfoTrackingFlow = 0x18811;
curve25519_donna = 0x1965d;
aes_test_alignment_detection = 0x1a391;
aes_mode_reset = 0x1a3ed;
aes_ecb_encrypt = 0x1a3f9;
aes_ecb_decrypt = 0x1a431;
aes_cbc_encrypt = 0x1a469;
aes_cbc_decrypt = 0x1a579;
aes_cfb_encrypt = 0x1a701;
aes_cfb_decrypt = 0x1a9e5;
aes_ofb_crypt = 0x1acc9;
aes_ctr_crypt = 0x1af7d;
aes_encrypt_key128 = 0x1b289;
aes_encrypt_key192 = 0x1b2a5;
aes_encrypt_key256 = 0x1b2c1;
aes_encrypt_key = 0x1b2e1;
aes_decrypt_key128 = 0x1b351;
aes_decrypt_key192 = 0x1b36d;
aes_decrypt_key256 = 0x1b389;
aes_decrypt_key = 0x1b3a9;
aes_init = 0x1b419;
CRYPTO_chacha_20 = 0x1b41d;
CRYPTO_poly1305_init = 0x1bc25;
CRYPTO_poly1305_update = 0x1bd09;
CRYPTO_poly1305_finish = 0x1bd8d;
rom_sha512_starts = 0x1ceb5;
rom_sha512_update = 0x1d009;
rom_sha512_finish = 0x1d011;
rom_sha512 = 0x1d261;
rom_sha512_hmac_starts = 0x1d299;
rom_sha512_hmac_update = 0x1d35d;
rom_sha512_hmac_finish = 0x1d365;
rom_sha512_hmac_reset = 0x1d3b5;
rom_sha512_hmac = 0x1d3d1;
rom_sha512_hkdf = 0x1d40d;
rom_ed25519_gen_keypair = 0x1d501;
rom_ed25519_gen_signature = 0x1d505;
rom_ed25519_verify_signature = 0x1d51d;
rom_ed25519_crypto_sign_seed_keypair = 0x1d521;
rom_ed25519_crypto_sign_detached = 0x1d579;
rom_ed25519_crypto_sign_verify_detached = 0x1d655;
rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d;
rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35;
rom_ed25519_ge_p3_tobytes = 0x207d5;
rom_ed25519_ge_scalarmult_base = 0x20821;
rom_ed25519_ge_tobytes = 0x209e1;
rom_ed25519_sc_muladd = 0x20a2d;
rom_ed25519_sc_reduce = 0x2603d;
__rtl_memchr_v1_00 = 0x28a4d;
__rtl_memcmp_v1_00 = 0x28ae1;
__rtl_memcpy_v1_00 = 0x28b49;
__rtl_memmove_v1_00 = 0x28bed;
__rtl_memset_v1_00 = 0x28cb5;
__rtl_strcat_v1_00 = 0x28d49;
__rtl_strchr_v1_00 = 0x28d91;
__rtl_strcmp_v1_00 = 0x28e55;
__rtl_strcpy_v1_00 = 0x28ec9;
__rtl_strlen_v1_00 = 0x28f15;
__rtl_strncat_v1_00 = 0x28f69;
__rtl_strncmp_v1_00 = 0x28fc5;
__rtl_strncpy_v1_00 = 0x2907d;
__rtl_strstr_v1_00 = 0x293cd;
__rtl_strsep_v1_00 = 0x2960d;
__rtl_strtok_v1_00 = 0x29619;
__rtl__strtok_r_v1_00 = 0x2962d;
__rtl_strtok_r_v1_00 = 0x29691;
__rtl_close_v1_00 = 0x29699;
__rtl_fstat_v1_00 = 0x296ad;
__rtl_isatty_v1_00 = 0x296c1;
__rtl_lseek_v1_00 = 0x296d5;
__rtl_open_v1_00 = 0x296e9;
__rtl_read_v1_00 = 0x296fd;
__rtl_write_v1_00 = 0x29711;
__rtl_sbrk_v1_00 = 0x29725;
__rtl_ltoa_v1_00 = 0x297bd;
__rtl_ultoa_v1_00 = 0x29855;
__rtl_dtoi_v1_00 = 0x298c5;
__rtl_dtoi64_v1_00 = 0x29945;
__rtl_dtoui_v1_00 = 0x299dd;
__rtl_ftol_v1_00 = 0x299e5;
__rtl_itof_v1_00 = 0x29a51;
__rtl_itod_v1_00 = 0x29ae9;
__rtl_i64tod_v1_00 = 0x29b79;
__rtl_uitod_v1_00 = 0x29c55;
__rtl_ftod_v1_00 = 0x29d2d;
__rtl_dtof_v1_00 = 0x29de9;
__rtl_uitof_v1_00 = 0x29e89;
__rtl_fadd_v1_00 = 0x29f65;
__rtl_fsub_v1_00 = 0x2a261;
__rtl_fmul_v1_00 = 0x2a559;
__rtl_fdiv_v1_00 = 0x2a695;
__rtl_dadd_v1_00 = 0x2a825;
__rtl_dsub_v1_00 = 0x2aed9;
__rtl_dmul_v1_00 = 0x2b555;
__rtl_ddiv_v1_00 = 0x2b8ad;
__rtl_dcmpeq_v1_00 = 0x2be4d;
__rtl_dcmplt_v1_00 = 0x2bebd;
__rtl_dcmpgt_v1_00 = 0x2bf51;
__rtl_dcmple_v1_00 = 0x2c049;
__rtl_fcmplt_v1_00 = 0x2c139;
__rtl_fcmpgt_v1_00 = 0x2c195;
__rtl_cos_f32_v1_00 = 0x2c229;
__rtl_sin_f32_v1_00 = 0x2c435;
__rtl_fabs_v1_00 = 0x2c639;
__rtl_fabsf_v1_00 = 0x2c641;
__rtl_dtoa_r_v1_00 = 0x2c77d;
__rom_mallocr_init_v1_00 = 0x2d7d1;
__rtl_free_r_v1_00 = 0x2d841;
__rtl_malloc_r_v1_00 = 0x2da31;
__rtl_realloc_r_v1_00 = 0x2df55;
__rtl_memalign_r_v1_00 = 0x2e331;
__rtl_valloc_r_v1_00 = 0x2e421;
__rtl_pvalloc_r_v1_00 = 0x2e42d;
__rtl_calloc_r_v1_00 = 0x2e441;
__rtl_cfree_r_v1_00 = 0x2e4a9;
__rtl_Balloc_v1_00 = 0x2e515;
__rtl_Bfree_v1_00 = 0x2e571;
__rtl_i2b_v1_00 = 0x2e585;
__rtl_multadd_v1_00 = 0x2e599;
__rtl_mult_v1_00 = 0x2e629;
__rtl_pow5mult_v1_00 = 0x2e769;
__rtl_hi0bits_v1_00 = 0x2e809;
__rtl_d2b_v1_00 = 0x2e845;
__rtl_lshift_v1_00 = 0x2e901;
__rtl_cmp_v1_00 = 0x2e9bd;
__rtl_diff_v1_00 = 0x2ea01;
__rtl_sread_v1_00 = 0x2eae9;
__rtl_seofread_v1_00 = 0x2eb39;
__rtl_swrite_v1_00 = 0x2eb3d;
__rtl_sseek_v1_00 = 0x2ebc1;
__rtl_sclose_v1_00 = 0x2ec11;
__rtl_sbrk_r_v1_00 = 0x2ec41;
__rtl_fflush_r_v1_00 = 0x2ef8d;
__rtl_vfprintf_r_v1_00 = 0x2f661;
__rtl_fpclassifyd = 0x30c15;
CpkClkTbl = 0x30c68;
ROM_IMG1_VALID_PATTEN = 0x30c80;
SpicCalibrationPattern = 0x30c88;
SpicInitCPUCLK = 0x30c98;
BAUDRATE = 0x30ca8;
OVSR = 0x30d1c;
DIV = 0x30d90;
OVSR_ADJ = 0x30e04;
__AES_rcon = 0x30e78;
__AES_Te4 = 0x30ea0;
I2CDmaChNo = 0x312a0;
UartLogRomCmdTable = 0x316a0;
_HalRuartOp = 0x31700;
_HalGdmaOp = 0x31760;
RTW_WPA_OUI_TYPE = 0x3540c;
WPA_CIPHER_SUITE_NONE = 0x35410;
WPA_CIPHER_SUITE_WEP40 = 0x35414;
WPA_CIPHER_SUITE_TKIP = 0x35418;
WPA_CIPHER_SUITE_CCMP = 0x3541c;
WPA_CIPHER_SUITE_WEP104 = 0x35420;
RSN_CIPHER_SUITE_NONE = 0x35424;
RSN_CIPHER_SUITE_WEP40 = 0x35428;
RSN_CIPHER_SUITE_TKIP = 0x3542c;
RSN_CIPHER_SUITE_CCMP = 0x35430;
RSN_CIPHER_SUITE_WEP104 = 0x35434;
RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444;
RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448;
RSN_VERSION_BSD = 0x3544c;
rom_wps_Te0 = 0x35988;
rom_wps_rcons = 0x35d88;
rom_wps_Td4s = 0x35d94;
rom_wps_Td0 = 0x35e94;
NewVectorTable = 0x10000000;
UserIrqFunTable = 0x10000100;
UserIrqDataTable = 0x10000200;
__rom_bss_start__ = 0x10000300;
CfgSysDebugWarn = 0x10000300;
CfgSysDebugInfo = 0x10000304;
CfgSysDebugErr = 0x10000308;
ConfigDebugWarn = 0x1000030c;
ConfigDebugInfo = 0x10000310;
ConfigDebugErr = 0x10000314;
HalTimerOp = 0x10000318;
GPIOState = 0x10000334;
gTimerRecord = 0x1000034c;
SSI_DBG_CONFIG = 0x10000350;
_pHAL_Gpio_Adapter = 0x10000354;
Timer2To7VectorTable = 0x10000358;
pUartLogCtl = 0x10000384;
UartLogBuf = 0x10000388;
UartLogCtl = 0x10000408;
UartLogHistoryBuf = 0x10000430;
ArgvArray = 0x100006ac;
rom_wlan_ram_map = 0x100006d4;
FalseAlmCnt = 0x100006e0;
ROMInfo = 0x10000720;
DM_CfoTrack = 0x10000738;
rom_libgloss_ram_map = 0x10000760;
__rtl_errno = 0x10000bc4;
_rtl_impure_ptr = 0x10001c60;
}
/* DATA_RAM: We cannot put Code(.text) in DATA_RAM, this region is reserved for Image1(boot loader).
But we can put .data/.bss of Image2 in this region */
MEMORY
{
TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
ROM_USED_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 0x10006000-0x10000bc8
DATA_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 0x10006000 - 0x10002100
BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 0x10070000 - 0x10006000
SD_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* _reset_init : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
__rom_bss_start__ = 0x10000300;
__rom_bss_end__ = 0x10000bc8;
__ram_table_start__ = 0x10000bc8;
/*
.ram.start.table :
{
} > ROM_USED_RAM
*/
.image2.table :
{
__image2_start__ = .;
__image2_entry_func__ = .;
KEEP(*(SORT(.image2.ram.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
} > BD_RAM
.text :
{
. = ALIGN(4);
*(.infra.ram.start*)
*(.mon.ram.text*)
*(.hal.flash.text*)
*(.hal.sdrc.text*)
*(.hal.gpio.text*)
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > BD_RAM
__etext = .;
__data_start__ = .;
.data :
{
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
} > BD_RAM
__data_end__ = .;
__image2_end__ = .;
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > BD_RAM
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > BD_RAM
__exidx_end = .;
.bss :
{
__bss_start__ = .;
*(.bss*)
*(.bdsram.data*)
*(COMMON)
__bss_end__ = .;
} > BD_RAM
.bf_data :
{
__buffer_data_start__ = .;
*(.bfsram.data*)
__buffer_data_end__ = .;
} > BD_RAM
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > BD_RAM
.TCM_overlay :
{
*(.tcm.heap*)
} > TCM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > BD_RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(BD_RAM) + LENGTH(BD_RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM exceeds ram limit")
}

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a Normal file
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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a Normal file
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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rom.a Normal file
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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
//define symbol __ICFEDIT_intvec_start__ = 0x00000000;
//include "main.icf";
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF;
define symbol __ICFEDIT_region_TCM_start__ = 0x1FFF0000;
define symbol __ICFEDIT_region_TCM_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_ROM_USED_RAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_ROM_USED_RAM_end__ = 0x10005FFF;
//define symbol __ICFEDIT_region_RECY_RAM_start__ = 0x10002090;
//define symbol __ICFEDIT_region_RECY_RAM_end__ = 0x100037FF;
if( !isdefinedsymbol( __ICFEDIT_region_BD_RAM_start__ ) ) {
define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10006000;
}
if( !isdefinedsymbol( __ICFEDIT_region_BD_RAM_end__ ) ) {
define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1006FFFF;
}
define symbol __ICFEDIT_region_SDRAM_RAM_start__ = 0x30000000;
define symbol __ICFEDIT_region_SDRAM_RAM_end__ = 0x301FFFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x19000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__];
define region ROM_USED_RAM_region = mem:[from __ICFEDIT_region_ROM_USED_RAM_start__ to __ICFEDIT_region_ROM_USED_RAM_end__];
//define region RECY_RAM_region = mem:[from __ICFEDIT_region_RECY_RAM_start__ to __ICFEDIT_region_RECY_RAM_end__];
define region BD_RAM_region = mem:[from __ICFEDIT_region_BD_RAM_start__ to __ICFEDIT_region_BD_RAM_end__];
define region SDRAM_RAM_region = mem:[from __ICFEDIT_region_SDRAM_RAM_start__ to __ICFEDIT_region_SDRAM_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
//initialize by copy { readwrite };
//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
//do not initialize { section * };
//place at address mem:__ICFEDIT_intvec_start__ { readonly section .vectors_table };
/*place in RAM_region { readwrite, block CSTACK, block HEAP };*/
//place in TCM_region { readwrite };
/****************************************
* ROM Section config *
****************************************/
keep { section .rom };
place at start of ROM_region { section .rom };
/****************************************
* BD RAM Section config *
****************************************/
keep { section .ram_dedecated_vector_table* };
define block .vector_table with fixed order{section .ram_dedecated_vector_table*};
keep { section .ram_user_define_irq_table* };
define block .user_vector_table with fixed order{section .ram_user_define_irq_table*};
keep { section .ram_user_define_data_table* };
define block .user_data_table with fixed order{section .ram_user_define_data_table*};
define block .rom.bss with fixed order{ section .hal.ram.bss* object hal_misc.o,
section .hal.ram.bss* object hal_pinmux.o,
section .hal.ram.bss* object diag.o,
section .hal.ram.bss* object rtl8195a_ssi_rom.o,
section .hal.ram.bss* object rtl8195a_gpio.o,
section .hal.ram.bss*,
section .timer2_7_vector_table.data*,
section .infra.ram.bss*,
section .mon.ram.bss*,
section .wlan_ram_map* object rom_wlan_ram_map.o,
section .wlan_ram_map*,
section .libc.ram.bss*,
};
keep { section .start.ram.data* };
define block .ram.start.table with fixed order{ section .start.ram.data* };
keep { section .image1.validate.rodata* };
keep { section .infra.ram.data* };
keep { section .timer.ram.data* };
keep { section .hal.ram.data* };
define block .ram_image1.data with fixed order{ section .image1.validate.rodata*,
section .infra.ram.data*,
section .timer.ram.data*,
section .cutb.ram.data*,
section .hal.ram.data* object rom.o, // for standard libaray __impure_data_ptr
section .cutc.ram.data*,
section .hal.ram.data*
};
define block .ram_image1.bss with fixed order{ //section .hal.flash.data*,
section .hal.sdrc.data*
};
define block .ram_image1.text with fixed order{ section .hal.ram.text*,
section .hal.sdrc.text*,
//section .text* object startup.o,
section .infra.ram.text*,
};
define block IMAGE1 with fixed order { section LOADER };
define block IMAGE1_DBG with fixed order { block .ram.start.table, block .ram_image1.data, block .ram_image1.bss, block .ram_image1.text };
place at start of ROM_USED_RAM_region {
block .vector_table,
block .user_vector_table,
block .user_data_table,
block .rom.bss,
block IMAGE1
};
keep { section .image2.ram.data* };
define block .image2.start.table1 with fixed order{ section .image2.ram.data* };
keep { section .image2.validate.rodata*, section .custom.validate.rodata* };
define block .image2.start.table2 with fixed order{ section .image2.validate.rodata*, section .custom.validate.rodata* };
define block SHT$$PREINIT_ARRAY { preinit_array };
define block SHT$$INIT_ARRAY { init_array };
define block CPP_INIT with alignment = 8, fixed order {
block SHT$$PREINIT_ARRAY,
block SHT$$INIT_ARRAY
};
define block FPB_REMAP with alignment = 256,fixed order {
section .fpb.remap*
};
define block .ram_image2.text with fixed order{ section .infra.ram.start*,
section .rodata*,
block CPP_INIT,
section .mon.ram.text*,
section .hal.flash.text*,
section .hal.gpio.text*,
section .text* object main.o,
section .text*,
section .wlan.text,
section .wps.text,
section CODE,
section .otg.rom.text,
section Veneer object startup.o,
section __DLIB_PERTHREAD,
section .iar.dynexit*,
//section .mdns.text
};
define block .ram.data with fixed order{ readwrite, readonly,
section .data*,
section .wlan.data,
section .wps.data,
section DATA,
section .ram.otg.data.a,
section .iar.init_table,
//section .mdns.data
};
define block IMAGE2 with fixed order { block .image2.start.table1, block .image2.start.table2, block .ram_image2.text, block .ram.data };
define block .ram.bss with fixed order{ section .bss*,
section .ssl_ram_map,
section .hal.flash.data*,
section .hal.gpio.data*,
section COMMON,
section .bdsram.data*,
section .bss* object heap_4.o
};
define block .bf_data with fixed order{ section .bfsram.data* };
define block .heap with fixed order{ section .heap* };
define block .stack_dummy with fixed order { section .stack };
place at start of BD_RAM_region {
block IMAGE2,
//block IMAGE1_DBG,
block .ram.bss,
//block .bf_data,
};
//place at address mem:0x10052b00 { readwrite,
place at end of BD_RAM_region {
block .bf_data,
block HEAP,
};
define block SDRAM with fixed order{ section .sdram.text*,
section .sdram.data*,
section .mdns.text*,
section .mdns.data*,
block FPB_REMAP
};
define block SDRBSS with fixed order{
section .sdram.bss*
};
place at start of SDRAM_RAM_region {
block SDRAM,
block SDRBSS,
//block IMAGE1_DBG
};
/* TCM placement */
define overlay TCM_overlay {
section .tcm.heap,
section .bss object lwip_mem.o,
section .bss object lwip_memp.o,
block .heap,
block .stack_dummy
};
/* dummy code placement */
define overlay TCM_overlay { block IMAGE1_DBG };
place at start of TCM_region { overlay TCM_overlay };
place at end of TCM_region { block CSTACK};
define exported symbol __rom_bss_start__ = 0x10000300; // use in rom
define exported symbol __rom_bss_end__ = 0x10000bc8; // use in rom
define exported symbol __ram_start_table_start__= 0x10000bc8; // use in rom
define exported symbol __image1_validate_code__= 0x10000bdc; // needed by ram code
define exported symbol _rtl_impure_ptr = 0x10001c60; // for standard library
define exported symbol __sdio_rom_bss_start__ = 0x1006D000;
define exported symbol __sdio_rom_bss_end__ = 0x1006fa10;

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/cmsis.h Normal file
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/* mbed Microcontroller Library
* A generic CMSIS include header
*******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "rtl8195a.h"
#include "cmsis_nvic.h"
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/cmsis_nvic.h Normal file
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/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
#define NVIC_ROM_VECTOR_ADDRESS (0x00000000) // Initial vector position at start of ROM
// CORE: 64 vectors = 64 bytes from 0x00 to 0x3F
// MCU Peripherals: 85 vectors = 340 bytes from 0x40 to ...
// Total: 128 vectors = 512 bytes (0x200) to be reserved in RAM
#define NVIC_NUM_VECTORS 128
#ifndef NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET 64
#endif
#include "cmsis.h"
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/diag.h Normal file
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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
#ifndef _DIAG_H_
#define _DIAG_H_
#include "platform_autoconf.h"
#include "basic_types.h"
#include <stddef.h> /* for size_t */
extern u32 ConfigDebugErr;
extern u32 ConfigDebugInfo;
extern u32 ConfigDebugWarn;
extern u32 CfgSysDebugErr;
extern u32 CfgSysDebugInfo;
extern u32 CfgSysDebugWarn;
#define DBG_ERR_MSG_ON(x) (ConfigDebugErr |= (x))
#define DBG_WARN_MSG_ON(x) (ConfigDebugWarn |= (x))
#define DBG_INFO_MSG_ON(x) (ConfigDebugInfo |= (x))
#define DBG_ERR_MSG_OFF(x) (ConfigDebugErr &= ~(x))
#define DBG_WARN_MSG_OFF(x) (ConfigDebugWarn &= ~(x))
#define DBG_INFO_MSG_OFF(x) (ConfigDebugInfo &= ~(x))
// Define debug group
#define _DBG_BOOT_ 0x00000001
#define _DBG_GDMA_ 0x00000002
#define _DBG_GPIO_ 0x00000004
#define _DBG_TIMER_ 0x00000008
#define _DBG_I2C_ 0x00000010
#define _DBG_I2S_ 0x00000020
#define _DBG_MII_ 0x00000040
#define _DBG_NFC_ 0x00000080
#define _DBG_PCM_ 0x00000100
#define _DBG_PWM_ 0x00000200
#define _DBG_SDIO_ 0x00000400
#define _DBG_SSI_ 0x00000800
#define _DBG_SPI_FLASH_ 0x00001000
#define _DBG_SDR_ 0x00002000
#define _DBG_UART_ 0x00004000
#define _DBG_USB_OTG_ 0x00008000
#define _DBG_USB_CORE_ 0x00010000
#define _DBG_CRYPTO_ 0x00020000
#define _DBG_ADC_ 0x00040000
#define _DBG_DAC_ 0x00080000
#define _DBG_MISC_ 0x40000000
#define _DBG_FAULT_ 0x80000000
enum _SYSTEM_DBG_DEFINE_ {
_SYSDBG_MISC_ = 1<<0,
_SYSDBG_MAILBOX_ = 1<<1,
_SYSDBG_TIMER_ = 1<<2
};
typedef uint32_t SYSTEM_DBG;
extern
_LONG_CALL_ROM_ u32
DiagPrintf(
IN const char *fmt, ...
);
u32
DiagSPrintf(
IN u8 *buf,
IN const char *fmt, ...
);
int
prvDiagPrintf(
IN const char *fmt, ...
);
int
prvDiagSPrintf(
IN char *buf,
IN const char *fmt, ...
);
#define _DbgDump DiagPrintf
#define DRIVER_PREFIX "RTL8195A[Driver]: "
#define HAL_PREFIX "RTL8195A[HAL]: "
#define DMA_PREFIX "RTL8195A[DMA]: "
#define SDIO_PREFIX "RTL8195A[SDIO]"
#define MBOX_PREFIX "[OS-MBOX]"
#define TIMER_PREFIX "[OS-TMR]"
#define BOOT_ERR_PREFIX "[BOOT Err]"
#define BOOT_WARN_PREFIX "[BOOT Wrn]"
#define BOOT_INFO_PREFIX "[BOOT Inf]"
#define GDMA_ERR_PREFIX "[GDMA Err]"
#define GDMA_WARN_PREFIX "[GDMA Wrn]"
#define GDMA_INFO_PREFIX "[GDMA Inf]"
#define GPIO_ERR_PREFIX "[GPIO Err]"
#define GPIO_WARN_PREFIX "[GPIO Wrn]"
#define GPIO_INFO_PREFIX "[GPIO Inf]"
#define TIMER_ERR_PREFIX "[TIMR Err]"
#define TIMER_WARN_PREFIX "[TIMR Wrn]"
#define TIMER_INFO_PREFIX "[TIMR Inf]"
#define I2C_ERR_PREFIX "[I2C Err]"
#define I2C_WARN_PREFIX "[I2C Wrn]"
#define I2C_INFO_PREFIX "[I2C Inf]"
#define I2S_ERR_PREFIX "[I2S Err]"
#define I2S_WARN_PREFIX "[I2S Wrn]"
#define I2S_INFO_PREFIX "[I2S Inf]"
#define MII_ERR_PREFIX "[MII Err]"
#define MII_WARN_PREFIX "[MII Wrn]"
#define MII_INFO_PREFIX "[MII Inf]"
#define NFC_ERR_PREFIX "[NFC Err]"
#define NFC_WARN_PREFIX "[NFC Wrn]"
#define NFC_INFO_PREFIX "[NFC Inf]"
#define PCM_ERR_PREFIX "[PCM Err]"
#define PCM_WARN_PREFIX "[PCM Wrn]"
#define PCM_INFO_PREFIX "[PCM Inf]"
#define PWM_ERR_PREFIX "[PWM Err]"
#define PWM_WARN_PREFIX "[PWM Wrn]"
#define PWM_INFO_PREFIX "[PWM Inf]"
#define SSI_ERR_PREFIX "[SSI Err]"
#define SSI_WARN_PREFIX "[SSI Wrn]"
#define SSI_INFO_PREFIX "[SSI Inf]"
#define SDIO_ERR_PREFIX "[SDIO Err]"
#define SDIO_WARN_PREFIX "[SDIO Wrn]"
#define SDIO_INFO_PREFIX "[SDIO Inf]"
#define SPIF_ERR_PREFIX "[SPIF Err]"
#define SPIF_WARN_PREFIX "[SPIF Wrn]"
#define SPIF_INFO_PREFIX "[SPIF Inf]"
#define SDR_ERR_PREFIX "[SDR Err]"
#define SDR_WARN_PREFIX "[SDR Wrn]"
#define SDR_INFO_PREFIX "[SDR Inf]"
#define UART_ERR_PREFIX "[UART Err]"
#define UART_WARN_PREFIX "[UART Wrn]"
#define UART_INFO_PREFIX "[UART Inf]"
#define USB_ERR_PREFIX "[USB Err]"
#define USB_WARN_PREFIX "[USB Wrn]"
#define USB_INFO_PREFIX "[USB Inf]"
#define IPSEC_ERR_PREFIX "[CRYP Err]"
#define IPSEC_WARN_PREFIX "[CRYP Wrn]"
#define IPSEC_INFO_PREFIX "[CRYP Inf]"
#define ADC_ERR_PREFIX "[ADC Err]"
#define ADC_WARN_PREFIX "[ADC Wrn]"
#define ADC_INFO_PREFIX "[ADC Inf]"
#define DAC_ERR_PREFIX "[DAC Err]"
#define DAC_WARN_PREFIX "[DAC Wrn]"
#define DAC_INFO_PREFIX "[DAC Inf]"
#define MISC_ERR_PREFIX "[MISC Err]"
#define MISC_WARN_PREFIX "[MISC Wrn]"
#define MISC_INFO_PREFIX "[MISC Inf]"
#define OTG_ERR_PREFIX "[OTG Err]"
#define OTG_WARN_PREFIX "[OTG Wrn]"
#define OTG_INFO_PREFIX "[OTG Inf]"
#define OTG_PREFIX "RTL8195A[OTG]: "
#define OTG_PREFIX_LVL "RTL8195A[OTG_LVL_%2x]: "
//#ifdef
#define CONFIG_DEBUG_ERROR 1
#define CONFIG_DEBUG_WARN 1
#define CONFIG_DEBUG_INFO 1
#ifndef likely
#define likely(x) (x)
#define unlikely(x) (x)
#endif
#ifdef CONFIG_DEBUG_LOG
#if CONFIG_DEBUG_ERROR // if Build-In Debug Error Message
#define DBG_BOOT_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_BOOT_)) \
_DbgDump("\r" BOOT_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_GDMA_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_GDMA_)) \
_DbgDump("\r" GDMA_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_GPIO_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_GPIO_)) \
_DbgDump("\r" GPIO_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_TIMER_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_TIMER_)) \
_DbgDump("\r" TIMER_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_I2C_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_I2C_)) \
_DbgDump("\r" I2C_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_I2S_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_I2S_)) \
_DbgDump("\r" I2S_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_MII_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_MII_)) \
_DbgDump("\r" MII_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_NFC_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_NFC_)) \
_DbgDump("\r" NFC_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_PCM_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_PCM_)) \
_DbgDump("\r" PCM_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_PWM_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_PWM_)) \
_DbgDump("\r" PWM_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SSI_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_SSI_)) \
_DbgDump("\r" SSI_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SDIO_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_SDIO_)) \
_DbgDump("\r" SDIO_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SPIF_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_SPI_FLASH_)) \
_DbgDump("\r" SPIF_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SDR_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_SDR_)) \
_DbgDump("\r" SDR_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_UART_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_UART_)) \
_DbgDump("\r" UART_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_USBOTG_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_USB_OTG_)) \
_DbgDump("\r" __VA_ARGS__);\
}while(0)
#define DBG_USBCOR_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_USB_CORE_)) \
_DbgDump("\r" USB_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_CRYPTO_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_CRYPTO_)) \
_DbgDump("\r" IPSEC_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_ADC_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_ADC_)) \
_DbgDump("\r" ADC_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_DAC_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_DAC_)) \
_DbgDump("\r" DAC_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define MSG_MBOX_ERR(...) do {\
if (likely(CfgSysDebugErr & _SYSDBG_MAILBOX_)) \
_DbgDump("\r" MBOX_PREFIX __VA_ARGS__);\
}while(0)
#define MSG_TIMER_ERR(...) do {\
if (likely(CfgSysDebugErr & _SYSDBG_TIMER_)) \
_DbgDump("\r" TIMER_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_OTG(...) do{\
if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \
_DbgDump("\r" OTG_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_OTG_INFO(...) do{\
if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \
_DbgDump("\r" OTG_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_OTG_WARN(...) do{\
if (unlikely(ConfigDebugWarn & _DBG_USB_OTG_)) \
_DbgDump("\r" OTG_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_OTG_ERR(...) do{\
if (unlikely(ConfigDebugErr & _DBG_USB_OTG_)) \
_DbgDump("\r" OTG_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_OTG_LVL(LVL,...) do{\
if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)){ \
_DbgDump("\r" OTG_PREFIX_LVL,LVL);\
_DbgDump(__VA_ARGS__);\
}\
}while(0)
#define DBG_MISC_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_MISC_)) \
_DbgDump("\r" MISC_ERR_PREFIX __VA_ARGS__);\
}while(0)
#else // else of "#if CONFIG_DEBUG_ERROR"
#define DBG_BOOT_ERR(...)
#define DBG_GDMA_ERR(...)
#define DBG_GPIO_ERR(...)
#define DBG_TIMER_ERR(...)
#define DBG_I2C_ERR(...)
#define DBG_I2S_ERR(...)
#define DBG_MII_ERR(...)
#define DBG_NFC_ERR(...)
#define DBG_PCM_ERR(...)
#define DBG_PWM_ERR(...)
#define DBG_SSI_ERR(...)
#define DBG_SDIO_ERR(...)
#define DBG_SPIF_ERR(...)
#define DBG_SDR_ERR(...)
#define DBG_UART_ERR(...)
#define DBG_USBOTG_ERR(...)
#define DBG_USBCOR_ERR(...)
#define DBG_CRYPTO_ERR(...)
#define DBG_ADC_ERR(...)
#define DBG_DAC_ERR(...)
#define MSG_MBOX_ERR(...)
#define MSG_TIMER_ERR(...)
#define DBG_8195A_OTG(...)
#define DBG_8195A_OTG_LVL(LVL,...)
#define DBG_8195A_OTG_INFO(...)
#define DBG_8195A_OTG_WARN(...)
#define DBG_8195A_OTG_ERR(...)
#endif // end of else of "#if CONFIG_DEBUG_ERROR"
// =============================================================
#if CONFIG_DEBUG_WARN // if Build-In Debug Warring Message
#define DBG_BOOT_WARN(...) do {\
if (unlikely(ConfigDebugWarn& _DBG_BOOT_)) \
_DbgDump("\r" BOOT_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_GDMA_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_GDMA_)) \
_DbgDump("\r" GDMA_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_GPIO_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_GPIO_)) \
_DbgDump("\r" GPIO_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_TIMER_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_TIMER_)) \
_DbgDump("\r" TIMER_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_I2C_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_I2C_)) \
_DbgDump("\r" I2C_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_I2S_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_I2S_)) \
_DbgDump("\r" I2S_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_MII_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_MII_)) \
_DbgDump("\r" MII_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_NFC_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_NFC_)) \
_DbgDump("\r" NFC_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_PCM_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_PCM_)) \
_DbgDump("\r" PCM_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_PWM_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_PWM_)) \
_DbgDump("\r" PWM_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SSI_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_SSI_)) \
_DbgDump("\r" SSI_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SDIO_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_SDIO_)) \
_DbgDump("\r" SDIO_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SPIF_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_SPI_FLASH_)) \
_DbgDump("\r" SPIF_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SDR_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_SDR_)) \
_DbgDump("\r" SDR_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_UART_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_UART_)) \
_DbgDump("\r" UART_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_USBOTG_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_USB_OTG_)) \
_DbgDump("\r" __VA_ARGS__);\
}while(0)
#define DBG_USBCOR_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_USB_CORE_)) \
_DbgDump("\r" USB_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_CRYPTO_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_CRYPTO_)) \
_DbgDump("\r" IPSEC_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_ADC_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_ADC_)) \
_DbgDump("\r" ADC_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_DAC_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_DAC_)) \
_DbgDump("\r" DAC_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define MSG_MBOX_WARN(...) do {\
if (unlikely(CfgSysDebugWarn& _SYSDBG_MAILBOX_)) \
_DbgDump("\r" MBOX_PREFIX __VA_ARGS__);\
}while(0)
#define MSG_TIMER_WARN(...) do {\
if (unlikely(CfgSysDebugWarn & _SYSDBG_TIMER_)) \
_DbgDump("\r" TIMER_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_MISC_WARN(...) do {\
if (likely(ConfigDebugWarn & _DBG_MISC_)) \
_DbgDump("\r" MISC_WARN_PREFIX __VA_ARGS__);\
}while(0)
#else // else of "#if CONFIG_DEBUG_WARN"
#define DBG_BOOT_WARN(...)
#define DBG_GDMA_WARN(...)
#define DBG_GPIO_WARN(...)
#define DBG_TIMER_WARN(...)
#define DBG_I2C_WARN(...)
#define DBG_I2S_WARN(...)
#define DBG_MII_WARN(...)
#define DBG_NFC_WARN(...)
#define DBG_PCM_WARN(...)
#define DBG_PWM_WARN(...)
#define DBG_SSI_WARN(...)
#define DBG_SDIO_WARN(...)
#define DBG_SPIF_WARN(...)
#define DBG_SDR_WARN(...)
#define DBG_UART_WARN(...)
#define DBG_USBOTG_WARN(...)
#define DBG_USBCOR_WARN(...)
#define DBG_CRYPTO_WARN(...)
#define DBG_ADC_WARN(...)
#define DBG_DAC_WARN(...)
#define DBG_MISC_WARN(...)
#define MSG_MBOX_WARN(...)
#define MSG_TIMER_WARN(...)
#endif // end of else of "#if CONFIG_DEBUG_WARN"
// =============================================================
#if CONFIG_DEBUG_INFO // if Build-In Debug Information Message
#define DBG_BOOT_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_BOOT_)) \
_DbgDump("\r" BOOT_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_GDMA_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_GDMA_)) \
_DbgDump("\r" GDMA_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_GPIO_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_GPIO_)) \
_DbgDump("\r" GPIO_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_TIMER_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_TIMER_)) \
_DbgDump("\r" TIMER_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_I2C_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_I2C_)) \
_DbgDump("\r" I2C_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_I2S_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_I2S_)) \
_DbgDump("\r" I2S_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_MII_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_MII_)) \
_DbgDump("\r" MII_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_NFC_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_NFC_)) \
_DbgDump("\r" NFC_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_PCM_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_PCM_)) \
_DbgDump("\r" PCM_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_PWM_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_PWM_)) \
_DbgDump("\r" PWM_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SSI_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_SSI_)) \
_DbgDump("\r" SSI_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SDIO_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_SDIO_)) \
_DbgDump("\r" SDIO_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SPIF_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_SPI_FLASH_)) \
_DbgDump("\r" SPIF_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SDR_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_SDR_)) \
_DbgDump("\r" SDR_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_UART_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_UART_)) \
_DbgDump("\r" UART_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_USBOTG_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \
_DbgDump("\r" __VA_ARGS__);\
}while(0)
#define DBG_USBCOR_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_USB_CORE_)) \
_DbgDump("\r" USB_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_CRYPTO_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_CRYPTO_)) \
_DbgDump("\r" IPSEC_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_ADC_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_ADC_)) \
_DbgDump("\r" ADC_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_DAC_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_DAC_)) \
_DbgDump("\r" DAC_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define MSG_MBOX_INFO(...) do {\
if (unlikely(CfgSysDebugInfo & _SYSDBG_MAILBOX_)) \
_DbgDump("\r" MBOX_PREFIX __VA_ARGS__);\
}while(0)
#define MSG_TIMER_INFO(...) do {\
if (unlikely(CfgSysDebugInfo & _SYSDBG_TIMER_)) \
_DbgDump("\r" TIMER_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_MISC_INFO(...) do {\
if (likely(ConfigDebugInfo & _DBG_MISC_)) \
_DbgDump("\r" MISC_INFO_PREFIX __VA_ARGS__);\
}while(0)
#else // else of "#if CONFIG_DEBUG_INFO"
#define DBG_BOOT_INFO(...)
#define DBG_GDMA_INFO(...)
#define DBG_GPIO_INFO(...)
#define DBG_TIMER_INFO(...)
#define DBG_I2C_INFO(...)
#define DBG_I2S_INFO(...)
#define DBG_MII_INFO(...)
#define DBG_NFC_INFO(...)
#define DBG_PCM_INFO(...)
#define DBG_PWM_INFO(...)
#define DBG_SSI_INFO(...)
#define DBG_SDIO_INFO(...)
#define DBG_SPIF_INFO(...)
#define DBG_SDR_INFO(...)
#define DBG_UART_INFO(...)
#define DBG_USBOTG_INFO(...)
#define DBG_USBCOR_INFO(...)
#define DBG_CRYPTO_INFO(...)
#define DBG_ADC_INFO(...)
#define DBG_DAC_INFO(...)
#define DBG_MISC_INFO(...)
#define MSG_MBOX_INFO(...)
#define MSG_TIMER_INFO(...)
#endif // end of else of "#if CONFIG_DEBUG_INFO"
#define DBG_8195A_DRIVER(...) do {\
if (unlikely(ConfigDebugErr & (_DBG_I2S_|_DBG_PCM_|_DBG_TIMER_))) \
_DbgDump("\r" DRIVER_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_HAL(...) do {\
if (unlikely(ConfigDebugErr & (_DBG_SDR_|_DBG_MISC_))) \
_DbgDump("\r" HAL_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_DMA(...) do {\
if (unlikely(ConfigDebugErr & _DBG_GDMA_)) \
_DbgDump("\r" DMA_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_SDIO(...) do {\
if (unlikely(ConfigDebugErr & _DBG_SDIO_)) \
_DbgDump("\r" SDIO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A(...) do {\
if (unlikely(ConfigDebugErr & _DBG_MISC_)) \
_DbgDump("\r" __VA_ARGS__);\
}while(0)
#define MONITOR_LOG(...) do {\
if (unlikely(ConfigDebugErr & _DBG_MISC_)) \
_DbgDump( __VA_ARGS__);\
}while(0)
#define DBG_ERROR_LOG(...) do {\
if (unlikely(ConfigDebugErr & _DBG_FAULT_)) \
_DbgDump( __VA_ARGS__);\
}while(0)
#ifdef __GNUC__
#define DBG_ASSERT(x) do {\
if (unlikely(!(x))) \
_DbgDump("Assertion: %s:%s, %d\n", __FILE__, __func__, __LINE__);\
}while(0)
#endif
#ifdef __ICCARM__
#define DBG_ASSERT(x) do {\
if (unlikely(!(x))) \
_DbgDump("Assertion: %s:%s, %d\n", __FILE__, __func__, __LINE__);\
}while(0)
#endif
#else // else of "#if CONFIG_DEBUG_LOG"
#define DBG_8195A_DRIVER(...)
#define DBG_8195A_HAL(...)
#define DBG_8195A(...)
#define DBG_8195A_DMA(...)
#define MONITOR_LOG(...)
#define DBG_ERROR_LOG(...)
#define DBG_8195A_SDIO(...)
#define DBG_BOOT_ERR(...)
#define DBG_GDMA_ERR(...)
#define DBG_GPIO_ERR(...)
#define DBG_TIMER_ERR(...)
#define DBG_I2C_ERR(...)
#define DBG_I2S_ERR(...)
#define DBG_MII_ERR(...)
#define DBG_NFC_ERR(...)
#define DBG_PCM_ERR(...)
#define DBG_PWM_ERR(...)
#define DBG_SSI_ERR(...)
#define DBG_SDIO_ERR(...)
#define DBG_SPIF_ERR(...)
#define DBG_SDR_ERR(...)
#define DBG_UART_ERR(...)
#define DBG_USBOTG_ERR(...)
#define DBG_USBCOR_ERR(...)
#define DBG_CRYPTO_ERR(...)
#define DBG_ADC_ERR(...)
#define DBG_DAC_ERR(...)
#define MSG_MBOX_ERR(...)
#define MSG_TIMER_ERR(...)
#define DBG_BOOT_WARN(...)
#define DBG_GDMA_WARN(...)
#define DBG_GPIO_WARN(...)
#define DBG_TIMER_WARN(...)
#define DBG_I2C_WARN(...)
#define DBG_I2S_WARN(...)
#define DBG_MII_WARN(...)
#define DBG_NFC_WARN(...)
#define DBG_PCM_WARN(...)
#define DBG_PWM_WARN(...)
#define DBG_SSI_WARN(...)
#define DBG_SDIO_WARN(...)
#define DBG_SPIF_WARN(...)
#define DBG_SDR_WARN(...)
#define DBG_UART_WARN(...)
#define DBG_USBOTG_WARN(...)
#define DBG_USBCOR_WARN(...)
#define DBG_CRYPTO_WARN(...)
#define DBG_ADC_WARN(...)
#define DBG_DAC_WARN(...)
#define MSG_MBOX_WARN(...)
#define MSG_TIMER_WARN(...)
#define DBG_BOOT_INFO(...)
#define DBG_GDMA_INFO(...)
#define DBG_GPIO_INFO(...)
#define DBG_TIMER_INFO(...)
#define DBG_I2C_INFO(...)
#define DBG_I2S_INFO(...)
#define DBG_MII_INFO(...)
#define DBG_NFC_INFO(...)
#define DBG_PCM_INFO(...)
#define DBG_PWM_INFO(...)
#define DBG_SSI_INFO(...)
#define DBG_SDIO_INFO(...)
#define DBG_SPIF_INFO(...)
#define DBG_SDR_INFO(...)
#define DBG_UART_INFO(...)
#define DBG_USBOTG_INFO(...)
#define DBG_USBCOR_INFO(...)
#define DBG_CRYPTO_INFO(...)
#define DBG_ADC_INFO(...)
#define DBG_DAC_INFO(...)
#define MSG_MBOX_INFO(...)
#define MSG_TIMER_INFO(...)
#define DBG_ASSERT(x)
#endif
#define ANSI_COLOR_GREEN "\x1b[32m"
#define ANSI_COLOR_CYAN "\x1b[36m"
#define ANSI_COLOR_YELLOW "\x1b[33m"
#define ANSI_COLOR_MAGENTA "\x1b[35m"
#define ANSI_COLOR_RED "\x1b[31m"
#define ANSI_COLOR_BLUE "\x1b[34m"
#define ANSI_COLOR_RESET "\x1b[0m"
#define IDENT_ONE_SPACE " "
#define IDENT_TWO_SPACE " "
#define IDENT_FOUR_SPACE " "
#define IDENT_SIX_SPACE " "
#define IDENT_EIGHT_SPACE " "
#ifdef CONFIG_DEBUG_LOG
enum _DBG_CFG_TYPE_ {
DBG_CFG_ERR=0,
DBG_CFG_WARN=1,
DBG_CFG_INFO=2
};
typedef uint32_t DBG_CFG_TYPE;
typedef struct _DBG_CFG_CMD_ {
u8 cmd_name[16];
u32 cmd_type;
} DBG_CFG_CMD, *PDBG_CFG_CMD;
#endif
enum _CONSOLE_OP_STAGE_ {
ROM_STAGE = 0,
RAM_STAGE = 1
};
typedef uint32_t CONSOLE_OP_STAGE;
#endif //_DIAG_H_

86
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/hal_pinmux.h Normal file
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@ -0,0 +1,86 @@
/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
#ifndef _HAL_PINMUX_
#define _HAL_PINMUX_
//Function Index
#define UART0 0
#define UART1 1
#define UART2 2
#define SPI0 8
#define SPI1 9
#define SPI2 10
#define SPI0_MCS 15
#define I2C0 16
#define I2C1 17
#define I2C2 18
#define I2C3 19
#define I2S0 24
#define I2S1 25
#define PCM0 28
#define PCM1 29
#define ADC0 32
#define DAC0 36
#define DAC1 37
#define SDIOD 64
#define SDIOH 65
#define USBOTG 66
#define MII 88
#define WL_LED 96
#define WL_ANT0 104
#define WL_ANT1 105
#define WL_BTCOEX 108
#define WL_BTCMD 109
#define NFC 112
#define PWM0 160
#define PWM1 161
#define PWM2 162
#define PWM3 163
#define ETE0 164
#define ETE1 165
#define ETE2 166
#define ETE3 167
#define EGTIM 168
#define SPI_FLASH 196
#define SDR 200
#define JTAG 216
#define TRACE 217
#define LOG_UART 220
#define LOG_UART_IR 221
#define SIC 224
#define EEPROM 225
#define DEBUG 226
//Location Index(Pin Mux Selection)
#define S0 0
#define S1 1
#define S2 2
#define S3 3
_LONG_CALL_ u8
HalPinCtrlRtl8195A(
IN u32 Function,
IN u32 PinLocation,
IN BOOL Operation);
u8 GpioFunctionChk(
IN u32 chip_pin,
IN u8 Operation);
u8
FunctionChk(
IN u32 Function,
IN u32 PinLocation
);
#endif //_HAL_PINMUX_

106
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/hal_platform.h Normal file
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@ -0,0 +1,106 @@
/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
#ifndef _HAL_PLATFORM_
#define _HAL_PLATFORM_
#define ROMVERSION 0x03
#define ROMINFORMATION (ROMVERSION)
#define SYSTEM_CLK PLATFORM_CLOCK
#define SDR_SDRAM_BASE 0x30000000
#define SYSTEM_CTRL_BASE 0x40000000
#define PERI_ON_BASE 0x40000000
#define VENDOR_REG_BASE 0x40002800
#define SPI_FLASH_BASE 0x98000000
#define SDR_CTRL_BASE 0x40005000
#define PERIPHERAL_IRQ_STATUS 0x04
#define PERIPHERAL_IRQ_MODE 0x08
#define PERIPHERAL_IRQ_EN 0x0C
#define LP_PERI_EXT_IRQ_STATUS 0x24
#define LP_PERI_EXT_IRQ_MODE 0x28
#define LP_PERI_EXT_IRQ_EN 0x2C
#define PERIPHERAL_IRQ_ALL_LEVEL 0
#define TIMER_CLK 32*1000
//3 Peripheral IP Base Address
#define GPIO_REG_BASE 0x40001000
#define TIMER_REG_BASE 0x40002000
#define NFC_INTERFACE_BASE 0x40002400
#define LOG_UART_REG_BASE 0x40003000
#define I2C2_REG_BASE 0x40003400
#define I2C3_REG_BASE 0x40003800
#define SPI_FLASH_CTRL_BASE 0x40006000
#define ADC_REG_BASE 0x40010000
#define DAC_REG_BASE 0x40011000
#define UART0_REG_BASE 0x40040000
#define UART1_REG_BASE 0x40040400
#define UART2_REG_BASE 0x40040800
#define SPI0_REG_BASE 0x40042000
#define SPI1_REG_BASE 0x40042400
#define SPI2_REG_BASE 0x40042800
#define I2C0_REG_BASE 0x40044000
#define I2C1_REG_BASE 0x40044400
#define SDIO_DEVICE_REG_BASE 0x40050000
#define MII_REG_BASE 0x40050000
#define SDIO_HOST_REG_BASE 0x40058000
#define GDMA0_REG_BASE 0x40060000
#define GDMA1_REG_BASE 0x40061000
#define I2S0_REG_BASE 0x40062000
#define I2S1_REG_BASE 0x40063000
#define PCM0_REG_BASE 0x40064000
#define PCM1_REG_BASE 0x40065000
#define CRYPTO_REG_BASE 0x40070000
#define WIFI_REG_BASE 0x40080000
#define USB_OTG_REG_BASE 0x400C0000
#define GDMA1_REG_OFF 0x1000
#define I2S1_REG_OFF 0x1000
#define PCM1_REG_OFF 0x1000
#define SSI_REG_OFF 0x400
#define RUART_REG_OFF 0x400
#define CPU_CLK_TYPE_NO 6
enum _BOOT_TYPE_ {
BOOT_FROM_FLASH = 0,
BOOT_FROM_SDIO = 1,
BOOT_FROM_USB = 2,
BOOT_FROM_RSVD = 3,
};
enum _EFUSE_CPU_CLK_ {
#if 1
CLK_200M = 0,
CLK_100M = 1,
CLK_50M = 2,
CLK_25M = 3,
CLK_12_5M = 4,
CLK_4M = 5,
#else
CLK_25M = 0,
CLK_200M = 1,
CLK_100M = 2,
CLK_50M = 3,
CLK_12_5M = 4,
CLK_4M = 5,
#endif
};
#endif //_HAL_PLATFORM_

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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
/*
* Automatically generated by make menuconfig: don't edit
*/
#define AUTOCONF_INCLUDED
/*
* Target Platform Selection
*/
#define CONFIG_WITHOUT_MONITOR 1
#undef CONFIG_RTL8195A
#define CONFIG_RTL8195A 1
#undef CONFIG_FPGA
#undef CONFIG_RTL_SIM
#undef CONFIG_POST_SIM
/*
* < Mass Production Option
*/
#undef CONFIG_MP
#undef CONFIG_CP
#undef CONFIG_FT
#define RTL8195A 1
#define CONFIG_CPU_CLK 1
#define CONFIG_CPU_166_6MHZ 1
#undef CONFIG_CPU_83_3MHZ
#undef CONFIG_CPU_41_6MHZ
#undef CONFIG_CPU_20_8MHZ
#undef CONFIG_CPU_10_4MHZ
#undef CONFIG_CPU_4MHZ
#undef CONFIG_FPGA_CLK
#define PLATFORM_CLOCK (166666666)
#define CPU_CLOCK_SEL_VALUE (0)
#define CONFIG_SDR_CLK 1
#define CONFIG_SDR_100MHZ 1
#undef CONFIG_SDR_50MHZ
#undef CONFIG_SDR_25MHZ
#undef CONFIG_SDR_12_5MHZ
#define SDR_CLOCK_SEL_VALUE (0)
#define CONFIG_BOOT_PROCEDURE 1
#define CONFIG_IMAGE_PAGE_LOAD 1
#undef CONFIG_IMAGE_AUTO_LOAD
//#undef CONFIG_IMAGE_PAGE_LOAD
//#define CONFIG_IMAGE_AUTO_LOAD 1
#define CONFIG_BOOT_TO_UPGRADE_IMG2 1
#undef CONFIG_PERI_UPDATE_IMG
#define CONFIG_BOOT_FROM_JTAG 1
#undef CONFIG_ALIGNMENT_EXCEPTION_ENABLE
#define CONFIG_KERNEL 1
#define PLATFORM_FREERTOS 1
#undef PLATFORM_UCOSII
#undef PLATFORM_ECOS
#undef CONFIG_TASK_SCHEDUL_DIS
#define TASK_SCHEDULER_DISABLED (0)
#define CONFIG_NORMALL_MODE 1
#undef CONFIG_MEMORY_VERIFY_MODE
#define CONFIG_TIMER_EN 1
#define CONFIG_TIMER_NORMAL 1
#undef CONFIG_TIMER_TEST
#define CONFIG_TIMER_MODULE 1
#define CONFIG_WDG 1
#undef CONFIG_WDG_NON
#define CONFIG_WDG_NORMAL 1
#define CONFIG_GDMA_EN 0
#define CONFIG_GDMA_NORMAL 1
#undef CONFIG_GDMA_TEST
#define CONFIG_GDMA_MODULE 1
#define CONFIG_WIFI_EN 1
#define CONFIG_WIFI_NORMAL 1
#undef CONFIG_WIFI_TEST
#define CONFIG_WIFI_MODULE 1
#define CONFIG_GPIO_EN 1
#define CONFIG_GPIO_NORMAL 1
#undef CONFIG_GPIO_TEST
#define CONFIG_GPIO_MODULE 1
#if defined(CONFIG_INIC) || (CONFIG_SDIOD)
#define CONFIG_SDIO_DEVICE_EN 1
#define CONFIG_SDIO_DEVICE_NORMAL 1
#undef CONFIG_SDIO_DEVICE_TEST
#define CONFIG_SDIO_DEVICE_MODULE 1
#else
#undef CONFIG_SDIO_DEVICE_EN
#endif
#define CONFIG_SDIO_HOST_EN 1
#define CONFIG_USB_EN 1
#undef CONFIG_USB_NORMAL
#define CONFIG_USB_TEST 1
#define CONFIG_USB_MODULE 1
#define CONFIG_USB_VERIFY 1
#undef CONFIG_USB_ROM_LIB
//#define CONFIG_USB_DBGINFO_EN 1
#if defined(CONFIG_INIC) || (CONFIG_USBD)
#define DWC_DEVICE_ONLY 1
#else
#define DWC_HOST_ONLY 1
#define CONFIG_USB_HOST_ONLY 1
#endif
#define CONFIG_SPI_COM_EN 1
#define CONFIG_SPI_COM_NORMAL 1
#undef CONFIG_SPI_COM_TEST
#define CONFIG_SPI_COM_MODULE 1
#define CONFIG_UART_EN 1
#define CONFIG_UART_NORMAL 1
#undef CONFIG_UART_TEST
#define CONFIG_UART_MODULE 1
#define CONFIG_I2C_EN 1
#define CONFIG_I2C_NORMAL 1
#undef CONFIG_I2C_TEST
#define CONFIG_I2C_MODULE 1
#undef CONFIG_DEBUG_LOG_I2C_HAL
#undef CONFIG_PCM_EN
#undef CONFIG_I2S_EN
#undef CONFIG_I2S_NORMAL
#undef CONFIG_I2S_TEST
#undef CONFIG_I2S_MODULE
#undef CONFIG_DEBUG_LOG_I2S_HAL
#undef CONFIG_NFC_EN
#undef CONFIG_NFC_NORMAL
#undef CONFIG_NFC_TEST
#undef CONFIG_NFC_MODULE
#define CONFIG_SOC_PS_EN 1
#define CONFIG_SOC_PS_NORMAL 1
#undef CONFIG_SOC_PS_TEST
//#define CONFIG_SOC_PS_MODULE 1
#define CONFIG_CRYPTO_EN 1
#define CONFIG_CRYPTO_NORMAL 1
#undef CONFIG_CRYPTO_TEST
#define CONFIG_CRYPTO_MODULE 1
#define CONFIG_MII_EN 1
#define CONFIG_PWM_EN 1
#define CONFIG_PWM_NORMAL 1
#undef CONFIG_PWM_TEST
#define CONFIG_PWM_MODULE 1
#define CONFIG_EFUSE_EN 1
#define CONFIG_EFUSE_NORMAL 1
#undef CONFIG_EFUSE_TEST
#define CONFIG_EFUSE_MODULE 1
#define CONFIG_SDR_EN 1
#define CONFIG_SDR_NORMAL 1
#undef CONFIG_SDR_TEST
#define CONFIG_SDR_MODULE 1
#define CONFIG_SPIC_EN 1
#define CONFIG_SPIC_NORMAL 1
#undef CONFIG_SPIC_TEST
#define CONFIG_SPIC_MODULE 1
#define CONFIG_ADC_EN 1
#define CONFIG_DAC_EN 1
#define CONFIG_NOR_FLASH 1
#undef CONFIG_SPI_FLASH
#undef CONFIG_NAND_FLASH
#undef CONFIG_NONE_FLASH
#undef CONFIG_BTBX_EN
/*
* < Engineer Mode Config
*/
#undef CONFIG_JTAG
#undef CONFIG_COMPILE_FLASH_DOWNLOAD_CODE
#undef CONIFG_COMPILE_EXTERNAL_SRAM_CALIBRATE
#undef CONFIG_CMSIS_MATH_LIB_EN
/*
* < Application Config
*/
#define CONFIG_NETWORK 1
#define CONFIG_RTLIB_EN 1
#define CONFIG_RTLIB_NORMAL 1
#undef CONFIG_RTLIB_TEST
#define CONFIG_RTLIB_MODULE 1
/*
* < System Debug Message Config
*/
#define CONFIG_UART_LOG_HISTORY 1
#undef CONFIG_CONSOLE_NORMALL_MODE
#define CONFIG_CONSOLE_VERIFY_MODE 1
#define CONFIG_DEBUG_LOG 1
#define CONFIG_DEBUG_ERR_MSG 1
#undef CONFIG_DEBUG_WARN_MSG
#undef CONFIG_DEBUG_INFO_MSG
/*
* < SDK Option Config
*/
//#undef CONFIG_MBED_ENABLED
#ifdef CONFIG_MBED_ENABLED
#undef PLATFORM_FREERTOS
#define PLATFORM_CMSIS_RTOS 1
#endif
#undef CONFIG_APP_DEMO
/*
* < Select Chip Version
*/
#undef CONFIG_CHIP_A_CUT
#define CONFIG_CHIP_B_CUT 1
#undef CONFIG_CHIP_C_CUT
#undef CONFIG_CHIP_E_CUT
/*
* < Select toolchain
*/
#undef CONFIG_TOOLCHAIN_ASDK
#undef CONFIG_TOOLCHAIN_ARM_GCC
/*
* < Build Option
*/
#define CONFIG_LINK_ROM_LIB 1
#undef CONFIG_LINK_ROM_SYMB
#undef CONFIG_NORMAL_BUILD
#undef CONFIG_RELEASE_BUILD
#undef CONFIG_RELEASE_BUILD_LIBRARIES
#undef CONFIG_LIB_BUILD_RAM
#define CONFIG_RELEASE_BUILD_RAM_ALL 1
#undef CONFIG_IMAGE_ALL
#define CONFIG_IMAGE_SEPARATE 1

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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
u32
Rand (
VOID
);

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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
#ifndef _HAL_8195A_H_
#define _HAL_8195A_H_
#include "platform_autoconf.h"
#include "basic_types.h"
#include "section_config.h"
#include "rtl8195a_sys_on.h"
#include "rtl8195a_peri_on.h"
#include "hal_platform.h"
#include "hal_pinmux.h"
#include "hal_api.h"
#include "hal_peri_on.h"
#include "hal_misc.h"
#include "hal_irqn.h"
#include "hal_vector_table.h"
#include "hal_diag.h"
#include "hal_spi_flash.h"
#include "rtl8195a_spi_flash.h"
//#include "hal_timer.h"
#include "hal_util.h"
#include "hal_efuse.h"
#include "hal_soc_ps_monitor.h"
#include "diag.h"
//#include "hal_common.h"
//#include "hal_soc_ps_monitor.h"
// from RDC team
#ifdef CONFIG_MBED_ENABLED
// Add for Mbed -OS
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include "rtl8195a_compiler.h"
#include "rtl8195a_platform.h"
#define REG32(reg) (*(volatile uint32_t *)(reg))
#define REG16(reg) (*(volatile uint16_t *)(reg))
#define REG08(reg) (*(volatile uint8_t *)(reg))
#ifndef BIT
#define BIT(x) (1 << (x))
#endif
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))
#define ABS(x) ((x > 0) ? x : -x)
#define MAX(x,y) ((x) < (y) ? (y) : (x))
#ifndef MIN
#define MIN(x,y) ((x) > (y) ? (y) : (x))
#endif
#define __RTK_READ32(B,A) (REG32((B) + (A)))
#define __RTK_READ16(B,A) (REG16((B) + (A)))
#define __RTK_READ08(B,A) (REG08((B) + (A)))
#define __RTK_WRITE32(B,A,V) (REG32((B) + (A)) = (V))
#define __RTK_WRITE16(B,A,V) (REG32((B) + (A)) = (V))
#define __RTK_WRITE08(B,A,V) (REG32((B) + (A)) = (V))
#define __RTK_SETBIT(A,V) (REG32(A) |= V)
#define __RTK_CLRBIT(A,V) (REG32(A) &= ~V)
#define __RTK_SETMSK(A,M,V) (REG32(A) = ((REG32(A) & (~M)) | V))
#define PERI_BASE 0x40000000
#define __BUILD_MACRO(name,ctrl) \
static inline uint32_t \
__##name##_READ32(uint32_t addr) \
{ \
return __RTK_READ32(ctrl##_BASE,addr); \
} \
static inline uint16_t \
__##name##_READ16(uint32_t addr) \
{ \
return __RTK_READ16(ctrl##_BASE,addr); \
} \
static inline uint8_t \
__##name##_READ08(uint32_t addr) \
{ \
return __RTK_READ08(ctrl##_BASE,addr); \
} \
static inline void \
__##name##_WRITE32(uint32_t addr, uint32_t val) \
{ \
__RTK_WRITE32(ctrl##_BASE,addr,val); \
} \
static inline void \
__##name##_WRITE16(uint32_t addr, uint16_t val) \
{ \
__RTK_WRITE16(ctrl##_BASE,addr,val); \
} \
static inline void \
__##name##_WRITE08(uint32_t addr, uint8_t val) \
{ \
__RTK_WRITE08(ctrl##_BASE,addr,val); \
} \
static inline void \
__##name##_SETBIT(uint32_t addr, uint32_t val) \
{ \
__RTK_SETBIT(ctrl##_BASE+addr,val); \
} \
static inline void \
__##name##_CLRBIT(uint32_t addr, uint32_t val) \
{ \
__RTK_CLRBIT(ctrl##_BASE+addr,val); \
} \
static inline void \
__##name##_SETMSK(uint32_t addr, uint32_t msk, uint32_t val) \
{ \
__RTK_SETMSK(ctrl##_BASE+addr,msk,val); \
} \
//__BUILD_MACRO(RTK_CTRL, CTRL)
//__BUILD_MACRO(RTK_PERI, PERI)
//__BUILD_MACRO(RTK_VENDOR, VENDOR)
//__BUILD_MACRO(RTK_SDRC, SDRC)
__BUILD_MACRO(RTK_CTRL, SYSTEM_CTRL)
__BUILD_MACRO(RTK_PERI, PERI)
__BUILD_MACRO(RTK_SDRC, SDR_CTRL)
__BUILD_MACRO(RTK_VENDOR, VENDOR_REG)
#define __BUILD_FCTRL_MACRO(name,ctrl) \
static inline void \
__##name##_Enable(void) \
{ \
__RTK_PERI_SETBIT(ctrl, BIT_FCTRL_##name); \
} \
static inline void \
__##name##_Disable(void) \
{ \
__RTK_READ32(name##_BASE, 0); \
__RTK_PERI_CLRBIT(ctrl, BIT_FCTRL_##name); \
}
#include "rtl8195a_trap.h"
#include "rtl8195a_clk.h"
#include "rtl8195a_misc.h"
#include "rtl8195a_sdio.h"
//#include "rtl8195a_luart.h"
#endif
/* ----------------------------------------------------------------------------
-- Cortex M3 Core Configuration
---------------------------------------------------------------------------- */
/*!
* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
* @{
*/
#define __CM3_REV 0x0200 /**< Core revision r0p0 */
#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig 1 /**< Vendor specific implementation of SysTickConfig is defined */
#include "core_cm3.h"
#ifdef CONFIG_TIMER_EN
#include "hal_timer.h"
#endif
#ifdef CONFIG_GDMA_EN
#include "hal_gdma.h"
#include "rtl8195a_gdma.h"
#endif
#ifdef CONFIG_GPIO_EN
#include "hal_gpio.h"
#include "rtl8195a_gpio.h"
#endif
#ifdef CONFIG_SPI_COM_EN
#include "hal_ssi.h"
#include "rtl8195a_ssi.h"
#endif
#ifdef CONFIG_UART_EN
#include "hal_uart.h"
#include "rtl8195a_uart.h"
#endif
#ifdef CONFIG_I2C_EN
#include "hal_i2c.h"
#include "rtl8195a_i2c.h"
#endif
//#ifdef CONFIG_PCM_EN
//#include "hal_pcm.h"
//#include "rtl8195a_pcm.h"
//#endif
#ifdef CONFIG_PWM_EN
#include "hal_pwm.h"
#include "rtl8195a_pwm.h"
#endif
#ifdef CONFIG_I2S_EN
#include "hal_i2s.h"
#include "rtl8195a_i2s.h"
#endif
#ifdef CONFIG_DAC_EN
#include "hal_dac.h"
#include "rtl8195a_dac.h"
#endif
#ifdef CONFIG_ADC_EN
#include "hal_adc.h"
#include "rtl8195a_adc.h"
#endif
#ifdef CONFIG_SDR_EN
#endif
#ifdef CONFIG_SPIC_EN
#endif
#ifdef CONFIG_SDIO_DEVICE_EN
//#include "hal_sdio.h"
#endif
#ifdef CONFIG_NFC_EN
//#include "hal_nfc.h"
//#include "rtl8195a_nfc.h"
#endif
#ifdef CONFIG_WDG
#include "rtl8195a_wdt.h"
#endif
#ifdef CONFIG_USB_EN
//#include "hal_usb.h"
//#include "rtl8195a_usb.h"
#endif
#include "hal_log_uart.h"
#ifdef CONFIG_MII_EN
//#include "hal_mii.h"
//#include "rtl8195a_mii.h"
#endif
// firmware information, located at the header of Image2
#define FW_VERSION (0x0100)
#define FW_SUBVERSION (0x0001)
#define FW_CHIP_ID (0x8195)
#define FW_CHIP_VER (0x01)
#define FW_BUS_TYPE (0x01) // the iNIC firmware type: USB/SDIO
#define FW_INFO_RSV1 (0x00) // the firmware information reserved
#define FW_INFO_RSV2 (0x00) // the firmware information reserved
#define FW_INFO_RSV3 (0x00) // the firmware information reserved
#define FW_INFO_RSV4 (0x00) // the firmware information reserved
#define FLASH_RESERVED_DATA_BASE 0x8000 // reserve 32K for Image1
#define FLASH_SYSTEM_DATA_ADDR 0x9000 // reserve 32K+4K for Image1 + Reserved data
// Flash Map for Calibration data
#define FLASH_CAL_DATA_BASE 0xA000
#define FLASH_CAL_DATA_ADDR(_offset) (FLASH_CAL_DATA_BASE + _offset)
#define FLASH_CAL_DATA_SIZE 0x1000
#define FLASH_SECTOR_SIZE 0x1000
// SPIC Calibration Data
#define FLASH_SPIC_PARA_OFFSET 0x80
#define FLASH_SPIC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SPIC_PARA_OFFSET)
// SDRC Calibration Data
#define FLASH_SDRC_PARA_OFFSET 0x180
#define FLASH_SDRC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SDRC_PARA_OFFSET)
// ADC Calibration Data
#define FLASH_ADC_PARA_OFFSET 0x200
#define FLASH_ADC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_ADC_PARA_OFFSET)
#endif //_HAL_8195A_H_

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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
#ifndef _RTL8195A_ADC_H_
#define _RTL8195A_ADC_H_
//================ Register Bit Field ==========================
//2 REG_ADC_FIFO_READ
#define BIT_SHIFT_ADC_FIFO_RO 0
#define BIT_MASK_ADC_FIFO_RO 0xffffffffL
#define BIT_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO)
#define BIT_CTRL_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO)
#define BIT_GET_ADC_FIFO_RO(x) (((x) >> BIT_SHIFT_ADC_FIFO_RO) & BIT_MASK_ADC_FIFO_RO)
//2 REG_ADC_CONTROL
#define BIT_SHIFT_ADC_DBG_SEL 24
#define BIT_MASK_ADC_DBG_SEL 0x7
#define BIT_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL)
#define BIT_CTRL_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL)
#define BIT_GET_ADC_DBG_SEL(x) (((x) >> BIT_SHIFT_ADC_DBG_SEL) & BIT_MASK_ADC_DBG_SEL)
#define BIT_SHIFT_ADC_THRESHOLD 16
#define BIT_MASK_ADC_THRESHOLD 0x3f
#define BIT_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD)
#define BIT_CTRL_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD)
#define BIT_GET_ADC_THRESHOLD(x) (((x) >> BIT_SHIFT_ADC_THRESHOLD) & BIT_MASK_ADC_THRESHOLD)
#define BIT_SHIFT_ADC_BURST_SIZE 8
#define BIT_MASK_ADC_BURST_SIZE 0x1f
#define BIT_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE)
#define BIT_CTRL_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE)
#define BIT_GET_ADC_BURST_SIZE(x) (((x) >> BIT_SHIFT_ADC_BURST_SIZE) & BIT_MASK_ADC_BURST_SIZE)
#define BIT_ADC_ENDIAN BIT(3)
#define BIT_SHIFT_ADC_ENDIAN 3
#define BIT_MASK_ADC_ENDIAN 0x1
#define BIT_CTRL_ADC_ENDIAN(x) (((x) & BIT_MASK_ADC_ENDIAN) << BIT_SHIFT_ADC_ENDIAN)
#define BIT_ADC_OVERWRITE BIT(2)
#define BIT_SHIFT_ADC_OVERWRITE 2
#define BIT_MASK_ADC_OVERWRITE 0x1
#define BIT_CTRL_ADC_OVERWRITE(x) (((x) & BIT_MASK_ADC_OVERWRITE) << BIT_SHIFT_ADC_OVERWRITE)
#define BIT_ADC_ONESHOT BIT(1)
#define BIT_SHIFT_ADC_ONESHOT 1
#define BIT_MASK_ADC_ONESHOT 0x1
#define BIT_CTRL_ADC_ONESHOT(x) (((x) & BIT_MASK_ADC_ONESHOT) << BIT_SHIFT_ADC_ONESHOT)
#define BIT_ADC_COMP_ONLY BIT(0)
#define BIT_SHIFT_ADC_COMP_ONLY 0
#define BIT_MASK_ADC_COMP_ONLY 0x1
#define BIT_CTRL_ADC_COMP_ONLY(x) (((x) & BIT_MASK_ADC_COMP_ONLY) << BIT_SHIFT_ADC_COMP_ONLY)
//2 REG_ADC_INTR_EN
#define BIT_ADC_AWAKE_CPU_EN BIT(7)
#define BIT_SHIFT_ADC_AWAKE_CPU_EN 7
#define BIT_MASK_ADC_AWAKE_CPU_EN 0x1
#define BIT_CTRL_ADC_AWAKE_CPU_EN(x) (((x) & BIT_MASK_ADC_AWAKE_CPU_EN) << BIT_SHIFT_ADC_AWAKE_CPU_EN)
#define BIT_ADC_FIFO_RD_ERROR_EN BIT(6)
#define BIT_SHIFT_ADC_FIFO_RD_ERROR_EN 6
#define BIT_MASK_ADC_FIFO_RD_ERROR_EN 0x1
#define BIT_CTRL_ADC_FIFO_RD_ERROR_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_EN) << BIT_SHIFT_ADC_FIFO_RD_ERROR_EN)
#define BIT_ADC_FIFO_RD_REQ_EN BIT(5)
#define BIT_SHIFT_ADC_FIFO_RD_REQ_EN 5
#define BIT_MASK_ADC_FIFO_RD_REQ_EN 0x1
#define BIT_CTRL_ADC_FIFO_RD_REQ_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_EN) << BIT_SHIFT_ADC_FIFO_RD_REQ_EN)
#define BIT_ADC_FIFO_FULL_EN BIT(4)
#define BIT_SHIFT_ADC_FIFO_FULL_EN 4
#define BIT_MASK_ADC_FIFO_FULL_EN 0x1
#define BIT_CTRL_ADC_FIFO_FULL_EN(x) (((x) & BIT_MASK_ADC_FIFO_FULL_EN) << BIT_SHIFT_ADC_FIFO_FULL_EN)
#define BIT_ADC_COMP_3_EN BIT(3)
#define BIT_SHIFT_ADC_COMP_3_EN 3
#define BIT_MASK_ADC_COMP_3_EN 0x1
#define BIT_CTRL_ADC_COMP_3_EN(x) (((x) & BIT_MASK_ADC_COMP_3_EN) << BIT_SHIFT_ADC_COMP_3_EN)
#define BIT_ADC_COMP_2_EN BIT(2)
#define BIT_SHIFT_ADC_COMP_2_EN 2
#define BIT_MASK_ADC_COMP_2_EN 0x1
#define BIT_CTRL_ADC_COMP_2_EN(x) (((x) & BIT_MASK_ADC_COMP_2_EN) << BIT_SHIFT_ADC_COMP_2_EN)
#define BIT_ADC_COMP_1_EN BIT(1)
#define BIT_SHIFT_ADC_COMP_1_EN 1
#define BIT_MASK_ADC_COMP_1_EN 0x1
#define BIT_CTRL_ADC_COMP_1_EN(x) (((x) & BIT_MASK_ADC_COMP_1_EN) << BIT_SHIFT_ADC_COMP_1_EN)
#define BIT_ADC_COMP_0_EN BIT(0)
#define BIT_SHIFT_ADC_COMP_0_EN 0
#define BIT_MASK_ADC_COMP_0_EN 0x1
#define BIT_CTRL_ADC_COMP_0_EN(x) (((x) & BIT_MASK_ADC_COMP_0_EN) << BIT_SHIFT_ADC_COMP_0_EN)
//2 REG_ADC_INTR_STS
#define BIT_ADC_FIFO_THRESHOLD BIT(7)
#define BIT_SHIFT_ADC_FIFO_THRESHOLD 7
#define BIT_MASK_ADC_FIFO_THRESHOLD 0x1
#define BIT_CTRL_ADC_FIFO_THRESHOLD(x) (((x) & BIT_MASK_ADC_FIFO_THRESHOLD) << BIT_SHIFT_ADC_FIFO_THRESHOLD)
#define BIT_ADC_FIFO_RD_ERROR_ST BIT(6)
#define BIT_SHIFT_ADC_FIFO_RD_ERROR_ST 6
#define BIT_MASK_ADC_FIFO_RD_ERROR_ST 0x1
#define BIT_CTRL_ADC_FIFO_RD_ERROR_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_ST) << BIT_SHIFT_ADC_FIFO_RD_ERROR_ST)
#define BIT_ADC_FIFO_RD_REQ_ST BIT(5)
#define BIT_SHIFT_ADC_FIFO_RD_REQ_ST 5
#define BIT_MASK_ADC_FIFO_RD_REQ_ST 0x1
#define BIT_CTRL_ADC_FIFO_RD_REQ_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_ST) << BIT_SHIFT_ADC_FIFO_RD_REQ_ST)
#define BIT_ADC_FIFO_FULL_ST BIT(4)
#define BIT_SHIFT_ADC_FIFO_FULL_ST 4
#define BIT_MASK_ADC_FIFO_FULL_ST 0x1
#define BIT_CTRL_ADC_FIFO_FULL_ST(x) (((x) & BIT_MASK_ADC_FIFO_FULL_ST) << BIT_SHIFT_ADC_FIFO_FULL_ST)
#define BIT_ADC_COMP_3_ST BIT(3)
#define BIT_SHIFT_ADC_COMP_3_ST 3
#define BIT_MASK_ADC_COMP_3_ST 0x1
#define BIT_CTRL_ADC_COMP_3_ST(x) (((x) & BIT_MASK_ADC_COMP_3_ST) << BIT_SHIFT_ADC_COMP_3_ST)
#define BIT_ADC_COMP_2_ST BIT(2)
#define BIT_SHIFT_ADC_COMP_2_ST 2
#define BIT_MASK_ADC_COMP_2_ST 0x1
#define BIT_CTRL_ADC_COMP_2_ST(x) (((x) & BIT_MASK_ADC_COMP_2_ST) << BIT_SHIFT_ADC_COMP_2_ST)
#define BIT_ADC_COMP_1_ST BIT(1)
#define BIT_SHIFT_ADC_COMP_1_ST 1
#define BIT_MASK_ADC_COMP_1_ST 0x1
#define BIT_CTRL_ADC_COMP_1_ST(x) (((x) & BIT_MASK_ADC_COMP_1_ST) << BIT_SHIFT_ADC_COMP_1_ST)
#define BIT_ADC_COMP_0_ST BIT(0)
#define BIT_SHIFT_ADC_COMP_0_ST 0
#define BIT_MASK_ADC_COMP_0_ST 0x1
#define BIT_CTRL_ADC_COMP_0_ST(x) (((x) & BIT_MASK_ADC_COMP_0_ST) << BIT_SHIFT_ADC_COMP_0_ST)
//2 REG_ADC_COMP_VALUE_L
#define BIT_SHIFT_ADC_COMP_TH_1 16
#define BIT_MASK_ADC_COMP_TH_1 0xffff
#define BIT_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1)
#define BIT_CTRL_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1)
#define BIT_GET_ADC_COMP_TH_1(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_1) & BIT_MASK_ADC_COMP_TH_1)
#define BIT_SHIFT_ADC_COMP_TH_0 0
#define BIT_MASK_ADC_COMP_TH_0 0xffff
#define BIT_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0)
#define BIT_CTRL_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0)
#define BIT_GET_ADC_COMP_TH_0(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_0) & BIT_MASK_ADC_COMP_TH_0)
//2 REG_ADC_COMP_VALUE_H
#define BIT_SHIFT_ADC_COMP_TH_3 16
#define BIT_MASK_ADC_COMP_TH_3 0xffff
#define BIT_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3)
#define BIT_CTRL_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3)
#define BIT_GET_ADC_COMP_TH_3(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_3) & BIT_MASK_ADC_COMP_TH_3)
#define BIT_SHIFT_ADC_COMP_TH_2 0
#define BIT_MASK_ADC_COMP_TH_2 0xffff
#define BIT_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2)
#define BIT_CTRL_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2)
#define BIT_GET_ADC_COMP_TH_2(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_2) & BIT_MASK_ADC_COMP_TH_2)
//2 REG_ADC_COMP_SET
#define BIT_SHIFT_ADC_GREATER_THAN 0
#define BIT_MASK_ADC_GREATER_THAN 0xf
#define BIT_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN)
#define BIT_CTRL_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN)
#define BIT_GET_ADC_GREATER_THAN(x) (((x) >> BIT_SHIFT_ADC_GREATER_THAN) & BIT_MASK_ADC_GREATER_THAN)
//2 REG_ADC_POWER
#define BIT_SHIFT_ADC_PWR_CUT_CNTR 16
#define BIT_MASK_ADC_PWR_CUT_CNTR 0xff
#define BIT_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR)
#define BIT_CTRL_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR)
#define BIT_GET_ADC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_ADC_PWR_CUT_CNTR) & BIT_MASK_ADC_PWR_CUT_CNTR)
#define BIT_ADC_FIFO_ON_ST BIT(11)
#define BIT_SHIFT_ADC_FIFO_ON_ST 11
#define BIT_MASK_ADC_FIFO_ON_ST 0x1
#define BIT_CTRL_ADC_FIFO_ON_ST(x) (((x) & BIT_MASK_ADC_FIFO_ON_ST) << BIT_SHIFT_ADC_FIFO_ON_ST)
#define BIT_ADC_ISO_ON_ST BIT(10)
#define BIT_SHIFT_ADC_ISO_ON_ST 10
#define BIT_MASK_ADC_ISO_ON_ST 0x1
#define BIT_CTRL_ADC_ISO_ON_ST(x) (((x) & BIT_MASK_ADC_ISO_ON_ST) << BIT_SHIFT_ADC_ISO_ON_ST)
#define BIT_ADC_PWR33_ON_ST BIT(9)
#define BIT_SHIFT_ADC_PWR33_ON_ST 9
#define BIT_MASK_ADC_PWR33_ON_ST 0x1
#define BIT_CTRL_ADC_PWR33_ON_ST(x) (((x) & BIT_MASK_ADC_PWR33_ON_ST) << BIT_SHIFT_ADC_PWR33_ON_ST)
#define BIT_ADC_PWR12_ON_ST BIT(8)
#define BIT_SHIFT_ADC_PWR12_ON_ST 8
#define BIT_MASK_ADC_PWR12_ON_ST 0x1
#define BIT_CTRL_ADC_PWR12_ON_ST(x) (((x) & BIT_MASK_ADC_PWR12_ON_ST) << BIT_SHIFT_ADC_PWR12_ON_ST)
#define BIT_ADC_ISO_MANUAL BIT(3)
#define BIT_SHIFT_ADC_ISO_MANUAL 3
#define BIT_MASK_ADC_ISO_MANUAL 0x1
#define BIT_CTRL_ADC_ISO_MANUAL(x) (((x) & BIT_MASK_ADC_ISO_MANUAL) << BIT_SHIFT_ADC_ISO_MANUAL)
#define BIT_ADC_PWR33_MANUAL BIT(2)
#define BIT_SHIFT_ADC_PWR33_MANUAL 2
#define BIT_MASK_ADC_PWR33_MANUAL 0x1
#define BIT_CTRL_ADC_PWR33_MANUAL(x) (((x) & BIT_MASK_ADC_PWR33_MANUAL) << BIT_SHIFT_ADC_PWR33_MANUAL)
#define BIT_ADC_PWR12_MANUAL BIT(1)
#define BIT_SHIFT_ADC_PWR12_MANUAL 1
#define BIT_MASK_ADC_PWR12_MANUAL 0x1
#define BIT_CTRL_ADC_PWR12_MANUAL(x) (((x) & BIT_MASK_ADC_PWR12_MANUAL) << BIT_SHIFT_ADC_PWR12_MANUAL)
#define BIT_ADC_PWR_AUTO BIT(0)
#define BIT_SHIFT_ADC_PWR_AUTO 0
#define BIT_MASK_ADC_PWR_AUTO 0x1
#define BIT_CTRL_ADC_PWR_AUTO(x) (((x) & BIT_MASK_ADC_PWR_AUTO) << BIT_SHIFT_ADC_PWR_AUTO)
//2 REG_ADC_ANAPAR_AD0
#define BIT_SHIFT_ADC_ANAPAR_AD0 2
#define BIT_MASK_ADC_ANAPAR_AD0 0x3fffffff
#define BIT_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0)
#define BIT_CTRL_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0)
#define BIT_GET_ADC_ANAPAR_AD0(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD0) & BIT_MASK_ADC_ANAPAR_AD0)
#define BIT_ADC_AUDIO_EN BIT(1)
#define BIT_SHIFT_ADC_AUDIO_EN 1
#define BIT_MASK_ADC_AUDIO_EN 0x1
#define BIT_CTRL_ADC_AUDIO_EN(x) (((x) & BIT_MASK_ADC_AUDIO_EN) << BIT_SHIFT_ADC_AUDIO_EN)
#define BIT_ADC_EN_MANUAL BIT(0)
#define BIT_SHIFT_ADC_EN_MANUAL 0
#define BIT_MASK_ADC_EN_MANUAL 0x1
#define BIT_CTRL_ADC_EN_MANUAL(x) (((x) & BIT_MASK_ADC_EN_MANUAL) << BIT_SHIFT_ADC_EN_MANUAL)
//2 REG_ADC_ANAPAR_AD1
#define BIT_SHIFT_ADC_ANAPAR_AD1 0
#define BIT_MASK_ADC_ANAPAR_AD1 0xffffffffL
#define BIT_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1)
#define BIT_CTRL_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1)
#define BIT_GET_ADC_ANAPAR_AD1(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD1) & BIT_MASK_ADC_ANAPAR_AD1)
//2 REG_ADC_ANAPAR_AD2
#define BIT_SHIFT_ADC_ANAPAR_AD2 0
#define BIT_MASK_ADC_ANAPAR_AD2 0xffffffffL
#define BIT_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2)
#define BIT_CTRL_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2)
#define BIT_GET_ADC_ANAPAR_AD2(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD2) & BIT_MASK_ADC_ANAPAR_AD2)
//2 REG_ADC_ANAPAR_AD3
#define BIT_SHIFT_ADC_ANAPAR_AD3 0
#define BIT_MASK_ADC_ANAPAR_AD3 0xffffffffL
#define BIT_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3)
#define BIT_CTRL_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3)
#define BIT_GET_ADC_ANAPAR_AD3(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD3) & BIT_MASK_ADC_ANAPAR_AD3)
//2 REG_ADC_ANAPAR_AD4
#define BIT_SHIFT_ADC_ANAPAR_AD4 0
#define BIT_MASK_ADC_ANAPAR_AD4 0xffffffffL
#define BIT_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4)
#define BIT_CTRL_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4)
#define BIT_GET_ADC_ANAPAR_AD4(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD4) & BIT_MASK_ADC_ANAPAR_AD4)
//2 REG_ADC_ANAPAR_AD5
#define BIT_SHIFT_ADC_ANAPAR_AD5 0
#define BIT_MASK_ADC_ANAPAR_AD5 0xffffffffL
#define BIT_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5)
#define BIT_CTRL_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5)
#define BIT_GET_ADC_ANAPAR_AD5(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD5) & BIT_MASK_ADC_ANAPAR_AD5)
//2 REG_ADC_CALI_DATA
#define BIT_SHIFT_ADC_CALI_DATA_6 16
#define BIT_MASK_ADC_CALI_DATA_6 0xffff
#define BIT_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6)
#define BIT_CTRL_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6)
#define BIT_GET_ADC_CALI_DATA_6(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_6) & BIT_MASK_ADC_CALI_DATA_6)
#define BIT_SHIFT_ADC_CALI_DATA_0 0
#define BIT_MASK_ADC_CALI_DATA_0 0xffff
#define BIT_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0)
#define BIT_CTRL_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0)
#define BIT_GET_ADC_CALI_DATA_0(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_0) & BIT_MASK_ADC_CALI_DATA_0)
//================ Register Reg Field =========================
#define REG_ADC_FIFO_READ 0x0000
#define REG_ADC_CONTROL 0x0004
#define REG_ADC_INTR_EN 0x0008
#define REG_ADC_INTR_STS 0x000C
#define REG_ADC_COMP_VALUE_L 0x0010
#define REG_ADC_COMP_VALUE_H 0x0014
#define REG_ADC_COMP_SET 0x0018
#define REG_ADC_POWER 0x001C
#define REG_ADC_ANAPAR_AD0 0x0020
#define REG_ADC_ANAPAR_AD1 0x0024
#define REG_ADC_ANAPAR_AD2 0x0028
#define REG_ADC_ANAPAR_AD3 0x002C
#define REG_ADC_ANAPAR_AD4 0x0030
#define REG_ADC_ANAPAR_AD5 0x0034
#define REG_ADC_CALI_DATA 0x0038
//================ ADC HAL related enumeration ==================
//================ ADC Function Prototypes =====================
#define HAL_ADC_WRITE32(addr, value) HAL_WRITE32(ADC_REG_BASE,addr,value)
#define HAL_ADC_READ32(addr) HAL_READ32(ADC_REG_BASE,addr)
RTK_STATUS HalADCInit8195a(IN VOID *Data);
RTK_STATUS HalADCDeInit8195a(IN VOID *Data);
RTK_STATUS HalADCEnableRtl8195a(IN VOID *Data);
RTK_STATUS HalADCIntrCtrl8195a(IN VOID *Data);
u32 HalADCReceiveRtl8195a(IN VOID *Data);
u32 HalADCReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg);
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_clk.h Normal file
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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_RTL8195A_CLK_H
#define MBED_RTL8195A_CLK_H
#define PLATFORM_CLK (200000000UL/6*5) // 166MHz
//#define SYSTEM_CLK PLATFORM_CLK
//#define TIMER_CLK (32*1000)
#define __BUILD_CCTRL_MACRO(name,ctrl) \
static inline void \
__##name##_ACTCK_Enable(void) \
{ \
__RTK_PERI_SETBIT(ctrl, BIT_ACTCK_##name); \
} \
static inline void \
__##name##_SLPCK_Enable(void) \
{ \
__RTK_PERI_SETBIT(ctrl, BIT_SLPCK_##name); \
} \
static inline void \
__##name##_ACTCK_Disable(void) \
{ \
__RTK_PERI_CLRBIT(ctrl, BIT_ACTCK_##name); \
} \
static inline void \
__##name##_SLPCK_Disable(void) \
{ \
__RTK_PERI_CLRBIT(ctrl, BIT_SLPCK_##name); \
} \
//enum clk_idx {
// CLK_ANACK = 0,
// CLK_A33CK = 1,
//};
// Interface to ROM functions
extern __longcall uint32_t HalGetCpuClk(void);
#define __CLK_GetCPUClk HalGetCpuClk
// Interface for HAL functions
static inline uint32_t CLK_GetCPUClk(void)
{
return __CLK_GetCPUClk();
}
extern void CLK_BackupCPUClk(void);
extern void CLK_ReFillCPUClk(void);
extern uint32_t CLK_Calculate(uint8_t clksel);
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_compiler.h Normal file
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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_RTL8195A_COMPILER_H
#define MBED_RTL8195A_COMPILER_H
#if defined (__ICCARM__)
#ifndef STRINGIFY
#define STRINGIFY(a) #a
#endif
#ifndef SECTION
#define SECTION(_name) _Pragma( STRINGIFY(location=##_name##))
#endif
#ifndef ALIGNMTO
#define ALIGNMTO(_bound) _Pragma( STRINGIFY(data_alignment=##_bound##))
#endif
#define __romcall
#define __longcall
#elif defined(__CC_ARM)
#ifndef __longcall
#define __longcall __attribute__ ((long_call))
#endif
#else
#define SECTION(_name) __attribute__ ((__section__(_name)))
#define ALIGNMTO(_bound) __attribute__ ((aligned (_bound)))
#ifndef __packed
#define __packed __attribute__ ((packed))
#endif
#ifndef __romcall
#define __romcall __attribute__ ((long_call))
#endif
#ifndef __longcall
#define __longcall __attribute__ ((long_call))
#endif
#ifndef __weak
#define __weak __attribute__ ((weak))
#endif
#endif
#endif

306
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_dac.h Normal file
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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
#ifndef _RTL8195A_DAC_H_
#define _RTL8195A_DAC_H_
//================ Register Bit Field ==========================
//2 REG_DAC0_FIFO_WR
#define BIT_SHIFT_DAC0_FIFO_WO 0
#define BIT_MASK_DAC0_FIFO_WO 0xffffffffL
#define BIT_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO)
#define BIT_CTRL_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO)
#define BIT_GET_DAC0_FIFO_WO(x) (((x) >> BIT_SHIFT_DAC0_FIFO_WO) & BIT_MASK_DAC0_FIFO_WO)
//2 REG_DAC_CTRL
#define BIT_SHIFT_DAC_DELTA_SIGMA 25
#define BIT_MASK_DAC_DELTA_SIGMA 0x7
#define BIT_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA)
#define BIT_CTRL_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA)
#define BIT_GET_DAC_DELTA_SIGMA(x) (((x) >> BIT_SHIFT_DAC_DELTA_SIGMA) & BIT_MASK_DAC_DELTA_SIGMA)
#define BIT_DAC_BYPASS_DSC BIT(24)
#define BIT_SHIFT_DAC_BYPASS_DSC 24
#define BIT_MASK_DAC_BYPASS_DSC 0x1
#define BIT_CTRL_DAC_BYPASS_DSC(x) (((x) & BIT_MASK_DAC_BYPASS_DSC) << BIT_SHIFT_DAC_BYPASS_DSC)
#define BIT_SHIFT_DAC_DSC_DBG_SEL 19
#define BIT_MASK_DAC_DSC_DBG_SEL 0x3
#define BIT_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL)
#define BIT_CTRL_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL)
#define BIT_GET_DAC_DSC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DSC_DBG_SEL) & BIT_MASK_DAC_DSC_DBG_SEL)
#define BIT_SHIFT_DAC_DBG_SEL 16
#define BIT_MASK_DAC_DBG_SEL 0x7
#define BIT_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL)
#define BIT_CTRL_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL)
#define BIT_GET_DAC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DBG_SEL) & BIT_MASK_DAC_DBG_SEL)
#define BIT_SHIFT_DAC_BURST_SIZE 8
#define BIT_MASK_DAC_BURST_SIZE 0xf
#define BIT_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE)
#define BIT_CTRL_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE)
#define BIT_GET_DAC_BURST_SIZE(x) (((x) >> BIT_SHIFT_DAC_BURST_SIZE) & BIT_MASK_DAC_BURST_SIZE)
#define BIT_DAC_FILTER_SETTLE BIT(4)
#define BIT_SHIFT_DAC_FILTER_SETTLE 4
#define BIT_MASK_DAC_FILTER_SETTLE 0x1
#define BIT_CTRL_DAC_FILTER_SETTLE(x) (((x) & BIT_MASK_DAC_FILTER_SETTLE) << BIT_SHIFT_DAC_FILTER_SETTLE)
#define BIT_DAC_OV_OPTION BIT(3)
#define BIT_SHIFT_DAC_OV_OPTION 3
#define BIT_MASK_DAC_OV_OPTION 0x1
#define BIT_CTRL_DAC_OV_OPTION(x) (((x) & BIT_MASK_DAC_OV_OPTION) << BIT_SHIFT_DAC_OV_OPTION)
#define BIT_DAC_ENDIAN BIT(2)
#define BIT_SHIFT_DAC_ENDIAN 2
#define BIT_MASK_DAC_ENDIAN 0x1
#define BIT_CTRL_DAC_ENDIAN(x) (((x) & BIT_MASK_DAC_ENDIAN) << BIT_SHIFT_DAC_ENDIAN)
#define BIT_DAC_SPEED BIT(1)
#define BIT_SHIFT_DAC_SPEED 1
#define BIT_MASK_DAC_SPEED 0x1
#define BIT_CTRL_DAC_SPEED(x) (((x) & BIT_MASK_DAC_SPEED) << BIT_SHIFT_DAC_SPEED)
#define BIT_DAC_FIFO_EN BIT(0)
#define BIT_SHIFT_DAC_FIFO_EN 0
#define BIT_MASK_DAC_FIFO_EN 0x1
#define BIT_CTRL_DAC_FIFO_EN(x) (((x) & BIT_MASK_DAC_FIFO_EN) << BIT_SHIFT_DAC_FIFO_EN)
//2 REG_DAC_INTR_CTRL
#define BIT_DAC_DSC_OVERFLOW1_EN BIT(6)
#define BIT_SHIFT_DAC_DSC_OVERFLOW1_EN 6
#define BIT_MASK_DAC_DSC_OVERFLOW1_EN 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW1_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW1_EN)
#define BIT_DAC_DSC_OVERFLOW0_EN BIT(5)
#define BIT_SHIFT_DAC_DSC_OVERFLOW0_EN 5
#define BIT_MASK_DAC_DSC_OVERFLOW0_EN 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW0_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW0_EN)
#define BIT_DAC__WRITE_ERROR_EN BIT(4)
#define BIT_SHIFT_DAC__WRITE_ERROR_EN 4
#define BIT_MASK_DAC__WRITE_ERROR_EN 0x1
#define BIT_CTRL_DAC__WRITE_ERROR_EN(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_EN) << BIT_SHIFT_DAC__WRITE_ERROR_EN)
#define BIT_DAC_FIFO_STOP_EN BIT(3)
#define BIT_SHIFT_DAC_FIFO_STOP_EN 3
#define BIT_MASK_DAC_FIFO_STOP_EN 0x1
#define BIT_CTRL_DAC_FIFO_STOP_EN(x) (((x) & BIT_MASK_DAC_FIFO_STOP_EN) << BIT_SHIFT_DAC_FIFO_STOP_EN)
#define BIT_DAC_FIFO_OVERFLOW_EN BIT(2)
#define BIT_SHIFT_DAC_FIFO_OVERFLOW_EN 2
#define BIT_MASK_DAC_FIFO_OVERFLOW_EN 0x1
#define BIT_CTRL_DAC_FIFO_OVERFLOW_EN(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_EN) << BIT_SHIFT_DAC_FIFO_OVERFLOW_EN)
#define BIT_DAC_FIFO_WR_REQ_EN BIT(1)
#define BIT_SHIFT_DAC_FIFO_WR_REQ_EN 1
#define BIT_MASK_DAC_FIFO_WR_REQ_EN 0x1
#define BIT_CTRL_DAC_FIFO_WR_REQ_EN(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_EN) << BIT_SHIFT_DAC_FIFO_WR_REQ_EN)
#define BIT_DAC_FIFO_FULL_EN BIT(0)
#define BIT_SHIFT_DAC_FIFO_FULL_EN 0
#define BIT_MASK_DAC_FIFO_FULL_EN 0x1
#define BIT_CTRL_DAC_FIFO_FULL_EN(x) (((x) & BIT_MASK_DAC_FIFO_FULL_EN) << BIT_SHIFT_DAC_FIFO_FULL_EN)
//2 REG_DAC_INTR_STS
#define BIT_DAC_DSC_OVERFLOW1_ST BIT(6)
#define BIT_SHIFT_DAC_DSC_OVERFLOW1_ST 6
#define BIT_MASK_DAC_DSC_OVERFLOW1_ST 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW1_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW1_ST)
#define BIT_DAC_DSC_OVERFLOW0_ST BIT(5)
#define BIT_SHIFT_DAC_DSC_OVERFLOW0_ST 5
#define BIT_MASK_DAC_DSC_OVERFLOW0_ST 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW0_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW0_ST)
#define BIT_DAC__WRITE_ERROR_ST BIT(4)
#define BIT_SHIFT_DAC__WRITE_ERROR_ST 4
#define BIT_MASK_DAC__WRITE_ERROR_ST 0x1
#define BIT_CTRL_DAC__WRITE_ERROR_ST(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_ST) << BIT_SHIFT_DAC__WRITE_ERROR_ST)
#define BIT_DAC_FIFO_STOP_ST BIT(3)
#define BIT_SHIFT_DAC_FIFO_STOP_ST 3
#define BIT_MASK_DAC_FIFO_STOP_ST 0x1
#define BIT_CTRL_DAC_FIFO_STOP_ST(x) (((x) & BIT_MASK_DAC_FIFO_STOP_ST) << BIT_SHIFT_DAC_FIFO_STOP_ST)
#define BIT_DAC_FIFO_OVERFLOW_ST BIT(2)
#define BIT_SHIFT_DAC_FIFO_OVERFLOW_ST 2
#define BIT_MASK_DAC_FIFO_OVERFLOW_ST 0x1
#define BIT_CTRL_DAC_FIFO_OVERFLOW_ST(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_ST) << BIT_SHIFT_DAC_FIFO_OVERFLOW_ST)
#define BIT_DAC_FIFO_WR_REQ_ST BIT(1)
#define BIT_SHIFT_DAC_FIFO_WR_REQ_ST 1
#define BIT_MASK_DAC_FIFO_WR_REQ_ST 0x1
#define BIT_CTRL_DAC_FIFO_WR_REQ_ST(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_ST) << BIT_SHIFT_DAC_FIFO_WR_REQ_ST)
#define BIT_DAC_FIFO_FULL_ST BIT(0)
#define BIT_SHIFT_DAC_FIFO_FULL_ST 0
#define BIT_MASK_DAC_FIFO_FULL_ST 0x1
#define BIT_CTRL_DAC_FIFO_FULL_ST(x) (((x) & BIT_MASK_DAC_FIFO_FULL_ST) << BIT_SHIFT_DAC_FIFO_FULL_ST)
//2 REG_DAC_PWR_CTRL
#define BIT_SHIFT_DAC_PWR_CUT_CNTR 16
#define BIT_MASK_DAC_PWR_CUT_CNTR 0xff
#define BIT_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR)
#define BIT_CTRL_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR)
#define BIT_GET_DAC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_DAC_PWR_CUT_CNTR) & BIT_MASK_DAC_PWR_CUT_CNTR)
#define BIT_ST_DAC_FIFO_ON BIT(11)
#define BIT_SHIFT_ST_DAC_FIFO_ON 11
#define BIT_MASK_ST_DAC_FIFO_ON 0x1
#define BIT_CTRL_ST_DAC_FIFO_ON(x) (((x) & BIT_MASK_ST_DAC_FIFO_ON) << BIT_SHIFT_ST_DAC_FIFO_ON)
#define BIT_ST_DAC_ISO_ON BIT(10)
#define BIT_SHIFT_ST_DAC_ISO_ON 10
#define BIT_MASK_ST_DAC_ISO_ON 0x1
#define BIT_CTRL_ST_DAC_ISO_ON(x) (((x) & BIT_MASK_ST_DAC_ISO_ON) << BIT_SHIFT_ST_DAC_ISO_ON)
#define BIT_ST_DAC_PWR33_ON BIT(9)
#define BIT_SHIFT_ST_DAC_PWR33_ON 9
#define BIT_MASK_ST_DAC_PWR33_ON 0x1
#define BIT_CTRL_ST_DAC_PWR33_ON(x) (((x) & BIT_MASK_ST_DAC_PWR33_ON) << BIT_SHIFT_ST_DAC_PWR33_ON)
#define BIT_ST_DAC_PWR12_ON BIT(8)
#define BIT_SHIFT_ST_DAC_PWR12_ON 8
#define BIT_MASK_ST_DAC_PWR12_ON 0x1
#define BIT_CTRL_ST_DAC_PWR12_ON(x) (((x) & BIT_MASK_ST_DAC_PWR12_ON) << BIT_SHIFT_ST_DAC_PWR12_ON)
#define BIT_DAC_ISO_MANU BIT(3)
#define BIT_SHIFT_DAC_ISO_MANU 3
#define BIT_MASK_DAC_ISO_MANU 0x1
#define BIT_CTRL_DAC_ISO_MANU(x) (((x) & BIT_MASK_DAC_ISO_MANU) << BIT_SHIFT_DAC_ISO_MANU)
#define BIT_DAC_PWR33_MANU BIT(2)
#define BIT_SHIFT_DAC_PWR33_MANU 2
#define BIT_MASK_DAC_PWR33_MANU 0x1
#define BIT_CTRL_DAC_PWR33_MANU(x) (((x) & BIT_MASK_DAC_PWR33_MANU) << BIT_SHIFT_DAC_PWR33_MANU)
#define BIT_DAC_PWR12_MANU BIT(1)
#define BIT_SHIFT_DAC_PWR12_MANU 1
#define BIT_MASK_DAC_PWR12_MANU 0x1
#define BIT_CTRL_DAC_PWR12_MANU(x) (((x) & BIT_MASK_DAC_PWR12_MANU) << BIT_SHIFT_DAC_PWR12_MANU)
#define BIT_DAC_PWR_AUTO BIT(0)
#define BIT_SHIFT_DAC_PWR_AUTO 0
#define BIT_MASK_DAC_PWR_AUTO 0x1
#define BIT_CTRL_DAC_PWR_AUTO(x) (((x) & BIT_MASK_DAC_PWR_AUTO) << BIT_SHIFT_DAC_PWR_AUTO)
//2 REG_DAC_ANAPAR_DA0
#define BIT_SHIFT_PWR_ALL_CNTR 12
#define BIT_MASK_PWR_ALL_CNTR 0xfffff
#define BIT_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR)
#define BIT_CTRL_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR)
#define BIT_GET_PWR_ALL_CNTR(x) (((x) >> BIT_SHIFT_PWR_ALL_CNTR) & BIT_MASK_PWR_ALL_CNTR)
#define BIT_SHIFT_PWR_FUP_CNTR 0
#define BIT_MASK_PWR_FUP_CNTR 0xfff
#define BIT_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR)
#define BIT_CTRL_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR)
#define BIT_GET_PWR_FUP_CNTR(x) (((x) >> BIT_SHIFT_PWR_FUP_CNTR) & BIT_MASK_PWR_FUP_CNTR)
//2 REG_DAC_ANAPAR_DA1
#define BIT_FUP_EN BIT(31)
#define BIT_SHIFT_FUP_EN 31
#define BIT_MASK_FUP_EN 0x1
#define BIT_CTRL_FUP_EN(x) (((x) & BIT_MASK_FUP_EN) << BIT_SHIFT_FUP_EN)
#define BIT_SHIFT_ANAPAR_DA 8
#define BIT_MASK_ANAPAR_DA 0x7fffff
#define BIT_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA)
#define BIT_CTRL_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA)
#define BIT_GET_ANAPAR_DA(x) (((x) >> BIT_SHIFT_ANAPAR_DA) & BIT_MASK_ANAPAR_DA)
#define BIT_D_POW_DACVREF BIT(7)
#define BIT_SHIFT_D_POW_DACVREF 7
#define BIT_MASK_D_POW_DACVREF 0x1
#define BIT_CTRL_D_POW_DACVREF(x) (((x) & BIT_MASK_D_POW_DACVREF) << BIT_SHIFT_D_POW_DACVREF)
#define BIT_D_POW_VREF2 BIT(6)
#define BIT_SHIFT_D_POW_VREF2 6
#define BIT_MASK_D_POW_VREF2 0x1
#define BIT_CTRL_D_POW_VREF2(x) (((x) & BIT_MASK_D_POW_VREF2) << BIT_SHIFT_D_POW_VREF2)
#define BIT_D_POW_MBIAS BIT(5)
#define BIT_SHIFT_D_POW_MBIAS 5
#define BIT_MASK_D_POW_MBIAS 0x1
#define BIT_CTRL_D_POW_MBIAS(x) (((x) & BIT_MASK_D_POW_MBIAS) << BIT_SHIFT_D_POW_MBIAS)
#define BIT_D_POW_DIV4 BIT(4)
#define BIT_SHIFT_D_POW_DIV4 4
#define BIT_MASK_D_POW_DIV4 0x1
#define BIT_CTRL_D_POW_DIV4(x) (((x) & BIT_MASK_D_POW_DIV4) << BIT_SHIFT_D_POW_DIV4)
#define BIT_D_POW_DF1SE_R BIT(3)
#define BIT_SHIFT_D_POW_DF1SE_R 3
#define BIT_MASK_D_POW_DF1SE_R 0x1
#define BIT_CTRL_D_POW_DF1SE_R(x) (((x) & BIT_MASK_D_POW_DF1SE_R) << BIT_SHIFT_D_POW_DF1SE_R)
#define BIT_D_POW_DF2SE_L BIT(2)
#define BIT_SHIFT_D_POW_DF2SE_L 2
#define BIT_MASK_D_POW_DF2SE_L 0x1
#define BIT_CTRL_D_POW_DF2SE_L(x) (((x) & BIT_MASK_D_POW_DF2SE_L) << BIT_SHIFT_D_POW_DF2SE_L)
#define BIT_D_POW_DAC_R BIT(1)
#define BIT_SHIFT_D_POW_DAC_R 1
#define BIT_MASK_D_POW_DAC_R 0x1
#define BIT_CTRL_D_POW_DAC_R(x) (((x) & BIT_MASK_D_POW_DAC_R) << BIT_SHIFT_D_POW_DAC_R)
#define BIT_D_POW_DAC_L BIT(0)
#define BIT_SHIFT_D_POW_DAC_L 0
#define BIT_MASK_D_POW_DAC_L 0x1
#define BIT_CTRL_D_POW_DAC_L(x) (((x) & BIT_MASK_D_POW_DAC_L) << BIT_SHIFT_D_POW_DAC_L)
//================ Register Reg Field =========================
#define REG_DAC0_FIFO_WR 0x0000
#define REG_DAC_CTRL 0x0004
#define REG_DAC_INTR_CTRL 0x0008
#define REG_DAC_INTR_STS 0x000C
#define REG_DAC_PWR_CTRL 0x0010
#define REG_DAC_ANAPAR_DA0 0x0014
#define REG_DAC_ANAPAR_DA1 0x0018
//================ DAC HAL related enumeration ==================
//================ DAC HAL Macro ===========================
#define HAL_DAC_WRITE32(dacidx, addr, value) HAL_WRITE32(DAC_REG_BASE+dacidx*0x800 \
,addr,value)
#define HAL_DAC_READ32(dacidx, addr) HAL_READ32(DAC_REG_BASE+dacidx*0x800,addr)
//================ DAC Function Prototypes =====================
RTK_STATUS HalDACInit8195a(IN VOID *Data);
RTK_STATUS HalDACDeInit8195a(IN VOID *Data);
RTK_STATUS HalDACEnableRtl8195a(IN VOID *Data);
RTK_STATUS HalDACIntrCtrl8195a(IN VOID *Data);
u8 HalDACSendRtl8195a(IN VOID *Data);
u32 HalDACReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg);
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_gdma.h Normal file
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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
#ifndef _RTL8195A_GDMA_H_
#define _RTL8195A_GDMA_H_
// Define GDMA Handshake interface with peripheral, 0 -> GDMA0, 1-> GDMA1
// Set this Hnadshake interface map to register REG_PESOC_SOC_CTRL
#define GDMA_HANDSHAKE_UART0_TX 0
#define GDMA_HANDSHAKE_UART0_RX 1
#define GDMA_HANDSHAKE_UART1_TX 2
#define GDMA_HANDSHAKE_UART1_RX 3
#define GDMA_HANDSHAKE_UART2_TX 14 // Only on GDMA 0, hardware fixed
#define GDMA_HANDSHAKE_UART2_RX 14 // Only on GDMA 1, hardware fixed
#define GDMA_HANDSHAKE_SSI0_TX 4
#define GDMA_HANDSHAKE_SSI0_RX 5
#define GDMA_HANDSHAKE_SSI1_TX 6
#define GDMA_HANDSHAKE_SSI1_RX 7
#define GDMA_HANDSHAKE_SSI2_TX 15 // Only on GDMA 0, hardware fixed
#define GDMA_HANDSHAKE_SSI2_RX 15 // Only on GDMA 1, hardware fixed
#define GDMA_HANDSHAKE_I2C0_TX 8
#define GDMA_HANDSHAKE_I2C0_RX 9
#define GDMA_HANDSHAKE_I2C1_TX 10
#define GDMA_HANDSHAKE_I2C1_RX 11
#define GDMA_HANDSHAKE_ADC 12
#define GDMA_HANDSHAKE_DAC0 13 // Only on GDMA 0, hardware fixed
#define GDMA_HANDSHAKE_DAC1 13 // Only on GDMA 1, hardware fixed
#define HAL_GDMAX_READ32(GdmaIndex, addr) \
HAL_READ32(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
#define HAL_GDMAX_WRITE32(GdmaIndex, addr, value) \
HAL_WRITE32((GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF)), addr, value)
#define HAL_GDMAX_READ16(GdmaIndex, addr) \
HAL_READ16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
#define HAL_GDMAX_WRITE16(GdmaIndex, addr, value) \
HAL_WRITE16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value)
#define HAL_GDMAX_READ8(GdmaIndex, addr) \
HAL_READ8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
#define HAL_GDMAX_WRITE8(GdmaIndex, addr, value) \
HAL_WRITE8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value)
#define GDMA_CH_MAX 0x06
#define REG_GDMA_CH_OFF 0x058
#define REG_GDMA_CH_SAR 0x000
#define REG_GDMA_CH_DAR 0x008
#define REG_GDMA_CH_LLP 0x010
#define REG_GDMA_CH_CTL 0x018
#define REG_GDMA_CH_SSTAT 0x020
#define REG_GDMA_CH_DSTAT 0x028
#define REG_GDMA_CH_SSTATAR 0x030
#define REG_GDMA_CH_DSTATAR 0x038
#define REG_GDMA_CH_CFG 0x040
#define REG_GDMA_CH_SGR 0x048
#define REG_GDMA_CH_DSR 0x050
#define MAX_DMA_BLOCK_SIZE 4092
//3 Interrupt Registers
#define REG_GDMA_RAW_INT_BASE 0x2C0
#define REG_GDMA_RAW_INT_TFR 0x2C0
#define REG_GDMA_RAW_INT_BLOCK 0x2c8
#define REG_GDMA_RAW_INT_SRC_TRAN 0x2D0
#define REG_GDMA_RAW_INT_DST_TRAN 0x2D8
#define REG_GDMA_RAW_INT_ERR 0x2E0
#define REG_GDMA_STATUS_INT_BASE 0x2E8
#define REG_GDMA_STATUS_INT_TFR 0x2E8
#define REG_GDMA_STATUS_INT_BLOCK 0x2F0
#define REG_GDMA_STATUS_INT_SRC_TRAN 0x2F8
#define REG_GDMA_STATUS_INT_DST_TRAN 0x300
#define REG_GDMA_STATUS_INT_ERR 0x308
#define REG_GDMA_MASK_INT_BASE 0x310
#define REG_GDMA_MASK_INT_TFR 0x310
#define REG_GDMA_MASK_INT_BLOCK 0x318
#define REG_GDMA_MASK_INT_SRC_TRAN 0x320
#define REG_GDMA_MASK_INT_DST_TRAN 0x328
#define REG_GDMA_MASK_INT_INT_ERR 0x330
#define REG_GDMA_CLEAR_INT_BASE 0x338
#define REG_GDMA_CLEAR_INT_TFR 0x338
#define REG_GDMA_CLEAR_INT_BLOCK 0x340
#define REG_GDMA_CLEAR_INT_SRC_TRAN 0x348
#define REG_GDMA_CLEAR_INT_DST_TRAN 0x350
#define REG_GDMA_CLEAR_INT_ERR 0x358
#define REG_GDMA_STATUS_INT 0x360
//3 Software handshaking Registers
#define REG_GDMA_REQ_SRC 0x368
#define REG_GDMA_REQ_DST 0x370
#define REG_GDMA_REQ_SGL_REQ 0x378
#define REG_GDMA_REQ_DST_REQ 0x380
#define REG_GDMA_REQ_LST_SRC 0x388
#define REG_GDMA_REQ_LST_DST 0x390
//3 Miscellaneous Registers
#define REG_GDMA_DMAC_CFG 0x398
#define REG_GDMA_CH_EN 0x3A0
#define REG_GDMA_DMA_ID 0x3A8
#define REG_GDMA_DMA_TEST 0x3B0
#define REG_GDMA_DMA_COM_PARAMS6 0x3C8
#define REG_GDMA_DMA_COM_PARAMS5 0x3D0
#define REG_GDMA_DMA_COM_PARAMS4 0x3D8
#define REG_GDMA_DMA_COM_PARAMS3 0x3E0
#define REG_GDMA_DMA_COM_PARAMS2 0x3E8
#define REG_GDMA_DMA_COM_PARAMS1 0x3F0
#define REG_GDMA_DMA_COM_PARAMS0 0x3F8
//3 CTL Register Bit Control
#define BIT_SHIFT_CTLX_LO_INT_EN 0
#define BIT_MASK_CTLX_LO_INT_EN 0x1
#define BIT_CTLX_LO_INT_EN(x)(((x) & BIT_MASK_CTLX_LO_INT_EN) << BIT_SHIFT_CTLX_LO_INT_EN)
#define BIT_INVC_CTLX_LO_INT_EN (~(BIT_MASK_CTLX_LO_INT_EN << BIT_SHIFT_CTLX_LO_INT_EN))
#define BIT_SHIFT_CTLX_LO_DST_TR_WIDTH 1
#define BIT_MASK_CTLX_LO_DST_TR_WIDTH 0x7
#define BIT_CTLX_LO_DST_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_DST_TR_WIDTH) << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH)
#define BIT_INVC_CTLX_LO_DST_TR_WIDTH (~(BIT_MASK_CTLX_LO_DST_TR_WIDTH << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH))
#define BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH 4
#define BIT_MASK_CTLX_LO_SRC_TR_WIDTH 0x7
#define BIT_CTLX_LO_SRC_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_SRC_TR_WIDTH) << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH)
#define BIT_INVC_CTLX_LO_SRC_TR_WIDTH (~(BIT_MASK_CTLX_LO_SRC_TR_WIDTH << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH))
#define BIT_SHIFT_CTLX_LO_DINC 7
#define BIT_MASK_CTLX_LO_DINC 0x3
#define BIT_CTLX_LO_DINC(x)(((x) & BIT_MASK_CTLX_LO_DINC) << BIT_SHIFT_CTLX_LO_DINC)
#define BIT_INVC_CTLX_LO_DINC (~(BIT_MASK_CTLX_LO_DINC << BIT_SHIFT_CTLX_LO_DINC))
#define BIT_SHIFT_CTLX_LO_SINC 9
#define BIT_MASK_CTLX_LO_SINC 0x3
#define BIT_CTLX_LO_SINC(x)(((x) & BIT_MASK_CTLX_LO_SINC) << BIT_SHIFT_CTLX_LO_SINC)
#define BIT_INVC_CTLX_LO_SINC (~(BIT_MASK_CTLX_LO_SINC << BIT_SHIFT_CTLX_LO_SINC))
#define BIT_SHIFT_CTLX_LO_DEST_MSIZE 11
#define BIT_MASK_CTLX_LO_DEST_MSIZE 0x7
#define BIT_CTLX_LO_DEST_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_DEST_MSIZE) << BIT_SHIFT_CTLX_LO_DEST_MSIZE)
#define BIT_INVC_CTLX_LO_DEST_MSIZE (~(BIT_MASK_CTLX_LO_DEST_MSIZE << BIT_SHIFT_CTLX_LO_DEST_MSIZE))
#define BIT_SHIFT_CTLX_LO_SRC_MSIZE 14
#define BIT_MASK_CTLX_LO_SRC_MSIZE 0x7
#define BIT_CTLX_LO_SRC_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_SRC_MSIZE) << BIT_SHIFT_CTLX_LO_SRC_MSIZE)
#define BIT_INVC_CTLX_LO_SRC_MSIZE (~(BIT_MASK_CTLX_LO_SRC_MSIZE << BIT_SHIFT_CTLX_LO_SRC_MSIZE))
#define BIT_SHIFT_CTLX_LO_SRC_GATHER_EN 17
#define BIT_MASK_CTLX_LO_SRC_GATHER_EN 0x1
#define BIT_CTLX_LO_SRC_GATHER_EN(x)(((x) & BIT_MASK_CTLX_LO_SRC_GATHER_EN) << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN)
#define BIT_INVC_CTLX_LO_SRC_GATHER_EN (~(BIT_MASK_CTLX_LO_SRC_GATHER_EN << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN))
#define BIT_SHIFT_CTLX_LO_DST_SCATTER_EN 18
#define BIT_MASK_CTLX_LO_DST_SCATTER_EN 0x1
#define BIT_CTLX_LO_DST_SCATTER_EN(x)(((x) & BIT_MASK_CTLX_LO_DST_SCATTER_EN) << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN)
#define BIT_INVC_CTLX_LO_DST_SCATTER_EN (~(BIT_MASK_CTLX_LO_DST_SCATTER_EN << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN))
#define BIT_SHIFT_CTLX_LO_TT_FC 20
#define BIT_MASK_CTLX_LO_TT_FC 0x7
#define BIT_CTLX_LO_TT_FC(x)(((x) & BIT_MASK_CTLX_LO_TT_FC) << BIT_SHIFT_CTLX_LO_TT_FC)
#define BIT_INVC_CTLX_LO_TT_FC (~(BIT_MASK_CTLX_LO_TT_FC << BIT_SHIFT_CTLX_LO_TT_FC))
#define BIT_SHIFT_CTLX_LO_DMS 23
#define BIT_MASK_CTLX_LO_DMS 0x3
#define BIT_CTLX_LO_DMS(x)(((x) & BIT_MASK_CTLX_LO_DMS) << BIT_MASK_CTLX_LO_DMS)
#define BIT_INVC_CTLX_LO_DMS (~(BIT_MASK_CTLX_LO_DMS << BIT_SHIFT_CTLX_LO_DMS))
#define BIT_SHIFT_CTLX_LO_SMS 25
#define BIT_MASK_CTLX_LO_SMS 0x3
#define BIT_CTLX_LO_SMS(x)(((x) & BIT_MASK_CTLX_LO_SMS) << BIT_SHIFT_CTLX_LO_SMS)
#define BIT_INVC_CTLX_LO_SMS (~(BIT_MASK_CTLX_LO_SMS << BIT_SHIFT_CTLX_LO_SMS))
#define BIT_SHIFT_CTLX_LO_LLP_DST_EN 27
#define BIT_MASK_CTLX_LO_LLP_DST_EN 0x1
#define BIT_CTLX_LO_LLP_DST_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_DST_EN) << BIT_SHIFT_CTLX_LO_LLP_DST_EN)
#define BIT_INVC_CTLX_LO_LLP_DST_EN (~(BIT_MASK_CTLX_LO_LLP_DST_EN << BIT_SHIFT_CTLX_LO_LLP_DST_EN))
#define BIT_SHIFT_CTLX_LO_LLP_SRC_EN 28
#define BIT_MASK_CTLX_LO_LLP_SRC_EN 0x1
#define BIT_CTLX_LO_LLP_SRC_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_SRC_EN) << BIT_SHIFT_CTLX_LO_LLP_SRC_EN)
#define BIT_INVC_CTLX_LO_LLP_SRC_EN (~(BIT_MASK_CTLX_LO_LLP_SRC_EN << BIT_SHIFT_CTLX_LO_LLP_SRC_EN))
#define BIT_SHIFT_CTLX_UP_BLOCK_BS 0
#define BIT_MASK_CTLX_UP_BLOCK_BS 0xFFF
#define BIT_CTLX_UP_BLOCK_BS(x)(((x) & BIT_MASK_CTLX_UP_BLOCK_BS) << BIT_SHIFT_CTLX_UP_BLOCK_BS)
#define BIT_INVC_CTLX_UP_BLOCK_BS (~(BIT_MASK_CTLX_UP_BLOCK_BS << BIT_SHIFT_CTLX_UP_BLOCK_BS))
#define BIT_SHIFT_CTLX_UP_DONE 12
#define BIT_MASK_CTLX_UP_DONE 0x1
#define BIT_CTLX_UP_DONE(x)(((x) & BIT_MASK_CTLX_UP_DONE) << BIT_SHIFT_CTLX_UP_DONE)
#define BIT_INVC_CTLX_UP_DONE (~(BIT_MASK_CTLX_UP_DONE << BIT_SHIFT_CTLX_UP_DONE))
//3 CFG Register Bit Control
#define BIT_SHIFT_CFGX_LO_CH_PRIOR 5
#define BIT_MASK_CFGX_LO_CH_PRIOR 0x7
#define BIT_CFGX_LO_CH_PRIOR(x)(((x) & BIT_MASK_CFGX_LO_CH_PRIOR) << BIT_SHIFT_CFGX_LO_CH_PRIOR)
#define BIT_INVC_CFGX_LO_CH_PRIOR (~(BIT_MASK_CFGX_LO_CH_PRIOR << BIT_SHIFT_CFGX_LO_CH_PRIOR))
#define BIT_SHIFT_CFGX_LO_CH_SUSP 8
#define BIT_MASK_CFGX_LO_CH_SUSP 0x1
#define BIT_CFGX_LO_CH_SUSP(x)(((x) & BIT_MASK_CFGX_LO_CH_SUSP) << BIT_SHIFT_CFGX_LO_CH_SUSP)
#define BIT_INVC_CFGX_LO_CH_SUSP (~(BIT_MASK_CFGX_LO_CH_SUSP << BIT_SHIFT_CFGX_LO_CH_SUSP))
#define BIT_SHIFT_CFGX_LO_FIFO_EMPTY 9
#define BIT_MASK_CFGX_LO_FIFO_EMPTY 0x1
#define BIT_CFGX_LO_FIFO_EMPTY(x)(((x) & BIT_MASK_CFGX_LO_FIFO_EMPTY) << BIT_SHIFT_CFGX_LO_FIFO_EMPTY)
#define BIT_INVC_CFGX_LO_FIFO_EMPTY (~(BIT_MASK_CFGX_LO_FIFO_EMPTY << BIT_SHIFT_CFGX_LO_FIFO_EMPTY))
#define BIT_SHIFT_CFGX_LO_HS_SEL_DST 10
#define BIT_MASK_CFGX_LO_HS_SEL_DST 0x1
#define BIT_CFGX_LO_HS_SEL_DST(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_DST) << BIT_SHIFT_CFGX_LO_HS_SEL_DST)
#define BIT_INVC_CFGX_LO_HS_SEL_DST (~(BIT_MASK_CFGX_LO_HS_SEL_DST << BIT_SHIFT_CFGX_LO_HS_SEL_DST))
#define BIT_SHIFT_CFGX_LO_HS_SEL_SRC 11
#define BIT_MASK_CFGX_LO_HS_SEL_SRC 0x1
#define BIT_CFGX_LO_HS_SEL_SRC(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_SRC) << BIT_SHIFT_CFGX_LO_HS_SEL_SRC)
#define BIT_INVC_CFGX_LO_HS_SEL_SRC (~(BIT_MASK_CFGX_LO_HS_SEL_SRC << BIT_SHIFT_CFGX_LO_HS_SEL_SRC))
#define BIT_SHIFT_CFGX_LO_LOCK_CH_L 12
#define BIT_MASK_CFGX_LO_LOCK_CH_L 0x3
#define BIT_CFGX_LO_LOCK_CH_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH_L) << BIT_SHIFT_CFGX_LO_LOCK_CH_L)
#define BIT_INVC_CFGX_LO_LOCK_CH_L (~(BIT_MASK_CFGX_LO_LOCK_CH_L << BIT_SHIFT_CFGX_LO_LOCK_CH_L))
#define BIT_SHIFT_CFGX_LO_LOCK_B_L 14
#define BIT_MASK_CFGX_LO_LOCK_B_L 0x3
#define BIT_CFGX_LO_LOCK_B_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B_L) << BIT_SHIFT_CFGX_LO_LOCK_B_L)
#define BIT_INVC_CFGX_LO_LOCK_B_L (~(BIT_MASK_CFGX_LO_LOCK_B_L << BIT_SHIFT_CFGX_LO_LOCK_B_L))
#define BIT_SHIFT_CFGX_LO_LOCK_CH 16
#define BIT_MASK_CFGX_LO_LOCK_CH 0x1
#define BIT_CFGX_LO_LOCK_CH(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH) << BIT_SHIFT_CFGX_LO_LOCK_CH)
#define BIT_INVC_CFGX_LO_LOCK_CH (~(BIT_MASK_CFGX_LO_LOCK_CH << BIT_SHIFT_CFGX_LO_LOCK_CH))
#define BIT_SHIFT_CFGX_LO_LOCK_B 17
#define BIT_MASK_CFGX_LO_LOCK_B 0x1
#define BIT_CFGX_LO_LOCK_B(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B) << BIT_SHIFT_CFGX_LO_LOCK_B)
#define BIT_INVC_CFGX_LO_LOCK_B (~(BIT_MASK_CFGX_LO_LOCK_B << BIT_SHIFT_CFGX_LO_LOCK_B))
#define BIT_SHIFT_CFGX_LO_DST_HS_POL 18
#define BIT_MASK_CFGX_LO_DST_HS_POL 0x1
#define BIT_CFGX_LO_DST_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_DST_HS_POL) << BIT_SHIFT_CFGX_LO_DST_HS_POL)
#define BIT_INVC_CFGX_LO_DST_HS_POL (~(BIT_MASK_CFGX_LO_DST_HS_POL << BIT_SHIFT_CFGX_LO_DST_HS_POL))
#define BIT_SHIFT_CFGX_LO_SRC_HS_POL 19
#define BIT_MASK_CFGX_LO_SRC_HS_POL 0x1
#define BIT_CFGX_LO_SRC_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_SRC_HS_POL) << BIT_SHIFT_CFGX_LO_SRC_HS_POL)
#define BIT_INVC_CFGX_LO_SRC_HS_POL (~(BIT_MASK_CFGX_LO_SRC_HS_POL << BIT_SHIFT_CFGX_LO_SRC_HS_POL))
#define BIT_SHIFT_CFGX_LO_MAX_ABRST 20
#define BIT_MASK_CFGX_LO_MAX_ABRST 0x3FF
#define BIT_CFGX_LO_MAX_ABRST(x)(((x) & BIT_MASK_CFGX_LO_MAX_ABRST) << BIT_SHIFT_CFGX_LO_MAX_ABRST)
#define BIT_INVC_CFGX_LO_MAX_ABRST (~(BIT_MASK_CFGX_LO_MAX_ABRST << BIT_SHIFT_CFGX_LO_MAX_ABRST))
#define BIT_SHIFT_CFGX_LO_RELOAD_SRC 30
#define BIT_MASK_CFGX_LO_RELOAD_SRC 0x1
#define BIT_CFGX_LO_RELOAD_SRC(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_SRC) << BIT_SHIFT_CFGX_LO_RELOAD_SRC)
#define BIT_INVC_CFGX_LO_RELOAD_SRC (~(BIT_MASK_CFGX_LO_RELOAD_SRC << BIT_SHIFT_CFGX_LO_RELOAD_SRC))
#define BIT_SHIFT_CFGX_LO_RELOAD_DST 31
#define BIT_MASK_CFGX_LO_RELOAD_DST 0x1
#define BIT_CFGX_LO_RELOAD_DST(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_DST) << BIT_SHIFT_CFGX_LO_RELOAD_DST)
#define BIT_INVC_CFGX_LO_RELOAD_DST (~(BIT_MASK_CFGX_LO_RELOAD_DST << BIT_SHIFT_CFGX_LO_RELOAD_DST))
#define BIT_SHIFT_CFGX_UP_FCMODE 0
#define BIT_MASK_CFGX_UP_FCMODE 0x1
#define BIT_CFGX_UP_FCMODE(x)(((x) & BIT_MASK_CFGX_UP_FCMODE) << BIT_SHIFT_CFGX_UP_FCMODE)
#define BIT_INVC_CFGX_UP_FCMODE (~(BIT_MASK_CFGX_UP_FCMODE << BIT_SHIFT_CFGX_UP_FCMODE))
#define BIT_SHIFT_CFGX_UP_FIFO_MODE 1
#define BIT_MASK_CFGX_UP_FIFO_MODE 0x1
#define BIT_CFGX_UP_FIFO_MODE(x)(((x) & BIT_MASK_CFGX_UP_FIFO_MODE) << BIT_SHIFT_CFGX_UP_FIFO_MODE)
#define BIT_INVC_CFGX_UP_FIFO_MODE (~(BIT_MASK_CFGX_UP_FIFO_MODE << BIT_SHIFT_CFGX_UP_FIFO_MODE))
#define BIT_SHIFT_CFGX_UP_PROTCTL 2
#define BIT_MASK_CFGX_UP_PROTCTL 0x7
#define BIT_CFGX_UP_PROTCTL(x)(((x) & BIT_MASK_CFGX_UP_PROTCTL) << BIT_SHIFT_CFGX_UP_PROTCTL)
#define BIT_INVC_CFGX_UP_PROTCTL (~(BIT_MASK_CFGX_UP_PROTCTL << BIT_SHIFT_CFGX_UP_PROTCTL))
#define BIT_SHIFT_CFGX_UP_DS_UPD_EN 5
#define BIT_MASK_CFGX_UP_DS_UPD_EN 0x1
#define BIT_CFGX_UP_DS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_DS_UPD_EN) << BIT_SHIFT_CFGX_UP_DS_UPD_EN)
#define BIT_INVC_CFGX_UP_DS_UPD_EN (~(BIT_MASK_CFGX_UP_DS_UPD_EN << BIT_SHIFT_CFGX_UP_DS_UPD_EN))
#define BIT_SHIFT_CFGX_UP_SS_UPD_EN 6
#define BIT_MASK_CFGX_UP_SS_UPD_EN 0x1
#define BIT_CFGX_UP_SS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_SS_UPD_EN) << BIT_SHIFT_CFGX_UP_SS_UPD_EN)
#define BIT_INVC_CFGX_UP_SS_UPD_EN (~(BIT_MASK_CFGX_UP_SS_UPD_EN << BIT_SHIFT_CFGX_UP_SS_UPD_EN))
#define BIT_SHIFT_CFGX_UP_SRC_PER 7
#define BIT_MASK_CFGX_UP_SRC_PER 0xF
#define BIT_CFGX_UP_SRC_PER(x)(((x) & BIT_MASK_CFGX_UP_SRC_PER) << BIT_SHIFT_CFGX_UP_SRC_PER)
#define BIT_INVC_CFGX_UP_SRC_PER (~(BIT_MASK_CFGX_UP_SRC_PER << BIT_SHIFT_CFGX_UP_SRC_PER))
#define BIT_SHIFT_CFGX_UP_DEST_PER 11
#define BIT_MASK_CFGX_UP_DEST_PER 0xF
#define BIT_CFGX_UP_DEST_PER(x)(((x) & BIT_MASK_CFGX_UP_DEST_PER) << BIT_SHIFT_CFGX_UP_DEST_PER)
#define BIT_INVC_CFGX_UP_DEST_PER (~(BIT_MASK_CFGX_UP_DEST_PER << BIT_SHIFT_CFGX_UP_DEST_PER))
enum _GDMA_CHANNEL_NUM_ {
GdmaNoCh = 0x0000,
GdmaCh0 = 0x0101,
GdmaCh1 = 0x0202,
GdmaCh2 = 0x0404,
GdmaCh3 = 0x0808,
GdmaCh4 = 0x1010,
GdmaCh5 = 0x2020,
GdmaCh6 = 0x4040,
GdmaCh7 = 0x8080,
GdmaAllCh = 0xffff
};
typedef uint32_t GDMA_CHANNEL_NUM;
typedef uint32_t *PGDMA_CHANNEL_NUM;
//3 CTL register struct
enum _GDMA_CTL_TT_FC_TYPE_ {
TTFCMemToMem = 0x00,
TTFCMemToPeri = 0x01,
TTFCPeriToMem = 0x02
};
typedef uint32_t GDMA_CTL_TT_FC_TYPE;
typedef uint32_t *PGDMA_CTL_TT_FC_TYPE;
//Max type = Bus Width
enum _GDMA_CTL_TR_WIDTH_ {
TrWidthOneByte = 0x00,
TrWidthTwoBytes = 0x01,
TrWidthFourBytes = 0x02
};
typedef uint32_t GDMA_CTL_TR_WIDTH;
typedef uint32_t *PGDMA_CTL_TR_WIDTH;
enum _GDMA_CTL_MSIZE_ {
MsizeOne = 0x00,
MsizeFour = 0x01,
MsizeEight = 0x02
};
typedef uint32_t GDMA_CTL_MSIZE;
typedef uint32_t *PGDMA_CTL_MSIZE;
enum _GDMA_INC_TYPE_ {
IncType = 0x00,
DecType = 0x01,
NoChange = 0x02
};
typedef uint32_t GDMA_INC_TYPE;
typedef uint32_t *PGDMA_INC_TYPE;
typedef struct _GDMA_CTL_REG_ {
GDMA_CTL_TT_FC_TYPE TtFc;
GDMA_CTL_TR_WIDTH DstTrWidth;
GDMA_CTL_TR_WIDTH SrcTrWidth;
GDMA_INC_TYPE Dinc;
GDMA_INC_TYPE Sinc;
GDMA_CTL_MSIZE DestMsize;
GDMA_CTL_MSIZE SrcMsize;
u8 IntEn :1; // Bit 0
u8 SrcGatherEn :1; // Bit 1
u8 DstScatterEn :1; // Bit 2
u8 LlpDstEn :1; // Bit 3
u8 LlpSrcEn :1; // Bit 4
u8 Done :1; // Bit 5
u8 Rsvd6To7 :2; //Bit 6 -7
u16 BlockSize;
}GDMA_CTL_REG, *PGDMA_CTL_REG;
//3 CFG Register Structure
enum _GDMA_CH_PRIORITY_ {
Prior0 = 0,
Prior1 = 1,
Prior2 = 2,
Prior3 = 3,
Prior4 = 4,
Prior5 = 5,
Prior6 = 6,
Prior7 = 7
};
typedef uint32_t GDMA_CH_PRIORITY;
typedef uint32_t *PGDMA_CH_PRIORITY;
enum _GDMA_LOCK_LEVEL_ {
OverComplDmaTransfer = 0x00,
OverComplDmaBlockTransfer = 0x01,
OverComplDmaTransation = 0x02
};
typedef uint32_t GDMA_LOCK_LEVEL;
typedef uint32_t *PGDMA_LOCK_LEVEL;
typedef struct _GDMA_CFG_REG_ {
GDMA_CH_PRIORITY ChPrior;
GDMA_LOCK_LEVEL LockBL;
GDMA_LOCK_LEVEL LockChL;
u16 MaxAbrst;
u8 SrcPer;
u8 DestPer;
u16 ChSusp :1; //Bit 0
u16 FifoEmpty :1; //Bit 1
u16 HsSelDst :1; //Bit 2
u16 HsSelSrc :1; //Bit 3
u16 LockCh :1; //Bit 4
u16 LockB :1; //Bit 5
u16 DstHsPol :1; //Bit 6
u16 SrcHsPol :1; //Bit 7
u16 ReloadSrc :1; //Bit 8
u16 ReloadDst :1; //Bit 9
u16 FifoMode :1; //Bit 10
u16 DsUpdEn :1; //Bit 11
u16 SsUpdEn :1; //Bit 12
u16 Rsvd13To15 :3;
}GDMA_CFG_REG, *PGDMA_CFG_REG;
enum _GDMA_ISR_TYPE_ {
TransferType = 0x1,
BlockType = 0x2,
SrcTransferType = 0x4,
DstTransferType = 0x8,
ErrType = 0x10
};
typedef uint32_t GDMA_ISR_TYPE;
typedef uint32_t *PGDMA_ISR_TYPE;
VOID
HalGdmaOnOffRtl8195a (
IN VOID *Data
);
BOOL
HalGdamChInitRtl8195a(
IN VOID *Data
);
BOOL
HalGdmaChSetingRtl8195a(
IN VOID *Data
);
BOOL
HalGdmaChBlockSetingRtl8195a(
IN VOID *Data
);
BOOL
HalGdmaChBlockSetingRtl8195a_Patch(
IN VOID *Data
);
VOID
HalGdmaChDisRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChEnRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChIsrEnAndDisRtl8195a (
IN VOID *Data
);
u8
HalGdmaChIsrCleanRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChCleanAutoSrcRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChCleanAutoDstRtl8195a (
IN VOID *Data
);
u32
HalGdmaQueryDArRtl8195a(
IN VOID *Data
);
u32
HalGdmaQuerySArRtl8195a(
IN VOID *Data
);
BOOL
HalGdmaQueryChEnRtl8195a (
IN VOID *Data
);
#ifdef CONFIG_CHIP_E_CUT
_LONG_CALL_ BOOL
HalGdmaChBlockSetingRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ u32
HalGdmaQueryDArRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ u32
HalGdmaQuerySArRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ BOOL
HalGdmaQueryChEnRtl8195a_V04 (
IN VOID *Data
);
#endif // #ifdef CONFIG_CHIP_E_CUT
#endif

341
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_gpio.h Normal file
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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
#ifndef _RTL8195A_GPIO_H_
#define _RTL8195A_GPIO_H_
#include "hal_api.h"
#include "hal_gpio.h"
#define GPIO_PORTA_DR 0x00 // data register
#define GPIO_PORTA_DDR 0x04 // data direction
#define GPIO_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software
#define GPIO_PORTB_DR 0x0c // data register
#define GPIO_PORTB_DDR 0x10 // data direction
#define GPIO_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software
#define GPIO_PORTC_DR 0x18 // data register
#define GPIO_PORTC_DDR 0x1c // data direction
#define GPIO_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software
//1 Only the PORTA can be configured to generate interrupts
#define GPIO_INT_EN 0x30 // Interrupt enable register
#define GPIO_INT_MASK 0x34 // Interrupt mask
#define GPIO_INT_TYPE 0x38 // Interrupt type(level/edge) register
#define GPIO_INT_POLARITY 0x3C // Interrupt polarity(Active low/high) register
#define GPIO_INT_STATUS 0x40 // Interrupt status
#define GPIO_INT_RAWSTATUS 0x44 // Interrupt status without mask
#define GPIO_DEBOUNCE 0x48 // Interrupt signal debounce
#define GPIO_PORTA_EOI 0x4c // Clear interrupt
#define GPIO_EXT_PORTA 0x50 // GPIO IN read or OUT read back
#define GPIO_EXT_PORTB 0x54 // GPIO IN read or OUT read back
#define GPIO_EXT_PORTC 0x58 // GPIO IN read or OUT read back
#define GPIO_INT_SYNC 0x60 // Is level-sensitive interrupt being sync sith PCLK
enum {
HAL_GPIO_HIGHZ = 0,
HAL_GPIO_PULL_LOW = 1,
HAL_GPIO_PULL_HIGH = 2
};
//======================================================
// ROM Function prototype
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
static __inline HAL_Status
GPIO_Lock (
VOID
)
{
HAL_Status Status;
if (_pHAL_Gpio_Adapter->EnterCritical) {
_pHAL_Gpio_Adapter->EnterCritical();
}
if(_pHAL_Gpio_Adapter->Locked) {
Status = HAL_BUSY;
}
else {
_pHAL_Gpio_Adapter->Locked = 1;
Status = HAL_OK;
}
if (_pHAL_Gpio_Adapter->ExitCritical) {
_pHAL_Gpio_Adapter->ExitCritical();
}
return Status;
}
static __inline VOID
GPIO_UnLock (
VOID
)
{
if (_pHAL_Gpio_Adapter->EnterCritical) {
_pHAL_Gpio_Adapter->EnterCritical();
}
_pHAL_Gpio_Adapter->Locked = 0;
if (_pHAL_Gpio_Adapter->ExitCritical) {
_pHAL_Gpio_Adapter->ExitCritical();
}
}
#endif // #ifndef CONFIG_RELEASE_BUILD_LIBRARIES
_LONG_CALL_ extern u32
HAL_GPIO_IrqHandler_8195a(
IN VOID *pData
);
_LONG_CALL_ extern u32
HAL_GPIO_MbedIrqHandler_8195a(
IN VOID *pData
);
_LONG_CALL_ HAL_Status
HAL_GPIO_IntCtrl_8195a(
HAL_GPIO_PIN *GPIO_Pin,
u32 En
);
_LONG_CALL_ HAL_Status
HAL_GPIO_Init_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_DeInit_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_GPIO_PIN_STATE
HAL_GPIO_ReadPin_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_WritePin_8195a(
HAL_GPIO_PIN *GPIO_Pin,
HAL_GPIO_PIN_STATE Pin_State
);
_LONG_CALL_ HAL_Status
HAL_GPIO_RegIrq_8195a(
IN PIRQ_HANDLE pIrqHandle
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UnRegIrq_8195a(
IN PIRQ_HANDLE pIrqHandle
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UserRegIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin,
VOID *IrqHandler,
VOID *IrqData
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UserUnRegIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_MaskIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UnMaskIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_IntDebounce_8195a(
HAL_GPIO_PIN *GPIO_Pin,
u8 Enable
);
_LONG_CALL_ u32
HAL_GPIO_GetIPPinName_8195a(
u32 chip_pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_PullCtrl_8195a(
u32 chip_pin,
u8 pull_type
);
_LONG_CALL_ u32
GPIO_GetChipPinName_8195a(
u32 port,
u32 pin
);
_LONG_CALL_ VOID
GPIO_PullCtrl_8195a(
u32 chip_pin,
u8 pull_type
);
_LONG_CALL_ VOID
GPIO_Int_SetType_8195a(
u8 pin_num,
u8 int_mode
);
_LONG_CALL_ HAL_Status HAL_GPIO_IntCtrl_8195aV02(HAL_GPIO_PIN *GPIO_Pin, u32 En);
_LONG_CALL_ u32 GPIO_Int_Clear_8195aV02(u32 irq_clr);
HAL_Status
HAL_GPIO_ClearISR_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
/********** HAL In-Line Functions **********/
/**
* @brief Reads the specified input port pin.
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval The input port pin current status(High or Low).
*/
static __inline s32
HAL_GPIO_ReadPin(
HAL_GPIO_PIN *GPIO_Pin
)
{
return (s32)HAL_GPIO_ReadPin_8195a(GPIO_Pin);
}
/**
* @brief Write the specified output port pin.
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @param Pin_State: The state going to be set to the assigned GPIO pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_WritePin(
HAL_GPIO_PIN *GPIO_Pin,
u32 Value
)
{
HAL_GPIO_WritePin_8195a(GPIO_Pin, (HAL_GPIO_PIN_STATE)Value);
}
/**
* @brief To register a user interrupt handler for a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @param IrqHandler: The IRQ handler to be assigned to the specified pin
*
* @param IrqData: The pointer will be pass the the IRQ handler
*
* @retval None
*/
static __inline VOID
HAL_GPIO_UserRegIrq(
HAL_GPIO_PIN *GPIO_Pin,
VOID *IrqHandler,
VOID *IrqData
)
{
HAL_GPIO_UserRegIrq_8195a(GPIO_Pin, IrqHandler, IrqData);
}
/**
* @brief To un-register a user interrupt handler for a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_UserUnRegIrq(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_UserUnRegIrq_8195a(GPIO_Pin);
}
/**
* @brief Enable/Disable GPIO interrupt
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization.
*
* @param En: Enable (1) or Disable (0)
*
* @retval HAL_Status
*/
static __inline VOID
HAL_GPIO_IntCtrl(
HAL_GPIO_PIN *GPIO_Pin,
u32 En
)
{
HAL_GPIO_IntCtrl_8195a(GPIO_Pin, En);
}
/**
* @brief Mask the interrupt of a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_MaskIrq(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_MaskIrq_8195a(GPIO_Pin);
}
/**
* @brief UnMask the interrupt of a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_UnMaskIrq(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_ClearISR_8195a(GPIO_Pin);
HAL_GPIO_UnMaskIrq_8195a(GPIO_Pin);
}
#endif // end of "#define _RTL8195A_GPIO_H_"

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_i2c.h Normal file
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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
#ifndef _RTL8195A_I2C_H_
#define _RTL8195A_I2C_H_
#include "hal_api.h"
//================ Register Bit Field ==================
//2 REG_DW_I2C_IC_CON
#define BIT_IC_CON_IC_SLAVE_DISABLE BIT(6)
#define BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE 6
#define BIT_MASK_IC_CON_IC_SLAVE_DISABLE 0x1
#define BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(x) (((x) & BIT_MASK_IC_CON_IC_SLAVE_DISABLE) << BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE)
#define BIT_IC_CON_IC_RESTART_EN BIT(5)
#define BIT_SHIFT_IC_CON_IC_RESTART_EN 5
#define BIT_MASK_IC_CON_IC_RESTART_EN 0x1
#define BIT_CTRL_IC_CON_IC_RESTART_EN(x) (((x) & BIT_MASK_IC_CON_IC_RESTART_EN) << BIT_SHIFT_IC_CON_IC_RESTART_EN)
#define BIT_IC_CON_IC_10BITADDR_MASTER BIT(4)
#define BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER 4
#define BIT_MASK_IC_CON_IC_10BITADDR_MASTER 0x1
#define BIT_CTRL_IC_CON_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER)
#define BIT_IC_CON_IC_10BITADDR_SLAVE BIT(3)
#define BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE 3
#define BIT_MASK_IC_CON_IC_10BITADDR_SLAVE 0x1
#define BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_SLAVE) << BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE)
#define BIT_SHIFT_IC_CON_SPEED 1
#define BIT_MASK_IC_CON_SPEED 0x3
#define BIT_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED)
#define BIT_CTRL_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED)
#define BIT_GET_IC_CON_SPEED(x) (((x) >> BIT_SHIFT_IC_CON_SPEED) & BIT_MASK_IC_CON_SPEED)
#define BIT_IC_CON_MASTER_MODE BIT(0)
#define BIT_SHIFT_IC_CON_MASTER_MODE 0
#define BIT_MASK_IC_CON_MASTER_MODE 0x1
#define BIT_CTRL_IC_CON_MASTER_MODE(x) (((x) & BIT_MASK_IC_CON_MASTER_MODE) << BIT_SHIFT_IC_CON_MASTER_MODE)
//2 REG_DW_I2C_IC_TAR
#define BIT_IC_TAR_IC_10BITADDR_MASTER BIT(12)
#define BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER 12
#define BIT_MASK_IC_TAR_IC_10BITADDR_MASTER 0x1
#define BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_TAR_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER)
#define BIT_IC_TAR_SPECIAL BIT(11)
#define BIT_SHIFT_IC_TAR_SPECIAL 11
#define BIT_MASK_IC_TAR_SPECIAL 0x1
#define BIT_CTRL_IC_TAR_SPECIAL(x) (((x) & BIT_MASK_IC_TAR_SPECIAL) << BIT_SHIFT_IC_TAR_SPECIAL)
#define BIT_IC_TAR_GC_OR_START BIT(10)
#define BIT_SHIFT_IC_TAR_GC_OR_START 10
#define BIT_MASK_IC_TAR_GC_OR_START 0x1
#define BIT_CTRL_IC_TAR_GC_OR_START(x) (((x) & BIT_MASK_IC_TAR_GC_OR_START) << BIT_SHIFT_IC_TAR_GC_OR_START)
#define BIT_SHIFT_IC_TAR 0
#define BIT_MASK_IC_TAR 0x3ff
#define BIT_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR)
#define BIT_CTRL_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR)
#define BIT_GET_IC_TAR(x) (((x) >> BIT_SHIFT_IC_TAR) & BIT_MASK_IC_TAR)
//2 REG_DW_I2C_IC_SAR
#define BIT_SHIFT_IC_SAR 0
#define BIT_MASK_IC_SAR 0x3ff
#define BIT_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR)
#define BIT_CTRL_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR)
#define BIT_GET_IC_SAR(x) (((x) >> BIT_SHIFT_IC_SAR) & BIT_MASK_IC_SAR)
//2 REG_DW_I2C_IC_HS_MADDR
#define BIT_SHIFT_IC_HS_MADDR 0
#define BIT_MASK_IC_HS_MADDR 0x7
#define BIT_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR)
#define BIT_CTRL_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR)
#define BIT_GET_IC_HS_MADDR(x) (((x) >> BIT_SHIFT_IC_HS_MADDR) & BIT_MASK_IC_HS_MADDR)
//2 REG_DW_I2C_IC_DATA_CMD
#define BIT_IC_DATA_CMD_RESTART BIT(10)
#define BIT_SHIFT_IC_DATA_CMD_RESTART 10
#define BIT_MASK_IC_DATA_CMD_RESTART 0x1
#define BIT_CTRL_IC_DATA_CMD_RESTART(x) (((x) & BIT_MASK_IC_DATA_CMD_RESTART) << BIT_SHIFT_IC_DATA_CMD_RESTART)
#define BIT_IC_DATA_CMD_STOP BIT(9)
#define BIT_SHIFT_IC_DATA_CMD_STOP 9
#define BIT_MASK_IC_DATA_CMD_STOP 0x1
#define BIT_CTRL_IC_DATA_CMD_STOP(x) (((x) & BIT_MASK_IC_DATA_CMD_STOP) << BIT_SHIFT_IC_DATA_CMD_STOP)
#define BIT_IC_DATA_CMD_CMD BIT(8)
#define BIT_SHIFT_IC_DATA_CMD_CMD 8
#define BIT_MASK_IC_DATA_CMD_CMD 0x1
#define BIT_CTRL_IC_DATA_CMD_CMD(x) (((x) & BIT_MASK_IC_DATA_CMD_CMD) << BIT_SHIFT_IC_DATA_CMD_CMD)
#define BIT_SHIFT_IC_DATA_CMD_DAT 0
#define BIT_MASK_IC_DATA_CMD_DAT 0xff
#define BIT_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT)
#define BIT_CTRL_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT)
#define BIT_GET_IC_DATA_CMD_DAT(x) (((x) >> BIT_SHIFT_IC_DATA_CMD_DAT) & BIT_MASK_IC_DATA_CMD_DAT)
//2 REG_DW_I2C_IC_SS_SCL_HCNT
#define BIT_SHIFT_IC_SS_SCL_HCNT 0
#define BIT_MASK_IC_SS_SCL_HCNT 0xffff
#define BIT_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT)
#define BIT_CTRL_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT)
#define BIT_GET_IC_SS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_HCNT) & BIT_MASK_IC_SS_SCL_HCNT)
//2 REG_DW_I2C_IC_SS_SCL_LCNT
#define BIT_SHIFT_IC_SS_SCL_LCNT 0
#define BIT_MASK_IC_SS_SCL_LCNT 0xffff
#define BIT_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT)
#define BIT_CTRL_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT)
#define BIT_GET_IC_SS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_LCNT) & BIT_MASK_IC_SS_SCL_LCNT)
//2 REG_DW_I2C_IC_FS_SCL_HCNT
#define BIT_SHIFT_IC_FS_SCL_HCNT 0
#define BIT_MASK_IC_FS_SCL_HCNT 0xffff
#define BIT_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT)
#define BIT_CTRL_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT)
#define BIT_GET_IC_FS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_HCNT) & BIT_MASK_IC_FS_SCL_HCNT)
//2 REG_DW_I2C_IC_FS_SCL_LCNT
#define BIT_SHIFT_IC_FS_SCL_LCNT 0
#define BIT_MASK_IC_FS_SCL_LCNT 0xffff
#define BIT_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT)
#define BIT_CTRL_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT)
#define BIT_GET_IC_FS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_LCNT) & BIT_MASK_IC_FS_SCL_LCNT)
//2 REG_DW_I2C_IC_HS_SCL_HCNT
#define BIT_SHIFT_IC_HS_SCL_HCNT 0
#define BIT_MASK_IC_HS_SCL_HCNT 0xffff
#define BIT_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT)
#define BIT_CTRL_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT)
#define BIT_GET_IC_HS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_HCNT) & BIT_MASK_IC_HS_SCL_HCNT)
//2 REG_DW_I2C_IC_HS_SCL_LCNT
#define BIT_SHIFT_IC_HS_SCL_LCNT 0
#define BIT_MASK_IC_HS_SCL_LCNT 0xffff
#define BIT_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT)
#define BIT_CTRL_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT)
#define BIT_GET_IC_HS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_LCNT) & BIT_MASK_IC_HS_SCL_LCNT)
//2 REG_DW_I2C_IC_INTR_STAT
#define BIT_IC_INTR_STAT_R_GEN_CALL BIT(11)
#define BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL 11
#define BIT_MASK_IC_INTR_STAT_R_GEN_CALL 0x1
#define BIT_CTRL_IC_INTR_STAT_R_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_GEN_CALL) << BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL)
#define BIT_IC_INTR_STAT_R_START_DET BIT(10)
#define BIT_SHIFT_IC_INTR_STAT_R_START_DET 10
#define BIT_MASK_IC_INTR_STAT_R_START_DET 0x1
#define BIT_CTRL_IC_INTR_STAT_R_START_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_START_DET) << BIT_SHIFT_IC_INTR_STAT_R_START_DET)
#define BIT_IC_INTR_STAT_R_STOP_DET BIT(9)
#define BIT_SHIFT_IC_INTR_STAT_R_STOP_DET 9
#define BIT_MASK_IC_INTR_STAT_R_STOP_DET 0x1
#define BIT_CTRL_IC_INTR_STAT_R_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_STOP_DET) << BIT_SHIFT_IC_INTR_STAT_R_STOP_DET)
#define BIT_IC_INTR_STAT_R_ACTIVITY BIT(8)
#define BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY 8
#define BIT_MASK_IC_INTR_STAT_R_ACTIVITY 0x1
#define BIT_CTRL_IC_INTR_STAT_R_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_ACTIVITY) << BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY)
#define BIT_IC_INTR_STAT_R_RX_DONE BIT(7)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_DONE 7
#define BIT_MASK_IC_INTR_STAT_R_RX_DONE 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_DONE) << BIT_SHIFT_IC_INTR_STAT_R_RX_DONE)
#define BIT_IC_INTR_STAT_R_TX_ABRT BIT(6)
#define BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT 6
#define BIT_MASK_IC_INTR_STAT_R_TX_ABRT 0x1
#define BIT_CTRL_IC_INTR_STAT_R_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_ABRT) << BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT)
#define BIT_IC_INTR_STAT_R_RD_REQ BIT(5)
#define BIT_SHIFT_IC_INTR_STAT_R_RD_REQ 5
#define BIT_MASK_IC_INTR_STAT_R_RD_REQ 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RD_REQ) << BIT_SHIFT_IC_INTR_STAT_R_RD_REQ)
#define BIT_IC_INTR_STAT_R_TX_EMPTY BIT(4)
#define BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY 4
#define BIT_MASK_IC_INTR_STAT_R_TX_EMPTY 0x1
#define BIT_CTRL_IC_INTR_STAT_R_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_EMPTY) << BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY)
#define BIT_IC_INTR_STAT_R_TX_OVER BIT(3)
#define BIT_SHIFT_IC_INTR_STAT_R_TX_OVER 3
#define BIT_MASK_IC_INTR_STAT_R_TX_OVER 0x1
#define BIT_CTRL_IC_INTR_STAT_R_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_TX_OVER)
#define BIT_IC_INTR_STAT_R_RX_FULL BIT(2)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_FULL 2
#define BIT_MASK_IC_INTR_STAT_R_RX_FULL 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_FULL) << BIT_SHIFT_IC_INTR_STAT_R_RX_FULL)
#define BIT_IC_INTR_STAT_R_RX_OVER BIT(1)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_OVER 1
#define BIT_MASK_IC_INTR_STAT_R_RX_OVER 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_RX_OVER)
#define BIT_IC_INTR_STAT_R_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER 0
#define BIT_MASK_IC_INTR_STAT_R_RX_UNDER 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_UNDER) << BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER)
//2 REG_DW_I2C_IC_INTR_MASK
#define BIT_IC_INTR_MASK_M_GEN_CALL BIT(11)
#define BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL 11
#define BIT_MASK_IC_INTR_MASK_M_GEN_CALL 0x1
#define BIT_CTRL_IC_INTR_MASK_M_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_GEN_CALL) << BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL)
#define BIT_IC_INTR_MASK_M_START_DET BIT(10)
#define BIT_SHIFT_IC_INTR_MASK_M_START_DET 10
#define BIT_MASK_IC_INTR_MASK_M_START_DET 0x1
#define BIT_CTRL_IC_INTR_MASK_M_START_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_START_DET) << BIT_SHIFT_IC_INTR_MASK_M_START_DET)
#define BIT_IC_INTR_MASK_M_STOP_DET BIT(9)
#define BIT_SHIFT_IC_INTR_MASK_M_STOP_DET 9
#define BIT_MASK_IC_INTR_MASK_M_STOP_DET 0x1
#define BIT_CTRL_IC_INTR_MASK_M_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_STOP_DET) << BIT_SHIFT_IC_INTR_MASK_M_STOP_DET)
#define BIT_IC_INTR_MASK_M_ACTIVITY BIT(8)
#define BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY 8
#define BIT_MASK_IC_INTR_MASK_M_ACTIVITY 0x1
#define BIT_CTRL_IC_INTR_MASK_M_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_ACTIVITY) << BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY)
#define BIT_IC_INTR_MASK_M_RX_DONE BIT(7)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_DONE 7
#define BIT_MASK_IC_INTR_MASK_M_RX_DONE 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_DONE) << BIT_SHIFT_IC_INTR_MASK_M_RX_DONE)
#define BIT_IC_INTR_MASK_M_TX_ABRT BIT(6)
#define BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT 6
#define BIT_MASK_IC_INTR_MASK_M_TX_ABRT 0x1
#define BIT_CTRL_IC_INTR_MASK_M_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_ABRT) << BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT)
#define BIT_IC_INTR_MASK_M_RD_REQ BIT(5)
#define BIT_SHIFT_IC_INTR_MASK_M_RD_REQ 5
#define BIT_MASK_IC_INTR_MASK_M_RD_REQ 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RD_REQ) << BIT_SHIFT_IC_INTR_MASK_M_RD_REQ)
#define BIT_IC_INTR_MASK_M_TX_EMPTY BIT(4)
#define BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY 4
#define BIT_MASK_IC_INTR_MASK_M_TX_EMPTY 0x1
#define BIT_CTRL_IC_INTR_MASK_M_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_EMPTY) << BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY)
#define BIT_IC_INTR_MASK_M_TX_OVER BIT(3)
#define BIT_SHIFT_IC_INTR_MASK_M_TX_OVER 3
#define BIT_MASK_IC_INTR_MASK_M_TX_OVER 0x1
#define BIT_CTRL_IC_INTR_MASK_M_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_TX_OVER)
#define BIT_IC_INTR_MASK_M_RX_FULL BIT(2)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_FULL 2
#define BIT_MASK_IC_INTR_MASK_M_RX_FULL 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_FULL) << BIT_SHIFT_IC_INTR_MASK_M_RX_FULL)
#define BIT_IC_INTR_MASK_M_RX_OVER BIT(1)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_OVER 1
#define BIT_MASK_IC_INTR_MASK_M_RX_OVER 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_RX_OVER)
#define BIT_IC_INTR_MASK_M_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER 0
#define BIT_MASK_IC_INTR_MASK_M_RX_UNDER 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_UNDER) << BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER)
//2 REG_DW_I2C_IC_RAW_INTR_STAT
#define BIT_IC_RAW_INTR_STAT_GEN_CALL BIT(11)
#define BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL 11
#define BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_GEN_CALL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL) << BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL)
#define BIT_IC_RAW_INTR_STAT_START_DET BIT(10)
#define BIT_SHIFT_IC_RAW_INTR_STAT_START_DET 10
#define BIT_MASK_IC_RAW_INTR_STAT_START_DET 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_START_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_START_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_START_DET)
#define BIT_IC_RAW_INTR_STAT_STOP_DET BIT(9)
#define BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET 9
#define BIT_MASK_IC_RAW_INTR_STAT_STOP_DET 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_STOP_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_STOP_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET)
#define BIT_IC_RAW_INTR_STAT_ACTIVITY BIT(8)
#define BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY 8
#define BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_ACTIVITY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY) << BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY)
#define BIT_IC_RAW_INTR_STAT_RX_DONE BIT(7)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE 7
#define BIT_MASK_IC_RAW_INTR_STAT_RX_DONE 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_DONE(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_DONE) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE)
#define BIT_IC_RAW_INTR_STAT_TX_ABRT BIT(6)
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT 6
#define BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_ABRT(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT)
#define BIT_IC_RAW_INTR_STAT_RD_REQ BIT(5)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ 5
#define BIT_MASK_IC_RAW_INTR_STAT_RD_REQ 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RD_REQ(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RD_REQ) << BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ)
#define BIT_IC_RAW_INTR_STAT_TX_EMPTY BIT(4)
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY 4
#define BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_EMPTY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY)
#define BIT_IC_RAW_INTR_STAT_TX_OVER BIT(3)
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER 3
#define BIT_MASK_IC_RAW_INTR_STAT_TX_OVER 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER)
#define BIT_IC_RAW_INTR_STAT_RX_FULL BIT(2)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL 2
#define BIT_MASK_IC_RAW_INTR_STAT_RX_FULL 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_FULL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_FULL) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL)
#define BIT_IC_RAW_INTR_STAT_RX_OVER BIT(1)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER 1
#define BIT_MASK_IC_RAW_INTR_STAT_RX_OVER 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER)
#define BIT_IC_RAW_INTR_STAT_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER 0
#define BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_UNDER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER)
//2 REG_DW_I2C_IC_RX_TL
#define BIT_SHIFT_IC_RX_TL 0
#define BIT_MASK_IC_RX_TL 0xff
#define BIT_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL)
#define BIT_CTRL_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL)
#define BIT_GET_IC_RX_TL(x) (((x) >> BIT_SHIFT_IC_RX_TL) & BIT_MASK_IC_RX_TL)
//2 REG_DW_I2C_IC_TX_TL
#define BIT_SHIFT_IC_TX_TL 0
#define BIT_MASK_IC_TX_TL 0xff
#define BIT_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL)
#define BIT_CTRL_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL)
#define BIT_GET_IC_TX_TL(x) (((x) >> BIT_SHIFT_IC_TX_TL) & BIT_MASK_IC_TX_TL)
//2 REG_DW_I2C_IC_CLR_INTR
#define BIT_IC_CLR_INTR BIT(0)
#define BIT_SHIFT_IC_CLR_INTR 0
#define BIT_MASK_IC_CLR_INTR 0x1
#define BIT_CTRL_IC_CLR_INTR(x) (((x) & BIT_MASK_IC_CLR_INTR) << BIT_SHIFT_IC_CLR_INTR)
//2 REG_DW_I2C_IC_CLR_RX_UNDER
#define BIT_IC_CLR_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_CLR_RX_UNDER 0
#define BIT_MASK_IC_CLR_RX_UNDER 0x1
#define BIT_CTRL_IC_CLR_RX_UNDER(x) (((x) & BIT_MASK_IC_CLR_RX_UNDER) << BIT_SHIFT_IC_CLR_RX_UNDER)
//2 REG_DW_I2C_IC_CLR_RX_OVER
#define BIT_IC_CLR_RX_OVER BIT(0)
#define BIT_SHIFT_IC_CLR_RX_OVER 0
#define BIT_MASK_IC_CLR_RX_OVER 0x1
#define BIT_CTRL_IC_CLR_RX_OVER(x) (((x) & BIT_MASK_IC_CLR_RX_OVER) << BIT_SHIFT_IC_CLR_RX_OVER)
//2 REG_DW_I2C_IC_CLR_TX_OVER
#define BIT_IC_CLR_TX_OVER BIT(0)
#define BIT_SHIFT_IC_CLR_TX_OVER 0
#define BIT_MASK_IC_CLR_TX_OVER 0x1
#define BIT_CTRL_IC_CLR_TX_OVER(x) (((x) & BIT_MASK_IC_CLR_TX_OVER) << BIT_SHIFT_IC_CLR_TX_OVER)
//2 REG_DW_I2C_IC_CLR_RD_REQ
#define BIT_IC_CLR_RD_REQ BIT(0)
#define BIT_SHIFT_IC_CLR_RD_REQ 0
#define BIT_MASK_IC_CLR_RD_REQ 0x1
#define BIT_CTRL_IC_CLR_RD_REQ(x) (((x) & BIT_MASK_IC_CLR_RD_REQ) << BIT_SHIFT_IC_CLR_RD_REQ)
//2 REG_DW_I2C_IC_CLR_TX_ABRT
#define BIT_CLR_RD_REQ BIT(0)
#define BIT_SHIFT_CLR_RD_REQ 0
#define BIT_MASK_CLR_RD_REQ 0x1
#define BIT_CTRL_CLR_RD_REQ(x) (((x) & BIT_MASK_CLR_RD_REQ) << BIT_SHIFT_CLR_RD_REQ)
//2 REG_DW_I2C_IC_CLR_RX_DONE
#define BIT_IC_CLR_RX_DONE BIT(0)
#define BIT_SHIFT_IC_CLR_RX_DONE 0
#define BIT_MASK_IC_CLR_RX_DONE 0x1
#define BIT_CTRL_IC_CLR_RX_DONE(x) (((x) & BIT_MASK_IC_CLR_RX_DONE) << BIT_SHIFT_IC_CLR_RX_DONE)
//2 REG_DW_I2C_IC_CLR_ACTIVITY
#define BIT_IC_CLR_ACTIVITY BIT(0)
#define BIT_SHIFT_IC_CLR_ACTIVITY 0
#define BIT_MASK_IC_CLR_ACTIVITY 0x1
#define BIT_CTRL_IC_CLR_ACTIVITY(x) (((x) & BIT_MASK_IC_CLR_ACTIVITY) << BIT_SHIFT_IC_CLR_ACTIVITY)
//2 REG_DW_I2C_IC_CLR_STOP_DET
#define BIT_IC_CLR_STOP_DET BIT(0)
#define BIT_SHIFT_IC_CLR_STOP_DET 0
#define BIT_MASK_IC_CLR_STOP_DET 0x1
#define BIT_CTRL_IC_CLR_STOP_DET(x) (((x) & BIT_MASK_IC_CLR_STOP_DET) << BIT_SHIFT_IC_CLR_STOP_DET)
//2 REG_DW_I2C_IC_CLR_START_DET
#define BIT_IC_CLR_START_DET BIT(0)
#define BIT_SHIFT_IC_CLR_START_DET 0
#define BIT_MASK_IC_CLR_START_DET 0x1
#define BIT_CTRL_IC_CLR_START_DET(x) (((x) & BIT_MASK_IC_CLR_START_DET) << BIT_SHIFT_IC_CLR_START_DET)
//2 REG_DW_I2C_IC_CLR_GEN_CALL
#define BIT_IC_CLR_GEN_CALL BIT(0)
#define BIT_SHIFT_IC_CLR_GEN_CALL 0
#define BIT_MASK_IC_CLR_GEN_CALL 0x1
#define BIT_CTRL_IC_CLR_GEN_CALL(x) (((x) & BIT_MASK_IC_CLR_GEN_CALL) << BIT_SHIFT_IC_CLR_GEN_CALL)
//2 REG_DW_I2C_IC_ENABLE
#define BIT_IC_ENABLE BIT(0)
#define BIT_SHIFT_IC_ENABLE 0
#define BIT_MASK_IC_ENABLE 0x1
#define BIT_CTRL_IC_ENABLE(x) (((x) & BIT_MASK_IC_ENABLE) << BIT_SHIFT_IC_ENABLE)
//2 REG_DW_I2C_IC_STATUS
#define BIT_IC_STATUS_SLV_ACTIVITY BIT(6)
#define BIT_SHIFT_IC_STATUS_SLV_ACTIVITY 6
#define BIT_MASK_IC_STATUS_SLV_ACTIVITY 0x1
#define BIT_CTRL_IC_STATUS_SLV_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_SLV_ACTIVITY) << BIT_SHIFT_IC_STATUS_SLV_ACTIVITY)
#define BIT_IC_STATUS_MST_ACTIVITY BIT(5)
#define BIT_SHIFT_IC_STATUS_MST_ACTIVITY 5
#define BIT_MASK_IC_STATUS_MST_ACTIVITY 0x1
#define BIT_CTRL_IC_STATUS_MST_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_MST_ACTIVITY) << BIT_SHIFT_IC_STATUS_MST_ACTIVITY)
#define BIT_IC_STATUS_RFF BIT(4)
#define BIT_SHIFT_IC_STATUS_RFF 4
#define BIT_MASK_IC_STATUS_RFF 0x1
#define BIT_CTRL_IC_STATUS_RFF(x) (((x) & BIT_MASK_IC_STATUS_RFF) << BIT_SHIFT_IC_STATUS_RFF)
#define BIT_IC_STATUS_RFNE BIT(3)
#define BIT_SHIFT_IC_STATUS_RFNE 3
#define BIT_MASK_IC_STATUS_RFNE 0x1
#define BIT_CTRL_IC_STATUS_RFNE(x) (((x) & BIT_MASK_IC_STATUS_RFNE) << BIT_SHIFT_IC_STATUS_RFNE)
#define BIT_IC_STATUS_TFE BIT(2)
#define BIT_SHIFT_IC_STATUS_TFE 2
#define BIT_MASK_IC_STATUS_TFE 0x1
#define BIT_CTRL_IC_STATUS_TFE(x) (((x) & BIT_MASK_IC_STATUS_TFE) << BIT_SHIFT_IC_STATUS_TFE)
#define BIT_IC_STATUS_TFNF BIT(1)
#define BIT_SHIFT_IC_STATUS_TFNF 1
#define BIT_MASK_IC_STATUS_TFNF 0x1
#define BIT_CTRL_IC_STATUS_TFNF(x) (((x) & BIT_MASK_IC_STATUS_TFNF) << BIT_SHIFT_IC_STATUS_TFNF)
#define BIT_IC_STATUS_ACTIVITY BIT(0)
#define BIT_SHIFT_IC_STATUS_ACTIVITY 0
#define BIT_MASK_IC_STATUS_ACTIVITY 0x1
#define BIT_CTRL_IC_STATUS_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_ACTIVITY) << BIT_SHIFT_IC_STATUS_ACTIVITY)
//2 REG_DW_I2C_IC_TXFLR
#define BIT_SHIFT_IC_TXFLR 0
#define BIT_MASK_IC_TXFLR 0x3f
#define BIT_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR)
#define BIT_CTRL_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR)
#define BIT_GET_IC_TXFLR(x) (((x) >> BIT_SHIFT_IC_TXFLR) & BIT_MASK_IC_TXFLR)
//2 REG_DW_I2C_IC_RXFLR
#define BIT_SHIFT_IC_RXFLR 0
#define BIT_MASK_IC_RXFLR 0x1f
#define BIT_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR)
#define BIT_CTRL_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR)
#define BIT_GET_IC_RXFLR(x) (((x) >> BIT_SHIFT_IC_RXFLR) & BIT_MASK_IC_RXFLR)
//2 REG_DW_I2C_IC_SDA_HOLD
#define BIT_SHIFT_IC_SDA_HOLD 0
#define BIT_MASK_IC_SDA_HOLD 0xffff
#define BIT_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD)
#define BIT_CTRL_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD)
#define BIT_GET_IC_SDA_HOLD(x) (((x) >> BIT_SHIFT_IC_SDA_HOLD) & BIT_MASK_IC_SDA_HOLD)
//2 REG_DW_I2C_IC_TX_ABRT_SOURCE
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX BIT(15)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 15
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST BIT(14)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 14
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO BIT(13)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 13
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO)
#define BIT_IC_TX_ABRT_SOURCE_ARB_LOST BIT(12)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST 12
#define BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ARB_LOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS BIT(11)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 11
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT BIT(10)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 10
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT BIT(9)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 9
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT BIT(8)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 8
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET BIT(7)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 7
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET BIT(6)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 6
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ BIT(5)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 5
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK BIT(4)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 4
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK BIT(3)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 3
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK BIT(2)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 2
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK BIT(1)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 1
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK BIT(0)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK)
//2 REG_DW_I2C_IC_SLV_DATA_NACK_ONLY
#define BIT_IC_SLV_DATA_NACK_ONLY BIT(0)
#define BIT_SHIFT_IC_SLV_DATA_NACK_ONLY 0
#define BIT_MASK_IC_SLV_DATA_NACK_ONLY 0x1
#define BIT_CTRL_IC_SLV_DATA_NACK_ONLY(x) (((x) & BIT_MASK_IC_SLV_DATA_NACK_ONLY) << BIT_SHIFT_IC_SLV_DATA_NACK_ONLY)
//2 REG_DW_I2C_IC_DMA_CR
#define BIT_IC_DMA_CR_TDMAE BIT(1)
#define BIT_SHIFT_IC_DMA_CR_TDMAE 1
#define BIT_MASK_IC_DMA_CR_TDMAE 0x1
#define BIT_CTRL_IC_DMA_CR_TDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_TDMAE) << BIT_SHIFT_IC_DMA_CR_TDMAE)
#define BIT_IC_DMA_CR_RDMAE BIT(0)
#define BIT_SHIFT_IC_DMA_CR_RDMAE 0
#define BIT_MASK_IC_DMA_CR_RDMAE 0x1
#define BIT_CTRL_IC_DMA_CR_RDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_RDMAE) << BIT_SHIFT_IC_DMA_CR_RDMAE)
//2 REG_DW_I2C_IC_DMA_TDLR
#define BIT_SHIFT_IC_DMA_TDLR_DMATDL 0
#define BIT_MASK_IC_DMA_TDLR_DMATDL 0x1f
#define BIT_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL)
#define BIT_CTRL_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL)
#define BIT_GET_IC_DMA_TDLR_DMATDL(x) (((x) >> BIT_SHIFT_IC_DMA_TDLR_DMATDL) & BIT_MASK_IC_DMA_TDLR_DMATDL)
//2 REG_DW_I2C_IC_DMA_RDLR
#define BIT_SHIFT_IC_DMA_RDLR_DMARDL 0
#define BIT_MASK_IC_DMA_RDLR_DMARDL 0xf
#define BIT_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL)
#define BIT_CTRL_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL)
#define BIT_GET_IC_DMA_RDLR_DMARDL(x) (((x) >> BIT_SHIFT_IC_DMA_RDLR_DMARDL) & BIT_MASK_IC_DMA_RDLR_DMARDL)
//2 REG_DW_I2C_IC_SDA_SETUP
#define BIT_SHIFT_IC_SDA_SETUP 0
#define BIT_MASK_IC_SDA_SETUP 0xff
#define BIT_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP)
#define BIT_CTRL_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP)
#define BIT_GET_IC_SDA_SETUP(x) (((x) >> BIT_SHIFT_IC_SDA_SETUP) & BIT_MASK_IC_SDA_SETUP)
//2 REG_DW_I2C_IC_ACK_GENERAL_CALL
#define BIT_IC_ACK_GENERAL_CALL BIT(0)
#define BIT_SHIFT_IC_ACK_GENERAL_CALL 0
#define BIT_MASK_IC_ACK_GENERAL_CALL 0x1
#define BIT_CTRL_IC_ACK_GENERAL_CALL(x) (((x) & BIT_MASK_IC_ACK_GENERAL_CALL) << BIT_SHIFT_IC_ACK_GENERAL_CALL)
//2 REG_DW_I2C_IC_ENABLE_STATUS
#define BIT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST BIT(2)
#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 2
#define BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 0x1
#define BIT_CTRL_IC_ENABLE_STATUS_SLV_RX_DATA_LOST(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST)
#define BIT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY BIT(1)
#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 1
#define BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 0x1
#define BIT_CTRL_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY)
#define BIT_IC_ENABLE_STATUS_IC_EN BIT(0)
#define BIT_SHIFT_IC_ENABLE_STATUS_IC_EN 0
#define BIT_MASK_IC_ENABLE_STATUS_IC_EN 0x1
#define BIT_CTRL_IC_ENABLE_STATUS_IC_EN(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_IC_EN) << BIT_SHIFT_IC_ENABLE_STATUS_IC_EN)
//2 REG_DW_I2C_IC_COMP_PARAM_1
#define BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 16
#define BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 0xff
#define BIT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
#define BIT_CTRL_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
#define BIT_GET_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
#define BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 8
#define BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 0xff
#define BIT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
#define BIT_CTRL_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
#define BIT_GET_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
#define BIT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS BIT(7)
#define BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 7
#define BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS) << BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS)
#define BIT_IC_COMP_PARAM_1_HAS_DMA BIT(6)
#define BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA 6
#define BIT_MASK_IC_COMP_PARAM_1_HAS_DMA 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_HAS_DMA(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HAS_DMA) << BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA)
#define BIT_IC_COMP_PARAM_1_INTR_IO BIT(5)
#define BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO 5
#define BIT_MASK_IC_COMP_PARAM_1_INTR_IO 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_INTR_IO(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_INTR_IO) << BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO)
#define BIT_IC_COMP_PARAM_1_HC_COUNT_VALUES BIT(4)
#define BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES 4
#define BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_HC_COUNT_VALUES(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES) << BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES)
#define BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE 2
#define BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE 0x3
#define BIT_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE)
#define BIT_CTRL_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE)
#define BIT_GET_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE)
#define BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH 0
#define BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH 0x3
#define BIT_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH)
#define BIT_CTRL_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH)
#define BIT_GET_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH)
//2 REG_DW_I2C_IC_COMP_VERSION
#define BIT_SHIFT_IC_COMP_VERSION 0
#define BIT_MASK_IC_COMP_VERSION 0xffffffffL
#define BIT_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION)
#define BIT_CTRL_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION)
#define BIT_GET_IC_COMP_VERSION(x) (((x) >> BIT_SHIFT_IC_COMP_VERSION) & BIT_MASK_IC_COMP_VERSION)
//2 REG_DW_I2C_IC_COMP_TYPE
#define BIT_SHIFT_IC_COMP_TYPE 0
#define BIT_MASK_IC_COMP_TYPE 0xffffffffL
#define BIT_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE)
#define BIT_CTRL_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE)
#define BIT_GET_IC_COMP_TYPE(x) (((x) >> BIT_SHIFT_IC_COMP_TYPE) & BIT_MASK_IC_COMP_TYPE)
//======================== Register Address Definition ========================
#define REG_DW_I2C_IC_CON 0x0000
#define REG_DW_I2C_IC_TAR 0x0004
#define REG_DW_I2C_IC_SAR 0x0008
#define REG_DW_I2C_IC_HS_MADDR 0x000C
#define REG_DW_I2C_IC_DATA_CMD 0x0010
#define REG_DW_I2C_IC_SS_SCL_HCNT 0x0014
#define REG_DW_I2C_IC_SS_SCL_LCNT 0x0018
#define REG_DW_I2C_IC_FS_SCL_HCNT 0x001C
#define REG_DW_I2C_IC_FS_SCL_LCNT 0x0020
#define REG_DW_I2C_IC_HS_SCL_HCNT 0x0024
#define REG_DW_I2C_IC_HS_SCL_LCNT 0x0028
#define REG_DW_I2C_IC_INTR_STAT 0x002C
#define REG_DW_I2C_IC_INTR_MASK 0x0030
#define REG_DW_I2C_IC_RAW_INTR_STAT 0x0034
#define REG_DW_I2C_IC_RX_TL 0x0038
#define REG_DW_I2C_IC_TX_TL 0x003C
#define REG_DW_I2C_IC_CLR_INTR 0x0040
#define REG_DW_I2C_IC_CLR_RX_UNDER 0x0044
#define REG_DW_I2C_IC_CLR_RX_OVER 0x0048
#define REG_DW_I2C_IC_CLR_TX_OVER 0x004C
#define REG_DW_I2C_IC_CLR_RD_REQ 0x0050
#define REG_DW_I2C_IC_CLR_TX_ABRT 0x0054
#define REG_DW_I2C_IC_CLR_RX_DONE 0x0058
#define REG_DW_I2C_IC_CLR_ACTIVITY 0x005C
#define REG_DW_I2C_IC_CLR_STOP_DET 0x0060
#define REG_DW_I2C_IC_CLR_START_DET 0x0064
#define REG_DW_I2C_IC_CLR_GEN_CALL 0x0068
#define REG_DW_I2C_IC_ENABLE 0x006C
#define REG_DW_I2C_IC_STATUS 0x0070
#define REG_DW_I2C_IC_TXFLR 0x0074
#define REG_DW_I2C_IC_RXFLR 0x0078
#define REG_DW_I2C_IC_SDA_HOLD 0x007C
#define REG_DW_I2C_IC_TX_ABRT_SOURCE 0x0080
#define REG_DW_I2C_IC_SLV_DATA_NACK_ONLY 0x0084
#define REG_DW_I2C_IC_DMA_CR 0x0088
#define REG_DW_I2C_IC_DMA_TDLR 0x008C
#define REG_DW_I2C_IC_DMA_RDLR 0x0090
#define REG_DW_I2C_IC_SDA_SETUP 0x0094
#define REG_DW_I2C_IC_ACK_GENERAL_CALL 0x0098
#define REG_DW_I2C_IC_ENABLE_STATUS 0x009C
#define REG_DW_I2C_IC_COMP_PARAM_1 0x00F4
#define REG_DW_I2C_IC_COMP_VERSION 0x00F8
#define REG_DW_I2C_IC_COMP_TYPE 0x00FC
//======================================================
// I2C related enumeration
// I2C Address Mode
enum _I2C_ADDR_MODE_ {
I2C_ADDR_7BIT = 0,
I2C_ADDR_10BIT = 1,
};
typedef uint32_t I2C_ADDR_MODE;
typedef uint32_t *PI2C_ADDR_MODE;
// I2C Speed Mode
enum _I2C_SPD_MODE_ {
I2C_SS_MODE = 1,
I2C_FS_MODE = 2,
I2C_HS_MODE = 3,
};
typedef uint32_t I2C_SPD_MODE;
typedef uint32_t *PI2C_SPD_MODE;
//I2C Timing Parameters
#define I2C_SS_MIN_SCL_HTIME 4000 //the unit is ns.
#define I2C_SS_MIN_SCL_LTIME 4700 //the unit is ns.
#define I2C_FS_MIN_SCL_HTIME 600 //the unit is ns.
#define I2C_FS_MIN_SCL_LTIME 1300 //the unit is ns.
#define I2C_HS_MIN_SCL_HTIME_100 60 //the unit is ns, with bus loading = 100pf
#define I2C_HS_MIN_SCL_LTIME_100 120 //the unit is ns., with bus loading = 100pf
#define I2C_HS_MIN_SCL_HTIME_400 160 //the unit is ns, with bus loading = 400pf
#define I2C_HS_MIN_SCL_LTIME_400 320 //the unit is ns., with bus loading = 400pf
//======================================================
//I2C Essential functions and macros
_LONG_CALL_ROM_ VOID HalI2CWrite32(IN u8 I2CIdx, IN u8 I2CReg, IN u32 I2CVal);
_LONG_CALL_ROM_ u32 HalI2CRead32(IN u8 I2CIdx, IN u8 I2CReg);
#define HAL_I2C_WRITE32(I2CIdx, addr, value) HalI2CWrite32(I2CIdx,addr,value)
#define HAL_I2C_READ32(I2CIdx, addr) HalI2CRead32(I2CIdx,addr)
// Rtl8195a I2C function prototypes
_LONG_CALL_ HAL_Status HalI2CEnableRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CInit8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CDeInit8195a(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CMassSendRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CSendRtl8195a(IN VOID *Data);
_LONG_CALL_ u8 HalI2CReceiveRtl8195a(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status HalI2CIntrCtrl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CClrIntrRtl8195a(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status HalI2CClrAllIntrRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CDMACtrl8195a(IN VOID *Data);
_LONG_CALL_ u32 HalI2CReadRegRtl8195a(IN VOID *Data, IN u8 I2CReg);
_LONG_CALL_ HAL_Status HalI2CWriteRegRtl8195a(IN VOID *Data, IN u8 I2CReg, IN u32 RegVal);
//Rtl8195a I2C V02 function prototype
_LONG_CALL_ HAL_Status HalI2CSendRtl8195aV02(IN VOID *Data);
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195aV02(IN VOID *Data);
#elif defined(CONFIG_CHIP_E_CUT)
_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195aV02(IN VOID *Data);
#endif
//Rtl8195a I2C V02 function prototype END
//Rtl8195a I2C V04 function prototype
_LONG_CALL_ HAL_Status HalI2CSendRtl8195a_V04(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CMassSendRtl8195a_V04(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CInit8195a_V04(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195a_V04(IN VOID *Data);
//Rtl8195a I2C V04 function prototype END
HAL_Status HalI2CInit8195a_Patch(IN VOID *Data);
HAL_Status HalI2CSendRtl8195a_Patch(IN VOID *Data);
HAL_Status HalI2CSetCLKRtl8195a_Patch(IN VOID *Data);
HAL_Status HalI2CMassSendRtl8195a_Patch(IN VOID *Data);
HAL_Status HalI2CEnableRtl8195a_Patch(IN VOID *Data);
HAL_Status HalI2CSetTarRtl8195a(IN VOID *Data);
HAL_Status HalI2CSetSarRtl8195a(IN VOID *Data);
#endif

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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "rtl8195a.h"
#include "system_8195a.h"
#if defined ( __CC_ARM ) /* ARM Compiler 4/5 */
extern uint8_t Image$$RW_IRAM1$$ZI$$Base[];
#define __bss_start__ Image$$RW_IRAM1$$ZI$$Base
extern uint8_t Image$$RW_IRAM1$$ZI$$Limit[];
#define __bss_end__ Image$$RW_IRAM1$$ZI$$Limit
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler 6 */
extern uint8_t Image$$RW_IRAM1$$ZI$$Base[];
#define __bss_start__ Image$$RW_IRAM1$$ZI$$Base
extern uint8_t Image$$RW_IRAM1$$ZI$$Limit[];
#define __bss_end__ Image$$RW_IRAM1$$ZI$$Limit
#elif defined ( __ICCARM__ )
#pragma section=".ram.bss"
#pragma section=".rom.bss"
#pragma section=".ram.start.table"
#pragma section=".ram_image1.bss"
#pragma section=".image2.start.table1"
#pragma section=".image2.start.table2"
uint8_t *__bss_start__;
uint8_t *__bss_end__;
void __iar_data_init_app(void)
{
__bss_start__ = (uint8_t *)__section_begin(".ram.bss");
__bss_end__ = (uint8_t *)__section_end(".ram.bss");
}
#else
extern uint8_t __bss_start__[];
extern uint8_t __bss_end__[];
extern uint8_t __image1_bss_start__[];
extern uint8_t __image1_bss_end__[];
extern uint8_t __image2_entry_func__[];
extern uint8_t __image2_validate_code__[];
#endif
extern VECTOR_Func NewVectorTable[];
extern void SystemCoreClockUpdate(void);
extern void PLAT_Start(void);
extern void PLAT_Main(void);
extern HAL_TIMER_OP HalTimerOp;
IMAGE2_START_RAM_FUN_SECTION const RAM_START_FUNCTION gImage2EntryFun0 = {
PLAT_Start
};
IMAGE1_VALID_PATTEN_SECTION const uint8_t RAM_IMG1_VALID_PATTEN[] = {
0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff
};
IMAGE2_VALID_PATTEN_SECTION const uint8_t RAM_IMG2_VALID_PATTEN[20] = {
'R', 'T', 'K', 'W', 'i', 'n', 0x0, 0xff,
(FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff),
(FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff),
(FW_CHIP_ID&0xff), ((FW_CHIP_ID >> 8)&0xff),
(FW_CHIP_VER),
(FW_BUS_TYPE),
(FW_INFO_RSV1),
(FW_INFO_RSV2),
(FW_INFO_RSV3),
(FW_INFO_RSV4)
};
void TRAP_NMIHandler(void)
{
#ifdef CONFIG_WDG_NORMAL
uint32_t val;
WDG_REG *ctl;
// Check if this NMI is triggered by Watchdog Timer
val = __RTK_READ32(VENDOR_REG_BASE, 0);
ctl = (WDG_REG*) &val;
if (ctl->WdgToISR) {
INTR_WatchdogHandler();
}
#endif
}
#if defined ( __ICCARM__ )
void __TRAP_HardFaultHandler_Patch(uint32_t addr)
{
uint32_t cfsr;
uint32_t bfar;
uint32_t stackpc;
uint16_t asmcode;
cfsr = HAL_READ32(0xE000ED28, 0x0);
// Violation to memory access protection
if (cfsr & 0x82) {
bfar = HAL_READ32(0xE000ED38, 0x0);
// invalid access to wifi register, usually happened in LPS 32K or IPS
if (bfar >= WIFI_REG_BASE && bfar < WIFI_REG_BASE + 0x40000) {
//__BKPT(0);
/* Get the MemManage fault PC, and step to next command.
* Otherwise it will keep hitting MemMange Fault on the same assembly code.
*
* To step to next command, we need parse the assembly code to check if
* it is 16-bit or 32-bit command.
* Ref: ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
* Chapter A6 - Thumb Instruction Set Encoding
*
* However, the fault assembly code (Ex. LDR or ADR) is not actually executed,
* So the register value is un-predictable.
**/
stackpc = HAL_READ32(addr, 0x18);
asmcode = HAL_READ16(stackpc, 0);
if ((asmcode & 0xF800) > 0xE000) {
// 32-bit instruction, (opcode[15:11] = 0b11111, 0b11110, 0b11101)
HAL_WRITE32(addr, 0x18, stackpc + 4);
} else {
// 16-bit instruction
HAL_WRITE32(addr, 0x18, stackpc + 2);
}
// clear Hard Fault Status Register
HAL_WRITE32(0xE000ED2C, 0x0, HAL_READ32(0xE000ED2C, 0x0));
return;
}
}
__TRAP_HardFaultHandler(addr);
}
void TRAP_HardFaultHandler_Patch(void)
{
__asm("TST LR, #4 \n"
"ITE EQ \n"
"MRSEQ R0, MSP \n"
"MRSNE R0, PSP \n"
"B __TRAP_HardFaultHandler_Patch ");
}
#endif
// Override original Interrupt Vector Table
INFRA_START_SECTION void TRAP_OverrideTable(uint32_t stackp)
{
// Override NMI Handler
NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
#if defined ( __ICCARM__ )
NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
#endif
}
INFRA_START_SECTION void PLAT_Init(void)
{
uint32_t val;
//Set SPS lower voltage
val = __RTK_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0);
val &= 0xf0ffffff;
val |= 0x6000000;
__RTK_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0, val);
//xtal buffer driving current
val = __RTK_CTRL_READ32(REG_SYS_XTAL_CTRL1);
val &= ~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1);
val |= BIT_SYS_XTAL_DRV_RF1(1);
__RTK_CTRL_WRITE32(REG_SYS_XTAL_CTRL1, val);
}
//3 Image 2
extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
//extern uint32_t mbed_stack_isr_start;
//extern uint32_t mbed_stack_isr_size;
INFRA_START_SECTION void PLAT_Start(void)
{
u8 isFlashEn;
#if defined ( __ICCARM__ )
__iar_data_init_app();
#endif
// Clear RAM BSS
__rtl_memset_v1_00((void *)__bss_start__, 0, __bss_end__ - __bss_start__);
TRAP_OverrideTable(0x1FFFFFFC);
/* add by Ian --for mbed isr stack address setting */
__set_MSP(0x1fffffbc);
#ifdef CONFIG_SPIC_MODULE
if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN) != 0) {
isFlashEn = 1;
} else {
isFlashEn = 0;
}
#endif
#ifdef CONFIG_TIMER_MODULE
HalTimerOpInit_Patch(&HalTimerOp);
#endif
//DBG_8195A("===== Enter Image 2 ====\n");
SystemCoreClockUpdate();
if (isFlashEn) {
#if CONFIG_SPIC_EN && SPIC_CALIBRATION_IN_NVM
SpicNVMCalLoadAll();
#endif
SpicReadIDRtl8195A();
// turn off SPIC for power saving
SpicDisableRtl8195A();
}
PLAT_Init();
#ifdef CONFIG_TIMER_MODULE
Calibration32k();
#ifdef CONFIG_WDG
#ifdef CONFIG_WDG_TEST
WDGInit();
#endif //CONFIG_WDG_TEST
#endif //CONFIG_WDG
#endif //CONFIG_TIMER_MODULE
#ifdef CONFIG_SOC_PS_MODULE
//InitSoCPM();
#endif
/* GPIOA_7 does not pull high at power on. It causes SDIO Device
* hardware to enable automatically and occupy GPIOA[7:0] */
#ifndef CONFIG_SDIO_DEVICE_EN
SDIO_DEV_Disable();
#endif
// Enter App start function
PLAT_Main();
}
extern void SVC_Handler(void);
extern void PendSV_Handler(void);
extern void SysTick_Handler(void);
#if defined (__CC_ARM)
__asm void ARM_PLAT_Main(void)
{
IMPORT SystemInit
IMPORT __main
BL SystemInit
BL __main
}
#endif
extern void __iar_program_start( void );
// The Main App entry point
void PLAT_Main(void)
{
TRAP_Init((void *)SVC_Handler, (void *)PendSV_Handler, (void *)SysTick_Handler);
#if defined (__ICCARM__)
//IAR_PLAT_Main();
SystemInit();
__iar_program_start();
#elif defined (__CC_ARM)
ARM_PLAT_Main();
#elif defined (__GNUC__)
__asm (
"ldr r0, =SystemInit \n"
"blx r0 \n"
"ldr r0, =_start \n"
"bx r0 \n"
);
#endif
// Never reached
for(;;);
}

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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_RTL8195A_MISC_H
#define MBED_RTL8195A_MISC_H
// Interface to ROM functions
extern __longcall void *_memset( void *s, int c, size_t n);
extern __longcall void *_memcpy( void *s1, const void *s2, size_t n );
extern __longcall int _memcmp( const void *av, const void *bv, size_t len);
extern __longcall size_t _strlen(const char *s);
extern __longcall int _strcmp(const char *cs, const char *ct);
#define __memset _memset
#define __memcpy _memcpy
#define __memcmp _memcmp
#define __strlen _strlen
#define __strcmp _strcmp
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_peri_on.h Normal file
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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_platform.h Normal file
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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// HCI_CLK_CTRL0
#define BIT_ACTCK_SDIOD BIT(0)
#define BIT_SLPCK_SDIOD BIT(1)
#define BIT_ACTCK_SDIOH BIT(2)
#define BIT_SLPCK_SDIOH BIT(3)
#define BIT_ACTCK_HCI_OTG BIT(4)
#define BIT_SLPCK_HCI_OTG BIT(5)
#define BIT_ACTCK_MII_MPHY BIT(24)
#define BIT_SLPCK_MII_MPHY BIT(25)

65
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_pwm.h Normal file
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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
#ifndef _RTL8195A_PWM_H_
#define _RTL8195A_PWM_H_
extern void
HAL_Pwm_SetDuty_8195a(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
extern HAL_Status
HAL_Pwm_Init_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Enable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Disable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
#ifdef CONFIG_CHIP_E_CUT
extern _LONG_CALL_ void
HAL_Pwm_SetDuty_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
extern _LONG_CALL_ HAL_Status
HAL_Pwm_Init_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern _LONG_CALL_ void
HAL_Pwm_Enable_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern _LONG_CALL_ void
HAL_Pwm_Disable_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
#endif
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_rom.h Normal file
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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
SECTIONS
{
__vectors_table = 0x0;
Reset_Handler = 0x101;
NMI_Handler = 0x109;
HardFault_Handler = 0x10d;
MemManage_Handler = 0x121;
BusFault_Handler = 0x125;
UsageFault_Handler = 0x129;
HalLogUartInit = 0x201;
HalSerialPutcRtl8195a = 0x2d9;
HalSerialGetcRtl8195a = 0x309;
HalSerialGetIsrEnRegRtl8195a = 0x329;
HalSerialSetIrqEnRegRtl8195a = 0x335;
HalCpuClkConfig = 0x341;
HalGetCpuClk = 0x355;
HalRomInfo = 0x39d;
HalGetRomInfo = 0x3b5;
HalResetVsr = 0x3c5;
HalDelayUs = 0x899;
HalNMIHandler = 0x8e1;
HalHardFaultHandler = 0x911;
HalMemManageHandler = 0xc09;
HalBusFaultHandler = 0xc39;
HalUsageFaultHandler = 0xc69;
HalUart0PinCtrlRtl8195A = 0xcfd;
HalUart1PinCtrlRtl8195A = 0xdc9;
HalUart2PinCtrlRtl8195A = 0xe9d;
HalSPI0PinCtrlRtl8195A = 0xf75;
HalSPI1PinCtrlRtl8195A = 0x1015;
HalSPI2PinCtrlRtl8195A = 0x10e5;
HalSPI0MCSPinCtrlRtl8195A = 0x11b5;
HalI2C0PinCtrlRtl8195A = 0x1275;
HalI2C1PinCtrlRtl8195A = 0x1381;
HalI2C2PinCtrlRtl8195A = 0x1459;
HalI2C3PinCtrlRtl8195A = 0x1529;
HalI2S0PinCtrlRtl8195A = 0x1639;
HalI2S1PinCtrlRtl8195A = 0x176d;
HalPCM0PinCtrlRtl8195A = 0x1845;
HalPCM1PinCtrlRtl8195A = 0x1949;
HalSDIODPinCtrlRtl8195A = 0x1a1d;
HalSDIOHPinCtrlRtl8195A = 0x1a6d;
HalMIIPinCtrlRtl8195A = 0x1ab9;
HalWLLEDPinCtrlRtl8195A = 0x1b51;
HalWLANT0PinCtrlRtl8195A = 0x1c0d;
HalWLANT1PinCtrlRtl8195A = 0x1c61;
HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5;
HalWLBTCMDPinCtrlRtl8195A = 0x1d05;
HalNFCPinCtrlRtl8195A = 0x1d59;
HalPWM0PinCtrlRtl8195A = 0x1da9;
HalPWM1PinCtrlRtl8195A = 0x1ead;
HalPWM2PinCtrlRtl8195A = 0x1fb5;
HalPWM3PinCtrlRtl8195A = 0x20b1;
HalETE0PinCtrlRtl8195A = 0x21b9;
HalETE1PinCtrlRtl8195A = 0x22c1;
HalETE2PinCtrlRtl8195A = 0x23c9;
HalETE3PinCtrlRtl8195A = 0x24d1;
HalEGTIMPinCtrlRtl8195A = 0x25d9;
HalSPIFlashPinCtrlRtl8195A = 0x2679;
HalSDRPinCtrlRtl8195A = 0x2725;
HalJTAGPinCtrlRtl8195A = 0x280d;
HalTRACEPinCtrlRtl8195A = 0x2861;
HalLOGUartPinCtrlRtl8195A = 0x28b9;
HalLOGUartIRPinCtrlRtl8195A = 0x291d;
HalSICPinCtrlRtl8195A = 0x2981;
HalEEPROMPinCtrlRtl8195A = 0x29d9;
HalDEBUGPinCtrlRtl8195A = 0x2a31;
HalPinCtrlRtl8195A = 0x2b39;
SpicRxCmdRtl8195A = 0x2e5d;
SpicWaitBusyDoneRtl8195A = 0x2ea5;
SpicGetFlashStatusRtl8195A = 0x2eb5;
SpicWaitWipDoneRtl8195A = 0x2f55;
SpicTxCmdRtl8195A = 0x2f6d;
SpicSetFlashStatusRtl8195A = 0x2fc1;
SpicCmpDataForCalibrationRtl8195A = 0x3049;
SpicLoadInitParaFromClockRtl8195A = 0x3081;
SpicInitRtl8195A = 0x30e5;
SpicEraseFlashRtl8195A = 0x31bd;
SpiFlashApp = 0x3279;
HalPeripheralIntrHandle = 0x33b5;
HalSysOnIntrHandle = 0x3439;
HalWdgIntrHandle = 0x3485;
HalTimer0IntrHandle = 0x34d5;
HalTimer1IntrHandle = 0x3525;
HalI2C3IntrHandle = 0x3575;
HalTimer2To7IntrHandle = 0x35c5;
HalSpi0IntrHandle = 0x3615;
HalGpioIntrHandle = 0x3665;
HalUart0IntrHandle = 0x36b5;
HalSpiFlashIntrHandle = 0x3705;
HalUsbOtgIntrHandle = 0x3755;
HalSdioHostIntrHandle = 0x37a5;
HalI2s0OrPcm0IntrHandle = 0x37f5;
HalI2s1OrPcm1IntrHandle = 0x3845;
HalWlDmaIntrHandle = 0x3895;
HalWlProtocolIntrHandle = 0x38e5;
HalCryptoIntrHandle = 0x3935;
HalGmacIntrHandle = 0x3985;
HalGdma0Ch0IntrHandle = 0x39d5;
HalGdma0Ch1IntrHandle = 0x3a25;
HalGdma0Ch2IntrHandle = 0x3a75;
HalGdma0Ch3IntrHandle = 0x3ac5;
HalGdma0Ch4IntrHandle = 0x3b15;
HalGdma0Ch5IntrHandle = 0x3b65;
HalGdma1Ch0IntrHandle = 0x3bb5;
HalGdma1Ch1IntrHandle = 0x3c05;
HalGdma1Ch2IntrHandle = 0x3c55;
HalGdma1Ch3IntrHandle = 0x3ca5;
HalGdma1Ch4IntrHandle = 0x3cf5;
HalGdma1Ch5IntrHandle = 0x3d45;
HalSdioDeviceIntrHandle = 0x3d95;
VectorTableInitRtl8195A = 0x3de5;
VectorTableInitForOSRtl8195A = 0x4019;
VectorIrqRegisterRtl8195A = 0x4029;
VectorIrqUnRegisterRtl8195A = 0x4091;
VectorIrqEnRtl8195A = 0x40f1;
VectorIrqDisRtl8195A = 0x418d;
_UartRxDmaIrqHandle = 0x422d;
HalRuartPutCRtl8195a = 0x4281;
HalRuartGetCRtl8195a = 0x429d;
HalRuartRTSCtrlRtl8195a = 0x42bd;
HalRuartGetDebugValueRtl8195a = 0x42e1;
HalRuartGetIMRRtl8195a = 0x43e1;
HalRuartSetIMRRtl8195a = 0x442d;
_UartIrqHandle = 0x4465;
HalRuartDmaInitRtl8195a = 0x4681;
HalRuartIntDisableRtl8195a = 0x4845;
HalRuartDeInitRtl8195a = 0x4855;
HalRuartIntEnableRtl8195a = 0x4985;
_UartTxDmaIrqHandle = 0x4995;
HalRuartRegIrqRtl8195a = 0x49d1;
HalRuartAdapterLoadDefRtl8195a = 0x4a4d;
HalRuartTxGdmaLoadDefRtl8195a = 0x4add;
HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9;
RuartLock = 0x4cc9;
RuartUnLock = 0x4ced;
HalRuartIntSendRtl8195a = 0x4d09;
HalRuartDmaSendRtl8195a = 0x4e35;
HalRuartStopSendRtl8195a = 0x4f89;
HalRuartIntRecvRtl8195a = 0x504d;
HalRuartDmaRecvRtl8195a = 0x51ad;
HalRuartStopRecvRtl8195a = 0x52cd;
RuartIsTimeout = 0x5385;
HalRuartSendRtl8195a = 0x53b1;
HalRuartRecvRtl8195a = 0x5599;
RuartResetRxFifoRtl8195a = 0x5751;
HalRuartResetRxFifoRtl8195a = 0x5775;
HalRuartInitRtl8195a = 0x5829;
HalGdmaOnOffRtl8195a = 0x5df1;
HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d;
HalGdmaChEnRtl8195a = 0x5e51;
HalGdmaChDisRtl8195a = 0x5e6d;
HalGdamChInitRtl8195a = 0x5e91;
HalGdmaChSetingRtl8195a = 0x5ebd;
HalGdmaChIsrCleanRtl8195a = 0x6419;
HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
HalGdmaChCleanAutoDstRtl8195a = 0x6501;
HalEFUSEPowerSwitch8195AROM = 0x6561;
HALEFUSEOneByteReadROM = 0x65f9;
HALEFUSEOneByteWriteROM = 0x6699;
__rtl_memcmpb_v1_00 = 0x681d;
__rtl_random_v1_00 = 0x6861;
__rtl_align_to_be32_v1_00 = 0x6881;
__rtl_memsetw_v1_00 = 0x6899;
__rtl_memsetb_v1_00 = 0x68ad;
__rtl_memcpyw_v1_00 = 0x68bd;
__rtl_memcpyb_v1_00 = 0x68dd;
__rtl_memDump_v1_00 = 0x68f5;
__rtl_AES_set_encrypt_key = 0x6901;
__rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11;
__rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95;
__rtl_cryptoEngine_init_v1_00 = 0x6ea9;
__rtl_cryptoEngine_exit_v1_00 = 0x7055;
__rtl_cryptoEngine_reset_v1_00 = 0x70b1;
__rtl_cryptoEngine_v1_00 = 0x70ed;
__rtl_crypto_cipher_init_v1_00 = 0x7c69;
__rtl_crypto_cipher_encrypt_v1_00 = 0x7c89;
__rtl_crypto_cipher_decrypt_v1_00 = 0x7cad;
HalSsiPinmuxEnableRtl8195a = 0x7cd5;
HalSsiEnableRtl8195a = 0x7e45;
HalSsiDisableRtl8195a = 0x7ef9;
HalSsiLoadSettingRtl8195a = 0x7fad;
HalSsiSetInterruptMaskRtl8195a = 0x8521;
HalSsiGetInterruptMaskRtl8195a = 0x85c9;
HalSsiSetSclkPolarityRtl8195a = 0x863d;
HalSsiSetSclkPhaseRtl8195a = 0x8715;
HalSsiWriteRtl8195a = 0x87e9;
HalSsiSetDeviceRoleRtl8195a = 0x8861;
HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9;
HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941;
HalSsiReadRtl8195a = 0x89b9;
HalSsiGetRxFifoLevelRtl8195a = 0x8a2d;
HalSsiGetTxFifoLevelRtl8195a = 0x8aa5;
HalSsiGetStatusRtl8195a = 0x8b1d;
HalSsiWriteableRtl8195a = 0x8b91;
HalSsiReadableRtl8195a = 0x8c09;
HalSsiBusyRtl8195a = 0x8c81;
HalSsiReadInterruptRtl8195a = 0x8cf9;
HalSsiWriteInterruptRtl8195a = 0x8efd;
HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009;
HalSsiGetInterruptStatusRtl8195a = 0x90d9;
HalSsiInterruptEnableRtl8195a = 0x914d;
HalSsiInterruptDisableRtl8195a = 0x9299;
HalSsiGetRawInterruptStatusRtl8195a = 0x93e9;
HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d;
HalSsiInitRtl8195a = 0x94d1;
_SsiReadInterrupt = 0x9ba5;
_SsiWriteInterrupt = 0x9db1;
_SsiIrqHandle = 0x9eb1;
HalI2CWrite32 = 0xa061;
HalI2CRead32 = 0xa09d;
HalI2CDeInit8195a = 0xa0dd;
HalI2CSendRtl8195a = 0xa1f1;
HalI2CReceiveRtl8195a = 0xa25d;
HalI2CEnableRtl8195a = 0xa271;
HalI2CIntrCtrl8195a = 0xa389;
HalI2CReadRegRtl8195a = 0xa3a1;
HalI2CWriteRegRtl8195a = 0xa3b1;
HalI2CSetCLKRtl8195a = 0xa3c5;
HalI2CMassSendRtl8195a = 0xa6e9;
HalI2CClrIntrRtl8195a = 0xa749;
HalI2CClrAllIntrRtl8195a = 0xa761;
HalI2CInit8195a = 0xa775;
HalI2CDMACtrl8195a = 0xaa31;
RtkI2CIoCtrl = 0xaa61;
RtkI2CPowerCtrl = 0xaa65;
HalI2COpInit = 0xaa69;
I2CIsTimeout = 0xac65;
I2CTXGDMAISRHandle = 0xb435;
I2CRXGDMAISRHandle = 0xb4c1;
RtkI2CIrqInit = 0xb54d;
RtkI2CIrqDeInit = 0xb611;
RtkI2CPinMuxInit = 0xb675;
RtkI2CPinMuxDeInit = 0xb7c9;
RtkI2CDMAInit = 0xb955;
RtkI2CInit = 0xbc95;
RtkI2CDMADeInit = 0xbdad;
RtkI2CDeInit = 0xbe4d;
RtkI2CSendUserAddr = 0xbee5;
RtkI2CSend = 0xc07d;
RtkI2CLoadDefault = 0xce51;
RtkSalI2COpInit = 0xcf21;
HalI2SWrite32 = 0xcf65;
HalI2SRead32 = 0xcf85;
HalI2SDeInitRtl8195a = 0xcfa9;
HalI2STxRtl8195a = 0xcfc9;
HalI2SRxRtl8195a = 0xd011;
HalI2SEnableRtl8195a = 0xd05d;
HalI2SIntrCtrlRtl8195a = 0xd0b1;
HalI2SReadRegRtl8195a = 0xd0d1;
HalI2SClrIntrRtl8195a = 0xd0dd;
HalI2SClrAllIntrRtl8195a = 0xd0fd;
HalI2SInitRtl8195a = 0xd11d;
GPIO_GetIPPinName_8195a = 0xd2e5;
GPIO_GetChipPinName_8195a = 0xd331;
GPIO_PullCtrl_8195a = 0xd39d;
GPIO_FuncOn_8195a = 0xd421;
GPIO_FuncOff_8195a = 0xd481;
GPIO_Int_Mask_8195a = 0xd4e9;
GPIO_Int_SetType_8195a = 0xd511;
HAL_GPIO_IrqHandler_8195a = 0xd5fd;
HAL_GPIO_MbedIrqHandler_8195a = 0xd645;
HAL_GPIO_UserIrqHandler_8195a = 0xd6a1;
HAL_GPIO_IntCtrl_8195a = 0xd6cd;
HAL_GPIO_Init_8195a = 0xd805;
HAL_GPIO_DeInit_8195a = 0xdac1;
HAL_GPIO_ReadPin_8195a = 0xdbd1;
HAL_GPIO_WritePin_8195a = 0xdc91;
HAL_GPIO_RegIrq_8195a = 0xddad;
HAL_GPIO_UnRegIrq_8195a = 0xddf5;
HAL_GPIO_UserRegIrq_8195a = 0xde15;
HAL_GPIO_UserUnRegIrq_8195a = 0xdef9;
HAL_GPIO_MaskIrq_8195a = 0xdfc1;
HAL_GPIO_UnMaskIrq_8195a = 0xe061;
HAL_GPIO_IntDebounce_8195a = 0xe101;
HAL_GPIO_GetIPPinName_8195a = 0xe1c1;
HAL_GPIO_PullCtrl_8195a = 0xe1c9;
DumpForOneBytes = 0xe259;
CmdRomHelp = 0xe419;
CmdWriteWord = 0xe491;
CmdDumpHelfWord = 0xe505;
CmdDumpWord = 0xe5f1;
CmdDumpByte = 0xe6f5;
CmdSpiFlashTool = 0xe751;
GetRomCmdNum = 0xe7a9;
CmdWriteByte = 0xe7ad;
Isspace = 0xe7ed;
Strtoul = 0xe801;
ArrayInitialize = 0xe8b1;
GetArgc = 0xe8c9;
GetArgv = 0xe8f9;
UartLogCmdExecute = 0xe95d;
UartLogShowBackSpace = 0xe9fd;
UartLogRecallOldCmd = 0xea39;
UartLogHistoryCmd = 0xea71;
UartLogCmdChk = 0xeadd;
UartLogIrqHandle = 0xebf5;
RtlConsolInit = 0xecc5;
RtlConsolTaskRom = 0xed49;
RtlExitConsol = 0xed79;
RtlConsolRom = 0xedcd;
HalTimerOpInit = 0xee0d;
HalTimerIrq2To7Handle = 0xee59;
HalGetTimerIdRtl8195a = 0xef09;
HalTimerInitRtl8195a = 0xef3d;
HalTimerDisRtl8195a = 0xf069;
HalTimerEnRtl8195a = 0xf089;
HalTimerReadCountRtl8195a = 0xf0a9;
HalTimerIrqClearRtl8195a = 0xf0bd;
HalTimerDumpRegRtl8195a = 0xf0d1;
VSprintf = 0xf129;
DiagPrintf = 0xf39d;
DiagSPrintf = 0xf3b9;
DiagSnPrintf = 0xf3d1;
prvDiagPrintf = 0xf3ed;
prvDiagSPrintf = 0xf40d;
_memcmp = 0xf429;
_memcpy = 0xf465;
_memset = 0xf511;
Rand = 0xf585;
_strncpy = 0xf60d;
_strcpy = 0xf629;
prvStrCpy = 0xf639;
_strlen = 0xf651;
_strnlen = 0xf669;
prvStrLen = 0xf699;
_strcmp = 0xf6b1;
_strncmp = 0xf6d1;
prvStrCmp = 0xf719;
StrUpr = 0xf749;
prvAtoi = 0xf769;
prvStrStr = 0xf7bd;
_strsep = 0xf7d5;
skip_spaces = 0xf815;
skip_atoi = 0xf831;
_parse_integer_fixup_radix = 0xf869;
_parse_integer = 0xf8bd;
simple_strtoull = 0xf915;
simple_strtoll = 0xf945;
simple_strtoul = 0xf965;
simple_strtol = 0xf96d;
_vsscanf = 0xf985;
_sscanf = 0xff71;
div_u64 = 0xff91;
div_s64 = 0xff99;
div_u64_rem = 0xffa1;
div_s64_rem = 0xffb1;
_strpbrk = 0xffc1;
_strchr = 0xffed;
aes_set_key = 0x10005;
aes_encrypt = 0x103d1;
aes_decrypt = 0x114a5;
AES_WRAP = 0x125c9;
AES_UnWRAP = 0x12701;
crc32_get = 0x12861;
arc4_byte = 0x12895;
rt_arc4_init = 0x128bd;
rt_arc4_crypt = 0x12901;
rt_md5_init = 0x131c1;
rt_md5_append = 0x131f5;
rt_md5_final = 0x1327d;
rt_md5_hmac = 0x132d5;
rtw_get_bit_value_from_ieee_value = 0x13449;
rtw_is_cckrates_included = 0x13475;
rtw_is_cckratesonly_included = 0x134b5;
rtw_check_network_type = 0x134dd;
rtw_set_fixed_ie = 0x1350d;
rtw_set_ie = 0x1352d;
rtw_get_ie = 0x1355d;
rtw_set_supported_rate = 0x13591;
rtw_get_rateset_len = 0x13611;
rtw_get_wpa_ie = 0x1362d;
rtw_get_wpa2_ie = 0x136c9;
rtw_get_wpa_cipher_suite = 0x13701;
rtw_get_wpa2_cipher_suite = 0x13769;
rtw_parse_wpa_ie = 0x137d1;
rtw_parse_wpa2_ie = 0x138ad;
rtw_get_sec_ie = 0x13965;
rtw_get_wps_ie = 0x13a15;
rtw_get_wps_attr = 0x13a99;
rtw_get_wps_attr_content = 0x13b49;
rtw_ieee802_11_parse_elems = 0x13b91;
str_2char2num = 0x13d9d;
key_2char2num = 0x13db9;
convert_ip_addr = 0x13dd1;
rom_psk_PasswordHash = 0x13e9d;
rom_psk_CalcGTK = 0x13ed5;
rom_psk_CalcPTK = 0x13f69;
wep_80211_encrypt = 0x14295;
wep_80211_decrypt = 0x142f5;
tkip_micappendbyte = 0x14389;
rtw_secmicsetkey = 0x143d9;
rtw_secmicappend = 0x14419;
rtw_secgetmic = 0x14435;
rtw_seccalctkipmic = 0x1449d;
tkip_phase1 = 0x145a5;
tkip_phase2 = 0x14725;
tkip_80211_encrypt = 0x14941;
tkip_80211_decrypt = 0x149d5;
aes1_encrypt = 0x14a8d;
aesccmp_construct_mic_iv = 0x14c65;
aesccmp_construct_mic_header1 = 0x14ccd;
aesccmp_construct_mic_header2 = 0x14d21;
aesccmp_construct_ctr_preload = 0x14db5;
aes_80211_encrypt = 0x14e29;
aes_80211_decrypt = 0x151ad;
_sha1_process_message_block = 0x155b9;
_sha1_pad_message = 0x15749;
rt_sha1_init = 0x157e5;
rt_sha1_update = 0x15831;
rt_sha1_finish = 0x158a9;
rt_hmac_sha1 = 0x15909;
rom_aes_128_cbc_encrypt = 0x15a65;
rom_aes_128_cbc_decrypt = 0x15ae1;
rom_rijndaelKeySetupEnc = 0x15b5d;
rom_aes_decrypt_init = 0x15c39;
rom_aes_internal_decrypt = 0x15d15;
rom_aes_decrypt_deinit = 0x16071;
rom_aes_encrypt_init = 0x16085;
rom_aes_internal_encrypt = 0x1609d;
rom_aes_encrypt_deinit = 0x16451;
bignum_init = 0x17b35;
bignum_deinit = 0x17b61;
bignum_get_unsigned_bin_len = 0x17b81;
bignum_get_unsigned_bin = 0x17b85;
bignum_set_unsigned_bin = 0x17c21;
bignum_cmp = 0x17cd1;
bignum_cmp_d = 0x17cd5;
bignum_add = 0x17cfd;
bignum_sub = 0x17d0d;
bignum_mul = 0x17d1d;
bignum_exptmod = 0x17d2d;
WPS_realloc = 0x17d51;
os_zalloc = 0x17d99;
rom_hmac_sha256_vector = 0x17dc1;
rom_hmac_sha256 = 0x17ebd;
rom_sha256_vector = 0x18009;
phy_CalculateBitShift = 0x18221;
PHY_SetBBReg_8195A = 0x18239;
PHY_QueryBBReg_8195A = 0x18279;
ROM_odm_QueryRxPwrPercentage = 0x1829d;
ROM_odm_EVMdbToPercentage = 0x182bd;
ROM_odm_SignalScaleMapping_8195A = 0x182e5;
ROM_odm_FalseAlarmCounterStatistics = 0x183cd;
ROM_odm_SetEDCCAThreshold = 0x18721;
ROM_odm_SetTRxMux = 0x18749;
ROM_odm_SetCrystalCap = 0x18771;
ROM_odm_GetDefaultCrytaltalCap = 0x187d5;
ROM_ODM_CfoTrackingReset = 0x187e9;
ROM_odm_CfoTrackingFlow = 0x18811;
curve25519_donna = 0x1965d;
aes_test_alignment_detection = 0x1a391;
aes_mode_reset = 0x1a3ed;
aes_ecb_encrypt = 0x1a3f9;
aes_ecb_decrypt = 0x1a431;
aes_cbc_encrypt = 0x1a469;
aes_cbc_decrypt = 0x1a579;
aes_cfb_encrypt = 0x1a701;
aes_cfb_decrypt = 0x1a9e5;
aes_ofb_crypt = 0x1acc9;
aes_ctr_crypt = 0x1af7d;
aes_encrypt_key128 = 0x1b289;
aes_encrypt_key192 = 0x1b2a5;
aes_encrypt_key256 = 0x1b2c1;
aes_encrypt_key = 0x1b2e1;
aes_decrypt_key128 = 0x1b351;
aes_decrypt_key192 = 0x1b36d;
aes_decrypt_key256 = 0x1b389;
aes_decrypt_key = 0x1b3a9;
aes_init = 0x1b419;
CRYPTO_chacha_20 = 0x1b41d;
CRYPTO_poly1305_init = 0x1bc25;
CRYPTO_poly1305_update = 0x1bd09;
CRYPTO_poly1305_finish = 0x1bd8d;
rom_sha512_starts = 0x1ceb5;
rom_sha512_update = 0x1d009;
rom_sha512_finish = 0x1d011;
rom_sha512 = 0x1d261;
rom_sha512_hmac_starts = 0x1d299;
rom_sha512_hmac_update = 0x1d35d;
rom_sha512_hmac_finish = 0x1d365;
rom_sha512_hmac_reset = 0x1d3b5;
rom_sha512_hmac = 0x1d3d1;
rom_sha512_hkdf = 0x1d40d;
rom_ed25519_gen_keypair = 0x1d501;
rom_ed25519_gen_signature = 0x1d505;
rom_ed25519_verify_signature = 0x1d51d;
rom_ed25519_crypto_sign_seed_keypair = 0x1d521;
rom_ed25519_crypto_sign_detached = 0x1d579;
rom_ed25519_crypto_sign_verify_detached = 0x1d655;
rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d;
rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35;
rom_ed25519_ge_p3_tobytes = 0x207d5;
rom_ed25519_ge_scalarmult_base = 0x20821;
rom_ed25519_ge_tobytes = 0x209e1;
rom_ed25519_sc_muladd = 0x20a2d;
rom_ed25519_sc_reduce = 0x2603d;
__rtl_memchr_v1_00 = 0x28a4d;
__rtl_memcmp_v1_00 = 0x28ae1;
__rtl_memcpy_v1_00 = 0x28b49;
__rtl_memmove_v1_00 = 0x28bed;
__rtl_memset_v1_00 = 0x28cb5;
__rtl_strcat_v1_00 = 0x28d49;
__rtl_strchr_v1_00 = 0x28d91;
__rtl_strcmp_v1_00 = 0x28e55;
__rtl_strcpy_v1_00 = 0x28ec9;
__rtl_strlen_v1_00 = 0x28f15;
__rtl_strncat_v1_00 = 0x28f69;
__rtl_strncmp_v1_00 = 0x28fc5;
__rtl_strncpy_v1_00 = 0x2907d;
__rtl_strstr_v1_00 = 0x293cd;
__rtl_strsep_v1_00 = 0x2960d;
__rtl_strtok_v1_00 = 0x29619;
__rtl__strtok_r_v1_00 = 0x2962d;
__rtl_strtok_r_v1_00 = 0x29691;
__rtl_close_v1_00 = 0x29699;
__rtl_fstat_v1_00 = 0x296ad;
__rtl_isatty_v1_00 = 0x296c1;
__rtl_lseek_v1_00 = 0x296d5;
__rtl_open_v1_00 = 0x296e9;
__rtl_read_v1_00 = 0x296fd;
__rtl_write_v1_00 = 0x29711;
__rtl_sbrk_v1_00 = 0x29725;
__rtl_ltoa_v1_00 = 0x297bd;
__rtl_ultoa_v1_00 = 0x29855;
__rtl_dtoi_v1_00 = 0x298c5;
__rtl_dtoi64_v1_00 = 0x29945;
__rtl_dtoui_v1_00 = 0x299dd;
__rtl_ftol_v1_00 = 0x299e5;
__rtl_itof_v1_00 = 0x29a51;
__rtl_itod_v1_00 = 0x29ae9;
__rtl_i64tod_v1_00 = 0x29b79;
__rtl_uitod_v1_00 = 0x29c55;
__rtl_ftod_v1_00 = 0x29d2d;
__rtl_dtof_v1_00 = 0x29de9;
__rtl_uitof_v1_00 = 0x29e89;
__rtl_fadd_v1_00 = 0x29f65;
__rtl_fsub_v1_00 = 0x2a261;
__rtl_fmul_v1_00 = 0x2a559;
__rtl_fdiv_v1_00 = 0x2a695;
__rtl_dadd_v1_00 = 0x2a825;
__rtl_dsub_v1_00 = 0x2aed9;
__rtl_dmul_v1_00 = 0x2b555;
__rtl_ddiv_v1_00 = 0x2b8ad;
__rtl_dcmpeq_v1_00 = 0x2be4d;
__rtl_dcmplt_v1_00 = 0x2bebd;
__rtl_dcmpgt_v1_00 = 0x2bf51;
__rtl_dcmple_v1_00 = 0x2c049;
__rtl_fcmplt_v1_00 = 0x2c139;
__rtl_fcmpgt_v1_00 = 0x2c195;
__rtl_cos_f32_v1_00 = 0x2c229;
__rtl_sin_f32_v1_00 = 0x2c435;
__rtl_fabs_v1_00 = 0x2c639;
__rtl_fabsf_v1_00 = 0x2c641;
__rtl_dtoa_r_v1_00 = 0x2c77d;
__rom_mallocr_init_v1_00 = 0x2d7d1;
__rtl_free_r_v1_00 = 0x2d841;
__rtl_malloc_r_v1_00 = 0x2da31;
__rtl_realloc_r_v1_00 = 0x2df55;
__rtl_memalign_r_v1_00 = 0x2e331;
__rtl_valloc_r_v1_00 = 0x2e421;
__rtl_pvalloc_r_v1_00 = 0x2e42d;
__rtl_calloc_r_v1_00 = 0x2e441;
__rtl_cfree_r_v1_00 = 0x2e4a9;
__rtl_Balloc_v1_00 = 0x2e515;
__rtl_Bfree_v1_00 = 0x2e571;
__rtl_i2b_v1_00 = 0x2e585;
__rtl_multadd_v1_00 = 0x2e599;
__rtl_mult_v1_00 = 0x2e629;
__rtl_pow5mult_v1_00 = 0x2e769;
__rtl_hi0bits_v1_00 = 0x2e809;
__rtl_d2b_v1_00 = 0x2e845;
__rtl_lshift_v1_00 = 0x2e901;
__rtl_cmp_v1_00 = 0x2e9bd;
__rtl_diff_v1_00 = 0x2ea01;
__rtl_sread_v1_00 = 0x2eae9;
__rtl_seofread_v1_00 = 0x2eb39;
__rtl_swrite_v1_00 = 0x2eb3d;
__rtl_sseek_v1_00 = 0x2ebc1;
__rtl_sclose_v1_00 = 0x2ec11;
__rtl_sbrk_r_v1_00 = 0x2ec41;
__rtl_fflush_r_v1_00 = 0x2ef8d;
__rtl_vfprintf_r_v1_00 = 0x2f661;
__rtl_fpclassifyd = 0x30c15;
CpkClkTbl = 0x30c68;
ROM_IMG1_VALID_PATTEN = 0x30c80;
SpicCalibrationPattern = 0x30c88;
SpicInitCPUCLK = 0x30c98;
BAUDRATE = 0x30ca8;
OVSR = 0x30d1c;
DIV = 0x30d90;
OVSR_ADJ = 0x30e04;
__AES_rcon = 0x30e78;
__AES_Te4 = 0x30ea0;
I2CDmaChNo = 0x312a0;
_GPIO_PinMap_Chip2IP_8195a = 0x312b4;
_GPIO_PinMap_PullCtrl_8195a = 0x3136c;
_GPIO_SWPORT_DDR_TBL = 0x31594;
_GPIO_EXT_PORT_TBL = 0x31598;
_GPIO_SWPORT_DR_TBL = 0x3159c;
UartLogRomCmdTable = 0x316a0;
_HalRuartOp = 0x31700;
_HalGdmaOp = 0x31760;
RTW_WPA_OUI_TYPE = 0x3540c;
WPA_CIPHER_SUITE_NONE = 0x35410;
WPA_CIPHER_SUITE_WEP40 = 0x35414;
WPA_CIPHER_SUITE_TKIP = 0x35418;
WPA_CIPHER_SUITE_CCMP = 0x3541c;
WPA_CIPHER_SUITE_WEP104 = 0x35420;
RSN_CIPHER_SUITE_NONE = 0x35424;
RSN_CIPHER_SUITE_WEP40 = 0x35428;
RSN_CIPHER_SUITE_TKIP = 0x3542c;
RSN_CIPHER_SUITE_CCMP = 0x35430;
RSN_CIPHER_SUITE_WEP104 = 0x35434;
RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444;
RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448;
RSN_VERSION_BSD = 0x3544c;
rom_wps_Te0 = 0x35988;
rom_wps_rcons = 0x35d88;
rom_wps_Td4s = 0x35d94;
rom_wps_Td0 = 0x35e94;
__rom_b_cut_end__ = 0x4467c;
__rom_c_cut_text_start__ = 0x4467c;
HalInitPlatformLogUartV02 = 0x4467d;
HalReInitPlatformLogUartV02 = 0x4471d;
HalInitPlatformTimerV02 = 0x44755;
HalShowBuildInfoV02 = 0x447cd;
SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831;
HalSpiInitV02 = 0x4488d;
HalBootFlowV02 = 0x44a29;
HalInitialROMCodeGlobalVarV02 = 0x44ae5;
HalResetVsrV02 = 0x44b41;
HalI2CSendRtl8195aV02 = 0x44ce1;
HalI2CSetCLKRtl8195aV02 = 0x44d59;
RtkI2CSendV02 = 0x4508d;
RtkI2CReceiveV02 = 0x459a1;
HalI2COpInitV02 = 0x461ed;
I2CISRHandleV02 = 0x463e9;
RtkSalI2COpInitV02 = 0x46be1;
SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25;
SpiFlashAppV02 = 0x46c85;
SpicInitRtl8195AV02 = 0x46dc5;
SpicEraseFlashRtl8195AV02 = 0x46ea1;
HalTimerIrq2To7HandleV02 = 0x46f5d;
HalTimerIrqRegisterRtl8195aV02 = 0x46fe1;
HalTimerInitRtl8195aV02 = 0x4706d;
HalTimerReadCountRtl8195aV02 = 0x471b5;
HalTimerReLoadRtl8195aV02 = 0x471d1;
HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d;
HalTimerDeInitRtl8195aV02 = 0x472c1;
HalTimerOpInitV02 = 0x472f9;
GPIO_LockV02 = 0x47345;
GPIO_UnLockV02 = 0x47379;
GPIO_Int_Clear_8195aV02 = 0x473a5;
HAL_GPIO_IntCtrl_8195aV02 = 0x473b5;
FindElementIndexV02 = 0x47541;
HalRuartInitRtl8195aV02 = 0x4756d;
DramInit_rom = 0x47619;
ChangeRandSeed_rom = 0x47979;
Sdr_Rand2_rom = 0x47985;
MemTest_rom = 0x479dd;
SdrCalibration_rom = 0x47a45;
SdrControllerInit_rom = 0x47d99;
SDIO_EnterCritical = 0x47e39;
SDIO_ExitCritical = 0x47e85;
SDIO_IRQ_Handler_Rom = 0x47ec5;
SDIO_Interrupt_Init_Rom = 0x47f31;
SDIO_Device_Init_Rom = 0x47f81;
SDIO_Interrupt_DeInit_Rom = 0x48215;
SDIO_Device_DeInit_Rom = 0x48255;
SDIO_Enable_Interrupt_Rom = 0x48281;
SDIO_Disable_Interrupt_Rom = 0x482a1;
SDIO_Clear_ISR_Rom = 0x482c1;
SDIO_Alloc_Rx_Pkt_Rom = 0x482d9;
SDIO_Free_Rx_Pkt_Rom = 0x48331;
SDIO_Recycle_Rx_BD_Rom = 0x48355;
SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1;
SDIO_RxTask_Rom = 0x4851d;
SDIO_Process_H2C_IOMsg_Rom = 0x4856d;
SDIO_Send_C2H_IOMsg_Rom = 0x4859d;
SDIO_Process_RPWM_Rom = 0x485b5;
SDIO_Reset_Cmd_Rom = 0x485e9;
SDIO_Rx_Data_Transaction_Rom = 0x48611;
SDIO_Send_C2H_PktMsg_Rom = 0x48829;
SDIO_Register_Tx_Callback_Rom = 0x488f5;
SDIO_ReadMem_Rom = 0x488fd;
SDIO_WriteMem_Rom = 0x489a9;
SDIO_SetMem_Rom = 0x48a69;
SDIO_TX_Pkt_Handle_Rom = 0x48b29;
SDIO_TX_FIFO_DataReady_Rom = 0x48c69;
SDIO_IRQ_Handler_BH_Rom = 0x48d95;
SDIO_TxTask_Rom = 0x48e9d;
SDIO_TaskUp_Rom = 0x48eed;
SDIO_Boot_Up = 0x48f55;
__rom_c_cut_text_end__ = 0x49070;
__rom_c_cut_rodata_start__ = 0x49070;
BAUDRATE_v02 = 0x49070;
OVSR_v02 = 0x490fc;
DIV_v02 = 0x49188;
OVSR_ADJ_v02 = 0x49214;
SdrDramInfo_rom = 0x492a0;
SdrDramTiming_rom = 0x492b4;
SdrDramModeReg_rom = 0x492e8;
SdrDramDev_rom = 0x49304;
__rom_c_cut_rodata_end__ = 0x49314;
NewVectorTable = 0x10000000;
UserhandlerTable = 0x10000100;
UserIrqDataTable = 0x10000200;
__rom_bss_start__ = 0x10000300;
CfgSysDebugWarn = 0x10000300;
CfgSysDebugInfo = 0x10000304;
CfgSysDebugErr = 0x10000308;
ConfigDebugWarn = 0x1000030c;
ConfigDebugInfo = 0x10000310;
ConfigDebugErr = 0x10000314;
HalTimerOp = 0x10000318;
GPIOState = 0x10000334;
gTimerRecord = 0x1000034c;
SSI_DBG_CONFIG = 0x10000350;
_pHAL_Gpio_Adapter = 0x10000354;
Timer2To7VectorTable = 0x10000358;
pUartLogCtl = 0x10000384;
UartLogBuf = 0x10000388;
UartLogCtl = 0x10000408;
UartLogHistoryBuf = 0x10000430;
ArgvArray = 0x100006ac;
rom_wlan_ram_map = 0x100006d4;
FalseAlmCnt = 0x100006e0;
ROMInfo = 0x10000720;
DM_CfoTrack = 0x10000738;
rom_libgloss_ram_map = 0x10000760;
__rtl_errno = 0x10000bc4;
}

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_sdio.h Normal file
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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_RTL8195A_SDIO_H
#define MBED_RTL8195A_SDIO_H
__BUILD_CCTRL_MACRO(SDIOD, REG_PESOC_HCI_CLK_CTRL0)
__BUILD_CCTRL_MACRO(SDIOH, REG_PESOC_HCI_CLK_CTRL0)
#define __SDIOD_Enable() \
do { \
__RTK_PERI_SETBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_EN); \
__RTK_PERI_SETBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_OFF_EN); \
} while (0)
#define __SDIOH_Enable() \
do { \
__RTK_PERI_SETBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOH_EN); \
} while (0)
#define __SDIOD_Disable() \
do { \
__RTK_READ32(SDIO_DEVICE_REG_BASE, 0); \
__RTK_PERI_CLRBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_EN); \
__RTK_PERI_CLRBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_OFF_EN); \
} while (0)
#define __SDIOH_Disable() \
do { \
__RTK_READ32(SDIO_HOST_REG_BASE, 0); \
__RTK_PERI_CLRBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOH_EN); \
} while (0)
// PERI_MCTRL_HCI
#define __SDIOD_PINMUX_Enable() __RTK_PERI_SETBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOD_PIN_EN)
#define __SDIOH_PINMUX_Enable() __RTK_PERI_SETBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOH_PIN_EN)
#define __SDIOD_PINMUX_Disable() __RTK_PERI_CLRBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOD_PIN_EN)
#define __SDIOH_PINMUX_Disable() __RTK_PERI_CLRBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOH_PIN_EN)
#define __MII_PINMUX_Enable() __RTK_PERI_SETBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_MII_PIN_EN)
#define __MII_PINMUX_Disable() __RTK_PERI_CLRBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_MII_PIN_EN)
// Interface for HAL functions
extern void SDIO_HST_Disable(void);
extern void SDIO_DEV_Disable(void);
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_spi_flash.h Normal file
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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_ssi.h Normal file
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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
#ifndef _RTL8195A_SSI_H_
#define _RTL8195A_SSI_H_
#define SSI_DUMMY_DATA 0x00 // for master mode, we need to push a Dummy data to TX FIFO for read
#define SSI_CLK_SPI1 (PLATFORM_CLOCK/2)
#define SSI_CLK_SPI0_2 (PLATFORM_CLOCK/4)
/* Parameters of DW_apb_ssi for RTL8195A */
#define SSI_TX_FIFO_DEPTH 64
#define TX_ABW 6 // 1-8, log2(SSI_TX_FIFO_DEPTH)
#define SSI_RX_FIFO_DEPTH 64
#define RX_ABW 6 // 1-8, log2(SSI_RX_FIFO_DEPTH)
#define SSI0_REG_BASE 0x40042000
#define SSI1_REG_BASE 0x40042400
#define SSI2_REG_BASE 0x40042800
/* Memory Map of DW_apb_ssi */
#define REG_DW_SSI_CTRLR0 0x00 // 16 bits
#define REG_DW_SSI_CTRLR1 0x04 // 16 bits
#define REG_DW_SSI_SSIENR 0x08 // 1 bit
#define REG_DW_SSI_MWCR 0x0C // 3 bits
#define REG_DW_SSI_SER 0x10 //
#define REG_DW_SSI_BAUDR 0x14 // 16 bits
#define REG_DW_SSI_TXFTLR 0x18 // TX_ABW
#define REG_DW_SSI_RXFTLR 0x1C // RX_ABW
#define REG_DW_SSI_TXFLR 0x20 //
#define REG_DW_SSI_RXFLR 0x24 //
#define REG_DW_SSI_SR 0x28 // 7 bits
#define REG_DW_SSI_IMR 0x2C //
#define REG_DW_SSI_ISR 0x30 // 6 bits
#define REG_DW_SSI_RISR 0x34 // 6 bits
#define REG_DW_SSI_TXOICR 0x38 // 1 bits
#define REG_DW_SSI_RXOICR 0x3C // 1 bits
#define REG_DW_SSI_RXUICR 0x40 // 1 bits
#define REG_DW_SSI_MSTICR 0x44 // 1 bits
#define REG_DW_SSI_ICR 0x48 // 1 bits
#define REG_DW_SSI_DMACR 0x4C // 2 bits
#define REG_DW_SSI_DMATDLR 0x50 // TX_ABW
#define REG_DW_SSI_DMARDLR 0x54 // RX_ABW
#define REG_DW_SSI_IDR 0x58 // 32 bits
#define REG_DW_SSI_COMP_VERSION 0x5C // 32 bits
#define REG_DW_SSI_DR 0x60 // 16 bits 0x60-0xEC
#define REG_DW_SSI_RX_SAMPLE_DLY 0xF0 // 8 bits
#define REG_DW_SSI_RSVD_0 0xF4 // 32 bits
#define REG_DW_SSI_RSVD_1 0xF8 // 32 bits
#define REG_DW_SSI_RSVD_2 0xFC // 32 bits
// CTRLR0 0x00 // 16 bits, 6.2.1
// DFS Reset Value: 0x7
#define BIT_SHIFT_CTRLR0_DFS 0
#define BIT_MASK_CTRLR0_DFS 0xF
#define BIT_CTRLR0_DFS(x)(((x) & BIT_MASK_CTRLR0_DFS) << BIT_SHIFT_CTRLR0_DFS)
#define BIT_INVC_CTRLR0_DFS (~(BIT_MASK_CTRLR0_DFS << BIT_SHIFT_CTRLR0_DFS))
#define BIT_SHIFT_CTRLR0_FRF 4
#define BIT_MASK_CTRLR0_FRF 0x3
#define BIT_CTRLR0_FRF(x)(((x) & BIT_MASK_CTRLR0_FRF) << BIT_SHIFT_CTRLR0_FRF)
#define BIT_INVC_CTRLR0_FRF (~(BIT_MASK_CTRLR0_FRF << BIT_SHIFT_CTRLR0_FRF))
#define BIT_SHIFT_CTRLR0_SCPH 6
#define BIT_MASK_CTRLR0_SCPH 0x1
#define BIT_CTRLR0_SCPH(x)(((x) & BIT_MASK_CTRLR0_SCPH) << BIT_SHIFT_CTRLR0_SCPH)
#define BIT_INVC_CTRLR0_SCPH (~(BIT_MASK_CTRLR0_SCPH << BIT_SHIFT_CTRLR0_SCPH))
#define BIT_SHIFT_CTRLR0_SCPOL 7
#define BIT_MASK_CTRLR0_SCPOL 0x1
#define BIT_CTRLR0_SCPOL(x)(((x) & BIT_MASK_CTRLR0_SCPOL) << BIT_SHIFT_CTRLR0_SCPOL)
#define BIT_INVC_CTRLR0_SCPOL (~(BIT_MASK_CTRLR0_SCPOL << BIT_SHIFT_CTRLR0_SCPOL))
#define BIT_SHIFT_CTRLR0_TMOD 8
#define BIT_MASK_CTRLR0_TMOD 0x3
#define BIT_CTRLR0_TMOD(x)(((x) & BIT_MASK_CTRLR0_TMOD) << BIT_SHIFT_CTRLR0_TMOD)
#define BIT_INVC_CTRLR0_TMOD (~(BIT_MASK_CTRLR0_TMOD << BIT_SHIFT_CTRLR0_TMOD))
#define BIT_SHIFT_CTRLR0_SLV_OE 10
#define BIT_MASK_CTRLR0_SLV_OE 0x1
#define BIT_CTRLR0_SLV_OE(x)(((x) & BIT_MASK_CTRLR0_SLV_OE) << BIT_SHIFT_CTRLR0_SLV_OE)
#define BIT_INVC_CTRLR0_SLV_OE (~(BIT_MASK_CTRLR0_SLV_OE << BIT_SHIFT_CTRLR0_SLV_OE))
#define BIT_SHIFT_CTRLR0_SRL 11
#define BIT_MASK_CTRLR0_SRL 0x1
#define BIT_CTRLR0_SRL(x)(((x) & BIT_MASK_CTRLR0_SRL) << BIT_SHIFT_CTRLR0_SRL)
#define BIT_INVC_CTRLR0_SRL (~(BIT_MASK_CTRLR0_SRL << BIT_SHIFT_CTRLR0_SRL))
#define BIT_SHIFT_CTRLR0_CFS 12
#define BIT_MASK_CTRLR0_CFS 0xF
#define BIT_CTRLR0_CFS(x)(((x) & BIT_MASK_CTRLR0_CFS) << BIT_SHIFT_CTRLR0_CFS)
#define BIT_INVC_CTRLR0_CFS (~(BIT_MASK_CTRLR0_CFS << BIT_SHIFT_CTRLR0_CFS))
// CTRLR1 0x04 // 16 bits
#define BIT_SHIFT_CTRLR1_NDF 0
#define BIT_MASK_CTRLR1_NDF 0xFFFF
#define BIT_CTRLR1_NDF(x)(((x) & BIT_MASK_CTRLR1_NDF) << BIT_SHIFT_CTRLR1_NDF)
#define BIT_INVC_CTRLR1_NDF (~(BIT_MASK_CTRLR1_NDF << BIT_SHIFT_CTRLR1_NDF))
// SSIENR 0x08 // 1 bit
#define BIT_SHIFT_SSIENR_SSI_EN 0
#define BIT_MASK_SSIENR_SSI_EN 0x1
#define BIT_SSIENR_SSI_EN(x)(((x) & BIT_MASK_SSIENR_SSI_EN) << BIT_SHIFT_SSIENR_SSI_EN)
#define BIT_INVC_SSIENR_SSI_EN (~(BIT_MASK_SSIENR_SSI_EN << BIT_SHIFT_SSIENR_SSI_EN))
// MWCR 0x0c // 3 bits
#define BIT_SHIFT_MWCR_MWMOD 0
#define BIT_MASK_MWCR_MWMOD 0x1
#define BIT_MWCR_MWMOD(x)(((x) & BIT_MASK_MWCR_MWMOD) << BIT_SHIFT_MWCR_MWMOD)
#define BIT_INVC_MWCR_MWMOD (~(BIT_MASK_MWCR_MWMOD << BIT_SHIFT_MWCR_MWMOD))
#define BIT_SHIFT_MWCR_MDD 1
#define BIT_MASK_MWCR_MDD 0x1
#define BIT_MWCR_MDD(x)(((x) & BIT_MASK_MWCR_MDD) << BIT_SHIFT_MWCR_MDD)
#define BIT_INVC_MWCR_MDD (~(BIT_MASK_MWCR_MDD << BIT_SHIFT_MWCR_MDD))
#define BIT_SHIFT_MWCR_MHS 2
#define BIT_MASK_MWCR_MHS 0x1
#define BIT_MWCR_MHS(x)(((x) & BIT_MASK_MWCR_MHS) << BIT_SHIFT_MWCR_MHS)
#define BIT_INVC_MWCR_MHS (~(BIT_MASK_MWCR_MHS << BIT_SHIFT_MWCR_MHS))
// SER 0x10 // Variable Length
#define BIT_SHIFT_SER_SER 0
#define BIT_MASK_SER_SER 0xFF
#define BIT_SER_SER(x)(((x) & BIT_MASK_SER_SER) << BIT_SHIFT_SER_SER)
#define BIT_INVC_SER_SER (~(BIT_MASK_SER_SER << BIT_SHIFT_SER_SER))
// BAUDR 0x14 // 16 bits
#define BIT_SHIFT_BAUDR_SCKDV 0
#define BIT_MASK_BAUDR_SCKDV 0xFFFF
#define BIT_BAUDR_SCKDV(x)(((x) & BIT_MASK_BAUDR_SCKDV) << BIT_SHIFT_BAUDR_SCKDV)
#define BIT_INVC_BAUDR_SCKDV (~(BIT_MASK_BAUDR_SCKDV << BIT_SHIFT_BAUDR_SCKDV))
// TXFLTR 0x18 // Variable Length
#define BIT_SHIFT_TXFTLR_TFT 0
#define BIT_MASK_TXFTLR_TFT 0x3F // (TX_ABW-1):0
#define BIT_TXFTLR_TFT(x)(((x) & BIT_MASK_TXFTLR_TFT) << BIT_SHIFT_TXFTLR_TFT)
#define BIT_INVC_TXFTLR_TFT (~(BIT_MASK_TXFTLR_TFT << BIT_SHIFT_TXFTLR_TFT))
// RXFLTR 0x1c // Variable Length
#define BIT_SHIFT_RXFTLR_RFT 0
#define BIT_MASK_RXFTLR_RFT 0x3F // (RX_ABW-1):0
#define BIT_RXFTLR_RFT(x)(((x) & BIT_MASK_RXFTLR_RFT) << BIT_SHIFT_RXFTLR_RFT)
#define BIT_INVC_RXFTLR_RFT (~(BIT_MASK_RXFTLR_RFT << BIT_SHIFT_RXFTLR_RFT))
// TXFLR 0x20 // see [READ ONLY]
#define BIT_MASK_TXFLR_TXTFL 0x7F // (TX_ABW):0
// RXFLR 0x24 // see [READ ONLY]
#define BIT_MASK_RXFLR_RXTFL 0x7F // (RX_ABW):0
// SR 0x28 // 7 bits [READ ONLY]
#define BIT_SR_BUSY BIT0
#define BIT_SR_TFNF BIT1
#define BIT_SR_TFE BIT2
#define BIT_SR_RFNE BIT3
#define BIT_SR_RFF BIT4
#define BIT_SR_TXE BIT5
#define BIT_SR_DCOL BIT6
// IMR 0x2c // see
#define BIT_SHIFT_IMR_TXEIM 0
#define BIT_MASK_IMR_TXEIM 0x1
// #define BIT_IMR_TXEIM(x)(((x) & BIT_MASK_IMR_TXEIM) << BIT_SHIFT_IMR_TXEIM)
#define BIT_INVC_IMR_TXEIM (~(BIT_MASK_IMR_TXEIM << BIT_SHIFT_IMR_TXEIM))
#define BIT_SHIFT_IMR_TXOIM 1
#define BIT_MASK_IMR_TXOIM 0x1
// #define BIT_IMR_TXOIM(x)(((x) & BIT_MASK_IMR_TXOIM) << BIT_SHIFT_IMR_TXOIM)
#define BIT_INVC_IMR_TXOIM (~(BIT_MASK_IMR_TXOIM << BIT_SHIFT_IMR_TXOIM))
#define BIT_SHIFT_IMR_RXUIM 2
#define BIT_MASK_IMR_RXUIM 0x1
// #define BIT_IMR_RXUIM(x)(((x) & BIT_MASK_IMR_RXUIM) << BIT_SHIFT_IMR_RXUIM)
#define BIT_INVC_IMR_RXUIM (~(BIT_MASK_IMR_RXUIM << BIT_SHIFT_IMR_RXUIM))
#define BIT_SHIFT_IMR_RXOIM 3
#define BIT_MASK_IMR_RXOIM 0x1
// #define BIT_IMR_RXOIM(x)(((x) & BIT_MASK_IMR_RXOIM) << BIT_SHIFT_IMR_RXOIM)
#define BIT_INVC_IMR_RXOIM (~(BIT_MASK_IMR_RXOIM << BIT_SHIFT_IMR_RXOIM))
#define BIT_SHIFT_IMR_RXFIM 4
#define BIT_MASK_IMR_RXFIM 0x1
// #define BIT_IMR_RXFIM(x)(((x) & BIT_MASK_IMR_RXFIM) << BIT_SHIFT_IMR_RXFIM)
#define BIT_INVC_IMR_RXFIM (~(BIT_MASK_IMR_RXFIM << BIT_SHIFT_IMR_RXFIM))
#define BIT_SHIFT_IMR_MSTIM 5
#define BIT_MASK_IMR_MSTIM 0x1
// #define BIT_IMR_MSTIM(x)(((x) & BIT_MASK_IMR_MSTIM) << BIT_SHIFT_IMR_MSTIM)
#define BIT_INVC_IMR_MSTIM (~(BIT_MASK_IMR_MSTIM << BIT_SHIFT_IMR_MSTIM))
#define BIT_IMR_TXEIM BIT0
#define BIT_IMR_TXOIM BIT1
#define BIT_IMR_RXUIM BIT2
#define BIT_IMR_RXOIM BIT3
#define BIT_IMR_RXFIM BIT4
#define BIT_IMR_MSTIM BIT5
// ISR 0x30 // 6 bits [READ ONLY]
#define BIT_ISR_TXEIS BIT0
#define BIT_ISR_TXOIS BIT1
#define BIT_ISR_RXUIS BIT2
#define BIT_ISR_RXOIS BIT3
#define BIT_ISR_RXFIS BIT4
#define BIT_ISR_MSTIS BIT5
// RISR 0x34 // 6 bits [READ ONLY]
#define BIT_RISR_TXEIR BIT0
#define BIT_RISR_TXOIR BIT1
#define BIT_RISR_RXUIR BIT2
#define BIT_RISR_RXOIR BIT3
#define BIT_RISR_RXFIR BIT4
#define BIT_RISR_MSTIR BIT5
// TXOICR 0x38 // 1 bits [READ ONLY]
// RXOICR 0x3c // 1 bits [READ ONLY]
// RXUICR 0x40 // 1 bits [READ ONLY]
// MSTICR 0x44 // 1 bits [READ ONLY]
// ICR 0x48 // 1 bits [READ ONLY]
// DMACR 0x4c // 2 bits
#define BIT_SHIFT_DMACR_RDMAE 0
#define BIT_MASK_DMACR_RDMAE 0x1
#define BIT_DMACR_RDMAE(x)(((x) & BIT_MASK_DMACR_RDMAE) << BIT_SHIFT_DMACR_RDMAE)
#define BIT_INVC_DMACR_RDMAE (~(BIT_MASK_DMACR_RDMAE << BIT_SHIFT_DMACR_RDMAE))
#define BIT_SHIFT_DMACR_TDMAE 1
#define BIT_MASK_DMACR_TDMAE 0x1
#define BIT_DMACR_TDMAE(x)(((x) & BIT_MASK_DMACR_TDMAE) << BIT_SHIFT_DMACR_TDMAE)
#define BIT_INVC_DMACR_TDMAE (~(BIT_MASK_DMACR_TDMAE << BIT_SHIFT_DMACR_TDMAE))
// DMATDLR 0x50
#define BIT_SHIFT_DMATDLR_DMATDL 0
#define BIT_MASK_DMATDLR_DMATDL 0x3F // (TX_ABW-1):0
#define BIT_DMATDLR_DMATDL(x)(((x) & BIT_MASK_DMATDLR_DMATDL) << BIT_SHIFT_DMATDLR_DMATDL)
#define BIT_INVC_DMATDLR_DMATDL (~(BIT_MASK_DMATDLR_DMATDL << BIT_SHIFT_DMATDLR_DMATDL))
// DMARDLR 0x54
#define BIT_SHIFT_DMARDLR_DMARDL 0
#define BIT_MASK_DMARDLR_DMARDL 0x3F // (RX_ABW-1):0
#define BIT_DMARDLR_DMARDL(x)(((x) & BIT_MASK_DMARDLR_DMARDL) << BIT_SHIFT_DMARDLR_DMARDL)
#define BIT_INVC_DMARDLR_DMARDL (~(BIT_MASK_DMARDLR_DMARDL << BIT_SHIFT_DMARDLR_DMARDL))
// IDR 0x58 // 32 bits [READ ONLY]
// COMP_VERSION 0x5c // 32 bits [READ ONLY]
// DR 0x60 // 16 bits 0x60-0xEC
#define BIT_SHIFT_DR_DR 0
#define BIT_MASK_DR_DR 0xFFFF
#define BIT_DR_DR(x)(((x) & BIT_MASK_DR_DR) << BIT_SHIFT_DR_DR)
#define BIT_INVC_DR_DR (~(BIT_MASK_DR_DR << BIT_SHIFT_DR_DR))
// RX_SAMPLE_DLY 0xF0 // 8 bits
#define BIT_SHIFT_RX_SAMPLE_DLY_RSD 0
#define BIT_MASK_RX_SAMPLE_DLY_RSD 0xFFFF
#define BIT_RX_SAMPLE_DLY_RSD(x)(((x) & BIT_MASK_RX_SAMPLE_DLY_RSD) << BIT_SHIFT_RX_SAMPLE_DLY_RSD)
#define BIT_INVC_RX_SAMPLE_DLY_RSD (~(BIT_MASK_RX_SAMPLE_DLY_RSD << BIT_SHIFT_RX_SAMPLE_DLY_RSD))
// RSVD_0 0xF4 // 32 bits
// RSVD_1 0xF8 // 32 bits
// RSVD_2 0xFC // 32 bits
// SSI0 Pinmux
#define BIT_SHIFT_SSI0_PIN_EN 0
#define BIT_MASK_SSI0_PIN_EN 0x1
#define BIT_SSI0_PIN_EN(x)(((x) & BIT_MASK_SSI0_PIN_EN) << BIT_SHIFT_SSI0_PIN_EN)
#define BIT_INVC_SSI0_PIN_EN (~(BIT_MASK_SSI0_PIN_EN << BIT_SHIFT_SSI0_PIN_EN))
#define BIT_SHIFT_SSI0_PIN_SEL 1
#define BIT_MASK_SSI0_PIN_SEL 0x7
#define BIT_SSI0_PIN_SEL(x)(((x) & BIT_MASK_SSI0_PIN_SEL) << BIT_SHIFT_SSI0_PIN_SEL)
#define BIT_INVC_SSI0_PIN_SEL (~(BIT_MASK_SSI0_PIN_SEL << BIT_SHIFT_SSI0_PIN_SEL))
// SSI1 Pinmux
#define BIT_SHIFT_SSI1_PIN_EN 4
#define BIT_MASK_SSI1_PIN_EN 0x1
#define BIT_SSI1_PIN_EN(x)(((x) & BIT_MASK_SSI1_PIN_EN) << BIT_SHIFT_SSI1_PIN_EN)
#define BIT_INVC_SSI1_PIN_EN (~(BIT_MASK_SSI1_PIN_EN << BIT_SHIFT_SSI1_PIN_EN))
#define BIT_SHIFT_SSI1_PIN_SEL 5
#define BIT_MASK_SSI1_PIN_SEL 0x7
#define BIT_SSI1_PIN_SEL(x)(((x) & BIT_MASK_SSI1_PIN_SEL) << BIT_SHIFT_SSI1_PIN_SEL)
#define BIT_INVC_SSI1_PIN_SEL (~(BIT_MASK_SSI1_PIN_SEL << BIT_SHIFT_SSI1_PIN_SEL))
// SSI2 Pinmux
#define BIT_SHIFT_SSI2_PIN_EN 8
#define BIT_MASK_SSI2_PIN_EN 0x1
#define BIT_SSI2_PIN_EN(x)(((x) & BIT_MASK_SSI2_PIN_EN) << BIT_SHIFT_SSI2_PIN_EN)
#define BIT_INVC_SSI2_PIN_EN (~(BIT_MASK_SSI2_PIN_EN << BIT_SHIFT_SSI2_PIN_EN))
#define BIT_SHIFT_SSI2_PIN_SEL 9
#define BIT_MASK_SSI2_PIN_SEL 0x7
#define BIT_SSI2_PIN_SEL(x)(((x) & BIT_MASK_SSI2_PIN_SEL) << BIT_SHIFT_SSI2_PIN_SEL)
#define BIT_INVC_SSI2_PIN_SEL (~(BIT_MASK_SSI2_PIN_SEL << BIT_SHIFT_SSI2_PIN_SEL))
// SSI0 Multiple Chip Selection (Pinmux Select is controlled by BIT_SSI0_PIN_SEL)
#define BIT_SHIFT_SSI0_MULTI_CS_EN 28
#define BIT_MASK_SSI0_MULTI_CS_EN 0x1
#define BIT_SSI0_MULTI_CS_EN(x)(((x) & BIT_MASK_SSI0_MULTI_CS_EN) << BIT_SHIFT_SSI0_MULTI_CS_EN)
#define BIT_INVC_SSI0_MULTI_CS_EN (~(BIT_MASK_SSI0_MULTI_CS_EN << BIT_SHIFT_SSI0_MULTI_CS_EN))
#define HAL_SSI_READ32(SsiIndex, addr) \
HAL_READ32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
#define HAL_SSI_WRITE32(SsiIndex, addr, value) \
HAL_WRITE32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
#define HAL_SSI_READ16(SsiIndex, addr) \
HAL_READ16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
#define HAL_SSI_WRITE16(SsiIndex, addr, value) \
HAL_WRITE16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
#define HAL_SSI_READ8(SsiIndex, addr) \
HAL_READ8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
#define HAL_SSI_WRITE8(SsiIndex, addr, value) \
HAL_WRITE8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
// SSI Pinmux Select
enum _SSI0_PINMUX_SELECT_ {
SSI0_MUX_TO_GPIOE = S0,
SSI0_MUX_TO_GPIOC = S1
};
typedef uint32_t SSI0_PINMUX_SELECT;
typedef uint32_t *PSSI0_PINMUX_SELECT;
enum _SSI1_PINMUX_SELECT_ {
SSI1_MUX_TO_GPIOA = S0,
SSI1_MUX_TO_GPIOB = S1,
SSI1_MUX_TO_GPIOD = S2
};
typedef uint32_t SSI1_PINMUX_SELECT;
typedef uint32_t *PSSI1_PINMUX_SELECT;
enum _SSI2_PINMUX_SELECT_ {
SSI2_MUX_TO_GPIOG = S0,
SSI2_MUX_TO_GPIOE = S1,
SSI2_MUX_TO_GPIOD = S2
};
typedef uint32_t SSI2_PINMUX_SELECT;
typedef uint32_t *PSSI2_PINMUX_SELECT;
enum _SSI0_MULTI_CS_PINMUX_SELECT_ {
SSI0_CS_MUX_TO_GPIOE = S0,
SSI0_CS_MUX_TO_GPIOC = S1
};
typedef uint32_t SSI0_MULTI_CS_PINMUX_SELECT;
typedef uint32_t *PSSI0_MULTI_CS_PINMUX_SELECT;
enum _SSI_CTRLR0_TMOD_ {
TMOD_TR = 0,
TMOD_TO = 1,
TMOD_RO = 2,
TMOD_EEPROM_R = 3
};
typedef uint32_t SSI_CTRLR0_TMOD;
typedef uint32_t *PSSI_CTRLR0_TMOD;
enum _SSI_CTRLR0_SCPOL_ {
SCPOL_INACTIVE_IS_LOW = 0,
SCPOL_INACTIVE_IS_HIGH = 1
};
typedef uint32_t SSI_CTRLR0_SCPOL;
typedef uint32_t *PSSI_CTRLR0_SCPOL;
enum _SSI_CTRLR0_SCPH_ {
SCPH_TOGGLES_IN_MIDDLE = 0,
SCPH_TOGGLES_AT_START = 1
};
typedef uint32_t SSI_CTRLR0_SCPH;
typedef uint32_t *PSSI_CTRLR0_SCPH;
enum _SSI_CTRLR0_DFS_ {
DFS_4_BITS = 3,
DFS_5_BITS = 4,
DFS_6_BITS = 5,
DFS_7_BITS = 6,
DFS_8_BITS = 7,
DFS_9_BITS = 8,
DFS_10_BITS = 9,
DFS_11_BITS = 10,
DFS_12_BITS = 11,
DFS_13_BITS = 12,
DFS_14_BITS = 13,
DFS_15_BITS = 14,
DFS_16_BITS = 15,
};
typedef uint32_t SSI_CTRLR0_DFS;
typedef uint32_t *PSSI_CTRLR0_DFS;
enum _SSI_CTRLR0_CFS_ {
CFS_1_BIT = 0,
CFS_2_BITS = 1,
CFS_3_BITS = 2,
CFS_4_BITS = 3,
CFS_5_BITS = 4,
CFS_6_BITS = 5,
CFS_7_BITS = 6,
CFS_8_BITS = 7,
CFS_9_BITS = 8,
CFS_10_BITS = 9,
CFS_11_BITS = 10,
CFS_12_BITS = 11,
CFS_13_BITS = 12,
CFS_14_BITS = 13,
CFS_15_BITS = 14,
CFS_16_BITS = 15
};
typedef uint32_t SSI_CTRLR0_CFS;
typedef uint32_t *PSSI_CTRLR0_CFS;
enum _SSI_CTRLR0_SLV_OE_ {
SLV_TXD_ENABLE = 0,
SLV_TXD_DISABLE = 1
};
typedef uint32_t SSI_CTRLR0_SLV_OE;
typedef uint32_t *PSSI_CTRLR0_SLV_OE;
enum _SSI_ROLE_SELECT_ {
SSI_SLAVE = 0,
SSI_MASTER = 1
};
typedef uint32_t SSI_ROLE_SELECT;
typedef uint32_t *PSSI_ROLE_SELECT;
enum _SSI_FRAME_FORMAT_ {
FRF_MOTOROLA_SPI = 0,
FRF_TI_SSP = 1,
FRF_NS_MICROWIRE = 2,
FRF_RSVD = 3
};
typedef uint32_t SSI_FRAME_FORMAT;
typedef uint32_t *PSSI_FRAME_FORMAT;
enum _SSI_DMACR_ENABLE_ {
SSI_NODMA = 0,
SSI_RXDMA_ENABLE = 1,
SSI_TXDMA_ENABLE = 2,
SSI_TRDMA_ENABLE = 3
};
typedef uint32_t SSI_DMACR_ENABLE;
typedef uint32_t *PSSI_DMACR_ENABLE;
enum _SSI_MWCR_HANDSHAKE_ {
MW_HANDSHAKE_DISABLE = 0,
MW_HANDSHAKE_ENABLE = 1
};
typedef uint32_t SSI_MWCR_HANDSHAKE;
typedef uint32_t *PSSI_MWCR_HANDSHAKE;
enum _SSI_MWCR_DIRECTION_ {
MW_DIRECTION_SLAVE_TO_MASTER = 0,
MW_DIRECTION_MASTER_TO_SLAVE = 1
};
typedef uint32_t SSI_MWCR_DIRECTION;
typedef uint32_t *PSSI_MWCR_DIRECTION;
enum _SSI_MWCR_TMOD_ {
MW_TMOD_NONSEQUENTIAL = 0,
MW_TMOD_SEQUENTIAL = 1
};
typedef uint32_t SSI_MWCR_TMOD;
typedef uint32_t *PSSI_MWCR_TMOD;
enum _SSI_DATA_TRANSFER_MECHANISM_ {
SSI_DTM_BASIC,
SSI_DTM_INTERRUPT,
SSI_DTM_DMA
};
typedef uint32_t SSI_DATA_TRANSFER_MECHANISM;
typedef uint32_t *PSSI_DATA_TRANSFER_MECHANISM;
_LONG_CALL_ HAL_Status HalSsiPinmuxEnableRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ HAL_Status HalSsiEnableRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ HAL_Status HalSsiDisableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiInitRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetSclkPolarityRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetSclkPhaseRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiWriteRtl8195a(VOID *Adaptor, u32 value);
_LONG_CALL_ HAL_Status HalSsiLoadSettingRtl8195a(VOID *Adaptor, VOID *Setting);
_LONG_CALL_ROM_ HAL_Status HalSsiSetInterruptMaskRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetDeviceRoleRtl8195a(VOID *Adaptor, u32 Role);
_LONG_CALL_ HAL_Status HalSsiInterruptEnableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiInterruptDisableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiReadInterruptRtl8195a(VOID *Adaptor, VOID *RxData, u32 Length);
_LONG_CALL_ROM_ HAL_Status HalSsiSetRxFifoThresholdLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetTxFifoThresholdLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiWriteInterruptRtl8195a(VOID *Adaptor, VOID *TxData, u32 Length);
_LONG_CALL_ROM_ HAL_Status HalSsiSetSlaveEnableRegisterRtl8195a(VOID *Adaptor, u32 SlaveIndex);
_LONG_CALL_ROM_ u32 HalSsiBusyRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ u32 HalSsiWriteableRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ u32 HalSsiReadableRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ u32 HalSsiGetInterruptMaskRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ u32 HalSsiGetRxFifoLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetTxFifoLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ u32 HalSsiGetStatusRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ u32 HalSsiGetInterruptStatusRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiReadRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetRawInterruptStatusRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ u32 HalSsiGetSlaveEnableRegisterRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ VOID _SsiReadInterrupt(VOID *Adaptor);
_LONG_CALL_ROM_ VOID _SsiWriteInterrupt(VOID *Adaptor);
_LONG_CALL_ u32 _SsiIrqHandle(VOID *Adaptor);
// ROM code patch
VOID _SsiReadInterruptRtl8195a(VOID *Adapter);
VOID _SsiWriteInterruptRtl8195a(VOID *Adapter);
HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor);
HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor);
HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor);
HAL_Status HalSsiDeInitRtl8195a(VOID * Adapter);
HAL_Status HalSsiClockOffRtl8195a(VOID * Adapter);
HAL_Status HalSsiClockOnRtl8195a(VOID * Adapter);
VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate);
HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length);
HAL_Status HalSsiIntWriteRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
VOID HalSsiTxFIFOThresholdRtl8195a(VOID *Adaptor, u32 txftl);
HAL_Status HalSsiEnterCriticalRtl8195a(VOID * Data);
HAL_Status HalSsiExitCriticalRtl8195a(VOID * Data);
HAL_Status HalSsiIsTimeoutRtl8195a(u32 StartCount, u32 TimeoutCnt);
HAL_Status HalSsiStopRecvRtl8195a(VOID * Data);
#if CONFIG_CHIP_E_CUT
HAL_Status HalSsiPinmuxEnableRtl8195a_V04(VOID *Adaptor);
HAL_Status HalSsiPinmuxDisableRtl8195a_V04(VOID * Adaptor);
VOID _SsiReadInterruptRtl8195a_V04(VOID *Adapter);
VOID _SsiWriteInterruptRtl8195a_V04(VOID *Adapter);
HAL_Status HalSsiInitRtl8195a_V04(VOID *Adaptor);
HAL_Status HalSsiSetFormatRtl8195a_V04(VOID * Adaptor);
HAL_Status HalSsiDeInitRtl8195a_V04(VOID *Adapter);
HAL_Status HalSsiIntReadRtl8195a_V04(VOID *Adapter, VOID *RxData, u32 Length);
HAL_Status HalSsiIntWriteRtl8195a_V04(VOID *Adapter, u8 *pTxData, u32 Length);
HAL_Status HalSsiClockOffRtl8195a_V04(VOID * Adapter);
HAL_Status HalSsiClockOnRtl8195a_V04(VOID * Adapter);
VOID HalSsiSetSclkRtl8195a_V04(VOID *Adapter, u32 ClkRate);
VOID HalSsiTxGdmaLoadDefRtl8195a_V04(IN VOID * Adapter);
VOID HalSsiRxGdmaLoadDefRtl8195a_V04(IN VOID * Adapter);
VOID HalSsiDmaInitRtl8195a_V04(VOID *Adapter);
HAL_Status HalSsiDmaSendRtl8195a_V04(IN VOID * Adapter, IN u8 * pTxData, IN u32 Length);
HAL_Status HalSsiDmaRecvRtl8195a_V04(IN VOID * Adapter, IN u8 * pRxData, IN u32 Length);
HAL_Status HalSsiDmaSendMultiBlockRtl8195a_V04(VOID * Adapter, u8 * pTxData, u32 Length);
HAL_Status HalSsiDmaRecvMultiBlockRtl8195a_V04(VOID * Adapter, u8 * pRxData, u32 Length);
#endif
#if CONFIG_GDMA_EN
VOID HalSsiTxGdmaLoadDefRtl8195a(VOID *Adapter);
VOID HalSsiRxGdmaLoadDefRtl8195a(VOID *Adapter);
VOID HalSsiDmaInitRtl8195a(VOID *Adapter);
HAL_Status HalSsiDmaSendRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
HAL_Status HalSsiDmaRecvRtl8195a(VOID *Adapter, u8 *pRxData, u32 Length);
HAL_Status HalSsiDmaSendMultiBlockRtl8195a(VOID * Adapter, u8 * pRxData, u32 Length);
HAL_Status HalSsiDmaRecvMultiBlockRtl8195a(VOID * Adapter, u8 * pRxData, u32 Length);
#endif // end of "#ifdef CONFIG_GDMA_EN"
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_sys_on.h Normal file
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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_timer.h Normal file
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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
#ifndef _RTL8195A_TIMER_H_
#define _RTL8195A_TIMER_H_
#define TIMER_TICK_US 31
#define TIMER_LOAD_COUNT_OFF 0x00
#define TIMER_CURRENT_VAL_OFF 0x04
#define TIMER_CTL_REG_OFF 0x08
#define TIMER_EOI_OFF 0x0c
#define TIMER_INT_STATUS_OFF 0x10
#define TIMER_INTERVAL 0x14
#define TIMERS_INT_STATUS_OFF 0xa0
#define TIMERS_EOI_OFF 0xa4
#define TIMERS_RAW_INT_STATUS_OFF 0xa8
#define TIMERS_COMP_VER_OFF 0xac
#define MAX_TIMER_VECTOR_TABLE_NUM 6
#define HAL_TIMER_READ32(addr) (*((volatile u32*)(TIMER_REG_BASE + addr)))//HAL_READ32(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE32(addr, value) ((*((volatile u32*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE32(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ16(addr) (*((volatile u16*)(TIMER_REG_BASE + addr)))//HAL_READ16(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE16(addr, value) ((*((volatile u16*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE16(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ8(addr) (*((volatile u8*)(TIMER_REG_BASE + addr)))//HAL_READ8(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE8(addr, value) ((*((volatile u8*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE8(TIMER_REG_BASE, addr, value)
_LONG_CALL_ u32
HalGetTimerIdRtl8195a(
IN u32 *TimerID
);
_LONG_CALL_ BOOL
HalTimerInitRtl8195a(
IN VOID *Data
);
_LONG_CALL_ u32
HalTimerReadCountRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerIrqClearRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDisRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerEnRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDumpRegRtl8195a(
IN u32 TimerId
);
// ROM Code patch
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
);
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
);
VOID
HalTimerClearIsrRtl8195a(
IN u32 TimerId
);
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
);
#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT)
__weak _LONG_CALL_
VOID
HalTimerIrq2To7HandleV02(
IN VOID *Data
);
__weak _LONG_CALL_ROM_
HAL_Status
HalTimerIrqRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
HAL_Status
HalTimerInitRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
u32
HalTimerReadCountRtl8195aV02(
IN u32 TimerId
);
__weak _LONG_CALL_
VOID
HalTimerReLoadRtl8195aV02(
IN u32 TimerId,
IN u32 LoadUs
);
__weak _LONG_CALL_ROM_
HAL_Status
HalTimerIrqUnRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
VOID
HalTimerDeInitRtl8195aV02(
IN VOID *Data
);
#endif // end of "#ifdef CONFIG_CHIP_C_CUT"
#ifdef CONFIG_CHIP_E_CUT
_LONG_CALL_ VOID
HalTimerReLoadRtl8195a_V04(
IN u32 TimerId,
IN u32 LoadUs
);
_LONG_CALL_ HAL_Status
HalTimerInitRtl8195a_V04(
IN VOID *Data
);
#endif // #ifdef CONFIG_CHIP_E_CUT
// HAL functions wrapper
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
static __inline HAL_Status
HalTimerInit(
IN VOID *Data
)
{
#ifdef CONFIG_CHIP_E_CUT
return (HalTimerInitRtl8195a_V04(Data));
#else
return (HalTimerInitRtl8195a_Patch(Data));
#endif
}
static __inline VOID
HalTimerEnable(
IN u32 TimerId
)
{
HalTimerIrqEnRtl8195a(TimerId);
HalTimerEnRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerDisable(
IN u32 TimerId
)
{
HalTimerDisRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerClearIsr(
IN u32 TimerId
)
{
HalTimerClearIsrRtl8195a(TimerId);
}
static __inline VOID
HalTimerReLoad(
IN u32 TimerId,
IN u32 LoadUs
)
{
#ifdef CONFIG_CHIP_E_CUT
HalTimerReLoadRtl8195a_V04(TimerId, LoadUs);
#else
HalTimerReLoadRtl8195a_Patch(TimerId, LoadUs);
#endif
}
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195a_Patch(Data);
}
#else
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195aV02(Data);
}
#endif // end of "#ifndef CONFIG_CHIP_C_CUT"
#endif // #ifndef CONFIG_RELEASE_BUILD_LIBRARIES
#endif //_RTL8195A_TIMER_H_

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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_RTL8195A_TRAP_H
#define MBED_RTL8195A_TRAP_H
typedef void (*VECTOR_Func)(void *data);
typedef struct {
void (*RamStartFun)(void);
} RAM_START_FUNCTION;
typedef struct {
void (*RamStartFun)(void);
void (*RamWakeupFun)(void);
void (*RamPatchFun0)(void);
void (*RamPatchFun1)(void);
void (*RamPatchFun2)(void);
} RAM_START_TABLE;
extern uint8_t * __ram_table_start__;
extern __longcall void HalWdgIntrHandle(void);
extern __longcall void HalHardFaultHandler(u32);
#define __TRAP_Init VectorTableInitForOSRtl8195A
#define __TRAP_SetVector VectorTableInitRtl8195A
#define __TRAP_HardFaultHandler HalHardFaultHandler
#define __INTR_Register VectorIrqRegisterRtl8195A
#define __INTR_Unregister VectorIrqUnRegisterRtl8195A
#define __INTR_Enable VectorIrqEnRtl8195A
#define __INTR_Disable VectorIrqDisRtl8195A
#define __INTR_WatchdogHandler HalWdgIntrHandle
// Interface for HAL layer
static inline void TRAP_Init(void *svc, void *svh, void *tick)
{
__TRAP_Init(svc, svh, tick);
}
static inline void TRAP_SetVector(uint32_t stackp)
{
__TRAP_SetVector(stackp);
}
static inline bool INTR_Register(IRQ_Handle *handle)
{
return __INTR_Register(handle);
}
static inline bool INTR_Unregister(IRQ_Handle *handle)
{
return __INTR_Unregister(handle);
}
static inline void INTR_Enable(IRQ_Handle *handle)
{
__INTR_Enable(handle);
}
static inline void INTR_Disable(IRQ_Handle *handle)
{
__INTR_Disable(handle);
}
static inline void INTR_WatchdogHandler(void)
{
__INTR_WatchdogHandler();
}
#endif

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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _RTL8195A_UART_H_
#define _RTL8195A_UART_H_
#define MAX_UART_INDEX 2
#define RUART_DLL_OFF 0x00
#define RUART_DLM_OFF 0x04 //RW, DLAB = 1
#define RUART_INTERRUPT_EN_REG_OFF 0x04
#define RUART_IER_ERBI 0x01 //BIT0, Enable Received Data Available Interrupt (rx trigger)
#define RUART_IER_ETBEI (1<<1) //BIT1, Enable Transmitter FIFO Empty Interrupt (tx fifo empty)
#define RUART_IER_ELSI (1<<2) //BIT2, Enable Receiver Line Status Interrupt (receiver line status)
#define RUART_IER_EDSSI (1<<3) //BIT3, Enable Modem Status Interrupt (modem status transition)
#define RUART_INT_ID_REG_OFF 0x08 //[R]
#define RUART_IIR_INT_PEND 0x01
#define RUART_IIR_INT_ID (0x07<<1) //011(3), 010(2), 110(6), 001(1), 000(0)
#define RUART_FIFO_CTL_REG_OFF 0x08 //[W]
#define RUART_FIFO_CTL_REG_FIFO_ENABLE 0x01 //BIT0
#define RUART_FIFO_CTL_REG_CLEAR_RXFIFO (1<<1) //BIT1, 0x02, Write 1 clear
#define RUART_FIFO_CTL_REG_CLEAR_TXFIFO (1<<2) //BIT2, 0x04, Write 1 clear
#define RUART_FIFO_CTL_REG_DMA_ENABLE 0x08 //BIT3
#define FIFO_CTL_DEFAULT_WITH_FIFO_DMA 0xC9
#define FIFO_CTL_DEFAULT_WITH_FIFO 0xC1
#define RUART_MODEM_CTL_REG_OFF 0x10
#define RUART_MCR_RTS BIT1
#define RUART_MCL_AUTOFLOW_ENABLE (1<<5) //BIT5, 0x20
#define RUART_LINE_CTL_REG_OFF 0x0C
#define RUART_LINE_CTL_REG_DLAB_ENABLE (1<<7) //BIT7, 0x80
#define RUART_LINE_STATUS_REG_OFF 0x14
#define RUART_LINE_STATUS_REG_DR 0x01 //BIT0, Data Ready indicator
#define RUART_LINE_STATUS_ERR_OVERRUN (1<<1) //BIT1, Over Run
#define RUART_LINE_STATUS_ERR_PARITY (1<<2) //BIT2, Parity error
#define RUART_LINE_STATUS_ERR_FRAMING (1<<3) //BIT3, Framing error
#define RUART_LINE_STATUS_ERR_BREAK (1<<4) //BIT4, Break interrupt error
#define RUART_LINE_STATUS_REG_THRE (1<<5) //BIT5, 0x20, Transmit Holding Register Empty Interrupt enable
#define RUART_LINE_STATUS_REG_TEMT (1<<6) //BIT6, 0x40, Transmitter Empty indicator(bit)
#define RUART_LINE_STATUS_ERR_RXFIFO (1<<7) //BIT7, RX FIFO error
#define RUART_LINE_STATUS_ERR (RUART_LINE_STATUS_ERR_OVERRUN|RUART_LINE_STATUS_ERR_PARITY| \
RUART_LINE_STATUS_ERR_FRAMING|RUART_LINE_STATUS_ERR_BREAK| \
RUART_LINE_STATUS_ERR_RXFIFO) //Line status error
#define RUART_MODEM_STATUS_REG_OFF 0x18 //Modem Status Register
#define RUART_SCRATCH_PAD_REG_OFF 0x1C //Scratch Pad Register
#define RUART_SP_REG_RXBREAK_INT_STATUS (1<<7) //BIT7, 0x80, Write 1 clear
#define RUART_SP_REG_DBG_SEL (0x0F<<8) //[11:8], Debug port selection
#define RUART_SP_REG_XFACTOR_ADJ (0x7FF<<16) //[26:16]
#define RUART_STS_REG_OFF 0x20
#define RUART_STS_REG_RESET_RCV (1<<3) //BIT3, 0x08, Reset Uart Receiver
#define RUART_STS_REG_XFACTOR 0xF<<4
#define RUART_REV_BUF_REG_OFF 0x24 //Receiver Buffer Register
#define RUART_TRAN_HOLD_REG_OFF 0x24 //Transmitter Holding Register
#define RUART_MISC_CTL_REG_OFF 0x28
#define RUART_TXDMA_BURSTSIZE_MASK 0xF8 //7:3
#define RUART_RXDMA_BURSTSIZE_MASK 0x1F00 //12:8
#define RUART_DEBUG_REG_OFF 0x3C
// RUART_LINE_CTL_REG_OFF (0x0C)
#define BIT_SHIFT_LCR_WLS 0 // word length select: 0: 7 bits, 1: 8bits
#define BIT_MASK_LCR_WLS_8BITS 0x1
#define BIT_LCR_WLS(x)(((x) & BIT_MASK_LCR_WLS_8BITS) << BIT_SHIFT_LCR_WLS)
#define BIT_CLR_LCR_WLS (~(BIT_MASK_LCR_WLS_8BITS << BIT_SHIFT_LCR_WLS))
#define BIT_SHIFT_LCR_STB 2 // Stop bit select: 0: no stop bit, 1: 1 stop bit
#define BIT_MASK_LCR_STB_EN 0x1
#define BIT_LCR_STB_EN(x)(((x) & BIT_MASK_LCR_STB_EN) << BIT_SHIFT_LCR_STB)
#define BIT_INVC_LCR_STB_EN (~(BIT_MASK_LCR_STB_EN << BIT_SHIFT_LCR_STB))
#define BIT_SHIFT_LCR_PARITY_EN 3
#define BIT_MASK_LCR_PARITY_EN 0x1
#define BIT_LCR_PARITY_EN(x)(((x) & BIT_MASK_LCR_PARITY_EN) << BIT_SHIFT_LCR_PARITY_EN)
#define BIT_INVC_LCR_PARITY_EN (~(BIT_MASK_LCR_PARITY_EN << BIT_SHIFT_LCR_PARITY_EN))
#define BIT_SHIFT_LCR_PARITY_TYPE 4
#define BIT_MASK_LCR_PARITY_TYPE 0x1
#define BIT_LCR_PARITY_TYPE(x)(((x) & BIT_MASK_LCR_PARITY_TYPE) << BIT_SHIFT_LCR_PARITY_TYPE)
#define BIT_INVC_LCR_PARITY_TYPE (~(BIT_MASK_LCR_PARITY_TYPE << BIT_SHIFT_LCR_PARITY_TYPE))
#define BIT_SHIFT_LCR_STICK_PARITY_EN 5
#define BIT_MASK_LCR_STICK_PARITY_EN 0x1
#define BIT_LCR_STICK_PARITY_EN(x)(((x) & BIT_MASK_LCR_STICK_PARITY_EN) << BIT_SHIFT_LCR_STICK_PARITY_EN)
#define BIT_INVC_LCR_STICK_PARITY_EN (~(BIT_MASK_LCR_STICK_PARITY_EN << BIT_SHIFT_LCR_STICK_PARITY_EN))
#define BIT_SHIFT_LCR_BREAK_CTRL 6
#define BIT_MASK_LCR_BREAK_CTRL 0x1
#define BIT_UART_LCR_BREAK_CTRL ((BIT_MASK_LCR_BREAK_CTRL) << BIT_SHIFT_LCR_BREAK_CTRL)
#define RUART_BAUD_RATE_2400 2400
#define RUART_BAUD_RATE_4800 4800
#define RUART_BAUD_RATE_9600 9600
#define RUART_BAUD_RATE_19200 19200
#define RUART_BAUD_RATE_38400 38400
#define RUART_BAUD_RATE_57600 57600
#define RUART_BAUD_RATE_115200 115200
#define RUART_BAUD_RATE_921600 921600
#define RUART_BAUD_RATE_1152000 1152000
#define HAL_RUART_READ32(UartIndex, addr) \
HAL_READ32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
#define HAL_RUART_WRITE32(UartIndex, addr, value) \
HAL_WRITE32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
#define HAL_RUART_READ16(UartIndex, addr) \
HAL_READ16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
#define HAL_RUART_WRITE16(UartIndex, addr, value) \
HAL_WRITE16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
#define HAL_RUART_READ8(UartIndex, addr) \
HAL_READ8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
#define HAL_RUART_WRITE8(UartIndex, addr, value) \
HAL_WRITE8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
#define UART_OVSR_POOL_MIN 1000
#define UART_OVSR_POOL_MAX 2090
#define DIVISOR_RESOLUTION 10
#define JITTER_LIMIT 100
#define UART_SCLK (200000000*5/12)
typedef struct _RUART_SPEED_SETTING_ {
u32 BaudRate;
u32 Ovsr;
u32 Div;
u32 Ovsr_adj;
#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES))
u8 Ovsr_adj_max_bits; // 9: No parity, 10: with Parity
u8 Ovsr_adj_bits;
u16 *Ovsr_adj_map;
u32 max_err; // 10 ~ 100: 30
u32 Ovsr_min; // 10 ~ 20: 1000
u32 Ovsr_max; // 10 ~ 20: 2000
u32 divisor_resolution; // 1 ~ 20: 10
u32 jitter_lim; // 50 ~ 100: 100
u32 sclk; // 83.33333 MHz
#endif
}RUART_SPEED_SETTING, *PRUART_SPEED_SETTING;
enum _UART_RXFIFO_TRIGGER_LEVEL_ {
OneByte = 0x00,
FourBytes = 0x01,
EightBytes = 0x10,
FourteenBytes = 0x11
};
typedef uint32_t UART_RXFIFO_TRIGGER_LEVEL;
typedef uint32_t *PUART_RXFIFO_TRIGGER_LEVEL;
enum _RUART0_PINMUX_SELECT_ {
RUART0_MUX_TO_GPIOC = S0,
RUART0_MUX_TO_GPIOE = S1,
RUART0_MUX_TO_GPIOA = S2
};
typedef uint32_t RUART0_PINMUX_SELECT;
typedef uint32_t *PRUART0_PINMUX_SELECT;
enum _RUART1_PINMUX_SELECT_ {
RUART1_MUX_TO_GPIOD = S0,
RUART1_MUX_TO_GPIOE = S1,
RUART1_MUX_TO_GPIOB = S2
};
typedef uint32_t RUART1_PINMUX_SELECT;
typedef uint32_t *PRUART1_PINMUX_SELECT;
enum _RUART2_PINMUX_SELECT_ {
RUART2_MUX_TO_GPIOA = S0,
RUART2_MUX_TO_GPIOC = S1,
RUART2_MUX_TO_GPIOD = S2
};
typedef uint32_t RUART2_PINMUX_SELECT;
typedef uint32_t *PRUART2_PINMUX_SELECT;
enum _RUART_FLOW_CONTROL_ {
AUTOFLOW_DISABLE = 0,
AUTOFLOW_ENABLE = 1
};
typedef uint32_t RUART_FLOW_CONTROL;
typedef uint32_t *PRUART_FLOW_CONTROL;
enum _RUART_WORD_LEN_SEL_ {
RUART_WLS_7BITS = 0,
RUART_WLS_8BITS = 1
};
typedef uint32_t RUART_WORD_LEN_SEL;
typedef uint32_t *PRUART_WORD_LEN_SEL;
enum _RUART_STOP_BITS_ {
RUART_STOP_BIT_1 = 0,
RUART_STOP_BIT_2 = 1
};
typedef uint32_t RUART_STOP_BITS;
typedef uint32_t *PRUART_STOP_BITS;
enum _RUART_PARITY_CONTROL_ {
RUART_PARITY_DISABLE = 0,
RUART_PARITY_ENABLE = 1
};
typedef uint32_t RUART_PARITY_CONTROL;
typedef uint32_t *PRUART_PARITY_CONTROL;
enum _RUART_PARITY_TYPE_ {
RUART_ODD_PARITY = 0,
RUART_EVEN_PARITY = 1
};
typedef uint32_t RUART_PARITY_TYPE;
typedef uint32_t *PRUART_PARITY_TYPE;
enum _RUART_STICK_PARITY_CONTROL_ {
RUART_STICK_PARITY_DISABLE = 0,
RUART_STICK_PARITY_ENABLE = 1
};
typedef uint32_t RUART_STICK_PARITY_CONTROL;
typedef uint32_t *PRUART_STICK_PARITY_CONTROL;
enum _UART_INT_ID_ {
ModemStatus = 0,
TxFifoEmpty = 1,
ReceiverDataAvailable = 2,
ReceivLineStatus = 3,
TimeoutIndication = 6
};
typedef uint32_t UART_INT_ID;
typedef uint32_t *PUART_INT_ID;
enum _HAL_UART_State_
{
HAL_UART_STATE_NULL = 0x00, // UART hardware not been initial yet
HAL_UART_STATE_READY = 0x10, // UART is initialed, ready to use
HAL_UART_STATE_BUSY = 0x20, // UART hardware is busy on configuration
HAL_UART_STATE_BUSY_TX = 0x21, // UART is buzy on TX
HAL_UART_STATE_BUSY_RX = 0x22, // UART is busy on RX
HAL_UART_STATE_BUSY_TX_RX = 0x23, // UART is busy on TX an RX
HAL_UART_STATE_TIMEOUT = 0x30, // Transfer timeout
HAL_UART_STATE_ERROR = 0x40 // UART Error
};
typedef uint32_t HAL_UART_State;
typedef uint32_t *PHAL_UART_State;
enum _HAL_UART_Status_
{
HAL_UART_STATUS_OK = 0x00, // Transfer OK
HAL_UART_STATUS_TIMEOUT = 0x01, // Transfer Timeout
HAL_UART_STATUS_ERR_OVERRUN = 0x02, // RX Over run
HAL_UART_STATUS_ERR_PARITY = 0x04, // Parity error
HAL_UART_STATUS_ERR_FRAM = 0x08, // Framing Error
HAL_UART_STATUS_ERR_BREAK = 0x10, // Break Interrupt
HAL_UART_STATUS_ERR_PARA = 0x20, // Parameter error
HAL_UART_STATUS_ERR_RXFIFO = 0x80, // RX FIFO error
};
typedef uint32_t HAL_UART_Status;
typedef uint32_t *PHAL_UART_Status;
u32
HalRuartGetDebugValueRtl8195a(
IN VOID* Data,
IN u32 DbgSel
);
#if 0
u32
FindElementIndex(
u32 Element,
u32* Array
);
#endif
VOID
RuartResetRxFifoRtl8195a(
IN u8 UartIndex
);
#if 0
VOID
RuartBusDomainEnableRtl8195a(
IN u8 UartIndex
);
#endif
HAL_Status
HalRuartResetRxFifoRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartInitRtl8195a(
IN VOID *Data
);
VOID
HalRuartDeInitRtl8195a(
IN VOID *Data ///< RUART Adapter
);
HAL_Status
HalRuartPutCRtl8195a(
IN VOID *Data,
IN u8 TxData
);
u32
HalRuartSendRtl8195a(
IN VOID *Data,
IN u8 *pTxData,
IN u32 Length,
IN u32 Timeout
);
HAL_Status
HalRuartIntSendRtl8195a(
IN VOID *Data, // PHAL_RUART_ADAPTER
IN u8 *pTxData, // the Buffer to be send
IN u32 Length // the length of data to be send
);
HAL_Status
HalRuartDmaSendRtl8195a(
IN VOID *Data, // PHAL_RUART_ADAPTER
IN u8 *pTxData, // the Buffer to be send
IN u32 Length // the length of data to be send
);
HAL_Status
HalRuartStopSendRtl8195a(
IN VOID *Data // PHAL_RUART_ADAPTER
);
HAL_Status
HalRuartGetCRtl8195a(
IN VOID *Data,
OUT u8 *pRxByte
);
u32
HalRuartRecvRtl8195a(
IN VOID *Data,
IN u8 *pRxData,
IN u32 Length,
IN u32 Timeout
);
HAL_Status
HalRuartIntRecvRtl8195a(
IN VOID *Data, ///< RUART Adapter
IN u8 *pRxData, ///< Rx buffer
IN u32 Length // buffer length
);
HAL_Status
HalRuartDmaRecvRtl8195a(
IN VOID *Data, ///< RUART Adapter
IN u8 *pRxData, ///< Rx buffer
IN u32 Length // buffer length
);
HAL_Status
HalRuartStopRecvRtl8195a(
IN VOID *Data // PHAL_RUART_ADAPTER
);
u8
HalRuartGetIMRRtl8195a(
IN VOID *Data
);
_LONG_CALL_ROM_ VOID
HalRuartSetIMRRtl8195a(
IN VOID *Data
);
VOID
HalRuartDmaInitRtl8195a(
IN VOID *Data
);
VOID
HalRuartRTSCtrlRtl8195a(
IN VOID *Data,
IN BOOLEAN RtsCtrl
);
VOID
HalRuartRegIrqRtl8195a(
IN VOID *Data
);
VOID
HalRuartIntEnableRtl8195a(
IN VOID *Data
);
VOID
HalRuartIntDisableRtl8195a(
IN VOID *Data
);
VOID
HalRuartAdapterLoadDefRtl8195a(
IN VOID *pAdp,
IN u8 UartIdx
);
VOID
HalRuartTxGdmaLoadDefRtl8195a(
IN VOID *pAdp,
IN VOID *pCfg
);
VOID
HalRuartRxGdmaLoadDefRtl8195a(
IN VOID *pAdp,
IN VOID *pCfg
);
_LONG_CALL_ HAL_Status HalRuartIntSendRtl8195aV02(
IN VOID *Data, // PHAL_RUART_ADAPTER
IN u8 *pTxData, // the Buffer to be send
IN u32 Length // the length of data to be send
);
_LONG_CALL_ HAL_Status
HalRuartIntRecvRtl8195aV02(
IN VOID *Data, ///< RUART Adapter
IN u8 *pRxData, ///< Rx buffer
IN u32 Length // buffer length
);
_LONG_CALL_ s32
FindElementIndex_v02(
u32 Element, ///< RUART Baudrate
u32* Array, ///< Pre-defined Baudrate Array
u32 ElementNo
);
_LONG_CALL_ HAL_Status HalRuartInitRtl8195a_v02(IN VOID *Data);
// New added function 2015/04/20
HAL_Status
HalRuartResetTxFifoRtl8195a(
IN VOID *Data ///< RUART Adapter
);
HAL_Status
HalRuartResetRxFifoRtl8195a_Patch(
IN VOID *Data ///< RUART Adapter
);
HAL_Status
HalRuartResetTRxFifoRtl8195a(
IN VOID *Data ///< RUART Adapter
);
HAL_Status
HalRuartSetBaudRateRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartEnableRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartDisableRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartFlowCtrlRtl8195a(
IN VOID *Data
);
u32
_UartTxDmaIrqHandle_Patch(
IN VOID *Data
);
u32
_UartRxDmaIrqHandle_Patch(
IN VOID *Data
);
HAL_Status
HalRuartDmaSendRtl8195a_Patch(
IN VOID *Data,
IN u8 *pTxData,
IN u32 Length
);
HAL_Status
HalRuartDmaRecvRtl8195a_Patch(
IN VOID *Data,
IN u8 *pRxData,
IN u32 Length
);
HAL_Status
HalRuartMultiBlkDmaSendRtl8195a(
IN VOID *Data,
IN u8 *pTxData,
IN u32 Length
);
HAL_Status
HalRuartMultiBlkDmaRecvRtl8195a(
IN VOID *Data,
IN u8 *pRxData,
IN u32 Length
);
HAL_Status
RuartIsTimeout (
u32 StartCount,
u32 TimeoutCnt
);
HAL_Status
HalRuartStopRecvRtl8195a_Patch(
IN VOID *Data
);
HAL_Status
HalRuartStopSendRtl8195a_Patch(
IN VOID *Data
);
VOID
HalRuartEnterCriticalRtl8195a(
IN VOID *Data
);
VOID
HalRuartExitCriticalRtl8195a(
IN VOID *Data
);
#if CONFIG_CHIP_E_CUT
_LONG_CALL_ HAL_Status
HalRuartResetTxFifoRtl8195a_V04(
IN VOID *Data ///< RUART Adapter
);
_LONG_CALL_ HAL_Status
HalRuartResetRxFifoRtl8195a_V04(
IN VOID *Data ///< RUART Adapter
);
_LONG_CALL_ HAL_Status
HalRuartResetTRxFifoRtl8195a_V04(
IN VOID *Data ///< RUART Adapter
);
_LONG_CALL_ HAL_Status
HalRuartSetBaudRateRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartInitRtl8195a_V04(
IN VOID *Data ///< RUART Adapter
);
_LONG_CALL_ HAL_Status
HalRuartEnableRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartDisableRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartFlowCtrlRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ u32
_UartTxDmaIrqHandle_V04(
IN VOID *Data
);
_LONG_CALL_ u32
_UartRxDmaIrqHandle_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartDmaSendRtl8195a_V04(
IN VOID *Data,
IN u8 *pTxData,
IN u32 Length
);
_LONG_CALL_ HAL_Status
HalRuartDmaRecvRtl8195a_V04(
IN VOID *Data,
IN u8 *pRxData,
IN u32 Length
);
_LONG_CALL_ HAL_Status
HalRuartMultiBlkDmaSendRtl8195a_V04(
IN VOID *Data,
IN u8 *pTxData,
IN u32 Length
);
_LONG_CALL_ HAL_Status
HalRuartMultiBlkDmaRecvRtl8195a_V04(
IN VOID *Data,
IN u8 *pRxData,
IN u32 Length
);
_LONG_CALL_ HAL_Status
HalRuartStopRecvRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartStopSendRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ VOID
HalRuartEnterCriticalRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ VOID
HalRuartExitCriticalRtl8195a_V04(
IN VOID *Data
);
#endif // #if CONFIG_CHIP_E_CUT
#ifdef CONFIG_MBED_ENABLED
// Interface to ROM functions
//extern __longcall void HalRuartAdapterLoadDefRtl8195a(UART_Handle *uart, uint8_t idx);
//extern __longcall void HalRuartDeInitRtl8195a(UART_Handle *uart);
//extern __longcall HAL_Status HalRuartDisableRtl8195a(UART_Handle *data);
//extern __longcall HAL_Status HalRuartEnableRtl8195a(UART_Handle *data);
//extern __longcall void HalRuartDmaInitRtl8195a(UART_Handle *data);
//extern __longcall void HalRuartTxGdmaLoadDefRtl8195a(UART_Handle *uart, RUART_DMA_Config *cfg);
//extern __longcall void HalRuartRxGdmaLoadDefRtl8195a(UART_Handle *uart, RUART_DMA_Config *cfg);
//extern __longcall HAL_Status HalRuartGetCRtl8195a(UART_Handle *uart, uint8_t *byte);
//extern __longcall HAL_Status HalRuartPutCRtl8195a(UART_Handle *uart, uint8_t byte);
//extern __longcall HAL_Status RuartLock(UART_Handle * uart);
//extern __longcall void RuartUnlock(UART_Handle * uart);
//extern __longcall void HalRuartSetIMRRtl8195a(UART_Handle *uart);
//extern __longcall uint8_t HalRuartGetIMRRtl8195a(UART_Handle *uart);
//extern __longcall uint32_t HalRuartSendRtl8195a(UART_Handle *, uint8_t *, uint32_t, uint32_t);
//extern __longcall HAL_Status HalRuartIntSendRtl8195a(UART_Handle *, uint8_t *, uint32_t);
//extern __longcall HAL_Status HalRuartIntRecvRtl8195a(UART_Handle *, uint8_t *, uint32_t);
//extern __longcall uint32_t HalRuartRecvRtl8195a(UART_Handle *, uint8_t *, uint32_t, uint32_t);
//extern __longcall void HalRuartRegIrqRtl8195a(UART_Handle *Data);
//extern __longcall void HalRuartIntEnableRtl8195a(UART_Handle *Data);
//extern __longcall void HalRuartIntDisableRtl8195a(UART_Handle *Data);
//extern __longcall uint32_t HalRuartGetDebugValueRtl8195a(HAL_RUART_ADAPTER *Data, uint32_t sel);
//extern __longcall void HalRuartRTSCtrlRtl8195a(UART_Handle *Data, bool val);
extern __longcall HAL_Status RuartIsTimeout(uint32_t StartCount, uint32_t TimeoutCnt);
#endif
#endif

94
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_wdt.h Normal file
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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
#ifndef _RTL8195A_WDT_H_
#define _RTL8195A_WDT_H_
#define WDGTIMERELY (10*1024) //us
typedef struct _WDG_REG_ {
u16 WdgScalar;
u8 WdgEnByte;
u8 WdgClear:1;
u8 WdgCunLimit:4;
u8 Rsvd:1;
u8 WdgMode:1;
u8 WdgToISR:1;
}WDG_REG, *PWDG_REG;
typedef struct _WDG_ADAPTER_ {
WDG_REG Ctrl;
IRQ_HANDLE IrqHandle;
TIMER_ADAPTER WdgGTimer;
VOID (*UserCallback)(u32 callback_id); // User callback function
u32 callback_id;
}WDG_ADAPTER, *PWDG_ADAPTER;
enum _WDG_CNTLMT_ {
CNT1H = 0,
CNT3H = 1,
CNT7H = 2,
CNTFH = 3,
CNT1FH = 4,
CNT3FH = 5,
CNT7FH = 6,
CNTFFH = 7,
CNT1FFH = 8,
CNT3FFH = 9,
CNT7FFH = 10,
CNTFFFH = 11
};
typedef uint32_t WDG_CNTLMT;
typedef uint32_t *PWDG_CNTLMT;
enum _WDG_MODE_ {
INT_MODE = 0,
RESET_MODE = 1
};
typedef uint32_t WDG_MODE;
typedef uint32_t *PWDG_MODE;
extern VOID
WDGInitial(
IN u32 Period
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGStop(
VOID
);
extern VOID
WDGRefresh(
VOID
);
extern VOID
WDGIrqCallBackReg(
IN VOID *CallBack,
IN u32 Id
);
#endif //_RTL8195A_WDT_H_

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl_utility.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __RTL_UTILITY_H_
#define __RTL_UTILITY_H_
VOID RtlMemcpy(VOID* dec, VOID* sour, u32 sz);
u32 RtlMemcmp(VOID *dst, VOID *src, u32 sz);
VOID RtlMemset(VOID *pbuf, u32 c, u32 sz);
s8 *
RtlStrncpy(
IN s8 *dest,
IN const s8 *src,
IN SIZE_T count
);
s8 *
RtlStrcpy(
IN s8 *dest,
IN const s8 *src
);
SIZE_T
RtlStrlen(
IN const s8 *s
);
SIZE_T
RtlStrnlen(
IN const s8 *s,
IN SIZE_T count
);
int
RtlStrcmp(
IN const s8 *cs,
IN const s8 *ct
);
int
RtlStrncmp(
IN const s8 *cs,
IN const s8 *ct,
IN SIZE_T count
);
#endif

77
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/system_8195a.h Normal file
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/**************************************************************************//**
* @file system_ARMCM3.h
* @brief CMSIS Device System Header File for
* ARMCM3 Device Series
* @version V1.08
* @date 23. November 2012
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef _SYSTEM_8195A_H
#define _SYSTEM_8195A_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
extern u32 SystemGetCpuClk(void);
extern u32 Rand2(void);
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_8195A_H */

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/va_list.h Normal file
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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
#ifndef _VA_LIST_H_
#define _VA_LIST_H_
#include "basic_types.h"
#ifndef va_arg
typedef s32 acpi_native_int;
#ifndef _VALIST
#define _VALIST
typedef char *va_list;
#endif /* _VALIST */
/* Storage alignment properties */
#define _AUPBND (sizeof (acpi_native_int) - 1)
#define _ADNBND (sizeof (acpi_native_int) - 1)
/* Variable argument list macro definitions */
#define _bnd(X, bnd) (((sizeof (X)) + (bnd)) & (~(bnd)))
#define va_arg(ap, T) (*(T *)(((ap) += (_bnd (T, _AUPBND))) - (_bnd (T,_ADNBND))))
#define va_end(ap) (ap = (va_list) NULL)
#define va_start(ap, A) (void) ((ap) = (((char *) &(A)) + (_bnd (A,_AUPBND))))
#endif /* va_arg */
#endif //_VA_LIST_H_

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef CONFIG_GPIO_EN
struct gpio_irq_s {
PinName pin;
uint32_t event;
HAL_GPIO_PIN hal_pin;
uint8_t hal_port_num;
uint8_t hal_pin_num;
};
typedef struct gpio_irq_s gpio_irq_t;
struct gpio_s {
PinName pin;
PinMode mode;
PinDirection direction;
HAL_GPIO_PIN hal_pin;
uint8_t hal_port_num;
uint8_t hal_pin_num;
};
typedef struct gpio_s gpio_t;
struct port_s {
PortName port;
uint32_t mask;
PinDirection direction;
uint8_t *pin_def;
};
#endif // end of "#ifdef CONFIG_GPIO_EN"
#ifdef CONFIG_UART_EN
struct serial_s {
int index;
HAL_RUART_OP hal_uart_op;
HAL_RUART_ADAPTER hal_uart_adp;
#ifdef CONFIG_GDMA_EN
UART_DMA_CONFIG uart_gdma_cfg;
HAL_GDMA_ADAPTER uart_gdma_adp_tx;
HAL_GDMA_ADAPTER uart_gdma_adp_rx;
UART_DMA_MULTIBLK gdma_multiblk_list_tx;
UART_DMA_MULTIBLK gdma_multiblk_list_rx;
#endif
uint32_t tx_len;
uint32_t rx_len;
};
#endif // end of "#ifdef CONFIG_UART_EN"
struct log_uart_s {
HAL_LOG_UART_ADAPTER log_hal_uart;
};
#ifdef CONFIG_SPI_COM_EN
#endif
#ifdef CONFIG_PWM_EN
struct pwmout_s {
uint8_t pwm_idx;
uint8_t pin_sel;
uint32_t period;
uint32_t pulse;
HAL_PWM_ADAPTER pwm_hal_adp;
};
#endif
#ifdef CONFIG_I2C_EN
struct i2c_s {
SAL_I2C_MNGT_ADPT SalI2CMngtAdpt;
SAL_I2C_HND_PRIV SalI2CHndPriv;
HAL_I2C_INIT_DAT HalI2CInitData;
HAL_I2C_OP HalI2COp;
IRQ_HANDLE I2CIrqHandleDat;
HAL_GDMA_ADAPTER HalI2CTxGdmaAdpt;
HAL_GDMA_ADAPTER HalI2CRxGdmaAdpt;
HAL_GDMA_OP HalI2CGdmaOp;
IRQ_HANDLE I2CTxGdmaIrqHandleDat;
IRQ_HANDLE I2CRxGdmaIrqHandleDat;
SAL_I2C_USER_CB SalI2CUserCB;
SAL_I2C_USERCB_ADPT SalI2CUserCBAdpt[SAL_USER_CB_NUM];
SAL_I2C_DMA_USER_DEF SalI2CDmaUserDef;
};
#endif
struct flash_s
{
SPIC_INIT_PARA SpicInitPara;
u32 Length;
};
#ifdef CONFIG_ADC_EN
struct analogin_s {
SAL_ADC_MNGT_ADPT SalADCMngtAdpt;
SAL_ADC_HND_PRIV SalADCHndPriv;
HAL_ADC_INIT_DAT HalADCInitData;
HAL_ADC_OP HalADCOp;
IRQ_HANDLE ADCIrqHandleDat;
HAL_GDMA_ADAPTER HalADCGdmaAdpt;
HAL_GDMA_OP HalADCGdmaOp;
IRQ_HANDLE ADCGdmaIrqHandleDat;
SAL_ADC_USER_CB SalADCUserCB;
SAL_ADC_USERCB_ADPT SalADCUserCBAdpt[SAL_ADC_USER_CB_NUM];
};
#endif
#if 0
struct i2c_s {
I2C_Type *i2c;
};
struct spi_s {
SPI_Type *spi;
};
#endif
#ifdef CONFIG_NFC_EN
struct nfctag_s {
NFC_ADAPTER NFCAdapter;
void *nfc_rd_cb; // read callback function
void *rd_cb_arg;
void *nfc_wr_cb; // write callback function
void *wr_cb_arg;
void *nfc_ev_cb; // event callback function
void *ev_cb_arg;
void *nfc_cache_rd_cb; // cache read callback function
void *cache_read_cb_arg;
unsigned int event_mask;
int pwr_status;
};
#endif
#ifdef CONFIG_TIMER_EN
struct gtimer_s {
TIMER_ADAPTER hal_gtimer_adp;
void *handler;
u32 hid;
u8 timer_id;
u8 is_periodcal;
};
#endif
#ifdef CONFIG_I2S_EN
struct i2s_s {
HAL_I2S_ADAPTER I2SAdapter;
HAL_I2S_INIT_DAT InitDat;
u8 sampling_rate;
u8 channel_num;
u8 word_length;
u8 direction;
};
#endif
#ifdef CONFIG_DAC_EN
/** \file objects.h
* \brief A Documented file.
*
* A documented file.
*/
/** \struct dac_s objects.h "rtl8195a/objects.h"
* \brief This is a dac_s structure.
*
* For analogout APIs, a pointer to dac_s is used as an input paras.
* A DAC initial data structure is the major element of dac_s.
*/
struct dac_s {
HAL_DAC_INIT_DAT DACpara;
};
#endif
#ifdef CONFIG_ADC_EN //True random number generator uses ADC
struct trng_s{
uint32_t pin;
struct analogin_s tradcng;
uint8_t inited;
};
#endif
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include "PinNames.h"
#include "hal_adc.h"
#include "analogin_api.h"
#if CONFIG_ADC_EN
#include "pinmap.h"
extern u32 ConfigDebugErr;
extern u32 ConfigDebuginfo;
void analogin_init (analogin_t *obj, PinName pin)
{
uint32_t adc_idx;
PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL;
PSAL_ADC_USERCB_ADPT pSalADCUserCBAdpt = NULL;
PSAL_ADC_HND pSalADCHND = NULL;
HAL_ADC_INIT_DAT HalADCInitDataTmp;
PHAL_ADC_INIT_DAT pHalADCInitDataTmp = &HalADCInitDataTmp;
/* To backup user config first */
_memset(&(obj->HalADCInitData), 0, sizeof(HAL_ADC_INIT_DAT));
_memcpy(pHalADCInitDataTmp, &(obj->HalADCInitData), sizeof(HAL_ADC_INIT_DAT));
_memset(obj, 0x00, sizeof(analogin_t));
ConfigDebugErr &= (~(_DBG_ADC_|_DBG_GDMA_));
ConfigDebugInfo&= (~(_DBG_ADC_|_DBG_GDMA_));
adc_idx = pin & 0x0F;
/* Get I2C device handler */
pSalADCMngtAdpt = &(obj->SalADCMngtAdpt);
pSalADCUserCBAdpt = (PSAL_ADC_USERCB_ADPT)&(obj->SalADCUserCBAdpt);
/*To assign the rest pointers*/
pSalADCMngtAdpt->pSalHndPriv = &(obj->SalADCHndPriv);
pSalADCMngtAdpt->pSalHndPriv->ppSalADCHnd = (void**)&(pSalADCMngtAdpt->pSalHndPriv);
/* To assign the default (ROM) HAL OP initialization function */
pSalADCMngtAdpt->pHalOpInit = &HalADCOpInit;
/* To assign the default (ROM) HAL GDMA OP initialization function */
pSalADCMngtAdpt->pHalGdmaOpInit = &HalGdmaOpInit;
/* To assign the default (ROM) SAL interrupt function */
pSalADCMngtAdpt->pSalIrqFunc = &ADCISRHandle;
/* To assign the default (ROM) SAL DMA TX interrupt function */
pSalADCMngtAdpt->pSalDMAIrqFunc = &ADCGDMAISRHandle;
/* To backup user config first */
//_memcpy(pHalADCInitDataTmp, &(obj->HalADCInitData), sizeof(HAL_ADC_INIT_DAT));
pSalADCMngtAdpt->pHalInitDat = &(obj->HalADCInitData);
pSalADCMngtAdpt->pHalOp = &(obj->HalADCOp);
pSalADCMngtAdpt->pIrqHnd = &(obj->ADCIrqHandleDat);
pSalADCMngtAdpt->pHalGdmaAdp = &(obj->HalADCGdmaAdpt);
pSalADCMngtAdpt->pHalGdmaOp = &(obj->HalADCGdmaOp);
pSalADCMngtAdpt->pIrqGdmaHnd = &(obj->ADCGdmaIrqHandleDat);
pSalADCMngtAdpt->pUserCB = &(obj->SalADCUserCB);
/* Assign the private SAL handle to public SAL handle */
pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv);
/* Assign the internal HAL initial data pointer to the SAL handle */
pSalADCHND->pInitDat = pSalADCMngtAdpt->pHalInitDat;
/* Assign the internal user callback pointer to the SAL handle */
pSalADCHND->pUserCB = pSalADCMngtAdpt->pUserCB;
/*To assign user callback pointers*/
pSalADCMngtAdpt->pUserCB->pTXCB = pSalADCUserCBAdpt;
pSalADCMngtAdpt->pUserCB->pTXCCB = (pSalADCUserCBAdpt+1);
pSalADCMngtAdpt->pUserCB->pRXCB = (pSalADCUserCBAdpt+2);
pSalADCMngtAdpt->pUserCB->pRXCCB = (pSalADCUserCBAdpt+3);
pSalADCMngtAdpt->pUserCB->pRDREQCB = (pSalADCUserCBAdpt+4);
pSalADCMngtAdpt->pUserCB->pERRCB = (pSalADCUserCBAdpt+5);
pSalADCMngtAdpt->pUserCB->pDMATXCB = (pSalADCUserCBAdpt+6);
pSalADCMngtAdpt->pUserCB->pDMATXCCB = (pSalADCUserCBAdpt+7);
pSalADCMngtAdpt->pUserCB->pDMARXCB = (pSalADCUserCBAdpt+8);
pSalADCMngtAdpt->pUserCB->pDMARXCCB = (pSalADCUserCBAdpt+9);
/* Set ADC Device Number */
pSalADCHND->DevNum = adc_idx;
/* Load ADC default value */
RtkADCLoadDefault(pSalADCHND);
/* Assign ADC Pin Mux */
pSalADCHND->PinMux = 0;
pSalADCHND->OpType = ADC_RDREG_TYPE;
/* Load user setting */
if ((pHalADCInitDataTmp->ADCEndian == ADC_DATA_ENDIAN_LITTLE) || (pHalADCInitDataTmp->ADCEndian == ADC_DATA_ENDIAN_BIG)) {
DBG_8195A("K\n");
pSalADCHND->pInitDat->ADCEndian = pHalADCInitDataTmp->ADCEndian;
}
if ((pHalADCInitDataTmp->ADCAudioEn != ADC_FEATURE_DISABLED) && (pHalADCInitDataTmp->ADCAudioEn < 2)) {
DBG_8195A("O\n");
pSalADCHND->pInitDat->ADCAudioEn = pHalADCInitDataTmp->ADCAudioEn;
}
/* Init ADC now */
pSalADCHND->pInitDat->ADCBurstSz = 8;
pSalADCHND->pInitDat->ADCOneShotTD = 8;
RtkADCInit(pSalADCHND);
}
float analogin_read(analogin_t *obj)
{
float value;
uint32_t AnaloginTmp[2] = {0,0};
uint32_t AnaloginDatMsk = 0xFFFF;
uint8_t AnaloginIdx = 0;
uint32_t AnalogDat = 0;
//no auto-calibration implemented yet, uses hard coded calibrate
uint32_t Offset = 0x2980;
uint32_t AnalogDatFull = 0xAA00;
PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL;
PSAL_ADC_HND pSalADCHND = NULL;
pSalADCMngtAdpt = &(obj->SalADCMngtAdpt);
pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv);
AnaloginIdx = pSalADCHND->DevNum;
RtkADCReceiveBuf(pSalADCHND,&AnaloginTmp[0]);
AnaloginDatMsk = (u32)(AnaloginDatMsk<<((u32)(16*(AnaloginIdx&0x01))));
AnalogDat = AnaloginTmp[(AnaloginIdx/2)];
AnalogDat = (AnalogDat & AnaloginDatMsk);
AnalogDat = (AnalogDat>>((u32)(16*(AnaloginIdx&0x01))));
AnalogDat -= Offset;
value = (float)(AnalogDat) / (float)(AnalogDatFull);
return (float)value;
}
uint16_t analogin_read_u16(analogin_t *obj)
{
uint32_t AnaloginTmp[2] = {0,0};
uint32_t AnaloginDatMsk = 0xFFFF;
uint8_t AnaloginIdx = 0;
uint32_t AnalogDat = 0;
PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL;
PSAL_ADC_HND pSalADCHND = NULL;
pSalADCMngtAdpt = &(obj->SalADCMngtAdpt);
pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv);
AnaloginIdx = pSalADCHND->DevNum;
RtkADCRxManualRotate(pSalADCHND,&AnaloginTmp[0]);
AnaloginDatMsk = (u32)(AnaloginDatMsk<<((u32)(16*(AnaloginIdx&0x01))));
AnalogDat = AnaloginTmp[(AnaloginIdx/2)];
AnalogDat = (AnalogDat & AnaloginDatMsk);
AnalogDat = (AnalogDat>>((u32)(16*(AnaloginIdx&0x01))));
return (uint16_t)AnalogDat;
}
void analogin_deinit(analogin_t *obj)
{
PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL;
PSAL_ADC_HND pSalADCHND = NULL;
pSalADCMngtAdpt = &(obj->SalADCMngtAdpt);
pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv);
/* To deinit analogin */
RtkADCDeInit(pSalADCHND);
}
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/analogin_ext.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_ANALOGIN_EXT_H
#define MBED_ANALOGIN_EXT_H
#ifdef __cplusplus
extern "C" {
#endif
extern void analogin_deinit(analogin_t *obj);
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/analogout_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include "analogout_api.h"
#if CONFIG_DAC_EN
#include "cmsis.h"
#include "pinmap.h"
#include <string.h>
#define DAC_POSITIVE_FULL_SCALE 0x7E0
#define DAC_NEGATIVE_FULL_SCALE 0x820
/** \brief analogout_init:\n
* to initialize DAC
*
* This function is mainly to initialize a DAC channel.
* \para dac_t *: obj
* \para PinName: pin
*/
void analogout_init(dac_t *obj, PinName pin)
{
uint32_t dac_idx;
uint32_t DacTemp;
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara);
dac_idx = pin & 0x0F;
/* Assign dac index */
pHalDacInitData->DACIdx = dac_idx;
pHalDacInitData->DACEn = DAC_DISABLE;
pHalDacInitData->DACDataRate = DAC_DATA_RATE_250K;
pHalDacInitData->DACEndian = DAC_DATA_ENDIAN_LITTLE;
pHalDacInitData->DACBurstSz = 10;
pHalDacInitData->DACDbgSel = DAC_DBG_SEL_DISABLE;
pHalDacInitData->DACDscDbgSel = DAC_DSC_DBG_SEL_DISABLE;
pHalDacInitData->DACBPDsc = DAC_BYPASS_DSC_SEL_DISABLE;
pHalDacInitData->DACDeltaSig = 0;
pHalDacInitData->DACAnaCtrl0 = 0;
pHalDacInitData->DACAnaCtrl1 = 0;
pHalDacInitData->DACIntrMSK = DAC_FEATURE_DISABLED;
/* DAC Function and Clock Enable*/
HalDACPinMuxInit(pHalDacInitData);
HalDACInit8195a(pHalDacInitData);
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_INTR_CTRL,
(BIT_DAC_FIFO_FULL_EN |
BIT_DAC_FIFO_OVERFLOW_EN |
BIT_DAC_FIFO_STOP_EN |
BIT_DAC__WRITE_ERROR_EN |
BIT_DAC_DSC_OVERFLOW0_EN |
BIT_DAC_DSC_OVERFLOW1_EN));
DBG_DAC_INFO("INTR MSK:%x\n", HAL_DAC_READ32(pHalDacInitData->DACIdx,REG_DAC_INTR_CTRL));
DacTemp = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_ANAPAR_DA1);
DacTemp |= (BIT31);
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_ANAPAR_DA1, DacTemp);
DBG_DAC_INFO("REG_DAC_ANAPAR_DA1:%08x\n",HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_ANAPAR_DA1));
DacTemp = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_CTRL);
DacTemp |= BIT3;
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_CTRL, DacTemp);
DBG_DAC_INFO("REG_DAC_CTRL:%08x\n",DacTemp);
pHalDacInitData->DACEn = DAC_ENABLE;
HalDACEnableRtl8195a(pHalDacInitData);
osDelay(6); //hardware needs some time to get ready
}
/** \brief analogout_free:\n
* to free DAC
*
* This function is mainly to free a DAC channel.
* \para dac_t *: obj
*/
void analogout_free(dac_t *obj)
{
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara);
HalDACPinMuxDeInit(pHalDacInitData);
pHalDacInitData->DACEn = DAC_DISABLE;
HalDACEnableRtl8195a(pHalDacInitData);
}
/** \brief analogout_write:\n
* to execute analogout_write
*
* This function is mainly to execute analog output and the value is a ratio.
* The upper/lower bound of DAC register input value is defined by
* DAC_XXXXX_FULL_SCALE. The parameter "value" of this function should be
* transfered to register value.
*
* \para dac_t * : obj
* \para float : value
*/
void analogout_write(dac_t *obj, float value)
{
uint32_t dactemp;
uint16_t dacnegtemp;
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara);
if (value < 0.0f) {
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, 0x00000000);
} else if (value > 1.0f) {
dactemp = (DAC_POSITIVE_FULL_SCALE<<16) | DAC_POSITIVE_FULL_SCALE;
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp);
} else {
if (value >= 0.5) {
dactemp = (uint32_t)((((value-0.5)/0.5) * (2^12)) * DAC_POSITIVE_FULL_SCALE);
dactemp = dactemp / (2^12);
dactemp = (dactemp<<16) | dactemp;
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp);
} else {
dacnegtemp = (DAC_NEGATIVE_FULL_SCALE & 0x7FF);
dacnegtemp = ((~dacnegtemp) + 1) & 0x7FF;
dactemp = (uint32_t)(((0.5-value)/0.5) * (2^12) * dacnegtemp);
dactemp = dactemp / (2^12);
dactemp = 0x1000 - dactemp; //change to 2's complement
dactemp = (dactemp<<16) | dactemp;
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp);
}
}
}
/** \brief analogout_write_u16:\n
* to execute analogout_write_u16
*
* The register value of DAC input is a format of 2's complement.
* The most maximum value of positive value drives DAC to output a voltage about 3.3V.
* The most mimimum value of negative value drives DAC to output a voltage about 0.
* And the middle value of 0x000 will drive DAC to output a voltage of half of max voltage.
*
* \para dac_t * : obj
* \para float : value
*/
void analogout_write_u16(dac_t *obj, uint16_t value)
{
uint32_t dactemp;
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara);
/* To give a two point data */
dactemp = (value << 16) | value;
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp);
}
/** \brief analogout_read_u16:\n
* to read back analog output value in float format
*
* This function is NOT available in rtl8195a hardware design.
* It always returns a fixed value of 0.0;
* \para dac_t * : obj
*/
float analogout_read(dac_t *obj)
{
return (float)0.0;
}
/** \brief analogout_read_u16:\n
* to read back analog output register value
*
* This function is NOT available in rtl8195a hardware design.
* It always returns a fixed value of 0xFFFF;
* \para dac_t * : obj
*/
uint16_t analogout_read_u16(dac_t *obj)
{
return (uint16_t)0xFFFF;
}
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include "PinNames.h"
#include "pinmap.h"
#include "rtl8195a.h"
#include "hal_spi_flash.h"
#include "hal_platform.h"
#include "rtl8195a_spi_flash.h"
#include "hal_api.h"
#include "flash_api.h"
extern u32 ConfigDebugInfo;
extern SPIC_INIT_PARA SpicInitParaAllClk[3][CPU_CLK_TYPE_NO];
_LONG_CALL_
extern VOID SpicWaitBusyDoneRtl8195A(VOID);
static int isinit = 0;
static flash_t flashobj;
static void flash_init(flash_t * obj);
static void flash_turnon();
/**
* global data structure
*/
//flash_t flash;
/**
* @brief Control the flash chip write protect enable/disable
* @param protect: 1/0: protect/unprotect
* @retval none
*/
void flash_write_protect(flash_t *obj, uint32_t protect)
{
flash_turnon();
if(isinit == 0)
flash_init(&flashobj);
SpicWriteProtectFlashRtl8195A(protect);
SpicDisableRtl8195A();
}
/**
* @brief Init Flash
* @param obj: address of the flash object
* @retval none
*/
void flash_init(flash_t *obj)
{
//SPIC_INIT_PARA spic_init_para;
// Init SPI Flash Controller
// DBG_8195A("Initial Spi Flash Controller\n");
//SPI_FLASH_PIN_FCTRL(ON);
if (!SpicFlashInitRtl8195A(SpicOneBitMode)){
DBG_8195A("SPI Init Fail!!!!!!\n");
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO3, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO3)|0xf);
} else {
isinit = 1;
}
flashobj.SpicInitPara.flashtype = SpicInitParaAllClk[0][0].flashtype;
}
void flash_turnon()
{
SPI_FLASH_PIN_FCTRL(ON);
SpicWaitBusyDoneRtl8195A();
}
/**
* @brief Erase flash sector
* @param address: Specifies the starting address to be erased.
* @retval none
*/
void flash_erase_sector(flash_t *obj, uint32_t address)
{
flash_turnon();
if(isinit == 0)
flash_init(&flashobj);
SpicSectorEraseFlashRtl8195A(SPI_FLASH_BASE + address);
SpicDisableRtl8195A();
}
void flash_erase_block(flash_t *obj, uint32_t address)
{
flash_turnon();
if(isinit == 0)
flash_init(&flashobj);
SpicBlockEraseFlashRtl8195A(SPI_FLASH_BASE + address);
SpicDisableRtl8195A();
}
/**
* @brief Read a word from specified address
* @param obj: Specifies the parameter of flash object.
* @param address: Specifies the address to be read.
* @param data: Specified the address to save the readback data.
* @retval status: Success:1 or Failure: Others.
*/
int flash_read_word(flash_t *obj, uint32_t address, uint32_t * data)
{
flash_turnon();
if(isinit == 0)
flash_init(&flashobj);
// Wait flash busy done (wip=0)
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
* data = HAL_READ32(SPI_FLASH_BASE, address);
SpicDisableRtl8195A();
return 1;
}
/**
* @brief Write a word to specified address
* @param obj: Specifies the parameter of flash object.
* @param address: Specifies the address to be programmed.
* @param data: Specified the data to be programmed.
* @retval status: Success:1 or Failure: Others.
*/
int flash_write_word(flash_t *obj, uint32_t address, uint32_t data)
{
u8 flashtype = 0;
flash_turnon();
if(isinit == 0)
flash_init(&flashobj);
flashtype = flashobj.SpicInitPara.flashtype;
//Write word
HAL_WRITE32(SPI_FLASH_BASE, address, data);
// Wait spic busy done
SpicWaitBusyDoneRtl8195A();
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
} else
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
SpicDisableRtl8195A();
return 1;
}
/**
* @brief Read a stream of data from specified address
* @param obj: Specifies the parameter of flash object.
* @param address: Specifies the address to be read.
* @param len: Specifies the length of the data to read.
* @param data: Specified the address to save the readback data.
* @retval status: Success:1 or Failure: Others.
*/
int flash_stream_read(flash_t *obj, uint32_t address, uint32_t len, uint8_t * data)
{
u32 offset_to_align;
u32 i;
u32 read_word;
uint8_t *ptr;
uint8_t *pbuf;
flash_turnon();
if(isinit == 0)
flash_init(&flashobj);
// Wait flash busy done (wip=0)
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
offset_to_align = address & 0x03;
pbuf = data;
if (offset_to_align != 0) {
// the start address is not 4-bytes aligned
read_word = HAL_READ32(SPI_FLASH_BASE, (address - offset_to_align));
ptr = (uint8_t*)&read_word + offset_to_align;
offset_to_align = 4 - offset_to_align;
for (i=0;i<offset_to_align;i++) {
*pbuf = *(ptr+i);
pbuf++;
len--;
if (len == 0) {
break;
}
}
}
address = (((address-1) >> 2) + 1) << 2; // address = next 4-bytes aligned
ptr = (uint8_t*)&read_word;
if ((u32)pbuf & 0x03) {
while (len >= 4) {
read_word = HAL_READ32(SPI_FLASH_BASE, address);
for (i=0;i<4;i++) {
*pbuf = *(ptr+i);
pbuf++;
}
address += 4;
len -= 4;
}
} else {
while (len >= 4) {
*((u32 *)pbuf) = HAL_READ32(SPI_FLASH_BASE, address);
pbuf += 4;
address += 4;
len -= 4;
}
}
if (len > 0) {
read_word = HAL_READ32(SPI_FLASH_BASE, address);
for (i=0;i<len;i++) {
*pbuf = *(ptr+i);
pbuf++;
}
}
SpicDisableRtl8195A();
return 1;
}
/**
* @brief Write a stream of data to specified address
* @param obj: Specifies the parameter of flash object.
* @param address: Specifies the address to be read.
* @param len: Specifies the length of the data to write.
* @param data: Specified the pointer of the data to be written.
* @retval status: Success:1 or Failure: Others.
*/
int flash_stream_write(flash_t *obj, uint32_t address, uint32_t len, uint8_t * data)
{
u32 offset_to_align;
u32 align_addr;
u32 i;
u32 write_word;
uint8_t *ptr;
uint8_t *pbuf;
u8 flashtype = 0;
flash_turnon();
if(isinit == 0)
flash_init(&flashobj);
flashtype = flashobj.SpicInitPara.flashtype;
offset_to_align = address & 0x03;
pbuf = data;
if (offset_to_align != 0) {
// the start address is not 4-bytes aligned
align_addr = (address - offset_to_align);
write_word = HAL_READ32(SPI_FLASH_BASE, align_addr);
ptr = (uint8_t*)&write_word + offset_to_align;
offset_to_align = 4 - offset_to_align;
for (i=0;i<offset_to_align;i++) {
*(ptr+i) = *pbuf;
pbuf++;
len--;
if (len == 0) {
break;
}
}
//Write word
HAL_WRITE32(SPI_FLASH_BASE, align_addr, write_word);
// Wait spic busy done
SpicWaitBusyDoneRtl8195A();
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
} else
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
}
address = (((address-1) >> 2) + 1) << 2; // address = next 4-bytes aligned
if ((u32)pbuf & 0x03) {
while (len >= 4) {
write_word = (u32)(*pbuf) | ((u32)(*(pbuf+1)) << 8) | ((u32)(*(pbuf+2)) << 16) | ((u32)(*(pbuf+3)) << 24);
//Write word
HAL_WRITE32(SPI_FLASH_BASE, address, write_word);
// Wait spic busy done
SpicWaitBusyDoneRtl8195A();
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
} else
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
pbuf += 4;
address += 4;
len -= 4;
}
} else {
while (len >= 4) {
//Write word
HAL_WRITE32(SPI_FLASH_BASE, address, (u32)*((u32 *)pbuf));
// Wait spic busy done
SpicWaitBusyDoneRtl8195A();
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
} else
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
pbuf += 4;
address += 4;
len -= 4;
}
}
if (len > 0) {
write_word = HAL_READ32(SPI_FLASH_BASE, address);
ptr = (uint8_t*)&write_word;
for (i=0;i<len;i++) {
*(ptr+i) = *pbuf;
pbuf++;
}
//Write word
HAL_WRITE32(SPI_FLASH_BASE, address, write_word);
// Wait spic busy done
SpicWaitBusyDoneRtl8195A();
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
} else
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
}
SpicDisableRtl8195A();
return 1;
}
/*
Function Description:
This function performans the same functionality as the function flash_stream_write.
It enhances write performance by reducing overheads.
Users can use either of functions depending on their needs.
* @brief Write a stream of data to specified address
* @param obj: Specifies the parameter of flash object.
* @param address: Specifies the address to be read.
* @param Length: Specifies the length of the data to write.
* @param data: Specified the pointer of the data to be written.
* @retval status: Success:1 or Failure: Others.
*/
int flash_burst_write(flash_t *obj, uint32_t address ,uint32_t Length, uint8_t * data)
{
u32 OccuSize;
u32 ProgramSize;
u32 PageSize;
u8 flashtype = 0;
PageSize = 256;
flash_turnon();
if(isinit == 0)
flash_init(&flashobj);
flashtype = flashobj.SpicInitPara.flashtype;
OccuSize = address & 0xFF;
if((Length >= PageSize) ||((Length + OccuSize) >= PageSize)){
ProgramSize = PageSize - OccuSize;
} else {
ProgramSize = Length;
}
flashobj.Length = Length;
while(Length > 0){
if(OccuSize){
SpicUserProgramRtl8195A(data, flashobj.SpicInitPara, address, &(flashobj.Length));
// Wait spic busy done
SpicWaitBusyDoneRtl8195A();
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
} else
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
address += ProgramSize;
data+= ProgramSize;
Length -= ProgramSize;
OccuSize = 0;
} else{
while((flashobj.Length) >= PageSize){
SpicUserProgramRtl8195A(data, flashobj.SpicInitPara, address, &(flashobj.Length));
// Wait spic busy done
SpicWaitBusyDoneRtl8195A();
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
} else
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
address += PageSize;
data+=PageSize;
Length -= PageSize;
}
flashobj.Length = Length;
if((flashobj.Length) > 0){
SpicUserProgramRtl8195A(data, flashobj.SpicInitPara, address, &(flashobj.Length));
// Wait spic busy done
SpicWaitBusyDoneRtl8195A();
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
} else
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
break;
}
}
flashobj.Length = Length;
}
SpicDisableRtl8195A();
return 1;
}
/**
* @brief Read a stream of data from specified address
* @param obj: Specifies the parameter of flash object.
* @param address: Specifies the address to be read.
* @param len: Specifies the length of the data to read.
* @param data: Specified the address to save the readback data.
* @retval status: Success:1 or Failure: Others.
*/
int flash_burst_read(flash_t *obj, uint32_t address, uint32_t Length, uint8_t * data)
{
flash_turnon();
if(isinit == 0)
flash_init(&flashobj);
// Wait flash busy done (wip=0)
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
SpicUserReadRtl8195A(Length, address, data, SpicOneBitMode);
SpicDisableRtl8195A();
return 1;
}
int flash_get_status(flash_t *obj)
{
u8 Status = 0;
flash_turnon();
if(isinit == 0)
flash_init(&flashobj);
Status = SpicGetFlashStatusRefinedRtl8195A(flashobj.SpicInitPara);
SpicDisableRtl8195A();
return Status;
}
/*
Function Description:
Please refer to the datatsheet of flash for more details of the content of status register.
The block protected area and the corresponding control bits are provided in the flash datasheet.
* @brief Set Status register to enable desired operation
* @param obj: Specifies the parameter of flash object.
* @param data: Specifies which bit users like to set
ex: if users want to set the third bit, data = 0x8.
*/
int flash_set_status(flash_t *obj, uint32_t data)
{
flash_turnon();
if(isinit == 0)
flash_init(&flashobj);
SpicSetFlashStatusRefinedRtl8195A(data, flashobj.SpicInitPara);
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
DBG_8195A("Status Register After Setting= %x\n", flash_get_status(&flashobj));
SpicDisableRtl8195A();
return 1;
}
/*
Function Description:
This function aims to reset the status register, please make sure the operation is appropriate.
*/
void flash_reset_status(flash_t *obj)
{
flash_turnon();
if(isinit == 0)
flash_init(&flashobj);
SpicSetFlashStatusRefinedRtl8195A(0, flashobj.SpicInitPara);
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
SpicDisableRtl8195A();
}
/*
Function Description:
This function is only for Micron 512Mbit flash to access beyond 128Mbit by switching between four 128 Mbit area.
Please refer to flash datasheet for more information about memory mapping.
*/
int flash_set_extend_addr(flash_t *obj, uint32_t data)
{
flash_turnon();
if(isinit == 0)
flash_init(&flashobj);
SpicSetExtendAddrRtl8195A(data, flashobj.SpicInitPara);
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
DBG_8195A("Extended Address Register After Setting= %x\n", flash_get_extend_addr(&flashobj));
SpicDisableRtl8195A();
return 1;
}
int flash_get_extend_addr(flash_t *obj)
{
u8 Status = 0;
flash_turnon();
if(isinit == 0)
flash_init(&flashobj);
Status = SpicGetExtendAddrRtl8195A(flashobj.SpicInitPara);
SpicDisableRtl8195A();
return Status;
}

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targets/TARGET_Realtek/TARGET_AMEBA/flash_api.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_EXT_FLASH_API_EXT_H
#define MBED_EXT_FLASH_API_EXT_H
#include "device.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct flash_s flash_t;
/**
* global data structure
*/
extern flash_t flash;
enum {
FLASH_COMPLETE = 0,
FLASH_ERROR_2 = 1,
};
//void flash_init (flash_t *obj);
void flash_erase_sector (flash_t *obj, uint32_t address);
void flash_erase_block(flash_t * obj, uint32_t address);
int flash_read_word (flash_t *obj, uint32_t address, uint32_t * data);
int flash_write_word (flash_t *obj, uint32_t address, uint32_t data);
int flash_stream_read (flash_t *obj, uint32_t address, uint32_t len, uint8_t * data);
int flash_stream_write (flash_t *obj, uint32_t address, uint32_t len, uint8_t * data);
void flash_write_protect (flash_t *obj, uint32_t protect);
int flash_get_status(flash_t * obj);
int flash_set_status(flash_t * obj, uint32_t data);
void flash_reset_status(flash_t * obj);
int flash_burst_write(flash_t * obj, uint32_t address, uint32_t Length, uint8_t * data);
int flash_burst_read(flash_t * obj, uint32_t address, uint32_t Length, uint8_t * data);
int flash_set_extend_addr(flash_t * obj, uint32_t data);
int flash_get_extend_addr(flash_t * obj);
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/gpio_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include "pinmap.h"
#if CONFIG_GPIO_EN
#include "gpio_api.h"
// convert Mbed pin mode to HAL Pin Mode
const u8 GPIO_InPinMode[] = {
DIN_PULL_NONE, // PullNone
DIN_PULL_HIGH, // PullUp
DIN_PULL_LOW, // PullDown
DIN_PULL_NONE // OpenDrain
};
const u8 GPIO_SWPORT_DR_TBL[] = {
GPIO_PORTA_DR,
GPIO_PORTB_DR,
GPIO_PORTC_DR
};
const u8 GPIO_EXT_PORT_TBL[] = {
GPIO_EXT_PORTA,
GPIO_EXT_PORTB,
GPIO_EXT_PORTC
};
const u8 GPIO_SWPORT_DDR_TBL[] = {
GPIO_PORTA_DDR,
GPIO_PORTB_DDR,
GPIO_PORTC_DDR
};
void gpio_set_hal_pin_mode(gpio_t *obj)
{
uint32_t mode;
mode = obj->mode;
if (obj->direction == PIN_OUTPUT) {
if (mode == OpenDrain) {
obj->hal_pin.pin_mode = DOUT_OPEN_DRAIN;
} else {
obj->hal_pin.pin_mode = DOUT_PUSH_PULL;
}
} else {
if (mode < 4) {
obj->hal_pin.pin_mode = GPIO_InPinMode[mode];
} else {
obj->hal_pin.pin_mode = DIN_PULL_NONE;
}
}
}
uint32_t gpio_set(PinName pin)
{
u32 ip_pin;
DBG_ASSERT(pin != (PinName)NC);
pin_function(pin, 0);
ip_pin = HAL_GPIO_GetPinName((u32)pin);
return ip_pin;
}
void gpio_init(gpio_t *obj, PinName pin)
{
uint32_t pin_name;
if (pin == (PinName)NC)
return;
obj->pin = pin;
obj->mode = PullNone;
obj->direction = PIN_INPUT;
pin_name = gpio_set(pin); // get the IP pin name
obj->hal_pin.pin_name = pin_name;
obj->hal_pin.pin_mode = DIN_PULL_NONE;
obj->hal_port_num = HAL_GPIO_GET_PORT_BY_NAME(pin_name);
obj->hal_pin_num = HAL_GPIO_GET_PIN_BY_NAME(pin_name);
HAL_GPIO_Init(&obj->hal_pin);
}
void gpio_mode(gpio_t *obj, PinMode mode)
{
obj->mode = mode;
gpio_set_hal_pin_mode(obj);
HAL_GPIO_Init(&obj->hal_pin);
}
// Initial the Pin direction
void gpio_dir(gpio_t *obj, PinDirection direction)
{
obj->direction = direction;
gpio_set_hal_pin_mode(obj);
HAL_GPIO_Init(&obj->hal_pin);
}
// Change the pin direction directly
void gpio_change_dir(gpio_t *obj, PinDirection direction)
{
uint32_t reg_value;
uint8_t port_num;
uint8_t pin_num;
obj->direction = direction;
gpio_set_hal_pin_mode(obj);
port_num = obj->hal_port_num;
pin_num = obj->hal_pin_num;
reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_SWPORT_DDR_TBL[port_num]);
if (direction) {
// Out
reg_value |= (1 << pin_num);
} else {
// In
reg_value &= ~(1 << pin_num);
}
HAL_WRITE32(GPIO_REG_BASE, GPIO_SWPORT_DDR_TBL[port_num], reg_value);
}
void gpio_write(gpio_t *obj, int value)
{
HAL_GPIO_PIN *hal_pin=&obj->hal_pin;
volatile uint32_t reg_value;
uint8_t port_num;
uint8_t pin_num;
if (hal_pin->pin_mode != DOUT_OPEN_DRAIN) {
port_num = obj->hal_port_num;
pin_num = obj->hal_pin_num;
reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[port_num]);
reg_value &= ~(1 << pin_num);
reg_value |= ((value&0x01)<< pin_num);
HAL_WRITE32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[port_num], reg_value);
} else {
HAL_GPIO_WritePin(&obj->hal_pin, value);
}
}
int gpio_read(gpio_t *obj)
{
volatile uint32_t reg_value;
uint8_t port_num;
uint8_t pin_num;
HAL_GPIO_PIN_MODE pin_mode;
port_num = obj->hal_port_num;
pin_num = obj->hal_pin_num;
pin_mode = obj->hal_pin.pin_mode;
reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_EXT_PORT_TBL[port_num]);
if (pin_mode != DOUT_OPEN_DRAIN) {
return ((reg_value >> pin_num) & 0x01);
} else {
return (!((reg_value >> pin_num) & 0x01));
}
}
// This API only works for non-Open-Drain pin
void gpio_direct_write(gpio_t *obj, BOOL value)
{
uint8_t port_num;
uint8_t pin_num;
uint32_t reg_value;
port_num = obj->hal_port_num;
pin_num = obj->hal_pin_num;
reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[port_num]);
reg_value &= ~(1 << pin_num);
reg_value |= (value<< pin_num);
HAL_WRITE32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[port_num], reg_value);
}
void gpio_pull_ctrl(gpio_t *obj, PinMode pull_type)
{
HAL_GPIO_PullCtrl((u32) obj->pin, (u32)pull_type);
}
void gpio_deinit(gpio_t *obj)
{
HAL_GPIO_DeInit(&obj->hal_pin);
}
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/gpio_irq_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include "pinmap.h"
#if CONFIG_GPIO_EN
#include "gpio_irq_api.h"
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
{
uint32_t pin_name;
if (pin == NC) return -1;
obj->pin = pin;
pin_name = HAL_GPIO_GetPinName((u32)pin);; // get the IP pin name
obj->hal_pin.pin_name = pin_name;
obj->hal_pin.pin_mode = INT_FALLING; // default use Falling trigger
obj->hal_port_num = HAL_GPIO_GET_PORT_BY_NAME(pin_name);
obj->hal_pin_num = HAL_GPIO_GET_PIN_BY_NAME(pin_name);
HAL_GPIO_Irq_Init(&obj->hal_pin);
HAL_GPIO_UserRegIrq(&obj->hal_pin, (VOID*) handler, (VOID*) id);
return 0;
}
void gpio_irq_free(gpio_irq_t *obj)
{
HAL_GPIO_UserUnRegIrq(&obj->hal_pin);
HAL_GPIO_DeInit(&obj->hal_pin);
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
{
HAL_GPIO_MaskIrq(&obj->hal_pin);
switch((uint32_t)event) {
case IRQ_RISE:
obj->hal_pin.pin_mode = INT_RISING;
break;
case IRQ_FALL:
obj->hal_pin.pin_mode = INT_FALLING;
break;
case IRQ_NONE:
break;
default:
break;
}
HAL_GPIO_Init_8195a(&obj->hal_pin);
HAL_GPIO_IntCtrl(&obj->hal_pin, enable);
if(enable){
HAL_GPIO_UnMaskIrq(&obj->hal_pin);
} else{
HAL_GPIO_MaskIrq(&obj->hal_pin);
}
}
void gpio_irq_enable(gpio_irq_t *obj)
{
HAL_GPIO_UnMaskIrq(&obj->hal_pin);
}
void gpio_irq_disable(gpio_irq_t *obj)
{
HAL_GPIO_MaskIrq(&obj->hal_pin);
}
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/i2c_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include "PinNames.h"
#include "hal_i2c.h"
#include "i2c_api.h"
#if CONFIG_I2C_EN
#include "pinmap.h"
static const PinMap PinMap_I2C_SDA[] = {
{PD_4, RTL_PIN_PERI(I2C0, 0, S0), RTL_PIN_FUNC(I2C0, S0)},
{PH_1, RTL_PIN_PERI(I2C0, 0, S1), RTL_PIN_FUNC(I2C0, S1)},
{PC_8, RTL_PIN_PERI(I2C0, 0, S2), RTL_PIN_FUNC(I2C0, S2)},
{PE_7, RTL_PIN_PERI(I2C0, 0, S3), RTL_PIN_FUNC(I2C0, S3)},
{PC_4, RTL_PIN_PERI(I2C1, 1, S0), RTL_PIN_FUNC(I2C1, S0)},
{PH_3, RTL_PIN_PERI(I2C1, 1, S1), RTL_PIN_FUNC(I2C1, S1)},
{PD_7, RTL_PIN_PERI(I2C1, 1, S2), RTL_PIN_FUNC(I2C1, S2)},
{PB_7, RTL_PIN_PERI(I2C2, 2, S0), RTL_PIN_FUNC(I2C2, S0)},
{PE_1, RTL_PIN_PERI(I2C2, 2, S1), RTL_PIN_FUNC(I2C2, S1)},
{PC_7, RTL_PIN_PERI(I2C2, 2, S2), RTL_PIN_FUNC(I2C2, S2)},
{PB_3, RTL_PIN_PERI(I2C3, 3, S0), RTL_PIN_FUNC(I2C3, S0)},
{PE_3, RTL_PIN_PERI(I2C3, 3, S1), RTL_PIN_FUNC(I2C3, S1)},
{PE_5, RTL_PIN_PERI(I2C3, 3, S2), RTL_PIN_FUNC(I2C3, S2)},
{PD_9, RTL_PIN_PERI(I2C3, 3, S3), RTL_PIN_FUNC(I2C3, S3)},
{NC, NC, 0}
};
static const PinMap PinMap_I2C_SCL[] = {
{PD_5, RTL_PIN_PERI(I2C0, 0, S0), RTL_PIN_FUNC(I2C0, S0)},
{PH_0, RTL_PIN_PERI(I2C0, 0, S1), RTL_PIN_FUNC(I2C0, S1)},
{PC_9, RTL_PIN_PERI(I2C0, 0, S2), RTL_PIN_FUNC(I2C0, S2)},
{PE_6, RTL_PIN_PERI(I2C0, 0, S3), RTL_PIN_FUNC(I2C0, S3)},
{PC_5, RTL_PIN_PERI(I2C1, 1, S0), RTL_PIN_FUNC(I2C1, S0)},
{PH_2, RTL_PIN_PERI(I2C1, 1, S1), RTL_PIN_FUNC(I2C1, S1)},
{PD_6, RTL_PIN_PERI(I2C1, 1, S2), RTL_PIN_FUNC(I2C1, S2)},
{PB_6, RTL_PIN_PERI(I2C2, 2, S0), RTL_PIN_FUNC(I2C2, S0)},
{PE_0, RTL_PIN_PERI(I2C2, 2, S1), RTL_PIN_FUNC(I2C2, S1)},
{PC_6, RTL_PIN_PERI(I2C2, 2, S2), RTL_PIN_FUNC(I2C2, S2)},
{PB_2, RTL_PIN_PERI(I2C3, 3, S0), RTL_PIN_FUNC(I2C3, S0)},
{PE_2, RTL_PIN_PERI(I2C3, 3, S1), RTL_PIN_FUNC(I2C3, S1)},
{PE_4, RTL_PIN_PERI(I2C3, 3, S2), RTL_PIN_FUNC(I2C3, S2)},
{PD_8, RTL_PIN_PERI(I2C3, 3, S3), RTL_PIN_FUNC(I2C3, S3)},
{NC, NC, 0}
};
static int address_save_int[4];
static int Byte_count[4];
static u32 address_save[4];
static uint16_t i2c_target_addr[4];
static SAL_I2C_TRANSFER_BUF i2ctxtranbuf[4];
static SAL_I2C_TRANSFER_BUF i2crxtranbuf[4];
extern u32 ConfigDebugErr;
extern u32 ConfigDebuginfo;
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
uint32_t i2c_sel;
uint32_t i2c_idx;
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_USERCB_ADPT pSalI2CUserCBAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
// Determine the I2C to use
uint32_t i2c_sda = (uint32_t)pinmap_peripheral(sda, PinMap_I2C_SDA);
uint32_t i2c_scl = (uint32_t)pinmap_peripheral(scl, PinMap_I2C_SCL);
ConfigDebugErr &= (~(_DBG_I2C_|_DBG_GDMA_));
ConfigDebugInfo&= (~(_DBG_I2C_|_DBG_GDMA_));
i2c_sel = (uint32_t)pinmap_merge(i2c_sda, i2c_scl);
i2c_idx = RTL_GET_PERI_IDX(i2c_sel);
if (unlikely(i2c_idx == NC)) {
DBG_8195A("%s: Cannot find matched UART\n", __FUNCTION__);
return;
}
/* Get I2C device handler */
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CUserCBAdpt = (PSAL_I2C_USERCB_ADPT)&(obj->SalI2CUserCBAdpt);
/*To assign the rest pointers*/
pSalI2CMngtAdpt->MstRDCmdCnt = 0;
pSalI2CMngtAdpt->InnerTimeOut = 2000; // inner time-out count, 2000 ms
pSalI2CMngtAdpt->pSalHndPriv = &(obj->SalI2CHndPriv);
pSalI2CMngtAdpt->pSalHndPriv->ppSalI2CHnd = (void**)&(pSalI2CMngtAdpt->pSalHndPriv);
/* To assign the default (ROM) HAL OP initialization function */
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
pSalI2CMngtAdpt->pHalOpInit = HalI2COpInit_Patch;
#elif defined(CONFIG_CHIP_E_CUT)
pSalI2CMngtAdpt->pHalOpInit = HalI2COpInit_V04;
#endif
/* To assign the default (ROM) HAL GDMA OP initialization function */
pSalI2CMngtAdpt->pHalGdmaOpInit = HalGdmaOpInit;
/* To assign the default (ROM) SAL interrupt function */
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
pSalI2CMngtAdpt->pSalIrqFunc = I2CISRHandle_Patch;
#elif defined(CONFIG_CHIP_E_CUT)
pSalI2CMngtAdpt->pSalIrqFunc = I2CISRHandle_V04;
#endif
/* To assign the default (ROM) SAL DMA TX interrupt function */
pSalI2CMngtAdpt->pSalDMATxIrqFunc = I2CTXGDMAISRHandle;
/* To assign the default (ROM) SAL DMA RX interrupt function */
pSalI2CMngtAdpt->pSalDMARxIrqFunc = I2CRXGDMAISRHandle;
pSalI2CMngtAdpt->pHalInitDat = &(obj->HalI2CInitData);
pSalI2CMngtAdpt->pHalOp = &(obj->HalI2COp);
pSalI2CMngtAdpt->pIrqHnd = &(obj->I2CIrqHandleDat);
pSalI2CMngtAdpt->pHalTxGdmaAdp = &(obj->HalI2CTxGdmaAdpt);
pSalI2CMngtAdpt->pHalRxGdmaAdp = &(obj->HalI2CRxGdmaAdpt);
pSalI2CMngtAdpt->pHalGdmaOp = &(obj->HalI2CGdmaOp);
pSalI2CMngtAdpt->pIrqTxGdmaHnd = &(obj->I2CTxGdmaIrqHandleDat);
pSalI2CMngtAdpt->pIrqRxGdmaHnd = &(obj->I2CRxGdmaIrqHandleDat);
pSalI2CMngtAdpt->pUserCB = &(obj->SalI2CUserCB);
pSalI2CMngtAdpt->pDMAConf = &(obj->SalI2CDmaUserDef);
/* Assign the private SAL handle to public SAL handle */
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
/* Assign the internal HAL initial data pointer to the SAL handle */
pSalI2CHND->pInitDat = pSalI2CMngtAdpt->pHalInitDat;
/* Assign the internal user callback pointer to the SAL handle */
pSalI2CHND->pUserCB = pSalI2CMngtAdpt->pUserCB;
/* Assign the internal user define DMA configuration to the SAL handle */
pSalI2CHND->pDMAConf = pSalI2CMngtAdpt->pDMAConf;
/*To assign user callback pointers*/
pSalI2CMngtAdpt->pUserCB->pTXCB = pSalI2CUserCBAdpt;
pSalI2CMngtAdpt->pUserCB->pTXCCB = (pSalI2CUserCBAdpt+1);
pSalI2CMngtAdpt->pUserCB->pRXCB = (pSalI2CUserCBAdpt+2);
pSalI2CMngtAdpt->pUserCB->pRXCCB = (pSalI2CUserCBAdpt+3);
pSalI2CMngtAdpt->pUserCB->pRDREQCB = (pSalI2CUserCBAdpt+4);
pSalI2CMngtAdpt->pUserCB->pERRCB = (pSalI2CUserCBAdpt+5);
pSalI2CMngtAdpt->pUserCB->pDMATXCB = (pSalI2CUserCBAdpt+6);
pSalI2CMngtAdpt->pUserCB->pDMATXCCB = (pSalI2CUserCBAdpt+7);
pSalI2CMngtAdpt->pUserCB->pDMARXCB = (pSalI2CUserCBAdpt+8);
pSalI2CMngtAdpt->pUserCB->pDMARXCCB = (pSalI2CUserCBAdpt+9);
pSalI2CMngtAdpt->pUserCB->pGENCALLCB= (pSalI2CUserCBAdpt+10);
/* Set I2C Device Number */
pSalI2CHND->DevNum = i2c_idx;
/* Load I2C default value */
RtkI2CLoadDefault(pSalI2CHND);
/* Assign I2C Pin Mux */
pSalI2CHND->PinMux = RTL_GET_PERI_SEL(i2c_sel);
pSalI2CHND->OpType = I2C_INTR_TYPE;
pSalI2CHND->I2CMaster = I2C_MASTER_MODE;
pSalI2CHND->I2CSpdMod = I2C_SS_MODE;
pSalI2CHND->I2CClk = 100;
pSalI2CHND->I2CAckAddr = 0;
pSalI2CHND->TimeOut = 300;
pSalI2CHND->AddRtyTimeOut = 3000;
pSalI2CHND->I2CExd |= (I2C_EXD_MTR_ADDR_RTY);
pSalI2CMngtAdpt->InnerTimeOut = pSalI2CHND->TimeOut;
/* Init I2C now */
pSalI2CHND->pInitDat->I2CAckAddr = i2c_target_addr[pSalI2CHND->DevNum];
HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat);
HalI2CSetSarRtl8195a(pSalI2CHND->pInitDat);
RtkI2CInitForPS(pSalI2CHND);
}
void i2c_frequency(i2c_t *obj, int hz)
{
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
uint16_t i2c_default_clk = (uint16_t) pSalI2CHND->I2CClk;
uint16_t i2c_user_clk = (uint16_t) (hz/1000);
if (i2c_default_clk != i2c_user_clk) {
/* Deinit I2C first */
i2c_reset(obj);
if (i2c_user_clk <= 100) {
pSalI2CHND->I2CSpdMod = I2C_SS_MODE;
} else if ((i2c_user_clk > 100) && (i2c_user_clk <= 400)) {
pSalI2CHND->I2CSpdMod = I2C_FS_MODE;
} else if (i2c_user_clk > 400) {
pSalI2CHND->I2CSpdMod = I2C_HS_MODE;
} else {
pSalI2CHND->I2CSpdMod = I2C_SS_MODE;
}
/* Load the user defined I2C clock */
pSalI2CHND->I2CClk = i2c_user_clk;
/* Init I2C now */
pSalI2CHND->pInitDat->I2CAckAddr = i2c_target_addr[pSalI2CHND->DevNum];
HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat);
HalI2CSetSarRtl8195a(pSalI2CHND->pInitDat);
RtkI2CInitForPS(pSalI2CHND);
}
}
inline int i2c_start(i2c_t *obj)
{
memset(address_save_int , 0, sizeof(address_save_int));
memset(Byte_count , 0, sizeof(Byte_count));
memset(address_save, 0, sizeof(address_save));
return 0;
}
inline int i2c_stop(i2c_t *obj)
{
return 0;
}
extern u32 HalDelayUs(IN u32 us);
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
u32 I2CInTOTcnt = 0;
u32 InTimeoutCount = 0;
u32 InStartCount = 0;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
address = (address & 0xFE ) >>1;
if (i2c_target_addr[pSalI2CHND->DevNum] != address) {
pSalI2CHND->pInitDat->I2CAckAddr = address;
i2c_target_addr[pSalI2CHND->DevNum] = address;
HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat);
}
/* Check if the it's the last byte or not */
pSalI2CHND->I2CExd &= (~I2C_EXD_MTR_HOLD_BUS);
if (!stop) {
pSalI2CHND->I2CExd |= I2C_EXD_MTR_HOLD_BUS;
}
pSalI2CHND->pRXBuf = &i2crxtranbuf[pSalI2CHND->DevNum];
pSalI2CHND->pRXBuf->DataLen = length;
pSalI2CHND->pRXBuf->TargetAddr= address;//pSalI2CHND->I2CAckAddr;
pSalI2CHND->pRXBuf->RegAddr = 0;
pSalI2CHND->pRXBuf->pDataBuf = (u8 *)data;
if (RtkI2CReceive(pSalI2CHND) != HAL_OK) {
length = length - pSalI2CHND->pRXBuf->DataLen;
return ((int)length);
} else {
/* Calculate user time out parameters */
I2CInTOTcnt = 300;
if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) {
InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US);
InStartCount = HalTimerOp.HalTimerReadCount(1);
}
while((pSalI2CHND->DevSts != I2C_STS_IDLE) &&
(pSalI2CHND->DevSts != I2C_STS_ERROR) &&
(pSalI2CHND->DevSts != I2C_STS_TIMEOUT)) {
/* Time-Out check */
if (InTimeoutCount > 0) {
if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) {
pSalI2CHND->DevSts = I2C_STS_TIMEOUT;
pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO;
return ((int)(length));
}
} else {
if (I2CInTOTcnt == 0) {
pSalI2CHND->DevSts = I2C_STS_TIMEOUT;
pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO;
return ((int)(length));
}
}
}
if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT) {
return ((int)(length - pSalI2CHND->pRXBuf->DataLen));
} else {
return ((int)(length));
}
}
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
{
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
u32 I2CInTOTcnt = 0;
u32 InTimeoutCount = 0;
u32 InStartCount = 0;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
address = (address & 0xFE ) >>1;
pSalI2CHND->pInitDat->I2CAckAddr = address;
i2c_target_addr[pSalI2CHND->DevNum] = address;
HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat);
/* Check if the it's the last byte or not */
pSalI2CHND->I2CExd &= (~I2C_EXD_MTR_HOLD_BUS);
if (!stop) {
pSalI2CHND->I2CExd |= I2C_EXD_MTR_HOLD_BUS;
}
pSalI2CHND->pTXBuf = &i2ctxtranbuf[pSalI2CHND->DevNum];
pSalI2CHND->pTXBuf->DataLen = length;
pSalI2CHND->pTXBuf->TargetAddr= address;
pSalI2CHND->pTXBuf->RegAddr = 0;
pSalI2CHND->pTXBuf->pDataBuf = (u8 *)data;
if (RtkI2CSend(pSalI2CHND) != HAL_OK) {
length = length - pSalI2CHND->pTXBuf->DataLen;
return ((int)length);
} else {
/* Calculate user time out parameters */
I2CInTOTcnt = 300;
if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) {
InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US);
InStartCount = HalTimerOp.HalTimerReadCount(1);
}
while((pSalI2CHND->DevSts != I2C_STS_IDLE) &&
(pSalI2CHND->DevSts != I2C_STS_ERROR) &&
(pSalI2CHND->DevSts != I2C_STS_TIMEOUT)) {
/* Time-Out check */
if (InTimeoutCount > 0) {
if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) {
pSalI2CHND->DevSts = I2C_STS_TIMEOUT;
pSalI2CHND->ErrType = I2C_ERR_TX_ADD_TO;
return ((int)(length));
}
} else {
if (I2CInTOTcnt == 0) {
pSalI2CHND->DevSts = I2C_STS_TIMEOUT;
pSalI2CHND->ErrType = I2C_ERR_TX_ADD_TO;
return ((int)(length));
}
}
}
if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT) {
return ((int)(length - pSalI2CHND->pTXBuf->DataLen));
} else {
return ((int)(length));
}
}
}
int i2c_byte_read(i2c_t *obj, int last)
{
uint8_t i2cdatlocal;
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
/* Check if the it's the last byte or not */
pSalI2CHND->I2CExd &= (~I2C_EXD_MTR_HOLD_BUS);
if (!last) {
pSalI2CHND->I2CExd |= I2C_EXD_MTR_HOLD_BUS;
}
pSalI2CHND->pRXBuf = &i2crxtranbuf[pSalI2CHND->DevNum];
pSalI2CHND->pRXBuf->DataLen = 1;
pSalI2CHND->pRXBuf->TargetAddr= i2c_target_addr[pSalI2CHND->DevNum];
pSalI2CHND->pRXBuf->RegAddr = 0;
pSalI2CHND->pRXBuf->pDataBuf = &i2cdatlocal;
RtkI2CReceive(pSalI2CHND);
return (int)i2cdatlocal;
}
int i2c_byte_write(i2c_t *obj, int data)
{
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
u8 * dp = (u8 *)&address_save[pSalI2CHND->DevNum];
if(Byte_count[pSalI2CHND->DevNum]<3){
dp[Byte_count[pSalI2CHND->DevNum]] = data;
Byte_count[pSalI2CHND->DevNum]++;
if(Byte_count[pSalI2CHND->DevNum]==3){
address_save_int[pSalI2CHND->DevNum] = (dp[1]<<8)+dp[2];
}
return 1;
}
int address = (dp[0] & 0xFE ) >> 1;
dp[1]= (unsigned char)(address_save_int[pSalI2CHND->DevNum] >> 8);
dp[2]= (unsigned char)(address_save_int[pSalI2CHND->DevNum] & 0xFF);
dp[3]= (unsigned char)data;
pSalI2CHND->pInitDat->I2CAckAddr = address;
i2c_target_addr[pSalI2CHND->DevNum] = address;
HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat);
pSalI2CHND->I2CExd &= (~I2C_EXD_MTR_HOLD_BUS);
pSalI2CHND->pTXBuf = &i2ctxtranbuf[pSalI2CHND->DevNum];
pSalI2CHND->pTXBuf->DataLen = 3;
pSalI2CHND->pTXBuf->TargetAddr= i2c_target_addr[pSalI2CHND->DevNum];
pSalI2CHND->pTXBuf->RegAddr = 0;
pSalI2CHND->pTXBuf->pDataBuf = dp+1;
if (RtkI2CSend(pSalI2CHND) != HAL_OK) {
return 0;
}
address_save_int[pSalI2CHND->DevNum]++;
return 1;
}
void i2c_reset(i2c_t *obj)
{
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
/* Deinit I2C directly */
RtkI2CDeInitForPS(pSalI2CHND);
}
#if DEVICE_I2CSLAVE
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
{
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
address = (address & 0xFE ) >>1;
uint16_t i2c_default_addr = (uint16_t) pSalI2CHND->I2CAckAddr;
uint16_t i2c_user_addr = (uint16_t) address;
if (i2c_target_addr[pSalI2CHND->DevNum] != i2c_user_addr) {
pSalI2CHND->pInitDat->I2CAckAddr = address;
i2c_target_addr[pSalI2CHND->DevNum] = address;
HalI2CSetSarRtl8195a(pSalI2CHND->pInitDat);
}
}
void i2c_slave_mode(i2c_t *obj, int enable_slave)
{
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
/* Deinit I2C first */
i2c_reset(obj);
/* Load the user defined I2C clock */
pSalI2CHND->I2CMaster = I2C_MASTER_MODE;
if (enable_slave)
pSalI2CHND->I2CMaster = I2C_SLAVE_MODE;
/* Init I2C now */
RtkI2CInitForPS(pSalI2CHND);
pSalI2CHND->pInitDat->I2CAckAddr = i2c_target_addr[pSalI2CHND->DevNum];
HalI2CSetSarRtl8195a(pSalI2CHND->pInitDat);
}
// See I2CSlave.h
#define NoData 0 // the slave has not been addressed
#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
#define WriteGeneral 2 // the master is writing to all slave
#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
int i2c_slave_receive(i2c_t *obj)
{
int i2cslvrevsts = NoData;
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
i2cslvrevsts = RtkSalI2CSts(pSalI2CHND);
return i2cslvrevsts;
}
int i2c_slave_read(i2c_t *obj, char *data, int length)
{
u32 I2CInTOTcnt = 0;
u32 InTimeoutCount = 0;
u32 InStartCount = 0;
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
pSalI2CHND->pRXBuf = &i2crxtranbuf[pSalI2CHND->DevNum];
pSalI2CHND->pRXBuf->DataLen = length;
pSalI2CHND->pRXBuf->pDataBuf = (u8 *)data;
if (RtkI2CReceive(pSalI2CHND) != HAL_OK) {
return 0; //error
} else {
/* Calculate user time out parameters */
I2CInTOTcnt = 300;
if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) {
InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US);
InStartCount = HalTimerOp.HalTimerReadCount(1);
}
while((pSalI2CHND->DevSts != I2C_STS_IDLE) &&
(pSalI2CHND->DevSts != I2C_STS_ERROR) &&
(pSalI2CHND->DevSts != I2C_STS_TIMEOUT)) {
/* Time-Out check */
if (InTimeoutCount > 0) {
if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) {
pSalI2CHND->DevSts = I2C_STS_TIMEOUT;
pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO;
return ((int)(length));
}
} else {
if (I2CInTOTcnt == 0) {
pSalI2CHND->DevSts = I2C_STS_TIMEOUT;
pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO;
return ((int)(length));
}
}
}
if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT) {
return ((int)(length - pSalI2CHND->pTXBuf->DataLen));
} else {
return ((int)(length));
}
}
}
int i2c_slave_write(i2c_t *obj, const char *data, int length)
{
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
pSalI2CHND->pTXBuf = &i2ctxtranbuf[pSalI2CHND->DevNum];
pSalI2CHND->pTXBuf->DataLen = length;
pSalI2CHND->pTXBuf->pDataBuf = (u8 *)data;
if (RtkI2CSend(pSalI2CHND) != HAL_OK) {
return 0; //error
}
return 1;
}
#endif // CONFIG_I2C_SLAVE_EN
#endif // CONFIG_I2C_EN

510
targets/TARGET_Realtek/TARGET_AMEBA/log_uart_api.c Normal file
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@ -0,0 +1,510 @@
/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include "log_uart_api.h"
#include <string.h>
const u32 log_uart_support_rate[] = {
UART_BAUD_RATE_2400, UART_BAUD_RATE_4800, UART_BAUD_RATE_9600,
UART_BAUD_RATE_19200, UART_BAUD_RATE_38400, UART_BAUD_RATE_57600,
UART_BAUD_RATE_115200, UART_BAUD_RATE_921600, UART_BAUD_RATE_1152000,
0xFFFFFFFF
};
extern HAL_TIMER_OP HalTimerOp;
extern u32 ConfigDebugErr;
extern u32 ConfigDebugWarn;
extern u32 ConfigDebugInfo;
extern u32 CfgSysDebugErr;
extern u32 CfgSysDebugInfo;
extern u32 CfgSysDebugWarn;
extern HAL_Status RuartIsTimeout (u32 StartCount, u32 TimeoutCnt);
extern u32 HalLogUartInitSetting(HAL_LOG_UART_ADAPTER *pUartAdapter);
extern VOID HalLogUartSetBaudRate(HAL_LOG_UART_ADAPTER *pUartAdapter);
extern VOID HalLogUartSetLineCtrl(HAL_LOG_UART_ADAPTER *pUartAdapter);
extern VOID HalLogUartIrqHandle(VOID * Data);
int32_t log_uart_init (log_uart_t *obj, int baudrate, int data_bits, SerialParity parity, int stop_bits)
{
HAL_LOG_UART_ADAPTER *pUartAdapter;
int i;
_memset((void*)obj, 0, sizeof(log_uart_t));
pUartAdapter = &obj->log_hal_uart;
// Check Baud rate
for (i=0; log_uart_support_rate[i]!=0xFFFFFF; i++) {
if (log_uart_support_rate[i] == baudrate) {
break;
}
}
if (log_uart_support_rate[i]== 0xFFFFFF) {
DBG_UART_ERR("log_uart_init: Not support Baud Rate %d\n", baudrate);
return -1;
}
// check word width
if ((data_bits < 5) || (data_bits > 8)) {
DBG_UART_ERR("log_uart_init: Not support Word Width %d\n", data_bits);
return -1;
}
//4 Inital Log uart
pUartAdapter->BaudRate = baudrate;
pUartAdapter->DataLength = data_bits-5;
pUartAdapter->FIFOControl = FCR_FIFO_EN | FCR_TX_TRIG_HF | FCR_RX_TRIG_HF;
// only enable Rx linstatus at initial,
// Tx & Rx interrupt will be enabled @ transfer start time
pUartAdapter->IntEnReg = IER_ELSI;
switch (parity) {
case ParityNone:
pUartAdapter->Parity = LCR_PARITY_NONE;
break;
case ParityOdd:
pUartAdapter->Parity = LCR_PARITY_ODD;
break;
case ParityEven:
pUartAdapter->Parity = LCR_PARITY_EVEN;
break;
default:
DBG_UART_ERR("log_uart_init: Not support parity type %d\n", parity);
return -1;
}
if (stop_bits > 1) {
// if width is 5 bits, stop bit will be 1.5 bit
pUartAdapter->Stop = LCR_STOP_2B;
} else {
pUartAdapter->Stop = LCR_STOP_1B;
}
//4 Initial Log Uart
HalLogUartInitSetting(pUartAdapter);
// disable all debug message
ConfigDebugErr = 0;
ConfigDebugWarn = 0;
ConfigDebugInfo = 0;
CfgSysDebugErr = 0;
CfgSysDebugInfo = 0;
CfgSysDebugWarn = 0;
return 0;
}
void log_uart_free(log_uart_t *obj)
{
LOG_UART_ADAPTER UartAdapter;
// Recover the Log UART for debug message printing
//4 Release log uart reset and clock
LOC_UART_FCTRL(OFF);
LOC_UART_FCTRL(ON);
ACTCK_LOG_UART_CCTRL(ON);
//4 Inital Log uart
UartAdapter.BaudRate = UART_BAUD_RATE_38400;
UartAdapter.DataLength = UART_DATA_LEN_8BIT;
UartAdapter.FIFOControl = 0xC1;
UartAdapter.IntEnReg = 0x00;
UartAdapter.Parity = UART_PARITY_DISABLE;
UartAdapter.Stop = UART_STOP_1BIT;
// un_register current IRQ first
InterruptUnRegister(&(obj->log_hal_uart.IrqHandle));
//4 Initial Log Uart
HalLogUartInit(UartAdapter);
}
void log_uart_baud(log_uart_t *obj, int baudrate)
{
HAL_LOG_UART_ADAPTER *pUartAdapter;
int i;
pUartAdapter = &obj->log_hal_uart;
// Check Baud rate
for (i=0; log_uart_support_rate[i]!=0xFFFFFFFF; i++) {
if (log_uart_support_rate[i] == baudrate) {
break;
}
}
if (log_uart_support_rate[i]== 0xFFFFFF) {
DBG_UART_ERR("log_uart_baud: Not support Baud Rate %d\n", baudrate);
return;
}
pUartAdapter->BaudRate = baudrate;
HalLogUartSetBaudRate(pUartAdapter);
}
void log_uart_format(log_uart_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
HAL_LOG_UART_ADAPTER *pUartAdapter;
pUartAdapter = &obj->log_hal_uart;
// check word width
if ((data_bits < 5) || (data_bits > 8)) {
DBG_UART_ERR("log_uart_format: Not support Word Width %d\n", data_bits);
return;
}
//4 Inital Log uart
pUartAdapter->DataLength = data_bits - 5;
switch (parity) {
case ParityNone:
pUartAdapter->Parity = LCR_PARITY_NONE;
break;
case ParityOdd:
pUartAdapter->Parity = LCR_PARITY_ODD;
break;
case ParityEven:
pUartAdapter->Parity = LCR_PARITY_EVEN;
break;
default:
DBG_UART_ERR("log_uart_format: Not support parity type %d\n", parity);
return;
}
if (stop_bits > 1) {
// if width is 5 bits, stop bit will be 1.5 bit
pUartAdapter->Stop = LCR_STOP_2B;
} else {
pUartAdapter->Stop = LCR_STOP_1B;
}
HalLogUartSetLineCtrl(pUartAdapter);
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
void log_uart_irq_handler(log_uart_t *obj, loguart_irq_handler handler, uint32_t id)
{
HAL_LOG_UART_ADAPTER *pUartAdapter;
pUartAdapter = &(obj->log_hal_uart);
pUartAdapter->api_irq_handler = handler;
pUartAdapter->api_irq_id = id;
}
void log_uart_irq_set(log_uart_t *obj, LOG_UART_INT_ID irq, uint32_t enable)
{
HAL_LOG_UART_ADAPTER *pUartAdapter;
u8 int_en=0;
pUartAdapter = &(obj->log_hal_uart);
switch (irq) {
case IIR_RX_RDY:
int_en = IER_ERBFI;
break;
case IIR_THR_EMPTY:
int_en = IER_ETBEI;
break;
case IIR_RX_LINE_STATUS:
int_en = IER_ELSI;
break;
case IIR_MODEM_STATUS:
int_en = IER_EDSSI;
break;
default:
DBG_UART_WARN("log_uart_irq_set: Unknown Irq Id\n");
return;
}
if (enable) {
pUartAdapter->IntEnReg |= int_en;
} else {
// disable
pUartAdapter->IntEnReg &= (~int_en);
}
HalLogUartSetIntEn(pUartAdapter);
}
/******************************************************************************
* READ/WRITE
******************************************************************************/
char log_uart_getc(log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
while (!log_uart_readable(obj));
return (char)(HAL_UART_READ32(UART_REV_BUF_OFF) & 0xFF);
}
void log_uart_putc(log_uart_t *obj, char c)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
while (!log_uart_writable(obj));
HAL_UART_WRITE8(UART_TRAN_HOLD_OFF, c);
}
int log_uart_readable(log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
volatile u8 line_status;
line_status = HAL_UART_READ8(UART_LINE_STATUS_REG_OFF);
if (line_status & LSR_DR) {
return 1;
} else {
return 0;
}
}
int log_uart_writable(log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
volatile u8 line_status;
line_status = HAL_UART_READ8(UART_LINE_STATUS_REG_OFF);
if (line_status & LSR_THRE) {
return 1;
} else {
return 0;
}
}
void log_uart_clear(log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
HalLogUartRstFIFO(pUartAdapter, (LOG_UART_RST_TX_FIFO|LOG_UART_RST_TX_FIFO));
pUartAdapter->TxCount = 0;
pUartAdapter->RxCount = 0;
}
void log_uart_clear_tx(log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
HalLogUartRstFIFO(pUartAdapter, LOG_UART_RST_TX_FIFO);
pUartAdapter->TxCount = 0;
}
void log_uart_clear_rx(log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
HalLogUartRstFIFO(pUartAdapter, LOG_UART_RST_RX_FIFO);
pUartAdapter->RxCount = 0;
}
void log_uart_break_set(log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
u32 RegValue;
RegValue = HAL_UART_READ32(UART_LINE_CTL_REG_OFF);
RegValue |= LCR_BC;
HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, RegValue);
}
void log_uart_break_clear(log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
u32 RegValue;
RegValue = HAL_UART_READ32(UART_LINE_CTL_REG_OFF);
RegValue &= ~LCR_BC;
HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, RegValue);
}
void log_uart_tx_comp_handler(log_uart_t *obj, void *handler, uint32_t id)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
pUartAdapter->TxCompCallback = (void(*)(void*))handler;
pUartAdapter->TxCompCbPara = (void*)id;
}
void log_uart_rx_comp_handler(log_uart_t *obj, void *handler, uint32_t id)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
pUartAdapter->RxCompCallback = (void(*)(void*))handler;
pUartAdapter->RxCompCbPara = (void*)id;
}
void log_uart_line_status_handler(log_uart_t *obj, void *handler, uint32_t id)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
pUartAdapter->LineStatusCallback = (void(*)(void*, u8))handler;
pUartAdapter->LineStatusCbPara = (void*)id;
}
// Blocked(busy wait) receive, return received bytes count
int32_t log_uart_recv (log_uart_t *obj, char *prxbuf, uint32_t len, uint32_t timeout_ms)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
int ret;
ret = (int)HalLogUartRecv(pUartAdapter, prxbuf, len, timeout_ms);
return (ret);
}
// Blocked(busy wait) send, return transmitted bytes count
int32_t log_uart_send (log_uart_t *obj, char *ptxbuf, uint32_t len, uint32_t timeout_ms)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
int ret;
ret = (int)HalLogUartSend(pUartAdapter, ptxbuf, len, timeout_ms);
return (ret);
}
// Interrupt mode(no wait) receive, return HAL function result
int32_t log_uart_recv_stream (log_uart_t *obj, char *prxbuf, uint32_t len)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
int ret;
ret = (int)HalLogUartIntRecv(pUartAdapter, (u8*)prxbuf, len);
return (ret);
}
// Interrupt Mode(no wait) send, return HAL function result
int32_t log_uart_send_stream (log_uart_t *obj, char *ptxbuf, uint32_t len)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
int ret;
ret = (int)HalLogUartIntSend(pUartAdapter, (u8*)ptxbuf, len);
return (ret);
}
// Interrupt mode(no wait) receive with timeout
// return the byte count received before timeout, or error(<0)
int32_t log_uart_recv_stream_timeout (log_uart_t *obj, char *prxbuf, uint32_t len,
uint32_t timeout_ms, void *force_cs)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
uint32_t TimeoutCount=0, StartCount;
int ret;
void (*task_yield)(void);
task_yield = NULL;
ret = (int)HalLogUartIntRecv(pUartAdapter, (u8*)prxbuf, len);
if ((ret == HAL_OK) && (timeout_ms > 0)) {
TimeoutCount = (timeout_ms*1000/TIMER_TICK_US);
StartCount = HalTimerOp.HalTimerReadCount(1);
task_yield = (void (*)(void))force_cs;
while (pUartAdapter->RxCount > 0) {
if (HAL_TIMEOUT == RuartIsTimeout(StartCount, TimeoutCount)) {
HalLogUartAbortIntRecv(pUartAdapter);
break;
}
if (NULL != task_yield) {
task_yield();
}
}
return (len - pUartAdapter->RxCount);
} else {
return (-ret);
}
}
// Abort Interrupt Mode TX and return how many bytes data has been sent
int32_t log_uart_send_stream_abort (log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
int ret;
HalLogUartAbortIntSend(pUartAdapter);
ret = (u32)pUartAdapter->pTxBuf - (u32)pUartAdapter->pTxStartAddr;
return (ret);
}
// Abort Interrupt Mode RX and return how many bytes data has been received
int32_t log_uart_recv_stream_abort (log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
int ret;
HalLogUartAbortIntRecv(pUartAdapter);
ret = (u32)pUartAdapter->pRxBuf - (u32)pUartAdapter->pRxStartAddr;
return (ret);
}
void log_uart_disable (log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
HalLogUartDisable(pUartAdapter);
}
void log_uart_enable (log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
HalLogUartEnable(pUartAdapter);
}
// to read Line-Status register
// Bit 0: RX Data Ready
// Bit 1: Overrun Error
// Bit 2: Parity Error
// Bit 3: Framing Error
// Bit 4: Break Interrupt (received data input is held in 0 state for a longer than a full word tx time)
// Bit 5: TX FIFO empty (THR empty)
// Bit 6: TX FIFO empty (THR & TSR both empty)
// Bit 7: Receiver FIFO Error (parity error, framing error or break indication)
uint8_t log_uart_raed_lsr(log_uart_t *obj)
{
uint8_t LineStatus;
LineStatus = HAL_UART_READ8(UART_LINE_STATUS_REG_OFF);
return LineStatus;
}
// to read Modem-Status register
// Bit 0: DCTS, The CTS line has changed its state
// Bit 1: DDSR, The DSR line has changed its state
// Bit 2: TERI, RI line has changed its state from low to high state
// Bit 3: DDCD, DCD line has changed its state
// Bit 4: Complement of the CTS input
// Bit 5: Complement of the DSR input
// Bit 6: Complement of the RI input
// Bit 7: Complement of the DCD input
uint8_t log_uart_raed_msr(log_uart_t *obj)
{
uint8_t RegValue;
RegValue = HAL_UART_READ8(UART_MODEM_STATUS_REG_OFF);
return RegValue;
}

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targets/TARGET_Realtek/TARGET_AMEBA/log_uart_api.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef LOG_UART_API_H
#define LOG_UART_API_H
#include "device.h"
#include "serial_api.h"
#include "hal_log_uart.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef void (*loguart_irq_handler)(uint32_t id, LOG_UART_INT_ID event);
typedef struct log_uart_s log_uart_t;
int32_t log_uart_init (log_uart_t *obj, int baudrate, int data_bits, SerialParity parity, int stop_bits);
void log_uart_free(log_uart_t *obj);
void log_uart_baud(log_uart_t *obj, int baudrate);
void log_uart_format(log_uart_t *obj, int data_bits, SerialParity parity, int stop_bits);
void log_uart_irq_handler(log_uart_t *obj, loguart_irq_handler handler, uint32_t id);
void log_uart_irq_set(log_uart_t *obj, LOG_UART_INT_ID irq, uint32_t enable);
char log_uart_getc(log_uart_t *obj);
void log_uart_putc(log_uart_t *obj, char c);
int log_uart_readable(log_uart_t *obj);
int log_uart_writable(log_uart_t *obj);
void log_uart_clear(log_uart_t *obj);
void log_uart_clear_tx(log_uart_t *obj);
void log_uart_clear_rx(log_uart_t *obj);
void log_uart_break_set(log_uart_t *obj);
void log_uart_break_clear(log_uart_t *obj);
void log_uart_tx_comp_handler(log_uart_t *obj, void *handler, uint32_t id);
void log_uart_rx_comp_handler(log_uart_t *obj, void *handler, uint32_t id);
void log_uart_line_status_handler(log_uart_t *obj, void *handler, uint32_t id);
int32_t log_uart_recv (log_uart_t *obj, char *prxbuf, uint32_t len, uint32_t timeout_ms);
int32_t log_uart_send (log_uart_t *obj, char *ptxbuf, uint32_t len, uint32_t timeout_ms);
int32_t log_uart_recv_stream (log_uart_t *obj, char *prxbuf, uint32_t len);
int32_t log_uart_send_stream (log_uart_t *obj, char *ptxbuf, uint32_t len);
int32_t log_uart_recv_stream_timeout (log_uart_t *obj, char *prxbuf, uint32_t len,
uint32_t timeout_ms, void *force_cs);
int32_t log_uart_send_stream_abort (log_uart_t *obj);
int32_t log_uart_recv_stream_abort (log_uart_t *obj);
void log_uart_disable (log_uart_t *obj);
void log_uart_enable (log_uart_t *obj);
uint8_t log_uart_raed_lsr(log_uart_t *obj);
uint8_t log_uart_raed_msr(log_uart_t *obj);
#ifdef __cplusplus
}
#endif
#endif // end of "#ifndef LOG_UART_API_H"

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targets/TARGET_Realtek/TARGET_AMEBA/port_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include "port_api.h"
#include "pinmap.h"
#include "gpio_api.h"
#include "PinNames.h"
#if CONFIG_GPIO_EN
#if DEVICE_PORTIN || DEVICE_PORTOUT
#define GPIO_PORT_NUM 3
#define GPIO_PORT_WIDTH 32
#define GPIO_PORT_WIDTH_MAX 32
const u8 Default_Port_PinDef[GPIO_PORT_NUM][GPIO_PORT_WIDTH+1] = {
// Port 0 has these pin:
{PA_0, PA_1, PB_3, PB_4,
PB_6, PB_7, PC_1, PC_3,
PC_4, PC_5, PC_6, PC_7,
PC_8, PC_9, PD_1, PD_3,
PD_4, PD_5, PD_6, PD_7,
PD_9, PE_1, PE_2, PE_3,
PE_5, PE_6, PE_7, PE_8,
PG_3, PH_1, PH_3, PH_5,
0xFF},
// Port 1
{PA_2, PA_3, PA_4, PA_5,
PA_6, PA_7, PB_0, PB_1,
PB_2, PB_5, PC_0, PC_2,
PD_0, PD_2, PD_8, PE_0,
PE_4, PE_9, PE_A, PF_0,
PF_1, PF_2, PF_3, PF_4,
PF_5, PG_0, PG_1, PG_2,
PG_4, PG_5, PG_6, PG_7,
0xFF},
// Port 2
{PH_0, PH_2, PH_4, PH_6,
PH_7, PI_0, PI_1, PI_2,
PI_3, PI_4, PI_5, PI_6,
PI_7, PJ_0, PJ_1, PJ_2,
PJ_3, PJ_4, PJ_5, PJ_6,
PK_0, PK_1, PK_2, PK_3,
PK_4, PK_5, PK_6,
0xFF}
};
extern const u8 GPIO_SWPORT_DR_TBL[];
extern const u8 GPIO_EXT_PORT_TBL[];
extern VOID HAL_GPIO_Init(HAL_GPIO_PIN *GPIO_Pin);
extern u32 HAL_GPIO_GetPinName(u32 chip_pin);
// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...)
// low nibble = pin number
PinName port_pin(PortName port, int pin_n)
{
return (PinName)(pin_n + (port << 4));
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
{
u32 i;
if (port >= GPIO_PORT_NUM) {
DBG_GPIO_ERR("port_init: Invalid port num(%d), max port num is %d\r\n", \
port, (GPIO_PORT_NUM-1));
}
// Fill PORT object structure for future use
obj->port = port;
obj->mask = mask;
obj->direction = dir;
if (obj->pin_def == NULL) {
DBG_GPIO_ERR("Port Define Table isn't assigned\n");
obj->pin_def = (uint8_t*)&Default_Port_PinDef[port][0];
}
i=0;
while (obj->pin_def[i] != 0xff) {
i++;
if (i == GPIO_PORT_WIDTH_MAX) {
break;
}
}
obj->mask &= ((1<<i) - 1);
port_dir(obj, dir);
}
void port_dir(port_t *obj, PinDirection dir)
{
uint32_t i;
HAL_GPIO_PIN GPIO_Pin;
obj->direction = dir;
for (i = 0; i < GPIO_PORT_WIDTH_MAX; i++) { // Process all pins
if (obj->pin_def[i] == 0xff) {
// end of table
break;
}
if (obj->mask & (1 << i)) { // If the pin is used
GPIO_Pin.pin_name = HAL_GPIO_GetPinName(obj->pin_def[i]); // get the IP pin name
if (dir == PIN_OUTPUT) {
GPIO_Pin.pin_mode = DOUT_PUSH_PULL;
} else { // PIN_INPUT
GPIO_Pin.pin_mode = DIN_PULL_NONE;
}
HAL_GPIO_Init(&GPIO_Pin);
}
}
}
void port_mode(port_t *obj, PinMode mode)
{
uint32_t i;
for (i = 0; i < GPIO_PORT_WIDTH_MAX; i++) { // Process all pins
if (obj->pin_def[i] == 0xff) {
// end of table
break;
}
if (obj->mask & (1 << i)) { // If the pin is used
pin_mode(obj->pin_def[i], mode);
}
}
}
void port_write(port_t *obj, int value)
{
uint32_t i;
uint32_t pin_name;
uint8_t port_num;
uint8_t pin_num;
uint32_t hal_port[3];
uint8_t port_changed[3];
for (i=0;i<3;i++) {
hal_port[i] = HAL_READ32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[i]);
port_changed[i] = 0;
}
for (i = 0; i < GPIO_PORT_WIDTH_MAX; i++) { // Process all pins
if (obj->pin_def[i] == 0xff) {
// end of table
break;
}
if (obj->mask & (1 << i)) { // If the pin is used
pin_name = HAL_GPIO_GetPinName(obj->pin_def[i]); // get the IP pin name
port_num = HAL_GPIO_GET_PORT_BY_NAME(pin_name);
pin_num = HAL_GPIO_GET_PIN_BY_NAME(pin_name);
hal_port[port_num] &= ~(1 << pin_num);
hal_port[port_num] |= (((value>>i) & 0x01)<< pin_num);
port_changed[port_num] = 1;
}
}
for (i=0;i<3;i++) {
if (port_changed[i]) {
HAL_WRITE32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[i], hal_port[i]);
}
}
}
int port_read(port_t *obj)
{
int value=0;
u32 i;
uint32_t pin_name;
uint8_t port_num;
uint8_t pin_num;
uint32_t hal_port[3];
for (i=0;i<3;i++) {
hal_port[i] = HAL_READ32(GPIO_REG_BASE, GPIO_EXT_PORT_TBL[i]);
}
for (i = 0; i < GPIO_PORT_WIDTH_MAX; i++) { // Process all pins
if (obj->pin_def[i] == 0xff) {
// end of table
break;
}
if (obj->mask & (1 << i)) { // If the pin is used
pin_name = HAL_GPIO_GetPinName(obj->pin_def[i]); // get the IP pin name
port_num = HAL_GPIO_GET_PORT_BY_NAME(pin_name);
pin_num = HAL_GPIO_GET_PIN_BY_NAME(pin_name);
if (hal_port[port_num] & (1<<pin_num)) {
value |= (1<<i);
}
}
}
return value;
}
#endif //#if DEVICE_PORTIN || DEVICE_PORTOUT
#endif //#if CONFIG_GPIO_EN

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targets/TARGET_Realtek/TARGET_AMEBA/pwmout_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "device.h"
#include "objects.h"
#include "pinmap.h"
#if DEVICE_PWMOUT
#ifdef CONFIG_PWM_EN
#include "pwmout_api.h"
static const PinMap PinMap_PWM[] = {
{PB_4, RTL_PIN_PERI(PWM0, 0, S0), RTL_PIN_FUNC(PWM0, S0)},
{PB_5, RTL_PIN_PERI(PWM1, 1, S0), RTL_PIN_FUNC(PWM1, S0)},
{PB_6, RTL_PIN_PERI(PWM2, 2, S0), RTL_PIN_FUNC(PWM2, S0)},
{PB_7, RTL_PIN_PERI(PWM3, 3, S0), RTL_PIN_FUNC(PWM3, S0)},
{PC_0, RTL_PIN_PERI(PWM0, 0, S1), RTL_PIN_FUNC(PWM0, S1)},
{PC_1, RTL_PIN_PERI(PWM1, 1, S1), RTL_PIN_FUNC(PWM1, S1)},
{PC_2, RTL_PIN_PERI(PWM2, 2, S1), RTL_PIN_FUNC(PWM2, S1)},
{PC_3, RTL_PIN_PERI(PWM3, 3, S1), RTL_PIN_FUNC(PWM3, S1)},
{PD_3, RTL_PIN_PERI(PWM0, 0, S2), RTL_PIN_FUNC(PWM0, S2)},
{PD_4, RTL_PIN_PERI(PWM1, 1, S2), RTL_PIN_FUNC(PWM1, S2)},
{PD_5, RTL_PIN_PERI(PWM2, 2, S2), RTL_PIN_FUNC(PWM2, S2)},
{PD_6, RTL_PIN_PERI(PWM3, 3, S2), RTL_PIN_FUNC(PWM3, S2)},
{PE_0, RTL_PIN_PERI(PWM0, 0, S3), RTL_PIN_FUNC(PWM0, S3)},
{PE_1, RTL_PIN_PERI(PWM1, 1, S3), RTL_PIN_FUNC(PWM1, S3)},
{PE_2, RTL_PIN_PERI(PWM2, 2, S3), RTL_PIN_FUNC(PWM2, S3)},
{PE_3, RTL_PIN_PERI(PWM3, 3, S3), RTL_PIN_FUNC(PWM3, S3)},
{NC, NC, 0}
};
void pwmout_init(pwmout_t* obj, PinName pin)
{
uint32_t peripheral;
u32 pwm_idx;
u32 pin_sel;
DBG_PWM_INFO("%s: Init PWM for pin(0x%x)\n", __FUNCTION__, pin);
// Get the peripheral name from the pin and assign it to the object
peripheral = pinmap_peripheral(pin, PinMap_PWM);
if (unlikely(peripheral == NC)) {
DBG_PWM_ERR("%s: Cannot find matched pwm for this pin(0x%x)\n", __FUNCTION__, pin);
return;
}
pwm_idx = RTL_GET_PERI_IDX(peripheral);
pin_sel = RTL_GET_PERI_SEL(peripheral);
obj->pwm_idx = pwm_idx;
obj->pin_sel = pin_sel;
obj->period = 0;
obj->pulse = 0;
_memset((void *)&obj->pwm_hal_adp, 0, sizeof(HAL_PWM_ADAPTER));
if (HAL_OK != HAL_Pwm_Init(&obj->pwm_hal_adp, pwm_idx, pin_sel)) {
DBG_PWM_ERR("pwmout_init Err!\n");
return;
}
pwmout_period_us(obj, 20000); // 20 ms per default
HAL_Pwm_Enable(&obj->pwm_hal_adp);
}
void pwmout_free(pwmout_t* obj)
{
HAL_Pwm_Disable(&obj->pwm_hal_adp);
}
void pwmout_write(pwmout_t* obj, float value)
{
if (value < (float)0.0) {
value = 0.0;
} else if (value > (float)1.0) {
value = 1.0;
}
obj->pulse = (uint32_t)((float)obj->period * value);
HAL_Pwm_SetDuty(&obj->pwm_hal_adp, obj->period, obj->pulse);
}
float pwmout_read(pwmout_t* obj)
{
float value = 0;
if (obj->period > 0) {
value = (float)(obj->pulse) / (float)(obj->period);
}
return ((value > (float)1.0) ? (float)(1.0) : (value));
}
void pwmout_period(pwmout_t* obj, float seconds)
{
pwmout_period_us(obj, (int)(seconds * 1000000.0f));
}
void pwmout_period_ms(pwmout_t* obj, int ms)
{
pwmout_period_us(obj, (int)(ms * 1000));
}
void pwmout_period_us(pwmout_t* obj, int us)
{
float dc = pwmout_read(obj);
obj->period = us;
// Set duty cycle again
pwmout_write(obj, dc);
}
void pwmout_pulsewidth(pwmout_t* obj, float seconds)
{
pwmout_pulsewidth_us(obj, (int)(seconds * 1000000.0f));
}
void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
{
pwmout_pulsewidth_us(obj, ms * 1000);
}
void pwmout_pulsewidth_us(pwmout_t* obj, int us)
{
float value = (float)us / (float)obj->period;
pwmout_write(obj, value);
}
#endif // #ifdef CONFIG_PWM_EN
#endif // #if DEVICE_PWMOUT

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "rtc_api.h"
#if DEVICE_RTC
#include <time.h>
#include "timer_api.h" // software-RTC: use a g-timer for the tick of the RTC
#define SW_RTC_TIMER_ID TIMER4
static gtimer_t sw_rtc;
static struct tm rtc_timeinfo;
static int sw_rtc_en=0;
static const u8 dim[14] = {
31, 0, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31, 31, 28 };
static inline bool is_leap_year(unsigned int year)
{
return (!(year % 4) && (year % 100)) || !(year % 400);
}
static u8 days_in_month (u8 month, u8 year)
{
u8 ret = dim [ month - 1 ];
if (ret == 0)
ret = is_leap_year (year) ? 29 : 28;
return ret;
}
void sw_rtc_tick_handler(uint32_t id)
{
if(++rtc_timeinfo.tm_sec > 59) { // Increment seconds, check for overflow
rtc_timeinfo.tm_sec = 0; // Reset seconds
if(++rtc_timeinfo.tm_min > 59) { // Increment minutes, check for overflow
rtc_timeinfo.tm_min = 0; // Reset minutes
if(++rtc_timeinfo.tm_hour > 23) { // Increment hours, check for overflow
rtc_timeinfo.tm_hour = 0; // Reset hours
++rtc_timeinfo.tm_yday; // Increment day of year
if(++rtc_timeinfo.tm_wday > 6) // Increment day of week, check for overflow
rtc_timeinfo.tm_wday = 0; // Reset day of week
// Increment day of month, check for overflow
if(++rtc_timeinfo.tm_mday >
days_in_month(rtc_timeinfo.tm_mon, rtc_timeinfo.tm_year + 1900)) {
rtc_timeinfo.tm_mday = 1; // Reset day of month
if(++rtc_timeinfo.tm_mon > 11) { // Increment month, check for overflow
rtc_timeinfo.tm_mon = 0; // Reset month
rtc_timeinfo.tm_yday = 0; // Reset day of year
++rtc_timeinfo.tm_year; // Increment year
} // - year
} // - month
} // - day
} // - hour
}
}
void rtc_init(void)
{
// Initial a periodical timer
gtimer_init(&sw_rtc, SW_RTC_TIMER_ID);
// Tick every 1 sec
gtimer_start_periodical(&sw_rtc, 1000000, (void*)sw_rtc_tick_handler, (uint32_t)&sw_rtc);
sw_rtc_en = 1;
}
void rtc_free(void)
{
sw_rtc_en = 0;
gtimer_stop(&sw_rtc);
gtimer_deinit(&sw_rtc);
}
int rtc_isenabled(void)
{
return(sw_rtc_en);
}
time_t rtc_read(void)
{
time_t t;
// Convert to timestamp
t = mktime(&rtc_timeinfo);
return t;
}
void rtc_write(time_t t)
{
// Convert the time in to a tm
struct tm *timeinfo = localtime(&t);
if (timeinfo == NULL) {
// Error
return;
}
gtimer_stop(&sw_rtc);
// Set the RTC
rtc_timeinfo.tm_sec = timeinfo->tm_sec;
rtc_timeinfo.tm_min = timeinfo->tm_min;
rtc_timeinfo.tm_hour = timeinfo->tm_hour;
rtc_timeinfo.tm_mday = timeinfo->tm_mday;
rtc_timeinfo.tm_wday = timeinfo->tm_wday;
rtc_timeinfo.tm_yday = timeinfo->tm_yday;
rtc_timeinfo.tm_mon = timeinfo->tm_mon;
rtc_timeinfo.tm_year = timeinfo->tm_year;
gtimer_start(&sw_rtc);
}
#endif // endof "#if DEVICE_RTC"

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/* mbed Microcontroller Library
* Copyright (c) 2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if DEVICE_EMAC
#include <stdio.h>
#include "mbed_assert.h"
#include "mbed_events.h"
#include "emac_api.h"
#include "rtos.h"
#include "lwip/pbuf.h"
#include "netif/etharp.h"
#include "lwip_intf.h"
#include "wifi_constants.h"
#include "wifi_conf.h"
#define RTW_EMAC_MTU_SIZE (1500U)
static emac_interface_t *_emac;
static emac_link_input_fn link_input_cb;
static emac_link_state_change_fn link_state_cb;
static void *link_input_data;
static void *link_state_data;
static uint32_t wlan_get_mtu_size(emac_interface_t *emac)
{
return RTW_EMAC_MTU_SIZE;
}
static void wlan_get_ifname(emac_interface_t *emac, char *name, uint8_t size)
{
MBED_ASSERT(name != NULL);
strncpy(name, "r0", size);
}
static uint8_t wlan_get_hwaddr_size(emac_interface_t *emac)
{
return ETHARP_HWADDR_LEN;
}
static void wlan_get_hwaddr(emac_interface_t *emac, uint8_t *addr)
{
char mac[20];
if(RTW_SUCCESS == wifi_get_mac_address(mac))
{
if (sscanf(mac, "%x:%x:%x:%x:%x:%x", &addr[0], &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6)
printf("Get HW address failed\r\n");
}else{
printf("Get HW address failed\r\n");
}
}
static void wlan_set_hwaddr(emac_interface_t *emac, uint8_t *addr)
{
}
static bool wlan_link_out(emac_interface_t *emac, emac_stack_mem_t *buf)
{
struct eth_drv_sg * sg_list=0;
int sg_len = 0;
int tot_len;
struct pbuf *p;
bool ret = true;
if (!rltk_wlan_running(0)) {
return false;
}
sg_list = (struct eth_drv_sg *)malloc(sizeof(struct eth_drv_sg)*MAX_ETH_DRV_SG);
if(sg_list == 0){//malloc fail
return false;
}
emac_stack_mem_ref(emac, buf);
p = (struct pbuf *)buf;
tot_len = p->tot_len;
for (; p != NULL && sg_len < MAX_ETH_DRV_SG; p = p->next) {
sg_list[sg_len].buf = (uint32_t) p->payload;
sg_list[sg_len].len = p->len;
sg_len++;
}
if (sg_len) {
if (rltk_wlan_send(0, sg_list, sg_len, tot_len) != 0) {
ret = false;
}
}
emac_stack_mem_free(emac, buf);
free(sg_list);
return ret;
}
static bool wlan_power_up(emac_interface_t *emac)
{
wifi_on(RTW_MODE_STA);
wait_ms(1000);
return true;
}
static void wlan_power_down(emac_interface_t *emac)
{
wifi_off();
}
static void wlan_set_link_input_cb(emac_interface_t *emac, emac_link_input_fn cb, void *data)
{
link_input_cb = cb;
link_input_data = data;
}
static void wlan_set_link_state_cb(emac_interface_t *emac, emac_link_state_change_fn cb, void *data)
{
link_state_cb = cb;
link_state_data = data;
}
void wlan_emac_recv(struct netif *netif, int len)
{
struct eth_drv_sg sg_list[MAX_ETH_DRV_SG];
emac_stack_mem_t *buf;
struct pbuf *p;
int sg_len = 0;
if (!rltk_wlan_running(0)) {
return;
}
if (len > MAX_ETH_MSG || len < 0) {
len = MAX_ETH_MSG;
}
buf = emac_stack_mem_alloc(NULL, len, 0);
if (buf == NULL) {
return;
}
p = (struct pbuf *)buf;
for (; p != NULL && sg_len < MAX_ETH_DRV_SG; p = p->next) {
sg_list[sg_len].buf = (uint32_t) p->payload;
sg_list[sg_len].len = p->len;
sg_len++;
}
rltk_wlan_recv(0, sg_list, sg_len);
if (link_input_cb) {
link_input_cb(link_input_data, buf);
}
return;
}
const emac_interface_ops_t wlan_emac_interface = {
.get_mtu_size = wlan_get_mtu_size,
.get_ifname = wlan_get_ifname,
.get_hwaddr_size = wlan_get_hwaddr_size,
.get_hwaddr = wlan_get_hwaddr,
.set_hwaddr = wlan_set_hwaddr,
.link_out = wlan_link_out,
.power_up = wlan_power_up,
.power_down = wlan_power_down,
.set_link_input_cb = wlan_set_link_input_cb,
.set_link_state_cb = wlan_set_link_state_cb
};
void mbed_default_mac_address(char *mac) {
unsigned char RTK_mac_addr[3] = {0x00, 0xE0, 0x4C}; // default Realtek mac address
mac[0] = RTK_mac_addr[0];
mac[1] = RTK_mac_addr[1];
mac[2] = RTK_mac_addr[2];
mac[3] = 0x87;
mac[4] = 0x00;
mac[5] = 0x01;
return;
}
void mbed_mac_address(char *mac)
{
char hwaddr[20];
if(RTW_SUCCESS == wifi_get_mac_address(hwaddr))
{
if (sscanf(hwaddr, "%x:%x:%x:%x:%x:%x", &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]) != 6)
printf("Get HW address failed\r\n");
}else{
printf("Get HW address failed\r\n");
mbed_default_mac_address(mac);
}
}
void wlan_emac_link_change(bool up)
{
if (link_state_cb) {
link_state_cb(link_state_data, up);
}
}
emac_interface_t *wlan_emac_init_interface()
{
if (_emac == NULL) {
_emac = new emac_interface_t();
if (_emac == NULL) {//new emac_interface_t fail
printf("emac initialization failed\r\n");
return NULL;
}
_emac->hw = NULL;
memcpy((void*)&_emac->ops, &wlan_emac_interface, sizeof(wlan_emac_interface));
}
return _emac;
}
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_WLAN_EMAC_H
#define MBED_WLAN_EMAC_H
#include "emac_api.h"
extern void wlan_emac_link_change(bool up);
extern emac_interface_t *wlan_emac_init_interface();
extern void wlan_emac_recv(struct netif *netif, uint32_t len);
#endif

279
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/dlist.h Normal file
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/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef __LIST_H
#define __LIST_H
#if defined ( __CC_ARM )
#ifndef inline
#define inline __inline
#endif
#endif
/* This file is from Linux Kernel (include/linux/list.h)
* and modified by simply removing hardware prefetching of list items.
* Here by copyright, credits attributed to wherever they belong.
* Kulesh Shanmugasundaram (kulesh [squiggly] isis.poly.edu)
*/
/*
* Simple doubly linked list implementation.
*
* Some of the internal functions ("__xxx") are useful when
* manipulating whole lists rather than single entries, as
* sometimes we already know the next/prev entries and we can
* generate better code by using them directly rather than
* using the generic single-entry routines.
*/
struct list_head {
struct list_head *next, *prev;
};
#define LIST_HEAD_INIT(name) { &(name), &(name) }
#define LIST_HEAD(name) \
struct list_head name = LIST_HEAD_INIT(name)
#define INIT_LIST_HEAD(ptr) do { \
(ptr)->next = (ptr); (ptr)->prev = (ptr); \
} while (0)
/*
* Insert a new entry between two known consecutive entries.
*
* This is only for internal list manipulation where we know
* the prev/next entries already!
*/
static inline void __list_add(struct list_head *newitem,
struct list_head *prev,
struct list_head *next)
{
next->prev = newitem;
newitem->next = next;
newitem->prev = prev;
prev->next = newitem;
}
/**
* list_add - add a new entry
* @new: new entry to be added
* @head: list head to add it after
*
* Insert a new entry after the specified head.
* This is good for implementing stacks.
*/
static inline void list_add(struct list_head *newitem, struct list_head *head)
{
__list_add(newitem, head, head->next);
}
/**
* list_add_tail - add a new entry
* @new: new entry to be added
* @head: list head to add it before
*
* Insert a new entry before the specified head.
* This is useful for implementing queues.
*/
static inline void list_add_tail(struct list_head *newitem, struct list_head *head)
{
__list_add(newitem, head->prev, head);
}
/*
* Delete a list entry by making the prev/next entries
* point to each other.
*
* This is only for internal list manipulation where we know
* the prev/next entries already!
*/
static inline void __list_del(struct list_head *prev, struct list_head *next)
{
next->prev = prev;
prev->next = next;
}
/**
* list_del - deletes entry from list.
* @entry: the element to delete from the list.
* Note: list_empty on entry does not return true after this, the entry is in an undefined state.
*/
static inline void list_del(struct list_head *entry)
{
__list_del(entry->prev, entry->next);
entry->next = (struct list_head *) 0;
entry->prev = (struct list_head *) 0;
}
/**
* list_del_init - deletes entry from list and reinitialize it.
* @entry: the element to delete from the list.
*/
static inline void list_del_init(struct list_head *entry)
{
__list_del(entry->prev, entry->next);
INIT_LIST_HEAD(entry);
}
/**
* list_move - delete from one list and add as another's head
* @list: the entry to move
* @head: the head that will precede our entry
*/
static inline void list_move(struct list_head *list, struct list_head *head)
{
__list_del(list->prev, list->next);
list_add(list, head);
}
/**
* list_move_tail - delete from one list and add as another's tail
* @list: the entry to move
* @head: the head that will follow our entry
*/
static inline void list_move_tail(struct list_head *list,
struct list_head *head)
{
__list_del(list->prev, list->next);
list_add_tail(list, head);
}
/**
* list_empty - tests whether a list is empty
* @head: the list to test.
*/
static inline int list_empty(struct list_head *head)
{
return head->next == head;
}
static inline void __list_splice(struct list_head *list,
struct list_head *head)
{
struct list_head *first = list->next;
struct list_head *last = list->prev;
struct list_head *at = head->next;
first->prev = head;
head->next = first;
last->next = at;
at->prev = last;
}
/**
* list_splice - join two lists
* @list: the new list to add.
* @head: the place to add it in the first list.
*/
static inline void list_splice(struct list_head *list, struct list_head *head)
{
if (!list_empty(list))
__list_splice(list, head);
}
/**
* list_splice_init - join two lists and reinitialise the emptied list.
* @list: the new list to add.
* @head: the place to add it in the first list.
*
* The list at @list is reinitialised
*/
static inline void list_splice_init(struct list_head *list,
struct list_head *head)
{
if (!list_empty(list)) {
__list_splice(list, head);
INIT_LIST_HEAD(list);
}
}
/**
* list_entry - get the struct for this entry
* @ptr: the &struct list_head pointer.
* @type: the type of the struct this is embedded in.
* @member: the name of the list_struct within the struct.
*/
#define list_entry(ptr, type, member) \
((type *)((char *)(ptr)-(unsigned long)(&((type *)0)->member)))
/**
* list_first_entry - get the first element from a list
* @ptr: the list head to take the element from.
* @type: the type of the struct this is embedded in.
* @member: the name of the list_head within the struct.
*
* Note, that list is expected to be not empty.
*/
#define list_first_entry(ptr, type, member) \
list_entry((ptr)->next, type, member)
/**
* list_for_each - iterate over a list
* @pos: the &struct list_head to use as a loop counter.
* @head: the head for your list.
*/
#define list_for_each(pos, head) \
for (pos = (head)->next; pos != (head); \
pos = pos->next)
/**
* list_for_each_prev - iterate over a list backwards
* @pos: the &struct list_head to use as a loop counter.
* @head: the head for your list.
*/
#define list_for_each_prev(pos, head) \
for (pos = (head)->prev; pos != (head); \
pos = pos->prev)
/**
* list_for_each_safe - iterate over a list safe against removal of list entry
* @pos: the &struct list_head to use as a loop counter.
* @n: another &struct list_head to use as temporary storage
* @head: the head for your list.
*/
#define list_for_each_safe(pos, n, head) \
for (pos = (head)->next, n = pos->next; pos != (head); \
pos = n, n = pos->next)
/**
* list_for_each_entry - iterate over list of given type
* @pos: the type * to use as a loop counter.
* @head: the head for your list.
* @member: the name of the list_struct within the struct.
*/
#define list_for_each_entry(pos, head, member, type) \
for (pos = list_entry((head)->next, type, member); \
&pos->member != (head); \
pos = list_entry(pos->member.next, type, member))
/**
* list_for_each_entry_safe - iterate over list of given type safe against removal of list entry
* @pos: the type * to use as a loop counter.
* @n: another type * to use as temporary storage
* @head: the head for your list.
* @member: the name of the list_struct within the struct.
*/
#define list_for_each_entry_safe(pos, n, head, member, type) \
for (pos = list_entry((head)->next, type, member), \
n = list_entry(pos->member.next, type, member); \
&pos->member != (head); \
pos = n, n = list_entry(n->member.next, type, member))
#endif

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/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#ifndef __PLATFORM_STDLIB_H__
#define __PLATFORM_STDLIB_H__
#define USE_CLIB_PATCH 0
#if defined (__GNUC__)
/* build rom should set USE_RTL_ROM_CLIB=0 */
#ifndef CONFIG_MBED_ENABLED
#include <rt_lib_rom.h>
#endif
#endif
#ifdef CONFIG_BUILD_ROM
#define USE_RTL_ROM_CLIB 0
#else
#define BUFFERED_PRINTF 0
#ifndef CONFIG_MBED_ENABLED
#define USE_RTL_ROM_CLIB 1
#else
#define USE_RTL_ROM_CLIB 0
#endif
#endif
#if defined(CONFIG_PLATFORM_8195A)
#if defined (__IARSTDLIB__)
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include "diag.h"
#define strsep(str, delim) _strsep(str, delim)
#elif defined (__CC_ARM)
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include "diag.h"
#define strsep(str, delim) _strsep(str, delim)
#else
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "diag.h"
#include "strproc.h"
#include "basic_types.h"
#include "hal_misc.h"
#if USE_RTL_ROM_CLIB
#include "rtl_lib.h"
#endif
#undef printf
#undef sprintf
#undef snprintf
#undef atoi
#undef memcmp
#undef memcpy
#undef memset
#undef strcmp
#undef strcpy
#undef strlen
#undef strncmp
#undef strncpy
#undef strsep
#undef strtok
#if USE_RTL_ROM_CLIB
#undef memchr
#undef memmove
#undef strcat
#undef strchr
#undef strncat
#undef strstr
#endif
#if USE_RTL_ROM_CLIB
#if BUFFERED_PRINTF
extern int buffered_printf(const char* fmt, ...);
#define printf buffered_printf
#else
#define printf rtl_printf
#endif
#define sprintf rtl_sprintf
#define snprintf rtl_snprintf
#define memchr rtl_memchr
#define memcmp rtl_memcmp
#define memcpy rtl_memcpy
#define memmove rtl_memmove
#define memset rtl_memset
#define strcat rtl_strcat
#define strchr rtl_strchr
#define strcmp(s1, s2) rtl_strcmp((const char *)s1, (const char *)s2)
#define strcpy rtl_strcpy
#define strlen(str) rtl_strlen((const char *)str)
#define strncat rtl_strncat
#define strncmp(s1, s2, n) rtl_strncmp((const char *)s1, (const char *)s2, n)
#define strncpy rtl_strncpy
#define strstr rtl_strstr
#define strsep rtl_strsep
#define strtok rtl_strtok
#else
#if USE_CLIB_PATCH
extern int DiagSscanfPatch(const char *buf, const char *fmt, ...);
extern char* DiagStrtokPatch(char *str, const char* delim);
extern char* DiagStrstrPatch(char *string, char *substring);
extern int DiagSnPrintfPatch(char *buf, size_t size, const char *fmt, ...);
extern u32 DiagPrintfPatch(const char *fmt, ...);
extern u32 DiagSPrintfPatch(u8 *buf, const char *fmt, ...);
#define printf DiagPrintfPatch
#define sprintf DiagSPrintfPatch
#define snprintf DiagSnPrintfPatch
#define strstr(a, b) DiagStrstrPatch((char *)(a), (char *)(b))
#define strtok DiagStrtokPatch
#else
#define printf DiagPrintf
#define sprintf(fmt, arg...) DiagSPrintf((u8*)fmt, ##arg)
#if defined (__GNUC__)
#define snprintf DiagSnPrintf // NULL function
#define strstr(str1, str2) prvStrStr(str1, str2) // NULL function
#endif
#define strtok(str, delim) _strsep(str, delim)
#endif
#define memcmp(dst, src, sz) _memcmp(dst, src, sz)
#define memcpy(dst, src, sz) _memcpy(dst, src, sz)
#define memset(dst, val, sz) _memset(dst, val, sz)
#define strchr(s, c) _strchr(s, c) // for B-cut ROM
#define strcmp(str1, str2) prvStrCmp((const unsigned char *) str1, (const unsigned char *) str2)
#define strcpy(dest, src) _strcpy(dest, src)
#define strlen(str) prvStrLen((const unsigned char *) str)
#define strncmp(str1, str2, cnt) _strncmp(str1, str2, cnt)
#define strncpy(dest, src, count) _strncpy(dest, src, count)
#define strsep(str, delim) _strsep(str, delim)
#endif
#define atoi(str) prvAtoi(str)
#define strpbrk(cs, ct) _strpbrk(cs, ct) // for B-cut ROM
#if USE_CLIB_PATCH
#undef sscanf
#define sscanf DiagSscanfPatch
#else
#if defined (__GNUC__)
#undef sscanf //_sscanf
//extern int DiagSscanfPatch(const char *buf, const char *fmt, ...);
//#define sscanf DiagSscanfPatch
#define sscanf sscanf // use libc sscanf
#endif
#endif
#endif // defined (__IARSTDLIB__)
//
// memory management
//
#ifndef CONFIG_MBED_ENABLED
extern void *pvPortMalloc( size_t xWantedSize );
extern void vPortFree( void *pv );
#define malloc pvPortMalloc
#define free vPortFree
#endif
#elif defined (CONFIG_PLATFORM_8711B)
#if defined (__IARSTDLIB__)
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include <stdarg.h> /* va_list */
#include "diag.h"
#define strsep(str, delim) _strsep(str, delim)
#else
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdarg.h> /* va_list */
#include "diag.h"
#include "strproc.h"
#include "memproc.h"
#include "basic_types.h"
#if USE_RTL_ROM_CLIB
#include "rtl_lib.h"
#include "rom_libc_string.h"
#endif
#undef printf
#undef sprintf
#undef snprintf
#undef memchr
#undef memcmp
#undef memcpy
#undef memset
#undef memmove
#undef strcmp
#undef strcpy
#undef strlen
#undef strncmp
#undef strncpy
#undef strsep
#undef strtok
#undef strcat
#undef strchr
#undef strncat
#undef strstr
#undef atol
#undef atoi
#undef strpbrk
#if USE_RTL_ROM_CLIB
#if BUFFERED_PRINTF
extern int buffered_printf(const char* fmt, ...);
#define printf buffered_printf
#else
#define printf rtl_printf
#endif
#define sprintf rtl_sprintf
#define snprintf rtl_snprintf
#define vsnprintf rtl_vsnprintf
#else
#define printf DiagPrintf
#define sprintf(fmt, arg...) DiagSPrintf((u8*)fmt, ##arg)
#define snprintf DiagSnPrintf // NULL function
#define vsnprintf(buf, size, fmt, ap) VSprintf(buf, fmt, ap)
#endif
#define memchr __rtl_memchr_v1_00
#define memcmp(dst, src, sz) _memcmp(dst, src, sz)
#define memcpy(dst, src, sz) _memcpy(dst, src, sz)
#define memmove __rtl_memmove_v1_00
#define memset(dst, val, sz) _memset(dst, val, sz)
#define strchr(s, c) _strchr(s, c) // for B-cut ROM
#define strcmp(str1, str2) prvStrCmp((const unsigned char *) str1, (const unsigned char *) str2)
#define strcpy(dest, src) _strcpy(dest, src)
#define strlen(str) prvStrLen((const unsigned char *) str)
#define strsep(str, delim) _strsep(str, delim)
#define strstr(str1, str2) prvStrStr(str1, str2) // NULL function
#define strtok(str, delim) prvStrtok(str, delim)//_strsep(str, delim)
#define strcat __rtl_strcat_v1_00
#define strncmp(str1, str2, cnt) _strncmp(str1, str2, cnt)
#define strncpy(dest, src, count) _strncpy(dest, src, count)
#define strncat __rtl_strncat_v1_00
#define atol(str) strtol(str,NULL,10)
#define atoi(str) prvAtoi(str)
#define strpbrk(cs, ct) _strpbrk(cs, ct) // for B-cut ROM
#if defined (__GNUC__)
#undef sscanf
#define sscanf _sscanf_patch
#define rand Rand
#endif
//extern int _sscanf_patch(const char *buf, const char *fmt, ...);
//#define sscanf _sscanf_patch
#endif // defined (__IARSTDLIB__)
//
// memory management
//
extern void *pvPortMalloc( size_t xWantedSize );
extern void vPortFree( void *pv );
#define malloc pvPortMalloc
#define free vPortFree
#elif defined(USE_STM322xG_EVAL) || defined(USE_STM324xG_EVAL) || defined(STM32F10X_XL)
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#endif
#endif //__PLATFORM_STDLIB_H__

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/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
* @file wifi_conf.h
* @author
* @version
* @brief This file provides user interface for Wi-Fi station and AP mode configuration
* base on the functionalities provided by Realtek Wi-Fi driver.
******************************************************************************
*/
#ifndef __WIFI_API_H
#define __WIFI_API_H
#include "osdep_service.h"
#include "wifi_constants.h"
#include "wifi_structures.h"
#include "wifi_util.h"
#include "wifi_ind.h"
#ifndef CONFIG_MBED_ENABLED
#include <platform/platform_stdlib.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************
* Macros
******************************************************/
#define RTW_ENABLE_API_INFO
#ifdef RTW_ENABLE_API_INFO
#define RTW_API_INFO(args) do {printf args;} while(0)
#else
#define RTW_API_INFO(args)
#endif
#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5]
#define CMP_MAC( a, b ) (((a[0])==(b[0]))&& \
((a[1])==(b[1]))&& \
((a[2])==(b[2]))&& \
((a[3])==(b[3]))&& \
((a[4])==(b[4]))&& \
((a[5])==(b[5])))
/******************************************************
* Constants
******************************************************/
#define SCAN_LONGEST_WAIT_TIME (4500)
#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
#define PSCAN_ENABLE 0x01 //enable for partial channel scan
#define PSCAN_FAST_SURVEY 0x02 //set to select scan time to FAST_SURVEY_TO, otherwise SURVEY_TO
#define PSCAN_SIMPLE_CONFIG 0x04 //set to select scan time to FAST_SURVEY_TO and resend probe request
/******************************************************
* Type Definitions
******************************************************/
/** Scan result callback function pointer type
*
* @param result_ptr : A pointer to the pointer that indicates where to put the next scan result
* @param user_data : User provided data
*/
typedef void (*rtw_scan_result_callback_t)( rtw_scan_result_t** result_ptr, void* user_data );
typedef rtw_result_t (*rtw_scan_result_handler_t)( rtw_scan_handler_result_t* malloced_scan_result );
/******************************************************
* Structures
******************************************************/
typedef struct {
char *buf;
int buf_len;
} scan_buf_arg;
/******************************************************
* Structures
******************************************************/
typedef struct internal_scan_handler{
rtw_scan_result_t** pap_details;
rtw_scan_result_t * ap_details;
int scan_cnt;
rtw_bool_t scan_complete;
unsigned char max_ap_size;
rtw_scan_result_handler_t gscan_result_handler;
#if SCAN_USE_SEMAPHORE
void *scan_semaphore;
#else
int scan_running;
#endif
void* user_data;
unsigned int scan_start_time;
} internal_scan_handler_t;
typedef struct {
rtw_network_info_t network_info;
void *join_sema;
} internal_join_result_t;
/******************************************************
* Function Declarations
******************************************************/
/**
* @brief Initialize Realtek WiFi API System.
* - Initialize the required parts of the software platform.
* i.e. worker, event registering, semaphore, etc.
* - Initialize the RTW API thread which handles the asynchronous event.
* @return RTW_SUCCESS if initialization is successful, RTW_ERROR otherwise
*/
int wifi_manager_init(void);
/**
* @brief Join a Wi-Fi network.
* Scan for, associate and authenticate with a Wi-Fi network.
* On successful return, the system is ready to send data packets.
*
* @param[in] ssid: A null terminated string containing the SSID name of the network to join.
* @param[in] security_type: Authentication type:
* - RTW_SECURITY_OPEN - Open Security
* - RTW_SECURITY_WEP_PSK - WEP Security with open authentication
* - RTW_SECURITY_WEP_SHARED - WEP Security with shared authentication
* - RTW_SECURITY_WPA_TKIP_PSK - WPA Security
* - RTW_SECURITY_WPA2_AES_PSK - WPA2 Security using AES cipher
* - RTW_SECURITY_WPA2_TKIP_PSK - WPA2 Security using TKIP cipher
* - RTW_SECURITY_WPA2_MIXED_PSK - WPA2 Security using AES and/or TKIP ciphers
* @param[in] password: A byte array containing either the cleartext security key for WPA/WPA2
* secured networks, or a pointer to an array of rtw_wep_key_t
* structures for WEP secured networks.
* @param[in] ssid_len: The length of the SSID in bytes.
* @param[in] password_len: The length of the security_key in bytes.
* @param[in] key_id: The index of the wep key (0, 1, 2, or 3). If not using it, leave it with value -1.
* @param[in] semaphore: A user provided semaphore that is flagged when the join is complete. If not using it, leave it with NULL value.
* @return RTW_SUCCESS: when the system is joined and ready to send data packets.
* @return RTW_ERROR: if an error occurred.
* @note Please make sure the Wi-Fi is enabled before invoking this function. (@ref wifi_on())
*/
int wifi_connect(
char *ssid,
rtw_security_t security_type,
char *password,
int ssid_len,
int password_len,
int key_id,
void *semaphore);
/**
* @brief Join a Wi-Fi network with specified BSSID.
* Scan for, associate and authenticate with a Wi-Fi network.
* On successful return, the system is ready to send data packets.
* @param[in] bssid: The specified BSSID to connect.
* @param[in] ssid: A null terminated string containing the SSID name of the network to join.
* @param[in] security_type: Authentication type:
* - RTW_SECURITY_OPEN - Open Security
* - RTW_SECURITY_WEP_PSK - WEP Security with open authentication
* - RTW_SECURITY_WEP_SHARED - WEP Security with shared authentication
* - RTW_SECURITY_WPA_TKIP_PSK - WPA Security
* - RTW_SECURITY_WPA2_AES_PSK - WPA2 Security using AES cipher
* - RTW_SECURITY_WPA2_TKIP_PSK - WPA2 Security using TKIP cipher
* - RTW_SECURITY_WPA2_MIXED_PSK - WPA2 Security using AES and/or TKIP ciphers
* @param[in] password: A byte array containing either the cleartext security key for WPA/WPA2
* secured networks, or a pointer to an array of rtw_wep_key_t
* structures for WEP secured networks.
* @param[in] ssid_len: The length of the SSID in bytes.
* @param[in] password_len: The length of the security_key in bytes.
* @param[in] key_id: The index of the wep key.
* @param[in] semaphore: A user provided semaphore that is flagged when the join is complete.
* @return RTW_SUCCESS: when the system is joined and ready to send data packets.
* @return RTW_ERROR: if an error occurred.
* @note Please make sure the Wi-Fi is enabled before invoking this function. (@ref wifi_on())
* @note The difference between @ref wifi_connect_bssid() and @ref wifi_connect() is that BSSID has higher priority as the basis of connection in @ref wifi_connect_bssid.
*/
int wifi_connect_bssid(
unsigned char bssid[ETH_ALEN],
char *ssid,
rtw_security_t security_type,
char *password,
int bssid_len,
int ssid_len,
int password_len,
int key_id,
void *semaphore);
/**
* @brief Disassociates from current Wi-Fi network.
* @param None
* @return RTW_SUCCESS: On successful disassociation from the AP.
* @return RTW_ERROR: If an error occurred.
*/
int wifi_disconnect(void);
/**
* @brief Check if Wi-Fi has connected to AP before dhcp.
* @param None
* @return RTW_SUCCESS: If conneced.
* @return RTW_ERROR: If not connect.
*/
int wifi_is_connected_to_ap(void);
/**
* @brief Check if the specified interface is up.
* @param[in] interface: The interface can be set as RTW_STA_INTERFACE or RTW_AP_INTERFACE. (@ref rtw_interface_t)
* @return If the function succeeds, the return value is 1. Otherwise, return 0.
*/
int wifi_is_up(rtw_interface_t interface);
/** Determines if a particular interface is ready to transceive ethernet packets
*
* @param Radio interface to check, options are
* RTW_STA_INTERFACE, RTW_AP_INTERFACE
* @return RTW_SUCCESS : if the interface is ready to
* transceive ethernet packets
* @return RTW_NOTFOUND : no AP with a matching SSID was
* found
* @return RTW_NOT_AUTHENTICATED: a matching AP was found but
* it won't let you
* authenticate. This can
* occur if this device is
* in the block list on the
* AP.
* @return RTW_NOT_KEYED: the device has authenticated and
* associated but has not completed
* the key exchange. This can occur
* if the passphrase is incorrect.
* @return RTW_ERROR : if the interface is not ready to
* transceive ethernet packets
*/
int wifi_is_ready_to_transceive(rtw_interface_t interface);
/**
* @brief This function sets the current Media Access Control (MAC) address of the 802.11 device.
* @param[in] mac: Wi-Fi MAC address.
* @return RTW_SUCCESS or RTW_ERROR
*/
int wifi_set_mac_address(char * mac);
/**
* @brief Retrieves the current Media Access Control (MAC) address
* (or Ethernet hardware address) of the 802.11 device.
* @param[in] mac: Point to the result of the mac address will be get.
* @return RTW_SUCCESS or RTW_ERROR
*/
int wifi_get_mac_address(char * mac);
/**
* @brief Enable Wi-Fi powersave mode.
* @param None
* @return RTW_SUCCESS or RTW_ERROR.
*/
int wifi_enable_powersave(void);
/**
* @brief Disable Wi-Fi powersave mode.
* @param None
* @return RTW_SUCCESS or RTW_ERROR.
*/
int wifi_disable_powersave(void);
/** Gets the tx power in index units
*
* @param dbm : The variable to receive the tx power in index.
*
* @return RTW_SUCCESS : if successful
* RTW_ERROR : if not successful
*/
int wifi_get_txpower(int *poweridx);
/**
* @brief Set the tx power in index units.
* @param[in] poweridx: The desired tx power in index.
* @return RTW_SUCCESS: if tx power is successfully set
* @return RTW_ERROR: if tx power is not successfully set
*/
int wifi_set_txpower(int poweridx);
/**
* @brief Get the associated clients with SoftAP.
* @param[out] client_list_buffer: The location where the client list will be stored.
* @param[in] buffer_length: The buffer length.
* @return RTW_SUCCESS: The result is successfully got.
* @return RTW_ERROR: The result is not successfully got.
*/
int wifi_get_associated_client_list(void * client_list_buffer, unsigned short buffer_length);
/**
* @brief Get the SoftAP information.
* @param[out] ap_info: The location where the AP info will be stored.
* @param[out] security: The security type.
* @return RTW_SUCCESS: The result is successfully got.
* @return RTW_ERROR: The result is not successfully got.
*/
int wifi_get_ap_info(rtw_bss_info_t * ap_info, rtw_security_t* security);
/**
* @brief Set the country code to driver to determine the channel set.
* @param[in] country_code: Specify the country code.
* @return RTW_SUCCESS: If result is successfully set.
* @return RTW_ERROR: If result is not successfully set.
*/
int wifi_set_country(rtw_country_code_t country_code);
/**
* @brief Retrieve the latest RSSI value.
* @param[out] pRSSI: Points to the integer to store the RSSI value gotten from driver.
* @return RTW_SUCCESS: If the RSSI is succesfully retrieved.
* @return RTW_ERROR: If the RSSI is not retrieved.
*/
int wifi_get_rssi(int *pRSSI);
/**
* @brief Set the listening channel for promiscuous mode.
* @param[in] channel: The desired channel.
* @return RTW_SUCCESS: If the channel is successfully set.
* @return RTW_ERROR: If the channel is not successfully set.
* @note Do NOT need to call this function for STA mode wifi driver, since it will determine the channel from received beacon.
*/
int wifi_set_channel(int channel);
/**
* @brief Get the current channel on STA interface.
* @param[out] channel: A pointer to the variable where the
* channel value will be written
* @return RTW_SUCCESS: If the channel is successfully read.
* @return RTW_ERROR: If the channel is not successfully read.
*/
int wifi_get_channel(int *channel);
/**
* @brief Register interest in a multicast address.\n
* Once a multicast address has been registered, all packets detected on the
* medium destined for that address are forwarded to the host.
* Otherwise they are ignored.
* @param[in] mac: Ethernet MAC address
* @return RTW_SUCCESS: If the address is registered successfully.
* @return RTW_ERROR: If the address is not registered.
*/
int wifi_register_multicast_address(rtw_mac_t *mac);
/**
* @brief Unregister interest in a multicast address.\n
* Once a multicast address has been unregistered, all packets detected on the
* medium destined for that address are ignored.
* @param[in] mac: Ethernet MAC address
* @return RTW_SUCCESS: If the address is unregistered successfully.
* @return RTW_ERROR: If the address is not unregistered.
*/
int wifi_unregister_multicast_address(rtw_mac_t *mac);
/**
* @brief Disable the adaptivity mode.
* @param None
* @return If the function succeeds, the return value is 0.
*/
void wifi_set_mib(void);
/**
* @brief Enable Wi-Fi RF.
* @param None
* @return If the function succeeds, the return value is 0.
* @note The difference between @ref wifi_rf_on() and @ref wifi_on() is that @ref wifi_rf_on() simply enable RF HAL, it does not enable the driver or allocate memory.
*/
int wifi_rf_on(void);
/**
* @brief Disable Wi-Fi RF.
* @param None
* @return If the function succeeds, the return value is 0.
* @note The difference between @ref wifi_rf_off() and @ref wifi_off() is that @ref wifi_rf_off() simply disable RF HAL, the driver and used heap memory will NOT be released.
*/
int wifi_rf_off(void);
/**
* @brief Enable Wi-Fi.
* - Bring the Wireless interface "Up"
* - Initialize the driver thread which arbitrates access
* to the SDIO/SPI bus
*
* @param[in] mode: Decide to enable WiFi in which mode. The optional modes are enumerated in @ref rtw_mode_t.
* @return RTW_SUCCESS: if the WiFi chip was initialized successfully.
* @return RTW_ERROR: if the WiFi chip was not initialized successfully.
*/
int wifi_on(rtw_mode_t mode);
/**
* @brief Disable Wi-Fi.
*
* @param None
* @return RTW_SUCCESS: if deinitialization is successful.
* @return RTW_ERROR: otherwise.
*/
int wifi_off(void);
/**
* Turn off the Wi-Fi device
*
* - Bring the Wireless interface "Down"
* - De-Initialises the driver thread which arbitrates access
* to the SDIO/SPI bus
*
* @return RTW_SUCCESS if deinitialization is successful,
* RTW_ERROR otherwise
*/
int wifi_off_fastly(void);
/**
* @brief Set IPS/LPS mode.
* @param[in] ips_mode: The desired IPS mode. It becomes effective when wlan enter ips.\n
* @ref ips_mode is inactive power save mode. Wi-Fi automatically turns RF off if it is not associated to AP. Set 1 to enable inactive power save mode.
* @param[in] lps_mode: The desired LPS mode. It becomes effective when wlan enter lps.\n
* @ref lps_mode is leisure power save mode. Wi-Fi automatically turns RF off during the association to AP is traffic is not busy while it also automatically turns RF on to listen to beacon. Set 1 to enable leisure power save mode.
* @return RTW_SUCCESS if setting LPS mode successful.
* @return RTW_ERROR otherwise.
*/
int wifi_set_power_mode(unsigned char ips_mode, unsigned char lps_mode);
/**
* Set TDMA parameters
*
* @param[in] slot_period : We separate TBTT into 2 or 3 slots.
* If we separate TBTT into 2 slots, then slot_period should be larger or equal to 50ms.
* It means 2 slot period is
* slot_period, 100-slot_period
* If we separate TBTT into 3 slots, then slot_period should be less or equal to 33ms.
* It means 3 slot period is
* 100 - 2 * slot_period, slot_period, slot_period
* @param[in] rfon_period_len_1: rf on period of slot 1
* @param[in] rfon_period_len_2: rf on period of slot 2
* @param[in] rfon_period_len_3: rf on period of slot 3
*
* @return RTW_SUCCESS if setting TDMA parameters successful
* RTW_ERROR otherwise
*/
int wifi_set_tdma_param(unsigned char slot_period, unsigned char rfon_period_len_1, unsigned char rfon_period_len_2, unsigned char rfon_period_len_3);
/**
* @brief Set LPS DTIM.
* @param[in] dtim: In LPS, the package can be buffered at AP side.
* STA leave LPS until dtim count of packages buffered at AP side.
* @return RTW_SUCCESS if setting LPS dtim successful.
* @return RTW_ERROR otherwise
*/
int wifi_set_lps_dtim(unsigned char dtim);
/**
* @brief Get LPS DTIM.
* @param[out] dtim: In LPS, the package can be buffered at AP side.
* STA leave LPS until dtim count of packages buffered at AP side.
* @return RTW_SUCCESS if getting LPS dtim successful.
* @return RTW_ERROR otherwise.
*/
int wifi_get_lps_dtim(unsigned char *dtim);
/**
* @brief Trigger Wi-Fi driver to start an infrastructure Wi-Fi network.
* @warning If a STA interface is active when this function is called, the softAP will
* start on the same channel as the STA. It will NOT use the channel provided!
* @param[in] ssid: A null terminated string containing the SSID name of the network.
* @param[in] security_type:
* - RTW_SECURITY_OPEN - Open Security
* - RTW_SECURITY_WPA_TKIP_PSK - WPA Security
* - RTW_SECURITY_WPA2_AES_PSK - WPA2 Security using AES cipher
* - RTW_SECURITY_WPA2_MIXED_PSK - WPA2 Security using AES and/or TKIP ciphers
* - WEP security is NOT IMPLEMENTED. It is NOT SECURE!
* @param[in] password: A byte array containing the cleartext security key for the network.
* @param[in] ssid_len: The length of the SSID in bytes.
* @param[in] password_len: The length of the security_key in bytes.
* @param[in] channel: 802.11 channel number.
* @return RTW_SUCCESS: If successfully creates an AP.
* @return RTW_ERROR: If an error occurred.
* @note Please make sure the Wi-Fi is enabled before invoking this function. (@ref wifi_on())
*/
int wifi_start_ap(
char *ssid,
rtw_security_t security_type,
char *password,
int ssid_len,
int password_len,
int channel);
/**
* @brief Start an infrastructure Wi-Fi network with hidden SSID.
* @warning If a STA interface is active when this function is called, the softAP will
* start on the same channel as the STA. It will NOT use the channel provided!
*
* @param[in] ssid: A null terminated string containing
* the SSID name of the network to join.
* @param[in] security_type: Authentication type: \n
* - RTW_SECURITY_OPEN - Open Security
* - RTW_SECURITY_WPA_TKIP_PSK - WPA Security
* - RTW_SECURITY_WPA2_AES_PSK - WPA2 Security using AES cipher
* - RTW_SECURITY_WPA2_MIXED_PSK - WPA2 Security using AES and/or TKIP ciphers
* - WEP security is NOT IMPLEMENTED. It is NOT SECURE!
* @param[in] password: A byte array containing the cleartext
* security key for the network.
* @param[in] ssid_len: The length of the SSID in bytes.
* @param[in] password_len: The length of the security_key in bytes.
* @param[in] channel: 802.11 channel number
*
* @return RTW_SUCCESS: If successfully creates an AP.
* @return RTW_ERROR: If an error occurred.
*/
int wifi_start_ap_with_hidden_ssid(
char *ssid,
rtw_security_t security_type,
char *password,
int ssid_len,
int password_len,
int channel);
/**
* @brief Initiate a scan to search for 802.11 networks.
*
* @param[in] scan_type: Specifies whether the scan should
* be Active, Passive or scan
* Prohibited channels
* @param[in] bss_type: Specifies whether the scan should
* search for Infrastructure
* networks (those using an Access
* Point), Ad-hoc networks, or both
* types.
* @param[in] result_ptr: Scan specific ssid. The first 4
* bytes is ssid lenth, and ssid name
* append after it.
* If no specific ssid need to scan,
* PLEASE CLEAN result_ptr before pass
* it into parameter.
* @param[out] result_ptr: a pointer to a pointer to a result
* storage structure.
* @return RTW_SUCCESS or RTW_ERROR
* @note The scan progressively accumulates results over time, and
* may take between 1 and 3 seconds to complete. The results of
* the scan will be individually provided to the callback
* function. Note: The callback function will be executed in
* the context of the RTW thread.
* @note When scanning specific channels, devices with a
* strong signal strength on nearby channels may be
* detected
*/
int wifi_scan(rtw_scan_type_t scan_type,
rtw_bss_type_t bss_type,
void* result_ptr);
/**
* @brief Initiate a scan to search for 802.11 networks, a higher level API based on wifi_scan
* to simplify the scan operation.
* @param[in] results_handler: The callback function which will receive and process the result data.
* @param[in] user_data: User specified data that will be passed directly to the callback function.
* @return RTW_SUCCESS or RTW_ERROR
* @note Callback must not use blocking functions, since it is called from the context of the RTW thread.
* The callback, user_data variables will be referenced after the function returns.
* Those variables must remain valid until the scan is completed.
* The usage of this api can reference ATWS in atcmd_wifi.c.
*/
int wifi_scan_networks(rtw_scan_result_handler_t results_handler, void* user_data);
/**
* @brief Initiate a scan to search for 802.11 networks with specified SSID.
* @param[in] results_handler: The callback function which will receive and process the result data.
* @param[in] user_data: User specified data that will be passed directly to the callback function.
* @param[in] scan_buflen: The length of the result storage structure.
* @param[in] ssid: The SSID of target network.
* @param[in] ssid_len: The length of the target network SSID.
* @return RTW_SUCCESS or RTW_ERROR
* @note Callback must not use blocking functions, since it is called from the context of the RTW thread.
* The callback, user_data variables will be referenced after the function returns.
* Those variables must remain valid until the scan is completed.
*/
int wifi_scan_networks_with_ssid(int (results_handler)(char*, int, char *, void *), void* user_data, int scan_buflen, char* ssid, int ssid_len);
/**
* @brief Set the channel used to be partial scanned.
* @param[in] channel_list: An array stores the channel list.
* @param[in] pscan_config: the pscan_config of the channel set.
* @param[in] length: The length of the channel_list.
* @return RTW_SUCCESS or RTW_ERROR.
* @note This function should be used with wifi_scan function. First, use @ref wifi_set_pscan_chan to
* indicate which channel will be scanned, and then use @ref wifi_scan to get scanned results.
*/
int wifi_set_pscan_chan(__u8 * channel_list,__u8 * pscan_config, __u8 length);
/**
* @brief Get current Wi-Fi setting from driver.
* @param[in] ifname: the wlan interface name, can be WLAN0_NAME or WLAN1_NAME.
* @param[out] pSetting: Points to the rtw_wifi_setting_t structure to store the WIFI setting gotten from driver.
* @return RTW_SUCCESS or RTW_ERROR.
*/
int wifi_get_setting(const char *ifname,rtw_wifi_setting_t *pSetting);
/**
* @brief Show the network information stored in a rtw_wifi_setting_t structure.
* @param[in] ifname: the wlan interface name, can be WLAN0_NAME or WLAN1_NAME.
* @param[in] pSetting: Points to the rtw_wifi_setting_t structure which information is gotten by @ref wifi_get_setting().
* @return RTW_SUCCESS or RTW_ERROR.
*/
int wifi_show_setting(const char *ifname,rtw_wifi_setting_t *pSetting);
/**
* @brief
Set the network mode according to the data rate its supported.
* Driver works in BGN mode in default after driver initialization. This function is used to
* change wireless network mode for station mode before connecting to AP.
* @param[in] mode: Network mode to set. The value can be RTW_NETWORK_B/RTW_NETWORK_BG/RTW_NETWORK_BGN.
* @return RTW_SUCCESS or RTW_ERROR.
*/
int wifi_set_network_mode(rtw_network_mode_t mode);
/**
* @brief Set the chip to start or stop the promiscuous mode.
* @param[in] enabled: enabled can be set 0, 1 and 2. if enabled is zero, disable the promisc, else enable the promisc.
* - 0 means disable the promisc.
* - 1 means enable the promisc.
* - 2 means enable the promisc special for length is used.
* @param[in] callback: the callback function which will
* receive and process the netowork data.
* @param[in] len_used: specify if the the promisc length is used.
* If len_used set to 1, packet length will be saved and transferred to callback function.
*
* @return RTW_SUCCESS or RTW_ERROR
* @note This function can be used to implement vendor specified simple configure.
*/
int wifi_set_promisc(rtw_rcr_level_t enabled, void (*callback)(unsigned char*, unsigned int, void*), unsigned char len_used);
/**
* @brief Let Wi-Fi enter promiscuous mode.
* @param[in] None
* @return None
*/
void wifi_enter_promisc_mode(void);
/** Set the wps phase
*
* @param is_trigger_wps[in] : to trigger wps function or not
*
* @return RTW_SUCCESS or RTW_ERROR
*/
int wifi_set_wps_phase(unsigned char is_trigger_wps);
/**
* @brief Trigger Wi-Fi driver to restart an infrastructure Wi-Fi network.
* @warning If a STA interface is active when this function is called, the softAP will
* start on the same channel as the STA. It will NOT use the channel provided!
* @param[in] ssid: A null terminated string containing the SSID name of the network.
* @param[in] security_type:
* - RTW_SECURITY_OPEN - Open Security
* - RTW_SECURITY_WPA_TKIP_PSK - WPA Security
* - RTW_SECURITY_WPA2_AES_PSK - WPA2 Security using AES cipher
* - RTW_SECURITY_WPA2_MIXED_PSK - WPA2 Security using AES and/or TKIP ciphers
* - WEP security is NOT IMPLEMENTED. It is NOT SECURE!
* @param[in] password: A byte array containing the cleartext security key for the network.
* @param[in] ssid_len: The length of the SSID in bytes.
* @param[in] password_len: The length of the security_key in bytes.
* @param[in] channel: 802.11 channel number.
* @return RTW_SUCCESS: If successfully creates an AP.
* @return RTW_ERROR: If an error occurred.
* @note Please make sure the Wi-Fi is enabled before invoking this function. (@ref wifi_on())
*/
int wifi_restart_ap(
unsigned char *ssid,
rtw_security_t security_type,
unsigned char *password,
int ssid_len,
int password_len,
int channel);
/**
* @brief Set reconnection mode with configuration.
* @param[in] mode: Set 1/0 to enalbe/disable the reconnection mode.
* @param[in] retry_times: The number of retry limit.
* @param[in] timeout: The timeout value (in seconds).
* @return 0 if success, otherwise return -1.
* @note Defining CONFIG_AUTO_RECONNECT in "autoconf.h" needs to be done before compiling,
* or this API won't be effective.
* @note The difference between @ref wifi_config_autoreconnect() and @ref wifi_set_autoreconnect() is that
* user can specify the retry times and timeout value in @ref wifi_config_autoreconnect().
* But in @ref wifi_set_autoreconnect() these values are set with 3 retry limit and 5 seconds timeout as default.
*/
int wifi_config_autoreconnect(__u8 mode, __u8 retry_times, __u16 timeout);
/**
* @brief Set reconnection mode with 3 retry limit and 5 seconds timeout as default.
* @param[in] mode: Set 1/0 to enalbe/disable the reconnection mode.
* @return 0 if success, otherwise return -1.
* @note Defining CONFIG_AUTO_RECONNECT in "autoconf.h" needs to be done before compiling,
* or this API won't be effective.
* @note The difference between @ref wifi_config_autoreconnect() and @ref wifi_set_autoreconnect() is that
* user can specify the retry times and timeout value in @ref wifi_config_autoreconnect().
* But in @ref wifi_set_autoreconnect() these values are set with 3 retry limit and 5 seconds timeout as default.
*/
int wifi_set_autoreconnect(__u8 mode);
/**
* @brief Get the result of setting reconnection mode.
* @param[out] mode: Point to the result of setting reconnection mode.
* @return 0 if success, otherwise return -1.
* @note Defining CONFIG_AUTO_RECONNECT in "autoconf.h" needs to be done before compiling,
* or this API won't be effective.
*/
int wifi_get_autoreconnect(__u8 *mode);
/**
* @brief Present the device disconnect reason while connecting.
* @param None
* @return @ref rtw_connect_error_flag_t
* - 0: RTW_NO_ERROR
* - 1: RTW_NONE_NETWORK
* - 2: RTW_CONNECT_FAIL
* - 3: RTW_WRONG_PASSWORD
* - 4: RTW_DHCP_FAIL
* - 5: RTW_UNKNOWN (initial status)
*/
int wifi_get_last_error(void);
#ifdef CONFIG_CUSTOM_IE
#ifndef BIT
#define BIT(x) ((__u32)1 << (x))
#endif
#ifndef _CUSTOM_IE_TYPE_
#define _CUSTOM_IE_TYPE_
/**
* @brief The enumeration is transmission type for wifi custom ie.
*/
enum CUSTOM_IE_TYPE{
PROBE_REQ = BIT(0),
PROBE_RSP = BIT(1),
BEACON = BIT(2),
};
typedef uint32_t rtw_custom_ie_type_t;
#endif /* _CUSTOM_IE_TYPE_ */
/* ie format
* +-----------+--------+-----------------------+
* |element ID | length | content in length byte|
* +-----------+--------+-----------------------+
*
* type: refer to CUSTOM_IE_TYPE
*/
#ifndef _CUS_IE_
#define _CUS_IE_
/**
* @brief The structure is used to set WIFI custom ie list, and type match CUSTOM_IE_TYPE.\n
* The ie will be transmitted according to the type.
*/
typedef struct _cus_ie{
__u8 *ie;
__u8 type;
}rtw_custom_ie_t, *p_rtw_custom_ie_t;
#endif /* _CUS_IE_ */
/**
* @brief Setup custom ie list.
* @warning This API can't be executed twice before deleting the previous custom ie list.
* @param[in] cus_ie: Pointer to WIFI CUSTOM IE list.
* @param[in] ie_num: The number of WIFI CUSTOM IE list.
* @return 0 if success, otherwise return -1.
* @note Defininig CONFIG_CUSTOM_IE in "autoconf.h" needs to be done before compiling,
* or this API won't be effective.
*/
int wifi_add_custom_ie(void *cus_ie, int ie_num);
/**
* @brief Update the item in WIFI CUSTOM IE list.
* @param[in] cus_ie: Pointer to WIFI CUSTOM IE address.
* @param[in] ie_index: Index of WIFI CUSTOM IE list.
* @return 0 if success, otherwise return -1.
* @note Defininig CONFIG_CUSTOM_IE in "autoconf.h" needs to be done before compiling,
* or this API won't be effective.
*/
int wifi_update_custom_ie(void *cus_ie, int ie_index);
/**
* @brief Delete WIFI CUSTOM IE list.
* @param None
* @return 0 if success, otherwise return -1.
* @note Defininig CONFIG_CUSTOM_IE in "autoconf.h" needs to be done before compiling,
* or this API won't be effective.
*/
int wifi_del_custom_ie(void);
#endif
#ifdef CONFIG_PROMISC
/**
* @brief Initialize packet filter related data.
* @param None
* @return None
*/
void wifi_init_packet_filter(void);
/**
* @brief Add packet filter.
* @param[in] filter_id: The filter id.
* @param[in] patt: Point to the filter pattern.
* @param[in] rule: Point to the filter rule.
* @return 0 if success, otherwise return -1.
* @note For now, the maximum number of filters is 5.
*/
int wifi_add_packet_filter(unsigned char filter_id, rtw_packet_filter_pattern_t *patt, rtw_packet_filter_rule_t rule);
/**
* @brief Enable the packet filter.
* @param[in] filter_id: The filter id.
* @return 0 if success, otherwise return -1.
* @note The filter can be used only if it has been enabled.
*/
int wifi_enable_packet_filter(unsigned char filter_id);
/**
* @brief Disable the packet filter.
* @param[in] filter_id: The filter id.
* @return 0 if success, otherwise return -1.
*/
int wifi_disable_packet_filter(unsigned char filter_id);
/**
* @brief Remove the packet filter.
* @param[in] filter_id: The filter id.
* @return 0 if success, otherwise return -1.
*/
int wifi_remove_packet_filter(unsigned char filter_id);
#endif
void wifi_set_indicate_mgnt(int enable);
#ifdef __cplusplus
}
#endif
#endif // __WIFI_API_H
//----------------------------------------------------------------------------//

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@ -0,0 +1,274 @@
/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#include "wifi/wifi_ind.h"
#include "wifi/wifi_conf.h"
#include "osdep_service.h"
#include "platform_stdlib.h"
/******************************************************
* Constants
******************************************************/
#define WIFI_INDICATE_MSG 0
#define WIFI_MANAGER_STACKSIZE 1300
#define WIFI_MANAGER_PRIORITY (0) //Actual priority is 4 since calling rtw_create_task
#define WIFI_MANAGER_Q_SZ 8
#define WIFI_EVENT_MAX_ROW 3
/******************************************************
* Globals
******************************************************/
static event_list_elem_t event_callback_list[WIFI_EVENT_MAX][WIFI_EVENT_MAX_ROW];
#if CONFIG_WIFI_IND_USE_THREAD
static rtw_worker_thread_t wifi_worker_thread;
#endif
//----------------------------------------------------------------------------//
#if CONFIG_WIFI_IND_USE_THREAD
static rtw_result_t rtw_send_event_to_worker(int event_cmd, char *buf, int buf_len, int flags)
{
rtw_event_message_t message;
int i;
rtw_result_t ret = RTW_SUCCESS;
char *local_buf = NULL;
if(event_cmd >= WIFI_EVENT_MAX)
return RTW_BADARG;
for(i = 0; i < WIFI_EVENT_MAX_ROW; i++){
if(event_callback_list[event_cmd][i].handler == NULL)
continue;
message.function = (event_handler_t)event_callback_list[event_cmd][i].handler;
message.buf_len = buf_len;
if(buf_len){
local_buf = (char*)pvPortMalloc(buf_len);
if(local_buf == NULL)
return RTW_NOMEM;
memcpy(local_buf, buf, buf_len);
//printf("\n!!!!!Allocate %p(%d) for evcmd %d\n", local_buf, buf_len, event_cmd);
}
message.buf = local_buf;
message.flags = flags;
message.user_data = event_callback_list[event_cmd][i].handler_user_data;
ret = rtw_push_to_xqueue(&wifi_worker_thread.event_queue, &message, 0);
if(ret != RTW_SUCCESS){
if(local_buf){
printf("\r\nrtw_send_event_to_worker: enqueue cmd %d failed and free %p(%d)\n", event_cmd, local_buf, buf_len);
vPortFree(local_buf);
}
break;
}
}
return ret;
}
#else
static rtw_result_t rtw_indicate_event_handle(int event_cmd, char *buf, int buf_len, int flags)
{
rtw_event_handler_t handle = NULL;
int i;
if(event_cmd >= WIFI_EVENT_MAX)
return RTW_BADARG;
for(i = 0; i < WIFI_EVENT_MAX_ROW; i++){
handle = event_callback_list[event_cmd][i].handler;
if(handle == NULL)
continue;
handle(buf, buf_len, flags, event_callback_list[event_cmd][i].handler_user_data);
}
return RTW_SUCCESS;
}
#endif
void wifi_indication( rtw_event_indicate_t event, char *buf, int buf_len, int flags)
{
//
// If upper layer application triggers additional operations on receiving of wext_wlan_indicate,
// please strictly check current stack size usage (by using uxTaskGetStackHighWaterMark() )
// , and tries not to share the same stack with wlan driver if remaining stack space is
// not available for the following operations.
// ex: using semaphore to notice another thread.
switch(event)
{
case WIFI_EVENT_DISCONNECT:
#if(WIFI_INDICATE_MSG==1)
printf("\n\r %s():Disconnection indication received", __FUNCTION__);
#endif
break;
case WIFI_EVENT_CONNECT:
// For WPA/WPA2 mode, indication of connection does not mean data can be
// correctly transmitted or received. Data can be correctly transmitted or
// received only when 4-way handshake is done.
// Please check WIFI_EVENT_FOURWAY_HANDSHAKE_DONE event
#if(WIFI_INDICATE_MSG==1)
// Sample: return mac address
if(buf != NULL && buf_len == 6)
{
printf("\n\r%s():Connect indication received: %02x:%02x:%02x:%02x:%02x:%02x", __FUNCTION__,
buf[0],buf[1],buf[2],buf[3],buf[4],buf[5]);
}
#endif
break;
case WIFI_EVENT_FOURWAY_HANDSHAKE_DONE:
#if(WIFI_INDICATE_MSG==1)
if(buf != NULL)
{
if(buf_len == strlen(IW_EXT_STR_FOURWAY_DONE))
printf("\n\r%s():%s", __FUNCTION__, buf);
}
#endif
break;
case WIFI_EVENT_SCAN_RESULT_REPORT:
#if(WIFI_INDICATE_MSG==1)
printf("\n\r%s(): WIFI_EVENT_SCAN_RESULT_REPORT\n", __func__);
#endif
break;
case WIFI_EVENT_SCAN_DONE:
#if(WIFI_INDICATE_MSG==1)
printf("\n\r%s(): WIFI_EVENT_SCAN_DONE\n", __func__);
#endif
break;
case WIFI_EVENT_RECONNECTION_FAIL:
#if(WIFI_INDICATE_MSG==1)
if(buf != NULL){
if(buf_len == strlen(IW_EXT_STR_RECONNECTION_FAIL))
printf("\n\r%s", buf);
}
#endif
break;
case WIFI_EVENT_NO_NETWORK:
#if(WIFI_INDICATE_MSG==1)
printf("\n\r%s(): WIFI_EVENT_NO_NETWORK\n", __func__);
#endif
break;
case WIFI_EVENT_RX_MGNT:
#if(WIFI_INDICATE_MSG==1)
printf("\n\r%s(): WIFI_EVENT_RX_MGNT\n", __func__);
#endif
break;
#if CONFIG_ENABLE_P2P
case WIFI_EVENT_SEND_ACTION_DONE:
#if(WIFI_INDICATE_MSG==1)
printf("\n\r%s(): WIFI_EVENT_SEND_ACTION_DONE\n", __func__);
#endif
break;
#endif //CONFIG_ENABLE_P2P
case WIFI_EVENT_STA_ASSOC:
#if(WIFI_INDICATE_MSG==1)
printf("\n\r%s(): WIFI_EVENT_STA_ASSOC\n", __func__);
#endif
break;
case WIFI_EVENT_STA_DISASSOC:
#if(WIFI_INDICATE_MSG==1)
printf("\n\r%s(): WIFI_EVENT_STA_DISASSOC\n", __func__);
#endif
break;
#ifdef CONFIG_WPS
case WIFI_EVENT_STA_WPS_START:
#if(WIFI_INDICATE_MSG==1)
printf("\n\r%s(): WIFI_EVENT_STA_WPS_START\n", __func__);
#endif
break;
case WIFI_EVENT_WPS_FINISH:
#if(WIFI_INDICATE_MSG==1)
printf("\n\r%s(): WIFI_EVENT_WPS_FINISH\n", __func__);
#endif
break;
case WIFI_EVENT_EAPOL_RECVD:
#if(WIFI_INDICATE_MSG==1)
printf("\n\r%s(): WIFI_EVENT_EAPOL_RECVD\n", __func__);
#endif
break;
#endif
case WIFI_EVENT_BEACON_AFTER_DHCP:
#if(WIFI_INDICATE_MSG==1)
printf("\n\r%s(): WIFI_EVENT_BEACON_AFTER_DHCP\n", __func__);
#endif
break;
}
#if CONFIG_INIC_EN
inic_indicate_event(event, buf, buf_len, flags);
#endif//CONFIG_INIC_EN
#if CONFIG_WIFI_IND_USE_THREAD
rtw_send_event_to_worker(event, buf, buf_len, flags);
#else
rtw_indicate_event_handle(event, buf, buf_len, flags);
#endif
}
void wifi_reg_event_handler(unsigned int event_cmds, rtw_event_handler_t handler_func, void *handler_user_data)
{
int i = 0, j = 0;
if(event_cmds < WIFI_EVENT_MAX){
for(i=0; i < WIFI_EVENT_MAX_ROW; i++){
if(event_callback_list[event_cmds][i].handler == NULL){
for(j=0; j<WIFI_EVENT_MAX_ROW; j++){
if(event_callback_list[event_cmds][j].handler == handler_func){
return;
}
}
event_callback_list[event_cmds][i].handler = handler_func;
event_callback_list[event_cmds][i].handler_user_data = handler_user_data;
return;
}
}
}
}
void wifi_unreg_event_handler(unsigned int event_cmds, rtw_event_handler_t handler_func)
{
int i;
if(event_cmds < WIFI_EVENT_MAX){
for(i = 0; i < WIFI_EVENT_MAX_ROW; i++){
if(event_callback_list[event_cmds][i].handler == handler_func){
event_callback_list[event_cmds][i].handler = NULL;
event_callback_list[event_cmds][i].handler_user_data = NULL;
return;
}
}
}
}
void init_event_callback_list(){
memset(event_callback_list, 0, sizeof(event_callback_list));
}
int wifi_manager_init()
{
#if CONFIG_WIFI_IND_USE_THREAD
rtw_create_worker_thread(&wifi_worker_thread,
WIFI_MANAGER_PRIORITY,
WIFI_MANAGER_STACKSIZE,
WIFI_MANAGER_Q_SZ);
#endif
return 0;
}
void rtw_wifi_manager_deinit()
{
#if CONFIG_WIFI_IND_USE_THREAD
rtw_delete_worker_thread(&wifi_worker_thread);
#endif
}

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/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
* @file wifi_ind.h
* @author
* @version
* @brief This file provides the functions related to event handler mechanism.
******************************************************************************
*/
#ifndef _WIFI_INDICATE_H
#define _WIFI_INDICATE_H
#include "wifi_conf.h"
typedef void (*rtw_event_handler_t)(char *buf, int buf_len, int flags, void* handler_user_data );
typedef struct
{
// rtw_event_indicate_t event_cmd;
rtw_event_handler_t handler;
void* handler_user_data;
} event_list_elem_t;
/**
* @brief Initialize the event callback list.
* @warning Please make sure this function has been invoked before
* using the event handler related mechanism.
* @param None
* @return None
*/
void init_event_callback_list(void);
/**
* @brief Wlan driver indicate event to upper layer through wifi_indication.
* @param[in] event: An event reported from driver to upper layer application. Please refer to rtw_event_indicate_t enum.
* @param[in] buf: If it is not NUL, buf is a pointer to the buffer for message string.
* @param[in] buf_len: The length of the buffer.
* @param[in] flags: Indicate some extra information, sometimes it is 0.
* @retval None
* @note If upper layer application triggers additional operations on receiving of wext_wlan_indicate,
* please strictly check current stack size usage (by using uxTaskGetStackHighWaterMark() ),
* and tries not to share the same stack with wlan driver if remaining stack space is not available
* for the following operations.
* ex: using semaphore to notice another thread instead of handing event directly in wifi_indication().
*/
extern void wifi_indication( rtw_event_indicate_t event, char *buf, int buf_len, int flags);
/**
* @brief Register the event listener.
* @param[in] event_cmds : The event command number indicated.
* @param[in] handler_func : the callback function which will
* receive and process the event.
* @param[in] handler_user_data : user specific data that will be
* passed directly to the callback function.
* @return RTW_SUCCESS : if successfully registers the event.
* @return RTW_ERROR : if an error occurred.
* @note Set the same event_cmds with empty handler_func will
* unregister the event_cmds.
*/
extern void wifi_reg_event_handler(unsigned int event_cmds, rtw_event_handler_t handler_func, void *handler_user_data);
/**
* @brief Un-register the event listener.
* @param[in] event_cmds : The event command number indicated.
* @param[in] handler_func : the callback function which will
* receive and process the event.
*
* @return RTW_SUCCESS : if successfully un-registers the event .
* @return RTW_ERROR : if an error occurred.
*/
extern void wifi_unreg_event_handler(unsigned int event_cmds, rtw_event_handler_t handler_func);
#endif //_WIFI_INDICATE_H

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/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#include "tcpip.h"
#include "wifi/wifi_conf.h"
#ifndef CONFIG_WLAN
#define CONFIG_WLAN 1
#endif
#if CONFIG_WLAN
#include <platform/platform_stdlib.h>
// Add extra interfaces to make release sdk able to determine promisc API linking
void promisc_deinit(void *padapter)
{
#ifdef CONFIG_PROMISC
_promisc_deinit(padapter);
#endif
}
int promisc_recv_func(void *padapter, void *rframe)
{
// Never reach here if not define CONFIG_PROMISC
#ifdef CONFIG_PROMISC
return _promisc_recv_func(padapter, rframe);
#else
return 0;
#endif
}
int promisc_set(rtw_rcr_level_t enabled, void (*callback)(unsigned char*, unsigned int, void*), unsigned char len_used)
{
#ifdef CONFIG_PROMISC
return _promisc_set(enabled, callback, len_used);
#else
return -1;
#endif
}
unsigned char is_promisc_enabled(void)
{
#ifdef CONFIG_PROMISC
return _is_promisc_enabled();
#else
return 0;
#endif
}
int promisc_get_fixed_channel(void *fixed_bssid, u8 *ssid, int *ssid_length)
{
#ifdef CONFIG_PROMISC
return _promisc_get_fixed_channel(fixed_bssid, ssid, ssid_length);
#else
return 0;
#endif
}
// End of Add extra interfaces
struct eth_frame {
struct eth_frame *prev;
struct eth_frame *next;
unsigned char da[6];
unsigned char sa[6];
unsigned int len;
unsigned char type;
signed char rssi;
};
#if CONFIG_INIC_CMD_RSP
#if defined(__IAR_SYSTEMS_ICC__)
#pragma pack(1)
#endif
struct inic_eth_frame {
unsigned char da[6];
unsigned char sa[6];
unsigned int len;
unsigned char type;
};
#if defined(__IAR_SYSTEMS_ICC__)
#pragma pack()
#endif
static struct inic_eth_frame *inic_frame, *inic_frame_tail = NULL;
static int inic_frame_cnt = 0;
#define MAX_INIC_FRAME_NUM 50 //maximum packets for each channel
extern void inic_c2h_msg(const char *atcmd, char status, char *msg, u16 msg_len);
#endif
struct eth_buffer {
struct eth_frame *head;
struct eth_frame *tail;
};
static struct eth_buffer eth_buffer;
#ifdef CONFIG_PROMISC
#define MAX_PACKET_FILTER_INFO 5
#define FILTER_ID_INIT_VALUE 10
rtw_packet_filter_info_t paff_array[MAX_PACKET_FILTER_INFO]={0, 0, 0, 0, 0};
static u8 packet_filter_enable_num = 0;
void promisc_init_packet_filter()
{
int i = 0;
for(i=0; i<MAX_PACKET_FILTER_INFO; i++){
paff_array[i].filter_id = FILTER_ID_INIT_VALUE;
paff_array[i].enable = 0;
paff_array[i].patt.mask_size = 0;
paff_array[i].rule = RTW_POSITIVE_MATCHING;
paff_array[i].patt.mask = NULL;
paff_array[i].patt.pattern = NULL;
}
packet_filter_enable_num = 0;
}
int promisc_add_packet_filter(u8 filter_id, rtw_packet_filter_pattern_t *patt, rtw_packet_filter_rule_t rule)
{
int i = 0;
while(i < MAX_PACKET_FILTER_INFO){
if(paff_array[i].filter_id == FILTER_ID_INIT_VALUE){
break;
}
i++;
}
if(i == MAX_PACKET_FILTER_INFO)
return -1;
paff_array[i].filter_id = filter_id;
paff_array[i].patt.offset= patt->offset;
paff_array[i].patt.mask_size = patt->mask_size;
paff_array[i].patt.mask = rtw_malloc(patt->mask_size);
memcpy(paff_array[i].patt.mask, patt->mask, patt->mask_size);
paff_array[i].patt.pattern= rtw_malloc(patt->mask_size);
memcpy(paff_array[i].patt.pattern, patt->pattern, patt->mask_size);
paff_array[i].rule = rule;
paff_array[i].enable = 0;
return 0;
}
int promisc_enable_packet_filter(u8 filter_id)
{
int i = 0;
while(i < MAX_PACKET_FILTER_INFO){
if(paff_array[i].filter_id == filter_id)
break;
i++;
}
if(i == MAX_PACKET_FILTER_INFO)
return -1;
paff_array[i].enable = 1;
packet_filter_enable_num++;
return 0;
}
int promisc_disable_packet_filter(u8 filter_id)
{
int i = 0;
while(i < MAX_PACKET_FILTER_INFO){
if(paff_array[i].filter_id == filter_id)
break;
i++;
}
if(i == MAX_PACKET_FILTER_INFO)
return -1;
paff_array[i].enable = 0;
packet_filter_enable_num--;
return 0;
}
int promisc_remove_packet_filter(u8 filter_id)
{
int i = 0;
while(i < MAX_PACKET_FILTER_INFO){
if(paff_array[i].filter_id == filter_id)
break;
i++;
}
if(i == MAX_PACKET_FILTER_INFO)
return -1;
paff_array[i].filter_id = FILTER_ID_INIT_VALUE;
paff_array[i].enable = 0;
paff_array[i].rule = 0;
if(paff_array[i].patt.mask){
rtw_mfree((void *) paff_array[i].patt.mask, paff_array[i].patt.mask_size);
paff_array[i].patt.mask = NULL;
}
if(paff_array[i].patt.pattern){
rtw_mfree((void *) paff_array[i].patt.pattern, paff_array[i].patt.mask_size);
paff_array[i].patt.pattern = NULL;
}
paff_array[i].patt.mask_size = 0;
return 0;
}
#endif
/* Make callback simple to prevent latency to wlan rx when promiscuous mode */
static void promisc_callback(unsigned char *buf, unsigned int len, void* userdata)
{
struct eth_frame *frame = (struct eth_frame *) rtw_malloc(sizeof(struct eth_frame));
if(frame) {
frame->prev = NULL;
frame->next = NULL;
memcpy(frame->da, buf, 6);
memcpy(frame->sa, buf+6, 6);
frame->len = len;
frame->rssi = ((ieee80211_frame_info_t *)userdata)->rssi;
_lock lock;
_irqL irqL;
rtw_enter_critical(&lock, &irqL);
if(eth_buffer.tail) {
eth_buffer.tail->next = frame;
frame->prev = eth_buffer.tail;
eth_buffer.tail = frame;
}
else {
eth_buffer.head = frame;
eth_buffer.tail = frame;
}
rtw_exit_critical(&lock, &irqL);
}
}
struct eth_frame* retrieve_frame(void)
{
struct eth_frame *frame = NULL;
_lock lock;
_irqL irqL;
rtw_enter_critical(&lock, &irqL);
if(eth_buffer.head) {
frame = eth_buffer.head;
if(eth_buffer.head->next) {
eth_buffer.head = eth_buffer.head->next;
eth_buffer.head->prev = NULL;
}
else {
eth_buffer.head = NULL;
eth_buffer.tail = NULL;
}
}
rtw_exit_critical(&lock, &irqL);
return frame;
}
static void promisc_test(int duration, unsigned char len_used)
{
int ch;
unsigned int start_time;
struct eth_frame *frame;
eth_buffer.head = NULL;
eth_buffer.tail = NULL;
wifi_enter_promisc_mode();
wifi_set_promisc(RTW_PROMISC_ENABLE, promisc_callback, len_used);
for(ch = 1; ch <= 13; ch ++) {
if(wifi_set_channel(ch) == 0)
printf("\n\n\rSwitch to channel(%d)", ch);
start_time = rtw_get_current_time();
while(1) {
unsigned int current_time = rtw_get_current_time();
if(rtw_systime_to_ms(current_time - start_time) < duration) {
frame = retrieve_frame();
if(frame) {
int i;
printf("\n\rDA:");
for(i = 0; i < 6; i ++)
printf(" %02x", frame->da[i]);
printf(", SA:");
for(i = 0; i < 6; i ++)
printf(" %02x", frame->sa[i]);
printf(", len=%d", frame->len);
printf(", RSSI=%d", frame->rssi);
#if CONFIG_INIC_CMD_RSP
if(inic_frame_tail){
if(inic_frame_cnt < MAX_INIC_FRAME_NUM){
memcpy(inic_frame_tail->da, frame->da, 6);
memcpy(inic_frame_tail->sa, frame->sa, 6);
inic_frame_tail->len = frame->len;
inic_frame_tail++;
inic_frame_cnt++;
}
}
#endif
rtw_mfree((void *) frame, sizeof(struct eth_frame));
}
else
rtw_mdelay_os(1); //delay 1 tick
}
else
break;
}
#if CONFIG_INIC_CMD_RSP
if(inic_frame){
inic_c2h_msg("ATWM", RTW_SUCCESS, (char *)inic_frame, sizeof(struct inic_eth_frame)*inic_frame_cnt);
memset(inic_frame, '\0', sizeof(struct inic_eth_frame)*MAX_INIC_FRAME_NUM);
inic_frame_tail = inic_frame;
inic_frame_cnt = 0;
rtw_msleep_os(10);
}
#endif
}
wifi_set_promisc(RTW_PROMISC_DISABLE, NULL, 0);
while((frame = retrieve_frame()) != NULL)
rtw_mfree((void *) frame, sizeof(struct eth_frame));
}
static void promisc_callback_all(unsigned char *buf, unsigned int len, void* userdata)
{
struct eth_frame *frame = (struct eth_frame *) rtw_malloc(sizeof(struct eth_frame));
if(frame) {
frame->prev = NULL;
frame->next = NULL;
memcpy(frame->da, buf+4, 6);
memcpy(frame->sa, buf+10, 6);
frame->len = len;
/*
* type is the first byte of Frame Control Field of 802.11 frame
* If the from/to ds information is needed, type could be reused as follows:
* frame->type = ((((ieee80211_frame_info_t *)userdata)->i_fc & 0x0100) == 0x0100) ? 2 : 1;
* 1: from ds; 2: to ds
*/
frame->type = *buf;
frame->rssi = ((ieee80211_frame_info_t *)userdata)->rssi;
_lock lock;
_irqL irqL;
rtw_enter_critical(&lock, &irqL);
if(eth_buffer.tail) {
eth_buffer.tail->next = frame;
frame->prev = eth_buffer.tail;
eth_buffer.tail = frame;
}
else {
eth_buffer.head = frame;
eth_buffer.tail = frame;
}
rtw_exit_critical(&lock, &irqL);
}
}
static void promisc_test_all(int duration, unsigned char len_used)
{
int ch;
unsigned int start_time;
struct eth_frame *frame;
eth_buffer.head = NULL;
eth_buffer.tail = NULL;
wifi_enter_promisc_mode();
wifi_set_promisc(RTW_PROMISC_ENABLE_2, promisc_callback_all, len_used);
for(ch = 1; ch <= 13; ch ++) {
if(wifi_set_channel(ch) == 0)
printf("\n\n\rSwitch to channel(%d)", ch);
start_time = rtw_get_current_time();
while(1) {
unsigned int current_time = rtw_get_current_time();
if(rtw_systime_to_ms(current_time - start_time) < duration) {
frame = retrieve_frame();
if(frame) {
int i;
printf("\n\rTYPE: 0x%x, ", frame->type);
printf("DA:");
for(i = 0; i < 6; i ++)
printf(" %02x", frame->da[i]);
printf(", SA:");
for(i = 0; i < 6; i ++)
printf(" %02x", frame->sa[i]);
printf(", len=%d", frame->len);
printf(", RSSI=%d", frame->rssi);
#if CONFIG_INIC_CMD_RSP
if(inic_frame_tail){
if(inic_frame_cnt < MAX_INIC_FRAME_NUM){
memcpy(inic_frame_tail->da, frame->da, 6);
memcpy(inic_frame_tail->sa, frame->sa, 6);
inic_frame_tail->len = frame->len;
inic_frame_tail->type = frame->type;
inic_frame_tail++;
inic_frame_cnt++;
}
}
#endif
rtw_mfree((void *) frame, sizeof(struct eth_frame));
}
else
rtw_mdelay_os(1); //delay 1 tick
}
else
break;
}
#if CONFIG_INIC_CMD_RSP
if(inic_frame){
inic_c2h_msg("ATWM", RTW_SUCCESS, (char *)inic_frame, sizeof(struct inic_eth_frame)*inic_frame_cnt);
memset(inic_frame, '\0', sizeof(struct inic_eth_frame)*MAX_INIC_FRAME_NUM);
inic_frame_tail = inic_frame;
inic_frame_cnt = 0;
rtw_msleep_os(10);
}
#endif
}
wifi_set_promisc(RTW_PROMISC_DISABLE, NULL, 0);
while((frame = retrieve_frame()) != NULL)
rtw_mfree((void *) frame, sizeof(struct eth_frame));
}
void cmd_promisc(int argc, char **argv)
{
int duration;
#if CONFIG_INIC_CMD_RSP
inic_frame_tail = inic_frame = rtw_malloc(sizeof(struct inic_eth_frame)*MAX_INIC_FRAME_NUM);
if(inic_frame == NULL){
inic_c2h_msg("ATWM", RTW_BUFFER_UNAVAILABLE_TEMPORARY, NULL, 0);
return;
}
#endif
#ifdef CONFIG_PROMISC
wifi_init_packet_filter();
#endif
if((argc == 2) && ((duration = atoi(argv[1])) > 0))
//promisc_test(duration, 0);
promisc_test_all(duration, 0);
else if((argc == 3) && ((duration = atoi(argv[1])) > 0) && (strcmp(argv[2], "with_len") == 0))
promisc_test(duration, 1);
else
printf("\n\rUsage: %s DURATION_SECONDS [with_len]", argv[0]);
#if CONFIG_INIC_CMD_RSP
if(inic_frame)
rtw_mfree(inic_frame, sizeof(struct inic_eth_frame)*MAX_INIC_FRAME_NUM);
inic_frame_tail = NULL;
inic_frame_cnt = 0;
#endif
}
#endif //#if CONFIG_WLAN

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/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef _UTIL_H
#define _UTIL_H
#include <wireless.h>
#include <wlan_intf.h>
#include <wifi_constants.h>
#include "wifi_structures.h"
#ifdef __cplusplus
extern "C" {
#endif
int wext_get_ssid(const char *ifname, __u8 *ssid);
int wext_set_ssid(const char *ifname, const __u8 *ssid, __u16 ssid_len);
int wext_set_auth_param(const char *ifname, __u16 idx, __u32 value);
int wext_set_key_ext(const char *ifname, __u16 alg, const __u8 *addr, int key_idx, int set_tx, const __u8 *seq, __u16 seq_len, __u8 *key, __u16 key_len);
int wext_get_enc_ext(const char *ifname, __u16 *alg, __u8 *key_idx, __u8 *passphrase);
int wext_set_passphrase(const char *ifname, const __u8 *passphrase, __u16 passphrase_len);
int wext_get_passphrase(const char *ifname, __u8 *passphrase);
int wext_set_mode(const char *ifname, int mode);
int wext_get_mode(const char *ifname, int *mode);
int wext_set_ap_ssid(const char *ifname, const __u8 *ssid, __u16 ssid_len);
int wext_set_country(const char *ifname, rtw_country_code_t country_code);
int wext_get_rssi(const char *ifname, int *rssi);
int wext_set_channel(const char *ifname, __u8 ch);
int wext_get_channel(const char *ifname, __u8 *ch);
int wext_register_multicast_address(const char *ifname, rtw_mac_t *mac);
int wext_unregister_multicast_address(const char *ifname, rtw_mac_t *mac);
int wext_set_scan(const char *ifname, char *buf, __u16 buf_len, __u16 flags);
int wext_get_scan(const char *ifname, char *buf, __u16 buf_len);
int wext_set_mac_address(const char *ifname, char * mac);
int wext_get_mac_address(const char *ifname, char * mac);
int wext_enable_powersave(const char *ifname, __u8 lps_mode, __u8 ips_mode);
int wext_disable_powersave(const char *ifname);
int wext_set_tdma_param(const char *ifname, __u8 slot_period, __u8 rfon_period_len_1, __u8 rfon_period_len_2, __u8 rfon_period_len_3);
int wext_set_lps_dtim(const char *ifname, __u8 lps_dtim);
int wext_get_lps_dtim(const char *ifname, __u8 *lps_dtim);
int wext_get_tx_power(const char *ifname, __u8 *poweridx);
int wext_set_txpower(const char *ifname, int poweridx);
int wext_get_associated_client_list(const char *ifname, void * client_list_buffer, __u16 buffer_length);
int wext_get_ap_info(const char *ifname, rtw_bss_info_t * ap_info, rtw_security_t* security);
int wext_mp_command(const char *ifname, char *cmd, int show_msg);
int wext_private_command(const char *ifname, char *cmd, int show_msg);
int wext_private_command_with_retval(const char *ifname, char *cmd, char *ret_buf, int ret_len);
void wext_wlan_indicate(unsigned int cmd, union iwreq_data *wrqu, char *extra);
int wext_set_pscan_channel(const char *ifname, __u8 *ch, __u8 *pscan_config, __u8 length);
int wext_set_autoreconnect(const char *ifname, __u8 mode, __u8 retry_times, __u16 timeout);
int wext_get_autoreconnect(const char *ifname, __u8 *mode);
int wext_set_adaptivity(rtw_adaptivity_mode_t adaptivity_mode);
int wext_set_adaptivity_th_l2h_ini(__u8 l2h_threshold);
int wext_get_auto_chl(const char *ifname, unsigned char *channel_set, unsigned char channel_num);
int wext_set_sta_num(unsigned char ap_sta_num);
int wext_del_station(const char *ifname, unsigned char* hwaddr);
int wext_init_mac_filter(void);
int wext_deinit_mac_filter(void);
int wext_add_mac_filter(unsigned char* hwaddr);
int wext_del_mac_filter(unsigned char* hwaddr);
void wext_set_indicate_mgnt(int enable);
#ifdef CONFIG_CUSTOM_IE
int wext_add_custom_ie(const char *ifname, void * cus_ie, int ie_num);
int wext_update_custom_ie(const char *ifname, void * cus_ie, int ie_index);
int wext_del_custom_ie(const char *ifname);
#endif
#define wext_handshake_done rltk_wlan_handshake_done
int wext_send_mgnt(const char *ifname, char *buf, __u16 buf_len, __u16 flags);
int wext_send_eapol(const char *ifname, char *buf, __u16 buf_len, __u16 flags);
int wext_set_gen_ie(const char *ifname, char *buf, __u16 buf_len, __u16 flags);
#ifdef __cplusplus
}
#endif
#endif /* _UTIL_H */

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targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/autoconf.h Normal file
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/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#ifndef WLANCONFIG_H
#define WLANCONFIG_H
/*
* Include user defined options first. Anything not defined in these files
* will be set to standard values. Override anything you dont like!
*/
#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) || defined(CONFIG_HARDWARE_8188F)
#include "platform_opts.h"
#endif
#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
#define CONFIG_PLATFORM_AMEBA_X
#endif
#if !defined(CONFIG_PLATFORM_AMEBA_X)
#define PLATFORM_FREERTOS 1
#define CONFIG_GSPI_HCI
#else
#define CONFIG_LX_HCI
#endif
#ifndef CONFIG_INIC_EN
#define CONFIG_INIC_EN 0 //For iNIC project
#endif
#if CONFIG_INIC_EN
#define CONFIG_LWIP_LAYER 0
#endif
#define CONFIG_LITTLE_ENDIAN
#define CONFIG_80211N_HT
//#define CONFIG_RECV_REORDERING_CTRL
#define RTW_NOTCH_FILTER 0
#define CONFIG_EMBEDDED_FWIMG
#define CONFIG_PHY_SETTING_WITH_ODM
#if !defined(CONFIG_PLATFORM_AMEBA_X)
#define CONFIG_ODM_REFRESH_RAMASK
#define HAL_MAC_ENABLE 1
#define HAL_BB_ENABLE 1
#define HAL_RF_ENABLE 1
#endif
#if defined(CONFIG_PLATFORM_AMEBA_X)
/* Patch when dynamic mechanism is not ready */
//#define CONFIG_DM_PATCH
#endif
//#define CONFIG_DEBUG
//#define CONFIG_DEBUG_RTL871X
#if defined(CONFIG_PLATFORM_AMEBA_X)
#define CONFIG_MEM_MONITOR MEM_MONITOR_SIMPLE
#define WLAN_INTF_DBG 0
//#define CONFIG_DEBUG_DYNAMIC
//#define DBG_TX 1
//#define DBG_XMIT_BUF 1
//#define DBG_XMIT_BUF_EXT 1
#define DBG_TX_DROP_FRAME
#else
#define CONFIG_MEM_MONITOR MEM_MONITOR_LEAK
//#define CONFIG_TRACE_SKB
//#define WLAN_INTF_DBG
#endif // CONFIG_PLATFORM_AMEBA_X
//#define CONFIG_DONT_CARE_TP
//#define CONFIG_HIGH_TP
//#define CONFIG_MEMORY_ACCESS_ALIGNED
#ifndef PLATFORM_CMSIS_RTOS // unsupported feature
#define CONFIG_POWER_SAVING
#endif
#ifdef CONFIG_POWER_SAVING
#define CONFIG_IPS
#define CONFIG_LPS
//#define CONFIG_LPS_LCLK
#define CONFIG_LPS_32K
#define TDMA_POWER_SAVING
#define CONFIG_WAIT_PS_ACK
#endif
#define BAD_MIC_COUNTERMEASURE 1
#define DEFRAGMENTATION 1
#define WIFI_LOGO_CERTIFICATION 0
#if WIFI_LOGO_CERTIFICATION
#define RX_AGGREGATION 1
#define RX_AMSDU 1
#else
#define RX_AGGREGATION 0
#define RX_AMSDU 0
#endif
#if defined(CONFIG_PLATFORM_AMEBA_X)
#if !defined(CONFIG_PLATFORM_8711B)
#define CONFIG_USE_TCM_HEAP 0 /* USE TCM HEAP */
#endif
#define CONFIG_RECV_TASKLET_THREAD
#define CONFIG_XMIT_TASKLET_THREAD
#else
#define CONFIG_XMIT_THREAD_MODE
#endif // CONFIG_PLATFORM_AMEBA_X
//#define CONFIG_RECV_THREAD_MODE /* Wlan IRQ Polling Mode*/
//#define CONFIG_ISR_THREAD_MODE_POLLING /* Wlan IRQ Polling Mode*/
//1 Chris
#ifndef CONFIG_SDIO_HCI
#define CONFIG_ISR_THREAD_MODE_INTERRUPT /* Wlan IRQ Interrupt Mode*/
#endif
#if defined(CONFIG_ISR_THREAD_MODE_POLLING) && defined(CONFIG_ISR_THREAD_MODE_INTERRUPT)
#error "CONFIG_ISR_THREAD_MODE_POLLING and CONFIG_ISR_THREAD_MODE_INTERRUPT are mutually exclusive. "
#endif
#if defined(CONFIG_PLATFORM_AMEBA_X)
/* CRC DMEM optimized mode consume 1k less SRM memory consumption */
#define CRC_IMPLEMENTATION_MODE CRC_IMPLEMENTATION_DMEM_OPTIMIZED
#endif
/* AES DMEM optimized mode comsume 10k less memory compare to
IMEM optimized mode AES_IMPLEMENTATION_IMEM_OPTIMIZED */
#define AES_IMPLEMENTATION_MODE AES_IMPLEMENTATION_DMEM_OPTIMIZED
#define USE_SKB_AS_XMITBUF 1
#if defined(CONFIG_PLATFORM_AMEBA_X)
#define USE_XMIT_EXTBUFF 1
#else
#define USE_XMIT_EXTBUFF 0
#endif
#define USE_MUTEX_FOR_SPINLOCK 1
// remove function to reduce code
#define NOT_SUPPORT_5G
#define NOT_SUPPORT_RF_MULTIPATH
#define NOT_SUPPORT_VHT
#define NOT_SUPPORT_40M
#define NOT_SUPPORT_80M
#ifndef CONFIG_PLATFORM_8711B
#define NOT_SUPPORT_BBSWING
#endif
#define NOT_SUPPORT_OLD_CHANNEL_PLAN
#define NOT_SUPPORT_BT
#define CONFIG_WIFI_SPEC 0
#define CONFIG_FAKE_EFUSE 0
#if CONFIG_FAKE_EFUSE
#define FAKE_CHIPID CHIPID_8710BN
#endif
#define CONFIG_AUTO_RECONNECT 1
#define ENABLE_HWPDN_PIN
#define SUPPORT_SCAN_BUF 1
#if !defined(CONFIG_PLATFORM_AMEBA_X)
#define BE_I_CUT 1
#endif
/* For WPA2 */
#define CONFIG_INCLUDE_WPA_PSK
#ifdef CONFIG_INCLUDE_WPA_PSK
#define CONFIG_MULTIPLE_WPA_STA
//#define CONFIG_WPA2_PREAUTH
#define PSK_SUPPORT_TKIP 1
#endif
//#define AP_PSK_SUPPORT_TKIP
/* For promiscuous mode */
#define CONFIG_PROMISC
#define PROMISC_DENY_PAIRWISE 0
/* For Simple Link */
#ifndef CONFIG_INCLUDE_SIMPLE_CONFIG
//#define CONFIG_INCLUDE_SIMPLE_CONFIG 1
#endif
// for probe request with custom vendor specific IE
#define CONFIG_CUSTOM_IE
#if !defined(CONFIG_PLATFORM_AMEBA_X)
/* For multicast */
#define CONFIG_MULTICAST
#endif
/* For STA+AP Concurrent MODE */
#define CONFIG_CONCURRENT_MODE
#ifdef CONFIG_CONCURRENT_MODE
#if defined(CONFIG_PLATFORM_8195A)
#define CONFIG_RUNTIME_PORT_SWITCH
#endif
#if defined(CONFIG_HARDWARE_8188F)
#define NET_IF_NUM 2
#else
#define NET_IF_NUM ((CONFIG_ETHERNET) + (CONFIG_WLAN) + 1)
#endif
#else
#if defined(CONFIG_HARDWARE_8188F)
#define NET_IF_NUM 1
#else
#define NET_IF_NUM ((CONFIG_ETHERNET) + (CONFIG_WLAN))
#endif
#endif
/****************** For EAP auth configurations *******************/
#define CONFIG_TLS 0
#define CONFIG_PEAP 0
#define CONFIG_TTLS 0
// DO NOT change the below config of EAP
#ifdef PRE_CONFIG_EAP
#define CONFIG_TLS 1
#define CONFIG_PEAP 1
#define CONFIG_TTLS 1
#endif
// enable 1X code in lib_wlan as default (increase 380 bytes)
#ifndef PLATFORM_CMSIS_RTOS // unsupported feature
#define CONFIG_EAP
#endif
#if CONFIG_TLS || CONFIG_PEAP || CONFIG_TTLS
#define EAP_REMOVE_UNUSED_CODE 1
#endif
#define EAP_SSL_VERIFY_SERVER
#if CONFIG_TLS
#define EAP_SSL_VERIFY_CLIENT
#endif
#if CONFIG_TTLS
#define EAP_MSCHAPv2
#define EAP_TTLS_MSCHAPv2
//#define EAP_TTLS_EAP
//#define EAP_TTLS_MSCHAP
//#define EAP_TTLS_PAP
//#define EAP_TTLS_CHAP
#endif
/****************** End of EAP configurations *******************/
/* For WPS and P2P */
#define CONFIG_WPS
#if 0
#define CONFIG_WPS_AP
#define CONFIG_P2P_NEW
#if (!defined(SUPPORT_SCAN_BUF)||!defined(CONFIG_WPS_AP)) && defined(CONFIG_P2P_NEW)
#error "If CONFIG_P2P_NEW, need to SUPPORT_SCAN_BUF"
#endif
#endif
#define CONFIG_NEW_SIGNAL_STAT_PROCESS
#define CONFIG_SKIP_SIGNAL_SCALE_MAPPING
/* For AP_MODE */
#define CONFIG_AP_MODE
extern unsigned char g_user_ap_sta_num;
#define USER_AP_STA_NUM g_user_ap_sta_num
#if defined(CONFIG_PLATFORM_AMEBA_X)
#define AP_STA_NUM 3 //2014/10/27 modify to 3
#define USE_DEDICATED_BCN_TX 0
#if USE_DEDICATED_BCN_TX
#error "WLAN driver for Ameba should not enable USE_DEDICATED_BCN_TX"
#endif
#else
extern unsigned int g_ap_sta_num;
#define AP_STA_NUM 3//g_ap_sta_num
#endif
#ifdef CONFIG_AP_MODE
#if defined(CONFIG_PLATFORM_8195A)
//softap sent qos null0 polling client alive or not
#define CONFIG_AP_POLLING_CLIENT_ALIVE
#endif
#define CONFIG_NATIVEAP_MLME
#if defined(CONFIG_PLATFORM_AMEBA_X)
#define CONFIG_INTERRUPT_BASED_TXBCN
#endif
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
//#define CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
#define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
#endif
// #define CONFIG_GK_REKEY
#if !defined(CONFIG_PLATFORM_AMEBA_X)
#define USE_DEDICATED_BCN_TX 1
#endif
#if CONFIG_INIC_EN
// #define REPORT_STA_EVENT //useless
#endif
#else
#if !defined(CONFIG_PLATFORM_AMEBA_X)
#define USE_DEDICATED_BCN_TX 0
#endif
#endif
#if defined(CONFIG_AP_MODE) && defined(CONFIG_GK_REKEY) && !defined(CONFIG_MULTIPLE_WPA_STA)
#error "If CONFIG_GK_REKEY when CONFIG_AP_MODE, need to CONFIG_MULTIPLE_WPA_STA"
#endif
#if !defined(CONFIG_PLATFORM_AMEBA_X)
#if !defined(CONFIG_AP_MODE) && defined(CONFIG_CONCURRENT_MODE)
#error "If CONFIG_CONCURRENT_MODEE, need to CONFIG_AP_MODE"
#endif
#endif
/* For efuse or flash config */
#if defined(CONFIG_PLATFORM_AMEBA_X)
#define CONFIG_RW_PHYSICAL_EFUSE 0 // Mask efuse user blocks
#define CONFIG_HIDE_PROTECT_EFUSE 1
#define CONFIG_ADAPTOR_INFO_CACHING_FLASH 1
#define CHECK_FLASH_VALID_MASK 1
#define CHECK_EFUSE_VALID_MASK 1
/* For K-free */
// #if !defined(CONFIG_PLATFORM_8711B)
#define CONFIG_RF_GAIN_OFFSET
// #endif
#endif // CONFIG_PLATFORM_AMEBA_X
/* For MP_MODE */
//#define CONFIG_MP_INCLUDED
#ifdef CONFIG_MP_INCLUDED
#define MP_DRIVER 1
#define CONFIG_MP_IWPRIV_SUPPORT
// #define HAL_EFUSE_MEMORY
#if defined(CONFIG_PLATFORM_AMEBA_X)
#define MP_REG_TEST
#endif
#else
#define MP_DRIVER 0
#if defined(CONFIG_PLATFORM_8195A)
//Control wifi mcu function
#define CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD
#define CONFIG_ODM_REFRESH_RAMASK
#endif
#endif // #ifdef CONFIG_MP_INCLUDED
#if defined(CONFIG_PLATFORM_AMEBA_X)
#if defined(CONFIG_PLATFORM_8195A)
#undef CONFIG_RTL8195A
#define CONFIG_RTL8195A
#endif
#if defined(CONFIG_PLATFORM_8711B)
#ifndef CONFIG_RTL8711B
#define CONFIG_RTL8711B
#endif
#undef CONFIG_ADAPTOR_INFO_CACHING_FLASH
#define CONFIG_ADAPTOR_INFO_CACHING_FLASH 0
//#undef CONFIG_EAP
//#undef CONFIG_IPS
#define CONFIG_8710B_MOVE_TO_ROM
#define CONFIG_EFUSE_SEPARATE
#define CONFIG_MOVE_PSK_TO_ROM
#define CONFIG_WOWLAN
#define CONFIG_TRAFFIC_PROTECT
#endif
#elif defined(CONFIG_HARDWARE_8188F)
#define CONFIG_RTL8188F
#else
#define CONFIG_RTL8188E
#endif
#define RTL8192C_SUPPORT 0
#define RTL8192CE_SUPPORT 0
#define RTL8192CU_SUPPORT 0
#define RTL8192D_SUPPORT 0
#define RTL8192DE_SUPPORT 0
#define RTL8192DU_SUPPORT 0
#define RTL8723A_SUPPORT 0
#define RTL8723AU_SUPPORT 0
#define RTL8723AS_SUPPORT 0
#define RTL8192E_SUPPORT 0
#define RTL8812A_SUPPORT 0
#define RTL8821A_SUPPORT 0
#define RTL8723B_SUPPORT 0
#define RTL8195A_SUPPORT 0
#define RTL8188E_SUPPORT 0
#define RTL8188F_SUPPORT 0
#define RTL8711B_SUPPORT 0
#if defined(CONFIG_PLATFORM_8195A)
#undef RTL8195A_SUPPORT
#define RTL8195A_SUPPORT 1
#elif defined(CONFIG_PLATFORM_8711B)
#undef RTL8711B_SUPPORT
#define RTL8711B_SUPPORT 1
#elif defined(CONFIG_HARDWARE_8188F)
#undef RTL8188F_SUPPORT
#define RTL8188F_SUPPORT 1
#else
#undef RTL8188E_SUPPORT
#define RTL8188E_SUPPORT 1
#endif
#define TEST_CHIP_SUPPORT 0
#define RTL8188E_FOR_TEST_CHIP 0
#define RTL8188E_FPGA_TRUE_PHY_VERIFICATION 0
// for Debug message
#define DBG 0
#if defined(CONFIG_PLATFORM_AMEBA_X)
#if(DBG == 0)
#define ROM_E_RTW_MSG 1
/* For DM debug*/
// BB
#define DBG_RX_INFO 1
#define DBG_TX_RATE 1 // DebugComponents: bit9
#define DBG_DM_RA 1 // DebugComponents: bit9
#define DBG_DM_DIG 1 // DebugComponents: bit0
#define DBG_DM_ADAPTIVITY 1 // DebugComponents: bit16
// RF
#define DBG_PWR_TRACKING 1 // DebugComponents: bit24
#define DBG_RF_IQK 1 // DebugComponents: bit26
// Common
#define DBG_PWR_INDEX 1 // DebugComponents: bit30
#endif
#endif
/* For DM support */
#if defined(CONFIG_RTL8188F)
#define RATE_ADAPTIVE_SUPPORT 0
#elif defined(CONFIG_PLATFORM_8711B)
#define RATE_ADAPTIVE_SUPPORT 1
#define CONFIG_ODM_REFRESH_RAMASK
#else
#define RATE_ADAPTIVE_SUPPORT 1
#endif
// adaptivity
#define RTW_ADAPTIVITY_EN_DISABLE 0
#define RTW_ADAPTIVITY_EN_ENABLE 1
#define CONFIG_RTW_ADAPTIVITY_EN RTW_ADAPTIVITY_EN_DISABLE
#define RTW_ADAPTIVITY_MODE_NORMAL 0
#define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1
#define CONFIG_RTW_ADAPTIVITY_MODE RTW_ADAPTIVITY_MODE_CARRIER_SENSE
#define CONFIG_RTW_ADAPTIVITY_DML 0
#if defined(CONFIG_PLATFORM_AMEBA_X)
#define CONFIG_POWER_TRAINING_WIL 0 // in RA
#else
#define POWER_BY_RATE_SUPPORT 0
#endif
#if defined(CONFIG_PLATFORM_AMEBA_X)
#define RTL8195A_FOR_TEST_CHIP 0
//#define CONFIG_WIFI_TEST 1
//#define CONFIG_MAC_LOOPBACK_DRIVER 1
//#define CONFIG_WLAN_HAL_TEST 1
//#define SKB_PRE_ALLOCATE_TX 1
#define SKB_PRE_ALLOCATE_RX 0
#define TX_CHECK_DSEC_ALWAYS 1
#define CONFIG_DBG_DISABLE_RDU_INTERRUPT
//#define CONFIG_WLAN_HAL_RX_TASK
#if (SKB_PRE_ALLOCATE_RX == 1)
#define EXCHANGE_LXBUS_RX_SKB 0
#endif
#ifdef CONFIG_FPGA
//Enable mac loopback for test mode (Ameba)
#define CONFIG_TWO_MAC_DRIVER // for test mode
#endif
#ifdef ENABLE_MAC_LB_FOR_TEST_MODE
#define CONFIG_SUDO_PHY_SETTING
#define INT_HANDLE_IN_ISR 1
#define CONFIG_LWIP_LAYER 0
#define CONFIG_WLAN_HAL_TEST
#define CONFIG_WLAN_HAL_RX_TASK
#define CONFIG_MAC_LOOPBACK_DRIVER_RTL8711B 1
#define HAL_MAC_ENABLE 1
#define CONFIG_TWO_MAC_TEST_MODE
#define DISABLE_BB_RF 1
#else
//#define CONFIG_TWO_MAC_DRIVER //for mornal driver; two mac
#ifdef CONFIG_TWO_MAC_DRIVER
#define CONFIG_SUDO_PHY_SETTING
#define HAL_MAC_ENABLE 1
#define DISABLE_BB_RF 1
#else
#define HAL_MAC_ENABLE 1
#define HAL_BB_ENABLE 1
#define HAL_RF_ENABLE 1
#define DISABLE_BB_RF 0
#endif
//#define INT_HANDLE_IN_ISR 1
#endif
#endif // CONFIG_PLATFORM_AMEBA_X
#ifndef CONFIG_LWIP_LAYER
#define CONFIG_LWIP_LAYER 1
#endif
#define CONFIG_MAC_ADDRESS 0
//fast reconnection
//#define CONFIG_FAST_RECONNECTION 1
#if defined(CONFIG_INIC_EN)&&(CONFIG_INIC_EN==1)
#define CONFIG_RECV_REORDERING_CTRL //enable reordering for iNIC high throughput
#undef RX_AGGREGATION
#define RX_AGGREGATION 1
#undef NOT_SUPPORT_40M
#undef CONFIG_CONCURRENT_MODE
#endif
#endif //WLANCONFIG_H

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/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#ifndef __DRV_CONF_H__
#define __DRV_CONF_H__
#include "autoconf.h"
#if ((RTL8195A_SUPPORT==1) || (RTL8711B_SUPPORT==1))
#include "platform_autoconf.h"
#endif
#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
#error "Shall be Linux or Windows, but not both!\n"
#endif
//Older Android kernel doesn't has CONFIG_ANDROID defined,
//add this to force CONFIG_ANDROID defined
#ifdef CONFIG_PLATFORM_ANDROID
#define CONFIG_ANDROID
#endif
#ifdef CONFIG_ANDROID
//Some Android build will restart the UI while non-printable ascii is passed
//between java and c/c++ layer (JNI). We force CONFIG_VALIDATE_SSID
//for Android here. If you are sure there is no risk on your system about this,
//mask this macro define to support non-printable ascii ssid.
//#define CONFIG_VALIDATE_SSID
#ifdef CONFIG_PLATFORM_ARM_SUNxI
#ifdef CONFIG_VALIDATE_SSID
#undef CONFIG_VALIDATE_SSID
#endif
#endif
//Android expect dbm as the rx signal strength unit
#define CONFIG_SIGNAL_DISPLAY_DBM
#endif
#if defined(CONFIG_HAS_EARLYSUSPEND) && defined (CONFIG_RESUME_IN_WORKQUEUE)
#warning "You have CONFIG_HAS_EARLYSUSPEND enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
#undef CONFIG_RESUME_IN_WORKQUEUE
#endif
#if defined(CONFIG_ANDROID_POWER) && defined (CONFIG_RESUME_IN_WORKQUEUE)
#warning "You have CONFIG_ANDROID_POWER enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
#undef CONFIG_RESUME_IN_WORKQUEUE
#endif
#ifdef CONFIG_RESUME_IN_WORKQUEUE //this can be removed, because there is no case for this...
#if !defined( CONFIG_WAKELOCK) && !defined(CONFIG_ANDROID_POWER)
#error "enable CONFIG_RESUME_IN_WORKQUEUE without CONFIG_WAKELOCK or CONFIG_ANDROID_POWER will suffer from the danger of wifi's unfunctionality..."
#error "If you still want to enable CONFIG_RESUME_IN_WORKQUEUE in this case, mask this preprossor checking and GOOD LUCK..."
#endif
#endif
//About USB VENDOR REQ
#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically"
#define CONFIG_USB_VENDOR_REQ_MUTEX
#endif
#if defined(CONFIG_VENDOR_REQ_RETRY) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_VENDOR_REQ_RETRY automatically"
#define CONFIG_USB_VENDOR_REQ_MUTEX
#endif
#ifndef CONFIG_RTW_ADAPTIVITY_EN
#define CONFIG_RTW_ADAPTIVITY_EN 0
#endif
#ifndef CONFIG_RTW_ADAPTIVITY_MODE
#define CONFIG_RTW_ADAPTIVITY_MODE 0
#endif
#ifndef CONFIG_RTW_ADAPTIVITY_DML
#define CONFIG_RTW_ADAPTIVITY_DML 0
#endif
#ifndef CONFIG_RTW_ADAPTIVITY_DC_BACKOFF
#define CONFIG_RTW_ADAPTIVITY_DC_BACKOFF 4
#endif
#ifndef CONFIG_RTW_NHM_EN
#define CONFIG_RTW_NHM_EN 0
#endif
//#include <rtl871x_byteorder.h>
#endif // __DRV_CONF_H__

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targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rom_aes.h Normal file
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/******************************************************************************
*
* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*
* This is ROM code section.
*
******************************************************************************/
#ifndef ROM_AES_H
#define ROM_AES_H
typedef struct
{
u32 erk[64]; /* encryption round keys */
u32 drk[64]; /* decryption round keys */
int nr; /* number of rounds */
}aes_context;
#define AES_BLOCKSIZE8 8
#define AES_BLK_SIZE 16 // # octets in an AES block
typedef union _aes_block // AES cipher block
{
unsigned long x[AES_BLK_SIZE/4]; // access as 8-bit octets or 32-bit words
unsigned char b[AES_BLK_SIZE];
}aes_block;
void AES_WRAP(unsigned char * plain, int plain_len,
unsigned char * iv, int iv_len,
unsigned char * kek, int kek_len,
unsigned char *cipher, unsigned short *cipher_len);
void AES_UnWRAP(unsigned char * cipher, int cipher_len,
unsigned char * kek, int kek_len,
unsigned char * plain);
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rtw_debug.h Normal file
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/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#ifndef __RTW_DEBUG_H__
#define __RTW_DEBUG_H__
#define _drv_always_ 1
#define _drv_emerg_ 2
#define _drv_alert_ 3
#define _drv_crit_ 4
#define _drv_err_ 5
#define _drv_warning_ 6
#define _drv_notice_ 7
#define _drv_info_ 8
#define _drv_dump_ 9
#define _drv_debug_ 10
#define _module_rtl871x_xmit_c_ BIT(0)
#define _module_xmit_osdep_c_ BIT(1)
#define _module_rtl871x_recv_c_ BIT(2)
#define _module_recv_osdep_c_ BIT(3)
#define _module_rtl871x_mlme_c_ BIT(4)
#define _module_mlme_osdep_c_ BIT(5)
#define _module_rtl871x_sta_mgt_c_ BIT(6)
#define _module_rtl871x_cmd_c_ BIT(7)
#define _module_cmd_osdep_c_ BIT(8)
#define _module_rtl871x_io_c_ BIT(9)
#define _module_io_osdep_c_ BIT(10)
#define _module_os_intfs_c_ BIT(11)
#define _module_rtl871x_security_c_ BIT(12)
#define _module_rtl871x_eeprom_c_ BIT(13)
#define _module_hal_init_c_ BIT(14)
#define _module_hci_hal_init_c_ BIT(15)
#define _module_rtl871x_ioctl_c_ BIT(16)
#define _module_rtl871x_ioctl_set_c_ BIT(17)
#define _module_rtl871x_ioctl_query_c_ BIT(18)
#define _module_rtl871x_pwrctrl_c_ BIT(19)
#define _module_hci_intfs_c_ BIT(20)
#define _module_hci_ops_c_ BIT(21)
#define _module_osdep_service_c_ BIT(22)
#define _module_mp_ BIT(23)
#define _module_hci_ops_os_c_ BIT(24)
#define _module_rtl871x_ioctl_os_c BIT(25)
#define _module_rtl8712_cmd_c_ BIT(26)
#define _module_fwcmd_c_ BIT(27)
#define _module_rtl8192c_xmit_c_ BIT(28)
#define _module_hal_xmit_c_ BIT(28)
#define _module_efuse_ BIT(29)
#define _module_rtl8712_recv_c_ BIT(30)
#define _module_rtl8712_led_c_ BIT(31)
#undef _MODULE_DEFINE_
#if defined _RTW_XMIT_C_
#define _MODULE_DEFINE_ _module_rtl871x_xmit_c_
#elif defined _XMIT_OSDEP_C_
#define _MODULE_DEFINE_ _module_xmit_osdep_c_
#elif defined _RTW_RECV_C_
#define _MODULE_DEFINE_ _module_rtl871x_recv_c_
#elif defined _RECV_OSDEP_C_
#define _MODULE_DEFINE_ _module_recv_osdep_c_
#elif defined _RTW_MLME_C_
#define _MODULE_DEFINE_ _module_rtl871x_mlme_c_
#elif defined _MLME_OSDEP_C_
#define _MODULE_DEFINE_ _module_mlme_osdep_c_
#elif defined _RTW_MLME_EXT_C_
#define _MODULE_DEFINE_ 1
#elif defined _RTW_STA_MGT_C_
#define _MODULE_DEFINE_ _module_rtl871x_sta_mgt_c_
#elif defined _RTW_CMD_C_
#define _MODULE_DEFINE_ _module_rtl871x_cmd_c_
#elif defined _CMD_OSDEP_C_
#define _MODULE_DEFINE_ _module_cmd_osdep_c_
#elif defined _RTW_IO_C_
#define _MODULE_DEFINE_ _module_rtl871x_io_c_
#elif defined _IO_OSDEP_C_
#define _MODULE_DEFINE_ _module_io_osdep_c_
#elif defined _OS_INTFS_C_
#define _MODULE_DEFINE_ _module_os_intfs_c_
#elif defined _RTW_SECURITY_C_
#define _MODULE_DEFINE_ _module_rtl871x_security_c_
#elif defined _RTW_EEPROM_C_
#define _MODULE_DEFINE_ _module_rtl871x_eeprom_c_
#elif defined _HAL_INTF_C_
#define _MODULE_DEFINE_ _module_hal_init_c_
#elif (defined _HCI_HAL_INIT_C_) || (defined _SDIO_HALINIT_C_)
#define _MODULE_DEFINE_ _module_hci_hal_init_c_
#elif defined _RTL871X_IOCTL_C_
#define _MODULE_DEFINE_ _module_rtl871x_ioctl_c_
#elif defined _RTL871X_IOCTL_SET_C_
#define _MODULE_DEFINE_ _module_rtl871x_ioctl_set_c_
#elif defined _RTL871X_IOCTL_QUERY_C_
#define _MODULE_DEFINE_ _module_rtl871x_ioctl_query_c_
#elif defined _RTL871X_PWRCTRL_C_
#define _MODULE_DEFINE_ _module_rtl871x_pwrctrl_c_
#elif defined _RTW_PWRCTRL_C_
#define _MODULE_DEFINE_ 1
#elif defined _HCI_INTF_C_
#define _MODULE_DEFINE_ _module_hci_intfs_c_
#elif defined _HCI_OPS_C_
#define _MODULE_DEFINE_ _module_hci_ops_c_
#elif defined _SDIO_OPS_C_
#define _MODULE_DEFINE_ 1
#elif defined _OSDEP_HCI_INTF_C_
#define _MODULE_DEFINE_ _module_hci_intfs_c_
#elif defined _OSDEP_SERVICE_C_
#define _MODULE_DEFINE_ _module_osdep_service_c_
#elif defined _HCI_OPS_OS_C_
#define _MODULE_DEFINE_ _module_hci_ops_os_c_
#elif defined _RTL871X_IOCTL_LINUX_C_
#define _MODULE_DEFINE_ _module_rtl871x_ioctl_os_c
#elif defined _RTL8712_CMD_C_
#define _MODULE_DEFINE_ _module_rtl8712_cmd_c_
#elif defined _RTL8192C_XMIT_C_
#define _MODULE_DEFINE_ 1
#elif defined _RTL8723AS_XMIT_C_
#define _MODULE_DEFINE_ 1
#elif defined _RTL8712_RECV_C_
#define _MODULE_DEFINE_ _module_rtl8712_recv_c_
#elif defined _RTL8192CU_RECV_C_
#define _MODULE_DEFINE_ _module_rtl8712_recv_c_
#elif defined _RTL871X_MLME_EXT_C_
#define _MODULE_DEFINE_ _module_mlme_osdep_c_
#elif defined _RTW_MP_C_
#define _MODULE_DEFINE_ _module_mp_
#elif defined _RTW_MP_IOCTL_C_
#define _MODULE_DEFINE_ _module_mp_
#elif defined _RTW_EFUSE_C_
#define _MODULE_DEFINE_ _module_efuse_
#endif
#ifdef PLATFORM_OS_CE
extern void rtl871x_cedbg(const char *fmt, ...);
#endif
#define RT_TRACE(_Comp, _Level, Fmt) do{}while(0)
#define _func_enter_ do{}while(0)
#define _func_exit_ do{}while(0)
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) do{}while(0)
#ifdef PLATFORM_WINDOWS
#define DBG_871X do {} while(0)
#define MSG_8192C do {} while(0)
#define DBG_8192C do {} while(0)
#define DBG_871X_LEVEL do {} while(0)
#else
#define DBG_871X(x, ...) do {} while(0)
#define MSG_8192C(x, ...) do {} while(0)
#define DBG_8192C(x,...) do {} while(0)
#define DBG_871X_LEVEL(x,...) do {} while(0)
#endif
#undef _dbgdump
#ifdef PLATFORM_WINDOWS
#ifdef PLATFORM_OS_XP
#define _dbgdump DbgPrint
#elif defined PLATFORM_OS_CE
#define _dbgdump rtl871x_cedbg
#endif
#elif defined PLATFORM_LINUX
#define _dbgdump printk
#elif defined PLATFORM_ECOS
#define _dbgdump diag_printf
#elif defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS)
#define _dbgdump printf("\n\r"); printf
#elif defined PLATFORM_FREEBSD
#define _dbgdump printf
#endif
#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B)
#define DRIVER_PREFIX "RTL871X: "
#endif
#define DEBUG_LEVEL (_drv_err_)
#if defined (_dbgdump)
#undef DBG_871X_LEVEL
#if defined (__ICCARM__) || defined (__CC_ARM) ||defined(__GNUC__)|| defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
#define DBG_871X_LEVEL(level, ...) \
do {\
_dbgdump(DRIVER_PREFIX __VA_ARGS__);\
}while(0)
#else
#define DBG_871X_LEVEL(level, fmt, arg...) \
do {\
if (level <= DEBUG_LEVEL) {\
if (level <= _drv_err_ && level > _drv_always_) {\
_dbgdump(DRIVER_PREFIX"ERROR " fmt, ##arg);\
} \
else {\
_dbgdump(DRIVER_PREFIX fmt, ##arg);\
} \
}\
}while(0)
#endif //#ifdef __CC_ARM
#endif
#ifdef CONFIG_DEBUG
#if defined (_dbgdump)
#undef DBG_871X
#define DBG_871X(...) do {\
_dbgdump(DRIVER_PREFIX __VA_ARGS__);\
}while(0)
#undef MSG_8192C
#define MSG_8192C(...) do {\
_dbgdump(DRIVER_PREFIX __VA_ARGS__);\
}while(0)
#undef DBG_8192C
#define DBG_8192C(...) do {\
_dbgdump(DRIVER_PREFIX __VA_ARGS__);\
}while(0)
#endif
#endif /* CONFIG_DEBUG */
#ifdef CONFIG_DEBUG_RTL871X
#ifndef _RTL871X_DEBUG_C_
extern u32 GlobalDebugLevel;
extern u64 GlobalDebugComponents;
#endif
#if defined (_dbgdump) && defined (_MODULE_DEFINE_)
#undef RT_TRACE
#define RT_TRACE(_Comp, _Level, Fmt)\
do {\
if((_Comp & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) {\
_dbgdump("%s [0x%08x,%d]", DRIVER_PREFIX, (unsigned int)_Comp, _Level);\
_dbgdump Fmt;\
}\
}while(0)
#endif
#if defined (_dbgdump)
#undef _func_enter_
#define _func_enter_ \
do { \
if (GlobalDebugLevel >= _drv_debug_) \
{ \
_dbgdump("\n %s : %s enters at %d\n", DRIVER_PREFIX, __FUNCTION__, __LINE__);\
} \
} while(0)
#undef _func_exit_
#define _func_exit_ \
do { \
if (GlobalDebugLevel >= _drv_debug_) \
{ \
_dbgdump("\n %s : %s exits at %d\n", DRIVER_PREFIX, __FUNCTION__, __LINE__); \
} \
} while(0)
#undef RT_PRINT_DATA
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
u8 *ptr = (u8 *)_HexData; \
printf("\r\n%s", DRIVER_PREFIX); \
printf(_TitleString "--------Len=%d\n\r", _HexDataLen); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
printf("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \
if (((__i + 1) % 16) == 0) printf("\n\r"); \
} \
printf("\n\r"); \
}
#endif
#endif /* CONFIG_DEBUG_RTL871X */
#ifdef CONFIG_PROC_DEBUG
int proc_get_drv_version(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_write_reg(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_set_write_reg(struct file *file, const char *buffer,
unsigned long count, void *data);
int proc_get_read_reg(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_set_read_reg(struct file *file, const char *buffer,
unsigned long count, void *data);
int proc_get_fwstate(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_sec_info(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_mlmext_state(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_qos_option(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_ht_option(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_rf_info(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_ap_info(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_adapter_state(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_trx_info(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_mac_reg_dump1(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_mac_reg_dump2(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_mac_reg_dump3(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_bb_reg_dump1(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_bb_reg_dump2(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_bb_reg_dump3(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_rf_reg_dump1(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_rf_reg_dump2(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_rf_reg_dump3(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_rf_reg_dump4(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
#ifdef CONFIG_AP_MODE
int proc_get_all_sta_info(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
#endif
#ifdef DBG_MEMORY_LEAK
int proc_get_malloc_cnt(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
#endif
#ifdef CONFIG_FIND_BEST_CHANNEL
int proc_get_best_channel(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
#endif
int proc_get_rx_signal(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_set_rx_signal(struct file *file, const char *buffer,
unsigned long count, void *data);
#ifdef CONFIG_80211N_HT
int proc_get_cbw40_enable(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_set_cbw40_enable(struct file *file, const char *buffer,
unsigned long count, void *data);
int proc_get_ampdu_enable(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_set_ampdu_enable(struct file *file, const char *buffer,
unsigned long count, void *data);
int proc_get_rx_stbc(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_set_rx_stbc(struct file *file, const char *buffer,
unsigned long count, void *data);
#endif //CONFIG_80211N_HT
int proc_get_two_path_rssi(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_rssi_disp(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_set_rssi_disp(struct file *file, const char *buffer,
unsigned long count, void *data);
#endif //CONFIG_PROC_DEBUG
#endif //__RTW_DEBUG_H__

544
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/wifi_constants.h Normal file
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@ -0,0 +1,544 @@
/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************
* @file wifi_constants.h
* @author
* @version
* @brief This file provides the data types used for wlan API.
******************************************************************************
*/
#ifndef _WIFI_CONSTANTS_H
#define _WIFI_CONSTANTS_H
#ifdef __cplusplus
extern "C" {
#endif
#ifndef WLAN0_NAME
#define WLAN0_NAME "wlan0"
#endif
#ifndef WLAN1_NAME
#define WLAN1_NAME "wlan1"
#endif
#define WEP_ENABLED 0x0001
#define TKIP_ENABLED 0x0002
#define AES_ENABLED 0x0004
#define WSEC_SWFLAG 0x0008
#define SHARED_ENABLED 0x00008000
#define WPA_SECURITY 0x00200000
#define WPA2_SECURITY 0x00400000
#define WPS_ENABLED 0x10000000
#define RTW_MAX_PSK_LEN (64)
#define RTW_MIN_PSK_LEN (8)
#define MCSSET_LEN 16
/**
* @brief The enumeration lists the results of the function.
*/
enum
{
RTW_SUCCESS = 0, /**< Success */
RTW_PENDING = 1, /**< Pending */
RTW_TIMEOUT = 2, /**< Timeout */
RTW_PARTIAL_RESULTS = 3, /**< Partial results */
RTW_INVALID_KEY = 4, /**< Invalid key */
RTW_DOES_NOT_EXIST = 5, /**< Does not exist */
RTW_NOT_AUTHENTICATED = 6, /**< Not authenticated */
RTW_NOT_KEYED = 7, /**< Not keyed */
RTW_IOCTL_FAIL = 8, /**< IOCTL fail */
RTW_BUFFER_UNAVAILABLE_TEMPORARY = 9, /**< Buffer unavailable temporarily */
RTW_BUFFER_UNAVAILABLE_PERMANENT = 10, /**< Buffer unavailable permanently */
RTW_WPS_PBC_OVERLAP = 11, /**< WPS PBC overlap */
RTW_CONNECTION_LOST = 12, /**< Connection lost */
RTW_ERROR = -1, /**< Generic Error */
RTW_BADARG = -2, /**< Bad Argument */
RTW_BADOPTION = -3, /**< Bad option */
RTW_NOTUP = -4, /**< Not up */
RTW_NOTDOWN = -5, /**< Not down */
RTW_NOTAP = -6, /**< Not AP */
RTW_NOTSTA = -7, /**< Not STA */
RTW_BADKEYIDX = -8, /**< BAD Key Index */
RTW_RADIOOFF = -9, /**< Radio Off */
RTW_NOTBANDLOCKED = -10, /**< Not band locked */
RTW_NOCLK = -11, /**< No Clock */
RTW_BADRATESET = -12, /**< BAD Rate valueset */
RTW_BADBAND = -13, /**< BAD Band */
RTW_BUFTOOSHORT = -14, /**< Buffer too short */
RTW_BUFTOOLONG = -15, /**< Buffer too long */
RTW_BUSY = -16, /**< Busy */
RTW_NOTASSOCIATED = -17, /**< Not Associated */
RTW_BADSSIDLEN = -18, /**< Bad SSID len */
RTW_OUTOFRANGECHAN = -19, /**< Out of Range Channel */
RTW_BADCHAN = -20, /**< Bad Channel */
RTW_BADADDR = -21, /**< Bad Address */
RTW_NORESOURCE = -22, /**< Not Enough Resources */
RTW_UNSUPPORTED = -23, /**< Unsupported */
RTW_BADLEN = -24, /**< Bad length */
RTW_NOTREADY = -25, /**< Not Ready */
RTW_EPERM = -26, /**< Not Permitted */
RTW_NOMEM = -27, /**< No Memory */
RTW_ASSOCIATED = -28, /**< Associated */
RTW_RANGE = -29, /**< Not In Range */
RTW_NOTFOUND = -30, /**< Not Found */
RTW_WME_NOT_ENABLED = -31, /**< WME Not Enabled */
RTW_TSPEC_NOTFOUND = -32, /**< TSPEC Not Found */
RTW_ACM_NOTSUPPORTED = -33, /**< ACM Not Supported */
RTW_NOT_WME_ASSOCIATION = -34, /**< Not WME Association */
RTW_SDIO_ERROR = -35, /**< SDIO Bus Error */
RTW_WLAN_DOWN = -36, /**< WLAN Not Accessible */
RTW_BAD_VERSION = -37, /**< Incorrect version */
RTW_TXFAIL = -38, /**< TX failure */
RTW_RXFAIL = -39, /**< RX failure */
RTW_NODEVICE = -40, /**< Device not present */
RTW_UNFINISHED = -41, /**< To be finished */
RTW_NONRESIDENT = -42, /**< access to nonresident overlay */
RTW_DISABLED = -43 /**< Disabled in this build */
};
typedef unsigned long rtw_result_t;
/**
* @brief The enumeration lists the possible security types to set when connection.\n
* Station mode supports OPEN, WEP, and WPA2.\n
* AP mode support OPEN and WPA2.
*/
enum {
RTW_SECURITY_OPEN = 0, /**< Open security */
RTW_SECURITY_WEP_PSK = WEP_ENABLED, /**< WEP Security with open authentication */
RTW_SECURITY_WEP_SHARED = ( WEP_ENABLED | SHARED_ENABLED ), /**< WEP Security with shared authentication */
RTW_SECURITY_WPA_TKIP_PSK = ( WPA_SECURITY | TKIP_ENABLED ), /**< WPA Security with TKIP */
RTW_SECURITY_WPA_AES_PSK = ( WPA_SECURITY | AES_ENABLED ), /**< WPA Security with AES */
RTW_SECURITY_WPA2_AES_PSK = ( WPA2_SECURITY | AES_ENABLED ), /**< WPA2 Security with AES */
RTW_SECURITY_WPA2_TKIP_PSK = ( WPA2_SECURITY | TKIP_ENABLED ), /**< WPA2 Security with TKIP */
RTW_SECURITY_WPA2_MIXED_PSK = ( WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED ), /**< WPA2 Security with AES & TKIP */
RTW_SECURITY_WPA_WPA2_MIXED = ( WPA_SECURITY | WPA2_SECURITY ), /**< WPA/WPA2 Security */
RTW_SECURITY_WPS_OPEN = WPS_ENABLED, /**< WPS with open security */
RTW_SECURITY_WPS_SECURE = (WPS_ENABLED | AES_ENABLED), /**< WPS with AES security */
RTW_SECURITY_UNKNOWN = -1, /**< May be returned by scan function if security is unknown. Do not pass this to the join function! */
RTW_SECURITY_FORCE_32_BIT = 0x7fffffff /**< Exists only to force rtw_security_t type to 32 bits */
};
typedef unsigned long rtw_security_t;
enum {
RTW_ENCRYPTION_UNKNOWN = 0,
RTW_ENCRYPTION_OPEN = 1,
RTW_ENCRYPTION_WEP40 = 2,
RTW_ENCRYPTION_WPA_TKIP = 3,
RTW_ENCRYPTION_WPA_AES = 4,
RTW_ENCRYPTION_WPA2_TKIP = 5,
RTW_ENCRYPTION_WPA2_AES = 6,
RTW_ENCRYPTION_WPA2_MIXED = 7,
RTW_ENCRYPTION_WEP104 = 9,
RTW_ENCRYPTION_UNDEF = 0xFF,
};
typedef unsigned long rtw_encryption_t;
enum {
RTW_FALSE = 0,
RTW_TRUE = 1
};
typedef unsigned long rtw_bool_t;
/**
* @brief The enumeration lists the band types.
*/
enum {
RTW_802_11_BAND_5GHZ = 0, /**< Denotes 5GHz radio band */
RTW_802_11_BAND_2_4GHZ = 1 /**< Denotes 2.4GHz radio band */
};
typedef unsigned long rtw_802_11_band_t;
/**
* @brief The enumeration lists all the country codes able to set to Wi-Fi driver.
*/
enum {
/* CHANNEL PLAN */
RTW_COUNTRY_WORLD1, // 0x20
RTW_COUNTRY_ETSI1, // 0x21
RTW_COUNTRY_FCC1, // 0x22
RTW_COUNTRY_MKK1, // 0x23
RTW_COUNTRY_ETSI2, // 0x24
RTW_COUNTRY_FCC2, // 0x2A
RTW_COUNTRY_WORLD2, // 0x47
RTW_COUNTRY_MKK2, // 0x58
/* SPECIAL */
RTW_COUNTRY_WORLD, // WORLD1
RTW_COUNTRY_EU, // ETSI1
/* JAPANESE */
RTW_COUNTRY_JP, // MKK1
/* FCC , 19 countries*/
RTW_COUNTRY_AS, // FCC2
RTW_COUNTRY_BM,
RTW_COUNTRY_CA,
RTW_COUNTRY_DM,
RTW_COUNTRY_DO,
RTW_COUNTRY_FM,
RTW_COUNTRY_GD,
RTW_COUNTRY_GT,
RTW_COUNTRY_GU,
RTW_COUNTRY_HT,
RTW_COUNTRY_MH,
RTW_COUNTRY_MP,
RTW_COUNTRY_NI,
RTW_COUNTRY_PA,
RTW_COUNTRY_PR,
RTW_COUNTRY_PW,
RTW_COUNTRY_TW,
RTW_COUNTRY_US,
RTW_COUNTRY_VI,
/* others, ETSI */
RTW_COUNTRY_AD, // ETSI1
RTW_COUNTRY_AE,
RTW_COUNTRY_AF,
RTW_COUNTRY_AI,
RTW_COUNTRY_AL,
RTW_COUNTRY_AM,
RTW_COUNTRY_AN,
RTW_COUNTRY_AR,
RTW_COUNTRY_AT,
RTW_COUNTRY_AU,
RTW_COUNTRY_AW,
RTW_COUNTRY_AZ,
RTW_COUNTRY_BA,
RTW_COUNTRY_BB,
RTW_COUNTRY_BD,
RTW_COUNTRY_BE,
RTW_COUNTRY_BF,
RTW_COUNTRY_BG,
RTW_COUNTRY_BH,
RTW_COUNTRY_BL,
RTW_COUNTRY_BN,
RTW_COUNTRY_BO,
RTW_COUNTRY_BR,
RTW_COUNTRY_BS,
RTW_COUNTRY_BT,
RTW_COUNTRY_BY,
RTW_COUNTRY_BZ,
RTW_COUNTRY_CF,
RTW_COUNTRY_CH,
RTW_COUNTRY_CI,
RTW_COUNTRY_CL,
RTW_COUNTRY_CN,
RTW_COUNTRY_CO,
RTW_COUNTRY_CR,
RTW_COUNTRY_CX,
RTW_COUNTRY_CY,
RTW_COUNTRY_CZ,
RTW_COUNTRY_DE,
RTW_COUNTRY_DK,
RTW_COUNTRY_DZ,
RTW_COUNTRY_EC,
RTW_COUNTRY_EE,
RTW_COUNTRY_EG,
RTW_COUNTRY_ES,
RTW_COUNTRY_ET,
RTW_COUNTRY_FI,
RTW_COUNTRY_FR,
RTW_COUNTRY_GB,
RTW_COUNTRY_GE,
RTW_COUNTRY_GF,
RTW_COUNTRY_GH,
RTW_COUNTRY_GL,
RTW_COUNTRY_GP,
RTW_COUNTRY_GR,
RTW_COUNTRY_GY,
RTW_COUNTRY_HK,
RTW_COUNTRY_HN,
RTW_COUNTRY_HR,
RTW_COUNTRY_HU,
RTW_COUNTRY_ID,
RTW_COUNTRY_IE,
RTW_COUNTRY_IL,
RTW_COUNTRY_IN,
RTW_COUNTRY_IQ,
RTW_COUNTRY_IR,
RTW_COUNTRY_IS,
RTW_COUNTRY_IT,
RTW_COUNTRY_JM,
RTW_COUNTRY_JO,
RTW_COUNTRY_KE,
RTW_COUNTRY_KH,
RTW_COUNTRY_KN,
RTW_COUNTRY_KP,
RTW_COUNTRY_KR,
RTW_COUNTRY_KW,
RTW_COUNTRY_KY,
RTW_COUNTRY_KZ,
RTW_COUNTRY_LA,
RTW_COUNTRY_LB,
RTW_COUNTRY_LC,
RTW_COUNTRY_LI,
RTW_COUNTRY_LK,
RTW_COUNTRY_LR,
RTW_COUNTRY_LS,
RTW_COUNTRY_LT,
RTW_COUNTRY_LU,
RTW_COUNTRY_LV,
RTW_COUNTRY_MA,
RTW_COUNTRY_MC,
RTW_COUNTRY_MD,
RTW_COUNTRY_ME,
RTW_COUNTRY_MF,
RTW_COUNTRY_MK,
RTW_COUNTRY_MN,
RTW_COUNTRY_MO,
RTW_COUNTRY_MQ,
RTW_COUNTRY_MR,
RTW_COUNTRY_MT,
RTW_COUNTRY_MU,
RTW_COUNTRY_MV,
RTW_COUNTRY_MW,
RTW_COUNTRY_MX,
RTW_COUNTRY_MY,
RTW_COUNTRY_NG,
RTW_COUNTRY_NL,
RTW_COUNTRY_NO,
RTW_COUNTRY_NP,
RTW_COUNTRY_NZ,
RTW_COUNTRY_OM,
RTW_COUNTRY_PE,
RTW_COUNTRY_PF,
RTW_COUNTRY_PG,
RTW_COUNTRY_PH,
RTW_COUNTRY_PK,
RTW_COUNTRY_PL,
RTW_COUNTRY_PM,
RTW_COUNTRY_PT,
RTW_COUNTRY_PY,
RTW_COUNTRY_QA,
RTW_COUNTRY_RS,
RTW_COUNTRY_RU,
RTW_COUNTRY_RW,
RTW_COUNTRY_SA,
RTW_COUNTRY_SE,
RTW_COUNTRY_SG,
RTW_COUNTRY_SI,
RTW_COUNTRY_SK,
RTW_COUNTRY_SN,
RTW_COUNTRY_SR,
RTW_COUNTRY_SV,
RTW_COUNTRY_SY,
RTW_COUNTRY_TC,
RTW_COUNTRY_TD,
RTW_COUNTRY_TG,
RTW_COUNTRY_TH,
RTW_COUNTRY_TN,
RTW_COUNTRY_TR,
RTW_COUNTRY_TT,
RTW_COUNTRY_TZ,
RTW_COUNTRY_UA,
RTW_COUNTRY_UG,
RTW_COUNTRY_UY,
RTW_COUNTRY_UZ,
RTW_COUNTRY_VC,
RTW_COUNTRY_VE,
RTW_COUNTRY_VN,
RTW_COUNTRY_VU,
RTW_COUNTRY_WF,
RTW_COUNTRY_WS,
RTW_COUNTRY_YE,
RTW_COUNTRY_YT,
RTW_COUNTRY_ZA,
RTW_COUNTRY_ZW,
RTW_COUNTRY_MAX
};
typedef unsigned long rtw_country_code_t;
/**
* @brief The enumeration lists the adaptivity types.
*/
enum {
RTW_ADAPTIVITY_DISABLE = 0,
RTW_ADAPTIVITY_NORMAL, // CE
RTW_ADAPTIVITY_CARRIER_SENSE // MKK
};
typedef unsigned long rtw_adaptivity_mode_t;
/**
* @brief The enumeration lists the supported operation mode by WIFI driver,
* including station and AP mode.
*/
enum {
RTW_MODE_NONE = 0,
RTW_MODE_STA,
RTW_MODE_AP,
RTW_MODE_STA_AP,
RTW_MODE_PROMISC,
RTW_MODE_P2P
};
typedef unsigned long rtw_mode_t;
enum {
RTW_SCAN_FULL = 0,
RTW_SCAN_SOCIAL,
RTW_SCAN_ONE
};
typedef unsigned long rtw_scan_mode_t;
/**
* @brief The enumeration lists the status to describe the connection link.
*/
enum {
RTW_LINK_DISCONNECTED = 0,
RTW_LINK_CONNECTED
};
typedef unsigned long rtw_link_status_t;
/**
* @brief The enumeration lists the scan types.
*/
enum {
RTW_SCAN_TYPE_ACTIVE = 0x00, /**< Actively scan a network by sending 802.11 probe(s) */
RTW_SCAN_TYPE_PASSIVE = 0x01, /**< Passively scan a network by listening for beacons from APs */
RTW_SCAN_TYPE_PROHIBITED_CHANNELS = 0x04 /**< Passively scan on channels not enabled by the country code */
};
typedef unsigned long rtw_scan_type_t;
/**
* @brief The enumeration lists the bss types.
*/
enum {
RTW_BSS_TYPE_INFRASTRUCTURE = 0, /**< Denotes infrastructure network */
RTW_BSS_TYPE_ADHOC = 1, /**< Denotes an 802.11 ad-hoc IBSS network */
RTW_BSS_TYPE_ANY = 2, /**< Denotes either infrastructure or ad-hoc network */
RTW_BSS_TYPE_UNKNOWN = -1 /**< May be returned by scan function if BSS type is unknown. Do not pass this to the Join function */
};
typedef unsigned long rtw_bss_type_t;
enum {
RTW_SCAN_COMMAMD = 0x01
};
typedef unsigned long rtw_scan_command_t;
enum{
COMMAND1 = 0x01
};
typedef unsigned long rtw_command_type;
enum {
RTW_WPS_TYPE_DEFAULT = 0x0000,
RTW_WPS_TYPE_USER_SPECIFIED = 0x0001,
RTW_WPS_TYPE_MACHINE_SPECIFIED = 0x0002,
RTW_WPS_TYPE_REKEY = 0x0003,
RTW_WPS_TYPE_PUSHBUTTON = 0x0004,
RTW_WPS_TYPE_REGISTRAR_SPECIFIED = 0x0005,
RTW_WPS_TYPE_NONE = 0x0006
};
typedef unsigned long rtw_wps_type_t;
/**
* @brief The enumeration lists all the network bgn mode.
*/
enum {
RTW_NETWORK_B = 1,
RTW_NETWORK_BG = 3,
RTW_NETWORK_BGN = 11
};
typedef unsigned long rtw_network_mode_t;
/**
* @brief The enumeration lists the interfaces.
*/
enum {
RTW_STA_INTERFACE = 0, /**< STA or Client Interface */
RTW_AP_INTERFACE = 1, /**< SoftAP Interface */
};
typedef unsigned long rtw_interface_t;
/**
* @brief The enumeration lists the packet filter rules.
*/
enum {
RTW_POSITIVE_MATCHING = 0, /**< Receive the data matching with this pattern and discard the other data */
RTW_NEGATIVE_MATCHING = 1 /**< Discard the data matching with this pattern and receive the other data */
};
typedef unsigned long rtw_packet_filter_rule_t;
/**
* @brief The enumeration lists the promisc levels.
*/
enum {
RTW_PROMISC_DISABLE = 0, /**< Disable the promisc */
RTW_PROMISC_ENABLE = 1, /**< Fetch all ethernet packets */
RTW_PROMISC_ENABLE_1 = 2, /**< Fetch only B/M packets */
RTW_PROMISC_ENABLE_2 = 3, /**< Fetch all 802.11 packets*/
RTW_PROMISC_ENABLE_3 = 4, /**< Fetch only B/M 802.11 packets*/
};
typedef unsigned long rtw_rcr_level_t;
/**
* @brief The enumeration lists the disconnect reasons.
*/
enum{
RTW_NO_ERROR = 0,
RTW_NONE_NETWORK = 1,
RTW_CONNECT_FAIL = 2,
RTW_WRONG_PASSWORD = 3 ,
RTW_DHCP_FAIL = 4,
RTW_UNKNOWN,
};
typedef unsigned long rtw_connect_error_flag_t;
enum {
RTW_TX_PWR_PERCENTAGE_100 = 0, /* 100%, default target output power. */
RTW_TX_PWR_PERCENTAGE_75 = 1, /* 75% */
RTW_TX_PWR_PERCENTAGE_50 = 2, /* 50% */
RTW_TX_PWR_PERCENTAGE_25 = 3, /* 25% */
RTW_TX_PWR_PERCENTAGE_12_5 = 4, /* 12.5% */
};
typedef unsigned long rtw_tx_pwr_percentage_t;
/**
* @brief The enumeration is event type indicated from wlan driver.
*/
enum _WIFI_EVENT_INDICATE{
WIFI_EVENT_CONNECT = 0,
WIFI_EVENT_DISCONNECT = 1,
WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2,
WIFI_EVENT_SCAN_RESULT_REPORT = 3,
WIFI_EVENT_SCAN_DONE = 4,
WIFI_EVENT_RECONNECTION_FAIL = 5,
WIFI_EVENT_SEND_ACTION_DONE = 6,
WIFI_EVENT_RX_MGNT = 7,
WIFI_EVENT_STA_ASSOC = 8,
WIFI_EVENT_STA_DISASSOC = 9,
WIFI_EVENT_STA_WPS_START = 10,
WIFI_EVENT_WPS_FINISH = 11,
WIFI_EVENT_EAPOL_START = 12,
WIFI_EVENT_EAPOL_RECVD = 13,
WIFI_EVENT_NO_NETWORK = 14,
WIFI_EVENT_BEACON_AFTER_DHCP = 15,
WIFI_EVENT_MAX,
};
typedef unsigned long rtw_event_indicate_t;
#ifdef __cplusplus
}
#endif
#endif /* _WIFI_CONSTANTS_H */

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/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************
* @file wifi_structures.h
* @author
* @version
* @brief This file provides the data structures used for wlan API.
******************************************************************************
*/
#ifndef _WIFI_STRUCTURES_H
#define _WIFI_STRUCTURES_H
//#include <freertos/freertos_service.h>
#include "wifi_constants.h"
#include "dlist.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__IAR_SYSTEMS_ICC__)
#pragma pack(1)
#endif
/**
* @brief The structure is used to describe the SSID.
*/
typedef struct rtw_ssid {
unsigned char len; /**< SSID length */
unsigned char val[33]; /**< SSID name (AP name) */
} rtw_ssid_t;
#if defined(__IAR_SYSTEMS_ICC__)
#pragma pack()
#endif
#if defined(__IAR_SYSTEMS_ICC__)
#pragma pack(1)
#endif
/**
* @brief The structure is used to describe the unique 6-byte MAC address.
*/
typedef struct rtw_mac {
unsigned char octet[6]; /**< Unique 6-byte MAC address */
} rtw_mac_t;
#if defined(__IAR_SYSTEMS_ICC__)
#pragma pack()
#endif
/**
* @brief The structure is used to describe the setting about SSID,
* security type, password and default channel, used to start AP mode.
* @note The data length of string pointed by ssid and password should not exceed 32.
*/
typedef struct rtw_ap_info {
rtw_ssid_t ssid;
rtw_security_t security_type;
unsigned char *password;
int password_len;
int channel;
}rtw_ap_info_t;
/**
* @brief The structure is used to describe the station mode setting about SSID,
* security type and password, used when connecting to an AP.
* @note The data length of string pointed by ssid and password should not exceed 32.
*/
typedef struct rtw_network_info {
rtw_ssid_t ssid;
rtw_mac_t bssid;
rtw_security_t security_type;
unsigned char *password;
int password_len;
int key_id;
}rtw_network_info_t;
#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
#pragma pack(1)
#endif
/**
* @brief The structure is used to describe the scan result of the AP.
*/
typedef struct rtw_scan_result {
rtw_ssid_t SSID; /**< Service Set Identification (i.e. Name of Access Point) */
rtw_mac_t BSSID; /**< Basic Service Set Identification (i.e. MAC address of Access Point) */
signed short signal_strength; /**< Receive Signal Strength Indication in dBm. <-90=Very poor, >-30=Excellent */
rtw_bss_type_t bss_type; /**< Network type */
rtw_security_t security; /**< Security type */
rtw_wps_type_t wps_type; /**< WPS type */
unsigned int channel; /**< Radio channel that the AP beacon was received on */
rtw_802_11_band_t band; /**< Radio band */
} rtw_scan_result_t;
#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
#pragma pack()
#endif
/**
* @brief The structure is used to describe the data needed by scan result handler function.
*/
typedef struct rtw_scan_handler_result {
rtw_scan_result_t ap_details;
rtw_bool_t scan_complete;
void* user_data;
} rtw_scan_handler_result_t;
#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
#pragma pack(1)
#endif
/**
* @brief The structure is used to store the WIFI setting gotten from WIFI driver.
*/
typedef struct rtw_wifi_setting {
rtw_mode_t mode;
unsigned char ssid[33];
unsigned char channel;
rtw_security_t security_type;
unsigned char password[65];
unsigned char key_idx;
}rtw_wifi_setting_t;
#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
#pragma pack()
#endif
/**
* @brief The structure is used to describe the setting when configure the network.
*/
typedef struct rtw_wifi_config {
unsigned int boot_mode;
unsigned char ssid[32];
unsigned char ssid_len;
unsigned char security_type;
unsigned char password[65];
unsigned char password_len;
unsigned char channel;
} rtw_wifi_config_t;
/**
* @brief The structure is used to describe the maclist.
*/
typedef struct
{
unsigned int count; /**< Number of MAC addresses in the list */
rtw_mac_t mac_list[1]; /**< Variable length array of MAC addresses */
} rtw_maclist_t;
/**
* @brief The structure is used to describe the bss info of the network.\n
* It include the version, BSSID, beacon_period, capability, SSID,
* channel, atm_window, dtim_period, RSSI e.g.
*/
typedef struct {
unsigned int version; /**< version field */
unsigned int length; /**< byte length of data in this record, */
/* starting at version and including IEs */
rtw_mac_t BSSID;
unsigned short beacon_period; /**< units are Kusec */
unsigned short capability; /**< Capability information */
unsigned char SSID_len;
unsigned char SSID[32];
unsigned char channel;
// struct {
// uint32_t count; /* # rates in this set */
// uint8_t rates[16]; /* rates in 500kbps units w/hi bit set if basic */
// } rateset; /* supported rates */
// rtw_chanspec_t chanspec; /* chanspec for bss */
unsigned short atim_window; /**< units are Kusec */
unsigned char dtim_period; /**< DTIM period */
signed short RSSI; /**< receive signal strength (in dBm) */
unsigned char n_cap; /**< BSS is 802.11N Capable */
unsigned int nbss_cap; /**< 802.11N BSS Capabilities (based on HT_CAP_*) */
unsigned char basic_mcs[MCSSET_LEN]; /**< 802.11N BSS required MCS set */
unsigned short ie_offset; /**< offset at which IEs start, from beginning */
unsigned int ie_length; /**< byte length of Information Elements */
} rtw_bss_info_t;
/**
* @brief The structure is used to set WIFI packet filter pattern.
*/
typedef struct {
unsigned short offset; /**< Offset in bytes to start filtering (referenced to the start of the ethernet packet) */
unsigned short mask_size; /**< Size of the mask in bytes */
unsigned char* mask; /**< Pattern mask bytes to be ANDed with the pattern eg. "\xff00" (must be in network byte order) */
unsigned char* pattern; /**< Pattern bytes used to filter eg. "\x0800" (must be in network byte order) */
} rtw_packet_filter_pattern_t;
typedef struct ieee80211_frame_info{
unsigned short i_fc;
unsigned short i_dur;
unsigned char i_addr1[6];
unsigned char i_addr2[6];
unsigned char i_addr3[6];
unsigned short i_seq;
unsigned char bssid[6];
unsigned char encrypt;
signed char rssi;
}ieee80211_frame_info_t;
typedef struct {
char filter_id;
rtw_packet_filter_pattern_t patt;
rtw_packet_filter_rule_t rule;
unsigned char enable;
}rtw_packet_filter_info_t;
typedef struct rtw_mac_filter_list{
struct list_head node;
unsigned char mac_addr[6];
}rtw_mac_filter_list_t;
#ifdef __cplusplus
}
#endif
#endif /* _WIFI_STRUCTURES_H */

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/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************
* Wrapper provide a linux-like interface
************************************************************************/
#ifndef __WRAPPER_H__
#define __WRAPPER_H__
//----- ------------------------------------------------------------------
// Include Files
//----- ------------------------------------------------------------------
#include <stdio.h>
#include <string.h>
#include "wireless.h"
#include <skbuff.h>
#ifdef PLATFORM_FREERTOS
#include "freertos_service.h"
#elif defined(PLATFORM_CMSIS_RTOS)
#include "rtx_service.h"
#endif
#ifndef __LIST_H
#warning "DLIST_NOT_DEFINE!!!!!!"
//----- ------------------------------------------------------------------
// Linled List
//----- ------------------------------------------------------------------
/*
* Simple doubly linked list implementation.
*
* Some of the internal functions ("__xxx") are useful when
* manipulating whole lists rather than single entries, as
* sometimes we already know the next/prev entries and we can
* generate better code by using them directly rather than
* using the generic single-entry routines.
*/
// struct list_head {
// struct list_head *next, *prev;
// };
#define LIST_HEAD_INIT(name) { &(name), &(name) }
#define INIT_LIST_HEAD(ptr) do { \
(ptr)->next = (ptr); (ptr)->prev = (ptr); \
} while (0)
/*
* Insert a new entry between two known consecutive entries.
*
* This is only for internal list manipulation where we know
* the prev/next entries already!
*/
static __inline void __list_add(struct list_head * new,
struct list_head * prev,
struct list_head * next)
{
next->prev = new;
new->next = next;
new->prev = prev;
prev->next = new;
}
/*
* Delete a list entry by making the prev/next entries
* point to each other.
*
* This is only for internal list manipulation where we know
* the prev/next entries already!
*/
static __inline void __list_del(struct list_head * prev,
struct list_head * next)
{
next->prev = prev;
prev->next = next;
}
/**
* list_del - deletes entry from list.
* @entry: the element to delete from the list.
* Note: list_empty on entry does not return true after this, the entry is in an undefined state.
*/
static __inline void list_del(struct list_head *entry)
{
__list_del(entry->prev, entry->next);
}
/**
* list_del_init - deletes entry from list and reinitialize it.
* @entry: the element to delete from the list.
*/
static __inline void list_del_init(struct list_head *entry)
{
__list_del(entry->prev, entry->next);
INIT_LIST_HEAD(entry);
}
/**
* list_empty - tests whether a list is empty
* @head: the list to test.
*/
static __inline int list_empty(struct list_head *head)
{
return head->next == head;
}
/**
* list_splice - join two lists
* @list: the new list to add.
* @head: the place to add it in the first list.
*/
static __inline void list_splice(struct list_head *list, struct list_head *head)
{
struct list_head *first = list->next;
if (first != list) {
struct list_head *last = list->prev;
struct list_head *at = head->next;
first->prev = head;
head->next = first;
last->next = at;
at->prev = last;
}
}
void list_add(struct list_head *new, struct list_head *head);
void list_add_tail(struct list_head *new, struct list_head *head);
#endif
extern void save_and_cli(void);
extern void restore_flags(void);
//----- ------------------------------------------------------------------
// SKB Operation
//----- ------------------------------------------------------------------
#define SMP_CACHE_BYTES 4
#define SKB_DATA_ALIGN(X) (((X) + (SMP_CACHE_BYTES - 1)) & ~(SMP_CACHE_BYTES - 1))
// Consideration for SKB size
// Tx: [INTF_CMD][TX_DESC][WLAN_HDR][QoS][IV][SNAP][Data][MIC][ICV][INTF_STATUS]
// Since SKB is used to accept ethernet packet from upper layer, SKB length of WLAN_MAX_ETHFRM_LEN
// (= 1514) is enough. But since SKB is also used to get spi receive packet, overall buffer space
// should be taken into consideration.
// RX: [INTF_CMD][RX_DESC][Drv_Info][WLAN_HDR][QoS][IV][SNAP][Data][MIC][ICV][CRC][INTF_STATUS]
//
// 32: Driver_Info that carry phy related information for each packets. Required only for receive case.
// WLAN_MAX_ETHFRM_LEN : May not be required because WLAN_HEADER +SNAP can totally
// cover ethernet header. Keep in only for safety.
//
// **Notes** SDIO requires 512 blocks r/w, so 512*4 = 2048 is required.
// 2003/12/26. The value is reduced from 2048 to 1658 for GSPI
// 2014/02/05. The value is 1650 for 8195A LX_BUS
#define SKB_RESERVED_FOR_SAFETY 0
#define SKB_WLAN_TX_EXTRA_LEN (TXDESC_SIZE + WLAN_HDR_A4_QOS_LEN + WLAN_MAX_IV_LEN + WLAN_SNAP_HEADER - WLAN_ETHHDR_LEN)
#define RX_DRIVER_INFO 32
#if (defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI)
#define HAL_INTERFACE_OVERHEAD_SKB_DATA 12 //HAL_INTERFACE_CMD (4) + HAL_INTERFACE_STATUS (8)
#elif defined(CONFIG_LX_HCI)
#define HAL_INTERFACE_OVERHEAD_SKB_DATA 0
#endif
#if defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI || defined(CONFIG_LX_HCI)
#if defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B)
#if defined(CONFIG_MP_INCLUDED)
#ifdef CONFIG_DONT_CARE_TP
#define MAX_RX_PKT_LIMIT ((WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_RX_ETHFRM_LEN + 511) / 512) // 4, for lxbus
#else
#define MAX_RX_PKT_LIMIT ((WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_ETHFRM_LEN + 511) / 512) // 4, for lxbus
#endif
#define MAX_RX_PKT_SIZE MAX_RX_PKT_LIMIT*512 // MAX_SKB_BUF_SIZE = 0+32+40+512*4+0 = 2120
#else
#ifdef CONFIG_DONT_CARE_TP
#define MAX_RX_PKT_SIZE WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_RX_ETHFRM_LEN
#else
#define MAX_RX_PKT_SIZE WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_ETHFRM_LEN // MAX_RX_PKT_SIZE = 64+1514 = 1578
#endif
#define MAX_RX_PKT_LIMIT ((MAX_RX_PKT_SIZE + 511) / 512) // ((1578 + 512) / 512) = 4
#endif
#else
#ifdef CONFIG_DONT_CARE_TP
#define MAX_RX_PKT_SIZE WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_RX_ETHFRM_LEN
#else
#define MAX_RX_PKT_SIZE WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_ETHFRM_LEN
#endif
#endif
#ifdef CONFIG_DONT_CARE_TP
#define MAX_TX_SKB_BUF_SIZE (HAL_INTERFACE_OVERHEAD_SKB_DATA+RX_DRIVER_INFO+\
((TXDESC_SIZE>RXDESC_SIZE)? TXDESC_SIZE:RXDESC_SIZE) +\
WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_TX_ETHFRM_LEN +\
SKB_RESERVED_FOR_SAFETY)
#define MAX_RX_SKB_BUF_SIZE (HAL_INTERFACE_OVERHEAD_SKB_DATA+RX_DRIVER_INFO+\
((TXDESC_SIZE>RXDESC_SIZE)? TXDESC_SIZE:RXDESC_SIZE) +\
MAX_RX_PKT_SIZE +\
SKB_RESERVED_FOR_SAFETY)
#else
#define MAX_SKB_BUF_SIZE (HAL_INTERFACE_OVERHEAD_SKB_DATA+RX_DRIVER_INFO+\
((TXDESC_SIZE>RXDESC_SIZE)? TXDESC_SIZE:RXDESC_SIZE) +\
MAX_RX_PKT_SIZE +\
SKB_RESERVED_FOR_SAFETY) // 0+32+40+1578+0 = 1650
#endif
#else
#define MAX_SKB_BUF_SIZE 2048
#endif
#if 0
struct sk_buff_head {
struct list_head *next, *prev;
u32 qlen;
};
struct sk_buff {
/* These two members must be first. */
struct sk_buff *next; /* Next buffer in list */
struct sk_buff *prev; /* Previous buffer in list */
struct sk_buff_head *list; /* List we are on */
unsigned char *head; /* Head of buffer */
unsigned char *data; /* Data head pointer */
unsigned char *tail; /* Tail pointer */
unsigned char *end; /* End pointer */
struct net_device *dev; /* Device we arrived on/are leaving by */
unsigned int len; /* Length of actual data */
};
/**
* skb_put - add data to a buffer
* @skb: buffer to use
* @len: amount of data to add
*
* This function extends the used data area of the buffer. If this would
* exceed the total buffer size the kernel will panic. A pointer to the
* first byte of the extra data is returned.
*/
static __inline__ unsigned char *skb_put(struct sk_buff *skb, unsigned int len)
{
unsigned char *tmp=skb->tail;
skb->tail+=len;
skb->len+=len;
if(skb->tail>skb->end) {
ASSERT(0);
}
return tmp;
}
static __inline__ unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len)
{
skb->len-=len;
skb->data = (unsigned char *)(((unsigned int)skb->data) + len);
return skb->data;
}
/**
* skb_reserve - adjust headroom
* @skb: buffer to alter
* @len: bytes to move
*
* Increase the headroom of an empty &sk_buff by reducing the tail
* room. This is only allowed for an empty buffer.
*/
static __inline__ void skb_reserve(struct sk_buff *skb, unsigned int len)
{
skb->data+=len;
skb->tail+=len;
}
static __inline__ void skb_queue_head_init(struct sk_buff_head *list)
{
list->prev = (struct list_head *)list;
list->next = (struct list_head *)list;
list->qlen = 0;
}
/**
* __skb_queue_tail - queue a buffer at the list tail
* @list: list to use
* @newsk: buffer to queue
*
* Queue a buffer at the end of a list. This function takes no locks
* and you must therefore hold required locks before calling it.
*
* A buffer cannot be placed on two lists at the same time.
*/
static __inline__ void __skb_queue_tail(struct sk_buff_head *list, struct sk_buff *newsk)
{
struct sk_buff *prev, *next;
newsk->list = list;
list->qlen++;
next = (struct sk_buff *)list;
prev = next->prev;
newsk->next = next;
newsk->prev = prev;
next->prev = newsk;
prev->next = newsk;
}
/**
* skb_queue_tail - queue a buffer at the list tail
* @list: list to use
* @newsk: buffer to queue
*
* Queue a buffer at the tail of the list. This function takes the
* list lock and can be used safely with other locking &sk_buff functions
* safely.
*
* A buffer cannot be placed on two lists at the same time.
*/
static __inline__ void skb_queue_tail(struct sk_buff_head *list, struct sk_buff *newsk)
{
save_and_cli();
__skb_queue_tail(list, newsk);
restore_flags();
}
static __inline__ void skb_assign_buf(struct sk_buff *skb, unsigned char *buf, unsigned int len)
{
skb->head = buf;
skb->data = buf;
skb->tail = buf;
skb->end = buf + len;
}
static __inline__ unsigned char *skb_tail_pointer(const struct sk_buff *skb)
{
return skb->tail;
}
static __inline__ void skb_reset_tail_pointer(struct sk_buff *skb)
{
skb->tail = skb->data;
}
static __inline__ void skb_set_tail_pointer(struct sk_buff *skb, const int offset)
{
skb->tail = skb->data + offset;
}
static __inline__ unsigned char *skb_end_pointer(const struct sk_buff *skb)
{
return skb->end;
}
#endif
/*
* External functions
*/
struct net_device;
extern void kfree_skb_chk_key(struct sk_buff *skb, struct net_device *root_dev);
#ifdef CONFIG_TRACE_SKB
extern void show_skb(void);
extern int _set_skb_list_flag(struct sk_buff *skb, unsigned int queueflag);
extern void dump_skb_list(void);
#define set_skb_list_flag(skb, queueflag) \
(\
_set_skb_list_flag((skb), queueflag), \
(skb) ? (skb)->funcname[(skb)->list_idx] = __FUNCTION__:NULL \
)
extern int _clear_skb_list_flag(struct sk_buff *skb, unsigned int queueflag);
#define clear_skb_list_flag(skb, queueflag) \
(\
_clear_skb_list_flag((skb), queueflag), \
(skb) ? (skb)->funcname[(skb)->list_idx] = __FUNCTION__ : NULL \
)
#define dev_kfree_skb_any(trx, holder, skb) \
do{\
clear_skb_list_flag(skb, SKBLIST_##trx##holder##_MASK);\
set_skb_list_flag(skb, SKBLIST_POOL);\
kfree_skb_chk_key(skb, skb->dev);\
}while (0)
#else
#define dev_kfree_skb_any(skb) kfree_skb_chk_key(skb, skb->dev)
#endif
extern struct sk_buff *dev_alloc_skb(unsigned int length, unsigned int reserve_len);
extern struct sk_buff *skb_clone(struct sk_buff *skb, int gfp_mask);
extern struct sk_buff *skb_copy(const struct sk_buff *skb, int gfp_mask, unsigned int reserve_len);
extern unsigned char *skb_pull(struct sk_buff *skb, unsigned int len);
//----- ------------------------------------------------------------------
// Device structure
//----- ------------------------------------------------------------------
struct net_device_stats {
unsigned long rx_packets; /* total packets received */
unsigned long tx_packets; /* total packets transmitted */
unsigned long rx_dropped; /* no space in linux buffers */
unsigned long tx_dropped; /* no space available in linux */
unsigned long rx_bytes; /* total bytes received */
unsigned long tx_bytes; /* total bytes transmitted */
unsigned long rx_overflow; /* rx fifo overflow count */
};
struct net_device {
char name[16];
void *priv; /* pointer to private data */
unsigned char dev_addr[6]; /* set during bootup */
int (*init)(void);
int (*open)(struct net_device *dev);
int (*stop)(struct net_device *dev);
int (*hard_start_xmit)(struct sk_buff *skb, struct net_device *dev);
int (*do_ioctl)(struct net_device *dev, struct iwreq *ifr, int cmd);
struct net_device_stats* (*get_stats)(struct net_device *dev);
};
typedef struct {
struct net_device *dev; /* Binding wlan driver netdev */
void *skb; /* pending Rx packet */
unsigned int tx_busy;
unsigned int rx_busy;
unsigned char enable;
unsigned char mac[6];
} Rltk_wlan_t;
#define netdev_priv(dev) dev->priv
extern struct net_device *alloc_etherdev(int sizeof_priv);
void free_netdev(struct net_device *dev);
int dev_alloc_name(struct net_device *net_dev, const char *ifname);
//----- ------------------------------------------------------------------
// Timer Operation
//----- ------------------------------------------------------------------
void init_timer(struct timer_list *timer);
void mod_timer(struct timer_list *timer, u32 delay_time_ms);
void cancel_timer_ex(struct timer_list * timer);
void del_timer_sync(struct timer_list * timer);
void init_timer_wrapper(void);
void deinit_timer_wrapper(void);
void rtw_init_timer(_timer *ptimer, void *adapter, TIMER_FUN pfunc,void* cntx, const char *name);
void rtw_set_timer(_timer *ptimer,u32 delay_time);
u8 rtw_cancel_timer(_timer *ptimer);
void rtw_del_timer(_timer *ptimer);
#endif //__WRAPPER_H__

271
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/lwip_intf.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
//#define _LWIP_INTF_C_
#include <autoconf.h>
#include <lwip_intf.h>
#include <lwip/netif.h>
#if !DEVICE_EMAC
#include <lwip_netconf.h>
#include <ethernetif.h>
#endif
#include <osdep_service.h>
#include <wifi/wifi_util.h>
//----- ------------------------------------------------------------------
// External Reference
//----- ------------------------------------------------------------------
#if (CONFIG_LWIP_LAYER == 1)
#if DEVICE_EMAC
extern struct netif *xnetif[];
#else
extern struct netif xnetif[]; //LWIP netif
#endif
#endif
/**
* rltk_wlan_set_netif_info - set netif hw address and register dev pointer to netif device
* @idx_wlan: netif index
* 0 for STA only or SoftAP only or STA in STA+SoftAP concurrent mode,
* 1 for SoftAP in STA+SoftAP concurrent mode
* @dev: register netdev pointer to LWIP. Reserved.
* @dev_addr: set netif hw address
*
* Return Value: None
*/
void rltk_wlan_set_netif_info(int idx_wlan, void * dev, unsigned char * dev_addr)
{
#if (CONFIG_LWIP_LAYER == 1)
#if DEVICE_EMAC
//rtw_memcpy(xnetif[idx_wlan]->hwaddr, dev_addr, 6);
//set netif hwaddr later
#else
rtw_memcpy(xnetif[idx_wlan].hwaddr, dev_addr, 6);
xnetif[idx_wlan].state = dev;
#endif
#endif
}
/**
* rltk_wlan_send - send IP packets to WLAN. Called by low_level_output().
* @idx: netif index
* @sg_list: data buffer list
* @sg_len: size of each data buffer
* @total_len: total data len
*
* Return Value: None
*/
int rltk_wlan_send(int idx, struct eth_drv_sg *sg_list, int sg_len, int total_len)
{
#if (CONFIG_LWIP_LAYER == 1)
struct eth_drv_sg *last_sg;
struct sk_buff *skb = NULL;
int ret = 0;
if(idx == -1){
DBG_ERR("netif is DOWN");
return -1;
}
DBG_TRACE("%s is called", __FUNCTION__);
save_and_cli();
if(rltk_wlan_check_isup(idx))
rltk_wlan_tx_inc(idx);
else {
DBG_ERR("netif is DOWN");
restore_flags();
return -1;
}
restore_flags();
skb = rltk_wlan_alloc_skb(total_len);
if (skb == NULL) {
//DBG_ERR("rltk_wlan_alloc_skb() for data len=%d failed!", total_len);
ret = -1;
goto exit;
}
for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
rtw_memcpy(skb->tail, (void *)(sg_list->buf), sg_list->len);
skb_put(skb, sg_list->len);
}
rltk_wlan_send_skb(idx, skb);
exit:
save_and_cli();
rltk_wlan_tx_dec(idx);
restore_flags();
return ret;
#endif
}
/**
* rltk_wlan_recv - indicate packets to LWIP. Called by ethernetif_recv().
* @idx: netif index
* @sg_list: data buffer list
* @sg_len: size of each data buffer
*
* Return Value: None
*/
void rltk_wlan_recv(int idx, struct eth_drv_sg *sg_list, int sg_len)
{
#if (CONFIG_LWIP_LAYER == 1)
struct eth_drv_sg *last_sg;
struct sk_buff *skb;
DBG_TRACE("%s is called", __FUNCTION__);
if (!rltk_wlan_check_isup(idx))
return;
if(idx == -1){
DBG_ERR("skb is NULL");
return;
}
skb = rltk_wlan_get_recv_skb(idx);
DBG_ASSERT(skb, "No pending rx skb");
for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
if (sg_list->buf != 0) {
rtw_memcpy((void *)(sg_list->buf), skb->data, sg_list->len);
skb_pull(skb, sg_list->len);
}
}
#endif
}
int netif_is_valid_IP(int idx, unsigned char *ip_dest)
{
#if CONFIG_LWIP_LAYER == 1
#if DEVICE_EMAC
return 1;
#else
struct netif *pnetif = &xnetif[idx];
ip_addr_t addr = { 0 };
#ifdef CONFIG_MEMORY_ACCESS_ALIGNED
unsigned int temp;
memcpy(&temp, ip_dest, sizeof(unsigned int));
u32_t *ip_dest_addr = &temp;
#else
u32_t *ip_dest_addr = (u32_t*)ip_dest;
#endif
addr.addr = *ip_dest_addr;
if(pnetif->ip_addr.addr == 0)
return 1;
if(ip_addr_ismulticast(&addr) || ip_addr_isbroadcast(&addr,pnetif)){
return 1;
}
//if(ip_addr_netcmp(&(pnetif->ip_addr), &addr, &(pnetif->netmask))) //addr&netmask
// return 1;
if(ip_addr_cmp(&(pnetif->ip_addr),&addr))
return 1;
DBG_TRACE("invalid IP: %d.%d.%d.%d ",ip_dest[0],ip_dest[1],ip_dest[2],ip_dest[3]);
#endif
#ifdef CONFIG_DONT_CARE_TP
if(pnetif->flags & NETIF_FLAG_IPSWITCH)
return 1;
else
#endif
return 0;
#endif
}
#if DEVICE_EMAC
#else
int netif_get_idx(struct netif *pnetif)
{
#if (CONFIG_LWIP_LAYER == 1)
int idx = pnetif - xnetif;
switch(idx) {
case 0:
return 0;
case 1:
return 1;
default:
return -1;
}
#else
return -1;
#endif
}
unsigned char *netif_get_hwaddr(int idx_wlan)
{
#if (CONFIG_LWIP_LAYER == 1)
return xnetif[idx_wlan].hwaddr;
#else
return NULL;
#endif
}
#endif
void netif_rx(int idx, unsigned int len)
{
#if (CONFIG_LWIP_LAYER == 1)
#if DEVICE_EMAC
wlan_emac_recv(NULL, len);
#else
ethernetif_recv(&xnetif[idx], len);
#endif
#endif
#if (CONFIG_INIC_EN == 1)
inic_netif_rx(idx, len);
#endif
}
void netif_post_sleep_processing(void)
{
#if (CONFIG_LWIP_LAYER == 1)
#if DEVICE_EMAC
#else
lwip_POST_SLEEP_PROCESSING(); //For FreeRTOS tickless to enable Lwip ARP timer when leaving IPS - Alex Fang
#endif
#endif
}
void netif_pre_sleep_processing(void)
{
#if (CONFIG_LWIP_LAYER == 1)
#if DEVICE_EMAC
#else
lwip_PRE_SLEEP_PROCESSING();
#endif
#endif
}
#ifdef CONFIG_WOWLAN
unsigned char *rltk_wlan_get_ip(int idx){
#if (CONFIG_LWIP_LAYER == 1)
return LwIP_GetIP(&xnetif[idx]);
#else
return NULL;
#endif
}
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/lwip_intf.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __LWIP_INTF_H__
#define __LWIP_INTF_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <wireless.h>
#include <skbuff.h>
struct netif;
//----- ------------------------------------------------------------------
// Ethernet Buffer
//----- ------------------------------------------------------------------
#if DEVICE_EMAC
struct eth_drv_sg {
unsigned int buf;
unsigned int len;
};
#define MAX_ETH_DRV_SG 32
#define MAX_ETH_MSG 1540
extern void wlan_emac_recv(struct netif *netif, int len);
#else
#include "ethernetif.h" // moved to ethernetif.h by jimmy 12/2/2015
#endif
//----- ------------------------------------------------------------------
// Wlan Interface Provided
//----- ------------------------------------------------------------------
unsigned char rltk_wlan_check_isup(int idx);
void rltk_wlan_tx_inc(int idx);
void rltk_wlan_tx_dec(int idx);
struct sk_buff * rltk_wlan_get_recv_skb(int idx);
struct sk_buff * rltk_wlan_alloc_skb(unsigned int total_len);
void rltk_wlan_set_netif_info(int idx_wlan, void * dev, unsigned char * dev_addr);
void rltk_wlan_send_skb(int idx, struct sk_buff *skb); //struct sk_buff as defined above comment line
int rltk_wlan_send(int idx, struct eth_drv_sg *sg_list, int sg_len, int total_len);
void rltk_wlan_recv(int idx, struct eth_drv_sg *sg_list, int sg_len);
unsigned char rltk_wlan_running(unsigned char idx); // interface is up. 0: interface is down
//----- ------------------------------------------------------------------
// Network Interface provided
//----- ------------------------------------------------------------------
int netif_is_valid_IP(int idx,unsigned char * ip_dest);
int netif_get_idx(struct netif *pnetif);
unsigned char *netif_get_hwaddr(int idx_wlan);
void netif_rx(int idx, unsigned int len);
void netif_post_sleep_processing(void);
void netif_pre_sleep_processing(void);
#if (CONFIG_LWIP_LAYER == 1)
#if !DEVICE_EMAC
extern void ethernetif_recv(struct netif *netif, int total_len);
#endif
extern void lwip_PRE_SLEEP_PROCESSING(void);
extern void lwip_POST_SLEEP_PROCESSING(void);
#endif //CONFIG_LWIP_LAYER == 1
#ifdef CONFIG_WOWLAN
extern unsigned char *rltk_wlan_get_ip(int idx);
#endif
#ifdef __cplusplus
}
#endif
#endif //#ifndef __LWIP_INTF_H__

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targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/skbuff.h Normal file
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/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#ifndef __SKBUFF_H__
#define __SKBUFF_H__
struct sk_buff_head {
struct list_head *next, *prev;
unsigned int qlen;
};
#ifdef CONFIG_TRACE_SKB
#define TRACE_SKB_DEPTH 8
#endif
struct sk_buff {
/* These two members must be first. */
struct sk_buff *next; /* Next buffer in list */
struct sk_buff *prev; /* Previous buffer in list */
struct sk_buff_head *list; /* List we are on */
unsigned char *head; /* Head of buffer */
unsigned char *data; /* Data head pointer */
unsigned char *tail; /* Tail pointer */
unsigned char *end; /* End pointer */
void *dev; /* Device we arrived on/are leaving by */
unsigned int len; /* Length of actual data */
#ifdef CONFIG_TRACE_SKB
unsigned int liston[TRACE_SKB_DEPTH]; /* Trace the Lists we went through */
const char *funcname[TRACE_SKB_DEPTH];
unsigned int list_idx; /* Trace the List we are on */
#endif
//#ifdef CONFIG_DONT_CARE_TP
int dyalloc_flag;
//#endif
};
unsigned char *skb_put(struct sk_buff *skb, unsigned int len);
unsigned char *skb_pull(struct sk_buff *skb, unsigned int len);
void skb_reserve(struct sk_buff *skb, unsigned int len);
void skb_assign_buf(struct sk_buff *skb, unsigned char *buf, unsigned int len);
unsigned char *skb_tail_pointer(const struct sk_buff *skb);
void skb_set_tail_pointer(struct sk_buff *skb, const int offset);
unsigned char *skb_end_pointer(const struct sk_buff *skb);
void init_skb_pool(void);
void init_skb_data_pool(void);
#ifndef CONFIG_DONT_CARE_TP
struct sk_buff *dev_alloc_skb(unsigned int length, unsigned int reserve_len);
#else
struct sk_buff *dev_alloc_tx_skb(unsigned int length, unsigned int reserve_len);
struct sk_buff *dev_alloc_rx_skb(unsigned int length, unsigned int reserve_len);
#define dev_alloc_skb dev_alloc_tx_skb
#endif
void kfree_skb(struct sk_buff *skb);
#endif //__SKBUFF_H__

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targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wireless.h Normal file
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targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wlan_intf.h Normal file
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/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#ifndef __WLAN_INTF_H__
#define __WLAN_INTF_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <autoconf.h>
#include <wireless.h>
#include "wifi_constants.h"
#ifndef WLAN0_IDX
#define WLAN0_IDX 0
#endif
#ifndef WLAN1_IDX
#define WLAN1_IDX 1
#endif
#ifndef WLAN_UNDEF
#define WLAN_UNDEF -1
#endif
/***********************************************************/
/*
struct sk_buff {
// These two members must be first.
struct sk_buff *next; // Next buffer in list
struct sk_buff *prev; // Previous buffer in list
struct sk_buff_head *list; // List we are on
unsigned char *head; // Head of buffer
unsigned char *data; // Data head pointer
unsigned char *tail; // Tail pointer
unsigned char *end; //End pointer
struct net_device *dev; //Device we arrived on/are leaving by
unsigned int len; // Length of actual data
};
*/
/************************************************************/
//----- ------------------------------------------------------------------
// Wlan Interface opened for upper layer
//----- ------------------------------------------------------------------
int rltk_wlan_init(int idx_wlan, rtw_mode_t mode); //return 0: success. -1:fail
void rltk_wlan_deinit(void);
void rltk_wlan_deinit_fastly(void);
int rltk_wlan_start(int idx_wlan);
void rltk_wlan_statistic(unsigned char idx);
unsigned char rltk_wlan_running(unsigned char idx); // interface is up. 0: interface is down
int rltk_wlan_control(unsigned long cmd, void *data);
int rltk_wlan_handshake_done(void);
int rltk_wlan_rf_on(void);
int rltk_wlan_rf_off(void);
int rltk_wlan_check_bus(void);
int rltk_wlan_wireless_mode(unsigned char mode);
int rltk_wlan_set_wps_phase(unsigned char is_trigger_wps);
int rtw_ps_enable(int enable);
int rltk_wlan_is_connected_to_ap(void);
#ifdef __cplusplus
}
#endif
#endif //#ifndef __WLAN_INTF_H__

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targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/network/dhcp/dhcps.c Normal file
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/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#include "osdep_service.h"
#include "dhcps.h"
#include "tcpip.h"
//static struct dhcp_server_state dhcp_server_state_machine;
static uint8_t dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
/* recorded the client MAC addr(default sudo mac) */
//static uint8_t dhcps_record_first_client_mac[6] = {0xff,0xff,0xff,0xff,0xff,0xff};
/* recorded transaction ID (default sudo id)*/
static uint8_t dhcp_recorded_xid[4] = {0xff, 0xff, 0xff, 0xff};
/* UDP Protocol Control Block(PCB) */
static struct udp_pcb *dhcps_pcb;
static ip_addr_t dhcps_send_broadcast_address;
static ip_addr_t dhcps_local_address;
static ip_addr_t dhcps_pool_start;
static ip_addr_t dhcps_pool_end;
static ip_addr_t dhcps_local_mask;
static ip_addr_t dhcps_local_gateway;
static ip_addr_t dhcps_network_id;
static ip_addr_t dhcps_subnet_broadcast;
static ip_addr_t dhcps_allocated_client_address;
static int dhcps_addr_pool_set = 0;
static ip_addr_t dhcps_addr_pool_start;
static ip_addr_t dhcps_addr_pool_end;
#if 1
static ip_addr_t dhcps_owned_first_ip;
static ip_addr_t dhcps_owned_last_ip;
static uint8_t dhcps_num_of_available_ips;
#endif
static struct dhcp_msg *dhcp_message_repository;
static int dhcp_message_total_options_lenth;
/* allocated IP range */
static struct table ip_table;
static ip_addr_t client_request_ip;
static uint8_t client_addr[6];
static _mutex dhcps_ip_table_semaphore;
static struct netif * dhcps_netif = NULL;
/**
* @brief latch the specific ip in the ip table.
* @param d the specific index
* @retval None.
*/
#if (!IS_USE_FIXED_IP)
static void mark_ip_in_table(uint8_t d)
{
#if (debug_dhcps)
printf("\r\nmark ip %d\r\n",d);
#endif
rtw_mutex_get_timeout(&dhcps_ip_table_semaphore, RTW_MAX_DELAY);
if (0 < d && d <= 32) {
ip_table.ip_range[0] = MARK_RANGE1_IP_BIT(ip_table, d);
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[0] = 0x%x\r\n",ip_table.ip_range[0]);
#endif
} else if (32 < d && d <= 64) {
ip_table.ip_range[1] = MARK_RANGE2_IP_BIT(ip_table, (d - 32));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[1] = 0x%x\r\n",ip_table.ip_range[1]);
#endif
} else if (64 < d && d <= 96) {
ip_table.ip_range[2] = MARK_RANGE3_IP_BIT(ip_table, (d - 64));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[2] = 0x%x\r\n",ip_table.ip_range[2]);
#endif
} else if (96 < d && d <= 128) {
ip_table.ip_range[3] = MARK_RANGE4_IP_BIT(ip_table, (d - 96));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[3] = 0x%x\r\n",ip_table.ip_range[3]);
#endif
} else if(128 < d && d <= 160) {
ip_table.ip_range[4] = MARK_RANGE5_IP_BIT(ip_table, d);
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[4] = 0x%x\r\n",ip_table.ip_range[4]);
#endif
} else if (160 < d && d <= 192) {
ip_table.ip_range[5] = MARK_RANGE6_IP_BIT(ip_table, (d - 160));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[5] = 0x%x\r\n",ip_table.ip_range[5]);
#endif
} else if (192 < d && d <= 224) {
ip_table.ip_range[6] = MARK_RANGE7_IP_BIT(ip_table, (d - 192));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[6] = 0x%x\r\n",ip_table.ip_range[6]);
#endif
} else if (224 < d) {
ip_table.ip_range[7] = MARK_RANGE8_IP_BIT(ip_table, (d - 224));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[7] = 0x%x\r\n",ip_table.ip_range[7]);
#endif
} else {
printf("\r\n Request ip over the range(1-128) \r\n");
}
rtw_mutex_put(&dhcps_ip_table_semaphore);
}
#ifdef CONFIG_DHCPS_KEPT_CLIENT_INFO
static void save_client_addr(ip_addr_t *client_ip, uint8_t *hwaddr)
{
uint8_t d = (uint8_t)ip4_addr4(client_ip);
rtw_mutex_get_timeout(&dhcps_ip_table_semaphore, RTW_MAX_DELAY);
memcpy(ip_table.client_mac[d], hwaddr, 6);
#if (debug_dhcps)
printf("\r\n%s: ip %d.%d.%d.%d, hwaddr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", __func__,
ip4_addr1(client_ip), ip4_addr2(client_ip), ip4_addr3(client_ip), ip4_addr4(client_ip),
hwaddr[0], hwaddr[1], hwaddr[2], hwaddr[3], hwaddr[4], hwaddr[5]);
#endif
rtw_mutex_put(&dhcps_ip_table_semaphore);
}
static uint8_t check_client_request_ip(ip_addr_t *client_req_ip, uint8_t *hwaddr)
{
int ip_addr4 = 0, i;
#if (debug_dhcps)
printf("\r\n%s: ip %d.%d.%d.%d, hwaddr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", __func__,
ip4_addr1(client_req_ip), ip4_addr2(client_req_ip), ip4_addr3(client_req_ip), ip4_addr4(client_req_ip),
hwaddr[0], hwaddr[1], hwaddr[2], hwaddr[3], hwaddr[4], hwaddr[5]);
#endif
rtw_mutex_get_timeout(&dhcps_ip_table_semaphore, RTW_MAX_DELAY);
for(i=DHCP_POOL_START;i<=DHCP_POOL_END;i++)
{
//printf("client[%d] = %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",i,ip_table.client_mac[i][0],ip_table.client_mac[i][0],ip_table.client_mac[i][1],ip_table.client_mac[i][2],ip_table.client_mac[i][3],ip_table.client_mac[i][4],ip_table.client_mac[i][5]);
if(memcmp(ip_table.client_mac[i], hwaddr, 6) == 0){
if((ip_table.ip_range[i/32]>>(i%32-1)) & 1){
ip_addr4 = i;
break;
}
}
}
rtw_mutex_put(&dhcps_ip_table_semaphore);
if(i == DHCP_POOL_END+1)
ip_addr4 = 0;
Exit:
return ip_addr4;
}
static void dump_client_table()
{
#if 0
int i;
uint8_t *p = NULL;
printf("\r\nip_range: %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x",
ip_table.ip_range[0], ip_table.ip_range[1], ip_table.ip_range[2], ip_table.ip_range[3],
ip_table.ip_range[4], ip_table.ip_range[5], ip_table.ip_range[6], ip_table.ip_range[7]);
for(i=1; i<=DHCPS_MAX_CLIENT_NUM; i++)
{
p = ip_table.client_mac[i];
printf("\r\nClient[%d]: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x",
i, p[0], p[1], p[2], p[3], p[4], p[5]);
}
printf("\r\n");
#endif
}
#endif //CONFIG_DHCPS_KEPT_CLIENT_INFO
#endif
/**
* @brief get one usable ip from the ip table of dhcp server.
* @param: None
* @retval the usable index which represent the ip4_addr(ip) of allocated ip addr.
*/
#if (!IS_USE_FIXED_IP)
static uint8_t search_next_ip(void)
{
uint8_t range_count, offset_count;
uint8_t start, end;
uint8_t max_count;
if(dhcps_addr_pool_set){
start = (uint8_t)ip4_addr4(&dhcps_addr_pool_start);
end = (uint8_t)ip4_addr4(&dhcps_addr_pool_end);
}else{
start = 0;
end = 255;
}
rtw_mutex_get_timeout(&dhcps_ip_table_semaphore, RTW_MAX_DELAY);
for (range_count = 0; range_count < (max_count = 8); range_count++) {
for (offset_count = 0;offset_count < 32; offset_count++) {
if ((((ip_table.ip_range[range_count] >> offset_count) & 0x01) == 0)
&&(((range_count * 32) + (offset_count + 1)) >= start)
&&(((range_count * 32) + (offset_count + 1)) <= end)) {
rtw_mutex_put(&dhcps_ip_table_semaphore);
return ((range_count * 32) + (offset_count + 1));
}
}
}
rtw_mutex_put(&dhcps_ip_table_semaphore);
return 0;
}
#endif
/**
* @brief fill in the option field with message type of a dhcp message.
* @param msg_option_base_addr: the addr be filled start.
* message_type: the type code you want to fill in
* @retval the start addr of the next dhcp option.
*/
static uint8_t *add_msg_type(uint8_t *msg_option_base_addr, uint8_t message_type)
{
uint8_t *option_start;
msg_option_base_addr[0] = DHCP_OPTION_CODE_MSG_TYPE;
msg_option_base_addr[1] = DHCP_OPTION_LENGTH_ONE;
msg_option_base_addr[2] = message_type;
option_start = msg_option_base_addr + 3;
if (DHCP_MESSAGE_TYPE_NAK == message_type)
*option_start++ = DHCP_OPTION_CODE_END;
return option_start;
}
static uint8_t *fill_one_option_content(uint8_t *option_base_addr,
uint8_t option_code, uint8_t option_length, void *copy_info)
{
uint8_t *option_data_base_address;
uint8_t *next_option_start_address = NULL;
option_base_addr[0] = option_code;
option_base_addr[1] = option_length;
option_data_base_address = option_base_addr + 2;
switch (option_length) {
case DHCP_OPTION_LENGTH_FOUR:
memcpy(option_data_base_address, copy_info, DHCP_OPTION_LENGTH_FOUR);
next_option_start_address = option_data_base_address + 4;
break;
case DHCP_OPTION_LENGTH_TWO:
memcpy(option_data_base_address, copy_info, DHCP_OPTION_LENGTH_TWO);
next_option_start_address = option_data_base_address + 2;
break;
case DHCP_OPTION_LENGTH_ONE:
memcpy(option_data_base_address, copy_info, DHCP_OPTION_LENGTH_ONE);
next_option_start_address = option_data_base_address + 1;
break;
}
return next_option_start_address;
}
/**
* @brief fill in the needed content of the dhcp offer message.
* @param optptr the addr which the tail of dhcp magic field.
* @retval the addr represent to add the end of option.
*/
static void add_offer_options(uint8_t *option_start_address)
{
uint8_t *temp_option_addr;
/* add DHCP options 1.
The subnet mask option specifies the client's subnet mask */
temp_option_addr = fill_one_option_content(option_start_address,
DHCP_OPTION_CODE_SUBNET_MASK, DHCP_OPTION_LENGTH_FOUR,
(void *)&dhcps_local_mask);
/* add DHCP options 3 (i.e router(gateway)). The time server option
specifies a list of RFC 868 [6] time servers available to the client. */
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_ROUTER, DHCP_OPTION_LENGTH_FOUR,
(void *)&dhcps_local_address);
/* add DHCP options 6 (i.e DNS).
The option specifies a list of DNS servers available to the client. */
//temp_option_addr = fill_one_option_content(temp_option_addr,
// DHCP_OPTION_CODE_DNS_SERVER, DHCP_OPTION_LENGTH_FOUR,
// (void *)&dhcps_local_address);
/* add DHCP options 51.
This option is used to request a lease time for the IP address. */
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_LEASE_TIME, DHCP_OPTION_LENGTH_FOUR,
(void *)&dhcp_option_lease_time);
/* add DHCP options 54.
The identifier is the IP address of the selected server. */
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_SERVER_ID, DHCP_OPTION_LENGTH_FOUR,
(void *)&dhcps_local_address);
/* add DHCP options 28.
This option specifies the broadcast address in use on client's subnet.*/
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_BROADCAST_ADDRESS, DHCP_OPTION_LENGTH_FOUR,
(void *)&dhcps_subnet_broadcast);
/* add DHCP options 26.
This option specifies the Maximum transmission unit to use */
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_INTERFACE_MTU, DHCP_OPTION_LENGTH_TWO,
(void *) &dhcp_option_interface_mtu);//dhcp_option_interface_mtu_576);
/* add DHCP options 31.
This option specifies whether or not the client should solicit routers */
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_PERFORM_ROUTER_DISCOVERY, DHCP_OPTION_LENGTH_ONE,
NULL);
*temp_option_addr++ = DHCP_OPTION_CODE_END;
}
/**
* @brief fill in common content of a dhcp message.
* @param m the pointer which point to the dhcp message store in.
* @retval None.
*/
static void dhcps_initialize_message(struct dhcp_msg *dhcp_message_repository)
{
dhcp_message_repository->op = DHCP_MESSAGE_OP_REPLY;
dhcp_message_repository->htype = DHCP_MESSAGE_HTYPE;
dhcp_message_repository->hlen = DHCP_MESSAGE_HLEN;
dhcp_message_repository->hops = 0;
memcpy((char *)dhcp_recorded_xid, (char *) dhcp_message_repository->xid,
sizeof(dhcp_message_repository->xid));
dhcp_message_repository->secs = 0;
dhcp_message_repository->flags = htons(BOOTP_BROADCAST);
memcpy((char *)dhcp_message_repository->yiaddr,
(char *)&dhcps_allocated_client_address,
sizeof(dhcp_message_repository->yiaddr));
memset((char *)dhcp_message_repository->ciaddr, 0,
sizeof(dhcp_message_repository->ciaddr));
memset((char *)dhcp_message_repository->siaddr, 0,
sizeof(dhcp_message_repository->siaddr));
memset((char *)dhcp_message_repository->giaddr, 0,
sizeof(dhcp_message_repository->giaddr));
memset((char *)dhcp_message_repository->sname, 0,
sizeof(dhcp_message_repository->sname));
memset((char *)dhcp_message_repository->file, 0,
sizeof(dhcp_message_repository->file));
memset((char *)dhcp_message_repository->options, 0,
dhcp_message_total_options_lenth);
memcpy((char *)dhcp_message_repository->options, (char *)dhcp_magic_cookie,
sizeof(dhcp_magic_cookie));
}
/**
* @brief init and fill in the needed content of dhcp offer message.
* @param packet_buffer packet buffer for UDP.
* @retval None.
*/
static void dhcps_send_offer(struct pbuf *packet_buffer)
{
uint8_t temp_ip = 0;
dhcp_message_repository = (struct dhcp_msg *)packet_buffer->payload;
#if (!IS_USE_FIXED_IP)
temp_ip = check_client_request_ip(&client_request_ip, client_addr);
/* create new client ip */
if(temp_ip == 0)
temp_ip = search_next_ip();
#if (debug_dhcps)
printf("\r\n temp_ip = %d",temp_ip);
#endif
if (temp_ip == 0) {
#if 0
memset(&ip_table, 0, sizeof(struct table));
mark_ip_in_table((uint8_t)ip4_addr4(&dhcps_local_address));
printf("\r\n reset ip table!!\r\n");
#endif
printf("\r\n No useable ip!!!!\r\n");
}
printf("\n\r[%d]DHCP assign ip = %d.%d.%d.%d\n", rtw_get_current_time(), ip4_addr1(&dhcps_network_id),ip4_addr2(&dhcps_network_id),ip4_addr3(&dhcps_network_id),temp_ip);
IP4_ADDR(&dhcps_allocated_client_address, (ip4_addr1(&dhcps_network_id)),
ip4_addr2(&dhcps_network_id), ip4_addr3(&dhcps_network_id), temp_ip);
#endif
dhcps_initialize_message(dhcp_message_repository);
add_offer_options(add_msg_type(&dhcp_message_repository->options[4],
DHCP_MESSAGE_TYPE_OFFER));
udp_sendto_if(dhcps_pcb, packet_buffer,
&dhcps_send_broadcast_address, DHCP_CLIENT_PORT, dhcps_netif);
}
/**
* @brief init and fill in the needed content of dhcp nak message.
* @param packet buffer packet buffer for UDP.
* @retval None.
*/
static void dhcps_send_nak(struct pbuf *packet_buffer)
{
dhcp_message_repository = (struct dhcp_msg *)packet_buffer->payload;
dhcps_initialize_message(dhcp_message_repository);
add_msg_type(&dhcp_message_repository->options[4], DHCP_MESSAGE_TYPE_NAK);
udp_sendto_if(dhcps_pcb, packet_buffer,
&dhcps_send_broadcast_address, DHCP_CLIENT_PORT, dhcps_netif);
}
/**
* @brief init and fill in the needed content of dhcp ack message.
* @param packet buffer packet buffer for UDP.
* @retval None.
*/
static void dhcps_send_ack(struct pbuf *packet_buffer)
{
dhcp_message_repository = (struct dhcp_msg *)packet_buffer->payload;
dhcps_initialize_message(dhcp_message_repository);
add_offer_options(add_msg_type(&dhcp_message_repository->options[4],
DHCP_MESSAGE_TYPE_ACK));
udp_sendto_if(dhcps_pcb, packet_buffer,
&dhcps_send_broadcast_address, DHCP_CLIENT_PORT, dhcps_netif);
}
/**
* @brief according by the input message type to reflect the correspond state.
* @param option_message_type the input server state
* @retval the server state which already transfer to.
*/
uint8_t dhcps_handle_state_machine_change(uint8_t option_message_type)
{
switch (option_message_type) {
case DHCP_MESSAGE_TYPE_DECLINE:
#if (debug_dhcps)
printf("\r\nget message DHCP_MESSAGE_TYPE_DECLINE\n");
#endif
dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
break;
case DHCP_MESSAGE_TYPE_DISCOVER:
#if (debug_dhcps)
printf("\r\nget message DHCP_MESSAGE_TYPE_DISCOVER\n");
#endif
if (dhcp_server_state_machine == DHCP_SERVER_STATE_IDLE) {
dhcp_server_state_machine = DHCP_SERVER_STATE_OFFER;
}
break;
case DHCP_MESSAGE_TYPE_REQUEST:
#if (debug_dhcps)
printf("\r\n[%d]get message DHCP_MESSAGE_TYPE_REQUEST\n", rtw_get_current_time());
#endif
#if (!IS_USE_FIXED_IP)
#if (debug_dhcps)
printf("\r\ndhcp_server_state_machine=%d", dhcp_server_state_machine);
printf("\r\ndhcps_allocated_client_address=%d.%d.%d.%d",
ip4_addr1(&dhcps_allocated_client_address),
ip4_addr2(&dhcps_allocated_client_address),
ip4_addr3(&dhcps_allocated_client_address),
ip4_addr4(&dhcps_allocated_client_address));
printf("\r\nclient_request_ip=%d.%d.%d.%d\n",
ip4_addr1(&client_request_ip),
ip4_addr2(&client_request_ip),
ip4_addr3(&client_request_ip),
ip4_addr4(&client_request_ip));
#endif
if (dhcp_server_state_machine == DHCP_SERVER_STATE_OFFER) {
if (ip4_addr4(&dhcps_allocated_client_address) != 0) {
if (memcmp((void *)&dhcps_allocated_client_address, (void *)&client_request_ip, 4) == 0) {
dhcp_server_state_machine = DHCP_SERVER_STATE_ACK;
} else {
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
}
} else {
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
}
} else if(dhcp_server_state_machine == DHCP_SERVER_STATE_IDLE){
uint8_t ip_addr4 = check_client_request_ip(&client_request_ip, client_addr);
if(ip_addr4 > 0){
IP4_ADDR(&dhcps_allocated_client_address, (ip4_addr1(&dhcps_network_id)),
ip4_addr2(&dhcps_network_id), ip4_addr3(&dhcps_network_id), ip_addr4);
dhcp_server_state_machine = DHCP_SERVER_STATE_ACK;
}else{
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
}
} else {
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
}
#else
if (!(dhcp_server_state_machine == DHCP_SERVER_STATE_ACK ||
dhcp_server_state_machine == DHCP_SERVER_STATE_NAK)) {
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
}
#endif
break;
case DHCP_MESSAGE_TYPE_RELEASE:
printf("get message DHCP_MESSAGE_TYPE_RELEASE\n");
dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
break;
}
return dhcp_server_state_machine;
}
/**
* @brief parse the dhcp message option part.
* @param optptr: the addr of the first option field.
* len: the total length of all option fields.
* @retval dhcp server state.
*/
static uint8_t dhcps_handle_msg_options(uint8_t *option_start, int16_t total_option_length)
{
int16_t option_message_type = 0;
uint8_t *option_end = option_start + total_option_length;
//dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
/* begin process the dhcp option info */
while (option_start < option_end) {
switch ((uint8_t)*option_start) {
case DHCP_OPTION_CODE_MSG_TYPE:
option_message_type = *(option_start + 2); // 2 => code(1)+lenth(1)
break;
case DHCP_OPTION_CODE_REQUEST_IP_ADDRESS :
#if IS_USE_FIXED_IP
if (memcmp((char *)&dhcps_allocated_client_address,
(char *)option_start + 2, 4) == 0)
dhcp_server_state_machine = DHCP_SERVER_STATE_ACK;
else
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
#else
memcpy((char *)&client_request_ip, (char *)option_start + 2, 4);
#endif
break;
}
// calculate the options offset to get next option's base addr
option_start += option_start[1] + 2; // optptr[1]: length value + (code(1)+ Len(1))
}
return dhcps_handle_state_machine_change(option_message_type);
}
/**
* @brief get message from buffer then check whether it is dhcp related or not.
* if yes , parse it more to undersatnd the client's request.
* @param same as recv callback function definition
* @retval if message is dhcp related then return dhcp server state,
* otherwise return 0
*/
static uint8_t dhcps_check_msg_and_handle_options(struct pbuf *packet_buffer)
{
int dhcp_message_option_offset;
dhcp_message_repository = (struct dhcp_msg *)packet_buffer->payload;
dhcp_message_option_offset = ((int)dhcp_message_repository->options
- (int)packet_buffer->payload);
dhcp_message_total_options_lenth = (packet_buffer->len
- dhcp_message_option_offset);
memcpy(client_addr, dhcp_message_repository->chaddr, 6);
/* check the magic number,if correct parse the content of options */
if (memcmp((char *)dhcp_message_repository->options,
(char *)dhcp_magic_cookie, sizeof(dhcp_magic_cookie)) == 0) {
return dhcps_handle_msg_options(&dhcp_message_repository->options[4],
(dhcp_message_total_options_lenth - 4));
}
return 0;
}
/**
* @brief handle imcoming dhcp message and response message to client
* @param same as recv callback function definition
* @retval None
*/
static void dhcps_receive_udp_packet_handler(void *arg, struct udp_pcb *udp_pcb,
struct pbuf *udp_packet_buffer, ip_addr_t *sender_addr, uint16_t sender_port)
{
int16_t total_length_of_packet_buffer;
struct pbuf *merged_packet_buffer = NULL;
dhcp_message_repository = (struct dhcp_msg *)udp_packet_buffer->payload;
if (udp_packet_buffer == NULL) {
printf("\n\r Error!!!! System doesn't allocate any buffer \n\r");
return;
}
if (sender_port == DHCP_CLIENT_PORT) {
total_length_of_packet_buffer = udp_packet_buffer->tot_len;
if (udp_packet_buffer->next != NULL) {
merged_packet_buffer = pbuf_coalesce(udp_packet_buffer,
PBUF_TRANSPORT);
if (merged_packet_buffer->tot_len !=
total_length_of_packet_buffer) {
pbuf_free(udp_packet_buffer);
return;
}
}
switch (dhcps_check_msg_and_handle_options(udp_packet_buffer)) {
case DHCP_SERVER_STATE_OFFER:
#if (debug_dhcps)
printf("%s DHCP_SERVER_STATE_OFFER\n",__func__);
#endif
dhcps_send_offer(udp_packet_buffer);
break;
case DHCP_SERVER_STATE_ACK:
#if (debug_dhcps)
printf("%s DHCP_SERVER_STATE_ACK\n",__func__);
#endif
dhcps_send_ack(udp_packet_buffer);
#if (!IS_USE_FIXED_IP)
mark_ip_in_table((uint8_t)ip4_addr4(&dhcps_allocated_client_address));
#ifdef CONFIG_DHCPS_KEPT_CLIENT_INFO
save_client_addr(&dhcps_allocated_client_address, client_addr);
memset(&client_request_ip, 0, sizeof(client_request_ip));
memset(&client_addr, 0, sizeof(client_addr));
memset(&dhcps_allocated_client_address, 0, sizeof(dhcps_allocated_client_address));
#if (debug_dhcps)
dump_client_table();
#endif
#endif
#endif
dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
break;
case DHCP_SERVER_STATE_NAK:
#if (debug_dhcps)
printf("%s DHCP_SERVER_STATE_NAK\n",__func__);
#endif
dhcps_send_nak(udp_packet_buffer);
dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
break;
case DHCP_OPTION_CODE_END:
#if (debug_dhcps)
printf("%s DHCP_OPTION_CODE_END\n",__func__);
#endif
break;
}
}
/* free the UDP connection, so we can accept new clients */
udp_disconnect(udp_pcb);
/* Free the packet buffer */
if (merged_packet_buffer != NULL)
pbuf_free(merged_packet_buffer);
else
pbuf_free(udp_packet_buffer);
}
void dhcps_set_addr_pool(int addr_pool_set, ip_addr_t * addr_pool_start, ip_addr_t *addr_pool_end)
{
//uint8_t *ip;
if(addr_pool_set){
dhcps_addr_pool_set = 1;
memcpy(&dhcps_addr_pool_start, addr_pool_start,
sizeof(ip_addr_t));
//ip = &dhcps_addr_pool_start;
//ip[3] = 100;
memcpy(&dhcps_addr_pool_end, addr_pool_end,
sizeof(ip_addr_t));
//ip = &dhcps_addr_pool_end;
//ip[3] = 200;
}else{
dhcps_addr_pool_set = 0;
}
}
/**
* @brief Initialize dhcp server.
* @param None.
* @retval None.
* Note, for now,we assume the server latch ip 192.168.1.1 and support dynamic
* or fixed IP allocation.
*/
void dhcps_init(struct netif * pnetif)
{
uint8_t *ip;
// printf("dhcps_init,wlan:%c\n\r",pnetif->name[1]);
#ifdef CONFIG_DHCPS_KEPT_CLIENT_INFO
memset(&ip_table, 0, sizeof(struct table));
// int i = 0;
// for(i=0; i< DHCPS_MAX_CLIENT_NUM+2; i++)
// memset(ip_table.client_mac[i], 0, 6);
// dump_client_table();
#endif
dhcps_netif = pnetif;
if (dhcps_pcb != NULL) {
udp_remove(dhcps_pcb);
dhcps_pcb = NULL;
}
dhcps_pcb = udp_new();
if (dhcps_pcb == NULL) {
printf("\n\r Error!!!upd_new error \n\r");
return;
}
IP4_ADDR(&dhcps_send_broadcast_address, 255, 255, 255, 255);
/* get net info from net interface */
memcpy(&dhcps_local_address, &pnetif->ip_addr,
sizeof(ip_addr_t));
memcpy(&dhcps_local_mask, &pnetif->netmask,
sizeof(ip_addr_t));
memcpy(&dhcps_local_gateway, &pnetif->gw,
sizeof(ip_addr_t));
/* calculate the usable network ip range */
dhcps_network_id.addr = ((pnetif->ip_addr.addr) &
(pnetif->netmask.addr));
dhcps_subnet_broadcast.addr = ((dhcps_network_id.addr |
~(pnetif->netmask.addr)));
#if 1
dhcps_owned_first_ip.addr = htonl((ntohl(dhcps_network_id.addr) + 1));
dhcps_owned_last_ip.addr = htonl(ntohl(dhcps_subnet_broadcast.addr) - 1);
dhcps_num_of_available_ips = ((ntohl(dhcps_owned_last_ip.addr)
- ntohl(dhcps_owned_first_ip.addr)) + 1);
#endif
#if IS_USE_FIXED_IP
IP4_ADDR(&dhcps_allocated_client_address, ip4_addr1(&dhcps_local_address)
, ip4_addr2(&dhcps_local_address), ip4_addr3(&dhcps_local_address),
(ip4_addr4(&dhcps_local_address)) + 1 );
#else
if (dhcps_ip_table_semaphore != NULL) {
rtw_mutex_free(&dhcps_ip_table_semaphore);
dhcps_ip_table_semaphore = NULL;
}
rtw_mutex_init(&dhcps_ip_table_semaphore);
//dhcps_ip_table = (struct ip_table *)(pvPortMalloc(sizeof(struct ip_table)));
memset(&ip_table, 0, sizeof(struct table));
mark_ip_in_table((uint8_t)ip4_addr4(&dhcps_local_address));
mark_ip_in_table((uint8_t)ip4_addr4(&dhcps_local_gateway));
#if 0
for (i = 1; i < ip4_addr4(&dhcps_local_address); i++) {
mark_ip_in_table(i);
}
#endif
#endif
memcpy(&dhcps_pool_start,&dhcps_local_address,sizeof(ip_addr_t));
ip = (uint8_t *)&dhcps_pool_start;
ip[3] = DHCP_POOL_START;
memcpy(&dhcps_pool_end,&dhcps_local_address,sizeof(ip_addr_t));
ip = (uint8_t *)&dhcps_pool_end;
ip[3] = DHCP_POOL_END;
dhcps_set_addr_pool(1,&dhcps_pool_start,&dhcps_pool_end);
udp_bind(dhcps_pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
udp_recv(dhcps_pcb, (udp_recv_fn)dhcps_receive_udp_packet_handler, NULL);
}
void dhcps_deinit(void)
{
if (dhcps_pcb != NULL) {
udp_remove(dhcps_pcb);
dhcps_pcb = NULL;
}
if (dhcps_ip_table_semaphore != NULL) {
rtw_mutex_free(&dhcps_ip_table_semaphore);
dhcps_ip_table_semaphore = NULL;
}
}

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/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef __DHCPS_H__
#define __DHCPS_H__
#include "lwip/arch.h"
#include "lwip/netif.h"
#include "lwip/udp.h"
#include "lwip/stats.h"
#include "lwip/sys.h"
#include "lwip/ip_addr.h"
#include <platform/platform_stdlib.h>
#define CONFIG_DHCPS_KEPT_CLIENT_INFO
#define DHCP_POOL_START 100
#define DHCP_POOL_END 200
#define DHCPS_MAX_CLIENT_NUM (DHCP_POOL_END-DHCP_POOL_START+1)
#define IS_USE_FIXED_IP 0
#define debug_dhcps 0
/* dhcp server states */
#define DHCP_SERVER_STATE_OFFER (1)
#define DHCP_SERVER_STATE_DECLINE (2)
#define DHCP_SERVER_STATE_ACK (3)
#define DHCP_SERVER_STATE_NAK (4)
#define DHCP_SERVER_STATE_IDLE (5)
#define BOOTP_BROADCAST (0x8000)
#define DHCP_MESSAGE_OP_REQUEST (1)
#define DHCP_MESSAGE_OP_REPLY (2)
#define DHCP_MESSAGE_HTYPE (1)
#define DHCP_MESSAGE_HLEN (6)
#define DHCP_SERVER_PORT (67)
#define DHCP_CLIENT_PORT (68)
#define DHCP_MESSAGE_TYPE_DISCOVER (1)
#define DHCP_MESSAGE_TYPE_OFFER (2)
#define DHCP_MESSAGE_TYPE_REQUEST (3)
#define DHCP_MESSAGE_TYPE_DECLINE (4)
#define DHCP_MESSAGE_TYPE_ACK (5)
#define DHCP_MESSAGE_TYPE_NAK (6)
#define DHCP_MESSAGE_TYPE_RELEASE (7)
#define DHCP_OPTION_LENGTH_ONE (1)
#define DHCP_OPTION_LENGTH_TWO (2)
#define DHCP_OPTION_LENGTH_THREE (3)
#define DHCP_OPTION_LENGTH_FOUR (4)
#define DHCP_OPTION_CODE_SUBNET_MASK (1)
#define DHCP_OPTION_CODE_ROUTER (3)
#define DHCP_OPTION_CODE_DNS_SERVER (6)
#define DHCP_OPTION_CODE_INTERFACE_MTU (26)
#define DHCP_OPTION_CODE_BROADCAST_ADDRESS (28)
#define DHCP_OPTION_CODE_PERFORM_ROUTER_DISCOVERY (31)
#define DHCP_OPTION_CODE_REQUEST_IP_ADDRESS (50)
#define DHCP_OPTION_CODE_LEASE_TIME (51)
#define DHCP_OPTION_CODE_MSG_TYPE (53)
#define DHCP_OPTION_CODE_SERVER_ID (54)
#define DHCP_OPTION_CODE_REQ_LIST (55)
#define DHCP_OPTION_CODE_END (255)
#define IP_FREE_TO_USE (1)
#define IP_ALREADY_IN_USE (0)
#define HW_ADDRESS_LENGTH (6)
/* Reference by RFC 2131 */
struct dhcp_msg {
uint8_t op; /* Message op code/message type. 1 = BOOTREQUEST, 2 = BOOTREPLY */
uint8_t htype; /* Hardware address type */
uint8_t hlen; /* Hardware address length */
uint8_t hops; /* Client sets to zero, optionally used by relay agents
when booting via a relay agent */
uint8_t xid[4]; /* Transaction ID, a random number chosen by the client,
used by the client and server to associate messages and
responses between a client and a server */
uint16_t secs; /* Filled in by client, seconds elapsed since client began address
acquisition or renewal process.*/
uint16_t flags; /* bit 0: Broadcast flag, bit 1~15:MBZ must 0*/
uint8_t ciaddr[4]; /* Client IP address; only filled in if client is in BOUND,
RENEW or REBINDING state and can respond to ARP requests. */
uint8_t yiaddr[4]; /* 'your' (client) IP address */
uint8_t siaddr[4]; /* IP address of next server to use in bootstrap;
returned in DHCPOFFER, DHCPACK by server. */
uint8_t giaddr[4]; /* Relay agent IP address, used in booting via a relay agent.*/
uint8_t chaddr[16]; /* Client hardware address */
uint8_t sname[64]; /* Optional server host name, null terminated string.*/
uint8_t file[128]; /* Boot file name, null terminated string; "generic" name or
null in DHCPDISCOVER, fully qualified directory-path name in DHCPOFFER.*/
uint8_t options[312]; /* Optional parameters field. reference the RFC 2132 */
};
/* use this to check whether the message is dhcp related or not */
static const uint8_t dhcp_magic_cookie[4] = {99, 130, 83, 99};
static const uint8_t dhcp_option_lease_time[] = {0x00, 0x00, 0x1c, 0x20}; //1 day
//static const uint8_t dhcp_option_lease_time[] = {0x00, 0x00, 0x0e, 0x10}; // one hour
//static const uint8_t dhcp_option_interface_mtu_576[] = {0x02, 0x40};
static const uint8_t dhcp_option_interface_mtu[] = {0x05, 0xDC};
struct table {
uint32_t ip_range[8];
#ifdef CONFIG_DHCPS_KEPT_CLIENT_INFO
uint8_t client_mac[256][6];
#endif
};
struct address_pool{
uint32_t start;
uint32_t end;
};
/* 01~32 */
#define MARK_RANGE1_IP_BIT(table, ip) ((table.ip_range[0]) | (1 << ((ip) - 1)))
/* 33~64 */
#define MARK_RANGE2_IP_BIT(table, ip) ((table.ip_range[1]) | (1 << ((ip) - 1)))
/* 65~96 */
#define MARK_RANGE3_IP_BIT(table, ip) ((table.ip_range[2]) | (1 << ((ip) - 1)))
/* 97~128 */
#define MARK_RANGE4_IP_BIT(table, ip) ((table.ip_range[3]) | (1 << ((ip) - 1)))
/* 129~160 */
#define MARK_RANGE5_IP_BIT(table, ip) ((table.ip_range[4]) | (1 << ((ip) - 1)))
/* 161~192 */
#define MARK_RANGE6_IP_BIT(table, ip) ((table.ip_range[5]) | (1 << ((ip) - 1)))
/* 193~224 */
#define MARK_RANGE7_IP_BIT(table, ip) ((table.ip_range[6]) | (1 << ((ip) - 1)))
/* 225~255 */
#define MARK_RANGE8_IP_BIT(table, ip) ((table.ip_range[7]) | (1 << ((ip) - 1)))
/* expose API */
void dhcps_set_addr_pool(int addr_pool_set, ip_addr_t * addr_pool_start, ip_addr_t *addr_pool_end);
void dhcps_init(struct netif * pnetif);
void dhcps_deinit(void);
extern struct netif *netif_default;
#endif /*__DHCPS_H__*/

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "osdep_service.h"
#include "device_lock.h"
//------------------------------------------------------
#define DEVICE_MUTEX_IS_INIT(device) (mutex_init & (1<<device))
#define DEVICE_MUTEX_SET_INIT(device) (mutex_init |= (1<<device))
#define DEVICE_MUTEX_CLR_INIT(device) (mutex_init &= (~(1<<device)))
static u32 mutex_init = 0;
static _mutex device_mutex[RT_DEV_LOCK_MAX];
//======================================================
static void device_mutex_init(RT_DEV_LOCK_E device)
{
if(!DEVICE_MUTEX_IS_INIT(device)){
_lock lock;
_irqL irqL;
rtw_enter_critical(&lock, &irqL);
if(!DEVICE_MUTEX_IS_INIT(device)){
rtw_mutex_init(&device_mutex[device]);
DEVICE_MUTEX_SET_INIT(device);
}
rtw_exit_critical(&lock, &irqL);
}
}
//======================================================
static void device_mutex_free(RT_DEV_LOCK_E device)
{
if(DEVICE_MUTEX_IS_INIT(device)){
_lock lock;
_irqL irqL;
rtw_enter_critical(&lock, &irqL);
if(!DEVICE_MUTEX_IS_INIT(device)){
rtw_mutex_free(&device_mutex[device]);
DEVICE_MUTEX_CLR_INIT(device);
}
rtw_exit_critical(&lock, &irqL);
}
}
//======================================================
void device_mutex_lock(RT_DEV_LOCK_E device)
{
device_mutex_init(device);
while(rtw_mutex_get_timeout(&device_mutex[device], 10000)<0)
printf("device lock timeout: %d\n", device);
}
//======================================================
void device_mutex_unlock(RT_DEV_LOCK_E device)
{
device_mutex_init(device);
rtw_mutex_put(&device_mutex[device]);
}

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _DEVICE_LOCK_H_
#define _DEVICE_LOCK_H_
enum _RT_DEV_LOCK_E
{
RT_DEV_LOCK_EFUSE = 0,
RT_DEV_LOCK_FLASH = 1,
RT_DEV_LOCK_CRYPTO = 2,
RT_DEV_LOCK_MAX = 3
};
typedef uint32_t RT_DEV_LOCK_E;
void device_mutex_lock(RT_DEV_LOCK_E device);
void device_mutex_unlock(RT_DEV_LOCK_E device);
#endif //_DEVICE_LOCK_H_

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __OSDEP_SERVICE_H_
#define __OSDEP_SERVICE_H_
/* OS dep feature enable */
#include <autoconf.h>
#ifdef __cplusplus
extern "C" {
#endif
#define CONFIG_LITTLE_ENDIAN
#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
#define CONFIG_PLATFORM_AMEBA_X
#endif
#if defined(CONFIG_PLATFORM_8195A)
#ifndef CONFIG_USE_TCM_HEAP
#define CONFIG_USE_TCM_HEAP 0 /* USE TCM HEAP */
#endif
#define USE_MUTEX_FOR_SPINLOCK 1
#endif
#if defined(CONFIG_PLATFORM_AMEBA_X)
#define CONFIG_MEM_MONITOR MEM_MONITOR_SIMPLE
#else
#define CONFIG_MEM_MONITOR MEM_MONITOR_LEAK
#endif
/* Define compilor specific symbol */
//
// inline function
//
#if defined ( __ICCARM__ )
#define __inline__ inline
#define __inline inline
#define __inline_definition //In dialect C99, inline means that a function's definition is provided
//only for inlining, and that there is another definition
//(without inline) somewhere else in the program.
//That means that this program is incomplete, because if
//add isn't inlined (for example, when compiling without optimization),
//then main will have an unresolved reference to that other definition.
// Do not inline function is the function body is defined .c file and this
// function will be called somewhere else, otherwise there is compile error
#elif defined ( __CC_ARM )
#define __inline__ __inline //__linine__ is not supported in keil compilor, use __inline instead
#define inline __inline
#define __inline_definition // for dialect C99
#elif defined ( __GNUC__ )
#define __inline__ inline
#define __inline inline
#define __inline_definition inline
#endif
#include <stdio.h>
#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
#include "platform_autoconf.h"
#else //for 8189FM/8189FTV add by frankie_li 20160408
#ifndef SUCCESS
#define SUCCESS 0
#endif
#ifndef FAIL
#define FAIL (-1)
#endif
#ifndef _SUCCESS
#define _SUCCESS 1
#endif
#ifndef _FAIL
#define _FAIL 0
#endif
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE (!FALSE)
#endif
#define _TRUE TRUE
#define _FALSE FALSE
#endif
#if defined( PLATFORM_FREERTOS)
#include "freertos_service.h"
#elif defined( PLATFORM_ECOS)
#include "ecos/ecos_service.h"
#elif defined(PLATFORM_CMSIS_RTOS)
#include "rtx2_service.h"
#endif
#define RTW_MAX_DELAY 0xFFFFFFFF
#define RTW_WAIT_FOREVER 0xFFFFFFFF
/* Definitions returned by xTaskGetSchedulerState(). */
#define OS_SCHEDULER_NOT_STARTED 0
#define OS_SCHEDULER_RUNNING 1
#define OS_SCHEDULER_SUSPENDED 2
struct timer_list {
_timerHandle timer_hdl;
unsigned long data;
void (*function)(void *);
};
typedef thread_return (*thread_func_t)(thread_context context);
typedef void (*TIMER_FUN)(void *context);
typedef int (*event_handler_t)(char *buf, int buf_len, int flags, void *user_data);
#define CONFIG_THREAD_COMM_SEMA
struct task_struct {
const char *task_name;
_thread_hdl_ task; /* I: workqueue thread */
#ifdef CONFIG_THREAD_COMM_SIGNAL
const char *name; /* I: workqueue thread name */
u32 queue_num; /* total signal num */
u32 cur_queue_num; /* cur signal num should < queue_num */
#elif defined(CONFIG_THREAD_COMM_SEMA)
_sema wakeup_sema;
_sema terminate_sema;
// _queue work_queue; //TODO
#endif
u32 blocked;
u32 callback_running;
};
typedef struct {
_xqueue event_queue;
struct task_struct thread;
}rtw_worker_thread_t;
typedef struct
{
event_handler_t function;
char *buf;
int buf_len;
int flags;
void *user_data;
} rtw_event_message_t;
struct worker_timer_entry {
struct list_head list;
_timerHandle timer_hdl;
rtw_event_message_t message;
rtw_worker_thread_t *worker_thread;
u32 timeout;
};
#ifdef CONFIG_THREAD_COMM_SIGNAL
struct work_struct;
typedef void (*work_func_t)(void *context);
struct work_struct {
_list list;
u32 data;
work_func_t func;
void *context;
struct task_struct *used_wq;
};
struct delayed_work {
struct work_struct work;
struct timer_list timer;
};
#endif
#ifdef CONFIG_MEM_MONITOR
//----- ------------------------------------------------------------------
// Memory Monitor
//----- ------------------------------------------------------------------
#define MEM_MONITOR_SIMPLE 0x1
#define MEM_MONITOR_LEAK 0x2
#define MEM_MONITOR_FLAG_WIFI_DRV 0x1
#define MEM_MONITOR_FLAG_WPAS 0x2
#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK
struct mem_entry {
struct list_head list;
int size;
void *ptr;
};
#endif
void init_mem_monitor(_list *pmem_table, int *used_num);
void deinit_mem_monitor(_list *pmem_table, int *used_num);
void add_mem_usage(_list *pmem_table, void *ptr, int size, int *used_num, int flag);
void del_mem_usage(_list *pmem_table, void *ptr, int *used_num, int flag);
int get_mem_usage(_list *pmem_table);
#endif
/*********************************** OSDEP API *****************************************/
u8* _rtw_vmalloc(u32 sz);
u8* _rtw_zvmalloc(u32 sz);
void _rtw_vmfree(u8 *pbuf, u32 sz);
u8* _rtw_zmalloc(u32 sz);
u8* _rtw_malloc(u32 sz);
void _rtw_mfree(u8 *pbuf, u32 sz);
#ifdef CONFIG_MEM_MONITOR
u8* rtw_vmalloc(u32 sz);
u8* rtw_zvmalloc(u32 sz);
void rtw_vmfree(u8 *pbuf, u32 sz);
u8* rtw_zmalloc(u32 sz);
u8* rtw_malloc(u32 sz);
void rtw_mfree(u8 *pbuf, u32 sz);
#else
#define rtw_vmalloc _rtw_vmalloc
#define rtw_zvmalloc _rtw_zvmalloc
#define rtw_vmfree _rtw_vmfree
#define rtw_zmalloc _rtw_zmalloc
#define rtw_malloc _rtw_malloc
#define rtw_mfree _rtw_mfree
#endif
#define rtw_free(buf) rtw_mfree((u8 *)buf, 0)
void* rtw_malloc2d(int h, int w, int size);
void rtw_mfree2d(void *pbuf, int h, int w, int size);
void rtw_memcpy(void* dst, void* src, u32 sz);
int rtw_memcmp(void *dst, void *src, u32 sz);
void rtw_memset(void *pbuf, int c, u32 sz);
void rtw_init_listhead(_list *list);
u32 rtw_is_list_empty(_list *phead);
void rtw_list_insert_head(_list *plist, _list *phead);
void rtw_list_insert_tail(_list *plist, _list *phead);
void rtw_list_delete(_list *plist);
void rtw_init_sema(_sema *sema, int init_val);
void rtw_free_sema(_sema *sema);
void rtw_up_sema(_sema *sema);
void rtw_up_sema_from_isr(_sema *sema);
u32 rtw_down_sema(_sema *sema);
u32 rtw_down_timeout_sema(_sema *sema, u32 timeout);
void rtw_mutex_init(_mutex *pmutex);
void rtw_mutex_free(_mutex *pmutex);
void rtw_mutex_put(_mutex *pmutex);
void rtw_mutex_get(_mutex *pmutex);
int rtw_mutex_get_timeout(_mutex *pmutex, u32 timeout_ms);
void rtw_enter_critical(_lock *plock, _irqL *pirqL);
void rtw_exit_critical(_lock *plock, _irqL *pirqL);
void rtw_enter_critical_from_isr(_lock *plock, _irqL *pirqL);
void rtw_exit_critical_from_isr(_lock *plock, _irqL *pirqL);
void rtw_enter_critical_bh(_lock *plock, _irqL *pirqL);
void rtw_exit_critical_bh(_lock *plock, _irqL *pirqL);
int rtw_enter_critical_mutex(_mutex *pmutex, _irqL *pirqL);
void rtw_exit_critical_mutex(_mutex *pmutex, _irqL *pirqL);
void rtw_spinlock_init(_lock *plock);
void rtw_spinlock_free(_lock *plock);
void rtw_spinlock_init(_lock *plock);
void rtw_spinlock_free(_lock *plock);
void rtw_spin_lock(_lock *plock);
void rtw_spin_unlock(_lock *plock);
void rtw_spinlock_irqsave(_lock *plock, _irqL *irqL);
void rtw_spinunlock_irqsave(_lock *plock, _irqL *irqL);
int rtw_init_xqueue( _xqueue* queue, const char* name, u32 message_size, u32 number_of_messages );
int rtw_push_to_xqueue( _xqueue* queue, void* message, u32 timeout_ms );
int rtw_pop_from_xqueue( _xqueue* queue, void* message, u32 timeout_ms );
int rtw_deinit_xqueue( _xqueue* queue );
void rtw_init_queue(_queue *pqueue);
void rtw_deinit_queue(_queue *pqueue);
u32 rtw_is_queue_empty(_queue *pqueue);
u32 rtw_queue_empty(_queue *pqueue);
u32 rtw_end_of_queue_search(_list *queue, _list *pelement);
_list* rtw_get_queue_head(_queue *queue);
u32 rtw_get_current_time(void);
u32 rtw_systime_to_ms(u32 systime);
u32 rtw_systime_to_sec(u32 systime);
u32 rtw_ms_to_systime(u32 ms);
u32 rtw_sec_to_systime(u32 sec);
s32 rtw_get_passing_time_ms(u32 start);
s32 rtw_get_time_interval_ms(u32 start, u32 end);
void rtw_msleep_os(int ms);
void rtw_usleep_os(int us);
u32 rtw_atoi(u8* s);
void rtw_mdelay_os(int ms);
void rtw_udelay_os(int us);
void rtw_yield_os(void);
//Atomic integer operations
void ATOMIC_SET(ATOMIC_T *v, int i);
int ATOMIC_READ(ATOMIC_T *v);
void ATOMIC_ADD(ATOMIC_T *v, int i);
void ATOMIC_SUB(ATOMIC_T *v, int i);
void ATOMIC_INC(ATOMIC_T *v);
void ATOMIC_DEC(ATOMIC_T *v);
int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i);
int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i);
int ATOMIC_INC_RETURN(ATOMIC_T *v);
int ATOMIC_DEC_RETURN(ATOMIC_T *v);
int ATOMIC_DEC_AND_TEST(ATOMIC_T *v);
u64 rtw_modular64(u64 x, u64 y);
int rtw_get_random_bytes(void* dst, u32 size);
u32 rtw_getFreeHeapSize(void);
void flush_signals_thread(void);
void rtw_acquire_wakelock(void);
void rtw_release_wakelock(void);
void rtw_wakelock_timeout(u32 timeout);
/*********************************** Thread related *****************************************/
int rtw_create_task(struct task_struct *task, const char *name, u32 stack_size, u32 priority, thread_func_t func, void *thctx);
void rtw_delete_task(struct task_struct * task);
void rtw_wakeup_task(struct task_struct *task);
int rtw_create_worker_thread( rtw_worker_thread_t* worker_thread, u8 priority, u32 stack_size, u32 event_queue_size );
int rtw_delete_worker_thread( rtw_worker_thread_t* worker_thread );
#if 0 //TODO
void rtw_init_delayed_work(struct delayed_work *dwork, work_func_t func, const char *name);
void rtw_deinit_delayed_work(struct delayed_work *dwork);
int rtw_queue_delayed_work(struct workqueue_struct *wq, struct delayed_work *dwork, u32 delay, void* context);
BOOLEAN rtw_cancel_delayed_work(struct delayed_work *dwork);
#endif
void rtw_thread_enter(char *name);
void rtw_thread_exit(void);
u8 rtw_get_scheduler_state(void);
#ifdef PLATFORM_LINUX
#define rtw_warn_on(condition) WARN_ON(condition)
#else
#define rtw_warn_on(condition) do {} while (0)
#endif
/*********************************** Timer related *****************************************/
_timerHandle rtw_timerCreate( const signed char *pcTimerName,
osdepTickType xTimerPeriodInTicks,
u32 uxAutoReload,
void * pvTimerID,
TIMER_FUN pxCallbackFunction );
u32 rtw_timerDelete( _timerHandle xTimer,
osdepTickType xBlockTime );
u32 rtw_timerIsTimerActive( _timerHandle xTimer );
u32 rtw_timerStop( _timerHandle xTimer,
osdepTickType xBlockTime );
u32 rtw_timerChangePeriod( _timerHandle xTimer,
osdepTickType xNewPeriod,
osdepTickType xBlockTime );
/*********************************** OSDEP API end *****************************************/
#define LIST_CONTAINOR(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)((char *)&((type *)ptr)->member - (char *)ptr)))
#define time_after(a,b) ((long)(b) - (long)(a) < 0)
#define time_before(a,b) time_after(b,a)
#define time_after_eq(a,b) ((long)(a) - (long)(b) >= 0)
#define time_before_eq(a,b) time_after_eq(b,a)
#define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r))
#define RND4(x) (((x >> 2) + (((x & 3) == 0) ? 0: 1)) << 2)
__inline static u32 _RND4(u32 sz)
{
u32 val;
val = ((sz >> 2) + ((sz & 3) ? 1: 0)) << 2;
return val;
}
__inline static u32 _RND8(u32 sz)
{
u32 val;
val = ((sz >> 3) + ((sz & 7) ? 1: 0)) << 3;
return val;
}
__inline static u32 _RND128(u32 sz)
{
u32 val;
val = ((sz >> 7) + ((sz & 127) ? 1: 0)) << 7;
return val;
}
__inline static u32 _RND256(u32 sz)
{
u32 val;
val = ((sz >> 8) + ((sz & 255) ? 1: 0)) << 8;
return val;
}
__inline static u32 _RND512(u32 sz)
{
u32 val;
val = ((sz >> 9) + ((sz & 511) ? 1: 0)) << 9;
return val;
}
__inline static u32 bitshift(u32 bitmask)
{
u32 i;
for (i = 0; i <= 31; i++)
if (((bitmask>>i) & 0x1) == 1) break;
return i;
}
/* Macros for handling unaligned memory accesses */
#define RTW_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1]))
#define RTW_PUT_BE16(a, val) \
do { \
(a)[0] = ((u16) (val)) >> 8; \
(a)[1] = ((u16) (val)) & 0xff; \
} while (0)
#define RTW_GET_LE16(a) ((u16) (((a)[1] << 8) | (a)[0]))
#define RTW_PUT_LE16(a, val) \
do { \
(a)[1] = ((u16) (val)) >> 8; \
(a)[0] = ((u16) (val)) & 0xff; \
} while (0)
#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \
((u32) (a)[2]))
#define RTW_PUT_BE24(a, val) \
do { \
(a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff); \
(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \
(a)[2] = (u8) (((u32) (val)) & 0xff); \
} while (0)
#define RTW_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \
(((u32) (a)[2]) << 8) | ((u32) (a)[3]))
#define RTW_PUT_BE32(a, val) \
do { \
(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \
(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \
(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \
(a)[3] = (u8) (((u32) (val)) & 0xff); \
} while (0)
#define RTW_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \
(((u32) (a)[1]) << 8) | ((u32) (a)[0]))
#define RTW_PUT_LE32(a, val) \
do { \
(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \
(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \
(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \
(a)[0] = (u8) (((u32) (val)) & 0xff); \
} while (0)
#define RTW_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \
(((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \
(((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \
(((u64) (a)[6]) << 8) | ((u64) (a)[7]))
#define RTW_PUT_BE64(a, val) \
do { \
(a)[0] = (u8) (((u64) (val)) >> 56); \
(a)[1] = (u8) (((u64) (val)) >> 48); \
(a)[2] = (u8) (((u64) (val)) >> 40); \
(a)[3] = (u8) (((u64) (val)) >> 32); \
(a)[4] = (u8) (((u64) (val)) >> 24); \
(a)[5] = (u8) (((u64) (val)) >> 16); \
(a)[6] = (u8) (((u64) (val)) >> 8); \
(a)[7] = (u8) (((u64) (val)) & 0xff); \
} while (0)
#define RTW_GET_LE64(a) ((((u64) (a)[7]) << 56) | (((u64) (a)[6]) << 48) | \
(((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \
(((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \
(((u64) (a)[1]) << 8) | ((u64) (a)[0]))
struct osdep_service_ops {
u8* (*rtw_vmalloc)(u32 sz);
u8* (*rtw_zvmalloc)(u32 sz);
void (*rtw_vmfree)(u8 *pbuf, u32 sz);
u8* (*rtw_malloc)(u32 sz);
u8* (*rtw_zmalloc)(u32 sz);
void (*rtw_mfree)(u8 *pbuf, u32 sz);
void (*rtw_memcpy)(void* dst, void* src, u32 sz);
int (*rtw_memcmp)(void *dst, void *src, u32 sz);
void (*rtw_memset)(void *pbuf, int c, u32 sz);
void (*rtw_init_sema)(_sema *sema, int init_val);
void (*rtw_free_sema)(_sema *sema);
void (*rtw_up_sema)(_sema *sema);
void (*rtw_up_sema_from_isr)(_sema *sema);
u32 (*rtw_down_timeout_sema)(_sema *sema, u32 timeout);
void (*rtw_mutex_init)(_mutex *pmutex);
void (*rtw_mutex_free)(_mutex *pmutex);
void (*rtw_mutex_get)(_mutex *pmutex);
int (*rtw_mutex_get_timeout)(_mutex *pmutex, u32 timeout_ms);
void (*rtw_mutex_put)(_mutex *pmutex);
void (*rtw_enter_critical)(_lock *plock, _irqL *pirqL);
void (*rtw_exit_critical)(_lock *plock, _irqL *pirqL);
void (*rtw_enter_critical_from_isr)(_lock *plock, _irqL *pirqL);
void (*rtw_exit_critical_from_isr)(_lock *plock, _irqL *pirqL);
void (*rtw_enter_critical_bh)(_lock *plock, _irqL *pirqL);
void (*rtw_exit_critical_bh)(_lock *plock, _irqL *pirqL);
int (*rtw_enter_critical_mutex)(_mutex *pmutex, _irqL *pirqL);
void (*rtw_exit_critical_mutex)(_mutex *pmutex, _irqL *pirqL);
void (*rtw_spinlock_init)(_lock *plock);
void (*rtw_spinlock_free)(_lock *plock);
void (*rtw_spin_lock)(_lock *plock);
void (*rtw_spin_unlock)(_lock *plock);
void (*rtw_spinlock_irqsave)(_lock *plock, _irqL *irqL);
void (*rtw_spinunlock_irqsave)(_lock *plock, _irqL *irqL);
int (*rtw_init_xqueue)( _xqueue* queue, const char* name, u32 message_size, u32 number_of_messages );
int (*rtw_push_to_xqueue)( _xqueue* queue, void* message, u32 timeout_ms );
int (*rtw_pop_from_xqueue)( _xqueue* queue, void* message, u32 timeout_ms );
int (*rtw_deinit_xqueue)( _xqueue* queue );
u32 (*rtw_get_current_time)(void);
u32 (*rtw_systime_to_ms)(u32 systime);
u32 (*rtw_systime_to_sec)(u32 systime);
u32 (*rtw_ms_to_systime)(u32 ms);
u32 (*rtw_sec_to_systime)(u32 sec);
void (*rtw_msleep_os)(int ms);
void (*rtw_usleep_os)(int us);
void (*rtw_mdelay_os)(int ms);
void (*rtw_udelay_os)(int us);
void (*rtw_yield_os)(void);
void (*ATOMIC_SET)(ATOMIC_T *v, int i);
int (*ATOMIC_READ)(ATOMIC_T *v);
void (*ATOMIC_ADD)(ATOMIC_T *v, int i);
void (*ATOMIC_SUB)(ATOMIC_T *v, int i);
void (*ATOMIC_INC)(ATOMIC_T *v);
void (*ATOMIC_DEC)(ATOMIC_T *v);
int (*ATOMIC_ADD_RETURN)(ATOMIC_T *v, int i);
int (*ATOMIC_SUB_RETURN)(ATOMIC_T *v, int i);
int (*ATOMIC_INC_RETURN)(ATOMIC_T *v);
int (*ATOMIC_DEC_RETURN)(ATOMIC_T *v);
u64 (*rtw_modular64)(u64 x, u64 y);
int (*rtw_get_random_bytes)(void* dst, u32 size);
u32 (*rtw_getFreeHeapSize)(void);
int (*rtw_create_task)(struct task_struct *task, const char *name, u32 stack_size, u32 priority, thread_func_t func, void *thctx);
void (*rtw_delete_task)(struct task_struct *task);
void (*rtw_wakeup_task)(struct task_struct *task);
#if 0 //TODO
void (*rtw_init_delayed_work)(struct delayed_work *dwork, work_func_t func, const char *name);
void (*rtw_deinit_delayed_work)(struct delayed_work *dwork);
int (*rtw_queue_delayed_work)(struct workqueue_struct *wq, struct delayed_work *dwork, unsigned long delay, void* context);
BOOLEAN (*rtw_cancel_delayed_work)(struct delayed_work *dwork);
#endif
void (*rtw_thread_enter)(char *name);
void (*rtw_thread_exit)(void);
_timerHandle (*rtw_timerCreate)( const signed char *pcTimerName,
osdepTickType xTimerPeriodInTicks,
u32 uxAutoReload,
void * pvTimerID,
TIMER_FUN pxCallbackFunction );
u32 (*rtw_timerDelete)( _timerHandle xTimer,
osdepTickType xBlockTime );
u32 (*rtw_timerIsTimerActive)( _timerHandle xTimer );
u32 (*rtw_timerStop)( _timerHandle xTimer,
osdepTickType xBlockTime );
u32 (*rtw_timerChangePeriod)( _timerHandle xTimer,
osdepTickType xNewPeriod,
osdepTickType xBlockTime );
void (*rtw_acquire_wakelock)(void);
void (*rtw_release_wakelock)(void);
void (*rtw_wakelock_timeout)(u32 timeoutMs);
u8 (*rtw_get_scheduler_state)(void);
};
/*********************************** OSDEP API end *****************************************/
#ifdef __cplusplus
}
#endif
#endif //#ifndef __OSDEP_SERVICE_H_

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#ifndef STRUCT_HEAP_H
#define STRUCT_HEAP_H
//#include <stdio.h>
#include <stdint.h>
#include <osdep_service.h>
/* NOTE: struct size must be a 2's power! */
typedef struct _MemChunk
{
struct _MemChunk *next;
int size;
} MemChunk;
typedef MemChunk heap_buf_t;
/// A heap
typedef struct Heap
{
struct _MemChunk *FreeList; ///< Head of the free list
} Heap;
/**
* Utility macro to allocate a heap of size \a size.
*
* \param name Variable name for the heap.
* \param size Heap size in bytes.
*/
#define HEAP_DEFINE_BUF(name, size) \
heap_buf_t name[((size) + sizeof(heap_buf_t) - 1) / sizeof(heap_buf_t)]
/// Initialize \a heap within the buffer pointed by \a memory which is of \a size bytes
void tcm_heap_init(void);
/// Allocate a chunk of memory of \a size bytes from the heap
void *tcm_heap_allocmem(int size);
/// Free a chunk of memory of \a size bytes from the heap
void tcm_heap_freemem(void *mem, int size);
int tcm_heap_freeSpace(void);
#define HNEW(heap, type) \
(type*)tcm_heap_allocmem(heap, sizeof(type))
#define HNEWVEC(heap, type, nelem) \
(type*)tcm_heap_allocmem(heap, sizeof(type) * (nelem))
#define HDELETE(heap, type, mem) \
tcm_heap_freemem(heap, mem, sizeof(type))
#define HDELETEVEC(heap, type, nelem, mem) \
tcm_heap_freemem(heap, mem, sizeof(type) * (nelem))
/**
* \name Compatibility interface with C standard library
* \{
*/
void *tcm_heap_malloc(int size);
void *tcm_heap_calloc(int size);
void tcm_heap_free(void * mem);
/** \} */
#endif /* STRUCT_HEAP_H */

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//#include <autoconf.h>
#include "tcm_heap.h"
#include <string.h> // memset()
#include <osdep_service.h>
//#define _DEBUG
#if CONFIG_USE_TCM_HEAP
#define FREE_FILL_CODE 0xDEAD
#define ALLOC_FILL_CODE 0xBEEF
#define ROUND_UP2(x, pad) (((x) + ((pad) - 1)) & ~((pad) - 1))
#define TCM_HEAP_SIZE (40*1024)
static struct Heap g_tcm_heap;
#if defined (__ICCARM__)
#pragma location=".tcm.heap"
#else
__attribute__((section(".tcm.heap")))
#endif
HEAP_DEFINE_BUF(tcm_heap, TCM_HEAP_SIZE);
//unsigned char tcm_heap[TCM_HEAP_SIZE];
static int g_heap_inited=0;
static _lock tcm_lock;
#ifdef PLATFORM_FREERTOS
extern void vPortSetExtFree( void (*free)( void *p ), uint32_t upper, uint32_t lower );
#else
extern void rtw_set_mfree_ext( void (*free)( void *p ), uint32_t upper, uint32_t lower );
#endif
void tcm_heap_init(void)
{
//#ifdef _DEBUG
//memset(memory, FREE_FILL_CODE, size);
//#endif
//ASSERT2(((int)memory % alignof(heap_buf_t)) == 0,
//"memory buffer is unaligned, please use the HEAP_DEFINE_BUF() macro to declare heap buffers!\n");
/* Initialize heap with a single big chunk */
g_tcm_heap.FreeList = (MemChunk *)&tcm_heap;
g_tcm_heap.FreeList->next = NULL;
g_tcm_heap.FreeList->size = sizeof(tcm_heap);
g_heap_inited = 1;
rtw_spinlock_init(&tcm_lock);
#if defined(PLATFORM_FREERTOS)
// let RTOS know how to free memory if using as task stack
vPortSetExtFree(tcm_heap_free, 0x20000000, 0x1fff0000);
#elif defined (PLATFORM_CMSIS_RTOS)
rtw_set_mfree_ext(tcm_heap_free, 0x20000000, 0x1fff0000);
#endif
}
void tcm_heap_dump(void)
{
MemChunk *chunk, *prev;
struct Heap* h = &g_tcm_heap;
printf("---Free List--\n\r");
for (prev = (MemChunk *)&h->FreeList, chunk = h->FreeList;
chunk;
prev = chunk, chunk = chunk->next)
{
printf(" prev %x, chunk %x, size %d \n\r", prev, chunk, chunk->size);
}
printf("--------------\n\r");
}
void *tcm_heap_allocmem(int size)
{
MemChunk *chunk, *prev;
struct Heap* h = &g_tcm_heap;
_irqL irqL;
rtw_enter_critical(&tcm_lock, &irqL);
if(!g_heap_inited) tcm_heap_init();
/* Round size up to the allocation granularity */
size = ROUND_UP2(size, sizeof(MemChunk));
/* Handle allocations of 0 bytes */
if (!size)
size = sizeof(MemChunk);
/* Walk on the free list looking for any chunk big enough to
* fit the requested block size.
*/
for (prev = (MemChunk *)&h->FreeList, chunk = h->FreeList;
chunk;
prev = chunk, chunk = chunk->next)
{
if (chunk->size >= size)
{
if (chunk->size == size)
{
/* Just remove this chunk from the free list */
prev->next = chunk->next;
#ifdef _DEBUG
memset(chunk, ALLOC_FILL_CODE, size);
#endif
rtw_exit_critical(&tcm_lock, &irqL);
//printf("----ALLOC1-----\n\r");
//tcm_heap_dump();
//printf("--------------\n\r");
return (void *)chunk;
}
else
{
/* Allocate from the END of an existing chunk */
chunk->size -= size;
#ifdef _DEBUG
memset((uint8_t *)chunk + chunk->size, ALLOC_FILL_CODE, size);
#endif
rtw_exit_critical(&tcm_lock, &irqL);
//printf("----ALLOC2-----\n\r");
//tcm_heap_dump();
//printf("--------------\n\r");
return (void *)((uint8_t *)chunk + chunk->size);
}
}
}
rtw_exit_critical(&tcm_lock, &irqL);
//printf("----ALLOC3-----\n\r");
//tcm_heap_dump();
//printf("--------------\n\r");
return NULL; /* fail */
}
void tcm_heap_freemem(void *mem, int size)
{
MemChunk *prev;
//ASSERT(mem);
struct Heap* h = &g_tcm_heap;
_irqL irqL;
rtw_enter_critical(&tcm_lock, &irqL);
if(!g_heap_inited) tcm_heap_init();
#ifdef _DEBUG
memset(mem, FREE_FILL_CODE, size);
#endif
/* Round size up to the allocation granularity */
size = ROUND_UP2(size, sizeof(MemChunk));
/* Handle allocations of 0 bytes */
if (!size)
size = sizeof(MemChunk);
/* Special cases: first chunk in the free list or memory completely full */
//ASSERT((uint8_t*)mem != (uint8_t*)h->FreeList);
if (((uint8_t *)mem) < ((uint8_t *)h->FreeList) || !h->FreeList)
{
/* Insert memory block before the current free list head */
prev = (MemChunk *)mem;
prev->next = h->FreeList;
prev->size = size;
h->FreeList = prev;
}
else /* Normal case: not the first chunk in the free list */
{
/*
* Walk on the free list. Stop at the insertion point (when mem
* is between prev and prev->next)
*/
prev = h->FreeList;
while (prev->next < (MemChunk *)mem && prev->next)
prev = prev->next;
/* Make sure mem is not *within* prev */
//ASSERT((uint8_t*)mem >= (uint8_t*)prev + prev->size);
/* Should it be merged with previous block? */
if (((uint8_t *)prev) + prev->size == ((uint8_t *)mem))
{
/* Yes */
prev->size += size;
}
else /* not merged with previous chunk */
{
MemChunk *curr = (MemChunk*)mem;
/* insert it after the previous node
* and move the 'prev' pointer forward
* for the following operations
*/
curr->next = prev->next;
curr->size = size;
prev->next = curr;
/* Adjust for the following test */
prev = curr;
}
}
/* Also merge with next chunk? */
if (((uint8_t *)prev) + prev->size == ((uint8_t *)prev->next))
{
prev->size += prev->next->size;
prev->next = prev->next->next;
/* There should be only one merge opportunity, becuase we always merge on free */
//ASSERT((uint8_t*)prev + prev->size != (uint8_t*)prev->next);
}
rtw_exit_critical(&tcm_lock, &irqL);
//printf("---FREE %x--\n\r", mem);
//tcm_heap_dump();
//printf("--------------\n\r");
}
int tcm_heap_freeSpace(void)
{
int free_mem = 0;
struct Heap* h = &g_tcm_heap;
_irqL irqL;
MemChunk *chunk;
rtw_enter_critical(&tcm_lock, &irqL);
if(!g_heap_inited) tcm_heap_init();
for (chunk = h->FreeList; chunk; chunk = chunk->next)
free_mem += chunk->size;
rtw_exit_critical(&tcm_lock, &irqL);
return free_mem;
}
/**
* Standard malloc interface
*/
void *tcm_heap_malloc(int size)
{
int *mem;
size += sizeof(int);
if ((mem = (int*)tcm_heap_allocmem(size))){
*mem++ = size;
}
return mem;
}
/**
* Standard calloc interface
*/
void *tcm_heap_calloc(int size)
{
void *mem;
if ((mem = tcm_heap_malloc(size)))
memset(mem, 0, size);
return mem;
}
/**
* Free a block of memory, determining its size automatically.
*
* \param h Heap from which the block was allocated.
* \param mem Pointer to a block of memory previously allocated with
* either heap_malloc() or heap_calloc().
*
* \note If \a mem is a NULL pointer, no operation is performed.
*
* \note Freeing the same memory block twice has undefined behavior.
*
* \note This function works like the ANSI C free().
*/
void tcm_heap_free(void *mem)
{
int *_mem = (int *)mem;
if (_mem)
{
--_mem;
tcm_heap_freemem(_mem, *_mem);
}
}
static void alloc_test(int size, int test_len)
{
//Simple test
uint8_t *a[100];
int i, j;
for (i = 0; i < test_len; i++)
{
a[i] = tcm_heap_allocmem(size);
//ASSERT(a[i]);
for (j = 0; j < size; j++)
a[i][j] = i;
}
//ASSERT(heap_freeSpace(&h) == HEAP_SIZE - test_len * ROUND_UP2(size, sizeof(MemChunk)));
for (i = 0; i < test_len; i++)
{
for (j = 0; j < size; j++)
{
printf("a[%d][%d] = %d\n", i, j, a[i][j]);
//ASSERT(a[i][j] == i);
}
tcm_heap_freemem(a[i], size);
}
//ASSERT(heap_freeSpace(&h) == HEAP_SIZE);
}
#define ALLOC_SIZE 256
#define ALLOC_SIZE2 1024
#define TEST_LEN 20
#define TEST_LEN2 10
#define HEAP_SIZE 59*1024
int tcm_heap_testRun(void)
{
alloc_test(ALLOC_SIZE, TEST_LEN);
alloc_test(ALLOC_SIZE2, TEST_LEN2);
/* Try to allocate the whole heap */
uint8_t *b = tcm_heap_allocmem(HEAP_SIZE);
int i, j;
//ASSERT(b);
//ASSERT(heap_freeSpace(&h) == 0);
//ASSERT(!heap_allocmem(&h, HEAP_SIZE));
for (j = 0; j < HEAP_SIZE; j++)
b[j] = j;
for (j = 0; j < HEAP_SIZE; j++)
{
printf("b[%d] = %d\n", j, j);
//ASSERT(b[j] == (j & 0xff));
}
tcm_heap_freemem(b, HEAP_SIZE);
//ASSERT(heap_freeSpace(&h) == HEAP_SIZE);
return 0;
}
#endif

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#ifndef _RTX2_SERVICE_H_
#define _RTX2_SERVICE_H_
//-----------------------------------------------------------------------
// Include Files
//-----------------------------------------------------------------------
#include "wireless.h"
#include "dlist.h"
#include <cmsis_os2.h>
//#include <rt_TypeDef.h>
#include "RTX_Config.h"
//#include <rt_Task.h>
//#include <rt_Semaphore.h>
//#include <rt_System.h>
#include "rtx_lib.h"
// --------------------------------------------
// Platform dependent include file
// --------------------------------------------
#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
//#include "platform_stdlib.h"
//#include "basic_types.h"
#include <rtl8195a.h>
#else
// other MCU may use standard library
#include <string.h>
#endif
#if (defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI) || defined(CONFIG_LX_HCI)
/* For SPI interface transfer and us delay implementation */
#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B)
#include <rtwlan_bsp.h>
#endif
#endif
// --------------------------------------------
// Platform dependent type define
// --------------------------------------------
#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B)
typedef unsigned char u8;
typedef unsigned short u16;
typedef unsigned int u32;
typedef signed char s8;
typedef signed short s16;
typedef signed int s32;
typedef signed long long s64;
typedef unsigned long long u64;
typedef unsigned int uint;
typedef signed int sint;
#ifndef bool
typedef int bool;
#define true 1
#define false 0
#endif
#define IN
#define OUT
#define VOID void
#define NDIS_OID uint
#define NDIS_STATUS uint
#ifndef PVOID
typedef void * PVOID;
#endif
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef __kernel_size_t SIZE_T;
typedef __kernel_ssize_t SSIZE_T;
#endif //CONFIG_PLATFORM_8195A
// === SEMAPHORE ===
typedef struct {
osSemaphoreId_t id;
osSemaphoreAttr_t attr;
os_semaphore_t data;
} rtx_sema_t;
// === THREAD ===
typedef struct {
osThreadId_t id;
osThreadAttr_t attr;
os_thread_t data;
} rtx_thread_data_t;
// === MUTEX ===
typedef struct {
osMutexId_t id;
osMutexAttr_t attr;
os_mutex_t data;
} rtx_mutex_t;
// === MAIL BOX ===
#define RTX_MB_SIZE 8
typedef struct {
osEventFlagsId_t id;
osEventFlagsAttr_t attr;
os_event_flags_t data;
uint8_t post_idx;
uint8_t fetch_idx;
void* queue[RTX_MB_SIZE];
} rtx_mqueue_t;
typedef struct {
osMessageQueueId_t id;
osMessageQueueAttr_t attr;
void *queue_mem;
os_message_queue_t data;
} rtx_mbox_t;
typedef struct{
osTimerId_t id;
osTimerAttr_t attr;
os_timer_t data;
}rtx_tmr_t;
#define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field)
// os types
typedef char osdepCHAR;
typedef float osdepFLOAT;
typedef double osdepDOUBLE;
typedef long osdepLONG;
typedef short osdepSHORT;
typedef unsigned long osdepSTACK_TYPE;
typedef long osdepBASE_TYPE;
typedef unsigned long osdepTickType;
typedef void * _timerHandle;
typedef void * _sema;
typedef void * _mutex;
typedef void * _lock;
typedef void * _queueHandle;
typedef void * _xqueue;
typedef struct timer_list _timer;
typedef struct sk_buff _pkt;
typedef unsigned char _buffer;
#ifndef __LIST_H
#warning "DLIST_NOT_DEFINE!!!!!!"
struct list_head {
struct list_head *next, *prev;
};
#endif
struct __queue {
struct list_head queue;
_lock lock;
};
typedef struct __queue _queue;
typedef struct list_head _list;
typedef unsigned long _irqL;
typedef void* _thread_hdl_;
typedef void thread_return;
typedef void* thread_context;
#define ATOMIC_T atomic_t
#define HZ configTICK_RATE_HZ
#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
/* emulate a modern version */
#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 17)
static __inline _list *get_next(_list *list)
{
return list->next;
}
static __inline _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)((char *)&((type *)ptr)->member - (char *)ptr)))
//#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n))
#define container_of(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
#define TASK_PRORITY_LOW osPriorityAboveNormal//osPriorityNormal
#define TASK_PRORITY_MIDDLE osPriorityHigh//osPriorityAboveNormal
#define TASK_PRORITY_HIGH osPriorityRealtime//osPriorityHigh
#define TASK_PRORITY_SUPER osPriorityRealtime
#define TASK_PRORITY_IDEL osPriorityIdle
#define TIMER_MAX_DELAY 0xFFFFFFFF
void save_and_cli(void);
void restore_flags(void);
void cli(void);
//----- ------------------------------------------------------------------
// Common Definition
//----- ------------------------------------------------------------------
#define __init
#define __exit
#define __devinit
#define __devexit
#define KERN_ERR
#define KERN_INFO
#define KERN_NOTICE
#define GFP_KERNEL 1
#define GFP_ATOMIC 1
#define SET_MODULE_OWNER(some_struct) do { } while (0)
#define SET_NETDEV_DEV(dev, obj) do { } while (0)
#define register_netdev(dev) (0)
#define unregister_netdev(dev) do { } while (0)
#define netif_queue_stopped(dev) (0)
#define netif_wake_queue(dev) do { } while (0)
#define printk printf
#define DBG_ERR(fmt, args...) printf("\n\r[%s] " fmt, __FUNCTION__, ## args)
#if WLAN_INTF_DBG
#define DBG_TRACE(fmt, args...) printf("\n\r[%s] " fmt, __FUNCTION__, ## args)
#define DBG_INFO(fmt, args...) printf("\n\r[%s] " fmt, __FUNCTION__, ## args)
#else
#define DBG_TRACE(fmt, args...)
#define DBG_INFO(fmt, args...)
#endif
#define HALT() do { cli(); for(;;);} while(0)
#define ASSERT(x) do { \
if((x) == 0) \
printf("\n\rAssert(" #x ") failed on line %d in file %s", __LINE__, __FILE__); \
HALT(); \
} while(0)
#undef DBG_ASSERT
#define DBG_ASSERT(x, msg) do { \
if((x) == 0) \
printf("\n\r%s, Assert(" #x ") failed on line %d in file %s", msg, __LINE__, __FILE__); \
} while(0)
//----- ------------------------------------------------------------------
// Atomic Operation
//----- ------------------------------------------------------------------
#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B) // for 8195A, it is defined in ..system../basic_types.h
typedef struct { volatile int counter; } atomic_t;
#endif
/*
* atomic_read - read atomic variable
* @v: pointer of type atomic_t
*
* Atomically reads the value of @v. Note that the guaranteed
* useful range of an atomic_t is only 24 bits.
*/
#define atomic_read(v) ((v)->counter)
/*
* atomic_set - set atomic variable
* @v: pointer of type atomic_t
* @i: required value
*
* Atomically sets the value of @v to @i. Note that the guaranteed
* useful range of an atomic_t is only 24 bits.
*/
#define atomic_set(v,i) ((v)->counter = (i))
/*
* These inlines deal with timer wrapping correctly. You are
* strongly encouraged to use them
* 1. Because people otherwise forget
* 2. Because if the timer wrap changes in future you wont have to
* alter your driver code.
*
* time_after(a,b) returns true if the time a is after time b.
*
* Do this with "<0" and ">=0" to only test the sign of the result. A
* good compiler would generate better code (and a really good compiler
* wouldn't care). Gcc is currently neither.
*/
#define time_after(a,b) ((long)(b) - (long)(a) < 0)
#define time_before(a,b) time_after(b,a)
#define time_after_eq(a,b) ((long)(a) - (long)(b) >= 0)
#define time_before_eq(a,b) time_after_eq(b,a)
extern void rtw_init_listhead(_list *list);
extern u32 rtw_is_list_empty(_list *phead);
extern void rtw_list_insert_head(_list *plist, _list *phead);
extern void rtw_list_insert_tail(_list *plist, _list *phead);
extern void rtw_list_delete(_list *plist);
#define vPortExitCritical save_and_cli
#endif /* _RTX_SERVICE_H_ */

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targets/TARGET_Realtek/TARGET_AMEBA/sdk/platform_opts.h Normal file
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/**
Copyright (c) 2016 Realtek Semiconductor Corp.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
******************************************************************************
*This file contains general configurations for ameba platform
******************************************************************************
*/
#ifndef __PLATFORM_OPTS_H__
#define __PLATFORM_OPTS_H__
/*For MP mode setting*/
#define SUPPORT_MP_MODE 1
/**
* For AT cmd Log service configurations
*/
#define SUPPORT_LOG_SERVICE 1
#if SUPPORT_LOG_SERVICE
#define LOG_SERVICE_BUFLEN 100 //can't larger than UART_LOG_CMD_BUFLEN(127)
#define CONFIG_LOG_HISTORY 0
#if CONFIG_LOG_HISTORY
#define LOG_HISTORY_LEN 5
#endif
#define SUPPORT_INTERACTIVE_MODE 0//on/off wifi_interactive_mode
#define CONFIG_LOG_SERVICE_LOCK 0
#define CONFIG_LOG_USE_HS_UART 0 //command/log via highspeed uart
#define CONFIG_LOG_USE_I2C 0 //command/log via I2C
#endif
/**
* For interactive mode configurations, depends on log service
*/
#if SUPPORT_INTERACTIVE_MODE
#define CONFIG_INTERACTIVE_MODE 1
#define CONFIG_INTERACTIVE_EXT 0
#else
#define CONFIG_INTERACTIVE_MODE 0
#define CONFIG_INTERACTIVE_EXT 0
#endif
/**
* For FreeRTOS tickless configurations
*/
#define FREERTOS_PMU_TICKLESS_PLL_RESERVED 0 // In sleep mode, 0: close PLL clock, 1: reserve PLL clock
#define FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM 1 // In sleep mode, 1: suspend SDRAM, 0: no act
/******************************************************************************/
/**
* For common flash usage
*/
#define AP_SETTING_SECTOR 0x000FE000
#define UART_SETTING_SECTOR 0x000FC000
#define FAST_RECONNECT_DATA (0x80000 - 0x1000)
/**
* For Wlan configurations
*/
#define CONFIG_WLAN 1
#if CONFIG_WLAN
#define CONFIG_LWIP_LAYER 1
#define CONFIG_INIT_NET 1 //init lwip layer when start up
#define CONFIG_WIFI_IND_USE_THREAD 0 // wifi indicate worker thread
//on/off relative commands in log service
#define CONFIG_SSL_CLIENT 0
#define CONFIG_WEBSERVER 0
#define CONFIG_OTA_UPDATE 1
#define CONFIG_BSD_TCP 0//NOTE : Enable CONFIG_BSD_TCP will increase about 11KB code size
#define CONFIG_AIRKISS 0//on or off tencent airkiss
#define CONFIG_UART_SOCKET 0
#define CONFIG_JD_SMART 0//on or off for jdsmart
#define CONFIG_JOYLINK 0//on or off for jdsmart2.0
#define CONFIG_QQ_LINK 0//on or off for qqlink
#define CONFIG_AIRKISS_CLOUD 0//on or off for weixin hardware cloud
#define CONFIG_UART_YMODEM 0//support uart ymodem upgrade or not
#define CONFIG_GOOGLE_NEST 0//on or off the at command control for google nest
#define CONFIG_TRANSPORT 0//on or off the at command for transport socket
#define CONFIG_ALINK 0//on or off for alibaba alink
/* For WPS and P2P */
#define CONFIG_ENABLE_WPS 0
#define CONFIG_ENABLE_P2P 0
#if CONFIG_ENABLE_P2P
#define CONFIG_ENABLE_WPS_AP 1
#undef CONFIG_WIFI_IND_USE_THREAD
#define CONFIG_WIFI_IND_USE_THREAD 1
#endif
#if (CONFIG_ENABLE_P2P && ((CONFIG_ENABLE_WPS_AP == 0) || (CONFIG_ENABLE_WPS == 0)))
#error "If CONFIG_ENABLE_P2P, need to define CONFIG_ENABLE_WPS_AP 1"
#endif
/* For Simple Link */
#define CONFIG_INCLUDE_SIMPLE_CONFIG 1
/*For fast reconnection*/
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
/*For wowlan service settings*/
#define CONFIG_WOWLAN_SERVICE 0
#define CONFIG_GAGENT 0
/*Disable CONFIG_EXAMPLE_WLAN_FAST_CONNECT when CONFIG_GAGENT is enabled,because
reconnect to previous AP is not suitable when re-configuration.
*/
#if CONFIG_GAGENT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
#endif //end of #if CONFIG_WLAN
/*******************************************************************************/
/**
* For Ethernet configurations
*/
#define CONFIG_ETHERNET 0
#if CONFIG_ETHERNET
#define CONFIG_LWIP_LAYER 1
#define CONFIG_INIT_NET 1 //init lwip layer when start up
//on/off relative commands in log service
#define CONFIG_SSL_CLIENT 0
#define CONFIG_BSD_TCP 0//NOTE : Enable CONFIG_BSD_TCP will increase about 11KB code size
#endif
/**
* For iNIC configurations
*/
#ifdef CONFIG_INIC //this flag is defined in IAR project
#define CONFIG_INIC_EN 1//enable iNIC mode
#undef CONFIG_ENABLE_WPS
#define CONFIG_ENABLE_WPS 1
#undef CONFIG_INCLUDE_SIMPLE_CONFIG
#define CONFIG_INCLUDE_SIMPLE_CONFIG 1
#undef CONFIG_WOWLAN_SERVICE
#define CONFIG_WOWLAN_SERVICE 1
#undef LOG_SERVICE_BUFLEN
#define LOG_SERVICE_BUFLEN 256
#undef CONFIG_LWIP_LAYER
#define CONFIG_LWIP_LAYER 0
#undef CONFIG_OTA_UPDATE
#define CONFIG_OTA_UPDATE 0
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#define CONFIG_INIC_SDIO_HCI 1 //for SDIO or USB iNIC
#define CONFIG_INIC_USB_HCI 0
#define CONFIG_INIC_CMD_RSP 1 //need to return msg to host
#endif
/******************End of iNIC configurations*******************/
/* For aj_basic_example */
#define CONFIG_EXAMPLE_AJ_BASIC 0
/*For aj_ameba_led example*/
#define CONFIG_EXAMPLE_AJ_AMEBA_LED 0
/* For WIFI GET BEACON FRAME example */
#define CONFIG_EXAMPLE_GET_BEACON_FRAME 0
/* For WIFI MAC MONITOR example */
#define CONFIG_EXAMPLE_WIFI_MAC_MONITOR 0
/* For HTTP CLIENT example */
#define CONFIG_EXAMPLE_HTTP_CLIENT 0
/* For MQTT example */
#define CONFIG_EXAMPLE_MQTT 0
/* For WiGadget example */
#define CONFIG_EXAMPLE_WIGADGET 0
/*For google nest example*/
#define CONFIG_EXAMPLE_GOOGLE_NEST 0
/* For mDNS example */
#define CONFIG_EXAMPLE_MDNS 0
/* For multicast example */
#define CONFIG_EXAMPLE_MCAST 0
/* For XML example */
#define CONFIG_EXAMPLE_XML 0
/* For socket select example */
#define CONFIG_EXAMPLE_SOCKET_SELECT 0
/* For socket nonblocking connect example */
#define CONFIG_EXAMPLE_NONBLOCK_CONNECT 0
/* For socket TCP bidirectional transmission example */
#define CONFIG_EXAMPLE_SOCKET_TCP_TRX 0
/* For ssl download example */
#define CONFIG_EXAMPLE_SSL_DOWNLOAD 0
/* For http download example */
#define CONFIG_EXAMPLE_HTTP_DOWNLOAD 0
/* For tcp keepalive example */
#define CONFIG_EXAMPLE_TCP_KEEPALIVE 0
/* For sntp show time example */
#define CONFIG_EXAMPLE_SNTP_SHOWTIME 0
/* For pppoe example */
#define CONFIG_EXAMPLE_PPPOE 0
/* For websocket client example */
#define CONFIG_EXAMPLE_WEBSOCKET 0
/*For Audio example */
#define CONFIG_EXAMPLE_AUDIO 0
#if CONFIG_EXAMPLE_AUDIO
#define FATFS_DISK_SD 1
#define CONFIG_EXAMPLE_CODEC_SGTL5000 1
#endif
/* For UART Module AT command example */
#define CONFIG_EXAMPLE_UART_ATCMD 0
#if CONFIG_EXAMPLE_UART_ATCMD
#undef FREERTOS_PMU_TICKLESS_PLL_RESERVED
#define FREERTOS_PMU_TICKLESS_PLL_RESERVED 1
#undef CONFIG_OTA_UPDATE
#define CONFIG_OTA_UPDATE 1
#undef CONFIG_TRANSPORT
#define CONFIG_TRANSPORT 1
#undef LOG_SERVICE_BUFLEN
#define LOG_SERVICE_BUFLEN 1600
#undef CONFIG_LOG_SERVICE_LOCK
#define CONFIG_LOG_SERVICE_LOCK 1
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
#define CONFIG_EXAMPLE_MEDIA_SS 0
#define CONFIG_EXAMPLE_MEDIA_MS 0
#define CONFIG_EXAMPLE_MEDIA_AUDIO_FROM_RTP 0
// Use media source/sink example
#if (CONFIG_EXAMPLE_MEDIA_SS==1) || (CONFIG_EXAMPLE_MEDIA_MS==1)
#undef CONFIG_INCLUDE_SIMPLE_CONFIG
#define CONFIG_INCLUDE_SIMPLE_CONFIG 0
#define CONFIG_ENABLE_WPS 0
#endif
/* For Mjpeg capture example*/
#define CONFIG_EXAMPLE_MJPEG_CAPTURE 0
#if CONFIG_EXAMPLE_MJPEG_CAPTURE
#define FATFS_DISK_SD 1
#endif
/****************** For EAP method example *******************/
#define CONFIG_EXAMPLE_EAP 0
// on/off specified eap method
#define CONFIG_ENABLE_PEAP 0
#define CONFIG_ENABLE_TLS 0
#define CONFIG_ENABLE_TTLS 0
// optional feature: whether to verify the cert of radius server
#define ENABLE_EAP_SSL_VERIFY_SERVER 0
#if CONFIG_ENABLE_PEAP || CONFIG_ENABLE_TLS || CONFIG_ENABLE_TTLS
#define CONFIG_ENABLE_EAP
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
#if CONFIG_ENABLE_TLS
#define ENABLE_EAP_SSL_VERIFY_CLIENT 1
#else
#define ENABLE_EAP_SSL_VERIFY_CLIENT 0
#endif
/******************End of EAP configurations*******************/
/* For usb mass storage example */
#define CONFIG_EXAMPLE_USB_MASS_STORAGE 0
/* For FATFS example*/
#define CONFIG_EXAMPLE_FATFS 0
#if CONFIG_EXAMPLE_FATFS
#define CONFIG_FATFS_EN 1
#if CONFIG_FATFS_EN
// fatfs version
#define FATFS_R_10C
// fatfs disk interface
#define FATFS_DISK_USB 0
#define FATFS_DISK_SD 1
#endif
#endif
/* For iNIC host example*/
#ifdef CONFIG_INIC_GSPI_HOST //this flag is defined in IAR project
#define CONFIG_EXAMPLE_INIC_GSPI_HOST 1
#if CONFIG_EXAMPLE_INIC_GSPI_HOST
#define CONFIG_INIC_HOST 1
#undef CONFIG_WLAN
#define CONFIG_WLAN 0
#undef CONFIG_INCLUDE_SIMPLE_CONFIG
#define CONFIG_INCLUDE_SIMPLE_CONFIG 0
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#undef CONFIG_LWIP_LAYER
#define CONFIG_LWIP_LAYER 1
#undef CONFIG_BSD_TCP
#define CONFIG_BSD_TCP 1
#endif
#endif
/*For uart update example*/
#define CONFIG_UART_UPDATE 0
#if CONFIG_UART_UPDATE
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
/*For arduino wifi shield example */
#define CONFIG_EXAMPLE_ARDUINO_WIFI 0
#if CONFIG_EXAMPLE_ARDUINO_WIFI
#undef CONFIG_WIFI_NORMAL
#endif
/* For uart adapter example */
/* Please also configure LWIP_UART_ADAPTER to 1
in lwip_opt.h for support uart adapter*/
#define CONFIG_EXAMPLE_UART_ADAPTER 0
#if CONFIG_EXAMPLE_UART_ADAPTER
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 1
#undef CONFIG_EXAMPLE_MDNS
#define CONFIG_EXAMPLE_MDNS 1
#undef FREERTOS_PMU_TICKLESS_PLL_RESERVED
#define FREERTOS_PMU_TICKLESS_PLL_RESERVED 1
#endif
#if CONFIG_JD_SMART
#if (CONFIG_ENABLE_WPS == 1)
#define CONFIG_ENABLE_WPS 0
#endif
#if (CONFIG_INCLUDE_SIMPLE_CONFIG == 1)
#define CONFIG_INCLUDE_SIMPLE_CONFIG 0
#endif
#if (CONFIG_EXAMPLE_WLAN_FAST_CONNECT == 1)
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
#endif
/* For wifi scenarios example (Wi-Fi, WPS enrollee, P2P GO) */
// also need to enable WPS and P2P
#define CONFIG_EXAMPLE_WLAN_SCENARIO 0
/* For broadcast example */
#define CONFIG_EXAMPLE_BCAST 0
/* For high-load memory use case memory usage */
#define CONFIG_EXAMPLE_HIGH_LOAD_MEMORY_USE 0
/* For rarp example */
#define CONFIG_EXAMPLE_RARP 0
/* For ssl server example */
#define CONFIG_EXAMPLE_SSL_SERVER 0
/* For ota update http example */
#define CONFIG_EXAMPLE_OTA_HTTP 0
#endif

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