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Add GIC_SetConfigration function to satisfy Cortex-A interrupt spec 

By updating to the codes of CMSIS5/RTX5, GIC_SetConfigration() function was added for Cortex-A, this function is set the interrupt configuration using GIC's ICFGR register. Therefore, I added this function to satisfy Cortex-A interrupt spec in the below files.
"can_api.c", "ethernet_api.c", "gpio_irq_api.c", "i2c_api.c", "spi_api.c" and "us_ticker.c"
pull/5767/head
TomoYamanaka 2017-12-14 20:25:27 +09:00 committed by adbridge
parent c30e107f6e
commit 2661bc27a9
6 changed files with 10 additions and 0 deletions
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1
targets/TARGET_RENESAS/TARGET_RZ_A1H/can_api.c
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@ -340,6 +340,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
}
InterruptHandlerRegister(can_int_info[obj->ch][type].int_num, can_int_info[obj->ch][type].handler);
GIC_SetPriority(can_int_info[obj->ch][type].int_num, 5);
GIC_SetConfiguration(can_int_info[obj->ch][type].int_num, 1);
GIC_EnableIRQ(can_int_info[obj->ch][type].int_num);
} else {
GIC_DisableIRQ(can_int_info[obj->ch][type].int_num);

1
targets/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c
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@ -582,6 +582,7 @@ static void lan_reg_set(int32_t link) {
ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */
InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */
GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */
GIC_SetConfiguration(ETHERI_IRQn, 1);
GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */
}

1
targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c
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@ -166,6 +166,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
InterruptHandlerRegister((IRQn_Type)(nIRQn_h+obj->ch), (void (*)(uint32_t))irq_tbl[obj->ch]);
INTCICR1 &= ~(0x3 << shift);
GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5);
GIC_SetConfiguration((IRQn_Type)(nIRQn_h + obj->ch), 1);
obj->int_enable = 1;
__enable_irq();

5
targets/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c
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@ -1062,6 +1062,11 @@ static void i2c_irqs_set(i2c_t *obj, uint32_t enable)
if (enable) {
InterruptHandlerRegister(irqTable[i], handlerTable[i]);
GIC_SetPriority(irqTable[i], 5);
if (i == 1) {
GIC_SetConfiguration(irqTable[i], 3);
} else {
GIC_SetConfiguration(irqTable[i], 1);
}
GIC_EnableIRQ(irqTable[i]);
} else {
GIC_DisableIRQ(irqTable[i]);

1
targets/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c
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@ -447,6 +447,7 @@ static void spi_irqs_set(spi_t *obj, uint32_t enable)
if (enable) {
InterruptHandlerRegister(irqTable[i], handlerTable[i]);
GIC_SetPriority(irqTable[i], 5);
GIC_SetConfiguration(irqTable[i], 1);
GIC_EnableIRQ(irqTable[i]);
} else {
GIC_DisableIRQ(irqTable[i]);

1
targets/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c
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@ -62,6 +62,7 @@ void us_ticker_init(void) {
// INTC settings
InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt);
GIC_SetPriority(US_TICKER_TIMER_IRQn, 5);
GIC_SetConfiguration(US_TICKER_TIMER_IRQn, 3);
GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
}