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Merge pull request #4299 from jeromecoutant/PULL_REQUEST_CUBE_UPDATE_F4_V1.16.0 

STM32F4 cube update from v1.12.0 to v1.16.0
pull/3069/merge
Sam Grove 2017-05-26 17:13:08 -05:00 committed by GitHub
parent 92e661b3c0 92c55e7f31
commit 2561e0bff4
264 changed files with 231681 additions and 76919 deletions
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6
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h
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@ -44,10 +44,10 @@
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

9981
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/stm32f411xe.h
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21
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/stm32f4xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -79,7 +79,7 @@
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
!defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
!defined (STM32F412Zx)
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -106,6 +106,9 @@
/* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
/* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
/* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -121,11 +124,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS version number V2.5.0
* @brief CMSIS version number V2.6.1
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@ -182,6 +185,10 @@
#include "stm32f412rx.h"
#elif defined(STM32F412Vx)
#include "stm32f412vx.h"
#elif defined(STM32F413xx)
#include "stm32f413xx.h"
#elif defined(STM32F423xx)
#include "stm32f423xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_stm32f4xx.c
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@ -159,7 +159,7 @@
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -837,7 +837,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSE oscillator and activate PLL with HSE as source */
@ -896,7 +896,7 @@ uint8_t SetSysClock_PLL_HSI(void)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSI oscillator and activate PLL with HSI as source */

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_stm32f4xx.h
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@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -75,6 +75,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h
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@ -44,10 +44,10 @@
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

17061
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/stm32f405xx.h
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27
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/stm32f4xx.h
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@ -2,23 +2,23 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F4xx device used in the target application
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral's registers
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -79,8 +79,8 @@
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
!defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
!defined (STM32F412Zx)
#define STM32F405xx /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
#define STM32F405xx /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
/* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
@ -106,6 +106,9 @@
/* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
/* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
/* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -121,11 +124,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS version number V2.5.0
* @brief CMSIS version number V2.6.1
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@ -182,6 +185,10 @@
#include "stm32f412rx.h"
#elif defined(STM32F412Vx)
#include "stm32f412vx.h"
#elif defined(STM32F413xx)
#include "stm32f413xx.h"
#elif defined(STM32F423xx)
#include "stm32f423xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif

4
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/system_stm32f4xx.c
View File

@ -138,7 +138,7 @@
*/
uint32_t SystemCoreClock = 48000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -778,7 +778,7 @@ void SetSysClock(void)
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/system_stm32f4xx.h
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@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -75,6 +75,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h
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@ -44,10 +44,10 @@
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

9981
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/stm32f411xe.h
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21
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/stm32f4xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -79,7 +79,7 @@
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
!defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
!defined (STM32F412Zx)
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -106,6 +106,9 @@
/* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
/* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
/* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -121,11 +124,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS version number V2.5.0
* @brief CMSIS version number V2.6.1
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@ -182,6 +185,10 @@
#include "stm32f412rx.h"
#elif defined(STM32F412Vx)
#include "stm32f412vx.h"
#elif defined(STM32F413xx)
#include "stm32f413xx.h"
#elif defined(STM32F423xx)
#include "stm32f423xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_stm32f4xx.c
View File

@ -164,7 +164,7 @@
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -842,7 +842,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSE oscillator and activate PLL with HSE as source */
@ -899,7 +899,7 @@ uint8_t SetSysClock_PLL_HSI(void)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSI oscillator and activate PLL with HSI as source */

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_stm32f4xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -75,6 +75,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

16
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_stm32f4xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -40,7 +40,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -157,7 +157,7 @@
*/
uint32_t SystemCoreClock = 84000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -325,8 +325,8 @@ void SystemCoreClockUpdate(void)
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
@ -835,7 +835,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSE oscillator and activate PLL with HSE as source */
@ -893,7 +893,7 @@ uint8_t SetSysClock_PLL_HSI(void)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSI oscillator and activate PLL with HSI as source */

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h
View File

@ -44,10 +44,10 @@
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

9943
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/stm32f401xc.h
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21
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/stm32f4xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -79,7 +79,7 @@
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
!defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
!defined (STM32F412Zx)
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -106,6 +106,9 @@
/* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
/* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
/* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -121,11 +124,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS version number V2.5.0
* @brief CMSIS version number V2.6.1
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@ -182,6 +185,10 @@
#include "stm32f412rx.h"
#elif defined(STM32F412Vx)
#include "stm32f412vx.h"
#elif defined(STM32F413xx)
#include "stm32f413xx.h"
#elif defined(STM32F423xx)
#include "stm32f423xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/system_stm32f4xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -75,6 +75,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

16
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/system_stm32f4xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -40,7 +40,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -157,7 +157,7 @@
*/
uint32_t SystemCoreClock = 84000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -325,8 +325,8 @@ void SystemCoreClockUpdate(void)
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
@ -835,7 +835,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSE oscillator and activate PLL with HSE as source */
@ -893,7 +893,7 @@ uint8_t SetSysClock_PLL_HSI(void)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSI oscillator and activate PLL with HSI as source */

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/hal_tick.h
View File

@ -44,10 +44,10 @@
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

9935
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/stm32f401xe.h
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21
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/stm32f4xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -79,7 +79,7 @@
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
!defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
!defined (STM32F412Zx)
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -106,6 +106,9 @@
/* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
/* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
/* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -121,11 +124,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS version number V2.5.0
* @brief CMSIS version number V2.6.1
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@ -182,6 +185,10 @@
#include "stm32f412rx.h"
#elif defined(STM32F412Vx)
#include "stm32f412vx.h"
#elif defined(STM32F413xx)
#include "stm32f413xx.h"
#elif defined(STM32F423xx)
#include "stm32f423xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/system_stm32f4xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -75,6 +75,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

16
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_stm32f4xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -40,7 +40,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -157,7 +157,7 @@
*/
uint32_t SystemCoreClock = 168000000; /* [CHANGED FOR MBED] */
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -326,8 +326,8 @@ void SystemCoreClockUpdate(void)
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
@ -1001,7 +1001,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSE oscillator and activate PLL with HSE as source */
@ -1060,7 +1060,7 @@ uint8_t SetSysClock_PLL_HSI(void)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSI oscillator and activate PLL with HSI as source */

16
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_stm32f4xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -40,7 +40,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -157,7 +157,7 @@
*/
uint32_t SystemCoreClock = 168000000; /* [CHANGED FOR MBED] */
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -326,8 +326,8 @@ void SystemCoreClockUpdate(void)
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
@ -1001,7 +1001,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSE oscillator and activate PLL with HSE as source */
@ -1060,7 +1060,7 @@ uint8_t SetSysClock_PLL_HSI(void)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSI oscillator and activate PLL with HSI as source */

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h
View File

@ -44,10 +44,10 @@
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

18425
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f407xx.h
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21
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f4xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -79,7 +79,7 @@
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
!defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
!defined (STM32F412Zx)
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
#define STM32F407xx /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -103,6 +103,9 @@
/* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
/* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
/* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -118,11 +121,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS version number V2.5.0
* @brief CMSIS version number V2.6.1
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@ -179,6 +182,10 @@
#include "stm32f412rx.h"
#elif defined(STM32F412Vx)
#include "stm32f412vx.h"
#elif defined(STM32F413xx)
#include "stm32f413xx.h"
#elif defined(STM32F423xx)
#include "stm32f423xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/system_stm32f4xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -75,6 +75,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

18
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/system_stm32f4xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -24,7 +24,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -140,9 +140,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000;
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -310,8 +310,8 @@ void SystemCoreClockUpdate(void)
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
@ -819,7 +819,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSE oscillator and activate PLL with HSE as source */
@ -879,7 +879,7 @@ uint8_t SetSysClock_PLL_HSI(void)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSI oscillator and activate PLL with HSI as source */

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h
View File

@ -44,10 +44,10 @@
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

8200
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/stm32f410rx.h
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File diff suppressed because it is too large Load Diff

21
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/stm32f4xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -79,7 +79,7 @@
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
!defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
!defined (STM32F412Zx)
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -106,6 +106,9 @@
/* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
/* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
/* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -121,11 +124,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS version number V2.5.0
* @brief CMSIS version number V2.6.1
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@ -182,6 +185,10 @@
#include "stm32f412rx.h"
#elif defined(STM32F412Vx)
#include "stm32f412vx.h"
#elif defined(STM32F413xx)
#include "stm32f413xx.h"
#elif defined(STM32F423xx)
#include "stm32f423xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/system_stm32f4xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -75,6 +75,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

16
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_stm32f4xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -40,7 +40,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -158,7 +158,7 @@
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -326,8 +326,8 @@ void SystemCoreClockUpdate(void)
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
@ -836,7 +836,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSE oscillator and activate PLL with HSE as source */
@ -900,7 +900,7 @@ uint8_t SetSysClock_PLL_HSI(void)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSI oscillator and activate PLL with HSI as source */

16
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/system_stm32f4xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -40,7 +40,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -158,7 +158,7 @@
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -326,8 +326,8 @@ void SystemCoreClockUpdate(void)
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
@ -836,7 +836,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSE oscillator and activate PLL with HSE as source */
@ -895,7 +895,7 @@ uint8_t SetSysClock_PLL_HSI(void)
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSI oscillator and activate PLL with HSI as source */

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h
View File

@ -44,10 +44,10 @@
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

9981
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/stm32f411xe.h
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File diff suppressed because it is too large Load Diff

21
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/stm32f4xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -79,7 +79,7 @@
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
!defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
!defined (STM32F412Zx)
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -106,6 +106,9 @@
/* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
/* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
/* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -121,11 +124,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS version number V2.5.0
* @brief CMSIS version number V2.6.1
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@ -182,6 +185,10 @@
#include "stm32f412rx.h"
#elif defined(STM32F412Vx)
#include "stm32f412vx.h"
#elif defined(STM32F413xx)
#include "stm32f413xx.h"
#elif defined(STM32F423xx)
#include "stm32f423xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/system_stm32f4xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -75,6 +75,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

20
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_stm32f4xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -40,7 +40,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -158,7 +158,7 @@
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -326,8 +326,8 @@ void SystemCoreClockUpdate(void)
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
@ -870,8 +870,8 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
@ -939,8 +939,8 @@ uint8_t SetSysClock_PLL_HSI(void)
PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h
View File

@ -44,10 +44,10 @@
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

17279
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/stm32f412zx.h
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21
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/stm32f4xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -79,7 +79,7 @@
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
!defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
!defined (STM32F412Zx)
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -106,6 +106,9 @@
#define STM32F412Zx /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
/* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
/* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -121,11 +124,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS version number V2.5.0
* @brief CMSIS version number V2.6.1
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@ -182,6 +185,10 @@
#include "stm32f412rx.h"
#elif defined(STM32F412Vx)
#include "stm32f412vx.h"
#elif defined(STM32F413xx)
#include "stm32f413xx.h"
#elif defined(STM32F423xx)
#include "stm32f423xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif

36
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/stm32f4xx_hal_conf.h
View File

@ -1,16 +1,24 @@
/**
******************************************************************************
* @file stm32f4xx_hal_conf.h
* @file stm32f4xx.h
* @author MCD Application Team
* @version V1.4.4
* @date 22-January-2016
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32f4xx_hal_conf.h.
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F4xx device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -118,6 +126,10 @@
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
!defined (STM32F412Zx)
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
#endif /* HSI_VALUE */
/**
@ -140,13 +152,13 @@
#endif /* LSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for I2S peripheral
* @brief CMSIS version number V2.5.0
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
@ -331,6 +343,10 @@
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f4xx_hal_i2s.h"
#elif defined(STM32F413xx)
#include "stm32f413xx.h"
#elif defined(STM32F423xx)
#include "stm32f423xx.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/system_stm32f4xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -75,6 +75,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

16
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_stm32f4xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -156,7 +156,7 @@
*/
uint32_t SystemCoreClock = 168000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -309,8 +309,8 @@ void SystemCoreClockUpdate(void)
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
@ -785,7 +785,7 @@ void SetSysClock(void)
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
@ -823,7 +823,7 @@ void SetSysClock(void)
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
@ -837,7 +837,7 @@ void SetSysClock(void)
RCC_OscInitStruct.PLL.PLLQ = 7;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
HAL_PWREx_ActivateOverDrive();
HAL_PWREx_EnableOverDrive();
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
|RCC_CLOCKTYPE_PCLK2;

16
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_stm32f4xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -157,7 +157,7 @@
*/
uint32_t SystemCoreClock = 168000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -310,8 +310,8 @@ void SystemCoreClockUpdate(void)
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
@ -786,7 +786,7 @@ void SetSysClock(void)
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
@ -824,7 +824,7 @@ void SetSysClock(void)
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
@ -838,7 +838,7 @@ void SetSysClock(void)
RCC_OscInitStruct.PLL.PLLQ = 7;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
HAL_PWREx_ActivateOverDrive();
HAL_PWREx_EnableOverDrive();
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
|RCC_CLOCKTYPE_PCLK2;

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h
View File

@ -44,10 +44,10 @@
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

20131
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f429xx.h
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21
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f4xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -79,7 +79,7 @@
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
!defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
!defined (STM32F412Zx)
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -106,6 +106,9 @@
/* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
/* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
/* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -121,11 +124,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS version number V2.5.0
* @brief CMSIS version number V2.6.1
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@ -182,6 +185,10 @@
#include "stm32f412rx.h"
#elif defined(STM32F412Vx)
#include "stm32f412vx.h"
#elif defined(STM32F413xx)
#include "stm32f413xx.h"
#elif defined(STM32F423xx)
#include "stm32f423xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/system_stm32f4xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -75,6 +75,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

16
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/system_stm32f4xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -38,7 +38,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -156,7 +156,7 @@
*/
uint32_t SystemCoreClock = 168000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -320,8 +320,8 @@ void SystemCoreClockUpdate(void)
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
@ -793,7 +793,7 @@ void SetSysClock(void)
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
@ -834,7 +834,7 @@ void SetSysClock(void)
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h
View File

@ -44,10 +44,10 @@
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

315
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f437xx.h
View File

@ -2,19 +2,19 @@
******************************************************************************
* @file stm32f437xx.h
* @author MCD Application Team
* @version V2.6.0
* @date 04-November-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F437xx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - peripherals registers declarations and bits definition
* - Macros to access peripheral’s registers hardware
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -1078,13 +1078,14 @@ typedef struct
#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END 0x081FFFFFU /*!< FLASH end address */
#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
#define SRAM_BB_BASE SRAM1_BB_BASE
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
@ -1130,7 +1131,9 @@ typedef struct
#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
/* Legacy define */
#define ADC_BASE ADC123_COMMON_BASE
#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
@ -1263,10 +1266,12 @@ typedef struct
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define USART6 ((USART_TypeDef *) USART6_BASE)
#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
/* Legacy define */
#define ADC ADC123_COMMON
#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
@ -1349,6 +1354,11 @@ typedef struct
/* Analog to Digital Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
*/
#define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD_Pos (0U)
#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
@ -1934,6 +1944,10 @@ typedef struct
#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
/* Legacy defines */
#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
/******************************************************************************/
/* */
/* Controller Area Network */
@ -2148,21 +2162,6 @@ typedef struct
#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
#define CAN_IER_EWGIE_Pos (8U)
#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error warning interrupt enable */
#define CAN_IER_EPVIE_Pos (9U)
#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error passive interrupt enable */
#define CAN_IER_BOFIE_Pos (10U)
#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-off interrupt enable */
#define CAN_IER_LECIE_Pos (11U)
#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last error code interrupt enable */
#define CAN_IER_ERRIE_Pos (15U)
#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error interrupt enable */
/******************** Bit definition for CAN_ESR register *******************/
#define CAN_ESR_EWGF_Pos (0U)
@ -7313,6 +7312,9 @@ typedef struct
#define FLASH_SR_PGSERR_Pos (7U)
#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
#define FLASH_SR_RDERR_Pos (8U)
#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
#define FLASH_SR_BSY_Pos (16U)
#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
#define FLASH_SR_BSY FLASH_SR_BSY_Msk
@ -10470,12 +10472,22 @@ typedef struct
#define RCC_CR_PLLRDY_Pos (25U)
#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
*/
#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
#define RCC_CR_PLLI2SON_Pos (26U)
#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
#define RCC_CR_PLLI2SRDY_Pos (27U)
#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
*/
#define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */
#define RCC_CR_PLLSAION_Pos (28U)
#define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
@ -10529,6 +10541,7 @@ typedef struct
#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
#define RCC_CFGR_SW_Pos (0U)
@ -10989,6 +11002,11 @@ typedef struct
#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
/******************** Bit definition for RCC_AHB2ENR register ***************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
*/
#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
#define RCC_AHB2ENR_DCMIEN_Pos (0U)
#define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
@ -11006,6 +11024,11 @@ typedef struct
#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
/******************** Bit definition for RCC_AHB3ENR register ***************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
*/
#define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
#define RCC_AHB3ENR_FMCEN_Pos (0U)
#define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
@ -11410,24 +11433,27 @@ typedef struct
#define RCC_CSR_BORRSTF_Pos (25U)
#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
#define RCC_CSR_PADRSTF_Pos (26U)
#define RCC_CSR_PADRSTF_Msk (0x1U << RCC_CSR_PADRSTF_Pos) /*!< 0x04000000 */
#define RCC_CSR_PADRSTF RCC_CSR_PADRSTF_Msk
#define RCC_CSR_PINRSTF_Pos (26U)
#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
#define RCC_CSR_PORRSTF_Pos (27U)
#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
#define RCC_CSR_SFTRSTF_Pos (28U)
#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
#define RCC_CSR_WDGRSTF_Pos (29U)
#define RCC_CSR_WDGRSTF_Msk (0x1U << RCC_CSR_WDGRSTF_Pos) /*!< 0x20000000 */
#define RCC_CSR_WDGRSTF RCC_CSR_WDGRSTF_Msk
#define RCC_CSR_IWDGRSTF_Pos (29U)
#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
#define RCC_CSR_WWDGRSTF_Pos (30U)
#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
#define RCC_CSR_LPWRRSTF_Pos (31U)
#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
/* Legacy defines */
#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
/******************** Bit definition for RCC_SSCGR register *****************/
#define RCC_SSCGR_MODPER_Pos (0U)
@ -11502,15 +11528,29 @@ typedef struct
#define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
/******************** Bit definition for RCC_DCKCFGR register ***************/
#define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
#define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
#define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
#define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
#define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
#define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
#define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
#define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
#define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
#define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
#define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
#define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
#define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
#define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
#define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
#define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
#define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
#define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
#define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
#define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
#define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
#define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
#define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
#define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
#define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
#define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
#define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
#define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
#define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
#define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
#define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
#define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
#define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
@ -11561,6 +11601,11 @@ typedef struct
/* Real-Time Clock (RTC) */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
*/
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
@ -11663,9 +11708,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk
#define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -11718,6 +11763,9 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
@ -12055,9 +12103,9 @@ typedef struct
#define RTC_TAFCR_TSINSEL_Pos (17U)
#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
#define RTC_TAFCR_TAMPINSEL_Pos (16U)
#define RTC_TAFCR_TAMPINSEL_Msk (0x1U << RTC_TAFCR_TAMPINSEL_Pos) /*!< 0x00010000 */
#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMPINSEL_Msk
#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
@ -12096,6 +12144,9 @@ typedef struct
#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
/* Legacy defines */
#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMASSR_MASKSS_Pos (24U)
#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
@ -12219,6 +12270,9 @@ typedef struct
#define RTC_BKP19R_Pos (0U)
#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
#define RTC_BKP19R RTC_BKP19R_Msk
/******************** Number of backup registers ******************************/
#define RTC_BKP_NUMBER 0x000000014U
/******************************************************************************/
/* */
@ -12554,10 +12608,10 @@ typedef struct
#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
#define SDIO_CMD_NIEN_Pos (13U)
#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
#define SDIO_CMD_CEATACMD_Pos (14U)
#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
/***************** Bit definition for SDIO_RESPCMD register *****************/
#define SDIO_RESPCMD_RESPCMD_Pos (0U)
@ -12843,11 +12897,8 @@ typedef struct
/* Serial Peripheral Interface */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
*/
#define SPI_I2S_SUPPORT /*!< I2S support */
#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_CPHA_Pos (0U)
#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
@ -13792,9 +13843,9 @@ typedef struct
#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
#define TIM_CNT_CNT_Pos (0U)
#define TIM_CNT_CNT_Msk (0xFFFFU << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
#define TIM_CNT_CNT_Pos (0U)
#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
/******************* Bit definition for TIM_PSC register ********************/
#define TIM_PSC_PSC_Pos (0U)
@ -13803,7 +13854,7 @@ typedef struct
/******************* Bit definition for TIM_ARR register ********************/
#define TIM_ARR_ARR_Pos (0U)
#define TIM_ARR_ARR_Msk (0xFFFFU << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
@ -13894,6 +13945,12 @@ typedef struct
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
/******************* Bit definition for TIM_OR register *********************/
#define TIM_OR_TI1_RMP_Pos (0U)
#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
#define TIM_OR_TI4_RMP_Pos (6U)
#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
@ -14505,9 +14562,9 @@ typedef struct
#define ETH_MACDBGR_TFNE_Pos (24U)
#define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
#define ETH_MACDBGR_TPWA_Pos (22U)
#define ETH_MACDBGR_TPWA_Msk (0x1U << ETH_MACDBGR_TPWA_Pos) /*!< 0x00400000 */
#define ETH_MACDBGR_TPWA ETH_MACDBGR_TPWA_Msk /* Tx FIFO write active */
#define ETH_MACDBGR_TFWA_Pos (22U)
#define ETH_MACDBGR_TFWA_Msk (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
#define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
#define ETH_MACDBGR_TFRS_Pos (20U)
#define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
@ -15403,10 +15460,11 @@ typedef struct
#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
@ -16539,6 +16597,10 @@ typedef struct
((INSTANCE) == ADC2) || \
((INSTANCE) == ADC3))
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
/******************************* CAN Instances ********************************/
#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
((INSTANCE) == CAN2))
@ -16594,12 +16656,15 @@ typedef struct
#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
/*************************** I2S Extended Instances ***************************/
#define IS_I2S_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == I2S2ext)|| \
#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
((INSTANCE) == I2S3ext))
/* Legacy Defines */
#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
@ -16727,15 +16792,13 @@ typedef struct
/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM9) || \
((INSTANCE) == TIM12))
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8))
/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
@ -16834,27 +16897,109 @@ typedef struct
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3))))
/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM9) || \
((INSTANCE) == TIM10)|| \
((INSTANCE) == TIM11)|| \
((INSTANCE) == TIM12)|| \
((INSTANCE) == TIM13)|| \
((INSTANCE) == TIM14))
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM9) || \
((INSTANCE) == TIM12))
/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM9) || \
((INSTANCE) == TIM12))
/****************** TIM Instances : supporting Hall sensor interface **********/
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == USART6))
/******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8))
/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8))
/* Legacy defines */
#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == USART6))
/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
/********************* UART Instances : Smart card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
@ -16895,6 +17040,12 @@ typedef struct
#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
/*
* @brief Specific devices reset values definitions
*/
#define RCC_PLLCFGR_RST_VALUE 0x24003010U
#define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
#define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
#define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
@ -16928,7 +17079,6 @@ typedef struct
#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
/******************************************************************************/
/* For a painless codes migration between the STM32F4xx device product */
/* lines, the aliases defined below are put in place to overcome the */
@ -16941,6 +17091,7 @@ typedef struct
/* Aliases for __IRQHandler */
#define FSMC_IRQHandler FMC_IRQHandler
/**
* @}
*/

12
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f4xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.6.0
* @date 04-November-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -124,11 +124,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS version number V2.5.0
* @brief CMSIS version number V2.6.1
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/system_stm32f4xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -75,6 +75,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

18
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/system_stm32f4xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -38,7 +38,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -157,7 +157,7 @@
*/
uint32_t SystemCoreClock = 168000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -321,8 +321,8 @@ void SystemCoreClockUpdate(void)
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
@ -797,7 +797,7 @@ void SetSysClock(void)
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
@ -835,7 +835,7 @@ void SetSysClock(void)
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
@ -849,7 +849,7 @@ void SetSysClock(void)
RCC_OscInitStruct.PLL.PLLQ = 7;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
HAL_PWREx_ActivateOverDrive();
HAL_PWREx_EnableOverDrive();
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
|RCC_CLOCKTYPE_PCLK2;

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/hal_tick.h
View File

@ -44,10 +44,10 @@
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

20383
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f439xx.h
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File diff suppressed because it is too large Load Diff

21
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f4xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -79,7 +79,7 @@
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
!defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
!defined (STM32F412Zx)
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -106,6 +106,9 @@
/* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
/* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
/* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -121,11 +124,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS version number V2.5.0
* @brief CMSIS version number V2.6.1
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@ -182,6 +185,10 @@
#include "stm32f412rx.h"
#elif defined(STM32F412Vx)
#include "stm32f412vx.h"
#elif defined(STM32F413xx)
#include "stm32f413xx.h"
#elif defined(STM32F423xx)
#include "stm32f423xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/system_stm32f4xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -75,6 +75,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

18
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_stm32f4xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -38,7 +38,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -159,7 +159,7 @@
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -327,8 +327,8 @@ void SystemCoreClockUpdate(void)
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
@ -867,7 +867,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
}
// Activate the OverDrive to reach the 180 MHz Frequency
if (HAL_PWREx_ActivateOverDrive() != HAL_OK)
if (HAL_PWREx_EnableOverDrive() != HAL_OK)
{
return 0; // FAIL
}
@ -876,8 +876,8 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLSAIP;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers

18
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_stm32f4xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -40,7 +40,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -159,7 +159,7 @@
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -327,8 +327,8 @@ void SystemCoreClockUpdate(void)
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
@ -867,7 +867,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
}
// Activate the OverDrive to reach the 180 MHz Frequency
if (HAL_PWREx_ActivateOverDrive() != HAL_OK)
if (HAL_PWREx_EnableOverDrive() != HAL_OK)
{
return 0; // FAIL
}
@ -876,8 +876,8 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLSAIP;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers

18
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/system_stm32f4xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -40,7 +40,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -159,7 +159,7 @@
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -327,8 +327,8 @@ void SystemCoreClockUpdate(void)
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
@ -867,7 +867,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
}
// Activate the OverDrive to reach the 180 MHz Frequency
if (HAL_PWREx_ActivateOverDrive() != HAL_OK)
if (HAL_PWREx_EnableOverDrive() != HAL_OK)
{
return 0; // FAIL
}
@ -876,8 +876,8 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLSAIP;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/hal_tick.h
View File

@ -44,10 +44,10 @@
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

18637
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/stm32f446xx.h
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File diff suppressed because it is too large Load Diff

21
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/stm32f4xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -79,7 +79,7 @@
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
!defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
!defined (STM32F412Zx)
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -106,6 +106,9 @@
/* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
/* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
/* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -121,11 +124,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS version number V2.5.0
* @brief CMSIS version number V2.6.1
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@ -182,6 +185,10 @@
#include "stm32f412rx.h"
#elif defined(STM32F412Vx)
#include "stm32f412vx.h"
#elif defined(STM32F413xx)
#include "stm32f413xx.h"
#elif defined(STM32F423xx)
#include "stm32f423xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/system_stm32f4xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -75,6 +75,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

18
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/system_stm32f4xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -38,7 +38,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -156,7 +156,7 @@
*/
uint32_t SystemCoreClock = 168000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -320,8 +320,8 @@ void SystemCoreClockUpdate(void)
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
@ -796,7 +796,7 @@ void SystemClock_Config(void)
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
@ -833,7 +833,7 @@ void SystemClock_Config(void)
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
@ -849,7 +849,7 @@ void SystemClock_Config(void)
HAL_RCC_OscConfig(&RCC_OscInitStruct);
HAL_PWREx_ActivateOverDrive();
HAL_PWREx_EnableOverDrive();
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
|RCC_CLOCKTYPE_PCLK2;

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/hal_tick.h
View File

@ -44,10 +44,10 @@
#define TIM_MST TIM2
#define TIM_MST_IRQ TIM2_IRQn
#define TIM_MST_RCC __TIM2_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM2_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

23803
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f469xx.h
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File diff suppressed because it is too large Load Diff

21
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f4xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -79,7 +79,7 @@
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
!defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
!defined (STM32F412Zx)
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -106,6 +106,9 @@
/* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
/* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
/* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -121,11 +124,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS version number V2.5.0
* @brief CMSIS version number V2.6.1
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@ -182,6 +185,10 @@
#include "stm32f412rx.h"
#elif defined(STM32F412Vx)
#include "stm32f412vx.h"
#elif defined(STM32F413xx)
#include "stm32f413xx.h"
#elif defined(STM32F423xx)
#include "stm32f423xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/system_stm32f4xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -75,6 +75,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/device/hal_tick.h
View File

@ -44,10 +44,10 @@
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

20381
targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/device/stm32f439xx.h
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21
targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/device/stm32f4xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -79,7 +79,7 @@
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
!defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
!defined (STM32F412Zx)
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -106,6 +106,9 @@
/* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
/* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
/* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -121,11 +124,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS version number V2.5.0
* @brief CMSIS version number V2.6.1
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@ -182,6 +185,10 @@
#include "stm32f412rx.h"
#elif defined(STM32F412Vx)
#include "stm32f412vx.h"
#elif defined(STM32F413xx)
#include "stm32f413xx.h"
#elif defined(STM32F423xx)
#include "stm32f423xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/device/system_stm32f4xx.c
View File

@ -157,7 +157,7 @@
*/
uint32_t SystemCoreClock = 168000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -795,7 +795,7 @@ void SetSysClock(void)
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
@ -833,7 +833,7 @@ void SetSysClock(void)
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
@ -847,7 +847,7 @@ void SetSysClock(void)
RCC_OscInitStruct.PLL.PLLQ = 7;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
HAL_PWREx_ActivateOverDrive();
HAL_PWREx_EnableOverDrive();
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
|RCC_CLOCKTYPE_PCLK2;

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/device/system_stm32f4xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V2.5.0
* @date 22-April-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -75,6 +75,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

10
targets/TARGET_STM/TARGET_STM32F4/analogin_api.c
View File

@ -82,28 +82,28 @@ void analogin_init(analogin_t *obj, PinName pin)
#if defined(ADC1)
if ((obj->adc == ADC_1) && adc1_inited) return;
if (obj->adc == ADC_1) {
__ADC1_CLK_ENABLE();
__HAL_RCC_ADC1_CLK_ENABLE();
adc1_inited = 1;
}
#endif
#if defined(ADC2)
if ((obj->adc == ADC_2) && adc2_inited) return;
if (obj->adc == ADC_2) {
__ADC2_CLK_ENABLE();
__HAL_RCC_ADC2_CLK_ENABLE();
adc2_inited = 1;
}
#endif
#if defined(ADC3)
if ((obj->adc == ADC_3) && adc3_inited) return;
if (obj->adc == ADC_3) {
__ADC3_CLK_ENABLE();
__HAL_RCC_ADC3_CLK_ENABLE();
adc3_inited = 1;
}
#endif
// Configure ADC
AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
AdcHandle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV2;
AdcHandle.Init.Resolution = ADC_RESOLUTION12b;
AdcHandle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
AdcHandle.Init.Resolution = ADC_RESOLUTION_12B;
AdcHandle.Init.ScanConvMode = DISABLE;
AdcHandle.Init.ContinuousConvMode = DISABLE;
AdcHandle.Init.DiscontinuousConvMode = DISABLE;

4
targets/TARGET_STM/TARGET_STM32F4/analogout_api.c
View File

@ -60,9 +60,9 @@ void analogout_init(dac_t *obj, PinName pin) {
// Configure GPIO
pinmap_pinout(pin, PinMap_DAC);
__GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__DAC_CLK_ENABLE();
__HAL_RCC_DAC_CLK_ENABLE();
DacHandle.Instance = DAC;

345
targets/TARGET_STM/TARGET_STM32F4/device/Release_Notes_stm32f4xx_hal.html
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File diff suppressed because one or more lines are too long

202
targets/TARGET_STM/TARGET_STM32F4/device/stm32_hal_legacy.h
View File

@ -2,14 +2,14 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version V1.5.0
* @date 06-May-2016
* @version V1.7.1
* @date 14-April-2017
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -138,6 +138,7 @@
#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
@ -150,6 +151,9 @@
#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
@ -160,8 +164,16 @@
#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
#if defined(STM32L0)
/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
/* to the second dedicated IO (only for COMP2). */
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
#else
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
#endif
#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
@ -229,9 +241,9 @@
#define DAC1_CHANNEL_1 DAC_CHANNEL_1
#define DAC1_CHANNEL_2 DAC_CHANNEL_2
#define DAC2_CHANNEL_1 DAC_CHANNEL_1
#define DAC_WAVE_NONE ((uint32_t)0x00000000U)
#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
#define DAC_WAVE_NONE 0x00000000U
#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
@ -344,6 +356,7 @@
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
/**
* @}
*/
@ -369,7 +382,7 @@
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{
*/
#if defined(STM32L4) || defined(STM32F7)
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
@ -841,6 +854,8 @@
#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
#define __DIV_LPUART UART_DIV_LPUART
#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
@ -902,48 +917,45 @@
#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
#define ETH_MMCCR ((uint32_t)0x00000100U)
#define ETH_MMCRIR ((uint32_t)0x00000104U)
#define ETH_MMCTIR ((uint32_t)0x00000108U)
#define ETH_MMCRIMR ((uint32_t)0x0000010CU)
#define ETH_MMCTIMR ((uint32_t)0x00000110U)
#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
#define ETH_MMCCR 0x00000100U
#define ETH_MMCRIR 0x00000104U
#define ETH_MMCTIR 0x00000108U
#define ETH_MMCRIMR 0x0000010CU
#define ETH_MMCTIMR 0x00000110U
#define ETH_MMCTGFSCCR 0x0000014CU
#define ETH_MMCTGFMSCCR 0x00000150U
#define ETH_MMCTGFCR 0x00000168U
#define ETH_MMCRFCECR 0x00000194U
#define ETH_MMCRFAECR 0x00000198U
#define ETH_MMCRGUFCR 0x000001C4U
#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#endif
#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
/**
* @}
@ -965,7 +977,7 @@
* @}
*/
#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{
@ -990,7 +1002,7 @@
/**
* @}
*/
#endif /* STM32L4xx || STM32F7*/
#endif /* STM32L4 || STM32F7*/
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
@ -1175,6 +1187,9 @@
* @{
*/
#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
#define HAL_LTDC_Relaod HAL_LTDC_Reload
#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
/**
* @}
*/
@ -1610,7 +1625,11 @@
#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
#if defined(STM32F1)
#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
#else
#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
#endif /* STM32F1 */
#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
@ -2216,26 +2235,26 @@
#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
@ -2637,10 +2656,22 @@
#define RCC_IT_HSI14 RCC_IT_HSI14RDY
#if defined(STM32L0)
#define RCC_IT_LSECSS RCC_IT_CSSLSE
#define RCC_IT_CSS RCC_IT_CSSHSE
#endif
#define RCC_IT_CSSLSE RCC_IT_LSECSS
#define RCC_IT_CSSHSE RCC_IT_CSS
#define RCC_PLLMUL_3 RCC_PLL_MUL3
#define RCC_PLLMUL_4 RCC_PLL_MUL4
#define RCC_PLLMUL_6 RCC_PLL_MUL6
#define RCC_PLLMUL_8 RCC_PLL_MUL8
#define RCC_PLLMUL_12 RCC_PLL_MUL12
#define RCC_PLLMUL_16 RCC_PLL_MUL16
#define RCC_PLLMUL_24 RCC_PLL_MUL24
#define RCC_PLLMUL_32 RCC_PLL_MUL32
#define RCC_PLLMUL_48 RCC_PLL_MUL48
#define RCC_PLLDIV_2 RCC_PLL_DIV2
#define RCC_PLLDIV_3 RCC_PLL_DIV3
#define RCC_PLLDIV_4 RCC_PLL_DIV4
#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
@ -2757,10 +2788,22 @@
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
#define DfsdmClockSelection Dfsdm1ClockSelection
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
/**
* @}
@ -2891,6 +2934,14 @@
#define SDIO_IRQn SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler
#endif
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
/**
* @}
*/
@ -3079,6 +3130,7 @@
* @{
*/
#define __HAL_LTDC_LAYER LTDC_LAYER
#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
/**
* @}
*/

54
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal.c
* @author MCD Application Team
* @version V1.5.0
* @date 06-May-2016
* @version V1.7.1
* @date 14-April-2017
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@ -23,7 +23,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -68,18 +68,18 @@
* @{
*/
/**
* @brief STM32F4xx HAL Driver version number V1.5.0
* @brief STM32F4xx HAL Driver version number V1.7.1
*/
#define __STM32F4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F4xx_HAL_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
#define __STM32F4xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
#define __STM32F4xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
|(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\
|(__STM32F4xx_HAL_VERSION_RC))
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFFU)
#define IDCODE_DEVID_MASK 0x00000FFFU
/* ------------ RCC registers bit address in the alias region ----------- */
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
@ -94,6 +94,12 @@
#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20U)
#define CMP_PD_BIT_NUMBER POSITION_VAL(SYSCFG_CMPCR_CMP_PD)
#define CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U))
/* --- MCHDLYCR Register ---*/
/* Alias word address of BSCKSEL bit */
#define MCHDLYCR_OFFSET (SYSCFG_OFFSET + 0x30U)
#define BSCKSEL_BIT_NUMBER POSITION_VAL(SYSCFG_MCHDLYCR_BSCKSEL)
#define MCHDLYCR_BSCKSEL_BB (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32U) + (BSCKSEL_BIT_NUMBER * 4U))
/**
* @}
*/
@ -263,7 +269,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
HAL_SYSTICK_Config(SystemCoreClock/1000U);
/*Configure the SysTick IRQ priority */
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
/* Return function status */
return HAL_OK;
@ -322,7 +328,7 @@ __weak uint32_t HAL_GetTick(void)
}
/**
* @brief This function provides accurate delay (in milliseconds) based
* @brief This function provides minimum delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
@ -334,9 +340,16 @@ __weak uint32_t HAL_GetTick(void)
*/
__weak void HAL_Delay(__IO uint32_t Delay)
{
uint32_t tickstart = 0U;
tickstart = HAL_GetTick();
while((HAL_GetTick() - tickstart) < Delay)
uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay;
/* Add a period to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
{
wait++;
}
while((HAL_GetTick() - tickstart) < wait)
{
}
}
@ -476,6 +489,18 @@ void HAL_DisableCompensationCell(void)
*(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE;
}
/**
* @brief Return the unique device identifier (UID based on 96 bits)
* @param UID: pointer to 3 words array.
* @retval Device identifier
*/
void HAL_GetUID(uint32_t *UID)
{
UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE)));
UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
}
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
/**
@ -509,7 +534,6 @@ void HAL_DisableMemorySwappingBank(void)
*(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE;
}
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
/**
* @}
*/

14
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.h
View File

@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_hal.h
* @author MCD Application Team
* @version V1.5.0
* @date 06-May-2016
* @version V1.7.1
* @date 14-April-2017
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -57,6 +57,7 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup HAL_Exported_Macros HAL Exported Macros
* @{
@ -149,7 +150,7 @@
}while(0);
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
* @{
*/
@ -163,7 +164,7 @@
/**
* @}
*/
/** @defgroup PVD_Lock_Enable PVD Lock
* @{
*/
@ -177,7 +178,7 @@
/**
* @}
*/
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
/**
* @}
*/
@ -220,6 +221,7 @@ void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);
void HAL_EnableCompensationCell(void);
void HAL_DisableCompensationCell(void);
void HAL_GetUID(uint32_t *UID);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
void HAL_EnableMemorySwappingBank(void);

65
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc.c
* @author MCD Application Team
* @version V1.5.0
* @date 06-May-2016
* @version V1.7.1
* @date 14-April-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and de-initialization functions
@ -164,7 +164,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -437,6 +437,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
__IO uint32_t counter = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@ -489,19 +490,24 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
@ -728,6 +734,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
{
__IO uint32_t counter = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@ -781,12 +788,17 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
@ -795,7 +807,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
__HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
@ -1013,6 +1025,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
__IO uint32_t counter = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@ -1066,12 +1079,17 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
@ -1099,7 +1117,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
@ -1279,6 +1297,7 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
__IO uint32_t counter = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
@ -1333,19 +1352,24 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
}
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* if ADC1 Channel_18 is selected enable VBAT Channel */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
{
/* Enable the VBAT channel*/
ADC->CCR |= ADC_CCR_VBATE;
tmpADC_Common->CCR |= ADC_CCR_VBATE;
}
/* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
{
/* Enable the TSVREFE channel*/
ADC->CCR |= ADC_CCR_TSVREFE;
tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
{
@ -1498,10 +1522,17 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
*/
static void ADC_Init(ADC_HandleTypeDef* hadc)
{
ADC_Common_TypeDef *tmpADC_Common;
/* Set ADC parameters */
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Set the ADC clock prescaler */
ADC->CCR &= ~(ADC_CCR_ADCPRE);
ADC->CCR |= hadc->Init.ClockPrescaler;
tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE);
tmpADC_Common->CCR |= hadc->Init.ClockPrescaler;
/* Set ADC scan mode */
hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);

102
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_adc.h
* @author MCD Application Team
* @version V1.5.0
* @date 06-May-2016
* @version V1.7.1
* @date 14-April-2017
* @brief Header file containing functions prototypes of ADC HAL library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -172,34 +172,34 @@ typedef struct
* @brief HAL ADC state machine: ADC states definition (bitfields)
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */
#define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */
/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */
#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */
/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Overrun occurrence */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3 */
#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3 */
/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */
#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */
/**
@ -233,11 +233,11 @@ typedef struct
/** @defgroup ADC_Error_Code ADC Error Code
* @{
*/
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking,
enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */
#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */
#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking,
enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */
#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */
/**
* @}
*/
@ -246,7 +246,7 @@ typedef struct
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
* @{
*/
#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U)
#define ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U
#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
@ -257,7 +257,7 @@ typedef struct
/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
* @{
*/
#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U)
#define ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U
#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
@ -280,7 +280,7 @@ typedef struct
/** @defgroup ADC_Resolution ADC Resolution
* @{
*/
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U)
#define ADC_RESOLUTION_12B 0x00000000U
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
@ -291,7 +291,7 @@ typedef struct
/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
* @{
*/
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
@ -304,7 +304,7 @@ typedef struct
*/
/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
/* compatibility with other STM32 devices. */
#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGCONV_T1_CC1 0x00000000U
#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
@ -328,7 +328,7 @@ typedef struct
/** @defgroup ADC_Data_align ADC Data Align
* @{
*/
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
#define ADC_DATAALIGN_RIGHT 0x00000000U
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
/**
* @}
@ -337,7 +337,7 @@ typedef struct
/** @defgroup ADC_channels ADC Common Channels
* @{
*/
#define ADC_CHANNEL_0 ((uint32_t)0x00000000U)
#define ADC_CHANNEL_0 0x00000000U
#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
@ -366,7 +366,7 @@ typedef struct
/** @defgroup ADC_sampling_times ADC Sampling Times
* @{
*/
#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U)
#define ADC_SAMPLETIME_3CYCLES 0x00000000U
#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
@ -381,9 +381,9 @@ typedef struct
/** @defgroup ADC_EOCSelection ADC EOC Selection
* @{
*/
#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U)
#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U)
#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U) /*!< reserved for future use */
#define ADC_EOC_SEQ_CONV 0x00000000U
#define ADC_EOC_SINGLE_CONV 0x00000001U
#define ADC_EOC_SINGLE_SEQ_CONV 0x00000002U /*!< reserved for future use */
/**
* @}
*/
@ -406,7 +406,7 @@ typedef struct
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U)
#define ADC_ANALOGWATCHDOG_NONE 0x00000000U
/**
* @}
*/
@ -438,9 +438,9 @@ typedef struct
/** @defgroup ADC_channels_type ADC Channels Type
* @{
*/
#define ADC_ALL_CHANNELS ((uint32_t)0x00000001U)
#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U) /*!< reserved for future use */
#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */
#define ADC_ALL_CHANNELS 0x00000001U
#define ADC_REGULAR_CHANNELS 0x00000002U /*!< reserved for future use */
#define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */
/**
* @}
*/
@ -597,11 +597,11 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/* Delay for ADC stabilization time. */
/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
/* Unit: us */
#define ADC_STAB_DELAY_US ((uint32_t) 3U)
#define ADC_STAB_DELAY_US 3U
/* Delay for temperature sensor stabilization time. */
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
/* Unit: us */
#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U)
#define ADC_TEMPSENSOR_DELAY_US 10U
/**
* @}
*/
@ -729,16 +729,16 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFFU))
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU)
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U)))
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)16U)))
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1U)) && ((NUMBER) <= ((uint32_t)8U)))
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= (16U)))
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFFU))) || \
(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FFU))) || \
(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FFU))) || \
(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003FU))))
((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \
(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \
(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= 0x00FFU)) || \
(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= 0x003FU)))
/**
* @brief Set ADC Regular channel sequence length.

97
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc_ex.c
* @author MCD Application Team
* @version V1.5.0
* @date 06-May-2016
* @version V1.7.1
* @date 14-April-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions
@ -86,7 +86,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -178,6 +178,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
{
__IO uint32_t counter = 0U;
uint32_t tmp1 = 0U, tmp2 = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Process locked */
__HAL_LOCK(hadc);
@ -228,9 +229,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
/* Clear injected group conversion flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
@ -267,6 +273,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
{
__IO uint32_t counter = 0U;
uint32_t tmp1 = 0U, tmp2 = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Process locked */
__HAL_LOCK(hadc);
@ -320,9 +327,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
/* Enable end of conversion interrupt for injected channels */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
@ -597,6 +609,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
__IO uint32_t counter = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@ -674,20 +687,25 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
if (hadc->Init.DMAContinuousRequests != DISABLE)
{
/* Enable the selected ADC DMA request after last transfer */
ADC->CCR |= ADC_CCR_DDS;
tmpADC_Common->CCR |= ADC_CCR_DDS;
}
else
{
/* Disable the selected ADC EOC rising on each regular channel conversion */
ADC->CCR &= ~ADC_CCR_DDS;
tmpADC_Common->CCR &= ~ADC_CCR_DDS;
}
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
@ -710,6 +728,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -720,12 +739,17 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Check if ADC is effectively disabled */
if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Disable the selected ADC DMA mode for multimode */
ADC->CCR &= ~ADC_CCR_DDS;
tmpADC_Common->CCR &= ~ADC_CCR_DDS;
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
/* DMA transfer is on going) */
@ -756,8 +780,15 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
*/
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
{
ADC_Common_TypeDef *tmpADC_Common;
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Return the multi mode conversion value */
return ADC->CDR;
return tmpADC_Common->CDR;
}
/**
@ -788,8 +819,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
#ifdef USE_FULL_ASSERT
uint32_t tmp = 0U;
#endif /* USE_FULL_ASSERT */
#endif /* USE_FULL_ASSERT */
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
@ -804,7 +838,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
#endif /* USE_FULL_ASSERT */
if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
}
@ -909,19 +943,24 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
break;
}
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* if ADC1 Channel_18 is selected enable VBAT Channel */
if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))
{
/* Enable the VBAT channel*/
ADC->CCR |= ADC_CCR_VBATE;
tmpADC_Common->CCR |= ADC_CCR_VBATE;
}
/* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))
{
/* Enable the TSVREFE channel*/
ADC->CCR |= ADC_CCR_TSVREFE;
tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
}
/* Process unlocked */
@ -941,6 +980,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
{
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_ADC_MODE(multimode->Mode));
assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
@ -948,18 +990,23 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
/* Process locked */
__HAL_LOCK(hadc);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Set ADC mode */
ADC->CCR &= ~(ADC_CCR_MULTI);
ADC->CCR |= multimode->Mode;
tmpADC_Common->CCR &= ~(ADC_CCR_MULTI);
tmpADC_Common->CCR |= multimode->Mode;
/* Set the ADC DMA access mode */
ADC->CCR &= ~(ADC_CCR_DMA);
ADC->CCR |= multimode->DMAAccessMode;
tmpADC_Common->CCR &= ~(ADC_CCR_DMA);
tmpADC_Common->CCR |= multimode->DMAAccessMode;
/* Set delay between two sampling phases */
ADC->CCR &= ~(ADC_CCR_DELAY);
ADC->CCR |= multimode->TwoSamplingDelay;
tmpADC_Common->CCR &= ~(ADC_CCR_DELAY);
tmpADC_Common->CCR |= multimode->TwoSamplingDelay;
/* Process unlocked */
__HAL_UNLOCK(hadc);

51
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_adc_ex.h
* @author MCD Application Team
* @version V1.5.0
* @date 06-May-2016
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -152,7 +152,7 @@ typedef struct
/** @defgroup ADCEx_Common_mode ADC Common Mode
* @{
*/
#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000U)
#define ADC_MODE_INDEPENDENT 0x00000000U
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
@ -172,7 +172,7 @@ typedef struct
/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
* @{
*/
#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000U) /*!< DMA mode disabled */
#define ADC_DMAACCESSMODE_DISABLED 0x00000000U /*!< DMA mode disabled */
#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
@ -183,7 +183,7 @@ typedef struct
/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
* @{
*/
#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE 0x00000000U
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
@ -194,7 +194,7 @@ typedef struct
/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
* @{
*/
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 0x00000000U
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0)
#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1)
#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
@ -218,10 +218,10 @@ typedef struct
/** @defgroup ADCEx_injected_rank ADC Injected Rank
* @{
*/
#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U)
#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002U)
#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003U)
#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004U)
#define ADC_INJECTED_RANK_1 0x00000001U
#define ADC_INJECTED_RANK_2 0x00000002U
#define ADC_INJECTED_RANK_3 0x00000003U
#define ADC_INJECTED_RANK_4 0x00000004U
/**
* @}
*/
@ -232,13 +232,14 @@ typedef struct
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
defined(STM32F412Cx)
defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cxs */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412Zx ||
STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
#if defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT ((uint32_t)0x10000000U) /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
#endif /* STM32F411xE || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
@ -257,7 +258,7 @@ typedef struct
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
/**
* @brief Disable internal path of ADC channel Vbat
* @Note Use case of this macro:
* @note Use case of this macro:
* On devices STM32F42x and STM32F43x, ADC internal channels
* Vbat and VrefInt share the same internal path, only
* one of them can be enabled.This macro is to be used when ADC
@ -322,9 +323,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||
STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@ -370,8 +372,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \
((INJTRIG) == ADC_INJECTED_SOFTWARE_START))
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)4U)))
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)4U)))
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= 4U))
/**
* @brief Set the selected injected Channel rank.
@ -382,6 +384,17 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
*/
#define ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_))))
/**
* @brief Defines if the selected ADC is within ADC common register ADC123 or ADC1
* if available (ADC2, ADC3 availability depends on STM32 product)
* @param __HANDLE__: ADC handle
* @retval Common control register ADC123 or ADC1
*/
#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define ADC_COMMON_REGISTER(__HANDLE__) ADC123_COMMON
#else
#define ADC_COMMON_REGISTER(__HANDLE__) ADC1_COMMON
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx || STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/

801
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.c
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File diff suppressed because it is too large Load Diff

166
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_can.h
* @author MCD Application Team
* @version V1.5.0
* @date 06-May-2016
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -45,8 +45,9 @@
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
defined(STM32F423xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@ -72,9 +73,13 @@ typedef enum
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX = 0x22U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX = 0x32U, /*!< CAN process is ongoing */
HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
}HAL_CAN_StateTypeDef;
@ -127,21 +132,21 @@ typedef struct
{
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
@ -172,7 +177,7 @@ typedef struct
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFFU */
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
This parameter can be a value of @ref CAN_Identifier_Type */
@ -197,7 +202,7 @@ typedef struct
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFFU */
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
This parameter can be a value of @ref CAN_Identifier_Type */
@ -230,7 +235,9 @@ typedef struct
CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
@ -249,19 +256,22 @@ typedef struct
* @{
*/
/** @defgroup HAL_CAN_Error_Code HAL CAN Error Code
/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
#define HAL_CAN_ERROR_NONE 0x00U /*!< No error */
#define HAL_CAN_ERROR_EWG 0x01U /*!< EWG error */
#define HAL_CAN_ERROR_EPV 0x02U /*!< EPV error */
#define HAL_CAN_ERROR_BOF 0x04U /*!< BOF error */
#define HAL_CAN_ERROR_STF 0x08U /*!< Stuff error */
#define HAL_CAN_ERROR_FOR 0x10U /*!< Form error */
#define HAL_CAN_ERROR_ACK 0x20U /*!< Acknowledgment error */
#define HAL_CAN_ERROR_BR 0x40U /*!< Bit recessive */
#define HAL_CAN_ERROR_BD 0x80U /*!< LEC dominant */
#define HAL_CAN_ERROR_CRC 0x100U /*!< LEC transfer error */
#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
/**
* @}
*/
@ -269,8 +279,8 @@ typedef struct
/** @defgroup CAN_InitStatus CAN InitStatus
* @{
*/
#define CAN_INITSTATUS_FAILED ((uint8_t)0x00U) /*!< CAN initialization failed */
#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01U) /*!< CAN initialization OK */
#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */
#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */
/**
* @}
*/
@ -278,7 +288,7 @@ typedef struct
/** @defgroup CAN_operating_mode CAN Operating Mode
* @{
*/
#define CAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
@ -289,7 +299,7 @@ typedef struct
/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
* @{
*/
#define CAN_SJW_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
@ -300,7 +310,7 @@ typedef struct
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
* @{
*/
#define CAN_BS1_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
@ -323,7 +333,7 @@ typedef struct
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
* @{
*/
#define CAN_BS2_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
@ -338,8 +348,8 @@ typedef struct
/** @defgroup CAN_filter_mode CAN Filter Mode
* @{
*/
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
/**
* @}
*/
@ -347,8 +357,8 @@ typedef struct
/** @defgroup CAN_filter_scale CAN Filter Scale
* @{
*/
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
/**
* @}
*/
@ -356,8 +366,8 @@ typedef struct
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */
#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
/**
* @}
*/
@ -365,8 +375,8 @@ typedef struct
/** @defgroup CAN_Identifier_Type CAN Identifier Type
* @{
*/
#define CAN_ID_STD ((uint32_t)0x00000000U) /*!< Standard Id */
#define CAN_ID_EXT ((uint32_t)0x00000004U) /*!< Extended Id */
#define CAN_ID_STD 0x00000000U /*!< Standard Id */
#define CAN_ID_EXT 0x00000004U /*!< Extended Id */
/**
* @}
*/
@ -374,8 +384,8 @@ typedef struct
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{
*/
#define CAN_RTR_DATA ((uint32_t)0x00000000U) /*!< Data frame */
#define CAN_RTR_REMOTE ((uint32_t)0x00000002U) /*!< Remote frame */
#define CAN_RTR_DATA 0x00000000U /*!< Data frame */
#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */
/**
* @}
*/
@ -383,8 +393,8 @@ typedef struct
/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
* @{
*/
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
/**
* @}
*/
@ -398,37 +408,37 @@ typedef struct
CAN_GetFlagStatus() function. */
/* Transmit Flags */
#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500U) /*!< Request MailBox0 flag */
#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508U) /*!< Request MailBox1 flag */
#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510U) /*!< Request MailBox2 flag */
#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501U) /*!< Transmission OK MailBox0 flag */
#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509U) /*!< Transmission OK MailBox1 flag */
#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511U) /*!< Transmission OK MailBox2 flag */
#define CAN_FLAG_TME0 ((uint32_t)0x0000051AU) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME1 ((uint32_t)0x0000051BU) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME2 ((uint32_t)0x0000051CU) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_RQCP0 0x00000500U /*!< Request MailBox0 flag */
#define CAN_FLAG_RQCP1 0x00000508U /*!< Request MailBox1 flag */
#define CAN_FLAG_RQCP2 0x00000510U /*!< Request MailBox2 flag */
#define CAN_FLAG_TXOK0 0x00000501U /*!< Transmission OK MailBox0 flag */
#define CAN_FLAG_TXOK1 0x00000509U /*!< Transmission OK MailBox1 flag */
#define CAN_FLAG_TXOK2 0x00000511U /*!< Transmission OK MailBox2 flag */
#define CAN_FLAG_TME0 0x0000051AU /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME1 0x0000051BU /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME2 0x0000051CU /*!< Transmit mailbox 0 empty flag */
/* Receive Flags */
#define CAN_FLAG_FF0 ((uint32_t)0x00000203U) /*!< FIFO 0 Full flag */
#define CAN_FLAG_FOV0 ((uint32_t)0x00000204U) /*!< FIFO 0 Overrun flag */
#define CAN_FLAG_FF0 0x00000203U /*!< FIFO 0 Full flag */
#define CAN_FLAG_FOV0 0x00000204U /*!< FIFO 0 Overrun flag */
#define CAN_FLAG_FF1 ((uint32_t)0x00000403U) /*!< FIFO 1 Full flag */
#define CAN_FLAG_FOV1 ((uint32_t)0x00000404U) /*!< FIFO 1 Overrun flag */
#define CAN_FLAG_FF1 0x00000403U /*!< FIFO 1 Full flag */
#define CAN_FLAG_FOV1 0x00000404U /*!< FIFO 1 Overrun flag */
/* Operating Mode Flags */
#define CAN_FLAG_INAK ((uint32_t)0x00000100U) /*!< Initialization acknowledge flag */
#define CAN_FLAG_SLAK ((uint32_t)0x00000101U) /*!< Sleep acknowledge flag */
#define CAN_FLAG_ERRI ((uint32_t)0x00000102U) /*!< Error flag */
#define CAN_FLAG_WKU ((uint32_t)0x00000103U) /*!< Wake up flag */
#define CAN_FLAG_SLAKI ((uint32_t)0x00000104U) /*!< Sleep acknowledge flag */
#define CAN_FLAG_INAK 0x00000100U /*!< Initialization acknowledge flag */
#define CAN_FLAG_SLAK 0x00000101U /*!< Sleep acknowledge flag */
#define CAN_FLAG_ERRI 0x00000102U /*!< Error flag */
#define CAN_FLAG_WKU 0x00000103U /*!< Wake up flag */
#define CAN_FLAG_SLAKI 0x00000104U /*!< Sleep acknowledge flag */
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
In this case the SLAK bit can be polled.*/
/* Error Flags */
#define CAN_FLAG_EWG ((uint32_t)0x00000300U) /*!< Error warning flag */
#define CAN_FLAG_EPV ((uint32_t)0x00000301U) /*!< Error passive flag */
#define CAN_FLAG_BOF ((uint32_t)0x00000302U) /*!< Bus-Off flag */
#define CAN_FLAG_EWG 0x00000300U /*!< Error warning flag */
#define CAN_FLAG_EPV 0x00000301U /*!< Error passive flag */
#define CAN_FLAG_BOF 0x00000302U /*!< Bus-Off flag */
/**
* @}
*/
@ -463,9 +473,9 @@ typedef struct
/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
* @{
*/
#define CAN_TXMAILBOX_0 ((uint8_t)0x00U)
#define CAN_TXMAILBOX_1 ((uint8_t)0x01U)
#define CAN_TXMAILBOX_2 ((uint8_t)0x02U)
#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
/**
* @}
*/
@ -508,7 +518,7 @@ typedef struct
* @retval The number of pending message.
*/
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & (uint32_t)0x03U)))
((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))
/** @brief Check whether the specified CAN flag is set or not.
* @param __HANDLE__: CAN Handle
@ -569,9 +579,9 @@ typedef struct
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))): \
((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__HANDLE__)->Instance->MSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))))
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
@ -704,8 +714,8 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
#define CAN_FLAG_MASK ((uint32_t)0x000000FFU)
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
#define CAN_FLAG_MASK 0x000000FFU
/**
* @}
*/
@ -732,10 +742,10 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
((FIFO) == CAN_FILTER_FIFO1))
#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FFU))
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFFU))
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U))
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
((IDTYPE) == CAN_ID_EXT))
@ -757,7 +767,7 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
STM32F412Vx || STM32F412Rx || STM32F412Cx */
STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
/**
* @}

33
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cec.c
* @author MCD Application Team
* @version V1.5.0
* @date 06-May-2016
* @version V1.7.1
* @date 14-April-2017
* @brief CEC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the High Definition Multimedia Interface
@ -24,31 +24,32 @@
(#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
(##) Enable the CEC interface clock.
(##) CEC pins configuration:
(+) Enable the clock for the CEC GPIOs.
(+) Configure these CEC pins as alternate function pull-up.
(+++) Enable the clock for the CEC GPIOs.
(+++) Configure these CEC pins as alternate function pull-up.
(##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
and HAL_CEC_Receive_IT() APIs):
(+) Configure the CEC interrupt priority.
(+) Enable the NVIC CEC IRQ handle.
(@) The specific CEC interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
and receive process.
(+++) Configure the CEC interrupt priority.
(+++) Enable the NVIC CEC IRQ handle.
(+++) The specific CEC interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
and receive process.
(#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
in case of Bit Rising Error, Error-Bit generation conditions, device logical
address and Listen mode in the hcec Init structure.
(#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
(@) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
[..]
(@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...)
by calling the customed HAL_CEC_MspInit() API.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -286,7 +287,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
{
hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16);
hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16U);
}
else
{
@ -378,7 +379,8 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
/**
* @brief Send data in interrupt mode
* @param hcec: CEC handle
* @param hcec: CEC handle
* @param InitiatorAddress: Initiator logical address
* @param DestinationAddress: destination logical address
* @param pData: pointer to input byte data buffer
* @param Size: amount of data to be sent in bytes (without counting the header).
@ -448,6 +450,7 @@ uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
/**
* @brief Change Rx Buffer.
* @param hcec: CEC handle
* @param Rxbuffer: Rx Buffer
* @note This function can be called only inside the HAL_CEC_RxCpltCallback()
* @retval Frame size
*/

76
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_cec.h
* @author MCD Application Team
* @version V1.5.0
* @date 06-May-2016
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -220,7 +220,7 @@ typedef struct
/** @defgroup CEC_Error_Code CEC Error Code
* @{
*/
#define HAL_CEC_ERROR_NONE ((uint32_t)0x00000000U)/*!< no error */
#define HAL_CEC_ERROR_NONE 0x00000000U /*!< no error */
#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
@ -237,14 +237,14 @@ typedef struct
/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
* @{
*/
#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
#define CEC_DEFAULT_SFT 0x00000000U
#define CEC_0_5_BITPERIOD_SFT 0x00000001U
#define CEC_1_5_BITPERIOD_SFT 0x00000002U
#define CEC_2_5_BITPERIOD_SFT 0x00000003U
#define CEC_3_5_BITPERIOD_SFT 0x00000004U
#define CEC_4_5_BITPERIOD_SFT 0x00000005U
#define CEC_5_5_BITPERIOD_SFT 0x00000006U
#define CEC_6_5_BITPERIOD_SFT 0x00000007U
/**
* @}
*/
@ -252,7 +252,7 @@ typedef struct
/** @defgroup CEC_Tolerance CEC Receiver Tolerance
* @{
*/
#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
#define CEC_STANDARD_TOLERANCE 0x00000000U
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
/**
* @}
@ -261,7 +261,7 @@ typedef struct
/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
* @{
*/
#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
#define CEC_NO_RX_STOP_ON_BRE 0x00000000U
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
/**
* @}
@ -270,7 +270,7 @@ typedef struct
/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
* @{
*/
#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define CEC_BRE_ERRORBIT_NO_GENERATION 0x00000000U
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
/**
* @}
@ -279,7 +279,7 @@ typedef struct
/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
* @{
*/
#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define CEC_LBPE_ERRORBIT_NO_GENERATION 0x00000000U
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
/**
* @}
@ -288,7 +288,7 @@ typedef struct
/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
* @{
*/
#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
#define CEC_BROADCASTERROR_ERRORBIT_GENERATION 0x00000000U
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
/**
* @}
@ -297,7 +297,7 @@ typedef struct
/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
* @{
*/
#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
#define CEC_SFT_START_ON_TXSOM 0x00000000U
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
/**
* @}
@ -306,7 +306,7 @@ typedef struct
/** @defgroup CEC_Listening_Mode CEC Listening mode option
* @{
*/
#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
#define CEC_REDUCED_LISTENING_MODE 0x00000000U
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
/**
* @}
@ -315,7 +315,7 @@ typedef struct
/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
* @{
*/
#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
#define CEC_CFGR_OAR_LSB_POS 16U
/**
* @}
*/
@ -323,7 +323,7 @@ typedef struct
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
* @{
*/
#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
#define CEC_INITIATOR_LSB_POS 4U
/**
* @}
*/
@ -331,22 +331,22 @@ typedef struct
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
* @{
*/
#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
#define CEC_OWN_ADDRESS_NONE ((uint16_t)0x0000) /* Reset value */
#define CEC_OWN_ADDRESS_0 ((uint16_t)0x0001) /* Logical Address 0 */
#define CEC_OWN_ADDRESS_1 ((uint16_t)0x0002) /* Logical Address 1 */
#define CEC_OWN_ADDRESS_2 ((uint16_t)0x0004) /* Logical Address 2 */
#define CEC_OWN_ADDRESS_3 ((uint16_t)0x0008) /* Logical Address 3 */
#define CEC_OWN_ADDRESS_4 ((uint16_t)0x0010) /* Logical Address 4 */
#define CEC_OWN_ADDRESS_5 ((uint16_t)0x0020) /* Logical Address 5 */
#define CEC_OWN_ADDRESS_6 ((uint16_t)0x0040) /* Logical Address 6 */
#define CEC_OWN_ADDRESS_7 ((uint16_t)0x0080) /* Logical Address 7 */
#define CEC_OWN_ADDRESS_8 ((uint16_t)0x0100) /* Logical Address 9 */
#define CEC_OWN_ADDRESS_9 ((uint16_t)0x0200) /* Logical Address 10 */
#define CEC_OWN_ADDRESS_10 ((uint16_t)0x0400) /* Logical Address 11 */
#define CEC_OWN_ADDRESS_11 ((uint16_t)0x0800) /* Logical Address 12 */
#define CEC_OWN_ADDRESS_12 ((uint16_t)0x1000) /* Logical Address 13 */
#define CEC_OWN_ADDRESS_13 ((uint16_t)0x2000) /* Logical Address 14 */
#define CEC_OWN_ADDRESS_14 ((uint16_t)0x4000) /* Logical Address 15 */
/**
* @}
*/
@ -702,7 +702,7 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
* @param __SIZE__: CEC message size.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10)
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
/** @brief Check CEC device Own Address Register (OAR) setting.
* OAR address is written in a 15-bit field within CEC_CFGR register.

95
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_conf.h
* @author MCD Application Team
* @version V1.5.0
* @date 06-May-2016
* @version V1.7.1
* @date 14-April-2017
* @brief HAL configuration file.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -95,6 +95,7 @@
#define HAL_SPDIFRX_MODULE_ENABLED
#define HAL_DFSDM_MODULE_ENABLED
#define HAL_LPTIM_MODULE_ENABLED
#define HAL_MMC_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
@ -116,26 +117,26 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz */
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */
#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
@ -144,7 +145,7 @@
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
@ -154,8 +155,8 @@
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define INSTRUCTION_CACHE_ENABLE 1U
@ -183,56 +184,56 @@
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848 PHY Address*/
#define DP83848_PHY_ADDRESS 0x01U
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FFU)
#define PHY_RESET_DELAY 0x000000FFU
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)
#define PHY_CONFIG_DELAY 0x00000FFFU
#define PHY_READ_TO ((uint32_t)0x0000FFFFU)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)
#define PHY_READ_TO 0x0000FFFFU
#define PHY_WRITE_TO 0x0000FFFFU
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */
#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x0010U) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x0011U) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x0012U) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* ################## SPI peripheral configuration ########################## */
@ -424,6 +425,10 @@
#include "stm32f4xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32f4xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
@ -437,7 +442,7 @@
#include "mbed_assert.h"
#define assert_param(expr) MBED_ASSERT(expr)
#else
#define assert_param(expr) ((void)0)
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */

50
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cortex.c
* @author MCD Application Team
* @version V1.5.0
* @date 06-May-2016
* @version V1.7.1
* @date 14-April-2017
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@ -26,7 +26,7 @@
function according to the following table.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
(#) please refer to programing manual for details in how to configure priority.
(#) please refer to programming manual for details in how to configure priority.
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
@ -45,7 +45,7 @@
(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
(++) Configures the SysTick IRQ priority to the lowest value (0x0FU).
(++) Configures the SysTick IRQ priority to the lowest value 0x0F.
(++) Resets the SysTick Counter register.
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt.
@ -70,7 +70,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -269,6 +269,46 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
*/
#if (__MPU_PRESENT == 1U)
/**
* @brief Disables the MPU
* @retval None
*/
void HAL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable fault exceptions */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
/* Disable the MPU and clear the control register*/
MPU->CTRL = 0U;
}
/**
* @brief Enable the MPU.
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Ensure MPU setting take effects */
__DSB();
__ISB();
}
/**
* @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains

215
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_cortex.h
* @author MCD Application Team
* @version V1.5.0
* @date 06-May-2016
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -58,7 +58,7 @@
* @{
*/
#if (__MPU_PRESENT == 1)
#if (__MPU_PRESENT == 1U)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
@ -105,16 +105,16 @@ typedef struct
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
0 bits for subpriority */
/**
* @}
*/
@ -122,8 +122,8 @@ typedef struct
/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
/**
* @}
@ -133,10 +133,11 @@ typedef struct
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
/**
* @}
*/
@ -144,8 +145,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE ((uint8_t)0x01U)
#define MPU_REGION_DISABLE ((uint8_t)0x00U)
#define MPU_REGION_ENABLE ((uint8_t)0x01)
#define MPU_REGION_DISABLE ((uint8_t)0x00)
/**
* @}
*/
@ -153,8 +154,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
/**
* @}
*/
@ -162,8 +163,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
/**
* @}
*/
@ -171,8 +172,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
/**
* @}
*/
@ -180,8 +181,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
/**
* @}
*/
@ -189,9 +190,9 @@ typedef struct
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
* @{
*/
#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
/**
* @}
*/
@ -199,34 +200,34 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*/
#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
/**
* @}
*/
@ -234,12 +235,12 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
/**
* @}
*/
@ -247,14 +248,14 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
/**
* @}
*/
@ -273,8 +274,8 @@ typedef struct
*/
/** @addtogroup CORTEX_Exported_Functions_Group1
* @{
*/
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
@ -287,12 +288,9 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
*/
/** @addtogroup CORTEX_Exported_Functions_Group2
* @{
*/
* @{
*/
/* Peripheral Control functions ***********************************************/
#if (__MPU_PRESENT == 1)
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
@ -302,6 +300,12 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
#if (__MPU_PRESENT == 1U)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
/**
* @}
*/
@ -397,57 +401,14 @@ void HAL_SYSTICK_Callback(void);
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
* @brief CORTEX private functions
* @{
*/
#if (__MPU_PRESENT == 1)
/**
* @brief Disables the MPU
* @retval None
*/
__STATIC_INLINE void HAL_MPU_Disable(void)
{
/* Disable fault exceptions */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
/* Disable the MPU */
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/**
* @brief Enables the MPU
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
}
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}

6
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_crc.c
* @author MCD Application Team
* @version V1.5.0
* @date 06-May-2016
* @version V1.7.1
* @date 14-April-2017
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@ -32,7 +32,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_crc.h
* @author MCD Application Team
* @version V1.5.0
* @date 06-May-2016
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

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