From ab92decf23956f0bb6244af81657281d3afc59a9 Mon Sep 17 00:00:00 2001 From: Marcomissyou Date: Tue, 7 Oct 2014 17:59:57 +0800 Subject: [PATCH 01/77] Marco add for new target DFCM_NNN40 --- .../TARGET_MCU_NRF51822/system_nrf51822.c | 8 +- .../TARGET_DFCM_NNN40_DT0R/PinNames.h | 178 ++++++++++++++++++ .../TARGET_DFCM_NNN40_DT0R/device.h | 57 ++++++ workspace_tools/targets.py | 10 + 4 files changed, 251 insertions(+), 2 deletions(-) create mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R/device.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c index 3a704439a5..7324f83eec 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c @@ -21,9 +21,13 @@ #include "nrf51822.h" #include "system_nrf51822.h" +#ifdef DFCM_NNN40_DT0R -#define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */ - + #define __SYSTEM_CLOCK (32000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 32MHz */ +#else + #define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */ +#endif + static bool is_manual_peripheral_setup_needed(void); static bool is_disabled_in_debug_needed(void); diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R/PinNames.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R/PinNames.h new file mode 100644 index 0000000000..be8ff8b4cf --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R/PinNames.h @@ -0,0 +1,178 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013 Nordic Semiconductor + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 3 + +typedef enum { + p0 = 0, + p1 = 1, + p2 = 2, + p3 = 3, + p4 = 4, + p5 = 5, + p6 = 6, + p7 = 7, + p8 = 8, + p9 = 9, + p10 = 10, + p11 = 11, + p12 = 12, + p13 = 13, + p14 = 14, + p15 = 15, + p16 = 16, + p17 = 17, + p18 = 18, + p19 = 19, + p20 = 20, + p21 = 21, + p22 = 22, + p23 = 23, + p24 = 24, + p25 = 25, + p26 = 26, + p27 = 27, + p28 = 28, + p29 = 29, + p30 = 30, + + P0_0 = p0, + P0_1 = p1, + P0_2 = p2, + P0_3 = p3, + P0_4 = p4, + P0_5 = p5, + P0_6 = p6, + P0_7 = p7, + + P0_8 = p8, + P0_9 = p9, + P0_10 = p10, + P0_11 = p11, + P0_12 = p12, + P0_13 = p13, + P0_14 = p14, + P0_15 = p15, + + P0_16 = p16, + P0_17 = p17, + P0_18 = p18, + P0_19 = p19, + P0_20 = p20, + P0_21 = p21, + P0_22 = p22, + P0_23 = p23, + + P0_24 = p24, + P0_25 = p25, + P0_26 = p26, + P0_27 = p27, + P0_28 = p28, + P0_29 = p29, + P0_30 = p30, + + LED1 = p21, + LED2 = p22, + LED3 = p23, + LED4 = p24, + + BUTTON1 = p17, + BUTTON2 = p18, + BUTTON3 = p19, + BUTTON4 = p20, + + RX_PIN_NUMBER = p11, + TX_PIN_NUMBER = p9, + CTS_PIN_NUMBER = p10, + RTS_PIN_NUMBER = p8, + + // mBed interface Pins + USBTX = TX_PIN_NUMBER, + USBRX = RX_PIN_NUMBER, + + SPI_PSELMOSI0 = p25, + SPI_PSELMISO0 = p28, + SPI_PSELSS0 = p24, + SPI_PSELSCK0 = p29, + + SPI_PSELMOSI1 = p13, + SPI_PSELMISO1 = p14, + SPI_PSELSS1 = p12, + SPI_PSELSCK1 = p15, + + SPIS_PSELMOSI = p13, + SPIS_PSELMISO = p14, + SPIS_PSELSS = p12, + SPIS_PSELSCK = p15, + + I2C_SDA0 = p30, + I2C_SCL0 = p7, + + D0 = p12, + D1 = p13, + D2 = p14, + D3 = p15, + D4 = p16, + D5 = p17, + D6 = p18, + D7 = p19, + + D8 = p20, + D9 = p23, + D10 = p24, + D11 = p25, + D12 = p28, + D13 = p29, + + D14 = p30, + D15 = p7, + + A0 = p1, + A1 = p2, + A2 = p3, + A3 = p4, + A4 = p5, + A5 = p6, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 3, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R/device.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R/device.h new file mode 100644 index 0000000000..9d5a5e2109 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R/device.h @@ -0,0 +1,57 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 0 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 563a68f6fd..99dfebc301 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -552,6 +552,15 @@ class NRF51_DK_OTA(Target): self.macros = ['TARGET_NRF51822', 'TARGET_NRF51_DK', 'TARGET_OTA_ENABLED'] self.supported_toolchains = ["ARM", "GCC_ARM"] self.is_disk_virtual = True + +class DFCM_NNN40_DT0R(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_32K'] + self.macros = ['TARGET_NRF51822', 'TARGET_OTA_ENABLED'] + self.supported_toolchains = ["ARM", "GCC_ARM"] + self.is_disk_virtual = True class LPC1549(LPCTarget): @@ -727,6 +736,7 @@ TARGETS = [ ARCH_BLE(), NRF51_DK(), NRF51_DK_OTA(), + DFCM_NNN40_DT0R(), ARCH_PRO(), ARCH_GPRS(), LPCCAPPUCCINO(), From b7f4d17aae5faa09513b962dd75d8cdd12bdcbbc Mon Sep 17 00:00:00 2001 From: Przemek Wirkus Date: Fri, 19 Dec 2014 13:14:53 +0000 Subject: [PATCH 02/77] Added new GPIO HAL function gpio_is_connected() used to check if gpio_t is connected or initialized with NC Simple gpio_t structure in TARGET_KPSDK_MCUS field name changed to allign to other HALs --- libraries/mbed/hal/gpio_api.h | 7 +++++++ .../TARGET_KPSDK_MCUS/gpio_object.h | 18 +++++++++++------- 2 files changed, 18 insertions(+), 7 deletions(-) diff --git a/libraries/mbed/hal/gpio_api.h b/libraries/mbed/hal/gpio_api.h index e4cf7fd6f5..ab5206aa93 100644 --- a/libraries/mbed/hal/gpio_api.h +++ b/libraries/mbed/hal/gpio_api.h @@ -28,6 +28,13 @@ extern "C" { **/ uint32_t gpio_set(PinName pin); +/* Checks if gpio object is connected (pin was not initialized with NC) + * @param pin The pin to be set as GPIO + * @return Non zero value if port is connected to pin + * 0 if port is initialized with NC + **/ +int gpio_is_connected(const gpio_t *obj); + /* GPIO object */ void gpio_init(gpio_t *obj, PinName pin); diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_object.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_object.h index 780eed9e68..7cdf6662ba 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_object.h @@ -25,27 +25,31 @@ extern "C" { #endif typedef struct { - PinName pinName; + PinName pin; } gpio_t; static inline void gpio_write(gpio_t *obj, int value) { - MBED_ASSERT(obj->pinName != (PinName)NC); - uint32_t port = obj->pinName >> GPIO_PORT_SHIFT; - uint32_t pin = obj->pinName & 0xFF; + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; + uint32_t pin = obj->pin & 0xFF; uint32_t gpio_addrs[] = GPIO_BASE_ADDRS; GPIO_HAL_WritePinOutput(gpio_addrs[port], pin, value); } static inline int gpio_read(gpio_t *obj) { - MBED_ASSERT(obj->pinName != (PinName)NC); - uint32_t port = obj->pinName >> GPIO_PORT_SHIFT; - uint32_t pin = obj->pinName & 0xFF; + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; + uint32_t pin = obj->pin & 0xFF; uint32_t gpio_addrs[] = GPIO_BASE_ADDRS; return (int)GPIO_HAL_ReadPinInput(gpio_addrs[port], pin); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif From a53cd59b51f1244ef21f4ffae13bfb078d280cc8 Mon Sep 17 00:00:00 2001 From: Przemek Wirkus Date: Fri, 19 Dec 2014 13:28:47 +0000 Subject: [PATCH 03/77] Added is_connected() method to Digital I/O classes APIs (DigitalIn, DigitalOut and DigitalInOut --- libraries/mbed/api/DigitalIn.h | 10 ++++++++++ libraries/mbed/api/DigitalInOut.h | 10 ++++++++++ libraries/mbed/api/DigitalOut.h | 10 ++++++++++ libraries/mbed/hal/gpio_api.h | 3 +-- .../hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_api.c | 10 +++++----- 5 files changed, 36 insertions(+), 7 deletions(-) diff --git a/libraries/mbed/api/DigitalIn.h b/libraries/mbed/api/DigitalIn.h index d81038b8cf..b089de9faa 100644 --- a/libraries/mbed/api/DigitalIn.h +++ b/libraries/mbed/api/DigitalIn.h @@ -80,6 +80,16 @@ public: gpio_mode(&gpio, pull); } + /** Return the output setting, represented as 0 or 1 (int) + * + * @returns + * Non zero value if pin is connected to uc GPIO + * 0 if gpio object was initialized with NC + */ + int is_connected() { + return gpio_is_connected(&gpio); + } + #ifdef MBED_OPERATORS /** An operator shorthand for read() */ diff --git a/libraries/mbed/api/DigitalInOut.h b/libraries/mbed/api/DigitalInOut.h index 5d9221b5dc..e30be0e638 100644 --- a/libraries/mbed/api/DigitalInOut.h +++ b/libraries/mbed/api/DigitalInOut.h @@ -85,6 +85,16 @@ public: gpio_mode(&gpio, pull); } + /** Return the output setting, represented as 0 or 1 (int) + * + * @returns + * Non zero value if pin is connected to uc GPIO + * 0 if gpio object was initialized with NC + */ + int is_connected() { + return gpio_is_connected(&gpio); + } + #ifdef MBED_OPERATORS /** A shorthand for write() */ diff --git a/libraries/mbed/api/DigitalOut.h b/libraries/mbed/api/DigitalOut.h index 0281770ff8..0d66f907b0 100644 --- a/libraries/mbed/api/DigitalOut.h +++ b/libraries/mbed/api/DigitalOut.h @@ -77,6 +77,16 @@ public: return gpio_read(&gpio); } + /** Return the output setting, represented as 0 or 1 (int) + * + * @returns + * Non zero value if pin is connected to uc GPIO + * 0 if gpio object was initialized with NC + */ + int is_connected() { + return gpio_is_connected(&gpio); + } + #ifdef MBED_OPERATORS /** A shorthand for write() */ diff --git a/libraries/mbed/hal/gpio_api.h b/libraries/mbed/hal/gpio_api.h index ab5206aa93..872b547eaa 100644 --- a/libraries/mbed/hal/gpio_api.h +++ b/libraries/mbed/hal/gpio_api.h @@ -30,8 +30,7 @@ uint32_t gpio_set(PinName pin); /* Checks if gpio object is connected (pin was not initialized with NC) * @param pin The pin to be set as GPIO - * @return Non zero value if port is connected to pin - * 0 if port is initialized with NC + * @return 0 if port is initialized with NC **/ int gpio_is_connected(const gpio_t *obj); diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_api.c index 73259e4dde..cde73ff4fd 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_api.c @@ -30,7 +30,7 @@ uint32_t gpio_set(PinName pin) { } void gpio_init(gpio_t *obj, PinName pin) { - obj->pinName = pin; + obj->pin = pin; if (pin == (PinName)NC) return; @@ -42,14 +42,14 @@ void gpio_init(gpio_t *obj, PinName pin) { } void gpio_mode(gpio_t *obj, PinMode mode) { - pin_mode(obj->pinName, mode); + pin_mode(obj->pin, mode); } void gpio_dir(gpio_t *obj, PinDirection direction) { - MBED_ASSERT(obj->pinName != (PinName)NC); - uint32_t port = obj->pinName >> GPIO_PORT_SHIFT; + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; uint32_t gpio_addrs[] = GPIO_BASE_ADDRS; - uint32_t pin_num = obj->pinName & 0xFF; + uint32_t pin_num = obj->pin & 0xFF; switch (direction) { case PIN_INPUT: From 6fa4b469f4a4aeffad33200dbcad2478bdb36ed2 Mon Sep 17 00:00:00 2001 From: Przemek Wirkus Date: Fri, 19 Dec 2014 13:37:16 +0000 Subject: [PATCH 04/77] Decorated all HALs with gpio_is_connected() function implementation --- .../targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_object.h | 4 ++++ .../targets/hal/TARGET_Freescale/TARGET_KLXX/gpio_object.h | 4 ++++ .../hal/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_object.h | 4 ++++ .../mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_object.h | 4 ++++ .../mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/gpio_object.h | 4 ++++ .../targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_object.h | 4 ++++ .../mbed/targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_object.h | 4 ++++ .../mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_object.h | 4 ++++ .../mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/gpio_object.h | 4 ++++ .../mbed/targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_object.h | 4 ++++ .../mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/gpio_object.h | 4 ++++ .../mbed/targets/hal/TARGET_NXP/TARGET_LPC43XX/gpio_object.h | 4 ++++ .../mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_object.h | 4 ++++ .../mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_object.h | 4 ++++ .../targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h | 4 ++++ .../targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_object.h | 4 ++++ .../targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_object.h | 4 ++++ .../targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_object.h | 4 ++++ .../targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_object.h | 4 ++++ .../targets/hal/TARGET_STM/TARGET_DISCO_F429ZI/gpio_object.h | 4 ++++ .../targets/hal/TARGET_STM/TARGET_DISCO_L053C8/gpio_object.h | 4 ++++ .../hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/gpio_object.h | 4 ++++ .../targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/gpio_object.h | 4 ++++ .../targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/gpio_object.h | 4 ++++ .../targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/gpio_object.h | 4 ++++ 25 files changed, 100 insertions(+) diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_object.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_object.h index ca2c0d64f8..b17219da0f 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_object.h @@ -46,6 +46,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_object.h index 2d93b59850..f295911aaa 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_object.h @@ -43,6 +43,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_mask_read) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_object.h index 35ef92f18e..0252448103 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_object.h @@ -46,6 +46,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC43XX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC43XX/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC43XX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC43XX/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_object.h index 75d9291620..eac21ab67e 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_object.h @@ -47,6 +47,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h index 6eb8d80402..c87a2aec1b 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h @@ -41,6 +41,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_object.h index fdc6112cb6..684d968757 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_object.h index d3142d5c71..d97ee5bf12 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_object.h @@ -63,6 +63,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_object.h index 5569efc465..bebf7db0c7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_object.h index 5569efc465..bebf7db0c7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F429ZI/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F429ZI/gpio_object.h index 5569efc465..bebf7db0c7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F429ZI/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F429ZI/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_L053C8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_L053C8/gpio_object.h index 75013b4188..4391135e3b 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_L053C8/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_L053C8/gpio_object.h @@ -62,6 +62,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/gpio_object.h index a8c99da3b6..1efcb162cd 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/gpio_object.h @@ -62,6 +62,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/gpio_object.h index fdc6112cb6..684d968757 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/gpio_object.h index fdc6112cb6..684d968757 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/gpio_object.h index fdc6112cb6..684d968757 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif From c4fc8e68ebb3b24c125cb46bd91f93b23c5be49a Mon Sep 17 00:00:00 2001 From: Przemek Wirkus Date: Fri, 19 Dec 2014 14:06:46 +0000 Subject: [PATCH 05/77] Added operator[] for BusIn and BusOut to add access to particular bit in random-iterator fashion --- libraries/mbed/api/BusIn.h | 6 ++++++ libraries/mbed/api/BusOut.h | 6 ++++++ libraries/mbed/common/BusIn.cpp | 12 ++++++++++++ libraries/mbed/common/BusOut.cpp | 11 +++++++++++ 4 files changed, 35 insertions(+) diff --git a/libraries/mbed/api/BusIn.h b/libraries/mbed/api/BusIn.h index c5ece1df68..92c9eeb5a6 100644 --- a/libraries/mbed/api/BusIn.h +++ b/libraries/mbed/api/BusIn.h @@ -58,10 +58,16 @@ public: */ void mode(PinMode pull); + static DigitalIn din_dummy; + #ifdef MBED_OPERATORS /** A shorthand for read() */ operator int(); + + /** Access to particular bit in random-iterator fashion + */ + DigitalIn & operator[] (unsigned int index); #endif protected: diff --git a/libraries/mbed/api/BusOut.h b/libraries/mbed/api/BusOut.h index 9a6608e89e..4212c76637 100644 --- a/libraries/mbed/api/BusOut.h +++ b/libraries/mbed/api/BusOut.h @@ -56,12 +56,18 @@ public: */ int read(); + static DigitalOut dout_dummy; + #ifdef MBED_OPERATORS /** A shorthand for write() */ BusOut& operator= (int v); BusOut& operator= (BusOut& rhs); + /** Access to particular bit in random-iterator fashion + */ + DigitalOut& operator[] (unsigned int index); + /** A shorthand for read() */ operator int(); diff --git a/libraries/mbed/common/BusIn.cpp b/libraries/mbed/common/BusIn.cpp index c1eb3dbdb1..895003c409 100644 --- a/libraries/mbed/common/BusIn.cpp +++ b/libraries/mbed/common/BusIn.cpp @@ -17,6 +17,8 @@ namespace mbed { +DigitalIn BusIn::din_dummy(NC); + BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) { PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15}; @@ -61,6 +63,16 @@ void BusIn::mode(PinMode pull) { BusIn::operator int() { return read(); } + +DigitalIn& BusIn::operator[] (unsigned int index) { + //MBED_ASSERT(index >= MBED_BUS_SIZE); + //MBED_ASSERT(_pin[index]); + if (index >= 16 || _pin[index] == NULL) { + return din_dummy; + } + return *_pin[index]; +} + #endif } // namespace mbed diff --git a/libraries/mbed/common/BusOut.cpp b/libraries/mbed/common/BusOut.cpp index 7e9a5f7dbe..6cf4f3c605 100644 --- a/libraries/mbed/common/BusOut.cpp +++ b/libraries/mbed/common/BusOut.cpp @@ -17,6 +17,8 @@ namespace mbed { +DigitalOut BusOut::dout_dummy(NC); + BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) { PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15}; @@ -68,6 +70,15 @@ BusOut& BusOut::operator= (BusOut& rhs) { return *this; } +DigitalOut& BusOut::operator[] (unsigned int index) { + //MBED_ASSERT(index >= MBED_BUS_SIZE); + //MBED_ASSERT(_pin[index]); + if (index >= 16 || _pin[index] == NULL) { + return dout_dummy; + } + return *_pin[index]; +} + BusOut::operator int() { return read(); } From db7e92853bd4dbb3940af973564c59c80e3de4b8 Mon Sep 17 00:00:00 2001 From: Przemek Wirkus Date: Fri, 19 Dec 2014 14:37:00 +0000 Subject: [PATCH 06/77] Added mask() function to BusIn and BusOut components You can use BusIn::mask() or BusOut::mask() to get binary mask of all connected and NC pins in bus --- libraries/mbed/api/BusIn.h | 14 ++++++++++++++ libraries/mbed/api/BusOut.h | 14 ++++++++++++++ libraries/mbed/common/BusIn.cpp | 8 ++++++++ libraries/mbed/common/BusOut.cpp | 8 ++++++++ 4 files changed, 44 insertions(+) diff --git a/libraries/mbed/api/BusIn.h b/libraries/mbed/api/BusIn.h index 92c9eeb5a6..6ef2e66c7d 100644 --- a/libraries/mbed/api/BusIn.h +++ b/libraries/mbed/api/BusIn.h @@ -58,6 +58,16 @@ public: */ void mode(PinMode pull); + /** Binary mask of bus pins connected to actual pins (not NC pins) + * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1 + * + * @returns + * Binary mask of connected pins + */ + int mask() { + return _nc_mask; + } + static DigitalIn din_dummy; #ifdef MBED_OPERATORS @@ -73,6 +83,10 @@ public: protected: DigitalIn* _pin[16]; + /** Mask of NC pins, if bit [n] bit is set to 1, [n] pin in bus is in NC state + */ + int _nc_mask; + /* disallow copy constructor and assignment operators */ private: BusIn(const BusIn&); diff --git a/libraries/mbed/api/BusOut.h b/libraries/mbed/api/BusOut.h index 4212c76637..27211d8b8a 100644 --- a/libraries/mbed/api/BusOut.h +++ b/libraries/mbed/api/BusOut.h @@ -56,6 +56,16 @@ public: */ int read(); + /** Binary mask of bus pins connected to actual pins (not NC pins) + * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1 + * + * @returns + * Binary mask of connected pins + */ + int mask() { + return _nc_mask; + } + static DigitalOut dout_dummy; #ifdef MBED_OPERATORS @@ -76,6 +86,10 @@ public: protected: DigitalOut* _pin[16]; + /** Mask of NC pins, if bit [n] bit is set to 1, [n] pin in bus is in NC state + */ + int _nc_mask; + /* disallow copy constructor and assignment operators */ private: BusOut(const BusOut&); diff --git a/libraries/mbed/common/BusIn.cpp b/libraries/mbed/common/BusIn.cpp index 895003c409..2858ccc2ea 100644 --- a/libraries/mbed/common/BusIn.cpp +++ b/libraries/mbed/common/BusIn.cpp @@ -22,14 +22,22 @@ DigitalIn BusIn::din_dummy(NC); BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) { PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15}; + _nc_mask = 0; for (int i=0; i<16; i++) { _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } } } BusIn::BusIn(PinName pins[16]) { + _nc_mask = 0; for (int i=0; i<16; i++) { _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } } } diff --git a/libraries/mbed/common/BusOut.cpp b/libraries/mbed/common/BusOut.cpp index 6cf4f3c605..445b3f8658 100644 --- a/libraries/mbed/common/BusOut.cpp +++ b/libraries/mbed/common/BusOut.cpp @@ -22,14 +22,22 @@ DigitalOut BusOut::dout_dummy(NC); BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) { PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15}; + _nc_mask = 0; for (int i=0; i<16; i++) { _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } } } BusOut::BusOut(PinName pins[16]) { + _nc_mask = 0; for (int i=0; i<16; i++) { _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } } } From 7720989e2096a9d70476c0fcc0ff710b13637e5e Mon Sep 17 00:00:00 2001 From: Przemek Wirkus Date: Fri, 19 Dec 2014 14:45:32 +0000 Subject: [PATCH 07/77] Added operator[] and mask() function to BusInOut This change follows changes in BUsIn and BusOUt API --- libraries/mbed/api/BusInOut.h | 17 +++++++++++++++++ libraries/mbed/common/BusInOut.cpp | 20 ++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/libraries/mbed/api/BusInOut.h b/libraries/mbed/api/BusInOut.h index 63dfda1606..50e8da5258 100644 --- a/libraries/mbed/api/BusInOut.h +++ b/libraries/mbed/api/BusInOut.h @@ -73,6 +73,18 @@ public: */ void mode(PinMode pull); + /** Binary mask of bus pins connected to actual pins (not NC pins) + * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1 + * + * @returns + * Binary mask of connected pins + */ + int mask() { + return _nc_mask; + } + + static DigitalInOut dinout_dummy; + #ifdef MBED_OPERATORS /** A shorthand for write() */ @@ -87,10 +99,15 @@ public: protected: DigitalInOut* _pin[16]; + /** Mask of NC pins, if bit [n] bit is set to 1, [n] pin in bus is in NC state + */ + int _nc_mask; + /* disallow copy constructor and assignment operators */ private: BusInOut(const BusInOut&); BusInOut & operator = (const BusInOut&); + DigitalInOut& operator[] (unsigned int index); }; } // namespace mbed diff --git a/libraries/mbed/common/BusInOut.cpp b/libraries/mbed/common/BusInOut.cpp index 84733a40cc..12c5063c1e 100644 --- a/libraries/mbed/common/BusInOut.cpp +++ b/libraries/mbed/common/BusInOut.cpp @@ -17,17 +17,27 @@ namespace mbed { +DigitalInOut BusInOut::dinout_dummy(NC); + BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) { PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15}; + _nc_mask = 0; for (int i=0; i<16; i++) { _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } } } BusInOut::BusInOut(PinName pins[16]) { + _nc_mask = 0; for (int i=0; i<16; i++) { _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } } } @@ -92,6 +102,16 @@ BusInOut& BusInOut::operator= (BusInOut& rhs) { return *this; } +DigitalInOut& BusInOut::operator[] (unsigned int index) { + //MBED_ASSERT(index >= MBED_BUS_SIZE); + //MBED_ASSERT(_pin[index]); + if (index >= 16 || _pin[index] == NULL) { + return dinout_dummy; + } + return *_pin[index]; +} + + BusInOut::operator int() { return read(); } From 11c5955959be22334ab9f28d77142fe621143175 Mon Sep 17 00:00:00 2001 From: Przemek Wirkus Date: Fri, 19 Dec 2014 14:48:39 +0000 Subject: [PATCH 08/77] Simple indent --- libraries/mbed/api/BusInOut.h | 1 - 1 file changed, 1 deletion(-) diff --git a/libraries/mbed/api/BusInOut.h b/libraries/mbed/api/BusInOut.h index 50e8da5258..919366aedb 100644 --- a/libraries/mbed/api/BusInOut.h +++ b/libraries/mbed/api/BusInOut.h @@ -51,7 +51,6 @@ public: */ void write(int value); - /** Read the value currently output on the bus * * @returns From 8690af3b7bc94289210d6303a71af6932beb6db3 Mon Sep 17 00:00:00 2001 From: Przemek Wirkus Date: Fri, 19 Dec 2014 14:53:35 +0000 Subject: [PATCH 09/77] Simple indent --- libraries/mbed/common/BusInOut.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/libraries/mbed/common/BusInOut.cpp b/libraries/mbed/common/BusInOut.cpp index 12c5063c1e..e3a1182aba 100644 --- a/libraries/mbed/common/BusInOut.cpp +++ b/libraries/mbed/common/BusInOut.cpp @@ -111,7 +111,6 @@ DigitalInOut& BusInOut::operator[] (unsigned int index) { return *_pin[index]; } - BusInOut::operator int() { return read(); } From 56e7514495c2f437894623f640e4f5fa9fc7051d Mon Sep 17 00:00:00 2001 From: Przemek Wirkus Date: Fri, 19 Dec 2014 14:59:06 +0000 Subject: [PATCH 10/77] Modiffied _ns_mack member's comment in Bus classes (BusIn, BusOUt, BusInOut) --- libraries/mbed/api/BusIn.h | 4 +++- libraries/mbed/api/BusInOut.h | 4 +++- libraries/mbed/api/BusOut.h | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/libraries/mbed/api/BusIn.h b/libraries/mbed/api/BusIn.h index 6ef2e66c7d..837a71bcec 100644 --- a/libraries/mbed/api/BusIn.h +++ b/libraries/mbed/api/BusIn.h @@ -83,7 +83,9 @@ public: protected: DigitalIn* _pin[16]; - /** Mask of NC pins, if bit [n] bit is set to 1, [n] pin in bus is in NC state + /** Mask of bus's NC pins + * If bit[n] is set to 1 - pin is connected + * if bit[n] is cleared - pin is not connected (NC) */ int _nc_mask; diff --git a/libraries/mbed/api/BusInOut.h b/libraries/mbed/api/BusInOut.h index 919366aedb..9d3c38154d 100644 --- a/libraries/mbed/api/BusInOut.h +++ b/libraries/mbed/api/BusInOut.h @@ -98,7 +98,9 @@ public: protected: DigitalInOut* _pin[16]; - /** Mask of NC pins, if bit [n] bit is set to 1, [n] pin in bus is in NC state + /** Mask of bus's NC pins + * If bit[n] is set to 1 - pin is connected + * if bit[n] is cleared - pin is not connected (NC) */ int _nc_mask; diff --git a/libraries/mbed/api/BusOut.h b/libraries/mbed/api/BusOut.h index 27211d8b8a..b979b3f16a 100644 --- a/libraries/mbed/api/BusOut.h +++ b/libraries/mbed/api/BusOut.h @@ -86,7 +86,9 @@ public: protected: DigitalOut* _pin[16]; - /** Mask of NC pins, if bit [n] bit is set to 1, [n] pin in bus is in NC state + /** Mask of bus's NC pins + * If bit[n] is set to 1 - pin is connected + * if bit[n] is cleared - pin is not connected (NC) */ int _nc_mask; From 32cea97577242466f4e4ccbf8860699c797c340d Mon Sep 17 00:00:00 2001 From: Przemek Wirkus Date: Fri, 19 Dec 2014 15:36:55 +0000 Subject: [PATCH 11/77] Added simple tests for BusOut component to check if we can use new features of BusOut::operator[] and DigitalOut::is_connected() --- libraries/tests/mbed/bus_out/main.cpp | 75 +++++++++++++++++++++ libraries/tests/utest/bus/busout_ut.cpp | 87 +++++++++++++++++++++++++ workspace_tools/tests.py | 16 ++++- 3 files changed, 177 insertions(+), 1 deletion(-) create mode 100644 libraries/tests/mbed/bus_out/main.cpp create mode 100644 libraries/tests/utest/bus/busout_ut.cpp diff --git a/libraries/tests/mbed/bus_out/main.cpp b/libraries/tests/mbed/bus_out/main.cpp new file mode 100644 index 0000000000..4f14348604 --- /dev/null +++ b/libraries/tests/mbed/bus_out/main.cpp @@ -0,0 +1,75 @@ +#include "mbed.h" +#include "test_env.h" + +BusOut bus_out(LED1, LED2, LED3, LED4); + +int main() +{ + notify_start(); + + bool result = false; + + for (;;) { + const int mask = bus_out.mask(); + int led_mask = 0x00; + if (LED1 != NC) led_mask |= 0x01; + if (LED2 != NC) led_mask |= 0x02; + if (LED3 != NC) led_mask |= 0x04; + if (LED4 != NC) led_mask |= 0x08; + + printf("MBED: BusIn mask: 0x%X\r\n", mask); + printf("MBED: BusIn LED mask: 0x%X\r\n", led_mask); + + // Let's check bus's connected pins mask + if (mask != led_mask) { + break; + } + + // Checking if DigitalOut is correctly set as connected + for (int i=0; i<4; i++) { + printf("MBED: BusOut.bit[%d] is %s\r\n", i, bus_out[i].is_connected() ? "connected" : "not connected"); + } + + if (LED1 != NC && bus_out[0].is_connected() == 0) { + break; + } + if (LED1 != NC && bus_out[1].is_connected() == 0) { + break; + } + if (LED1 != NC && bus_out[2].is_connected() == 0) { + break; + } + if (LED1 != NC && bus_out[3].is_connected() == 0) { + break; + } + + // Write mask all LEDs + bus_out.write(mask); // Set all LED's pins in high state + if (bus_out.read() != mask) { + break; + } + // Zero all LEDs and see if mask is correctly cleared on all bits + bus_out.write(~mask); + if (bus_out.read() != 0x00) { + break; + } + + result = true; + break; + } + + printf("MBED: Blinking LEDs...\r\n"); + + // Just a quick LED blinking... + for (int i=0; i<4; i++) { + if (bus_out[i].is_connected()) { + bus_out[i] = 1; + } + wait(0.2); + if (bus_out[i].is_connected()) { + bus_out[i] = 0; + } + } + + notify_completion(result); +} diff --git a/libraries/tests/utest/bus/busout_ut.cpp b/libraries/tests/utest/bus/busout_ut.cpp new file mode 100644 index 0000000000..d7f2a408df --- /dev/null +++ b/libraries/tests/utest/bus/busout_ut.cpp @@ -0,0 +1,87 @@ +#include "TestHarness.h" +#include +#include "mbed.h" + +TEST_GROUP(BusOut_mask) +{ +}; + +TEST(BusOut_mask, led_1_2_3) +{ + BusOut bus_data(LED1, LED2, LED3); + CHECK_EQUAL(0x07, bus_data.mask()); +} + +TEST(BusOut_mask, led_nc_nc_nc_nc) +{ + BusOut bus_data(NC, NC, NC, NC); + CHECK_EQUAL(0x00, bus_data.mask()); +} + +TEST(BusOut_mask, led_1_2_3_nc_nc) +{ + BusOut bus_data(LED1, LED2, LED3, NC, NC); + CHECK_EQUAL(0x07, bus_data.mask()); +} + +TEST(BusOut_mask, led_1_nc_2_nc_nc_3) +{ + BusOut bus_data(LED1, NC, LED2, NC, NC, LED3); + CHECK_EQUAL(0x25, bus_data.mask()); +} + +/////////////////////////////////////////////////////////////////////////////// + +TEST_GROUP(BusOut_dummy) +{ +}; + +TEST(BusOut_dummy, dummy) +{ +} + +#ifdef MBED_OPERATORS +TEST_GROUP(BusOut_digitalout_write) +{ +}; + +TEST(BusOut_digitalout_write, led_nc) +{ + BusOut bus_data(NC); + CHECK_EQUAL(false, bus_data[0].is_connected()) +} + + +TEST(BusOut_digitalout_write, led_1_2_3) +{ + BusOut bus_data(LED1, LED2, LED3); + bus_data[0].write(1); + bus_data[1].write(1); + bus_data[2].write(1); + CHECK(bus_data[0].read()); + CHECK(bus_data[1].read()); + CHECK(bus_data[2].read()); +} + +TEST(BusOut_digitalout_write, led_1_2_3_nc_nc) +{ + BusOut bus_data(LED1, LED2, LED3, NC, NC); + bus_data[0].write(0); + bus_data[1].write(0); + bus_data[2].write(0); + CHECK(bus_data[0].read() == 0); + CHECK(bus_data[1].read() == 0); + CHECK(bus_data[2].read() == 0); +} + +TEST(BusOut_digitalout_write, led_1_nc_2_nc_nc_3) +{ + BusOut bus_data(LED1, NC, LED2, NC, NC, LED3); + bus_data[0].write(1); + bus_data[2].write(0); + bus_data[5].write(0); + CHECK(bus_data[0].read()); + CHECK(bus_data[2].read() == 0); + CHECK(bus_data[5].read() == 0); +} +#endif diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index dd8ed79c90..e6d27cbbda 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -262,6 +262,14 @@ TESTS = [ "duration": 15, }, + { + "id": "MBED_BUSOUT", "description": "BusOut", + "source_dir": join(TEST_DIR, "mbed", "bus_out"), + "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB], + "automated": True, + "duration": 15, + }, + # Size benchmarks { "id": "BENCHMARK_1", "description": "Size (c environment)", @@ -527,7 +535,7 @@ TESTS = [ "automated": True, "host_test": "wait_us_auto" }, - + # CMSIS RTOS tests { @@ -899,6 +907,12 @@ TESTS = [ "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY], "automated": False, }, + { + "id": "UT_BUSIO", "description": "BusIn BusOut", + "source_dir": join(TEST_DIR, "utest", "bus"), + "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY], + "automated": False, + }, # Tests used for target information purposes { From 2af565c827181a833e0fb1d6215676efd1552001 Mon Sep 17 00:00:00 2001 From: Olaf Hagendorf Date: Tue, 30 Dec 2014 19:21:09 +0100 Subject: [PATCH 12/77] Update README.md --- workspace_tools/export/README.md | 1089 ++++++++++++++++++++++++------ 1 file changed, 901 insertions(+), 188 deletions(-) diff --git a/workspace_tools/export/README.md b/workspace_tools/export/README.md index 768b79cbfe..ca87279f63 100644 --- a/workspace_tools/export/README.md +++ b/workspace_tools/export/README.md @@ -1,195 +1,908 @@ -Exporter Toolchain/Platform Support +Exporter IDE/Platform Support ----------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
LPCXpressoCode SourceryCoIDEDS-5GCC ARMIARKEIL uVision
NXP LPC1768✓✓✓✓✓✓✓
NXP LPC1549✓✓✓✓
NXP LPC11U24✓✓✓
NXP LPC812✓✓✓
NXP LPC4088✓✓✓✓
NXP LPC1347✓✓
NXP LPC1114✓✓✓
Freescale KL05Z✓✓✓✓
Freescale KL20D5M✓✓
Freescale KL25Z✓✓✓✓
Freescale KL46Z✓✓✓
Freescale K64F✓✓
ST Nucleo F030R8✓✓
ST Nucleo F103RB✓✓
Platformcodesourcerycoideds5_5emblocksgcc_armiarkdslpcxpressouvision
ST Nucleo F302R8✓✓
ST Nucleo F401RE✓✓
ST Nucleo L152RE✓✓
ARCH_BLE---✓✓---✓
Nordic NRF51822✓
ARCH_GPRS---✓-----
ARCH_MAX---✓✓---✓
ARCH_PRO✓✓✓✓✓✓-✓✓
ARM_MPS2---✓-----
BLE_SMURFS---✓✓---✓
BLE_SMURFS_OTA---✓-----
DISCO_F051R8---✓✓----
DISCO_F100RB---✓✓----
DISCO_F303VC-✓-✓✓----
DISCO_F334C8-✓-✓✓----
DISCO_F407VG-✓-✓✓---✓
DISCO_F429ZI-✓-✓✓----
DISCO_L053C8---✓✓----
HRM1017---✓✓---✓
K20D50M---✓✓✓--✓
K22F---✓✓✓✓-✓
K64F---✓✓✓✓-✓
KL05Z-✓-✓✓✓--✓
KL25Z-✓-✓✓✓--✓
KL43Z---✓✓---✓
KL46Z---✓✓✓--✓
LPC1114---✓✓✓-✓✓
LPC11C24---✓----✓
LPC11U24--✓✓✓✓--✓
LPC11U24_301---✓-----
LPC11U35_401---✓✓✓-✓-
LPC11U35_501---✓✓✓-✓-
LPC11U35_Y5_MBUG---✓-----
LPC11U37_501---✓-----
LPC11U68---✓---✓-
LPC1347---✓-✓--✓
LPC1549---✓✓✓-✓✓
LPC1768✓✓✓✓✓✓-✓✓
LPC2368---✓✓----
LPC4088---✓✓✓-✓✓
LPC4330_M0---------
LPC4330_M4---✓✓--✓✓
LPC4337--------✓
LPC810---------
LPC812--✓--✓--✓
LPC824---✓-----
LPCCAPPUCCINO---✓✓✓-✓-
MTS_GAMBIT---✓✓---✓
MTS_MDOT_F405RG-✓-✓✓✓--✓
MTS_MDOT_F411RE-✓-✓✓✓---
NRF51822---✓✓---✓
NRF51822_OTA---✓-----
NRF51822_Y5_MBUG---✓-----
NRF51_DK---✓✓---✓
NRF51_DK_OTA---✓-----
NRF51_DONGLE---✓✓---✓
NUCLEO_F030R8-✓-✓✓✓--✓
NUCLEO_F070RB---✓✓✓--✓
NUCLEO_F072RB-✓-✓✓✓--✓
NUCLEO_F091RC-----✓--✓
NUCLEO_F103RB---✓-✓--✓
NUCLEO_F302R8-✓-✓✓✓--✓
NUCLEO_F303RE-----✓--✓
NUCLEO_F334R8-✓-✓✓✓--✓
NUCLEO_F401RE-✓-✓✓✓--✓
NUCLEO_F411RE-✓-✓✓✓--✓
NUCLEO_L053R8---✓✓✓--✓
NUCLEO_L152RE-✓-✓✓✓--✓
OC_MBUINO---✓-----
RBLAB_BLENANO---✓-----
RBLAB_NRF51822---✓-----
RZ_A1H---------
SSCI824---------
STM32F3XX---✓-----
STM32F407---✓✓✓---
UBLOX_C027✓✓✓✓✓✓-✓✓
WALLBOT_BLE---✓-----
XADOW_M0---✓-----
+Total IDEs: 9 +
Total platforms: 74 +
Total permutations: 225 From b57fefbd0c19e7d3e25582f2af044fc7aaa5b6d2 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Tue, 30 Dec 2014 19:26:43 +0100 Subject: [PATCH 13/77] [workspace_tools] project.py adding 2 cmdline options - Adding an option to print a matrix similar to build.py -S with targets and supported IDEs - Adding an option to write README.md in workspace_tools/export --- workspace_tools/export/__init__.py | 58 +++++++++++++++++++++++++++++- workspace_tools/project.py | 32 ++++++++++++++++- 2 files changed, 88 insertions(+), 2 deletions(-) diff --git a/workspace_tools/export/__init__.py b/workspace_tools/export/__init__.py index e35785a66f..8cba2a453b 100644 --- a/workspace_tools/export/__init__.py +++ b/workspace_tools/export/__init__.py @@ -21,7 +21,7 @@ from shutil import copytree, rmtree from workspace_tools.utils import mkdir from workspace_tools.export import uvision4, codesourcery, codered, gccarm, ds5_5, iar, emblocks, coide, kds from workspace_tools.export.exporters import zip_working_directory_and_clean_up, OldLibrariesException -from workspace_tools.targets import EXPORT_MAP +from workspace_tools.targets import TARGET_NAMES, EXPORT_MAP EXPORTERS = { 'uvision': uvision4.Uvision4, @@ -118,3 +118,59 @@ def setup_user_prj(user_dir, prj_path, lib_paths=None): if lib_paths is not None: for lib_path in lib_paths: copy_tree(lib_path, join(user_lib, basename(lib_path))) + +def get_unique_supported_ides(): + """ Get list of all unique IDEs supported by targets """ + unique_supported_ides = [] + for key in EXPORTERS.iterkeys(): + unique_supported_ides.append(key) + return unique_supported_ides + +def mcu_ide_matrix(verbose_html=False, platform_filter=None): + """ Shows target map using prettytable """ + supported_ides = [] + for key in EXPORTERS.iterkeys(): + supported_ides.append(key) + supported_ides.sort() + from prettytable import PrettyTable, ALL # Only use it in this function so building works without extra modules + + # All tests status table print + columns = ["Platform"] + supported_ides + pt = PrettyTable(columns) + # Align table + for col in columns: + pt.align[col] = "c" + pt.align["Platform"] = "l" + + perm_counter = 0 + target_counter = 0 + for target in sorted(TARGET_NAMES): + target_counter += 1 + + row = [target] # First column is platform name + for ide in supported_ides: + text = "-" + if target in EXPORTERS[ide].TARGETS: + if verbose_html: + text = "✓" + else: + text = "x" + perm_counter += 1 + row.append(text) + pt.add_row(row) + + pt.border = True + pt.vrules = ALL + pt.hrules = ALL + # creates a html page suitable for a browser + # result = pt.get_html_string(format=True) if verbose_html else pt.get_string() + # creates a html page in a shorter format suitable for readme.md + result = pt.get_html_string() if verbose_html else pt.get_string() + result += "\n" + result += "Total IDEs: %d\n"% (len(supported_ides)) + if verbose_html: result += "
" + result += "Total platforms: %d\n"% (target_counter) + if verbose_html: result += "
" + result += "Total permutations: %d"% (perm_counter) + if verbose_html: result = result.replace("&", "&") + return result diff --git a/workspace_tools/project.py b/workspace_tools/project.py index 234fbd1e04..6f7fd1c473 100644 --- a/workspace_tools/project.py +++ b/workspace_tools/project.py @@ -8,7 +8,7 @@ from optparse import OptionParser from workspace_tools.paths import EXPORT_DIR, EXPORT_WORKSPACE, EXPORT_TMP from workspace_tools.paths import MBED_BASE, MBED_LIBRARIES -from workspace_tools.export import export, setup_user_prj, EXPORTERS +from workspace_tools.export import export, setup_user_prj, EXPORTERS, mcu_ide_matrix from workspace_tools.utils import args_error from workspace_tools.tests import TESTS, Test, TEST_MAP from workspace_tools.targets import TARGET_NAMES @@ -65,6 +65,18 @@ if __name__ == '__main__': default=False, help="list available programs in order and exit") + parser.add_option("-S", "--list-matrix", + action="store_true", + dest="supported_ides", + default=False, + help="displays supported matrix of MCUs and IDEs") + + parser.add_option("-E", + action="store_true", + dest="supported_ides_html", + default=False, + help="writes workspace_tools/export/README.md") + (options, args) = parser.parse_args() # Print available tests in order and exit @@ -72,6 +84,24 @@ if __name__ == '__main__': print '\n'.join(map(str, sorted(TEST_MAP.values()))) sys.exit() + # Only prints matrix of supported IDEs + if options.supported_ides: + print mcu_ide_matrix() + exit(0) + + # Only prints matrix of supported IDEs + if options.supported_ides_html: + html = mcu_ide_matrix(verbose_html=True) + f = open("./export/README.md","w") + try: + f.write("Exporter IDE/Platform Support\n") + f.write("-----------------------------------\n") + f.write("\n"); + f.write(html) + finally: + f.close() + exit(0) + # Clean Export Directory if options.clean: if exists(EXPORT_DIR): From f75f3c92e3b95eedb9fa1b082d03e6d7bc885b2e Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Tue, 30 Dec 2014 20:08:36 +0100 Subject: [PATCH 14/77] [workspace_tools] project.py adding 2 cmdline options Forgot to remove an unsed method. --- workspace_tools/export/__init__.py | 7 ------- 1 file changed, 7 deletions(-) diff --git a/workspace_tools/export/__init__.py b/workspace_tools/export/__init__.py index 8cba2a453b..0b7164d73a 100644 --- a/workspace_tools/export/__init__.py +++ b/workspace_tools/export/__init__.py @@ -119,13 +119,6 @@ def setup_user_prj(user_dir, prj_path, lib_paths=None): for lib_path in lib_paths: copy_tree(lib_path, join(user_lib, basename(lib_path))) -def get_unique_supported_ides(): - """ Get list of all unique IDEs supported by targets """ - unique_supported_ides = [] - for key in EXPORTERS.iterkeys(): - unique_supported_ides.append(key) - return unique_supported_ides - def mcu_ide_matrix(verbose_html=False, platform_filter=None): """ Shows target map using prettytable """ supported_ides = [] From 7d54c823316f24297cd20092e8bc1305d591b351 Mon Sep 17 00:00:00 2001 From: Przemek Wirkus Date: Tue, 6 Jan 2015 08:32:16 +0000 Subject: [PATCH 15/77] * Changed Bus operator[]() parameter from unsigned int to int to match mbed code guidelines. * Uncommented assertions in operators and added check for operator[] index < 0. * Moved one operator from private to public, this was a typo thing. --- libraries/mbed/api/BusIn.h | 2 +- libraries/mbed/api/BusInOut.h | 5 ++++- libraries/mbed/api/BusOut.h | 2 +- libraries/mbed/common/BusIn.cpp | 6 +++--- libraries/mbed/common/BusInOut.cpp | 6 +++--- libraries/mbed/common/BusOut.cpp | 6 +++--- 6 files changed, 15 insertions(+), 12 deletions(-) diff --git a/libraries/mbed/api/BusIn.h b/libraries/mbed/api/BusIn.h index 837a71bcec..6f20875fa4 100644 --- a/libraries/mbed/api/BusIn.h +++ b/libraries/mbed/api/BusIn.h @@ -77,7 +77,7 @@ public: /** Access to particular bit in random-iterator fashion */ - DigitalIn & operator[] (unsigned int index); + DigitalIn & operator[] (int index); #endif protected: diff --git a/libraries/mbed/api/BusInOut.h b/libraries/mbed/api/BusInOut.h index 9d3c38154d..e9a12c5f92 100644 --- a/libraries/mbed/api/BusInOut.h +++ b/libraries/mbed/api/BusInOut.h @@ -90,6 +90,10 @@ public: BusInOut& operator= (int v); BusInOut& operator= (BusInOut& rhs); + /** Access to particular bit in random-iterator fashion + */ + DigitalInOut& operator[] (int index); + /** A shorthand for read() */ operator int(); @@ -108,7 +112,6 @@ protected: private: BusInOut(const BusInOut&); BusInOut & operator = (const BusInOut&); - DigitalInOut& operator[] (unsigned int index); }; } // namespace mbed diff --git a/libraries/mbed/api/BusOut.h b/libraries/mbed/api/BusOut.h index b979b3f16a..9e88e2d170 100644 --- a/libraries/mbed/api/BusOut.h +++ b/libraries/mbed/api/BusOut.h @@ -76,7 +76,7 @@ public: /** Access to particular bit in random-iterator fashion */ - DigitalOut& operator[] (unsigned int index); + DigitalOut& operator[] (int index); /** A shorthand for read() */ diff --git a/libraries/mbed/common/BusIn.cpp b/libraries/mbed/common/BusIn.cpp index 2858ccc2ea..dbecf4a9a7 100644 --- a/libraries/mbed/common/BusIn.cpp +++ b/libraries/mbed/common/BusIn.cpp @@ -72,9 +72,9 @@ BusIn::operator int() { return read(); } -DigitalIn& BusIn::operator[] (unsigned int index) { - //MBED_ASSERT(index >= MBED_BUS_SIZE); - //MBED_ASSERT(_pin[index]); +DigitalIn& BusIn::operator[] (int index) { + MBED_ASSERT(index < 0 || index >= MBED_BUS_SIZE); + MBED_ASSERT(_pin[index]); if (index >= 16 || _pin[index] == NULL) { return din_dummy; } diff --git a/libraries/mbed/common/BusInOut.cpp b/libraries/mbed/common/BusInOut.cpp index e3a1182aba..d4ed0bda12 100644 --- a/libraries/mbed/common/BusInOut.cpp +++ b/libraries/mbed/common/BusInOut.cpp @@ -102,9 +102,9 @@ BusInOut& BusInOut::operator= (BusInOut& rhs) { return *this; } -DigitalInOut& BusInOut::operator[] (unsigned int index) { - //MBED_ASSERT(index >= MBED_BUS_SIZE); - //MBED_ASSERT(_pin[index]); +DigitalInOut& BusInOut::operator[] (int index) { + MBED_ASSERT(index < 0 || index >= MBED_BUS_SIZE); + MBED_ASSERT(_pin[index]); if (index >= 16 || _pin[index] == NULL) { return dinout_dummy; } diff --git a/libraries/mbed/common/BusOut.cpp b/libraries/mbed/common/BusOut.cpp index 445b3f8658..9d94a4c9d7 100644 --- a/libraries/mbed/common/BusOut.cpp +++ b/libraries/mbed/common/BusOut.cpp @@ -78,9 +78,9 @@ BusOut& BusOut::operator= (BusOut& rhs) { return *this; } -DigitalOut& BusOut::operator[] (unsigned int index) { - //MBED_ASSERT(index >= MBED_BUS_SIZE); - //MBED_ASSERT(_pin[index]); +DigitalOut& BusOut::operator[] (int index) { + MBED_ASSERT(index < 0 || index >= MBED_BUS_SIZE); + MBED_ASSERT(_pin[index]); if (index >= 16 || _pin[index] == NULL) { return dout_dummy; } From d068a2b4794a08636fed04ea139c910082dbf1fe Mon Sep 17 00:00:00 2001 From: Przemek Wirkus Date: Tue, 6 Jan 2015 08:42:49 +0000 Subject: [PATCH 16/77] Replaced const define with hardcoded bus size of 16 --- libraries/mbed/common/BusIn.cpp | 2 +- libraries/mbed/common/BusInOut.cpp | 2 +- libraries/mbed/common/BusOut.cpp | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/libraries/mbed/common/BusIn.cpp b/libraries/mbed/common/BusIn.cpp index dbecf4a9a7..5ec8cbb8f2 100644 --- a/libraries/mbed/common/BusIn.cpp +++ b/libraries/mbed/common/BusIn.cpp @@ -73,7 +73,7 @@ BusIn::operator int() { } DigitalIn& BusIn::operator[] (int index) { - MBED_ASSERT(index < 0 || index >= MBED_BUS_SIZE); + MBED_ASSERT(index < 0 || index >= 16); MBED_ASSERT(_pin[index]); if (index >= 16 || _pin[index] == NULL) { return din_dummy; diff --git a/libraries/mbed/common/BusInOut.cpp b/libraries/mbed/common/BusInOut.cpp index d4ed0bda12..bd8bc82726 100644 --- a/libraries/mbed/common/BusInOut.cpp +++ b/libraries/mbed/common/BusInOut.cpp @@ -103,7 +103,7 @@ BusInOut& BusInOut::operator= (BusInOut& rhs) { } DigitalInOut& BusInOut::operator[] (int index) { - MBED_ASSERT(index < 0 || index >= MBED_BUS_SIZE); + MBED_ASSERT(index < 0 || index >= 16); MBED_ASSERT(_pin[index]); if (index >= 16 || _pin[index] == NULL) { return dinout_dummy; diff --git a/libraries/mbed/common/BusOut.cpp b/libraries/mbed/common/BusOut.cpp index 9d94a4c9d7..86b2acb29a 100644 --- a/libraries/mbed/common/BusOut.cpp +++ b/libraries/mbed/common/BusOut.cpp @@ -79,7 +79,7 @@ BusOut& BusOut::operator= (BusOut& rhs) { } DigitalOut& BusOut::operator[] (int index) { - MBED_ASSERT(index < 0 || index >= MBED_BUS_SIZE); + MBED_ASSERT(index < 0 || index >= 16); MBED_ASSERT(_pin[index]); if (index >= 16 || _pin[index] == NULL) { return dout_dummy; From c18633dcf27645e42c299b504a045f900921f27a Mon Sep 17 00:00:00 2001 From: Rohit Grover Date: Tue, 25 Nov 2014 09:17:57 +0000 Subject: [PATCH 17/77] switching timestamp_t back to 32-bits. The underlying us_tickers used for comparison are still 32-bits; keeping a 64-bit timestamp isn't going to be useful. fixes #838 --- libraries/mbed/hal/us_ticker_api.h | 2 +- .../targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/libraries/mbed/hal/us_ticker_api.h b/libraries/mbed/hal/us_ticker_api.h index ea62d7c06f..b7df3b57a1 100644 --- a/libraries/mbed/hal/us_ticker_api.h +++ b/libraries/mbed/hal/us_ticker_api.h @@ -22,7 +22,7 @@ extern "C" { #endif -typedef uint64_t timestamp_t; +typedef uint32_t timestamp_t; uint32_t us_ticker_read(void); diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c index d544106d25..aea896a9c3 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c @@ -40,7 +40,7 @@ uint32_t us_ticker_read() us_ticker_init(); } - timestamp_t value; + uint64_t value; app_timer_cnt_get(&value); /* This returns the RTC counter (which is fed by the 32khz crystal clock source) */ return ((value * 1000000) / (uint32_t)APP_TIMER_CLOCK_FREQ); /* Return a pseudo microsecond counter value. * This is only as precise as the 32khz low-freq @@ -72,7 +72,7 @@ void us_ticker_set_interrupt(timestamp_t timestamp) return; } - timestamp_t currentCounter64; + uint64_t currentCounter64; app_timer_cnt_get(¤tCounter64); uint32_t currentCounter = currentCounter64 & MAX_RTC_COUNTER_VAL; uint32_t targetCounter = ((uint32_t)((timestamp * (uint64_t)APP_TIMER_CLOCK_FREQ) / 1000000) + 1) & MAX_RTC_COUNTER_VAL; From e7a9c01708f590f820775812a97ebfe6f54d8aa4 Mon Sep 17 00:00:00 2001 From: Rohit Grover Date: Tue, 6 Jan 2015 09:43:03 +0000 Subject: [PATCH 18/77] update us_ticker_appTimerRunning after a call to app_timer_stop() --- .../hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c index aea896a9c3..1ac290aaba 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c @@ -94,13 +94,17 @@ void us_ticker_set_interrupt(timestamp_t timestamp) void us_ticker_disable_interrupt(void) { if (us_ticker_appTimerRunning) { - app_timer_stop(us_ticker_appTimerID); + if (app_timer_stop(us_ticker_appTimerID) == NRF_SUCCESS) { + us_ticker_appTimerRunning = false; + } } } void us_ticker_clear_interrupt(void) { if (us_ticker_appTimerRunning) { - app_timer_stop(us_ticker_appTimerID); + if (app_timer_stop(us_ticker_appTimerID) == NRF_SUCCESS) { + us_ticker_appTimerRunning = false; + } } } From f7a78073e8df7b114d34da23905733221d14d78a Mon Sep 17 00:00:00 2001 From: Rohit Grover Date: Wed, 7 Jan 2015 12:38:17 +0000 Subject: [PATCH 19/77] add 1 to the scheduler-op pool to allow deleting a timer whilst in its handler. Please note that this commit goes with another recent commit to the nRF51822 repository which updated values under projectconfig.h. Please remember to update nRF51822 as well. This has a bearing on issue #832. --- .../targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c index 1ac290aaba..4834db308d 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c @@ -18,6 +18,7 @@ #include "cmsis.h" #include "PeripheralNames.h" #include "app_timer.h" +#include "projectconfig.h" static bool us_ticker_inited = false; static volatile bool us_ticker_appTimerRunning = false; @@ -29,7 +30,7 @@ void us_ticker_init(void) return; } - APP_TIMER_INIT(0 /*CFG_TIMER_PRESCALER*/ , 1 /*CFG_TIMER_MAX_INSTANCE*/, 1 /*CFG_TIMER_OPERATION_QUEUE_SIZE*/, false /*CFG_SCHEDULER_ENABLE*/); + APP_TIMER_INIT(CFG_TIMER_PRESCALER, CFG_TIMER_MAX_INSTANCE, CFG_TIMER_OPERATION_QUEUE_SIZE, CFG_SCHEDULER_ENABLE); us_ticker_inited = true; } From c8b9b9c2f58a596364064a5e9a63279c32ab32cf Mon Sep 17 00:00:00 2001 From: Rohit Grover Date: Mon, 12 Jan 2015 07:58:31 +0000 Subject: [PATCH 20/77] add a declaration for the signed version of timestamp_t; used in a comparison --- libraries/mbed/common/us_ticker_api.c | 2 +- libraries/mbed/hal/us_ticker_api.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/libraries/mbed/common/us_ticker_api.c b/libraries/mbed/common/us_ticker_api.c index 3c803a3c37..19d5997ece 100644 --- a/libraries/mbed/common/us_ticker_api.c +++ b/libraries/mbed/common/us_ticker_api.c @@ -70,7 +70,7 @@ void us_ticker_insert_event(ticker_event_t *obj, timestamp_t timestamp, uint32_t ticker_event_t *prev = NULL, *p = head; while (p != NULL) { /* check if we come before p */ - if ((int64_t)(timestamp - p->timestamp) < 0) { + if ((signedTimestamp_t)(timestamp - p->timestamp) < 0) { break; } /* go to the next element */ diff --git a/libraries/mbed/hal/us_ticker_api.h b/libraries/mbed/hal/us_ticker_api.h index b7df3b57a1..ace3942919 100644 --- a/libraries/mbed/hal/us_ticker_api.h +++ b/libraries/mbed/hal/us_ticker_api.h @@ -23,6 +23,7 @@ extern "C" { #endif typedef uint32_t timestamp_t; +typedef int32_t signedTimestamp_t; /* The signed version of the above declaration. */ uint32_t us_ticker_read(void); From fb2ed147689469d800b50f52a0a0b9160214d217 Mon Sep 17 00:00:00 2001 From: bcostm Date: Mon, 12 Jan 2015 16:30:05 +0100 Subject: [PATCH 21/77] [NUCLEO_F303RE] Correct ADC initialization Same as #809 --- .../TARGET_NUCLEO_F303RE/analogin_api.c | 87 ++++++++++--------- 1 file changed, 47 insertions(+), 40 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogin_api.c index dc5cd4d5cc..487a993316 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogin_api.c @@ -37,13 +37,13 @@ ADC_HandleTypeDef AdcHandle; -int adc1_inited = 0; -int adc2_inited = 0; -int adc3_inited = 0; -int adc4_inited = 0; - void analogin_init(analogin_t *obj, PinName pin) { + static int adc1_inited = 0; + static int adc2_inited = 0; + static int adc3_inited = 0; + static int adc4_inited = 0; + // Get the peripheral name from the pin and assign it to the object obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); MBED_ASSERT(obj->adc != (ADCName)NC); @@ -54,42 +54,49 @@ void analogin_init(analogin_t *obj, PinName pin) // Save pin number for the read function obj->pin = pin; - // The ADC initialization is done only once for each ADC - if ((adc1_inited == 0) || (adc2_inited == 0) || (adc3_inited == 0) || (adc4_inited == 0)) { - if (obj->adc == ADC_1) { - __ADC12_CLK_ENABLE(); - adc1_inited = 1; - } - if (obj->adc == ADC_2) { - __ADC12_CLK_ENABLE(); - adc2_inited = 1; - } - if (obj->adc == ADC_3) { - __ADC34_CLK_ENABLE(); - adc3_inited = 1; - } - if (obj->adc == ADC_4) { - __ADC34_CLK_ENABLE(); - adc4_inited = 1; - } - // Configure ADC - AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); - AdcHandle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV2; - AdcHandle.Init.Resolution = ADC_RESOLUTION12b; - AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT; - AdcHandle.Init.ScanConvMode = DISABLE; - AdcHandle.Init.EOCSelection = DISABLE; - AdcHandle.Init.LowPowerAutoWait = DISABLE; - AdcHandle.Init.ContinuousConvMode = DISABLE; - AdcHandle.Init.NbrOfConversion = 1; - AdcHandle.Init.DiscontinuousConvMode = DISABLE; - AdcHandle.Init.NbrOfDiscConversion = 0; - AdcHandle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1; - AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - AdcHandle.Init.DMAContinuousRequests = DISABLE; - AdcHandle.Init.Overrun = OVR_DATA_OVERWRITTEN; - HAL_ADC_Init(&AdcHandle); + // Check if ADC is already initialized + if ((obj->adc == ADC_1) && adc1_inited) return; + if ((obj->adc == ADC_2) && adc2_inited) return; + if ((obj->adc == ADC_3) && adc3_inited) return; + if ((obj->adc == ADC_4) && adc4_inited) return; + + if (obj->adc == ADC_1) { + __ADC12_CLK_ENABLE(); + adc1_inited = 1; } + + if (obj->adc == ADC_2) { + __ADC12_CLK_ENABLE(); + adc2_inited = 1; + } + + if (obj->adc == ADC_3) { + __ADC34_CLK_ENABLE(); + adc3_inited = 1; + } + + if (obj->adc == ADC_4) { + __ADC34_CLK_ENABLE(); + adc4_inited = 1; + } + + // Configure ADC + AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); + AdcHandle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV2; + AdcHandle.Init.Resolution = ADC_RESOLUTION12b; + AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT; + AdcHandle.Init.ScanConvMode = DISABLE; + AdcHandle.Init.EOCSelection = DISABLE; + AdcHandle.Init.LowPowerAutoWait = DISABLE; + AdcHandle.Init.ContinuousConvMode = DISABLE; + AdcHandle.Init.NbrOfConversion = 1; + AdcHandle.Init.DiscontinuousConvMode = DISABLE; + AdcHandle.Init.NbrOfDiscConversion = 0; + AdcHandle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1; + AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + AdcHandle.Init.DMAContinuousRequests = DISABLE; + AdcHandle.Init.Overrun = OVR_DATA_OVERWRITTEN; + HAL_ADC_Init(&AdcHandle); } static inline uint16_t adc_read(analogin_t *obj) From 7726496957bca8382f741bc8ac55c35dceb4a609 Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Thu, 15 Jan 2015 14:00:42 +0900 Subject: [PATCH 22/77] Implement some USB functions to RZ-A1H Implemented functions as below. - USB Host - USB Device(Full speed) --- .../USBDevice/USBDevice/USBHAL_RZ_A1H.cpp | 757 +++-- .../TARGET_RZ_A1H/inc/devdrv_usb_host_api.h | 332 ++ .../TARGET_RZ_A1H/inc/usb0_host.h | 156 + .../TARGET_RZ_A1H/inc/usb0_host_api.h | 112 + .../TARGET_RZ_A1H/inc/usb0_host_dmacdrv.h | 139 + .../TARGET_RZ_A1H/inc/usb_host.h | 201 ++ .../TARGET_RZ_A1H/inc/usb_host_version.h | 32 + .../TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c | 1051 ++++++ .../TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h | 60 + .../TARGET_RZ_A1H/ohci_wrapp_RZ_A1_local.h | 49 + .../src/common/usb0_host_dataio.c | 2835 +++++++++++++++++ .../TARGET_RZ_A1H/src/common/usb0_host_dma.c | 355 +++ .../src/common/usb0_host_intrn.c | 285 ++ .../TARGET_RZ_A1H/src/common/usb0_host_lib.c | 1580 +++++++++ .../src/host/usb0_host_controlrw.c | 434 +++ .../src/host/usb0_host_drv_api.c | 889 ++++++ .../TARGET_RZ_A1H/src/host/usb0_host_global.c | 137 + .../TARGET_RZ_A1H/src/host/usb0_host_usbint.c | 496 +++ .../TARGET_RZ_A1H/src/host/usb0_host_usbsig.c | 637 ++++ .../src/userdef/usb0_host_dmacdrv.c | 698 ++++ .../src/userdef/usb0_host_ohci_wrapp_pipe.c | 156 + .../src/userdef/usb0_host_userdef.c | 770 +++++ .../{USBHALHost.cpp => USBHALHost_LPC17.cpp} | 3 + .../USBHost/USBHost/USBHALHost_RZ_A1.cpp | 293 ++ libraries/USBHost/USBHostHub/USBHostHub.cpp | 3 + .../TARGET_RZ_A1H}/rza_io_regrw.c | 0 26 files changed, 12215 insertions(+), 245 deletions(-) create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_host_api.h create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host.h create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_api.h create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_dmacdrv.h create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host.h create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host_version.h create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1_local.h create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dataio.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dma.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_intrn.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_lib.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_controlrw.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_drv_api.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_global.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbint.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbsig.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_dmacdrv.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_ohci_wrapp_pipe.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_userdef.c rename libraries/USBHost/USBHost/{USBHALHost.cpp => USBHALHost_LPC17.cpp} (99%) create mode 100644 libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp rename libraries/{USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef => mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H}/rza_io_regrw.c (100%) diff --git a/libraries/USBDevice/USBDevice/USBHAL_RZ_A1H.cpp b/libraries/USBDevice/USBDevice/USBHAL_RZ_A1H.cpp index 04ae139095..75378b821b 100644 --- a/libraries/USBDevice/USBDevice/USBHAL_RZ_A1H.cpp +++ b/libraries/USBDevice/USBDevice/USBHAL_RZ_A1H.cpp @@ -1,19 +1,26 @@ /* Copyright (c) 2010-2011 mbed.org, MIT License * -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: +* Permission is hereby granted, free of charge, to any person +* obtaining a copy of this software and associated documentation +* files (the "Software"), to deal in the Software without +* restriction, including without limitation the rights to use, +* copy, modify, merge, publish, distribute, sublicense, and/or +* sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following +* conditions: * -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. +* The above copyright notice and this permission notice shall be +* included in all copies or substantial portions of the +* Software. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY +* KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +* PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #if defined(TARGET_RZ_A1H) @@ -59,8 +66,9 @@ const struct PIPECFGREC { USB_FUNCTION_DIR_P_OUT | USB_FUNCTION_EP1, ( ( ( 64) / 64 - 1 ) << 10 ) | 0x04u, - 64, - DEVDRV_USBF_OFF | 0, + MAX_PACKET_SIZE_EP1, + DEVDRV_USBF_OFF | + ( 3 << USB_PIPEPERI_IITV_SHIFT ), }, { EP1IN, /*EP1: Host <- Func, INT*/ @@ -73,8 +81,9 @@ const struct PIPECFGREC { USB_FUNCTION_DIR_P_IN | USB_FUNCTION_EP1, ( ( ( 64) / 64 - 1 ) << 10 ) | 0x05u, - 64, - DEVDRV_USBF_OFF | 0, + MAX_PACKET_SIZE_EP1, + DEVDRV_USBF_OFF | + ( 3 << USB_PIPEPERI_IITV_SHIFT ), }, { EP2OUT, /*EP2: Host -> Func, BULK*/ @@ -87,8 +96,9 @@ const struct PIPECFGREC { USB_FUNCTION_DIR_P_OUT | USB_FUNCTION_EP2, ( ( (2048) / 64 - 1 ) << 10 ) | 0x30u, - 512, - DEVDRV_USBF_OFF | 0, + MAX_PACKET_SIZE_EP2, + DEVDRV_USBF_OFF | + ( 0 << USB_PIPEPERI_IITV_SHIFT ), }, { EP2IN, /*EP2: Host <- Func, BULK*/ @@ -101,8 +111,9 @@ const struct PIPECFGREC { USB_FUNCTION_DIR_P_IN | USB_FUNCTION_EP2, ( ( (2048) / 64 - 1 ) << 10 ) | 0x50u, - 512, - DEVDRV_USBF_OFF | 0, + MAX_PACKET_SIZE_EP2, + DEVDRV_USBF_OFF | + ( 0 << USB_PIPEPERI_IITV_SHIFT ), }, { EP3OUT, /*EP3: Host -> Func, ISO*/ @@ -110,13 +121,14 @@ const struct PIPECFGREC { USB_FUNCTION_ISO | USB_FUNCTION_BFREOFF | USB_FUNCTION_DBLBON | - USB_FUNCTION_CNTMDON | + USB_FUNCTION_CNTMDOFF | USB_FUNCTION_SHTNAKON | USB_FUNCTION_DIR_P_OUT | USB_FUNCTION_EP3, - ( ( (1024) / 64 - 1 ) << 10 ) | 0x10u, - 192, - DEVDRV_USBF_OFF | 1, + ( ( ( 512) / 64 - 1 ) << 10 ) | 0x10u, + MAX_PACKET_SIZE_EP3, + DEVDRV_USBF_OFF | + ( 0 << USB_PIPEPERI_IITV_SHIFT ), }, { EP3IN, /*EP3: Host <- Func, ISO*/ @@ -124,13 +136,14 @@ const struct PIPECFGREC { USB_FUNCTION_ISO | USB_FUNCTION_BFREOFF | USB_FUNCTION_DBLBON | - USB_FUNCTION_CNTMDON | + USB_FUNCTION_CNTMDOFF | USB_FUNCTION_SHTNAKOFF | USB_FUNCTION_DIR_P_IN | USB_FUNCTION_EP3, - ( ( (1024) / 64 - 1 ) << 10 ) | 0x20u, - 192, - DEVDRV_USBF_OFF | 1, + ( ( ( 512) / 64 - 1 ) << 10 ) | 0x20u, + MAX_PACKET_SIZE_EP3, + DEVDRV_USBF_OFF | + ( 0 << USB_PIPEPERI_IITV_SHIFT ), }, { /*terminator*/ 0, 0, 0, 0, 0, @@ -142,13 +155,12 @@ const struct PIPECFGREC { /* workareas */ USBHAL * USBHAL::instance; - static IRQn_Type int_id; /* interrupt ID */ static uint16_t int_level; /* initerrupt level */ static uint16_t clock_mode; /* input clock selector */ static uint16_t mode; /* USB speed (HIGH/FULL) */ -static DigitalOut *usb0_en; +//static DigitalOut *usb0_en; static uint16_t EP0_read_status; static uint16_t EPx_read_status; @@ -160,17 +172,28 @@ static uint8_t recv_buffer[MAX_PACKET_SIZE_EPBULK]; volatile static uint16_t recv_error; - /*************************************************************************/ /* prototypes for C */ +extern "C" { + void usb0_function_BRDYInterruptPIPE0 (uint16_t status, uint16_t intenb, + USBHAL *object, void (USBHAL::*EP0func)(void)); + + void usb0_function_BRDYInterrupt (uint16_t status, uint16_t intenb, + USBHAL *object, bool (USBHAL::*epCallback[])(void)); + + void usb0_function_NRDYInterruptPIPE0(uint16_t status, uint16_t intenb, + USBHAL *object, void (USBHAL::*EP0func)(void)); + + void usb0_function_NRDYInterrupt (uint16_t status, uint16_t intenb, + USBHAL *object, bool (USBHAL::*epCallback[])(void)); + + void usb0_function_BEMPInterruptPIPE0(uint16_t status, uint16_t intenb, + USBHAL *object, void (USBHAL::*EP0func)(void)); + + void usb0_function_BEMPInterrupt (uint16_t status, uint16_t intenb, + USBHAL *object, bool (USBHAL::*epCallback[])(void)); +} -/* This C++ functions changed to macro functions. - static uint32_t EP2PIPE(uint8_t endpoint); - static void usb0_function_save_request(void); - void usb0_function_BRDYInterrupt(uint16_t status, uint16_t intenb); - void usb0_function_NRDYInterrupt (uint16_t status, uint16_t intenb); - void usb0_function_BEMPInterrupt (uint16_t status, uint16_t intenb); -*/ /*************************************************************************/ /* macros */ @@ -182,66 +205,72 @@ volatile static uint16_t recv_error; * : uint16_t intenb ; BRDYENB Register Value * Return Value : none *****************************************************************************/ -#define usb0_function_BRDYInterruptPIPE0(status, intenb) \ - { \ - volatile uint16_t dumy_sts; \ - uint16_t read_status; \ - \ - USB200.BRDYSTS = \ - (uint16_t)~g_usb0_function_bit_set[USB_FUNCTION_PIPE0]; \ - RZA_IO_RegWrite_16( \ - &USB200.CFIFOSEL, USB_FUNCTION_PIPE0, \ - USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE); \ - \ - g_usb0_function_PipeDataSize[USB_FUNCTION_PIPE0] = \ - g_usb0_function_data_count[USB_FUNCTION_PIPE0]; \ - \ - read_status = usb0_function_read_buffer_c(USB_FUNCTION_PIPE0); \ - \ - g_usb0_function_PipeDataSize[USB_FUNCTION_PIPE0] -= \ - g_usb0_function_data_count[USB_FUNCTION_PIPE0]; \ - \ - switch (read_status) { \ - case USB_FUNCTION_READING: /* Continue of data read */ \ - case USB_FUNCTION_READEND: /* End of data read */ \ - /* PID = BUF */ \ - usb0_function_set_pid_buf(USB_FUNCTION_PIPE0); \ - \ - /*callback*/ \ - EP0out(); \ - break; \ - \ - case USB_FUNCTION_READSHRT: /* End of data read */ \ - usb0_function_disable_brdy_int(USB_FUNCTION_PIPE0); \ - /* PID = BUF */ \ - usb0_function_set_pid_buf(USB_FUNCTION_PIPE0); \ - \ - /*callback*/ \ - EP0out(); \ - break; \ - \ - case USB_FUNCTION_READOVER: /* FIFO access error */ \ - /* Buffer Clear */ \ - USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; \ - usb0_function_disable_brdy_int(USB_FUNCTION_PIPE0); \ - /* Req Error */ \ - usb0_function_set_pid_stall(USB_FUNCTION_PIPE0); \ - \ - /*callback*/ \ - EP0out(); \ - break; \ - \ - case DEVDRV_USBF_FIFOERROR: /* FIFO access error */ \ - default: \ - usb0_function_disable_brdy_int(USB_FUNCTION_PIPE0); \ - /* Req Error */ \ - usb0_function_set_pid_stall(USB_FUNCTION_PIPE0); \ - break; \ - } \ - /* Three dummy reads for clearing interrupt requests */ \ - dumy_sts = USB200.BRDYSTS; \ - } +extern "C" { + void usb0_function_BRDYInterruptPIPE0 ( + uint16_t status, + uint16_t intenb, + USBHAL *object, + void (USBHAL::*EP0func)(void) + ) + { + volatile uint16_t dumy_sts; + uint16_t read_status; + USB200.BRDYSTS = + (uint16_t)~g_usb0_function_bit_set[USB_FUNCTION_PIPE0]; + RZA_IO_RegWrite_16( + &USB200.CFIFOSEL, USB_FUNCTION_PIPE0, + USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE); + + g_usb0_function_PipeDataSize[USB_FUNCTION_PIPE0] = + g_usb0_function_data_count[USB_FUNCTION_PIPE0]; + + read_status = usb0_function_read_buffer_c(USB_FUNCTION_PIPE0); + + g_usb0_function_PipeDataSize[USB_FUNCTION_PIPE0] -= + g_usb0_function_data_count[USB_FUNCTION_PIPE0]; + + switch (read_status) { + case USB_FUNCTION_READING: /* Continue of data read */ + case USB_FUNCTION_READEND: /* End of data read */ + /* PID = BUF */ + usb0_function_set_pid_buf(USB_FUNCTION_PIPE0); + + /*callback*/ + (object->*EP0func)(); + break; + + case USB_FUNCTION_READSHRT: /* End of data read */ + usb0_function_disable_brdy_int(USB_FUNCTION_PIPE0); + /* PID = BUF */ + usb0_function_set_pid_buf(USB_FUNCTION_PIPE0); + + /*callback*/ + (object->*EP0func)(); + break; + + case USB_FUNCTION_READOVER: /* FIFO access error */ + /* Buffer Clear */ + USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; + usb0_function_disable_brdy_int(USB_FUNCTION_PIPE0); + /* Req Error */ + usb0_function_set_pid_stall(USB_FUNCTION_PIPE0); + + /*callback*/ + (object->*EP0func)(); + break; + + case DEVDRV_USBF_FIFOERROR: /* FIFO access error */ + default: + usb0_function_disable_brdy_int(USB_FUNCTION_PIPE0); + /* Req Error */ + usb0_function_set_pid_stall(USB_FUNCTION_PIPE0); + break; + } + /* Three dummy reads for clearing interrupt requests */ + dumy_sts = USB200.BRDYSTS; + } +} /****************************************************************************** @@ -251,85 +280,100 @@ volatile static uint16_t recv_error; * : uint16_t intenb ; BRDYENB Register Value * Return Value : none *****************************************************************************/ -#define usb0_function_BRDYInterrupt(status, intenb) \ - { \ - volatile uint16_t dumy_sts; \ - \ - /************************************************************** \ - * Function Name: usb0_function_brdy_int \ - * Description : Executes BRDY interrupt(USB_FUNCTION_PIPE1-9). \ - * : According to the pipe that interrupt is generated in, \ - * : reads/writes buffer allocated in the pipe. \ - * : This function is executed in the BRDY \ - * : interrupt handler. This function \ - * : clears BRDY interrupt status and BEMP \ - * : interrupt status. \ - * Arguments : uint16_t Status ; BRDYSTS Register Value \ - * : uint16_t Int_enbl ; BRDYENB Register Value \ - * Return Value : none \ - *************************************************************/ \ - /* copied from usb0_function_intrn.c */ \ - uint32_t int_sense = 0; \ - uint16_t pipe; \ - uint16_t pipebit; \ - uint16_t ep; \ - \ - for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) { \ - pipebit = g_usb0_function_bit_set[pipe]; \ - \ - if ((status & pipebit) && (intenb & pipebit)) { \ - USB200.BRDYSTS = (uint16_t)~pipebit; \ - USB200.BEMPSTS = (uint16_t)~pipebit; \ - \ - switch (g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) { \ - case USB_FUNCTION_D0FIFO_DMA: \ - if (g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] != USB_FUNCTION_DMA_READY) { \ - /*now, DMA is not supported*/ \ - usb0_function_dma_interrupt_d0fifo(int_sense); \ - } \ - \ - if (RZA_IO_RegRead_16( \ - &g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) { \ - /*now, DMA is not supported*/ \ - usb0_function_read_dma(pipe); \ - usb0_function_disable_brdy_int(pipe); \ - } else { \ - USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; \ - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; \ - } \ - break; \ - \ - case USB_FUNCTION_D1FIFO_DMA: \ - if (g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] != USB_FUNCTION_DMA_READY) { \ - /*now, DMA is not supported*/ \ - usb0_function_dma_interrupt_d1fifo(int_sense); \ - } \ - \ - if (RZA_IO_RegRead_16( \ - &g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) { \ - /*now, DMA is not supported*/ \ - usb0_function_read_dma(pipe); \ - usb0_function_disable_brdy_int(pipe); \ - } else { \ - USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; \ - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; \ - } \ - break; \ - \ - default: \ - ep = (g_usb0_function_pipecfg[pipe] & USB_PIPECFG_EPNUM) >> USB_PIPECFG_EPNUM_SHIFT; \ - ep <<= 1; \ - ep += (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)? \ - (0): (1); \ - EPx_read_status = DEVDRV_USBF_PIPE_WAIT; \ - (instance->*(epCallback[ep - 2])) (); \ - EPx_read_status = DEVDRV_USBF_PIPE_DONE; \ - } \ - } \ - } \ - /* Three dummy reads for clearing interrupt requests */ \ - dumy_sts = USB200.BRDYSTS; \ +extern "C" { + void usb0_function_BRDYInterrupt( + uint16_t status, + uint16_t intenb, + USBHAL *object, + bool (USBHAL::*epCallback[])(void) + ) + { + volatile uint16_t dumy_sts; + + /************************************************************** + * Function Name: usb0_function_brdy_int + * Description : Executes BRDY interrupt(USB_FUNCTION_PIPE1-9). + * : According to the pipe that interrupt is generated in, + * : reads/writes buffer allocated in the pipe. + * : This function is executed in the BRDY + * : interrupt handler. This function + * : clears BRDY interrupt status and BEMP + * : interrupt status. + * Arguments : uint16_t Status ; BRDYSTS Register Value + * : uint16_t Int_enbl ; BRDYENB Register Value + * Return Value : none + *************************************************************/ + /* copied from usb0_function_intrn.c */ + uint32_t int_sense = 0; + uint16_t pipe; + uint16_t pipebit; + uint16_t ep; + + for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) { + pipebit = g_usb0_function_bit_set[pipe]; + + if ((status & pipebit) && (intenb & pipebit)) { + USB200.BRDYSTS = (uint16_t)~pipebit; + USB200.BEMPSTS = (uint16_t)~pipebit; + + switch (g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) { + case USB_FUNCTION_D0FIFO_DMA: + if (g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] != USB_FUNCTION_DMA_READY) { + /*now, DMA is not supported*/ + usb0_function_dma_interrupt_d0fifo(int_sense); + } + + if (RZA_IO_RegRead_16( + &g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) { + /*now, DMA is not supported*/ + usb0_function_read_dma(pipe); + usb0_function_disable_brdy_int(pipe); + } else { + USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + } + break; + + case USB_FUNCTION_D1FIFO_DMA: + if (g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] != USB_FUNCTION_DMA_READY) { + /*now, DMA is not supported*/ + usb0_function_dma_interrupt_d1fifo(int_sense); + } + + if (RZA_IO_RegRead_16( + &g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) { + /*now, DMA is not supported*/ + usb0_function_read_dma(pipe); + usb0_function_disable_brdy_int(pipe); + } else { + USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + } + break; + + default: + ep = (g_usb0_function_pipecfg[pipe] & USB_PIPECFG_EPNUM) >> USB_PIPECFG_EPNUM_SHIFT; + ep <<= 1; + if (RZA_IO_RegRead_16( + &g_usb0_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) { + /* read */ + EPx_read_status = DEVDRV_USBF_PIPE_WAIT; + (object->*(epCallback[ep - 2])) (); + EPx_read_status = DEVDRV_USBF_PIPE_DONE; + } else { + /* write */ + EPx_read_status = DEVDRV_USBF_PIPE_WAIT; + (object->*(epCallback[ep - 2 + 1])) (); + EPx_read_status = DEVDRV_USBF_PIPE_DONE; + usb0_function_write_buffer(pipe); + } + } + } + } + /* Three dummy reads for clearing interrupt requests */ + dumy_sts = USB200.BRDYSTS; } +} /****************************************************************************** @@ -339,16 +383,24 @@ volatile static uint16_t recv_error; * : uint16_t intenb ; NRDYENB Register Value * Return Value : none *****************************************************************************/ -#define usb0_function_NRDYInterruptPIPE0(status, intenb) \ - { \ - volatile uint16_t dumy_sts; \ - \ - USB200.NRDYSTS = \ - (uint16_t)~g_usb0_function_bit_set[USB_FUNCTION_PIPE0]; \ - \ - /* Three dummy reads for clearing interrupt requests */ \ - dumy_sts = USB200.NRDYSTS; \ +extern "C" { + void usb0_function_NRDYInterruptPIPE0( + uint16_t status, + uint16_t intenb, + USBHAL *object, + void (USBHAL::*EP0func)(void) + ) + { + volatile uint16_t dumy_sts; + + USB200.NRDYSTS = + (uint16_t)~g_usb0_function_bit_set[USB_FUNCTION_PIPE0]; + + /* Three dummy reads for clearing interrupt requests */ + dumy_sts = USB200.NRDYSTS; } +} + /****************************************************************************** * Function Name: usb0_function_NRDYInterrupt @@ -357,16 +409,124 @@ volatile static uint16_t recv_error; * : uint16_t intenb ; NRDYENB Register Value * Return Value : none *****************************************************************************/ -#define usb0_function_NRDYInterrupt(status, intenb) \ - { \ - volatile uint16_t dumy_sts; \ - \ - usb0_function_nrdy_int(status, intenb); \ - \ - /* Three dummy reads for clearing interrupt requests */ \ - dumy_sts = USB200.NRDYSTS; \ - } +extern "C" { + void usb0_function_NRDYInterrupt( + uint16_t status, + uint16_t intenb, + USBHAL *object, + bool (USBHAL::*epCallback[])(void) + ) + { + volatile uint16_t dumy_sts; + /************************************************************** + * Function Name: usb0_function_nrdy_int + * Description : Executes NRDY interrupt(USB_FUNCTION_PIPE1-9). + * : Checks NRDY interrupt cause by PID. When the cause if STALL, + * : regards the pipe state as STALL and ends the processing. + * : Then the cause is not STALL, increments the error count to + * : communicate again. When the error count is 3, determines + * : the pipe state as DEVDRV_USBF_PIPE_NORES and ends the processing. + * : This function is executed in the NRDY interrupt handler. + * : This function clears NRDY interrupt status. + * Arguments : uint16_t status ; NRDYSTS Register Value + * : uint16_t int_enb ; NRDYENB Register Value + * Return Value : none + *************************************************************/ + /* copied from usb0_function_intrn.c */ +#if 0 + uint16_t usefifo; +#endif + uint16_t pid; + uint16_t pipe; + uint16_t bitcheck; +#if 0 + uint16_t mbw; + uint32_t size; +#endif + uint16_t ep; + + bitcheck = (uint16_t)(status & intenb); + + USB200.NRDYSTS = (uint16_t)~status; + + + if (RZA_IO_RegRead_16(&USB200.SYSCFG0, USB_SYSCFG_DCFM_SHIFT, USB_SYSCFG_DCFM) == 1) { + /* USB HOST */ + /* not support */ + + } else { + /* USB Function */ + for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) { + if ((bitcheck&g_usb0_function_bit_set[pipe]) != g_usb0_function_bit_set[pipe]) { + continue; + } + + if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_WAIT) { + continue; + } + +#if 0 + usb0_function_set_pid_nak(pipe); + + size = (uint32_t)g_usb0_function_data_count[pipe]; + mbw = usb0_function_get_mbw( + size, (uint32_t)g_usb0_function_data_pointer[pipe]); + + usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); + switch (usefifo) { + + case USB_FUNCTION_D0FIFO_USE: + usb0_function_set_curpipe( + pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw); + USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; + break; + + case USB_FUNCTION_D1FIFO_USE: + usb0_function_set_curpipe( + pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw); + USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; + break; + + default: + usb0_function_set_curpipe( + pipe, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_READ, mbw); + USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; + break; + } + + usb0_function_aclrm(pipe); + + usb0_function_enable_nrdy_int(pipe); + usb0_function_enable_brdy_int(pipe); + + usb0_function_set_pid_buf(pipe); +#endif + + pid = usb0_function_get_pid(pipe); + if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2)) { + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL; + } else { + usb0_function_set_pid_buf(pipe); + } + + ep = (g_usb0_function_pipecfg[pipe] & USB_PIPECFG_EPNUM) >> USB_PIPECFG_EPNUM_SHIFT; + ep <<= 1; + if (RZA_IO_RegRead_16( + &g_usb0_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) { + /* read */ + __nop(); + } else { + /* write */ + __nop(); + } + } + } + + /* Three dummy reads for clearing interrupt requests */ + dumy_sts = USB200.NRDYSTS; + } +} /****************************************************************************** * Function Name: usb0_function_BEMPInterruptPIPE0 @@ -375,22 +535,29 @@ volatile static uint16_t recv_error; * : uint16_t intenb ; BEMPENB Register Value * Return Value : none *****************************************************************************/ -#define usb0_function_BEMPInterruptPIPE0(status, intenb) \ - { \ - volatile uint16_t dumy_sts; \ - \ - USB200.BEMPSTS = \ - (uint16_t)~g_usb0_function_bit_set[USB_FUNCTION_PIPE0]; \ - RZA_IO_RegWrite_16( \ - &USB200.CFIFOSEL, USB_FUNCTION_PIPE0, \ - USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE); \ - \ - /*usb0_function_write_buffer_c(USB_FUNCTION_PIPE0);*/ \ - EP0in(); \ - \ - /* Three dummy reads for clearing interrupt requests */ \ - dumy_sts = USB200.BEMPSTS; \ +extern "C" { + void usb0_function_BEMPInterruptPIPE0( + uint16_t status, + uint16_t intenb, + USBHAL *object, + void (USBHAL::*EP0func)(void) + ) + { + volatile uint16_t dumy_sts; + + USB200.BEMPSTS = + (uint16_t)~g_usb0_function_bit_set[USB_FUNCTION_PIPE0]; + RZA_IO_RegWrite_16( + &USB200.CFIFOSEL, USB_FUNCTION_PIPE0, + USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE); + + /*usb0_function_write_buffer_c(USB_FUNCTION_PIPE0);*/ + (object->*EP0func)(); + + /* Three dummy reads for clearing interrupt requests */ + dumy_sts = USB200.BEMPSTS; } +} /****************************************************************************** @@ -400,16 +567,84 @@ volatile static uint16_t recv_error; * : uint16_t intenb ; BEMPENB Register Value * Return Value : none *****************************************************************************/ -#define usb0_function_BEMPInterrupt(status, intenb) \ - { \ - volatile uint16_t dumy_sts; \ - \ - usb0_function_bemp_int(status, intenb); \ - \ - /* Three dummy reads for clearing interrupt requests */ \ - dumy_sts = USB200.BEMPSTS; \ -} +extern "C" { + void usb0_function_BEMPInterrupt( + uint16_t status, + uint16_t intenb, + USBHAL *object, + bool (USBHAL::*epCallback[])(void) + ) + { + volatile uint16_t dumy_sts; + /************************************************************** + * Function Name: usb0_function_bemp_int + * Description : Executes BEMP interrupt(USB_FUNCTION_PIPE1-9). + * Arguments : uint16_t status ; BEMPSTS Register Value + * : uint16_t intenb ; BEMPENB Register Value + * Return Value : none + *************************************************************/ + /* copied from usb0_function_intrn.c */ + uint16_t pid; + uint16_t pipe; + uint16_t bitcheck; + uint16_t inbuf; + uint16_t ep; + + bitcheck = (uint16_t)(status & intenb); + + USB200.BEMPSTS = (uint16_t)~status; + + for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) { + if ((bitcheck&g_usb0_function_bit_set[pipe]) != g_usb0_function_bit_set[pipe]) { + continue; + } + + pid = usb0_function_get_pid(pipe); + + if ((pid == DEVDRV_USBF_PID_STALL) || + (pid == DEVDRV_USBF_PID_STALL2)) { + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL; + + } else { + inbuf = usb0_function_get_inbuf(pipe); + + if (inbuf == 0) { + usb0_function_disable_bemp_int(pipe); + usb0_function_set_pid_nak(pipe); + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + + switch (g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) { + case USB_FUNCTION_D0FIFO_DMA: + /*now, DMA is not supported*/ + break; + + case USB_FUNCTION_D1FIFO_DMA: + /*now, DMA is not supported*/ + break; + + default: + ep = (g_usb0_function_pipecfg[pipe] & USB_PIPECFG_EPNUM) >> USB_PIPECFG_EPNUM_SHIFT; + ep <<= 1; + if (RZA_IO_RegRead_16( + &g_usb0_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) { + /* read */ + __nop(); + } else { + /* write */ + EPx_read_status = DEVDRV_USBF_PIPE_WAIT; + (object->*(epCallback[ep - 2 + 1])) (); + EPx_read_status = DEVDRV_USBF_PIPE_DONE; + } + } + } + } + } + + /* Three dummy reads for clearing interrupt requests */ + dumy_sts = USB200.BEMPSTS; + } +} /****************************************************************************** * Function Name: EP2PIPE @@ -440,7 +675,7 @@ volatile static uint16_t recv_error; *bufO++ = USB200.USBINDX; \ /*data[6] data[6] <= wIndex*/ \ *bufO++ = USB200.USBLENG; \ -} + } /*************************************************************************/ @@ -452,13 +687,17 @@ volatile static uint16_t recv_error; USBHAL::USBHAL(void) { /* ---- P4_1 : P4_1 (USB0_EN for GR-PEACH) ---- */ - usb0_en = new DigitalOut(P4_1, 1); + //usb0_en = new DigitalOut(P4_1, 1); /* some constants */ int_id = USBI0_IRQn; int_level = ( 2 << 3 ); clock_mode = USBFCLOCK_X1_48MHZ; +#if 1 mode = USB_FUNCTION_HIGH_SPEED; +#else + mode = USB_FUNCTION_FULL_SPEED; +#endif EP0_read_status = DEVDRV_USBF_WRITEEND; EPx_read_status = DEVDRV_USBF_PIPE_DONE; @@ -572,7 +811,7 @@ USBHAL::~USBHAL(void) /* Unregisters interrupt function and priority */ InterruptHandlerRegister( int_id, (uint32_t)NULL ); - usb0_en = NULL; + //usb0_en = NULL; instance = NULL; } @@ -580,7 +819,7 @@ USBHAL::~USBHAL(void) void USBHAL::connect(void) { /* Activates USB0_EN */ - (*usb0_en) = 0; + //(*usb0_en) = 0; } @@ -588,7 +827,7 @@ void USBHAL::connect(void) void USBHAL::disconnect(void) { /* Deactivates USB0_EN */ - (*usb0_en) = 1; + //(*usb0_en) = 1; } @@ -790,15 +1029,19 @@ EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t max_size) EP_STATUS status = EP_COMPLETED; pipe_status = usb0_api_function_check_pipe_status(pipe, &pipe_size); - pipe_size = (max_size < pipe_size)? (max_size): (pipe_size); - if (pipe_status == DEVDRV_USBF_PIPE_IDLE) { - usb0_api_function_set_pid_nak(pipe); - usb0_api_function_clear_pipe_status(pipe); + switch (pipe_status) { + case DEVDRV_USBF_PIPE_IDLE: + case DEVDRV_USBF_PIPE_WAIT: + usb0_api_function_set_pid_nak(pipe); + usb0_api_function_clear_pipe_status(pipe); - usb0_api_function_start_receive_transfer(pipe, pipe_size, recv_buffer); - } else { - status = EP_PENDING; + usb0_api_function_start_receive_transfer(pipe, max_size, recv_buffer); + break; + + default: + status = EP_PENDING; + break; } return status; @@ -819,14 +1062,18 @@ EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *buffer, uint32_t } pipe_status = usb0_api_function_check_pipe_status(pipe, bytes_read); - if (pipe_status == DEVDRV_USBF_PIPE_IDLE) { - return EP_COMPLETED; - } - if (pipe_status == DEVDRV_USBF_PIPE_DONE) { - return EP_COMPLETED; - } - if (pipe_status != DEVDRV_USBF_PIPE_WAIT) { - return status; + switch (pipe_status) { + case DEVDRV_USBF_PIPE_IDLE: + return EP_COMPLETED; + + case DEVDRV_USBF_PIPE_DONE: + return EP_COMPLETED; + + case DEVDRV_USBF_PIPE_WAIT: + break; + + default: + return status; } /* sets the output buffer and size */ @@ -835,10 +1082,30 @@ EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *buffer, uint32_t /* receives data from pipe */ err = usb0_function_read_buffer(pipe); recv_error = err; + switch (err) { + case USB_FUNCTION_READEND: + case USB_FUNCTION_READSHRT: + case USB_FUNCTION_READOVER: + *bytes_read = g_usb0_function_PipeDataSize[pipe]; + break; + + case USB_FUNCTION_READING: + case DEVDRV_USBF_FIFOERROR: + break; + } pipe_status = usb0_api_function_check_pipe_status(pipe, bytes_read); - if (pipe_status == DEVDRV_USBF_PIPE_DONE) { - status = EP_COMPLETED; + switch (pipe_status) { + case DEVDRV_USBF_PIPE_DONE: + status = EP_COMPLETED; + break; + + case DEVDRV_USBF_PIPE_IDLE: + case DEVDRV_USBF_PIPE_NORES: + case DEVDRV_USBF_PIPE_STALL: + case DEVDRV_USBF_FIFOERROR: + default: + break; } return status; @@ -1112,19 +1379,19 @@ void USBHAL::usbisr(void) (int_enb0 & USB_FUNCTION_BITBEMP) && ((int_sts3 & int_enb4) & g_usb0_function_bit_set[USB_FUNCTION_PIPE0])) { /* ==== BEMP PIPE0 ==== */ - usb0_function_BEMPInterruptPIPE0(int_sts3, int_enb4); + usb0_function_BEMPInterruptPIPE0(int_sts3, int_enb4, this, &USBHAL::EP0in); } else if ( (int_sts0 & USB_FUNCTION_BITBRDY) && (int_enb0 & USB_FUNCTION_BITBRDY) && ((int_sts1 & int_enb2) & g_usb0_function_bit_set[USB_FUNCTION_PIPE0])) { /* ==== BRDY PIPE0 ==== */ - usb0_function_BRDYInterruptPIPE0(int_sts1, int_enb2); + usb0_function_BRDYInterruptPIPE0(int_sts1, int_enb2, this, &USBHAL::EP0out); } else if ( (int_sts0 & USB_FUNCTION_BITNRDY) && (int_enb0 & USB_FUNCTION_BITNRDY) && ((int_sts2 & int_enb3) & g_usb0_function_bit_set[USB_FUNCTION_PIPE0])) { /* ==== NRDY PIPE0 ==== */ - usb0_function_NRDYInterruptPIPE0(int_sts2, int_enb3); + usb0_function_NRDYInterruptPIPE0(int_sts2, int_enb3, this, NULL); } else if ( (int_sts0 & USB_FUNCTION_BITCTRT) && (int_enb0 & USB_FUNCTION_BITCTRE)) { int_sts0 = USB200.INTSTS0; @@ -1198,19 +1465,19 @@ void USBHAL::usbisr(void) (int_enb0 & USB_FUNCTION_BITBEMP) && (int_sts3 & int_enb4) ) { /* ==== BEMP PIPEx ==== */ - usb0_function_BEMPInterrupt(int_sts3, int_enb4); + usb0_function_BEMPInterrupt(int_sts3, int_enb4, this, epCallback); } else if ( (int_sts0 & USB_FUNCTION_BITBRDY) && (int_enb0 & USB_FUNCTION_BITBRDY) && (int_sts1 & int_enb2) ) { /* ==== BRDY PIPEx ==== */ - usb0_function_BRDYInterrupt(int_sts1, int_enb2); + usb0_function_BRDYInterrupt(int_sts1, int_enb2, this, epCallback); } else if ( (int_sts0 & USB_FUNCTION_BITNRDY) && (int_enb0 & USB_FUNCTION_BITNRDY) && (int_sts2 & int_enb3)) { /* ==== NRDY PIPEx ==== */ - usb0_function_NRDYInterrupt(int_sts2, int_enb3); + usb0_function_NRDYInterrupt(int_sts2, int_enb3, this, epCallback); } else { /* Do Nothing */ } diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_host_api.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_host_api.h new file mode 100644 index 0000000000..eb08292c99 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_host_api.h @@ -0,0 +1,332 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : devdrv_usb_host_api.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB_HOST_API_H +#define USB_HOST_API_H + +#include "r_typedefs.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define USB_HOST_PORTNUM (2) + +#define USB_HOST_ELT_INTERRUPT_LEVEL (9) + +#define USBHCLOCK_X1_48MHZ (0x0000u) /* USB_X1_48MHz */ +#define USBHCLOCK_EXTAL_12MHZ (0x0004u) /* EXTAL_12MHz */ + +#define USB_HOST_MAX_DEVICE (10) + +#define USB_HOST_ON (1) +#define USB_HOST_OFF (0) +#define USB_HOST_YES (1) +#define USB_HOST_NO (0) + +#define USB_HOST_NON_SPEED (0) +#define USB_HOST_LOW_SPEED (1) +#define USB_HOST_FULL_SPEED (2) +#define USB_HOST_HIGH_SPEED (3) + +/* DEVDRV_SUCCESS(0) & DEVDRV_ERROR(-1) is dev_drv.h */ +#define DEVDRV_USBH_STALL (-2) +#define DEVDRV_USBH_TIMEOUT (-3) +#define DEVDRV_USBH_NAK_TIMEOUT (-4) +#define DEVDRV_USBH_DETACH_ERR (-5) +#define DEVDRV_USBH_SETUP_ERR (-6) +#define DEVDRV_USBH_CTRL_COM_ERR (-7) +#define DEVDRV_USBH_COM_ERR (-8) +#define DEVDRV_USBH_DEV_ADDR_ERR (-9) + +#define USB_HOST_ATTACH (1) +#define USB_HOST_DETACH (0) + +#define USB_HOST_MAX_PIPE_NO (9u) +#define USB_HOST_PIPE0 (0) +#define USB_HOST_PIPE1 (1) +#define USB_HOST_PIPE2 (2) +#define USB_HOST_PIPE3 (3) +#define USB_HOST_PIPE4 (4) +#define USB_HOST_PIPE5 (5) +#define USB_HOST_PIPE6 (6) +#define USB_HOST_PIPE7 (7) +#define USB_HOST_PIPE8 (8) +#define USB_HOST_PIPE9 (9) + +#define USB_HOST_ISO (0xc000u) +#define USB_HOST_INTERRUPT (0x8000u) +#define USB_HOST_BULK (0x4000u) + +#define USB_HOST_PIPE_IDLE (0x00) +#define USB_HOST_PIPE_WAIT (0x01) +#define USB_HOST_PIPE_DONE (0x02) +#define USB_HOST_PIPE_NORES (0x03) +#define USB_HOST_PIPE_STALL (0x04) +#define USB_HOST_PIPE_ERROR (0x05) + +#define USB_HOST_NONE (0x0000u) +#define USB_HOST_BFREFIELD (0x0400u) +#define USB_HOST_BFREON (0x0400u) +#define USB_HOST_BFREOFF (0x0000u) +#define USB_HOST_DBLBFIELD (0x0200u) +#define USB_HOST_DBLBON (0x0200u) +#define USB_HOST_DBLBOFF (0x0000u) +#define USB_HOST_CNTMDFIELD (0x0100u) +#define USB_HOST_CNTMDON (0x0100u) +#define USB_HOST_CNTMDOFF (0x0000u) +#define USB_HOST_SHTNAKON (0x0080u) +#define USB_HOST_SHTNAKOFF (0x0000u) +#define USB_HOST_DIRFIELD (0x0010u) +#define USB_HOST_DIR_H_OUT (0x0010u) +#define USB_HOST_DIR_H_IN (0x0000u) +#define USB_HOST_EPNUMFIELD (0x000fu) + +#define USB_HOST_CUSE (0) +#define USB_HOST_D0USE (1) +#define USB_HOST_D0DMA (2) +#define USB_HOST_D1USE (3) +#define USB_HOST_D1DMA (4) + +#define USB_HOST_CFIFO_USE (0x0000) +#define USB_HOST_D0FIFO_USE (0x1000) +#define USB_HOST_D1FIFO_USE (0x2000) +#define USB_HOST_D0FIFO_DMA (0x5000) +#define USB_HOST_D1FIFO_DMA (0x6000) + +#define USB_HOST_BUF2FIFO (0) +#define USB_HOST_FIFO2BUF (1) + +#define USB_HOST_DRV_DETACHED (0x0000) +#define USB_HOST_DRV_ATTACHED (0x0001) +#define USB_HOST_DRV_GET_DEVICE_DESC_64 (0x0002) +#define USB_HOST_DRV_POWERED (0x0003) +#define USB_HOST_DRV_DEFAULT (0x0004) +#define USB_HOST_DRV_SET_ADDRESS (0x0005) +#define USB_HOST_DRV_ADDRESSED (0x0006) +#define USB_HOST_DRV_GET_DEVICE_DESC_18 (0x0007) +#define USB_HOST_DRV_GET_CONGIG_DESC_9 (0x0008) +#define USB_HOST_DRV_GET_CONGIG_DESC (0x0009) +#define USB_HOST_DRV_SET_CONFIG (0x000a) +#define USB_HOST_DRV_CONFIGURED (0x000b) +#define USB_HOST_DRV_SUSPEND (0x1000) +#define USB_HOST_DRV_NORES (0x0100) +#define USB_HOST_DRV_STALL (0x0200) + +#define USB_HOST_TESTMODE_FORCE (0x000du) +#define USB_HOST_TESTMODE_TESTPACKET (0x000cu) +#define USB_HOST_TESTMODE_SE0_NAK (0x000bu) +#define USB_HOST_TESTMODE_K (0x000au) +#define USB_HOST_TESTMODE_J (0x0009u) +#define USB_HOST_TESTMODE_NORMAL (0x0000u) + +#define USB_HOST_DT_DEVICE (0x01) +#define USB_HOST_DT_CONFIGURATION (0x02) +#define USB_HOST_DT_STRING (0x03) +#define USB_HOST_DT_INTERFACE (0x04) +#define USB_HOST_DT_ENDPOINT (0x05) +#define USB_HOST_DT_DEVICE_QUALIFIER (0x06) +#define USB_HOST_DT_OTHER_SPEED_CONFIGURATION (0x07) +#define USB_HOST_DT_INTERFACE_POWER (0x08) + +#define USB_HOST_IF_CLS_NOT (0x00) +#define USB_HOST_IF_CLS_AUDIO (0x01) +#define USB_HOST_IF_CLS_CDC_CTRL (0x02) +#define USB_HOST_IF_CLS_HID (0x03) +#define USB_HOST_IF_CLS_PHYSICAL (0x05) +#define USB_HOST_IF_CLS_IMAGE (0x06) +#define USB_HOST_IF_CLS_PRINTER (0x07) +#define USB_HOST_IF_CLS_MASS (0x08) +#define USB_HOST_IF_CLS_HUB (0x09) +#define USB_HOST_IF_CLS_CDC_DATA (0x0a) +#define USB_HOST_IF_CLS_CRAD (0x0b) +#define USB_HOST_IF_CLS_CONTENT (0x0d) +#define USB_HOST_IF_CLS_VIDEO (0x0e) +#define USB_HOST_IF_CLS_DIAG (0xdc) +#define USB_HOST_IF_CLS_WIRELESS (0xe0) +#define USB_HOST_IF_CLS_APL (0xfe) +#define USB_HOST_IF_CLS_VENDOR (0xff) +#define USB_HOST_IF_CLS_HELE (0xaa) + +#define USB_HOST_EP_DIR_MASK (0x80) +#define USB_HOST_EP_OUT (0x00) +#define USB_HOST_EP_IN (0x80) +#define USB_HOST_EP_TYPE (0x03) +#define USB_HOST_EP_CNTRL (0x00) +#define USB_HOST_EP_ISO (0x01) +#define USB_HOST_EP_BULK (0x02) +#define USB_HOST_EP_INT (0x03) +#define USB_HOST_EP_NUM_MASK (0x0f) + +#define USB_HOST_PIPE_IN (0) +#define USB_HOST_PIPE_OUT (1) + +#define USB_END_POINT_ERROR (0xffff) + +#define USB_HOST_REQ_GET_STATUS (0x0000) +#define USB_HOST_REQ_CLEAR_FEATURE (0x0100) +#define USB_HOST_REQ_RESERVED2 (0x0200) +#define USB_HOST_REQ_SET_FEATURE (0x0300) +#define USB_HOST_REQ_RESERVED4 (0x0400) +#define USB_HOST_REQ_SET_ADDRESS (0x0500) +#define USB_HOST_REQ_GET_DESCRIPTOR (0x0600) +#define USB_HOST_REQ_SET_DESCRIPTOR (0x0700) +#define USB_HOST_REQ_GET_CONFIGURATION (0x0800) +#define USB_HOST_REQ_SET_CONFIGURATION (0x0900) +#define USB_HOST_REQ_GET_INTERFACE (0x0a00) +#define USB_HOST_REQ_SET_INTERFACE (0x0b00) +#define USB_HOST_REQ_SYNCH_FRAME (0x0c00) + +#define USB_HOST_REQTYPE_HOST_TO_DEVICE (0x0000) +#define USB_HOST_REQTYPE_DEVICE_TO_HOST (0x0080) +#define USB_HOST_REQTYPE_STANDARD (0x0020) +#define USB_HOST_REQTYPE_CLASS (0x0040) +#define USB_HOST_REQTYPE_VENDOR (0x0060) +#define USB_HOST_REQTYPE_DEVICE (0x0000) +#define USB_HOST_REQTYPE_INTERFACE (0x0001) +#define USB_HOST_REQTYPE_ENDPOINT (0x0002) +#define USB_HOST_REQTYPE_OTHER (0x0003) + +#define USB_HOST_DESCTYPE_DEVICE (0x0100) +#define USB_HOST_DESCTYPE_CONFIGURATION (0x0200) +#define USB_HOST_DESCTYPE_STRING (0x0300) +#define USB_HOST_DESCTYPE_INTERFACE (0x0400) +#define USB_HOST_DESCTYPE_ENDPOINT (0x0500) +#define USB_HOST_DESCTYPE_DEVICE_QUALIFIER (0x0600) +#define USB_HOST_DESCTYPE_OTHER_SPEED_CONFIGURATION (0x0700) +#define USB_HOST_DESCTYPE_INTERFACE_POWER (0x0800) + + +/******************************************************************************* +Variable Externs +*******************************************************************************/ +typedef struct +{ + uint16_t pipe_number; + uint16_t pipe_cfg; + uint16_t pipe_buf; + uint16_t pipe_max_pktsize; + uint16_t pipe_cycle; + uint16_t fifo_port; +} USB_HOST_CFG_PIPETBL_t; + +typedef struct +{ + uint32_t fifo; + uint32_t buffer; + uint32_t bytes; + uint32_t dir; + uint32_t size; +} USB_HOST_DMA_t; + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ +uint16_t R_USB_api_host_init(uint16_t root, uint8_t int_level, uint16_t mode, uint16_t clockmode); +int32_t R_USB_api_host_enumeration(uint16_t root, uint16_t devadr); +int32_t R_USB_api_host_detach(uint16_t root); +int32_t R_USB_api_host_data_in(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf); +int32_t R_USB_api_host_data_in2(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf, uint32_t *bytes); +int32_t R_USB_api_host_data_out(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf); +int32_t R_USB_api_host_control_transfer(uint16_t root, uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf); +int32_t R_USB_api_host_set_endpoint(uint16_t root, uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor); +int32_t R_USB_api_host_clear_endpoint(uint16_t root, USB_HOST_CFG_PIPETBL_t *user_table); +int32_t R_USB_api_host_clear_endpoint_pipe(uint16_t root, uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table); +uint16_t R_USB_api_host_SetEndpointTable(uint16_t root, uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t* Table); + +int32_t R_USB_api_host_GetDeviceDescriptor(uint16_t root, uint16_t devadr, uint16_t size, uint8_t *buf); +int32_t R_USB_api_host_GetConfigDescriptor(uint16_t root, uint16_t devadr, uint16_t size, uint8_t *buf); +int32_t R_USB_api_host_SetConfig(uint16_t root, uint16_t devadr, uint16_t confignum); +int32_t R_USB_api_host_SetInterface(uint16_t root, uint16_t devadr, uint16_t interface_alt, uint16_t interface_index); +int32_t R_USB_api_host_ClearStall(uint16_t root, uint16_t devadr, uint16_t ep_dir); +uint16_t R_USB_api_host_GetUsbDeviceState(uint16_t root); + +void R_USB_api_host_elt_clocksel(uint16_t clockmode); +void R_USB_api_host_elt_4_4(uint16_t root); +void R_USB_api_host_elt_4_5(uint16_t root); +void R_USB_api_host_elt_4_6(uint16_t root); +void R_USB_api_host_elt_4_7(uint16_t root); +void R_USB_api_host_elt_4_8(uint16_t root); +void R_USB_api_host_elt_4_9(uint16_t root); +void R_USB_api_host_elt_get_desc(uint16_t root); + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host_api.h" +#if(1) /* ohci_wrapp */ +#else +#include "usb1_host_api.h" +#endif + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ +#ifdef USB0_HOST_API_H +uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid(void); +uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid(void); +void Userdef_USB_usb0_host_attach(void); +void Userdef_USB_usb0_host_detach(void); +void Userdef_USB_usb0_host_delay_1ms(void); +void Userdef_USB_usb0_host_delay_xms(uint32_t msec); +void Userdef_USB_usb0_host_delay_10us(uint32_t usec); +void Userdef_USB_usb0_host_delay_500ns(void); +void Userdef_USB_usb0_host_start_dma(USB_HOST_DMA_t * dma, uint16_t dfacc); +uint32_t Userdef_USB_usb0_host_stop_dma0(void); +uint32_t Userdef_USB_usb0_host_stop_dma1(void); +void Userdef_USB_usb0_host_notice(const char * format); +void Userdef_USB_usb0_host_user_rdy(const char * format, uint16_t data); +#endif + +#ifdef USB1_HOST_API_H +uint16_t Userdef_USB_usb1_host_d0fifo_dmaintid(void); +uint16_t Userdef_USB_usb1_host_d1fifo_dmaintid(void); +void Userdef_USB_usb1_host_attach(void); +void Userdef_USB_usb1_host_detach(void); +void Userdef_USB_usb1_host_delay_1ms(void); +void Userdef_USB_usb1_host_delay_xms(uint32_t msec); +void Userdef_USB_usb1_host_delay_10us(uint32_t usec); +void Userdef_USB_usb1_host_delay_500ns(void); +void Userdef_USB_usb1_host_start_dma(USB_HOST_DMA_t * dma, uint16_t dfacc); +uint32_t Userdef_USB_usb1_host_stop_dma0(void); +uint32_t Userdef_USB_usb1_host_stop_dma1(void); +void Userdef_USB_usb1_host_notice(const char * format); +void Userdef_USB_usb1_host_user_rdy(const char * format, uint16_t data); +#endif + +#endif /* USB_HOST_API_H */ + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host.h new file mode 100644 index 0000000000..70e5c21151 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host.h @@ -0,0 +1,156 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB0_HOST_H +#define USB0_HOST_H + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "devdrv_usb_host_api.h" +#include "usb_host.h" + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ +extern const uint16_t g_usb0_host_bit_set[]; +extern uint32_t g_usb0_host_data_count[USB_HOST_MAX_PIPE_NO + 1]; +extern uint8_t *g_usb0_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1]; + +extern uint16_t g_usb0_host_PipeIgnore[]; +extern uint16_t g_usb0_host_PipeTbl[]; +extern uint16_t g_usb0_host_pipe_status[]; +extern uint32_t g_usb0_host_PipeDataSize[]; + +extern USB_HOST_DMA_t g_usb0_host_DmaInfo[]; +extern uint16_t g_usb0_host_DmaPipe[]; +extern uint16_t g_usb0_host_DmaBval[]; +extern uint16_t g_usb0_host_DmaStatus[]; + +extern uint16_t g_usb0_host_driver_state; +extern uint16_t g_usb0_host_ConfigNum; +extern uint16_t g_usb0_host_CmdStage; +extern uint16_t g_usb0_host_bchg_flag; +extern uint16_t g_usb0_host_detach_flag; +extern uint16_t g_usb0_host_attach_flag; + +extern uint16_t g_usb0_host_UsbAddress; +extern uint16_t g_usb0_host_setUsbAddress; +extern uint16_t g_usb0_host_default_max_packet[USB_HOST_MAX_DEVICE + 1]; +extern uint16_t g_usb0_host_UsbDeviceSpeed; +extern uint16_t g_usb0_host_SupportUsbDeviceSpeed; + +extern uint16_t g_usb0_host_SavReq; +extern uint16_t g_usb0_host_SavVal; +extern uint16_t g_usb0_host_SavIndx; +extern uint16_t g_usb0_host_SavLen; + +extern uint16_t g_usb0_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1]; +extern uint16_t g_usb0_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1]; +extern uint16_t g_usb0_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1]; +extern uint16_t g_usb0_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1]; + +/******************************************************************************* +Functions Prototypes +*******************************************************************************/ +/* ==== common ==== */ +void usb0_host_dma_stop_d0(uint16_t pipe, uint32_t remain); +void usb0_host_dma_stop_d1(uint16_t pipe, uint32_t remain); +uint16_t usb0_host_is_hispeed(void); +uint16_t usb0_host_is_hispeed_enable(void); +uint16_t usb0_host_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data); +uint16_t usb0_host_write_buffer(uint16_t pipe); +uint16_t usb0_host_write_buffer_c(uint16_t pipe); +uint16_t usb0_host_write_buffer_d0(uint16_t pipe); +uint16_t usb0_host_write_buffer_d1(uint16_t pipe); +void usb0_host_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data); +uint16_t usb0_host_read_buffer(uint16_t pipe); +uint16_t usb0_host_read_buffer_c(uint16_t pipe); +uint16_t usb0_host_read_buffer_d0(uint16_t pipe); +uint16_t usb0_host_read_buffer_d1(uint16_t pipe); +uint16_t usb0_host_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); +void usb0_host_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); +void usb0_host_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc); +uint16_t usb0_host_get_mbw(uint32_t trncount, uint32_t dtptr); +uint16_t usb0_host_read_dma(uint16_t pipe); +void usb0_host_stop_transfer(uint16_t pipe); +void usb0_host_brdy_int(uint16_t status, uint16_t int_enb); +void usb0_host_nrdy_int(uint16_t status, uint16_t int_enb); +void usb0_host_bemp_int(uint16_t status, uint16_t int_enb); +void usb0_host_setting_interrupt(uint8_t level); +void usb0_host_reset_module(uint16_t clockmode); +uint16_t usb0_host_get_buf_size(uint16_t pipe); +uint16_t usb0_host_get_mxps(uint16_t pipe); +void usb0_host_enable_brdy_int(uint16_t pipe); +void usb0_host_disable_brdy_int(uint16_t pipe); +void usb0_host_clear_brdy_sts(uint16_t pipe); +void usb0_host_enable_bemp_int(uint16_t pipe); +void usb0_host_disable_bemp_int(uint16_t pipe); +void usb0_host_clear_bemp_sts(uint16_t pipe); +void usb0_host_enable_nrdy_int(uint16_t pipe); +void usb0_host_disable_nrdy_int(uint16_t pipe); +void usb0_host_clear_nrdy_sts(uint16_t pipe); +void usb0_host_set_pid_buf(uint16_t pipe); +void usb0_host_set_pid_nak(uint16_t pipe); +void usb0_host_set_pid_stall(uint16_t pipe); +void usb0_host_clear_pid_stall(uint16_t pipe); +uint16_t usb0_host_get_pid(uint16_t pipe); +void usb0_host_set_sqclr(uint16_t pipe); +void usb0_host_set_sqset(uint16_t pipe); +void usb0_host_set_csclr(uint16_t pipe); +void usb0_host_aclrm(uint16_t pipe); +void usb0_host_set_aclrm(uint16_t pipe); +void usb0_host_clr_aclrm(uint16_t pipe); +uint16_t usb0_host_get_sqmon(uint16_t pipe); +uint16_t usb0_host_get_inbuf(uint16_t pipe); + +/* ==== host ==== */ +void usb0_host_init_pipe_status(void); +int32_t usb0_host_CtrlTransStart(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf); +void usb0_host_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len); +void usb0_host_CtrlReadStart(uint32_t Bsize, uint8_t *Table); +uint16_t usb0_host_CtrlWriteStart(uint32_t Bsize, uint8_t *Table); +void usb0_host_StatusStage(void); +void usb0_host_get_devadd(uint16_t addr, uint16_t *devadd); +void usb0_host_set_devadd(uint16_t addr, uint16_t *devadd); +void usb0_host_InitModule(void); +uint16_t usb0_host_CheckAttach(void); +void usb0_host_UsbDetach(void); +void usb0_host_UsbDetach2(void); +void usb0_host_UsbAttach(void); +uint16_t usb0_host_UsbBusReset(void); +int32_t usb0_host_UsbResume(void); +int32_t usb0_host_UsbSuspend(void); +void usb0_host_Enable_DetachINT(void); +void usb0_host_Disable_DetachINT(void); +void usb0_host_UsbStateManager(void); + + +#endif /* USB0_HOST_H */ + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_api.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_api.h new file mode 100644 index 0000000000..dbdd64d6d9 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_api.h @@ -0,0 +1,112 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_api.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB0_HOST_API_H +#define USB0_HOST_API_H + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Variable Externs +*******************************************************************************/ + + +/******************************************************************************* +Functions Prototypes +*******************************************************************************/ +void usb0_host_interrupt(uint32_t int_sense); +void usb0_host_dma_interrupt_d0fifo(uint32_t int_sense); +void usb0_host_dma_interrupt_d1fifo(uint32_t int_sense); + +uint16_t usb0_api_host_init(uint8_t int_level, uint16_t mode, uint16_t clockmode); +int32_t usb0_api_host_enumeration(uint16_t devadr); +int32_t usb0_api_host_detach(void); +int32_t usb0_api_host_data_in(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf); +int32_t usb0_api_host_data_out(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf); +int32_t usb0_api_host_control_transfer(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf); +int32_t usb0_api_host_set_endpoint(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor); +int32_t usb0_api_host_clear_endpoint(USB_HOST_CFG_PIPETBL_t *user_table); +int32_t usb0_api_host_clear_endpoint_pipe(uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table); +uint16_t usb0_api_host_SetEndpointTable(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t* Table); +int32_t usb0_api_host_data_count(uint16_t pipe, uint32_t *data_count); + +int32_t usb0_api_host_GetDeviceDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf); +int32_t usb0_api_host_GetConfigDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf); +int32_t usb0_api_host_SetConfig(uint16_t devadr, uint16_t confignum); +int32_t usb0_api_host_SetInterface(uint16_t devadr, uint16_t interface_alt, uint16_t interface_index); +int32_t usb0_api_host_ClearStall(uint16_t devadr, uint16_t ep_dir); +uint16_t usb0_api_host_GetUsbDeviceState(void); + +void usb0_api_host_elt_4_4(void); +void usb0_api_host_elt_4_5(void); +void usb0_api_host_elt_4_6(void); +void usb0_api_host_elt_4_7(void); +void usb0_api_host_elt_4_8(void); +void usb0_api_host_elt_4_9(void); +void usb0_api_host_elt_get_desc(void); + +void usb0_host_EL_ModeInit(void); +void usb0_host_EL_SetUACT(void); +void usb0_host_EL_ClearUACT(void); +void usb0_host_EL_SetTESTMODE(uint16_t mode); +void usb0_host_EL_ClearNRDYSTS(uint16_t pipe); +uint16_t usb0_host_EL_GetINTSTS1(void); +void usb0_host_EL_UsbBusReset(void); +void usb0_host_EL_UsbAttach(void); +void usb0_host_EL_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len); +void usb0_host_EL_StatusStage(void); +void usb0_host_EL_CtrlReadStart(uint32_t Bsize, uint8_t *Table); +int32_t usb0_host_EL_UsbSuspend(void); +int32_t usb0_host_EL_UsbResume(void); + +#if 0 /* prototype in devdrv_usb_host_api.h */ +uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid(void); +uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid(void); +void Userdef_USB_usb0_host_attach(void); +void Userdef_USB_usb0_host_detach(void); +void Userdef_USB_usb0_host_delay_1ms(void); +void Userdef_USB_usb0_host_delay_xms(uint32_t msec); +void Userdef_USB_usb0_host_delay_10us(uint32_t usec); +void Userdef_USB_usb0_host_delay_500ns(void); +void Userdef_USB_usb0_host_start_dma(USB_HOST_DMA_t *dma, uint16_t dfacc); +uint32_t Userdef_USB_usb0_host_stop_dma0(void); +uint32_t Userdef_USB_usb0_host_stop_dma1(void); +#endif + +#endif /* USB0_HOST_API_H */ + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_dmacdrv.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_dmacdrv.h new file mode 100644 index 0000000000..3e5e40c3bb --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_dmacdrv.h @@ -0,0 +1,139 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_dmacdrv.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB0_HOST_DMACDRV_H +#define USB0_HOST_DMACDRV_H + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ +typedef struct dmac_transinfo +{ + uint32_t src_addr; /* Transfer source address */ + uint32_t dst_addr; /* Transfer destination address */ + uint32_t count; /* Transfer byte count */ + uint32_t src_size; /* Transfer source data size */ + uint32_t dst_size; /* Transfer destination data size */ + uint32_t saddr_dir; /* Transfer source address direction */ + uint32_t daddr_dir; /* Transfer destination address direction */ +} dmac_transinfo_t; + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +/* ==== Transfer specification of the sample program ==== */ +#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */ +#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */ + +/* ==== DMA modes ==== */ +#define DMAC_MODE_REGISTER (0) /* Register mode */ +#define DMAC_MODE_LINK (1) /* Link mode */ + +/* ==== Transfer requests ==== */ +#define DMAC_REQ_MODE_EXT (0) /* External request */ +#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */ +#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */ + +/* ==== DMAC transfer sizes ==== */ +#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */ +#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */ +#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */ +#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */ +#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */ +#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */ +#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */ +#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */ + +/* ==== Address increment for transferring ==== */ +#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */ +#define DMAC_TRANS_ADR_INC (0) /* Increment */ + +/* ==== Method for detecting DMA request ==== */ +#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */ +#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */ +#define DMAC_REQ_DET_LOW (2) /* Low level detection */ +#define DMAC_REQ_DET_HIGH (3) /* High level detection */ + +/* ==== Request Direction ==== */ +#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */ +#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */ + +/* ==== Descriptors ==== */ +#define DMAC_DESC_HEADER (0) /* Header */ +#define DMAC_DESC_SRC_ADDR (1) /* Source Address */ +#define DMAC_DESC_DST_ADDR (2) /* Destination Address */ +#define DMAC_DESC_COUNT (3) /* Transaction Byte */ +#define DMAC_DESC_CHCFG (4) /* Channel Confg */ +#define DMAC_DESC_CHITVL (5) /* Channel Interval */ +#define DMAC_DESC_CHEXT (6) /* Channel Extension */ +#define DMAC_DESC_LINK_ADDR (7) /* Link Address */ + +/* ==== On-chip peripheral module requests ===== */ +typedef enum dmac_request_factor +{ + DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */ + DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */ + DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */ + DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */ + DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */ + DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */ + DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */ + DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */ +} dmac_request_factor_t; + + +/******************************************************************************* +Variable Externs +*******************************************************************************/ + + +/******************************************************************************* +Functions Prototypes +*******************************************************************************/ +void usb0_host_DMAC1_PeriReqInit(const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction); +int32_t usb0_host_DMAC1_Open(uint32_t req); +void usb0_host_DMAC1_Close(uint32_t * remain); +void usb0_host_DMAC1_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count); + +void usb0_host_DMAC2_PeriReqInit(const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction); +int32_t usb0_host_DMAC2_Open(uint32_t req); +void usb0_host_DMAC2_Close(uint32_t * remain); +void usb0_host_DMAC2_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count); + +#endif /* USB0_HOST_DMACDRV_H */ + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host.h new file mode 100644 index 0000000000..287e0860e1 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host.h @@ -0,0 +1,201 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb_host.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB_HOST_H +#define USB_HOST_H + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "r_typedefs.h" +#include "iodefine.h" +#include "rza_io_regrw.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define USB_HOST_DEVICE_0 (0u) +#define USB_HOST_DEVICE_1 (1u) +#define USB_HOST_DEVICE_2 (2u) +#define USB_HOST_DEVICE_3 (3u) +#define USB_HOST_DEVICE_4 (4u) +#define USB_HOST_DEVICE_5 (5u) +#define USB_HOST_DEVICE_6 (6u) +#define USB_HOST_DEVICE_7 (7u) +#define USB_HOST_DEVICE_8 (8u) +#define USB_HOST_DEVICE_9 (9u) +#define USB_HOST_DEVICE_10 (10u) + +#define USB_HOST_ENDPOINT_DESC (0x05) + +#define USB_HOST_BITUPLLE (0x0002u) +#define USB_HOST_BITUCKSEL (0x0004u) +#define USB_HOST_BITBWAIT (0x003fu) + +#define USB_HOST_BUSWAIT_02 (0x0000u) +#define USB_HOST_BUSWAIT_03 (0x0001u) +#define USB_HOST_BUSWAIT_04 (0x0002u) +#define USB_HOST_BUSWAIT_05 (0x0003u) +#define USB_HOST_BUSWAIT_06 (0x0004u) +#define USB_HOST_BUSWAIT_07 (0x0005u) +#define USB_HOST_BUSWAIT_08 (0x0006u) +#define USB_HOST_BUSWAIT_09 (0x0007u) +#define USB_HOST_BUSWAIT_10 (0x0008u) +#define USB_HOST_BUSWAIT_11 (0x0009u) +#define USB_HOST_BUSWAIT_12 (0x000au) +#define USB_HOST_BUSWAIT_13 (0x000bu) +#define USB_HOST_BUSWAIT_14 (0x000cu) +#define USB_HOST_BUSWAIT_15 (0x000du) +#define USB_HOST_BUSWAIT_16 (0x000eu) +#define USB_HOST_BUSWAIT_17 (0x000fu) + +#define USB_HOST_FS_JSTS (0x0001u) +#define USB_HOST_LS_JSTS (0x0002u) + +#define USB_HOST_BITRST (0x0040u) +#define USB_HOST_BITRESUME (0x0020u) +#define USB_HOST_BITUACT (0x0010u) +#define USB_HOST_HSPROC (0x0004u) +#define USB_HOST_HSMODE (0x0003u) +#define USB_HOST_FSMODE (0x0002u) +#define USB_HOST_LSMODE (0x0001u) +#define USB_HOST_UNDECID (0x0000u) + +#define USB_HOST_BITRCNT (0x8000u) +#define USB_HOST_BITDREQE (0x1000u) +#define USB_HOST_BITMBW (0x0c00u) +#define USB_HOST_BITMBW_8 (0x0000u) +#define USB_HOST_BITMBW_16 (0x0400u) +#define USB_HOST_BITMBW_32 (0x0800u) +#define USB_HOST_BITBYTE_LITTLE (0x0000u) +#define USB_HOST_BITBYTE_BIG (0x0100u) +#define USB_HOST_BITISEL (0x0020u) +#define USB_HOST_BITCURPIPE (0x000fu) + +#define USB_HOST_CFIFO_READ (0x0000u) +#define USB_HOST_CFIFO_WRITE (0x0020u) + +#define USB_HOST_BITBVAL (0x8000u) +#define USB_HOST_BITBCLR (0x4000u) +#define USB_HOST_BITFRDY (0x2000u) +#define USB_HOST_BITDTLN (0x0fffu) + +#define USB_HOST_BITBEMPE (0x0400u) +#define USB_HOST_BITNRDYE (0x0200u) +#define USB_HOST_BITBRDYE (0x0100u) +#define USB_HOST_BITBEMP (0x0400u) +#define USB_HOST_BITNRDY (0x0200u) +#define USB_HOST_BITBRDY (0x0100u) + +#define USB_HOST_BITBCHGE (0x4000u) +#define USB_HOST_BITDTCHE (0x1000u) +#define USB_HOST_BITATTCHE (0x0800u) +#define USB_HOST_BITEOFERRE (0x0040u) +#define USB_HOST_BITBCHG (0x4000u) +#define USB_HOST_BITDTCH (0x1000u) +#define USB_HOST_BITATTCH (0x0800u) +#define USB_HOST_BITEOFERR (0x0040u) + +#define USB_HOST_BITSIGNE (0x0020u) +#define USB_HOST_BITSACKE (0x0010u) +#define USB_HOST_BITSIGN (0x0020u) +#define USB_HOST_BITSACK (0x0010u) + +#define USB_HOST_BITSUREQ (0x4000u) +#define USB_HOST_BITSQSET (0x0080u) +#define USB_HOST_PID_STALL2 (0x0003u) +#define USB_HOST_PID_STALL (0x0002u) +#define USB_HOST_PID_BUF (0x0001u) +#define USB_HOST_PID_NAK (0x0000u) + +#define USB_HOST_PIPExBUF (64u) + +#define USB_HOST_D0FIFO (0) +#define USB_HOST_D1FIFO (1) +#define USB_HOST_DMA_READY (0) +#define USB_HOST_DMA_BUSY (1) +#define USB_HOST_DMA_BUSYEND (2) + +#define USB_HOST_FIFO_USE (0x7000) + +#define USB_HOST_FIFOERROR (0xffff) +#define USB_HOST_WRITEEND (0) +#define USB_HOST_WRITESHRT (1) +#define USB_HOST_WRITING (2) +#define USB_HOST_WRITEDMA (3) +#define USB_HOST_READEND (0) +#define USB_HOST_READSHRT (1) +#define USB_HOST_READING (2) +#define USB_HOST_READOVER (3) +#define USB_HOST_READZERO (4) + +#define USB_HOST_CMD_IDLE (0x0000) +#define USB_HOST_CMD_DOING (0x0001) +#define USB_HOST_CMD_DONE (0x0002) +#define USB_HOST_CMD_NORES (0x0003) +#define USB_HOST_CMD_STALL (0x0004) +#define USB_HOST_CMD_FIELD (0x000f) + +#if 0 +#define USB_HOST_CHG_CMDFIELD( r, v ) do { r &= ( ~USB_HOST_CMD_FIELD ); \ + r |= v; } while(0) +#endif + +#define USB_HOST_MODE_WRITE (0x0100) +#define USB_HOST_MODE_READ (0x0200) +#define USB_HOST_MODE_NO_DATA (0x0300) +#define USB_HOST_MODE_FIELD (0x0f00) + +#define USB_HOST_STAGE_SETUP (0x0010) +#define USB_HOST_STAGE_DATA (0x0020) +#define USB_HOST_STAGE_STATUS (0x0030) +#define USB_HOST_STAGE_FIELD (0x00f0) + +#if 0 +#define USB_HOST_CHG_STAGEFIELD( r, v ) do { r &= ( ~USB_HOST_STAGE_FIELD ); \ + r |= v; } while(0) +#endif + +#define USB_HOST_DEVADD_MASK (0x7fc0) + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ +extern uint16_t g_usb_host_elt_clockmode; + +#endif /* USB_HOST_H */ + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host_version.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host_version.h new file mode 100644 index 0000000000..33b82ea6f9 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host_version.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb_host_version.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ + +#define USB_HOST_LOCAL_Rev "VER080_140709" + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c new file mode 100644 index 0000000000..e1a96e60fe --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c @@ -0,0 +1,1051 @@ +/* Copyright (c) 2010-2011 mbed.org, MIT License +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this software +* and associated documentation files (the "Software"), to deal in the Software without +* restriction, including without limitation the rights to use, copy, modify, merge, publish, +* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#include +#include "cmsis.h" +#include "cmsis_os.h" +#include "ohci_wrapp_RZ_A1.h" +#include "ohci_wrapp_RZ_A1_local.h" + +#include "rza_io_regrw.h" +#include "usb0_host.h" + +/* ------------------ HcControl Register --------------------- */ +#define OR_CONTROL_PLE (0x00000004) +#define OR_CONTROL_CLE (0x00000010) +#define OR_CONTROL_BLE (0x00000020) +/* ----------------- HcCommandStatus Register ----------------- */ +#define OR_CMD_STATUS_HCR (0x00000001) +#define OR_CMD_STATUS_CLF (0x00000002) +#define OR_CMD_STATUS_BLF (0x00000004) +#define OR_CMD_STATUS_OCR (0x00000008) +/* --------------- HcInterruptStatus Register ----------------- */ +#define OR_INTR_STATUS_WDH (0x00000002) +#define OR_INTR_STATUS_RHSC (0x00000040) +/* --------------- HcInterruptEnable Register ----------------- */ +#define OR_INTR_ENABLE_WDH (0x00000002) +#define OR_INTR_ENABLE_RHSC (0x00000040) +/* -------------- HcRhPortStatus[1:NDP] Register -------------- */ +#define OR_RH_PORT_CSC (0x00010000) +#define OR_RH_PORT_LSDA (0x00000200) +#define OR_RH_PORT_PRS (0x00000010) +#define OR_RH_PORT_POCI (0x00000008) +#define OR_RH_PORT_CCS (0x00000001) + +#define ED_SKIP (0x00004000) /* Skip this ep in queue */ +#define ED_TOGLE_CARRY (0x00000002) +#define ED_HALTED (0x00000001) + +#define TD_SETUP (0x00000000) /* Direction of Setup Packet */ +#define TD_OUT (0x00080000) /* Direction Out */ +#define TD_TOGGLE_0 (0x02000000) /* Toggle 0 */ +#define TD_TOGGLE_1 (0x03000000) /* Toggle 1 */ + +/* -------------- USB Standard Requests -------------- */ +#define GET_STATUS (0x00) +#define SET_FEATURE (0x03) +#define SET_ADDRESS (0x05) + +#define TD_CTL_MSK_DP (0x00180000) +#define TD_CTL_MSK_T (0x03000000) +#define TD_CTL_MSK_CC (0xF0000000) +#define TD_CTL_MSK_EC (0x0C000000) +#define TD_CTL_SHFT_CC (28) +#define TD_CTL_SHFT_EC (26) +#define TD_CTL_SHFT_T (24) +#define ED_SHFT_TOGLE_CARRY (1) +#define SIG_GEN_LIST_REQ (1) + +#define CTL_TRANS_TIMEOUT (1000) +#define BLK_TRANS_TIMEOUT (5) +#define INT_TRANS_MAX_NUM (4) /* min:1 max:4 */ +#define TOTAL_SEM_NUM (5 + (2 * INT_TRANS_MAX_NUM)) + +#define PORT_LOW_SPEED (0x00000200) +#define PORT_HIGH_SPEED (0x00000400) +#define PORT_NUM (16 + 1) /* num + root(1) */ + +typedef struct tag_hctd { + uint32_t control; /* Transfer descriptor control */ + uint8_t *currBufPtr; /* Physical address of current buffer pointer */ + struct tag_hctd *nextTD; /* Physical pointer to next Transfer Descriptor */ + uint8_t *bufEnd; /* Physical address of end of buffer */ +} hctd_t; + +typedef struct tag_hced { + uint32_t control; /* Endpoint descriptor control */ + hctd_t *tailTD; /* Physical address of tail in Transfer descriptor list */ + hctd_t *headTD; /* Physcial address of head in Transfer descriptor list */ + struct tag_hced *nextED; /* Physical address of next Endpoint descriptor */ +} hced_t; + +typedef struct tag_hcca { + uint32_t IntTable[32]; /* Interrupt Table */ + uint32_t FrameNumber; /* Frame Number */ + uint32_t DoneHead; /* Done Head */ + volatile uint8_t Reserved[116]; /* Reserved for future use */ + volatile uint8_t Unknown[4]; /* Unused */ +} hcca_t; + +typedef struct tag_usb_ohci_reg { + volatile uint32_t HcRevision; + volatile uint32_t HcControl; + volatile uint32_t HcCommandStatus; + volatile uint32_t HcInterruptStatus; + volatile uint32_t HcInterruptEnable; + volatile uint32_t HcInterruptDisable; + volatile uint32_t HcHCCA; + volatile uint32_t HcPeriodCurrentED; + volatile uint32_t HcControlHeadED; + volatile uint32_t HcControlCurrentED; + volatile uint32_t HcBulkHeadED; + volatile uint32_t HcBulkCurrentED; + volatile uint32_t HcDoneHead; + volatile uint32_t HcFmInterval; + volatile uint32_t HcFmRemaining; + volatile uint32_t HcFmNumber; + volatile uint32_t HcPeriodicStart; + volatile uint32_t HcLSThreshold; + volatile uint32_t HcRhDescriptorA; + volatile uint32_t HcRhDescriptorB; + volatile uint32_t HcRhStatus; + volatile uint32_t HcRhPortStatus1; +} usb_ohci_reg_t; + +typedef struct tag_genelal_ed { + osThreadId tskid; + osSemaphoreId semid_wait; + osSemaphoreId semid_list; + hctd_t *p_curr_td; + hced_t *p_curr_ed; + uint32_t pipe_no; + uint32_t trans_wait; + uint32_t cycle_time; + uint8_t *p_start_buf; +} genelal_ed_t; + +typedef struct tag_tdinfo { + uint32_t count; + uint32_t direction; + uint32_t msp; + uint16_t devadr; + uint16_t speed; /* 1:Speed = Low */ + uint8_t endpoint_no; +} tdinfo_t; + +typedef struct tag_split_trans { + uint16_t root_devadr; + uint16_t get_port; + uint16_t port_speed; + uint16_t reset_port; + uint32_t seq_cnt; + uint32_t port_sts_bits[PORT_NUM]; +} split_trans_t; + +static void callback_task(void const * argument); +static void control_ed_task(void const * argument); +static void bulk_ed_task(void const * argument); +static void int_ed_task(void const * argument); +static int32_t int_trans_doing(hced_t *p_ed, uint32_t index); +static int32_t chk_genelal_ed(genelal_ed_t *p_g_ed); +static void chk_td_done(genelal_ed_t *p_g_ed); +static void chk_split_trans_setting(genelal_ed_t *p_g_ed); +static void set_split_trans_setting(void); +static void control_trans(genelal_ed_t *p_g_ed); +static void bulk_trans(genelal_ed_t *p_g_ed); +static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index); +static uint32_t chk_cycle(hced_t *p_ed); +static void int_trans(genelal_ed_t *p_g_ed); +static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info); +static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed); +static void connect_check(void); + +extern USB_HOST_CFG_PIPETBL_t usb0_host_blk_ep_tbl1[]; +extern USB_HOST_CFG_PIPETBL_t usb0_host_int_ep_tbl1[]; + +static usb_ohci_reg_t usb_reg; +static usb_ohci_reg_t *p_usb_reg = &usb_reg; +static usbisr_fnc_t *p_usbisr_cb = NULL; +static osSemaphoreId semid_cb = NULL; +static uint32_t connect_change = 0xFFFFFFFF; +static uint32_t init_end = 0; +static genelal_ed_t ctl_ed; +static genelal_ed_t blk_ed; +static genelal_ed_t int_ed[INT_TRANS_MAX_NUM]; +static split_trans_t split_ctl; + +osSemaphoreDef(ohciwrapp_sem_01); +osSemaphoreDef(ohciwrapp_sem_02); +osSemaphoreDef(ohciwrapp_sem_03); +osSemaphoreDef(ohciwrapp_sem_04); +osSemaphoreDef(ohciwrapp_sem_05); +osSemaphoreDef(ohciwrapp_sem_06); +osSemaphoreDef(ohciwrapp_sem_07); +#if (INT_TRANS_MAX_NUM >= 2) +osSemaphoreDef(ohciwrapp_sem_08); +osSemaphoreDef(ohciwrapp_sem_09); +#endif +#if (INT_TRANS_MAX_NUM >= 3) +osSemaphoreDef(ohciwrapp_sem_10); +osSemaphoreDef(ohciwrapp_sem_11); +#endif +#if (INT_TRANS_MAX_NUM >= 4) +osSemaphoreDef(ohciwrapp_sem_12); +osSemaphoreDef(ohciwrapp_sem_13); +#endif + +osThreadDef(callback_task, osPriorityHigh, 512); +osThreadDef(control_ed_task, osPriorityNormal, 512); +osThreadDef(bulk_ed_task, osPriorityNormal, 512); +osThreadDef(int_ed_task, osPriorityAboveNormal, 512); + +void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc, uint32_t hi_speed) { + static const osSemaphoreDef_t * const sem_def_tbl[TOTAL_SEM_NUM] = { + osSemaphore(ohciwrapp_sem_01), osSemaphore(ohciwrapp_sem_02), osSemaphore(ohciwrapp_sem_03) + , osSemaphore(ohciwrapp_sem_04), osSemaphore(ohciwrapp_sem_05), osSemaphore(ohciwrapp_sem_06) + , osSemaphore(ohciwrapp_sem_07) +#if (INT_TRANS_MAX_NUM >= 2) + , osSemaphore(ohciwrapp_sem_08), osSemaphore(ohciwrapp_sem_09) +#endif +#if (INT_TRANS_MAX_NUM >= 3) + , osSemaphore(ohciwrapp_sem_10), osSemaphore(ohciwrapp_sem_11) +#endif +#if (INT_TRANS_MAX_NUM >= 4) + , osSemaphore(ohciwrapp_sem_12), osSemaphore(ohciwrapp_sem_13) +#endif + }; + uint32_t cnt; + uint32_t index = 0; + + /* Disables interrupt for usb */ + GIC_DisableIRQ(USBI0_IRQn); + + /* P4_1(USB0_EN) */ + GPIOP4 &= ~0x0002; /* Outputs low level */ + GPIOPMC4 &= ~0x0002; /* Port mode */ + GPIOPM4 &= ~0x0002; /* Output mode */ + + p_usbisr_cb = p_usbisr_fnc; + if (hi_speed == 0) { + g_usb0_host_SupportUsbDeviceSpeed = USB_HOST_FULL_SPEED; + } else { + g_usb0_host_SupportUsbDeviceSpeed = USB_HOST_HIGH_SPEED; + } + p_usb_reg->HcRevision = 0x00000010; + p_usb_reg->HcControl = 0x00000000; + p_usb_reg->HcCommandStatus = 0x00000000; + p_usb_reg->HcInterruptStatus = 0x00000000; + p_usb_reg->HcInterruptEnable = 0x00000000; + p_usb_reg->HcInterruptDisable = 0x00000000; + p_usb_reg->HcHCCA = 0x00000000; + p_usb_reg->HcPeriodCurrentED = 0x00000000; + p_usb_reg->HcControlHeadED = 0x00000000; + p_usb_reg->HcControlCurrentED = 0x00000000; + p_usb_reg->HcBulkHeadED = 0x00000000; + p_usb_reg->HcBulkCurrentED = 0x00000000; + p_usb_reg->HcDoneHead = 0x00000000; + p_usb_reg->HcFmInterval = 0x00002EDF; + p_usb_reg->HcFmRemaining = 0x00002EDF; + p_usb_reg->HcFmNumber = 0x00000000; + p_usb_reg->HcPeriodicStart = 0x00000000; + p_usb_reg->HcLSThreshold = 0x00000628; + p_usb_reg->HcRhDescriptorA = 0xFF000901; + p_usb_reg->HcRhDescriptorB = 0x00020000; + p_usb_reg->HcRhStatus = 0x00000000; + p_usb_reg->HcRhPortStatus1 = 0x00000000; + + GPIOP4 |= 0x0002; /* P4_1 Outputs high level */ + osDelay(5); + GPIOP4 &= ~0x0002; /* P4_1 Outputs low level */ + osDelay(10); + + if (init_end == 0) { + (void)memset(&ctl_ed, 0, sizeof(ctl_ed)); + (void)memset(&blk_ed, 0, sizeof(blk_ed)); + (void)memset(&int_ed[0], 0, sizeof(int_ed)); + + /* callback */ + semid_cb = osSemaphoreCreate(sem_def_tbl[index], 0); + index++; + (void)osThreadCreate(osThread(callback_task), 0); + + /* control transfer */ + ctl_ed.semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0); + index++; + ctl_ed.semid_list = osSemaphoreCreate(sem_def_tbl[index], 0); + index++; + ctl_ed.tskid = osThreadCreate(osThread(control_ed_task), 0); + + /* bulk transfer */ + blk_ed.semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0); + index++; + blk_ed.semid_list = osSemaphoreCreate(sem_def_tbl[index], 0); + index++; + blk_ed.tskid = osThreadCreate(osThread(bulk_ed_task), 0); + + /* interrupt transfer */ + for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) { + int_ed[cnt].semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0); + index++; + int_ed[cnt].semid_list = osSemaphoreCreate(sem_def_tbl[index], 0); + index++; + int_ed[cnt].tskid = osThreadCreate(osThread(int_ed_task), (void *)cnt); + } + init_end = 1; + } +} + +uint32_t ohciwrapp_reg_r(uint32_t reg_ofs) { + if (init_end == 0) { + return 0; + } + + return *(uint32_t *)((uint8_t *)p_usb_reg + reg_ofs); +} + +void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data) { + uint32_t cnt; + uint32_t last_data; + hcca_t *p_hcca; + + if (init_end == 0) { + return; + } + + switch (reg_ofs) { + case OHCI_REG_CONTROL: + last_data = p_usb_reg->HcControl; + p_usb_reg->HcControl = (set_data & 0x000007FF); + if ((last_data & OR_CONTROL_CLE) != (set_data & OR_CONTROL_CLE)) { + /* change CLE */ + if ((set_data & OR_CONTROL_CLE) != 0) { + (void)osSemaphoreRelease(ctl_ed.semid_list); + } else { + if (ctl_ed.trans_wait == 1) { + ctl_ed.trans_wait = 0; + (void)osSemaphoreRelease(ctl_ed.semid_wait); + } + (void)osSemaphoreWait(ctl_ed.semid_list, osWaitForever); + } + } + if ((last_data & OR_CONTROL_BLE) != (set_data & OR_CONTROL_BLE)) { + /* change BLE */ + if ((set_data & OR_CONTROL_BLE) != 0) { + (void)osSemaphoreRelease(blk_ed.semid_list); + } else { + if (blk_ed.trans_wait == 1) { + blk_ed.trans_wait = 0; + (void)osSemaphoreRelease(blk_ed.semid_wait); + } + (void)osSemaphoreWait(blk_ed.semid_list, osWaitForever); + } + } + if ((last_data & OR_CONTROL_PLE) != (set_data & OR_CONTROL_PLE)) { + /* change PLE */ + for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) { + if ((set_data & OR_CONTROL_PLE) != 0) { + (void)osSemaphoreRelease(int_ed[cnt].semid_list); + } else { + if (int_ed[cnt].trans_wait == 1) { + int_ed[cnt].trans_wait = 0; + (void)osSemaphoreRelease(int_ed[cnt].semid_wait); + } + (void)osSemaphoreWait(int_ed[cnt].semid_list, osWaitForever); + } + } + } + break; + case OHCI_REG_COMMANDSTATUS: + if ((set_data & OR_CMD_STATUS_HCR) != 0) { /* HostController Reset */ + p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_HCR; + if (usb0_api_host_init(16, g_usb0_host_SupportUsbDeviceSpeed, USBHCLOCK_X1_48MHZ) == USB_HOST_ATTACH) { + ohciwrapp_loc_Connect(1); + } + p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_HCR; + } + if ((set_data & OR_CMD_STATUS_CLF) != 0) { + p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_CLF; + osSignalSet(ctl_ed.tskid, SIG_GEN_LIST_REQ); + } + if ((set_data & OR_CMD_STATUS_BLF) != 0) { + p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_BLF; + osSignalSet(blk_ed.tskid, SIG_GEN_LIST_REQ); + } + if ((set_data & OR_CMD_STATUS_OCR) != 0) { + p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_OCR; + } else { + p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_OCR; + } + break; + case OHCI_REG_INTERRUPTSTATUS: + if (((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) != 0) + && ((set_data & OR_INTR_STATUS_WDH) != 0)) { + if (p_usb_reg->HcDoneHead != 0x00000000) { + p_hcca = (hcca_t *)p_usb_reg->HcHCCA; + p_hcca->DoneHead = p_usb_reg->HcDoneHead; + p_usb_reg->HcDoneHead = 0x00000000; + p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH; + (void)osSemaphoreRelease(semid_cb); + } else { + p_usb_reg->HcInterruptStatus &= ~OR_INTR_STATUS_WDH; + } + } + if ((set_data & OR_INTR_STATUS_RHSC) != 0) { + p_usb_reg->HcInterruptStatus &= ~OR_INTR_STATUS_RHSC; + } + break; + case OHCI_REG_INTERRUPTENABLE: + case OHCI_REG_INTERRUPTDISABLE: + case OHCI_REG_HCCA: + case OHCI_REG_CONTROLHEADED: + case OHCI_REG_CONTROLCURRENTED: + case OHCI_REG_BULKHEADED: + case OHCI_REG_BULKCURRENTED: + case OHCI_REG_FMINTERVAL: + case OHCI_REG_FMREMAINING: + case OHCI_REG_PERIODICSTART: + case OHCI_REG_LSTHRESHOLD: + case OHCI_REG_RHDESCRIPTORA: + case OHCI_REG_RHDESCRIPTORB: + case OHCI_REG_RHSTATUS: + *(uint32_t *)((uint8_t *)p_usb_reg + reg_ofs) = set_data; + break; + case OHCI_REG_RHPORTSTATUS1: + p_usb_reg->HcRhPortStatus1 &= ~(set_data & 0xFFFF0000); + if ((set_data & OR_RH_PORT_PRS) != 0) { /* Set Port Reset */ + p_usb_reg->HcRhPortStatus1 |= OR_RH_PORT_PRS; + usb0_host_UsbBusReset(); + p_usb_reg->HcRhPortStatus1 &= ~OR_RH_PORT_PRS; + } + break; + case OHCI_REG_REVISION: + case OHCI_REG_PERIODCURRENTED: + case OHCI_REG_DONEHEADED: + case OHCI_REG_FMNUMBER: + default: + /* Do Nothing */ + break; + } +} + +static void callback_task(void const * argument) { + usbisr_fnc_t *p_wk_cb = p_usbisr_cb; + + if (p_wk_cb == NULL) { + return; + } + + while (1) { + osSemaphoreWait(semid_cb, osWaitForever); + if (connect_change != 0xFFFFFFFF) { + connect_change = 0xFFFFFFFF; + connect_check(); + } + p_wk_cb(); + } +} + +static void control_ed_task(void const * argument) { + while (1) { + osSignalWait(SIG_GEN_LIST_REQ, osWaitForever); + (void)osSemaphoreWait(ctl_ed.semid_list, osWaitForever); + while ((p_usb_reg->HcControl & OR_CONTROL_CLE) != 0) { + if ((p_usb_reg->HcControlCurrentED == 0) + && ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_CLF) != 0)) { + p_usb_reg->HcControlCurrentED = p_usb_reg->HcControlHeadED; + p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_CLF; + } + if (p_usb_reg->HcControlCurrentED != 0) { + ctl_ed.p_curr_ed = (hced_t *)p_usb_reg->HcControlCurrentED; + if (chk_genelal_ed(&ctl_ed) != 0) { + control_trans(&ctl_ed); + chk_split_trans_setting(&ctl_ed); + p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_CLF; + chk_td_done(&ctl_ed); + } + p_usb_reg->HcControlCurrentED = (uint32_t)ctl_ed.p_curr_ed->nextED; + } else { + break; + } + } + if ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_CLF) != 0) { + osSignalSet(ctl_ed.tskid, SIG_GEN_LIST_REQ); + } + (void)osSemaphoreRelease(ctl_ed.semid_list); + } +} + +static void bulk_ed_task(void const * argument) { + while (1) { + osSignalWait(SIG_GEN_LIST_REQ, osWaitForever); + (void)osSemaphoreWait(blk_ed.semid_list, osWaitForever); + while ((p_usb_reg->HcControl & OR_CONTROL_BLE) != 0) { + if ((p_usb_reg->HcBulkCurrentED == 0) + && ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_BLF) != 0)) { + p_usb_reg->HcBulkCurrentED = p_usb_reg->HcBulkHeadED; + p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_BLF; + } + if (p_usb_reg->HcBulkCurrentED != 0) { + blk_ed.p_curr_ed = (hced_t *)p_usb_reg->HcBulkCurrentED; + if (chk_genelal_ed(&blk_ed) != 0) { + bulk_trans(&blk_ed); + p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_BLF; + chk_td_done(&blk_ed); + } + p_usb_reg->HcBulkCurrentED = (uint32_t)blk_ed.p_curr_ed->nextED; + } else { + break; + } + } + if ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_BLF) != 0) { + osSignalSet(blk_ed.tskid, SIG_GEN_LIST_REQ); + } + (void)osSemaphoreRelease(blk_ed.semid_list); + } +} + +static void int_ed_task(void const * argument) { + genelal_ed_t *p_int_ed = &int_ed[(uint32_t)argument]; + uint32_t cnt; + uint32_t wait_cnt = 0; + hcca_t *p_hcca; + hced_t *p_ed; + + while (1) { + (void)osSemaphoreWait(p_int_ed->semid_list, osWaitForever); + if (p_int_ed->p_curr_ed == NULL) { + for (cnt = 0; (cnt < 32) && ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0) + && (p_int_ed->p_curr_ed == NULL); cnt++) { + p_hcca = (hcca_t *)p_usb_reg->HcHCCA; + p_ed = (hced_t *)p_hcca->IntTable[cnt]; + while ((p_ed != NULL) && ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0) + && (p_int_ed->p_curr_ed == NULL)) { + if (int_trans_doing(p_ed, (uint32_t)argument) == 0) { + p_int_ed->p_curr_ed = p_ed; + if (chk_genelal_ed(p_int_ed) != 0) { + int_trans_setting(p_int_ed, (uint32_t)argument); + } else { + p_int_ed->p_curr_ed = NULL; + } + } + p_ed = p_ed->nextED; + } + } + } + if (p_int_ed->p_curr_ed != NULL) { + while ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0) { + if (chk_genelal_ed(p_int_ed) != 0) { + int_trans(p_int_ed); + chk_td_done(p_int_ed); + wait_cnt = p_int_ed->cycle_time; + } else { + if (wait_cnt > 0) { + wait_cnt--; + } else { + p_int_ed->p_curr_ed = NULL; + } + break; + } + } + } + (void)osSemaphoreRelease(p_int_ed->semid_list); + if (p_int_ed->p_curr_ed == NULL) { + osDelay(10); + } else { + osDelay(1); + } + } +} + +static int32_t int_trans_doing(hced_t *p_ed, uint32_t index) { + uint32_t cnt; + int32_t ret = 0; + + for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) { + if ((index != cnt) && (int_ed[cnt].p_curr_ed == p_ed)) { + ret = 1; + } + } + + return ret; +} + +static int32_t chk_genelal_ed(genelal_ed_t *p_g_ed){ + int32_t ret = 0; + hced_t *p_ed = p_g_ed->p_curr_ed; + + if (((p_ed->control & ED_SKIP) != 0) + || (((uint32_t)p_ed->headTD & ED_HALTED) != 0) + || (((uint32_t)p_ed->tailTD & 0xFFFFFFF0) == ((uint32_t)p_ed->headTD & 0xFFFFFFF0))) { + /* Do Nothing */ + } else if ((p_ed->control & 0x0000007F) > 10) { + p_ed->headTD = (hctd_t *)((uint32_t)p_ed->headTD | ED_HALTED); + } else { + p_g_ed->p_curr_td = (hctd_t *)((uint32_t)p_ed->headTD & 0xFFFFFFF0); + if (p_g_ed->p_curr_td == NULL) { + p_ed->headTD = (hctd_t *)((uint32_t)p_ed->headTD | ED_HALTED); + } else { + p_g_ed->p_start_buf = p_g_ed->p_curr_td->currBufPtr; + ret = 1; + } + } + + return ret; +} + +static void chk_td_done(genelal_ed_t *p_g_ed) { + hcca_t *p_hcca; + uint32_t ConditionCode = RZA_IO_RegRead_32(&p_g_ed->p_curr_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC); + + if ((ConditionCode != TD_CC_NOT_ACCESSED_1) && (ConditionCode != TD_CC_NOT_ACCESSED_2)) { + p_g_ed->p_curr_ed->headTD = (hctd_t *)(((uint32_t)p_g_ed->p_curr_td->nextTD & 0xFFFFFFF0) + | ((uint32_t)p_g_ed->p_curr_ed->headTD & 0x0000000F)); + p_g_ed->p_curr_td->nextTD = (hctd_t *)p_usb_reg->HcDoneHead; + p_usb_reg->HcDoneHead = (uint32_t)p_g_ed->p_curr_td; + if ((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) == 0) { + p_hcca = (hcca_t *)p_usb_reg->HcHCCA; + p_hcca->DoneHead = p_usb_reg->HcDoneHead; + p_usb_reg->HcDoneHead = 0x00000000; + p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH; + (void)osSemaphoreRelease(semid_cb); + } + } +} + +static void chk_split_trans_setting(genelal_ed_t *p_g_ed) { + uint8_t *p_buf; + tdinfo_t td_info; + + /* Hi-Speed mode only */ + if (g_usb0_host_UsbDeviceSpeed != USB_HOST_HIGH_SPEED) { + return; + } + + if (RZA_IO_RegRead_32(&p_g_ed->p_curr_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC) != TD_CC_NOERROR) { + return; + } + + get_td_info(p_g_ed, &td_info); + p_buf = p_g_ed->p_start_buf; + + if (td_info.direction == 0) { + uint8_t bRequest = p_buf[1]; + uint16_t wValue = (p_buf[3] << 8) + p_buf[2]; + uint16_t wIndx = (p_buf[5] << 8) + p_buf[4]; + uint16_t devadd; + + if ((td_info.devadr == 0) && (bRequest == SET_ADDRESS)) { + /* SET_ADDRESS */ + usb0_host_get_devadd(USB_HOST_DEVICE_0, &devadd); + usb0_host_set_devadd(wValue, &devadd); + if (split_ctl.root_devadr == 0) { + split_ctl.root_devadr = wValue; /* New Address */ + } + } else if ((td_info.devadr == split_ctl.root_devadr) && (bRequest == SET_FEATURE) + && (wValue == 0x0004) && (split_ctl.root_devadr != 0)) { + /* SET_FEATURE PORT_RESET */ + split_ctl.reset_port = (wIndx & 0x00FF); + } else if ((td_info.devadr == split_ctl.root_devadr) && (bRequest == GET_STATUS)) { + /* GET_STATUS */ + split_ctl.get_port = wIndx; + split_ctl.seq_cnt = 1; + } else { + /* Do Nothing */ + } + } else if (td_info.direction == 2) { + if ((td_info.devadr == split_ctl.root_devadr) && (split_ctl.seq_cnt == 1)) { + if (split_ctl.get_port < PORT_NUM) { + split_ctl.port_sts_bits[split_ctl.get_port] = (p_buf[1] << 8) + p_buf[0]; + } + split_ctl.seq_cnt = 0; + } + } else { + /* Do Nothing */ + } +} + +static void set_split_trans_setting(void) { + uint16_t port_speed; + uint16_t devadd; + + if ((split_ctl.root_devadr != 0) && (split_ctl.reset_port != 0) && (split_ctl.reset_port < PORT_NUM)) { + usb0_host_get_devadd(USB_HOST_DEVICE_0, &devadd); + RZA_IO_RegWrite_16(&devadd, split_ctl.root_devadr, USB_DEVADDn_UPPHUB_SHIFT, USB_DEVADDn_UPPHUB); + RZA_IO_RegWrite_16(&devadd, split_ctl.reset_port, USB_DEVADDn_HUBPORT_SHIFT, USB_DEVADDn_HUBPORT); + if ((split_ctl.port_sts_bits[split_ctl.reset_port] & PORT_HIGH_SPEED) != 0) { + port_speed = USB_HOST_HIGH_SPEED; + } else if ((split_ctl.port_sts_bits[split_ctl.reset_port] & PORT_LOW_SPEED) != 0) { + port_speed = USB_HOST_LOW_SPEED; + } else { + port_speed = USB_HOST_FULL_SPEED; + } + RZA_IO_RegWrite_16(&devadd, port_speed, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD); + usb0_host_set_devadd(USB_HOST_DEVICE_0, &devadd); + split_ctl.reset_port = 0; + } +} + +static void control_trans(genelal_ed_t *p_g_ed) { + hctd_t *p_td = p_g_ed->p_curr_td; + tdinfo_t td_info; + uint16_t devadd; + + get_td_info(p_g_ed, &td_info); + + if (g_usb0_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) { + if (td_info.devadr == 0) { + set_split_trans_setting(); + } + } else { + /* When a non-Hi-Speed, the communication speed is determined from the TD. */ + usb0_host_get_devadd(USB_HOST_DEVICE_0, &devadd); + if (td_info.speed == 1) { + RZA_IO_RegWrite_16(&devadd, USB_HOST_LOW_SPEED, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD); + } else { + RZA_IO_RegWrite_16(&devadd, USB_HOST_FULL_SPEED, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD); + } + usb0_host_set_devadd(td_info.devadr, &devadd); + } + + USB200.DCPMAXP = (td_info.devadr << 12) + td_info.msp; + if (td_info.direction == 0) { + g_usb0_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE); + } else if (td_info.count != 0) { + g_usb0_host_CmdStage = (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE); + } else { + g_usb0_host_CmdStage = (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE); + } + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT; + p_g_ed->pipe_no = USB_HOST_PIPE0; + + p_g_ed->trans_wait = 1; + + if (td_info.direction == 0) { + uint16_t Req = (p_td->currBufPtr[1] << 8) + p_td->currBufPtr[0]; + uint16_t Val = (p_td->currBufPtr[3] << 8) + p_td->currBufPtr[2]; + uint16_t Indx = (p_td->currBufPtr[5] << 8) + p_td->currBufPtr[4]; + uint16_t Len = (p_td->currBufPtr[7] << 8) + p_td->currBufPtr[6]; + + g_usb0_host_data_pointer[USB_HOST_PIPE0] = p_td->bufEnd; + usb0_host_SetupStage(Req, Val, Indx, Len); + } else if (td_info.direction == 1) { + usb0_host_CtrlWriteStart(td_info.count, p_td->currBufPtr); + } else { + usb0_host_CtrlReadStart(td_info.count, p_td->currBufPtr); + } + + (void)osSemaphoreWait(p_g_ed->semid_wait, CTL_TRANS_TIMEOUT); + if (p_g_ed->trans_wait == 1) { + p_g_ed->trans_wait = 0; + RZA_IO_RegWrite_32(&p_td->control, TD_CC_DEVICENOTRESPONDING, TD_CTL_SHFT_CC, TD_CTL_MSK_CC); + } + + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE; + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE; +} + +static void bulk_trans(genelal_ed_t *p_g_ed) { + hctd_t *p_td = p_g_ed->p_curr_td; + hced_t *p_ed = p_g_ed->p_curr_ed; + tdinfo_t td_info; + USB_HOST_CFG_PIPETBL_t *user_table = &usb0_host_blk_ep_tbl1[0]; + uint8_t wk_table[6]; + + get_td_info(p_g_ed, &td_info); + + wk_table[0] = 0; + wk_table[1] = USB_HOST_ENDPOINT_DESC; + wk_table[2] = td_info.endpoint_no; + if (td_info.direction == 2) { + wk_table[2] |= USB_HOST_EP_IN; + } + wk_table[3] = USB_HOST_EP_BULK; + wk_table[4] = (uint8_t)td_info.msp; + wk_table[5] = (uint8_t)(td_info.msp >> 8); + p_g_ed->pipe_no = user_table->pipe_number; + usb0_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table); + + set_togle(p_g_ed->pipe_no, p_td, p_ed); + + p_g_ed->trans_wait = 1; + if (td_info.direction == 1) { + usb0_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); + } else { + usb0_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); + } + + (void)osSemaphoreWait(p_g_ed->semid_wait, BLK_TRANS_TIMEOUT); + usb0_host_stop_transfer(p_g_ed->pipe_no); +} + +static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) { + hctd_t *p_td = p_g_ed->p_curr_td; + hced_t *p_ed = p_g_ed->p_curr_ed; + tdinfo_t td_info; + USB_HOST_CFG_PIPETBL_t *user_table = &usb0_host_int_ep_tbl1[index]; + uint8_t wk_table[6]; + uint32_t cycle_time; + uint16_t devadd; + + get_td_info(p_g_ed, &td_info); + + wk_table[0] = 0; + wk_table[1] = USB_HOST_ENDPOINT_DESC; + wk_table[2] = td_info.endpoint_no; + if (td_info.direction == 2) { + wk_table[2] |= USB_HOST_EP_IN; + } + wk_table[3] = USB_HOST_EP_INT; + wk_table[4] = (uint8_t)td_info.msp; + wk_table[5] = (uint8_t)(td_info.msp >> 8); + cycle_time = chk_cycle(p_ed); + p_g_ed->cycle_time = cycle_time; + user_table->pipe_cycle = 0; + while (cycle_time > 1) { + cycle_time >>= 1; + user_table->pipe_cycle++; + } + if (g_usb0_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) { + usb0_host_get_devadd(td_info.devadr, &devadd); + if (RZA_IO_RegRead_16(&devadd, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD) == USB_HOST_HIGH_SPEED) { + user_table->pipe_cycle += 3; + if (user_table->pipe_cycle > 7) { + user_table->pipe_cycle = 7; + } + } + } + + p_g_ed->pipe_no = user_table->pipe_number; + usb0_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table); + + set_togle(p_g_ed->pipe_no, p_td, p_ed); +} + +static uint32_t chk_cycle(hced_t *p_ed) { + uint32_t cnt; + uint32_t hit_cnt = 0; + uint32_t cycle_time = 1; + hcca_t *p_hcca; + hced_t *p_wk_ed; + + p_hcca = (hcca_t *)p_usb_reg->HcHCCA; + + for (cnt = 0; cnt < 32; cnt++) { + p_wk_ed = (hced_t *)p_hcca->IntTable[cnt]; + while (p_wk_ed != NULL) { + if (p_wk_ed == p_ed) { + hit_cnt++; + break; + } + p_wk_ed = p_wk_ed->nextED; + } + } + if (hit_cnt < 2) { + cycle_time = 32; + } else if (hit_cnt < 4) { + cycle_time = 16; + } else if (hit_cnt < 8) { + cycle_time = 8; + } else if (hit_cnt < 16) { + cycle_time = 4; + } else if (hit_cnt < 32) { + cycle_time = 2; + } else{ + cycle_time = 1; + } + + return cycle_time; +} + +static void int_trans(genelal_ed_t *p_g_ed) { + hctd_t *p_td = p_g_ed->p_curr_td; + tdinfo_t td_info; + + get_td_info(p_g_ed, &td_info); + p_g_ed->trans_wait = 1; + if (td_info.direction == 1) { + usb0_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); + } else { + usb0_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); + } + (void)osSemaphoreWait(p_g_ed->semid_wait, osWaitForever); + usb0_host_stop_transfer(p_g_ed->pipe_no); +} + +static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info) { + hctd_t *p_td = p_g_ed->p_curr_td; + hced_t *p_ed = p_g_ed->p_curr_ed; + + p_td_info->endpoint_no = (uint8_t)((p_ed->control >> 7) & 0x0000000F); + p_td_info->msp = (p_ed->control >> 16) & 0x000007FF; + p_td_info->devadr = p_ed->control & 0x0000000F; + p_td_info->speed = (p_ed->control >> 13) & 0x00000001; + p_td_info->direction = (p_ed->control >> 11) & 0x00000003; + if ((p_td_info->direction == 0) || (p_td_info->direction == 3)) { + if ((p_td->control & TD_CTL_MSK_DP) == TD_SETUP) { + p_td_info->direction = 0; + } else if ((p_td->control & TD_CTL_MSK_DP) == TD_OUT) { + p_td_info->direction = 1; + } else { + p_td_info->direction = 2; + } + } + if (p_td->currBufPtr != NULL) { + p_td_info->count = (uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1; + } else { + p_td_info->count = 0; + } +} + +static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed) { + if ((p_td->control & TD_CTL_MSK_T) == TD_TOGGLE_0) { + usb0_host_set_sqclr(pipe); + } else if ((p_td->control & TD_CTL_MSK_T) == TD_TOGGLE_1) { + usb0_host_set_sqset(pipe); + } else if (((uint32_t)p_ed->headTD & ED_TOGLE_CARRY) == 0) { + usb0_host_set_sqclr(pipe); + } else { + usb0_host_set_sqset(pipe); + } +} + +static void connect_check(void) { + uint32_t cnt; + uint32_t type = 0; + uint16_t stat; + uint16_t devadd = 0; + uint32_t wk_HcRhPortStatus1 = p_usb_reg->HcRhPortStatus1; + + if (usb0_host_CheckAttach() == USB_HOST_ATTACH) { + type = 1; + } + + if ((((wk_HcRhPortStatus1 & OR_RH_PORT_CCS) == 0) && (type == 0)) + || (((wk_HcRhPortStatus1 & OR_RH_PORT_CCS) != 0) && (type != 0))) { + return; + } + + if (type == 0) { + usb0_host_UsbDetach(); + wk_HcRhPortStatus1 &= ~OR_RH_PORT_CCS; + } else { + usb0_host_UsbAttach(); + stat = usb0_host_UsbBusReset(); + RZA_IO_RegWrite_16(&devadd, 0, USB_DEVADDn_UPPHUB_SHIFT, USB_DEVADDn_UPPHUB); + RZA_IO_RegWrite_16(&devadd, 0, USB_DEVADDn_HUBPORT_SHIFT, USB_DEVADDn_HUBPORT); + if (stat == USB_HOST_HSMODE) { + wk_HcRhPortStatus1 &= ~OR_RH_PORT_LSDA; + RZA_IO_RegWrite_16(&USB200.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL); + g_usb0_host_UsbDeviceSpeed = USB_HOST_HIGH_SPEED; + } else if (stat == USB_HOST_FSMODE) { + wk_HcRhPortStatus1 &= ~OR_RH_PORT_LSDA; + RZA_IO_RegWrite_16(&USB200.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL); + g_usb0_host_UsbDeviceSpeed = USB_HOST_FULL_SPEED; + } else { + wk_HcRhPortStatus1 |= OR_RH_PORT_LSDA; + RZA_IO_RegWrite_16(&USB200.SOFCFG, 1, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL); + g_usb0_host_UsbDeviceSpeed = USB_HOST_LOW_SPEED; + } + RZA_IO_RegWrite_16(&devadd, g_usb0_host_UsbDeviceSpeed, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD); + usb0_host_init_pipe_status(); + usb0_host_set_devadd(USB_HOST_DEVICE_0, &devadd); + wk_HcRhPortStatus1 |= OR_RH_PORT_CCS; + } + wk_HcRhPortStatus1 |= OR_RH_PORT_CSC; + p_usb_reg->HcRhPortStatus1 = wk_HcRhPortStatus1; + p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_RHSC; + (void)memset(&split_ctl, 0, sizeof(split_ctl)); + + if (type == 0) { + if (ctl_ed.trans_wait == 1) { + ohciwrapp_loc_TransEnd(ctl_ed.pipe_no, TD_CC_DEVICENOTRESPONDING); + } + if (blk_ed.trans_wait == 1) { + ohciwrapp_loc_TransEnd(blk_ed.pipe_no, TD_CC_DEVICENOTRESPONDING); + } + for (cnt = 0; cnt< INT_TRANS_MAX_NUM; cnt++) { + if (int_ed[cnt].trans_wait == 1) { + ohciwrapp_loc_TransEnd(int_ed[cnt].pipe_no, TD_CC_DEVICENOTRESPONDING); + } + } + } +} + +void ohciwrapp_loc_Connect(uint32_t type) { + connect_change = type; + (void)osSemaphoreRelease(semid_cb); +} + +void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode) { + uint32_t cnt; + uint32_t sqmon; + hctd_t *p_td; + hced_t *p_ed; + genelal_ed_t *p_wait_ed = NULL; + + if (ctl_ed.pipe_no == pipe) { + p_wait_ed = &ctl_ed; + } else if (blk_ed.pipe_no == pipe) { + p_wait_ed = &blk_ed; + } else { + for (cnt = 0; cnt< INT_TRANS_MAX_NUM; cnt++) { + if (int_ed[cnt].pipe_no == pipe) { + p_wait_ed = &int_ed[cnt]; + break; + } + } + } + if (p_wait_ed == NULL) { + return; + } + + p_td = p_wait_ed->p_curr_td; + p_ed = p_wait_ed->p_curr_ed; + if ((p_td == NULL) || (p_ed == NULL)) { + return; + } + + if (ConditionCode == TD_CC_NOERROR) { + /* ErrorCount */ + RZA_IO_RegWrite_32(&p_td->control, 0, TD_CTL_SHFT_EC, TD_CTL_MSK_EC); + + /* CurrentBufferPointer */ + p_td->currBufPtr += ((uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1) - g_usb0_host_data_count[pipe]; + } else { + /* ErrorCount */ + RZA_IO_RegWrite_32(&p_td->control, 3, TD_CTL_SHFT_EC, TD_CTL_MSK_EC); + } + + /* DataToggle */ + sqmon = usb0_host_get_sqmon(pipe); + RZA_IO_RegWrite_32(&p_td->control, sqmon, TD_CTL_SHFT_T, TD_CTL_MSK_T); + if (sqmon == 0) { + p_ed->headTD = (hctd_t *)((uint32_t)p_ed->headTD & ~ED_TOGLE_CARRY); + } else { + p_ed->headTD = (hctd_t *)((uint32_t)p_ed->headTD | ED_TOGLE_CARRY); + } + + /* ConditionCode */ + RZA_IO_RegWrite_32(&p_td->control, ConditionCode, TD_CTL_SHFT_CC, TD_CTL_MSK_CC); + + p_wait_ed->trans_wait = 0; + + (void)osSemaphoreRelease(p_wait_ed->semid_wait); +} + diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h new file mode 100644 index 0000000000..33f3281595 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h @@ -0,0 +1,60 @@ +/* Copyright (c) 2010-2011 mbed.org, MIT License +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this software +* and associated documentation files (the "Software"), to deal in the Software without +* restriction, including without limitation the rights to use, copy, modify, merge, publish, +* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef OHCI_WRAPP_RZ_A1_H +#define OHCI_WRAPP_RZ_A1_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define OHCI_REG_REVISION (0x00) +#define OHCI_REG_CONTROL (0x04) +#define OHCI_REG_COMMANDSTATUS (0x08) +#define OHCI_REG_INTERRUPTSTATUS (0x0C) +#define OHCI_REG_INTERRUPTENABLE (0x10) +#define OHCI_REG_INTERRUPTDISABLE (0x14) +#define OHCI_REG_HCCA (0x18) +#define OHCI_REG_PERIODCURRENTED (0x1C) +#define OHCI_REG_CONTROLHEADED (0x20) +#define OHCI_REG_CONTROLCURRENTED (0x24) +#define OHCI_REG_BULKHEADED (0x28) +#define OHCI_REG_BULKCURRENTED (0x2C) +#define OHCI_REG_DONEHEADED (0x30) +#define OHCI_REG_FMINTERVAL (0x34) +#define OHCI_REG_FMREMAINING (0x38) +#define OHCI_REG_FMNUMBER (0x3C) +#define OHCI_REG_PERIODICSTART (0x40) +#define OHCI_REG_LSTHRESHOLD (0x44) +#define OHCI_REG_RHDESCRIPTORA (0x48) +#define OHCI_REG_RHDESCRIPTORB (0x4C) +#define OHCI_REG_RHSTATUS (0x50) +#define OHCI_REG_RHPORTSTATUS1 (0x54) + +typedef void (usbisr_fnc_t)(void); + +extern void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc, uint32_t hi_speed); +extern uint32_t ohciwrapp_reg_r(uint32_t reg_ofs); +extern void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data); +extern void ohciwrapp_interrupt(uint32_t int_sense); + +#ifdef __cplusplus +} +#endif + +#endif /* OHCI_WRAPP_RZ_A1_H */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1_local.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1_local.h new file mode 100644 index 0000000000..250c45b660 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1_local.h @@ -0,0 +1,49 @@ +/* Copyright (c) 2010-2011 mbed.org, MIT License +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this software +* and associated documentation files (the "Software"), to deal in the Software without +* restriction, including without limitation the rights to use, copy, modify, merge, publish, +* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef OHCI_WRAPP_RZ_A1_LOCAL_H +#define OHCI_WRAPP_RZ_A1_LOCAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* ConditionCode */ +#define TD_CC_NOERROR (0) +#define TD_CC_CRC (1) +#define TD_CC_BITSTUFFING (2) +#define TD_CC_DATATOGGLEMISMATCH (3) +#define TD_CC_STALL (4) +#define TD_CC_DEVICENOTRESPONDING (5) +#define TD_CC_PIDCHECKFAILURE (6) +#define TD_CC_UNEXPECTEDPID (7) +#define TD_CC_DATAOVERRUN (8) +#define TD_CC_DATAUNDERRUN (9) +#define TD_CC_BUFFEROVERRUN (12) +#define TD_CC_BUFFERUNDERRUN (13) +#define TD_CC_NOT_ACCESSED_1 (14) +#define TD_CC_NOT_ACCESSED_2 (15) + +extern void ohciwrapp_loc_Connect(uint32_t type); +extern void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode); + +#ifdef __cplusplus +} +#endif + +#endif /* OHCI_WRAPP_RZ_A1_LOCAL_H */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dataio.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dataio.c new file mode 100644 index 0000000000..bb7b68f2bf --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dataio.c @@ -0,0 +1,2835 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_dataio.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +static uint16_t g_usb0_host_mbw[(USB_HOST_MAX_PIPE_NO + 1)]; + +static void usb0_host_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb0_host_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb0_host_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb0_host_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb0_host_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data); +static uint16_t usb0_host_read_dma_d0(uint16_t pipe); +static uint16_t usb0_host_read_dma_d1(uint16_t pipe); +static uint16_t usb0_host_write_dma_d0(uint16_t pipe); +static uint16_t usb0_host_write_dma_d1(uint16_t pipe); + +static void usb0_host_read_c_fifo(uint16_t pipe, uint16_t count); +static void usb0_host_write_c_fifo(uint16_t Pipe, uint16_t count); +static void usb0_host_read_d0_fifo(uint16_t pipe, uint16_t count); +static void usb0_host_write_d0_fifo(uint16_t pipe, uint16_t count); +static void usb0_host_read_d1_fifo(uint16_t pipe, uint16_t count); +static void usb0_host_write_d1_fifo(uint16_t pipe, uint16_t count); + +static void usb0_host_clear_transaction_counter(uint16_t pipe); +static void usb0_host_set_transaction_counter(uint16_t pipe, uint32_t count); + +static uint32_t usb0_host_com_get_dmasize(uint32_t trncount, uint32_t dtptr); + +static uint16_t usb0_host_set_dfacc_d0(uint16_t mbw, uint32_t count); +static uint16_t usb0_host_set_dfacc_d1(uint16_t mbw, uint32_t count); + + +/******************************************************************************* +* Function Name: usb0_host_start_send_transfer +* Description : Starts the USB data communication using pipe specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data data Address +* Return Value : USB_HOST_WRITEEND ; Write end +* : USB_HOST_WRITESHRT ; short data +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_WRITEDMA ; Write DMA +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t status; + uint16_t usefifo; + uint16_t mbw; + + g_usb0_host_data_count[pipe] = size; + g_usb0_host_data_pointer[pipe] = (uint8_t *)data; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + usb0_host_clear_bemp_sts(pipe); + usb0_host_clear_brdy_sts(pipe); + usb0_host_clear_nrdy_sts(pipe); + + mbw = usb0_host_get_mbw(size, (uint32_t)data); + + usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + switch (usefifo) + { + case USB_HOST_D0FIFO_USE: + case USB_HOST_D0FIFO_DMA: + usefifo = USB_HOST_D0USE; + break; + + case USB_HOST_D1FIFO_USE: + case USB_HOST_D1FIFO_DMA: + usefifo = USB_HOST_D1USE; + break; + + default: + usefifo = USB_HOST_CUSE; + break; + }; + + usb0_host_set_curpipe(USB_HOST_PIPE0, usefifo, USB_HOST_NO, mbw); + + usb0_host_clear_transaction_counter(pipe); + +#if(1) /* ohci_wrapp */ +#else + usb0_host_aclrm(pipe); +#endif + + status = usb0_host_write_buffer(pipe); + + if (status != USB_HOST_FIFOERROR) + { + usb0_host_set_pid_buf(pipe); + } + + return status; +} + +/******************************************************************************* +* Function Name: usb0_host_write_buffer +* Description : Writes data in the buffer allocated in the pipe specified by +* : the argument. The FIFO for using is set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND ; Write end +* : USB_HOST_WRITESHRT ; short data +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_WRITEDMA ; Write DMA +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_write_buffer (uint16_t pipe) +{ + uint16_t status; + uint16_t usefifo; + + g_usb0_host_PipeIgnore[pipe] = 0; + usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + switch (usefifo) + { + case USB_HOST_D0FIFO_USE: + status = usb0_host_write_buffer_d0(pipe); + break; + + case USB_HOST_D1FIFO_USE: + status = usb0_host_write_buffer_d1(pipe); + break; + + case USB_HOST_D0FIFO_DMA: + status = usb0_host_write_dma_d0(pipe); + break; + + case USB_HOST_D1FIFO_DMA: + status = usb0_host_write_dma_d1(pipe); + break; + + default: + status = usb0_host_write_buffer_c(pipe); + break; + }; + + switch (status) + { + case USB_HOST_WRITING: /* Continue of data write */ + usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ + usb0_host_enable_brdy_int(pipe); /* Enable Ready Interrupt */ + break; + + case USB_HOST_WRITEEND: /* End of data write */ + case USB_HOST_WRITESHRT: /* End of data write */ + usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + + usb0_host_clear_nrdy_sts(pipe); + usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ + + /* for last transfer */ + usb0_host_enable_bemp_int(pipe); /* Enable Empty Interrupt */ + break; + + case USB_HOST_WRITEDMA: /* DMA write */ + usb0_host_clear_nrdy_sts(pipe); + usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ + break; + + case USB_HOST_FIFOERROR: /* FIFO access status */ + default: + usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + usb0_host_disable_bemp_int(pipe); /* Disable Empty Interrupt */ + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; + break; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_write_buffer_c +* Description : Writes data in the buffer allocated in the pipe specified in +* : the argument. Writes data by CPU transfer using CFIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND ; Write end +* : USB_HOST_WRITESHRT ; short data +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_WRITEDMA ; Write DMA +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_write_buffer_c (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + + if (pipe == USB_HOST_PIPE0) + { + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_CFIFO_WRITE, mbw); + } + else + { + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw); + } + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_host_data_count[pipe] <= (uint32_t)size) + { + status = USB_HOST_WRITEEND; /* write continues */ + count = g_usb0_host_data_count[pipe]; + + if (count == 0) + { + status = USB_HOST_WRITESHRT; /* Null Packet is end of write */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ + } + } + else + { + status = USB_HOST_WRITING; /* write continues */ + count = (uint32_t)size; + } + + usb0_host_write_c_fifo(pipe, (uint16_t)count); + + if (g_usb0_host_data_count[pipe] < (uint32_t)size) + { + g_usb0_host_data_count[pipe] = 0; + + if (RZA_IO_RegRead_16(&USB200.CFIFOCTR, + USB_CFIFOCTR_BVAL_SHIFT, + USB_CFIFOCTR_BVAL) == 0) + { + USB200.CFIFOCTR = USB_HOST_BITBVAL; /* Short Packet */ + } + } + else + { + g_usb0_host_data_count[pipe] -= count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_write_buffer_d0 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by CPU transfer using D0FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND ; Write end +* : USB_HOST_WRITESHRT ; short data +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_WRITEDMA ; Write DMA +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_write_buffer_d0 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_host_data_count[pipe] <= (uint32_t)size) + { + status = USB_HOST_WRITEEND; /* write continues */ + count = g_usb0_host_data_count[pipe]; + + if (count == 0) + { + status = USB_HOST_WRITESHRT; /* Null Packet is end of write */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ + } + } + else + { + status = USB_HOST_WRITING; /* write continues */ + count = (uint32_t)size; + } + + usb0_host_write_d0_fifo(pipe, (uint16_t)count); + + if (g_usb0_host_data_count[pipe] < (uint32_t)size) + { + g_usb0_host_data_count[pipe] = 0; + + if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL) == 0) + { + USB200.D0FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */ + } + } + else + { + g_usb0_host_data_count[pipe] -= count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_write_buffer_d1 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by CPU transfer using D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND ; Write end +* : USB_HOST_WRITESHRT ; short data +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_WRITEDMA ; Write DMA +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_write_buffer_d1 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_host_data_count[pipe] <= (uint32_t)size) + { + status = USB_HOST_WRITEEND; /* write continues */ + count = g_usb0_host_data_count[pipe]; + + if (count == 0) + { + status = USB_HOST_WRITESHRT; /* Null Packet is end of write */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ + } + } + else + { + status = USB_HOST_WRITING; /* write continues */ + count = (uint32_t)size; + } + + usb0_host_write_d1_fifo(pipe, (uint16_t)count); + + if (g_usb0_host_data_count[pipe] < (uint32_t)size) + { + g_usb0_host_data_count[pipe] = 0; + + if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL) == 0) + { + USB200.D1FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */ + } + } + else + { + g_usb0_host_data_count[pipe] -= count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_write_dma_d0 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by DMA transfer using D0FIFO. +* : The DMA-ch for using is specified by Userdef_USB_usb0_host_start_dma(). +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND : Write end +* : USB_HOST_WRITESHRT : short data +* : USB_HOST_WRITING : Continue of data write +* : USB_HOST_WRITEDMA : Write DMA +* : USB_HOST_FIFOERROR : FIFO status +*******************************************************************************/ +static uint16_t usb0_host_write_dma_d0 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t status; + uint16_t mbw; + uint16_t dfacc = 0; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + count = g_usb0_host_data_count[pipe]; + + if (count != 0) + { + g_usb0_host_DmaPipe[USB_HOST_D0FIFO] = pipe; + + if ((count % size) != 0) + { + g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 1; + } + else + { + g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 0; + } + + dfacc = usb0_host_set_dfacc_d0(mbw, count); + + if (mbw == USB_HOST_BITMBW_32) + { + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_HOST_BITMBW_16) + { + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */ + } + + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA; + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_BUF2FIFO; + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe]; + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].bytes = count; + + Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D0FIFO], dfacc); + + usb0_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc); + + RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, + 1, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); + + g_usb0_host_data_count[pipe] = 0; + g_usb0_host_data_pointer[pipe] += count; + + status = USB_HOST_WRITEDMA; /* DMA write */ + } + else + { + if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL) == 0) + { + RZA_IO_RegWrite_16(&USB200.D0FIFOCTR, + 1, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL); /* Short Packet */ + } + status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_write_dma_d1 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by DMA transfer using D1FIFO. +* : The DMA-ch for using is specified by Userdef_USB_usb0_host_start_dma(). +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND : Write end +* : USB_HOST_WRITESHRT : short data +* : USB_HOST_WRITING : Continue of data write +* : USB_HOST_WRITEDMA : Write DMA +* : USB_HOST_FIFOERROR : FIFO status +*******************************************************************************/ +static uint16_t usb0_host_write_dma_d1 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t status; + uint16_t mbw; + uint16_t dfacc = 0; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + count = g_usb0_host_data_count[pipe]; + + if (count != 0) + { + g_usb0_host_DmaPipe[USB_HOST_D1FIFO] = pipe; + + if ((count % size) != 0) + { + g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 1; + } + else + { + g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 0; + } + + dfacc = usb0_host_set_dfacc_d1(mbw, count); + + if (mbw == USB_HOST_BITMBW_32) + { + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_HOST_BITMBW_16) + { + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */ + } + + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA; + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_BUF2FIFO; + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe]; + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].bytes = count; + + Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D1FIFO], dfacc); + + usb0_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw, dfacc); + + RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, + 1, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); + + g_usb0_host_data_count[pipe] = 0; + g_usb0_host_data_pointer[pipe] += count; + + status = USB_HOST_WRITEDMA; /* DMA write */ + } + else + { + if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL) == 0) + { + RZA_IO_RegWrite_16(&USB200.D1FIFOCTR, + 1, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL); /* Short Packet */ + } + status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_start_receive_transfer +* Description : Starts USB data reception using the pipe specified in the argument. +* : The FIFO for using is set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +void usb0_host_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t usefifo; + + usb0_host_clear_bemp_sts(pipe); + usb0_host_clear_brdy_sts(pipe); + usb0_host_clear_nrdy_sts(pipe); + + usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + switch (usefifo) + { + case USB_HOST_D0FIFO_USE: + usb0_host_start_receive_trns_d0(pipe, size, data); + break; + + case USB_HOST_D1FIFO_USE: + usb0_host_start_receive_trns_d1(pipe, size, data); + break; + + case USB_HOST_D0FIFO_DMA: + usb0_host_start_receive_dma_d0(pipe, size, data); + break; + + case USB_HOST_D1FIFO_DMA: + usb0_host_start_receive_dma_d1(pipe, size, data); + break; + + default: + usb0_host_start_receive_trns_c(pipe, size, data); + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_start_receive_trns_c +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using CFIFO. +* : When storing data in the buffer allocated in the pipe specified in the +* : argument, BRDY interrupt is generated to read data +* : in the interrupt. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb0_host_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb0_host_set_pid_nak(pipe); + g_usb0_host_data_count[pipe] = size; + g_usb0_host_data_pointer[pipe] = (uint8_t *)data; + g_usb0_host_PipeIgnore[pipe] = 0; + + g_usb0_host_PipeDataSize[pipe] = size; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + mbw = usb0_host_get_mbw(size, (uint32_t)data); + usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_CFIFO_READ, mbw); + USB200.CFIFOCTR = USB_HOST_BITBCLR; + + usb0_host_set_transaction_counter(pipe, size); + +#if(1) /* ohci_wrapp */ +#else + usb0_host_aclrm(pipe); +#endif + + usb0_host_enable_nrdy_int(pipe); + usb0_host_enable_brdy_int(pipe); + + usb0_host_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb0_host_start_receive_trns_d0 +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using D0FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, BRDY interrupt is generated to read data in the +* : interrupt. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb0_host_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb0_host_set_pid_nak(pipe); + g_usb0_host_data_count[pipe] = size; + g_usb0_host_data_pointer[pipe] = (uint8_t *)data; + g_usb0_host_PipeIgnore[pipe] = 0; + + g_usb0_host_PipeDataSize[pipe] = size; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + mbw = usb0_host_get_mbw(size, (uint32_t)data); + usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw); + + usb0_host_set_transaction_counter(pipe, size); + +#if(1) /* ohci_wrapp */ +#else + usb0_host_aclrm(pipe); +#endif + + usb0_host_enable_nrdy_int(pipe); + usb0_host_enable_brdy_int(pipe); + + usb0_host_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb0_host_start_receive_trns_d1 +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using D1FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, BRDY interrupt is generated to read data. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb0_host_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb0_host_set_pid_nak(pipe); + g_usb0_host_data_count[pipe] = size; + g_usb0_host_data_pointer[pipe] = (uint8_t *)data; + g_usb0_host_PipeIgnore[pipe] = 0; + + g_usb0_host_PipeDataSize[pipe] = size; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + mbw = usb0_host_get_mbw(size, (uint32_t)data); + usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw); + + usb0_host_set_transaction_counter(pipe, size); + +#if(1) /* ohci_wrapp */ +#else + usb0_host_aclrm(pipe); +#endif + + usb0_host_enable_nrdy_int(pipe); + usb0_host_enable_brdy_int(pipe); + + usb0_host_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb0_host_start_receive_dma_d0 +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by DMA transfer using D0FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, delivered read request to DMAC to read data from +* : the buffer by DMAC. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb0_host_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb0_host_set_pid_nak(pipe); + g_usb0_host_data_count[pipe] = size; + g_usb0_host_data_pointer[pipe] = (uint8_t *)data; + g_usb0_host_PipeIgnore[pipe] = 0; + + g_usb0_host_PipeDataSize[pipe] = 0; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + mbw = usb0_host_get_mbw(size, (uint32_t)data); + usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw); + + usb0_host_set_transaction_counter(pipe, size); + +#if(1) /* ohci_wrapp */ +#else + usb0_host_aclrm(pipe); +#endif + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + usb0_host_read_dma(pipe); + + usb0_host_enable_nrdy_int(pipe); + usb0_host_enable_brdy_int(pipe); + } + else + { + usb0_host_enable_nrdy_int(pipe); + usb0_host_enable_brdy_int(pipe); + } + + usb0_host_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb0_host_start_receive_dma_d1 +* Description : Read data from the buffer allocated in the pipe specified in the argument. +* : Reads data by DMA transfer using D0FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, delivered read request to DMAC to read data from +* : the buffer by DMAC. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb0_host_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb0_host_set_pid_nak(pipe); + g_usb0_host_data_count[pipe] = size; + g_usb0_host_data_pointer[pipe] = (uint8_t *)data; + g_usb0_host_PipeIgnore[pipe] = 0; + + g_usb0_host_PipeDataSize[pipe] = 0; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + mbw = usb0_host_get_mbw(size, (uint32_t)data); + usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw); + + usb0_host_set_transaction_counter(pipe, size); + +#if(1) /* ohci_wrapp */ +#else + usb0_host_aclrm(pipe); +#endif + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + usb0_host_read_dma(pipe); + + usb0_host_enable_nrdy_int(pipe); + usb0_host_enable_brdy_int(pipe); + } + else + { + usb0_host_enable_nrdy_int(pipe); + usb0_host_enable_brdy_int(pipe); + } + + usb0_host_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb0_host_read_buffer +* Description : Reads data from the buffer allocated in the pipe specified +* : in the argument. +* : Uses FIF0 set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_read_buffer (uint16_t pipe) +{ + uint16_t status; + + g_usb0_host_PipeIgnore[pipe] = 0; + + if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE) + { + status = usb0_host_read_buffer_d0(pipe); + } + else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE) + { + status = usb0_host_read_buffer_d1(pipe); + } + else + { + status = usb0_host_read_buffer_c(pipe); + } + + switch (status) + { + case USB_HOST_READING: /* Continue of data read */ + break; + + case USB_HOST_READEND: /* End of data read */ + case USB_HOST_READSHRT: /* End of data read */ + usb0_host_disable_brdy_int(pipe); + g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe]; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + break; + + case USB_HOST_READOVER: /* buffer over */ + if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE) + { + USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE) + { + USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + else + { + USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ +#if(1) /* ohci_wrapp */ + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; +#else + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; +#endif + g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe]; + break; + + case USB_HOST_FIFOERROR: /* FIFO access status */ + default: + usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; + break; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_read_buffer_c +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using CFIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_read_buffer_c (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_HOST_READOVER; + usb0_host_set_pid_nak(pipe); /* Set NAK */ + count = g_usb0_host_data_count[pipe]; + } + else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_HOST_READEND; + usb0_host_set_pid_nak(pipe); /* Set NAK */ + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_HOST_READING; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + usb0_host_set_pid_nak(pipe); /* Set NAK */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + usb0_host_set_pid_nak(pipe); /* Set NAK */ + } + } + + if (count == 0) /* 0 length packet */ + { + USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + else + { + usb0_host_read_c_fifo(pipe, (uint16_t)count); + } + + g_usb0_host_data_count[pipe] -= count; + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_read_buffer_d0 +* Description : Reads data from the buffer allocated in the pipe specified in +* : the argument. +* : Reads data by CPU transfer using D0FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_read_buffer_d0 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t pipebuf_size; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_HOST_READOVER; + usb0_host_set_pid_nak(pipe); /* Set NAK */ + count = g_usb0_host_data_count[pipe]; + } + else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_HOST_READEND; + usb0_host_set_pid_nak(pipe); /* Set NAK */ + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_HOST_READING; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + usb0_host_set_pid_nak(pipe); /* Set NAK */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + usb0_host_set_pid_nak(pipe); /* Set NAK */ + } + else + { + pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + + if (count != pipebuf_size) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + usb0_host_set_pid_nak(pipe); /* Set NAK */ + } + } + } + + if (count == 0) /* 0 length packet */ + { + USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + else + { + usb0_host_read_d0_fifo(pipe, (uint16_t)count); + } + + g_usb0_host_data_count[pipe] -= count; + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_read_buffer_d1 +* Description : Reads data from the buffer allocated in the pipe specified +* : in the argument. +* : Reads data by CPU transfer using D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_read_buffer_d1 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t pipebuf_size; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_HOST_READOVER; + usb0_host_set_pid_nak(pipe); /* Set NAK */ + count = g_usb0_host_data_count[pipe]; + } + else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_HOST_READEND; + usb0_host_set_pid_nak(pipe); /* Set NAK */ + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) !=0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_HOST_READING; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + usb0_host_set_pid_nak(pipe); /* Set NAK */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + usb0_host_set_pid_nak(pipe); /* Set NAK */ + } + else + { + pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + if (count != pipebuf_size) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + usb0_host_set_pid_nak(pipe); /* Set NAK */ + } + } + } + + if (count == 0) /* 0 length packet */ + { + USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + else + { + usb0_host_read_d1_fifo(pipe, (uint16_t)count); + } + + g_usb0_host_data_count[pipe] -= count; + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_read_dma +* Description : Reads data from the buffer allocated in the pipe specified +* : in the argument. +* : Reads data by DMA transfer using D0FIFO or D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READZERO ; zero data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_read_dma (uint16_t pipe) +{ + uint16_t status; + + g_usb0_host_PipeIgnore[pipe] = 0; + + if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA) + { + status = usb0_host_read_dma_d0(pipe); + } + else + { + status = usb0_host_read_dma_d1(pipe); + } + + switch (status) + { + case USB_HOST_READING: /* Continue of data read */ + break; + + case USB_HOST_READZERO: /* End of data read */ + usb0_host_disable_brdy_int(pipe); + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + break; + + case USB_HOST_READEND: /* End of data read */ + case USB_HOST_READSHRT: /* End of data read */ + usb0_host_disable_brdy_int(pipe); + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe]; + } + break; + + case USB_HOST_READOVER: /* buffer over */ + usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe]; + } +#if(1) /* ohci_wrapp */ + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; +#else + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; +#endif + break; + + case USB_HOST_FIFOERROR: /* FIFO access status */ + default: + usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; + break; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_read_dma_d0 +* Description : Writes data in the buffer allocated in the pipe specified +* : in the argument. +* : Reads data by DMA transfer using D0FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READZERO ; zero data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +static uint16_t usb0_host_read_dma_d0 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t dfacc = 0; + uint16_t pipebuf_size; + + g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + count = g_usb0_host_data_count[pipe]; + status = USB_HOST_READING; + } + else + { + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_HOST_READOVER; + count = g_usb0_host_data_count[pipe]; + } + else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_HOST_READEND; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_HOST_READING; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + else + { + pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + + if (count != pipebuf_size) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + } + } + + if (count == 0) /* 0 length packet */ + { + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear B_CLR */ + status = USB_HOST_READZERO; /* Null Packet receive */ + } + else + { + usb0_host_set_curpipe(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw); + /* transaction counter No set */ + /* FRDY = 1, DTLN = 0 -> BRDY */ + } + } + else + { + dfacc = usb0_host_set_dfacc_d0(mbw, count); + + if (mbw == USB_HOST_BITMBW_32) + { + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_HOST_BITMBW_16) + { + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */ + } + + g_usb0_host_DmaPipe[USB_HOST_D0FIFO] = pipe; /* not use in read operation */ + g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 0; /* not use in read operation */ + + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA; + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_FIFO2BUF; + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe]; + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].bytes = count; + + if (status == USB_HOST_READING) + { + g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSY; + } + else + { + g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSYEND; + } + + Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D0FIFO], dfacc); + + usb0_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc); + + RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, + 1, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + g_usb0_host_data_count[pipe] -= count; + g_usb0_host_data_pointer[pipe] += count; + g_usb0_host_PipeDataSize[pipe] += count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_read_dma_d1 +* Description : Reads data from the buffer allocated in the pipe specified in +* : the argument. +* : Reads data by DMA transfer using D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READZERO ; zero data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +static uint16_t usb0_host_read_dma_d1 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t dfacc = 0; + uint16_t pipebuf_size; + + g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + count = g_usb0_host_data_count[pipe]; + status = USB_HOST_READING; + } + else + { + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_HOST_READOVER; + count = g_usb0_host_data_count[pipe]; + } + else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_HOST_READEND; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_HOST_READING; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + else + { + pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + + if (count != pipebuf_size) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + } + } + + if (count == 0) /* 0 length packet */ + { + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + status = USB_HOST_READZERO; /* Null Packet receive */ + } + else + { + usb0_host_set_curpipe(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw); + /* transaction counter No set */ + /* FRDY = 1, DTLN = 0 -> BRDY */ + } + } + else + { + dfacc = usb0_host_set_dfacc_d1(mbw, count); + + if (mbw == USB_HOST_BITMBW_32) + { + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_HOST_BITMBW_16) + { + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */ + } + + g_usb0_host_DmaPipe[USB_HOST_D1FIFO] = pipe; /* not use in read operation */ + g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 0; /* not use in read operation */ + + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA; + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_FIFO2BUF; + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe]; + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].bytes = count; + + if (status == USB_HOST_READING) + { + g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSY; + } + else + { + g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSYEND; + } + + Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D1FIFO], dfacc); + + usb0_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw, dfacc); + + RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, + 1, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + g_usb0_host_data_count[pipe] -= count; + g_usb0_host_data_pointer[pipe] += count; + g_usb0_host_PipeDataSize[pipe] += count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_change_fifo_port +* Description : Allocates FIF0 specified by the argument in the pipe assigned +* : by the argument. After allocating FIF0, waits in the software +* : till the corresponding pipe becomes ready. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t fifosel ; Select FIFO +* : uint16_t isel ; FIFO Access Direction +* : uint16_t mbw ; FIFO Port Access Bit Width +* Return Value : USB_HOST_FIFOERROR ; Error +* : Others ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value +*******************************************************************************/ +uint16_t usb0_host_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw) +{ + uint16_t buffer; + uint32_t loop; + volatile uint32_t loop2; + + usb0_host_set_curpipe(pipe, fifosel, isel, mbw); + + for (loop = 0; loop < 4; loop++) + { + switch (fifosel) + { + case USB_HOST_CUSE: + buffer = USB200.CFIFOCTR; + break; + + case USB_HOST_D0USE: + case USB_HOST_D0DMA: + buffer = USB200.D0FIFOCTR; + break; + + case USB_HOST_D1USE: + case USB_HOST_D1DMA: + buffer = USB200.D1FIFOCTR; + break; + + default: + buffer = 0; + break; + } + + if ((buffer & USB_HOST_BITFRDY) == USB_HOST_BITFRDY) + { + return buffer; + } + + loop2 = 25; + + while (loop2-- > 0) + { + /* wait */ + } + } + + return USB_HOST_FIFOERROR; +} + +/******************************************************************************* +* Function Name: usb0_host_set_curpipe +* Description : Allocates FIF0 specified by the argument in the pipe assigned +* : by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t fifosel ; Select FIFO +* : uint16_t isel ; FIFO Access Direction +* : uint16_t mbw ; FIFO Port Access Bit Width +* Return Value : none +*******************************************************************************/ +void usb0_host_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw) +{ + uint16_t buffer; + uint32_t loop; + volatile uint32_t loop2; + + g_usb0_host_mbw[pipe] = mbw; + + switch (fifosel) + { + case USB_HOST_CUSE: + buffer = USB200.CFIFOSEL; + buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE); + buffer |= (uint16_t)(~isel & USB_HOST_BITISEL); + USB200.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)) + == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + + buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(isel | pipe | mbw); + USB200.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)) + == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_HOST_D0DMA: + case USB_HOST_D0USE: + buffer = USB200.D0FIFOSEL; + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); + USB200.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB200.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_HOST_D1DMA: + case USB_HOST_D1USE: + buffer = USB200.D1FIFOSEL; + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); + USB200.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB200.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + default: + break; + } + + /* Cautions !!! + * Depending on the external bus speed of CPU, you may need to wait for 450ns here. + * For details, please look at the data sheet. */ + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } +} + +/******************************************************************************* +* Function Name: usb0_host_set_curpipe2 +* Description : Allocates FIF0 specified by the argument in the pipe assigned +* : by the argument.(DFACC) +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t fifosel ; Select FIFO +* : uint16_t isel ; FIFO Access Direction +* : uint16_t mbw ; FIFO Port Access Bit Width +* : uint16_t dfacc ; DFACC Access mode +* Return Value : none +*******************************************************************************/ +void usb0_host_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc) +{ + uint16_t buffer; + uint32_t loop; +#ifdef __USB_HOST_DF_ACC_ENABLE__ + uint32_t dummy; +#endif + volatile uint32_t loop2; + + g_usb0_host_mbw[pipe] = mbw; + + switch (fifosel) + { + case USB_HOST_CUSE: + buffer = USB200.CFIFOSEL; + buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE); + buffer |= (uint16_t)(~isel & USB_HOST_BITISEL); + USB200.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)) + == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + + buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(isel | pipe | mbw); + USB200.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)) + == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_HOST_D0DMA: + case USB_HOST_D0USE: + buffer = USB200.D0FIFOSEL; +#ifdef __USB_HOST_DF_ACC_ENABLE__ + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + + if (dfacc != 0) + { + buffer |= (uint16_t)(USB_HOST_BITMBW_32); + } +#else + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); +#endif + USB200.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + +#ifdef __USB_HOST_DF_ACC_ENABLE__ + if (dfacc != 0) + { + dummy = USB200.D0FIFO.UINT32; + } +#endif + + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB200.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_HOST_D1DMA: + case USB_HOST_D1USE: + buffer = USB200.D1FIFOSEL; +#ifdef __USB_HOST_DF_ACC_ENABLE__ + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + + if (dfacc != 0) + { + buffer |= (uint16_t)(USB_HOST_BITMBW_32); + } +#else + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); +#endif + USB200.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + +#ifdef __USB_HOST_DF_ACC_ENABLE__ + if (dfacc != 0) + { + dummy = USB200.D1FIFO.UINT32; + loop = dummy; // avoid warning. + } +#endif + + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB200.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + default: + break; + } + + /* Cautions !!! + * Depending on the external bus speed of CPU, you may need to wait for 450ns here. + * For details, please look at the data sheet. */ + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } +} + +/******************************************************************************* +* Function Name: usb0_host_write_c_fifo +* Description : Writes data in CFIFO. +* : Writes data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating CFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb1_host_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_host_write_c_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + USB200.CFIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe]; + g_usb0_host_data_pointer[pipe] += 1; + } + } + else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)(count / 2); even; --even) + { + USB200.CFIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]); + g_usb0_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)(count / 4); even; --even) + { + USB200.CFIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]); + g_usb0_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_read_c_fifo +* Description : Reads data from CFIFO. +* : Reads data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating CFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb0_host_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_host_read_c_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + *g_usb0_host_data_pointer[pipe] = USB200.CFIFO.UINT8[HH]; + g_usb0_host_data_pointer[pipe] += 1; + } + } + else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)((count + 1) / 2); even; --even) + { + *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.CFIFO.UINT16[H]; + g_usb0_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)((count + 3) / 4); even; --even) + { + *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.CFIFO.UINT32; + g_usb0_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_write_d0_fifo +* Description : Writes data in D0FIFO. +* : Writes data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating CFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb0_host_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_host_write_d0_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + USB200.D0FIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe]; + g_usb0_host_data_pointer[pipe] += 1; + } + } + else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)(count / 2); even; --even) + { + USB200.D0FIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]); + g_usb0_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)(count / 4); even; --even) + { + USB200.D0FIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]); + g_usb0_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_read_d0_fifo +* Description : Reads data from D0FIFO. +* : Reads data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating DOFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb0_host_mbw[]. +* Arguments : uint16_t Pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_host_read_d0_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + *g_usb0_host_data_pointer[pipe] = USB200.D0FIFO.UINT8[HH]; + g_usb0_host_data_pointer[pipe] += 1; + } + } + else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)((count + 1) / 2); even; --even) + { + *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.D0FIFO.UINT16[H]; + g_usb0_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)((count + 3) / 4); even; --even) + { + *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.D0FIFO.UINT32; + g_usb0_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_write_d1_fifo +* Description : Writes data in D1FIFO. +* : Writes data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating D1FIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb1_host_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_host_write_d1_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + USB200.D1FIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe]; + g_usb0_host_data_pointer[pipe] += 1; + } + } + else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)(count / 2); even; --even) + { + USB200.D1FIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]); + g_usb0_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)(count / 4); even; --even) + { + USB200.D1FIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]); + g_usb0_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_read_d1_fifo +* Description : Reads data from D1FIFO. +* : Reads data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating D1FIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb1_host_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_host_read_d1_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + *g_usb0_host_data_pointer[pipe] = USB200.D1FIFO.UINT8[HH]; + g_usb0_host_data_pointer[pipe] += 1; + } + } + else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)((count + 1) / 2); even; --even) + { + *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.D1FIFO.UINT16[H]; + g_usb0_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)((count + 3) / 4); even; --even) + { + *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.D1FIFO.UINT32; + g_usb0_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_com_get_dmasize +* Description : Calculates access width of DMA transfer by the argument to + return as the Return Value. +* Arguments : uint32_t trncount : transfer byte +* : uint32_t dtptr : transfer data pointer +* Return Value : DMA transfer size : 0 8bit +* : : 1 16bit +* : : 2 32bit +*******************************************************************************/ +static uint32_t usb0_host_com_get_dmasize (uint32_t trncount, uint32_t dtptr) +{ + uint32_t size; + + if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0)) + { + /* When transfer byte count is odd */ + /* or transfer data area is 8-bit alignment */ + size = 0; /* 8bit */ + } + else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0)) + { + /* When the transfer byte count is multiples of 2 */ + /* or the transfer data area is 16-bit alignment */ + size = 1; /* 16bit */ + } + else + { + /* When the transfer byte count is multiples of 4 */ + /* or the transfer data area is 32-bit alignment */ + size = 2; /* 32bit */ + } + + return size; +} + +/******************************************************************************* +* Function Name: usb0_host_get_mbw +* Description : Calculates access width of DMA to return the value set in MBW. +* Arguments : uint32_t trncount : transfer byte +* : uint32_t dtptr : transfer data pointer +* Return Value : FIFO transfer size : USB_HOST_BITMBW_8 8bit +* : : USB_HOST_BITMBW_16 16bit +* : : USB_HOST_BITMBW_32 32bit +*******************************************************************************/ +uint16_t usb0_host_get_mbw (uint32_t trncount, uint32_t dtptr) +{ + uint32_t size; + uint16_t mbw; + + size = usb0_host_com_get_dmasize(trncount, dtptr); + + if (size == 0) + { + /* 8bit */ + mbw = USB_HOST_BITMBW_8; + } + else if (size == 1) + { + /* 16bit */ + mbw = USB_HOST_BITMBW_16; + } + else + { + /* 32bit */ + mbw = USB_HOST_BITMBW_32; + } + + return mbw; +} + +/******************************************************************************* +* Function Name: usb0_host_set_transaction_counter +* Description : Sets transaction counter by the argument(PIPEnTRN). +* : Clears transaction before setting to enable transaction counter setting. +* Arguments : uint16_t pipe ; Pipe number +* : uint32_t bsize : Data transfer size +* Return Value : none +*******************************************************************************/ +static void usb0_host_set_transaction_counter (uint16_t pipe, uint32_t bsize) +{ + uint16_t mxps; + uint16_t cnt; + + if (bsize == 0) + { + return; + } + + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if ((bsize % mxps) == 0) + { + cnt = (uint16_t)(bsize / mxps); + } + else + { + cnt = (uint16_t)((bsize / mxps) + 1); + } + + switch (pipe) + { + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE1TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE1TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE2TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE2TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE3TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE3TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE4TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE4TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE5TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE5TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE9TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE9TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_clear_transaction_counter +* Description : Clears the transaction counter by the argument. +* : After executing this function, the transaction counter is invalid. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb0_host_clear_transaction_counter (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE1TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE2TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE3TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE4TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE5TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE9TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_stop_transfer +* Description : Stops the USB transfer in the pipe specified by the argument. +* : After stopping the USB transfer, clears the buffer allocated in +* : the pipe. +* : After executing this function, allocation in FIF0 becomes USB_HOST_PIPE0; +* : invalid. After executing this function, BRDY/NRDY/BEMP interrupt +* : in the corresponding pipe becomes invalid. Sequence bit is also +* : cleared. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_stop_transfer (uint16_t pipe) +{ + uint16_t usefifo; + uint32_t remain; + + usb0_host_set_pid_nak(pipe); + + usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + switch (usefifo) + { + case USB_HOST_D0FIFO_USE: + usb0_host_clear_transaction_counter(pipe); + USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + break; + + case USB_HOST_D1FIFO_USE: + usb0_host_clear_transaction_counter(pipe); + USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + break; + + case USB_HOST_D0FIFO_DMA: + remain = Userdef_USB_usb0_host_stop_dma0(); + usb0_host_dma_stop_d0(pipe, remain); + usb0_host_clear_transaction_counter(pipe); + USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + break; + + case USB_HOST_D1FIFO_DMA: + remain = Userdef_USB_usb0_host_stop_dma1(); + usb0_host_dma_stop_d1(pipe, remain); + usb0_host_clear_transaction_counter(pipe); + USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + break; + + default: + usb0_host_clear_transaction_counter(pipe); + USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + break; + } + + /* Interrupt of pipe set is disabled */ + usb0_host_disable_brdy_int(pipe); + usb0_host_disable_nrdy_int(pipe); + usb0_host_disable_bemp_int(pipe); + +#if(1) /* ohci_wrapp */ +#else + usb0_host_aclrm(pipe); +#endif + usb0_host_set_csclr(pipe); +} + +/******************************************************************************* +* Function Name: usb0_host_set_dfacc_d0 +* Description : Sets the DFACC setting value in D0FIFO using the transfer size. +* Arguments : uint16_t mbw ; MBW +* : uint16_t count ; data count +* Return Value : DFACC Access mode +*******************************************************************************/ +static uint16_t usb0_host_set_dfacc_d0 (uint16_t mbw, uint32_t count) +{ + uint16_t dfacc = 0; + +#ifndef __USB_HOST_DF_ACC_ENABLE__ + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; +#else + if (mbw == USB_HOST_BITMBW_32) + { + if ((count % 32) == 0) + { + /* 32byte transfer */ + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 2, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 2; + } + else if ((count % 16) == 0) + { + /* 16byte transfer */ + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 1, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 1; + } + else + { + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + } + else if (mbw == USB_HOST_BITMBW_16) + { + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + else + { + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } +#endif + + return dfacc; +} + +/******************************************************************************* +* Function Name: usb0_host_set_dfacc_d1 +* Description : Sets the DFACC setting value in D1FIFO using the transfer size. +* Arguments : uint16_t mbw ; MBW +* : uint16_t count ; data count +* Return Value : DFACC Access mode +*******************************************************************************/ +static uint16_t usb0_host_set_dfacc_d1 (uint16_t mbw, uint32_t count) +{ + uint16_t dfacc = 0; + +#ifndef __USB_HOST_DF_ACC_ENABLE__ + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; +#else + if (mbw == USB_HOST_BITMBW_32) + { + if ((count % 32) == 0) + { + /* 32byte transfer */ + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 2, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 2; + } + else if ((count % 16) == 0) + { + /* 16byte transfer */ + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 1, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 1; + } + else + { + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + } + else if (mbw == USB_HOST_BITMBW_16) + { + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + else + { + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } +#endif + + return dfacc; +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dma.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dma.c new file mode 100644 index 0000000000..57e6e5a084 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dma.c @@ -0,0 +1,355 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_dma.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" +/* #include "usb0_host_dmacdrv.h" */ + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +static void usb0_host_dmaint(uint16_t fifo); +static void usb0_host_dmaint_buf2fifo(uint16_t pipe); +static void usb0_host_dmaint_fifo2buf(uint16_t pipe); + + +/******************************************************************************* +* Function Name: usb0_host_dma_stop_d0 +* Description : D0FIFO DMA stop +* Arguments : uint16_t pipe : pipe number +* : uint32_t remain : transfer byte +* Return Value : none +*******************************************************************************/ +void usb0_host_dma_stop_d0 (uint16_t pipe, uint32_t remain) +{ + uint16_t dtln; + uint16_t dfacc; + uint16_t buffer; + uint16_t sds_b = 1; + + dfacc = RZA_IO_RegRead_16(&USB200.D0FBCFG, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + if (dfacc == 2) + { + sds_b = 32; + } + else if (dfacc == 1) + { + sds_b = 16; + } + else + { + if (g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size == 2) + { + sds_b = 4; + } + else if (g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size == 1) + { + sds_b = 2; + } + else + { + sds_b = 1; + } + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE) + { + buffer = USB200.D0FIFOCTR; + dtln = (buffer & USB_HOST_BITDTLN); + + if ((dtln % sds_b) != 0) + { + remain += (sds_b - (dtln % sds_b)); + } + g_usb0_host_PipeDataSize[pipe] = (g_usb0_host_data_count[pipe] - remain); + g_usb0_host_data_count[pipe] = remain; + } + } + + RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, + 0, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); +} + +/******************************************************************************* +* Function Name: usb0_host_dma_stop_d1 +* Description : D1FIFO DMA stop +* Arguments : uint16_t pipe : pipe number +* : uint32_t remain : transfer byte +* Return Value : none +*******************************************************************************/ +void usb0_host_dma_stop_d1 (uint16_t pipe, uint32_t remain) +{ + uint16_t dtln; + uint16_t dfacc; + uint16_t buffer; + uint16_t sds_b = 1; + + dfacc = RZA_IO_RegRead_16(&USB200.D1FBCFG, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + if (dfacc == 2) + { + sds_b = 32; + } + else if (dfacc == 1) + { + sds_b = 16; + } + else + { + if (g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size == 2) + { + sds_b = 4; + } + else if (g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size == 1) + { + sds_b = 2; + } + else + { + sds_b = 1; + } + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE) + { + buffer = USB200.D1FIFOCTR; + dtln = (buffer & USB_HOST_BITDTLN); + + if ((dtln % sds_b) != 0) + { + remain += (sds_b - (dtln % sds_b)); + } + g_usb0_host_PipeDataSize[pipe] = (g_usb0_host_data_count[pipe] - remain); + g_usb0_host_data_count[pipe] = remain; + } + } + + RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, + 0, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); +} + +/******************************************************************************* +* Function Name: usb0_host_dma_interrupt_d0fifo +* Description : This function is DMA interrupt handler entry. +* : Execute usb1_host_dmaint() after disabling DMA interrupt in this function. +* : Disable DMA interrupt to DMAC executed when USB_HOST_D0FIFO_DMA is +* : specified by dma->fifo. +* : Register this function as DMA complete interrupt. +* Arguments : uint32_t int_sense ; Interrupts detection mode +* : ; INTC_LEVEL_SENSITIVE : Level sense +* : ; INTC_EDGE_TRIGGER : Edge trigger +* Return Value : none +*******************************************************************************/ +void usb0_host_dma_interrupt_d0fifo (uint32_t int_sense) +{ + usb0_host_dmaint(USB_HOST_D0FIFO); + g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY; +} + +/******************************************************************************* +* Function Name: usb0_host_dma_interrupt_d1fifo +* Description : This function is DMA interrupt handler entry. +* : Execute usb0_host_dmaint() after disabling DMA interrupt in this function. +* : Disable DMA interrupt to DMAC executed when USB_HOST_D1FIFO_DMA is +* : specified by dma->fifo. +* : Register this function as DMA complete interrupt. +* Arguments : uint32_t int_sense ; Interrupts detection mode +* : ; INTC_LEVEL_SENSITIVE : Level sense +* : ; INTC_EDGE_TRIGGER : Edge trigger +* Return Value : none +*******************************************************************************/ +void usb0_host_dma_interrupt_d1fifo (uint32_t int_sense) +{ + usb0_host_dmaint(USB_HOST_D1FIFO); + g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY; +} + +/******************************************************************************* +* Function Name: usb0_host_dmaint +* Description : This function is DMA transfer end interrupt +* Arguments : uint16_t fifo ; fifo number +* : ; USB_HOST_D0FIFO +* : ; USB_HOST_D1FIFO +* Return Value : none +*******************************************************************************/ +static void usb0_host_dmaint (uint16_t fifo) +{ + uint16_t pipe; + + pipe = g_usb0_host_DmaPipe[fifo]; + + if (g_usb0_host_DmaInfo[fifo].dir == USB_HOST_BUF2FIFO) + { + usb0_host_dmaint_buf2fifo(pipe); + } + else + { + usb0_host_dmaint_fifo2buf(pipe); + } +} + +/******************************************************************************* +* Function Name: usb0_host_dmaint_fifo2buf +* Description : Executes read completion from FIFO by DMAC. +* Arguments : uint16_t pipe : pipe number +* Return Value : none +*******************************************************************************/ +static void usb0_host_dmaint_fifo2buf (uint16_t pipe) +{ + uint32_t remain; + uint16_t useport; + + if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE) + { + useport = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + if (useport == USB_HOST_D0FIFO_DMA) + { + remain = Userdef_USB_usb0_host_stop_dma0(); + usb0_host_dma_stop_d0(pipe, remain); + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + if (g_usb0_host_DmaStatus[USB_HOST_D0FIFO] == USB_HOST_DMA_BUSYEND) + { + USB200.D0FIFOCTR = USB_HOST_BITBCLR; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + } + else + { + usb0_host_enable_brdy_int(pipe); + } + } + } + else + { + remain = Userdef_USB_usb0_host_stop_dma1(); + usb0_host_dma_stop_d1(pipe, remain); + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + if (g_usb0_host_DmaStatus[USB_HOST_D1FIFO] == USB_HOST_DMA_BUSYEND) + { + USB200.D1FIFOCTR = USB_HOST_BITBCLR; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + } + else + { + usb0_host_enable_brdy_int(pipe); + } + } + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_dmaint_buf2fifo +* Description : Executes write completion in FIFO by DMAC. +* Arguments : uint16_t pipe : pipe number +* Return Value : none +*******************************************************************************/ +static void usb0_host_dmaint_buf2fifo (uint16_t pipe) +{ + uint16_t useport; + uint32_t remain; + + useport = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + if (useport == USB_HOST_D0FIFO_DMA) + { + remain = Userdef_USB_usb0_host_stop_dma0(); + usb0_host_dma_stop_d0(pipe, remain); + + if (g_usb0_host_DmaBval[USB_HOST_D0FIFO] != 0) + { + RZA_IO_RegWrite_16(&USB200.D0FIFOCTR, + 1, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL); + } + } + else + { + remain = Userdef_USB_usb0_host_stop_dma1(); + usb0_host_dma_stop_d1(pipe, remain); + + if (g_usb0_host_DmaBval[USB_HOST_D1FIFO] != 0) + { + RZA_IO_RegWrite_16(&USB200.D1FIFOCTR, + 1, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL); + } + } + + usb0_host_enable_bemp_int(pipe); +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_intrn.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_intrn.c new file mode 100644 index 0000000000..968a513526 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_intrn.c @@ -0,0 +1,285 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_intrn.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" +#if(1) /* ohci_wrapp */ +#include "ohci_wrapp_RZ_A1_local.h" +#endif + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_host_brdy_int +* Description : Executes BRDY interrupt(USB_HOST_PIPE1-9). +* : According to the pipe that interrupt is generated in, +* : reads/writes buffer allocated in the pipe. +* : This function is executed in the BRDY interrupt handler. +* : This function clears BRDY interrupt status and BEMP interrupt +* : status. +* Arguments : uint16_t status ; BRDYSTS Register Value +* : uint16_t int_enb ; BRDYENB Register Value +* Return Value : none +*******************************************************************************/ +void usb0_host_brdy_int (uint16_t status, uint16_t int_enb) +{ + uint32_t int_sense = 0; + uint16_t pipe; + uint16_t pipebit; + + for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++) + { + pipebit = g_usb0_host_bit_set[pipe]; + + if ((status & pipebit) && (int_enb & pipebit)) + { + USB200.BRDYSTS = (uint16_t)~pipebit; + USB200.BEMPSTS = (uint16_t)~pipebit; + + if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA) + { + if (g_usb0_host_DmaStatus[USB_HOST_D0FIFO] != USB_HOST_DMA_READY) + { + usb0_host_dma_interrupt_d0fifo(int_sense); + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + usb0_host_read_dma(pipe); + usb0_host_disable_brdy_int(pipe); + } + else + { + USB200.D0FIFOCTR = USB_HOST_BITBCLR; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + } + } + else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_DMA) + { + if (g_usb0_host_DmaStatus[USB_HOST_D1FIFO] != USB_HOST_DMA_READY) + { + usb0_host_dma_interrupt_d1fifo(int_sense); + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + usb0_host_read_dma(pipe); + usb0_host_disable_brdy_int(pipe); + } + else + { + USB200.D1FIFOCTR = USB_HOST_BITBCLR; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + } + } + else + { + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) + { + usb0_host_read_buffer(pipe); + } + else + { + usb0_host_write_buffer(pipe); + } + } +#if(1) /* ohci_wrapp */ + switch (g_usb0_host_pipe_status[pipe]) + { + case USB_HOST_PIPE_DONE: + ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR); + break; + case USB_HOST_PIPE_NORES: + case USB_HOST_PIPE_STALL: + case USB_HOST_PIPE_ERROR: + ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL); + break; + default: + /* Do Nothing */ + break; + } +#endif + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_nrdy_int +* Description : Executes NRDY interrupt(USB_HOST_PIPE1-9). +* : Checks NRDY interrupt cause by PID. When the cause if STALL, +* : regards the pipe state as STALL and ends the processing. +* : Then the cause is not STALL, increments the error count to +* : communicate again. When the error count is 3, determines +* : the pipe state as USB_HOST_PIPE_NORES and ends the processing. +* : This function is executed in the NRDY interrupt handler. +* : This function clears NRDY interrupt status. +* Arguments : uint16_t status ; NRDYSTS Register Value +* : uint16_t int_enb ; NRDYENB Register Value +* Return Value : none +*******************************************************************************/ +void usb0_host_nrdy_int (uint16_t status, uint16_t int_enb) +{ + uint16_t pid; + uint16_t pipe; + uint16_t bitcheck; + + bitcheck = (uint16_t)(status & int_enb); + + USB200.NRDYSTS = (uint16_t)~status; + + for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++) + { + if ((bitcheck&g_usb0_host_bit_set[pipe]) == g_usb0_host_bit_set[pipe]) + { + if (RZA_IO_RegRead_16(&USB200.SYSCFG0, + USB_SYSCFG_DCFM_SHIFT, + USB_SYSCFG_DCFM) == 1) + { + if (g_usb0_host_pipe_status[pipe] == USB_HOST_PIPE_WAIT) + { + pid = usb0_host_get_pid(pipe); + + if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2)) + { + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_STALL; +#if(1) /* ohci_wrapp */ + ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL); +#endif + } + else + { +#if(1) /* ohci_wrapp */ + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_NORES; + ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL); +#else + g_usb0_host_PipeIgnore[pipe]++; + + if (g_usb0_host_PipeIgnore[pipe] == 3) + { + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_NORES; + } + else + { + usb0_host_set_pid_buf(pipe); + } +#endif + } + } + } + else + { + /* USB Function */ + } + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_bemp_int +* Description : Executes BEMP interrupt(USB_HOST_PIPE1-9). +* Arguments : uint16_t status ; BEMPSTS Register Value +* : uint16_t int_enb ; BEMPENB Register Value +* Return Value : none +*******************************************************************************/ +void usb0_host_bemp_int (uint16_t status, uint16_t int_enb) +{ + uint16_t pid; + uint16_t pipe; + uint16_t bitcheck; + uint16_t inbuf; + + bitcheck = (uint16_t)(status & int_enb); + + USB200.BEMPSTS = (uint16_t)~status; + + for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++) + { + if ((bitcheck&g_usb0_host_bit_set[pipe]) == g_usb0_host_bit_set[pipe]) + { + pid = usb0_host_get_pid(pipe); + + if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2)) + { + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_STALL; +#if(1) /* ohci_wrapp */ + ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL); +#endif + } + else + { + inbuf = usb0_host_get_inbuf(pipe); + + if (inbuf == 0) + { + usb0_host_disable_bemp_int(pipe); + usb0_host_set_pid_nak(pipe); + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; +#if(1) /* ohci_wrapp */ + ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR); +#endif + } + } + } + } +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_lib.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_lib.c new file mode 100644 index 0000000000..eb3359e286 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_lib.c @@ -0,0 +1,1580 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_lib.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" +#if(1) /* ohci_wrapp */ +#include "MBRZA1H.h" /* INTC Driver Header */ +#else +#include "devdrv_intc.h" /* INTC Driver Header */ +#endif + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_host_enable_brdy_int +* Description : Enables BRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling +* : BRDY. Enables BRDY interrupt in the pipe specified by the argument +* : in the disabled status. After enabling BRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_enable_brdy_int (uint16_t pipe) +{ + /* enable brdy interrupt */ + USB200.BRDYENB |= (uint16_t)g_usb0_host_bit_set[pipe]; +} + +/******************************************************************************* +* Function Name: usb0_host_disable_brdy_int +* Description : Disables BRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling +* : BRDY. Enables BRDY interrupt in the pipe specified by the argument +* : in the disabled status. After disabling BRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_disable_brdy_int (uint16_t pipe) +{ + /* disable brdy interrupt */ + USB200.BRDYENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_host_clear_brdy_sts +* Description : Clear BRDY interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_clear_brdy_sts (uint16_t pipe) +{ + /* clear brdy status */ + USB200.BRDYSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_host_enable_bemp_int +* Description : Enables BEMP interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling +* : BEMP. Enables BEMP interrupt in the pipe specified by the argument +* : in the disabled status. After enabling BEMP, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_enable_bemp_int (uint16_t pipe) +{ + /* enable bemp interrupt */ + USB200.BEMPENB |= (uint16_t)g_usb0_host_bit_set[pipe]; +} + +/******************************************************************************* +* Function Name: usb0_host_disable_bemp_int +* Description : Disables BEMP interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling +* : BEMP. Enables BEMP interrupt in the pipe specified by the argument +* : in the disabled status. After enabling BEMP, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_disable_bemp_int (uint16_t pipe) +{ + /* disable bemp interrupt */ + USB200.BEMPENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_host_clear_bemp_sts +* Description : Clear BEMP interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_clear_bemp_sts (uint16_t pipe) +{ + /* clear bemp status */ + USB200.BEMPSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_host_enable_nrdy_int +* Description : Enables NRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling +* : NRDY. Enables NRDY interrupt in the pipe specified by the argument +* : in the disabled status. After enabling NRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_enable_nrdy_int (uint16_t pipe) +{ + /* enable nrdy interrupt */ + USB200.NRDYENB |= (uint16_t)g_usb0_host_bit_set[pipe]; +} + +/******************************************************************************* +* Function Name: usb0_host_disable_nrdy_int +* Description : Disables NRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling +* : NRDY. Disables NRDY interrupt in the pipe specified by the argument +* : in the disabled status. After disabling NRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_disable_nrdy_int (uint16_t pipe) +{ + /* disable nrdy interrupt */ + USB200.NRDYENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_host_clear_nrdy_sts +* Description : Clear NRDY interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_clear_nrdy_sts (uint16_t pipe) +{ + /* clear nrdy status */ + USB200.NRDYSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_host_is_hispeed +* Description : Returns the result of USB reset hand shake (RHST) as +* : return value. +* Arguments : none +* Return Value : USB_HOST_HIGH_SPEED ; Hi-Speed +* : USB_HOST_FULL_SPEED ; Full-Speed +* : USB_HOST_LOW_SPEED ; Low-Speed +* : USB_HOST_NON_SPEED ; error +*******************************************************************************/ +uint16_t usb0_host_is_hispeed (void) +{ + uint16_t rhst; + uint16_t speed; + + rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0, + USB_DVSTCTR0_RHST_SHIFT, + USB_DVSTCTR0_RHST); + if (rhst == USB_HOST_HSMODE) + { + speed = USB_HOST_HIGH_SPEED; + } + else if (rhst == USB_HOST_FSMODE) + { + speed = USB_HOST_FULL_SPEED; + } + else if (rhst == USB_HOST_LSMODE) + { + speed = USB_HOST_LOW_SPEED; + } + else + { + speed = USB_HOST_NON_SPEED; + } + + return speed; +} + +/******************************************************************************* +* Function Name: usb0_host_is_hispeed_enable +* Description : Returns the USB High-Speed connection enabled status as +* : return value. +* Arguments : none +* Return Value : USB_HOST_YES : Hi-Speed Enable +* : USB_HOST_NO : Hi-Speed Disable +*******************************************************************************/ +uint16_t usb0_host_is_hispeed_enable (void) +{ + uint16_t ret; + + ret = USB_HOST_NO; + + if (RZA_IO_RegRead_16(&USB200.SYSCFG0, + USB_SYSCFG_HSE_SHIFT, + USB_SYSCFG_HSE) == 1) + { + ret = USB_HOST_YES; + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_host_set_pid_buf +* Description : Enables communicaqtion in the pipe specified by the argument +* : (BUF). +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_set_pid_buf (uint16_t pipe) +{ + uint16_t pid; + + pid = usb0_host_get_pid(pipe); + + if (pid == USB_HOST_PID_STALL2) + { + usb0_host_set_pid_nak(pipe); + } + + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + USB_HOST_PID_BUF, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_set_pid_nak +* Description : Disables communication (NAK) in the pipe specified by the argument. +* : When the pipe status was enabling communication (BUF) before +* : executing before executing this function, waits in the software +* : until the pipe becomes ready after setting disabled. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_set_pid_nak (uint16_t pipe) +{ + uint16_t pid; + uint16_t pbusy; + uint32_t loop; + + pid = usb0_host_get_pid(pipe); + + if (pid == USB_HOST_PID_STALL2) + { + usb0_host_set_pid_stall(pipe); + } + + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + USB_HOST_PID_NAK, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + default: + break; + } + + if (pid == USB_HOST_PID_BUF) + { + for (loop = 0; loop < 200; loop++) + { + switch (pipe) + { + case USB_HOST_PIPE0: + pbusy = RZA_IO_RegRead_16(&USB200.DCPCTR, + USB_DCPCTR_PBUSY_SHIFT, + USB_DCPCTR_PBUSY); + break; + + case USB_HOST_PIPE1: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE1CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_HOST_PIPE2: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE2CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_HOST_PIPE3: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE3CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_HOST_PIPE4: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE4CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_HOST_PIPE5: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE5CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_HOST_PIPE6: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE6CTR, + USB_PIPEnCTR_6_8_PBUSY_SHIFT, + USB_PIPEnCTR_6_8_PBUSY); + break; + + case USB_HOST_PIPE7: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE7CTR, + USB_PIPEnCTR_6_8_PBUSY_SHIFT, + USB_PIPEnCTR_6_8_PBUSY); + break; + + case USB_HOST_PIPE8: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE8CTR, + USB_PIPEnCTR_6_8_PBUSY_SHIFT, + USB_PIPEnCTR_6_8_PBUSY); + break; + + case USB_HOST_PIPE9: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE9CTR, + USB_PIPEnCTR_9_PBUSY_SHIFT, + USB_PIPEnCTR_9_PBUSY); + break; + + default: + pbusy = 1; + break; + } + + if (pbusy == 0) + { + break; + } + + Userdef_USB_usb0_host_delay_500ns(); + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_set_pid_stall +* Description : Disables communication (STALL) in the pipe specified by the +* : argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_set_pid_stall (uint16_t pipe) +{ + uint16_t pid; + + pid = usb0_host_get_pid(pipe); + + if (pid == USB_HOST_PID_BUF) + { + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + USB_HOST_PID_STALL2, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + default: + break; + } + } + else + { + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + USB_HOST_PID_STALL, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + default: + break; + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_clear_pid_stall +* Description : Disables communication (NAK) in the pipe specified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_clear_pid_stall (uint16_t pipe) +{ + usb0_host_set_pid_nak(pipe); +} + +/******************************************************************************* +* Function Name: usb0_host_get_pid +* Description : Returns the pipe state specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : PID +*******************************************************************************/ +uint16_t usb0_host_get_pid (uint16_t pipe) +{ + uint16_t pid; + + switch (pipe) + { + case USB_HOST_PIPE0: + pid = RZA_IO_RegRead_16(&USB200.DCPCTR, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_HOST_PIPE1: + pid = RZA_IO_RegRead_16(&USB200.PIPE1CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE2: + pid = RZA_IO_RegRead_16(&USB200.PIPE2CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE3: + pid = RZA_IO_RegRead_16(&USB200.PIPE3CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE4: + pid = RZA_IO_RegRead_16(&USB200.PIPE4CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE5: + pid = RZA_IO_RegRead_16(&USB200.PIPE5CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE6: + pid = RZA_IO_RegRead_16(&USB200.PIPE6CTR, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE7: + pid = RZA_IO_RegRead_16(&USB200.PIPE7CTR, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE8: + pid = RZA_IO_RegRead_16(&USB200.PIPE8CTR, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE9: + pid = RZA_IO_RegRead_16(&USB200.PIPE9CTR, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + default: + pid = 0; + break; + } + + return pid; +} + +/******************************************************************************* +* Function Name: usb0_host_set_csclr +* Description : CSPLIT status clear setting of sprit transaction in specified +* : pipe is performed. +* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit +* : in DCPCTR register are continuously changed (when the sequence +* : toggle bit of data PID is continuously changed over two or more pipes), +* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary. +* : Do not set both SQCLR bit and SQSET bit to 1 at the same time. +* : In addition, both bits should be operated after PID is set to NAK. +* : However, when it is set to the isochronous transfer as the transfer type +* : (TYPE=11), writing in SQSET bit is disabled. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb0_host_set_csclr (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + 1, + USB_DCPCTR_CSCLR_SHIFT, + USB_DCPCTR_CSCLR); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_CSCLR_SHIFT, + USB_PIPEnCTR_6_8_CSCLR); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_CSCLR_SHIFT, + USB_PIPEnCTR_6_8_CSCLR); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_CSCLR_SHIFT, + USB_PIPEnCTR_6_8_CSCLR); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + 1, + USB_PIPEnCTR_9_CSCLR_SHIFT, + USB_PIPEnCTR_9_CSCLR); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_set_sqclr +* Description : Sets the sequence bit of the pipe specified by the argument to +* : DATA0. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_set_sqclr (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + 1, + USB_DCPCTR_SQCLR_SHIFT, + USB_DCPCTR_SQCLR); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_SQCLR_SHIFT, + USB_PIPEnCTR_6_8_SQCLR); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_SQCLR_SHIFT, + USB_PIPEnCTR_6_8_SQCLR); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_SQCLR_SHIFT, + USB_PIPEnCTR_6_8_SQCLR); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + 1, + USB_PIPEnCTR_9_SQCLR_SHIFT, + USB_PIPEnCTR_9_SQCLR); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_set_sqset +* Description : Sets the sequence bit of the pipe specified by the argument to +* : DATA1. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb0_host_set_sqset (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + 1, + USB_DCPCTR_SQSET_SHIFT, + USB_DCPCTR_SQSET); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_SQSET_SHIFT, + USB_PIPEnCTR_6_8_SQSET); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_SQSET_SHIFT, + USB_PIPEnCTR_6_8_SQSET); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_SQSET_SHIFT, + USB_PIPEnCTR_6_8_SQSET); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + 1, + USB_PIPEnCTR_9_SQSET_SHIFT, + USB_PIPEnCTR_9_SQSET); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_get_sqmon +* Description : Toggle bit of specified pipe is obtained +* Arguments : uint16_t pipe ; Pipe number +* Return Value : sqmon +*******************************************************************************/ +uint16_t usb0_host_get_sqmon (uint16_t pipe) +{ + uint16_t sqmon; + + switch (pipe) + { + case USB_HOST_PIPE0: + sqmon = RZA_IO_RegRead_16(&USB200.DCPCTR, + USB_DCPCTR_SQMON_SHIFT, + USB_DCPCTR_SQMON); + break; + + case USB_HOST_PIPE1: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE1CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_HOST_PIPE2: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE2CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_HOST_PIPE3: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE3CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_HOST_PIPE4: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE4CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_HOST_PIPE5: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE5CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_HOST_PIPE6: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE6CTR, + USB_PIPEnCTR_6_8_SQMON_SHIFT, + USB_PIPEnCTR_6_8_SQMON); + break; + + case USB_HOST_PIPE7: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE7CTR, + USB_PIPEnCTR_6_8_SQMON_SHIFT, + USB_PIPEnCTR_6_8_SQMON); + break; + + case USB_HOST_PIPE8: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE8CTR, + USB_PIPEnCTR_6_8_SQMON_SHIFT, + USB_PIPEnCTR_6_8_SQMON); + break; + + case USB_HOST_PIPE9: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE9CTR, + USB_PIPEnCTR_9_SQMON_SHIFT, + USB_PIPEnCTR_9_SQMON); + break; + + default: + sqmon = 0; + break; + } + + return sqmon; +} + +/******************************************************************************* +* Function Name: usb0_host_aclrm +* Description : The buffer of specified pipe is initialized +* Arguments : uint16_t pipe : Pipe +* Return Value : none +*******************************************************************************/ +void usb0_host_aclrm (uint16_t pipe) +{ + usb0_host_set_aclrm(pipe); + usb0_host_clr_aclrm(pipe); +} + +/******************************************************************************* +* Function Name: usb0_host_set_aclrm +* Description : The auto buffer clear mode of specified pipe is enabled +* Arguments : uint16_t pipe : Pipe +* Return Value : none +*******************************************************************************/ +void usb0_host_set_aclrm (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE0: + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + 1, + USB_PIPEnCTR_9_ACLRM_SHIFT, + USB_PIPEnCTR_9_ACLRM); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_clr_aclrm +* Description : The auto buffer clear mode of specified pipe is enabled +* Arguments : uint16_t pipe : Pipe +* Return Value : none +*******************************************************************************/ +void usb0_host_clr_aclrm (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE0: + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + 0, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + 0, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + 0, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + 0, + USB_PIPEnCTR_9_ACLRM_SHIFT, + USB_PIPEnCTR_9_ACLRM); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_get_inbuf +* Description : Returns INBUFM of the pipe specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : inbuf +*******************************************************************************/ +uint16_t usb0_host_get_inbuf (uint16_t pipe) +{ + uint16_t inbuf; + + switch (pipe) + { + case USB_HOST_PIPE0: + inbuf = 0; + break; + + case USB_HOST_PIPE1: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE1CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_HOST_PIPE2: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE2CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_HOST_PIPE3: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE3CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_HOST_PIPE4: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE4CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_HOST_PIPE5: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE5CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_HOST_PIPE6: + inbuf = 0; + break; + + case USB_HOST_PIPE7: + inbuf = 0; + break; + + case USB_HOST_PIPE8: + inbuf = 0; + break; + + case USB_HOST_PIPE9: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE9CTR, + USB_PIPEnCTR_9_INBUFM_SHIFT, + USB_PIPEnCTR_9_INBUFM); + break; + + default: + inbuf = 0; + break; + } + + return inbuf; +} + +/******************************************************************************* +* Function Name: usb0_host_setting_interrupt +* Description : Sets the USB module interrupt level. +* Arguments : uint8_t level ; interrupt level +* Return Value : none +*******************************************************************************/ +void usb0_host_setting_interrupt (uint8_t level) +{ +#if(1) /* ohci_wrapp */ + IRQn_Type d0fifo_dmaintid; + IRQn_Type d1fifo_dmaintid; + + InterruptHandlerRegister(USBI0_IRQn, usb0_host_interrupt); + GIC_SetPriority(USBI0_IRQn, level); + GIC_EnableIRQ(USBI0_IRQn); + + d0fifo_dmaintid = (IRQn_Type)Userdef_USB_usb0_host_d0fifo_dmaintid(); + + if (d0fifo_dmaintid != 0xFFFF) + { + InterruptHandlerRegister(d0fifo_dmaintid, usb0_host_dma_interrupt_d0fifo); + GIC_SetPriority(d0fifo_dmaintid, level); + GIC_EnableIRQ(d0fifo_dmaintid); + } + + d1fifo_dmaintid = (IRQn_Type)Userdef_USB_usb0_host_d1fifo_dmaintid(); + + if (d1fifo_dmaintid != 0xFFFF) + { + InterruptHandlerRegister(d1fifo_dmaintid, usb0_host_dma_interrupt_d1fifo); + GIC_SetPriority(d1fifo_dmaintid, level); + GIC_EnableIRQ(d1fifo_dmaintid); + } +#else + uint16_t d0fifo_dmaintid; + uint16_t d1fifo_dmaintid; + + R_INTC_RegistIntFunc(INTC_ID_USBI0, usb0_host_interrupt); + R_INTC_SetPriority(INTC_ID_USBI0, level); + R_INTC_Enable(INTC_ID_USBI0); + + d0fifo_dmaintid = Userdef_USB_usb0_host_d0fifo_dmaintid(); + + if (d0fifo_dmaintid != 0xFFFF) + { + R_INTC_RegistIntFunc(d0fifo_dmaintid, usb0_host_dma_interrupt_d0fifo); + R_INTC_SetPriority(d0fifo_dmaintid, level); + R_INTC_Enable(d0fifo_dmaintid); + } + + d1fifo_dmaintid = Userdef_USB_usb0_host_d1fifo_dmaintid(); + + if (d1fifo_dmaintid != 0xFFFF) + { + R_INTC_RegistIntFunc(d1fifo_dmaintid, usb0_host_dma_interrupt_d1fifo); + R_INTC_SetPriority(d1fifo_dmaintid, level); + R_INTC_Enable(d1fifo_dmaintid); + } +#endif +} + +/******************************************************************************* +* Function Name: usb0_host_reset_module +* Description : Initializes the USB module. +* : Enables providing clock to the USB module. +* : Sets USB bus wait register. +* Arguments : uint16_t clockmode ; 48MHz ; USBHCLOCK_X1_48MHZ +* : ; 12MHz ; USBHCLOCK_EXTAL_12MHZ +* Return Value : none +*******************************************************************************/ +void usb0_host_reset_module (uint16_t clockmode) +{ + if (RZA_IO_RegRead_16(&USB200.SYSCFG0, + USB_SYSCFG_UPLLE_SHIFT, + USB_SYSCFG_UPLLE) == 1) + { + if ((USB200.SYSCFG0 & USB_HOST_BITUCKSEL) != clockmode) + { + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + USB200.SYSCFG0 = 0; + USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode); + Userdef_USB_usb0_host_delay_xms(1); + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + } + else + { + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + Userdef_USB_usb0_host_delay_xms(1); + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + } + } + else + { + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + USB200.SYSCFG0 = 0; + USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode); + Userdef_USB_usb0_host_delay_xms(1); + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + } + + USB200.BUSWAIT = (uint16_t)(USB_HOST_BUSWAIT_05 & USB_HOST_BITBWAIT); +} + +/******************************************************************************* +* Function Name: usb0_host_get_buf_size +* Description : Obtains pipe buffer size specified by the argument and +* : maximum packet size of the USB device in use. +* : When USB_HOST_PIPE0 is specified by the argument, obtains the maximum +* : packet size of the USB device using the corresponding pipe. +* : For the case that USB_HOST_PIPE0 is not assigned by the argument, when the +* : corresponding pipe is in continuous transfer mode, +* : obtains the buffer size allocated in the corresponcing pipe, +* : when incontinuous transfer, obtains maximum packet size. +* Arguments : uint16_t ; pipe Number +* Return Value : Maximum packet size or buffer size +*******************************************************************************/ +uint16_t usb0_host_get_buf_size (uint16_t pipe) +{ + uint16_t size; + uint16_t bufsize; + + if (pipe == USB_HOST_PIPE0) + { + size = RZA_IO_RegRead_16(&USB200.DCPMAXP, + USB_DCPMAXP_MXPS_SHIFT, + USB_DCPMAXP_MXPS); + } + else + { + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1) + { + bufsize = RZA_IO_RegRead_16(&g_usb0_host_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE); + size = (uint16_t)((bufsize + 1) * USB_HOST_PIPExBUF); + } + else + { + size = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS); + } + } + return size; +} + +/******************************************************************************* +* Function Name: usb0_host_get_mxps +* Description : Obtains maximum packet size of the USB device using the pipe +* : specified by the argument. +* Arguments : uint16_t ; Pipe Number +* Return Value : Max Packet Size +*******************************************************************************/ +uint16_t usb0_host_get_mxps (uint16_t pipe) +{ + uint16_t size; + + if (pipe == USB_HOST_PIPE0) + { + size = RZA_IO_RegRead_16(&USB200.DCPMAXP, + USB_DCPMAXP_MXPS_SHIFT, + USB_DCPMAXP_MXPS); + } + else + { + size = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS); + } + + return size; +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_controlrw.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_controlrw.c new file mode 100644 index 0000000000..2f8ef12a38 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_controlrw.c @@ -0,0 +1,434 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_controlrw.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" +#include "dev_drv.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_host_CtrlTransStart +* Description : Executes USB control transfer. +* Arguments : uint16_t devadr ; device address +* : uint16_t Req ; bmRequestType & bRequest +* : uint16_t Val ; wValue +* : uint16_t Indx ; wIndex +* : uint16_t Len ; wLength +* : uint8_t *Buf ; Data buffer +* Return Value : DEVDRV_SUCCESS ; SUCCESS +* : DEVDRV_ERROR ; ERROR +*******************************************************************************/ +int32_t usb0_host_CtrlTransStart (uint16_t devadr, uint16_t Req, uint16_t Val, + uint16_t Indx, uint16_t Len, uint8_t * Buf) +{ + if (g_usb0_host_UsbDeviceSpeed == USB_HOST_LOW_SPEED) + { + RZA_IO_RegWrite_16(&USB200.SOFCFG, + 1, + USB_SOFCFG_TRNENSEL_SHIFT, + USB_SOFCFG_TRNENSEL); + } + else + { + RZA_IO_RegWrite_16(&USB200.SOFCFG, + 0, + USB_SOFCFG_TRNENSEL_SHIFT, + USB_SOFCFG_TRNENSEL); + } + + USB200.DCPMAXP = (uint16_t)((uint16_t)(devadr << 12) + g_usb0_host_default_max_packet[devadr]); + + if (g_usb0_host_pipe_status[USB_HOST_PIPE0] == USB_HOST_PIPE_IDLE) + { + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT; + g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */ + g_usb0_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE); + + if (Len == 0) + { + g_usb0_host_CmdStage |= USB_HOST_MODE_NO_DATA; /* No-data Control */ + } + else + { + if ((Req & 0x0080) != 0) + { + g_usb0_host_CmdStage |= USB_HOST_MODE_READ; /* Control Read */ + } + else + { + g_usb0_host_CmdStage |= USB_HOST_MODE_WRITE; /* Control Write */ + } + } + + g_usb0_host_SavReq = Req; /* save request */ + g_usb0_host_SavVal = Val; + g_usb0_host_SavIndx = Indx; + g_usb0_host_SavLen = Len; + } + else + { + if ((g_usb0_host_SavReq != Req) || (g_usb0_host_SavVal != Val) + || (g_usb0_host_SavIndx != Indx) || (g_usb0_host_SavLen != Len)) + { + return DEVDRV_ERROR; + } + } + + switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) + { + /* --------------- SETUP STAGE --------------- */ + case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE): + usb0_host_SetupStage(Req, Val, Indx, Len); + break; + + case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DOING): + /* do nothing */ + break; + + case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DONE): /* goto next stage */ + g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */ + switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD))) + { + case USB_HOST_MODE_WRITE: + g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA; + break; + + case USB_HOST_MODE_READ: + g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA; + break; + + case USB_HOST_MODE_NO_DATA: + g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS; + break; + + default: + break; + } + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE; + break; + + case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_NORES): + if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3) + { + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */ + } + else + { + g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */ + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE; + } + break; + + /* --------------- DATA STAGE --------------- */ + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE): + switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD))) + { + case USB_HOST_MODE_WRITE: + usb0_host_CtrlWriteStart((uint32_t)Len, Buf); + break; + + case USB_HOST_MODE_READ: + usb0_host_CtrlReadStart((uint32_t)Len, Buf); + break; + + default: + break; + } + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): + /* do nothing */ + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DONE): /* goto next stage */ + g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */ + g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS; + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE; + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_NORES): + if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3) + { + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */ + } + else + { + g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */ + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DOING; + usb0_host_clear_pid_stall(USB_HOST_PIPE0); + usb0_host_set_pid_buf(USB_HOST_PIPE0); + } + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_STALL): + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */ + break; + + /* --------------- STATUS STAGE --------------- */ + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE): + usb0_host_StatusStage(); + break; + + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + /* do nothing */ + break; + + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DONE): /* end of Control transfer */ + usb0_host_set_pid_nak(USB_HOST_PIPE0); + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_DONE; /* exit DONE */ + break; + + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_NORES): + if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3) + { + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */ + } + else + { + g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */ + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DOING; + usb0_host_clear_pid_stall(USB_HOST_PIPE0); + usb0_host_set_pid_buf(USB_HOST_PIPE0); + } + break; + + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_STALL): + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */ + break; + + default: + break; + } + + if (g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT) + { + RZA_IO_RegWrite_16(&USB200.SOFCFG, + 0, + USB_SOFCFG_TRNENSEL_SHIFT, + USB_SOFCFG_TRNENSEL); + } + + return DEVDRV_SUCCESS; +} + +/******************************************************************************* +* Function Name: usb0_host_SetupStage +* Description : Executes USB control transfer/set up stage. +* Arguments : uint16_t Req ; bmRequestType & bRequest +* : uint16_t Val ; wValue +* : uint16_t Indx ; wIndex +* : uint16_t Len ; wLength +* Return Value : none +*******************************************************************************/ +void usb0_host_SetupStage (uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len) +{ + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DOING; + + USB200.INTSTS1 = (uint16_t)~(USB_HOST_BITSACK | USB_HOST_BITSIGN); /* Status Clear */ + USB200.USBREQ = Req; + USB200.USBVAL = Val; + USB200.USBINDX = Indx; + USB200.USBLENG = Len; + USB200.DCPCTR = USB_HOST_BITSUREQ; /* PID=NAK & Send Setup */ +} + +/******************************************************************************* +* Function Name: usb0_host_StatusStage +* Description : Executes USB control transfer/status stage. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_StatusStage (void) +{ + uint8_t Buf1[16]; + + switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD))) + { + case USB_HOST_MODE_READ: + usb0_host_CtrlWriteStart((uint32_t)0, (uint8_t *)&Buf1); + break; + + case USB_HOST_MODE_WRITE: + usb0_host_CtrlReadStart((uint32_t)0, (uint8_t *)&Buf1); + break; + + case USB_HOST_MODE_NO_DATA: + usb0_host_CtrlReadStart((uint32_t)0, (uint8_t *)&Buf1); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_CtrlWriteStart +* Description : Executes USB control transfer/data stage(write). +* Arguments : uint32_t Bsize ; Data Size +* : uint8_t *Table ; Data Table Address +* Return Value : USB_HOST_WRITESHRT ; End of data write +* : USB_HOST_WRITEEND ; End of data write (not null) +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_FIFOERROR ; FIFO access error +*******************************************************************************/ +uint16_t usb0_host_CtrlWriteStart (uint32_t Bsize, uint8_t * Table) +{ + uint16_t EndFlag_K; + uint16_t mbw; + + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DOING; + + usb0_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */ + g_usb0_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */ + g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */ + + USB200.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */ +#if(1) /* ohci_wrapp */ + Userdef_USB_usb0_host_delay_10us(3); +#endif + RZA_IO_RegWrite_16(&USB200.DCPCFG, + 1, + USB_DCPCFG_DIR_SHIFT, + USB_DCPCFG_DIR); + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]); + usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_BITISEL, mbw); + USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + + usb0_host_clear_pid_stall(USB_HOST_PIPE0); + EndFlag_K = usb0_host_write_buffer_c(USB_HOST_PIPE0); + /* Host Control sequence */ + switch (EndFlag_K) + { + case USB_HOST_WRITESHRT: /* End of data write */ + g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS; + usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */ + usb0_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */ + break; + + case USB_HOST_WRITEEND: /* End of data write (not null) */ + case USB_HOST_WRITING: /* Continue of data write */ + usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */ + usb0_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */ + break; + + case USB_HOST_FIFOERROR: /* FIFO access error */ + break; + + default: + break; + } + usb0_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */ + return (EndFlag_K); /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_CtrlReadStart +* Description : Executes USB control transfer/data stage(read). +* Arguments : uint32_t Bsize ; Data Size +* : uint8_t *Table ; Data Table Address +* Return Value : none +*******************************************************************************/ +void usb0_host_CtrlReadStart (uint32_t Bsize, uint8_t * Table) +{ + uint16_t mbw; + + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DOING; + + usb0_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */ + g_usb0_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */ + g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */ + + USB200.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */ +#if(1) /* ohci_wrapp */ + Userdef_USB_usb0_host_delay_10us(3); +#endif + RZA_IO_RegWrite_16(&USB200.DCPCFG, + 0, + USB_DCPCFG_DIR_SHIFT, + USB_DCPCFG_DIR); + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]); + usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, mbw); + USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + + usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */ + usb0_host_enable_brdy_int(USB_HOST_PIPE0); /* Ok */ + usb0_host_clear_pid_stall(USB_HOST_PIPE0); + usb0_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */ +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_drv_api.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_drv_api.c new file mode 100644 index 0000000000..baa39adaac --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_drv_api.c @@ -0,0 +1,889 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_drv_api.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" +#include "dev_drv.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +static void usb0_host_resetEP(USB_HOST_CFG_PIPETBL_t *tbl); + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_api_host_init +* Description : Initializes USB module in the USB host mode. +* : USB connection is executed when executing this function in +* : the states that USB device isconnected to the USB port. +* Arguments : uint8_t int_level : USB Module interrupt level +* : USBU16 mode : USB_HOST_HIGH_SPEED +* : USB_HOST_FULL_SPEED +* : uint16_t clockmode : USB Clock mode +* Return Value : USB detach or attach +* : USB_HOST_ATTACH +* : USB_HOST_DETACH +*******************************************************************************/ +uint16_t usb0_api_host_init (uint8_t int_level, uint16_t mode, uint16_t clockmode) +{ + uint16_t connect; + volatile uint8_t dummy_buf; + + CPG.STBCR7 &= 0xfd; /*The clock of USB0 modules is permitted */ + dummy_buf = CPG.STBCR7; /* (Dummy read) */ + + g_usb0_host_SupportUsbDeviceSpeed = mode; + + usb0_host_setting_interrupt(int_level); + usb0_host_reset_module(clockmode); + + g_usb0_host_bchg_flag = USB_HOST_NO; + g_usb0_host_detach_flag = USB_HOST_NO; + g_usb0_host_attach_flag = USB_HOST_NO; + + g_usb0_host_driver_state = USB_HOST_DRV_DETACHED; + g_usb0_host_default_max_packet[USB_HOST_DEVICE_0] = 64; + + usb0_host_InitModule(); + + connect = usb0_host_CheckAttach(); + + if (connect == USB_HOST_ATTACH) + { + g_usb0_host_attach_flag = USB_HOST_YES; + } + else + { + usb0_host_UsbDetach2(); + } + + return connect; +} + +#if(1) /* ohci_wrapp */ +#else +/******************************************************************************* +* Function Name: usb0_api_host_enumeration +* Description : Initializes USB module in the USB host mode. +* : USB connection is executed when executing this function in +* : the states that USB device isconnected to the USB port. +* Arguments : uint16_t devadr : device address +* Return Value : DEVDRV_USBH_DETACH_ERR : device detach +* : DEVDRV_SUCCESS : device enumeration success +* : DEVDRV_ERROR : device enumeration error +*******************************************************************************/ +int32_t usb0_api_host_enumeration (uint16_t devadr) +{ + int32_t ret; + uint16_t driver_sts; + + g_usb0_host_setUsbAddress = devadr; + + while (1) + { + driver_sts = usb0_api_host_GetUsbDeviceState(); + + if (driver_sts == USB_HOST_DRV_DETACHED) + { + ret = DEVDRV_USBH_DETACH_ERR; + break; + } + else if (driver_sts == USB_HOST_DRV_CONFIGURED) + { + ret = DEVDRV_SUCCESS; + break; + } + else if (driver_sts == USB_HOST_DRV_STALL) + { + ret = DEVDRV_ERROR; + break; + } + else if (driver_sts == USB_HOST_DRV_NORES) + { + ret = DEVDRV_ERROR; + break; + } + else + { + /* Do Nothing */ + } + } + + if (driver_sts == USB_HOST_DRV_NORES) + { + while (1) + { + driver_sts = usb0_api_host_GetUsbDeviceState(); + + if (driver_sts == USB_HOST_DRV_DETACHED) + { + break; + } + } + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_api_host_detach +* Description : USB detach routine +* Arguments : none +* Return Value : USB_HOST_DETACH : USB detach +* : USB_HOST_ATTACH : USB attach +* : DEVDRV_ERROR : error +*******************************************************************************/ +int32_t usb0_api_host_detach (void) +{ + int32_t ret; + uint16_t driver_sts; + + while (1) + { + driver_sts = usb0_api_host_GetUsbDeviceState(); + + if (driver_sts == USB_HOST_DRV_DETACHED) + { + ret = USB_HOST_DETACH; + break; + } + else if (driver_sts == USB_HOST_DRV_CONFIGURED) + { + ret = USB_HOST_ATTACH; + break; + } + else if (driver_sts == USB_HOST_DRV_STALL) + { + ret = DEVDRV_ERROR; + break; + } + else if (driver_sts == USB_HOST_DRV_NORES) + { + ret = DEVDRV_ERROR; + break; + } + else + { + /* Do Nothing */ + } + } + + if (driver_sts == USB_HOST_DRV_NORES) + { + while (1) + { + driver_sts = usb0_api_host_GetUsbDeviceState(); + + if (driver_sts == USB_HOST_DRV_DETACHED) + { + break; + } + } + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_api_host_data_in +* Description : Executes USB transfer as data-in in the argument specified pipe. +* Arguments : uint16_t devadr ; device address +* : uint16_t Pipe ; Pipe Number +* : uint32_t Size ; Data Size +* : uint8_t *data_buf ; Data data_buf Address +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb0_api_host_data_in (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf) +{ + int32_t ret; + + if (Pipe == USB_HOST_PIPE0) + { + return DEVDRV_ERROR; + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr) + { + return DEVDRV_ERROR; + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 1) + { + return DEVDRV_ERROR; + } + + if (g_usb0_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE) + { + usb0_host_start_receive_transfer(Pipe, Size, data_buf); + } + else + { + return DEVDRV_ERROR; /* Now pipe is busy */ + } + + /* waiting for completing routine */ + do + { + if (g_usb0_host_detach_flag == USB_HOST_YES) + { + break; + } + + if ((g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT)) + { + break; + } + + } while (1); + + if (g_usb0_host_detach_flag == USB_HOST_YES) + { + return DEVDRV_USBH_DETACH_ERR; + } + + switch (g_usb0_host_pipe_status[Pipe]) + { + case USB_HOST_PIPE_DONE: + ret = DEVDRV_SUCCESS; + break; + + case USB_HOST_PIPE_STALL: + ret = DEVDRV_USBH_STALL; + break; + + case USB_HOST_PIPE_NORES: + ret = DEVDRV_USBH_COM_ERR; + break; + + default: + ret = DEVDRV_ERROR; + break; + } + + usb0_host_stop_transfer(Pipe); + + g_usb0_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE; + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_api_host_data_out +* Description : Executes USB transfer as data-out in the argument specified pipe. +* Arguments : uint16_t devadr ; device address +* : uint16_t Pipe ; Pipe Number +* : uint32_t Size ; Data Size +* : uint8_t *data_buf ; Data data_buf Address +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb0_api_host_data_out (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf) +{ + int32_t ret; + + if (Pipe == USB_HOST_PIPE0) + { + return DEVDRV_ERROR; + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr) + { + return DEVDRV_ERROR; + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) + { + return DEVDRV_ERROR; + } + + if (g_usb0_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE) + { + usb0_host_start_send_transfer(Pipe, Size, data_buf); + } + else + { + return DEVDRV_ERROR; /* Now pipe is busy */ + } + + /* waiting for completing routine */ + do + { + if (g_usb0_host_detach_flag == USB_HOST_YES) + { + break; + } + + if ((g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT)) + { + break; + } + + } while (1); + + if (g_usb0_host_detach_flag == USB_HOST_YES) + { + return DEVDRV_USBH_DETACH_ERR; + } + + switch (g_usb0_host_pipe_status[Pipe]) + { + case USB_HOST_PIPE_DONE: + ret = DEVDRV_SUCCESS; + break; + + case USB_HOST_PIPE_STALL: + ret = DEVDRV_USBH_STALL; + break; + + case USB_HOST_PIPE_NORES: + ret = DEVDRV_USBH_COM_ERR; + break; + + default: + ret = DEVDRV_ERROR; + break; + } + + usb0_host_stop_transfer(Pipe); + + g_usb0_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE; + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_api_host_control_transfer +* Description : Executes USB control transfer. +* Arguments : uint16_t devadr ; device address +* : uint16_t Req ; bmRequestType & bRequest +* : uint16_t Val ; wValue +* : uint16_t Indx ; wIndex +* : uint16_t Len ; wLength +* : uint8_t *buf ; Buffer +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_USBH_DETACH_ERR ; device detach +* : DEVDRV_USBH_CTRL_COM_ERR ; device no response +* : DEVDRV_USBH_STALL ; STALL +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb0_api_host_control_transfer (uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, + uint16_t Len, uint8_t * Buf) +{ + int32_t ret; + + do + { + ret = usb0_host_CtrlTransStart(devadr, Req, Val, Indx, Len, Buf); + + if (ret == DEVDRV_SUCCESS) + { + if (g_usb0_host_detach_flag == USB_HOST_YES) + { + break; + } + + if ((g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_IDLE) + && (g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT)) + { + break; + } + } + else + { + return DEVDRV_ERROR; + } + } while (1); + + if (g_usb0_host_detach_flag == USB_HOST_YES) + { + return DEVDRV_USBH_DETACH_ERR; + } + + switch (g_usb0_host_pipe_status[USB_HOST_PIPE0]) + { + case USB_HOST_PIPE_DONE: + ret = DEVDRV_SUCCESS; + break; + + case USB_HOST_PIPE_STALL: + ret = DEVDRV_USBH_STALL; + break; + + case USB_HOST_PIPE_NORES: + ret = DEVDRV_USBH_CTRL_COM_ERR; + break; + + default: + ret = DEVDRV_ERROR; + break; + } + + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE; + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_api_host_set_endpoint +* Description : Sets end point on the information specified in the argument. +* Arguments : uint16_t devadr ; device address +* : uint8_t *configdescriptor ; device configration descriptor +* : USB_HOST_CFG_PIPETBL_t *user_table ; pipe table +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb0_api_host_set_endpoint (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * configdescriptor) +{ + uint16_t ret; + uint32_t end_point; + uint32_t offset; + uint32_t totalLength; + USB_HOST_CFG_PIPETBL_t * pipe_table; + + /* End Point Search */ + end_point = 0; + offset = configdescriptor[0]; + totalLength = (uint16_t)(configdescriptor[2] + ((uint16_t)configdescriptor[3] << 8)); + + do + { + if (configdescriptor[offset + 1] == USB_HOST_ENDPOINT_DESC) + { + pipe_table = &user_table[end_point]; + + if (pipe_table->pipe_number == 0xffff) + { + break; + } + + ret = usb0_api_host_SetEndpointTable(devadr, pipe_table, (uint8_t *)&configdescriptor[offset]); + + if ((ret != USB_HOST_PIPE_IN) && (ret != USB_HOST_PIPE_OUT)) + { + return DEVDRV_ERROR; + } + + ++end_point; + } + + /* Next End Point Search */ + offset += configdescriptor[offset]; + + } while (offset < totalLength); + + return DEVDRV_SUCCESS; +} + +/******************************************************************************* +* Function Name: usb0_api_host_clear_endpoint +* Description : Clears the pipe definition table specified in the argument. +* Arguments : USB_HOST_CFG_PIPETBL_t *user_table : pipe table +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb0_api_host_clear_endpoint (USB_HOST_CFG_PIPETBL_t * user_table) +{ + uint16_t pipe; + + for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe) + { + if (user_table->pipe_number == 0xffff) + { + break; + } + user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD); + user_table->pipe_max_pktsize = 0; + user_table->pipe_cycle = 0; + + user_table++; + } + + return DEVDRV_SUCCESS; +} + +/******************************************************************************* +* Function Name: usb0_api_host_clear_endpoint_pipe +* Description : Clears the pipe definition table specified in the argument. +* Arguments : uint16_t pipe_sel : Pipe Number +* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb0_api_host_clear_endpoint_pipe (uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t * user_table) +{ + uint16_t pipe; + + for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe) + { + if (user_table->pipe_number == 0xffff) + { + break; + } + + if (user_table->pipe_number == pipe_sel) + { + user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD); + user_table->pipe_max_pktsize = 0; + user_table->pipe_cycle = 0; + break; + } + + user_table++; + } + + return DEVDRV_SUCCESS; +} +#endif + +/******************************************************************************* +* Function Name: usb0_api_host_SetEndpointTable +* Description : Sets the end point on the information specified by the argument. +* Arguments : uint16_t devadr : device address +* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table +* : uint8_t *Table : Endpoint descriptor +* Return Value : USB_HOST_DIR_H_IN ; IN endpoint +* : USB_HOST_DIR_H_OUT ; OUT endpoint +* : USB_END_POINT_ERROR ; error +*******************************************************************************/ +uint16_t usb0_api_host_SetEndpointTable (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * Table) +{ + uint16_t PipeCfg; + uint16_t PipeMaxp; + uint16_t pipe_number; + uint16_t ret; + uint16_t ret_flag = 0; // avoid warning. + + pipe_number = user_table->pipe_number; + + if (Table[1] != USB_HOST_ENDPOINT_DESC) + { + return USB_END_POINT_ERROR; + } + + switch (Table[3] & USB_HOST_EP_TYPE) + { + case USB_HOST_EP_CNTRL: + ret_flag = USB_END_POINT_ERROR; + break; + + case USB_HOST_EP_ISO: + if ((pipe_number != USB_HOST_PIPE1) && (pipe_number != USB_HOST_PIPE2)) + { + return USB_END_POINT_ERROR; + } + + PipeCfg = USB_HOST_ISO; + break; + + case USB_HOST_EP_BULK: + if ((pipe_number < USB_HOST_PIPE1) || (pipe_number > USB_HOST_PIPE5)) + { + return USB_END_POINT_ERROR; + } + + PipeCfg = USB_HOST_BULK; + break; + + case USB_HOST_EP_INT: + if ((pipe_number < USB_HOST_PIPE6) || (pipe_number > USB_HOST_PIPE9)) + { + return USB_END_POINT_ERROR; + } + + PipeCfg = USB_HOST_INTERRUPT; + break; + + default: + ret_flag = USB_END_POINT_ERROR; + break; + } + + if (ret_flag == USB_END_POINT_ERROR) + { + return ret_flag; + } + + /* Set pipe configuration table */ + if ((Table[2] & USB_HOST_EP_DIR_MASK) == USB_HOST_EP_IN) /* IN(receive) */ + { + if (PipeCfg == USB_HOST_ISO) + { + /* Transfer Type is ISO*/ + PipeCfg |= USB_HOST_DIR_H_IN; + + switch (user_table->fifo_port) + { + case USB_HOST_CUSE: + case USB_HOST_D0USE: + case USB_HOST_D1USE: + case USB_HOST_D0DMA: + case USB_HOST_D1DMA: + PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD); + break; + + default: + ret_flag = USB_END_POINT_ERROR; + break; + } + + if (ret_flag == USB_END_POINT_ERROR) + { + return ret_flag; + } + } + else + { + /* Transfer Type is BULK or INT */ + PipeCfg |= (USB_HOST_SHTNAKON | USB_HOST_DIR_H_IN); /* Compulsory SHTNAK */ + + switch (user_table->fifo_port) + { + case USB_HOST_CUSE: + case USB_HOST_D0USE: + case USB_HOST_D1USE: + PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD)); + break; + + case USB_HOST_D0DMA: + case USB_HOST_D1DMA: + PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD)); +#ifdef __USB_DMA_BFRE_ENABLE__ + /* this routine cannnot be perfomred if read operation is executed in buffer size */ + PipeCfg |= USB_HOST_BFREON; +#endif + break; + + default: + ret_flag = USB_END_POINT_ERROR; + break; + } + + if (ret_flag == USB_END_POINT_ERROR) + { + return ret_flag; + } + } + ret = USB_HOST_PIPE_IN; + } + else /* OUT(send) */ + { + if (PipeCfg == USB_HOST_ISO) + { + /* Transfer Type is ISO*/ + PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD); + } + else + { + /* Transfer Type is BULK or INT */ + PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD)); + } + PipeCfg |= USB_HOST_DIR_H_OUT; + ret = USB_HOST_PIPE_OUT; + } + + switch (user_table->fifo_port) + { + case USB_HOST_CUSE: + g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_CFIFO_USE; + break; + + case USB_HOST_D0USE: + g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_USE; + break; + + case USB_HOST_D1USE: + g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_USE; + break; + + case USB_HOST_D0DMA: + g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_DMA; + break; + + case USB_HOST_D1DMA: + g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_DMA; + break; + + default: + ret_flag = USB_END_POINT_ERROR; + break; + } + + if (ret_flag == USB_END_POINT_ERROR) + { + return ret_flag; + } + + /* Endpoint number set */ + PipeCfg |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK); + g_usb0_host_PipeTbl[pipe_number] |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK); + + /* Max packet size set */ + PipeMaxp = (uint16_t)((uint16_t)Table[4] | (uint16_t)((uint16_t)Table[5] << 8)); + + if (PipeMaxp == 0u) + { + return USB_END_POINT_ERROR; + } + + /* Set device address */ + PipeMaxp |= (uint16_t)(devadr << 12); + + user_table->pipe_cfg = PipeCfg; + user_table->pipe_max_pktsize = PipeMaxp; + + usb0_host_resetEP(user_table); + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_host_resetEP +* Description : Sets the end point on the information specified by the argument. +* Arguments : USB_HOST_CFG_PIPETBL_t *tbl : pipe table +* Return Value : none +*******************************************************************************/ +static void usb0_host_resetEP (USB_HOST_CFG_PIPETBL_t * tbl) +{ + + uint16_t pipe; + + /* Host pipe */ + /* The pipe number of pipe definition table is obtained */ + pipe = (uint16_t)(tbl->pipe_number & USB_HOST_BITCURPIPE); /* Pipe Number */ + + /* FIFO port access pipe is set to initial value */ + /* The connection with FIFO should be cut before setting the pipe */ + if (RZA_IO_RegRead_16(&USB200.CFIFOSEL, + USB_CFIFOSEL_CURPIPE_SHIFT, + USB_CFIFOSEL_CURPIPE) == pipe) + { + usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, USB_HOST_BITMBW_16); + } + + if (RZA_IO_RegRead_16(&USB200.D0FIFOSEL, + USB_DnFIFOSEL_CURPIPE_SHIFT, + USB_DnFIFOSEL_CURPIPE) == pipe) + { + usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, USB_HOST_BITMBW_16); + } + + if (RZA_IO_RegRead_16(&USB200.D1FIFOSEL, + USB_DnFIFOSEL_CURPIPE_SHIFT, + USB_DnFIFOSEL_CURPIPE) == pipe) + { + usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, USB_HOST_BITMBW_16); + } + + /* Interrupt of pipe set is disabled */ + usb0_host_disable_brdy_int(pipe); + usb0_host_disable_nrdy_int(pipe); + usb0_host_disable_bemp_int(pipe); + + /* Pipe to set is set to NAK */ + usb0_host_set_pid_nak(pipe); + + /* Pipe is set */ + USB200.PIPESEL = pipe; + + USB200.PIPECFG = tbl->pipe_cfg; + USB200.PIPEBUF = tbl->pipe_buf; + USB200.PIPEMAXP = tbl->pipe_max_pktsize; + USB200.PIPEPERI = tbl->pipe_cycle; + + g_usb0_host_pipecfg[pipe] = tbl->pipe_cfg; + g_usb0_host_pipebuf[pipe] = tbl->pipe_buf; + g_usb0_host_pipemaxp[pipe] = tbl->pipe_max_pktsize; + g_usb0_host_pipeperi[pipe] = tbl->pipe_cycle; + + /* Sequence bit clear */ + usb0_host_set_sqclr(pipe); + + usb0_host_aclrm(pipe); + usb0_host_set_csclr(pipe); + + /* Pipe window selection is set to unused */ + USB200.PIPESEL = USB_HOST_PIPE0; + +} + +#if(1) /* ohci_wrapp */ +#else +/******************************************************************************* +* Function Name: usb0_api_host_data_count +* Description : Get g_usb0_host_data_count[pipe] +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t *data_count ; return g_usb0_data_count[pipe] +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb0_api_host_data_count (uint16_t pipe, uint32_t * data_count) +{ + if (pipe > USB_HOST_MAX_PIPE_NO) + { + return DEVDRV_ERROR; + } + + *data_count = g_usb0_host_PipeDataSize[pipe]; + + return DEVDRV_SUCCESS; +} +#endif + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_global.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_global.c new file mode 100644 index 0000000000..2d1d5f5fc4 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_global.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_global.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +const uint16_t g_usb0_host_bit_set[16] = +{ + 0x0001, 0x0002, 0x0004, 0x0008, + 0x0010, 0x0020, 0x0040, 0x0080, + 0x0100, 0x0200, 0x0400, 0x0800, + 0x1000, 0x2000, 0x4000, 0x8000 +}; + +uint32_t g_usb0_host_data_count[USB_HOST_MAX_PIPE_NO + 1]; +uint8_t * g_usb0_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1]; + +uint16_t g_usb0_host_PipeIgnore[USB_HOST_MAX_PIPE_NO + 1]; +uint16_t g_usb0_host_PipeTbl[USB_HOST_MAX_PIPE_NO + 1]; +uint16_t g_usb0_host_pipe_status[USB_HOST_MAX_PIPE_NO + 1]; +uint32_t g_usb0_host_PipeDataSize[USB_HOST_MAX_PIPE_NO + 1]; + +USB_HOST_DMA_t g_usb0_host_DmaInfo[2]; + +uint16_t g_usb0_host_DmaPipe[2]; +uint16_t g_usb0_host_DmaBval[2]; +uint16_t g_usb0_host_DmaStatus[2]; + +uint16_t g_usb0_host_driver_state; +uint16_t g_usb0_host_ConfigNum; +uint16_t g_usb0_host_CmdStage; +uint16_t g_usb0_host_bchg_flag; +uint16_t g_usb0_host_detach_flag; +uint16_t g_usb0_host_attach_flag; + +uint16_t g_usb0_host_UsbAddress; +uint16_t g_usb0_host_setUsbAddress; +uint16_t g_usb0_host_default_max_packet[USB_HOST_MAX_DEVICE + 1]; +uint16_t g_usb0_host_UsbDeviceSpeed; +uint16_t g_usb0_host_SupportUsbDeviceSpeed; + +uint16_t g_usb0_host_SavReq; +uint16_t g_usb0_host_SavVal; +uint16_t g_usb0_host_SavIndx; +uint16_t g_usb0_host_SavLen; + +uint16_t g_usb0_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1]; +uint16_t g_usb0_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1]; +uint16_t g_usb0_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1]; +uint16_t g_usb0_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1]; + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_host_init_pipe_status +* Description : Initialize pipe status. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_init_pipe_status (void) +{ + uint16_t loop; + + g_usb0_host_ConfigNum = 0; + + for (loop = 0; loop < (USB_HOST_MAX_PIPE_NO + 1); ++loop) + { + g_usb0_host_pipe_status[loop] = USB_HOST_PIPE_IDLE; + g_usb0_host_PipeDataSize[loop] = 0; + + /* pipe configuration in usb0_host_resetEP() */ + g_usb0_host_pipecfg[loop] = 0; + g_usb0_host_pipebuf[loop] = 0; + g_usb0_host_pipemaxp[loop] = 0; + g_usb0_host_pipeperi[loop] = 0; + } +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbint.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbint.c new file mode 100644 index 0000000000..f4e5a27c77 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbint.c @@ -0,0 +1,496 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_usbint.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" +#if(1) /* ohci_wrapp */ +#include "ohci_wrapp_RZ_A1_local.h" +#endif + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +static void usb0_host_interrupt1(void); +static void usb0_host_BRDYInterrupt(uint16_t Status, uint16_t Int_enbl); +static void usb0_host_NRDYInterrupt(uint16_t Status, uint16_t Int_enbl); +static void usb0_host_BEMPInterrupt(uint16_t Status, uint16_t Int_enbl); + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_host_interrupt +* Description : Executes USB interrupt. +* : Register this function in the USB interrupt handler. +* : Set CFIF0 in the pipe set before the interrupt after executing +* : this function. +* Arguments : uint32_t int_sense ; Interrupts detection mode +* : ; INTC_LEVEL_SENSITIVE : Level sense +* : ; INTC_EDGE_TRIGGER : Edge trigger +* Return Value : none +*******************************************************************************/ +void usb0_host_interrupt (uint32_t int_sense) +{ + uint16_t savepipe1; + uint16_t savepipe2; + uint16_t buffer; + + savepipe1 = USB200.CFIFOSEL; + savepipe2 = USB200.PIPESEL; + usb0_host_interrupt1(); + + /* Control transmission changes ISEL within interruption processing. */ + /* For this reason, write return of ISEL cannot be performed. */ + buffer = USB200.CFIFOSEL; + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); + buffer |= (uint16_t)(savepipe1 & USB_HOST_BITCURPIPE); + USB200.CFIFOSEL = buffer; + USB200.PIPESEL = savepipe2; +} + +/******************************************************************************* +* Function Name: usb0_host_interrupt1 +* Description : Execue the USB interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_interrupt1 (void) +{ + uint16_t intsts0; + uint16_t intsts1; + uint16_t intenb0; + uint16_t intenb1; + uint16_t brdysts; + uint16_t nrdysts; + uint16_t bempsts; + uint16_t brdyenb; + uint16_t nrdyenb; + uint16_t bempenb; + volatile uint16_t dumy_sts; + + intsts0 = USB200.INTSTS0; + intsts1 = USB200.INTSTS1; + intenb0 = USB200.INTENB0; + intenb1 = USB200.INTENB1; + + if ((intsts1 & USB_HOST_BITBCHG) && (intenb1 & USB_HOST_BITBCHGE)) + { + USB200.INTSTS1 = (uint16_t)~USB_HOST_BITBCHG; + RZA_IO_RegWrite_16(&USB200.INTENB1, + 0, + USB_INTENB1_BCHGE_SHIFT, + USB_INTENB1_BCHGE); + g_usb0_host_bchg_flag = USB_HOST_YES; + } + else if ((intsts1 & USB_HOST_BITSACK) && (intenb1 & USB_HOST_BITSACKE)) + { + USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSACK; +#if(1) /* ohci_wrapp */ + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); +#else + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; +#endif + } + else if ((intsts1 & USB_HOST_BITSIGN) && (intenb1 & USB_HOST_BITSIGNE)) + { + USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSIGN; +#if(1) /* ohci_wrapp */ + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */ + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL); +#else + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_NORES; +#endif + } + else if (((intsts1 & USB_HOST_BITDTCH) == USB_HOST_BITDTCH) + && ((intenb1 & USB_HOST_BITDTCHE) == USB_HOST_BITDTCHE)) + { + USB200.INTSTS1 = (uint16_t)~USB_HOST_BITDTCH; + RZA_IO_RegWrite_16(&USB200.INTENB1, + 0, + USB_INTENB1_DTCHE_SHIFT, + USB_INTENB1_DTCHE); + g_usb0_host_detach_flag = USB_HOST_YES; + + Userdef_USB_usb0_host_detach(); + + usb0_host_UsbDetach2(); + } + else if (((intsts1 & USB_HOST_BITATTCH) == USB_HOST_BITATTCH) + && ((intenb1 & USB_HOST_BITATTCHE) == USB_HOST_BITATTCHE)) + { + USB200.INTSTS1 = (uint16_t)~USB_HOST_BITATTCH; + RZA_IO_RegWrite_16(&USB200.INTENB1, + 0, + USB_INTENB1_ATTCHE_SHIFT, + USB_INTENB1_ATTCHE); + g_usb0_host_attach_flag = USB_HOST_YES; + + Userdef_USB_usb0_host_attach(); + + usb0_host_UsbAttach(); + } + else if ((intsts0 & intenb0 & (USB_HOST_BITBEMP | USB_HOST_BITNRDY | USB_HOST_BITBRDY))) + { + brdysts = USB200.BRDYSTS; + nrdysts = USB200.NRDYSTS; + bempsts = USB200.BEMPSTS; + brdyenb = USB200.BRDYENB; + nrdyenb = USB200.NRDYENB; + bempenb = USB200.BEMPENB; + + if ((intsts0 & USB_HOST_BITBRDY) && (intenb0 & USB_HOST_BITBRDYE) && (brdysts & brdyenb)) + { + usb0_host_BRDYInterrupt(brdysts, brdyenb); + } + else if ((intsts0 & USB_HOST_BITBEMP) && (intenb0 & USB_HOST_BITBEMPE) && (bempsts & bempenb)) + { + usb0_host_BEMPInterrupt(bempsts, bempenb); + } + else if ((intsts0 & USB_HOST_BITNRDY) && (intenb0 & USB_HOST_BITNRDYE) && (nrdysts & nrdyenb)) + { + usb0_host_NRDYInterrupt(nrdysts, nrdyenb); + } + else + { + /* Do Nothing */ + } + } + else + { + /* Do Nothing */ + } + + /* Three dummy read for clearing interrupt requests */ + dumy_sts = USB200.INTSTS0; + dumy_sts = USB200.INTSTS1; + +} + +/******************************************************************************* +* Function Name: usb0_host_BRDYInterrupt +* Description : Executes USB BRDY interrupt. +* Arguments : uint16_t Status ; BRDYSTS Register Value +* : uint16_t Int_enbl ; BRDYENB Register Value +* Return Value : none +*******************************************************************************/ +void usb0_host_BRDYInterrupt (uint16_t Status, uint16_t Int_enbl) +{ + uint16_t buffer; + volatile uint16_t dumy_sts; + + if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0])) + { + USB200.BRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0]; + +#if(1) /* ohci_wrapp */ + switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) + { + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0); + usb0_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): + buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0); + switch (buffer) + { + case USB_HOST_READING: /* Continue of data read */ + break; + + case USB_HOST_READEND: /* End of data read */ + case USB_HOST_READSHRT: /* End of data read */ + usb0_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); + break; + + case USB_HOST_READOVER: /* buffer over */ + USB200.CFIFOCTR = USB_HOST_BITBCLR; + usb0_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); + break; + + case USB_HOST_FIFOERROR: /* FIFO access error */ + default: + break; + } + break; + + default: + break; + } +#else + switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) + { + case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + case (USB_HOST_MODE_NO_DATA | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0); + usb0_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; + break; + + case (USB_HOST_MODE_READ | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): + buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0); + + switch (buffer) + { + case USB_HOST_READING: /* Continue of data read */ + break; + + case USB_HOST_READEND: /* End of data read */ + case USB_HOST_READSHRT: /* End of data read */ + usb0_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; + break; + + case USB_HOST_READOVER: /* buffer over */ + USB200.CFIFOCTR = USB_HOST_BITBCLR; + usb0_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; + break; + + case USB_HOST_FIFOERROR: /* FIFO access error */ + default: + break; + } + break; + + default: + break; + } +#endif + } + else + { + usb0_host_brdy_int(Status, Int_enbl); + } + + /* Three dummy reads for clearing interrupt requests */ + dumy_sts = USB200.BRDYSTS; +} + +/******************************************************************************* +* Function Name: usb0_host_NRDYInterrupt +* Description : Executes USB NRDY interrupt. +* Arguments : uint16_t Status ; NRDYSTS Register Value +* : uint16_t Int_enbl ; NRDYENB Register Value +* Return Value : none +*******************************************************************************/ +void usb0_host_NRDYInterrupt (uint16_t Status, uint16_t Int_enbl) +{ + uint16_t pid; + volatile uint16_t dumy_sts; + + if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0])) + { + USB200.NRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0]; + pid = usb0_host_get_pid(USB_HOST_PIPE0); + + if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2)) + { + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_STALL; +#if(1) /* ohci_wrapp */ + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL); +#endif + } + else if (pid == USB_HOST_PID_NAK) + { + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_NORES; +#if(1) /* ohci_wrapp */ + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL); +#endif + } + else + { + /* Do Nothing */ + } + } + else + { + usb0_host_nrdy_int(Status, Int_enbl); + } + + /* Three dummy reads for clearing interrupt requests */ + dumy_sts = USB200.NRDYSTS; +} + +/******************************************************************************* +* Function Name: usb0_host_BEMPInterrupt +* Description : Executes USB BEMP interrupt. +* Arguments : uint16_t Status ; BEMPSTS Register Value +* : uint16_t Int_enbl ; BEMPENB Register Value +* Return Value : none +*******************************************************************************/ +void usb0_host_BEMPInterrupt (uint16_t Status, uint16_t Int_enbl) +{ + uint16_t buffer; + uint16_t pid; + volatile uint16_t dumy_sts; + + if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0])) + { + USB200.BEMPSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0]; + pid = usb0_host_get_pid(USB_HOST_PIPE0); + + if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2)) + { + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_STALL; +#if(1) /* ohci_wrapp */ + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */ + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL); +#endif + } + else + { +#if(1) /* ohci_wrapp */ + switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) + { + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): + buffer = usb0_host_write_buffer(USB_HOST_PIPE0); + switch (buffer) + { + case USB_HOST_WRITING: /* Continue of data write */ + case USB_HOST_WRITEEND: /* End of data write (zero-length) */ + break; + + case USB_HOST_WRITESHRT: /* End of data write */ + g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); + break; + + case USB_HOST_FIFOERROR: /* FIFO access error */ + default: + break; + } + break; + + default: + /* do nothing */ + break; + } +#else + switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) + { + case (USB_HOST_MODE_READ | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; + break; + + case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): + buffer = usb0_host_write_buffer(USB_HOST_PIPE0); + switch (buffer) + { + case USB_HOST_WRITING: /* Continue of data write */ + case USB_HOST_WRITEEND: /* End of data write (zero-length) */ + break; + + case USB_HOST_WRITESHRT: /* End of data write */ + g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS; + break; + + case USB_HOST_FIFOERROR: /* FIFO access error */ + default: + break; + } + break; + + case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE; + break; + + default: + /* do nothing */ + break; + } +#endif + } + } + else + { + usb0_host_bemp_int(Status, Int_enbl); + } + + /* Three dummy reads for clearing interrupt requests */ + dumy_sts = USB200.BEMPSTS; +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbsig.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbsig.c new file mode 100644 index 0000000000..4c5f810db3 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbsig.c @@ -0,0 +1,637 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_usbsig.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" +#include "dev_drv.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +static void usb0_host_EnableINT_Module(void); +static void usb0_host_Enable_AttachINT(void); +static void usb0_host_Disable_AttachINT(void); +static void usb0_host_Disable_BchgINT(void); + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_host_InitModule +* Description : Initializes the USB module in USB host module. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_InitModule (void) +{ + uint16_t buf1; + uint16_t buf2; + uint16_t buf3; + + usb0_host_init_pipe_status(); + + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 1, + USB_SYSCFG_DCFM_SHIFT, + USB_SYSCFG_DCFM); /* HOST mode */ + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 1, + USB_SYSCFG_DRPD_SHIFT, + USB_SYSCFG_DRPD); /* PORT0 D+, D- setting */ + + do + { + buf1 = RZA_IO_RegRead_16(&USB200.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + Userdef_USB_usb0_host_delay_xms(50); + buf2 = RZA_IO_RegRead_16(&USB200.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + Userdef_USB_usb0_host_delay_xms(50); + buf3 = RZA_IO_RegRead_16(&USB200.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + + } while ((buf1 != buf2) || (buf1 != buf3)); + + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 1, + USB_SYSCFG_USBE_SHIFT, + USB_SYSCFG_USBE); + + USB200.CFIFOSEL = (uint16_t)(USB_HOST_BITRCNT | USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE); + USB200.D0FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE); + USB200.D1FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE); +} + +/******************************************************************************* +* Function Name: usb0_host_CheckAttach +* Description : Returns the USB device connection state. +* Arguments : none +* Return Value : uint16_t ; USB_HOST_ATTACH : Attached +* : ; USB_HOST_DETACH : not Attached +*******************************************************************************/ +uint16_t usb0_host_CheckAttach (void) +{ + uint16_t buf1; + uint16_t buf2; + uint16_t buf3; + uint16_t rhst; + + do + { + buf1 = RZA_IO_RegRead_16(&USB200.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + Userdef_USB_usb0_host_delay_xms(50); + buf2 = RZA_IO_RegRead_16(&USB200.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + Userdef_USB_usb0_host_delay_xms(50); + buf3 = RZA_IO_RegRead_16(&USB200.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + + } while ((buf1 != buf2) || (buf1 != buf3)); + + rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0, + USB_DVSTCTR0_RHST_SHIFT, + USB_DVSTCTR0_RHST); + if (rhst == USB_HOST_UNDECID) + { + if (buf1 == USB_HOST_FS_JSTS) + { + if (g_usb0_host_SupportUsbDeviceSpeed == USB_HOST_HIGH_SPEED) + { + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 1, + USB_SYSCFG_HSE_SHIFT, + USB_SYSCFG_HSE); + } + else + { + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 0, + USB_SYSCFG_HSE_SHIFT, + USB_SYSCFG_HSE); + } + return USB_HOST_ATTACH; + } + else if (buf1 == USB_HOST_LS_JSTS) + { + /* Low Speed Device */ + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 0, + USB_SYSCFG_HSE_SHIFT, + USB_SYSCFG_HSE); + return USB_HOST_ATTACH; + } + else + { + /* Do Nothing */ + } + } + else if ((rhst == USB_HOST_HSMODE) || (rhst == USB_HOST_FSMODE)) + { + return USB_HOST_ATTACH; + } + else if (rhst == USB_HOST_LSMODE) + { + return USB_HOST_ATTACH; + } + else + { + /* Do Nothing */ + } + + return USB_HOST_DETACH; +} + +/******************************************************************************* +* Function Name: usb0_host_UsbAttach +* Description : Connects the USB device. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_UsbAttach (void) +{ + usb0_host_EnableINT_Module(); + usb0_host_Disable_BchgINT(); + usb0_host_Disable_AttachINT(); + usb0_host_Enable_DetachINT(); +} + +/******************************************************************************* +* Function Name: usb0_host_UsbDetach +* Description : Disconnects the USB device. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_UsbDetach (void) +{ + uint16_t pipe; + uint16_t devadr; + + g_usb0_host_driver_state = USB_HOST_DRV_DETACHED; + + /* Terminate all the pipes in which communications on port */ + /* are currently carried out */ + for (pipe = 0; pipe < (USB_HOST_MAX_PIPE_NO + 1); ++pipe) + { + if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_IDLE) + { + if (pipe == USB_HOST_PIPE0) + { + devadr = RZA_IO_RegRead_16(&USB200.DCPMAXP, + USB_DCPMAXP_DEVSEL_SHIFT, + USB_DCPMAXP_DEVSEL); + } + else + { + devadr = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL); + } + + if (devadr == g_usb0_host_UsbAddress) + { + usb0_host_stop_transfer(pipe); + } + + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_IDLE; + } + } + + g_usb0_host_ConfigNum = 0; + g_usb0_host_UsbAddress = 0; + g_usb0_host_default_max_packet[USB_HOST_DEVICE_0] = 64; + + usb0_host_UsbDetach2(); +} + +/******************************************************************************* +* Function Name: usb0_host_UsbDetach2 +* Description : Disconnects the USB device. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_UsbDetach2 (void) +{ + usb0_host_Disable_DetachINT(); + usb0_host_Disable_BchgINT(); + usb0_host_Enable_AttachINT(); +} + +/******************************************************************************* +* Function Name: usb0_host_UsbBusReset +* Description : Issues the USB bus reset signal. +* Arguments : none +* Return Value : uint16_t ; RHST +*******************************************************************************/ +uint16_t usb0_host_UsbBusReset (void) +{ + uint16_t buffer; + uint16_t loop; + + RZA_IO_RegWrite_16(&USB200.DVSTCTR0, + 1, + USB_DVSTCTR0_USBRST_SHIFT, + USB_DVSTCTR0_USBRST); + RZA_IO_RegWrite_16(&USB200.DVSTCTR0, + 0, + USB_DVSTCTR0_UACT_SHIFT, + USB_DVSTCTR0_UACT); + + Userdef_USB_usb0_host_delay_xms(50); + + buffer = USB200.DVSTCTR0; + buffer &= (uint16_t)(~(USB_HOST_BITRST)); + buffer |= USB_HOST_BITUACT; + USB200.DVSTCTR0 = buffer; + + Userdef_USB_usb0_host_delay_xms(20); + + for (loop = 0, buffer = USB_HOST_HSPROC; loop < 3; ++loop) + { + buffer = RZA_IO_RegRead_16(&USB200.DVSTCTR0, + USB_DVSTCTR0_RHST_SHIFT, + USB_DVSTCTR0_RHST); + if (buffer == USB_HOST_HSPROC) + { + Userdef_USB_usb0_host_delay_xms(10); + } + else + { + break; + } + } + + return buffer; +} + +/******************************************************************************* +* Function Name: usb0_host_UsbResume +* Description : Issues the USB resume signal. +* Arguments : none +* Return Value : int32_t ; DEVDRV_SUCCESS +* : ; DEVDRV_ERROR +*******************************************************************************/ +int32_t usb0_host_UsbResume (void) +{ + uint16_t buf; + + if ((g_usb0_host_driver_state & USB_HOST_DRV_SUSPEND) == 0) + { + /* not SUSPEND */ + return DEVDRV_ERROR; + } + + RZA_IO_RegWrite_16(&USB200.INTENB1, + 0, + USB_INTENB1_BCHGE_SHIFT, + USB_INTENB1_BCHGE); + RZA_IO_RegWrite_16(&USB200.DVSTCTR0, + 1, + USB_DVSTCTR0_RESUME_SHIFT, + USB_DVSTCTR0_RESUME); + Userdef_USB_usb0_host_delay_xms(20); + + buf = USB200.DVSTCTR0; + buf &= (uint16_t)(~(USB_HOST_BITRESUME)); + buf |= USB_HOST_BITUACT; + USB200.DVSTCTR0 = buf; + + g_usb0_host_driver_state &= (uint16_t)~USB_HOST_DRV_SUSPEND; + + return DEVDRV_SUCCESS; +} + +/******************************************************************************* +* Function Name: usb0_host_UsbSuspend +* Description : Issues the USB suspend signal. +* Arguments : none +* Return Value : int32_t ; DEVDRV_SUCCESS :not SUSPEND +* : ; DEVDRV_ERROR :SUSPEND +*******************************************************************************/ +int32_t usb0_host_UsbSuspend (void) +{ + uint16_t buf; + + if ((g_usb0_host_driver_state & USB_HOST_DRV_SUSPEND) != 0) + { + /* SUSPEND */ + return DEVDRV_ERROR; + } + + RZA_IO_RegWrite_16(&USB200.DVSTCTR0, + 0, + USB_DVSTCTR0_UACT_SHIFT, + USB_DVSTCTR0_UACT); + + Userdef_USB_usb0_host_delay_xms(5); + + buf = RZA_IO_RegRead_16(&USB200.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + if ((buf != USB_HOST_FS_JSTS) && (buf != USB_HOST_LS_JSTS)) + { + usb0_host_UsbDetach(); + } + else + { + g_usb0_host_driver_state |= USB_HOST_DRV_SUSPEND; + } + + return DEVDRV_SUCCESS; +} + +/******************************************************************************* +* Function Name: usb0_host_Enable_DetachINT +* Description : Enables the USB disconnection interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_Enable_DetachINT (void) +{ + USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH)); + RZA_IO_RegWrite_16(&USB200.INTENB1, + 1, + USB_INTENB1_DTCHE_SHIFT, + USB_INTENB1_DTCHE); +} + +/******************************************************************************* +* Function Name: usb0_host_Disable_DetachINT +* Description : Disables the USB disconnection interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_Disable_DetachINT (void) +{ + USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH)); + RZA_IO_RegWrite_16(&USB200.INTENB1, + 0, + USB_INTENB1_DTCHE_SHIFT, + USB_INTENB1_DTCHE); +} + +/******************************************************************************* +* Function Name: usb0_host_Enable_AttachINT +* Description : Enables the USB connection detection interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_Enable_AttachINT (void) +{ + USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH)); + RZA_IO_RegWrite_16(&USB200.INTENB1, + 1, + USB_INTENB1_ATTCHE_SHIFT, + USB_INTENB1_ATTCHE); +} + +/******************************************************************************* +* Function Name: usb0_host_Disable_AttachINT +* Description : Disables the USB connection detection interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_Disable_AttachINT (void) +{ + USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH)); + RZA_IO_RegWrite_16(&USB200.INTENB1, + 0, + USB_INTENB1_ATTCHE_SHIFT, + USB_INTENB1_ATTCHE); +} + +/******************************************************************************* +* Function Name: usb0_host_Disable_BchgINT +* Description : Disables the USB bus change detection interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_Disable_BchgINT (void) +{ + USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITBCHG)); + RZA_IO_RegWrite_16(&USB200.INTENB1, + 0, + USB_INTENB1_BCHGE_SHIFT, + USB_INTENB1_BCHGE); +} + +/******************************************************************************* +* Function Name: usb0_host_set_devadd +* Description : DEVADDn register is set by specified value +* Arguments : uint16_t addr : Device address +* : uint16_t *devadd : Set value +* Return Value : none +*******************************************************************************/ +void usb0_host_set_devadd (uint16_t addr, uint16_t * devadd) +{ + uint16_t * ptr; + uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning. + + switch (addr) + { + case USB_HOST_DEVICE_0: + ptr = (uint16_t *)&USB200.DEVADD0; + break; + + case USB_HOST_DEVICE_1: + ptr = (uint16_t *)&USB200.DEVADD1; + break; + + case USB_HOST_DEVICE_2: + ptr = (uint16_t *)&USB200.DEVADD2; + break; + + case USB_HOST_DEVICE_3: + ptr = (uint16_t *)&USB200.DEVADD3; + break; + + case USB_HOST_DEVICE_4: + ptr = (uint16_t *)&USB200.DEVADD4; + break; + + case USB_HOST_DEVICE_5: + ptr = (uint16_t *)&USB200.DEVADD5; + break; + + case USB_HOST_DEVICE_6: + ptr = (uint16_t *)&USB200.DEVADD6; + break; + + case USB_HOST_DEVICE_7: + ptr = (uint16_t *)&USB200.DEVADD7; + break; + + case USB_HOST_DEVICE_8: + ptr = (uint16_t *)&USB200.DEVADD8; + break; + + case USB_HOST_DEVICE_9: + ptr = (uint16_t *)&USB200.DEVADD9; + break; + + case USB_HOST_DEVICE_10: + ptr = (uint16_t *)&USB200.DEVADDA; + break; + + default: + ret_flag = DEVDRV_FLAG_OFF; + break; + } + + if (ret_flag == DEVDRV_FLAG_ON) + { + *ptr = (uint16_t)(*devadd & USB_HOST_DEVADD_MASK); + } +} + +/******************************************************************************* +* Function Name: usb0_host_get_devadd +* Description : DEVADDn register is obtained +* Arguments : uint16_t addr : Device address +* : uint16_t *devadd : USB_HOST_DEVADD register value +* Return Value : none +*******************************************************************************/ +void usb0_host_get_devadd (uint16_t addr, uint16_t * devadd) +{ + uint16_t * ptr; + uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning. + + switch (addr) + { + case USB_HOST_DEVICE_0: + ptr = (uint16_t *)&USB200.DEVADD0; + break; + + case USB_HOST_DEVICE_1: + ptr = (uint16_t *)&USB200.DEVADD1; + break; + + case USB_HOST_DEVICE_2: + ptr = (uint16_t *)&USB200.DEVADD2; + break; + + case USB_HOST_DEVICE_3: + ptr = (uint16_t *)&USB200.DEVADD3; + break; + + case USB_HOST_DEVICE_4: + ptr = (uint16_t *)&USB200.DEVADD4; + break; + + case USB_HOST_DEVICE_5: + ptr = (uint16_t *)&USB200.DEVADD5; + break; + + case USB_HOST_DEVICE_6: + ptr = (uint16_t *)&USB200.DEVADD6; + break; + + case USB_HOST_DEVICE_7: + ptr = (uint16_t *)&USB200.DEVADD7; + break; + + case USB_HOST_DEVICE_8: + ptr = (uint16_t *)&USB200.DEVADD8; + break; + + case USB_HOST_DEVICE_9: + ptr = (uint16_t *)&USB200.DEVADD9; + break; + + case USB_HOST_DEVICE_10: + ptr = (uint16_t *)&USB200.DEVADDA; + break; + + default: + ret_flag = DEVDRV_FLAG_OFF; + break; + } + + if (ret_flag == DEVDRV_FLAG_ON) + { + *devadd = *ptr; + } +} + +/******************************************************************************* +* Function Name: usb0_host_EnableINT_Module +* Description : Enables BEMP/NRDY/BRDY interrupt and SIGN/SACK interrupt. +* : Enables NRDY/BEMP interrupt in the pipe0. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_EnableINT_Module (void) +{ + uint16_t buf; + + buf = USB200.INTENB0; + buf |= (USB_HOST_BITBEMPE | USB_HOST_BITNRDYE | USB_HOST_BITBRDYE); + USB200.INTENB0 = buf; + + buf = USB200.INTENB1; + buf |= (USB_HOST_BITSIGNE | USB_HOST_BITSACKE); + USB200.INTENB1 = buf; + + usb0_host_enable_nrdy_int(USB_HOST_PIPE0); + usb0_host_enable_bemp_int(USB_HOST_PIPE0); +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_dmacdrv.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_dmacdrv.c new file mode 100644 index 0000000000..8f081a618f --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_dmacdrv.c @@ -0,0 +1,698 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_dmacdrv.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "r_typedefs.h" +#include "iodefine.h" +#include "rza_io_regrw.h" +#include "usb0_host_dmacdrv.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */ + +/* ==== Request setting information for on-chip peripheral module ==== */ +typedef enum dmac_peri_req_reg_type +{ + DMAC_REQ_MID, + DMAC_REQ_RID, + DMAC_REQ_AM, + DMAC_REQ_LVL, + DMAC_REQ_REQD +} dmac_peri_req_reg_type_t; + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +/* ==== Prototype declaration ==== */ + +/* ==== Global variable ==== */ +/* On-chip peripheral module request setting table */ +static const uint8_t usb0_host_dmac_peri_req_init_table[8][5] = +{ + /* MID,RID, AM,LVL,REQD */ + { 32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */ + { 32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */ + { 33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */ + { 33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */ + { 34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */ + { 34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */ + { 35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */ + { 35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */ +}; + + +/******************************************************************************* +* Function Name: usb0_host_DMAC1_PeriReqInit +* Description : Sets the register mode for DMA mode and the on-chip peripheral +* : module request for transfer request for DMAC channel 1. +* : Executes DMAC initial setting using the DMA information +* : specified by the argument *trans_info and the enabled/disabled +* : continuous transfer specified by the argument continuation. +* : Registers DMAC channel 1 interrupt handler function and sets +* : the interrupt priority level. Then enables transfer completion +* : interrupt. +* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC +* : : register +* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) +* : uint32_t continuation : Set continuous transfer to be valid +* : : after DMA transfer has been completed +* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer +* : DMAC_SAMPLE_SINGLE : Do not execute continuous +* : : transfer +* : uint32_t request_factor : Factor for on-chip peripheral module +* : : request +* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match +* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match +* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match +* : : +* : uint32_t req_direction : Setting value of CHCFG_n register +* : : REQD bit +* Return Value : none +*******************************************************************************/ +void usb0_host_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction) +{ + /* ==== Register mode ==== */ + if (DMAC_MODE_REGISTER == dmamode) + { + /* ==== Next0 register set ==== */ + DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ + DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ + DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */ + + /* DAD : Transfer destination address counting direction */ + /* SAD : Transfer source address counting direction */ + /* DDS : Transfer destination transfer size */ + /* SDS : Transfer source transfer size */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + trans_info->daddr_dir, + DMAC1_CHCFG_n_DAD_SHIFT, + DMAC1_CHCFG_n_DAD); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + trans_info->saddr_dir, + DMAC1_CHCFG_n_SAD_SHIFT, + DMAC1_CHCFG_n_SAD); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + trans_info->dst_size, + DMAC1_CHCFG_n_DDS_SHIFT, + DMAC1_CHCFG_n_DDS); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + trans_info->src_size, + DMAC1_CHCFG_n_SDS_SHIFT, + DMAC1_CHCFG_n_SDS); + + /* DMS : Register mode */ + /* RSEL : Select Next0 register set */ + /* SBE : No discharge of buffer data when aborted */ + /* DEM : No DMA interrupt mask */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_DMS_SHIFT, + DMAC1_CHCFG_n_DMS); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_RSEL_SHIFT, + DMAC1_CHCFG_n_RSEL); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_SBE_SHIFT, + DMAC1_CHCFG_n_SBE); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_DEM_SHIFT, + DMAC1_CHCFG_n_DEM); + + /* ---- Continuous transfer ---- */ + if (DMAC_SAMPLE_CONTINUATION == continuation) + { + /* REN : Execute continuous transfer */ + /* RSW : Change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 1, + DMAC1_CHCFG_n_REN_SHIFT, + DMAC1_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 1, + DMAC1_CHCFG_n_RSW_SHIFT, + DMAC1_CHCFG_n_RSW); + } + /* ---- Single transfer ---- */ + else + { + /* REN : Do not execute continuous transfer */ + /* RSW : Do not change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_REN_SHIFT, + DMAC1_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_RSW_SHIFT, + DMAC1_CHCFG_n_RSW); + } + + /* TM : Single transfer */ + /* SEL : Channel setting */ + /* HIEN, LOEN : On-chip peripheral module request */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_TM_SHIFT, + DMAC1_CHCFG_n_TM); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 1, + DMAC1_CHCFG_n_SEL_SHIFT, + DMAC1_CHCFG_n_SEL); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 1, + DMAC1_CHCFG_n_HIEN_SHIFT, + DMAC1_CHCFG_n_HIEN); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_LOEN_SHIFT, + DMAC1_CHCFG_n_LOEN); + + /* ---- Set factor by specified on-chip peripheral module request ---- */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], + DMAC1_CHCFG_n_AM_SHIFT, + DMAC1_CHCFG_n_AM); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], + DMAC1_CHCFG_n_LVL_SHIFT, + DMAC1_CHCFG_n_LVL); + if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) + { + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], + DMAC1_CHCFG_n_REQD_SHIFT, + DMAC1_CHCFG_n_REQD); + } + else + { + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + req_direction, + DMAC1_CHCFG_n_REQD_SHIFT, + DMAC1_CHCFG_n_REQD); + } + RZA_IO_RegWrite_32(&DMAC01.DMARS, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], + DMAC01_DMARS_CH1_RID_SHIFT, + DMAC01_DMARS_CH1_RID); + RZA_IO_RegWrite_32(&DMAC01.DMARS, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], + DMAC01_DMARS_CH1_MID_SHIFT, + DMAC01_DMARS_CH1_MID); + + /* PR : Round robin mode */ + RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, + 1, + DMAC07_DCTRL_0_7_PR_SHIFT, + DMAC07_DCTRL_0_7_PR); + } +} + +/******************************************************************************* +* Function Name: usb0_host_DMAC1_Open +* Description : Enables DMAC channel 1 transfer. +* Arguments : uint32_t req : DMAC request mode +* Return Value : 0 : Succeeded in enabling DMA transfer +* : -1 : Failed to enable DMA transfer (due to DMA operation) +*******************************************************************************/ +int32_t usb0_host_DMAC1_Open (uint32_t req) +{ + int32_t ret; + volatile uint8_t dummy; + + /* Transferable? */ + if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, + DMAC1_CHSTAT_n_EN_SHIFT, + DMAC1_CHSTAT_n_EN)) && + (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, + DMAC1_CHSTAT_n_TACT_SHIFT, + DMAC1_CHSTAT_n_TACT))) + { + /* Clear Channel Status Register */ + RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, + 1, + DMAC1_CHCTRL_n_SWRST_SHIFT, + DMAC1_CHCTRL_n_SWRST); + dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n, + DMAC1_CHCTRL_n_SWRST_SHIFT, + DMAC1_CHCTRL_n_SWRST); + /* Enable DMA transfer */ + RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, + 1, + DMAC1_CHCTRL_n_SETEN_SHIFT, + DMAC1_CHCTRL_n_SETEN); + + /* ---- Request by software ---- */ + if (DMAC_REQ_MODE_SOFT == req) + { + /* DMA transfer Request by software */ + RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, + 1, + DMAC1_CHCTRL_n_STG_SHIFT, + DMAC1_CHCTRL_n_STG); + } + + ret = 0; + } + else + { + ret = -1; + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_host_DMAC1_Close +* Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer +* : byte count at the time of DMA transfer abort to the argument +* : *remain. +* Arguments : uint32_t * remain : Remaining transfer byte count when +* : : DMA transfer is aborted +* Return Value : none +*******************************************************************************/ +void usb0_host_DMAC1_Close (uint32_t * remain) +{ + + /* ==== Abort transfer ==== */ + RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, + 1, + DMAC1_CHCTRL_n_CLREN_SHIFT, + DMAC1_CHCTRL_n_CLREN); + + while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, + DMAC1_CHSTAT_n_TACT_SHIFT, + DMAC1_CHSTAT_n_TACT)) + { + /* Loop until transfer is aborted */ + } + + while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, + DMAC1_CHSTAT_n_EN_SHIFT, + DMAC1_CHSTAT_n_EN)) + { + /* Loop until 0 is set in EN before checking the remaining transfer byte count */ + } + /* ==== Obtain remaining transfer byte count ==== */ + *remain = DMAC1.CRTB_n; +} + +/******************************************************************************* +* Function Name: usb0_host_DMAC1_Load_Set +* Description : Sets the transfer source address, transfer destination +* : address, and total transfer byte count respectively +* : specified by the argument src_addr, dst_addr, and count to +* : DMAC channel 1 as DMA transfer information. +* : Sets the register set selected by the CHCFG_n register +* : RSEL bit from the Next0 or Next1 register set. +* : This function should be called when DMA transfer of DMAC +* : channel 1 is aboted. +* Arguments : uint32_t src_addr : Transfer source address +* : uint32_t dst_addr : Transfer destination address +* : uint32_t count : Total transfer byte count +* Return Value : none +*******************************************************************************/ +void usb0_host_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) +{ + uint8_t reg_set; + + /* Obtain register set in use */ + reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, + DMAC1_CHSTAT_n_SR_SHIFT, + DMAC1_CHSTAT_n_SR); + + /* ==== Load ==== */ + if (0 == reg_set) + { + /* ---- Next0 Register Set ---- */ + DMAC1.N0SA_n = src_addr; /* Start address of transfer source */ + DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */ + DMAC1.N0TB_n = count; /* Total transfer byte count */ + } + else + { + /* ---- Next1 Register Set ---- */ + DMAC1.N1SA_n = src_addr; /* Start address of transfer source */ + DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */ + DMAC1.N1TB_n = count; /* Total transfer byte count */ + } +} + +/******************************************************************************* +* Function Name: usb0_host_DMAC2_PeriReqInit +* Description : Sets the register mode for DMA mode and the on-chip peripheral +* : module request for transfer request for DMAC channel 2. +* : Executes DMAC initial setting using the DMA information +* : specified by the argument *trans_info and the enabled/disabled +* : continuous transfer specified by the argument continuation. +* : Registers DMAC channel 2 interrupt handler function and sets +* : the interrupt priority level. Then enables transfer completion +* : interrupt. +* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC +* : : register +* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) +* : uint32_t continuation : Set continuous transfer to be valid +* : : after DMA transfer has been completed +* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer +* : DMAC_SAMPLE_SINGLE : Do not execute continuous +* : : transfer +* : uint32_t request_factor : Factor for on-chip peripheral module +* : : request +* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match +* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match +* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match +* : : +* : uint32_t req_direction : Setting value of CHCFG_n register +* : : REQD bit +* Return Value : none +*******************************************************************************/ +void usb0_host_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction) +{ + /* ==== Register mode ==== */ + if (DMAC_MODE_REGISTER == dmamode) + { + /* ==== Next0 register set ==== */ + DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ + DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ + DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */ + + /* DAD : Transfer destination address counting direction */ + /* SAD : Transfer source address counting direction */ + /* DDS : Transfer destination transfer size */ + /* SDS : Transfer source transfer size */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + trans_info->daddr_dir, + DMAC2_CHCFG_n_DAD_SHIFT, + DMAC2_CHCFG_n_DAD); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + trans_info->saddr_dir, + DMAC2_CHCFG_n_SAD_SHIFT, + DMAC2_CHCFG_n_SAD); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + trans_info->dst_size, + DMAC2_CHCFG_n_DDS_SHIFT, + DMAC2_CHCFG_n_DDS); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + trans_info->src_size, + DMAC2_CHCFG_n_SDS_SHIFT, + DMAC2_CHCFG_n_SDS); + + /* DMS : Register mode */ + /* RSEL : Select Next0 register set */ + /* SBE : No discharge of buffer data when aborted */ + /* DEM : No DMA interrupt mask */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_DMS_SHIFT, + DMAC2_CHCFG_n_DMS); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_RSEL_SHIFT, + DMAC2_CHCFG_n_RSEL); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_SBE_SHIFT, + DMAC2_CHCFG_n_SBE); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_DEM_SHIFT, + DMAC2_CHCFG_n_DEM); + + /* ---- Continuous transfer ---- */ + if (DMAC_SAMPLE_CONTINUATION == continuation) + { + /* REN : Execute continuous transfer */ + /* RSW : Change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 1, + DMAC2_CHCFG_n_REN_SHIFT, + DMAC2_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 1, + DMAC2_CHCFG_n_RSW_SHIFT, + DMAC2_CHCFG_n_RSW); + } + /* ---- Single transfer ---- */ + else + { + /* REN : Do not execute continuous transfer */ + /* RSW : Do not change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_REN_SHIFT, + DMAC2_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_RSW_SHIFT, + DMAC2_CHCFG_n_RSW); + } + + /* TM : Single transfer */ + /* SEL : Channel setting */ + /* HIEN, LOEN : On-chip peripheral module request */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_TM_SHIFT, + DMAC2_CHCFG_n_TM); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 2, + DMAC2_CHCFG_n_SEL_SHIFT, + DMAC2_CHCFG_n_SEL); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 1, + DMAC2_CHCFG_n_HIEN_SHIFT, + DMAC2_CHCFG_n_HIEN); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_LOEN_SHIFT, + DMAC2_CHCFG_n_LOEN); + + /* ---- Set factor by specified on-chip peripheral module request ---- */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], + DMAC2_CHCFG_n_AM_SHIFT, + DMAC2_CHCFG_n_AM); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], + DMAC2_CHCFG_n_LVL_SHIFT, + DMAC2_CHCFG_n_LVL); + if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) + { + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], + DMAC2_CHCFG_n_REQD_SHIFT, + DMAC2_CHCFG_n_REQD); + } + else + { + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + req_direction, + DMAC2_CHCFG_n_REQD_SHIFT, + DMAC2_CHCFG_n_REQD); + } + RZA_IO_RegWrite_32(&DMAC23.DMARS, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], + DMAC23_DMARS_CH2_RID_SHIFT, + DMAC23_DMARS_CH2_RID); + RZA_IO_RegWrite_32(&DMAC23.DMARS, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], + DMAC23_DMARS_CH2_MID_SHIFT, + DMAC23_DMARS_CH2_MID); + + /* PR : Round robin mode */ + RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, + 1, + DMAC07_DCTRL_0_7_PR_SHIFT, + DMAC07_DCTRL_0_7_PR); + } +} + +/******************************************************************************* +* Function Name: usb0_host_DMAC2_Open +* Description : Enables DMAC channel 2 transfer. +* Arguments : uint32_t req : DMAC request mode +* Return Value : 0 : Succeeded in enabling DMA transfer +* : -1 : Failed to enable DMA transfer (due to DMA operation) +*******************************************************************************/ +int32_t usb0_host_DMAC2_Open (uint32_t req) +{ + int32_t ret; + volatile uint8_t dummy; + + /* Transferable? */ + if ((0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, + DMAC2_CHSTAT_n_EN_SHIFT, + DMAC2_CHSTAT_n_EN)) && + (0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, + DMAC2_CHSTAT_n_TACT_SHIFT, + DMAC2_CHSTAT_n_TACT))) + { + /* Clear Channel Status Register */ + RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, + 1, + DMAC2_CHCTRL_n_SWRST_SHIFT, + DMAC2_CHCTRL_n_SWRST); + dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n, + DMAC2_CHCTRL_n_SWRST_SHIFT, + DMAC2_CHCTRL_n_SWRST); + /* Enable DMA transfer */ + RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, + 1, + DMAC2_CHCTRL_n_SETEN_SHIFT, + DMAC2_CHCTRL_n_SETEN); + + /* ---- Request by software ---- */ + if (DMAC_REQ_MODE_SOFT == req) + { + /* DMA transfer Request by software */ + RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, + 1, + DMAC2_CHCTRL_n_STG_SHIFT, + DMAC2_CHCTRL_n_STG); + } + + ret = 0; + } + else + { + ret = -1; + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_host_DMAC2_Close +* Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer +* : byte count at the time of DMA transfer abort to the argument +* : *remain. +* Arguments : uint32_t * remain : Remaining transfer byte count when +* : : DMA transfer is aborted +* Return Value : none +*******************************************************************************/ +void usb0_host_DMAC2_Close (uint32_t * remain) +{ + + /* ==== Abort transfer ==== */ + RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, + 1, + DMAC2_CHCTRL_n_CLREN_SHIFT, + DMAC2_CHCTRL_n_CLREN); + + while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, + DMAC2_CHSTAT_n_TACT_SHIFT, + DMAC2_CHSTAT_n_TACT)) + { + /* Loop until transfer is aborted */ + } + + while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, + DMAC2_CHSTAT_n_EN_SHIFT, + DMAC2_CHSTAT_n_EN)) + { + /* Loop until 0 is set in EN before checking the remaining transfer byte count */ + } + /* ==== Obtain remaining transfer byte count ==== */ + *remain = DMAC2.CRTB_n; +} + +/******************************************************************************* +* Function Name: usb0_host_DMAC2_Load_Set +* Description : Sets the transfer source address, transfer destination +* : address, and total transfer byte count respectively +* : specified by the argument src_addr, dst_addr, and count to +* : DMAC channel 2 as DMA transfer information. +* : Sets the register set selected by the CHCFG_n register +* : RSEL bit from the Next0 or Next1 register set. +* : This function should be called when DMA transfer of DMAC +* : channel 2 is aboted. +* Arguments : uint32_t src_addr : Transfer source address +* : uint32_t dst_addr : Transfer destination address +* : uint32_t count : Total transfer byte count +* Return Value : none +*******************************************************************************/ +void usb0_host_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) +{ + uint8_t reg_set; + + /* Obtain register set in use */ + reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, + DMAC2_CHSTAT_n_SR_SHIFT, + DMAC2_CHSTAT_n_SR); + + /* ==== Load ==== */ + if (0 == reg_set) + { + /* ---- Next0 Register Set ---- */ + DMAC2.N0SA_n = src_addr; /* Start address of transfer source */ + DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */ + DMAC2.N0TB_n = count; /* Total transfer byte count */ + } + else + { + /* ---- Next1 Register Set ---- */ + DMAC2.N1SA_n = src_addr; /* Start address of transfer source */ + DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */ + DMAC2.N1TB_n = count; /* Total transfer byte count */ + } +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_ohci_wrapp_pipe.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_ohci_wrapp_pipe.c new file mode 100644 index 0000000000..b69b0b2783 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_ohci_wrapp_pipe.c @@ -0,0 +1,156 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "devdrv_usb_host_api.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/********************************************************************************************************/ +/* Endpoint Configuration Data Format */ +/********************************************************************************************************/ +/* LINE1: Pipe Window Select Register */ +/* CPU Access PIPE : PIPE1 to PIPE9 [ ### SET ### ] */ +/* LINE2: Pipe Configuration Register */ +/* Transfer Type : USB_HOST_NONE [ USB_HOST_NONE ] */ +/* Buffer Ready interrupt : USB_HOST_NONE [ USB_HOST_NONE ] */ +/* Double Buffer Mode : USB_HOST_CNT_ON / USB_HOST_CNT_OFF [ ### SET ### ] */ +/* Continuous Transmit: : USB_HOST_CNT_ON / USB_HOST_CNT_OFF [ ### SET ### ] */ +/* Short NAK : USB_HOST_NONE [ USB_HOST_NONE ] */ +/* Transfer Direction : USB_HOST_NONE [ USB_HOST_NONE ] */ +/* Endpoint Number : USB_HOST_NONE [ USB_HOST_NONE ] */ +/* LINE3: Pipe Buffer Configuration Register */ +/* Buffer Size : (uint16_t)((uint16_t)(((x) / 64) - 1) << 10) */ +/* [ ### SET ### ] */ +/* Buffer Top Number : (uint16_t)(x) [ ### SET ### ] */ +/* LINE4: Pipe Maxpacket Size Register */ +/* Max Packet Size : USB_HOST_NONE [ USB_HOST_NONE ] */ +/* LINE5: Pipe Cycle Configuration Register (0x6C) */ +/* ISO Buffer Flush Mode : USB_HOST_NONE [ USB_HOST_NONE ] */ +/* ISO Interval Value : USB_HOST_NONE [ USB_HOST_NONE ] */ +/* LINE6: use FIFO port */ +/* : USB_HOST_CUSE [ ### SET ### ] */ +/* : USB_HOST_D0USE / USB_HOST_D1USE */ +/* : USB_HOST_D0DMA / USB_HOST_D0DMA */ +/* LINE7: use FIFO port Endian : USB_HOST_FIFO_BIG / USB_HOST_FIFO_LITTLE [ #SET# ] */ +/********************************************************************************************************/ + +/* Device Address 1 */ +USB_HOST_CFG_PIPETBL_t usb0_host_blk_ep_tbl1[ ] = +{ + { + USB_HOST_PIPE1, + /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(8), + USB_HOST_NONE, + USB_HOST_NONE, + USB_HOST_D0USE + }, + + { + /* Pipe end */ + 0xFFFF, + 0xFFFF, + 0xFFFF, + 0xFFFF, + 0xFFFF, + 0xFFFF + } +}; + +USB_HOST_CFG_PIPETBL_t usb0_host_int_ep_tbl1[ ] = +{ + { + USB_HOST_PIPE6, + /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(40), + USB_HOST_NONE, + USB_HOST_NONE, + USB_HOST_D1USE + }, + + { + USB_HOST_PIPE7, + /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(41), + USB_HOST_NONE, + USB_HOST_NONE, + USB_HOST_D1USE + }, + + { + USB_HOST_PIPE8, + /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(42), + USB_HOST_NONE, + USB_HOST_NONE, + USB_HOST_D1USE + }, + + { + USB_HOST_PIPE9, + /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(43), + USB_HOST_NONE, + USB_HOST_NONE, + USB_HOST_D1USE + }, + + { + /* Pipe end */ + 0xFFFF, + 0xFFFF, + 0xFFFF, + 0xFFFF, + 0xFFFF, + 0xFFFF + } +}; + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_userdef.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_userdef.c new file mode 100644 index 0000000000..07528eefdd --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_userdef.c @@ -0,0 +1,770 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_userdef.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include +#include "cmsis_os.h" +#include "r_typedefs.h" +#include "iodefine.h" +#include "devdrv_usb_host_api.h" +#include "usb0_host.h" +#include "MBRZA1H.h" /* INTC Driver Header */ +#include "usb0_host_dmacdrv.h" +#include "ohci_wrapp_RZ_A1_local.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define DUMMY_ACCESS (*(volatile unsigned long *)(OSTM0CNT)) + +/* #define CACHE_WRITEBACK */ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ +extern int32_t io_cwb(unsigned long start, unsigned long end); + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +static void usb0_host_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc); +static void usb0_host_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc); +static void Userdef_USB_usb0_host_delay_10us_2(void); + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_d0fifo_dmaintid +* Description : get D0FIFO DMA Interrupt ID +* Arguments : none +* Return Value : D0FIFO DMA Interrupt ID +*******************************************************************************/ +uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid (void) +{ + return DMAINT1_IRQn; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_d1fifo_dmaintid +* Description : get D1FIFO DMA Interrupt ID +* Arguments : none +* Return Value : D1FIFO DMA Interrupt ID +*******************************************************************************/ +uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid (void) +{ + return DMAINT2_IRQn; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_attach +* Description : Wait for the software of 1ms. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_attach (void) +{ +// printf("\n"); +// printf("channel 0 attach device\n"); +// printf("\n"); + ohciwrapp_loc_Connect(1); +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_detach +* Description : Wait for the software of 1ms. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_detach (void) +{ +// printf("\n"); +// printf("channel 0 detach device\n"); +// printf("\n"); + ohciwrapp_loc_Connect(0); +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_delay_1ms +* Description : Wait for the software of 1ms. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_delay_1ms (void) +{ + osDelay(1); +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_delay_xms +* Description : Wait for the software in the period of time specified by the +* : argument. +* : Alter this function according to the user's system. +* Arguments : uint32_t msec ; Wait Time (msec) +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_delay_xms (uint32_t msec) +{ + osDelay(msec); +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_delay_10us +* Description : Waits for software for the period specified by the argument. +* : Alter this function according to the user's system. +* Arguments : uint32_t usec ; Wait Time(x 10usec) +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_delay_10us (uint32_t usec) +{ + volatile int i; + + /* Wait 10us (Please change for your MCU) */ + for (i = 0; i < usec; ++i) + { + Userdef_USB_usb0_host_delay_10us_2(); + } +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_delay_10us_2 +* Description : Waits for software for the period specified by the argument. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +static void Userdef_USB_usb0_host_delay_10us_2 (void) +{ + volatile int i; + volatile unsigned long tmp; + + /* Wait 1us (Please change for your MCU) */ + for (i = 0; i < 14; ++i) + { + tmp = DUMMY_ACCESS; + } +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_delay_500ns +* Description : Wait for software for 500ns. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_delay_500ns (void) +{ + volatile int i; + volatile unsigned long tmp; + + /* Wait 500ns (Please change for your MCU) */ + /* Wait 500ns I clock 266MHz */ + tmp = DUMMY_ACCESS; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_start_dma +* Description : Enables DMA transfer on the information specified by the argument. +* : Set DMAC register by this function to enable DMA transfer. +* : After executing this function, USB module is set to start DMA +* : transfer. DMA transfer should not wait for DMA transfer complete. +* Arguments : USB_HOST_DMA_t *dma : DMA parameter +* : typedef struct{ +* : uint32_t fifo; FIFO for using +* : uint32_t buffer; Start address of transfer source/destination +* : uint32_t bytes; Transfer size(Byte) +* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer) +* : uint32_t size; DMA transfer size +* : } USB_HOST_DMA_t; +* : uint16_t dfacc ; 0 : cycle steal mode +* : 1 : 16byte continuous mode +* : 2 : 32byte continuous mode +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_start_dma (USB_HOST_DMA_t * dma, uint16_t dfacc) +{ + uint32_t trncount; + uint32_t src; + uint32_t dst; + uint32_t size; + uint32_t dir; +#ifdef CACHE_WRITEBACK + uint32_t ptr; +#endif + + trncount = dma->bytes; + dir = dma->dir; + + if (dir == USB_HOST_FIFO2BUF) + { + /* DxFIFO determination */ + dst = dma->buffer; +#ifndef __USB_HOST_DF_ACC_ENABLE__ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB200.D1FIFO.UINT32); + } + size = dma->size; + + if (size == 0) + { + src += 3; /* byte access */ + } + else if (size == 1) + { + src += 2; /* short access */ + } + else + { + /* Do Nothing */ + } +#else + size = dma->size; + + if (size == 2) + { + /* 32bit access */ + if (dfacc == 2) + { + /* 32byte access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFOB0); + } + else + { + src = (uint32_t)(&USB200.D1FIFOB0); + } + } + else if (dfacc == 1) + { + /* 16byte access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFOB0); + } + else + { + src = (uint32_t)(&USB200.D1FIFOB0); + } + } + else + { + /* normal access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB200.D1FIFO.UINT32); + } + } + } + else if (size == 1) + { + /* 16bit access */ + dfacc = 0; /* force normal access */ + + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB200.D1FIFO.UINT32); + } + src += 2; /* short access */ + } + else + { + /* 8bit access */ + dfacc = 0; /* force normal access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB200.D1FIFO.UINT32); + } + src += 3; /* byte access */ + } +#endif + } + else + { + /* DxFIFO determination */ + src = dma->buffer; +#ifndef __USB_HOST_DF_ACC_ENABLE__ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB200.D1FIFO.UINT32); + } + size = dma->size; + + if (size == 0) + { + dst += 3; /* byte access */ + } + else if (size == 1) + { + dst += 2; /* short access */ + } + else + { + /* Do Nothing */ + } +#else + size = dma->size; + if (size == 2) + { + /* 32bit access */ + if (dfacc == 2) + { + /* 32byte access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFOB0); + } + else + { + dst = (uint32_t)(&USB200.D1FIFOB0); + } + } + else if (dfacc == 1) + { + /* 16byte access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFOB0); + } + else + { + dst = (uint32_t)(&USB200.D1FIFOB0); + } + } + else + { + /* normal access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB200.D1FIFO.UINT32); + } + } + } + else if (size == 1) + { + /* 16bit access */ + dfacc = 0; /* force normal access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB200.D1FIFO.UINT32); + } + dst += 2; /* short access */ + } + else + { + /* 8bit access */ + dfacc = 0; /* force normal access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB200.D1FIFO.UINT32); + } + dst += 3; /* byte access */ + } +#endif + } + +#ifdef CACHE_WRITEBACK + ptr = (uint32_t)dma->buffer; + if ((ptr & 0x20000000ul) == 0) + { + io_cwb((uint32_t)ptr,(uint32_t)(ptr)+trncount); + } +#endif + + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + usb0_host_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc); + } + else + { + usb0_host_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc); + } +} + +/******************************************************************************* +* Function Name: usb0_host_enable_dmac0 +* Description : Enables DMA transfer on the information specified by the argument. +* Arguments : uint32_t src : src address +* : uint32_t dst : dst address +* : uint32_t count : transfer byte +* : uint32_t size : transfer size +* : uint32_t dir : direction +* : uint32_t fifo : FIFO(D0FIFO or D1FIFO) +* : uint16_t dfacc : 0 : normal access +* : : 1 : 16byte access +* : : 2 : 32byte access +* Return Value : none +*******************************************************************************/ +static void usb0_host_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc) +{ + dmac_transinfo_t trans_info; + uint32_t request_factor = 0; + int32_t ret; + + /* ==== Variable setting for DMAC initialization ==== */ + trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */ + trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */ + trans_info.count = (uint32_t)count; /* Total byte count to be transferred */ +#ifndef __USB_HOST_DF_ACC_ENABLE__ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { +// printf("size error!!\n"); + } +#else + if (dfacc == 2) + { + /* 32byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */ + } + else if (dfacc == 1) + { + /* 16byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */ + } + else + { + /* normal access */ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { +// printf("size error!!\n"); + } + } +#endif + + if (dir == USB_HOST_FIFO2BUF) + { + request_factor = DMAC_REQ_USB0_DMA0_RX; /* USB_0 channel 0 receive FIFO full */ + trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */ + } + else if (dir == USB_HOST_BUF2FIFO) + { + request_factor = DMAC_REQ_USB0_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */ + trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */ + } + else + { + /* Do Nothing */ + } + + /* ==== DMAC initialization ==== */ + usb0_host_DMAC1_PeriReqInit((const dmac_transinfo_t *)&trans_info, + DMAC_MODE_REGISTER, + DMAC_SAMPLE_SINGLE, + request_factor, + 0); /* Don't care DMAC_REQ_REQD is setting in usb0_host_DMAC1_PeriReqInit() */ + + /* ==== DMAC startup ==== */ + ret = usb0_host_DMAC1_Open(DMAC_REQ_MODE_PERI); + + if (ret != 0) + { +// printf("DMAC1 Open error!!\n"); + } + + return; +} + +/******************************************************************************* +* Function Name: usb0_host_enable_dmac1 +* Description : Enables DMA transfer on the information specified by the argument. +* Arguments : uint32_t src : src address +* : uint32_t dst : dst address +* : uint32_t count : transfer byte +* : uint32_t size : transfer size +* : uint32_t dir : direction +* : uint32_t fifo : FIFO(D0FIFO or D1FIFO) +* : uint16_t dfacc : 0 : normal access +* : : 1 : 16byte access +* : : 2 : 32byte access +* Return Value : none +*******************************************************************************/ +static void usb0_host_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc) +{ + dmac_transinfo_t trans_info; + uint32_t request_factor = 0; + int32_t ret; + + /* ==== Variable setting for DMAC initialization ==== */ + trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */ + trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */ + trans_info.count = (uint32_t)count; /* Total byte count to be transferred */ +#ifndef __USB_HOST_DF_ACC_ENABLE__ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { +// printf("size error!!\n"); + } +#else + if (dfacc == 2) + { + /* 32byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */ + } + else if (dfacc == 1) + { + /* 16byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */ + } + else + { + /* normal access */ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { +// printf("size error!!\n"); + } + } +#endif + + if (dir == USB_HOST_FIFO2BUF) + { + request_factor =DMAC_REQ_USB0_DMA1_RX; /* USB_0 channel 0 receive FIFO full */ + trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */ + } + else if (dir == USB_HOST_BUF2FIFO) + { + request_factor =DMAC_REQ_USB0_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */ + trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */ + } + else + { + /* Do Nothing */ + } + + /* ==== DMAC initialization ==== */ + usb0_host_DMAC2_PeriReqInit((const dmac_transinfo_t *)&trans_info, + DMAC_MODE_REGISTER, + DMAC_SAMPLE_SINGLE, + request_factor, + 0); /* Don't care DMAC_REQ_REQD is setting in usb0_host_DMAC2_PeriReqInit() */ + + /* ==== DMAC startup ==== */ + ret = usb0_host_DMAC2_Open(DMAC_REQ_MODE_PERI); + + if (ret != 0) + { +// printf("DMAC2 Open error!!\n"); + } + + return; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_stop_dma0 +* Description : Disables DMA transfer. +* Arguments : none +* Return Value : uint32_t return Transfer Counter register(DMATCRn) value +* : regarding to the bus width. +* Notice : This function should be executed to DMAC executed at the time +* : of specification of D0_FIF0_DMA in dma->fifo. +*******************************************************************************/ +uint32_t Userdef_USB_usb0_host_stop_dma0 (void) +{ + uint32_t remain; + + /* ==== DMAC release ==== */ + usb0_host_DMAC1_Close(&remain); + + return remain; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_stop_dma1 +* Description : Disables DMA transfer. +* : This function should be executed to DMAC executed at the time +* : of specification of D1_FIF0_DMA in dma->fifo. +* Arguments : none +* Return Value : uint32_t return Transfer Counter register(DMATCRn) value +* : regarding to the bus width. +*******************************************************************************/ +uint32_t Userdef_USB_usb0_host_stop_dma1 (void) +{ + uint32_t remain; + + /* ==== DMAC release ==== */ + usb0_host_DMAC2_Close(&remain); + + return remain; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_notice +* Description : Notice of USER +* Arguments : const char *format +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_notice (const char * format) +{ +// printf(format); + + return; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_user_rdy +* Description : This function notify a user and wait for trigger +* Arguments : const char *format +* : uint16_t data +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_user_rdy (const char * format, uint16_t data) +{ +// printf(format, data); + getchar(); + + return; +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/USBHALHost.cpp b/libraries/USBHost/USBHost/USBHALHost_LPC17.cpp similarity index 99% rename from libraries/USBHost/USBHost/USBHALHost.cpp rename to libraries/USBHost/USBHost/USBHALHost_LPC17.cpp index 2d67798d04..c1eadf3896 100644 --- a/libraries/USBHost/USBHost/USBHALHost.cpp +++ b/libraries/USBHost/USBHost/USBHALHost_LPC17.cpp @@ -14,6 +14,8 @@ * limitations under the License. */ +#if defined(TARGET_LPC1768) + #include "mbed.h" #include "USBHALHost.h" #include "dbg.h" @@ -320,3 +322,4 @@ void USBHALHost::UsbIrqhandler() { } } } +#endif diff --git a/libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp b/libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp new file mode 100644 index 0000000000..321d30b718 --- /dev/null +++ b/libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp @@ -0,0 +1,293 @@ +/* mbed USBHost Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(TARGET_RZ_A1H) + +#include "mbed.h" +#include "USBHALHost.h" +#include "dbg.h" + +#include "ohci_wrapp_RZ_A1.h" + + +#define HCCA_SIZE sizeof(HCCA) +#define ED_SIZE sizeof(HCED) +#define TD_SIZE sizeof(HCTD) + +#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE)) +#define ALIGNE_MSK (0x0000000F) + +static volatile uint8_t usb_buf[TOTAL_SIZE + ALIGNE_MSK]; //16 bytes aligned! + +USBHALHost * USBHALHost::instHost; + +USBHALHost::USBHALHost() { + instHost = this; + memInit(); + memset((void*)usb_hcca, 0, HCCA_SIZE); + for (int i = 0; i < MAX_ENDPOINT; i++) { + edBufAlloc[i] = false; + } + for (int i = 0; i < MAX_TD; i++) { + tdBufAlloc[i] = false; + } +} + +void USBHALHost::init() { + ohciwrapp_init(&_usbisr, 1); + + ohciwrapp_reg_w(OHCI_REG_CONTROL, 1); // HARDWARE RESET + ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, 0); // Initialize Control list head to Zero + ohciwrapp_reg_w(OHCI_REG_BULKHEADED, 0); // Initialize Bulk list head to Zero + + // Wait 100 ms before apply reset + wait_ms(100); + + // software reset + ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_HCR); + + // Write Fm Interval and Largest Data Packet Counter + ohciwrapp_reg_w(OHCI_REG_FMINTERVAL, DEFAULT_FMINTERVAL); + ohciwrapp_reg_w(OHCI_REG_PERIODICSTART, FI * 90 / 100); + + // Put HC in operational state + ohciwrapp_reg_w(OHCI_REG_CONTROL, (ohciwrapp_reg_r(OHCI_REG_CONTROL) & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER); + // Set Global Power + ohciwrapp_reg_w(OHCI_REG_RHSTATUS, OR_RH_STATUS_LPSC); + + ohciwrapp_reg_w(OHCI_REG_HCCA, (uint32_t)(usb_hcca)); + + // Clear Interrrupt Status + ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS)); + + ohciwrapp_reg_w(OHCI_REG_INTERRUPTENABLE, OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC); + + // Enable the USB Interrupt + ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC); + ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC); + + // Check for any connected devices + if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) { + //Device connected + wait_ms(150); + USB_DBG("Device connected (%08x)\n\r", ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1)); + deviceConnected(0, 1, ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA); + } +} + +uint32_t USBHALHost::controlHeadED() { + return ohciwrapp_reg_r(OHCI_REG_CONTROLHEADED); +} + +uint32_t USBHALHost::bulkHeadED() { + return ohciwrapp_reg_r(OHCI_REG_BULKHEADED); +} + +uint32_t USBHALHost::interruptHeadED() { + return usb_hcca->IntTable[0]; +} + +void USBHALHost::updateBulkHeadED(uint32_t addr) { + ohciwrapp_reg_w(OHCI_REG_BULKHEADED, addr); +} + + +void USBHALHost::updateControlHeadED(uint32_t addr) { + ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, addr); +} + +void USBHALHost::updateInterruptHeadED(uint32_t addr) { + usb_hcca->IntTable[0] = addr; +} + + +void USBHALHost::enableList(ENDPOINT_TYPE type) { + uint32_t wk_data; + + switch(type) { + case CONTROL_ENDPOINT: + ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_CLF); + wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_CLE); + ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data); + break; + case ISOCHRONOUS_ENDPOINT: + break; + case BULK_ENDPOINT: + ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_BLF); + wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_BLE); + ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data); + break; + case INTERRUPT_ENDPOINT: + wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_PLE); + ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data); + break; + } +} + + +bool USBHALHost::disableList(ENDPOINT_TYPE type) { + uint32_t wk_data; + + switch(type) { + case CONTROL_ENDPOINT: + wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL); + if(wk_data & OR_CONTROL_CLE) { + wk_data &= ~OR_CONTROL_CLE; + ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data); + return true; + } + return false; + case ISOCHRONOUS_ENDPOINT: + return false; + case BULK_ENDPOINT: + wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL); + if(wk_data & OR_CONTROL_BLE) { + wk_data &= ~OR_CONTROL_BLE; + ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data); + return true; + } + return false; + case INTERRUPT_ENDPOINT: + wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL); + if(wk_data & OR_CONTROL_PLE) { + wk_data &= ~OR_CONTROL_PLE; + ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data); + return true; + } + return false; + } + return false; +} + + +void USBHALHost::memInit() { + volatile uint8_t *p_wk_buf = (uint8_t *)(((uint32_t)usb_buf + ALIGNE_MSK) & ~ALIGNE_MSK); + + usb_hcca = (volatile HCCA *)p_wk_buf; + usb_edBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE); + usb_tdBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE)); +} + +volatile uint8_t * USBHALHost::getED() { + for (int i = 0; i < MAX_ENDPOINT; i++) { + if ( !edBufAlloc[i] ) { + edBufAlloc[i] = true; + return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE); + } + } + perror("Could not allocate ED\r\n"); + return NULL; //Could not alloc ED +} + +volatile uint8_t * USBHALHost::getTD() { + int i; + for (i = 0; i < MAX_TD; i++) { + if ( !tdBufAlloc[i] ) { + tdBufAlloc[i] = true; + return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE); + } + } + perror("Could not allocate TD\r\n"); + return NULL; //Could not alloc TD +} + + +void USBHALHost::freeED(volatile uint8_t * ed) { + int i; + i = (ed - usb_edBuf) / ED_SIZE; + edBufAlloc[i] = false; +} + +void USBHALHost::freeTD(volatile uint8_t * td) { + int i; + i = (td - usb_tdBuf) / TD_SIZE; + tdBufAlloc[i] = false; +} + + +void USBHALHost::resetRootHub() { + // Initiate port reset + ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRS); + + while (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRS); + + // ...and clear port reset signal + ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC); +} + + +void USBHALHost::_usbisr(void) { + if (instHost) { + instHost->UsbIrqhandler(); + } +} + +void USBHALHost::UsbIrqhandler() { + uint32_t int_status = ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS) & ohciwrapp_reg_r(OHCI_REG_INTERRUPTENABLE); + + if (int_status != 0) { //Is there something to actually process? + // Root hub status change interrupt + if (int_status & OR_INTR_STATUS_RHSC) { + if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CSC) { + if (ohciwrapp_reg_r(OHCI_REG_RHSTATUS) & OR_RH_STATUS_DRWE) { + // When DRWE is on, Connect Status Change + // means a remote wakeup event. + } else { + + //Root device connected + if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) { + + // wait 150ms to avoid bounce + wait_ms(150); + + //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed + deviceConnected(0, 1, ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA); + } + + //Root device disconnected + else { + + if (!(int_status & OR_INTR_STATUS_WDH)) { + usb_hcca->DoneHead = 0; + } + + // wait 200ms to avoid bounce + wait_ms(200); + + deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE); + + if (int_status & OR_INTR_STATUS_WDH) { + usb_hcca->DoneHead = 0; + ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_WDH); + } + } + } + ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC); + } + if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRSC) { + ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC); + } + ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_RHSC); + } + + // Writeback Done Head interrupt + if (int_status & OR_INTR_STATUS_WDH) { + transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE); + ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_WDH); + } + } +} +#endif diff --git a/libraries/USBHost/USBHostHub/USBHostHub.cpp b/libraries/USBHost/USBHostHub/USBHostHub.cpp index 7a9660bdb1..75c57f3ea8 100644 --- a/libraries/USBHost/USBHostHub/USBHostHub.cpp +++ b/libraries/USBHost/USBHostHub/USBHostHub.cpp @@ -222,6 +222,9 @@ void USBHostHub::portReset(uint8_t port) { uint32_t status; USB_DBG("reset port %d on hub: %p [this: %p]", port, dev, this) setPortFeature(PORT_RESET_FEATURE, port); +#if defined(TARGET_RZ_A1H) + Thread::wait(50); // Reset release waiting for Hi-Speed check. +#endif while(1) { status = getPortStatus(port); if (status & (PORT_ENABLE | PORT_RESET)) diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/rza_io_regrw.c b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/rza_io_regrw.c similarity index 100% rename from libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/rza_io_regrw.c rename to libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/rza_io_regrw.c From 63cfe8da231e640afa53bbe9f0680da859e4ee47 Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Thu, 15 Jan 2015 14:01:48 +0900 Subject: [PATCH 23/77] Fix some bugs about USBHost common codes. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Find some bugs in USBHost common codes. Bugs as below. - USBHostMouse.cpp 　- Memory destroy will occur when the size of interrupt transfer is larger than 4 bytes. - USBHostMSD.cpp 　- Type declaration of vender dependent. 　U16　-> uint16_t - USBHostSerial.cpp - connected() will not be "true". - Communication with USBSerial will not start. --- libraries/USBHost/USBHostHID/USBHostMouse.cpp | 11 ++++++++++- libraries/USBHost/USBHostMSD/USBHostMSD.cpp | 2 +- libraries/USBHost/USBHostSerial/USBHostSerial.cpp | 4 +++- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/libraries/USBHost/USBHostHID/USBHostMouse.cpp b/libraries/USBHost/USBHostHID/USBHostMouse.cpp index 493f12dc6c..52fcf8c5b3 100644 --- a/libraries/USBHost/USBHostHID/USBHostMouse.cpp +++ b/libraries/USBHost/USBHostHID/USBHostMouse.cpp @@ -47,6 +47,7 @@ bool USBHostMouse::connected() { } bool USBHostMouse::connect() { + int len_listen; if (dev_connected) { return true; @@ -69,7 +70,11 @@ bool USBHostMouse::connect() { host->registerDriver(dev, mouse_intf, this, &USBHostMouse::init); int_in->attach(this, &USBHostMouse::rxHandler); - host->interruptRead(dev, int_in, report, int_in->getSize(), false); + len_listen = int_in->getSize(); + if (len_listen > sizeof(report)) { + len_listen = sizeof(report); + } + host->interruptRead(dev, int_in, report, len_listen, false); dev_connected = true; return true; @@ -109,6 +114,10 @@ void USBHostMouse::rxHandler() { y = report[2]; z = report[3]; + if (len_listen > sizeof(report)) { + len_listen = sizeof(report); + } + if (dev) host->interruptRead(dev, int_in, report, len_listen, false); } diff --git a/libraries/USBHost/USBHostMSD/USBHostMSD.cpp b/libraries/USBHost/USBHostMSD/USBHostMSD.cpp index f159d20d47..1fcb54abf8 100644 --- a/libraries/USBHost/USBHostMSD/USBHostMSD.cpp +++ b/libraries/USBHost/USBHostMSD/USBHostMSD.cpp @@ -303,7 +303,7 @@ int USBHostMSD::getMaxLun() { int USBHostMSD::disk_initialize() { USB_DBG("FILESYSTEM: init"); - U16 i, timeout = 10; + uint16_t i, timeout = 10; getMaxLun(); diff --git a/libraries/USBHost/USBHostSerial/USBHostSerial.cpp b/libraries/USBHost/USBHostSerial/USBHostSerial.cpp index 2d3b1736db..428026ff54 100644 --- a/libraries/USBHost/USBHostSerial/USBHostSerial.cpp +++ b/libraries/USBHost/USBHostSerial/USBHostSerial.cpp @@ -71,6 +71,7 @@ bool USBHostSerial::connect() { { USBHostSerialPort::connect(host,d,port_intf,bulk_in, bulk_out); dev = d; + dev_connected = true; } } } @@ -171,6 +172,7 @@ bool USBHostMultiSerial::connect() { { ports[port]->connect(host,d,port_intf[port],bulk_in, bulk_out); dev = d; + dev_connected = true; } } } @@ -242,7 +244,7 @@ void USBHostSerialPort::connect(USBHost* _host, USBDeviceConnected * _dev, USB_INFO("New Serial device: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, serial_intf); dev->setName("Serial", serial_intf); host->registerDriver(dev, serial_intf, this, &USBHostSerialPort::init); - //baud(9600); + baud(9600); size_bulk_in = bulk_in->getSize(); size_bulk_out = bulk_out->getSize(); bulk_in->attach(this, &USBHostSerialPort::rxHandler); From e21c65041d9a718f866ed6438e5791b13f9c6d91 Mon Sep 17 00:00:00 2001 From: Paul Staron Date: Thu, 15 Jan 2015 19:11:40 +0000 Subject: [PATCH 24/77] New platform - Teensy 3.1 --- .../TARGET_K20D50M/MK20D5.h | 2 +- .../TOOLCHAIN_ARM_STD/MK20D5.sct | 0 .../TOOLCHAIN_ARM_STD/startup_MK20D5.s | 2 +- .../TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp | 2 +- .../TOOLCHAIN_GCC_ARM/MK20D5.ld | 0 .../TOOLCHAIN_GCC_ARM/startup_MK20D5..s} | 2 +- .../TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf | 0 .../TOOLCHAIN_IAR/startup_MK20D5.s | 0 .../{ => TARGET_K20XX}/TARGET_K20D50M/cmsis.h | 2 +- .../TARGET_K20D50M/cmsis_nvic.c | 2 +- .../TARGET_K20D50M/cmsis_nvic.h | 2 +- .../TARGET_K20D50M/system_MK20D5.c | 2 +- .../TARGET_K20D50M/system_MK20D5.h | 2 +- .../TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h | 6032 +++++++++++++++++ .../TOOLCHAIN_ARM_STD/MK20DX256.sct | 13 + .../TOOLCHAIN_ARM_STD/startup_MK20DX256.s | 559 ++ .../TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TOOLCHAIN_GCC_ARM/MK20DX256.ld | 163 + .../TOOLCHAIN_GCC_ARM/startup_MK20DX256.s | 361 + .../TARGET_K20XX/TARGET_TEENSY3_1/cmsis.h | 13 + .../TARGET_TEENSY3_1/cmsis_nvic.c | 55 + .../TARGET_TEENSY3_1/cmsis_nvic.h | 51 + .../TARGET_TEENSY3_1/system_MK20DX256.c | 330 + .../TARGET_TEENSY3_1/system_MK20DX256.h | 85 + .../TARGET_K20XX/PeripheralPins.h | 46 + .../PortNames.h | 2 +- .../TARGET_K20D50M/PeripheralNames.h | 7 +- .../TARGET_K20D50M/PeripheralPins.c | 120 + .../TARGET_K20D50M/PinNames.h | 2 +- .../TARGET_K20D50M/device.h | 2 +- .../TARGET_TEENSY3_1/PeripheralNames.h | 86 + .../TARGET_TEENSY3_1/PeripheralPins.c | 137 + .../TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h | 293 + .../TARGET_K20XX/TARGET_TEENSY3_1/device.h | 58 + .../analogin_api.c | 18 +- .../TARGET_K20XX/analogout_api.c | 84 + .../clk_freqs.h | 2 +- .../gpio_api.c | 2 +- .../gpio_irq_api.c | 2 +- .../gpio_object.h | 3 +- .../i2c_api.c | 30 +- .../objects.h | 8 +- .../{TARGET_K20D50M => TARGET_K20XX}/pinmap.c | 2 +- .../port_api.c | 2 +- .../pwmout_api.c | 32 +- .../rtc_api.c => TARGET_K20XX/rtc.api.c} | 2 +- .../serial_api.c | 22 +- .../{TARGET_K20D50M => TARGET_K20XX}/sleep.c | 2 +- .../spi_api.c | 27 +- .../us_ticker.c | 2 +- workspace_tools/build_release.py | 1 + workspace_tools/build_travis.py | 1 + workspace_tools/targets.py | 27 +- 53 files changed, 8594 insertions(+), 139 deletions(-) rename libraries/mbed/targets/cmsis/TARGET_Freescale/{ => TARGET_K20XX}/TARGET_K20D50M/MK20D5.h (99%) rename libraries/mbed/targets/cmsis/TARGET_Freescale/{ => TARGET_K20XX}/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct (100%) rename libraries/mbed/targets/cmsis/TARGET_Freescale/{ => TARGET_K20XX}/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s (99%) rename libraries/mbed/targets/cmsis/TARGET_Freescale/{ => TARGET_K20XX}/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp (92%) rename libraries/mbed/targets/cmsis/TARGET_Freescale/{ => TARGET_K20XX}/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld (100%) rename libraries/mbed/targets/cmsis/TARGET_Freescale/{TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s => TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5..s} (99%) rename libraries/mbed/targets/cmsis/TARGET_Freescale/{ => TARGET_K20XX}/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf (100%) rename libraries/mbed/targets/cmsis/TARGET_Freescale/{ => TARGET_K20XX}/TARGET_K20D50M/TOOLCHAIN_IAR/startup_MK20D5.s (100%) rename libraries/mbed/targets/cmsis/TARGET_Freescale/{ => TARGET_K20XX}/TARGET_K20D50M/cmsis.h (77%) rename libraries/mbed/targets/cmsis/TARGET_Freescale/{ => TARGET_K20XX}/TARGET_K20D50M/cmsis_nvic.c (97%) rename libraries/mbed/targets/cmsis/TARGET_Freescale/{ => TARGET_K20XX}/TARGET_K20D50M/cmsis_nvic.h (97%) rename libraries/mbed/targets/cmsis/TARGET_Freescale/{ => TARGET_K20XX}/TARGET_K20D50M/system_MK20D5.c (99%) rename libraries/mbed/targets/cmsis/TARGET_Freescale/{ => TARGET_K20XX}/TARGET_K20D50M/system_MK20D5.h (97%) create mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/MK20DX256.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/startup_MK20DX256.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld create mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.h create mode 100644 libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/PeripheralPins.h rename libraries/mbed/targets/hal/TARGET_Freescale/{TARGET_K20D50M => TARGET_K20XX}/PortNames.h (95%) rename libraries/mbed/targets/hal/TARGET_Freescale/{ => TARGET_K20XX}/TARGET_K20D50M/PeripheralNames.h (95%) create mode 100644 libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/PeripheralPins.c rename libraries/mbed/targets/hal/TARGET_Freescale/{ => TARGET_K20XX}/TARGET_K20D50M/PinNames.h (99%) rename libraries/mbed/targets/hal/TARGET_Freescale/{ => TARGET_K20XX}/TARGET_K20D50M/device.h (97%) create mode 100644 libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralPins.c create mode 100644 libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device.h rename libraries/mbed/targets/hal/TARGET_Freescale/{TARGET_K20D50M => TARGET_K20XX}/analogin_api.c (87%) create mode 100644 libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/analogout_api.c rename libraries/mbed/targets/hal/TARGET_Freescale/{TARGET_K20D50M => TARGET_K20XX}/clk_freqs.h (99%) rename libraries/mbed/targets/hal/TARGET_Freescale/{TARGET_K20D50M => TARGET_K20XX}/gpio_api.c (97%) rename libraries/mbed/targets/hal/TARGET_Freescale/{TARGET_K20D50M => TARGET_K20XX}/gpio_irq_api.c (99%) rename libraries/mbed/targets/hal/TARGET_Freescale/{TARGET_K20D50M => TARGET_K20XX}/gpio_object.h (96%) rename libraries/mbed/targets/hal/TARGET_Freescale/{TARGET_K20D50M => TARGET_K20XX}/i2c_api.c (95%) rename libraries/mbed/targets/hal/TARGET_Freescale/{TARGET_K20D50M => TARGET_K20XX}/objects.h (92%) rename libraries/mbed/targets/hal/TARGET_Freescale/{TARGET_K20D50M => TARGET_K20XX}/pinmap.c (97%) rename libraries/mbed/targets/hal/TARGET_Freescale/{TARGET_K20D50M => TARGET_K20XX}/port_api.c (98%) rename libraries/mbed/targets/hal/TARGET_Freescale/{TARGET_K20D50M => TARGET_K20XX}/pwmout_api.c (75%) rename libraries/mbed/targets/hal/TARGET_Freescale/{TARGET_K20D50M/rtc_api.c => TARGET_K20XX/rtc.api.c} (98%) rename libraries/mbed/targets/hal/TARGET_Freescale/{TARGET_K20D50M => TARGET_K20XX}/serial_api.c (95%) rename libraries/mbed/targets/hal/TARGET_Freescale/{TARGET_K20D50M => TARGET_K20XX}/sleep.c (97%) rename libraries/mbed/targets/hal/TARGET_Freescale/{TARGET_K20D50M => TARGET_K20XX}/spi_api.c (91%) rename libraries/mbed/targets/hal/TARGET_Freescale/{TARGET_K20D50M => TARGET_K20XX}/us_ticker.c (99%) diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/MK20D5.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/MK20D5.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/MK20D5.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/MK20D5.h index bd430e10bd..b979eb7db3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/MK20D5.h +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/MK20D5.h @@ -14,7 +14,7 @@ ** Abstract: ** CMSIS Peripheral Access Layer for MK20D5 ** -** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved. +** Copyright: 1997 - 2015 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http: www.freescale.com ** mail: support@freescale.com diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s index db50cd5aa4..24de2c2504 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s @@ -5,7 +5,7 @@ ; * @version: 1.0 ; * @date: 2011-12-15 ; * -; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved. +; * Copyright: 1997 - 2015 Freescale Semiconductor, Inc. All Rights Reserved. ;* ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ; * diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp similarity index 92% rename from libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp index b129b2c2a5..3296df1928 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - stackheap - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * Copyright (C) 2009-2015 ARM Limited. All rights reserved. * * Setup a fixed single stack/heap memory model, * between the top of the RW/ZI region and the stackpointer diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5..s similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5..s index d4dc59acaa..ffa33181ff 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5..s @@ -4,7 +4,7 @@ * Version: V1.3 * Date: 08 Feb 2012 * - * Copyright (c) 2012, ARM Limited + * Copyright (c) 2015, ARM Limited * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_IAR/startup_MK20D5.s b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/startup_MK20D5.s similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_IAR/startup_MK20D5.s rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/startup_MK20D5.s diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis.h similarity index 77% rename from libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/cmsis.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis.h index bebfa6d698..099017c7f7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/cmsis.h +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * Copyright (C) 2009-2015 ARM Limited. All rights reserved. * * A generic CMSIS include header, pulling in LPC11U24 specifics */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.c similarity index 97% rename from libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/cmsis_nvic.c rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.c index 077924407b..16d1b1f7e4 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.c @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * CMSIS-style functionality to support dynamic vectors ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. + * Copyright (c) 2015 ARM Limited. All rights reserved. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.h similarity index 97% rename from libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/cmsis_nvic.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.h index 86c17cfb84..04cf15b21f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/cmsis_nvic.h +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.h @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * CMSIS-style functionality to support dynamic vectors ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. + * Copyright (c) 2015 ARM Limited. All rights reserved. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/system_MK20D5.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.c similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/system_MK20D5.c rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.c index 393d1f0c5d..9cd3c16b0c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/system_MK20D5.c +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.c @@ -16,7 +16,7 @@ ** contains the system frequency. It configures the device and initializes ** the oscillator (PLL) that is part of the microcontroller device. ** -** Copyright: 2011 Freescale Semiconductor, Inc. All Rights Reserved. +** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http: www.freescale.com ** mail: support@freescale.com diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/system_MK20D5.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.h similarity index 97% rename from libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/system_MK20D5.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.h index 0396163f48..7387917905 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/system_MK20D5.h +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.h @@ -16,7 +16,7 @@ ** contains the system frequency. It configures the device and initializes ** the oscillator (PLL) that is part of the microcontroller device. ** -** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved. +** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http: www.freescale.com ** mail: support@freescale.com diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h new file mode 100644 index 0000000000..041f997824 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h @@ -0,0 +1,6032 @@ +/* +** ################################################################### +** Processors: MK20DX64VLH7 +** MK20DX128VLH7 +** MK20DX256VLH7 +** MK20DX64VLK7 +** MK20DX128VLK7 +** MK20DX256VLK7 +** MK20DX128VLL7 +** MK20DX256VLL7 +** MK20DX64VMB7 +** MK20DX128VMB7 +** MK20DX256VMB7 +** MK20DX128VML7 +** MK20DX256VML7 +** +** Compilers: ARM Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: Kxx (P1 silicon) Sub-Family Reference Manual Rev. 0, draft A Oct 2011 +** Version: rev. 1.0, 2012-01-15 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2012-01-15) +** Initial public version. +** +** ################################################################### +*/ + +/** + * @file MK20DX256.h + * @version 2.0 + * @date 2012-03-19 + * @brief CMSIS Peripheral Access Layer for MK20DX256 + * + * CMSIS Peripheral Access Layer for MK20DX256 + */ + +#if !defined(MK20DX256_H_) +#define MK20DX256_H_ /**< Symbol preventing repeated inclusion */ +#define MCU_MK20DX256 +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0200u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000u + +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +typedef enum IRQn { + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + + DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */ + DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */ + DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */ + DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */ + DMA4_IRQn = 4, + DMA5_IRQn = 5, + DMA6_IRQn = 6, + DMA7_IRQn = 7, + DMA8_IRQn = 8, + DMA9_IRQn = 9, + DMA10_IRQn = 10, + DMA11_IRQn = 11, + DMA12_IRQn = 12, + DMA13_IRQn = 13, + DMA14_IRQn = 14, + DMA15_IRQn = 15, + DMA_Error_IRQn = 16, /**< DMA error interrupt */ + Reserved33_IRQn = 17, + FTFL_IRQn = 18, /**< FTFL interrupt */ + Read_Collision_IRQn = 19, /**< Read collision interrupt */ + LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ + LLW_IRQn = 21, /**< Low Leakage Wakeup */ + Watchdog_IRQn = 22, /**< WDOG interrupt */ + Reserved39_IRQn = 23, + I2C0_IRQn = 24, /**< I2C0 interrupt */ + I2C1_IRQn = 25, + SPI0_IRQn = 26, /**< SPI0 interrupt */ + SPI1_IRQn = 27, + Reserved44_IRQn = 28, + CAN0_ORed_Message_buffer_IRQn = 29, /**< CAN0 OR'd message buffers interrupt */ + CAN0_Bus_Off_IRQn = 30, /**< CAN0 bus off interrupt */ + CAN0_Error_IRQn = 31, /**< CAN0 error interrupt */ + CAN0_Tx_Warning_IRQn = 32, /**< CAN0 Tx warning interrupt */ + CAN0_Rx_Warning_IRQn = 33, /**< CAN0 Rx warning interrupt */ + CAN0_Wake_Up_IRQn = 34, /**< CAN0 wake up interrupt */ + I2S0_Tx_IRQn = 35, /**< I2S0 transmit interrupt */ + I2S0_Rx_IRQn = 36, /**< I2S0 receive interrupt */ + Reserved53_IRQn = 37, + Reserved54_IRQn = 38, + Reserved55_IRQn = 39, + Reserved56_IRQn = 40, + Reserved57_IRQn = 41, + Reserved58_IRQn = 42, + Reserved59_IRQn = 43, + UART0_LON_IRQn = 44, /**< UART0 LON interrupt */ + UART0_RX_TX_IRQn = 45, /**< UART0 receive/transmit interrupt */ + UART0_ERR_IRQn = 46, /**< UART0 error interrupt */ + UART1_RX_TX_IRQn = 47, /**< UART1 receive/transmit interrupt */ + UART1_ERR_IRQn = 48, /**< UART1 error interrupt */ + UART2_RX_TX_IRQn = 49, /**< UART2 receive/transmit interrupt */ + UART2_ERR_IRQn = 50, /**< UART2 error interrupt */ + Reserved67_IRQn = 51, + Reserved68_IRQn = 52, + Reserved69_IRQn = 53, + Reserved70_IRQn = 54, + Reserved71_IRQn = 55, + Reserved72_IRQn = 56, + ADC0_IRQn = 57, /**< ADC0 interrupt */ + ADC1_IRQn = 58, + CMP0_IRQn = 59, /**< CMP0 interrupt */ + CMP1_IRQn = 60, /**< CMP1 interrupt */ + CMP2_IRQn = 61, + FTM0_IRQn = 62, /**< FTM0 fault, overflow and channels interrupt */ + FTM1_IRQn = 63, /**< FTM1 fault, overflow and channels interrupt */ + FTM2_IRQn = 64, + CMT_IRQn = 65, /**< CMT interrupt */ + RTC_IRQn = 66, /**< RTC interrupt */ + RTC_Seconds_IRQn = 67, /**< RTC seconds interrupt */ + PIT0_IRQn = 68, /**< PIT timer channel 0 interrupt */ + PIT1_IRQn = 69, /**< PIT timer channel 1 interrupt */ + PIT2_IRQn = 70, /**< PIT timer channel 2 interrupt */ + PIT3_IRQn = 71, /**< PIT timer channel 3 interrupt */ + PDB0_IRQn = 72, /**< PDB0 interrupt */ + USB0_IRQn = 73, /**< USB0 interrupt */ + USBDCD_IRQn = 74, /**< USBDCD interrupt */ + Reserved91_IRQn = 75, + Reserved92_IRQn = 76, + Reserved93_IRQn = 77, + Reserved94_IRQn = 78, + Reserved95_IRQn = 79, + Reserved96_IRQn = 80, + DAC0_IRQn = 81, + Reserved98_IRQn = 82, + TSI0_IRQn = 83, /**< TSI0 interrupt */ + MCG_IRQn = 84, /**< MCG interrupt */ + LPTimer_IRQn = 85, /**< LPTimer interrupt */ + Reserved102_IRQn = 86, + PORTA_IRQn = 87, /**< Port A interrupt */ + PORTB_IRQn = 88, /**< Port B interrupt */ + PORTC_IRQn = 89, /**< Port C interrupt */ + PORTD_IRQn = 90, /**< Port D interrupt */ + PORTE_IRQn = 91, /**< Port E interrupt */ + Reserved108_IRQn = 92, + Reserved109_IRQn = 93, + SWI_IRQn = 94 /**< Software interrupt */ + +} IRQn_Type; + +/** + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M4 Core Configuration + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ +#include "system_MK20DX256.h" /* Device specific configuration file */ + +/** + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */ + __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */ + __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */ + __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */ + __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */ + __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */ + __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */ + __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */ + __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */ + __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */ + __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */ + __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */ + __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */ + __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */ + __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */ + __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */ + __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */ + __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */ + uint8_t RESERVED_0[4]; + __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */ + __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */ + __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */ + __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */ + __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */ + __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */ + __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* SC1 Bit Fields */ +#define ADC_SC1_ADCH_MASK 0x1Fu +#define ADC_SC1_ADCH_SHIFT 0 +#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<>> ------------------ +; * +; *****************************************************************************/ + + +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt + DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt + DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt + DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt + DCD DMA4_IRQHandler ; DMA channel 4 transfer complete interrupt + DCD DMA5_IRQHandler ; DMA channel 5 transfer complete interrupt + DCD DMA6_IRQHandler ; DMA channel 6 transfer complete interrupt + DCD DMA7_IRQHandler ; DMA channel 7 transfer complete interrupt + DCD DMA8_IRQHandler ; DMA channel 8 transfer complete interrupt + DCD DMA9_IRQHandler ; DMA channel 9 transfer complete interrupt + DCD DMA10_IRQHandler ; DMA channel 10 transfer complete interrupt + DCD DMA11_IRQHandler ; DMA channel 11 transfer complete interrupt + DCD DMA12_IRQHandler ; DMA channel 12 transfer complete interrupt + DCD DMA13_IRQHandler ; DMA channel 13 transfer complete interrupt + DCD DMA14_IRQHandler ; DMA channel 14 transfer complete interrupt + DCD DMA15_IRQHandler ; DMA channel 15 transfer complete interrupt + DCD DMA_Error_IRQHandler ; DMA error interrupt + DCD Reserved33_IRQHandler ; Reserved interrupt 33 + DCD FTFL_IRQHandler ; FTFL interrupt + DCD Read_Collision_IRQHandler ; Read collision interrupt + DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning + DCD LLW_IRQHandler ; Low Leakage Wakeup + DCD Watchdog_IRQHandler ; WDOG interrupt + DCD Reserved39_IRQHandler ; Reserved interrupt 39 + DCD I2C0_IRQHandler ; I2C0 interrupt + DCD I2C1_IRQHandler ; I2C1 interrupt + DCD SPI0_IRQHandler ; SPI0 interrupt + DCD SPI1_IRQHandler ; SPI1 interrupt + DCD Reserved44_IRQHandler ; Reserved interrupt 44 + DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt + DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt + DCD CAN0_Error_IRQHandler ; CAN0 error interrupt + DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt + DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt + DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt + DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt + DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt + DCD Reserved53_IRQHandler ; Reserved interrupt 53 + DCD Reserved54_IRQHandler ; Reserved interrupt 54 + DCD Reserved55_IRQHandler ; Reserved interrupt 55 + DCD Reserved56_IRQHandler ; Reserved interrupt 56 + DCD Reserved57_IRQHandler ; Reserved interrupt 57 + DCD Reserved58_IRQHandler ; Reserved interrupt 58 + DCD Reserved59_IRQHandler ; Reserved interrupt 59 + DCD UART0_LON_IRQHandler ; UART0 LON interrupt + DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt + DCD UART0_ERR_IRQHandler ; UART0 error interrupt + DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt + DCD UART1_ERR_IRQHandler ; UART1 error interrupt + DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt + DCD UART2_ERR_IRQHandler ; UART2 error interrupt + DCD Reserved67_IRQHandler ; Reserved interrupt 67 + DCD Reserved68_IRQHandler ; Reserved interrupt 68 + DCD Reserved69_IRQHandler ; Reserved interrupt 69 + DCD Reserved70_IRQHandler ; Reserved interrupt 70 + DCD Reserved71_IRQHandler ; Reserved interrupt 71 + DCD Reserved72_IRQHandler ; Reserved interrupt 72 + DCD ADC0_IRQHandler ; ADC0 interrupt + DCD ADC1_IRQHandler ; ADC1 interrupt + DCD CMP0_IRQHandler ; CMP0 interrupt + DCD CMP1_IRQHandler ; CMP1 interrupt + DCD CMP2_IRQHandler ; CMP2 interrupt + DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt + DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt + DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt + DCD CMT_IRQHandler ; CMT interrupt + DCD RTC_IRQHandler ; RTC interrupt + DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt + DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt + DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt + DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt + DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt + DCD PDB0_IRQHandler ; PDB0 interrupt + DCD USB0_IRQHandler ; USB0 interrupt + DCD USBDCD_IRQHandler ; USBDCD interrupt + DCD Reserved91_IRQHandler ; Reserved interrupt 91 + DCD Reserved92_IRQHandler ; Reserved interrupt 92 + DCD Reserved93_IRQHandler ; Reserved interrupt 93 + DCD Reserved94_IRQHandler ; Reserved interrupt 94 + DCD Reserved95_IRQHandler ; Reserved interrupt 95 + DCD Reserved96_IRQHandler ; Reserved interrupt 96 + DCD DAC0_IRQHandler ; DAC0 interrupt + DCD Reserved98_IRQHandler ; Reserved interrupt 98 + DCD TSI0_IRQHandler ; TSI0 interrupt + DCD MCG_IRQHandler ; MCG interrupt + DCD LPTimer_IRQHandler ; LPTimer interrupt + DCD Reserved102_IRQHandler ; Reserved interrupt 102 + DCD PORTA_IRQHandler ; Port A interrupt + DCD PORTB_IRQHandler ; Port B interrupt + DCD PORTC_IRQHandler ; Port C interrupt + DCD PORTD_IRQHandler ; Port D interrupt + DCD PORTE_IRQHandler ; Port E interrupt + DCD Reserved108_IRQHandler ; Reserved interrupt 108 + DCD Reserved109_IRQHandler ; Reserved interrupt 109 + DCD SWI_IRQHandler ; Software interrupt +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; Flash Configuration +; 16-byte flash configuration field that stores default protection settings (loaded on reset) +; and security information that allows the MCU to restrict acces to the FTFL module. +; Backdoor Comparison Key +; Backdoor Key 0 <0x0-0xFF:2> +; Backdoor Key 1 <0x0-0xFF:2> +; Backdoor Key 2 <0x0-0xFF:2> +; Backdoor Key 3 <0x0-0xFF:2> +; Backdoor Key 4 <0x0-0xFF:2> +; Backdoor Key 5 <0x0-0xFF:2> +; Backdoor Key 6 <0x0-0xFF:2> +; Backdoor Key 7 <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; +; Program flash protection bytes (FPROT) +; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; Each bit protects a 1/32 region of the program flash memory. +; FPROT0 +; Program flash protection bytes +; 1/32 - 8/32 region +; FPROT0.0 +; FPROT0.1 +; FPROT0.2 +; FPROT0.3 +; FPROT0.4 +; FPROT0.5 +; FPROT0.6 +; FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; +; FPROT1 +; Program Flash Region Protect Register 1 +; 9/32 - 16/32 region +; FPROT1.0 +; FPROT1.1 +; FPROT1.2 +; FPROT1.3 +; FPROT1.4 +; FPROT1.5 +; FPROT1.6 +; FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; +; FPROT2 +; Program Flash Region Protect Register 2 +; 17/32 - 24/32 region +; FPROT2.0 +; FPROT2.1 +; FPROT2.2 +; FPROT2.3 +; FPROT2.4 +; FPROT2.5 +; FPROT2.6 +; FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; +; FPROT3 +; Program Flash Region Protect Register 3 +; 25/32 - 32/32 region +; FPROT3.0 +; FPROT3.1 +; FPROT3.2 +; FPROT3.3 +; FPROT3.4 +; FPROT3.5 +; FPROT3.6 +; FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; +; +; Data flash protection byte (FDPROT) +; Each bit protects a 1/8 region of the data flash memory. +; (Program flash only devices: Reserved) +; FDPROT.0 +; FDPROT.1 +; FDPROT.2 +; FDPROT.3 +; FDPROT.4 +; FDPROT.5 +; FDPROT.6 +; FDPROT.7 +nFDPROT EQU 0x00 +FDPROT EQU nFDPROT:EOR:0xFF +; +; EEPROM protection byte (FEPROT) +; FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. +; (Program flash only devices: Reserved) +; FEPROT.0 +; FEPROT.1 +; FEPROT.2 +; FEPROT.3 +; FEPROT.4 +; FEPROT.5 +; FEPROT.6 +; FEPROT.7 +nFEPROT EQU 0x00 +FEPROT EQU nFEPROT:EOR:0xFF +; +; Flash nonvolatile option byte (FOPT) +; Allows the user to customize the operation of the MCU at boot time. +; LPBOOT +; <0=> Low-power boot +; <1=> normal boot +; EZPORT_DIS +; <0=> EzPort operation is enabled +; <1=> EzPort operation is disabled +FOPT EQU 0xFF +; +; Flash security byte (FSEC) +; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; Flash Security +; This bits define the security state of the MCU. +; FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; Freescale Failure Analysis Access Code +; This bits define the security state of the MCU. +; MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; Mass Erase Enable Bits +; Enables and disables mass erase capability of the FTFL module +; KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; Backdoor key Security Enable +; These bits enable and disable backdoor key access to the FTFL module. +FSEC EQU 0xFE +; +; + IF :LNOT::DEF:RAM_TARGET + AREA |.ARM.__at_0x400|, CODE, READONLY + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0, FPROT1, FPROT2, FPROT3 + DCB FSEC, FOPT, FEPROT, FDPROT + ENDIF + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DMA0_IRQHandler [WEAK] + EXPORT DMA1_IRQHandler [WEAK] + EXPORT DMA2_IRQHandler [WEAK] + EXPORT DMA3_IRQHandler [WEAK] + EXPORT DMA4_IRQHandler [WEAK] + EXPORT DMA5_IRQHandler [WEAK] + EXPORT DMA6_IRQHandler [WEAK] + EXPORT DMA7_IRQHandler [WEAK] + EXPORT DMA8_IRQHandler [WEAK] + EXPORT DMA9_IRQHandler [WEAK] + EXPORT DMA10_IRQHandler [WEAK] + EXPORT DMA11_IRQHandler [WEAK] + EXPORT DMA12_IRQHandler [WEAK] + EXPORT DMA13_IRQHandler [WEAK] + EXPORT DMA14_IRQHandler [WEAK] + EXPORT DMA15_IRQHandler [WEAK] + EXPORT DMA_Error_IRQHandler [WEAK] + EXPORT Reserved33_IRQHandler [WEAK] + EXPORT FTFL_IRQHandler [WEAK] + EXPORT Read_Collision_IRQHandler [WEAK] + EXPORT LVD_LVW_IRQHandler [WEAK] + EXPORT LLW_IRQHandler [WEAK] + EXPORT Watchdog_IRQHandler [WEAK] + EXPORT Reserved39_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT Reserved44_IRQHandler [WEAK] + EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK] + EXPORT CAN0_Bus_Off_IRQHandler [WEAK] + EXPORT CAN0_Error_IRQHandler [WEAK] + EXPORT CAN0_Tx_Warning_IRQHandler [WEAK] + EXPORT CAN0_Rx_Warning_IRQHandler [WEAK] + EXPORT CAN0_Wake_Up_IRQHandler [WEAK] + EXPORT I2S0_Tx_IRQHandler [WEAK] + EXPORT I2S0_Rx_IRQHandler [WEAK] + EXPORT Reserved53_IRQHandler [WEAK] + EXPORT Reserved54_IRQHandler [WEAK] + EXPORT Reserved55_IRQHandler [WEAK] + EXPORT Reserved56_IRQHandler [WEAK] + EXPORT Reserved57_IRQHandler [WEAK] + EXPORT Reserved58_IRQHandler [WEAK] + EXPORT Reserved59_IRQHandler [WEAK] + EXPORT UART0_LON_IRQHandler [WEAK] + EXPORT UART0_RX_TX_IRQHandler [WEAK] + EXPORT UART0_ERR_IRQHandler [WEAK] + EXPORT UART1_RX_TX_IRQHandler [WEAK] + EXPORT UART1_ERR_IRQHandler [WEAK] + EXPORT UART2_RX_TX_IRQHandler [WEAK] + EXPORT UART2_ERR_IRQHandler [WEAK] + EXPORT Reserved67_IRQHandler [WEAK] + EXPORT Reserved68_IRQHandler [WEAK] + EXPORT Reserved69_IRQHandler [WEAK] + EXPORT Reserved70_IRQHandler [WEAK] + EXPORT Reserved71_IRQHandler [WEAK] + EXPORT Reserved72_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT FTM0_IRQHandler [WEAK] + EXPORT FTM1_IRQHandler [WEAK] + EXPORT FTM2_IRQHandler [WEAK] + EXPORT CMT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT PIT0_IRQHandler [WEAK] + EXPORT PIT1_IRQHandler [WEAK] + EXPORT PIT2_IRQHandler [WEAK] + EXPORT PIT3_IRQHandler [WEAK] + EXPORT PDB0_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT USBDCD_IRQHandler [WEAK] + EXPORT Reserved91_IRQHandler [WEAK] + EXPORT Reserved92_IRQHandler [WEAK] + EXPORT Reserved93_IRQHandler [WEAK] + EXPORT Reserved94_IRQHandler [WEAK] + EXPORT Reserved95_IRQHandler [WEAK] + EXPORT Reserved96_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT Reserved98_IRQHandler [WEAK] + EXPORT TSI0_IRQHandler [WEAK] + EXPORT MCG_IRQHandler [WEAK] + EXPORT LPTimer_IRQHandler [WEAK] + EXPORT Reserved102_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTB_IRQHandler [WEAK] + EXPORT PORTC_IRQHandler [WEAK] + EXPORT PORTD_IRQHandler [WEAK] + EXPORT PORTE_IRQHandler [WEAK] + EXPORT Reserved108_IRQHandler [WEAK] + EXPORT Reserved109_IRQHandler [WEAK] + EXPORT SWI_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] + +DMA0_IRQHandler +DMA1_IRQHandler +DMA2_IRQHandler +DMA3_IRQHandler +DMA4_IRQHandler +DMA5_IRQHandler +DMA6_IRQHandler +DMA7_IRQHandler +DMA8_IRQHandler +DMA9_IRQHandler +DMA10_IRQHandler +DMA11_IRQHandler +DMA12_IRQHandler +DMA13_IRQHandler +DMA14_IRQHandler +DMA15_IRQHandler +DMA_Error_IRQHandler +Reserved33_IRQHandler +FTFL_IRQHandler +Read_Collision_IRQHandler +LVD_LVW_IRQHandler +LLW_IRQHandler +Watchdog_IRQHandler +Reserved39_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +Reserved44_IRQHandler +CAN0_ORed_Message_buffer_IRQHandler +CAN0_Bus_Off_IRQHandler +CAN0_Error_IRQHandler +CAN0_Tx_Warning_IRQHandler +CAN0_Rx_Warning_IRQHandler +CAN0_Wake_Up_IRQHandler +I2S0_Tx_IRQHandler +I2S0_Rx_IRQHandler +Reserved53_IRQHandler +Reserved54_IRQHandler +Reserved55_IRQHandler +Reserved56_IRQHandler +Reserved57_IRQHandler +Reserved58_IRQHandler +Reserved59_IRQHandler +UART0_LON_IRQHandler +UART0_RX_TX_IRQHandler +UART0_ERR_IRQHandler +UART1_RX_TX_IRQHandler +UART1_ERR_IRQHandler +UART2_RX_TX_IRQHandler +UART2_ERR_IRQHandler +Reserved67_IRQHandler +Reserved68_IRQHandler +Reserved69_IRQHandler +Reserved70_IRQHandler +Reserved71_IRQHandler +Reserved72_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +FTM0_IRQHandler +FTM1_IRQHandler +FTM2_IRQHandler +CMT_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT0_IRQHandler +PIT1_IRQHandler +PIT2_IRQHandler +PIT3_IRQHandler +PDB0_IRQHandler +USB0_IRQHandler +USBDCD_IRQHandler +Reserved91_IRQHandler +Reserved92_IRQHandler +Reserved93_IRQHandler +Reserved94_IRQHandler +Reserved95_IRQHandler +Reserved96_IRQHandler +DAC0_IRQHandler +Reserved98_IRQHandler +TSI0_IRQHandler +MCG_IRQHandler +LPTimer_IRQHandler +Reserved102_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +Reserved108_IRQHandler +Reserved109_IRQHandler +SWI_IRQHandler +DefaultISR + + B . + + ENDP + + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..3296df1928 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2015 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld new file mode 100644 index 0000000000..71925fc817 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld @@ -0,0 +1,163 @@ +/* + * K20DX256 ARM GCC linker script file + */ + +MEMORY +{ + VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010 + FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x00000410 + RAM (rwx) : ORIGIN = 0x1FFF81C0, LENGTH = 64K - 0x1C0 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * _reset_init : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .isr_vector : + { + __vector_table = .; + KEEP(*(.vector_table)) + *(.text.Reset_Handler) + *(.text.System_Init) + . = ALIGN(4); + } > VECTORS + + .flash_protect : + { + KEEP(*(.kinetis_flash_config_field)) + . = ALIGN(4); + } > FLASH_PROTECTION + + .text : + { + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s new file mode 100644 index 0000000000..c2eaa33f46 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s @@ -0,0 +1,361 @@ +/* File: startup_MK20DX256.s + * Purpose: startup file for Cortex-M4 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.3 + * Date: 08 Feb 2012 + * + * Copyright (c) 2015, ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the ARM Limited nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x400 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0xC00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector + +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long DMA0_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA1_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA2_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA3_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA4_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA5_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA6_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA7_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA8_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA9_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA10_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA11_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA12_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA13_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA14_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA15_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA_Error_IRQHandler // DMA error interrupt + .long Reserved33_IRQHandler // Reserved interrupt 33 + .long FTFL_IRQHandler // FTFL interrupt + .long Read_Collision_IRQHandler // Read collision interrupt + .long LVD_LVW_IRQHandler // Low Voltage Detect, Low Voltage Warning + .long LLW_IRQHandler // Low Leakage Wakeup + .long Watchdog_IRQHandler // WDOG interrupt + .long Reserved39_IRQHandler // Reserved interrupt 39 + .long I2C0_IRQHandler // I2C0 interrupt + .long I2C1_IRQHandler // I2C1 interrupt + .long SPI0_IRQHandler // SPI0 interrupt + .long SPI1_IRQHandler // SPI1 interrupt + .long Reserved44_IRQHandler // Reserved interrupt 44 + .long CAN0_ORed_Message_buffer_IRQHandler // CAN0 OR'd message buffers interrupt + .long CAN0_Bus_Off_IRQHandler // CAN0 bus off interrupt + .long CAN0_Error_IRQHandler // CAN0 error interrupt + .long CAN0_Tx_Warning_IRQHandler // CAN0 Tx warning interrupt + .long CAN0_Rx_Warning_IRQHandler // CAN0 Rx warning interrupt + .long CAN0_Wake_Up_IRQHandler // CAN0 wake up interrupt + .long I2S0_Tx_IRQHandler // I2S0 transmit interrupt + .long I2S0_Rx_IRQHandler // I2S0 receive interrupt + .long Reserved53_IRQHandler // Reserved interrupt 53 + .long Reserved54_IRQHandler // Reserved interrupt 54 + .long Reserved55_IRQHandler // Reserved interrupt 55 + .long Reserved56_IRQHandler // Reserved interrupt 56 + .long Reserved57_IRQHandler // Reserved interrupt 57 + .long Reserved58_IRQHandler // Reserved interrupt 58 + .long Reserved59_IRQHandler // Reserved interrupt 59 + .long UART0_LON_IRQHandler // UART0 LON interrupt + .long UART0_RX_TX_IRQHandler // UART0 receive/transmit interrupt + .long UART0_ERR_IRQHandler // UART0 error interrupt + .long UART1_RX_TX_IRQHandler // UART1 receive/transmit interrupt + .long UART1_ERR_IRQHandler // UART1 error interrupt + .long UART2_RX_TX_IRQHandler // UART2 receive/transmit interrupt + .long UART2_ERR_IRQHandler // UART2 error interrupt + .long Reserved67_IRQHandler // Reserved interrupt 67 + .long Reserved68_IRQHandler // Reserved interrupt 68 + .long Reserved69_IRQHandler // Reserved interrupt 69 + .long Reserved70_IRQHandler // Reserved interrupt 70 + .long Reserved71_IRQHandler // Reserved interrupt 71 + .long Reserved72_IRQHandler // Reserved interrupt 72 + .long ADC0_IRQHandler // ADC0 interrupt + .long ADC1_IRQHandler // ADC1 interrupt + .long CMP0_IRQHandler // CMP0 interrupt + .long CMP1_IRQHandler // CMP1 interrupt + .long CMP2_IRQHandler // CMP2 interrupt + .long FTM0_IRQHandler // FTM0 fault, overflow and channels interrupt + .long FTM1_IRQHandler // FTM1 fault, overflow and channels interrupt + .long FTM2_IRQHandler // FTM2 fault, overflow and channels interrupt + .long CMT_IRQHandler // CMT interrupt + .long RTC_IRQHandler // RTC interrupt + .long RTC_Seconds_IRQHandler // RTC seconds interrupt + .long PIT0_IRQHandler // PIT timer channel 0 interrupt + .long PIT1_IRQHandler // PIT timer channel 1 interrupt + .long PIT2_IRQHandler // PIT timer channel 2 interrupt + .long PIT3_IRQHandler // PIT timer channel 3 interrupt + .long PDB0_IRQHandler // PDB0 interrupt + .long USB0_IRQHandler // USB0 interrupt + .long USBDCD_IRQHandler // USBDCD interrupt + .long Reserved91_IRQHandler // Reserved interrupt 91 + .long Reserved92_IRQHandler // Reserved interrupt 92 + .long Reserved93_IRQHandler // Reserved interrupt 93 + .long Reserved94_IRQHandler // Reserved interrupt 94 + .long Reserved95_IRQHandler // Reserved interrupt 95 + .long Reserved96_IRQHandler // Reserved interrupt 96 + .long DAC0_IRQHandler // DAC0 interrupt + .long Reserved98_IRQHandler // Reserved interrupt 98 + .long TSI0_IRQHandler // TSI0 interrupt + .long MCG_IRQHandler // MCG interrupt + .long LPTimer_IRQHandler // LPTimer interrupt + .long Reserved102_IRQHandler // Reserved interrupt 102 + .long PORTA_IRQHandler // Port A interrupt + .long PORTB_IRQHandler // Port B interrupt + .long PORTC_IRQHandler // Port C interrupt + .long PORTD_IRQHandler // Port D interrupt + .long PORTE_IRQHandler // Port E interrupt + .long Reserved108_IRQHandler // Reserved interrupt 108 + .long Reserved109_IRQHandler // Reserved interrupt 109 + .long SWI_IRQHandler // Software interrupt + + .size __isr_vector, . - __isr_vector + + .section .text.Reset_Handler + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.Lflash_to_ram_loop: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .Lflash_to_ram_loop + +.Lflash_to_ram_loop_end: + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + + def_irq_default_handler DMA0_IRQHandler + def_irq_default_handler DMA1_IRQHandler + def_irq_default_handler DMA2_IRQHandler + def_irq_default_handler DMA3_IRQHandler + def_irq_default_handler DMA4_IRQHandler + def_irq_default_handler DMA5_IRQHandler + def_irq_default_handler DMA6_IRQHandler + def_irq_default_handler DMA7_IRQHandler + def_irq_default_handler DMA8_IRQHandler + def_irq_default_handler DMA9_IRQHandler + def_irq_default_handler DMA10_IRQHandler + def_irq_default_handler DMA11_IRQHandler + def_irq_default_handler DMA12_IRQHandler + def_irq_default_handler DMA13_IRQHandler + def_irq_default_handler DMA14_IRQHandler + def_irq_default_handler DMA15_IRQHandler + def_irq_default_handler DMA_Error_IRQHandler + def_irq_default_handler Reserved33_IRQHandler + def_irq_default_handler FTFL_IRQHandler + def_irq_default_handler Read_Collision_IRQHandler + def_irq_default_handler LVD_LVW_IRQHandler + def_irq_default_handler LLW_IRQHandler + def_irq_default_handler Watchdog_IRQHandler + def_irq_default_handler Reserved39_IRQHandler + def_irq_default_handler I2C0_IRQHandler + def_irq_default_handler I2C1_IRQHandler + def_irq_default_handler SPI0_IRQHandler + def_irq_default_handler SPI1_IRQHandler + def_irq_default_handler Reserved44_IRQHandler + def_irq_default_handler CAN0_ORed_Message_buffer_IRQHandler + def_irq_default_handler CAN0_Bus_Off_IRQHandler + def_irq_default_handler CAN0_Error_IRQHandler + def_irq_default_handler CAN0_Tx_Warning_IRQHandler + def_irq_default_handler CAN0_Rx_Warning_IRQHandler + def_irq_default_handler CAN0_Wake_Up_IRQHandler + def_irq_default_handler I2S0_Tx_IRQHandler + def_irq_default_handler I2S0_Rx_IRQHandler + def_irq_default_handler Reserved53_IRQHandler + def_irq_default_handler Reserved54_IRQHandler + def_irq_default_handler Reserved55_IRQHandler + def_irq_default_handler Reserved56_IRQHandler + def_irq_default_handler Reserved57_IRQHandler + def_irq_default_handler Reserved58_IRQHandler + def_irq_default_handler Reserved59_IRQHandler + def_irq_default_handler UART0_LON_IRQHandler + def_irq_default_handler UART0_RX_TX_IRQHandler + def_irq_default_handler UART0_ERR_IRQHandler + def_irq_default_handler UART1_RX_TX_IRQHandler + def_irq_default_handler UART1_ERR_IRQHandler + def_irq_default_handler UART2_RX_TX_IRQHandler + def_irq_default_handler UART2_ERR_IRQHandler + def_irq_default_handler Reserved67_IRQHandler + def_irq_default_handler Reserved68_IRQHandler + def_irq_default_handler Reserved69_IRQHandler + def_irq_default_handler Reserved70_IRQHandler + def_irq_default_handler Reserved71_IRQHandler + def_irq_default_handler Reserved72_IRQHandler + def_irq_default_handler ADC0_IRQHandler + def_irq_default_handler ADC1_IRQHandler + def_irq_default_handler CMP0_IRQHandler + def_irq_default_handler CMP1_IRQHandler + def_irq_default_handler CMP2_IRQHandler + def_irq_default_handler FTM0_IRQHandler + def_irq_default_handler FTM1_IRQHandler + def_irq_default_handler FTM2_IRQHandler + def_irq_default_handler CMT_IRQHandler + def_irq_default_handler RTC_IRQHandler + def_irq_default_handler RTC_Seconds_IRQHandler + def_irq_default_handler PIT0_IRQHandler + def_irq_default_handler PIT1_IRQHandler + def_irq_default_handler PIT2_IRQHandler + def_irq_default_handler PIT3_IRQHandler + def_irq_default_handler PDB0_IRQHandler + def_irq_default_handler USB0_IRQHandler + def_irq_default_handler USBDCD_IRQHandler + def_irq_default_handler Reserved91_IRQHandler + def_irq_default_handler Reserved92_IRQHandler + def_irq_default_handler Reserved93_IRQHandler + def_irq_default_handler Reserved94_IRQHandler + def_irq_default_handler Reserved95_IRQHandler + def_irq_default_handler Reserved96_IRQHandler + def_irq_default_handler DAC0_IRQHandler + def_irq_default_handler Reserved98_IRQHandler + def_irq_default_handler TSI0_IRQHandler + def_irq_default_handler MCG_IRQHandler + def_irq_default_handler LPTimer_IRQHandler + def_irq_default_handler Reserved102_IRQHandler + def_irq_default_handler PORTA_IRQHandler + def_irq_default_handler PORTB_IRQHandler + def_irq_default_handler PORTC_IRQHandler + def_irq_default_handler PORTD_IRQHandler + def_irq_default_handler PORTE_IRQHandler + def_irq_default_handler Reserved108_IRQHandler + def_irq_default_handler Reserved109_IRQHandler + def_irq_default_handler SWI_IRQHandler + def_irq_default_handler DefaultISR + +/* Flash protection region, placed at 0x400 */ + .text + .thumb + .align 2 + .section .kinetis_flash_config_field,"a",%progbits +kinetis_flash_config: + .long 0xffffffff + .long 0xffffffff + .long 0xffffffff + .long 0xfffffffe + + .end diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis.h new file mode 100644 index 0000000000..86440692b3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis.h @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2015 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC11U24 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "MK20DX256.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.c new file mode 100644 index 0000000000..8148ba87ff --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.c @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2012 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x1FFF8000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + 16] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + 16]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.h new file mode 100644 index 0000000000..ce9de13c98 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.h @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2015 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS (16 + 95) // CORE + MCU Peripherals +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c new file mode 100644 index 0000000000..aa2158efce --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c @@ -0,0 +1,330 @@ +/* +** ################################################################### +** Compilers: ARM Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** +** +** Version: rev. 1.0, 2011-12-15 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2011-12-15) +** Initial version +** +** ################################################################### +*/ + +/** + * @file MK20DX256 + * @version 1.0 + * @date 2011-12-15 + * @brief Device specific configuration file for MK20DX256 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "MK20DX256.h" + +#define DISABLE_WDOG 1 + +#define CLOCK_SETUP 3 +/* Predefined clock setups + 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode + Reference clock source for MCG module is the slow internal clock source 32.768kHz + Core clock = 41.94MHz, BusClock = 41.94MHz + 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode + Reference clock source for MCG module is an external crystal 8MHz + Core clock = 48MHz, BusClock = 48MHz + 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode + Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication + Core clock = 8MHz, BusClock = 8MHz + 3 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode + Reference clock source for MCG module is an external crystal 16MHz + Core clock = 72MHz, BusClock = 48MHz + This is the Teensy3.1 72Mhz set up +*/ + +/*---------------------------------------------------------------------------- + Define clock source values + *----------------------------------------------------------------------------*/ +#if (CLOCK_SETUP == 0) + #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ + #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ + #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ + #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ + #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */ +#elif (CLOCK_SETUP == 1) + #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ + #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ + #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ + #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ + #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#elif (CLOCK_SETUP == 2) + #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ + #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ + #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ + #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ + #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */ +#elif (CLOCK_SETUP == 3) + #define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */ + #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ + #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ + #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ + #define DEFAULT_SYSTEM_CLOCK 72000000u /* Default System clock value */ +#endif /* (CLOCK_SETUP == 2) */ + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { +#if (DISABLE_WDOG) + /* Disable the WDOG module */ + /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */ + WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */ + /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */ + WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */ + /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ + WDOG->STCTRLH = (uint16_t)0x01D2u; +#endif /* (DISABLE_WDOG) */ +#if (CLOCK_SETUP == 0) + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ + SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* Switch to FEI Mode */ + /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x06u; + /* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x00u; + /* MCG_C4: DMX32=0,DRST_DRS=1 */ + MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u); + /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ + MCG->C5 = (uint8_t)0x00u; + /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x00u; + while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */ + } + while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */ + } +#elif (CLOCK_SETUP == 1) + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ + SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* Switch to FBE Mode */ + /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + OSC0->CR = (uint8_t)0x00u; + /* MCG->C7: OSCSEL=0 */ + MCG->C7 = (uint8_t)0x00u; + /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x24u; + /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x9Au; + /* MCG->C4: DMX32=0,DRST_DRS=0 */ + MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; + /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ + MCG->C5 = (uint8_t)0x03u; + /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x00u; + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ + } +#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ + while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ + } +#endif + while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ + } + /* Switch to PBE Mode */ + /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ + MCG->C5 = (uint8_t)0x03u; + /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x40u; + while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */ + } + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ + } + /* Switch to PEE Mode */ + /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x1Au; + while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */ + } + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ + } +#elif (CLOCK_SETUP == 2) + /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ + SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* Switch to FBE Mode */ + /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + OSC0->CR = (uint8_t)0x00u; + /* MCG->C7: OSCSEL=0 */ + MCG->C7 = (uint8_t)0x00u; + /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x24u; + /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x9Au; + /* MCG->C4: DMX32=0,DRST_DRS=0 */ + MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; + /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ + MCG->C5 = (uint8_t)0x00u; + /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x00u; + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ + } +#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ + while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ + } +#endif + while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ + } + /* Switch to BLPE Mode */ + /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x24u; + +#elif (CLOCK_SETUP == 3) + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ + SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* Switch to FBE Mode */ + /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + OSC0->CR = (uint8_t)0x0Au; // this is required if there are no external capacitors fitted to the Xtal + /* MCG->C7: OSCSEL=0 */ + MCG->C7 = (uint8_t)0x00u; + /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x24u; + /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x9Au; + /* MCG->C4: DMX32=0,DRST_DRS=0 */ + MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; + /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ + MCG->C5 = (uint8_t)0x07u; + /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x00u; + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ + } +#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ + while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ + } +#endif + while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ + } + /* Switch to PBE Mode */ + /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ + MCG->C5 = (uint8_t)0x05u; + /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x43u; + while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */ + } + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ + } + /* Switch to PEE Mode */ + /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x22u; + while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */ + } + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ + } + +#endif /* (CLOCK_SETUP == 3) */ +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ + uint8_t Divider; + + if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { + /* Output of FLL or PLL is selected */ + if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { + /* FLL is selected */ + if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { + /* External reference clock is selected */ + if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ + Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ + if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) { + MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */ + } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */ + } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ + } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ + /* Select correct multiplier to calculate the MCG output clock */ + switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { + case 0x0u: + MCGOUTClock *= 640u; + break; + case 0x20u: + MCGOUTClock *= 1280u; + break; + case 0x40u: + MCGOUTClock *= 1920u; + break; + case 0x60u: + MCGOUTClock *= 2560u; + break; + case 0x80u: + MCGOUTClock *= 732u; + break; + case 0xA0u: + MCGOUTClock *= 1464u; + break; + case 0xC0u: + MCGOUTClock *= 2197u; + break; + case 0xE0u: + MCGOUTClock *= 2929u; + break; + default: + break; + } + } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ + /* PLL is selected */ + Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); + MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ + Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); + MCGOUTClock *= Divider; /* Calculate the MCG output clock */ + } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) { + /* Internal reference clock is selected */ + if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) { + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ + } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ + MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */ + } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) { + /* External reference clock is selected */ + if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ + } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ + /* Reserved value */ + return; + } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ + SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.h new file mode 100644 index 0000000000..3c916d0389 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.h @@ -0,0 +1,85 @@ +/* +** ################################################################### +** Compilers: ARM Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** +** +** Version: rev. 2.0, 2012-03-19 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2011-12-15) +** Initial version +** - rev. 2.0 (2012-03-19) +** PDB Peripheral register structure updated. +** DMA Registers and bits for unsupported DMA channels removed. +** +** ################################################################### +*/ + +/** + * @file MK20DX256 + * @version 2.0 + * @date 2012-03-19 + * @brief Device specific configuration file for MK20DX256 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef SYSTEM_MK20DX256_H_ +#define SYSTEM_MK20DX256_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* #if !defined(SYSTEM_MK20DX256_H_) */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/PeripheralPins.h new file mode 100644 index 0000000000..d6b5cfbfd9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/PeripheralPins.h @@ -0,0 +1,46 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************DAC***************/ +extern const PinMap PinMap_DAC[]; + +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/PortNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/PortNames.h similarity index 95% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/PortNames.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/PortNames.h index 476845b76d..12ef064790 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/PortNames.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/PortNames.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/PeripheralNames.h similarity index 95% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/PeripheralNames.h index 9253890e04..6984d1bc2a 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/PeripheralNames.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -62,11 +62,6 @@ typedef enum { ADC0_SE15 = 15 } ADCName; -typedef enum { - DAC_0 = 0 -} DACName; - - typedef enum { SPI_0 = (int)SPI0_BASE, } SPIName; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/PeripheralPins.c new file mode 100644 index 0000000000..8981f6d371 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/PeripheralPins.c @@ -0,0 +1,120 @@ + +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {PTC2, ADC0_SE4b, 0}, + {PTD1, ADC0_SE5b, 0}, + {PTD5, ADC0_SE6b, 0}, + {PTD6, ADC0_SE7b, 0}, + {PTB0, ADC0_SE8, 0}, + {PTB1, ADC0_SE9, 0}, + {PTB2, ADC0_SE12, 0}, + {PTB3, ADC0_SE13, 0}, + {PTC0, ADC0_SE14, 0}, + {PTC1, ADC0_SE15, 0}, + {NC, NC, 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {PTB1, I2C_0, 2}, + {PTB3, I2C_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PTB0, I2C_0, 2}, + {PTB2, I2C_0, 2}, + {NC , NC, 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {PTB17, UART_0, 3}, + {PTC4 , UART_1, 3}, + {PTD3 , UART_2, 3}, + {PTD7 , UART_0, 3}, + {PTE0 , UART_1, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PTB16, UART_0, 3}, + {PTC3 , UART_1, 3}, + {PTD2 , UART_2, 3}, + {PTD6 , UART_0, 3}, + {PTE1 , UART_1, 3}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {PTC5, SPI_0, 2}, + {PTD1, SPI_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PTD2, SPI_0, 2}, + {PTC6, SPI_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PTD3, SPI_0, 2}, + {PTC7, SPI_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PTD0, SPI_0, 2}, + {PTC4, SPI_0, 2}, + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + // LEDs + {LED_RED , PWM_3 , 4}, // PTC3, FTM0 CH2 + {LED_GREEN, PWM_5, 4}, // PTD4, FTM0 CH4 + {LED_BLUE , PWM_8 , 3}, // PTA2, FTM0 CH7 + + // Arduino digital pinout + {D3, PWM_5 , 4}, // PTD4, FTM0 CH4 + {D5, PWM_7 , 3}, // PTA1, FTM0 CH6 + {D6, PWM_3 , 4}, // PTC3, FTM0 CH2 + {D9, PWM_6 , 4}, // PTD5, FTM0 CH6 + {D10, PWM_2 , 4}, // PTC2, FTM0 CH1 + + {PTA0, PWM_6 , 3}, // PTA0, FTM0 CH5 + {PTA3, PWM_1 , 3}, // PTA3, FTM0 CH0 + {PTA4, PWM_2 , 3}, // PTA4, FTM0 CH1 + {PTA5, PWM_3 , 3}, // PTA5, FTM0 CH2 + {PTA12, PWM_9 , 3}, // PTA12, FTM1 CH0 + {PTA13, PWM_10, 3}, // PTA13, FTM1 CH1 + {PTB0, PWM_9 , 3}, // PTB0, FTM1 CH0 + {PTB1, PWM_10, 3}, // PTB1, FTM1 CH1 + {PTC1, PWM_1 , 4}, // PTC1, FTM0 CH0 + {PTD4, PWM_4 , 4}, // PTD4, FTM0 CH3 + {PTD6, PWM_7 , 4}, // PTD6, FTM0 CH6 + {PTD7, PWM_8 , 4}, // PTD7, FTM0 CH7 + + {NC , NC , 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/PinNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/PinNames.h similarity index 99% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/PinNames.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/PinNames.h index f9c8ff93f2..7bba6da7ea 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/PinNames.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/device.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/device.h similarity index 97% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/device.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/device.h index 6a6d5cae5b..220ba743f4 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/device.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/device.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralNames.h new file mode 100644 index 0000000000..3cbb1530a9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralNames.h @@ -0,0 +1,86 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)UART0_BASE, + UART_1 = (int)UART1_BASE, + UART_2 = (int)UART2_BASE +} UARTName; +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +typedef enum { + I2C_0 = (int)I2C0_BASE, + I2C_1 = (int)I2C1_BASE, +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 + PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 + PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 + PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 + PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 +} PWMName; + +typedef enum { + ADC0_SE4b = 4, + ADC0_SE5b = 5, + ADC0_SE6b = 6, + ADC0_SE7b = 7, + ADC0_SE8 = 8, + ADC0_SE9 = 9, + ADC0_SE12 = 12, + ADC0_SE13 = 13, + ADC0_SE14 = 14, + ADC0_SE15 = 15, + ADC1_SE4b = 16, + ADC1_SE5b = 17, + ADC1_SE6b = 18, + ADC1_SE7b = 19, +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + +typedef enum { + SPI_0 = (int)SPI0_BASE, + SPI_1 = (int)SPI0_BASE, + SPI_2 = (int)SPI0_BASE, + SPI_3 = (int)SPI0_BASE, + SPI_4 = (int)SPI0_BASE, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralPins.c new file mode 100644 index 0000000000..90a5b1eadb --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralPins.c @@ -0,0 +1,137 @@ + +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {PTC2, ADC0_SE4b, 0}, + {PTD1, ADC0_SE5b, 0}, + {PTD5, ADC0_SE6b, 0}, + {PTD6, ADC0_SE7b, 0}, + {PTB0, ADC0_SE8, 0}, + {PTB1, ADC0_SE9, 0}, + {PTB2, ADC0_SE12, 0}, + {PTB3, ADC0_SE13, 0}, + {PTC0, ADC0_SE14, 0}, + {PTC1, ADC0_SE15, 0}, + {PTC8, ADC1_SE4b, 0}, + {PTC9, ADC1_SE5b, 0}, + {PTC10,ADC1_SE6b, 0}, + {PTC11,ADC1_SE7b, 0}, + {NC, NC, 0} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {DAC0_OUT, DAC_0, 0}, + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {PTB1, I2C_0, 2}, + {PTB3, I2C_0, 2}, + {PTE0, I2C_1, 2}, + {PTC11, I2C_1, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PTB0, I2C_0, 2}, + {PTB2, I2C_0, 2}, + {PTE1, I2C_1, 2}, + {PTC10, I2C_1, 2}, + {NC , NC, 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {PTB17, UART_0, 3}, + {PTC4 , UART_1, 3}, + {PTD3 , UART_2, 3}, + {PTD7 , UART_0, 3}, + {PTE0 , UART_1, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PTB16, UART_0, 3}, + {PTC3 , UART_1, 3}, + {PTD2 , UART_2, 3}, + {PTD6 , UART_0, 3}, + {PTE1 , UART_1, 3}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { // SCK + {PTC5, SPI_0, 2}, + {PTD1, SPI_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { // DOUT + {PTD2, SPI_0, 2}, + {PTC6, SPI_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { // DIN + {PTD3, SPI_0, 2}, + {PTC7, SPI_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { // CS + {PTD0, SPI_0, 2}, + {PTC4, SPI_0, 2}, + {PTD4, SPI_0, 2}, + {PTC3, SPI_0, 2}, + {PTC2, SPI_0, 2}, + {PTD5, SPI_0, 2}, + {PTD6, SPI_0, 2}, + {PTC1, SPI_0, 2}, + {PTC0, SPI_0, 2} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + // LEDs + {LED_RED , PWM_3 , 4}, // PTC3, FTM0 CH2 + {LED_GREEN, PWM_5, 4}, // PTD4, FTM0 CH4 + {LED_BLUE , PWM_8 , 3}, // PTA2, FTM0 CH7 + + {PTA0, PWM_6 , 3}, // PTA0, FTM0 CH5 + {PTA1, PWM_7 , 3}, // PTA1, FTM0 CH6 + {PTA3, PWM_1 , 3}, // PTA3, FTM0 CH0 + {PTA4, PWM_2 , 3}, // PTA4, FTM0 CH1 + {PTA5, PWM_3 , 3}, // PTA5, FTM0 CH2 + {PTA12, PWM_9 , 3}, // PTA12, FTM1 CH0 + {PTA13, PWM_10, 3}, // PTA13, FTM1 CH1 + {PTB0, PWM_9 , 3}, // PTB0, FTM1 CH0 + {PTB1, PWM_10, 3}, // PTB1, FTM1 CH1 + {PTC1, PWM_1 , 4}, // PTC1, FTM0 CH0 + {PTC2, PWM_2 , 4}, // PTC2, FTM0 CH1 + {PTC3, PWM_3 , 4}, // PTC3, FTM0 CH2 + {PTD4, PWM_4 , 4}, // PTD4, FTM0 CH3 + {PTD5, PWM_6 , 4}, // PTD5, FTM0 CH6 + {PTD6, PWM_7 , 4}, // PTD6, FTM0 CH6 + {PTD7, PWM_8 , 4}, // PTD7, FTM0 CH7 + + {NC , NC , 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h new file mode 100644 index 0000000000..024a276909 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h @@ -0,0 +1,293 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +/* PCR - 0x1000 */ +#define PORT_SHIFT 12 + +typedef enum { + PTA0 = 0x0, + PTA1 = 0x4, + PTA2 = 0x8, + PTA3 = 0xc, + PTA4 = 0x10, + PTA5 = 0x14, + PTA6 = 0x18, + PTA7 = 0x1c, + PTA8 = 0x20, + PTA9 = 0x24, + PTA10 = 0x28, + PTA11 = 0x2c, + PTA12 = 0x30, + PTA13 = 0x34, + PTA14 = 0x38, + PTA15 = 0x3c, + PTA16 = 0x40, + PTA17 = 0x44, + PTA18 = 0x48, + PTA19 = 0x4c, + PTA20 = 0x50, + PTA21 = 0x54, + PTA22 = 0x58, + PTA23 = 0x5c, + PTA24 = 0x60, + PTA25 = 0x64, + PTA26 = 0x68, + PTA27 = 0x6c, + PTA28 = 0x70, + PTA29 = 0x74, + PTA30 = 0x78, + PTA31 = 0x7c, + PTB0 = 0x1000, + PTB1 = 0x1004, + PTB2 = 0x1008, + PTB3 = 0x100c, + PTB4 = 0x1010, + PTB5 = 0x1014, + PTB6 = 0x1018, + PTB7 = 0x101c, + PTB8 = 0x1020, + PTB9 = 0x1024, + PTB10 = 0x1028, + PTB11 = 0x102c, + PTB12 = 0x1030, + PTB13 = 0x1034, + PTB14 = 0x1038, + PTB15 = 0x103c, + PTB16 = 0x1040, + PTB17 = 0x1044, + PTB18 = 0x1048, + PTB19 = 0x104c, + PTB20 = 0x1050, + PTB21 = 0x1054, + PTB22 = 0x1058, + PTB23 = 0x105c, + PTB24 = 0x1060, + PTB25 = 0x1064, + PTB26 = 0x1068, + PTB27 = 0x106c, + PTB28 = 0x1070, + PTB29 = 0x1074, + PTB30 = 0x1078, + PTB31 = 0x107c, + PTC0 = 0x2000, + PTC1 = 0x2004, + PTC2 = 0x2008, + PTC3 = 0x200c, + PTC4 = 0x2010, + PTC5 = 0x2014, + PTC6 = 0x2018, + PTC7 = 0x201c, + PTC8 = 0x2020, + PTC9 = 0x2024, + PTC10 = 0x2028, + PTC11 = 0x202c, + PTC12 = 0x2030, + PTC13 = 0x2034, + PTC14 = 0x2038, + PTC15 = 0x203c, + PTC16 = 0x2040, + PTC17 = 0x2044, + PTC18 = 0x2048, + PTC19 = 0x204c, + PTC20 = 0x2050, + PTC21 = 0x2054, + PTC22 = 0x2058, + PTC23 = 0x205c, + PTC24 = 0x2060, + PTC25 = 0x2064, + PTC26 = 0x2068, + PTC27 = 0x206c, + PTC28 = 0x2070, + PTC29 = 0x2074, + PTC30 = 0x2078, + PTC31 = 0x207c, + PTD0 = 0x3000, + PTD1 = 0x3004, + PTD2 = 0x3008, + PTD3 = 0x300c, + PTD4 = 0x3010, + PTD5 = 0x3014, + PTD6 = 0x3018, + PTD7 = 0x301c, + PTD8 = 0x3020, + PTD9 = 0x3024, + PTD10 = 0x3028, + PTD11 = 0x302c, + PTD12 = 0x3030, + PTD13 = 0x3034, + PTD14 = 0x3038, + PTD15 = 0x303c, + PTD16 = 0x3040, + PTD17 = 0x3044, + PTD18 = 0x3048, + PTD19 = 0x304c, + PTD20 = 0x3050, + PTD21 = 0x3054, + PTD22 = 0x3058, + PTD23 = 0x305c, + PTD24 = 0x3060, + PTD25 = 0x3064, + PTD26 = 0x3068, + PTD27 = 0x306c, + PTD28 = 0x3070, + PTD29 = 0x3074, + PTD30 = 0x3078, + PTD31 = 0x307c, + PTE0 = 0x4000, + PTE1 = 0x4004, + PTE2 = 0x4008, + PTE3 = 0x400c, + PTE4 = 0x4010, + PTE5 = 0x4014, + PTE6 = 0x4018, + PTE7 = 0x401c, + PTE8 = 0x4020, + PTE9 = 0x4024, + PTE10 = 0x4028, + PTE11 = 0x402c, + PTE12 = 0x4030, + PTE13 = 0x4034, + PTE14 = 0x4038, + PTE15 = 0x403c, + PTE16 = 0x4040, + PTE17 = 0x4044, + PTE18 = 0x4048, + PTE19 = 0x404c, + PTE20 = 0x4050, + PTE21 = 0x4054, + PTE22 = 0x4058, + PTE23 = 0x405c, + PTE24 = 0x4060, + PTE25 = 0x4064, + PTE26 = 0x4068, + PTE27 = 0x406c, + PTE28 = 0x4070, + PTE29 = 0x4074, + PTE30 = 0x4078, + PTE31 = 0x407c, + + LED_RED = PTC5, // set these to the only led on board + LED_GREEN = PTC5, // + LED_BLUE = PTC5, // + + // mbed original LED naming + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_BLUE, + + // USB Pins + USBTX = PTB17, + USBRX = PTB16, + + // DAC Pins + DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */ + + // Teensy3.1 Headers + p0 = PTB16, + p1 = PTB17, + p2 = PTD0, + p3 = PTA12, + p4 = PTA13, + p5 = PTD7, + p6 = PTD4, + p7 = PTD2, + p8 = PTD3, + p9 = PTC3, + p10 = PTC4, + p11 = PTC6, + p12 = PTC7, + p13 = PTC5, + p14 = PTD1, + p15 = PTC0, + p16 = PTB0, + p17 = PTB1, + p18 = PTB3, + p19 = PTB2, + p20 = PTD5, + p21 = PTD6, + p22 = PTC1, + p23 = PTC2, + p24 = PTA5, + p25 = PTD19, + p26 = PTE1, + p27 = PTC9, + p28 = PTC8, + p29 = PTC10, + p30 = PTC11, + p31 = PTE0, + p32 = PTB18, + p33 = PTA4, + + A0 = PTD1, + A1 = PTC0, + A2 = PTB0, + A3 = PTB1, + A4 = PTB3, + A5 = PTB2, + A6 = PTD5, + A7 = PTD6, + A8 = PTC1, + A9 = PTC2, + + I2C_SCL = PTB3, + I2C_SDA = PTB2, + + SPI_SCK = PTC5, // sclk + SPI_DOUT = PTC6, // mosi + SPI_DIN = PTC7, // miso + SPI_CS = PTC4, // ssel + + SERIAL_TX = PTB17, + SERIAL_RX = PTB16, + + PWM = PTD7, + + DAC = DAC0_OUT, + + TSI_ELEC0 = PTC1, + TSI_ELEC1 = PTC2, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 2, + PullUp = 3, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device.h new file mode 100644 index 0000000000..23dd0c0a46 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device.h @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 1 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 1 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/analogin_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/analogin_api.c similarity index 87% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/analogin_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/analogin_api.c index 62e3289ea1..473c5d0394 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/analogin_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -19,23 +19,10 @@ #include "cmsis.h" #include "pinmap.h" #include "clk_freqs.h" +#include "PeripheralPins.h" #define MAX_FADC 6000000 -static const PinMap PinMap_ADC[] = { - {PTC2, ADC0_SE4b, 0}, - {PTD1, ADC0_SE5b, 0}, - {PTD5, ADC0_SE6b, 0}, - {PTD6, ADC0_SE7b, 0}, - {PTB0, ADC0_SE8, 0}, - {PTB1, ADC0_SE9, 0}, - {PTB2, ADC0_SE12, 0}, - {PTB3, ADC0_SE13, 0}, - {PTC0, ADC0_SE14, 0}, - {PTC1, ADC0_SE15, 0}, - {NC, NC, 0} -}; - void analogin_init(analogin_t *obj, PinName pin) { obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); MBED_ASSERT(obj->adc != (ADCName)NC); @@ -90,4 +77,3 @@ float analogin_read(analogin_t *obj) { uint16_t value = analogin_read_u16(obj); return (float)value * (1.0f / (float)0xFFFF); } - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/analogout_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/analogout_api.c new file mode 100644 index 0000000000..9e3c4c0c25 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/analogout_api.c @@ -0,0 +1,84 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_assert.h" +#include "analogout_api.h" + +#if DEVICE_ANALOGOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +#define RANGE_12BIT 0xFFF + +void analogout_init(dac_t *obj, PinName pin) { + obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); + MBED_ASSERT(obj->dac != (DACName)NC); + + SIM->SCGC2 |= SIM_SCGC2_DAC0_MASK; + + uint32_t port = (uint32_t)pin >> PORT_SHIFT; + SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port); + + DAC0->DAT[obj->dac].DATH = 0; + DAC0->DAT[obj->dac].DATL = 0; + + DAC0->C1 = DAC_C1_DACBFMD_MASK; // One-Time Scan Mode + + DAC0->C0 = DAC_C0_DACEN_MASK // Enable + | DAC_C0_DACSWTRG_MASK // Software Trigger + | DAC_C0_DACRFS_MASK; // VDDA selected + + analogout_write_u16(obj, 0); +} + +void analogout_free(dac_t *obj) {} + +static inline void dac_write(dac_t *obj, int value) { + DAC0->DAT[obj->dac].DATL = (uint8_t)( value & 0xFF); + DAC0->DAT[obj->dac].DATH = (uint8_t)((value >> 8) & 0xFF); +} + +static inline int dac_read(dac_t *obj) { + return ((DAC0->DAT[obj->dac].DATH << 8) | DAC0->DAT[obj->dac].DATL); +} + +void analogout_write(dac_t *obj, float value) { + if (value < 0.0) { + dac_write(obj, 0); + } else if (value > 1.0) { + dac_write(obj, RANGE_12BIT); + } else { + dac_write(obj, value * (float)RANGE_12BIT); + } +} + +void analogout_write_u16(dac_t *obj, uint16_t value) { + dac_write(obj, value >> 4); // 12-bit +} + +float analogout_read(dac_t *obj) { + uint32_t value = dac_read(obj); + return (float)value * (1.0f / (float)RANGE_12BIT); +} + +uint16_t analogout_read_u16(dac_t *obj) { + uint32_t value = dac_read(obj); // 12-bit + return (value << 4) | ((value >> 8) & 0x003F); +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/clk_freqs.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/clk_freqs.h similarity index 99% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/clk_freqs.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/clk_freqs.h index 2a2f5dc774..86d2076232 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/clk_freqs.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/clk_freqs.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_api.c similarity index 97% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_api.c index 77a8d21cbc..952412cbdc 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_irq_api.c similarity index 99% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_irq_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_irq_api.c index 05f3bea5fd..ab3d58654c 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_irq_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_irq_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_object.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_object.h similarity index 96% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_object.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_object.h index ca2c0d64f8..81ea007d59 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_object.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -25,7 +25,6 @@ extern "C" { typedef struct { PinName pin; uint32_t mask; - __IO uint32_t *reg_dir; __IO uint32_t *reg_set; __IO uint32_t *reg_clr; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/i2c_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/i2c_api.c similarity index 95% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/i2c_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/i2c_api.c index b2801bbd7c..df1aa5c18d 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/i2c_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -19,18 +19,7 @@ #include "cmsis.h" #include "pinmap.h" #include "clk_freqs.h" - -static const PinMap PinMap_I2C_SDA[] = { - {PTB1, I2C_0, 2}, - {PTB3, I2C_0, 2}, - {NC , NC , 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {PTB0, I2C_0, 2}, - {PTB2, I2C_0, 2}, - {NC , NC, 0} -}; +#include "PeripheralPins.h" static const uint16_t ICR[0x40] = { 20, 22, 24, 26, 28, @@ -54,10 +43,16 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) { I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); obj->i2c = (I2C_Type*)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT((int)obj->i2c != NC); - - SIM->SCGC4 |= SIM_SCGC4_I2C0_MASK; - SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK; + MBED_ASSERT((int)obj->i2c != NC); + +#if defined(TARGET_K20DX256) + switch ((int)obj->i2c) { + case I2C_0: SIM->SCGC4 |= SIM_SCGC4_I2C0_MASK; + case I2C_1: SIM->SCGC4 |= SIM_SCGC4_I2C1_MASK; + } +#else + SIM->SCGC4 |= SIM_SCGC4_I2C0_MASK; +#endif // set default frequency at 100k i2c_frequency(obj, 100000); @@ -381,4 +376,3 @@ void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { obj->i2c->A1 = address & 0xfe; } #endif - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/objects.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/objects.h similarity index 92% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/objects.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/objects.h index 257bc5c802..edf5aaa6ce 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/objects.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/objects.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -54,6 +54,12 @@ struct analogin_s { ADCName adc; }; +#if DEVICE_ANALOGOUT +struct dac_s { + DACName dac; +}; +#endif + struct i2c_s { I2C_Type *i2c; }; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/pinmap.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/pinmap.c similarity index 97% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/pinmap.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/pinmap.c index 89f83c2cd9..2971f9241e 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/pinmap.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/pinmap.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/port_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/port_api.c similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/port_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/port_api.c index 7a25a3b525..27cfdfd8b4 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/port_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/port_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/pwmout_api.c similarity index 75% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/pwmout_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/pwmout_api.c index 0966e2d795..fa318980aa 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/pwmout_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,35 +18,7 @@ #include "cmsis.h" #include "pinmap.h" - -static const PinMap PinMap_PWM[] = { - // LEDs - {LED_RED , PWM_3 , 4}, // PTC3, FTM0 CH2 - {LED_GREEN, PWM_5, 4}, // PTD4, FTM0 CH4 - {LED_BLUE , PWM_8 , 3}, // PTA2, FTM0 CH7 - - // Arduino digital pinout - {D3, PWM_5 , 4}, // PTD4, FTM0 CH4 - {D5, PWM_7 , 3}, // PTA1, FTM0 CH6 - {D6, PWM_3 , 4}, // PTC3, FTM0 CH2 - {D9, PWM_6 , 4}, // PTD5, FTM0 CH6 - {D10, PWM_2 , 4}, // PTC2, FTM0 CH1 - - {PTA0, PWM_6 , 3}, // PTA0, FTM0 CH5 - {PTA3, PWM_1 , 3}, // PTA3, FTM0 CH0 - {PTA4, PWM_2 , 3}, // PTA4, FTM0 CH1 - {PTA5, PWM_3 , 3}, // PTA5, FTM0 CH2 - {PTA12, PWM_9 , 3}, // PTA12, FTM1 CH0 - {PTA13, PWM_10, 3}, // PTA13, FTM1 CH1 - {PTB0, PWM_9 , 3}, // PTB0, FTM1 CH0 - {PTB1, PWM_10, 3}, // PTB1, FTM1 CH1 - {PTC1, PWM_1 , 4}, // PTC1, FTM0 CH0 - {PTD4, PWM_4 , 4}, // PTD4, FTM0 CH3 - {PTD6, PWM_7 , 4}, // PTD6, FTM0 CH6 - {PTD7, PWM_8 , 4}, // PTD7, FTM0 CH7 - - {NC , NC , 0} -}; +#include "PeripheralPins.h" static float pwm_clock = 0; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/rtc_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/rtc.api.c similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/rtc_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/rtc.api.c index a61141a129..459c7b691a 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/rtc_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/rtc.api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/serial_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/serial_api.c similarity index 95% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/serial_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/serial_api.c index 6cee6bb898..87e2c5a7e2 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/serial_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -21,24 +21,7 @@ #include "cmsis.h" #include "pinmap.h" #include "clk_freqs.h" - -static const PinMap PinMap_UART_TX[] = { - {PTB17, UART_0, 3}, - {PTC4 , UART_1, 3}, - {PTD3 , UART_2, 3}, - {PTD7 , UART_0, 3}, - {PTE0 , UART_1, 3}, - {NC , NC , 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {PTB16, UART_0, 3}, - {PTC3 , UART_1, 3}, - {PTD2 , UART_2, 3}, - {PTD6 , UART_0, 3}, - {PTE1 , UART_1, 3}, - {NC , NC , 0} -}; +#include "PeripheralPins.h" #define UART_NUM 3 @@ -316,4 +299,3 @@ void serial_break_set(serial_t *obj) { void serial_break_clear(serial_t *obj) { obj->uart->C2 &= ~UART_C2_SBK_MASK; } - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/sleep.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c similarity index 97% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/sleep.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c index 3fcffd4fbd..b5e8df31de 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/sleep.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/spi_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/spi_api.c similarity index 91% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/spi_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/spi_api.c index 49746e6d5f..5f1313b131 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/spi_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2013 ARM Limited + * Copyright (c) 2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -21,30 +21,7 @@ #include "cmsis.h" #include "pinmap.h" #include "clk_freqs.h" - -static const PinMap PinMap_SPI_SCLK[] = { - {PTC5, SPI_0, 2}, - {PTD1, SPI_0, 2}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {PTD2, SPI_0, 2}, - {PTC6, SPI_0, 2}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {PTD3, SPI_0, 2}, - {PTC7, SPI_0, 2}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {PTD0, SPI_0, 2}, - {PTC4, SPI_0, 2}, - {NC , NC , 0} -}; +#include "PeripheralPins.h" void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { // determine the SPI to use diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/us_ticker.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/us_ticker.c similarity index 99% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/us_ticker.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/us_ticker.c index 4d62e8d37a..93a1512b50 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/us_ticker.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 62a57ad5b9..6b39a09161 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -52,6 +52,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('K64F', ('ARM', 'GCC_ARM', 'IAR')), ('K22F', ('ARM', 'GCC_ARM', 'IAR')), ('K20D50M', ('ARM', 'GCC_ARM' , 'IAR')), + ('TEENSY3_1', ('ARM', 'GCC_ARM')), ('NUCLEO_F030R8', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('NUCLEO_F070RB', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), diff --git a/workspace_tools/build_travis.py b/workspace_tools/build_travis.py index b62c83f110..e33c4606a9 100644 --- a/workspace_tools/build_travis.py +++ b/workspace_tools/build_travis.py @@ -63,6 +63,7 @@ build_list = ( { "target": "KL43Z", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] }, { "target": "KL46Z", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] }, { "target": "K20D50M", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "TEENSY3_1", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, { "target": "K64F", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] }, { "target": "LPC4088", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] }, { "target": "ARCH_PRO", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index d6769343ed..f11d2cb6d8 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -380,10 +380,34 @@ class K20D50M(Target): def __init__(self): Target.__init__(self) self.core = "Cortex-M4" - self.extra_labels = ['Freescale'] + self.extra_labels = ['Freescale', 'K20XX'] self.supported_toolchains = ["GCC_ARM", "ARM", "IAR"] self.is_disk_virtual = True self.detect_code = ["0230"] + +class TEENSY3_1(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4" + self.extra_labels = ['Freescale', 'K20XX', 'K20DX256'] + self.supported_toolchains = ["GCC_ARM", "ARM"] + self.is_disk_virtual = True + self.detect_code = ["0230"] + + OUTPUT_EXT = '.hex' + + def init_hooks(self, hook, toolchain_name): + if toolchain_name in ['ARM_STD', 'ARM_MICRO', 'GCC_ARM']: + hook.hook_add_binary("post", self.binary_hook) + + @staticmethod + def binary_hook(t_self, resources, elf, binf): + from intelhex import IntelHex + binh = IntelHex() + binh.loadbin(binf, offset = 0) + + with open(binf.replace(".bin", ".hex"), "w") as f: + binh.tofile(f, format='hex') class K22F(Target): def __init__(self): @@ -876,6 +900,7 @@ TARGETS = [ KL43Z(), KL46Z(), K20D50M(), + TEENSY3_1(), K22F(), K64F(), MTS_GAMBIT(), # FRDM K64F From 6606e3e3cb85a4724313865ea36d5ee5f1fb3d60 Mon Sep 17 00:00:00 2001 From: Austin Blackstone Date: Thu, 15 Jan 2015 18:01:28 -0600 Subject: [PATCH 25/77] added README.html to every offline export. This will redirect to a handbook page where we can keep an errata of things that need doing with various platforms and various toolchains. --- workspace_tools/export/__init__.py | 2 ++ 1 file changed, 2 insertions(+) mode change 100644 => 100755 workspace_tools/export/__init__.py diff --git a/workspace_tools/export/__init__.py b/workspace_tools/export/__init__.py old mode 100644 new mode 100755 index e35785a66f..72b866a781 --- a/workspace_tools/export/__init__.py +++ b/workspace_tools/export/__init__.py @@ -84,6 +84,8 @@ def export(project_path, project_name, ide, target, destination='/tmp/', zip_path = None if report['success']: + # add readme file to every offline export. + open(tempdir+"\\README.html",'w').write(''% (target,ide)) zip_path = zip_working_directory_and_clean_up(tempdir, destination, project_name, clean) return zip_path, report From 7c55ec959009555fdc01c9518259f40e7325828b Mon Sep 17 00:00:00 2001 From: ytsuboi Date: Sat, 17 Jan 2015 00:41:17 +0900 Subject: [PATCH 26/77] [LPC1114] remove reset pin name to protect people. If user set P0_0 as DigitalOut and set it to low, LPC1114 will be in reset condion. To avoid this situation, p4, xp4 and dp23 was removed from PinNames.h. --- .../TARGET_LPC11XX_11CXX/TARGET_LPC11XX/PinNames.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/PinNames.h index 25b3bf9a3b..263fb3bb78 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/PinNames.h @@ -78,7 +78,7 @@ typedef enum { P3_5 = (3 << PORT_SHIFT) | (5 << PIN_SHIFT) | 0x48, // mbed DIP Pin Names (CQ board) - p4 = P0_0, +// p4 = P0_0, p5 = P0_9, p6 = P0_8, p7 = P0_6, @@ -114,7 +114,7 @@ typedef enum { USBRX = P1_6, // mbed DIP Pin Names (LPCXpresso LPC1114) - xp4 = P0_0, +// xp4 = P0_0, xp5 = P0_9, xp6 = P0_8, xp7 = P2_11, @@ -173,7 +173,7 @@ typedef enum { dp16 = P1_7, dp17 = P1_8, dp18 = P1_9, - dp23 = P0_0, +// dp23 = P0_0, dp24 = P0_1, dp25 = P0_2, dp26 = P0_3, @@ -194,7 +194,7 @@ typedef enum { dip16 = P1_7, dip17 = P1_8, dip18 = P1_9, - dip23 = P0_0, +// dip23 = P0_0, dip24 = P0_1, dip25 = P0_2, dip26 = P0_3, From 5b8a42ffe96b48f9e8351090b49b3e3977b6a6dd Mon Sep 17 00:00:00 2001 From: ytsuboi Date: Sat, 17 Jan 2015 01:33:22 +0900 Subject: [PATCH 27/77] [LPC824] I2C pin names were crossed --- .../TARGET_LPC82X/TARGET_LPC824/PeripheralNames.h | 2 +- .../hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PinNames.h | 8 ++++---- .../TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h | 2 +- .../TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h | 8 ++++---- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PeripheralNames.h index 2d39ea9959..9cef1835a0 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PeripheralNames.h @@ -30,7 +30,7 @@ extern "C" { #define MBED_UART0 P0_7, P0_18 #define MBED_UARTUSB USBTX, USBRX -#define MBED_I2C0 P0_10, P0_11 +#define MBED_I2C0 P0_11, P0_10 typedef enum { ADC_0 = 0, diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PinNames.h index 4aa2995ffe..a63498be03 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PinNames.h @@ -102,10 +102,10 @@ typedef enum { USBRX = P0_18, // I2C pins - SDA = P0_10, - SCL = P0_11, - I2C_SDA = P0_10, - I2C_SCL = P0_11, + SCL = P0_10, + SDA = P0_11, + I2C_SCL = P0_10, + I2C_SDA = P0_11, // Not connected NC = (int)0xFFFFFFFF, diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h index 2d39ea9959..9cef1835a0 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h @@ -30,7 +30,7 @@ extern "C" { #define MBED_UART0 P0_7, P0_18 #define MBED_UARTUSB USBTX, USBRX -#define MBED_I2C0 P0_10, P0_11 +#define MBED_I2C0 P0_11, P0_10 typedef enum { ADC_0 = 0, diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h index 373c472927..e2fb12338d 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h @@ -102,10 +102,10 @@ typedef enum { USBRX = P0_18, // I2C pins - SDA = P0_10, - SCL = P0_11, - I2C_SDA = P0_10, - I2C_SCL = P0_11, + SCL = P0_10, + SDA = P0_11, + I2C_SCL = P0_10, + I2C_SDA = P0_11, // Not connected NC = (int)0xFFFFFFFF, From ac0504da136ef5c973394006f3557468c49f8a4f Mon Sep 17 00:00:00 2001 From: Sissors Date: Fri, 16 Jan 2015 22:28:13 +0100 Subject: [PATCH 28/77] [EXPORT][TEENSY3_1] Added uVision Teensy3.1 exporter Copy paste of K20D50M code, pretty sure I modified the most important bits. --- workspace_tools/export/uvision4.py | 1 + .../export/uvision4_teensy3_1.uvopt.tmpl | 204 +++++++++ .../export/uvision4_teensy3_1.uvproj.tmpl | 423 ++++++++++++++++++ 3 files changed, 628 insertions(+) create mode 100644 workspace_tools/export/uvision4_teensy3_1.uvopt.tmpl create mode 100644 workspace_tools/export/uvision4_teensy3_1.uvproj.tmpl diff --git a/workspace_tools/export/uvision4.py b/workspace_tools/export/uvision4.py index 6d2b09cdf1..b85af2fb7a 100644 --- a/workspace_tools/export/uvision4.py +++ b/workspace_tools/export/uvision4.py @@ -31,6 +31,7 @@ class Uvision4(Exporter): 'K64F', 'K22F', 'K20D50M', + 'TEENSY3_1', 'LPC1347', 'LPC1114', 'LPC11C24', diff --git a/workspace_tools/export/uvision4_teensy3_1.uvopt.tmpl b/workspace_tools/export/uvision4_teensy3_1.uvopt.tmpl new file mode 100644 index 0000000000..678b04edee --- /dev/null +++ b/workspace_tools/export/uvision4_teensy3_1.uvopt.tmpl @@ -0,0 +1,204 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + mbed TEENSY3_1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 14 + + + 0 + Data Sheet + DATASHTS\Freescale\K20PB.pdf + + + 1 + Technical Reference Manual + datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF + + + 2 + Generic User Guide + datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 14 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ULP2CM3 + -O2510 -S0 -C0 -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P128_50MHZ -FS00 -FL020000) + + + 0 + CMSIS_AGDI + -X"MBED CMSIS-DAP" -UA000000001 -O462 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P128_50MHZ -FS00 -FL020000 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + src + 1 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 1 + 2 + 0 + main.cpp + main.cpp + + + + diff --git a/workspace_tools/export/uvision4_teensy3_1.uvproj.tmpl b/workspace_tools/export/uvision4_teensy3_1.uvproj.tmpl new file mode 100644 index 0000000000..dd2052b846 --- /dev/null +++ b/workspace_tools/export/uvision4_teensy3_1.uvproj.tmpl @@ -0,0 +1,423 @@ + + + + 1.1 + +
###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision
+ + + + mbed TEENSY3_1 + 0x4 + ARM-ADS + + + MK20DX256xxx7 + Freescale + IRAM(0x1FFF8000-0x1FFFFFFF) IRAM2(0x20000000-0x20007FFF) IROM(0x0-0x3FFFF) IROM2(0x10000000-0x10007FFF) CLOCK(12000000) CPUTYPE("Cortex-M4") ELITTLE + + "STARTUP\Freescale\Kinetis\startup_MK20D7.s" ("Freescale MK20Xxxxxxx7 Startup Code") + ULP2CM3(-O2510 -S0 -C0 -FO15 -FD20000000 -FC800 -FN2 -FF0MK_P256 -FS00 -FL040000 -FF1MK_D32_72MHZ -FS110000000 -FL108000) + 6298 + MK20D7.H + + + + + + + + + + SFD\Freescale\Kinetis\MK20D5.sfr + 0 + + + + Freescale\Kinetis\ + Freescale\Kinetis\ + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin -o build\{{name}}_K20D5M.bin build\{{name}}.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + 0 + 14 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4105 + + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fffe000 + 0x2000 + + + 1 + 0x0 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fffe000 + 0x2000 + + + 0 + 0x20000000 + 0x2000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + {%if file.type == "1" %} + + + + + --c99 + + + + + {% endif %} + + {% endfor %} + + + {% endfor %} + + + + + From c1307163b3c81d149033a3722a09373d2faa6f8b Mon Sep 17 00:00:00 2001 From: Adam Green Date: Sun, 4 Jan 2015 01:39:16 -0800 Subject: [PATCH 29/77] Fixes to get LPC4330 GCC based builds to run I was getting Hard Faults in even the simplest of samples before I made these fixes. * WaitUs() did nothing on optimized builds. I added the volatile qualifier to the cyc variable to make sure that the delay loop doesn't get optimized out. * I removed the #ifdef which skipped the fpuInit() call when building with GCC. --- .../targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c index 6cfcd6850a..e8d591a513 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c @@ -150,11 +150,9 @@ void SystemInit(void) SCB->VTOR = (unsigned int) &g_pfnVectors; #endif -#if !defined(TOOLCHAIN_GCC) #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1 /* Initialize floating point */ fpuInit(); -#endif #endif SystemSetupPins(pre_clock_mux, COUNT_OF(pre_clock_mux)); /* Configure pins */ @@ -367,7 +365,7 @@ void fpuInit(void) static void WaitUs(uint32_t us) { - uint32_t cyc = us * CPU_NANOSEC(1000) / 4; + volatile uint32_t cyc = us * CPU_NANOSEC(1000) / 4; while (cyc--) ; } From f38d985cc84c78beea0ffdcba77837937861287f Mon Sep 17 00:00:00 2001 From: "nitin.bhaskar.27.09@gmail.com" Date: Sat, 17 Jan 2015 13:29:17 +0530 Subject: [PATCH 30/77] Initial support for LPC11U37H_401 --- .../TARGET_LPC11U37H_401/LPC11U37.sct | 20 + .../TARGET_LPC11U37H_401/startup_LPC11xx.s | 325 +++ .../TARGET_LPC11U37H_401/LPC11U37.sct | 20 + .../TARGET_LPC11U37H_401/startup_LPC11xx.s | 308 +++ .../TARGET_LPC11U37H_401/LPC11U37.ld | 152 ++ .../TARGET_LPC11U37H_401/LPC11U37.ld | 157 ++ .../TARGET_LPC11U37H_401/PeripheralNames.h | 71 + .../TARGET_LPC11U37H_401/PeripheralPins.c | 117 + .../TARGET_LPC11U37H_401/PinNames.h | 170 ++ .../TARGET_LPC11U37H_401/device.h | 59 + workspace_tools/export/codered.py | 1 + .../codered_lpc11u37h_401_cproject.tmpl | 1901 +++++++++++++++++ .../export/codered_lpc11u37h_401_project.tmpl | 84 + .../export/gcc_arm_lpc11u37h_401.tmpl | 76 + workspace_tools/export/gccarm.py | 1 + workspace_tools/export/uvision4.py | 2 + .../export/uvision4_lpc11u37h_401.uvopt.tmpl | 181 ++ .../export/uvision4_lpc11u37h_401.uvproj.tmpl | 419 ++++ workspace_tools/targets.py | 10 + 19 files changed, 4074 insertions(+) create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/LPC11U37.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/startup_LPC11xx.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/LPC11U37.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/startup_LPC11xx.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37H_401/LPC11U37.ld create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U37H_401/LPC11U37.ld create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralPins.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/device.h create mode 100644 workspace_tools/export/codered_lpc11u37h_401_cproject.tmpl create mode 100644 workspace_tools/export/codered_lpc11u37h_401_project.tmpl create mode 100644 workspace_tools/export/gcc_arm_lpc11u37h_401.tmpl create mode 100644 workspace_tools/export/uvision4_lpc11u37h_401.uvopt.tmpl create mode 100644 workspace_tools/export/uvision4_lpc11u37h_401.uvproj.tmpl diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/LPC11U37.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/LPC11U37.sct new file mode 100644 index 0000000000..2d8853b914 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/LPC11U37.sct @@ -0,0 +1,20 @@ + +LR_IROM1 0x00000000 0x20000 { ; load region size_region (128K) + ER_IROM1 0x00000000 0x20000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 + ; 8KB - 0xC0 = 0x1F40 + RW_IRAM1 0x100000C0 0x1F40 { + .ANY (+RW +ZI) + } + RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM + .ANY (IOHANDLER_RAM) + } + RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM + .ANY (USBRAM) + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/startup_LPC11xx.s new file mode 100644 index 0000000000..69b9f35861 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/startup_LPC11xx.s @@ -0,0 +1,325 @@ +;/***************************************************************************** +; * @file: startup_LPC11xx.s +; * @purpose: CMSIS Cortex-M0 Core Device Startup File +; * for the NXP LPC11xx Device Series +; * @version: V1.0 +; * @date: 25. Nov. 2008 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2008 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U3x + + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + ; for LPC11Uxx (With USB) + DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx + DCD FLEX_INT1_IRQHandler + DCD FLEX_INT2_IRQHandler + DCD FLEX_INT3_IRQHandler + DCD FLEX_INT4_IRQHandler + DCD FLEX_INT5_IRQHandler + DCD FLEX_INT6_IRQHandler + DCD FLEX_INT7_IRQHandler + DCD GINT0_IRQHandler + DCD GINT1_IRQHandler ; PIO0 (0:7) + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD USB_IRQHandler ; USB IRQ + DCD USB_FIQHandler ; USB FIQ + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD FMC_IRQHandler ; IP2111 Flash Memory Controller + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD USBWakeup_IRQHandler ; USB wake up + DCD Reserved_IRQHandler ; Reserved + + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + + AREA |.text|, CODE, READONLY + + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled +; for particular peripheral. +;NMI_Handler PROC +; EXPORT NMI_Handler [WEAK] +; B . +; ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Reserved_IRQHandler PROC + EXPORT Reserved_IRQHandler [WEAK] + B . + ENDP + +Default_Handler PROC +; for LPC11Uxx (With USB) + EXPORT NMI_Handler [WEAK] + EXPORT FLEX_INT0_IRQHandler [WEAK] + EXPORT FLEX_INT1_IRQHandler [WEAK] + EXPORT FLEX_INT2_IRQHandler [WEAK] + EXPORT FLEX_INT3_IRQHandler [WEAK] + EXPORT FLEX_INT4_IRQHandler [WEAK] + EXPORT FLEX_INT5_IRQHandler [WEAK] + EXPORT FLEX_INT6_IRQHandler [WEAK] + EXPORT FLEX_INT7_IRQHandler [WEAK] + EXPORT GINT0_IRQHandler [WEAK] + EXPORT GINT1_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT TIMER16_0_IRQHandler [WEAK] + EXPORT TIMER16_1_IRQHandler [WEAK] + EXPORT TIMER32_0_IRQHandler [WEAK] + EXPORT TIMER32_1_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT UART_IRQHandler [WEAK] + + EXPORT USB_IRQHandler [WEAK] + EXPORT USB_FIQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT USBWakeup_IRQHandler [WEAK] + +NMI_Handler +FLEX_INT0_IRQHandler +FLEX_INT1_IRQHandler +FLEX_INT2_IRQHandler +FLEX_INT3_IRQHandler +FLEX_INT4_IRQHandler +FLEX_INT5_IRQHandler +FLEX_INT6_IRQHandler +FLEX_INT7_IRQHandler +GINT0_IRQHandler +GINT1_IRQHandler +SSP1_IRQHandler +I2C_IRQHandler +TIMER16_0_IRQHandler +TIMER16_1_IRQHandler +TIMER32_0_IRQHandler +TIMER32_1_IRQHandler +SSP0_IRQHandler +UART_IRQHandler +USB_IRQHandler +USB_FIQHandler +ADC_IRQHandler +WDT_IRQHandler +BOD_IRQHandler +FMC_IRQHandler +USBWakeup_IRQHandler + + B . + + ENDP + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/LPC11U37.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/LPC11U37.sct new file mode 100644 index 0000000000..ff71e26bfb --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/LPC11U37.sct @@ -0,0 +1,20 @@ + +LR_IROM1 0x00000000 0x20000 { ; load region size_region (128K) + ER_IROM1 0x00000000 0x10000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 + ; 8KB - 0xC0 = 0x1F40 + RW_IRAM1 0x100000C0 0x1F40 { + .ANY (+RW +ZI) + } + RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM + .ANY (IOHANDLER_RAM) + } + RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM + .ANY (USBRAM) + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/startup_LPC11xx.s new file mode 100644 index 0000000000..e8bb645b73 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/startup_LPC11xx.s @@ -0,0 +1,308 @@ +;/***************************************************************************** +; * @file: startup_LPC11xx.s +; * @purpose: CMSIS Cortex-M0 Core Device Startup File +; * for the NXP LPC11xx Device Series +; * @version: V1.0 +; * @date: 25. Nov. 2008 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2008 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + +__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U3x + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + ; for LPC11Uxx (With USB) + DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx + DCD FLEX_INT1_IRQHandler + DCD FLEX_INT2_IRQHandler + DCD FLEX_INT3_IRQHandler + DCD FLEX_INT4_IRQHandler + DCD FLEX_INT5_IRQHandler + DCD FLEX_INT6_IRQHandler + DCD FLEX_INT7_IRQHandler + DCD GINT0_IRQHandler + DCD GINT1_IRQHandler ; PIO0 (0:7) + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD USB_IRQHandler ; USB IRQ + DCD USB_FIQHandler ; USB FIQ + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD FMC_IRQHandler ; IP2111 Flash Memory Controller + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD USBWakeup_IRQHandler ; USB wake up + DCD Reserved_IRQHandler ; Reserved + + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + + AREA |.text|, CODE, READONLY + + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled +; for particular peripheral. +;NMI_Handler PROC +; EXPORT NMI_Handler [WEAK] +; B . +; ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Reserved_IRQHandler PROC + EXPORT Reserved_IRQHandler [WEAK] + B . + ENDP + +Default_Handler PROC +; for LPC11Uxx (With USB) + EXPORT NMI_Handler [WEAK] + EXPORT FLEX_INT0_IRQHandler [WEAK] + EXPORT FLEX_INT1_IRQHandler [WEAK] + EXPORT FLEX_INT2_IRQHandler [WEAK] + EXPORT FLEX_INT3_IRQHandler [WEAK] + EXPORT FLEX_INT4_IRQHandler [WEAK] + EXPORT FLEX_INT5_IRQHandler [WEAK] + EXPORT FLEX_INT6_IRQHandler [WEAK] + EXPORT FLEX_INT7_IRQHandler [WEAK] + EXPORT GINT0_IRQHandler [WEAK] + EXPORT GINT1_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT TIMER16_0_IRQHandler [WEAK] + EXPORT TIMER16_1_IRQHandler [WEAK] + EXPORT TIMER32_0_IRQHandler [WEAK] + EXPORT TIMER32_1_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT UART_IRQHandler [WEAK] + + EXPORT USB_IRQHandler [WEAK] + EXPORT USB_FIQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT USBWakeup_IRQHandler [WEAK] + +NMI_Handler +FLEX_INT0_IRQHandler +FLEX_INT1_IRQHandler +FLEX_INT2_IRQHandler +FLEX_INT3_IRQHandler +FLEX_INT4_IRQHandler +FLEX_INT5_IRQHandler +FLEX_INT6_IRQHandler +FLEX_INT7_IRQHandler +GINT0_IRQHandler +GINT1_IRQHandler +SSP1_IRQHandler +I2C_IRQHandler +TIMER16_0_IRQHandler +TIMER16_1_IRQHandler +TIMER32_0_IRQHandler +TIMER32_1_IRQHandler +SSP0_IRQHandler +UART_IRQHandler +USB_IRQHandler +USB_FIQHandler +ADC_IRQHandler +WDT_IRQHandler +BOD_IRQHandler +FMC_IRQHandler +USBWakeup_IRQHandler + + B . + + ENDP + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37H_401/LPC11U37.ld b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37H_401/LPC11U37.ld new file mode 100644 index 0000000000..463c4287db --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37H_401/LPC11U37.ld @@ -0,0 +1,152 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 + RAMIO (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 + USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text.Reset_Handler) + + /* Only vectors and code running at reset are safe to be in first 512 + bytes since RAM can be mapped into this area for RAM based interrupt + vectors. */ + . = 0x00000200; + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U37H_401/LPC11U37.ld b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U37H_401/LPC11U37.ld new file mode 100644 index 0000000000..55ee248fa5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U37H_401/LPC11U37.ld @@ -0,0 +1,157 @@ +/* mbed - LPC11U35 linker script + * Based linker script generated by Code Red Technologies Red Suite 4.1 + */ +GROUP(libgcc.a libc_s.a libstdc++_s.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o) + +MEMORY +{ + /* Define each memory region */ + MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128k */ + RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 /* 8k */ + RamIo1 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2k */ + RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2k */ +} + /* Define a symbol for the top of each memory region */ + __top_MFlash32 = 0x0 + 0x10000; + __top_RamLoc8 = 0x10000000 + 0x1F40; + __top_RamIo1 = 0x20000000 + 0x800; + __top_RamUsb2 = 0x20004000 + 0x800; + +ENTRY(ResetISR) + +SECTIONS +{ + + /* MAIN TEXT SECTION */ + .text : ALIGN(4) + { + FILL(0xff) + KEEP(*(.isr_vector)) + *(.text.ResetISR) + . = 0x200; + + /* Global Section Table */ + . = ALIGN(4) ; + __section_table_start = .; + __data_section_table = .; + LONG(LOADADDR(.data)); + LONG( ADDR(.data)) ; + LONG( SIZEOF(.data)); + LONG(LOADADDR(.data_RAM2)); + LONG( ADDR(.data_RAM2)) ; + LONG( SIZEOF(.data_RAM2)); + __data_section_table_end = .; + __bss_section_table = .; + LONG( ADDR(.bss)); + LONG( SIZEOF(.bss)); + LONG( ADDR(.bss_RAM2)); + LONG( SIZEOF(.bss_RAM2)); + __bss_section_table_end = .; + __section_table_end = . ; + /* End of Global Section Table */ + + + *(.after_vectors*) + + *(.text*) + *(.rodata .rodata.*) + . = ALIGN(4); + + /* C++ constructors etc */ + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + KEEP(*(.fini)); + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + /* End C++ */ + } > MFlash32 + + /* + * for exception handling/unwind - some Newlib functions (in common + * with C++ and STDC++) use this. + */ + .ARM.extab : ALIGN(4) + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > MFlash32 + __exidx_start = .; + + .ARM.exidx : ALIGN(4) + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > MFlash32 + __exidx_end = .; + + _etext = .; + + + .data_RAM2 : ALIGN(4) + { + FILL(0xff) + *(.data.$RAM2*) + *(.data.$RamUsb2*) + . = ALIGN(4) ; + } > RamUsb2 AT>MFlash32 + + /* MAIN DATA SECTION */ + + .uninit_RESERVED : ALIGN(4) + { + KEEP(*(.bss.$RESERVED*)) + } > RamLoc8 + + .data : ALIGN(4) + { + FILL(0xff) + _data = .; + *(vtable) + *(.data*) + . = ALIGN(4) ; + _edata = .; + } > RamLoc8 AT>MFlash32 + + + .bss_RAM2 : ALIGN(4) + { + *(.bss.$RAM2*) + *(.bss.$RamUsb2*) + . = ALIGN(4) ; + } > RamUsb2 + + /* MAIN BSS SECTION */ + .bss : ALIGN(4) + { + _bss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4) ; + _ebss = .; + PROVIDE(end = .); + __end__ = .; + } > RamLoc8 + + PROVIDE(_pvHeapStart = .); + PROVIDE(_vStackTop = __top_RamLoc8 - 0); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralNames.h new file mode 100644 index 0000000000..969f15f2f6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralNames.h @@ -0,0 +1,71 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)LPC_USART_BASE +} UARTName; + +typedef enum { + I2C_0 = (int)LPC_I2C_BASE +} I2CName; + +typedef enum { + ADC0_0 = 0, + ADC0_1, + ADC0_2, + ADC0_3, + ADC0_4, + ADC0_5, + ADC0_6, + ADC0_7 +} ADCName; + +typedef enum { + SPI_0 = (int)LPC_SSP0_BASE, + SPI_1 = (int)LPC_SSP1_BASE +} SPIName; + +typedef enum { + PWM_1 = 0, + PWM_2, + PWM_3, + PWM_4, + PWM_5, + PWM_6, + PWM_7, + PWM_8, + PWM_9, + PWM_10, + PWM_11 +} PWMName; + +#define STDIO_UART_TX UART_TX +#define STDIO_UART_RX UART_RX +#define STDIO_UART UART_0 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralPins.c new file mode 100644 index 0000000000..b583d12c1b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralPins.c @@ -0,0 +1,117 @@ + +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {P0_11, ADC0_0, 0x02}, + {P0_12, ADC0_1, 0x02}, + {P0_13, ADC0_2, 0x02}, + {P0_14, ADC0_3, 0x02}, + {P0_15, ADC0_4, 0x02}, + {P0_16, ADC0_5, 0x01}, + {P0_22, ADC0_6, 0x01}, + {P0_23, ADC0_7, 0x01}, + {NC , NC , 0 } +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {P0_5, I2C_0, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {P0_4, I2C_0, 1}, + {NC , NC, 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {P0_19, UART_0, 1}, + {P1_13, UART_0, 3}, + {P1_27, UART_0, 2}, + { NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {P0_18, UART_0, 1}, + {P1_14, UART_0, 3}, + {P1_26, UART_0, 2}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {P0_6 , SPI_0, 0x02}, + {P0_10, SPI_0, 0x02}, + {P1_29, SPI_0, 0x01}, + {P1_15, SPI_1, 0x03}, + {P1_20, SPI_1, 0x02}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {P0_9 , SPI_0, 0x01}, + {P0_21, SPI_1, 0x02}, + {P1_22, SPI_1, 0x02}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {P0_8 , SPI_0, 0x01}, + {P0_22, SPI_1, 0x03}, + {P1_21, SPI_1, 0x02}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {P0_2 , SPI_0, 0x01}, + {P1_19, SPI_1, 0x02}, + {P1_23, SPI_1, 0x02}, + {NC , NC , 0} +}; + +/************PWM***************/ +/* To have a PWM where we can change both the period and the duty cycle, + * we need an entire timer. With the following conventions: + * * MR3 is used for the PWM period + * * MR0, MR1, MR2 are used for the duty cycle + */ +const PinMap PinMap_PWM[] = { + /* CT16B0 */ + {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */ + {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */ + {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */ + + /* CT16B1 */ + {P0_21, PWM_4, 1}, /* MR0 */ + {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */ + + /* CT32B0 */ + {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */ + {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */ + {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */ + + /* CT32B1 */ + {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */ + {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */ + {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */ + + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PinNames.h new file mode 100644 index 0000000000..f1d484c9d2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PinNames.h @@ -0,0 +1,170 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 5 + +typedef enum { + // LPC11U Pin Names + P0_0 = 0, + P0_1 = 1, + P0_2 = 2, + P0_3 = 3, + P0_4 = 4, + P0_5 = 5, + P0_6 = 6, + P0_7 = 7, + P0_8 = 8, + P0_9 = 9, + P0_10 = 10, + P0_11 = 11, + P0_12 = 12, + P0_13 = 13, + P0_14 = 14, + P0_15 = 15, + P0_16 = 16, + P0_17 = 17, + P0_18 = 18, + P0_19 = 19, + P0_20 = 20, + P0_21 = 21, + P0_22 = 22, + P0_23 = 23, + P0_24 = 24, + P0_25 = 25, + P0_26 = 26, + P0_27 = 27, + + P1_0 = 32, + P1_1 = 33, + P1_2 = 34, + P1_3 = 35, + P1_4 = 36, + P1_5 = 37, + P1_6 = 38, + P1_7 = 39, + P1_8 = 40, + P1_9 = 41, + P1_10 = 42, + P1_11 = 43, + P1_12 = 44, + P1_13 = 45, + P1_14 = 46, + P1_15 = 47, + P1_16 = 48, + P1_17 = 49, + P1_18 = 50, + P1_19 = 51, + P1_20 = 52, + P1_21 = 53, + P1_22 = 54, + P1_23 = 55, + P1_24 = 56, + P1_25 = 57, + P1_26 = 58, + P1_27 = 59, + P1_28 = 60, + P1_29 = 61, + + P1_31 = 63, + + // LED Names + LED1 = P1_24, + LED2 = P1_25, + LED3 = P1_26, + LED4 = P0_0, + LED5 = P1_3, + LED6 = P1_2, + LED7 = P1_1, + LED8 = P1_0, + + // BTN Names + BTN1 = P0_16, + BTN2 = P0_1, + + // UART + UART_TX = P0_19, + UART_RX = P0_18, + + // Arduino Shield Receptacles Names + D0 = P0_18, + D1 = P0_19, + D2 = P1_17, + D3 = P1_24, + D4 = P1_5, + D5 = P0_1, + D6 = P1_27, + D7 = P0_7, + D8 = P0_2, + D9 = P1_25, + D10= P1_23, + D11= P0_21, + D12= P0_22, + D13= P1_15, + D14= P0_5, + D15= P0_4, + + A0 = P0_11, + A1 = P0_12, + A2 = P0_13, + A3 = P0_16, + A4 = P0_5, // same port as SDA + A5 = P0_4, // same port as SCL + + SDA= P0_5, // same port as A4 + SCL= P0_4, // same port as A5 + + // Not connected + NC = (int)0xFFFFFFFF, +} PinName; + +typedef enum { + CHANNEL0 = FLEX_INT0_IRQn, + CHANNEL1 = FLEX_INT1_IRQn, + CHANNEL2 = FLEX_INT2_IRQn, + CHANNEL3 = FLEX_INT3_IRQn, + CHANNEL4 = FLEX_INT4_IRQn, + CHANNEL5 = FLEX_INT5_IRQn, + CHANNEL6 = FLEX_INT6_IRQn, + CHANNEL7 = FLEX_INT7_IRQn +} Channel; + +typedef enum { + PullUp = 2, + PullDown = 1, + PullNone = 0, + Repeater = 3, + OpenDrain = 4, + PullDefault = PullDown +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/device.h new file mode 100644 index 0000000000..120ca9edb6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/device.h @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif diff --git a/workspace_tools/export/codered.py b/workspace_tools/export/codered.py index 5747585e30..d1ee495d2d 100755 --- a/workspace_tools/export/codered.py +++ b/workspace_tools/export/codered.py @@ -35,6 +35,7 @@ class CodeRed(Exporter): 'LPC11U68', 'LPCCAPPUCCINO', 'LPC824', + 'LPC11U37H_401', ] def generate(self): diff --git a/workspace_tools/export/codered_lpc11u37h_401_cproject.tmpl b/workspace_tools/export/codered_lpc11u37h_401_cproject.tmpl new file mode 100644 index 0000000000..e0c06fdb58 --- /dev/null +++ b/workspace_tools/export/codered_lpc11u37h_401_cproject.tmpl @@ -0,0 +1,1901 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + <?xml version="1.0" encoding="UTF-8"?> +<TargetConfig> +<Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC11U37H/401" property_count="5" version="70002"/> +<infoList vendor="NXP"> +<info chip="LPC11U37H/401" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x0001BC40" name="LPC11U37H/401" stub="crt_emu_lpc11_13_nxp"> +<chip> +<name>LPC11U37H/401</name> +<family>LPC11Uxx</family> +<vendor>NXP (formerly Philips)</vendor> +<reset board="None" core="Real" sys="Real"/> +<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> +<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> +<memory id="RAM" type="RAM"/> +<memory id="Periph" is_volatile="true" type="Peripheral"/> +<memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/> +<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> +<memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/> +<peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/> +<peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/> +<peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/> +<peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/> +<peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/> +<peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/> +<peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/> +<peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/> +<peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/> +<peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/> +<peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/> +<peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/> +<peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/> +<peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> +<peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/> +<peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/> +<peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/> +<peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/> +<peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/> +<peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/> +<peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/> +</chip> +<processor> +<name gcc_name="cortex-m0">Cortex-M0</name> +<family>Cortex-M</family> +</processor> +<link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/> +</info> +</infoList> +</TargetConfig> + + + + + diff --git a/workspace_tools/export/codered_lpc11u37h_401_project.tmpl b/workspace_tools/export/codered_lpc11u37h_401_project.tmpl new file mode 100644 index 0000000000..42ef4384de --- /dev/null +++ b/workspace_tools/export/codered_lpc11u37h_401_project.tmpl @@ -0,0 +1,84 @@ + + + {{name}} + This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Code-Red + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/{{name}}/Debug} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + diff --git a/workspace_tools/export/gcc_arm_lpc11u37h_401.tmpl b/workspace_tools/export/gcc_arm_lpc11u37h_401.tmpl new file mode 100644 index 0000000000..abdbbb11cb --- /dev/null +++ b/workspace_tools/export/gcc_arm_lpc11u37h_401.tmpl @@ -0,0 +1,76 @@ +# This file was automagically generated by mbed.org. For more information, +# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded + +GCC_BIN = +PROJECT = {{name}} +OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %} +SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %} +INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %} +LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %} +LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %} +LINKER_SCRIPT = {{linker_script}} + +############################################################################### +AS = $(GCC_BIN)arm-none-eabi-as +CC = $(GCC_BIN)arm-none-eabi-gcc +CPP = $(GCC_BIN)arm-none-eabi-g++ +LD = $(GCC_BIN)arm-none-eabi-gcc +OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy +OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump +SIZE = $(GCC_BIN)arm-none-eabi-size + +CPU = -mcpu=cortex-m0 -mthumb +CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections +CC_FLAGS += -MMD -MP +CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %} + +LD_FLAGS = -mcpu=cortex-m0 -mthumb -Wl,--gc-sections --specs=nano.specs +LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref +LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +ifeq ($(DEBUG), 1) + CC_FLAGS += -DDEBUG -O0 +else + CC_FLAGS += -DNDEBUG -Os +endif + +all: $(PROJECT).bin $(PROJECT).hex size + +clean: + rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS) + +.s.o: + $(AS) $(CPU) -o $@ $< + +.c.o: + $(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $< + +.cpp.o: + $(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 $(INCLUDE_PATHS) -o $@ $< + + +$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) + $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS) + @echo "" + @echo "*****" + @echo "***** You must modify vector checksum value in *.bin and *.hex files." + @echo "*****" + @echo "" + +$(PROJECT).bin: $(PROJECT).elf + @$(OBJCOPY) -O binary $< $@ + +$(PROJECT).hex: $(PROJECT).elf + @$(OBJCOPY) -O ihex $< $@ + +$(PROJECT).lst: $(PROJECT).elf + @$(OBJDUMP) -Sdh $< > $@ + +lst: $(PROJECT).lst + +size: + $(SIZE) $(PROJECT).elf + +DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d) +-include $(DEPS) + diff --git a/workspace_tools/export/gccarm.py b/workspace_tools/export/gccarm.py index be37c7241a..82a37a3245 100644 --- a/workspace_tools/export/gccarm.py +++ b/workspace_tools/export/gccarm.py @@ -38,6 +38,7 @@ class GccArm(Exporter): 'LPC1114', 'LPC11U35_401', 'LPC11U35_501', + 'LPC11U37H_401', 'STM32F407', 'DISCO_F100RB', 'DISCO_F051R8', diff --git a/workspace_tools/export/uvision4.py b/workspace_tools/export/uvision4.py index 6d2b09cdf1..8aa2ede9d0 100644 --- a/workspace_tools/export/uvision4.py +++ b/workspace_tools/export/uvision4.py @@ -66,6 +66,7 @@ class Uvision4(Exporter): 'NRF51_DK', 'NRF51_DONGLE', 'BLE_SMURFS', + 'LPC11U37H_401', ] USING_MICROLIB = [ @@ -88,6 +89,7 @@ class Uvision4(Exporter): 'LPC1549', 'LPC11U35_501', 'KL05Z', + 'LPC11U37H_401', ] FILE_TYPES = { diff --git a/workspace_tools/export/uvision4_lpc11u37h_401.uvopt.tmpl b/workspace_tools/export/uvision4_lpc11u37h_401.uvopt.tmpl new file mode 100644 index 0000000000..93f73fb2e6 --- /dev/null +++ b/workspace_tools/export/uvision4_lpc11u37h_401.uvopt.tmpl @@ -0,0 +1,181 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + mbed NXP LPC11U37H_401 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMP1.DLL + -pLPC11U14 + SARMCM3.DLL + + TARMP1.DLL + -pLPC11U14 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 14 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"MBED CMSIS-DAP" -UA000000001 -O206 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_32 -FS00 -FL08000 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + src + 1 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 1 + 2 + 0 + main.cpp + main.cpp + + + + diff --git a/workspace_tools/export/uvision4_lpc11u37h_401.uvproj.tmpl b/workspace_tools/export/uvision4_lpc11u37h_401.uvproj.tmpl new file mode 100644 index 0000000000..3a0f057af8 --- /dev/null +++ b/workspace_tools/export/uvision4_lpc11u37h_401.uvproj.tmpl @@ -0,0 +1,419 @@ + + + + 1.1 + +
###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision
+ + + + mbed NXP LPC11U37H_401 + 0x4 + ARM-ADS + + + LPC11U37/401 + NXP + IRAM(0x10000000-0x10001FFF) IRAM2(0x20004000-0x200047FF) IROM(0-0x1FFFF) CLOCK(12000000) CPUTYPE("Cortex-M0") + + "STARTUP\NXP\LPC11Uxx\startup_LPC11Uxx.s" ("NXP LPC11Uxx Startup Code") + UL2CM3(-O4303 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_32 -FS00 -FL08000) + 5738 + LPC11Uxx.h + + + + + + + + + + SFD\NXP\LPC11Uxx\LPC11Uxx.SFR + 0 + + + + NXP\LPC11Uxx\ + NXP\LPC11Uxx\ + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 1 + $K\ARM\BIN\ELFDWT.EXE "!L" + fromelf --bin -o {{name}}_LPC11U37H.bin build\{{name}}.axf + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMP1.DLL + -pLPC11U14 + SARMCM3.DLL + + TARMP1.DLL + -pLPC11U37 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + 0 + 14 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4105 + + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x2000 + + + 1 + 0x0 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x2000 + + + 0 + 0x20004000 + 0x800 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + {%if file.type == "1" %} + + + + + --c99 + + + + + {% endif %} + + {% endfor %} + + + {% endfor %} + + + + + diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index f11d2cb6d8..64f5af18fa 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -334,6 +334,15 @@ class LPC1800(LPCTarget): self.extra_labels = ['NXP', 'LPC43XX'] self.supported_toolchains = ["ARM", "GCC_CR", "IAR"] +class LPC11U37H_401(LPCTarget): + def __init__(self): + LPCTarget.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['NXP', 'LPC11UXX'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO"] + ### Freescale ### @@ -893,6 +902,7 @@ TARGETS = [ LPC4330_M4(), LPC4330_M0(), LPC4337(), + LPC11U37H_401(), ### Freescale ### KL05Z(), From 4fece5da1c75749fe8dd3ff6d63565488e93ca6c Mon Sep 17 00:00:00 2001 From: NitinBhaskar Date: Tue, 20 Jan 2015 14:40:41 +0530 Subject: [PATCH 31/77] Update build_release.py Added new target LPC11U37H_401 --- workspace_tools/build_release.py | 1 + 1 file changed, 1 insertion(+) diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 6b39a09161..1f513e4cdb 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -44,6 +44,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('XADOW_M0', ('ARM', 'uARM','GCC_ARM','GCC_CR')), ('ARCH_GPRS', ('ARM', 'uARM', 'GCC_ARM', 'GCC_CR', 'IAR')), ('LPC4337', ('ARM',)), + ('LPC11U37H_401', ('ARM', 'uARM','GCC_ARM','GCC_CR', 'IAR')), ('KL05Z', ('ARM', 'uARM', 'GCC_ARM', 'IAR')), ('KL25Z', ('ARM', 'GCC_ARM', 'IAR')), From 0fbe72662a1219177bc348dd8db23553a71bb30c Mon Sep 17 00:00:00 2001 From: NitinBhaskar Date: Tue, 20 Jan 2015 14:43:26 +0530 Subject: [PATCH 32/77] Added new target LPC11U37H_401 --- workspace_tools/build_travis.py | 1 + 1 file changed, 1 insertion(+) diff --git a/workspace_tools/build_travis.py b/workspace_tools/build_travis.py index e33c4606a9..9c01fe20d6 100644 --- a/workspace_tools/build_travis.py +++ b/workspace_tools/build_travis.py @@ -57,6 +57,7 @@ build_list = ( { "target": "UBLOX_C027", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "LPC11U35_501", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, { "target": "LPC11U68", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, + { "target": "LPC11U37H_401", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, { "target": "KL05Z", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "KL25Z", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] }, From 5e57cd3d295114f766bf90e8b0fd48ed7c087304 Mon Sep 17 00:00:00 2001 From: bcostm Date: Tue, 20 Jan 2015 13:10:22 +0100 Subject: [PATCH 33/77] [NUCLEO_F303RE] Add GCC_ARM toolchain --- .../TOOLCHAIN_GCC_ARM/STM32F303XE.ld | 155 ++++++ .../TOOLCHAIN_GCC_ARM/startup_stm32f303xe.s | 505 ++++++++++++++++++ workspace_tools/targets.py | 2 +- 3 files changed, 661 insertions(+), 1 deletion(-) create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_GCC_ARM/STM32F303XE.ld create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.s diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_GCC_ARM/STM32F303XE.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_GCC_ARM/STM32F303XE.ld new file mode 100644 index 0000000000..a98a441f7d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_GCC_ARM/STM32F303XE.ld @@ -0,0 +1,155 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K + CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 16K + RAM (rwx) : ORIGIN = 0x20000194, LENGTH = 64K - 0x194 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.s new file mode 100644 index 0000000000..efa5681b0e --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.s @@ -0,0 +1,505 @@ +/** + ****************************************************************************** + * @file startup_stm32f303xe.s + * @author MCD Application Team + * @version + * @date 12-Sept-2014 + * @brief STM32F303xE devices vector table for Atollic + * TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Atollic update: set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main +/** + * Calling the crt0 'cold-start' entry point. There __libc_init_array is called + * and when existing hardware_init_hook() and software_init_hook() before + * starting main(). software_init_hook() is available and has to be called due + * to initializsation when using rtos. +*/ + bl _start + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_TSC_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN_TX_IRQHandler + .word USB_LP_CAN_RX0_IRQHandler + .word CAN_RX1_IRQHandler + .word CAN_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FMC_IRQHandler + .word 0 + .word 0 + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ADC4_IRQHandler + .word 0 + .word 0 + .word COMP1_2_3_IRQHandler + .word COMP4_5_6_IRQHandler + .word COMP7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word USBWakeUp_RMP_IRQHandler + .word TIM20_BRK_IRQHandler + .word TIM20_UP_IRQHandler + .word TIM20_TRG_COM_IRQHandler + .word TIM20_CC_IRQHandler + .word FPU_IRQHandler + .word 0 + .word 0 + .word SPI4_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_TSC_IRQHandler + .thumb_set EXTI2_TSC_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN_TX_IRQHandler + .thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN_RX0_IRQHandler + .thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler + + .weak CAN_RX1_IRQHandler + .thumb_set CAN_RX1_IRQHandler,Default_Handler + + .weak CAN_SCE_IRQHandler + .thumb_set CAN_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ADC4_IRQHandler + .thumb_set ADC4_IRQHandler,Default_Handler + + .weak COMP1_2_3_IRQHandler + .thumb_set COMP1_2_3_IRQHandler,Default_Handler + + .weak COMP4_5_6_IRQHandler + .thumb_set COMP4_5_6_IRQHandler,Default_Handler + + .weak COMP7_IRQHandler + .thumb_set COMP7_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak USBWakeUp_RMP_IRQHandler + .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler + + .weak TIM20_BRK_IRQHandler + .thumb_set TIM20_BRK_IRQHandler,Default_Handler + + .weak TIM20_UP_IRQHandler + .thumb_set TIM20_UP_IRQHandler,Default_Handler + + .weak TIM20_TRG_COM_IRQHandler + .thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler + + .weak TIM20_CC_IRQHandler + .thumb_set TIM20_CC_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index d6769343ed..3e585c3213 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -486,7 +486,7 @@ class NUCLEO_F303RE(Target): Target.__init__(self) self.core = "Cortex-M4F" self.extra_labels = ['STM', 'STM32F3', 'STM32F303RE'] - self.supported_toolchains = ["ARM", "uARM", "IAR"] + self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"] self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO", "MORPHO"] self.detect_code = ["0706"] From b223f83441341d3eb4aa7507716ac587332b0766 Mon Sep 17 00:00:00 2001 From: milangit Date: Tue, 20 Jan 2015 21:40:05 +0100 Subject: [PATCH 34/77] Updated gpio irq hal with max num of irq - EXTI lines 5 to 9 - EXTI lines 10 to 15 --- .../TARGET_NUCLEO_F103RB/gpio_irq_api.c | 140 +++++++++++++----- .../TARGET_STM/TARGET_NUCLEO_F103RB/objects.h | 1 + 2 files changed, 108 insertions(+), 33 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_irq_api.c index fba80fbc5c..3857a496fb 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_irq_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_irq_api.c @@ -39,62 +39,125 @@ #define EDGE_BOTH (3) #define CHANNEL_NUM (7) +// Max pins for one line (max with EXTI10_15) +#define MAX_PIN_LINE (6) -static uint32_t channel_ids[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0}; -static uint32_t channel_gpio[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0}; -static uint32_t channel_pin[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0}; +typedef struct gpio_channel { + uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts + uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance + uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group + uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group +} gpio_channel_t; + +static gpio_channel_t channels[CHANNEL_NUM] = { + {.pin_mask = 0}, + {.pin_mask = 0}, + {.pin_mask = 0}, + {.pin_mask = 0}, + {.pin_mask = 0}, + {.pin_mask = 0}, + {.pin_mask = 0} +}; + +// Used to return the index for channels array. +static uint32_t pin_base_nr[16] = { + // EXTI0 + 0, // pin 0 + // EXTI1 + 0, // pin 1 + // EXTI2 + 0, // pin 2 + // EXTI3 + 0, // pin 3 + // EXTI4 + 0, // pin 4 + // EXTI5_9 + 0, // pin 5 + 1, // pin 6 + 2, // pin 7 + 3, // pin 8 + 4, // pin 9 + // EXTI10_15 + 0, // pin 10 + 1, // pin 11 + 2, // pin 12 + 3, // pin 13 + 4, // pin 14 + 5 // pin 15 +}; static gpio_irq_handler irq_handler; -static void handle_interrupt_in(uint32_t irq_index) +static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) { - // Retrieve the gpio and pin that generate the irq - GPIO_TypeDef *gpio = (GPIO_TypeDef *)(channel_gpio[irq_index]); - uint32_t pin = (uint32_t)(1 << channel_pin[irq_index]); + gpio_channel_t *gpio_channel = &channels[irq_index]; + uint32_t gpio_idx; - // Clear interrupt flag - if (EXTI_GetITStatus(pin) != RESET) { - EXTI_ClearITPendingBit(pin); - } + for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) { + uint32_t current_mask = (1 << gpio_idx); - if (channel_ids[irq_index] == 0) return; + if (gpio_channel->pin_mask & current_mask) { + // Retrieve the gpio and pin that generate the irq + GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]); + uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx])); - // Check which edge has generated the irq - if ((gpio->IDR & pin) == 0) { - irq_handler(channel_ids[irq_index], IRQ_FALL); - } else { - irq_handler(channel_ids[irq_index], IRQ_RISE); + // Clear interrupt flag + if (EXTI_GetITStatus(pin) != RESET) { + EXTI_ClearITPendingBit(pin); + + if (gpio_channel->channel_ids[gpio_idx] == 0) continue; + + // Check which edge has generated the irq + if ((gpio->IDR & pin) == 0) { + irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL); + } else { + irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE); + } + } + } } } -// The irq_index is passed to the function +// EXTI line 0 static void gpio_irq0(void) { - handle_interrupt_in(0); // EXTI line 0 + handle_interrupt_in(0, 1); } + +// EXTI line 1 static void gpio_irq1(void) { - handle_interrupt_in(1); // EXTI line 1 + handle_interrupt_in(1, 1); } + +// EXTI line 2 static void gpio_irq2(void) { - handle_interrupt_in(2); // EXTI line 2 + handle_interrupt_in(2, 1); } + +// EXTI line 3 static void gpio_irq3(void) { - handle_interrupt_in(3); // EXTI line 3 + handle_interrupt_in(3, 1); } + +// EXTI line 4 static void gpio_irq4(void) { - handle_interrupt_in(4); // EXTI line 4 + handle_interrupt_in(4, 1); } + +// EXTI lines 5 to 9 static void gpio_irq5(void) { - handle_interrupt_in(5); // EXTI lines 5 to 9 + handle_interrupt_in(5, 5); } + +// EXTI lines 10 to 15 static void gpio_irq6(void) { - handle_interrupt_in(6); // EXTI lines 10 to 15 + handle_interrupt_in(6, 6); } extern uint32_t Set_GPIO_Clock(uint32_t port_idx); @@ -104,6 +167,8 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 IRQn_Type irq_n = (IRQn_Type)0; uint32_t vector = 0; uint32_t irq_index; + gpio_channel_t *gpio_channel; + uint32_t gpio_idx; if (pin == NC) return -1; @@ -193,9 +258,13 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 obj->irq_n = irq_n; obj->irq_index = irq_index; obj->event = EDGE_NONE; - channel_ids[irq_index] = id; - channel_gpio[irq_index] = gpio_add; - channel_pin[irq_index] = pin_index; + + gpio_channel = &channels[irq_index]; + gpio_idx = pin_base_nr[pin_index]; + gpio_channel->pin_mask |= (1 << gpio_idx); + gpio_channel->channel_ids[gpio_idx] = id; + gpio_channel->channel_gpio[gpio_idx] = gpio_add; + gpio_channel->channel_pin[gpio_idx] = pin_index; irq_handler = handler; @@ -204,9 +273,15 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->irq_index] = 0; - channel_gpio[obj->irq_index] = 0; - channel_pin[obj->irq_index] = 0; + gpio_channel_t *gpio_channel = &channels[obj->irq_index]; + uint32_t pin_index = STM_PIN(obj->pin); + uint32_t gpio_idx = pin_base_nr[pin_index]; + + gpio_channel->pin_mask &= ~(1 << gpio_idx); + gpio_channel->channel_ids[gpio_idx] = 0; + gpio_channel->channel_gpio[gpio_idx] = 0; + gpio_channel->channel_pin[gpio_idx] = 0; + // Disable EXTI line EXTI_InitTypeDef EXTI_InitStructure; EXTI_StructInit(&EXTI_InitStructure); @@ -217,8 +292,7 @@ void gpio_irq_free(gpio_irq_t *obj) void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { EXTI_InitTypeDef EXTI_InitStructure; - - uint32_t pin_index = channel_pin[obj->irq_index]; + uint32_t pin_index = STM_PIN(obj->pin); EXTI_InitStructure.EXTI_Line = (uint32_t)(1 << pin_index); EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/objects.h index 3b8a442be8..162117e03d 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/objects.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/objects.h @@ -43,6 +43,7 @@ struct gpio_irq_s { IRQn_Type irq_n; uint32_t irq_index; uint32_t event; + PinName pin; }; struct port_s { From c548c2693f003eccbddb96c87f5029a6f35ad8a4 Mon Sep 17 00:00:00 2001 From: Austin Blackstone Date: Wed, 21 Jan 2015 11:13:33 -0600 Subject: [PATCH 35/77] fixed readme.html so it works on all OS's, previous commit only worked on windows --- workspace_tools/export/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/workspace_tools/export/__init__.py b/workspace_tools/export/__init__.py index 72b866a781..ee26e2425d 100755 --- a/workspace_tools/export/__init__.py +++ b/workspace_tools/export/__init__.py @@ -85,7 +85,7 @@ def export(project_path, project_name, ide, target, destination='/tmp/', zip_path = None if report['success']: # add readme file to every offline export. - open(tempdir+"\\README.html",'w').write(''% (target,ide)) + open(os.path.join(temdir, 'README.html'),'w').write(''% (target,ide)) zip_path = zip_working_directory_and_clean_up(tempdir, destination, project_name, clean) return zip_path, report From 35d1ffd787f1c141bebaeb2bafd7c25d699494ac Mon Sep 17 00:00:00 2001 From: Adam Green Date: Wed, 21 Jan 2015 18:52:24 -0800 Subject: [PATCH 36/77] Correct warning when assigning HEAP_START to stack_pointer This fixes issue #856 reported by @neilt6. I tested on mbedLPC1768 and mbedLPC11U24 using the GCC_ARM toolchain. --- libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h index b0e88066cb..e7e5311390 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h @@ -304,10 +304,10 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL} #endif #ifdef __CC_ARM -extern unsigned char Image$$RW_IRAM1$$ZI$$Limit[]; +extern uint32_t Image$$RW_IRAM1$$ZI$$Limit[]; #define HEAP_START (Image$$RW_IRAM1$$ZI$$Limit) #elif defined(__GNUC__) -extern unsigned char __end__[]; +extern uint32_t __end__[]; #define HEAP_START (__end__) #elif defined(__ICCARM__) #pragma section="HEAP" From cb36f2c472e660e1adfb64a096a199f95969fa1f Mon Sep 17 00:00:00 2001 From: bcostm Date: Thu, 22 Jan 2015 11:10:09 +0100 Subject: [PATCH 37/77] [NUCLEO_F303RE] Update SetSysClock function --- .../TARGET_STM32F3/TARGET_NUCLEO_F303RE/system_stm32f3xx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/system_stm32f3xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/system_stm32f3xx.c index b64ee6735b..697063c674 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/system_stm32f3xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/system_stm32f3xx.c @@ -375,6 +375,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) } RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { @@ -414,9 +415,10 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { From 66a5f716e38dd3b97c45687484f5738f76d81b89 Mon Sep 17 00:00:00 2001 From: Marcomissyou Date: Fri, 23 Jan 2015 16:40:26 +0800 Subject: [PATCH 38/77] modify i2c_api, analog_api, system_brf51822.c, targets/py and add device.h, PinNames --- .../TARGET_MCU_NRF51822/system_nrf51822.c | 4 +- .../TARGET_DFCM_NNN40/PinNames.h | 123 +++ .../TARGET_DFCM_NNN40/device.h | 57 ++ .../TARGET_DFCM_NNN40_DT0R.7z | Bin 0 -> 1375 bytes .../TARGET_MCU_NRF51822/analogin_api.c | 15 + .../TARGET_MCU_NRF51822/i2c_api.c | 13 + .../TARGET_MCU_NRF51822/rtc_api.c | 175 ++++ libraries/tests/mbed/analog_in/main.cpp | 4 +- libraries/tests/mbed/blinky/main.cpp | 54 +- workspace_tools/muts_all.json | 8 + workspace_tools/targets.py | 890 +++++++++++------- workspace_tools/test_spec.json | 5 + 12 files changed, 1002 insertions(+), 346 deletions(-) create mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40/device.h create mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R.7z create mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/rtc_api.c create mode 100644 workspace_tools/muts_all.json create mode 100644 workspace_tools/test_spec.json diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c index 7324f83eec..26a92ac236 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c @@ -21,7 +21,7 @@ #include "nrf51822.h" #include "system_nrf51822.h" -#ifdef DFCM_NNN40_DT0R +#ifdef TARGET_DFCM_NNN40 #define __SYSTEM_CLOCK (32000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 32MHz */ #else @@ -73,6 +73,8 @@ void SystemInit(void) #ifdef TARGET_HRM1017 NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos); +#elifdef TARGET_DFCM_NNN40 + NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos); #else NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos); #endif diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40/PinNames.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40/PinNames.h new file mode 100644 index 0000000000..6b435862c7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40/PinNames.h @@ -0,0 +1,123 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013 Nordic Semiconductor + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 3 + +typedef enum { + NC = (int)0xFFFFFFFF, + p0 = 0, + p1 = 1, + p2 = 2, + p3 = 3, + p4 = 4, + p5 = 5, + p6 = 6, + p7 = 7, + p8 = NC, + p9 = NC, + p10 = NC, + p11 = NC, + p12 = 12, + p13 = NC, + p14 = NC, + p15 = NC, + p16 = 16, + p17 = 17, + p18 = NC, + p19 = NC, + p20 = 20, + p21 = 21, + p22 = 22, + p23 = 23, + p24 = 24, + p25 = 25, + p26 = 26, + p27 = 27, + p28 = NC, + p29 = 29, + p30 = 30, + p31 = 31, + + LED1 = p1, + LED2 = p2, + + BUTTON0 = p16, + BUTTON1 = p17, + + RX_PIN_NUMBER = p16, + TX_PIN_NUMBER = p17, + + // mBed interface Pins + USBTX = TX_PIN_NUMBER, + USBRX = RX_PIN_NUMBER, + + SPI_PSELMOSI0 = p24, + SPI_PSELMISO0 = p29, + SPI_PSELSS0 = p6, + SPI_PSELSCK0 = p21, + + SPIS_PSELMOSI = p24, + SPIS_PSELMISO = p29, + SPIS_PSELSS = p6, + SPIS_PSELSCK = p21, + + I2C_SDA0 = p22, + I2C_SCL0 = p20, + + A0 = p0, + A1 = p1, + A2 = p2, + A3 = p3, + A4 = p4, + A5 = p5, + + // Not connected + + CTS_PIN_NUMBER = NC, + RTS_PIN_NUMBER = NC, + SPI_PSELMOSI1 = NC, + SPI_PSELMISO1 = NC, + SPI_PSELSS1 = NC, + SPI_PSELSCK1 = NC, + LED3 = NC, + LED4 = NC +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 3, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40/device.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40/device.h new file mode 100644 index 0000000000..fd66610a0c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40/device.h @@ -0,0 +1,57 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 0 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 1 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R.7z b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R.7z new file mode 100644 index 0000000000000000000000000000000000000000..7c0e9dbda0105386e5e7424be9ebe6e578409aae GIT binary patch literal 1375 zcmV-l1)%yjdc3bE8~_8shK$u51poj50000Z000000002x4gm517m9!;{c%r?0p0C| z1T&enHWy5&)&=qRl79BU@P2u=T{E=Q0m7f=aNP?37IcS+4Ltq^N$F(tqdiob*+zvA zQrW``hLFDdoVk!V=5$BbQ>j^|r8fp9D)!qd%pspCd=|~2pHVEdKG0Z)PPc%HzH~U{ zOUTaxm7f-#dfM6YyQqD2WN$s?fUh^1DC1wQMzYv%|88w;&lH(181}t{sm4DDHaEnH zLOk7STQ)X$=u2DGAqsNveU}c&6*R=u_9YO@(6X~Z?-*}K@s0y*UVFbe?e1_dO^T+w zj>SC>M^a)0!j5`7zU(iQudSsm3+N{&SEmG`GsMFf?us$dWk2AWr1-*mquYj;&29qN zVP)Fl#}E&kj2LdLk7=rBOrrck#k%K3$h$@F6jS`6?x9Y{9LULz|k3D{Ru z2cxa3Buv0o4D!!1CZ#H%JvNA}z5!->L9xp^NThrKcZi5dj%nV!D;)eB8LmT$Vi{=B z5iDrO)cXAX?E`%p(lPhs9P!4vc$1kCj!OeVr@#?b@R4>0udD z)L56zV|FF1VvK{0z>wA={hCR<%)COn36-*QR)U`ZWqxx!Gh~2|DYOrf_B4zKmkEUA z#Okw`K2KN6Zhc^&l(n2Cir45&PPk*A4(g=o{EAu}f!Qp_%oSz;IF<2Si#uJ;zjXp2 z3|~Uos9@G?SRwz;OG+>cnGc9f^>-(!wziiM4Uc&;+FgB-G^ldQaxM6U)M>X_7J{7D zNis%B<(sJmS?~zhB!iH;5<}uJAYm<;Cht&;lhN!#=!%?sd@J&#dl^vQ)oZD~-U~qB zz+d`r<6pcJ8^b|Rl05TtvofkAap_^tTyOe_TqLpil{Y4ClCYN0Vj3GuQZ^!SC1@rN;#ShK z$@V0M|FyszLukwJi#oOkU`2}$LEbAbr#f3hPTLgZziRkbFwKrzhlkcfTHwcDYP=Z0 zL*^8JQW0KDd-goOS2=UhMmCgUYRTk8UE!YoW`$OB)k-T1YJ3V<3Y*nhrSrS!7!CQrw5Hn>Aiyl*Jd?hOf7U zqXFVbvb#hQXZPK*cR!EQp45NF2sb@NxZzJm&?FfUC1(BnSSsUt-R9K*0D&_Ht`F5) zlE4=v)Bdx5FNu=AzC8-Dke@wABQE&hG7_N*%#;IOHhw>MwGZ@N(b+_NPKyirL8uuZ z=}ZSB2xP~K6&O&WlptP2KV%ZjFOQf$E5C8xSffot^!gA88008DEl%xOv literal 0 HcmV?d00001 diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/analogin_api.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/analogin_api.c index ab6da87545..a3058d012f 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/analogin_api.c @@ -22,6 +22,20 @@ #define ADC_10BIT_RANGE 0x3FF #define ADC_RANGE ADC_10BIT_RANGE +#ifdef TARGET_DFCM_NNN40 + +static const PinMap PinMap_ADC[] = { + {p0, ADC0_0, 4}, + {p1, ADC0_0, 8}, + {p2, ADC0_0, 16}, + {p3, ADC0_0, 32}, + {p4, ADC0_0, 64}, + {p5, ADC0_0, 128}, + {NC, NC, 0} +}; + +#else + static const PinMap PinMap_ADC[] = { {p1, ADC0_0, 4}, {p2, ADC0_0, 8}, @@ -31,6 +45,7 @@ static const PinMap PinMap_ADC[] = { {p6, ADC0_0, 128}, {NC, NC, 0} }; +#endif void analogin_init(analogin_t *obj, PinName pin) { diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/i2c_api.c index 63a21eddeb..3fdd0275d8 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/i2c_api.c @@ -18,7 +18,19 @@ #include "cmsis.h" #include "pinmap.h" + +#ifdef TARGET_DFCM_NNN40 static const PinMap PinMap_I2C_SDA[] = { + {I2C_SDA0, I2C_0, 1}, + {NC, NC, 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {I2C_SCL0, I2C_0, 1}, + {NC, NC, 0} +}; +#else + static const PinMap PinMap_I2C_SDA[] = { {p22, I2C_0, 1}, {p13, I2C_1, 2}, {NC, NC, 0} @@ -29,6 +41,7 @@ static const PinMap PinMap_I2C_SCL[] = { {p15, I2C_1, 2}, {NC, NC, 0} }; +#endif void i2c_interface_enable(i2c_t *obj) { diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/rtc_api.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/rtc_api.c new file mode 100644 index 0000000000..16b88ccb45 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/rtc_api.c @@ -0,0 +1,175 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "rtc_api.h" + +#if DEVICE_RTC + +#include "wait_api.h" + +#define LSE_STARTUP_TIMEOUT ((uint16_t)500) // delay in ms + +static int rtc_inited = 0; + +void rtc_init(void) { + uint32_t StartUpCounter = 0; + uint32_t LSEStatus = 0; + uint32_t rtc_freq = 0; + + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); // Enable PWR clock + + PWR_BackupAccessCmd(ENABLE); // Enable access to Backup domain + + // Reset back up registers + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); + + // Enable LSE clock + RCC_LSEConfig(RCC_LSE_ON); + + // Wait till LSE is ready + do { + LSEStatus = RCC_GetFlagStatus(RCC_FLAG_LSERDY); + wait_ms(1); + StartUpCounter++; + } while ((LSEStatus == 0) && (StartUpCounter <= LSE_STARTUP_TIMEOUT)); + + if (StartUpCounter > LSE_STARTUP_TIMEOUT) { + // The LSE has not started, use LSI instead. + // The RTC Clock may vary due to LSI frequency dispersion. + RCC_LSEConfig(RCC_LSE_OFF); + RCC_LSICmd(ENABLE); // Enable LSI + while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) {} // Wait until ready + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); // Select the RTC Clock Source + rtc_freq = 40000; // [TODO] To be measured precisely using a timer input capture + } else { + // The LSE has correctly started + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); // Select the RTC Clock Source + rtc_freq = LSE_VALUE; + } + + RCC_RTCCLKCmd(ENABLE); // Enable RTC Clock + + RTC_WaitForSynchro(); // Wait for RTC registers synchronization + + RTC_InitTypeDef RTC_InitStructure; + RTC_InitStructure.RTC_AsynchPrediv = 127; + RTC_InitStructure.RTC_SynchPrediv = (rtc_freq / 128) - 1; + RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24; + RTC_Init(&RTC_InitStructure); + + PWR_BackupAccessCmd(DISABLE); // Disable access to Backup domain + + rtc_inited = 1; +} + +void rtc_free(void) { + // Reset RTC + PWR_BackupAccessCmd(ENABLE); // Enable access to Backup Domain + RTC_DeInit(); + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); + // Disable RTC, LSE and LSI clocks + RCC_RTCCLKCmd(DISABLE); + RCC_LSEConfig(RCC_LSE_OFF); + RCC_LSICmd(DISABLE); + + rtc_inited = 0; +} + +int rtc_isenabled(void) { + return rtc_inited; +} + +/* + RTC Registers + RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday + RTC_Month 1=january, 2=february, ..., 12=december + RTC_Date day of the month 1-31 + RTC_Year year 0-99 + struct tm + tm_sec seconds after the minute 0-61 + tm_min minutes after the hour 0-59 + tm_hour hours since midnight 0-23 + tm_mday day of the month 1-31 + tm_mon months since January 0-11 + tm_year years since 1900 + tm_wday days since Sunday 0-6 + tm_yday days since January 1 0-365 + tm_isdst Daylight Saving Time flag +*/ +time_t rtc_read(void) { + RTC_DateTypeDef dateStruct; + RTC_TimeTypeDef timeStruct; + struct tm timeinfo; + + // Read actual date and time + RTC_GetTime(RTC_Format_BIN, &timeStruct); + RTC_GetDate(RTC_Format_BIN, &dateStruct); + + // Setup a tm structure based on the RTC + timeinfo.tm_wday = dateStruct.RTC_WeekDay; + timeinfo.tm_mon = dateStruct.RTC_Month - 1; + timeinfo.tm_mday = dateStruct.RTC_Date; + timeinfo.tm_year = dateStruct.RTC_Year + 100; + timeinfo.tm_hour = timeStruct.RTC_Hours; + timeinfo.tm_min = timeStruct.RTC_Minutes; + timeinfo.tm_sec = timeStruct.RTC_Seconds; + + // Convert to timestamp + time_t t = mktime(&timeinfo); + + return t; +} + +void rtc_write(time_t t) { + RTC_DateTypeDef dateStruct; + RTC_TimeTypeDef timeStruct; + + // Convert the time into a tm + struct tm *timeinfo = localtime(&t); + + // Fill RTC structures + dateStruct.RTC_WeekDay = timeinfo->tm_wday; + dateStruct.RTC_Month = timeinfo->tm_mon + 1; + dateStruct.RTC_Date = timeinfo->tm_mday; + dateStruct.RTC_Year = timeinfo->tm_year - 100; + timeStruct.RTC_Hours = timeinfo->tm_hour; + timeStruct.RTC_Minutes = timeinfo->tm_min; + timeStruct.RTC_Seconds = timeinfo->tm_sec; + timeStruct.RTC_H12 = RTC_HourFormat_24; + + // Change the RTC current date/time + PWR_BackupAccessCmd(ENABLE); // Enable access to RTC + RTC_SetDate(RTC_Format_BIN, &dateStruct); + RTC_SetTime(RTC_Format_BIN, &timeStruct); + PWR_BackupAccessCmd(DISABLE); // Disable access to RTC +} + +#endif diff --git a/libraries/tests/mbed/analog_in/main.cpp b/libraries/tests/mbed/analog_in/main.cpp index 157885df36..2886219396 100644 --- a/libraries/tests/mbed/analog_in/main.cpp +++ b/libraries/tests/mbed/analog_in/main.cpp @@ -50,9 +50,9 @@ int main() { } if (successes > 8) { - notify_success(true); + notify_completion(true); } else { - notify_success(false); + notify_completion(false); } } \ No newline at end of file diff --git a/libraries/tests/mbed/blinky/main.cpp b/libraries/tests/mbed/blinky/main.cpp index 3e6293939f..9c87526a67 100644 --- a/libraries/tests/mbed/blinky/main.cpp +++ b/libraries/tests/mbed/blinky/main.cpp @@ -1,12 +1,60 @@ #include "mbed.h" +#include "nrf_soc.h" + +#define CMD_POWER_DOWN (0xB9) + +DigitalOut LED00(p0); +DigitalOut LED01(p1); +DigitalOut LED02(p2); +DigitalOut LED03(p3); +DigitalOut LED04(p4); +DigitalOut LED05(p5); +DigitalOut Flash_CS(p28); +InterruptIn button(p20); + +void intoSystemoff() { + Flash_CS = 0; + LED00 = 0; + LED01 = 0; + LED02 = 0; + LED03 = 0; + //ble.init(); + wait(1); + NRF_POWER->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter; + //sd_power_system_off(); + //NRF_POWER->RAMON = POWER_RAMON_OFFRAM3_RAM3Off << POWER_RAMON_OFFRAM3_Pos; + //NRF_POWER->RAMON = POWER_RAMON_OFFRAM2_RAM2Off << POWER_RAMON_OFFRAM2_Pos; + //wait(5); + //NRF_POWER->RAMON = POWER_RAMON_OFFRAM1_RAM1On << POWER_RAMON_ONRAM1_Pos; + //NRF_POWER->RAMON = POWER_RAMON_OFFRAM0_RAM0On << POWER_RAMON_ONRAM0_Pos; + + } + +int main() { + LED00 = 1; + button.fall(&intoSystemoff); + for(;;) + { + LED03 = 1; + wait(1); + LED03 = 0; + wait(1); + } + + +} + + + +/*#include "mbed.h" DigitalOut myled(LED1); int main() { while(1) { myled = 1; - wait(0.2); + wait(2); myled = 0; - wait(0.2); + wait(2); } -} +}*/ diff --git a/workspace_tools/muts_all.json b/workspace_tools/muts_all.json new file mode 100644 index 0000000000..15a50fa70a --- /dev/null +++ b/workspace_tools/muts_all.json @@ -0,0 +1,8 @@ +{ + "1" : { + "mcu": "DFCM_NNN40", + "port":"COM55", + "disk":"F:\\", + "peripherals": [""] + } +} \ No newline at end of file diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 99dfebc301..8f73c57d66 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -16,12 +16,13 @@ limitations under the License. """ CORE_LABELS = { - "ARM7TDMI-S": "ARM7", - "Cortex-M0" : "M0", - "Cortex-M0+": "M0P", - "Cortex-M3" : "M3", - "Cortex-M4" : "M4", - "Cortex-M4F" : "M4" + "ARM7TDMI-S": ["ARM7"], + "Cortex-M0" : ["M0", "CORTEX_M"], + "Cortex-M0+": ["M0P", "CORTEX_M"], + "Cortex-M3" : ["M3", "CORTEX_M"], + "Cortex-M4" : ["M4", "CORTEX_M"], + "Cortex-M4F" : ["M4", "CORTEX_M"], + "Cortex-A9" : ["A9", "CORTEX_A"] } import os @@ -50,18 +51,22 @@ class Target: self.name = self.__class__.__name__ - # Code used to determine device' platform - self.detect_code = "" + # Code used to determine devices' platform + # This code is prefix in URL link provided in mbed.htm (in mbed disk) + self.detect_code = [] def program_cycle_s(self): return 4 if self.is_disk_virtual else 1.5 def get_labels(self): - return [self.name, CORE_LABELS[self.core]] + self.extra_labels + return [self.name] + CORE_LABELS[self.core] + self.extra_labels def init_hooks(self, hook, toolchain_name): pass + +### NXP ### + # This class implements the post-link patching step needed by LPC targets class LPCTarget(Target): def __init__(self): @@ -75,13 +80,117 @@ class LPCTarget(Target): t_self.debug("LPC Patch: %s" % os.path.split(binf)[1]) patch(binf) -class LPC2368(LPCTarget): +class LPC11C24(LPCTarget): def __init__(self): LPCTarget.__init__(self) - self.core = "ARM7TDMI-S" - self.extra_labels = ['NXP', 'LPC23XX'] - self.supported_toolchains = ["ARM", "GCC_ARM", "GCC_CR"] + self.core = "Cortex-M0" + self.extra_labels = ['NXP', 'LPC11XX_11CXX', 'LPC11CXX'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] +class LPC1114(LPCTarget): + def __init__(self): + LPCTarget.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['NXP', 'LPC11XX_11CXX', 'LPC11XX'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"] + self.default_toolchain = "uARM" + +class LPC11U24(LPCTarget): + def __init__(self): + LPCTarget.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['NXP', 'LPC11UXX', 'LPC11U24_401'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] + self.default_toolchain = "uARM" + self.detect_code = ["1040"] + +class OC_MBUINO(LPC11U24): + def __init__(self): + LPC11U24.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['NXP', 'LPC11UXX'] + self.macros = ['TARGET_LPC11U24'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] + self.default_toolchain = "uARM" + +class LPC11U24_301(LPCTarget): + def __init__(self): + LPCTarget.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['NXP', 'LPC11UXX'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] + +class LPC11U35_401(LPCTarget): + def __init__(self): + LPCTarget.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['NXP', 'LPC11UXX'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"] + self.default_toolchain = "uARM" + +class LPC11U35_501(LPCTarget): + def __init__(self): + LPCTarget.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['NXP', 'LPC11UXX', 'MCU_LPC11U35_501'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR" , "IAR"] + self.default_toolchain = "uARM" + +class LPC11U35_Y5_MBUG(LPCTarget): + def __init__(self): + LPCTarget.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['NXP', 'LPC11UXX', 'MCU_LPC11U35_501'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR" , "IAR"] + self.default_toolchain = "uARM" + +class LPC11U37_501(LPCTarget): + def __init__(self): + LPCTarget.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['NXP', 'LPC11UXX'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"] + self.default_toolchain = "uARM" + +class LPCCAPPUCCINO(LPC11U37_501): + def __init__(self): + LPC11U37_501.__init__(self) + +class ARCH_GPRS(LPCTarget): + def __init__(self): + LPCTarget.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['NXP', 'LPC11UXX', 'LPC11U37_501'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO"] + +class LPC11U68(LPCTarget): + def __init__(self): + LPCTarget.__init__(self) + self.core = "Cortex-M0+" + self.extra_labels = ['NXP', 'LPC11U6X'] + self.supported_toolchains = ["uARM", "GCC_CR", "GCC_ARM", "IAR"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO"] + self.detect_code = ["1168"] + +class LPC1347(LPCTarget): + def __init__(self): + LPCTarget.__init__(self) + self.core = "Cortex-M3" + self.extra_labels = ['NXP', 'LPC13XX'] + self.supported_toolchains = ["ARM", "GCC_ARM","IAR"] + +class LPC1549(LPCTarget): + def __init__(self): + LPCTarget.__init__(self) + self.core = "Cortex-M3" + self.extra_labels = ['NXP', 'LPC15XX'] + self.supported_toolchains = ["uARM", "GCC_CR", "GCC_ARM", "IAR"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO"] + self.detect_code = ["1549"] class LPC1768(LPCTarget): def __init__(self): @@ -89,91 +198,40 @@ class LPC1768(LPCTarget): self.core = "Cortex-M3" self.extra_labels = ['NXP', 'LPC176X', 'MBED_LPC1768'] self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CS", "GCC_CR", "IAR"] - self.detect_code = "1010" + self.detect_code = ["1010"] - -class LPC11U24(LPCTarget): +class ARCH_PRO(LPCTarget): def __init__(self): LPCTarget.__init__(self) - self.core = "Cortex-M0" - self.extra_labels = ['NXP', 'LPC11UXX', 'LPC11U24_401'] - self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"] - self.default_toolchain = "uARM" - self.detect_code = "1040" + self.core = "Cortex-M3" + self.extra_labels = ['NXP', 'LPC176X'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CS", "GCC_CR", "IAR"] + self.macros = ['TARGET_LPC1768'] + self.supported_form_factors = ["ARDUINO"] - -class LPC11U24_301(LPCTarget): +class UBLOX_C027(LPCTarget): def __init__(self): LPCTarget.__init__(self) - self.core = "Cortex-M0" - self.extra_labels = ['NXP', 'LPC11UXX'] - self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"] + self.core = "Cortex-M3" + self.extra_labels = ['NXP', 'LPC176X'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CS", "GCC_CR", "IAR"] + self.macros = ['TARGET_LPC1768'] + self.supported_form_factors = ["ARDUINO"] - -class KL05Z(Target): +class LPC2368(LPCTarget): def __init__(self): - Target.__init__(self) + LPCTarget.__init__(self) + self.core = "ARM7TDMI-S" + self.extra_labels = ['NXP', 'LPC23XX'] + self.supported_toolchains = ["ARM", "GCC_ARM", "GCC_CR"] + +class LPC810(LPCTarget): + def __init__(self): + LPCTarget.__init__(self) self.core = "Cortex-M0+" - self.extra_labels = ['Freescale', 'KLXX'] - self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"] + self.extra_labels = ['NXP', 'LPC81X'] + self.supported_toolchains = ["uARM", "IAR"] self.default_toolchain = "uARM" - self.supported_form_factors = ["ARDUINO"] - self.is_disk_virtual = True - - -class KL25Z(Target): - def __init__(self): - Target.__init__(self) - self.core = "Cortex-M0+" - self.extra_labels = ['Freescale', 'KLXX'] - self.supported_toolchains = ["ARM", "GCC_CW_EWL", "GCC_CW_NEWLIB", "GCC_ARM"] - self.supported_form_factors = ["ARDUINO"] - self.is_disk_virtual = True - self.detect_code = "0200" - - -class KL46Z(Target): - def __init__(self): - Target.__init__(self) - self.core = "Cortex-M0+" - self.extra_labels = ['Freescale', 'KLXX'] - self.supported_toolchains = ["GCC_ARM", "ARM"] - self.supported_form_factors = ["ARDUINO"] - self.is_disk_virtual = True - self.detect_code = "0220" - - -class K20D50M(Target): - def __init__(self): - Target.__init__(self) - self.core = "Cortex-M4" - self.extra_labels = ['Freescale'] - self.supported_toolchains = ["GCC_ARM", "ARM"] - self.is_disk_virtual = True - self.detect_code = "0230" - - -class K64F(Target): - def __init__(self): - Target.__init__(self) - self.core = "Cortex-M4F" - self.extra_labels = ['Freescale', 'KPSDK_MCUS', 'KPSDK_CODE', 'MCU_K64F', 'FRDM'] - self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED"] - self.supported_toolchains = ["ARM", "GCC_ARM"] - self.supported_form_factors = ["ARDUINO"] - self.is_disk_virtual = True - self.default_toolchain = "ARM" - self.detect_code = "0240" - - -class K22F(Target): - def __init__(self): - Target.__init__(self) - self.core = "Cortex-M4F" - self.extra_labels = ['Freescale', 'KPSDK_MCUS', 'KPSDK_CODE'] - self.macros = ["CPU_MK22FN512VLH12 ", "FSL_RTOS_MBED"] - self.supported_toolchains = ["ARM", "GCC_ARM"] - self.supported_form_factors = ["ARDUINO"] self.is_disk_virtual = True class LPC812(LPCTarget): @@ -181,29 +239,37 @@ class LPC812(LPCTarget): LPCTarget.__init__(self) self.core = "Cortex-M0+" self.extra_labels = ['NXP', 'LPC81X'] - self.supported_toolchains = ["uARM"] + self.supported_toolchains = ["uARM", "IAR"] self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO"] self.is_disk_virtual = True - self.detect_code = "1050" + self.detect_code = ["1050"] - -class LPC810(LPCTarget): +class LPC824(LPCTarget): def __init__(self): LPCTarget.__init__(self) self.core = "Cortex-M0+" - self.extra_labels = ['NXP', 'LPC81X'] + self.extra_labels = ['NXP', 'LPC82X'] + self.supported_toolchains = ["uARM", "GCC_ARM","GCC_CR"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO"] + self.is_disk_virtual = True + +class SSCI824(LPCTarget): + def __init__(self): + LPCTarget.__init__(self) + self.core = "Cortex-M0+" + self.extra_labels = ['NXP', 'LPC82X'] self.supported_toolchains = ["uARM"] self.default_toolchain = "uARM" self.is_disk_virtual = True - class LPC4088(LPCTarget): def __init__(self): LPCTarget.__init__(self) self.core = "Cortex-M4F" self.extra_labels = ['NXP', 'LPC408X'] - self.supported_toolchains = ["ARM", "GCC_CR", "GCC_ARM"] + self.supported_toolchains = ["ARM", "GCC_CR", "GCC_ARM", "IAR"] self.is_disk_virtual = True def init_hooks(self, hook, toolchain_name): @@ -247,7 +313,6 @@ class LPC4330_M4(LPCTarget): self.extra_labels = ['NXP', 'LPC43XX', 'LPC4330'] self.supported_toolchains = ["ARM", "GCC_CR", "IAR", "GCC_ARM"] - class LPC4330_M0(LPCTarget): def __init__(self): LPCTarget.__init__(self) @@ -270,111 +335,211 @@ class LPC1800(LPCTarget): self.supported_toolchains = ["ARM", "GCC_CR", "IAR"] -class STM32F407(Target): +### Freescale ### + +class KL05Z(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0+" + self.extra_labels = ['Freescale', 'KLXX'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO"] + self.is_disk_virtual = True + +class KL25Z(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0+" + self.extra_labels = ['Freescale', 'KLXX'] + self.supported_toolchains = ["ARM", "GCC_CW_EWL", "GCC_CW_NEWLIB", "GCC_ARM","IAR"] + self.supported_form_factors = ["ARDUINO"] + self.is_disk_virtual = True + self.detect_code = ["0200"] + +class KL43Z(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0+" + self.extra_labels = ['Freescale', 'KLXX'] + self.supported_toolchains = ["GCC_ARM", "ARM"] + self.supported_form_factors = ["ARDUINO"] + self.is_disk_virtual = True + +class KL46Z(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0+" + self.extra_labels = ['Freescale', 'KLXX'] + self.supported_toolchains = ["GCC_ARM", "ARM", "IAR"] + self.supported_form_factors = ["ARDUINO"] + self.is_disk_virtual = True + self.detect_code = ["0220"] + +class K20D50M(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4" + self.extra_labels = ['Freescale'] + self.supported_toolchains = ["GCC_ARM", "ARM", "IAR"] + self.is_disk_virtual = True + self.detect_code = ["0230"] + +class K22F(Target): def __init__(self): Target.__init__(self) self.core = "Cortex-M4F" - self.extra_labels = ['STM', 'STM32F4', 'STM32F4XX'] - self.supported_toolchains = ["ARM", "GCC_ARM"] + self.extra_labels = ['Freescale', 'KPSDK_MCUS', 'KPSDK_CODE'] + self.macros = ["CPU_MK22FN512VLH12", "FSL_RTOS_MBED"] + self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] + self.supported_form_factors = ["ARDUINO"] + self.is_disk_virtual = True + self.detect_code = ["0201"] +class K64F(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['Freescale', 'KPSDK_MCUS', 'KPSDK_CODE', 'MCU_K64F', 'FRDM'] + self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED"] + self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] + self.supported_form_factors = ["ARDUINO"] + self.is_disk_virtual = True + self.default_toolchain = "ARM" + self.detect_code = ["0240"] + +class MTS_GAMBIT(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['Freescale', 'KPSDK_MCUS', 'KPSDK_CODE', 'MCU_K64F'] + self.supported_toolchains = ["ARM", "GCC_ARM"] + self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"] + self.is_disk_virtual = True + self.default_toolchain = "ARM" + + +### STMicro ### class NUCLEO_F030R8(Target): def __init__(self): Target.__init__(self) self.core = "Cortex-M0" self.extra_labels = ['STM', 'STM32F0', 'STM32F030R8'] - self.supported_toolchains = ["ARM", "uARM"] + self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"] self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO", "MORPHO"] - self.detect_code = "0725" + self.detect_code = ["0725"] +class NUCLEO_F070RB(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['STM', 'STM32F0', 'STM32F070RB'] + self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO", "MORPHO"] + self.detect_code = ["0755"] class NUCLEO_F072RB(Target): def __init__(self): Target.__init__(self) self.core = "Cortex-M0" self.extra_labels = ['STM', 'STM32F0', 'STM32F072RB'] - self.supported_toolchains = ["ARM", "uARM"] + self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"] self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO", "MORPHO"] - self.detect_code = "0730" + self.detect_code = ["0730"] +class NUCLEO_F091RC(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['STM', 'STM32F0', 'STM32F091RC'] + self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO", "MORPHO"] + self.detect_code = ["0731"] class NUCLEO_F103RB(Target): def __init__(self): Target.__init__(self) self.core = "Cortex-M3" self.extra_labels = ['STM', 'STM32F1', 'STM32F103RB'] - self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO", "MORPHO"] - self.detect_code = "0700" - + self.detect_code = ["0700"] class NUCLEO_F302R8(Target): def __init__(self): Target.__init__(self) self.core = "Cortex-M4F" self.extra_labels = ['STM', 'STM32F3', 'STM32F302R8'] - self.supported_toolchains = ["ARM", "uARM"] + self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"] self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO", "MORPHO"] - self.detect_code = "0705" + self.detect_code = ["0705"] +class NUCLEO_F303RE(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32F3', 'STM32F303RE'] + self.supported_toolchains = ["ARM", "uARM", "IAR"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO", "MORPHO"] + self.detect_code = ["0706"] class NUCLEO_F334R8(Target): def __init__(self): Target.__init__(self) self.core = "Cortex-M4F" self.extra_labels = ['STM', 'STM32F3', 'STM32F334R8'] - self.supported_toolchains = ["ARM", "uARM"] + self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"] self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO", "MORPHO"] - self.detect_code = "0735" - + self.detect_code = ["0735"] class NUCLEO_F401RE(Target): def __init__(self): Target.__init__(self) self.core = "Cortex-M4F" self.extra_labels = ['STM', 'STM32F4', 'STM32F401RE'] - self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO", "MORPHO"] - self.detect_code = "0720" - + self.detect_code = ["0720"] class NUCLEO_F411RE(Target): def __init__(self): Target.__init__(self) self.core = "Cortex-M4F" self.extra_labels = ['STM', 'STM32F4', 'STM32F411RE'] - self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO", "MORPHO"] - self.detect_code = "0740" - + self.detect_code = ["0740"] class NUCLEO_L053R8(Target): def __init__(self): Target.__init__(self) self.core = "Cortex-M0+" self.extra_labels = ['STM', 'STM32L0', 'STM32L053R8'] - self.supported_toolchains = ["ARM", "uARM"] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO", "MORPHO"] - self.detect_code = "0715" - + self.detect_code = ["0715"] class NUCLEO_L152RE(Target): def __init__(self): Target.__init__(self) self.core = "Cortex-M3" self.extra_labels = ['STM', 'STM32L1', 'STM32L152RE'] - self.supported_toolchains = ["ARM", "uARM"] + self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"] self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO", "MORPHO"] - self.detect_code = "0710" + self.detect_code = ["0710"] class STM32F3XX(Target): def __init__(self): @@ -384,73 +549,123 @@ class STM32F3XX(Target): self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"] self.default_toolchain = "uARM" - -class LPC1347(LPCTarget): +class STM32F407(Target): def __init__(self): - LPCTarget.__init__(self) - self.core = "Cortex-M3" - self.extra_labels = ['NXP', 'LPC13XX'] - self.supported_toolchains = ["ARM", "GCC_ARM"] + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32F4', 'STM32F4XX'] + self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] - -class LPC1114(LPCTarget): +class ARCH_MAX(Target): def __init__(self): - LPCTarget.__init__(self) - self.core = "Cortex-M0" - self.extra_labels = ['NXP', 'LPC11XX_11CXX', 'LPC11XX'] - self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR"] - self.default_toolchain = "uARM" - - -class LPC11C24(LPCTarget): - def __init__(self): - LPCTarget.__init__(self) - self.core = "Cortex-M0" - self.extra_labels = ['NXP', 'LPC11XX_11CXX', 'LPC11CXX'] + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32F4', 'STM32F407', 'STM32F407VG'] self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"] - -class LPC11U35_401(LPCTarget): +class DISCO_F051R8(Target): def __init__(self): - LPCTarget.__init__(self) + Target.__init__(self) self.core = "Cortex-M0" - self.extra_labels = ['NXP', 'LPC11UXX'] - self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR"] + self.extra_labels = ['STM', 'STM32F0', 'STM32F051', 'STM32F051R8'] + self.supported_toolchains = ["GCC_ARM"] self.default_toolchain = "uARM" - -class LPC11U35_501(LPCTarget): +class DISCO_F100RB(Target): def __init__(self): - LPCTarget.__init__(self) - self.core = "Cortex-M0" - self.extra_labels = ['NXP', 'LPC11UXX', 'MCU_LPC11U35_501'] - self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR"] - self.default_toolchain = "uARM" - - -class LPC11U37_501(LPCTarget): - def __init__(self): - LPCTarget.__init__(self) - self.core = "Cortex-M0" - self.extra_labels = ['NXP', 'LPC11UXX'] - self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR"] - self.default_toolchain = "uARM" - - -class UBLOX_C027(LPCTarget): - def __init__(self): - LPCTarget.__init__(self) + Target.__init__(self) self.core = "Cortex-M3" - self.extra_labels = ['NXP', 'LPC176X'] - self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CS", "GCC_CR", "IAR"] - self.macros = ['TARGET_LPC1768'] - self.supported_form_factors = ["ARDUINO"] + self.extra_labels = ['STM', 'STM32F1', 'STM32F100RB'] + self.supported_toolchains = ["GCC_ARM"] + self.default_toolchain = "uARM" +class DISCO_F303VC(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32F3', 'STM32F303', 'STM32F303VC'] + self.supported_toolchains = ["GCC_ARM"] + self.default_toolchain = "uARM" + +class DISCO_F334C8(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32F3', 'STM32F334C8'] + self.supported_toolchains = ["GCC_ARM",] + self.default_toolchain = "GCC_ARM" + self.detect_code = ["0735"] + +class DISCO_F407VG(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32F4', 'STM32F407', 'STM32F407VG'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"] + +class DISCO_F429ZI(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32F4', 'STM32F429', 'STM32F429ZI'] + self.supported_toolchains = ["GCC_ARM", "IAR"] + self.default_toolchain = "GCC_ARM" + +class DISCO_L053C8(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0+" + self.extra_labels = ['STM', 'STM32L0', 'STM32L053C8'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"] + self.default_toolchain = "uARM" + +class MTS_MDOT_F405RG(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32F4', 'STM32F405RG'] + self.macros = ['HSE_VALUE=26000000', 'OS_CLOCK=48000000'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] + self.is_disk_virtual = True + self.default_toolchain = "ARM" + +class MTS_MDOT_F411RE(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32F4', 'STM32F411RE'] + self.macros = ['HSE_VALUE=26000000', 'OS_CLOCK=96000000', 'USE_PLL_HSE_EXTC=0'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] + self.default_toolchain = "uARM" + +class MTS_DRAGONFLY_F411RE(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32F4', 'STM32F411RE'] + self.macros = ['HSE_VALUE=26000000'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] + self.default_toolchain = "ARM" + +class DISCO_F401VC(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32F4', 'STM32F401', 'STM32F401VC'] + self.supported_toolchains = ["GCC_ARM"] + self.default_toolchain = "GCC_ARM" + + +### Nordic ### class NRF51822(Target): # the following is a list of possible Nordic softdevices in decreasing order # of preference. EXPECTED_SOFTDEVICES_WITH_OFFSETS = [ + { + 'name' : 's110_nrf51822_7.1.0_softdevice.hex', + 'offset' : 0x16000 + }, { 'name' : 's110_nrf51822_7.0.0_softdevice.hex', 'offset' : 0x16000 @@ -461,6 +676,7 @@ class NRF51822(Target): } ] OUTPUT_EXT = '.hex' + MERGE_SOFT_DEVICE = True def __init__(self): Target.__init__(self) @@ -468,13 +684,13 @@ class NRF51822(Target): self.extra_labels = ["NORDIC", "NRF51822_MKIT", "MCU_NRF51822", "MCU_NORDIC_16K"] self.supported_toolchains = ["ARM", "GCC_ARM"] self.is_disk_virtual = True - self.detect_code = "1070" + self.detect_code = ["1070"] def program_cycle_s(self): return 6 def init_hooks(self, hook, toolchain_name): - if toolchain_name in ['ARM_STD', 'ARM_MICRO']: + if toolchain_name in ['ARM_STD', 'ARM_MICRO', 'GCC_ARM']: hook.hook_add_binary("post", self.binary_hook) @staticmethod @@ -497,44 +713,21 @@ class NRF51822(Target): binh = IntelHex() binh.loadbin(binf, offset=softdeviceAndOffsetEntry['offset']) - sdh = IntelHex(hexf) - sdh.merge(binh) + if t_self.target.MERGE_SOFT_DEVICE is True: + sdh = IntelHex(hexf) + binh.merge(sdh) with open(binf.replace(".bin", ".hex"), "w") as f: - sdh.tofile(f, format='hex') + binh.tofile(f, format='hex') - -class NRF51822_OTA(Target): +class NRF51822_OTA(NRF51822): def __init__(self): - Target.__init__(self) + NRF51822.__init__(self) self.core = "Cortex-M0" self.extra_labels = ["NORDIC", "NRF51822_MKIT", "MCU_NRF51822", "MCU_NORDIC_16K", "NRF51822"] self.macros = ['TARGET_NRF51822', 'TARGET_OTA_ENABLED'] self.supported_toolchains = ["ARM", "GCC_ARM"] - self.is_disk_virtual = True - - -class ARCH_BLE(NRF51822): - def __init__(self): - NRF51822.__init__(self) - self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] - self.macros = ['TARGET_NRF51822'] - self.supported_form_factors = ["ARDUINO"] - - -class HRM1017(NRF51822): - def __init__(self): - NRF51822.__init__(self) - self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] - self.macros = ['TARGET_NRF51822'] - - -class RBLAB_NRF51822(NRF51822): - def __init__(self): - NRF51822.__init__(self) - self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] - self.macros = ['TARGET_NRF51822'] - + self.MERGE_SOFT_DEVICE = False class NRF51_DK(NRF51822): def __init__(self): @@ -543,124 +736,98 @@ class NRF51_DK(NRF51822): self.macros = ['TARGET_NRF51822'] self.supported_form_factors = ["ARDUINO"] - -class NRF51_DK_OTA(Target): +class NRF51_DK_OTA(NRF51822): def __init__(self): - Target.__init__(self) + NRF51822.__init__(self) self.core = "Cortex-M0" - self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_32K', "NRF51_DK"] + self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_32K', 'NRF51_DK'] self.macros = ['TARGET_NRF51822', 'TARGET_NRF51_DK', 'TARGET_OTA_ENABLED'] self.supported_toolchains = ["ARM", "GCC_ARM"] - self.is_disk_virtual = True - -class DFCM_NNN40_DT0R(Target): + self.MERGE_SOFT_DEVICE = False + +class NRF51_DONGLE(NRF51822): def __init__(self): - Target.__init__(self) - self.core = "Cortex-M0" + NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_32K'] - self.macros = ['TARGET_NRF51822', 'TARGET_OTA_ENABLED'] - self.supported_toolchains = ["ARM", "GCC_ARM"] - self.is_disk_virtual = True + self.macros = ['TARGET_NRF51822'] - -class LPC1549(LPCTarget): +class ARCH_BLE(NRF51822): def __init__(self): - LPCTarget.__init__(self) - self.core = "Cortex-M3" - self.extra_labels = ['NXP', 'LPC15XX'] - self.supported_toolchains = ["uARM", "GCC_CR", "GCC_ARM"] - self.default_toolchain = "uARM" + NRF51822.__init__(self) + self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] + self.macros = ['TARGET_NRF51822'] self.supported_form_factors = ["ARDUINO"] - self.detect_code = "1549" - -class LPC11U68(LPCTarget): +class BLE_SMURFS(NRF51822): def __init__(self): - LPCTarget.__init__(self) - self.core = "Cortex-M0+" - self.extra_labels = ['NXP', 'LPC11U6X'] - self.supported_toolchains = ["uARM", "GCC_CR", "GCC_ARM"] - self.default_toolchain = "uARM" + NRF51822.__init__(self) + self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] + self.macros = ['TARGET_NRF51822'] + +class BLE_SMURFS_OTA(NRF51822): + def __init__(self): + NRF51822.__init__(self) + self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] + self.macros = ['TARGET_NRF51822', 'TARGET_BLE_SMURFS', 'TARGET_OTA_ENABLED'] + self.MERGE_SOFT_DEVICE = False + +class HRM1017(NRF51822): + def __init__(self): + NRF51822.__init__(self) + self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] + self.macros = ['TARGET_NRF51822'] + +class RBLAB_NRF51822(NRF51822): + def __init__(self): + NRF51822.__init__(self) + self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] + self.macros = ['TARGET_NRF51822'] self.supported_form_factors = ["ARDUINO"] - self.detect_code = "1168" - -class DISCO_F100RB(Target): +class RBLAB_BLENANO(NRF51822): def __init__(self): - Target.__init__(self) - self.core = "Cortex-M3" - self.extra_labels = ['STM', 'STM32F1', 'STM32F100RB'] - self.supported_toolchains = ["GCC_ARM"] - self.default_toolchain = "uARM" + NRF51822.__init__(self) + self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] + self.macros = ['TARGET_NRF51822'] - -class DISCO_F051R8(Target): +class NRF51822_Y5_MBUG(NRF51822): def __init__(self): - Target.__init__(self) - self.core = "Cortex-M0" - self.extra_labels = ['STM', 'STM32F0', 'STM32F051', 'STM32F051R8'] - self.supported_toolchains = ["GCC_ARM"] - self.default_toolchain = "uARM" - - -class DISCO_F407VG(Target): - def __init__(self): - Target.__init__(self) - self.core = "Cortex-M4F" - self.extra_labels = ['STM', 'STM32F4', 'STM32F407', 'STM32F407VG'] - self.supported_toolchains = ["ARM", "GCC_ARM"] - self.default_toolchain = "uARM" - -class ARCH_MAX(Target): - def __init__(self): - Target.__init__(self) - self.core = "Cortex-M4F" - self.extra_labels = ['STM', 'STM32F4', 'STM32F407', 'STM32F407VG'] - self.supported_toolchains = ["ARM", "GCC_ARM"] - self.default_toolchain = "uARM" - -class DISCO_F303VC(Target): - def __init__(self): - Target.__init__(self) - self.core = "Cortex-M4F" - self.extra_labels = ['STM', 'STM32F3', 'STM32F303', 'STM32F303VC'] - self.supported_toolchains = ["GCC_ARM"] - self.default_toolchain = "uARM" - + NRF51822.__init__(self) + self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] + self.macros = ['TARGET_NRF51822'] class XADOW_M0(LPCTarget): def __init__(self): LPCTarget.__init__(self) self.core = "Cortex-M0" self.extra_labels = ['NXP', 'LPC11UXX', 'MCU_LPC11U35_501'] - self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR"] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"] self.default_toolchain = "uARM" - -class ARCH_PRO(LPCTarget): +class WALLBOT_BLE(NRF51822): def __init__(self): - LPCTarget.__init__(self) - self.core = "Cortex-M3" - self.extra_labels = ['NXP', 'LPC176X'] - self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CS", "GCC_CR", "IAR"] - self.macros = ['TARGET_LPC1768'] - self.supported_form_factors = ["ARDUINO"] - - -class ARCH_GPRS(LPCTarget): + NRF51822.__init__(self) + self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] + self.macros = ['TARGET_NRF51822'] + +class DFCM_NNN40(NRF51822): def __init__(self): - LPCTarget.__init__(self) + NRF51822.__init__(self) self.core = "Cortex-M0" - self.extra_labels = ['NXP', 'LPC11UXX', 'LPC11U37_501'] - self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR"] - self.default_toolchain = "uARM" - self.supported_form_factors = ["ARDUINO"] + self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] + self.macros = ['TARGET_NRF51822'] + self.supported_toolchains = "GCC_ARM" - -class LPCCAPPUCCINO(LPC11U37_501): +class DFCM_NNN40_OTA(NRF51822): def __init__(self): - LPC11U37_501.__init__(self) + NRF51822.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'DFCM_NNN40'] + self.macros = ['TARGET_NRF51822', 'TARGET_DFCM_NNN40','TARGET_OTA_ENABLED'] + self.supported_toolchains = "GCC_ARM" + self.MERGE_SOFT_DEVICE = False +### ARM ### class ARM_MPS2(Target): def __init__(self): @@ -671,81 +838,114 @@ class ARM_MPS2(Target): self.default_toolchain = "ARM" -class OC_MBUINO(LPC11U24): - def __init__(self): - LPC11U24.__init__(self) - self.core = "Cortex-M0" - self.extra_labels = ['NXP', 'LPC11UXX'] - self.macros = ['TARGET_LPC11U24'] - self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"] - self.default_toolchain = "uARM" +### Renesas ### -class MTS_GAMBIT(Target): +class RZ_A1H(Target): def __init__(self): Target.__init__(self) - self.core = "Cortex-M4F" - self.extra_labels = ['Freescale', 'KPSDK_MCUS', 'KPSDK_CODE', 'MCU_K64F'] - self.supported_toolchains = ["ARM", "GCC_ARM"] - self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"] - self.is_disk_virtual = True + self.core = "Cortex-A9" + self.extra_labels = ['RENESAS', 'MBRZA1H'] + self.supported_toolchains = ["ARM"] + self.supported_form_factors = ["ARDUINO"] self.default_toolchain = "ARM" + def program_cycle_s(self): + return 2 + + + # Get a single instance for each target TARGETS = [ - LPC2368(), - LPC1768(), + + ### NXP ### + LPC11C24(), LPC11U24(), + OC_MBUINO(), # LPC11U24 LPC11U24_301(), - KL05Z(), - KL25Z(), - KL46Z(), - K20D50M(), - K64F(), - K22F(), - LPC812(), + LPC11U35_401(), + LPC11U35_501(), + XADOW_M0(), # LPC11U35_501 + LPC11U35_Y5_MBUG(), + LPC11U37_501(), + LPCCAPPUCCINO(),# LPC11U37_501 + ARCH_GPRS(), # LPC11U37_501 + LPC11U68(), + LPC1114(), + LPC1347(), + LPC1549(), + LPC1768(), + ARCH_PRO(), # LPC1768 + UBLOX_C027(), # LPC1768 + LPC2368(), LPC810(), + LPC812(), + LPC824(), + SSCI824(), # LPC824 LPC4088(), LPC4330_M4(), + LPC4330_M0(), LPC4337(), - STM32F3XX(), - STM32F407(), + + ### Freescale ### + KL05Z(), + KL25Z(), + KL43Z(), + KL46Z(), + K20D50M(), + K22F(), + K64F(), + MTS_GAMBIT(), # FRDM K64F + + ### STMicro ### NUCLEO_F030R8(), + NUCLEO_F070RB(), NUCLEO_F072RB(), + NUCLEO_F091RC(), NUCLEO_F103RB(), NUCLEO_F302R8(), + NUCLEO_F303RE(), NUCLEO_F334R8(), NUCLEO_F401RE(), NUCLEO_F411RE(), NUCLEO_L053R8(), NUCLEO_L152RE(), - LPC1347(), - LPC1114(), - LPC11C24(), - LPC11U35_401(), - LPC11U35_501(), - NRF51822(), - NRF51822_OTA(), - UBLOX_C027(), - LPC1549(), - LPC11U68(), + STM32F3XX(), + STM32F407(), DISCO_F051R8(), DISCO_F100RB(), DISCO_F303VC(), - DISCO_F407VG(), - XADOW_M0(), - ARCH_BLE(), + DISCO_F334C8(), + DISCO_F407VG(), # STM32F407 + ARCH_MAX(), # STM32F407 + DISCO_F429ZI(), + DISCO_L053C8(), + MTS_MDOT_F405RG(), + MTS_MDOT_F411RE(), + MTS_DRAGONFLY_F411RE(), + DISCO_F401VC(), + + ### Nordic ### + NRF51822(), + NRF51822_OTA(), # nRF51822 NRF51_DK(), - NRF51_DK_OTA(), - DFCM_NNN40_DT0R(), - ARCH_PRO(), - ARCH_GPRS(), - LPCCAPPUCCINO(), - HRM1017(), + NRF51_DK_OTA(), # nRF51822 + NRF51_DONGLE(), + ARCH_BLE(), # nRF51822 + BLE_SMURFS(), + BLE_SMURFS_OTA(), + HRM1017(), # nRF51822 + RBLAB_NRF51822(),# nRF51822 + RBLAB_BLENANO(),# nRF51822 + NRF51822_Y5_MBUG(),#nRF51822 + WALLBOT_BLE(), # nRF51822 + DFCM_NNN40(), # nRF51822 + DFCM_NNN40_OTA(), + + ### ARM ### ARM_MPS2(), - RBLAB_NRF51822(), - OC_MBUINO(), - MTS_GAMBIT(), - ARCH_MAX(), + + ### Renesas ### + RZ_A1H(), ] # Map each target name to its unique instance @@ -757,3 +957,13 @@ TARGET_NAMES = TARGET_MAP.keys() # Some targets with different name have the same exporters EXPORT_MAP = {} + +# Detection APIs +def get_target_detect_codes(): + """ Returns dictionary mapping detect_code -> platform_name + """ + result = {} + for target in TARGETS: + for detect_code in target.detect_code: + result[detect_code] = target.name + return result diff --git a/workspace_tools/test_spec.json b/workspace_tools/test_spec.json new file mode 100644 index 0000000000..923a52e50c --- /dev/null +++ b/workspace_tools/test_spec.json @@ -0,0 +1,5 @@ +{ + "targets": { + "DFCM_NNN40" : ["GCC_ARM"] + } +} \ No newline at end of file From 466223a617cc9b0aace84b7e7c0966e7aa4c7f9d Mon Sep 17 00:00:00 2001 From: ZKvAH Date: Sat, 24 Jan 2015 13:38:20 +0800 Subject: [PATCH 39/77] fix read_result always false read_result always false when read file success --- libraries/tests/mbed/sd/main.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/libraries/tests/mbed/sd/main.cpp b/libraries/tests/mbed/sd/main.cpp index ef7151e810..1e192811bc 100644 --- a/libraries/tests/mbed/sd/main.cpp +++ b/libraries/tests/mbed/sd/main.cpp @@ -86,6 +86,7 @@ int main() printf("SD: Reading data ... "); FILE *f = fopen(sd_file_path, "r"); if (f) { + read_result = true; for (int i = 0; i < DATA_SIZE; i++) { uint8_t data = fgetc(f); if (data != data_written[i]) { From 19fd60321b9055843b55a6a309318a9cce931eea Mon Sep 17 00:00:00 2001 From: "nitin.bhaskar.27.09@gmail.com" Date: Sat, 24 Jan 2015 22:57:01 +0530 Subject: [PATCH 40/77] On-Board SD Card support added, SD Card related test cases updated too --- .../TARGET_LPC11UXX/TARGET_LPC11U37H_401/PinNames.h | 6 ++++++ libraries/tests/mbed/dir_sd/main.cpp | 2 ++ libraries/tests/mbed/sd/main.cpp | 3 +++ libraries/tests/mbed/sd_perf_fatfs/main.cpp | 3 +++ libraries/tests/mbed/sd_perf_fhandle/main.cpp | 3 +++ libraries/tests/mbed/sd_perf_stdio/main.cpp | 3 +++ 6 files changed, 20 insertions(+) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PinNames.h index f1d484c9d2..9a0e81a15b 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PinNames.h @@ -139,6 +139,12 @@ typedef enum { SDA= P0_5, // same port as A4 SCL= P0_4, // same port as A5 + //SD Card pins + SDMOSI = P0_9, + SDMISO = P0_8, + SDSCLK = P1_29, + SDSSEL = P1_12, + // Not connected NC = (int)0xFFFFFFFF, } PinName; diff --git a/libraries/tests/mbed/dir_sd/main.cpp b/libraries/tests/mbed/dir_sd/main.cpp index c88d589bcb..c29bd39e87 100644 --- a/libraries/tests/mbed/dir_sd/main.cpp +++ b/libraries/tests/mbed/dir_sd/main.cpp @@ -79,6 +79,8 @@ int main() defined(TARGET_NUCLEO_L053R8) || \ defined(TARGET_NUCLEO_L152RE) SDFileSystem sd(D11, D12, D13, D10, "sd"); +#elif defined(TARGET_LPC11U37H_401) + SDFileSystem sd(SDMOSI, SDMISO, SDSCLK, SDSSEL, "sd"); #else SDFileSystem sd(p11, p12, p13, p14, "sd"); #endif diff --git a/libraries/tests/mbed/sd/main.cpp b/libraries/tests/mbed/sd/main.cpp index ef7151e810..5dbdb563e8 100644 --- a/libraries/tests/mbed/sd/main.cpp +++ b/libraries/tests/mbed/sd/main.cpp @@ -49,6 +49,9 @@ SDFileSystem sd(D11, D12, D13, D10, "sd"); #elif defined(TARGET_RZ_A1H) SDFileSystem sd(P8_5, P8_6, P8_3, P8_4, "sd"); +#elif defined(TARGET_LPC11U37H_401) +SDFileSystem sd(SDMOSI, SDMISO, SDSCLK, SDSSEL, "sd"); + #else SDFileSystem sd(p11, p12, p13, p14, "sd"); #endif diff --git a/libraries/tests/mbed/sd_perf_fatfs/main.cpp b/libraries/tests/mbed/sd_perf_fatfs/main.cpp index 79bf184db7..beb2ef25b1 100644 --- a/libraries/tests/mbed/sd_perf_fatfs/main.cpp +++ b/libraries/tests/mbed/sd_perf_fatfs/main.cpp @@ -48,6 +48,9 @@ SDFileSystem sd(D11, D12, D13, D10, "sd"); #elif defined(TARGET_LPC1549) SDFileSystem sd(D11, D12, D13, D10, "sd"); +#elif defined(TARGET_LPC11U37H_401) +SDFileSystem sd(SDMOSI, SDMISO, SDSCLK, SDSSEL, "sd"); + #else SDFileSystem sd(p11, p12, p13, p14, "sd"); #endif diff --git a/libraries/tests/mbed/sd_perf_fhandle/main.cpp b/libraries/tests/mbed/sd_perf_fhandle/main.cpp index 016c0b7e61..375f29a91a 100644 --- a/libraries/tests/mbed/sd_perf_fhandle/main.cpp +++ b/libraries/tests/mbed/sd_perf_fhandle/main.cpp @@ -48,6 +48,9 @@ SDFileSystem sd(D11, D12, D13, D10, "sd"); #elif defined(TARGET_LPC1549) SDFileSystem sd(D11, D12, D13, D10, "sd"); +#elif defined(TARGET_LPC11U37H_401) +SDFileSystem sd(SDMOSI, SDMISO, SDSCLK, SDSSEL, "sd"); + #else SDFileSystem sd(p11, p12, p13, p14, "sd"); #endif diff --git a/libraries/tests/mbed/sd_perf_stdio/main.cpp b/libraries/tests/mbed/sd_perf_stdio/main.cpp index 3f19087f08..598dba143c 100644 --- a/libraries/tests/mbed/sd_perf_stdio/main.cpp +++ b/libraries/tests/mbed/sd_perf_stdio/main.cpp @@ -48,6 +48,9 @@ SDFileSystem sd(D11, D12, D13, D10, "sd"); #elif defined(TARGET_LPC1549) SDFileSystem sd(D11, D12, D13, D10, "sd"); +#elif defined(TARGET_LPC11U37H_401) +SDFileSystem sd(SDMOSI, SDMISO, SDSCLK, SDSSEL, "sd"); + #else SDFileSystem sd(p11, p12, p13, p14, "sd"); #endif From 3b7d9635b7d882d7b6c936445f1743b2eef56c50 Mon Sep 17 00:00:00 2001 From: Willem23 Date: Sat, 24 Jan 2015 20:59:01 +0100 Subject: [PATCH 41/77] I2C blockread and blockwrite fixed for LPC812 Quick fix of block read and write. The i2c_start is still wrong: it should setup the address before initiating a Start condition. Status read is also wrong in i2c_do_read. --- .../hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c | 88 ++++++++++++------- 1 file changed, 57 insertions(+), 31 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c index c0de44279d..1fa7d11ab7 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c @@ -86,11 +86,16 @@ inline int i2c_start(i2c_t *obj) { return status; } + + +//Generate Stop condition and wait until bus is Idle +//Will also send NAK for previous RD inline int i2c_stop(i2c_t *obj) { int timeout = 0; - obj->i2c->MSTCTL = (1 << 2) | (1 << 0); - while ((obj->i2c->STAT & ((1 << 0) | (7 << 1))) != ((1 << 0) | (0 << 1))) { + obj->i2c->MSTCTL = (1 << 2) | (1 << 0); // STP bit and Continue bit. Sends NAK to complete previous RD + + while ((obj->i2c->STAT & ((7 << 1) | (1 << 0))) != ((0 << 1) | (1 << 0))) { //Spin until Ready (b0 == 1)and Status is Idle (b3..b1 == 000) timeout ++; if (timeout > 100000) return 1; } @@ -98,7 +103,6 @@ inline int i2c_stop(i2c_t *obj) { return 0; } - static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) { // write the data I2C_DAT(obj) = value; @@ -145,62 +149,82 @@ void i2c_frequency(i2c_t *obj, int hz) { // because something is setup wrong (e.g. wiring), and we don't need to programatically // check for that +//New version WH, Tested OK for Start and Repeated Start +//Old version was Wrong: Calls i2c_start without setting address, i2c_do_read continues before checking status, status check for wrong value int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int count, status; - i2c_start(obj); - - status = i2c_do_write(obj, (address | 0x01), 1); - if (status != 0x01) { + //Store the address+RD and then generate STA + I2C_DAT(obj) = address | 0x01; + i2c_start(obj); + + // Wait for completion of STA and Sending of SlaveAddress+RD and first Read byte + i2c_wait_SI(obj); + status = i2c_status(obj); + if (status == 0x03) { // NAK on SlaveAddress i2c_stop(obj); return I2C_ERROR_NO_SLAVE; } - + // Read in all except last byte - for (count = 0; count < (length - 1); count++) { - int value = i2c_do_read(obj, 0); - status = i2c_status(obj); - if (status != 0x00) { - i2c_stop(obj); - return count; - } - data[count] = (char) value; - } - - // read in last byte - int value = i2c_do_read(obj, 1); - status = i2c_status(obj); - if (status != 0x01) { + for (count = 0; count < (length-1); count++) { + + // Wait for it to arrive, note that first byte read after address+RD is already waiting + i2c_wait_SI(obj); + status = i2c_status(obj); + if (status != 0x01) { // RX RDY i2c_stop(obj); - return length - 1; + return count; + } + data[count] = I2C_DAT(obj) & 0xFF; // Store read byte + + obj->i2c->MSTCTL = (1 << 0); // Send ACK and Continue to read } - data[count] = (char) value; - + // Read final byte + // Wait for it to arrive + i2c_wait_SI(obj); + + status = i2c_status(obj); + if (status != 0x01) { // RX RDY + i2c_stop(obj); + return count; + } + data[count] = I2C_DAT(obj) & 0xFF; // Store final read byte + // If not repeated start, send stop. if (stop) { - i2c_stop(obj); + i2c_stop(obj); // Also sends NAK for last read byte } else { repeated_start = 1; } - + return length; } + + +//New version WH, Tested OK for Start and Repeated Start +//Old version was Wrong: Calls i2c_start without setting address first int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { int i, status; - + + //Store the address+/WR and then generate STA + I2C_DAT(obj) = address & 0xFE; i2c_start(obj); - status = i2c_do_write(obj, (address & 0xFE), 1); - if (status != 0x02) { + // Wait for completion of STA and Sending of SlaveAddress+/WR + i2c_wait_SI(obj); + status = i2c_status(obj); + if (status == 0x03) { // NAK SlaveAddress i2c_stop(obj); return I2C_ERROR_NO_SLAVE; } + //Write all bytes for (i=0; i Date: Mon, 26 Jan 2015 08:47:44 +0000 Subject: [PATCH 42/77] Removed extra checks for operator[] and replaced them with MBED_ASSERT for cleaner code --- libraries/mbed/api/BusIn.h | 2 -- libraries/mbed/api/BusInOut.h | 2 -- libraries/mbed/api/BusOut.h | 2 -- libraries/mbed/common/BusIn.cpp | 7 +---- libraries/mbed/common/BusInOut.cpp | 7 +---- libraries/mbed/common/BusOut.cpp | 7 +---- libraries/tests/mbed/bus_out/main.cpp | 39 ++++++++++++++++----------- 7 files changed, 26 insertions(+), 40 deletions(-) diff --git a/libraries/mbed/api/BusIn.h b/libraries/mbed/api/BusIn.h index 6f20875fa4..d1c9a9cd4e 100644 --- a/libraries/mbed/api/BusIn.h +++ b/libraries/mbed/api/BusIn.h @@ -68,8 +68,6 @@ public: return _nc_mask; } - static DigitalIn din_dummy; - #ifdef MBED_OPERATORS /** A shorthand for read() */ diff --git a/libraries/mbed/api/BusInOut.h b/libraries/mbed/api/BusInOut.h index e9a12c5f92..54328fb021 100644 --- a/libraries/mbed/api/BusInOut.h +++ b/libraries/mbed/api/BusInOut.h @@ -82,8 +82,6 @@ public: return _nc_mask; } - static DigitalInOut dinout_dummy; - #ifdef MBED_OPERATORS /** A shorthand for write() */ diff --git a/libraries/mbed/api/BusOut.h b/libraries/mbed/api/BusOut.h index 9e88e2d170..1c55be07e9 100644 --- a/libraries/mbed/api/BusOut.h +++ b/libraries/mbed/api/BusOut.h @@ -66,8 +66,6 @@ public: return _nc_mask; } - static DigitalOut dout_dummy; - #ifdef MBED_OPERATORS /** A shorthand for write() */ diff --git a/libraries/mbed/common/BusIn.cpp b/libraries/mbed/common/BusIn.cpp index 5ec8cbb8f2..56885ba9db 100644 --- a/libraries/mbed/common/BusIn.cpp +++ b/libraries/mbed/common/BusIn.cpp @@ -17,8 +17,6 @@ namespace mbed { -DigitalIn BusIn::din_dummy(NC); - BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) { PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15}; @@ -73,11 +71,8 @@ BusIn::operator int() { } DigitalIn& BusIn::operator[] (int index) { - MBED_ASSERT(index < 0 || index >= 16); + MBED_ASSERT(index >= 0 && index <= 16); MBED_ASSERT(_pin[index]); - if (index >= 16 || _pin[index] == NULL) { - return din_dummy; - } return *_pin[index]; } diff --git a/libraries/mbed/common/BusInOut.cpp b/libraries/mbed/common/BusInOut.cpp index bd8bc82726..3e56e61729 100644 --- a/libraries/mbed/common/BusInOut.cpp +++ b/libraries/mbed/common/BusInOut.cpp @@ -17,8 +17,6 @@ namespace mbed { -DigitalInOut BusInOut::dinout_dummy(NC); - BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) { PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15}; @@ -103,11 +101,8 @@ BusInOut& BusInOut::operator= (BusInOut& rhs) { } DigitalInOut& BusInOut::operator[] (int index) { - MBED_ASSERT(index < 0 || index >= 16); + MBED_ASSERT(index >= 0 && index <= 16); MBED_ASSERT(_pin[index]); - if (index >= 16 || _pin[index] == NULL) { - return dinout_dummy; - } return *_pin[index]; } diff --git a/libraries/mbed/common/BusOut.cpp b/libraries/mbed/common/BusOut.cpp index 86b2acb29a..7368c00e6a 100644 --- a/libraries/mbed/common/BusOut.cpp +++ b/libraries/mbed/common/BusOut.cpp @@ -17,8 +17,6 @@ namespace mbed { -DigitalOut BusOut::dout_dummy(NC); - BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) { PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15}; @@ -79,11 +77,8 @@ BusOut& BusOut::operator= (BusOut& rhs) { } DigitalOut& BusOut::operator[] (int index) { - MBED_ASSERT(index < 0 || index >= 16); + MBED_ASSERT(index >= 0 && index <= 16); MBED_ASSERT(_pin[index]); - if (index >= 16 || _pin[index] == NULL) { - return dout_dummy; - } return *_pin[index]; } diff --git a/libraries/tests/mbed/bus_out/main.cpp b/libraries/tests/mbed/bus_out/main.cpp index 4f14348604..35fccc4fa1 100644 --- a/libraries/tests/mbed/bus_out/main.cpp +++ b/libraries/tests/mbed/bus_out/main.cpp @@ -1,7 +1,10 @@ #include "mbed.h" #include "test_env.h" +namespace { BusOut bus_out(LED1, LED2, LED3, LED4); +PinName led_pins[4] = {LED1, LED2, LED3, LED4}; // Temp, used to map pins in bus_out +} int main() { @@ -26,21 +29,18 @@ int main() } // Checking if DigitalOut is correctly set as connected - for (int i=0; i<4; i++) { - printf("MBED: BusOut.bit[%d] is %s\r\n", i, bus_out[i].is_connected() ? "connected" : "not connected"); + for (int i=0; i < 4; i++) { + printf("MBED: BusOut.bit[%d] is %s\r\n", + i, + (led_pins[i] != NC && bus_out[i].is_connected()) + ? "connected" + : "not connected"); } - if (LED1 != NC && bus_out[0].is_connected() == 0) { - break; - } - if (LED1 != NC && bus_out[1].is_connected() == 0) { - break; - } - if (LED1 != NC && bus_out[2].is_connected() == 0) { - break; - } - if (LED1 != NC && bus_out[3].is_connected() == 0) { - break; + for (int i=0; i < 4; i++) { + if (led_pins[i] != NC && bus_out[0].is_connected() == 0) { + break; + } } // Write mask all LEDs @@ -58,18 +58,25 @@ int main() break; } - printf("MBED: Blinking LEDs...\r\n"); + printf("MBED: Blinking LEDs: \r\n"); // Just a quick LED blinking... for (int i=0; i<4; i++) { - if (bus_out[i].is_connected()) { + if (led_pins[i] != NC && bus_out[i].is_connected()) { bus_out[i] = 1; + printf("%c", 'A' + i); + } else { + printf("."); } wait(0.2); - if (bus_out[i].is_connected()) { + if (led_pins[i] != NC && bus_out[i].is_connected()) { bus_out[i] = 0; + printf("%c", 'a' + i); + } else { + printf("."); } } + printf("\r\n"); notify_completion(result); } From 1fca34a0681180f4a294203dfc640e174ff30fa6 Mon Sep 17 00:00:00 2001 From: 0xc0170 Date: Mon, 26 Jan 2015 15:32:14 +0100 Subject: [PATCH 43/77] HAL - NRF51822 - us ticker fix for the #839 There was a project header file which does not exist in mbed SDK, neither some defines used from it most probably. This commit reverts those parts. --- libraries/mbed/common/us_ticker_api.c | 2 +- libraries/mbed/hal/us_ticker_api.h | 1 - .../targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c | 4 +--- 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/libraries/mbed/common/us_ticker_api.c b/libraries/mbed/common/us_ticker_api.c index 19d5997ece..9d9c6562be 100644 --- a/libraries/mbed/common/us_ticker_api.c +++ b/libraries/mbed/common/us_ticker_api.c @@ -70,7 +70,7 @@ void us_ticker_insert_event(ticker_event_t *obj, timestamp_t timestamp, uint32_t ticker_event_t *prev = NULL, *p = head; while (p != NULL) { /* check if we come before p */ - if ((signedTimestamp_t)(timestamp - p->timestamp) < 0) { + if ((int)(timestamp - p->timestamp) < 0) { break; } /* go to the next element */ diff --git a/libraries/mbed/hal/us_ticker_api.h b/libraries/mbed/hal/us_ticker_api.h index ace3942919..b7df3b57a1 100644 --- a/libraries/mbed/hal/us_ticker_api.h +++ b/libraries/mbed/hal/us_ticker_api.h @@ -23,7 +23,6 @@ extern "C" { #endif typedef uint32_t timestamp_t; -typedef int32_t signedTimestamp_t; /* The signed version of the above declaration. */ uint32_t us_ticker_read(void); diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c index 4834db308d..ae973caba9 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c @@ -18,7 +18,6 @@ #include "cmsis.h" #include "PeripheralNames.h" #include "app_timer.h" -#include "projectconfig.h" static bool us_ticker_inited = false; static volatile bool us_ticker_appTimerRunning = false; @@ -30,8 +29,7 @@ void us_ticker_init(void) return; } - APP_TIMER_INIT(CFG_TIMER_PRESCALER, CFG_TIMER_MAX_INSTANCE, CFG_TIMER_OPERATION_QUEUE_SIZE, CFG_SCHEDULER_ENABLE); - +APP_TIMER_INIT(0 /*CFG_TIMER_PRESCALER*/ , 1 /*CFG_TIMER_MAX_INSTANCE*/, 1 /*CFG_TIMER_OPERATION_QUEUE_SIZE*/, false /*CFG_SCHEDULER_ENABLE*/); us_ticker_inited = true; } From 23afc625b7429b9409f9bda12630e3c11f502f2d Mon Sep 17 00:00:00 2001 From: 0xc0170 Date: Mon, 26 Jan 2015 16:22:55 +0100 Subject: [PATCH 44/77] Tools - expoters init file - tempdir name fix --- workspace_tools/export/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/workspace_tools/export/__init__.py b/workspace_tools/export/__init__.py index ee26e2425d..2f8b5bf107 100755 --- a/workspace_tools/export/__init__.py +++ b/workspace_tools/export/__init__.py @@ -85,7 +85,7 @@ def export(project_path, project_name, ide, target, destination='/tmp/', zip_path = None if report['success']: # add readme file to every offline export. - open(os.path.join(temdir, 'README.html'),'w').write(''% (target,ide)) + open(os.path.join(tempdir, 'README.html'),'w').write(''% (target,ide)) zip_path = zip_working_directory_and_clean_up(tempdir, destination, project_name, clean) return zip_path, report From 28435e93bf0bace391015e34bffba66afc724338 Mon Sep 17 00:00:00 2001 From: Olaf Hagendorf Date: Mon, 26 Jan 2015 17:43:08 +0100 Subject: [PATCH 45/77] [workspace_tools] project.py - some changes ... ... suggested by PrzemekWirkus --- workspace_tools/export/README.html | 908 +++++++++++++++++++++++++++++ workspace_tools/project.py | 18 +- 2 files changed, 919 insertions(+), 7 deletions(-) create mode 100644 workspace_tools/export/README.html diff --git a/workspace_tools/export/README.html b/workspace_tools/export/README.html new file mode 100644 index 0000000000..a8797f9b5a --- /dev/null +++ b/workspace_tools/export/README.html @@ -0,0 +1,908 @@ +Exporter IDE/Platform Support +----------------------------------- + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Platformcodesourcerycoideds5_5emblocksgcc_armiarkdslpcxpressouvision
ARCH_BLE---✓✓---✓
ARCH_GPRS---✓-----
ARCH_MAX---✓✓---✓
ARCH_PRO✓✓✓✓✓✓-✓✓
ARM_MPS2---✓-----
BLE_SMURFS---✓✓---✓
BLE_SMURFS_OTA---✓-----
DISCO_F051R8---✓✓----
DISCO_F100RB---✓✓----
DISCO_F303VC-✓-✓✓----
DISCO_F334C8-✓-✓✓----
DISCO_F407VG-✓-✓✓---✓
DISCO_F429ZI-✓-✓✓----
DISCO_L053C8---✓✓----
HRM1017---✓✓---✓
K20D50M---✓✓✓--✓
K22F---✓✓✓✓-✓
K64F---✓✓✓✓-✓
KL05Z-✓-✓✓✓--✓
KL25Z-✓-✓✓✓--✓
KL43Z---✓✓---✓
KL46Z---✓✓✓--✓
LPC1114---✓✓✓-✓✓
LPC11C24---✓----✓
LPC11U24--✓✓✓✓--✓
LPC11U24_301---✓-----
LPC11U35_401---✓✓✓-✓-
LPC11U35_501---✓✓✓-✓-
LPC11U35_Y5_MBUG---✓-----
LPC11U37_501---✓-----
LPC11U68---✓---✓-
LPC1347---✓-✓--✓
LPC1549---✓✓✓-✓✓
LPC1768✓✓✓✓✓✓-✓✓
LPC2368---✓✓----
LPC4088---✓✓✓-✓✓
LPC4330_M0---------
LPC4330_M4---✓✓--✓✓
LPC4337--------✓
LPC810---------
LPC812--✓--✓--✓
LPC824---✓-----
LPCCAPPUCCINO---✓✓✓-✓-
MTS_GAMBIT---✓✓---✓
MTS_MDOT_F405RG-✓-✓✓✓--✓
MTS_MDOT_F411RE-✓-✓✓✓---
NRF51822---✓✓---✓
NRF51822_OTA---✓-----
NRF51822_Y5_MBUG---✓-----
NRF51_DK---✓✓---✓
NRF51_DK_OTA---✓-----
NRF51_DONGLE---✓✓---✓
NUCLEO_F030R8-✓-✓✓✓--✓
NUCLEO_F070RB---✓✓✓--✓
NUCLEO_F072RB-✓-✓✓✓--✓
NUCLEO_F091RC-----✓--✓
NUCLEO_F103RB---✓-✓--✓
NUCLEO_F302R8-✓-✓✓✓--✓
NUCLEO_F303RE-----✓--✓
NUCLEO_F334R8-✓-✓✓✓--✓
NUCLEO_F401RE-✓-✓✓✓--✓
NUCLEO_F411RE-✓-✓✓✓--✓
NUCLEO_L053R8---✓✓✓--✓
NUCLEO_L152RE-✓-✓✓✓--✓
OC_MBUINO---✓-----
RBLAB_BLENANO---✓-----
RBLAB_NRF51822---✓-----
RZ_A1H---------
SSCI824---------
STM32F3XX---✓-----
STM32F407---✓✓✓---
UBLOX_C027✓✓✓✓✓✓-✓✓
WALLBOT_BLE---✓-----
XADOW_M0---✓-----
+Total IDEs: 9 +
Total platforms: 74 +
Total permutations: 225 \ No newline at end of file diff --git a/workspace_tools/project.py b/workspace_tools/project.py index 6f7fd1c473..b8f9e8452d 100644 --- a/workspace_tools/project.py +++ b/workspace_tools/project.py @@ -92,14 +92,18 @@ if __name__ == '__main__': # Only prints matrix of supported IDEs if options.supported_ides_html: html = mcu_ide_matrix(verbose_html=True) - f = open("./export/README.md","w") try: - f.write("Exporter IDE/Platform Support\n") - f.write("-----------------------------------\n") - f.write("\n"); - f.write(html) - finally: - f.close() + with open("./export/README.html","w") as f: # you have to rename README.htlm to README.md manually + f.write("Exporter IDE/Platform Support\n") + f.write("-----------------------------------\n") + f.write("\n"); + f.write(html) + f.close() + except IOError as e: + print "I/O error({0}): {1}".format(e.errno, e.strerror) + except: + print "Unexpected error:", sys.exc_info()[0] + raise exit(0) # Clean Export Directory From ea2a3c27a0dd6baae0e79569c673d0cbff32e8d3 Mon Sep 17 00:00:00 2001 From: milangit Date: Mon, 26 Jan 2015 21:46:06 +0100 Subject: [PATCH 46/77] Assigned a value to pin variable --- .../hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_irq_api.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_irq_api.c index 3857a496fb..a218fdf3c8 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_irq_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_irq_api.c @@ -258,7 +258,8 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 obj->irq_n = irq_n; obj->irq_index = irq_index; obj->event = EDGE_NONE; - + obj->pin = pin; + gpio_channel = &channels[irq_index]; gpio_idx = pin_base_nr[pin_index]; gpio_channel->pin_mask |= (1 << gpio_idx); @@ -286,6 +287,9 @@ void gpio_irq_free(gpio_irq_t *obj) EXTI_InitTypeDef EXTI_InitStructure; EXTI_StructInit(&EXTI_InitStructure); EXTI_Init(&EXTI_InitStructure); + + pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_Out_PP, 0)); + pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)); obj->event = EDGE_NONE; } From 7b4f177cdbd0b2a541277c453f28cadec8b27d0a Mon Sep 17 00:00:00 2001 From: Marcomissyou Date: Tue, 27 Jan 2015 14:56:59 +0800 Subject: [PATCH 47/77] remove older target --- .../TARGET_DFCM_NNN40/PinNames.h | 123 ------------ .../TARGET_DFCM_NNN40/device.h | 57 ------ .../TARGET_DFCM_NNN40_DT0R.7z | Bin 1375 -> 0 bytes .../TARGET_DFCM_NNN40_DT0R/PinNames.h | 178 ------------------ .../TARGET_DFCM_NNN40_DT0R/device.h | 57 ------ libraries/tests/mbed/i2c_eeprom/main.cpp | 3 + libraries/tests/mbed/i2c_eeprom_line/main.cpp | 3 + 7 files changed, 6 insertions(+), 415 deletions(-) delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40/PinNames.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40/device.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R.7z delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R/PinNames.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R/device.h diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40/PinNames.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40/PinNames.h deleted file mode 100644 index 6b435862c7..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40/PinNames.h +++ /dev/null @@ -1,123 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 3 - -typedef enum { - NC = (int)0xFFFFFFFF, - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = NC, - p9 = NC, - p10 = NC, - p11 = NC, - p12 = 12, - p13 = NC, - p14 = NC, - p15 = NC, - p16 = 16, - p17 = 17, - p18 = NC, - p19 = NC, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = NC, - p29 = 29, - p30 = 30, - p31 = 31, - - LED1 = p1, - LED2 = p2, - - BUTTON0 = p16, - BUTTON1 = p17, - - RX_PIN_NUMBER = p16, - TX_PIN_NUMBER = p17, - - // mBed interface Pins - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - - SPI_PSELMOSI0 = p24, - SPI_PSELMISO0 = p29, - SPI_PSELSS0 = p6, - SPI_PSELSCK0 = p21, - - SPIS_PSELMOSI = p24, - SPIS_PSELMISO = p29, - SPIS_PSELSS = p6, - SPIS_PSELSCK = p21, - - I2C_SDA0 = p22, - I2C_SCL0 = p20, - - A0 = p0, - A1 = p1, - A2 = p2, - A3 = p3, - A4 = p4, - A5 = p5, - - // Not connected - - CTS_PIN_NUMBER = NC, - RTS_PIN_NUMBER = NC, - SPI_PSELMOSI1 = NC, - SPI_PSELMISO1 = NC, - SPI_PSELSS1 = NC, - SPI_PSELSCK1 = NC, - LED3 = NC, - LED4 = NC -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40/device.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40/device.h deleted file mode 100644 index fd66610a0c..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40/device.h +++ /dev/null @@ -1,57 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 0 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 0 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 0 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 0 -#define DEVICE_LOCALFILESYSTEM 0 - -#define DEVICE_SLEEP 1 - -#define DEVICE_DEBUG_AWARENESS 1 - -#define DEVICE_STDIO_MESSAGES 0 - -#define DEVICE_ERROR_PATTERN 1 - -#include "objects.h" - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R.7z b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R.7z deleted file mode 100644 index 7c0e9dbda0105386e5e7424be9ebe6e578409aae..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1375 zcmV-l1)%yjdc3bE8~_8shK$u51poj50000Z000000002x4gm517m9!;{c%r?0p0C| z1T&enHWy5&)&=qRl79BU@P2u=T{E=Q0m7f=aNP?37IcS+4Ltq^N$F(tqdiob*+zvA zQrW``hLFDdoVk!V=5$BbQ>j^|r8fp9D)!qd%pspCd=|~2pHVEdKG0Z)PPc%HzH~U{ zOUTaxm7f-#dfM6YyQqD2WN$s?fUh^1DC1wQMzYv%|88w;&lH(181}t{sm4DDHaEnH zLOk7STQ)X$=u2DGAqsNveU}c&6*R=u_9YO@(6X~Z?-*}K@s0y*UVFbe?e1_dO^T+w zj>SC>M^a)0!j5`7zU(iQudSsm3+N{&SEmG`GsMFf?us$dWk2AWr1-*mquYj;&29qN zVP)Fl#}E&kj2LdLk7=rBOrrck#k%K3$h$@F6jS`6?x9Y{9LULz|k3D{Ru z2cxa3Buv0o4D!!1CZ#H%JvNA}z5!->L9xp^NThrKcZi5dj%nV!D;)eB8LmT$Vi{=B z5iDrO)cXAX?E`%p(lPhs9P!4vc$1kCj!OeVr@#?b@R4>0udD z)L56zV|FF1VvK{0z>wA={hCR<%)COn36-*QR)U`ZWqxx!Gh~2|DYOrf_B4zKmkEUA z#Okw`K2KN6Zhc^&l(n2Cir45&PPk*A4(g=o{EAu}f!Qp_%oSz;IF<2Si#uJ;zjXp2 z3|~Uos9@G?SRwz;OG+>cnGc9f^>-(!wziiM4Uc&;+FgB-G^ldQaxM6U)M>X_7J{7D zNis%B<(sJmS?~zhB!iH;5<}uJAYm<;Cht&;lhN!#=!%?sd@J&#dl^vQ)oZD~-U~qB zz+d`r<6pcJ8^b|Rl05TtvofkAap_^tTyOe_TqLpil{Y4ClCYN0Vj3GuQZ^!SC1@rN;#ShK z$@V0M|FyszLukwJi#oOkU`2}$LEbAbr#f3hPTLgZziRkbFwKrzhlkcfTHwcDYP=Z0 zL*^8JQW0KDd-goOS2=UhMmCgUYRTk8UE!YoW`$OB)k-T1YJ3V<3Y*nhrSrS!7!CQrw5Hn>Aiyl*Jd?hOf7U zqXFVbvb#hQXZPK*cR!EQp45NF2sb@NxZzJm&?FfUC1(BnSSsUt-R9K*0D&_Ht`F5) zlE4=v)Bdx5FNu=AzC8-Dke@wABQE&hG7_N*%#;IOHhw>MwGZ@N(b+_NPKyirL8uuZ z=}ZSB2xP~K6&O&WlptP2KV%ZjFOQf$E5C8xSffot^!gA88008DEl%xOv diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R/PinNames.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R/PinNames.h deleted file mode 100644 index be8ff8b4cf..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R/PinNames.h +++ /dev/null @@ -1,178 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 3 - -typedef enum { - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = 8, - p9 = 9, - p10 = 10, - p11 = 11, - p12 = 12, - p13 = 13, - p14 = 14, - p15 = 15, - p16 = 16, - p17 = 17, - p18 = 18, - p19 = 19, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = 28, - p29 = 29, - p30 = 30, - - P0_0 = p0, - P0_1 = p1, - P0_2 = p2, - P0_3 = p3, - P0_4 = p4, - P0_5 = p5, - P0_6 = p6, - P0_7 = p7, - - P0_8 = p8, - P0_9 = p9, - P0_10 = p10, - P0_11 = p11, - P0_12 = p12, - P0_13 = p13, - P0_14 = p14, - P0_15 = p15, - - P0_16 = p16, - P0_17 = p17, - P0_18 = p18, - P0_19 = p19, - P0_20 = p20, - P0_21 = p21, - P0_22 = p22, - P0_23 = p23, - - P0_24 = p24, - P0_25 = p25, - P0_26 = p26, - P0_27 = p27, - P0_28 = p28, - P0_29 = p29, - P0_30 = p30, - - LED1 = p21, - LED2 = p22, - LED3 = p23, - LED4 = p24, - - BUTTON1 = p17, - BUTTON2 = p18, - BUTTON3 = p19, - BUTTON4 = p20, - - RX_PIN_NUMBER = p11, - TX_PIN_NUMBER = p9, - CTS_PIN_NUMBER = p10, - RTS_PIN_NUMBER = p8, - - // mBed interface Pins - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - - SPI_PSELMOSI0 = p25, - SPI_PSELMISO0 = p28, - SPI_PSELSS0 = p24, - SPI_PSELSCK0 = p29, - - SPI_PSELMOSI1 = p13, - SPI_PSELMISO1 = p14, - SPI_PSELSS1 = p12, - SPI_PSELSCK1 = p15, - - SPIS_PSELMOSI = p13, - SPIS_PSELMISO = p14, - SPIS_PSELSS = p12, - SPIS_PSELSCK = p15, - - I2C_SDA0 = p30, - I2C_SCL0 = p7, - - D0 = p12, - D1 = p13, - D2 = p14, - D3 = p15, - D4 = p16, - D5 = p17, - D6 = p18, - D7 = p19, - - D8 = p20, - D9 = p23, - D10 = p24, - D11 = p25, - D12 = p28, - D13 = p29, - - D14 = p30, - D15 = p7, - - A0 = p1, - A1 = p2, - A2 = p3, - A3 = p4, - A4 = p5, - A5 = p6, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R/device.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R/device.h deleted file mode 100644 index 9d5a5e2109..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DFCM_NNN40_DT0R/device.h +++ /dev/null @@ -1,57 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 0 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 0 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 0 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 0 -#define DEVICE_LOCALFILESYSTEM 0 - -#define DEVICE_SLEEP 1 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 0 - -#define DEVICE_ERROR_PATTERN 1 - -#include "objects.h" - -#endif diff --git a/libraries/tests/mbed/i2c_eeprom/main.cpp b/libraries/tests/mbed/i2c_eeprom/main.cpp index 97a962d217..bc3091aa5e 100644 --- a/libraries/tests/mbed/i2c_eeprom/main.cpp +++ b/libraries/tests/mbed/i2c_eeprom/main.cpp @@ -45,6 +45,9 @@ I2C i2c(P0_23, P0_22); #elif defined(TARGET_LPC11U68) I2C i2c(SDA, SCL); +#elif defined(TARGET_DELTA_DFCM_NNN40) +I2C i2c(I2C_SDA0, I2C_SCL0); + #elif defined(TARGET_NUCLEO_F030R8) || \ defined(TARGET_NUCLEO_F070RB) || \ defined(TARGET_NUCLEO_F072RB) || \ diff --git a/libraries/tests/mbed/i2c_eeprom_line/main.cpp b/libraries/tests/mbed/i2c_eeprom_line/main.cpp index 1b701d469d..754242326a 100644 --- a/libraries/tests/mbed/i2c_eeprom_line/main.cpp +++ b/libraries/tests/mbed/i2c_eeprom_line/main.cpp @@ -55,6 +55,9 @@ I2C i2c(P0_23, P0_22); #elif defined(TARGET_LPC11U68) I2C i2c(SDA, SCL); +#elif defined(TARGET_DELTA_DFCM_NNN40) +I2C i2c(I2C_SDA0, I2C_SCL0); + #elif defined(TARGET_NUCLEO_F030R8) || \ defined(TARGET_NUCLEO_F070RB) || \ defined(TARGET_NUCLEO_F072RB) || \ From f578ea38f743b493791f52325314df9ad7e44a1d Mon Sep 17 00:00:00 2001 From: Marcomissyou Date: Tue, 27 Jan 2015 15:07:57 +0800 Subject: [PATCH 48/77] delet rtc_api.c --- .../TARGET_MCU_NRF51822/rtc_api.c | 175 ------------------ 1 file changed, 175 deletions(-) delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/rtc_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/rtc_api.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/rtc_api.c deleted file mode 100644 index 16b88ccb45..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/rtc_api.c +++ /dev/null @@ -1,175 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "rtc_api.h" - -#if DEVICE_RTC - -#include "wait_api.h" - -#define LSE_STARTUP_TIMEOUT ((uint16_t)500) // delay in ms - -static int rtc_inited = 0; - -void rtc_init(void) { - uint32_t StartUpCounter = 0; - uint32_t LSEStatus = 0; - uint32_t rtc_freq = 0; - - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); // Enable PWR clock - - PWR_BackupAccessCmd(ENABLE); // Enable access to Backup domain - - // Reset back up registers - RCC_BackupResetCmd(ENABLE); - RCC_BackupResetCmd(DISABLE); - - // Enable LSE clock - RCC_LSEConfig(RCC_LSE_ON); - - // Wait till LSE is ready - do { - LSEStatus = RCC_GetFlagStatus(RCC_FLAG_LSERDY); - wait_ms(1); - StartUpCounter++; - } while ((LSEStatus == 0) && (StartUpCounter <= LSE_STARTUP_TIMEOUT)); - - if (StartUpCounter > LSE_STARTUP_TIMEOUT) { - // The LSE has not started, use LSI instead. - // The RTC Clock may vary due to LSI frequency dispersion. - RCC_LSEConfig(RCC_LSE_OFF); - RCC_LSICmd(ENABLE); // Enable LSI - while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) {} // Wait until ready - RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); // Select the RTC Clock Source - rtc_freq = 40000; // [TODO] To be measured precisely using a timer input capture - } else { - // The LSE has correctly started - RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); // Select the RTC Clock Source - rtc_freq = LSE_VALUE; - } - - RCC_RTCCLKCmd(ENABLE); // Enable RTC Clock - - RTC_WaitForSynchro(); // Wait for RTC registers synchronization - - RTC_InitTypeDef RTC_InitStructure; - RTC_InitStructure.RTC_AsynchPrediv = 127; - RTC_InitStructure.RTC_SynchPrediv = (rtc_freq / 128) - 1; - RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24; - RTC_Init(&RTC_InitStructure); - - PWR_BackupAccessCmd(DISABLE); // Disable access to Backup domain - - rtc_inited = 1; -} - -void rtc_free(void) { - // Reset RTC - PWR_BackupAccessCmd(ENABLE); // Enable access to Backup Domain - RTC_DeInit(); - RCC_BackupResetCmd(ENABLE); - RCC_BackupResetCmd(DISABLE); - // Disable RTC, LSE and LSI clocks - RCC_RTCCLKCmd(DISABLE); - RCC_LSEConfig(RCC_LSE_OFF); - RCC_LSICmd(DISABLE); - - rtc_inited = 0; -} - -int rtc_isenabled(void) { - return rtc_inited; -} - -/* - RTC Registers - RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday - RTC_Month 1=january, 2=february, ..., 12=december - RTC_Date day of the month 1-31 - RTC_Year year 0-99 - struct tm - tm_sec seconds after the minute 0-61 - tm_min minutes after the hour 0-59 - tm_hour hours since midnight 0-23 - tm_mday day of the month 1-31 - tm_mon months since January 0-11 - tm_year years since 1900 - tm_wday days since Sunday 0-6 - tm_yday days since January 1 0-365 - tm_isdst Daylight Saving Time flag -*/ -time_t rtc_read(void) { - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - struct tm timeinfo; - - // Read actual date and time - RTC_GetTime(RTC_Format_BIN, &timeStruct); - RTC_GetDate(RTC_Format_BIN, &dateStruct); - - // Setup a tm structure based on the RTC - timeinfo.tm_wday = dateStruct.RTC_WeekDay; - timeinfo.tm_mon = dateStruct.RTC_Month - 1; - timeinfo.tm_mday = dateStruct.RTC_Date; - timeinfo.tm_year = dateStruct.RTC_Year + 100; - timeinfo.tm_hour = timeStruct.RTC_Hours; - timeinfo.tm_min = timeStruct.RTC_Minutes; - timeinfo.tm_sec = timeStruct.RTC_Seconds; - - // Convert to timestamp - time_t t = mktime(&timeinfo); - - return t; -} - -void rtc_write(time_t t) { - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - - // Convert the time into a tm - struct tm *timeinfo = localtime(&t); - - // Fill RTC structures - dateStruct.RTC_WeekDay = timeinfo->tm_wday; - dateStruct.RTC_Month = timeinfo->tm_mon + 1; - dateStruct.RTC_Date = timeinfo->tm_mday; - dateStruct.RTC_Year = timeinfo->tm_year - 100; - timeStruct.RTC_Hours = timeinfo->tm_hour; - timeStruct.RTC_Minutes = timeinfo->tm_min; - timeStruct.RTC_Seconds = timeinfo->tm_sec; - timeStruct.RTC_H12 = RTC_HourFormat_24; - - // Change the RTC current date/time - PWR_BackupAccessCmd(ENABLE); // Enable access to RTC - RTC_SetDate(RTC_Format_BIN, &dateStruct); - RTC_SetTime(RTC_Format_BIN, &timeStruct); - PWR_BackupAccessCmd(DISABLE); // Disable access to RTC -} - -#endif From 48aed8e75f08f805882cc1dcbe0c8da4ab5462e3 Mon Sep 17 00:00:00 2001 From: Marcomissyou Date: Tue, 27 Jan 2015 15:34:33 +0800 Subject: [PATCH 49/77] remove DFCM_NNN40 PinMap_ADC --- .../TARGET_MCU_NRF51822/analogin_api.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/analogin_api.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/analogin_api.c index a3058d012f..ab6da87545 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/analogin_api.c @@ -22,20 +22,6 @@ #define ADC_10BIT_RANGE 0x3FF #define ADC_RANGE ADC_10BIT_RANGE -#ifdef TARGET_DFCM_NNN40 - -static const PinMap PinMap_ADC[] = { - {p0, ADC0_0, 4}, - {p1, ADC0_0, 8}, - {p2, ADC0_0, 16}, - {p3, ADC0_0, 32}, - {p4, ADC0_0, 64}, - {p5, ADC0_0, 128}, - {NC, NC, 0} -}; - -#else - static const PinMap PinMap_ADC[] = { {p1, ADC0_0, 4}, {p2, ADC0_0, 8}, @@ -45,7 +31,6 @@ static const PinMap PinMap_ADC[] = { {p6, ADC0_0, 128}, {NC, NC, 0} }; -#endif void analogin_init(analogin_t *obj, PinName pin) { From e7c32aff0fc88d1701c233df9c73be16e9bcb0eb Mon Sep 17 00:00:00 2001 From: Marcomissyou Date: Tue, 27 Jan 2015 15:41:52 +0800 Subject: [PATCH 50/77] modify main.cpp of analog and analog_in --- libraries/tests/mbed/analog/main.cpp | 2 +- libraries/tests/mbed/analog_in/main.cpp | 4 +- libraries/tests/mbed/blinky/main.cpp | 54 ++----------------------- workspace_tools/targets.py | 2 +- 4 files changed, 7 insertions(+), 55 deletions(-) diff --git a/libraries/tests/mbed/analog/main.cpp b/libraries/tests/mbed/analog/main.cpp index 8dcc1772ab..a4e368af3c 100644 --- a/libraries/tests/mbed/analog/main.cpp +++ b/libraries/tests/mbed/analog/main.cpp @@ -62,4 +62,4 @@ int main() { } notify_completion(check); -} +} \ No newline at end of file diff --git a/libraries/tests/mbed/analog_in/main.cpp b/libraries/tests/mbed/analog_in/main.cpp index 2886219396..157885df36 100644 --- a/libraries/tests/mbed/analog_in/main.cpp +++ b/libraries/tests/mbed/analog_in/main.cpp @@ -50,9 +50,9 @@ int main() { } if (successes > 8) { - notify_completion(true); + notify_success(true); } else { - notify_completion(false); + notify_success(false); } } \ No newline at end of file diff --git a/libraries/tests/mbed/blinky/main.cpp b/libraries/tests/mbed/blinky/main.cpp index 9c87526a67..3e6293939f 100644 --- a/libraries/tests/mbed/blinky/main.cpp +++ b/libraries/tests/mbed/blinky/main.cpp @@ -1,60 +1,12 @@ #include "mbed.h" -#include "nrf_soc.h" - -#define CMD_POWER_DOWN (0xB9) - -DigitalOut LED00(p0); -DigitalOut LED01(p1); -DigitalOut LED02(p2); -DigitalOut LED03(p3); -DigitalOut LED04(p4); -DigitalOut LED05(p5); -DigitalOut Flash_CS(p28); -InterruptIn button(p20); - -void intoSystemoff() { - Flash_CS = 0; - LED00 = 0; - LED01 = 0; - LED02 = 0; - LED03 = 0; - //ble.init(); - wait(1); - NRF_POWER->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter; - //sd_power_system_off(); - //NRF_POWER->RAMON = POWER_RAMON_OFFRAM3_RAM3Off << POWER_RAMON_OFFRAM3_Pos; - //NRF_POWER->RAMON = POWER_RAMON_OFFRAM2_RAM2Off << POWER_RAMON_OFFRAM2_Pos; - //wait(5); - //NRF_POWER->RAMON = POWER_RAMON_OFFRAM1_RAM1On << POWER_RAMON_ONRAM1_Pos; - //NRF_POWER->RAMON = POWER_RAMON_OFFRAM0_RAM0On << POWER_RAMON_ONRAM0_Pos; - - } - -int main() { - LED00 = 1; - button.fall(&intoSystemoff); - for(;;) - { - LED03 = 1; - wait(1); - LED03 = 0; - wait(1); - } - - -} - - - -/*#include "mbed.h" DigitalOut myled(LED1); int main() { while(1) { myled = 1; - wait(2); + wait(0.2); myled = 0; - wait(2); + wait(0.2); } -}*/ +} diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index bdff0f6fef..3a1345bf40 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -971,7 +971,7 @@ TARGETS = [ BLE_SMURFS_OTA(), HRM1017(), # nRF51822 RBLAB_NRF51822(),# nRF51822 - RBLAB_BLENANO(),# nRF51822git + RBLAB_BLENANO(),# nRF51822 NRF51822_Y5_MBUG(),#nRF51822 WALLBOT_BLE(), # nRF51822 DELTA_DFCM_NNN40(), # nRF51822 From a9bde7df030b99d07bd4a0dc0aee43702ccd29cd Mon Sep 17 00:00:00 2001 From: Olaf Hagendorf Date: Tue, 27 Jan 2015 10:50:51 +0100 Subject: [PATCH 51/77] [workspace_tools] project.py - some more changes ... ... suggested by PrzemekWirkus --- workspace_tools/project.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/workspace_tools/project.py b/workspace_tools/project.py index b8f9e8452d..7bf165b0bd 100644 --- a/workspace_tools/project.py +++ b/workspace_tools/project.py @@ -93,12 +93,11 @@ if __name__ == '__main__': if options.supported_ides_html: html = mcu_ide_matrix(verbose_html=True) try: - with open("./export/README.html","w") as f: # you have to rename README.htlm to README.md manually + with open("./export/README.md","w") as f: f.write("Exporter IDE/Platform Support\n") f.write("-----------------------------------\n") - f.write("\n"); + f.write("\n") f.write(html) - f.close() except IOError as e: print "I/O error({0}): {1}".format(e.errno, e.strerror) except: From d6721ad2cae1efe380fa942edcadd111a2e1ef05 Mon Sep 17 00:00:00 2001 From: Olaf Hagendorf Date: Tue, 27 Jan 2015 16:34:28 +0100 Subject: [PATCH 52/77] [export/README.md] some minor issues - current development status - deleting readme.html - a remainder of the disscussion of PR #819 --- workspace_tools/export/README.html | 908 ----------------------------- workspace_tools/export/README.md | 76 ++- 2 files changed, 62 insertions(+), 922 deletions(-) delete mode 100644 workspace_tools/export/README.html diff --git a/workspace_tools/export/README.html b/workspace_tools/export/README.html deleted file mode 100644 index a8797f9b5a..0000000000 --- a/workspace_tools/export/README.html +++ /dev/null @@ -1,908 +0,0 @@ -Exporter IDE/Platform Support ------------------------------------ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Platformcodesourcerycoideds5_5emblocksgcc_armiarkdslpcxpressouvision
ARCH_BLE---✓✓---✓
ARCH_GPRS---✓-----
ARCH_MAX---✓✓---✓
ARCH_PRO✓✓✓✓✓✓-✓✓
ARM_MPS2---✓-----
BLE_SMURFS---✓✓---✓
BLE_SMURFS_OTA---✓-----
DISCO_F051R8---✓✓----
DISCO_F100RB---✓✓----
DISCO_F303VC-✓-✓✓----
DISCO_F334C8-✓-✓✓----
DISCO_F407VG-✓-✓✓---✓
DISCO_F429ZI-✓-✓✓----
DISCO_L053C8---✓✓----
HRM1017---✓✓---✓
K20D50M---✓✓✓--✓
K22F---✓✓✓✓-✓
K64F---✓✓✓✓-✓
KL05Z-✓-✓✓✓--✓
KL25Z-✓-✓✓✓--✓
KL43Z---✓✓---✓
KL46Z---✓✓✓--✓
LPC1114---✓✓✓-✓✓
LPC11C24---✓----✓
LPC11U24--✓✓✓✓--✓
LPC11U24_301---✓-----
LPC11U35_401---✓✓✓-✓-
LPC11U35_501---✓✓✓-✓-
LPC11U35_Y5_MBUG---✓-----
LPC11U37_501---✓-----
LPC11U68---✓---✓-
LPC1347---✓-✓--✓
LPC1549---✓✓✓-✓✓
LPC1768✓✓✓✓✓✓-✓✓
LPC2368---✓✓----
LPC4088---✓✓✓-✓✓
LPC4330_M0---------
LPC4330_M4---✓✓--✓✓
LPC4337--------✓
LPC810---------
LPC812--✓--✓--✓
LPC824---✓-----
LPCCAPPUCCINO---✓✓✓-✓-
MTS_GAMBIT---✓✓---✓
MTS_MDOT_F405RG-✓-✓✓✓--✓
MTS_MDOT_F411RE-✓-✓✓✓---
NRF51822---✓✓---✓
NRF51822_OTA---✓-----
NRF51822_Y5_MBUG---✓-----
NRF51_DK---✓✓---✓
NRF51_DK_OTA---✓-----
NRF51_DONGLE---✓✓---✓
NUCLEO_F030R8-✓-✓✓✓--✓
NUCLEO_F070RB---✓✓✓--✓
NUCLEO_F072RB-✓-✓✓✓--✓
NUCLEO_F091RC-----✓--✓
NUCLEO_F103RB---✓-✓--✓
NUCLEO_F302R8-✓-✓✓✓--✓
NUCLEO_F303RE-----✓--✓
NUCLEO_F334R8-✓-✓✓✓--✓
NUCLEO_F401RE-✓-✓✓✓--✓
NUCLEO_F411RE-✓-✓✓✓--✓
NUCLEO_L053R8---✓✓✓--✓
NUCLEO_L152RE-✓-✓✓✓--✓
OC_MBUINO---✓-----
RBLAB_BLENANO---✓-----
RBLAB_NRF51822---✓-----
RZ_A1H---------
SSCI824---------
STM32F3XX---✓-----
STM32F407---✓✓✓---
UBLOX_C027✓✓✓✓✓✓-✓✓
WALLBOT_BLE---✓-----
XADOW_M0---✓-----
-Total IDEs: 9 -
Total platforms: 74 -
Total permutations: 225 \ No newline at end of file diff --git a/workspace_tools/export/README.md b/workspace_tools/export/README.md index ca87279f63..ba01295a91 100644 --- a/workspace_tools/export/README.md +++ b/workspace_tools/export/README.md @@ -101,7 +101,7 @@ Exporter IDE/Platform Support DISCO_F051R8 - - - + ✓ - ✓ ✓ @@ -113,7 +113,7 @@ Exporter IDE/Platform Support DISCO_F100RB - - - + ✓ - ✓ ✓ @@ -146,6 +146,18 @@ Exporter IDE/Platform Support - - + + DISCO_F401VC + - + ✓ + - + ✓ + ✓ + - + - + - + - + DISCO_F407VG - @@ -173,14 +185,14 @@ Exporter IDE/Platform Support DISCO_L053C8 - - - + ✓ - ✓ ✓ - - - - - + ✓ HRM1017 @@ -362,6 +374,18 @@ Exporter IDE/Platform Support - - + + LPC11U37H_401 + - + - + - + ✓ + ✓ + - + - + ✓ + ✓ + LPC11U37_501 - @@ -515,7 +539,7 @@ Exporter IDE/Platform Support - - - - - + ✓ - @@ -530,6 +554,18 @@ Exporter IDE/Platform Support ✓ - + + MTS_DRAGONFLY_F411RE + - + - + - + ✓ + - + ✓ + - + - + - + MTS_GAMBIT - @@ -677,10 +713,10 @@ Exporter IDE/Platform Support NUCLEO_F091RC - + ✓ - - - - - - - + ✓ + ✓ ✓ - - @@ -689,11 +725,11 @@ Exporter IDE/Platform Support NUCLEO_F103RB - - - - - ✓ - ✓ + ✓ + ✓ - - ✓ @@ -715,7 +751,7 @@ Exporter IDE/Platform Support - - - - - + ✓ - ✓ - @@ -761,7 +797,7 @@ Exporter IDE/Platform Support NUCLEO_L053R8 - - - + ✓ - ✓ ✓ @@ -866,6 +902,18 @@ Exporter IDE/Platform Support - - + + TEENSY3_1 + - + - + - + ✓ + - + - + - + - + ✓ + UBLOX_C027 ✓ @@ -904,5 +952,5 @@ Exporter IDE/Platform Support Total IDEs: 9 -
Total platforms: 74 -
Total permutations: 225 +
Total platforms: 78 +
Total permutations: 248 \ No newline at end of file From 74cd9484708acc2fccb2e827c9da96ec4f7e4df8 Mon Sep 17 00:00:00 2001 From: Wim Date: Tue, 27 Jan 2015 20:48:51 +0100 Subject: [PATCH 53/77] Update system_LPC8xx.h Added extern MainClock to allow the use of the PLL and correct the wrong clock source for serial_api.c --- .../mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h index f559e944c6..c392f2a4a7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h @@ -30,6 +30,8 @@ extern "C" { #include +//WH +extern uint32_t MainClock; /*!< Main Clock Frequency */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ From 6fefefa3bb79f567ecf919f0c9923c4b1ed28a8f Mon Sep 17 00:00:00 2001 From: Wim Date: Tue, 27 Jan 2015 21:00:01 +0100 Subject: [PATCH 54/77] Update system_LPC8xx.c LPC812 was running at 12MHz on IRC. Added and fixed PLL activation to change the clockspeed into the expected 30MHz. Clock source is still the IRC. Selecting the 12 MHz XTAL clocksource should also work with the PLL. Added MainClock to fix wrong setting of SystemCoreClock and allow the serial_api to use the correct clock. --- .../TARGET_LPC812/system_LPC8xx.c | 51 +++++++++++-------- 1 file changed, 29 insertions(+), 22 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c index 2d1a94535a..61fe203524 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c @@ -102,21 +102,26 @@ */ #define CLOCK_SETUP 1 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal: +//WH Fixed to use PLL #if (CLOCK_SETUP == 1) +//use PLL for IRC #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000 - #define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 - #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000 - #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 + #define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz + #define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 Select IRC + #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT + #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz + #elif (CLOCK_SETUP == 2) +//use PLL for XTAL #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000 - #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 - #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 - #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 + #define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz + #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 Select XTAL + #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT + #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz #endif +//WH /* //-------- <<< end of configuration section >>> ------------------------------ @@ -245,9 +250,11 @@ /*---------------------------------------------------------------------------- Clock Variable definitions *----------------------------------------------------------------------------*/ +//WH Added MainClock +uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ - +//WH Replaced SystemCoreClock with MainClock /*---------------------------------------------------------------------------- Clock functions *----------------------------------------------------------------------------*/ @@ -278,48 +285,48 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ switch (LPC_SYSCON->MAINCLKSEL & 0x03) { case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; + MainClock = __IRC_OSC_CLK; break; case 1: /* Input Clock to System PLL */ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; + MainClock = __IRC_OSC_CLK; break; case 1: /* System oscillator */ - SystemCoreClock = __SYS_OSC_CLK; + MainClock = __SYS_OSC_CLK; break; case 2: /* Reserved */ - SystemCoreClock = 0; + MainClock = 0; break; case 3: /* CLKIN pin */ - SystemCoreClock = __CLKIN_CLK; + MainClock = __CLKIN_CLK; break; } break; case 2: /* WDT Oscillator */ - SystemCoreClock = wdt_osc; + MainClock = wdt_osc; break; case 3: /* System PLL Clock Out */ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + MainClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); break; case 1: /* System oscillator */ - SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + MainClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); break; case 2: /* Reserved */ - SystemCoreClock = 0; + MainClock = 0; break; case 3: /* CLKIN pin */ - SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + MainClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); break; } - break; + break; } - SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; - + SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV; } +//WH /** * Initialize the system From fd82a674abd45f5593123bdbe23b3540a3435226 Mon Sep 17 00:00:00 2001 From: Wim Date: Tue, 27 Jan 2015 21:04:17 +0100 Subject: [PATCH 55/77] Update serial_api.c Fixed the incorrect clocksource for the baud generator. Should be MainClock instead of SystemCoreClock. This also allows the correct use of the PLL for MainClock and SystemCoreClock without breaking the serial baudrate. --- .../mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c index 5e83d9370c..b1964f40df 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c @@ -117,9 +117,10 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { /* Peripheral reset control to UART, a "1" bring it out of reset. */ LPC_SYSCON->PRESETCTRL &= ~(0x1 << (3 + uart_n)); LPC_SYSCON->PRESETCTRL |= (0x1 << (3 + uart_n)); - - UARTSysClk = SystemCoreClock / LPC_SYSCON->UARTCLKDIV; - + +//WH + UARTSysClk = MainClock / LPC_SYSCON->UARTCLKDIV; + // set default baud rate and format serial_baud (obj, 9600); serial_format(obj, 8, ParityNone, 1); From 46317484f7f766f787ca71a93089356aea67d963 Mon Sep 17 00:00:00 2001 From: bcostm Date: Wed, 28 Jan 2015 11:06:44 +0100 Subject: [PATCH 56/77] [NUCLEO_F303RE] Corrections in ADC - remove unavailable ADCs and channels - correct initialization routine --- .../TARGET_NUCLEO_F303RE/PeripheralNames.h | 4 +- .../TARGET_NUCLEO_F303RE/PeripheralPins.c | 8 +-- .../TARGET_NUCLEO_F303RE/analogin_api.c | 62 ++++--------------- 3 files changed, 13 insertions(+), 61 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralNames.h index fea7af3f18..4b9db2f0dc 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralNames.h @@ -38,9 +38,7 @@ extern "C" { typedef enum { ADC_1 = (int)ADC1_BASE, - ADC_2 = (int)ADC2_BASE, - ADC_3 = (int)ADC3_BASE, - ADC_4 = (int)ADC4_BASE + ADC_2 = (int)ADC2_BASE } ADCName; typedef enum { diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralPins.c index f7789176a7..df0db00ae8 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralPins.c @@ -44,18 +44,12 @@ const PinMap PinMap_ADC[] = { {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 {PA_4, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN1 - ARDUINO A2 - {PA_5, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN2 - Warning: LED1 is connected on this pin + {PA_5, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN2 - Warning: LED1 is also connected to this pin {PA_6, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN3 {PA_7, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN4 - {PB_0, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN12 - ARDUINO A3 - {PB_1, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN1 {PB_2, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN12 {PB_11, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN14 - {PB_12, ADC_4, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC4_IN3 - {PB_13, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN5 - {PB_14, ADC_4, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC4_IN4 - {PB_15, ADC_4, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC4_IN5 {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN6 - ARDUINO A5 {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN7 - ARDUINO A4 diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogin_api.c index 487a993316..22c05f53dd 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogin_api.c @@ -41,8 +41,6 @@ void analogin_init(analogin_t *obj, PinName pin) { static int adc1_inited = 0; static int adc2_inited = 0; - static int adc3_inited = 0; - static int adc4_inited = 0; // Get the peripheral name from the pin and assign it to the object obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); @@ -57,8 +55,6 @@ void analogin_init(analogin_t *obj, PinName pin) // Check if ADC is already initialized if ((obj->adc == ADC_1) && adc1_inited) return; if ((obj->adc == ADC_2) && adc2_inited) return; - if ((obj->adc == ADC_3) && adc3_inited) return; - if ((obj->adc == ADC_4) && adc4_inited) return; if (obj->adc == ADC_1) { __ADC12_CLK_ENABLE(); @@ -70,23 +66,13 @@ void analogin_init(analogin_t *obj, PinName pin) adc2_inited = 1; } - if (obj->adc == ADC_3) { - __ADC34_CLK_ENABLE(); - adc3_inited = 1; - } - - if (obj->adc == ADC_4) { - __ADC34_CLK_ENABLE(); - adc4_inited = 1; - } - // Configure ADC AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); AdcHandle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV2; AdcHandle.Init.Resolution = ADC_RESOLUTION12b; AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT; AdcHandle.Init.ScanConvMode = DISABLE; - AdcHandle.Init.EOCSelection = DISABLE; + AdcHandle.Init.EOCSelection = EOC_SINGLE_CONV; AdcHandle.Init.LowPowerAutoWait = DISABLE; AdcHandle.Init.ContinuousConvMode = DISABLE; AdcHandle.Init.NbrOfConversion = 1; @@ -114,51 +100,22 @@ static inline uint16_t adc_read(analogin_t *obj) switch (obj->pin) { case PA_0: - sConfig.Channel = ADC_CHANNEL_1; - break; - case PA_1: - sConfig.Channel = ADC_CHANNEL_2; - break; - case PA_2: - sConfig.Channel = ADC_CHANNEL_3; - break; - case PA_3: - sConfig.Channel = ADC_CHANNEL_4; - break; case PA_4: sConfig.Channel = ADC_CHANNEL_1; break; + case PA_1: case PA_5: sConfig.Channel = ADC_CHANNEL_2; break; + case PA_2: case PA_6: sConfig.Channel = ADC_CHANNEL_3; break; + case PA_3: case PA_7: sConfig.Channel = ADC_CHANNEL_4; break; - case PB_0: - sConfig.Channel = ADC_CHANNEL_12; - break; - case PB_1: - sConfig.Channel = ADC_CHANNEL_1; - break; - case PB_2: - sConfig.Channel = ADC_CHANNEL_12; - break; - case PB_11: - sConfig.Channel = ADC_CHANNEL_14; - break; - case PB_12: - sConfig.Channel = ADC_CHANNEL_3; - break; - case PB_13: - sConfig.Channel = ADC_CHANNEL_5; - break; - case PB_14: - sConfig.Channel = ADC_CHANNEL_4; - break; - case PB_15: + case PC_4: sConfig.Channel = ADC_CHANNEL_5; break; case PC_0: @@ -173,12 +130,15 @@ static inline uint16_t adc_read(analogin_t *obj) case PC_3: sConfig.Channel = ADC_CHANNEL_9; break; - case PC_4: - sConfig.Channel = ADC_CHANNEL_5; - break; case PC_5: sConfig.Channel = ADC_CHANNEL_11; break; + case PB_2: + sConfig.Channel = ADC_CHANNEL_12; + break; + case PB_11: + sConfig.Channel = ADC_CHANNEL_14; + break; default: return 0; } From 7ee7fab4ee1c1b80c3b6b7b683eaf8d41f1d737b Mon Sep 17 00:00:00 2001 From: Jun-Ru Chang Date: Wed, 28 Jan 2015 18:55:37 +0800 Subject: [PATCH 57/77] Include missing header file MBED_ASSERT was defined in mbed_assert.h. Signed-off-by: Jun-Ru Chang --- libraries/mbed/common/BusIn.cpp | 1 + libraries/mbed/common/BusInOut.cpp | 1 + libraries/mbed/common/BusOut.cpp | 1 + 3 files changed, 3 insertions(+) diff --git a/libraries/mbed/common/BusIn.cpp b/libraries/mbed/common/BusIn.cpp index 56885ba9db..ea67cbcb80 100644 --- a/libraries/mbed/common/BusIn.cpp +++ b/libraries/mbed/common/BusIn.cpp @@ -14,6 +14,7 @@ * limitations under the License. */ #include "BusIn.h" +#include "mbed_assert.h" namespace mbed { diff --git a/libraries/mbed/common/BusInOut.cpp b/libraries/mbed/common/BusInOut.cpp index 3e56e61729..5575f90d41 100644 --- a/libraries/mbed/common/BusInOut.cpp +++ b/libraries/mbed/common/BusInOut.cpp @@ -14,6 +14,7 @@ * limitations under the License. */ #include "BusInOut.h" +#include "mbed_assert.h" namespace mbed { diff --git a/libraries/mbed/common/BusOut.cpp b/libraries/mbed/common/BusOut.cpp index 7368c00e6a..4277c57272 100644 --- a/libraries/mbed/common/BusOut.cpp +++ b/libraries/mbed/common/BusOut.cpp @@ -14,6 +14,7 @@ * limitations under the License. */ #include "BusOut.h" +#include "mbed_assert.h" namespace mbed { From 81a364c6e9d158da2ef117789df16ec57585969f Mon Sep 17 00:00:00 2001 From: "nitin.bhaskar.27.09@gmail.com" Date: Wed, 28 Jan 2015 20:57:37 +0530 Subject: [PATCH 58/77] Extended RTOS support for LPC4330 Target --- libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h | 3 +++ libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c | 7 +++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h index e7e5311390..1b6e53587b 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h @@ -238,6 +238,9 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL} #elif defined(TARGET_LPC4088) #define INITIAL_SP (0x10010000UL) +#elif defined(TARGET_LPC4330) +#define INITIAL_SP (0x10008000UL) + #elif defined(TARGET_LPC4337) #define INITIAL_SP (0x10008000UL) diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c index 6baab3a3eb..7f4274d1dd 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c @@ -49,7 +49,7 @@ // counting "main", but not counting "osTimerThread" // Default: 6 #ifndef OS_TASKCNT -# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ +# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \ || defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) # define OS_TASKCNT 14 @@ -65,7 +65,7 @@ // Scheduler (+ interrupts) stack size [bytes] <64-4096:8><#/4> #ifndef OS_SCHEDULERSTKSIZE -# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ +# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \ || defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) # define OS_SCHEDULERSTKSIZE 256 @@ -138,6 +138,9 @@ # elif defined(TARGET_LPC4088) || defined(TARGET_K64F) || defined(TARGET_K22F) # define OS_CLOCK 120000000 +# elif defined(TARGET_LPC4330) +# define OS_CLOCK 204000000 + # elif defined(TARGET_LPC4337) # define OS_CLOCK 204000000 From 04937dc38bc0667fe7935ecff464e810bc7d7ed0 Mon Sep 17 00:00:00 2001 From: Marcomissyou Date: Thu, 29 Jan 2015 13:46:58 +0800 Subject: [PATCH 59/77] remove json, delete toolchain list in target.py because NNN40 is inherit from NRF51822, add SWIO default setting in system_nrf51822.c and SWIO,VERF pin in PinName.h --- .../TARGET_MCU_NRF51822/system_nrf51822.c | 11 +++++++++++ .../TARGET_DELTA_DFCM_NNN40/PinNames.h | 6 ++++-- workspace_tools/muts_all.json | 8 -------- workspace_tools/targets.py | 3 --- workspace_tools/test_spec.json | 5 ----- 5 files changed, 15 insertions(+), 18 deletions(-) delete mode 100644 workspace_tools/muts_all.json delete mode 100644 workspace_tools/test_spec.json diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c index 88cbe35ba6..e3f60b3b1b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c @@ -83,6 +83,17 @@ void SystemInit(void) while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) { // Do nothing. } + + // Default SWIO setting, pull SWIO(p19) to low for turning antenna switch to BLE radiated path. +#ifdef TARGET_DELTA_DFCM_NNN40 + NRF_GPIO->PIN_CNF[19] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + + NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN19_Clear << GPIO_OUTCLR_PIN19_Pos); +#endif } static bool is_manual_peripheral_setup_needed(void) diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h index 7e19c11cb5..1acb4d2a0b 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h @@ -50,7 +50,7 @@ typedef enum { p16 = 16, p17 = 17, p18 = NC, - p19 = NC, + p19 = 19, p20 = 20, p21 = 21, p22 = 22, @@ -96,7 +96,9 @@ typedef enum { A3 = p3, A4 = p4, A5 = p5, - + + SWIO = p19, + VERF0 = p0, // Not connected CTS_PIN_NUMBER = NC, diff --git a/workspace_tools/muts_all.json b/workspace_tools/muts_all.json deleted file mode 100644 index a40550a43f..0000000000 --- a/workspace_tools/muts_all.json +++ /dev/null @@ -1,8 +0,0 @@ -{ - "1" : { - "mcu": "DELTA_DFCM_NNN40", - "port":"COM56", - "disk":"F:\\", - "peripherals": ["24LC256"] - } -} \ No newline at end of file diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 3a1345bf40..953f07343d 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -849,15 +849,12 @@ class DELTA_DFCM_NNN40(NRF51822): self.core = "Cortex-M0" self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] - self.supported_toolchains = "GCC_ARM" class DELTA_DFCM_NNN40_OTA(NRF51822): def __init__(self): NRF51822.__init__(self) self.core = "Cortex-M0" self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'DELTA_DFCM_NNN40'] - self.macros = ['TARGET_NRF51822', 'TARGET_DELTA_DFCM_NNN40','TARGET_OTA_ENABLED'] - self.supported_toolchains = "GCC_ARM" self.MERGE_SOFT_DEVICE = False diff --git a/workspace_tools/test_spec.json b/workspace_tools/test_spec.json deleted file mode 100644 index 647f21f89f..0000000000 --- a/workspace_tools/test_spec.json +++ /dev/null @@ -1,5 +0,0 @@ -{ - "targets": { - "DELTA_DFCM_NNN40" : ["GCC_ARM"] - } -} \ No newline at end of file From 25131013bda23257cf0eff4ba3209e370985f36f Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Thu, 29 Jan 2015 16:37:41 +0900 Subject: [PATCH 60/77] Add RTC function. User can use set_time() and time() by this addition. --- .../hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h | 2 +- .../TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c | 374 ++++++++++++++++++ 2 files changed, 375 insertions(+), 1 deletion(-) create mode 100644 libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h index cae2a6318f..82a80e3b6e 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h @@ -44,7 +44,7 @@ #define DEVICE_CAN 0 -#define DEVICE_RTC 0 +#define DEVICE_RTC 1 #define DEVICE_ETHERNET 1 diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c new file mode 100644 index 0000000000..e984517275 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c @@ -0,0 +1,374 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_assert.h" +#include "device.h" + +#if DEVICE_RTC + +#include "rtc_api.h" +#include "rtc_iodefine.h" + + +#define RCR1_VAL_ON (0x08u) // AIE = 1 +#define RCR1_VAL_OFF (0x00u) +#define RCR2_VAL_ALLSTOP (0x00u) +#define RCR2_VAL_START (0x01u) // START = 1 +#define RCR2_VAL_RESET (0x02u) // RESET = 1 +#define RCR3_VAL (0x00u) +#define RCR5_VAL_EXTAL (0x01u) // RCKSEL = connect EXTAL +#define RCR5_VAL_RTCX1 (0x00u) // RCKSEL = disconnect EXTAL +#define RFRH_VAL_13333 (0x8003u) // 13.3333MHz (= 64Hz * 0x32DCD) +#define RFRL_VAL_13333 (0x2DCDu) // +#define RFRH_VAL_MAX (0x0007u) // MAX value (= 128Hz * 0x7FFFF) +#define RFRL_VAL_MAX (0xFFFFu) // + +#define MASK_00_03_POS (0x000Fu) +#define MASK_04_07_POS (0x00F0u) +#define MASK_08_11_POS (0x0F00u) +#define MASK_12_15_POS (0xF000u) +#define MASK_16_20_POS (0x000F0000u) +#define SHIFT_1_HBYTE (4u) +#define SHIFT_2_HBYTE (8u) +#define SHIFT_3_HBYTE (12u) +#define SHIFT_1BYTE (8u) +#define SHIFT_2BYTE (16u) + +#define TIME_ERROR_VAL (0xFFFFFFFFu) + +static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val); +static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val); +static uint8_t rtc_hex8_to_dec(uint8_t hex_val); +static uint16_t rtc_hex16_to_dec(uint16_t hex_val); + + +/* + * Setup the RTC based on a time structure. + * The rtc_init function should be executed first. + * [in] + * None. + * [out] + * None. + */ +void rtc_init(void) { + volatile uint8_t dummy_read; + + // Set control register + RTC.RCR2 = RCR2_VAL_ALLSTOP; + RTC.RCR1 = RCR1_VAL_ON; + RTC.RCR3 = RCR3_VAL; + RTC.RCR5 = RCR5_VAL_EXTAL; + RTC.RFRH = RFRH_VAL_13333; + RTC.RFRL = RFRL_VAL_13333; + + // Dummy read + dummy_read = RTC.RCR2; + dummy_read = RTC.RCR2; + + RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 + + // Dummy read + dummy_read = RTC.RCR2; + dummy_read = RTC.RCR2; + + // Set timer and alarm. Default value :01-01-1970 00:00:00 + RTC.RSECCNT = 0; + RTC.RMINCNT = 0; + RTC.RHRCNT = 0; + RTC.RWKCNT = 0; + RTC.RDAYCNT = 1; + RTC.RMONCNT = 1; + RTC.RYRCNT = 0x1970; + RTC.RSECAR = 0; + RTC.RMINAR = 0; + RTC.RHRAR = 0; + RTC.RWKAR = 0; + RTC.RDAYAR = 1; + RTC.RMONAR = 1; + RTC.RYRAR = 0x1970; + + // Dummy read + dummy_read = RTC.RYRCNT; + dummy_read = RTC.RYRCNT; + +} + + +/* + * Release the RTC based on a time structure. + * [in] + * None. + * [out] + * None. + */ +void rtc_free(void) { + volatile uint8_t dummy_read; + + // Set control register + RTC.RCR2 = RCR2_VAL_ALLSTOP; + RTC.RCR1 = RCR1_VAL_OFF; + RTC.RCR3 = RCR3_VAL; + RTC.RCR5 = RCR5_VAL_RTCX1; + RTC.RFRH = RFRH_VAL_MAX; + RTC.RFRL = RFRL_VAL_MAX; + + // Dummy read + dummy_read = RTC.RCR2; + dummy_read = RTC.RCR2; + RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 + + // Dummy read + dummy_read = RTC.RCR2; + dummy_read = RTC.RCR2; + + // Set timer and alarm. Default value :01-01-1970 00:00:00 + RTC.RSECCNT = 0; + RTC.RMINCNT = 0; + RTC.RHRCNT = 0; + RTC.RWKCNT = 0; + RTC.RDAYCNT = 1; + RTC.RMONCNT = 1; + RTC.RYRCNT = 0x1970; + RTC.RSECAR = 0; + RTC.RMINAR = 0; + RTC.RHRAR = 0; + RTC.RWKAR = 0; + RTC.RDAYAR = 1; + RTC.RMONAR = 1; + RTC.RYRAR = 0x1970; + + // Dummy read + dummy_read = RTC.RYRCNT; + dummy_read = RTC.RYRCNT; + +} + + +/* + * Check the RTC has been enabled. + * Clock Control Register RTC.RCR1(bit3): 0 = Disabled, 1 = Enabled. + * [in] + * None. + * [out] + * 0:Disabled, 1:Enabled. + */ +int rtc_isenabled(void) { + int ret_val = 0; + + if ((RTC.RCR1 & RCR1_VAL_ON) != 0) { // RTC ON ? + ret_val = 1; + } + + return ret_val; +} + + +/* + * RTC read function. + * [in] + * None. + * [out] + * UNIX timestamp value. + */ +time_t rtc_read(void) { + + struct tm timeinfo; + int err = 0; + uint8_t tmp_regdata; + time_t t; + + if (rtc_isenabled() != 0) { + RTC.RCR1 &= ~0x10u; // CIE = 0 + do { + // before reading process + tmp_regdata = RTC.RCR1; + tmp_regdata &= ~0x80u; // CF = 0 + tmp_regdata |= 0x01u; // AF = 1 + RTC.RCR1 = tmp_regdata; + + // Read RTC register + err = rtc_dec8_to_hex(RTC.RSECCNT , 0 , &timeinfo.tm_sec); + err += rtc_dec8_to_hex(RTC.RMINCNT , 0 , &timeinfo.tm_min); + err += rtc_dec8_to_hex(RTC.RHRCNT , 0 , &timeinfo.tm_hour); + err += rtc_dec8_to_hex(RTC.RDAYCNT , 0 , &timeinfo.tm_mday); + err += rtc_dec8_to_hex(RTC.RMONCNT , 1 , &timeinfo.tm_mon); + err += rtc_dec16_to_hex(RTC.RYRCNT , 1900 , &timeinfo.tm_year); + } while ((RTC.RCR1 & 0x80u) != 0); + } else { + err = 1; + } + + if (err == 0) { + // Convert to timestamp + t = mktime(&timeinfo); + } else { + // Error + t = TIME_ERROR_VAL; + } + + return t; +} + +/* + * Dec(8bit) to Hex function for RTC. + * [in] + * dec_val:Decimal value (from 0x00 to 0x99). + * offset:Subtract offset from dec_val. + * hex_val:Pointer of output hexadecimal value. + * [out] + * 0:Success + * 1:Error + */ +static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val) { + int err = 0; + uint8_t ret_val; + + if (hex_val != NULL) { + if (((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) || + ((dec_val & MASK_00_03_POS) >= 0x0A)) { + err = 1; + } else { + ret_val = ((dec_val & MASK_04_07_POS) >> SHIFT_1_HBYTE) * 10 + + (dec_val & MASK_00_03_POS); + if (ret_val < offset) { + err = 1; + } else { + *hex_val = ret_val - offset; + } + } + } else { + err = 1; + } + + return err; +} + +/* + * Dec(16bit) to Hex function for RTC + * [in] + * dec_val:Decimal value (from 0x0000 to 0x9999). + * offset:Subtract offset from dec_val. + * hex_val:Pointer of output hexadecimal value. + * [out] + * 0:Success + * 1:Error + */ +static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val) { + int err = 0; + uint16_t ret_val; + + if (hex_val != NULL) { + if (((dec_val & MASK_12_15_POS) >= (0x0A << SHIFT_3_HBYTE)) || + ((dec_val & MASK_08_11_POS) >= (0x0A << SHIFT_2_HBYTE)) || + ((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) || + ((dec_val & MASK_00_03_POS) >= 0x0A)) { + err = 1; + *hex_val = 0; + } else { + ret_val = (((dec_val & MASK_12_15_POS)) >> SHIFT_3_HBYTE) * 1000 + + (((dec_val & MASK_08_11_POS)) >> SHIFT_2_HBYTE) * 100 + + (((dec_val & MASK_04_07_POS)) >> SHIFT_1_HBYTE) * 10 + + (dec_val & MASK_00_03_POS); + if (ret_val < offset) { + err = 1; + } else { + *hex_val = ret_val - offset; + } + } + } else { + err = 1; + } + return err; +} + +/* + * RTC write function + * [in] + * t:UNIX timestamp value + * [out] + * None. + */ +void rtc_write(time_t t) { + + struct tm *timeinfo = localtime(&t); + volatile uint16_t dummy_read; + + if (rtc_isenabled() != 0) { + RTC.RCR2 = RCR2_VAL_ALLSTOP; + dummy_read = (uint16_t)RTC.RCR2; + dummy_read = (uint16_t)RTC.RCR2; + RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 + dummy_read = (uint16_t)RTC.RCR2; + dummy_read = (uint16_t)RTC.RCR2; + + RTC.RSECCNT = rtc_hex8_to_dec(timeinfo->tm_sec); + RTC.RMINCNT = rtc_hex8_to_dec(timeinfo->tm_min); + RTC.RHRCNT = rtc_hex8_to_dec(timeinfo->tm_hour); + RTC.RDAYCNT = rtc_hex8_to_dec(timeinfo->tm_mday); + RTC.RMONCNT = rtc_hex8_to_dec(timeinfo->tm_mon + 1); + RTC.RYRCNT = rtc_hex16_to_dec(timeinfo->tm_year + 1900); + dummy_read = (uint16_t)RTC.RYRCNT; + dummy_read = (uint16_t)RTC.RYRCNT; + + RTC.RCR2 = RCR2_VAL_START; // START = 1 + + dummy_read = (uint16_t)RTC.RCR2; + dummy_read = (uint16_t)RTC.RCR2; + } +} + +/* + * HEX to Dec(8bit) function for RTC. + * [in] + * hex_val:Hexadecimal value. + * [out] + * decimal value:From 0x00 to 0x99. + */ +static uint8_t rtc_hex8_to_dec(uint8_t hex_val) { + uint32_t calc_data; + + calc_data = hex_val / 10 * 0x10; + calc_data += hex_val % 10; + + if (calc_data > 0x99) { + calc_data = 0; + } + + return (uint8_t)calc_data; +} + +/* + * HEX to Dec(16bit) function for RTC. + * [in] + * hex_val:Hexadecimal value. + * [out] + * decimal value:From 0x0000 to 0x9999. + */ +static uint16_t rtc_hex16_to_dec(uint16_t hex_val) { + uint32_t calc_data; + calc_data = hex_val / 1000 * 0x1000; + calc_data += ((hex_val / 100) % 10) * 0x100; + calc_data += ((hex_val / 10) % 10) * 0x10; + calc_data += hex_val % 10; + + if (calc_data > 0x9999) { + calc_data = 0; + } + return (uint16_t)calc_data; + +} + +#endif /* DEVICE_RTC */ From 83712b1f8308df76c2445769c4c55acc4bbe1c17 Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Thu, 29 Jan 2015 16:38:21 +0900 Subject: [PATCH 61/77] Add Serial flow control and fix a bug that parity setting is wrong. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Modifies are as below. - Add flow control - Change the range of baud rate that can be set in the baud function. 　8138 bps more -> 128 bps more - Fixed a bug that designation of parity had been reversed in format(). --- .../TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c | 371 ++++++++++++++---- 1 file changed, 289 insertions(+), 82 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c index 64048fbfc7..83b0004dee 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -30,6 +30,8 @@ /****************************************************************************** * INITIALIZATION ******************************************************************************/ +#define PCLK (66666666) // Define the peripheral clock P1 frequency. + #define UART_NUM 8 #define IRQ_NUM 2 @@ -52,35 +54,54 @@ static void uart7_rx_irq(void); static const PinMap PinMap_UART_TX[] = { - {P6_3 , UART2, 7}, {P2_14 , UART0, 6}, - {P5_0 , UART4, 5}, - {P5_3 , UART3, 5}, - {P5_6 , UART6, 5}, {P2_5 , UART1, 6}, + {P6_3 , UART2, 7}, + {P5_3 , UART3, 5}, + {P8_8 , UART3, 7}, + {P5_0 , UART4, 5}, {P8_14 , UART4, 7}, {P8_13 , UART5, 5}, - {P7_4 , UART7, 4}, {P11_10, UART5, 3}, {P6_6 , UART5, 5}, + {P5_6 , UART6, 5}, + {P11_1 , UART6, 4}, + {P7_4 , UART7, 4}, {NC , NC , 0} }; static const PinMap PinMap_UART_RX[] = { - {P6_2 , UART2, 7}, {P2_15 , UART0, 6}, - {P5_1 , UART4, 5}, - {P5_4 , UART3, 5}, - {P5_7 , UART6, 5}, {P2_6 , UART1, 6}, + {P6_2 , UART2, 7}, + {P5_4 , UART3, 5}, + {P8_9 , UART3, 7}, + {P5_1 , UART4, 5}, {P8_15 , UART4, 7}, {P8_11 , UART5, 5}, - {P7_5 , UART7, 4}, {P11_11, UART5, 3}, {P6_7 , UART5, 5}, + {P5_7 , UART6, 5}, + {P11_2 , UART6, 4}, + {P7_5 , UART7, 4}, {NC , NC , 0} }; +static const PinMap PinMap_UART_CTS[] = { + {P2_3 , UART1, 6}, + {P11_7 , UART5, 3}, + {P7_6 , UART7, 4}, + {NC , NC , 0} +}; +static const PinMap PinMap_UART_RTS[] = { + {P2_7 , UART1, 6}, + {P11_8 , UART5, 3}, + {P7_7 , UART7, 4}, + {NC , NC , 0} +}; + + + static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST; static uart_irq_handler irq_handler; @@ -141,7 +162,7 @@ static __IO uint16_t *SCFSR_MATCH[] = { void serial_init(serial_t *obj, PinName tx, PinName rx) { - volatile uint8_t dummy ; + volatile uint8_t dummy ; int is_stdio_uart = 0; // determine the UART to use uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); @@ -153,14 +174,30 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { obj->uart = (struct st_scif *)SCIF[uart]; // enable power switch (uart) { - case UART0: CPG.STBCR4 &= ~(1 << 7); break; - case UART1: CPG.STBCR4 &= ~(1 << 6); break; - case UART2: CPG.STBCR4 &= ~(1 << 5); break; - case UART3: CPG.STBCR4 &= ~(1 << 4); break; - case UART4: CPG.STBCR4 &= ~(1 << 3); break; - case UART5: CPG.STBCR4 &= ~(1 << 2); break; - case UART6: CPG.STBCR4 &= ~(1 << 1); break; - case UART7: CPG.STBCR4 &= ~(1 << 0); break; + case UART0: + CPG.STBCR4 &= ~(1 << 7); + break; + case UART1: + CPG.STBCR4 &= ~(1 << 6); + break; + case UART2: + CPG.STBCR4 &= ~(1 << 5); + break; + case UART3: + CPG.STBCR4 &= ~(1 << 4); + break; + case UART4: + CPG.STBCR4 &= ~(1 << 3); + break; + case UART5: + CPG.STBCR4 &= ~(1 << 2); + break; + case UART6: + CPG.STBCR4 &= ~(1 << 1); + break; + case UART7: + CPG.STBCR4 &= ~(1 << 0); + break; } dummy = CPG.STBCR4; @@ -181,7 +218,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { /* ORER bit clear */ obj->uart->SCLSR = 0; - /* ---- Serial extension mode register (SCEMR) setting ---- + /* ---- Serial extension mode register (SCEMR) setting ---- b7 BGDM - Baud rate generator double-speed mode : Normal mode b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */ obj->uart->SCEMR = 0x0000u; @@ -193,26 +230,49 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { /* ---- FIFO control register (SCFCR) setting ---- */ obj->uart->SCFCR = 0x0030u; - /* ---- Serial port register (SCSPTR) setting ---- + /* ---- Serial port register (SCSPTR) setting ---- b1 SPB2IO - Serial port break output : disabled b0 SPB2DT - Serial port break data : High-level */ - //obj->uart->SCSPTR |= 0x0000u; + obj->uart->SCSPTR = 0x0003u; // SPB2IO = 1, SPB2DT = 1 obj->uart->SCSCR = 0x00F0; + /* ---- Line status register (SCLSR) setting ---- + b0 ORER - Overrun error detect : clear */ + + if (obj->uart->SCLSR & 0x0001) { + obj->uart->SCLSR = 0u; // ORER clear + } + // pinout the chosen uart pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(rx, PinMap_UART_RX); switch (uart) { - case UART0: obj->index = 0; break; - case UART1: obj->index = 1; break; - case UART2: obj->index = 2; break; - case UART3: obj->index = 3; break; - case UART4: obj->index = 4; break; - case UART5: obj->index = 5; break; - case UART6: obj->index = 6; break; - case UART7: obj->index = 7; break; + case UART0: + obj->index = 0; + break; + case UART1: + obj->index = 1; + break; + case UART2: + obj->index = 2; + break; + case UART3: + obj->index = 3; + break; + case UART4: + obj->index = 4; + break; + case UART5: + obj->index = 5; + break; + case UART6: + obj->index = 6; + break; + case UART7: + obj->index = 7; + break; } uart_data[obj->index].sw_rts.pin = NC; uart_data[obj->index].sw_cts.pin = NC; @@ -232,13 +292,52 @@ void serial_free(serial_t *obj) { // serial_baud // set the baud rate, taking in to account the current SystemFrequency void serial_baud(serial_t *obj, int baudrate) { + uint16_t DL; - uint32_t PCLK = 66666666; + obj->uart->SCSMR &= ~0x0003; - uint16_t DL = (PCLK / (32 * baudrate)) -1; - - // set LCR[DLAB] to enable writing to divider registers - obj->uart->SCBRR = DL; + if (baudrate > 32552) { + obj->uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1 + DL = PCLK / (8 * baudrate); + if (DL > 0) { + DL--; + } + obj->uart->SCBRR = (uint8_t)DL; + } else if (baudrate > 16276) { + obj->uart->SCEMR = 0x0080; // BGDM = 1 + obj->uart->SCBRR = PCLK / (16 * baudrate) - 1; + } else if (baudrate > 8138) { + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = PCLK / (32 * baudrate) - 1; + } else if (baudrate > 4169) { + obj->uart->SCSMR |= 0x0001; + obj->uart->SCEMR = 0x0080; // BGDM = 1 + obj->uart->SCBRR = PCLK / (64 * baudrate) - 1; + } else if (baudrate > 2034) { + obj->uart->SCSMR |= 0x0001; + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = PCLK / (128 * baudrate) - 1; + } else if (baudrate > 1017) { + obj->uart->SCSMR |= 0x0002; + obj->uart->SCEMR = 0x0080; // BGDM = 1 + obj->uart->SCBRR = PCLK / (256 * baudrate) - 1; + } else if (baudrate > 508) { + obj->uart->SCSMR |= 0x0002; + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = PCLK / (512 * baudrate) - 1; + } else if (baudrate > 254) { + obj->uart->SCSMR |= 0x0003; + obj->uart->SCEMR = 0x0080; // BGDM = 1 + obj->uart->SCBRR = PCLK / (1024 * baudrate) - 1; + } else if (baudrate > 127) { + obj->uart->SCSMR |= 0x0003; + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = PCLK / (2048 * baudrate) - 1; + } else { + obj->uart->SCSMR |= 0x0003; + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = 0xFFu; + } } void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { @@ -246,9 +345,9 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b int parity_select; MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits - MBED_ASSERT((data_bits > 6) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits + MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 5: 5 data bits ... 3: 8 data bits MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || - (parity == ParityForced1) || (parity == ParityForced0)); + (parity == ParityForced1) || (parity == ParityForced0)); stop_bits = (stop_bits == 1)? 0: (stop_bits == 2)? 1: @@ -259,28 +358,30 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b 0; // must not to be switch (parity) { - case ParityNone: - parity_enable = 0; - parity_select = 0; - break; - case ParityOdd: - parity_enable = 1; - parity_select = 0; - break; - case ParityEven: - parity_enable = 1; - parity_select = 1; - break; - default: - parity_enable = 0; - parity_select = 0; - break; + case ParityNone: + parity_enable = 0; + parity_select = 0; + break; + case ParityOdd: + parity_enable = 1; + parity_select = 1; + break; + case ParityEven: + parity_enable = 1; + parity_select = 0; + break; + case ParityForced1: + case ParityForced0: + default: + parity_enable = 0; + parity_select = 0; + break; } obj->uart->SCSMR = data_bits << 6 - | parity_enable << 5 - | parity_select << 4 - | stop_bits << 3; + | parity_enable << 5 + | parity_select << 4 + | stop_bits << 3; } /****************************************************************************** @@ -312,23 +413,55 @@ static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) { } /* TX handler */ -static void uart0_tx_irq(void) {uart_tx_irq(SCIFTXI0_IRQn, 0);} -static void uart1_tx_irq(void) {uart_tx_irq(SCIFTXI1_IRQn, 1);} -static void uart2_tx_irq(void) {uart_tx_irq(SCIFTXI2_IRQn, 2);} -static void uart3_tx_irq(void) {uart_tx_irq(SCIFTXI3_IRQn, 3);} -static void uart4_tx_irq(void) {uart_tx_irq(SCIFTXI4_IRQn, 4);} -static void uart5_tx_irq(void) {uart_tx_irq(SCIFTXI5_IRQn, 5);} -static void uart6_tx_irq(void) {uart_tx_irq(SCIFTXI6_IRQn, 6);} -static void uart7_tx_irq(void) {uart_tx_irq(SCIFTXI7_IRQn, 7);} +static void uart0_tx_irq(void) { + uart_tx_irq(SCIFTXI0_IRQn, 0); +} +static void uart1_tx_irq(void) { + uart_tx_irq(SCIFTXI1_IRQn, 1); +} +static void uart2_tx_irq(void) { + uart_tx_irq(SCIFTXI2_IRQn, 2); +} +static void uart3_tx_irq(void) { + uart_tx_irq(SCIFTXI3_IRQn, 3); +} +static void uart4_tx_irq(void) { + uart_tx_irq(SCIFTXI4_IRQn, 4); +} +static void uart5_tx_irq(void) { + uart_tx_irq(SCIFTXI5_IRQn, 5); +} +static void uart6_tx_irq(void) { + uart_tx_irq(SCIFTXI6_IRQn, 6); +} +static void uart7_tx_irq(void) { + uart_tx_irq(SCIFTXI7_IRQn, 7); +} /* RX handler */ -static void uart0_rx_irq(void) {uart_rx_irq(SCIFRXI0_IRQn, 0);} -static void uart1_rx_irq(void) {uart_rx_irq(SCIFRXI1_IRQn, 1);} -static void uart2_rx_irq(void) {uart_rx_irq(SCIFRXI2_IRQn, 2);} -static void uart3_rx_irq(void) {uart_rx_irq(SCIFRXI3_IRQn, 3);} -static void uart4_rx_irq(void) {uart_rx_irq(SCIFRXI4_IRQn, 4);} -static void uart5_rx_irq(void) {uart_rx_irq(SCIFRXI5_IRQn, 5);} -static void uart6_rx_irq(void) {uart_rx_irq(SCIFRXI6_IRQn, 6);} -static void uart7_rx_irq(void) {uart_rx_irq(SCIFRXI7_IRQn, 7);} +static void uart0_rx_irq(void) { + uart_rx_irq(SCIFRXI0_IRQn, 0); +} +static void uart1_rx_irq(void) { + uart_rx_irq(SCIFRXI1_IRQn, 1); +} +static void uart2_rx_irq(void) { + uart_rx_irq(SCIFRXI2_IRQn, 2); +} +static void uart3_rx_irq(void) { + uart_rx_irq(SCIFRXI3_IRQn, 3); +} +static void uart4_rx_irq(void) { + uart_rx_irq(SCIFRXI4_IRQn, 4); +} +static void uart5_rx_irq(void) { + uart_rx_irq(SCIFRXI5_IRQn, 5); +} +static void uart6_rx_irq(void) { + uart_rx_irq(SCIFRXI6_IRQn, 6); +} +static void uart7_rx_irq(void) { + uart_rx_irq(SCIFRXI7_IRQn, 7); +} void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { irq_handler = handler; @@ -369,42 +502,79 @@ static void serial_flow_irq_set(serial_t *obj, uint32_t enable) { * READ/WRITE ******************************************************************************/ int serial_getc(serial_t *obj) { - uint16_t dummy_read; + uint16_t err_read; int data; + int was_masked; + was_masked = __disable_irq(); if (obj->uart->SCFSR & 0x93) { - dummy_read = obj->uart->SCFSR; - obj->uart->SCFSR = (dummy_read & ~0x93); + err_read = obj->uart->SCFSR; + obj->uart->SCFSR = (err_read & ~0x93); } obj->uart->SCSCR |= 0x0040; // Set RIE + if (!was_masked) { + __enable_irq(); + } + + if (obj->uart->SCLSR & 0x0001) { + obj->uart->SCLSR = 0u; // ORER clear + } + while (!serial_readable(obj)); data = obj->uart->SCFRDR & 0xff; - obj->uart->SCFSR &= 0xfffc; // Clear DR,RDF + + was_masked = __disable_irq(); + err_read = obj->uart->SCFSR; + obj->uart->SCFSR = (err_read & 0xfffD); // Clear RDF + if (!was_masked) { + __enable_irq(); + } + + if (err_read & 0x80) { + data = -1; //err + } return data; } void serial_putc(serial_t *obj, int c) { uint16_t dummy_read; - + int was_masked; + + was_masked = __disable_irq(); obj->uart->SCSCR |= 0x0080; // Set TIE + if (!was_masked) { + __enable_irq(); + } while (!serial_writable(obj)); obj->uart->SCFTDR = c; + was_masked = __disable_irq(); dummy_read = obj->uart->SCFSR; obj->uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE + if (!was_masked) { + __enable_irq(); + } uart_data[obj->index].count++; } int serial_readable(serial_t *obj) { - return obj->uart->SCFSR & 0x02; // RDF + return ((obj->uart->SCFSR & 0x02) != 0); // RDF } int serial_writable(serial_t *obj) { - return obj->uart->SCFSR & 0x20; // TDFE + return ((obj->uart->SCFSR & 0x20) != 0); // TDFE } void serial_clear(serial_t *obj) { - obj->uart->SCFCR = 0x06; - obj->uart->SCFCR = 0x06; + int was_masked; + was_masked = __disable_irq(); + + obj->uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1 + obj->uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0 + obj->uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0 + + if (!was_masked) { + __enable_irq(); + } } void serial_pinout_tx(PinName tx) { @@ -412,12 +582,49 @@ void serial_pinout_tx(PinName tx) { } void serial_break_set(serial_t *obj) { + int was_masked; + was_masked = __disable_irq(); + // TxD Output(L) + obj->uart->SCSPTR &= ~0x0001u; // SPB2DT = 0 + obj->uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable) + if (!was_masked) { + __enable_irq(); + } } void serial_break_clear(serial_t *obj) { + int was_masked; + was_masked = __disable_irq(); + obj->uart->SCSCR |= 0x0020u; // TE = 1 (Output enable) + obj->uart->SCSPTR |= 0x0001u; // SPB2DT = 1 + if (!was_masked) { + __enable_irq(); + } } void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { + // determine the UART to use + int was_masked; + serial_flow_irq_set(obj, 0); + + if (type == FlowControlRTSCTS) { + was_masked = __disable_irq(); + obj->uart->SCFCR = 0x0008u; // CTS/RTS enable + if (!was_masked) { + __enable_irq(); + } + pinmap_pinout(rxflow, PinMap_UART_RTS); + pinmap_pinout(txflow, PinMap_UART_CTS); + } else { + was_masked = __disable_irq(); + obj->uart->SCFCR = 0x0000u; // CTS/RTS diable + if (!was_masked) { + __enable_irq(); + } + } } + + + From 44b4fb4b41f107fa71a4ff601af0ff9fdb07a33b Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Thu, 29 Jan 2015 16:38:48 +0900 Subject: [PATCH 62/77] Modify some processing of AnalgIn. Modifies are as below. - Change the A/D conversion time to run fast. - Change the macro value of ANALOGIN_MEDIAN_FILTER 1 -> 0 --- .../TARGET_RZ_A1H/analogin_api.c | 61 +++++++++---------- 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c index cafb21ed16..eebc3c0507 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c @@ -22,20 +22,18 @@ #include "adc_iodefine.h" #include "cpg_iodefine.h" -#define ANALOGIN_MEDIAN_FILTER 1 - -#define ADC_12BIT_RANGE 0xFFF +#define ANALOGIN_MEDIAN_FILTER 0 static const PinMap PinMap_ADC[] = { {P1_8, AN0, 1}, {P1_9, AN1, 1}, {P1_10, AN2, 1}, {P1_11, AN3, 1}, - {P1_12, AN3, 1}, + {P1_12, AN3, 1}, {P1_13, AN5, 1}, - {P1_14, AN5, 1}, + {P1_14, AN5, 1}, {P1_15, AN7, 1}, - {NC, NC, 0} + {NC, NC, 0} }; static volatile uint16_t *ADCDR[] = { @@ -49,45 +47,41 @@ static volatile uint16_t *ADCDR[] = { &ADCADDRH, }; -#define ADC_RANGE ADC_12BIT_RANGE - void analogin_init(analogin_t *obj, PinName pin) { obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); MBED_ASSERT(obj->adc != (ADCName)NC); - + CPGSTBCR3 &= ~(1 << 1); CPGSTBCR6 &= ~(1 << 7); - // 000_0 000_1 00_00 0_xxx - // 15: ADFlag 14: IntEn 13: start, [12:9] Triger..0 - // [8:6] CLK 100 :: 12-bit 1054tclk - // [5:3] scanmode 000 :: single mode - // [2:0] channel select - ADCADCSR = 0x01c0 ; - - for (int i = 0; i< sizeof(PinMap_ADC)/sizeof(PinMap); i++) { - pinmap_pinout(PinMap_ADC[i].pin, PinMap_ADC); - } + // 15: ADF 14: ADIE 13: ADST, [12:9] TRGS..0 + // [8:6] CKS 000 :: 256tclk + // [5:3] MDS 000 :: single mode + // [2:0] CH 000 :: AN0 + ADCADCSR = 0x0000; - //pinmap_pinout(pin, PinMap_ADC); + pinmap_pinout(pin, PinMap_ADC); } static inline uint32_t adc_read(analogin_t *obj) { + volatile uint16_t data; + // Select the appropriate channel and start conversion - ADCADCSR &= 0xfff8; - ADCADCSR |= (1 << 13 | (obj->adc&0x7)); - - // Repeatedly get the sample data until DONE bit -#define nothing - while ((ADCADCSR & (1 << 15)) == 0 || (ADCADCSR & (1<<13)) != 0) nothing; - + ADCADCSR |= (1 << 13 | (obj->adc & 0x7)); + + // Wait end of conversion + do { + data = ADCADCSR; + } while (((data & (1 << 15)) == 0) || ((data & (1 << 13)) != 0)); + // clear flag ADCADCSR &= ~(1 << 15); - - return ((*(ADCDR[obj->adc]))>>4) & ADC_RANGE; // 12 bit + + return ((*(ADCDR[obj->adc])) >> 4) & 0x0FFF; // 12 bits range } +#if ANALOGIN_MEDIAN_FILTER static inline void order(uint32_t *a, uint32_t *b) { if (*a > *b) { uint32_t t = *a; @@ -95,6 +89,7 @@ static inline void order(uint32_t *a, uint32_t *b) { *b = t; } } +#endif static inline uint32_t adc_read_u32(analogin_t *obj) { uint32_t value; @@ -114,12 +109,12 @@ static inline uint32_t adc_read_u32(analogin_t *obj) { uint16_t analogin_read_u16(analogin_t *obj) { uint32_t value = adc_read_u32(obj); - - return value; - //(value << 4) | ((value >> 8) & 0x000F); // 12 bit + + return (value << 4) | ((value >> 8) & 0x000F); // 12-bit to 16-bit conversion } float analogin_read(analogin_t *obj) { uint32_t value = adc_read_u32(obj); - return (float)value * (1.0f / (float)ADC_RANGE); + + return (float)value * (1.0f / (float)0x0FFF); // 12 bits range } From 88604ff8fefa235023e1d8dfd173f377d5024615 Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Thu, 29 Jan 2015 16:40:16 +0900 Subject: [PATCH 63/77] Add some processing of I2C driver Changes are as below - Add STOP condition omission processing of I2C Master - Add I2C Slave processing --- .../TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c | 395 +++++++++++------- .../TARGET_RENESAS/TARGET_RZ_A1H/objects.h | 1 + 2 files changed, 253 insertions(+), 143 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c index 7232396925..e9bbc3f69a 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c @@ -34,8 +34,9 @@ volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; /* RIICnCR2 */ #define CR2_ST (1 << 1) +#define CR2_RS (1 << 2) #define CR2_SP (1 << 3) -#define CR2_NACKF (1 << 4) +#define CR2_TRS (1 << 5) #define CR2_BBSY (1 << 7) /* RIICnMR3 */ @@ -43,7 +44,14 @@ volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; #define MR3_ACKWP (1 << 4) #define MR3_WAIT (1 << 6) +/* RIICnSER */ +#define SER_SAR0E (1 << 0) + +/* RIICnSR1 */ +#define SR1_AAS0 (1 << 0) + /* RIICnSR2 */ +#define SR2_START (1 << 2) #define SR2_STOP (1 << 3) #define SR2_NACKF (1 << 4) #define SR2_RDRF (1 << 5) @@ -67,35 +75,10 @@ static const PinMap PinMap_I2C_SCL[] = { }; -/* Clear the Transmit data Empty TDRE */ -static inline int i2c_addressed(i2c_t *obj) { - volatile int sar0 = (REG(SR1.UINT8[0])&1), - trs = (REG(CR2.UINT8[0])&0x20) >> 5; - return sar0 | (trs <<1); -} - static inline int i2c_status(i2c_t *obj) { return REG(SR2.UINT8[0]); } -static inline void i2c_clear_TDRE(i2c_t *obj) { - REG(SR2.UINT32) &= ~SR2_TDRE; -} - -static inline int i2c_wait_RDRF(i2c_t *obj) { - int timeout = 0; - - /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ - while (!(i2c_status(obj) & SR2_RDRF)) { - timeout ++; - if (timeout >= TIMEOUT_1S) { - return -1; - } - } - - return 0; -} - static void i2c_reg_reset(i2c_t *obj) { /* full reset */ REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off @@ -119,7 +102,20 @@ static void i2c_reg_reset(i2c_t *obj) { REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset } -/* Wait until the Trans Data Empty (TDRE) is set */ +static inline int i2c_wait_RDRF(i2c_t *obj) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while (!(i2c_status(obj) & SR2_RDRF)) { + timeout ++; + if (timeout >= TIMEOUT_1S) { + return -1; + } + } + + return 0; +} + static int i2c_wait_TDRE(i2c_t *obj) { int timeout = 0; @@ -149,6 +145,20 @@ static int i2c_wait_TEND(i2c_t *obj) { } +static int i2c_wait_START(i2c_t *obj) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while (!(i2c_status(obj) & SR2_START)) { + timeout ++; + if (timeout >= TIMEOUT_1S) { + return -1; + } + } + + return 0; +} + static int i2c_wait_STOP(i2c_t *obj) { int timeout = 0; @@ -163,26 +173,42 @@ static int i2c_wait_STOP(i2c_t *obj) { return 0; } -static void i2c_set_NACKF_STOP(i2c_t *obj) { +static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) { /* SR2.NACKF = 0 */ REG(SR2.UINT32) &= ~SR2_NACKF; - /* SR2.STOP = 0 */ + /* SR2.STOP = 0 */ REG(SR2.UINT32) &= ~SR2_STOP; } -static void i2c_set_err_noslave(i2c_t *obj) { - i2c_stop(obj); - (void)i2c_wait_STOP(obj); - i2c_set_NACKF_STOP(obj); +static void i2c_set_MR3_NACK(i2c_t *obj) { + /* send a NOT ACK */ + REG(MR3.UINT32) |= MR3_ACKWP; + REG(MR3.UINT32) |= MR3_ACKBT; + REG(MR3.UINT32) &= ~MR3_ACKWP; +} + +static void i2c_set_MR3_ACK(i2c_t *obj) { + /* send a ACK */ + REG(MR3.UINT32) |= MR3_ACKWP; + REG(MR3.UINT32) &= ~MR3_ACKBT; + REG(MR3.UINT32) &= ~MR3_ACKWP; } static inline void i2c_power_enable(i2c_t *obj) { volatile uint8_t dummy; switch ((int)obj->i2c) { - case I2C_0: CPGSTBCR9 &= ~(0x80); break; - case I2C_1: CPGSTBCR9 &= ~(0x40); break; - case I2C_2: CPGSTBCR9 &= ~(0x20); break; - case I2C_3: CPGSTBCR9 &= ~(0x10); break; + case I2C_0: + CPGSTBCR9 &= ~(0x80); + break; + case I2C_1: + CPGSTBCR9 &= ~(0x40); + break; + case I2C_2: + CPGSTBCR9 &= ~(0x20); + break; + case I2C_3: + CPGSTBCR9 &= ~(0x10); + break; } dummy = CPGSTBCR9; } @@ -202,6 +228,8 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) { pinmap_pinout(sda, PinMap_I2C_SDA); pinmap_pinout(scl, PinMap_I2C_SCL); + + obj->last_stop_flag = 1; } inline int i2c_start(i2c_t *obj) { @@ -210,10 +238,7 @@ inline int i2c_start(i2c_t *obj) { while (REG(CR2.UINT32) & CR2_BBSY) { timeout ++; if (timeout >= obj->bbsy_wait_cnt) { - i2c_reg_reset(obj); - /* Start Condition */ - REG(CR2.UINT8[0]) |= CR2_ST; - return 0; + break; } } /* Start Condition */ @@ -222,8 +247,17 @@ inline int i2c_start(i2c_t *obj) { return 0; } +inline int i2c_restart(i2c_t *obj) { + /* SR2.START = 0 */ + REG(SR2.UINT32) &= ~SR2_START; + /* ReStart condition */ + REG(CR2.UINT32) |= CR2_RS; + + return 0; +} + inline int i2c_stop(i2c_t *obj) { - /* SR2.STOP = 0 */ + /* SR2.STOP = 0 */ REG(SR2.UINT32) &= ~SR2_STOP; /* Stop condition */ REG(CR2.UINT32) |= CR2_SP; @@ -231,6 +265,19 @@ inline int i2c_stop(i2c_t *obj) { return 0; } +static void i2c_set_err_noslave(i2c_t *obj, int stop) { + if (stop) { + (void)i2c_stop(obj); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + } else { + (void)i2c_restart(obj); + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + REG(SR2.UINT32) &= ~SR2_START; + } +} + static inline int i2c_do_write(i2c_t *obj, int value) { int timeout = 0; @@ -259,14 +306,14 @@ static inline int i2c_do_write(i2c_t *obj, int value) { static inline int i2c_read_address_write(i2c_t *obj, int value) { int status; + status = i2c_wait_TDRE(obj); if (status == 0) { /* write the data */ REG(DRT.UINT32) = value; - return 0; - } else { - return status; } + + return status; } @@ -276,15 +323,9 @@ static inline int i2c_do_read(i2c_t *obj, int last) { /* Set MR3 WAIT bit is 1 */; REG(MR3.UINT32) |= MR3_WAIT; } else if (last == 1) { - /* send a NOT ACK */ - REG(MR3.UINT32) |= MR3_ACKWP; - REG(MR3.UINT32) |= MR3_ACKBT; - REG(MR3.UINT32) &= ~MR3_ACKWP; + i2c_set_MR3_NACK(obj); } else { - /* send a ACK */ - REG(MR3.UINT32) |= MR3_ACKWP; - REG(MR3.UINT32) &= ~MR3_ACKBT; - REG(MR3.UINT32) &= ~MR3_ACKWP; + i2c_set_MR3_ACK(obj); } /* return the data */ @@ -383,27 +424,45 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int value; volatile uint32_t work_reg = 0; - status = i2c_start(obj); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_BUS_BUSY; + if(length <= 0) { + return 0; } + i2c_set_MR3_ACK(obj); + /* There is a STOP condition for last processing */ + if (obj->last_stop_flag != 0) { + status = i2c_start(obj); + if (status != 0) { + i2c_set_err_noslave(obj, stop); + return I2C_ERROR_BUS_BUSY; + } + } + obj->last_stop_flag = stop; /* Send Slave address */ status = i2c_read_address_write(obj, (address | 0x01)); if (status != 0) { - i2c_set_err_noslave(obj); + i2c_set_err_noslave(obj, stop); return I2C_ERROR_NO_SLAVE; } - /* wati RDRF */ + /* wait RDRF */ status = i2c_wait_RDRF(obj); /* check ACK/NACK */ - if ((status != 0) || (REG(SR2.UINT32) & CR2_NACKF == 1)) { + if ((status != 0) || (REG(SR2.UINT32) & SR2_NACKF == 1)) { /* Slave sends NACK */ - i2c_stop(obj); - /* dummy read */ - value = REG(DRR.UINT32); - (void)i2c_wait_STOP(obj); - i2c_set_NACKF_STOP(obj); + /* If not repeated start, send stop. */ + if (stop) { + i2c_stop(obj); + /* dummy read */ + value = REG(DRR.UINT32); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + } else { + (void)i2c_restart(obj); + /* dummy read */ + value = REG(DRR.UINT32); + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + REG(SR2.UINT32) &= ~SR2_START; + } return I2C_ERROR_NO_SLAVE; } /* Read in all except last byte */ @@ -414,7 +473,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { /* wait for it to arrive */ status = i2c_wait_RDRF(obj); if (status != 0) { - i2c_set_err_noslave(obj); + i2c_set_err_noslave(obj, stop); return I2C_ERROR_NO_SLAVE; } /* Recieve the data */ @@ -428,60 +487,55 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { data[count] = (char)value; } } else if (length == 2) { - /* Set MR3 WATI bit is 1 */; + /* Set MR3 WATI bit is 1 */ REG(MR3.UINT32) |= MR3_WAIT; /* dummy read */ value = REG(DRR.UINT32); /* wait for it to arrive */ status = i2c_wait_RDRF(obj); if (status != 0) { - i2c_set_err_noslave(obj); + i2c_set_err_noslave(obj, stop); return I2C_ERROR_NO_SLAVE; } - /* send a NOT ACK */ - REG(MR3.UINT32) |= MR3_ACKWP; - REG(MR3.UINT32) |= MR3_ACKBT; - REG(MR3.UINT32) &= ~MR3_ACKWP; + i2c_set_MR3_NACK(obj); data[count] = (char)REG(DRR.UINT32); count++; - } else if (length == 1) { + } else { + /* length == 1 */ /* Set MR3 WATI bit is 1 */; REG(MR3.UINT32) |= MR3_WAIT; - /* send a NOT ACK */ - REG(MR3.UINT32) |= MR3_ACKWP; - REG(MR3.UINT32) |= MR3_ACKBT; - REG(MR3.UINT32) &= ~MR3_ACKWP; + i2c_set_MR3_NACK(obj); /* dummy read */ value = REG(DRR.UINT32); - } else { - return I2C_ERROR_NO_SLAVE; } /* wait for it to arrive */ status = i2c_wait_RDRF(obj); if (status != 0) { - i2c_set_err_noslave(obj); + i2c_set_err_noslave(obj, stop); return I2C_ERROR_NO_SLAVE; } + /* If not repeated start, send stop. */ if (stop) { - /* RIICnSR2.STOP = 0 */ - REG(SR2.UINT32) &= ~SR2_STOP; - /* RIICnCR2.SP = 1 */ - REG(CR2.UINT32) |= CR2_SP; + (void)i2c_stop(obj); /* RIICnDRR read */ value = REG(DRR.UINT32) & 0xFF; data[count] = (char)value; /* RIICnMR3.WAIT = 0 */ REG(MR3.UINT32) &= ~MR3_WAIT; (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); } else { + (void)i2c_restart(obj); /* RIICnDRR read */ value = REG(DRR.UINT32) & 0xFF; data[count] = (char)value; /* RIICnMR3.WAIT = 0 */ REG(MR3.UINT32) &= ~MR3_WAIT; + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + REG(SR2.UINT32) &= ~SR2_START; } - i2c_set_NACKF_STOP(obj); return length; } @@ -490,37 +544,51 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { int cnt; int status; - status = i2c_start(obj); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_BUS_BUSY; + if(length <= 0) { + return 0; } + + /* There is a STOP condition for last processing */ + if (obj->last_stop_flag != 0) { + status = i2c_start(obj); + if (status != 0) { + i2c_set_err_noslave(obj, stop); + return I2C_ERROR_BUS_BUSY; + } + } + obj->last_stop_flag = stop; /* Send Slave address */ status = i2c_do_write(obj, address); if (status != 0) { - i2c_set_err_noslave(obj); + i2c_set_err_noslave(obj, stop); return I2C_ERROR_NO_SLAVE; } /* Send Write data */ for (cnt=0; cnt> 4; + switch(status) { - case 0x3: retval = 1; break; - case 0x2: retval = 2; break; - case 0x1: retval = 3; break; - default : retval = 1; break; + case 0x01: + /* the master is writing to this slave */ + retval = 3; + break; + case 0x02: + /* the master is writing to all slave */ + retval = 2; + break; + case 0x03: + /* the master has requested a read from this slave */ + retval = 1; + break; + default : + /* no data */ + retval = 0; + break; } - return(retval); + return retval; } int i2c_slave_read(i2c_t *obj, char *data, int length) { - int count = 0; - int status; + int timeout = 0; + int count; + int break_flg = 0; - volatile int dummy = REG(DRR.UINT32) ; - - do { - i2c_wait_RDRF(obj); - status = i2c_status(obj); - if(!(status & 0x10)) { - data[count] = REG(DRR.UINT32) & 0xFF; - } - count++; - } while ( !(status & 0x10) && (count < length) ); - - if(status & 0x10) { - i2c_stop(obj); - (void)i2c_wait_STOP(obj); - i2c_set_NACKF_STOP(obj); + if(length <= 0) { + return 0; } + for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) { + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while ((i2c_status(obj) & SR2_STOP) || (!(i2c_status(obj) & SR2_RDRF))) { + /* RIICnSR2.STOP = 1 or RIICnSR2.RDRF = 0 */ + if (i2c_status(obj) & SR2_STOP) { + /* RIICnSR2.STOP = 1 */ + break_flg = 1; + break; + } + timeout ++; + if (timeout >= TIMEOUT_1S) { + return -1; + } + } + if (break_flg == 0) { + if (count == 0) { + /* dummy read */ + (void)REG(DRR.UINT32); + } else { + data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF); + } + } + } + if (break_flg == 0) { + (void)i2c_wait_STOP(obj); + } else { + if (i2c_status(obj) & SR2_RDRF) { + if (count <= 1) { + /* fail safe */ + /* dummy read */ + (void)REG(DRR.UINT32); + } else { + data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF); + } + } + } + /* SR2.STOP = 0 */ + REG(SR2.UINT32) &= ~SR2_STOP; - //i2c_clear_TDRE(obj); - - return count; + return (count - 1); } int i2c_slave_write(i2c_t *obj, const char *data, int length) { int count = 0; - int status; + int status = 0; if(length <= 0) { - return(0); + return 0; } - do { + while ((count < length) && (status == 0)) { status = i2c_do_write(obj, data[count]); count++; - } while ((count < length) && !(status & 0x10)); - - if (!(status & 0x10)) { - i2c_stop(obj); - (void)i2c_wait_STOP(obj); - i2c_set_NACKF_STOP(obj); } + if (status == 0) { + /* Wait send end */ + status = i2c_wait_TEND(obj); + if (status != 0) { + i2c_set_err_noslave(obj, 1); + return 0; + } + } + /* dummy read */ + (void)REG(DRR.UINT32); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); - i2c_clear_TDRE(obj); - - return(count); + return count; } void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { - REG(SAR0.UINT32) = address & 0xfe; + REG(SAR0.UINT32) = address & 0xfffffffe; } diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h index bb7d45b50d..c1f7c142e6 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h @@ -35,6 +35,7 @@ struct i2c_s { uint8_t width_low; uint8_t width_hi; int bbsy_wait_cnt; + int last_stop_flag; }; struct spi_s { From 4d371d2c9ed99054c1418d23a9a585d36a523d1f Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Thu, 29 Jan 2015 16:41:08 +0900 Subject: [PATCH 64/77] Add include mbed_assert.h. --- .../mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h index c87a2aec1b..8bf5b45cba 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h @@ -16,6 +16,8 @@ #ifndef MBED_GPIO_OBJECT_H #define MBED_GPIO_OBJECT_H +#include "mbed_assert.h" + #ifdef __cplusplus extern "C" { #endif From 8013d158763c35807b893f24a1c532cb13b472fb Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Thu, 29 Jan 2015 16:41:35 +0900 Subject: [PATCH 65/77] Modify ticker driver to make consistent with Pull Reqest#839 and #864. timestamp_t type had been changed from uint64_t to uint32_t by Reqest#839 and #864. --- .../TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c | 51 ++++++++++++++++--- 1 file changed, 45 insertions(+), 6 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c index 03611d2451..c7eed18125 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c @@ -61,9 +61,12 @@ void us_ticker_init(void) { GIC_EnableIRQ(US_TICKER_TIMER_IRQn); } -uint32_t us_ticker_read() { +uint64_t us_ticker_read64() { uint32_t val; - uint64_t val64; + volatile uint64_t val64; + int check_irq_masked; + + check_irq_masked = __disable_irq(); if (!us_ticker_inited) us_ticker_init(); @@ -77,14 +80,50 @@ uint32_t us_ticker_read() { val64 = ((uint64_t)wrap_arround << 32) + val; /* clock to us */ - val = (uint32_t)(val64 / count_clock); - return val; + val64 = val64 / count_clock; + + if (!check_irq_masked) { + __enable_irq(); + } + + return val64; +} + +uint32_t us_ticker_read() { + return (uint32_t)us_ticker_read64(); } void us_ticker_set_interrupt(timestamp_t timestamp) { // set match value - timestamp = (timestamp_t)(timestamp * count_clock); - OSTM1CMP = (uint32_t)(timestamp & 0xffffffff); + volatile uint64_t set_cmp_val = 0; + uint64_t timestamp_tmp; + int64_t timestamp_req; + int64_t timestamp_comp; + uint64_t timestamp_now = us_ticker_read64(); + + /* calc compare mach timestamp */ + set_cmp_val = (timestamp_now & 0xFFFFFFFF00000000) + timestamp; + + timestamp_tmp = (uint64_t)timestamp; + timestamp_req = (int64_t)timestamp_tmp; + + timestamp_tmp = (uint64_t)(timestamp_now & 0x00000000FFFFFFFF); + timestamp_comp = (int64_t)timestamp_tmp; + + if (timestamp_req <= timestamp_comp + 1) { + if (((timestamp_req - timestamp_comp) <= 1) && ((timestamp_req - timestamp_comp) >= -10)) { + /* This event was in the past */ + us_ticker_irq_handler(); + return; + } else { + /* This event is wrap arround */ + set_cmp_val += 0x100000000; + } + } + + /* calc compare mach timestamp */ + set_cmp_val = set_cmp_val * count_clock; + OSTM1CMP = (uint32_t)(set_cmp_val & 0xffffffff); GIC_EnableIRQ(US_TICKER_TIMER_IRQn); } From 60f875ac8b30ea16efcdce920981d2aa65fb0710 Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Thu, 29 Jan 2015 16:41:56 +0900 Subject: [PATCH 66/77] Modify gpio api to make consistent with Merge branch 'PrzemekWirkus-pinology'. --- .../mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c index 14831bd688..4061325fd0 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c @@ -25,9 +25,9 @@ uint32_t gpio_set(PinName pin) { void gpio_init(gpio_t *obj, PinName pin) { int group ; + obj->pin = pin; if(pin == NC) return; - obj->pin = pin; obj->mask = gpio_set(pin); group = PINGROUP(pin); From 232821bb991c4b15f3c00a62d8a0f37900da39e2 Mon Sep 17 00:00:00 2001 From: Marcomissyou Date: Thu, 29 Jan 2015 16:00:36 +0800 Subject: [PATCH 67/77] add SWIO setting in mbed_overrides.c to substitute SWIO setting in system_nrf51822.c --- .../TARGET_MCU_NRF51822/system_nrf51822.c | 11 ----- .../TARGET_DELTA_DFCM_NNN40/mbed_overrides.c | 46 +++++++++++++++++++ 2 files changed, 46 insertions(+), 11 deletions(-) create mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c index e3f60b3b1b..88cbe35ba6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c @@ -83,17 +83,6 @@ void SystemInit(void) while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) { // Do nothing. } - - // Default SWIO setting, pull SWIO(p19) to low for turning antenna switch to BLE radiated path. -#ifdef TARGET_DELTA_DFCM_NNN40 - NRF_GPIO->PIN_CNF[19] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - - NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN19_Clear << GPIO_OUTCLR_PIN19_Pos); -#endif } static bool is_manual_peripheral_setup_needed(void) diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c new file mode 100644 index 0000000000..0a575b1b41 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c @@ -0,0 +1,46 @@ +/* mbed Microcontroller Library + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "cmsis.h" + +// This function is called after RAM initialization and before main. +void mbed_sdk_init() +{ + // Update the SystemCoreClock variable. + + // Default SWIO setting, pull SWIO(p19) to low for turning antenna switch to BLE radiated path. +#ifdef TARGET_DELTA_DFCM_NNN40 + NRF_GPIO->PIN_CNF[19] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + + NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN19_Clear << GPIO_OUTCLR_PIN19_Pos); + +#endif +} From ee9d3cf801ab0fa8e4816299aaff6a0291481c3e Mon Sep 17 00:00:00 2001 From: Marcomissyou Date: Thu, 29 Jan 2015 17:17:46 +0800 Subject: [PATCH 68/77] gcc_arm_delta_dfcm_nnn40.tmpl uvision4_deta_dfcm_nnn40.uvopt.tmpl uvision4_deta_dfcm_nnn40.uvproj.tmpl --- .../export/gcc_arm_delta_dfcm_nnn40.tmpl | 76 +++ .../uvision4_deta_dfcm_nnn40.uvopt.tmpl | 214 +++++++++ .../uvision4_deta_dfcm_nnn40.uvproj.tmpl | 431 ++++++++++++++++++ 3 files changed, 721 insertions(+) create mode 100644 workspace_tools/export/gcc_arm_delta_dfcm_nnn40.tmpl create mode 100644 workspace_tools/export/uvision4_deta_dfcm_nnn40.uvopt.tmpl create mode 100644 workspace_tools/export/uvision4_deta_dfcm_nnn40.uvproj.tmpl diff --git a/workspace_tools/export/gcc_arm_delta_dfcm_nnn40.tmpl b/workspace_tools/export/gcc_arm_delta_dfcm_nnn40.tmpl new file mode 100644 index 0000000000..48be881791 --- /dev/null +++ b/workspace_tools/export/gcc_arm_delta_dfcm_nnn40.tmpl @@ -0,0 +1,76 @@ +# This file was automagically generated by mbed.org. For more information, +# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded + +GCC_BIN = +PROJECT = {{name}} +OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %} +SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %} +INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %} +LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %} +LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %} +LINKER_SCRIPT = {{linker_script}} +SOFTDEVICE = mbed/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_0_0/s110_nrf51822_7.0.0_softdevice.hex + +############################################################################### +AS = $(GCC_BIN)arm-none-eabi-as +CC = $(GCC_BIN)arm-none-eabi-gcc +CPP = $(GCC_BIN)arm-none-eabi-g++ +LD = $(GCC_BIN)arm-none-eabi-gcc +OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy +OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump +SIZE = $(GCC_BIN)arm-none-eabi-size +SREC_CAT = srec_cat + +CPU = -mcpu=cortex-m0 -mthumb +CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer +CC_FLAGS += -MMD -MP +CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %} + +LD_FLAGS = $(CPU) -Wl,--gc-sections -Wl,--wrap=main --specs=nano.specs -u _printf_float -u _scanf_float +LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref +LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +ifeq ($(DEBUG), 1) + CC_FLAGS += -DDEBUG -O0 +else + CC_FLAGS += -DNDEBUG -Os +endif + +all: $(PROJECT).bin $(PROJECT).hex + +clean: + rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS) + +.s.o: + $(AS) $(CPU) -o $@ $< + +.c.o: + $(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $< + +.cpp.o: + $(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 -fno-rtti $(INCLUDE_PATHS) -o $@ $< + + +$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) + $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS) + $(SIZE) $@ + +$(PROJECT).bin: $(PROJECT).elf + @$(OBJCOPY) -O binary $< $@ + +$(PROJECT).hex: $(PROJECT).elf + @$(OBJCOPY) -O ihex $< $@ + +$(PROJECT).lst: $(PROJECT).elf + @$(OBJDUMP) -Sdh $< > $@ + +lst: $(PROJECT).lst + +size: + $(SIZE) $(PROJECT).elf + +DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d) +-include $(DEPS) + +merge: + $(SREC_CAT) $(SOFTDEVICE) -intel $(PROJECT).hex -intel -o combined.hex -intel --line-length=44 diff --git a/workspace_tools/export/uvision4_deta_dfcm_nnn40.uvopt.tmpl b/workspace_tools/export/uvision4_deta_dfcm_nnn40.uvopt.tmpl new file mode 100644 index 0000000000..2d8cbbceb0 --- /dev/null +++ b/workspace_tools/export/uvision4_deta_dfcm_nnn40.uvopt.tmpl @@ -0,0 +1,214 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + nRF51822AA + 0x4 + ARM-ADS + + 16000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 12 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + JL2CM3 + -U480204337 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO31 -FD20000000 -FC2000 -FN1 -FF0nrf51xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF51xxx$Flash\nrf51xxx.flm) + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51$Flash\nrf51xxx.flm)) + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + ULP2CM3 + -O2510 -S0 -C0 -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P128_48MHZ -FS00 -FL020000) + + + 0 + CMSIS_AGDI + -X"MBED CMSIS-DAP" -U107002011FE6E019E2180F91 -O718 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO31 -FD20000000 -FC2000 -FN1 -FF0nrf51xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF51xxx$Flash\nrf51xxx.flm) + + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + src + 1 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 1 + 2 + 0 + main.cpp + main.cpp + + + + diff --git a/workspace_tools/export/uvision4_deta_dfcm_nnn40.uvproj.tmpl b/workspace_tools/export/uvision4_deta_dfcm_nnn40.uvproj.tmpl new file mode 100644 index 0000000000..713e1412bd --- /dev/null +++ b/workspace_tools/export/uvision4_deta_dfcm_nnn40.uvproj.tmpl @@ -0,0 +1,431 @@ + + + + 1.1 + +
###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision
+ + + + nRF51822AA + 0x4 + ARM-ADS + + + nRF51xxx + Nordic Semiconductor + IROM(0x00000000,0x40000) IRAM(0x20000000,0x4000) CPUTYPE("Cortex-M0") CLOCK(16000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51xxx$Flash\nrf51xxx.flm)) + 0 + $$Device:nRF51xxx$Device\Include\nrf.h + + + + + + + + + + $$Device:nRF51xxx$SVD\nrf51.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + 0 + 1 + + + + + + + + + + + + + + BIN\UL2CM3.DLL + + + + + 1 + 0 + 0 + 0 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + {%if file.type == "1" %} + + + + + --c99 + + + + + {% endif %} + + {% endfor %} + + + {% endfor %} + + + + + From b2cc8227f1c6c7fc7239b7351292f415e2626cba Mon Sep 17 00:00:00 2001 From: Wim Date: Thu, 29 Jan 2015 20:30:43 +0100 Subject: [PATCH 69/77] Update system_LPC8xx.c Fix and enable the PLL for the LPC812. Removed unnecessary comments --- .../TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c index 61fe203524..c96d6c446b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c @@ -102,7 +102,7 @@ */ #define CLOCK_SETUP 1 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal: -//WH Fixed to use PLL +//Fixed to use PLL #if (CLOCK_SETUP == 1) //use PLL for IRC #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 @@ -121,7 +121,6 @@ #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz #endif -//WH /* //-------- <<< end of configuration section >>> ------------------------------ @@ -250,11 +249,10 @@ /*---------------------------------------------------------------------------- Clock Variable definitions *----------------------------------------------------------------------------*/ -//WH Added MainClock uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ -//WH Replaced SystemCoreClock with MainClock +//Replaced SystemCoreClock with MainClock /*---------------------------------------------------------------------------- Clock functions *----------------------------------------------------------------------------*/ @@ -326,7 +324,6 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV; } -//WH /** * Initialize the system From 898b4ab772bbec977e99df228e79758986f9feee Mon Sep 17 00:00:00 2001 From: Wim Date: Thu, 29 Jan 2015 20:32:08 +0100 Subject: [PATCH 70/77] Update system_LPC8xx.h Fix and enable the PLL for the LPC812. Removed unnecessary comments --- .../mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h | 1 - 1 file changed, 1 deletion(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h index c392f2a4a7..e95975d0ad 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h @@ -30,7 +30,6 @@ extern "C" { #include -//WH extern uint32_t MainClock; /*!< Main Clock Frequency */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ From d03329fb3fe952546e13bf7085b797dc485a4dfe Mon Sep 17 00:00:00 2001 From: Wim Date: Thu, 29 Jan 2015 20:33:22 +0100 Subject: [PATCH 71/77] Update serial_api.c Fix and enable the PLL for the LPC812. Removed unnecessary comments --- .../mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c index b1964f40df..19473496ec 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c @@ -118,7 +118,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { LPC_SYSCON->PRESETCTRL &= ~(0x1 << (3 + uart_n)); LPC_SYSCON->PRESETCTRL |= (0x1 << (3 + uart_n)); -//WH + // Derive UART Clock from MainClock UARTSysClk = MainClock / LPC_SYSCON->UARTCLKDIV; // set default baud rate and format From 9cbe36213c2ae31ae8fdd90850dc8161f43798f7 Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Fri, 30 Jan 2015 11:17:22 +0900 Subject: [PATCH 72/77] Modify A/D convert time. --- .../hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c index eebc3c0507..80ebd767ea 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c @@ -54,11 +54,11 @@ void analogin_init(analogin_t *obj, PinName pin) { CPGSTBCR3 &= ~(1 << 1); CPGSTBCR6 &= ~(1 << 7); - // 15: ADF 14: ADIE 13: ADST, [12:9] TRGS..0 - // [8:6] CKS 000 :: 256tclk - // [5:3] MDS 000 :: single mode - // [2:0] CH 000 :: AN0 - ADCADCSR = 0x0000; + // 15: ADF 14: ADIE 13: ADST, [12:9] TRGS..0 + // [8:6] CKS 010 :: 340tclk + // [5:3] MDS 000 :: single mode + // [2:0] CH 000 :: AN0 + ADCADCSR = 0x0080; pinmap_pinout(pin, PinMap_ADC); } From 64465b68adbdb446cb89ac0d5f2ad21ef110fd3f Mon Sep 17 00:00:00 2001 From: Marcomissyou Date: Fri, 30 Jan 2015 15:05:03 +0800 Subject: [PATCH 73/77] extend year and add toolchain system_nrf51822.c, PinNames.h,device.h,mbed_overrides.c,targets.py --- .../TARGET_MCU_NRF51822/system_nrf51822.c | 2 +- .../TARGET_DELTA_DFCM_NNN40/PinNames.h | 2 +- .../TARGET_DELTA_DFCM_NNN40/device.h | 2 +- .../TARGET_DELTA_DFCM_NNN40/mbed_overrides.c | 28 +------------------ workspace_tools/targets.py | 4 ++- 5 files changed, 7 insertions(+), 31 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c index 88cbe35ba6..74271f3a51 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor. + * Copyright (c) 2015 Nordic Semiconductor. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h index 1acb4d2a0b..c6c288ec62 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor + * Copyright (c) 2015 Nordic Semiconductor * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h index fd66610a0c..21442bcf3a 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c index 0a575b1b41..993cec1925 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c @@ -1,37 +1,11 @@ /* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * Copyright (c) 2015, Cyntec */ #include "cmsis.h" // This function is called after RAM initialization and before main. void mbed_sdk_init() { - // Update the SystemCoreClock variable. - // Default SWIO setting, pull SWIO(p19) to low for turning antenna switch to BLE radiated path. #ifdef TARGET_DELTA_DFCM_NNN40 NRF_GPIO->PIN_CNF[19] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 953f07343d..0712d9f739 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -1,6 +1,6 @@ """ mbed SDK -Copyright (c) 2011-2013 ARM Limited +Copyright (c) 2011-2015 ARM Limited Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -848,6 +848,7 @@ class DELTA_DFCM_NNN40(NRF51822): NRF51822.__init__(self) self.core = "Cortex-M0" self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] + self.supported_toolchains = ["ARM", "GCC_ARM"] self.macros = ['TARGET_NRF51822'] class DELTA_DFCM_NNN40_OTA(NRF51822): @@ -855,6 +856,7 @@ class DELTA_DFCM_NNN40_OTA(NRF51822): NRF51822.__init__(self) self.core = "Cortex-M0" self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'DELTA_DFCM_NNN40'] + self.supported_toolchains = ["ARM", "GCC_ARM"] self.MERGE_SOFT_DEVICE = False From 1b4c6f8a7fa283b0ad3057ee816681ef7207776e Mon Sep 17 00:00:00 2001 From: Marcomissyou Date: Fri, 30 Jan 2015 15:22:19 +0800 Subject: [PATCH 74/77] add target NNN40 in uvision4.py and gccarm.py --- workspace_tools/export/gccarm.py | 1 + workspace_tools/export/uvision4.py | 1 + 2 files changed, 2 insertions(+) diff --git a/workspace_tools/export/gccarm.py b/workspace_tools/export/gccarm.py index 82a37a3245..a5f4b21bd5 100644 --- a/workspace_tools/export/gccarm.py +++ b/workspace_tools/export/gccarm.py @@ -74,6 +74,7 @@ class GccArm(Exporter): 'NRF51_DONGLE', 'BLE_SMURFS', 'DISCO_F401VC', + 'DELTA_DFCM_NNN40', ] DOT_IN_RELATIVE_PATH = True diff --git a/workspace_tools/export/uvision4.py b/workspace_tools/export/uvision4.py index 29cfd37c08..452853a87d 100644 --- a/workspace_tools/export/uvision4.py +++ b/workspace_tools/export/uvision4.py @@ -68,6 +68,7 @@ class Uvision4(Exporter): 'NRF51_DONGLE', 'BLE_SMURFS', 'LPC11U37H_401', + 'DELTA_DFCM_NNN40', ] USING_MICROLIB = [ From 69a98d743f481228b4d0e85808245c4660398d8c Mon Sep 17 00:00:00 2001 From: Marcomissyou Date: Fri, 30 Jan 2015 15:34:24 +0800 Subject: [PATCH 75/77] correct filename uvision4_delta_dfcm_nnn40.uvproj.tmpl and uvision4_delta_dfcm_nnn40.uvopt.tmpl --- ...dfcm_nnn40.uvopt.tmpl => uvision4_delta_dfcm_nnn40.uvopt.tmpl} | 0 ...cm_nnn40.uvproj.tmpl => uvision4_delta_dfcm_nnn40.uvproj.tmpl} | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename workspace_tools/export/{uvision4_deta_dfcm_nnn40.uvopt.tmpl => uvision4_delta_dfcm_nnn40.uvopt.tmpl} (100%) rename workspace_tools/export/{uvision4_deta_dfcm_nnn40.uvproj.tmpl => uvision4_delta_dfcm_nnn40.uvproj.tmpl} (100%) diff --git a/workspace_tools/export/uvision4_deta_dfcm_nnn40.uvopt.tmpl b/workspace_tools/export/uvision4_delta_dfcm_nnn40.uvopt.tmpl similarity index 100% rename from workspace_tools/export/uvision4_deta_dfcm_nnn40.uvopt.tmpl rename to workspace_tools/export/uvision4_delta_dfcm_nnn40.uvopt.tmpl diff --git a/workspace_tools/export/uvision4_deta_dfcm_nnn40.uvproj.tmpl b/workspace_tools/export/uvision4_delta_dfcm_nnn40.uvproj.tmpl similarity index 100% rename from workspace_tools/export/uvision4_deta_dfcm_nnn40.uvproj.tmpl rename to workspace_tools/export/uvision4_delta_dfcm_nnn40.uvproj.tmpl From f2a04daeaa271d182d6a9527bc399cb8d2b3578e Mon Sep 17 00:00:00 2001 From: Marcomissyou Date: Fri, 30 Jan 2015 15:39:11 +0800 Subject: [PATCH 76/77] remove self.supported_toolchains description --- workspace_tools/targets.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 0712d9f739..eefd1bf419 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -848,7 +848,6 @@ class DELTA_DFCM_NNN40(NRF51822): NRF51822.__init__(self) self.core = "Cortex-M0" self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] - self.supported_toolchains = ["ARM", "GCC_ARM"] self.macros = ['TARGET_NRF51822'] class DELTA_DFCM_NNN40_OTA(NRF51822): @@ -856,7 +855,6 @@ class DELTA_DFCM_NNN40_OTA(NRF51822): NRF51822.__init__(self) self.core = "Cortex-M0" self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'DELTA_DFCM_NNN40'] - self.supported_toolchains = ["ARM", "GCC_ARM"] self.MERGE_SOFT_DEVICE = False From 5bd982c17184ae6613289b13f3cfa2db0d1ecd99 Mon Sep 17 00:00:00 2001 From: 0xc0170 Date: Mon, 2 Feb 2015 15:22:55 +0000 Subject: [PATCH 77/77] Targets - gpio_is_connected() for STM targets where it was not implemented --- .../hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_object.h | 4 ++++ .../hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h | 5 +++++ .../hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h | 4 ++++ .../hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_object.h | 4 ++++ .../hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h | 4 ++++ .../hal/TARGET_STM/TARGET_NUCLEO_L053R8/gpio_object.h | 4 ++++ .../hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h | 4 ++++ .../targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_object.h | 4 ++++ .../targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_object.h | 4 ++++ 9 files changed, 37 insertions(+) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_object.h index fdc6112cb6..684d968757 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h index fdc6112cb6..e49e172b72 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h @@ -64,6 +64,11 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h index 5569efc465..bebf7db0c7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_object.h index 5569efc465..bebf7db0c7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h index 5569efc465..bebf7db0c7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/gpio_object.h index fdc6112cb6..684d968757 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h index fdc6112cb6..684d968757 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_object.h index 75013b4188..4391135e3b 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_object.h @@ -62,6 +62,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_object.h index fcf499289e..f43f2f8530 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_object.h @@ -46,6 +46,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif