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Merge pull request #4351 from jeromecoutant/PULL_REQUEST_CUBE_UPDATE_L4_V1.8.0 

STM32L4 cube update from v1.5.0 to v1.8.0
pull/4332/merge
Sam Grove 2017-05-26 16:58:37 -05:00 committed by GitHub
parent 73d1745e19 5dc49b7d6c
commit 2500ab03f2
198 changed files with 59895 additions and 40047 deletions
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6
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_stm32l4xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32l4xx.c
* @author MCD Application Team
* @version V1.1.1
* @date 29-April-2016
* @version V1.3.1
* @date 21-April-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
*
* This file provides two functions and one global variable to be called from
@ -45,7 +45,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h
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@ -44,10 +44,10 @@
#define TIM_MST TIM2
#define TIM_MST_IRQ TIM2_IRQn
#define TIM_MST_RCC __TIM2_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM2_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

17305
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h
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27
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx.h
* @author MCD Application Team
* @version V1.1.1
* @date 29-April-2016
* @version V1.3.1
* @date 21-April-2017
* @brief CMSIS STM32L4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -76,17 +76,24 @@
*/
#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
!defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx)
!defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
!defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
!defined (STM32L496xx) && !defined (STM32L4A6xx)
/* #define STM32L431xx */ /*!< STM32L431xx Devices */
#define STM32L432xx /*!< STM32L432xx Devices */
/* #define STM32L433xx */ /*!< STM32L433xx Devices */
/* #define STM32L442xx */ /*!< STM32L442xx Devices */
/* #define STM32L443xx */ /*!< STM32L443xx Devices */
/* #define STM32L451xx */ /*!< STM32L451xx Devices */
/* #define STM32L452xx */ /*!< STM32L452xx Devices */
/* #define STM32L462xx */ /*!< STM32L462xx Devices */
/* #define STM32L471xx */ /*!< STM32L471xx Devices */
/* #define STM32L475xx */ /*!< STM32L475xx Devices */
/* #define STM32L476xx */ /*!< STM32L476xx Devices */
/* #define STM32L485xx */ /*!< STM32L485xx Devices */
/* #define STM32L486xx */ /*!< STM32L486xx Devices */
/* #define STM32L496xx */ /*!< STM32L496xx Devices */
/* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -102,10 +109,10 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.1.1
* @brief CMSIS Device version number V1.3.1
*/
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
@ -151,14 +158,6 @@
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S9xx)
#include "stm32l4s9xx.h"
#else
#error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
#endif

6
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h
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@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32l4xx.h
* @author MCD Application Team
* @version V1.1.1
* @date 29-April-2016
* @version V1.3.1
* @date 21-April-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_stm32l4xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32l4xx.c
* @author MCD Application Team
* @version V1.1.1
* @date 29-April-2016
* @version V1.3.1
* @date 21-April-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
*
* This file provides two functions and one global variable to be called from
@ -43,7 +43,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_stm32l4xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32l4xx.c
* @author MCD Application Team
* @version V1.1.1
* @date 29-April-2016
* @version V1.3.1
* @date 21-April-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
*
* This file provides two functions and one global variable to be called from
@ -43,7 +43,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h
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@ -44,10 +44,10 @@
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

20114
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l476xx.h
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31
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l4xx.h
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@ -2,23 +2,23 @@
******************************************************************************
* @file stm32l4xx.h
* @author MCD Application Team
* @version V1.1.1
* @date 29-April-2016
* @version V1.3.1
* @date 21-April-2017
* @brief CMSIS STM32L4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32L4xx device used in the target application
* - To use or not the peripheral<EFBFBD>s drivers in application code(i.e.
* code will be based on direct access to peripheral<EFBFBD>s registers
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -76,17 +76,24 @@
*/
#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
!defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx)
!defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
!defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
!defined (STM32L496xx) && !defined (STM32L4A6xx)
/* #define STM32L431xx */ /*!< STM32L431xx Devices */
/* #define STM32L432xx */ /*!< STM32L432xx Devices */
/* #define STM32L433xx */ /*!< STM32L433xx Devices */
/* #define STM32L442xx */ /*!< STM32L442xx Devices */
/* #define STM32L443xx */ /*!< STM32L443xx Devices */
/* #define STM32L451xx */ /*!< STM32L451xx Devices */
/* #define STM32L452xx */ /*!< STM32L452xx Devices */
/* #define STM32L462xx */ /*!< STM32L462xx Devices */
/* #define STM32L471xx */ /*!< STM32L471xx Devices */
/* #define STM32L475xx */ /*!< STM32L475xx Devices */
#define STM32L476xx /*!< STM32L476xx Devices */
/* #define STM32L485xx */ /*!< STM32L485xx Devices */
/* #define STM32L486xx */ /*!< STM32L486xx Devices */
/* #define STM32L496xx */ /*!< STM32L496xx Devices */
/* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -102,10 +109,10 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.1.1
* @brief CMSIS Device version number V1.3.1
*/
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
@ -151,14 +158,6 @@
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S9xx)
#include "stm32l4s9xx.h"
#else
#error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
#endif

8
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/system_stm32l4xx.h
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@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32l4xx.h
* @author MCD Application Team
* @version V1.1.1
* @date 29-April-2016
* @version V1.3.1
* @date 21-April-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -75,7 +75,7 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */

6
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_stm32l4xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32l4xx.c
* @author MCD Application Team
* @version V1.1.1
* @date 29-April-2016
* @version V1.3.1
* @date 21-April-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
*
* This file provides two functions and one global variable to be called from
@ -43,7 +43,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h
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@ -44,10 +44,10 @@
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

20378
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l486xx.h
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23
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l4xx.h
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@ -2,23 +2,23 @@
******************************************************************************
* @file stm32l4xx.h
* @author MCD Application Team
* @version V1.1.1
* @date 29-April-2016
* @version V1.3.1
* @date 21-April-2017
* @brief CMSIS STM32L4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32L4xx device used in the target application
* - To use or not the peripheral<EFBFBD>s drivers in application code(i.e.
* code will be based on direct access to peripheral<EFBFBD>s registers
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -76,17 +76,24 @@
*/
#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
!defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx)
!defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
!defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
!defined (STM32L496xx) && !defined (STM32L4A6xx)
/* #define STM32L431xx */ /*!< STM32L431xx Devices */
/* #define STM32L432xx */ /*!< STM32L432xx Devices */
/* #define STM32L433xx */ /*!< STM32L433xx Devices */
/* #define STM32L442xx */ /*!< STM32L442xx Devices */
/* #define STM32L443xx */ /*!< STM32L443xx Devices */
/* #define STM32L451xx */ /*!< STM32L451xx Devices */
/* #define STM32L452xx */ /*!< STM32L452xx Devices */
/* #define STM32L462xx */ /*!< STM32L462xx Devices */
/* #define STM32L471xx */ /*!< STM32L471xx Devices */
/* #define STM32L475xx */ /*!< STM32L475xx Devices */
/* #define STM32L476xx */ /*!< STM32L476xx Devices */
/* #define STM32L485xx */ /*!< STM32L485xx Devices */
#define STM32L486xx /*!< STM32L486xx Devices */
/* #define STM32L496xx */ /*!< STM32L496xx Devices */
/* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -102,10 +109,10 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.1.1
* @brief CMSIS Device version number V1.3.1
*/
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\

6
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/system_stm32l4xx.h
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@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32l4xx.h
* @author MCD Application Team
* @version V1.1.1
* @date 29-April-2016
* @version V1.3.1
* @date 21-April-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

79
targets/TARGET_STM/TARGET_STM32L4/device/Release_Notes_stm32l4xx_hal.html
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178
targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h
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@ -2,14 +2,14 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -138,6 +138,7 @@
#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
@ -150,6 +151,9 @@
#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
@ -160,8 +164,16 @@
#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
#if defined(STM32L0)
/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
/* to the second dedicated IO (only for COMP2). */
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
#else
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
#endif
#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
@ -229,9 +241,9 @@
#define DAC1_CHANNEL_1 DAC_CHANNEL_1
#define DAC1_CHANNEL_2 DAC_CHANNEL_2
#define DAC2_CHANNEL_1 DAC_CHANNEL_1
#define DAC_WAVE_NONE ((uint32_t)0x00000000U)
#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
#define DAC_WAVE_NONE 0x00000000U
#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
@ -344,6 +356,7 @@
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
/**
* @}
*/
@ -841,6 +854,8 @@
#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
#define __DIV_LPUART UART_DIV_LPUART
#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
@ -902,45 +917,48 @@
#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
#define ETH_MMCCR ((uint32_t)0x00000100U)
#define ETH_MMCRIR ((uint32_t)0x00000104U)
#define ETH_MMCTIR ((uint32_t)0x00000108U)
#define ETH_MMCRIMR ((uint32_t)0x0000010CU)
#define ETH_MMCTIMR ((uint32_t)0x00000110U)
#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
#define ETH_MMCCR 0x00000100U
#define ETH_MMCRIR 0x00000104U
#define ETH_MMCTIR 0x00000108U
#define ETH_MMCRIMR 0x0000010CU
#define ETH_MMCTIMR 0x00000110U
#define ETH_MMCTGFSCCR 0x0000014CU
#define ETH_MMCTGFMSCCR 0x00000150U
#define ETH_MMCTGFCR 0x00000168U
#define ETH_MMCRFCECR 0x00000194U
#define ETH_MMCRFAECR 0x00000198U
#define ETH_MMCRGUFCR 0x000001C4U
#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
#endif
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
/**
* @}
@ -962,7 +980,7 @@
* @}
*/
#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{
@ -987,7 +1005,7 @@
/**
* @}
*/
#endif /* STM32L4xx || STM32F7*/
#endif /* STM32L4 || STM32F7*/
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
@ -1213,6 +1231,7 @@
#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE
#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
@ -2213,26 +2232,26 @@
#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
@ -2634,10 +2653,22 @@
#define RCC_IT_HSI14 RCC_IT_HSI14RDY
#if defined(STM32L0)
#define RCC_IT_LSECSS RCC_IT_CSSLSE
#define RCC_IT_CSS RCC_IT_CSSHSE
#endif
#define RCC_IT_CSSLSE RCC_IT_LSECSS
#define RCC_IT_CSSHSE RCC_IT_CSS
#define RCC_PLLMUL_3 RCC_PLL_MUL3
#define RCC_PLLMUL_4 RCC_PLL_MUL4
#define RCC_PLLMUL_6 RCC_PLL_MUL6
#define RCC_PLLMUL_8 RCC_PLL_MUL8
#define RCC_PLLMUL_12 RCC_PLL_MUL12
#define RCC_PLLMUL_16 RCC_PLL_MUL16
#define RCC_PLLMUL_24 RCC_PLL_MUL24
#define RCC_PLLMUL_32 RCC_PLL_MUL32
#define RCC_PLLMUL_48 RCC_PLL_MUL48
#define RCC_PLLDIV_2 RCC_PLL_DIV2
#define RCC_PLLDIV_3 RCC_PLL_DIV3
#define RCC_PLLDIV_4 RCC_PLL_DIV4
#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
@ -2754,11 +2785,14 @@
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
#define DfsdmClockSelection Dfsdm1ClockSelection
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
/**
* @}
*/

53
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@ -23,7 +23,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -67,10 +67,10 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
* @brief STM32L4xx HAL Driver version number V1.5.1
* @brief STM32L4xx HAL Driver version number V1.7.1
*/
#define __STM32L4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L4xx_HAL_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
#define __STM32L4xx_HAL_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L4xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32L4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L4xx_HAL_VERSION ((__STM32L4xx_HAL_VERSION_MAIN << 24)\
@ -318,7 +318,8 @@ __weak uint32_t HAL_GetTick(void)
}
/**
* @brief Provide accurate delay (in milliseconds) based on variable incremented.
* @brief This function provides minimum delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
* is incremented.
@ -329,9 +330,16 @@ __weak uint32_t HAL_GetTick(void)
*/
__weak void HAL_Delay(uint32_t Delay)
{
uint32_t tickstart = 0;
tickstart = HAL_GetTick();
while((HAL_GetTick() - tickstart) < Delay)
uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay;
/* Add a period to guaranty minimum wait */
if (wait < HAL_MAX_DELAY)
{
wait++;
}
while((HAL_GetTick() - tickstart) < wait)
{
}
}
@ -395,6 +403,33 @@ uint32_t HAL_GetDEVID(void)
return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
}
/**
* @brief Return the first word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw0(void)
{
return(READ_REG(*((uint32_t *)UID_BASE)));
}
/**
* @brief Return the second word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw1(void)
{
return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
}
/**
* @brief Return the third word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw2(void)
{
return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
}
/**
* @}
*/

100
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h
View File

@ -2,14 +2,14 @@
******************************************************************************
* @file stm32l4xx_hal.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -66,10 +66,15 @@
*/
#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000)
#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
#define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx */
#define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
#define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)
/**
@ -90,7 +95,7 @@
* @}
*/
/** @defgroup SYSCFG_SRAM2WRP SRAM2 Write protection
/** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31)
* @{
*/
#define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */
@ -109,6 +114,7 @@
#define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
#define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
#define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
#if defined(SYSCFG_SWPR_PAGE31)
#define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
#define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
#define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
@ -125,11 +131,54 @@
#define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
#define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
#define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
#endif /* SYSCFG_SWPR_PAGE31 */
/**
* @}
*/
#if defined(SYSCFG_SWPR2_PAGE63)
/** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63)
* @{
*/
#define SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */
#define SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */
#define SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */
#define SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */
#define SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */
#define SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */
#define SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */
#define SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */
#define SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */
#define SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */
#define SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */
#define SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */
#define SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */
#define SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */
#define SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */
#define SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */
#define SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */
#define SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */
#define SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */
#define SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */
#define SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */
#define SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */
#define SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */
#define SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */
#define SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */
#define SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */
#define SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */
#define SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */
#define SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */
#define SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */
#define SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */
#define SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */
/**
* @}
*/
#endif /* SYSCFG_SWPR2_PAGE63 */
#if defined(VREFBUF)
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
* @{
@ -254,11 +303,21 @@
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#endif
#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP)
#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP)
#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)
#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
@ -314,11 +373,15 @@
*/
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx */
/** @brief QUADSPI mapped at 0x00000000.
*/
@ -338,14 +401,24 @@
*/
#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
/** @brief SRAM2 page write protection enable macro
* @param __SRAM2WRP__: This parameter can be a value of @ref SYSCFG_SRAM2WRP
* @note write protection can only be disabled by a system reset
/** @brief SRAM2 page 0 to 31 write protection enable macro
* @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP
* @note Write protection can only be disabled by a system reset
*/
#define __HAL_SYSCFG_SRAM2_WRP_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\
}while(0)
#if defined(SYSCFG_SWPR2_PAGE63)
/** @brief SRAM2 page 32 to 63 write protection enable macro
* @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63
* @note Write protection can only be disabled by a system reset
*/
#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\
}while(0)
#endif /* SYSCFG_SWPR2_PAGE63 */
/** @brief SRAM2 page write protection unlock prior to erase
* @note Writing a wrong key reactivates the write protection
*/
@ -509,6 +582,9 @@ void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
uint32_t HAL_GetUIDw0(void);
uint32_t HAL_GetUIDw1(void);
uint32_t HAL_GetUIDw2(void);
/**
* @}

1131
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c
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537
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h
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@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_adc.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -36,8 +36,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_ADC_H
#define __STM32L4xx_ADC_H
#ifndef __STM32L4xx_HAL_ADC_H
#define __STM32L4xx_HAL_ADC_H
#ifdef __cplusplus
extern "C" {
@ -45,35 +45,34 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Types ADC Exported Types
* @{
*/
*/
/**
* @brief ADC Regular Conversion Oversampling structure definition
* @brief ADC group regular oversampling structure definition
*/
typedef struct
{
uint32_t Ratio; /*!< Configures the oversampling ratio.
This parameter can be a value of @ref ADCEx_Oversampling_Ratio */
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
This parameter can be a value of @ref ADCEx_Right_Bit_Shift */
uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
This parameter can be a value of @ref ADCEx_Triggered_Oversampling_Mode */
uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.
The oversampling is either temporary stopped or reset upon an injected
sequence interruption.
@ -81,103 +80,160 @@ typedef struct
is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
(the oversampling buffer is zeroed during injection sequence).
This parameter can be a value of @ref ADCEx_Regular_Oversampling_Mode */
}ADC_OversamplingTypeDef;
/** @defgroup ADC_States ADC States
* @{
*/
/**
* @brief HAL ADC state machine: ADC State bitfield definition
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy because of an internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
/* States of ADC regular group */
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A regular conversion is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on, multimode ADC master control
when multimode feature available) */
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Regular conversion data available */
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< End Of Sampling flag raised */
/* States of ADC injected group */
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< An injected conversion is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on, multimode ADC master control
when multimode feature available) */
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Injected conversion data available */
#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Injected queue overflow occurrence */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of Analog Watchdog 1 */
#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Out-of-window occurrence of Analog Watchdog 2 */
#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Out-of-window occurrence of Analog Watchdog 3 */
/* States of ADC multi-mode when feature available */
#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
}ADC_OversamplingTypeDef;
/**
* @}
*/
/**
* @brief ADC Injection Configuration
* @brief Structure definition of ADC instance and ADC group regular.
* @note Parameters of this structure are shared within 2 scopes:
* - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
* ScanConvMode, EOCSelection, LowPowerAutoWait.
* - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,
* ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
* @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled
* - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
* - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter
* (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each
HAL_ADCEx_InjectedConfigChannel() call to finally initialize
JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
uint32_t ChannelCount; /*!< Number of channels in the injected sequence */
}ADC_InjectionConfigTypeDef;
uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from System/PLLSAI1/PLLSAI2 clocks) and clock prescaler.
This parameter can be a value of @ref ADC_ClockPrescaler.
Note: The clock is common for all the ADCs.
Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
Note: In case of usage of the ADC dedicated PLL clock, it must be preliminarily enabled at RCC top level.
Note: This parameter can be modified only if all ADCs are disabled. */
uint32_t Resolution; /*!< Configure the ADC resolution.
This parameter can be a value of @ref ADC_Resolution */
uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left).
Refer to reference manual for alignments formats versus resolutions.
This parameter can be a value of @ref ADC_Data_align */
uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected.
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer).
Scan direction is upward: from rank 1 to rank 'n'.
This parameter can be a value of @ref ADC_Scan_mode */
/**
* @brief Structure definition of ADC channel for regular group
* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned by ADC state.
uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
This parameter can be a value of @ref ADC_EOCSelection. */
uint32_t LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,
using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
for low frequency applications.
This parameter can be set to ENABLE or DISABLE.
Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
to free the IRQ vector sequencer.
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
(in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
uint32_t ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
after the first ADC conversion start trigger occurred (software start or external trigger).
This parameter can be set to ENABLE or DISABLE. */
uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer.
To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 16.
Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without
continuous mode or external trigger that could launch a conversion). */
uint32_t DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
(main sequence subdivided in successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE. */
uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
This parameter can be a value of @ref ADC_regular_external_trigger_source.
Caution: external trigger source is common to all ADC instances. */
uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_regular_external_trigger_edge */
uint32_t DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
or in continuous mode (DMA transfer unlimited, whatever number of conversions).
This parameter can be set to ENABLE or DISABLE.
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
This parameter applies to ADC group regular only.
This parameter can be a value of @ref ADC_Overrun.
Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
Note: Error reporting with respect to the conversion mode:
- Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
- Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
uint32_t OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */
ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
uint32_t DFSDMConfig; /*!< Specify whether ADC conversion data is sent directly to DFSDM.
This parameter can be a value of @ref ADCEx_DFSDM_Mode_Configuration.
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
}ADC_InitTypeDef;
/**
* @brief Structure definition of ADC channel for regular group
* @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
* - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
* - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter
* (which fulfills the ADC state condition) on the fly).
*/
typedef struct
typedef struct
{
uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
This parameter can be a value of @ref ADC_channels
Note: Depending on devices and ADC instances, some channels may not be available. Refer to device DataSheet for channels availability. */
uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
This parameter can be a value of @ref ADCEx_regular_rank
Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
uint32_t Rank; /*!< Specify the rank in the regular group sequencer.
This parameter can be a value of @ref ADC_regular_rank
Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
the new channel setting (or parameter number of conversions adjusted) */
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
Unit: ADC clock cycles
Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
Conversion time is the addition of sampling time and processing time
(12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
This parameter can be a value of @ref ADC_sampling_times
Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
Caution: This parameter applies to a channel that can be used into regular and/or injected group.
It overwrites the last setting.
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
sampling time constraints must be respected (sampling time can be adjusted with respect to the ADC clock frequency and sampling time setting)
Refer to device DataSheet for timings values. */
uint32_t SingleDiff; /*!< Selection of single-ended or differential input.
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
Refer to device datasheet for timings values. */
uint32_t SingleDiff; /*!< Select single-ended or differential input.
In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
This parameter must be a value of @ref ADCEx_SingleDifferential
@ -186,12 +242,14 @@ typedef struct
Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
of another parameter update on the fly) */
uint32_t OffsetNumber; /*!< Selects the offset number
uint32_t OffsetNumber; /*!< Select the offset number
This parameter can be a value of @ref ADCEx_OffsetNumber
Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
uint32_t Offset; /*!< Defines the offset to be subtracted from the raw converted data.
uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data.
Offset value must be a positive number.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
0x3FF, 0xFF or 0x3F respectively.
@ -199,45 +257,100 @@ typedef struct
without continuous mode or external trigger that could launch a conversion). */
}ADC_ChannelConfTypeDef;
/**
/**
* @brief Structure definition of ADC analog watchdog
* @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned by ADC state.
* ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular and injected groups.
* @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
* ADC state can be either:
* ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.
*/
typedef struct
{
uint32_t WatchdogNumber; /*!< Selects which ADC analog watchdog is applied to the selected channel.
uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
This parameter can be a value of @ref ADCEx_analog_watchdog_number. */
uint32_t WatchdogMode; /*!< For Analog Watchdog 1: Configures the ADC analog watchdog mode: single channel/overall group of channels, regular/injected group.
For Analog Watchdog 2 and 3: There is no configuration for overall group of channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset
uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel/all channels, ADC groups regular and/or injected.
For Analog Watchdog 2 and 3: There is no configuration for all channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset
channels group programmed with parameter 'Channel', set any other value to program the channel(s) to be monitored.
This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
For Analog Watchdog 2 and 3: Several channels can be monitored (successive calls of HAL_ADC_AnalogWDGConfig() must be done, one for each channel.
Channels group reset can be done by setting WatchdogMode to 'ADC_ANALOGWATCHDOG_NONE').
For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
This parameter can be a value of @ref ADC_channels. */
uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
0x3FF, 0xFF or 0x3F respectively.
uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
}ADC_AnalogWDGConfTypeDef;
/** @defgroup ADC_States ADC States
* @{
*/
/**
* @brief HAL ADC state machine: ADC states definition (bitfields)
* @note ADC state machine is managed by bitfields, state must be compared
* with bit by bit.
* For example:
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy due to an internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on this STM32 serie: End Of Sampling flag raised */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Injected queue overflow occurrence */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Out-of-window occurrence of ADC analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADC_Exported_Constants ADC Exported Constants
@ -247,17 +360,17 @@ typedef struct
/** @defgroup ADC_Error_Code ADC Error Code
* @{
*/
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: problem of
clocking, enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
#define HAL_ADC_ERROR_JQOVF ((uint32_t)0x08) /*!< Injected context queue overflow error */
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error (problem of clocking,
enable/disable, erroneous state, ...) */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
#define HAL_ADC_ERROR_JQOVF ((uint32_t)0x08) /*!< Injected context queue overflow error */
/**
* @}
*/
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
/** @defgroup ADC_ClockPrescaler ADC clock source and clock prescaler
* @{
*/
#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided */
@ -283,20 +396,19 @@ typedef struct
/**
* @}
*/
/** @defgroup ADC_Resolution ADC Resolution
* @{
*/
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR_RES_0) /*!< ADC 10-bit resolution */
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_1) /*!< ADC 8-bit resolution */
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR_RES) /*!< ADC 6-bit resolution */
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_1) /*!< ADC 8-bit resolution */
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR_RES) /*!< ADC 6-bit resolution */
/**
* @}
*/
/** @defgroup ADC_Data_align ADC Data Alignment
/** @defgroup ADC_Data_align ADC conversion data alignment
* @{
*/
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) /*!< Data right alignment */
@ -305,7 +417,7 @@ typedef struct
* @}
*/
/** @defgroup ADC_Scan_mode ADC Scan Mode
/** @defgroup ADC_Scan_mode ADC sequencer scan mode
* @{
*/
#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */
@ -314,22 +426,10 @@ typedef struct
* @}
*/
/** @defgroup ADC_Regular_External_Trigger_Source_Edge ADC External Trigger Source Edge for Regular Group
/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
* @{
*/
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) /*!< Regular conversions hardware trigger detection disabled */
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0) /*!< Regular conversions hardware trigger detection on the rising edge */
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1) /*!< Regular conversions hardware trigger detection on the falling edge */
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN) /*!< Regular conversions hardware trigger detection on both the rising and falling edges */
/**
* @}
*/
/** @defgroup ADC_Regular_External_Trigger_Source ADC External Trigger Source for Regular Group
* @{
*/
/* External triggers of ADC regular group */
/* ADC group regular trigger sources for all ADC instances */
#define ADC_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000) /*!< Event 0 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) /*!< Event 1 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) /*!< Event 2 triggers regular group conversion start */
@ -346,18 +446,27 @@ typedef struct
#define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) /*!< Event 13 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) /*!< Event 14 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL) /*!< Event 15 triggers regular group conversion start */
#define ADC_SOFTWARE_START ((uint32_t)0x00000001) /*!< Software triggers regular group conversion start */
/**
* @}
*/
/** @defgroup ADC_EOCSelection ADC End of Regular Sequence/Conversion
/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
* @{
*/
#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) /*!< End of conversion flag */
#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) /*!< End of sequence flag */
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) /*!< Regular conversions hardware trigger detection disabled */
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0) /*!< Regular conversions hardware trigger detection on the rising edge */
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1) /*!< Regular conversions hardware trigger detection on the falling edge */
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN) /*!< Regular conversions hardware trigger detection on both the rising and falling edges */
/**
* @}
*/
/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
* @{
*/
#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) /*!< End of unitary conversion flag */
#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) /*!< End of sequence conversions flag */
#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< Reserved for future use */
/**
* @}
@ -372,7 +481,30 @@ typedef struct
* @}
*/
/** @defgroup ADC_channels ADC Channels
/** @defgroup ADC_regular_rank ADC group regular sequencer rank
* @{
*/
#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */
#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */
#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */
#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */
#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */
#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */
#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */
#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */
#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */
#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */
#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */
#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */
#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */
#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */
#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */
#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */
/**
* @}
*/
/** @defgroup ADC_channels ADC channels
* @{
*/
#define ADC_CHANNEL_0 ((uint32_t)(0x00000000)) /*!< ADC channel 0 */
@ -400,18 +532,29 @@ typedef struct
#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_17 /*!< ADC temperature sensor channel */
#define ADC_CHANNEL_VBAT ADC_CHANNEL_18 /*!< ADC Vbat channel */
#define ADC_CHANNEL_VREFINT ADC_CHANNEL_0 /*!< ADC Vrefint channel */
#if defined(ADC1) && !defined(ADC2)
#define ADC_CHANNEL_DAC1CH1 (ADC_CHANNEL_17) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, they cannot be used both simultenaeously. */
#define ADC_CHANNEL_DAC1CH2 (ADC_CHANNEL_18) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, they cannot be used both simultenaeously. */
#elif defined(ADC2)
#define ADC_CHANNEL_DAC1CH1_ADC2 (ADC_CHANNEL_17) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
#define ADC_CHANNEL_DAC1CH2_ADC2 (ADC_CHANNEL_18) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
#if defined(ADC3)
#define ADC_CHANNEL_DAC1CH1_ADC3 (ADC_CHANNEL_14) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */
#define ADC_CHANNEL_DAC1CH2_ADC3 (ADC_CHANNEL_15) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */
#endif
#endif
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup ADC_Private_Macro ADC Private Macros
* @{
*/
@ -424,7 +567,7 @@ typedef struct
*/
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
(((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
/**
* @brief Return resolution bits in CFGR register RES[1:0] field.
* @param __HANDLE__: ADC handle.
@ -449,7 +592,6 @@ typedef struct
((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
) ? SET : RESET)
/**
* @brief Check if conversion is on going on regular group.
* @param __HANDLE__: ADC handle.
@ -458,8 +600,7 @@ typedef struct
#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
(( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
) ? RESET : SET)
/**
* @brief Simultaneously clear and set specific bits of the handle State.
* @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
@ -474,19 +615,18 @@ typedef struct
* @param __RESOLUTION__: ADC resolution (12, 10, 8 or 6 bits).
* @param __ADC_VALUE__: value checked against the resolution.
* @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
*/
*/
#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \
(((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \
(((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \
(((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F))) )
/**
* @brief Verify the length of the scheduled regular conversions group.
* @param __LENGTH__: number of programmed conversions.
* @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
*/
*/
#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
@ -494,7 +634,7 @@ typedef struct
* @brief Verify the number of scheduled regular conversions in discontinuous mode.
* @param NUMBER: number of scheduled regular conversions in discontinuous mode.
* @retval SET (NUMBER is within the maximum number of regular conversions in discontinous mode) or RESET (NUMBER is null or too large)
*/
*/
#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
@ -502,7 +642,7 @@ typedef struct
* @brief Verify the ADC clock setting.
* @param __ADC_CLOCK__: programmed ADC clock.
* @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)
*/
*/
#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
@ -524,7 +664,7 @@ typedef struct
* @brief Verify the ADC resolution setting.
* @param __RESOLUTION__: programmed ADC resolution.
* @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
*/
*/
#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
@ -564,8 +704,6 @@ typedef struct
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
/**
* @brief Verify the ADC regular conversions external trigger.
@ -589,9 +727,7 @@ typedef struct
((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
\
((__REGTRIG__) == ADC_SOFTWARE_START) )
((__REGTRIG__) == ADC_SOFTWARE_START) )
/**
* @brief Verify the ADC regular conversions check for converted data availability.
@ -625,7 +761,7 @@ typedef struct
((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) )
#else
#else
#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \
@ -634,18 +770,41 @@ typedef struct
((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) )
#endif
#endif
/**
* @brief Verify the ADC regular channel setting.
* @param __CHANNEL__: programmed ADC regular channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/
#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
((__CHANNEL__) == ADC_REGULAR_RANK_16) )
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup ADC_Private_Constants ADC Private Constants
* @{
*/
*/
/* Fixed timeout values for ADC conversion (including sampling time) */
/* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */
/* Maximum conversion time is 12.5 + Maximum sampling time */
@ -656,20 +815,20 @@ typedef struct
#define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 5) /*!< ADC stop time-out value */
/* Delay for temperature sensor stabilization time. */
/* Maximum delay is 120us (refer device datasheet, parameter tSTART). */
/* Unit: us */
/* Maximum delay is 120us (refer device datasheet, parameter tSTART). */
/* Unit: us */
#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 120)
/**
* @}
*/
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup ADC_Exported_Macro ADC Exported Macros
* @{
*/
/** @brief Reset ADC handle state.
* @param __HANDLE__: ADC handle.
* @retval None
@ -788,15 +947,15 @@ typedef struct
#include "stm32l4xx_hal_adc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADC_Exported_Functions ADC Exported Functions
/** @addtogroup ADC_Exported_Functions
* @{
*/
*/
/** @addtogroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions **********************************/
/** @addtogroup ADC_Exported_Functions_Group1
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
@ -805,10 +964,12 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
* @}
*/
/** @addtogroup ADC_Exported_Functions_Group2 Input and Output operation functions
* @brief IO operation functions
* @{
*/
/** @addtogroup ADC_Exported_Functions_Group2
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
@ -839,34 +1000,34 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
/**
* @}
*/
/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
* @brief ADC Peripheral State functions
* @{
*/
/* Peripheral State functions *************************************************/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/** @addtogroup ADC_Exported_Functions_Group4
* @{
*/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @}
*/
/**
* @}
*/
*/
/* Private functions -----------------------------------------------------------*/
/** @addtogroup ADC_Private_Functions ADC Private Functions
* @{
*/
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
@ -880,7 +1041,7 @@ void ADC_DMAError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
*/
/**
* @}
@ -890,7 +1051,7 @@ void ADC_DMAError(DMA_HandleTypeDef *hdma);
}
#endif
#endif /*__STM32L4xx_ADC_H */
#endif /* __STM32L4xx_HAL_ADC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.c
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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_can.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief CAN HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
@ -73,7 +73,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -366,6 +366,12 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy
/* Initialisation mode for the filter */
CAN1->FMR |= (uint32_t)CAN_FMR_FINIT;
#if defined(CAN2)
/* Select the start slave bank */
CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);
#endif
/* Filter Deactivation */
CAN1->FA1R &= ~(uint32_t)filternbrbitpos;

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_can.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_comp.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief COMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the COMP peripheral:
@ -123,7 +123,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

99
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_comp.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of COMP HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -172,7 +172,9 @@ typedef struct
#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */
#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN ) /*!< Comparator input minus connected to VrefInt */
#define COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
#if defined(DAC_CHANNEL2_SUPPORT)
#define COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
#endif
#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */
#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */
#if defined(COMP_CSR_INMESEL_1)
@ -207,14 +209,34 @@ typedef struct
/** @defgroup COMP_BlankingSrce COMP blanking source
* @{
*/
/* Note: Some blanking sources are not available depending on timer */
/* availability or devices specificities */
/* (STM32L43xx, STM32L44xx, STM32L45xx, STM32L46xx) */
#define COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000) /*!< No blanking source */
/* Blanking sources for COMP instance: COMP1 */
#define COMP_BLANKINGSRC_TIM1_OC5_COMP1 (COMP_CSR_BLANKING_0) /*!< Blanking source for COMP1: TIM1 OC5 selected as blanking source for comparator */
#define COMP_BLANKINGSRC_TIM2_OC3_COMP1 (COMP_CSR_BLANKING_1) /*!< Blanking source for COMP1: TIM2 OC3 selected as blanking source for comparator */
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
#define COMP_BLANKINGSRC_TIM3_OC3_COMP1 (COMP_CSR_BLANKING_2) /*!< Blanking source for COMP1: TIM3 OC3 selected as blanking source for comparator */
#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
/* STM32L496xx || STM32L4A6xx */
/* Blanking sources for COMP instance: COMP2 */
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
#define COMP_BLANKINGSRC_TIM3_OC4_COMP2 (COMP_CSR_BLANKING_0) /*!< Blanking source for COMP2: TIM3 OC4 selected as blanking source for comparator */
#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
/* STM32L496xx || STM32L4A6xx */
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
#define COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_1) /*!< Blanking source for COMP2: TIM8 OC5 selected as blanking source for comparator */
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
/* STM32L496xx || STM32L4A6xx */
#define COMP_BLANKINGSRC_TIM15_OC1_COMP2 (COMP_CSR_BLANKING_2) /*!< Blanking source for COMP2: TIM15 OC1 selected as blanking source for comparator */
/**
* @}
@ -558,7 +580,7 @@ typedef struct
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
/* compatibility with other STM32 families. */
#if defined(COMP_CSR_INMESEL_1)
#if defined(COMP_CSR_INMESEL_1) && defined(DAC_CHANNEL2_SUPPORT)
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
@ -570,7 +592,18 @@ typedef struct
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5))
#else
#elif defined(COMP_CSR_INMESEL_1)
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5))
#elif defined(DAC_CHANNEL2_SUPPORT)
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
@ -579,6 +612,14 @@ typedef struct
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))
#else
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))
#endif
#define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \
@ -589,6 +630,51 @@ typedef struct
#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
((__POL__) == COMP_OUTPUTPOL_INVERTED))
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
#define IS_COMP_BLANKINGSRCE(__SOURCE__) (((__SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __BLANKINGSRCE__) \
((((__INSTANCE__) == COMP1) && \
(((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE) || \
((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1))) \
|| \
(((__INSTANCE__) == COMP2) && \
(((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE) || \
((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))))
#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
#define IS_COMP_BLANKINGSRCE(__SOURCE__) (((__SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __BLANKINGSRCE__) \
((((__INSTANCE__) == COMP1) && \
(((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE) || \
((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1))) \
|| \
(((__INSTANCE__) == COMP2) && \
(((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE) || \
((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \
((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))))
#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
#define IS_COMP_BLANKINGSRCE(__SOURCE__) (((__SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
@ -610,6 +696,9 @@ typedef struct
((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) || \
((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))))
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
/* STM32L496xx || STM32L4A6xx */
#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \

98
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_conf.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief HAL configuration file.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -58,10 +58,13 @@
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DCMI_MODULE_ENABLED
#define HAL_DFSDM_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_DMA2D_MODULE_ENABLED
#define HAL_FIREWALL_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_HASH_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
@ -131,18 +134,18 @@
* which is subject to manufacturing process variations.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
The real value my vary depending on manufacturing process variations.*/
#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
The real value my vary depending on manufacturing process variations.*/
#endif /* HSI48_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
@ -182,17 +185,26 @@
*/
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 0
#define INSTRUCTION_CACHE_ENABLE 1
#define DATA_CACHE_ENABLE 1
#define USE_RTOS 0U
#define PREFETCH_ENABLE 0U
#define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 1U
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1 */
/* #define USE_FULL_ASSERT 1U */
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 1U
/* Includes ------------------------------------------------------------------*/
/**
@ -243,6 +255,14 @@
#include "stm32l4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32l4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32l4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_FIREWALL_MODULE_ENABLED
#include "stm32l4xx_hal_firewall.h"
#endif /* HAL_FIREWALL_MODULE_ENABLED */
@ -251,6 +271,10 @@
#include "stm32l4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32l4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32l4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
@ -264,95 +288,95 @@
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32l4xx_hal_i2c.h"
#include "stm32l4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32l4xx_hal_iwdg.h"
#include "stm32l4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LCD_MODULE_ENABLED
#include "stm32l4xx_hal_lcd.h"
#include "stm32l4xx_hal_lcd.h"
#endif /* HAL_LCD_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32l4xx_hal_lptim.h"
#include "stm32l4xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_OPAMP_MODULE_ENABLED
#include "stm32l4xx_hal_opamp.h"
#include "stm32l4xx_hal_opamp.h"
#endif /* HAL_OPAMP_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32l4xx_hal_pwr.h"
#include "stm32l4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
#include "stm32l4xx_hal_qspi.h"
#include "stm32l4xx_hal_qspi.h"
#endif /* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32l4xx_hal_rng.h"
#include "stm32l4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32l4xx_hal_rtc.h"
#include "stm32l4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32l4xx_hal_sai.h"
#include "stm32l4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32l4xx_hal_sd.h"
#include "stm32l4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32l4xx_hal_smbus.h"
#include "stm32l4xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32l4xx_hal_spi.h"
#include "stm32l4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_SWPMI_MODULE_ENABLED
#include "stm32l4xx_hal_swpmi.h"
#include "stm32l4xx_hal_swpmi.h"
#endif /* HAL_SWPMI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32l4xx_hal_tim.h"
#include "stm32l4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_TSC_MODULE_ENABLED
#include "stm32l4xx_hal_tsc.h"
#include "stm32l4xx_hal_tsc.h"
#endif /* HAL_TSC_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32l4xx_hal_uart.h"
#include "stm32l4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32l4xx_hal_usart.h"
#include "stm32l4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32l4xx_hal_irda.h"
#include "stm32l4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32l4xx_hal_smartcard.h"
#include "stm32l4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32l4xx_hal_wwdg.h"
#include "stm32l4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32l4xx_hal_pcd.h"
#include "stm32l4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32l4xx_hal_hcd.h"
#include "stm32l4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_cortex.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@ -92,7 +92,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_cortex.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_crc.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CRC peripheral:
@ -33,7 +33,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_crc.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_crc_ex.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Extended CRC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the CRC peripheral.
@ -20,7 +20,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_crc_ex.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of CRC HAL extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

96
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_cryp.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief CRYP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
@ -42,7 +42,7 @@
(#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures:
(++) The data type: 1-bit, 8-bit, 16-bit and 32-bit
(++) The AES operating mode (encryption, key derivation and/or decryption)
(++) The AES chaining mode (ECB, CBC, CTR, GCM, GMAC, CMAC)
(++) The AES chaining mode (ECB, CBC, CTR, GCM, GMAC, CMAC when applicable, CCM when applicable)
(++) The encryption/decryption key if so required
(++) The initialization vector or nonce if applicable (not used in ECB mode).
@ -60,7 +60,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -92,7 +92,7 @@
#ifdef HAL_CRYP_MODULE_ENABLED
#if defined (STM32L442xx) || defined (STM32L443xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx)
/** @addtogroup STM32L4xx_HAL_Driver
* @{
@ -196,7 +196,7 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
* @{
*/
/**
/**
* @brief Initialize the CRYP according to the specified
* parameters in the CRYP_InitTypeDef and initialize the associated handle.
* @note Specific care must be taken to format the key and the Initialization Vector IV
@ -230,16 +230,28 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
/* Check the proper operating/chaining modes combinations */
/*========================================================*/
/* Check the proper chaining when the operating mode is key derivation and decryption */
#if defined(AES_CR_NPBLB)
if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\
((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR) \
|| (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) \
|| (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)))
|| (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)))
#else
if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\
((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR) \
|| (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) \
|| (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)))
#endif
{
return HAL_ERROR;
}
/* Check that key derivation is not set in CMAC mode */
/* Check that key derivation is not set in CMAC mode or CCM mode when applicable */
#if defined(AES_CR_NPBLB)
if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
&& (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
&& (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM))
#else
if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
&& (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
#endif
{
return HAL_ERROR;
}
@ -262,7 +274,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
hcryp->State = HAL_CRYP_STATE_BUSY;
/* Disable the Peripheral */
__HAL_CRYP_DISABLE();
__HAL_CRYP_DISABLE(hcryp);
/*=============================================================*/
/* AES initialization common to all operating modes */
@ -271,7 +283,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
MODIFY_REG(hcryp->Instance->CR, AES_CR_KEYSIZE, hcryp->Init.KeySize);
/* Set the default CRYP phase when this parameter is not used.
Phase is updated below in case of GCM/GMAC/CMAC setting. */
Phase is updated below in case of GCM/GMAC(/CMAC)(/CCM) setting. */
hcryp->Phase = HAL_CRYP_PHASE_NOT_USED;
@ -292,23 +304,31 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
}
else
/* Encryption / Decryption (with or without key derivation) / authentication */
{
{
#if !defined(AES_CR_NPBLB)
/* Set data type, operating and chaining modes.
In case of GCM or GMAC, data type is forced to 0b00 */
if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
{
MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.OperatingMode|hcryp->Init.ChainingMode);
MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.OperatingMode|hcryp->Init.ChainingMode);
}
else
#endif
{
MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.DataType|hcryp->Init.OperatingMode|hcryp->Init.ChainingMode);
}
/* Specify the encryption/decryption phase in case of Galois counter mode (GCM),
Galois message authentication code (GMAC) or cipher message authentication code (CMAC) */
Galois message authentication code (GMAC), cipher message authentication code (CMAC) when applicable
or Counter with Cipher Mode (CCM) when applicable */
#if defined(AES_CR_NPBLB)
if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
|| (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM))
#else
if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
|| (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
#endif
{
MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, hcryp->Init.GCMCMACPhase);
hcryp->Phase = HAL_CRYP_PHASE_START;
@ -333,6 +353,11 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
}
}
}
#if defined(AES_CR_NPBLB)
/* Clear NPBLB field */
CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB);
#endif
/* Reset CrypInCount and CrypOutCount */
hcryp->CrypInCount = 0;
@ -348,7 +373,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
hcryp->State = HAL_CRYP_STATE_READY;
/* Enable the Peripheral */
__HAL_CRYP_ENABLE();
__HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
@ -379,7 +404,7 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
hcryp->CrypOutCount = 0;
/* Disable the CRYP Peripheral Clock */
__HAL_CRYP_DISABLE();
__HAL_CRYP_DISABLE(hcryp);
/* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_CRYP_MspDeInit(hcryp);
@ -1099,16 +1124,16 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
{
/* Check if error occurred */
if (__HAL_CRYP_GET_IT_SOURCE(CRYP_IT_ERRIE) != RESET)
if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERRIE) != RESET)
{
/* If Write Error occurred */
if (__HAL_CRYP_GET_FLAG(CRYP_IT_WRERR) != RESET)
if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_WRERR) != RESET)
{
hcryp->ErrorCode |= HAL_CRYP_WRITE_ERROR;
hcryp->State = HAL_CRYP_STATE_ERROR;
}
/* If Read Error occurred */
if (__HAL_CRYP_GET_FLAG(CRYP_IT_RDERR) != RESET)
if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_RDERR) != RESET)
{
hcryp->ErrorCode |= HAL_CRYP_READ_ERROR;
hcryp->State = HAL_CRYP_STATE_ERROR;
@ -1118,9 +1143,9 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
if (hcryp->State == HAL_CRYP_STATE_ERROR)
{
/* Disable Error and Computation Complete Interrupts */
__HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
/* Clear all Interrupt flags */
__HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR|CRYP_CCF_CLEAR);
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR|CRYP_CCF_CLEAR);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
@ -1129,14 +1154,20 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
return;
}
}
/* Check if computation complete interrupt is enabled
and if the computation complete flag is raised */
if((__HAL_CRYP_GET_FLAG(CRYP_IT_CCF) != RESET) && (__HAL_CRYP_GET_IT_SOURCE(CRYP_IT_CCFIE) != RESET))
{
if((__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET) && (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET))
{
#if defined(AES_CR_NPBLB)
if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
|| (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM))
#else
if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
|| (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
#endif
{
/* To ensure proper suspension requests management, CCF flag
is reset in CRYP_AES_Auth_IT() according to the current
@ -1146,7 +1177,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
else
{
/* Clear Computation Complete Flag */
__HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
CRYP_AES_IT(hcryp);
}
}
@ -1257,7 +1288,8 @@ static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp)
static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp)
{
uint32_t ivaddr = 0x0;
#if !defined(AES_CR_NPBLB)
if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
{
hcryp->Instance->IVR3 = 0;
@ -1266,6 +1298,7 @@ static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp)
hcryp->Instance->IVR0 = 0;
}
else
#endif
{
if (hcryp->Init.pInitVect == NULL)
{
@ -1298,15 +1331,12 @@ static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp)
static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t inputaddr = 0;
uint32_t outputaddr = 0;
uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
if(hcryp->State == HAL_CRYP_STATE_BUSY)
{
if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
{
/* Get the output data address */
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
{
/* Read the last available output block from the Data Output Register */
*(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
outputaddr+=4;
@ -1348,7 +1378,7 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
if ((hcryp->CrypOutCount == 0) || (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION))
{
/* Disable Computation Complete Flag and Errors Interrupts */
__HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
@ -1367,7 +1397,7 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
/* Disable Computation Complete Flag and Errors Interrupts */
__HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_SUSPENDED;
@ -1420,7 +1450,7 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
* @}
*/
#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined(STM32L485xx) || defined(STM32L486xx) */
#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) */
#endif /* HAL_CRYP_MODULE_ENABLED */

138
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_cryp.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -43,7 +43,7 @@
extern "C" {
#endif
#if defined (STM32L442xx) || defined (STM32L443xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
@ -82,15 +82,17 @@ typedef struct
This parameter can be a value of @ref CRYP_Key_Write */
uint32_t GCMCMACPhase; /*!< Indicates the processing phase of the Galois Counter Mode (GCM),
Galois Message Authentication Code (GMAC) or Cipher Message
Authentication Code (CMAC) mode.
Galois Message Authentication Code (GMAC), Cipher Message
Authentication Code (CMAC) (when applicable) or Counter with Cipher
Mode (CCM) (when applicable).
This parameter can be a value of @ref CRYP_GCM_CMAC_Phase */
uint8_t* pKey; /*!< Encryption/Decryption Key */
uint8_t* pInitVect; /*!< Initialization Vector used for CTR, CBC, GCM/GMAC and CMAC modes */
uint8_t* pInitVect; /*!< Initialization Vector used for CTR, CBC, GCM/GMAC, CMAC (when applicable)
and CCM (when applicable) modes */
uint8_t* Header; /*!< Header used in GCM/GMAC and CMAC modes */
uint8_t* Header; /*!< Header used in GCM/GMAC, CMAC (when applicable) and CCM (when applicable) modes */
uint64_t HeaderSize; /*!< Header size in bytes */
@ -114,17 +116,17 @@ typedef enum
*/
typedef enum
{
HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */
HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */
HAL_CRYP_PHASE_START = 0x03, /*!< CRYP peripheral has been initialized but GCM/GMAC/CMAC
initialization phase has not started */
HAL_CRYP_PHASE_INIT_OVER = 0x04, /*!< GCM/GMAC/CMAC init phase has been carried out */
HAL_CRYP_PHASE_HEADER_OVER = 0x05, /*!< GCM/GMAC/CMAC header phase has been carried out */
HAL_CRYP_PHASE_PAYLOAD_OVER = 0x06, /*!< GCM/GMAC/CMAC payload phase has been carried out */
HAL_CRYP_PHASE_FINAL_OVER = 0x07, /*!< GCM/GMAC/CMAC final phase has been carried out */
HAL_CRYP_PHASE_HEADER_SUSPENDED = 0x08, /*!< GCM/GMAC/CMAC header phase has been suspended */
HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09, /*!< GCM/GMAC payload phase has been suspended */
HAL_CRYP_PHASE_NOT_USED = 0x0a /*!< Phase is irrelevant to the current chaining mode */
HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */
HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */
HAL_CRYP_PHASE_START = 0x03, /*!< CRYP peripheral has been initialized but
GCM/GMAC(/CMAC)(/CCM) initialization phase has not started */
HAL_CRYP_PHASE_INIT_OVER = 0x04, /*!< GCM/GMAC(/CMAC)(/CCM) init phase has been carried out */
HAL_CRYP_PHASE_HEADER_OVER = 0x05, /*!< GCM/GMAC(/CMAC)(/CCM) header phase has been carried out */
HAL_CRYP_PHASE_PAYLOAD_OVER = 0x06, /*!< GCM(/CCM) payload phase has been carried out */
HAL_CRYP_PHASE_FINAL_OVER = 0x07, /*!< GCM/GMAC(/CMAC)(/CCM) final phase has been carried out */
HAL_CRYP_PHASE_HEADER_SUSPENDED = 0x08, /*!< GCM/GMAC(/CMAC)(/CCM) header phase has been suspended */
HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09, /*!< GCM(/CCM) payload phase has been suspended */
HAL_CRYP_PHASE_NOT_USED = 0x0a /*!< Phase is irrelevant to the current chaining mode */
}HAL_PhaseTypeDef;
/**
@ -164,9 +166,10 @@ typedef struct
uint32_t CrypOutCount; /*!< Output data size in bytes */
HAL_PhaseTypeDef Phase; /*!< CRYP peripheral processing phase for GCM, GMAC or CMAC modes.
Indicates the last phase carried out to ease
phase transitions */
HAL_PhaseTypeDef Phase; /*!< CRYP peripheral processing phase for GCM, GMAC, CMAC (when applicable)
or CCM (when applicable) modes.
Indicates the last phase carried out to ease
phase transitions */
DMA_HandleTypeDef *hdmain; /*!< CRYP peripheral Input DMA handle parameters */
@ -223,24 +226,28 @@ typedef struct
/** @defgroup CRYP_AES_OperatingMode AES operating mode
* @{
*/
#define CRYP_ALGOMODE_ENCRYPT ((uint32_t)0x00000000) /*!< Encryption mode */
#define CRYP_ALGOMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode */
#define CRYP_ALGOMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption */
#define CRYP_ALGOMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption */
#define CRYP_ALGOMODE_TAG_GENERATION ((uint32_t)0x00000000) /*!< GMAC or CMAC authentication tag generation */
#define CRYP_ALGOMODE_ENCRYPT ((uint32_t)0x00000000) /*!< Encryption mode */
#define CRYP_ALGOMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode */
#define CRYP_ALGOMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption */
#define CRYP_ALGOMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption */
#define CRYP_ALGOMODE_TAG_GENERATION ((uint32_t)0x00000000) /*!< GMAC or CMAC (when applicable) authentication tag generation */
/**
* @}
*/
/** @defgroup CRYP_AES_ChainingMode AES chaining mode
* @{
*/
*/
#define CRYP_CHAINMODE_AES_ECB ((uint32_t)0x00000000) /*!< Electronic codebook chaining algorithm */
#define CRYP_CHAINMODE_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
#define CRYP_CHAINMODE_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */
#define CRYP_CHAINMODE_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
#if defined(AES_CR_NPBLB)
#define CRYP_CHAINMODE_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */
#else
#define CRYP_CHAINMODE_AES_CMAC AES_CR_CHMOD_2 /*!< Cipher message authentication code */
/**
#endif
/**
* @}
*/
@ -272,13 +279,19 @@ typedef struct
*/
/** @defgroup CRYP_GCM_CMAC_Phase GCM/GMAC and CMAC processing phase selection
/** @defgroup CRYP_GCM_CMAC_Phase GCM/GMAC and CCM/CMAC (when applicable) processing phase selection
* @{
*/
#define CRYP_GCM_INIT_PHASE ((uint32_t)0x00000000) /*!< GCM/GMAC init phase */
#define CRYP_GCMCMAC_HEADER_PHASE AES_CR_GCMPH_0 /*!< GCM/GMAC or CMAC header phase */
#define CRYP_GCM_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< GCM payload phaset */
#define CRYP_GCMCMAC_FINAL_PHASE AES_CR_GCMPH /*!< GCM/GMAC or CMAC final phase */
#define CRYP_GCM_INIT_PHASE ((uint32_t)0x00000000) /*!< GCM/GMAC (or CCM) init phase */
#define CRYP_GCMCMAC_HEADER_PHASE AES_CR_GCMPH_0 /*!< GCM/GMAC/CCM/CMAC header phase */
#define CRYP_GCM_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< GCM/CCM payload phase */
#define CRYP_GCMCMAC_FINAL_PHASE AES_CR_GCMPH /*!< GCM/GMAC/CCM/CMAC final phase */
/* Definitions duplication for code readibility's sake:
supported or not supported chain modes are not specified for each phase */
#define CRYP_INIT_PHASE ((uint32_t)0x00000000) /*!< Init phase */
#define CRYP_HEADER_PHASE AES_CR_GCMPH_0 /*!< Header phase */
#define CRYP_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< Payload phase */
#define CRYP_FINAL_PHASE AES_CR_GCMPH /*!< Final phase */
/**
* @}
*/
@ -341,18 +354,21 @@ typedef struct
/**
* @brief Enable the CRYP AES peripheral.
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
#define __HAL_CRYP_ENABLE() (AES->CR |= AES_CR_EN)
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
/**
* @brief Disable the CRYP AES peripheral.
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
#define __HAL_CRYP_DISABLE() (AES->CR &= ~AES_CR_EN)
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
/**
* @brief Set the algorithm operating mode.
* @param __HANDLE__: specifies the CRYP handle.
* @param __OPERATING_MODE__: specifies the operating mode
* This parameter can be one of the following values:
* @arg @ref CRYP_ALGOMODE_ENCRYPT encryption
@ -361,25 +377,27 @@ typedef struct
* @arg @ref CRYP_ALGOMODE_KEYDERIVATION_DECRYPT key derivation and decryption
* @retval None
*/
#define __HAL_CRYP_SET_OPERATINGMODE(__OPERATING_MODE__) MODIFY_REG(AES->CR, AES_CR_MODE, (__OPERATING_MODE__))
#define __HAL_CRYP_SET_OPERATINGMODE(__HANDLE__, __OPERATING_MODE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_MODE, (__OPERATING_MODE__))
/**
* @brief Set the algorithm chaining mode.
* @param __HANDLE__: specifies the CRYP handle.
* @param __CHAINING_MODE__: specifies the chaining mode
* This parameter can be one of the following values:
* @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook
* @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining
* @arg @ref CRYP_CHAINMODE_AES_CTR CounTeR mode
* @arg @ref CRYP_CHAINMODE_AES_GCM_GMAC Galois Counter Mode or Galois Message Authentication Code
* @arg @ref CRYP_CHAINMODE_AES_CMAC Cipher Message Authentication Code
* @arg @ref CRYP_CHAINMODE_AES_CMAC Cipher Message Authentication Code (or Counter with Cipher Mode when applicable)
* @retval None
*/
#define __HAL_CRYP_SET_CHAININGMODE(__CHAINING_MODE__) MODIFY_REG(AES->CR, AES_CR_CHMOD, (__CHAINING_MODE__))
#define __HAL_CRYP_SET_CHAININGMODE(__HANDLE__, __CHAINING_MODE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_CHMOD, (__CHAINING_MODE__))
/** @brief Check whether the specified CRYP status flag is set or not.
* @param __HANDLE__: specifies the CRYP handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
@ -388,31 +406,34 @@ typedef struct
* @arg @ref CRYP_IT_CCF Computation Complete
* @retval The state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CRYP_GET_FLAG(__FLAG__) ((AES->SR & (__FLAG__)) == (__FLAG__))
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clear the CRYP pending status flag.
* @param __HANDLE__: specifies the CRYP handle.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
* @retval None
*/
#define __HAL_CRYP_CLEAR_FLAG(__FLAG__) SET_BIT(AES->CR, (__FLAG__))
#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
/** @brief Check whether the specified CRYP interrupt source is enabled or not.
* @param __HANDLE__: specifies the CRYP handle.
* @param __INTERRUPT__: CRYP interrupt source to check
* This parameter can be one of the following values:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* @retval State of interruption (TRUE or FALSE).
*/
#define __HAL_CRYP_GET_IT_SOURCE(__INTERRUPT__) ((AES->CR & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Check whether the specified CRYP interrupt is set or not.
* @param __HANDLE__: specifies the CRYP handle.
* @param __INTERRUPT__: specifies the interrupt to check.
* This parameter can be one of the following values:
* @arg @ref CRYP_IT_WRERR Write Error
@ -420,40 +441,43 @@ typedef struct
* @arg @ref CRYP_IT_CCF Computation Complete
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_CRYP_GET_IT(__INTERRUPT__) ((AES->SR & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Clear the CRYP pending interrupt.
* @param __HANDLE__: specifies the CRYP handle.
* @param __INTERRUPT__: specifies the IT to clear.
* This parameter can be one of the following values:
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
* @retval None
*/
#define __HAL_CRYP_CLEAR_IT(__INTERRUPT__) SET_BIT(AES->CR, (__INTERRUPT__))
#define __HAL_CRYP_CLEAR_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/**
* @brief Enable the CRYP interrupt.
* @param __HANDLE__: specifies the CRYP handle.
* @param __INTERRUPT__: CRYP Interrupt.
* This parameter can be one of the following values:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* @retval None
*/
#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((AES->CR) |= (__INTERRUPT__))
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
/**
* @brief Disable the CRYP interrupt.
* @param __HANDLE__: specifies the CRYP handle.
* @param __INTERRUPT__: CRYP Interrupt.
* This parameter can be one of the following values:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* @retval None
*/
#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((AES->CR) &= ~(__INTERRUPT__))
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
/**
* @}
@ -505,12 +529,20 @@ typedef struct
* @brief Verify the selected CRYP chaining algorithm.
* @param __CHAINMODE__: Selected CRYP chaining algorithm.
* @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid)
*/
*/
#if defined(AES_CR_NPBLB)
#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \
((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC))
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CCM))
#else
#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \
((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC))
#endif
/**
* @brief Verify the deciphering key write option.
@ -541,10 +573,10 @@ typedef struct
* @param __PHASE__: CRYP AES ciphering/deciphering/authentication algorithm phase.
* @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid)
*/
#define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_GCM_INIT_PHASE) || \
((__PHASE__) == CRYP_GCMCMAC_HEADER_PHASE) || \
((__PHASE__) == CRYP_GCM_PAYLOAD_PHASE) || \
((__PHASE__) == CRYP_GCMCMAC_FINAL_PHASE))
#define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_INIT_PHASE) || \
((__PHASE__) == CRYP_HEADER_PHASE) || \
((__PHASE__) == CRYP_PAYLOAD_PHASE) || \
((__PHASE__) == CRYP_FINAL_PHASE))
/**
* @}
@ -655,7 +687,7 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
* @}
*/
#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined(STM32L485xx) || defined(STM32L486xx) */
#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) */
#ifdef __cplusplus
}

780
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.c
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File diff suppressed because it is too large Load Diff

10
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_cryp_ex.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of CRYPEx HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -43,7 +43,7 @@
extern "C" {
#endif
#if defined (STM32L442xx) || defined (STM32L443xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx)
/* Includes ------------------------------------------------------------------*/
@ -137,7 +137,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp);
* @}
*/
#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined(STM32L485xx) || defined(STM32L486xx) */
#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) */
#ifdef __cplusplus
}

170
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dac.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
@ -21,14 +21,18 @@
*** DAC Channels ***
====================
[..]
STM32L4 devices integrate two 12-bit Digital Analog Converters
STM32L4 devices integrate one or two 12-bit Digital Analog Converters
(i.e. one or 2 channel(s))
1 channel : STM32L451xx STM32L452xx STM32L462xx
2 channels: STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx
STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx
The 2 converters (i.e. channel1 & channel2)
When 2 channels are available, the 2 converters (i.e. channel1 & channel2)
can be used independently or simultaneously (dual mode):
(#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
peripherals (ex. OPAMPs, comparators).
(#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip
peripherals (ex. OPAMPs, comparators).
(#) Whenever present, DAC channel2 with DAC_OUT2 (PA5) as output
or connected to on-chip peripherals (ex. OPAMPs, comparators).
*** DAC Triggers ***
====================
@ -82,7 +86,7 @@
"sample and hold" mode (i.e. low power mode).
In the sample and hold mode, the DAC core converts data, then holds the
converted voltage on a capacitor. When not converting, the DAC cores and
buffer are completely turned off between samples and the DAC output is
buffer are completely turned off between samples and the DAC output is
tri-stated, therefore reducing the overall power consumption. A new
stabilization period is needed before each new conversion.
@ -162,7 +166,7 @@
(#) DAC channel1: mapped either on
(++) DMA1 request 6 channel3
(++) or DMA2 request channel4 which must be already configured
(#) DAC channel2: mapped either on
(#) DAC channel2 (whenever present): mapped either on
(++) DMA1 request 5 channel4
(++) or DMA2 request 3 channel5 which must be already configured
[..]
@ -229,7 +233,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -277,7 +281,8 @@
/** @addtogroup DAC_Private_Constants DAC Private Constants
* @{
*/
#define TIMEOUT_DAC_CALIBCONFIG ((uint32_t)1) /* 1ms */
#define TIMEOUT_DAC_CALIBCONFIG ((uint32_t)1) /* 1 ms */
#define HFSEL_ENABLE_THRESHOLD_80MHZ ((uint32_t)80000000) /* 80 mHz */
/**
* @}
*/
@ -452,7 +457,7 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected (when supported)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
@ -469,6 +474,8 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, Channel);
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
if(Channel == DAC_CHANNEL_1)
{
/* Check if software trigger enabled */
@ -487,7 +494,18 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
}
}
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
/* Check if software trigger enabled */
if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
{
/* Enable the selected DAC software conversion */
SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
}
#endif /* STM32L451xx STM32L452xx STM32L462xx */
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@ -523,6 +541,89 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
return HAL_OK;
}
#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
/**
* @brief Enables DAC and starts conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @param pData: The destination peripheral Buffer address.
* @param Length: The length of data to be transferred from memory to DAC peripheral
* @param Alignment: Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_ALIGN(Alignment));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Set the DMA transfer complete callback for channel1 */
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
/* Set the DMA half transfer complete callback for channel1 */
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
/* Set the DMA error callback for channel1 */
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
/* Enable the selected DAC channel1 DMA request */
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
/* Case of use of channel 1 */
switch(Alignment)
{
case DAC_ALIGN_12B_R:
/* Get DHR12R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
break;
case DAC_ALIGN_12B_L:
/* Get DHR12L1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
break;
case DAC_ALIGN_8B_R:
/* Get DHR8R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
break;
default:
break;
}
/* Enable the DMA channel */
/* Enable the DAC DMA underrun interrupt */
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
/* Enable the DMA channel */
HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
/* Process Unlocked */
__HAL_UNLOCK(hdac);
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, Channel);
/* Return function status */
return HAL_OK;
}
#endif /* STM32L451xx STM32L452xx STM32L462xx */
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
/**
* @brief Enables DAC and starts conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
@ -648,7 +749,9 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
/* Return function status */
return HAL_OK;
}
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
/**
* @brief Disables DAC and stop conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
@ -673,6 +776,8 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
__HAL_DAC_DISABLE(hdac, Channel);
/* Disable the DMA channel */
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
/* Channel1 is used */
if (Channel == DAC_CHANNEL_1)
{
@ -690,6 +795,16 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
}
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
/* Disable the DMA channel */
status = HAL_DMA_Abort(hdac->DMA_Handle1);
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
#endif /* STM32L451xx STM32L452xx STM32L462xx */
/* Check if DMA Channel effectively disabled */
if (status != HAL_OK)
@ -707,7 +822,9 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
return status;
}
/* DAC channel 2 is available on top of DAC channel 1 */
/* DAC channel 2 is available on top of DAC channel 1 in */
/* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
/**
* @brief Handles DAC interrupt request
@ -740,6 +857,8 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
}
}
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
{
/* Check underrun flag of DAC channel 1 */
@ -761,6 +880,8 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
}
}
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
}
/**
@ -904,6 +1025,12 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
assert_param(IS_DAC_CHANNEL(Channel));
/* Returns the DAC channel data output register value */
#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
return hdac->Instance->DOR1;
#endif /* STM32L451xx STM32L452xx STM32L462xx */
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
if(Channel == DAC_CHANNEL_1)
{
return hdac->Instance->DOR1;
@ -912,6 +1039,8 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
return hdac->Instance->DOR2;
}
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
}
/**
@ -922,15 +1051,16 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected (Whenever present)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
{
uint32_t tmpreg1 = 0, tmpreg2 = 0;
uint32_t tickstart = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
@ -981,6 +1111,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf
HAL_Delay(1);
hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
#if !defined (STM32L451xx) & !defined (STM32L452xx) & !defined (STM32L462xx)
else /* Channel 2 */
{
/* SHSR2 can be written when BWST2 equals RESET */
@ -1002,10 +1133,12 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf
HAL_Delay(1);
hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
#endif /* STM32L451xx STM32L452xx STM32L462xx */
/* HoldTime */
hdac->Instance->SHHR = (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)<<Channel;
MODIFY_REG (hdac->Instance->SHHR, DAC_SHHR_THOLD1<<Channel, (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)<<Channel);
/* RefreshTime */
hdac->Instance->SHRR = (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)<<Channel;
MODIFY_REG (hdac->Instance->SHRR, DAC_SHRR_TREFRESH1<<Channel, (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)<<Channel);
}
if(sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
@ -1048,6 +1181,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf
tmpreg2 = (sConfig->DAC_Trigger);
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << Channel;
/* Write to DAC CR */
hdac->Instance->CR = tmpreg1;

37
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_dac.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -176,8 +176,17 @@ typedef struct
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#endif /* STM32L451xx STM32L452xx STM32L462xx */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
@ -188,7 +197,9 @@ typedef struct
#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */
#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx*/
/**
* @}
@ -208,7 +219,11 @@ typedef struct
* @{
*/
#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
/**
* @}
@ -275,7 +290,7 @@ typedef struct
/**
* @}
*/
/**
* @}
*/
@ -388,8 +403,16 @@ typedef struct
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
((CHANNEL) == DAC_CHANNEL_2))
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
#endif /* STM32L451xx STM32L452xx STM32L462xx */
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
((ALIGN) == DAC_ALIGN_12B_L) || \

182
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dac_ex.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the DAC peripheral.
@ -30,7 +30,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -198,7 +198,8 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
return HAL_OK;
}
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
/**
* @brief Set the specified data holding register value for dual DAC channel.
@ -307,6 +308,8 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
*/
}
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
/**
* @brief Run the self calibration of one DAC channel.
@ -342,91 +345,100 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC
{
status = HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdac);
/* Store configuration */
oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << Channel));
/* Disable the selected DAC channel */
CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_EN1 << Channel));
/* Set mode in MCR for calibration */
MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), 0);
/* Set DAC Channel1 DHR register to the middle value */
/* HAL_DAC_SetValue(hdac, Channel, DAC_ALIGN_12B_R, 0x0800); */
tmp = (uint32_t)hdac->Instance;
if(Channel == DAC_CHANNEL_1)
{
tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
}
else
{
tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
}
*(__IO uint32_t *) tmp = 0x0800;
/* Enable the selected DAC channel calibration */
/* i.e. set DAC_CR_CENx bit */
SET_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel));
/* Init trimming counter */
/* Medium value */
trimmingvalue = 16;
delta = 8;
while (delta != 0)
/* Process locked */
__HAL_LOCK(hdac);
/* Store configuration */
oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << Channel));
/* Disable the selected DAC channel */
CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_EN1 << Channel));
/* Set mode in MCR for calibration */
MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), 0);
/* Set DAC Channel1 DHR register to the middle value */
tmp = (uint32_t)hdac->Instance;
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
if(Channel == DAC_CHANNEL_1)
{
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
/* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
/* i.e. minimum time needed between two calibration steps */
HAL_Delay(1);
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<<Channel)) == RESET)
tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
}
else
{
tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
}
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
#endif /* STM32L451xx STM32L452xx STM32L462xx */
*(__IO uint32_t *) tmp = 0x0800;
/* Enable the selected DAC channel calibration */
/* i.e. set DAC_CR_CENx bit */
SET_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel));
/* Init trimming counter */
/* Medium value */
trimmingvalue = 16;
delta = 8;
while (delta != 0)
{
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
/* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
/* i.e. minimum time needed between two calibration steps */
HAL_Delay(1);
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<<Channel)) == (DAC_SR_CAL_FLAG1<<Channel))
{
/* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
trimmingvalue += delta;
trimmingvalue -= delta;
}
else
{
/* DAC_SR_CAL_FLAGx is LOW try lower trimming */
trimmingvalue -= delta;
}
delta >>= 1;
trimmingvalue += delta;
}
delta >>= 1;
}
/* Still need to check if right calibration is current value or one step below */
/* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1 */
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
/* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
/* i.e. minimum time needed between two calibration steps */
HAL_Delay(1);
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<<Channel)) == RESET)
{
{
/* OPAMP_CSR_OUTCAL is actually one value more */
trimmingvalue++;
/* Set right trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
}
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
}
/* Disable the selected DAC channel calibration */
/* i.e. clear DAC_CR_CENx bit */
CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel));
sConfig->DAC_TrimmingValue = trimmingvalue;
sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
/* Restore configuration */
MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), oldmodeconfiguration);
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Disable the selected DAC channel calibration */
/* i.e. clear DAC_CR_CENx bit */
CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel));
sConfig->DAC_TrimmingValue = trimmingvalue;
sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
/* Restore configuration */
MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), oldmodeconfiguration);
/* Process unlocked */
__HAL_UNLOCK(hdac);
}
return status;
}
@ -457,20 +469,21 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_Channe
{
status = HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdac);
/* Set new trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (NewTrimmingValue<<Channel));
/* Update trimming mode */
sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
sConfig->DAC_TrimmingValue = NewTrimmingValue;
/* Process unlocked */
__HAL_UNLOCK(hdac);
else
{
/* Process locked */
__HAL_LOCK(hdac);
/* Set new trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (NewTrimmingValue<<Channel));
/* Update trimming mode */
sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
sConfig->DAC_TrimmingValue = NewTrimmingValue;
/* Process unlocked */
__HAL_UNLOCK(hdac);
}
return status;
}
@ -510,6 +523,9 @@ uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
* @}
*/
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@ -547,10 +563,16 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
* @}
*/
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
/**
* @}
*/
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
/* Private functions ---------------------------------------------------------*/
/** @defgroup DACEx_Private_Functions DACEx private functions
* @brief Extended private functions
@ -606,6 +628,8 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
/**
* @}
*/
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
#endif /* HAL_DAC_MODULE_ENABLED */

49
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_dac_ex.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of DAC HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -66,7 +66,7 @@
* @{
*/
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
* @{
*/
#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
@ -109,17 +109,25 @@
/** @defgroup DACEx_Private_Macros DACEx Private Macros
* @{
*/
*/
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32L451xx STM32L452xx STM32L462xx */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
@ -129,7 +137,7 @@
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */
#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x0000003FF)
@ -194,12 +202,20 @@
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue);
@ -213,7 +229,12 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_Channe
*/
/* Peripheral Control functions ***********************************************/
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel);
/**
@ -224,6 +245,9 @@ uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel);
* @}
*/
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
/** @addtogroup DACEx_Private_Functions
* @{
*/
@ -237,7 +261,8 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
/**
* @}
*/
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
/**
* @}
*/

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/**
******************************************************************************
* @file stm32l4xx_hal_dcmi.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of DCMI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_DCMI_H
#define __STM32L4xx_HAL_DCMI_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(STM32L496xx) || defined(STM32L4A6xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup DCMI DCMI
* @brief DCMI HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DCMI_Exported_Types DCMI Exported Types
* @{
*/
/**
* @brief DCMI Embedded Synchronisation CODE Init structure definition
*/
typedef struct
{
uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
}DCMI_CodesInitTypeDef;
/**
* @brief DCMI Embedded Synchronisation CODE Init structure definition
*/
typedef struct
{
uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
uint8_t LineStartUnmask; /*!< Specifies the line start delimiter unmask. */
uint8_t LineEndUnmask; /*!< Specifies the line end delimiter unmask. */
uint8_t FrameEndUnmask; /*!< Specifies the frame end delimiter unmask. */
}DCMI_SyncUnmaskTypeDef;
/**
* @brief DCMI Init structure definition
*/
typedef struct
{
uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
This parameter can be a value of @ref DCMI_Synchronization_Mode. */
uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
This parameter can be a value of @ref DCMI_PIXCK_Polarity. */
uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
This parameter can be a value of @ref DCMI_VSYNC_Polarity. */
uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
This parameter can be a value of @ref DCMI_HSYNC_Polarity. */
uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
This parameter can be a value of @ref DCMI_Capture_Rate. */
uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
This parameter can be a value of @ref DCMI_Extended_Data_Mode. */
DCMI_CodesInitTypeDef SynchroCode; /*!< Specifies the frame start delimiter codes. */
uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
This parameter can be a value of @ref DCMI_JPEG_Mode. */
uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface.
This parameter can be a value of @ref DCMI_Byte_Select_Mode. */
uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd.
This parameter can be a value of @ref DCMI_Byte_Select_Start. */
uint32_t LineSelectMode; /*!< Specifies the data line to be captured by the interface.
This parameter can be a value of @ref DCMI_Line_Select_Mode. */
uint32_t LineSelectStart; /*!< Specifies if the data line to be captured by the interface is even or odd.
This parameter can be a value of @ref DCMI_Line_Select_Start. */
}DCMI_InitTypeDef;
/**
* @brief HAL DCMI State structures definition
*/
typedef enum
{
HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */
HAL_DCMI_STATE_READY = 0x01U, /*!< DCMI initialized and ready for use */
HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */
HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */
HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */
HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */
}HAL_DCMI_StateTypeDef;
/**
* @brief DCMI handle Structure definition
*/
typedef struct
{
DCMI_TypeDef *Instance; /*!< DCMI Register base address */
DCMI_InitTypeDef Init; /*!< DCMI init parameters */
HAL_LockTypeDef Lock; /*!< DCMI locking object */
__IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */
__IO uint32_t XferCount; /*!< DMA transfers counter */
__IO uint32_t XferSize; /*!< DMA transfer size */
uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to DMA handler */
DMA_HandleTypeDef *DMAM2M_Handle; /*!< Pointer to DMA handler for memory to memory copy
(case picture size > maximum DMA transfer length) */
__IO uint32_t ErrorCode; /*!< DCMI Error code */
uint32_t pCircularBuffer; /*!< Pointer to intermediate copy buffer
(case picture size > maximum DMA transfer length) */
uint32_t HalfCopyLength; /*!< Intermediate copies length
(case picture size > maximum DMA transfer length) */
}DCMI_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DCMI_Exported_Constants DCMI Exported Constants
* @{
*/
/** @defgroup DCMI_Error_Code DCMI Error Code
* @{
*/
#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001) /*!< Overrun error */
#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */
#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
#define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error */
/**
* @}
*/
/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
* @{
*/
#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000) /*!< The received data are transferred continuously
into the destination memory through the DMA */
#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
frame and then transfers a single frame through the DMA */
/**
* @}
*/
/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
* @{
*/
#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000) /*!< Hardware synchronization data capture (frame/line start/stop)
is synchronized with the HSYNC/VSYNC signals */
#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
synchronization codes embedded in the data flow */
/**
* @}
*/
/** @defgroup DCMI_PIXCK_Polarity DCMI Pixel Clock Polarity
* @{
*/
#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000) /*!< Pixel clock active on Falling edge */
#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
/**
* @}
*/
/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
* @{
*/
#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Vertical synchronization active Low */
#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
/**
* @}
*/
/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
* @{
*/
#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Horizontal synchronization active Low */
#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
/**
* @}
*/
/** @defgroup DCMI_JPEG_Mode DCMI JPEG Mode
* @{
*/
#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000) /*!< JPEG mode disabled */
#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< JPEG mode enabled */
/**
* @}
*/
/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
* @{
*/
#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000) /*!< All frames are captured */
#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
/**
* @}
*/
/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
* @{
*/
#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000) /*!< Interface captures 8-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
/**
* @}
*/
/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode
* @{
*/
#define DCMI_BSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received data */
#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
/**
* @}
*/
/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start
* @{
*/
#define DCMI_OEBS_ODD ((uint32_t)0x00000000) /*!< Interface captures first data from the frame/line start, second one being dropped */
#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
/**
* @}
*/
/** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode
* @{
*/
#define DCMI_LSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received lines */
#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
/**
* @}
*/
/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start
* @{
*/
#define DCMI_OELS_ODD ((uint32_t)0x00000000) /*!< Interface captures first line from the frame start, second one being dropped */
#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
/**
* @}
*/
/** @defgroup DCMI_interrupt_sources DCMI Interrupt Sources
* @{
*/
#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) /*!< Capture complete interrupt */
#define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE) /*!< Overrun interrupt */
#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) /*!< Synchronization error interrupt */
#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) /*!< VSYNC interrupt */
#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) /*!< Line interrupt */
/**
* @}
*/
/** @defgroup DCMI_Flags DCMI Flags
* @{
*/
/**
* @brief DCMI SR register
*/
#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */
#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */
/**
* @brief DCMI RIS register
*/
#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) /*!< Capture complete interrupt flag */
#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) /*!< Overrun interrupt flag */
#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) /*!< Synchronization error interrupt flag */
#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) /*!< VSYNC interrupt flag */
#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) /*!< Line interrupt flag */
/**
* @brief DCMI MIS register
*/
#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Capture complete masked interrupt status */
#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */
#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */
#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */
#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DCMI_Exported_Macros DCMI Exported Macros
* @{
*/
/** @brief Reset DCMI handle state
* @param __HANDLE__: specifies the DCMI handle.
* @retval None
*/
#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
/**
* @brief Enable the DCMI.
* @param __HANDLE__: DCMI handle
* @retval None
*/
#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
/**
* @brief Disable the DCMI.
* @param __HANDLE__: DCMI handle
* @retval None
*/
#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
/* Interrupt & Flag management */
/**
* @brief Get the DCMI pending flag.
* @param __HANDLE__: DCMI handle
* @param __FLAG__: Get the specified flag.
* This parameter can be one of the following values (no combination allowed)
* @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
* @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
* @arg DCMI_FLAG_FNE: FIFO empty flag
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag
* @arg DCMI_FLAG_OVRRI: Overrun flag
* @arg DCMI_FLAG_ERRRI: Synchronization error flag
* @arg DCMI_FLAG_VSYNCRI: VSYNC flag
* @arg DCMI_FLAG_LINERI: Line flag
* @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
* @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
* @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
* @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
* @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
* @retval The state of FLAG.
*/
#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\
(((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
/**
* @brief Clear the DCMI pending flag.
* @param __HANDLE__: DCMI handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag
* @arg DCMI_FLAG_OVRRI: Overrun flag
* @arg DCMI_FLAG_ERRRI: Synchronization error flag
* @arg DCMI_FLAG_VSYNCRI: VSYNC flag
* @arg DCMI_FLAG_LINERI: Line flag
* @retval None
*/
#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/**
* @brief Enable the specified DCMI interrupts.
* @param __HANDLE__: DCMI handle
* @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg DCMI_IT_FRAME: Frame capture complete interrupt
* @arg DCMI_IT_OVR: Overrun interrupt
* @arg DCMI_IT_ERR: Synchronization error interrupt
* @arg DCMI_IT_VSYNC: VSYNC interrupt
* @arg DCMI_IT_LINE: Line interrupt
* @retval None
*/
#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/**
* @brief Disable the specified DCMI interrupts.
* @param __HANDLE__: DCMI handle
* @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg DCMI_IT_FRAME: Frame capture complete interrupt
* @arg DCMI_IT_OVR: Overrun interrupt
* @arg DCMI_IT_ERR: Synchronization error interrupt
* @arg DCMI_IT_VSYNC: VSYNC interrupt
* @arg DCMI_IT_LINE: Line interrupt
* @retval None
*/
#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
/**
* @brief Check whether or not the specified DCMI interrupt has occurred and that the interruption is enabled at the same time.
* @note A bit in MIS register is set if the corresponding enable bit in
* DCMI_IER is set and the corresponding bit in DCMI_RIS is set.
* @param __HANDLE__: DCMI handle
* @param __INTERRUPT__: specifies the DCMI interrupt flag and source to check.
* This parameter can be one of the following values:
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
* @arg DCMI_IT_OVR: Overrun interrupt mask
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
* @arg DCMI_IT_LINE: Line interrupt mask
* @retval The state of INTERRUPT.
*/
#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MIS & (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DCMI_Exported_Functions
* @{
*/
/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
/**
* @}
*/
/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);
void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
/**
* @}
*/
/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
/**
* @}
*/
/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
* @{
*/
/* Peripheral State functions *************************************************/
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup DCMI_Private_Constants DCMI Private Constants
* @{
*/
/** @defgroup DCMI_Registers_Indices DCMI Registers Indices
* @{
*/
#define DCMI_MIS_INDEX ((uint32_t)0x1000) /*!< DCMI MIS register index */
#define DCMI_SR_INDEX ((uint32_t)0x2000) /*!< DCMI SR register index */
/**
* @}
*/
/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
* @{
*/
#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF) /*!< Window coordinate */
/**
* @}
*/
/** @defgroup DCMI_Window_Height DCMI Window Height
* @{
*/
#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFF) /*!< Window Height */
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup DCMI_Private_Macros DCMI Private Macros
* @{
*/
#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
((MODE) == DCMI_MODE_SNAPSHOT))
#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
((MODE) == DCMI_SYNCHRO_EMBEDDED))
#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
((POLARITY) == DCMI_PCKPOLARITY_RISING))
#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
((POLARITY) == DCMI_VSPOLARITY_HIGH))
#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
((POLARITY) == DCMI_HSPOLARITY_HIGH))
#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
((JPEG_MODE) == DCMI_JPEG_ENABLE))
#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
((DATA) == DCMI_EXTEND_DATA_10B) || \
((DATA) == DCMI_EXTEND_DATA_12B) || \
((DATA) == DCMI_EXTEND_DATA_14B))
#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
((MODE) == DCMI_BSM_OTHER) || \
((MODE) == DCMI_BSM_ALTERNATE_4) || \
((MODE) == DCMI_BSM_ALTERNATE_2))
#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
((POLARITY) == DCMI_OEBS_EVEN))
#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
((MODE) == DCMI_LSM_ALTERNATE_2))
#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
((POLARITY) == DCMI_OELS_EVEN))
#define IS_DCMI_INTERRUPTS(INTERRUPTS) ((INTERRUPTS) <= DCMI_IER_INT_IE)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* STM32L496xx || STM32L4A6xx */
#ifdef __cplusplus
}
#endif
#endif /* __STM32L4xx_HAL_DCMI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h
View File

@ -2,14 +2,14 @@
******************************************************************************
* @file stm32l4xx_hal_def.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

29
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dfsdm.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Digital Filter for Sigma-Delta Modulators
* (DFSDM) peripherals:
@ -161,7 +161,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -195,7 +195,10 @@
* @{
*/
#ifdef HAL_DFSDM_MODULE_ENABLED
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
/** @defgroup DFSDM DFSDM
* @brief DFSDM HAL driver module
* @{
@ -230,7 +233,11 @@
#define DFSDM_MSB_MASK 0xFFFF0000U
#define DFSDM_LSB_MASK 0x0000FFFFU
#define DFSDM_CKAB_TIMEOUT 5000U
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
#define DFSDM1_CHANNEL_NUMBER 4U
#else /* STM32L451xx || STM32L452xx || STM32L462xx */
#define DFSDM1_CHANNEL_NUMBER 8U
#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
/**
* @}
*/
@ -1734,7 +1741,7 @@ int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filte
/* Extract channel and regular conversion value */
*Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
value = ((reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET);
value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET);
/* return regular conversion value */
return value;
@ -2144,7 +2151,7 @@ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filt
/* Extract channel and injected conversion value */
*Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
value = ((reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET);
value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET);
/* return regular conversion value */
return value;
@ -2329,7 +2336,7 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
/* Extract channel and extreme detector maximum value */
*Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
value = ((reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET);
value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET);
/* return extreme detector maximum value */
return value;
@ -2357,7 +2364,7 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
/* Extract channel and extreme detector minimum value */
*Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
value = ((reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET);
value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET);
/* return extreme detector minimum value */
return value;
@ -2820,6 +2827,8 @@ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
{
channel = 3;
}
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
else if(Instance == DFSDM1_Channel4)
{
channel = 4;
@ -2836,6 +2845,7 @@ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
{
channel = 7;
}
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
return channel;
}
@ -3009,8 +3019,9 @@ static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
/**
* @}
*/
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
#endif /* HAL_DFSDM_MODULE_ENABLED */
/**
* @}
*/

62
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_dfsdm.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of DFSDM HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -43,7 +43,9 @@
extern "C" {
#endif
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
@ -87,7 +89,9 @@ typedef struct
*/
typedef struct
{
uint32_t Multiplexer; /*!< Input is external serial inputs or internal register.
uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output.
ADC output is available only on STM32L451xx, STM32L452xx, STM32L462xx,
STM32L496xx, STM32L4A6xx products.
This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
This parameter can be a value of @ref DFSDM_Channel_DataPacking */
@ -266,6 +270,10 @@ typedef struct
* @{
*/
#define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
#define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0 /*!< Data are taken from ADC output */
#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
#define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */
/**
* @}
@ -336,6 +344,15 @@ typedef struct
/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
* @{
*/
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */
#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */
#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */
#else
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */
@ -347,6 +364,7 @@ typedef struct
#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */
#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
/**
* @}
*/
@ -417,6 +435,12 @@ typedef struct
- the channel mask is 0x00000020 (bit 5 is set)
- the channel number 5 is 0x00050000
--> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U)
#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U)
#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U)
#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U)
#else /* STM32L451xx || STM32L452xx || STM32L462xx */
#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U)
#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U)
#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U)
@ -425,6 +449,7 @@ typedef struct
#define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U)
#define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U)
#define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U)
#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
/**
* @}
*/
@ -618,8 +643,15 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \
((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
#else
#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
((MODE) == DFSDM_CHANNEL_DUAL_MODE))
@ -646,6 +678,15 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
#else
#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
@ -657,6 +698,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
@ -672,6 +714,13 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU)
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
((CHANNEL) == DFSDM_CHANNEL_1) || \
((CHANNEL) == DFSDM_CHANNEL_2) || \
((CHANNEL) == DFSDM_CHANNEL_3))
#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x0003000FU))
#else /* STM32L451xx || STM32L452xx || STM32L462xx */
#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
((CHANNEL) == DFSDM_CHANNEL_1) || \
((CHANNEL) == DFSDM_CHANNEL_2) || \
@ -681,6 +730,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
((CHANNEL) == DFSDM_CHANNEL_6) || \
((CHANNEL) == DFSDM_CHANNEL_7))
#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU))
#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
#define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
((MODE) == DFSDM_CONTINUOUS_CONV_ON))
/**
@ -695,7 +745,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
/**
* @}
*/
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
#ifdef __cplusplus
}
#endif

52
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dma.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief DMA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access (DMA) peripheral:
@ -25,6 +25,9 @@
Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
using HAL_DMA_Init() function.
Prior to HAL_DMA_Init the CLK shall be enabled for both DMA thanks to:
__HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE()
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
detection.
@ -72,7 +75,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -161,7 +164,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
uint32_t tmp = 0;
/* Check the DMA handle allocation */
if(hdma == NULL)
{
@ -177,6 +180,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
assert_param(IS_DMA_MODE(hdma->Init.Mode));
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
{
assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
@ -195,7 +199,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
hdma->DmaBaseAddress = DMA2;
}
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
@ -292,11 +296,11 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
hdma->DmaBaseAddress = DMA2;
}
/* Clear all flags */
hdma->DmaBaseAddress->IFCR |= ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
/* Reset DMA channel selection register */
if (DMA1 == hdma->DmaBaseAddress)
{
@ -453,7 +457,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
HAL_StatusTypeDef status = HAL_OK;
if(HAL_DMA_STATE_BUSY != hdma->State)
{
/* no transfer ongoing */
@ -470,7 +474,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE(hdma);
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
@ -484,7 +488,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
/**
* @brief Aborts the DMA Transfer in Interrupt mode.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
@ -507,7 +511,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE(hdma);
/* Clear all flags */
hdma->DmaBaseAddress->IFCR |= ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
@ -574,7 +578,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Clear all flags */
hdma->DmaBaseAddress->IFCR |= ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
@ -609,7 +613,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
{
/* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR |= (DMA_FLAG_TC1 << hdma->ChannelIndex);
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << hdma->ChannelIndex);
/* The selected Channelx EN bit is cleared (DMA is disabled and
all transfers are complete) */
@ -618,7 +622,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
else
{
/* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR |= (DMA_FLAG_HT1 << hdma->ChannelIndex);
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << hdma->ChannelIndex);
}
/* Process unlocked */
@ -648,7 +652,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
}
/* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR |= (DMA_ISR_HTIF1 << hdma->ChannelIndex);
hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << hdma->ChannelIndex);
/* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */
@ -672,7 +676,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
hdma->State = HAL_DMA_STATE_READY;
}
/* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR |= (DMA_ISR_TCIF1 << hdma->ChannelIndex);
hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << hdma->ChannelIndex);
/* Process Unlocked */
__HAL_UNLOCK(hdma);
@ -693,7 +697,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
/* Clear all flags */
hdma->DmaBaseAddress->IFCR |= (DMA_ISR_GIF1 << hdma->ChannelIndex);
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
@ -716,7 +720,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/**
* @brief Register callbacks
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* the configuration information for the specified DMA Channel.
* @param CallbackID: User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @param pCallback: pointer to private callbacsk function which has pointer to
@ -752,7 +756,7 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call
default:
status = HAL_ERROR;
break;
break;
}
}
else
@ -769,7 +773,7 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call
/**
* @brief UnRegister callbacks
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* the configuration information for the specified DMA Channel.
* @param CallbackID: User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @retval HAL status
@ -810,7 +814,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
default:
status = HAL_ERROR;
break;
break;
}
}
else
@ -823,7 +827,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
return status;
}
/**
* @}
*/
@ -893,7 +897,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
/* Clear all flags */
hdma->DmaBaseAddress->IFCR |= (DMA_ISR_GIF1 << hdma->ChannelIndex);
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;

26
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_dma.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -121,9 +121,9 @@ typedef enum
{
HAL_DMA_XFER_CPLT_CB_ID = 0x00, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, /*!< Half transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */
HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */
}HAL_DMA_CallbackIDTypeDef;
@ -169,11 +169,11 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_Error_Code DMA Error Code
* @{
*/
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoing transfer */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100) /*!< Not supported mode */
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoing transfer */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100) /*!< Not supported mode */
/**
* @}
*/
@ -189,7 +189,6 @@ typedef struct __DMA_HandleTypeDef
#define DMA_REQUEST_5 ((uint32_t)0x00000005)
#define DMA_REQUEST_6 ((uint32_t)0x00000006)
#define DMA_REQUEST_7 ((uint32_t)0x00000007)
/**
* @}
*/
@ -200,7 +199,6 @@ typedef struct __DMA_HandleTypeDef
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
/**
* @}
*/
@ -450,7 +448,7 @@ typedef struct __DMA_HandleTypeDef
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
(DMA2->IFCR |= (__FLAG__)) : (DMA1->IFCR |= (__FLAG__)))
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
/**
* @brief Enable the specified DMA Channel interrupts.

1768
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.c Normal file
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619
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h Normal file
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@ -0,0 +1,619 @@
/**
******************************************************************************
* @file stm32l4xx_hal_dma2d.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of DMA2D HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_DMA2D_H
#define __STM32L4xx_HAL_DMA2D_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(STM32L496xx) || defined(STM32L4A6xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup DMA2D DMA2D
* @brief DMA2D HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMA2D_Exported_Types DMA2D Exported Types
* @{
*/
#define MAX_DMA2D_LAYER 2U
/**
* @brief DMA2D color Structure definition
*/
typedef struct
{
uint32_t Blue; /*!< Configures the blue value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t Green; /*!< Configures the green value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t Red; /*!< Configures the red value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
} DMA2D_ColorTypeDef;
/**
* @brief DMA2D CLUT Structure definition
*/
typedef struct
{
uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode.
This parameter can be one value of @ref DMA2D_CLUT_CM. */
uint32_t Size; /*!< Configures the DMA2D CLUT size.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
} DMA2D_CLUTCfgTypeDef;
/**
* @brief DMA2D Init structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Configures the DMA2D transfer mode.
This parameter can be one value of @ref DMA2D_Mode. */
uint32_t ColorMode; /*!< Configures the color format of the output image.
This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
uint32_t OutputOffset; /*!< Specifies the Offset value.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter.
This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
for the output pixel format converter.
This parameter can be one value of @ref DMA2D_RB_Swap. */
} DMA2D_InitTypeDef;
/**
* @brief DMA2D Layer structure definition
*/
typedef struct
{
uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
This parameter can be one value of @ref DMA2D_Alpha_Mode. */
uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
@note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
- InputAlpha[24:31] is the alpha value ALPHA[0:7]
- InputAlpha[16:23] is the red value RED[0:7]
- InputAlpha[8:15] is the green value GREEN[0:7]
- InputAlpha[0:7] is the blue value BLUE[0:7]. */
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value.
This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
This parameter can be one value of @ref DMA2D_RB_Swap. */
} DMA2D_LayerCfgTypeDef;
/**
* @brief HAL DMA2D State structures definition
*/
typedef enum
{
HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */
HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */
HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */
}HAL_DMA2D_StateTypeDef;
/**
* @brief DMA2D handle Structure definition
*/
typedef struct __DMA2D_HandleTypeDef
{
DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */
void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */
DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
HAL_LockTypeDef Lock; /*!< DMA2D lock. */
__IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
__IO uint32_t ErrorCode; /*!< DMA2D error code. */
} DMA2D_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
* @{
*/
/** @defgroup DMA2D_Error_Code DMA2D Error Code
* @{
*/
#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U) /*!< Configuration error */
#define HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U) /*!< CLUT access error */
#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
/**
* @}
*/
/** @defgroup DMA2D_Mode DMA2D Mode
* @{
*/
#define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */
#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
#define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
/**
* @}
*/
/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
* @{
*/
#define DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D color mode */
#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */
#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */
#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */
/**
* @}
*/
/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
* @{
*/
#define DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 color mode */
#define DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 color mode */
#define DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 color mode */
#define DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 color mode */
#define DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 color mode */
#define DMA2D_INPUT_L8 ((uint32_t)0x00000005U) /*!< L8 color mode */
#define DMA2D_INPUT_AL44 ((uint32_t)0x00000006U) /*!< AL44 color mode */
#define DMA2D_INPUT_AL88 ((uint32_t)0x00000007U) /*!< AL88 color mode */
#define DMA2D_INPUT_L4 ((uint32_t)0x00000008U) /*!< L4 color mode */
#define DMA2D_INPUT_A8 ((uint32_t)0x00000009U) /*!< A8 color mode */
#define DMA2D_INPUT_A4 ((uint32_t)0x0000000AU) /*!< A4 color mode */
/**
* @}
*/
/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
* @{
*/
#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */
#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U) /*!< Replace original alpha channel value by programmed alpha value */
#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U) /*!< Replace original alpha channel value by programmed alpha value
with original alpha channel value */
/**
* @}
*/
/** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion
* @{
*/
#define DMA2D_REGULAR_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */
#define DMA2D_INVERTED_ALPHA ((uint32_t)0x00000001U) /*!< Invert the alpha channel value */
/**
* @}
*/
/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
* @{
*/
#define DMA2D_RB_REGULAR ((uint32_t)0x00000000U) /*!< Select regular mode (RGB or ARGB) */
#define DMA2D_RB_SWAP ((uint32_t)0x00000001U) /*!< Select swap mode (BGR or ABGR) */
/**
* @}
*/
/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
* @{
*/
#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D CLUT color mode */
#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 DMA2D CLUT color mode */
/**
* @}
*/
/** @defgroup DMA2D_Interrupts DMA2D Interrupts
* @{
*/
#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
/**
* @}
*/
/** @defgroup DMA2D_Flags DMA2D Flags
* @{
*/
#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
/**
* @}
*/
/** @defgroup DMA2D_Aliases DMA2D API Aliases
* @{
*/
#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
/**
* @}
*/
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
* @{
*/
/** @brief Reset DMA2D handle state
* @param __HANDLE__: specifies the DMA2D handle.
* @retval None
*/
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
/**
* @brief Enable the DMA2D.
* @param __HANDLE__: DMA2D handle
* @retval None.
*/
#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
/* Interrupt & Flag management */
/**
* @brief Get the DMA2D pending flags.
* @param __HANDLE__: DMA2D handle
* @param __FLAG__: flag to check.
* This parameter can be any combination of the following values:
* @arg DMA2D_FLAG_CE: Configuration error flag
* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
* @arg DMA2D_FLAG_CAE: CLUT access error flag
* @arg DMA2D_FLAG_TW: Transfer Watermark flag
* @arg DMA2D_FLAG_TC: Transfer complete flag
* @arg DMA2D_FLAG_TE: Transfer error flag
* @retval The state of FLAG.
*/
#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
/**
* @brief Clear the DMA2D pending flags.
* @param __HANDLE__: DMA2D handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA2D_FLAG_CE: Configuration error flag
* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
* @arg DMA2D_FLAG_CAE: CLUT access error flag
* @arg DMA2D_FLAG_TW: Transfer Watermark flag
* @arg DMA2D_FLAG_TC: Transfer complete flag
* @arg DMA2D_FLAG_TE: Transfer error flag
* @retval None
*/
#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
/**
* @brief Enable the specified DMA2D interrupts.
* @param __HANDLE__: DMA2D handle
* @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg DMA2D_IT_CE: Configuration error interrupt mask
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
* @arg DMA2D_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
* @brief Disable the specified DMA2D interrupts.
* @param __HANDLE__: DMA2D handle
* @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg DMA2D_IT_CE: Configuration error interrupt mask
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
* @arg DMA2D_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified DMA2D interrupt source is enabled or not.
* @param __HANDLE__: DMA2D handle
* @param __INTERRUPT__: specifies the DMA2D interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA2D_IT_CE: Configuration error interrupt mask
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
* @arg DMA2D_IT_TE: Transfer error interrupt mask
* @retval The state of INTERRUPT source.
*/
#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
* @{
*/
/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *******************************/
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
/**
* @}
*/
/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
/**
* @}
*/
/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* Peripheral Control functions *************************************************/
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
/**
* @}
*/
/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
* @{
*/
/* Peripheral State functions ***************************************************/
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
* @{
*/
/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
* @{
*/
#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */
/**
* @}
*/
/** @defgroup DMA2D_Color_Value DMA2D Color Value
* @{
*/
#define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU) /*!< Color value mask */
/**
* @}
*/
/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
* @{
*/
#define DMA2D_MAX_LAYER 2 /*!< DMA2D maximum number of layers */
/**
* @}
*/
/** @defgroup DMA2D_Offset DMA2D Offset
* @{
*/
#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
/**
* @}
*/
/** @defgroup DMA2D_Size DMA2D Size
* @{
*/
#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D number of pixels per line */
#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of lines */
/**
* @}
*/
/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
* @{
*/
#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D CLUT size */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
* @{
*/
#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER)
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
((INPUT_CM) == DMA2D_INPUT_A4))
#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
((AlphaMode) == DMA2D_COMBINE_ALPHA))
#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
((RB_Swap) == DMA2D_RB_SWAP))
#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* STM32L496xx || STM32L4A6xx || */
#ifdef __cplusplus
}
#endif
#endif /* __STM32L4xx_HAL_DMA2D_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_firewall.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief FIREWALL HAL module driver.
* This file provides firmware functions to manage the Firewall
* Peripheral initialization and enabling.
@ -34,7 +34,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_firewall.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of FIREWALL HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

75
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_flash.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@ -77,7 +77,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -119,7 +119,8 @@
#ifdef HAL_FLASH_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
#define FLASH_NB_DOUBLE_WORDS_IN_ROW 32
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Variables FLASH Private Variables
@ -196,6 +197,18 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
{
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Deactivate the data cache if they are activated to avoid data misbehavior */
if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
{
/* Disable data cache */
__HAL_FLASH_DATA_CACHE_DISABLE();
pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
}
else
{
pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
}
if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
{
/* Program double-word (64-bit) at a specified address */
@ -222,6 +235,9 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
{
CLEAR_BIT(FLASH->CR, prog_bit);
}
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches();
}
/* Process Unlocked */
@ -253,6 +269,18 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Deactivate the data cache if they are activated to avoid data misbehavior */
if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
{
/* Disable data cache */
__HAL_FLASH_DATA_CACHE_DISABLE();
pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
}
else
{
pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
}
/* Set internal variables used by the IRQ handler */
if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
{
@ -272,7 +300,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
/* Program double-word (64-bit) at a specified address */
FLASH_Program_DoubleWord(Address, Data);
}
else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
{
/* Fast program a 32 row double-word (64-bit) at a specified address */
FLASH_Program_Fast(Address, (uint32_t)Data);
@ -291,7 +319,8 @@ void HAL_FLASH_IRQHandler(void)
/* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */
CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB));
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
CLEAR_BIT(FLASH->CR, FLASH_CR_MER2);
#endif
@ -307,7 +336,8 @@ void HAL_FLASH_IRQHandler(void)
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR)) ||
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) ||
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) ||
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY)))
#else
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)))
@ -316,14 +346,17 @@ void HAL_FLASH_IRQHandler(void)
/*Save the error code*/
FLASH_SetErrorCode();
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches() ;
/* FLASH error interrupt user callback */
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)
{
HAL_FLASH_EndOfOperationCallback(pFlash.Page);
HAL_FLASH_OperationErrorCallback(pFlash.Page);
}
else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE)
{
HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
HAL_FLASH_OperationErrorCallback(pFlash.Bank);
}
else if((pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) ||
(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST))
@ -331,8 +364,6 @@ void HAL_FLASH_IRQHandler(void)
HAL_FLASH_OperationErrorCallback(pFlash.Address);
}
HAL_FLASH_OperationErrorCallback(pFlash.Address);
/*Stop the procedure ongoing*/
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
@ -375,12 +406,12 @@ void HAL_FLASH_IRQHandler(void)
}
else
{
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches() ;
if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE)
{
/* MassErase ended. Return the selected bank */
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches() ;
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
}
@ -629,7 +660,8 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR)) ||
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) ||
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) ||
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY)))
#else
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)))
@ -713,7 +745,8 @@ static void FLASH_SetErrorCode(void)
pFlash.ErrorCode |= HAL_FLASH_ERROR_ECCD;
}
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PEMPTY;
@ -745,16 +778,16 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
}
/**
* @brief Fast program a 32 row double-word (64-bit) at a specified address.
* @brief Fast program a row double-word (64-bit) at a specified address.
* @param Address: specifies the address to be programmed.
* @param DataAddress: specifies the address where the data are stored.
* @retval None
*/
static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
{
uint8_t row_index = 32;
__IO uint64_t *dest_addr = (__IO uint64_t*)Address;
__IO uint64_t *src_addr = (__IO uint64_t*)DataAddress;
uint8_t row_index = (2*FLASH_NB_DOUBLE_WORDS_IN_ROW);
__IO uint32_t *dest_addr = (__IO uint32_t*)Address;
__IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;
/* Check the parameters */
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
@ -765,7 +798,7 @@ static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
/* Disable interrupts to avoid any interruption during the loop */
__disable_irq();
/* Program the 32 double word */
/* Program the double word of the row */
do
{
*dest_addr++ = *src_addr++;

74
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_flash.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -125,6 +125,17 @@ typedef enum
FLASH_PROC_PROGRAM_LAST
} FLASH_ProcedureTypeDef;
/**
* @brief FLASH Cache structure definition
*/
typedef enum
{
FLASH_CACHE_DISABLED = 0,
FLASH_CACHE_ICACHE_ENABLED,
FLASH_CACHE_DCACHE_ENABLED,
FLASH_CACHE_ICACHE_DCACHE_ENABLED
} FLASH_CacheTypeDef;
/**
* @brief FLASH handle Structure definition
*/
@ -137,6 +148,7 @@ typedef struct
__IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */
__IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */
__IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */
__IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */
}FLASH_ProcessTypeDef;
/**
@ -163,7 +175,8 @@ typedef struct
#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000100)
#define HAL_FLASH_ERROR_OPTV ((uint32_t)0x00000200)
#define HAL_FLASH_ERROR_ECCD ((uint32_t)0x00000400)
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
#define HAL_FLASH_ERROR_PEMPTY ((uint32_t)0x00000800)
#endif
/**
@ -183,7 +196,8 @@ typedef struct
* @{
*/
#define FLASH_BANK_1 ((uint32_t)0x01) /*!< Bank 1 */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
#define FLASH_BANK_2 ((uint32_t)0x02) /*!< Bank 2 */
#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */
#else
@ -222,7 +236,8 @@ typedef struct
*/
#define OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00) /*!< Flash Bank 1 Area A */
#define OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01) /*!< Flash Bank 1 Area B */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
#define OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02) /*!< Flash Bank 2 Area A */
#define OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04) /*!< Flash Bank 2 Area B */
#endif
@ -251,7 +266,8 @@ typedef struct
#define OB_USER_IWDG_STOP ((uint32_t)0x0010) /*!< Independent watchdog counter freeze in stop mode */
#define OB_USER_IWDG_STDBY ((uint32_t)0x0020) /*!< Independent watchdog counter freeze in standby mode */
#define OB_USER_WWDG_SW ((uint32_t)0x0040) /*!< Window watchdog selection */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
#define OB_USER_BFB2 ((uint32_t)0x0080) /*!< Dual-bank boot */
#define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 512KB or 256KB Flash memory devices */
#endif
@ -259,7 +275,9 @@ typedef struct
#define OB_USER_SRAM2_PE ((uint32_t)0x0400) /*!< SRAM2 parity check enable */
#define OB_USER_SRAM2_RST ((uint32_t)0x0800) /*!< SRAM2 Erase when system reset */
#define OB_USER_nRST_SHDW ((uint32_t)0x1000) /*!< Reset generated when entering the shutdown mode */
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
#define OB_USER_nSWBOOT0 ((uint32_t)0x2000) /*!< Software BOOT0 */
#define OB_USER_nBOOT0 ((uint32_t)0x4000) /*!< nBOOT0 option bit */
#endif
@ -342,7 +360,8 @@ typedef struct
* @}
*/
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
/** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
* @{
*/
@ -351,7 +370,6 @@ typedef struct
/**
* @}
*/
/** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type
* @{
*/
@ -389,7 +407,9 @@ typedef struct
* @}
*/
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
/** @defgroup OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
* @{
*/
@ -465,7 +485,8 @@ typedef struct
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */
#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
#define FLASH_FLAG_PEMPTY FLASH_SR_PEMPTY /*!< FLASH Program empty */
#endif
#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */
@ -758,10 +779,16 @@ uint32_t HAL_FLASH_GetError(void);
*/
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x200 << 10) : \
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
#else
#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
#endif
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1)
#else
#define FLASH_BANK_SIZE (FLASH_SIZE)
@ -782,7 +809,8 @@ uint32_t HAL_FLASH_GetError(void);
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
((VALUE) == FLASH_TYPEERASE_MASSERASE))
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
((BANK) == FLASH_BANK_2) || \
((BANK) == FLASH_BANK_BOTH))
@ -809,11 +837,15 @@ uint32_t HAL_FLASH_GetError(void);
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \
((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \
((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \
((PAGE) < 256)))))
#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 256) : \
((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \
((PAGE) < 256))))
#else
#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \
((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? ((PAGE) < 64) : \
@ -822,7 +854,8 @@ uint32_t HAL_FLASH_GetError(void);
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)))
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
#else
@ -833,7 +866,7 @@ uint32_t HAL_FLASH_GetError(void);
((LEVEL) == OB_RDP_LEVEL_1)/* ||\
((LEVEL) == OB_RDP_LEVEL_2)*/)
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0))
#else
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7F) && ((TYPE) != 0) && (((TYPE)&0x0180) == 0))
@ -857,7 +890,8 @@ uint32_t HAL_FLASH_GetError(void);
#define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
#define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
#define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL))
@ -869,7 +903,9 @@ uint32_t HAL_FLASH_GetError(void);
#define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
#define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
#define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET))

300
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_flash_ex.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extended peripheral:
@ -50,7 +50,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -171,6 +171,34 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
{
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Deactivate the cache if they are activated to avoid data misbehavior */
if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
{
/* Disable instruction cache */
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
{
/* Disable data cache */
__HAL_FLASH_DATA_CACHE_DISABLE();
pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
}
else
{
pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
}
}
else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
{
/* Disable data cache */
__HAL_FLASH_DATA_CACHE_DISABLE();
pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
}
else
{
pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
}
if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
{
/* Mass erase to be done */
@ -179,7 +207,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
/* If the erase operation is completed, disable the MER1 and MER2 Bits */
CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
#else
@ -240,6 +269,34 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Deactivate the cache if they are activated to avoid data misbehavior */
if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
{
/* Disable instruction cache */
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
{
/* Disable data cache */
__HAL_FLASH_DATA_CACHE_DISABLE();
pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
}
else
{
pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
}
}
else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
{
/* Disable data cache */
__HAL_FLASH_DATA_CACHE_DISABLE();
pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
}
else
{
pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
}
/* Enable End of Operation and Error interrupts */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
@ -274,7 +331,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
*/
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
{
HAL_StatusTypeDef status = HAL_ERROR;
HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
__HAL_LOCK(&pFlash);
@ -288,28 +345,44 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
if((pOBInit->OptionType & OPTIONBYTE_WRP) != RESET)
{
/* Configure of Write protection on the selected area */
status = FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset);
if(FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset) != HAL_OK)
{
status = HAL_ERROR;
}
}
/* Read protection configuration */
if((pOBInit->OptionType & OPTIONBYTE_RDP) != RESET)
{
/* Configure the Read protection level */
status = FLASH_OB_RDPConfig(pOBInit->RDPLevel);
if(FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK)
{
status = HAL_ERROR;
}
}
/* User Configuration */
if((pOBInit->OptionType & OPTIONBYTE_USER) != RESET)
{
/* Configure the user option bytes */
status = FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
if(FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK)
{
status = HAL_ERROR;
}
}
/* PCROP Configuration */
if((pOBInit->OptionType & OPTIONBYTE_PCROP) != RESET)
{
/* Configure the Proprietary code readout protection */
status = FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr);
if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr)
{
/* Configure the Proprietary code readout protection */
if(FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr) != HAL_OK)
{
status = HAL_ERROR;
}
}
}
/* Process Unlocked */
@ -321,18 +394,28 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
/**
* @brief Get the Option bytes configuration.
* @param pOBInit: pointer to an FLASH_OBInitStruct structure that contains the
* configuration information. The fields pOBInit->WRPArea and
* pOBInit->PCROPConfig should indicate which area is requested
* for the WRP and PCROP
* configuration information.
* @note The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate
* which area is requested for the WRP and PCROP, else no information will be returned
*
* @retval None
*/
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
{
pOBInit->OptionType = (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP);
pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
/* Get write protection on the selected area */
FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) ||
(pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))
#else
if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB))
#endif
{
pOBInit->OptionType |= OPTIONBYTE_WRP;
/* Get write protection on the selected area */
FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
}
/* Get Read protection level */
pOBInit->RDPLevel = FLASH_OB_GetRDP();
@ -340,9 +423,17 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
/* Get the user option bytes */
pOBInit->USERConfig = FLASH_OB_GetUser();
/* Get the Proprietary code readout protection */
FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr));
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
if((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2))
#else
if(pOBInit->PCROPConfig == FLASH_BANK_1)
#endif
{
pOBInit->OptionType |= OPTIONBYTE_PCROP;
/* Get the Proprietary code readout protection */
FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr));
}
}
/**
@ -369,22 +460,25 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
*/
static void FLASH_MassErase(uint32_t Banks)
{
/* Check the parameters */
assert_param(IS_FLASH_BANK(Banks));
{
/* Check the parameters */
assert_param(IS_FLASH_BANK(Banks));
/* Set the Mass Erase Bit for the bank 1 if requested */
if((Banks & FLASH_BANK_1) != RESET)
{
SET_BIT(FLASH->CR, FLASH_CR_MER1);
}
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
/* Set the Mass Erase Bit for the bank 2 if requested */
if((Banks & FLASH_BANK_2) != RESET)
{
SET_BIT(FLASH->CR, FLASH_CR_MER2);
}
/* Set the Mass Erase Bit for the bank 1 if requested */
if((Banks & FLASH_BANK_1) != RESET)
{
SET_BIT(FLASH->CR, FLASH_CR_MER1);
}
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
/* Set the Mass Erase Bit for the bank 2 if requested */
if((Banks & FLASH_BANK_2) != RESET)
{
SET_BIT(FLASH->CR, FLASH_CR_MER2);
}
#endif
}
/* Proceed to erase all sectors */
SET_BIT(FLASH->CR, FLASH_CR_STRT);
@ -395,7 +489,7 @@ static void FLASH_MassErase(uint32_t Banks)
* @param Page: FLASH page to erase
* This parameter must be a value between 0 and (max number of pages in the bank - 1)
* @param Banks: Bank(s) where the page will be erased
* This parameter can be one or a combination of the following values:
* This parameter can be one of the following values:
* @arg FLASH_BANK_1: Page in bank 1 to be erased
* @arg FLASH_BANK_2: Page in bank 2 to be erased
* @retval None
@ -404,21 +498,25 @@ void FLASH_PageErase(uint32_t Page, uint32_t Banks)
{
/* Check the parameters */
assert_param(IS_FLASH_PAGE(Page));
assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
if((Banks & FLASH_BANK_1) != RESET)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
{
CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
}
else
{
SET_BIT(FLASH->CR, FLASH_CR_BKER);
assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
if((Banks & FLASH_BANK_1) != RESET)
{
CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
}
else
{
SET_BIT(FLASH->CR, FLASH_CR_BKER);
}
}
#endif
/* Proceed to erase the page */
MODIFY_REG(FLASH->CR, FLASH_CR_PNB, (Page << 3));
MODIFY_REG(FLASH->CR, FLASH_CR_PNB, (Page << POSITION_VAL(FLASH_CR_PNB)));
SET_BIT(FLASH->CR, FLASH_CR_PER);
SET_BIT(FLASH->CR, FLASH_CR_STRT);
}
@ -430,10 +528,9 @@ void FLASH_PageErase(uint32_t Page, uint32_t Banks)
void FLASH_FlushCaches(void)
{
/* Flush instruction cache */
if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
if((pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_ENABLED) ||
(pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
{
/* Disable instruction cache */
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
/* Reset instruction cache */
__HAL_FLASH_INSTRUCTION_CACHE_RESET();
/* Enable instruction cache */
@ -441,15 +538,17 @@ void FLASH_FlushCaches(void)
}
/* Flush data cache */
if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
if((pFlash.CacheToReactivate == FLASH_CACHE_DCACHE_ENABLED) ||
(pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
{
/* Disable data cache */
__HAL_FLASH_DATA_CACHE_DISABLE();
/* Reset data cache */
__HAL_FLASH_DATA_CACHE_RESET();
/* Enable data cache */
__HAL_FLASH_DATA_CACHE_ENABLE();
}
/* Reset internal variable */
pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
}
/**
@ -504,7 +603,8 @@ static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartO
MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END),
(WRPStartOffset | (WRDPEndOffset << 16)));
}
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
{
MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END),
@ -686,7 +786,8 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon
optr_reg_mask |= FLASH_OPTR_WWDG_SW;
}
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
if((UserType & OB_USER_BFB2) != RESET)
{
/* BFB2 option byte should be modified */
@ -738,7 +839,9 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon
optr_reg_mask |= FLASH_OPTR_SRAM2_RST;
}
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
if((UserType & OB_USER_nSWBOOT0) != RESET)
{
/* nSWBOOT0 option byte should be modified */
@ -801,7 +904,8 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR
HAL_StatusTypeDef status = HAL_OK;
uint32_t reg_value = 0;
uint32_t bank1_addr;
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
uint32_t bank2_addr;
#endif
@ -816,7 +920,8 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR
if(status == HAL_OK)
{
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
/* Get the information about the bank swapping */
if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
{
@ -832,25 +937,28 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR
bank1_addr = FLASH_BASE;
#endif
/* Configure the Proprietary code readout protection */
if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
{
reg_value = ((PCROPStartAddr - bank1_addr) >> 3);
MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
reg_value = ((PCROPEndAddr - bank1_addr) >> 3);
MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
}
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
{
reg_value = ((PCROPStartAddr - bank2_addr) >> 3);
MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
reg_value = ((PCROPEndAddr - bank2_addr) >> 3);
MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
}
/* Configure the Proprietary code readout protection */
if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
{
reg_value = ((PCROPStartAddr - bank1_addr) >> 3);
MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
reg_value = ((PCROPEndAddr - bank1_addr) >> 3);
MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
}
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
{
reg_value = ((PCROPStartAddr - bank2_addr) >> 3);
MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
reg_value = ((PCROPEndAddr - bank2_addr) >> 3);
MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
}
#endif
}
MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
@ -887,9 +995,6 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR
*/
static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset)
{
/* Check the parameters */
assert_param(IS_OB_WRPAREA(WRPArea));
/* Get the configuration of the write protected area */
if(WRPArea == OB_WRPAREA_BANK1_AREAA)
{
@ -901,7 +1006,8 @@ static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_
*WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
*WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16);
}
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
{
*WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);
@ -975,14 +1081,13 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr,
{
uint32_t reg_value = 0;
uint32_t bank1_addr;
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
uint32_t bank2_addr;
#endif
/* Check the parameters */
assert_param(IS_FLASH_BANK_EXCLUSIVE((*PCROPConfig) & FLASH_BANK_BOTH));
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
/* Get the information about the bank swapping */
if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
{
@ -998,24 +1103,27 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr,
bank1_addr = FLASH_BASE;
#endif
if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
{
reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
*PCROPStartAddr = (reg_value << 3) + bank1_addr;
reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
*PCROPEndAddr = (reg_value << 3) + bank1_addr;
}
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
{
reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
*PCROPStartAddr = (reg_value << 3) + bank2_addr;
reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
*PCROPEndAddr = (reg_value << 3) + bank2_addr;
}
if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
{
reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
*PCROPStartAddr = (reg_value << 3) + bank1_addr;
reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
*PCROPEndAddr = (reg_value << 3) + bank1_addr;
}
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
{
reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
*PCROPStartAddr = (reg_value << 3) + bank2_addr;
reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
*PCROPEndAddr = (reg_value << 3) + bank2_addr;
}
#endif
}
*PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP);
}

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_flash_ex.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of FLASH HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

8
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_flash_ramfunc.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief FLASH RAMFUNC driver.
* This file provides a Flash firmware functions which should be
* executed from internal SRAM
@ -37,7 +37,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -82,6 +82,8 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
extern FLASH_ProcessTypeDef pFlash;
/* Private function prototypes -----------------------------------------------*/
/* Exported functions -------------------------------------------------------*/

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_flash_ramfunc.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_gpio.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
@ -93,7 +93,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

9
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_gpio.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -231,7 +231,8 @@ typedef enum
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) (((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00)
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\
(((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00))
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\

381
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_gpio_ex.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of GPIO HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -65,6 +65,243 @@
* @{
*/
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
/*--------------STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx---*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#if defined(STM32L433xx) || defined(STM32L443xx)
#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
#endif /* STM32L433xx || STM32L443xx */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART1 Alternate Function mapping */
#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */
#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */
/**
* @brief AF 4 selection
*/
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define GPIO_AF6_COMP1 ((uint8_t)0x06) /* COMP1 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */
/**
* @brief AF 10 selection
*/
#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
#define GPIO_AF10_USB_FS ((uint8_t)0x0A) /* USB_FS Alternate Function mapping */
#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */
#if defined(STM32L433xx) || defined(STM32L443xx)
/**
* @brief AF 11 selection
*/
#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */
#endif /* STM32L433xx || STM32L443xx */
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_SWPMI1 ((uint8_t)0x0C) /* SWPMI1 Alternate Function mapping */
#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
/**
* @brief AF 13 selection
*/
#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
/**
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
/*--------------STM32L451xx/STM32L452xx/STM32L462xx---------------------------*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_I2C4 ((uint8_t)0x02) /* I2C4 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */
#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */
#define GPIO_AF3_CAN1 ((uint8_t)0x03) /* CAN1 Alternate Function mapping */
#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */
/**
* @brief AF 4 selection
*/
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */
#define GPIO_AF6_COMP1 ((uint8_t)0x06) /* COMP1 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */
/**
* @brief AF 10 selection
*/
#if defined(STM32L452xx) || defined(STM32L462xx)
#define GPIO_AF10_USB_FS ((uint8_t)0x0A) /* USB_FS Alternate Function mapping */
#endif /* STM32L452xx || STM32L462xx */
#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */
#define GPIO_AF10_CAN1 ((uint8_t)0x0A) /* CAN1 Alternate Function mapping */
/**
* @brief AF 11 selection
*/
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
/**
* @brief AF 13 selection
*/
#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
/**
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
/*--------------STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx/STM32L486xx---*/
/**
@ -148,64 +385,61 @@
* @brief AF 10 selection
*/
#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */
#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */
#if defined(STM32L476xx) || defined(STM32L486xx)
/**
* @brief AF 11 selection
*/
#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */
#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */
#endif /* STM32L476xx || STM32L486xx */
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
#define GPIO_AF12_SWPMI1 ((uint8_t)0xC) /* SWPMI1 Alternate Function mapping */
#define GPIO_AF12_COMP1 ((uint8_t)0xC) /* COMP1 Alternate Function mapping */
#define GPIO_AF12_COMP2 ((uint8_t)0xC) /* COMP2 Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */
#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
#define GPIO_AF12_SWPMI1 ((uint8_t)0x0C) /* SWPMI1 Alternate Function mapping */
#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
/**
* @brief AF 13 selection
*/
#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */
#define GPIO_AF13_TIM8_COMP2 ((uint8_t)0x0D) /* TIM8/COMP2 Break in Alternate Function mapping */
#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */
#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */
#define GPIO_AF13_TIM8_COMP2 ((uint8_t)0x0D) /* TIM8/COMP2 Break in Alternate Function mapping */
#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF14_TIM8_COMP1 ((uint8_t)0x0E) /* TIM8/COMP1 Break in Alternate Function mapping */
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF14_TIM8_COMP1 ((uint8_t)0x0E) /* TIM8/COMP1 Break in Alternate Function mapping */
/**
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
/*--------------STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx---*/
#if defined(STM32L496xx) || defined(STM32L4A6xx)
/*--------------------------------STM32L496xx/STM32L4A6xx---------------------*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#if defined(STM32L433xx) || defined(STM32L443xx)
#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
#endif /* STM32L433xx || STM32L443xx */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
/**
@ -213,6 +447,8 @@
*/
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
@ -221,13 +457,22 @@
*/
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define GPIO_AF2_I2C4 ((uint8_t)0x02) /* I2C4 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART1 Alternate Function mapping */
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */
#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF3_CAN2 ((uint8_t)0x03) /* CAN2 Alternate Function mapping */
#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */
#define GPIO_AF3_QUADSPI ((uint8_t)0x03) /* QUADSPI Alternate Function mapping */
#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */
#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */
/**
* @brief AF 4 selection
@ -235,18 +480,24 @@
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */
#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */
#define GPIO_AF5_QUADSPI ((uint8_t)0x05) /* QUADSPI Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define GPIO_AF6_COMP1 ((uint8_t)0x06) /* COMP1 Alternate Function mapping */
#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */
#define GPIO_AF6_I2C3 ((uint8_t)0x06) /* I2C3 Alternate Function mapping */
/**
* @brief AF 7 selection
@ -258,58 +509,68 @@
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
#define GPIO_AF8_CAN2 ((uint8_t)0x08) /* CAN2 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */
/**
* @brief AF 10 selection
*/
#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
#define GPIO_AF10_USB_FS ((uint8_t)0xA) /* USB_FS Alternate Function mapping */
#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */
#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */
#define GPIO_AF10_CAN2 ((uint8_t)0x0A) /* CAN2 Alternate Function mapping */
#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */
#if defined(STM32L433xx) || defined(STM32L443xx)
/**
* @brief AF 11 selection
*/
#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */
#endif /* STM32L433xx || STM32L443xx */
#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_SWPMI1 ((uint8_t)0xC) /* SWPMI1 Alternate Function mapping */
#define GPIO_AF12_COMP1 ((uint8_t)0xC) /* COMP1 Alternate Function mapping */
#define GPIO_AF12_COMP2 ((uint8_t)0xC) /* COMP2 Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */
#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
#define GPIO_AF12_SWPMI1 ((uint8_t)0x0C) /* SWPMI1 Alternate Function mapping */
#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */
/**
* @brief AF 13 selection
*/
#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */
#define GPIO_AF13_TIM8_COMP2 ((uint8_t)0x0D) /* TIM8/COMP2 Break in Alternate Function mapping */
#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF14_TIM8_COMP1 ((uint8_t)0x0E) /* TIM8/COMP1 Break in Alternate Function mapping */
/**
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
#endif /* STM32L496xx || STM32L4A6xx */
/**
* @}
@ -345,6 +606,16 @@
#endif /* STM32L432xx || STM32L442xx */
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :\
((__GPIOx__) == (GPIOD))? 3U :\
((__GPIOx__) == (GPIOE))? 4U : 7U)
#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
@ -357,6 +628,20 @@
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
#if defined(STM32L496xx) || defined(STM32L4A6xx)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :\
((__GPIOx__) == (GPIOD))? 3U :\
((__GPIOx__) == (GPIOE))? 4U :\
((__GPIOx__) == (GPIOF))? 5U :\
((__GPIOx__) == (GPIOG))? 6U :\
((__GPIOx__) == (GPIOH))? 7U : 8U)
#endif /* STM32L496xx || STM32L4A6xx */
/**
* @}
*/

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@ -0,0 +1,582 @@
/**
******************************************************************************
* @file stm32l4xx_hal_hash.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_HASH_H
#define __STM32L4xx_HAL_HASH_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined (STM32L4A6xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup HASH
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup HASH_Exported_Types HASH Exported Types
* @{
*/
/**
* @brief HASH Configuration Structure definition
*/
typedef struct
{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data.
This parameter can be a value of @ref HASH_Data_Type. */
uint32_t KeySize; /*!< The key size is used only in HMAC operation. */
uint8_t* pKey; /*!< The key is used only in HMAC operation. */
} HASH_InitTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_HASH_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
HAL_HASH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
HAL_HASH_STATE_BUSY = 0x02, /*!< Processing (hashing) is ongoing */
HAL_HASH_STATE_TIMEOUT = 0x06, /*!< Timeout state */
HAL_HASH_STATE_ERROR = 0x07, /*!< Error state */
HAL_HASH_STATE_SUSPENDED = 0x08 /*!< Suspended state */
}HAL_HASH_StateTypeDef;
/**
* @brief HAL phase structures definition
*/
typedef enum
{
HAL_HASH_PHASE_READY = 0x01, /*!< HASH peripheral is ready to start */
HAL_HASH_PHASE_PROCESS = 0x02, /*!< HASH peripheral is in HASH processing phase */
HAL_HASH_PHASE_HMAC_STEP_1 = 0x03, /*!< HASH peripheral is in HMAC step 1 processing phase
(step 1 consists in entering the inner hash function key) */
HAL_HASH_PHASE_HMAC_STEP_2 = 0x04, /*!< HASH peripheral is in HMAC step 2 processing phase
(step 2 consists in entering the message text) */
HAL_HASH_PHASE_HMAC_STEP_3 = 0x05 /*!< HASH peripheral is in HMAC step 3 processing phase
(step 3 consists in entering the outer hash function key) */
}HAL_HASH_PhaseTypeDef;
/**
* @brief HAL HASH mode suspend definitions
*/
typedef enum
{
HAL_HASH_SUSPEND_NONE = 0x00, /*!< HASH peripheral suspension not requested */
HAL_HASH_SUSPEND = 0x01 /*!< HASH peripheral suspension is requested */
}HAL_HASH_SuspendTypeDef;
/**
* @brief HASH Handle Structure definition
*/
typedef struct
{
HASH_InitTypeDef Init; /*!< HASH required parameters */
uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
uint32_t HashBuffSize; /*!< Size of buffer to be processed */
__IO uint32_t HashInCount; /*!< Counter of inputted data */
__IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
__IO uint32_t HashKeyCount; /*!< Counter for Key inputted data (HMAC only) */
HAL_StatusTypeDef Status; /*!< HASH peripheral status */
HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */
DMA_HandleTypeDef *hdmain; /*!< HASH In DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */
HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */
FlagStatus DigestCalculationDisable; /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */
__IO uint32_t NbWordsAlreadyPushed; /*!< Numbers of words already pushed in FIFO before inputting new block */
} HASH_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HASH_Exported_Constants HASH Exported Constants
* @{
*/
/** @defgroup HASH_Algo_Selection HASH algorithm selection
* @{
*/
#define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */
#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
/**
* @}
*/
/** @defgroup HASH_Algorithm_Mode HASH algorithm mode
* @{
*/
#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */
#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
/**
* @}
*/
/** @defgroup HASH_Data_Type HASH input data type
* @{
*/
#define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */
#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
/**
* @}
*/
/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode HMAC key length type
* @{
*/
#define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000) /*!< HMAC Key size is <= 64 bytes */
#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > 64 bytes */
/**
* @}
*/
/** @defgroup HASH_flags_definition HASH flags definitions
* @{
*/
#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
/**
* @}
*/
/** @defgroup HASH_interrupts_definition HASH interrupts definitions
* @{
*/
#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
/**
* @}
*/
/** @defgroup HASH_alias HASH API alias
* @{
*/
#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup HASH_Exported_Macros HASH Exported Macros
* @{
*/
/** @brief Check whether or not the specified HASH flag is set.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
* @arg @ref HASH_FLAG_DCIS Digest calculation complete.
* @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
* @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
* @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \
((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
((HASH->SR & (__FLAG__)) == (__FLAG__)) )
/** @brief Clear the specified HASH flag.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
* @arg @ref HASH_FLAG_DCIS Digest calculation complete
* @retval None
*/
#define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
/** @brief Enable the specified HASH interrupt.
* @param __INTERRUPT__: specifies the HASH interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
* @arg @ref HASH_IT_DCI Digest calculation complete
* @retval None
*/
#define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
/** @brief Disable the specified HASH interrupt.
* @param __INTERRUPT__: specifies the HASH interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
* @arg @ref HASH_IT_DCI Digest calculation complete
* @retval None
*/
#define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
/** @brief Reset HASH handle state.
* @param __HANDLE__: HASH handle.
* @retval None
*/
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
/** @brief Reset HASH handle status.
* @param __HANDLE__: HASH handle.
* @retval None
*/
#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
/**
* @brief Enable the multi-buffer DMA transfer mode.
* @note This bit is set when hashing large files when multiple DMA transfers are needed.
* @retval None
*/
#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT)
/**
* @brief Disable the multi-buffer DMA transfer mode.
* @retval None
*/
#define __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
/**
* @brief Start the digest computation.
* @retval None
*/
#define __HAL_HASH_START_DIGEST() SET_BIT(HASH->STR, HASH_STR_DCAL)
/**
* @brief Set the number of valid bits in the last word written in data register DIN.
* @param __SIZE__: size in bytes of last data written in Data register.
* @retval None
*/
#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * ((__SIZE__) % 4))
/**
* @brief Reset the HASH core.
* @retval None
*/
#define __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup HASH_Private_Macros HASH Private Macros
* @{
*/
/**
* @brief Return digest length in bytes.
* @retval Digest length
*/
#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20 : \
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28 : \
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32 : 16 ) ) )
/**
* @brief Return number of words already pushed in the FIFO.
* @retval Number of words already pushed in the FIFO
*/
#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8)
/**
* @brief Ensure that HASH input data type is valid.
* @param __DATATYPE__: HASH input data type.
* @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
*/
#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
((__DATATYPE__) == HASH_DATATYPE_16B)|| \
((__DATATYPE__) == HASH_DATATYPE_8B) || \
((__DATATYPE__) == HASH_DATATYPE_1B))
/**
* @brief Ensure that input data buffer size is valid for multi-buffer HASH
* processing in polling mode.
* @note This check is valid only for multi-buffer HASH processing in polling mode.
* @param __SIZE__: input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4) == 0)
/**
* @brief Ensure that input data buffer size is valid for multi-buffer HASH
* processing in DMA mode.
* @note This check is valid only for multi-buffer HASH processing in DMA mode.
* @param __SIZE__: input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == RESET) || (((__SIZE__) % 4) == 0))
/**
* @brief Ensure that input data buffer size is valid for multi-buffer HMAC
* processing in DMA mode.
* @note This check is valid only for multi-buffer HMAC processing in DMA mode.
* @param __HANDLE__: HASH handle.
* @param __SIZE__: input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4) == 0))
/**
* @brief Ensure that handle phase is set to HASH processing.
* @param __HANDLE__: HASH handle.
* @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
*/
#define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
/**
* @brief Ensure that handle phase is set to HMAC processing.
* @param __HANDLE__: HASH handle.
* @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
*/
#define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \
((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
/**
* @}
*/
/* Include HASH HAL Extended module */
#include "stm32l4xx_hal_hash_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HASH_Exported_Functions HASH Exported Functions
* @{
*/
/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization methods **********************************/
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
/**
* @}
*/
/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
* @{
*/
/* HASH processing using polling *********************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
* @{
*/
/* HASH processing using IT **************************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
/**
* @}
*/
/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
* @{
*/
/* HASH processing using DMA *************************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
/**
* @}
*/
/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
* @{
*/
/* HASH-MAC processing using polling *****************************************/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
/**
* @}
*/
/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
* @{
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
/**
* @}
*/
/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
* @{
*/
/* HASH-HMAC processing using DMA ********************************************/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions
* @{
*/
/* Peripheral State methods **************************************************/
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
/**
* @}
*/
/**
* @}
*/
/* Private functions -----------------------------------------------------------*/
/** @addtogroup HASH_Private_Functions HASH Private Functions
* @{
*/
/* Private functions */
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (STM32L4A6xx) */
#ifdef __cplusplus
}
#endif
#endif /* __STM32L4xx_HAL_HASH_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32l4xx_hal_hash_ex.c
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @brief Extended HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral for SHA-224 and SHA-256
* alogrithms:
* + HASH or HMAC processing in polling mode
* + HASH or HMAC processing in interrupt mode
* + HASH or HMAC processing in DMA mode
* Additionally, this file provides functions to manage HMAC
* multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224
* and SHA-256.
*
*
@verbatim
===============================================================================
##### HASH peripheral extended features #####
===============================================================================
[..]
The SHA-224 and SHA-256 HASH and HMAC processing can be carried out exactly
the same way as for SHA-1 or MD-5 algorithms.
(#) Three modes are available.
(##) Polling mode: processing APIs are blocking functions
i.e. they process the data and wait till the digest computation is finished,
e.g. HAL_HASHEx_xxx_Start()
(##) Interrupt mode: processing APIs are not blocking functions
i.e. they process the data under interrupt,
e.g. HAL_HASHEx_xxx_Start_IT()
(##) DMA mode: processing APIs are not blocking functions and the CPU is
not used for data transfer i.e. the data transfer is ensured by DMA,
e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to
HAL_HASHEx_xxx_Finish() is then required to retrieve the digest.
(#)Multi-buffer processing is possible in polling and DMA mode.
(##) In polling mode, only multi-buffer HASH processing is possible.
API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one.
User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as
well the computed digest.
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
(+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
From that point, each buffer can be fed to the IP thru HAL_HASHEx_xxx_Start_DMA() API.
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
macro then wrap-up the HASH processing in feeding the last input buffer thru the
same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
API HAL_HASHEx_xxx_Finish().
(+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to
extended functions): after initialization, the key and the first input buffer are entered
in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
starts step 2.
The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this
point, the HMAC processing is still carrying out step 2.
Then, step 2 for the last input buffer and step 3 are carried out by a single call
to HAL_HMACEx_xxx_Step2_3_DMA().
The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish() for
MD-5 and SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 and SHA-256.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
#ifdef HAL_HASH_MODULE_ENABLED
#if defined (STM32L4A6xx)
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup HASHEx HASHEx
* @brief HASH HAL extended module driver.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup HASHEx_Exported_Functions HASH Extended Exported Functions
* @{
*/
/** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
* @brief HASH extended processing functions using polling mode.
*
@verbatim
===============================================================================
##### Polling mode HASH extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in polling mode
the hash value using one of the following algorithms:
(+) SHA224
(++) HAL_HASHEx_SHA224_Start()
(++) HAL_HASHEx_SHA224_Accumulate()
(+) SHA256
(++) HAL_HASHEx_SHA256_Start()
(++) HAL_HASHEx_SHA256_Accumulate()
[..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
[..] In case of multi-buffer HASH processing (a single digest is computed while
several buffers are fed to the IP), the user can resort to successive calls
to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call
to HAL_HASHEx_xxx_Start().
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout: Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief If not already done, initialize the HASH peripheral in SHA224 mode then
* processes pInBuffer.
* @note Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed
* several input buffers back-to-back to the IP that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASHEx_SHA224_Start().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the IP has already been initialized.
* @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Start()
* to read it, feeding at the same time the last input buffer to the IP.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Start() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
}
/**
* @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout: Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
}
/**
* @brief If not already done, initialize the HASH peripheral in SHA256 mode then
* processes pInBuffer.
* @note Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed
* several input buffers back-to-back to the IP that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASHEx_SHA256_Start().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the IP has already been initialized.
* @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Start()
* to read it, feeding at the same time the last input buffer to the IP.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Start() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
/** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
* @brief HASH extended processing functions using interrupt mode.
*
@verbatim
===============================================================================
##### Interruption mode HASH extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in interrupt mode
the hash value using one of the following algorithms:
(+) SHA224
(++) HAL_HASHEx_SHA224_Start_IT()
(+) SHA256
(++) HAL_HASHEx_SHA256_Start_IT()
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
}
/**
* @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
/** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
* @brief HASH extended processing functions using DMA mode.
*
@verbatim
===============================================================================
##### DMA mode HASH extended processing functionss #####
===============================================================================
[..] This section provides functions allowing to calculate in DMA mode
the hash value using one of the following algorithms:
(+) SHA224
(++) HAL_HASHEx_SHA224_Start_DMA()
(++) HAL_HASHEx_SHA224_Finish()
(+) SHA256
(++) HAL_HASHEx_SHA256_Start_DMA()
(++) HAL_HASHEx_SHA256_Finish()
[..] When resorting to DMA mode to enter the data in the IP, user must resort
to HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with
HAL_HASHEx_xxx_Finish().
[..] In case of multi-buffer HASH processing, MDMAT bit must first be set before
the successive calls to HAL_HASHEx_xxx_Start_DMA(). Then, MDMAT bit needs to be
reset before the last call to HAL_HASHEx_xxx_Start_DMA(). Digest is finally
retrieved thanks to HAL_HASHEx_xxx_Finish().
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer
* to feed the input buffer to the IP.
* @note Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must
* be called to retrieve the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief Return the computed digest in SHA224 mode.
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in
* HMAC SHA224 mode.
* @param hhash: HASH handle.
* @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout: Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
{
return HASH_Finish(hhash, pOutBuffer, Timeout);
}
/**
* @brief Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer
* to feed the input buffer to the IP.
* @note Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must
* be called to retrieve the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
* @brief Return the computed digest in SHA256 mode.
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in
* HMAC SHA256 mode.
* @param hhash: HASH handle.
* @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout: Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
{
return HASH_Finish(hhash, pOutBuffer, Timeout);
}
/**
* @}
*/
/** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
* @brief HMAC extended processing functions using polling mode.
*
@verbatim
===============================================================================
##### Polling mode HMAC extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in polling mode
the HMAC value using one of the following algorithms:
(+) SHA224
(++) HAL_HMACEx_SHA224_Start()
(+) SHA256
(++) HAL_HMACEx_SHA256_Start()
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout: Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout: Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
/** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
* @brief HMAC extended processing functions using interruption mode.
*
@verbatim
===============================================================================
##### Interrupt mode HMAC extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in interrupt mode
the HMAC value using one of the following algorithms:
(+) SHA224
(++) HAL_HMACEx_SHA224_Start_IT()
(+) SHA256
(++) HAL_HMACEx_SHA256_Start_IT()
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
* read the computed digest in interrupt mode.
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
* read the computed digest in interrupt mode.
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
/** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
* @brief HMAC extended processing functions using DMA mode.
*
@verbatim
===============================================================================
##### DMA mode HMAC extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in DMA mode
the HMAC value using one of the following algorithms:
(+) SHA224
(++) HAL_HMACEx_SHA224_Start_DMA()
(+) SHA256
(++) HAL_HMACEx_SHA256_Start_DMA()
[..] When resorting to DMA mode to enter the data in the IP for HMAC processing,
user must resort to HAL_HMACEx_xxx_Start_DMA() then read the resulting digest
with HAL_HASHEx_xxx_Finish().
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
* DMA transfers to feed the key and the input buffer to the IP.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve
* the computed digest.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note If MDMAT bit is set before calling this function (multi-buffer
* HASH processing case), the input buffer size (in bytes) must be
* a multiple of 4 otherwise, the HASH digest computation is corrupted.
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
* DMA transfers to feed the key and the input buffer to the IP.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note If MDMAT bit is set before calling this function (multi-buffer
* HASH processing case), the input buffer size (in bytes) must be
* a multiple of 4 otherwise, the HASH digest computation is corrupted.
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
/** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
* @brief HMAC extended processing functions in multi-buffer DMA mode.
*
@verbatim
===============================================================================
##### Multi-buffer DMA mode HMAC extended processing functions #####
===============================================================================
[..] This section provides functions to manage HMAC multi-buffer
DMA-based processing for MD5, SHA1, SHA224 and SHA256 algorithms.
(+) MD5
(++) HAL_HMACEx_MD5_Step1_2_DMA()
(++) HAL_HMACEx_MD5_Step2_DMA()
(++) HAL_HMACEx_MD5_Step2_3_DMA()
(+) SHA1
(++) HAL_HMACEx_SHA1_Step1_2_DMA()
(++) HAL_HMACEx_SHA1_Step2_DMA()
(++) HAL_HMACEx_SHA1_Step2_3_DMA()
(+) SHA256
(++) HAL_HMACEx_SHA224_Step1_2_DMA()
(++) HAL_HMACEx_SHA224_Step2_DMA()
(++) HAL_HMACEx_SHA224_Step2_3_DMA()
(+) SHA256
(++) HAL_HMACEx_SHA256_Step1_2_DMA()
(++) HAL_HMACEx_SHA256_Step2_DMA()
(++) HAL_HMACEx_SHA256_Step2_3_DMA()
[..] User must first start-up the multi-buffer DMA-based HMAC computation in
calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
intiates step 2 with the first input buffer.
[..] The following buffers are next fed to the IP with a call to the API
HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls
to this API.
[..] Multi-buffer DMA-based HMAC computation is wrapped up by a call to
HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input
buffer to the IP then carries out step 3.
[..] Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or
SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256.
[..] If only two buffers need to be consecutively processed, a call to
HAL_HMACEx_xxx_Step1_2_DMA() followed by a call to HAL_HMACEx_xxx_Step2_3_DMA()
is sufficient.
@endverbatim
* @{
*/
/**
* @brief MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
* @note Step 1 consists in writing the inner hash function key in the IP,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
* the first buffer entered to the IP. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = SET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
* @brief MD5 HMAC step 2 in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
if (hhash->DigestCalculationDisable != SET)
{
return HAL_ERROR;
}
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
* @brief MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
* then carries out HMAC step 3.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = RESET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
* @brief SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
* @note Step 1 consists in writing the inner hash function key in the IP,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
* the first buffer entered to the IP. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = SET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
/**
* @brief SHA1 HMAC step 2 in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
if (hhash->DigestCalculationDisable != SET)
{
return HAL_ERROR;
}
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
/**
* @brief SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
* then carries out HMAC step 3.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = RESET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
/**
* @brief SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
* @note Step 1 consists in writing the inner hash function key in the IP,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
* the first buffer entered to the IP. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = SET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief SHA224 HMAC step 2 in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
if (hhash->DigestCalculationDisable != SET)
{
return HAL_ERROR;
}
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
* then carries out HMAC step 3.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = RESET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
* @note Step 1 consists in writing the inner hash function key in the IP,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
* the first buffer entered to the IP. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = SET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
* @brief SHA256 HMAC step 2 in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
if (hhash->DigestCalculationDisable != SET)
{
return HAL_ERROR;
}
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
* @brief SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
* then carries out HMAC step 3.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = RESET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (STM32L4A6xx) */
#endif /* HAL_HASH_MODULE_ENABLED */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

182
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.h Normal file
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@ -0,0 +1,182 @@
/**
******************************************************************************
* @file stm32l4xx_hal_hash_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_HASH_EX_H
#define __STM32L4xx_HAL_HASH_EX_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined (STM32L4A6xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup HASHEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HASHEx_Exported_Functions HASH Extended Exported Functions
* @{
*/
/** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
* @{
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
/** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
* @{
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
/**
* @}
*/
/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
* @{
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
/**
* @}
*/
/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
* @{
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
/**
* @}
*/
/** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
* @{
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
/**
* @}
*/
/** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
* @{
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
/** @addtogroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
* @{
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (STM32L4A6xx) */
#ifdef __cplusplus
}
#endif
#endif /* __STM32L4xx_HAL_HASH_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_hcd.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief HCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -42,7 +42,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -72,7 +72,8 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
/** @addtogroup STM32L4xx_HAL_Driver
* @{
@ -1277,6 +1278,7 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
* @}
*/
#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_hcd.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -43,7 +43,8 @@
extern "C" {
#endif
#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_ll_usb.h"
@ -250,7 +251,8 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
* @}
*/
#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx */
#ifdef __cplusplus
}

147
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_i2c.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
@ -88,16 +88,19 @@
*** Interrupt mode IO sequential operation ***
===================================
==============================================
[..]
(@) These interfaces allow to manage a sequential transfer with a repeated start condition
when a direction change during transfer
[..]
(+) A specific option field manage the different steps of a sequential transfer
(+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
(+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition
(++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition, an then permit a call the same master sequential interface
several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT())
(++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
and with new data to transfer if the direction change or manage only the new data to transfer
if no direction change and without a final stop condition in both cases
@ -115,8 +118,6 @@
(++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit
(+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive
(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
(+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
@ -212,7 +213,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -275,7 +276,7 @@
#define SlaveAddr_MSK 0x06U
/* Private define for @ref PreviousState usage */
#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */
#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
@ -293,6 +294,9 @@
#define I2C_XFER_ERROR_IT (0x00000011U)
#define I2C_XFER_CPLT_IT (0x00000012U)
#define I2C_XFER_RELOAD_IT (0x00000012U)
/* Private define Sequential Transfer Options default/reset value */
#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
/**
* @}
*/
@ -436,18 +440,17 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Configure I2Cx: Own Address1 and ack own address1 mode */
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
if(hi2c->Init.OwnAddress1 != 0U)
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
{
if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
}
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
@ -460,6 +463,9 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
@ -613,7 +619,8 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
* @brief Transmits in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
@ -736,7 +743,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
* @brief Receives in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
@ -747,7 +755,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
uint32_t tickstart = 0U;
if(hi2c->State == HAL_I2C_STATE_READY)
{
{
/* Process Locked */
__HAL_LOCK(hi2c);
@ -835,7 +843,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
return HAL_TIMEOUT;
}
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
@ -877,7 +885,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
}
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@ -958,9 +966,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Normal use case for Transmitter mode */
/* A NACK is generated to confirm the end of transfer */
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Normal use case for Transmitter mode */
/* A NACK is generated to confirm the end of transfer */
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
}
else
{
@ -1010,7 +1018,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
uint32_t tickstart = 0U;
if(hi2c->State == HAL_I2C_STATE_READY)
{
{
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
@ -1131,7 +1139,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
* @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@ -1199,7 +1208,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
* @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@ -1365,7 +1375,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
* @brief Transmit in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@ -1472,7 +1483,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
* @brief Receive in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@ -1655,7 +1667,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
}
/* Process Locked */
__HAL_LOCK(hi2c);
@ -1709,7 +1721,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
* @brief Write an amount of data in blocking mode to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@ -1860,7 +1873,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
* @brief Read an amount of data in blocking mode from a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@ -2003,7 +2017,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
* @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@ -2101,7 +2116,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
* @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@ -2198,7 +2214,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@ -2313,7 +2330,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
* @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@ -2428,7 +2446,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
* @note This function is used with Memory devices
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param Trials Number of trials
* @param Timeout Timeout duration
* @retval HAL status
@ -2545,7 +2564,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
@ -2610,7 +2630,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
@ -2685,7 +2706,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
if(hi2c->State == HAL_I2C_STATE_LISTEN)
if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
{
if((pData == NULL) || (Size == 0U))
{
@ -2697,6 +2718,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
/* Process Locked */
__HAL_LOCK(hi2c);
/* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
/* and then toggle the HAL slave RX state to TX state */
if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
{
/* Disable associated Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
}
hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
@ -2751,7 +2780,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
if(hi2c->State == HAL_I2C_STATE_LISTEN)
if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
{
if((pData == NULL) || (Size == 0U))
{
@ -2763,7 +2792,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u
/* Process Locked */
__HAL_LOCK(hi2c);
/* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
/* and then toggle the HAL slave TX state to RX state */
if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
/* Disable associated Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
}
hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@ -2861,7 +2898,8 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
* @brief Abort a master I2C IT or DMA process communication with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
@ -3039,7 +3077,7 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
* @brief Slave Address Match callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFEROPTIONS
* @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
* @param AddrMatchCode: Address Match Code
* @retval None
*/
@ -3240,7 +3278,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
/* Write data to TXDR */
hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
hi2c->XferSize--;
hi2c->XferCount--;
hi2c->XferCount--;
}
else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
{
@ -3578,7 +3616,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
* @brief Master sends target device address followed by internal memory address for write request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param Timeout Timeout duration
@ -3644,7 +3683,8 @@ return HAL_OK;
* @brief Master sends target device address followed by internal memory address for read request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param Timeout Timeout duration
@ -3719,6 +3759,9 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
uint16_t ownadd1code = 0U;
uint16_t ownadd2code = 0U;
/* Prevent unused argument(s) compilation warning */
UNUSED(ITFlags);
/* In case of Listen state, need to inform upper layer of address match code event */
if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
{
@ -4290,6 +4333,9 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma);
/* No specific action, Master fully manage the generation of STOP condition */
/* Mean that this generation can arrive at any time, at the end or during DMA process */
/* So STOP condition should be manage through Interrupt treatment */
@ -4344,6 +4390,9 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma);
/* No specific action, Master fully manage the generation of STOP condition */
/* Mean that this generation can arrive at any time, at the end or during DMA process */
/* So STOP condition should be manage through Interrupt treatment */

11
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_i2c.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -245,8 +245,8 @@ typedef struct __I2C_HandleTypeDef
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
* @{
*/
#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
@ -314,7 +314,7 @@ typedef struct __I2C_HandleTypeDef
* @}
*/
/** @defgroup I2C_XferDirection I2C Transfer Direction
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
* @{
*/
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
@ -658,6 +658,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
((REQUEST) == I2C_NO_STARTSTOP))
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME))

15
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_i2c_ex.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
@ -31,12 +31,12 @@
(++) HAL_I2CEx_DisableWakeUp()
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
(++) HAL_I2CEx_EnableFastModePlus()
(++) HAL_I2CEx_DisbleFastModePlus()
(++) HAL_I2CEx_DisableFastModePlus()
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -151,7 +151,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t
* @brief Configure I2C Digital noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
@ -238,7 +238,6 @@ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
}
}
/**
* @brief Disable I2C wakeup from stop mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@ -291,6 +290,8 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @retval None
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
@ -318,6 +319,8 @@ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @retval None
*/
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)

64
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_i2c_ex.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of I2C HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -50,7 +50,7 @@
* @{
*/
/** @addtogroup I2CEx I2CEx
/** @addtogroup I2CEx
* @{
*/
@ -64,7 +64,7 @@
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
* @{
*/
#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
@ -73,13 +73,28 @@
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{
*/
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
#else
#define I2C_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */
#define I2C_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */
#endif
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#if defined(SYSCFG_CFGR1_I2C2_FMP)
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
#else
#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */
#endif
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
#if defined(SYSCFG_CFGR1_I2C4_FMP)
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
#else
#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */
#endif
/**
* @}
*/
@ -124,22 +139,17 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
((FILTER) == I2C_ANALOGFILTER_DISABLE))
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#if defined (STM32L432xx) || defined (STM32L442xx)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))
#else
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))
#endif /* STM32L432xx || STM32L442xx */
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))
/**
* @}
*/

1670
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.c
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File diff suppressed because it is too large Load Diff

40
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_irda.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -159,7 +159,8 @@ typedef enum
HAL_IRDA_ERROR_NE = 0x02, /*!< Noise error */
HAL_IRDA_ERROR_FE = 0x04, /*!< frame error */
HAL_IRDA_ERROR_ORE = 0x08, /*!< Overrun error */
HAL_IRDA_ERROR_DMA = 0x10 /*!< DMA transfer error */
HAL_IRDA_ERROR_DMA = 0x10, /*!< DMA transfer error */
HAL_IRDA_ERROR_BUSY = 0x20 /*!< Busy Error */
}HAL_IRDA_ErrorTypeDef;
/**
@ -180,7 +181,7 @@ typedef enum
*/
typedef struct
{
USART_TypeDef *Instance; /*!< USART registers base address */
USART_TypeDef *Instance; /*!< IRDA registers base address */
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
@ -188,15 +189,15 @@ typedef struct
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
uint16_t TxXferCount; /* !<IRDA Tx Transfer Counter */
__IO uint16_t TxXferCount; /* !<IRDA Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
__IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
uint16_t Mask; /*!< USART RX RDR register mask */
uint16_t Mask; /*!< IRDA RX RDR register mask */
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
@ -346,7 +347,7 @@ typedef enum
#define IRDA_FLAG_RXNE ((uint32_t)0x00000020) /*!< IRDA Read data register not empty */
#define IRDA_FLAG_ORE ((uint32_t)0x00000008) /*!< IRDA Overrun error */
#define IRDA_FLAG_NE ((uint32_t)0x00000004) /*!< IRDA Noise error */
#define IRDA_FLAG_FE ((uint32_t)0x00000002) /*!< IRDA Noise error */
#define IRDA_FLAG_FE ((uint32_t)0x00000002) /*!< IRDA Framing error */
#define IRDA_FLAG_PE ((uint32_t)0x00000001) /*!< IRDA Parity error */
/**
* @}
@ -367,17 +368,7 @@ typedef enum
#define IRDA_IT_TC ((uint16_t)0x0626) /*!< IRDA Transmission complete interruption */
#define IRDA_IT_RXNE ((uint16_t)0x0525) /*!< IRDA Read data register not empty interruption */
#define IRDA_IT_IDLE ((uint16_t)0x0424) /*!< IRDA Idle interruption */
/* Elements values convention: 000000000XXYYYYYb
- YYYYY : Interrupt source position in the XX register (5bits)
- XX : Interrupt source register (2bits)
- 01: CR1 register
- 10: CR2 register
- 11: CR3 register */
#define IRDA_IT_ERR ((uint16_t)0x0060) /*!< IRDA Error interruption */
/* Elements values convention: 0000ZZZZ00000000b
- ZZZZ : Flag position in the ISR register(4bits) */
#define IRDA_IT_ORE ((uint16_t)0x0300) /*!< IRDA Overrun error interruption */
#define IRDA_IT_NE ((uint16_t)0x0200) /*!< IRDA Noise error interruption */
#define IRDA_IT_FE ((uint16_t)0x0100) /*!< IRDA Frame error interruption */
@ -801,12 +792,23 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda);
/**
* @}

96
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_irda_ex.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of IRDA HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -70,7 +70,7 @@
* @param __CLOCKSOURCE__: output variable.
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
*/
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
@ -292,6 +292,94 @@
} \
} \
} while(0)
#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART4CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_UART4CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART4CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} while(0)
#endif
/**

20
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_iwdg.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
@ -50,19 +50,19 @@
==============================================================================
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
(+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts downcounting.
(+) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
(++) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
IWDG_WINR.
(+) Configure the IWDG prescaler and counter reload value. This reload
(++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
(+) wait for status flags to be reset"
(+) Depending on window parameter:
(++) If Window Init parameter is same as Window register value,
(++) Wait for status flags to be reset
(++) Depending on window parameter:
(+++) If Window Init parameter is same as Window register value,
nothing more is done but reload counter value in order to exit
function withy exact time base.
(++) Else modify Window register. This will automatically reload
(+++) Else modify Window register. This will automatically reload
watchdog counter.
(#) Then the application program must refresh the IWDG counter at regular
@ -81,7 +81,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_iwdg.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

10
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_lcd.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief LCD Controller HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the LCD Controller (LCD) peripheral:
@ -70,7 +70,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -100,7 +100,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
#if defined(STM32L433xx) || defined(STM32L443xx) || defined(STM32L476xx) || defined(STM32L486xx)
#if defined(STM32L433xx) || defined(STM32L443xx) || defined(STM32L476xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
/** @addtogroup STM32L4xx_HAL_Driver
* @{
@ -620,7 +620,7 @@ HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd)
* @}
*/
#endif /* STM32L433xx || STM32L443xx || STM32L476xx || STM32L486xx */
#endif /* STM32L433xx || STM32L443xx || STM32L476xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

10
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_lcd.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of LCD Controller HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -43,7 +43,7 @@
extern "C" {
#endif
#if defined(STM32L433xx) || defined(STM32L443xx) || defined(STM32L476xx) || defined(STM32L486xx)
#if defined(STM32L433xx) || defined(STM32L443xx) || defined(STM32L476xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
@ -778,7 +778,7 @@ HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd);
* @}
*/
#endif /* STM32L433xx || STM32L443xx || STM32L476xx || STM32L486xx */
#endif /* STM32L433xx || STM32L443xx || STM32L476xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
#ifdef __cplusplus
}

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_lptim.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief LPTIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Low Power Timer (LPTIM) peripheral:
@ -96,7 +96,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_lptim.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of LPTIM HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

12
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_nand.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
@ -55,7 +55,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -85,7 +85,8 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
/** @addtogroup STM32L4xx_HAL_Driver
* @{
@ -1125,6 +1126,7 @@ static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTyp
* @}
*/
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx || */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_nand.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -43,7 +43,8 @@
extern "C" {
#endif
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_ll_fmc.h"
@ -294,7 +295,8 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
* @}
*/
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx || */
#ifdef __cplusplus
}

12
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_nor.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
@ -55,7 +55,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -85,7 +85,8 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
/** @addtogroup STM32L4xx_HAL_Driver
* @{
@ -1060,6 +1061,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
* @}
*/
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx || */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_nor.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -43,7 +43,8 @@
extern "C" {
#endif
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_ll_fmc.h"
@ -290,7 +291,8 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
* @}
*/
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx || */
#ifdef __cplusplus
}

12
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_opamp.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief OPAMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the operational amplifier(s) peripheral:
@ -180,7 +180,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -447,11 +447,11 @@ HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
/* Update the OPAMP state*/
hopamp->State = HAL_OPAMP_STATE_RESET;
/* Process unlocked */
__HAL_UNLOCK(hopamp);
}
/* Process unlocked */
__HAL_UNLOCK(hopamp);
return status;
}

27
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_opamp.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of OPAMP HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -236,8 +236,6 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef;
#define OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */
#define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM /*!< User trimming */
#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
((TRIMMING) == OPAMP_TRIMMING_USER))
/**
* @}
*/
@ -302,26 +300,29 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef;
((INPUT) == OPAMP_PGA_MODE) || \
((INPUT) == OPAMP_FOLLOWER_MODE))
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
#define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
((INPUT) == OPAMP_INVERTINGINPUT_IO1))
#endif
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) ((INPUT) == OPAMP_INVERTINGINPUT_IO0)
#endif
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx STM32L451xx STM32L452xx STM32L462xx */
#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH))
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
#define IS_OPAMP_INVERTING_INPUT_PGA(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
((INPUT) == OPAMP_INVERTINGINPUT_IO1)|| \
((INPUT) == OPAMP_INVERTINGINPUT_CONNECT_NO))
#endif
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define IS_OPAMP_INVERTING_INPUT_PGA(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
((INPUT) == OPAMP_INVERTINGINPUT_CONNECT_NO))
#endif
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx STM32L451xx STM32L452xx STM32L462xx */
#define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \
((GAIN) == OPAMP_PGA_GAIN_4) || \

9
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_opamp_ex.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Extended OPAMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc)
@ -15,7 +15,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -67,7 +67,8 @@
* @{
*/
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
/** @addtogroup OPAMPEx_Exported_Functions_Group1
* @brief Extended operation functions

9
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_opamp_ex.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of OPAMP HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -61,7 +61,8 @@
* @{
*/
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
/* I/O operation functions *****************************************************/
/** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions

125
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_pcd.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -43,7 +43,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -84,14 +84,20 @@
#ifdef HAL_PCD_MODULE_ENABLED
#if defined(STM32L475xx) || defined(STM32L476xx) || \
defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L432xx) || defined(STM32L433xx) || \
defined(STM32L442xx) || defined(STM32L443xx)
#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/**
* USB_OTG_CORE VERSION ID
*/
#define USB_OTG_CORE_ID_310A 0x4F54310A
#define USB_OTG_CORE_ID_320A 0x4F54320A
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
* @{
@ -142,7 +148,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
uint32_t index = 0;
uint32_t index = 0U;
/* Check the PCD handle allocation */
if(hpcd == NULL)
@ -199,6 +205,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->OUT_ep[index].xfer_buff = 0;
hpcd->OUT_ep[index].xfer_len = 0;
}
/* Init Device */
USB_DevInit(hpcd->Instance, hpcd->Init);
@ -332,8 +339,8 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t index = 0, ep_intr = 0, epint = 0, epnum = 0;
uint32_t fifoemptymsk = 0, temp = 0;
uint32_t index = 0U, ep_intr = 0U, epint = 0U, epnum = 0U;
uint32_t fifoemptymsk = 0U, temp = 0U;
USB_OTG_EPTypeDef *ep = NULL;
uint32_t hclk = 80000000;
@ -359,40 +366,69 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
while ( ep_intr )
while (ep_intr)
{
if (ep_intr & 0x1)
{
epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
if (( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
if ((( (USBx_OUTEP(0)->DOEPINT & 0x8000) == 0)) )
/* setup/out transaction management for Core ID 310A */
if (USBx->GSNPSID == USB_OTG_CORE_ID_310A)
{
if(hpcd->Init.dma_enable == 1)
{
hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
if (!(USBx_OUTEP(0)->DOEPINT & (0x1 << 15)))
{
if (hpcd->Init.dma_enable == 1)
{
hpcd->OUT_ep[epnum].xfer_count =
hpcd->OUT_ep[epnum].maxpacket -
(USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
hpcd->OUT_ep[epnum].xfer_buff +=
hpcd->OUT_ep[epnum].maxpacket;
}
HAL_PCD_DataOutStageCallback(hpcd, epnum);
if (hpcd->Init.dma_enable == 1)
{
if (!epnum && !hpcd->OUT_ep[epnum].xfer_len)
{
/* this is ZLP, so prepare EP0 for next setup */
USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
}
}
}
HAL_PCD_DataOutStageCallback(hpcd, epnum);
if(hpcd->Init.dma_enable == 1)
/* Clear the SetPktRcvd flag*/
USBx_OUTEP(0)->DOEPINT |= (0x1 << 15) | (0x1 << 5);
}
else
{
if (hpcd->Init.dma_enable == 1)
{
if((epnum == 0) && (hpcd->OUT_ep[epnum].xfer_len == 0))
hpcd->OUT_ep[epnum].xfer_count =
hpcd->OUT_ep[epnum].maxpacket -
(USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
}
HAL_PCD_DataOutStageCallback(hpcd, epnum);
if (hpcd->Init.dma_enable == 1)
{
if (!epnum && !hpcd->OUT_ep[epnum].xfer_len)
{
/* this is ZLP, so prepare EP0 for next setup */
USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
}
}
}
}
/* Clear the SetPktRcvd flag*/
USBx_OUTEP(0)->DOEPINT |= 0x8020;
}
if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
{
/* Inform the upper layer that a setup packet is available */
@ -404,6 +440,14 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
}
#ifdef USB_OTG_DOEPINT_OTEPSPR
/* Clear Status Phase Received interrupt */
if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
}
#endif /* USB_OTG_DOEPINT_OTEPSPR */
}
epnum++;
ep_intr >>= 1;
@ -523,7 +567,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
{
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
USB_FlushTxFifo(hpcd->Instance , 0 );
USB_FlushTxFifo(hpcd->Instance , 0x10);
for (index = 0; index < hpcd->Init.dev_endpoints ; index++)
{
@ -540,7 +584,11 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
else
{
#ifdef USB_OTG_DOEPINT_OTEPSPR
USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM);
#else
USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
#endif /* USB_OTG_DOEPINT_OTEPSPR */
USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
}
@ -1360,7 +1408,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
USB_OTG_EPTypeDef *ep = NULL;
int32_t len = 0;
int32_t len = 0U;
uint32_t len32b = 0;
uint32_t fifoemptymsk = 0;
@ -1616,17 +1664,16 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
* @}
*/
/**
* @}
*/
#endif /* STM32L475xx || STM32L476xx || */
/* STM32L485xx || STM32L486xx || */
/* STM32L432xx || STM32L433xx || */
/* STM32L442xx || STM32L443xx */
#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
/* STM32L452xx || STM32L462xx || */
/* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx */
#endif /* HAL_PCD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}

31
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_pcd.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -43,10 +43,10 @@
extern "C" {
#endif
#if defined(STM32L475xx) || defined(STM32L476xx) || \
defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L432xx) || defined(STM32L433xx) || \
defined(STM32L442xx) || defined(STM32L443xx)
#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_ll_usb.h"
@ -839,8 +839,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
#endif /* USB */
#if defined(STM32L432xx) || defined(STM32L433xx) || \
defined(STM32L442xx) || defined(STM32L443xx)
#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
defined(STM32L452xx) || defined(STM32L462xx)
/** @defgroup PCD_Instance_definition PCD Instance definition
* @{
*/
@ -848,8 +849,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/**
* @}
*/
#endif /* STM32L432xx || STM32L433xx || */
/* STM32L442xx || STM32L443xx */
#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
/* STM32L452xx || STM32L462xx */
/**
* @}
@ -863,10 +864,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @}
*/
#endif /* STM32L475xx || STM32L476xx || */
/* STM32L485xx || STM32L486xx || */
/* STM32L432xx || STM32L433xx || */
/* STM32L442xx || STM32L443xx */
#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
/* STM32L452xx || STM32L462xx || */
/* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx */
#ifdef __cplusplus
}

25
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_pcd_ex.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief PCD Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -47,11 +47,10 @@
*/
#ifdef HAL_PCD_MODULE_ENABLED
#if defined(STM32L475xx) || defined(STM32L476xx) || \
defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L432xx) || defined(STM32L433xx) || \
defined(STM32L442xx) || defined(STM32L443xx)
#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
/** @defgroup PCDEx PCDEx
* @brief PCD Extended HAL module driver
@ -461,7 +460,7 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
return HAL_OK;
}
#endif /* USB_FS */
#endif /* USB */
/**
* @brief Send LPM message to user layer callback.
@ -512,10 +511,10 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m
* @}
*/
#endif /* STM32L475xx || STM32L476xx || */
/* STM32L485xx || STM32L486xx || */
/* STM32L432xx || STM32L433xx || */
/* STM32L442xx || STM32L443xx */
#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
/* STM32L452xx || STM32L462xx || */
/* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx */
#endif /* HAL_PCD_MODULE_ENABLED */

24
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_pcd_ex.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -43,10 +43,10 @@
extern "C" {
#endif
#if defined(STM32L475xx) || defined(STM32L476xx) || \
defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L432xx) || defined(STM32L433xx) || \
defined(STM32L442xx) || defined(STM32L443xx)
#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
@ -96,7 +96,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
uint16_t ep_addr,
uint16_t ep_kind,
uint32_t pmaadress);
#endif /* USB_FS */
#endif /* USB */
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
@ -121,10 +121,10 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
* @}
*/
#endif /* STM32L475xx || STM32L476xx || */
/* STM32L485xx || STM32L486xx || */
/* STM32L432xx || STM32L433xx || */
/* STM32L442xx || STM32L443xx */
#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
/* STM32L452xx || STM32L462xx || */
/* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx */
#ifdef __cplusplus
}

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_pwr.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_pwr.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

250
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_pwr_ex.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -57,11 +57,19 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#define PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_0|PWR_GPIO_BIT_1)
#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
#define PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_0|PWR_GPIO_BIT_1|PWR_GPIO_BIT_3)
#endif
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x00000003) /* PH0/PH1 */
#elif defined (STM32L496xx) || defined (STM32L4A6xx)
#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000FFFF) /* PH0..PH15 */
#endif
#if defined (STM32L496xx) || defined (STM32L4A6xx)
#define PWR_PORTI_AVAILABLE_PINS ((uint32_t)0x00000FFF) /* PI0..PI11 */
#endif
/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
* @{
@ -219,7 +227,7 @@ void HAL_PWREx_DisableBatteryCharging(void)
}
#if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(PWR_CR2_USV)
/**
* @brief Enable VDDUSB supply.
* @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
@ -239,9 +247,9 @@ void HAL_PWREx_DisableVddUSB(void)
{
CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
}
#endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#endif /* PWR_CR2_USV */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(PWR_CR2_IOSV)
/**
* @brief Enable VDDIO2 supply.
* @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.
@ -261,7 +269,7 @@ void HAL_PWREx_DisableVddIO2(void)
{
CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
}
#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#endif /* PWR_CR2_IOSV */
/**
@ -298,10 +306,10 @@ void HAL_PWREx_DisableInternalWakeUpLine(void)
* @note Even if a PUy bit to set is reserved, the other PUy bits entered as input
* parameter at the same time are set.
* @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
* to select the GPIO peripheral.
* (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
* @param GPIONumber: Specify the I/O pins numbers.
* This parameter can be one of the following values:
* PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
* PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
* I/O pins are available) or the logical OR of several of them to set
* several bits for a given port in a single API call.
* @retval HAL Status
@ -315,44 +323,58 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
{
case PWR_GPIO_A:
SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
break;
case PWR_GPIO_B:
SET_BIT(PWR->PUCRB, GPIONumber);
CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
break;
CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
break;
case PWR_GPIO_C:
SET_BIT(PWR->PUCRC, GPIONumber);
CLEAR_BIT(PWR->PDCRC, GPIONumber);
break;
#if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
CLEAR_BIT(PWR->PDCRC, GPIONumber);
break;
#if defined(GPIOD)
case PWR_GPIO_D:
SET_BIT(PWR->PUCRD, GPIONumber);
CLEAR_BIT(PWR->PDCRD, GPIONumber);
break;
case PWR_GPIO_E:
SET_BIT(PWR->PUCRE, GPIONumber);
CLEAR_BIT(PWR->PDCRE, GPIONumber);
CLEAR_BIT(PWR->PDCRD, GPIONumber);
break;
#endif
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(GPIOE)
case PWR_GPIO_E:
SET_BIT(PWR->PUCRE, GPIONumber);
CLEAR_BIT(PWR->PDCRE, GPIONumber);
break;
#endif
#if defined(GPIOF)
case PWR_GPIO_F:
SET_BIT(PWR->PUCRF, GPIONumber);
CLEAR_BIT(PWR->PDCRF, GPIONumber);
CLEAR_BIT(PWR->PDCRF, GPIONumber);
break;
#endif
#if defined(GPIOG)
case PWR_GPIO_G:
SET_BIT(PWR->PUCRG, GPIONumber);
CLEAR_BIT(PWR->PDCRG, GPIONumber);
CLEAR_BIT(PWR->PDCRG, GPIONumber);
break;
#endif
#endif
case PWR_GPIO_H:
SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
break;
#if defined (STM32L496xx) || defined (STM32L4A6xx)
CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
#else
CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
#endif
break;
#if defined(GPIOI)
case PWR_GPIO_I:
SET_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
break;
#endif
default:
return HAL_ERROR;
return HAL_ERROR;
}
return HAL_OK;
}
@ -364,10 +386,10 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
* @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input
* parameter at the same time are reset.
* @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
* to select the GPIO peripheral.
* (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
* @param GPIONumber: Specify the I/O pins numbers.
* This parameter can be one of the following values:
* PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
* PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
* I/O pins are available) or the logical OR of several of them to reset
* several bits for a given port in a single API call.
* @retval HAL Status
@ -380,37 +402,46 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber
switch (GPIO)
{
case PWR_GPIO_A:
CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
break;
case PWR_GPIO_B:
CLEAR_BIT(PWR->PUCRB, GPIONumber);
break;
break;
case PWR_GPIO_C:
CLEAR_BIT(PWR->PUCRC, GPIONumber);
break;
#if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
break;
#if defined(GPIOD)
case PWR_GPIO_D:
CLEAR_BIT(PWR->PUCRD, GPIONumber);
break;
#endif
#if defined(GPIOE)
case PWR_GPIO_E:
CLEAR_BIT(PWR->PUCRE, GPIONumber);
break;
#endif
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(GPIOF)
case PWR_GPIO_F:
CLEAR_BIT(PWR->PUCRF, GPIONumber);
break;
#endif
#if defined(GPIOG)
case PWR_GPIO_G:
CLEAR_BIT(PWR->PUCRG, GPIONumber);
break;
#endif
case PWR_GPIO_H:
#endif
case PWR_GPIO_H:
CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
break;
break;
#if defined(GPIOI)
case PWR_GPIO_I:
CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
break;
#endif
default:
return HAL_ERROR;
return HAL_ERROR;
}
return HAL_OK;
}
@ -429,10 +460,10 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber
* @note Even if a PDy bit to set is reserved, the other PDy bits entered as input
* parameter at the same time are set.
* @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
* to select the GPIO peripheral.
* (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
* @param GPIONumber: Specify the I/O pins numbers.
* This parameter can be one of the following values:
* PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
* PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
* I/O pins are available) or the logical OR of several of them to set
* several bits for a given port in a single API call.
* @retval HAL Status
@ -443,47 +474,61 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumbe
assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
switch (GPIO)
{
{
case PWR_GPIO_A:
SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
break;
case PWR_GPIO_B:
SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
CLEAR_BIT(PWR->PUCRB, GPIONumber);
break;
CLEAR_BIT(PWR->PUCRB, GPIONumber);
break;
case PWR_GPIO_C:
SET_BIT(PWR->PDCRC, GPIONumber);
CLEAR_BIT(PWR->PUCRC, GPIONumber);
break;
#if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
CLEAR_BIT(PWR->PUCRC, GPIONumber);
break;
#if defined(GPIOD)
case PWR_GPIO_D:
SET_BIT(PWR->PDCRD, GPIONumber);
CLEAR_BIT(PWR->PUCRD, GPIONumber);
break;
case PWR_GPIO_E:
SET_BIT(PWR->PDCRE, GPIONumber);
CLEAR_BIT(PWR->PUCRE, GPIONumber);
CLEAR_BIT(PWR->PUCRD, GPIONumber);
break;
#endif
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(GPIOE)
case PWR_GPIO_E:
SET_BIT(PWR->PDCRE, GPIONumber);
CLEAR_BIT(PWR->PUCRE, GPIONumber);
break;
#endif
#if defined(GPIOF)
case PWR_GPIO_F:
SET_BIT(PWR->PDCRF, GPIONumber);
CLEAR_BIT(PWR->PUCRF, GPIONumber);
CLEAR_BIT(PWR->PUCRF, GPIONumber);
break;
#endif
#if defined(GPIOG)
case PWR_GPIO_G:
SET_BIT(PWR->PDCRG, GPIONumber);
CLEAR_BIT(PWR->PUCRG, GPIONumber);
CLEAR_BIT(PWR->PUCRG, GPIONumber);
break;
#endif
#endif
case PWR_GPIO_H:
#if defined (STM32L496xx) || defined (STM32L4A6xx)
SET_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
#else
SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
break;
#endif
CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
break;
#if defined(GPIOI)
case PWR_GPIO_I:
SET_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
break;
#endif
default:
return HAL_ERROR;
return HAL_ERROR;
}
return HAL_OK;
}
@ -495,10 +540,10 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumbe
* @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
* parameter at the same time are reset.
* @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
* to select the GPIO peripheral.
* (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
* @param GPIONumber: Specify the I/O pins numbers.
* This parameter can be one of the following values:
* PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
* PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
* I/O pins are available) or the logical OR of several of them to reset
* several bits for a given port in a single API call.
* @retval HAL Status
@ -511,37 +556,50 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumb
switch (GPIO)
{
case PWR_GPIO_A:
CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
break;
case PWR_GPIO_B:
CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
break;
case PWR_GPIO_C:
CLEAR_BIT(PWR->PDCRC, GPIONumber);
break;
#if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
break;
#if defined(GPIOD)
case PWR_GPIO_D:
CLEAR_BIT(PWR->PDCRD, GPIONumber);
break;
#endif
#if defined(GPIOE)
case PWR_GPIO_E:
CLEAR_BIT(PWR->PDCRE, GPIONumber);
break;
#endif
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(GPIOF)
case PWR_GPIO_F:
CLEAR_BIT(PWR->PDCRF, GPIONumber);
break;
#endif
#if defined(GPIOG)
case PWR_GPIO_G:
CLEAR_BIT(PWR->PDCRG, GPIONumber);
break;
#endif
#endif
case PWR_GPIO_H:
CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
break;
#if defined (STM32L496xx) || defined (STM32L4A6xx)
CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
#else
CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
#endif
break;
#if defined(GPIOI)
case PWR_GPIO_I:
CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
break;
#endif
default:
return HAL_ERROR;
return HAL_ERROR;
}
return HAL_OK;
}
@ -602,7 +660,7 @@ void HAL_PWREx_DisableSRAM2ContentRetention(void)
#if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(PWR_CR2_PVME1)
/**
* @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
* @retval None
@ -620,10 +678,10 @@ void HAL_PWREx_DisablePVM1(void)
{
CLEAR_BIT(PWR->CR2, PWR_PVM_1);
}
#endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#endif /* PWR_CR2_PVME1 */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(PWR_CR2_PVME2)
/**
* @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
* @retval None
@ -641,7 +699,7 @@ void HAL_PWREx_DisablePVM2(void)
{
CLEAR_BIT(PWR->CR2, PWR_PVM_2);
}
#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#endif /* PWR_CR2_PVME2 */
/**
@ -708,7 +766,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
configure the corresponding EXTI line accordingly. */
switch (sConfigPVM->PVMType)
{
#if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(PWR_CR2_PVME1)
case PWR_PVM_1:
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
__HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
@ -739,9 +797,9 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
__HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
}
break;
#endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#endif /* PWR_CR2_PVME1 */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(PWR_CR2_PVME2)
case PWR_PVM_2:
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
__HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
@ -772,7 +830,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
__HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
}
break;
#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#endif /* PWR_CR2_PVME2 */
case PWR_PVM_3:
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
@ -1098,7 +1156,7 @@ void HAL_PWREx_PVD_PVM_IRQHandler(void)
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
}
/* Next, successively check PVMx exti flags */
#if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(PWR_CR2_PVME1)
if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET)
{
/* PWR PVM1 interrupt user callback */
@ -1107,8 +1165,8 @@ void HAL_PWREx_PVD_PVM_IRQHandler(void)
/* Clear PVM1 exti pending bit */
__HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
}
#endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET)
{
/* PWR PVM2 interrupt user callback */
@ -1117,7 +1175,7 @@ void HAL_PWREx_PVD_PVM_IRQHandler(void)
/* Clear PVM2 exti pending bit */
__HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
}
#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#endif /* PWR_CR2_PVME2 */
if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET)
{
/* PWR PVM3 interrupt user callback */
@ -1137,7 +1195,7 @@ void HAL_PWREx_PVD_PVM_IRQHandler(void)
}
#if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(PWR_CR2_PVME1)
/**
* @brief PWR PVM1 interrupt callback
* @retval None
@ -1148,9 +1206,9 @@ __weak void HAL_PWREx_PVM1Callback(void)
HAL_PWREx_PVM1Callback() API can be implemented in the user file
*/
}
#endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#endif /* PWR_CR2_PVME1 */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(PWR_CR2_PVME2)
/**
* @brief PWR PVM2 interrupt callback
* @retval None
@ -1161,7 +1219,7 @@ __weak void HAL_PWREx_PVM2Callback(void)
HAL_PWREx_PVM2Callback() API can be implemented in the user file
*/
}
#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#endif /* PWR_CR2_PVME2 */
/**
* @brief PWR PVM3 interrupt callback

125
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_pwr_ex.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of PWR HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -124,13 +124,12 @@ typedef struct
/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
* @{
*/
#if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(PWR_CR2_PVME1)
#define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
#define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
#endif /* PWR_CR2_PVME2 */
#define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
#define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */
/**
@ -210,16 +209,22 @@ typedef struct
#define PWR_GPIO_A 0x00000000 /*!< GPIO port A */
#define PWR_GPIO_B 0x00000001 /*!< GPIO port B */
#define PWR_GPIO_C 0x00000002 /*!< GPIO port C */
#if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(GPIOD_BASE)
#define PWR_GPIO_D 0x00000003 /*!< GPIO port D */
#endif
#if defined(GPIOE_BASE)
#define PWR_GPIO_E 0x00000004 /*!< GPIO port E */
#endif
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(GPIOF_BASE)
#define PWR_GPIO_F 0x00000005 /*!< GPIO port F */
#endif
#if defined(GPIOG_BASE)
#define PWR_GPIO_G 0x00000006 /*!< GPIO port G */
#endif
#define PWR_GPIO_H 0x00000007 /*!< GPIO port H */
#if defined(GPIOI_BASE)
#define PWR_GPIO_I 0x00000008 /*!< GPIO port I */
#endif
/**
* @}
*/
@ -227,12 +232,12 @@ typedef struct
/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
* @{
*/
#if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(PWR_CR2_PVME1)
#define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */
#endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
#define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */
#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#endif /* PWR_CR2_PVME2 */
#define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */
#define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */
/**
@ -242,12 +247,12 @@ typedef struct
/** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
* @{
*/
#if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(PWR_CR2_PVME1)
#define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /*!< Event line 35 Connected to the PVM1 EXTI Line */
#endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
#define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /*!< Event line 36 Connected to the PVM2 EXTI Line */
#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#endif /* PWR_CR2_PVME2 */
#define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /*!< Event line 37 Connected to the PVM3 EXTI Line */
#define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */
/**
@ -277,12 +282,12 @@ typedef struct
#define PWR_FLAG_REGLPF ((uint32_t)0x0049) /*!< Low-power regulator flag */
#define PWR_FLAG_VOSF ((uint32_t)0x004A) /*!< Voltage scaling flag */
#define PWR_FLAG_PVDO ((uint32_t)0x004B) /*!< Power Voltage Detector output flag */
#if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(PWR_CR2_PVME1)
#define PWR_FLAG_PVMO1 ((uint32_t)0x004C) /*!< Power Voltage Monitoring 1 output flag */
#endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
#define PWR_FLAG_PVMO2 ((uint32_t)0x004D) /*!< Power Voltage Monitoring 2 output flag */
#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#endif /* PWR_CR2_PVME2 */
#define PWR_FLAG_PVMO3 ((uint32_t)0x004E) /*!< Power Voltage Monitoring 3 output flag */
#define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /*!< Power Voltage Monitoring 4 output flag */
/**
@ -298,7 +303,7 @@ typedef struct
* @{
*/
#if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(PWR_CR2_PVME1)
/**
* @brief Enable the PVM1 Extended Interrupt Line.
* @retval None
@ -387,10 +392,10 @@ typedef struct
*/
#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
#endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#endif /* PWR_CR2_PVME1 */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(PWR_CR2_PVME2)
/**
* @brief Enable the PVM2 Extended Interrupt Line.
* @retval None
@ -479,7 +484,7 @@ typedef struct
*/
#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#endif /* PWR_CR2_PVME2 */
/**
@ -711,7 +716,8 @@ typedef struct
((PIN) == PWR_WAKEUP_PIN4_LOW) || \
((PIN) == PWR_WAKEUP_PIN5_LOW))
#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx)
#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
((TYPE) == PWR_PVM_2) ||\
((TYPE) == PWR_PVM_3) ||\
@ -722,11 +728,11 @@ typedef struct
((TYPE) == PWR_PVM_4))
#endif
#if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
#if defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
((TYPE) == PWR_PVM_3) ||\
((TYPE) == PWR_PVM_4))
#elif defined (STM32L431xx)
#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx)
#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\
((TYPE) == PWR_PVM_4))
#endif
@ -751,17 +757,8 @@ typedef struct
#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\
((GPIO) == PWR_GPIO_D) ||\
((GPIO) == PWR_GPIO_E) ||\
((GPIO) == PWR_GPIO_F) ||\
((GPIO) == PWR_GPIO_G) ||\
((GPIO) == PWR_GPIO_H))
#endif
#if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx)
#if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \
defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\
@ -773,6 +770,25 @@ typedef struct
((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\
((GPIO) == PWR_GPIO_H))
#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\
((GPIO) == PWR_GPIO_D) ||\
((GPIO) == PWR_GPIO_E) ||\
((GPIO) == PWR_GPIO_F) ||\
((GPIO) == PWR_GPIO_G) ||\
((GPIO) == PWR_GPIO_H))
#elif defined (STM32L496xx) || defined (STM32L4A6xx)
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\
((GPIO) == PWR_GPIO_D) ||\
((GPIO) == PWR_GPIO_E) ||\
((GPIO) == PWR_GPIO_F) ||\
((GPIO) == PWR_GPIO_G) ||\
((GPIO) == PWR_GPIO_H) ||\
((GPIO) == PWR_GPIO_I))
#endif
@ -794,15 +810,15 @@ typedef struct
uint32_t HAL_PWREx_GetVoltageRange(void);
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
void HAL_PWREx_DisableBatteryCharging(void);
#if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
void HAL_PWREx_DisableBatteryCharging(void);
#if defined(PWR_CR2_USV)
void HAL_PWREx_EnableVddUSB(void);
void HAL_PWREx_DisableVddUSB(void);
#endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#endif /* PWR_CR2_USV */
#if defined(PWR_CR2_IOSV)
void HAL_PWREx_EnableVddIO2(void);
void HAL_PWREx_DisableVddIO2(void);
#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#endif /* PWR_CR2_IOSV */
void HAL_PWREx_EnableInternalWakeUpLine(void);
void HAL_PWREx_DisableInternalWakeUpLine(void);
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
@ -813,14 +829,14 @@ void HAL_PWREx_EnablePullUpPullDownConfig(void);
void HAL_PWREx_DisablePullUpPullDownConfig(void);
void HAL_PWREx_EnableSRAM2ContentRetention(void);
void HAL_PWREx_DisableSRAM2ContentRetention(void);
#if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(PWR_CR2_PVME1)
void HAL_PWREx_EnablePVM1(void);
void HAL_PWREx_DisablePVM1(void);
#endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
void HAL_PWREx_EnablePVM2(void);
void HAL_PWREx_DisablePVM2(void);
#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#endif /* PWR_CR2_PVME2 */
void HAL_PWREx_EnablePVM3(void);
void HAL_PWREx_DisablePVM3(void);
void HAL_PWREx_EnablePVM4(void);
@ -837,16 +853,15 @@ void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
void HAL_PWREx_EnterSHUTDOWNMode(void);
void HAL_PWREx_PVD_PVM_IRQHandler(void);
#if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#if defined(PWR_CR2_PVME1)
void HAL_PWREx_PVM1Callback(void);
#endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
void HAL_PWREx_PVM2Callback(void);
#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
#endif /* PWR_CR2_PVME2 */
void HAL_PWREx_PVM3Callback(void);
void HAL_PWREx_PVM4Callback(void);
/**
* @}
*/

16
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_qspi.c
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief QSPI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the QuadSPI interface (QSPI).
@ -138,7 +138,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -213,7 +213,7 @@ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);
static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
/* Exported functions --------------------------------------------------------*/
@ -263,7 +263,9 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
@ -297,7 +299,9 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
if(status == HAL_OK)
{
/* Configure QSPI Clock Prescaler and Sample Shift */
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
((hqspi->Init.ClockPrescaler << POSITION_VAL(QUADSPI_CR_PRESCALER)) |
hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash));

34
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_qspi.h
* @author MCD Application Team
* @version V1.5.1
* @date 31-May-2016
* @version V1.7.1
* @date 21-April-2017
* @brief Header file of QSPI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -81,7 +81,9 @@ typedef struct
This parameter can be a value of @ref QSPI_ChipSelectHighTime */
uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
This parameter can be a value of @ref QSPI_ClockMode */
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
uint32_t FlashID; /* Specifies the Flash which will be used,
This parameter can be a value of @ref QSPI_Flash_Select */
uint32_t DualFlash; /* Specifies the Dual Flash Mode State
@ -113,11 +115,11 @@ typedef struct
QUADSPI_TypeDef *Instance; /* QSPI registers base address */
QSPI_InitTypeDef Init; /* QSPI communication parameters */
uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
__IO uint16_t TxXferSize; /* QSPI Tx Transfer size */
__IO uint16_t TxXferCount; /* QSPI Tx Transfer Counter */
__IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
__IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
__IO uint16_t RxXferSize; /* QSPI Rx Transfer size */
__IO uint16_t RxXferCount; /* QSPI Rx Transfer Counter */
__IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
__IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
__IO HAL_LockTypeDef Lock; /* Locking object */
__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
@ -246,7 +248,9 @@ typedef struct
* @}
*/
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
/** @defgroup QSPI_Flash_Select QSPI Flash Select
* @{
*/
@ -345,7 +349,9 @@ typedef struct
* @{
*/
#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
#endif
/**
@ -605,7 +611,9 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
((CLKMODE) == QSPI_CLOCK_MODE_3))
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
#define IS_QSPI_FLASH_ID(FLASH) (((FLASH) == QSPI_FLASH_ID_1) || \
((FLASH) == QSPI_FLASH_ID_2))
@ -650,7 +658,9 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
#else

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