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Updated TARGET_Cypress sub-tree for FUTURE_SEQUANA target: 

1. Complete set of HAL drivers for all peripherals of CY8C63xx PSoC chips.
2. Cypress PDL library updated to official 3.0.1 version.
3. Tree structure reorganized and cleaned up:
 + TARGET_Cypress
 +--+ TARGET_PSOC6+                  -> code & libs applicable to all PSoC 6 based devices
    +--+ TARGET_CY86XX               -> code & libs applicable to PSoC 63 based devices
    |  +--- TARGET_MCU_PSOC6_M0      -> code & libs applicable to PSoC6 Corted M0+ core
    |  +--- TARGET_MCU_PSOC6_M4      -> code & libs applicable to PSoC6 Corted M0F core
    |
    +--+ TARGET_FUTURE_SEQUANA       -> code applicable to Sequana board, both cores
       +--- TARGET_FUTURE_SEQUANA_M0 -> code applicable only to M0+ core on Sequana board
pull/8637/head
Leszek Rusinowicz 2018-10-22 14:08:05 +02:00 committed by Cruz Monrreal II
parent 5e629e428c
commit 24fcd69e1a
321 changed files with 29055 additions and 99359 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

109
targets/TARGET_Cypress/TARGET_PSOC6/PeripheralNames.h Normal file
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/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)SCB0_BASE,
UART_1 = (int)SCB1_BASE,
UART_2 = (int)SCB2_BASE,
UART_3 = (int)SCB3_BASE,
UART_4 = (int)SCB4_BASE,
UART_5 = (int)SCB5_BASE,
UART_6 = (int)SCB6_BASE,
UART_7 = (int)SCB7_BASE,
} UARTName;
typedef enum {
SPI_0 = (int)SCB0_BASE,
SPI_1 = (int)SCB1_BASE,
SPI_2 = (int)SCB2_BASE,
SPI_3 = (int)SCB3_BASE,
SPI_4 = (int)SCB4_BASE,
SPI_5 = (int)SCB5_BASE,
SPI_6 = (int)SCB6_BASE,
SPI_7 = (int)SCB7_BASE,
} SPIName;
typedef enum {
I2C_0 = (int)SCB0_BASE,
I2C_1 = (int)SCB1_BASE,
I2C_2 = (int)SCB2_BASE,
I2C_3 = (int)SCB3_BASE,
I2C_4 = (int)SCB4_BASE,
I2C_5 = (int)SCB5_BASE,
I2C_6 = (int)SCB6_BASE,
I2C_7 = (int)SCB7_BASE,
} I2CName;
typedef enum {
PWM_32b_0 = TCPWM0_BASE,
PWM_32b_1,
PWM_32b_2,
PWM_32b_3,
PWM_32b_4,
PWM_32b_5,
PWM_32b_6,
PWM_32b_7,
PWM_16b_0 = TCPWM1_BASE,
PWM_16b_1,
PWM_16b_2,
PWM_16b_3,
PWM_16b_4,
PWM_16b_5,
PWM_16b_6,
PWM_16b_7,
PWM_16b_8,
PWM_16b_9,
PWM_16b_10,
PWM_16b_11,
PWM_16b_12,
PWM_16b_13,
PWM_16b_14,
PWM_16b_15,
PWM_16b_16,
PWM_16b_17,
PWM_16b_18,
PWM_16b_19,
PWM_16b_20,
PWM_16b_21,
PWM_16b_22,
PWM_16b_23,
} PWMName;
typedef enum {
ADC_0 = (int)SAR_BASE,
}ADCName;
typedef enum {
DAC_0 = (int)CTDAC0_BASE,
} DACName;
#ifdef __cplusplus
}
#endif
#endif

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/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H
#include "pinmap.h"
#include "PeripheralNames.h"
// //*** I2C ***
#if DEVICE_I2C
extern const PinMap PinMap_I2C_SDA[];
extern const PinMap PinMap_I2C_SCL[];
#endif
//*** PWM ***
#if DEVICE_PWMOUT
extern const PinMap PinMap_PWM_OUT[];
#endif
//*** SERIAL ***
#ifdef DEVICE_SERIAL
extern const PinMap PinMap_UART_TX[];
extern const PinMap PinMap_UART_RX[];
extern const PinMap PinMap_UART_RTS[];
extern const PinMap PinMap_UART_CTS[];
#endif
//*** SPI ***
#ifdef DEVICE_SPI
extern const PinMap PinMap_SPI_MOSI[];
extern const PinMap PinMap_SPI_MISO[];
extern const PinMap PinMap_SPI_SCLK[];
extern const PinMap PinMap_SPI_SSEL[];
#endif
//*** ADC ***
#ifdef DEVICE_ANALOGIN
extern const PinMap PinMap_ADC[];
#endif
//*** DAC ***
#ifdef DEVICE_ANALOGOUT
extern const PinMap PinMap_DAC[];
#endif
#endif

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/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMESTYPES_H
#define MBED_PINNAMESTYPES_H
#include "cmsis.h"
typedef enum {
PIN_INPUT = 0,
PIN_OUTPUT
} PinDirection;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrainDriveLow = 3,
OpenDrainDriveHigh = 4,
OpenDrain = OpenDrainDriveLow,
PushPull = 5,
AnalogMode = 6,
PullDefault = PullNone
} PinMode;
typedef struct {
en_hsiom_sel_t hsiom : 8;
en_clk_dst_t clock : 8;
PinMode mode : 4;
PinDirection dir : 1;
} PinFunction;
// Encode pin function.
// Output function
#define CY_PIN_FUNCTION(hsiom, clock, mode, dir) (int)(((dir) << 20) | ((mode) << 16) | ((clock) << 8) | (hsiom))
#define CY_PIN_OUT_FUNCTION(hsiom, clock) CY_PIN_FUNCTION(hsiom, clock, PushPull, PIN_OUTPUT)
#define CY_PIN_OD_FUNCTION(hsiom, clock) CY_PIN_FUNCTION(hsiom, clock, OpenDrain, PIN_OUTPUT)
#define CY_PIN_IN_FUNCTION(hsiom, clock) CY_PIN_FUNCTION(hsiom, clock, PullDefault, PIN_INPUT)
#define CY_PIN_PULLUP_FUNCTION(hsiom, clock) CY_PIN_FUNCTION(hsiom, clock, PullUp, PIN_INPUT)
#define CY_PIN_ANALOG_FUNCTION(clock) CY_PIN_FUNCTION(HSIOM_SEL_GPIO, clock, AnalogMode, 0)
// Create unique name to force 32-bit PWM usage on a pin.
#define CY_PIN_FORCE_PWM_32(pin) ((uint32_t)(pin) + 0x8000)
static inline en_hsiom_sel_t CY_PIN_HSIOM(int function)
{
return (en_hsiom_sel_t)(function & 0xFF);
}
static inline en_clk_dst_t CY_PIN_CLOCK(int function)
{
return (en_clk_dst_t)((function >> 8) & 0xFF);
}
static inline PinMode CY_PIN_MODE(int function)
{
return (PinMode)((function >> 16) & 0x0F);
}
static inline PinDirection CY_PIN_DIRECTION(int function)
{
return (PinDirection)((function >> 20) & 1);
}
static inline int CY_PERIPHERAL_BASE(int peripheral)
{
return peripheral & 0xffff0000;
}
#endif

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/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
// Port[15-0]
typedef enum {
Port0 = 0x0,
Port1 = 0x1,
Port2 = 0x2,
Port3 = 0x3,
Port4 = 0x4,
Port5 = 0x5,
Port6 = 0x6,
Port7 = 0x7,
Port8 = 0x8,
Port9 = 0x9,
Port10 = 0xA,
Port11 = 0xB,
Port12 = 0xC,
Port13 = 0xD,
Port14 = 0xE
} PortName;
#ifdef __cplusplus
}
#endif
#endif

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/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralNames.h"
#include "PeripheralPins.h"
#include "pinmap.h"
#if DEVICE_SERIAL
//*** SERIAL ***
const PinMap PinMap_UART_RX[] = {
{P0_2, UART_0, CY_PIN_IN_FUNCTION( P0_2_SCB0_UART_RX, PCLK_SCB0_CLOCK)},
{P1_0, UART_7, CY_PIN_IN_FUNCTION( P1_0_SCB7_UART_RX, PCLK_SCB7_CLOCK)},
{P5_0, UART_5, CY_PIN_IN_FUNCTION( P5_0_SCB5_UART_RX, PCLK_SCB5_CLOCK)},
{P6_0, UART_3, CY_PIN_IN_FUNCTION( P6_0_SCB3_UART_RX, PCLK_SCB3_CLOCK)},
{P6_4, UART_6, CY_PIN_IN_FUNCTION( P6_4_SCB6_UART_RX, PCLK_SCB6_CLOCK)},
{P7_0, UART_4, CY_PIN_IN_FUNCTION( P7_0_SCB4_UART_RX, PCLK_SCB4_CLOCK)},
{P8_0, UART_4, CY_PIN_IN_FUNCTION( P8_0_SCB4_UART_RX, PCLK_SCB4_CLOCK)},
{P9_0, UART_2, CY_PIN_IN_FUNCTION( P9_0_SCB2_UART_RX, PCLK_SCB2_CLOCK)},
{P10_0, UART_1, CY_PIN_IN_FUNCTION( P10_0_SCB1_UART_RX, PCLK_SCB1_CLOCK)},
{P11_0, UART_5, CY_PIN_IN_FUNCTION( P11_0_SCB5_UART_RX, PCLK_SCB5_CLOCK)},
{P12_0, UART_6, CY_PIN_IN_FUNCTION( P12_0_SCB6_UART_RX, PCLK_SCB6_CLOCK)},
{P13_0, UART_6, CY_PIN_IN_FUNCTION( P13_0_SCB6_UART_RX, PCLK_SCB6_CLOCK)},
{NC, NC, 0}
};
const PinMap PinMap_UART_TX[] = {
{P0_3, UART_0, CY_PIN_OUT_FUNCTION( P0_3_SCB0_UART_TX, PCLK_SCB0_CLOCK)},
{P1_1, UART_7, CY_PIN_OUT_FUNCTION( P1_1_SCB7_UART_TX, PCLK_SCB7_CLOCK)},
{P5_1, UART_5, CY_PIN_OUT_FUNCTION( P5_1_SCB5_UART_TX, PCLK_SCB5_CLOCK)},
{P6_1, UART_3, CY_PIN_OUT_FUNCTION( P6_1_SCB3_UART_TX, PCLK_SCB3_CLOCK)},
{P6_5, UART_6, CY_PIN_OUT_FUNCTION( P6_5_SCB6_UART_TX, PCLK_SCB6_CLOCK)},
{P7_1, UART_4, CY_PIN_OUT_FUNCTION( P7_1_SCB4_UART_TX, PCLK_SCB4_CLOCK)},
{P8_1, UART_4, CY_PIN_OUT_FUNCTION( P8_1_SCB4_UART_TX, PCLK_SCB4_CLOCK)},
{P9_1, UART_2, CY_PIN_OUT_FUNCTION( P9_1_SCB2_UART_TX, PCLK_SCB2_CLOCK)},
{P10_1, UART_1, CY_PIN_OUT_FUNCTION( P10_1_SCB1_UART_TX, PCLK_SCB1_CLOCK)},
{P11_1, UART_5, CY_PIN_OUT_FUNCTION( P11_1_SCB5_UART_TX, PCLK_SCB5_CLOCK)},
{P12_1, UART_6, CY_PIN_OUT_FUNCTION( P12_1_SCB6_UART_TX, PCLK_SCB6_CLOCK)},
{P13_1, UART_6, CY_PIN_OUT_FUNCTION( P13_1_SCB6_UART_TX, PCLK_SCB6_CLOCK)},
{NC, NC, 0}
};
const PinMap PinMap_UART_RTS[] = {
{P0_4, UART_0, CY_PIN_OUT_FUNCTION( P0_4_SCB0_UART_RTS, PCLK_SCB0_CLOCK)},
{P1_2, UART_7, CY_PIN_OUT_FUNCTION( P1_2_SCB7_UART_RTS, PCLK_SCB7_CLOCK)},
{P5_2, UART_5, CY_PIN_OUT_FUNCTION( P5_2_SCB5_UART_RTS, PCLK_SCB5_CLOCK)},
{P6_2, UART_3, CY_PIN_OUT_FUNCTION( P6_2_SCB3_UART_RTS, PCLK_SCB3_CLOCK)},
{P6_6, UART_6, CY_PIN_OUT_FUNCTION( P6_6_SCB6_UART_RTS, PCLK_SCB6_CLOCK)},
{P7_2, UART_4, CY_PIN_OUT_FUNCTION( P7_2_SCB4_UART_RTS, PCLK_SCB4_CLOCK)},
{P8_2, UART_4, CY_PIN_OUT_FUNCTION( P8_2_SCB4_UART_RTS, PCLK_SCB4_CLOCK)},
{P9_2, UART_2, CY_PIN_OUT_FUNCTION( P9_2_SCB2_UART_RTS, PCLK_SCB2_CLOCK)},
{P10_2, UART_1, CY_PIN_OUT_FUNCTION( P10_2_SCB1_UART_RTS, PCLK_SCB1_CLOCK)},
{P11_2, UART_5, CY_PIN_OUT_FUNCTION( P11_2_SCB5_UART_RTS, PCLK_SCB5_CLOCK)},
{P12_2, UART_6, CY_PIN_OUT_FUNCTION( P12_2_SCB6_UART_RTS, PCLK_SCB6_CLOCK)},
{NC, NC, 0}
};
const PinMap PinMap_UART_CTS[] = {
{P0_5, UART_0, CY_PIN_IN_FUNCTION( P0_5_SCB0_UART_CTS, PCLK_SCB0_CLOCK)},
{P1_3, UART_7, CY_PIN_IN_FUNCTION( P1_3_SCB7_UART_CTS, PCLK_SCB7_CLOCK)},
{P5_3, UART_5, CY_PIN_IN_FUNCTION( P5_3_SCB5_UART_CTS, PCLK_SCB5_CLOCK)},
{P6_3, UART_3, CY_PIN_IN_FUNCTION( P6_3_SCB3_UART_CTS, PCLK_SCB3_CLOCK)},
{P6_7, UART_6, CY_PIN_IN_FUNCTION( P6_7_SCB6_UART_CTS, PCLK_SCB6_CLOCK)},
{P7_3, UART_4, CY_PIN_IN_FUNCTION( P7_3_SCB4_UART_CTS, PCLK_SCB4_CLOCK)},
{P8_3, UART_4, CY_PIN_IN_FUNCTION( P8_3_SCB4_UART_CTS, PCLK_SCB4_CLOCK)},
{P9_3, UART_2, CY_PIN_IN_FUNCTION( P9_3_SCB2_UART_CTS, PCLK_SCB2_CLOCK)},
{P10_3, UART_1, CY_PIN_IN_FUNCTION( P10_3_SCB1_UART_CTS, PCLK_SCB1_CLOCK)},
{P11_3, UART_5, CY_PIN_IN_FUNCTION( P11_3_SCB5_UART_CTS, PCLK_SCB5_CLOCK)},
{P12_3, UART_6, CY_PIN_IN_FUNCTION( P12_3_SCB6_UART_CTS, PCLK_SCB6_CLOCK)},
{NC, NC, 0}
};
#endif // DEVICE_SERIAL
#if DEVICE_I2C
//*** I2C ***
const PinMap PinMap_I2C_SCL[] = {
{P0_2, I2C_0, CY_PIN_OD_FUNCTION( P0_2_SCB0_I2C_SCL, PCLK_SCB0_CLOCK)},
{P1_0, I2C_7, CY_PIN_OD_FUNCTION( P1_0_SCB7_I2C_SCL, PCLK_SCB7_CLOCK)},
{P5_0, I2C_5, CY_PIN_OD_FUNCTION( P5_0_SCB5_I2C_SCL, PCLK_SCB5_CLOCK)},
{P6_0, I2C_3, CY_PIN_OD_FUNCTION( P6_0_SCB3_I2C_SCL, PCLK_SCB3_CLOCK)},
{P6_4, I2C_6, CY_PIN_OD_FUNCTION( P6_4_SCB6_I2C_SCL, PCLK_SCB6_CLOCK)},
{P7_0, I2C_4, CY_PIN_OD_FUNCTION( P7_0_SCB4_I2C_SCL, PCLK_SCB4_CLOCK)},
{P8_0, I2C_4, CY_PIN_OD_FUNCTION( P8_0_SCB4_I2C_SCL, PCLK_SCB4_CLOCK)},
{P9_0, I2C_2, CY_PIN_OD_FUNCTION( P9_0_SCB2_I2C_SCL, PCLK_SCB2_CLOCK)},
{P10_0, I2C_1, CY_PIN_OD_FUNCTION( P10_0_SCB1_I2C_SCL, PCLK_SCB1_CLOCK)},
{P11_0, I2C_5, CY_PIN_OD_FUNCTION( P11_0_SCB5_I2C_SCL, PCLK_SCB5_CLOCK)},
{P12_0, I2C_6, CY_PIN_OD_FUNCTION( P12_0_SCB6_I2C_SCL, PCLK_SCB6_CLOCK)},
{P13_0, I2C_6, CY_PIN_OD_FUNCTION( P13_0_SCB6_I2C_SCL, PCLK_SCB6_CLOCK)},
{NC, NC, 0}
};
const PinMap PinMap_I2C_SDA[] = {
{P0_3, I2C_0, CY_PIN_OD_FUNCTION( P0_3_SCB0_I2C_SDA, PCLK_SCB0_CLOCK)},
{P1_1, I2C_7, CY_PIN_OD_FUNCTION( P1_1_SCB7_I2C_SDA, PCLK_SCB7_CLOCK)},
{P5_1, I2C_5, CY_PIN_OD_FUNCTION( P5_1_SCB5_I2C_SDA, PCLK_SCB5_CLOCK)},
{P6_1, I2C_3, CY_PIN_OD_FUNCTION( P6_1_SCB3_I2C_SDA, PCLK_SCB3_CLOCK)},
{P6_5, I2C_6, CY_PIN_OD_FUNCTION( P6_5_SCB6_I2C_SDA, PCLK_SCB6_CLOCK)},
{P7_1, I2C_4, CY_PIN_OD_FUNCTION( P7_1_SCB4_I2C_SDA, PCLK_SCB4_CLOCK)},
{P8_1, I2C_4, CY_PIN_OD_FUNCTION( P8_1_SCB4_I2C_SDA, PCLK_SCB4_CLOCK)},
{P9_1, I2C_2, CY_PIN_OD_FUNCTION( P9_1_SCB2_I2C_SDA, PCLK_SCB2_CLOCK)},
{P10_1, I2C_1, CY_PIN_OD_FUNCTION( P10_1_SCB1_I2C_SDA, PCLK_SCB1_CLOCK)},
{P11_1, I2C_5, CY_PIN_OD_FUNCTION( P11_1_SCB5_I2C_SDA, PCLK_SCB5_CLOCK)},
{P12_1, I2C_6, CY_PIN_OD_FUNCTION( P12_1_SCB6_I2C_SDA, PCLK_SCB6_CLOCK)},
{P13_1, I2C_6, CY_PIN_OD_FUNCTION( P13_1_SCB6_I2C_SDA, PCLK_SCB6_CLOCK)},
{NC, NC, 0}
};
#endif // DEVICE_I2C
#if DEVICE_SPI
//*** SPI ***
const PinMap PinMap_SPI_MOSI[] = {
{P0_2, SPI_0, CY_PIN_OUT_FUNCTION( P0_2_SCB0_SPI_MOSI, PCLK_SCB0_CLOCK)},
{P1_0, SPI_7, CY_PIN_OUT_FUNCTION( P1_0_SCB7_SPI_MOSI, PCLK_SCB7_CLOCK)},
{P5_0, SPI_5, CY_PIN_OUT_FUNCTION( P5_0_SCB5_SPI_MOSI, PCLK_SCB5_CLOCK)},
{P6_0, SPI_3, CY_PIN_OUT_FUNCTION( P6_0_SCB3_SPI_MOSI, PCLK_SCB3_CLOCK)},
{P6_4, SPI_6, CY_PIN_OUT_FUNCTION( P6_4_SCB6_SPI_MOSI, PCLK_SCB6_CLOCK)},
{P7_0, SPI_4, CY_PIN_OUT_FUNCTION( P7_0_SCB4_SPI_MOSI, PCLK_SCB4_CLOCK)},
{P8_0, SPI_4, CY_PIN_OUT_FUNCTION( P8_0_SCB4_SPI_MOSI, PCLK_SCB4_CLOCK)},
{P9_0, SPI_2, CY_PIN_OUT_FUNCTION( P9_0_SCB2_SPI_MOSI, PCLK_SCB2_CLOCK)},
{P10_0, SPI_1, CY_PIN_OUT_FUNCTION( P10_0_SCB1_SPI_MOSI, PCLK_SCB1_CLOCK)},
{P11_0, SPI_5, CY_PIN_OUT_FUNCTION( P11_0_SCB5_SPI_MOSI, PCLK_SCB5_CLOCK)},
{P12_0, SPI_6, CY_PIN_OUT_FUNCTION( P12_0_SCB6_SPI_MOSI, PCLK_SCB6_CLOCK)},
{P13_0, SPI_6, CY_PIN_OUT_FUNCTION( P13_0_SCB6_SPI_MOSI, PCLK_SCB6_CLOCK)},
{NC, NC, 0}
};
const PinMap PinMap_SPI_MISO[] = {
{P0_3, SPI_0, CY_PIN_IN_FUNCTION( P0_3_SCB0_SPI_MISO, PCLK_SCB0_CLOCK)},
{P1_1, SPI_7, CY_PIN_IN_FUNCTION( P1_1_SCB7_SPI_MISO, PCLK_SCB7_CLOCK)},
{P5_1, SPI_5, CY_PIN_IN_FUNCTION( P5_1_SCB5_SPI_MISO, PCLK_SCB5_CLOCK)},
{P6_1, SPI_3, CY_PIN_IN_FUNCTION( P6_1_SCB3_SPI_MISO, PCLK_SCB3_CLOCK)},
{P6_5, SPI_6, CY_PIN_IN_FUNCTION( P6_5_SCB6_SPI_MISO, PCLK_SCB6_CLOCK)},
{P7_1, SPI_4, CY_PIN_IN_FUNCTION( P7_1_SCB4_SPI_MISO, PCLK_SCB4_CLOCK)},
{P8_1, SPI_4, CY_PIN_IN_FUNCTION( P8_1_SCB4_SPI_MISO, PCLK_SCB4_CLOCK)},
{P9_1, SPI_2, CY_PIN_IN_FUNCTION( P9_1_SCB2_SPI_MISO, PCLK_SCB2_CLOCK)},
{P10_1, SPI_1, CY_PIN_IN_FUNCTION( P10_1_SCB1_SPI_MISO, PCLK_SCB1_CLOCK)},
{P11_1, SPI_5, CY_PIN_IN_FUNCTION( P11_1_SCB5_SPI_MISO, PCLK_SCB5_CLOCK)},
{P12_1, SPI_6, CY_PIN_IN_FUNCTION( P12_1_SCB6_SPI_MISO, PCLK_SCB6_CLOCK)},
{P13_1, SPI_6, CY_PIN_IN_FUNCTION( P13_1_SCB6_SPI_MISO, PCLK_SCB6_CLOCK)},
{NC, NC, 0}
};
const PinMap PinMap_SPI_SCLK[] = {
{P0_4, SPI_0, CY_PIN_OUT_FUNCTION( P0_4_SCB0_SPI_CLK, PCLK_SCB0_CLOCK)},
{P1_2, SPI_7, CY_PIN_OUT_FUNCTION( P1_2_SCB7_SPI_CLK, PCLK_SCB7_CLOCK)},
{P5_2, SPI_5, CY_PIN_OUT_FUNCTION( P5_2_SCB5_SPI_CLK, PCLK_SCB5_CLOCK)},
{P6_2, SPI_3, CY_PIN_OUT_FUNCTION( P6_2_SCB3_SPI_CLK, PCLK_SCB3_CLOCK)},
{P6_6, SPI_6, CY_PIN_OUT_FUNCTION( P6_6_SCB6_SPI_CLK, PCLK_SCB6_CLOCK)},
{P7_2, SPI_4, CY_PIN_OUT_FUNCTION( P7_2_SCB4_SPI_CLK, PCLK_SCB4_CLOCK)},
{P8_2, SPI_4, CY_PIN_OUT_FUNCTION( P8_2_SCB4_SPI_CLK, PCLK_SCB4_CLOCK)},
{P9_2, SPI_2, CY_PIN_OUT_FUNCTION( P9_2_SCB2_SPI_CLK, PCLK_SCB2_CLOCK)},
{P10_2, SPI_1, CY_PIN_OUT_FUNCTION( P10_2_SCB1_SPI_CLK, PCLK_SCB1_CLOCK)},
{P11_2, SPI_5, CY_PIN_OUT_FUNCTION( P11_2_SCB5_SPI_CLK, PCLK_SCB5_CLOCK)},
{P12_2, SPI_6, CY_PIN_OUT_FUNCTION( P12_2_SCB6_SPI_CLK, PCLK_SCB6_CLOCK)},
{NC, NC, 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{P0_5, SPI_0, CY_PIN_OUT_FUNCTION( P0_5_SCB0_SPI_SELECT0, PCLK_SCB0_CLOCK)},
{P1_3, SPI_7, CY_PIN_OUT_FUNCTION( P1_3_SCB7_SPI_SELECT0, PCLK_SCB7_CLOCK)},
{P5_3, SPI_5, CY_PIN_OUT_FUNCTION( P5_3_SCB5_SPI_SELECT0, PCLK_SCB5_CLOCK)},
{P6_3, SPI_3, CY_PIN_OUT_FUNCTION( P6_3_SCB3_SPI_SELECT0, PCLK_SCB3_CLOCK)},
{P6_7, SPI_6, CY_PIN_OUT_FUNCTION( P6_7_SCB6_SPI_SELECT0, PCLK_SCB6_CLOCK)},
{P7_3, SPI_4, CY_PIN_OUT_FUNCTION( P7_3_SCB4_SPI_SELECT0, PCLK_SCB4_CLOCK)},
{P8_3, SPI_4, CY_PIN_OUT_FUNCTION( P8_3_SCB4_SPI_SELECT0, PCLK_SCB4_CLOCK)},
{P9_3, SPI_2, CY_PIN_OUT_FUNCTION( P9_3_SCB2_SPI_SELECT0, PCLK_SCB2_CLOCK)},
{P10_3, SPI_1, CY_PIN_OUT_FUNCTION( P10_3_SCB1_SPI_SELECT0, PCLK_SCB1_CLOCK)},
{P11_3, SPI_5, CY_PIN_OUT_FUNCTION( P11_3_SCB5_SPI_SELECT0, PCLK_SCB5_CLOCK)},
{P12_3, SPI_6, CY_PIN_OUT_FUNCTION( P12_3_SCB6_SPI_SELECT0, PCLK_SCB6_CLOCK)},
{NC, NC, 0}
};
#endif // DEVICE_SPI
#if DEVICE_PWMOUT
//*** PWM ***
const PinMap PinMap_PWM_OUT[] = {
// 16-bit PWM outputs
{P0_0, PWM_16b_0, CY_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0, PCLK_TCPWM1_CLOCKS0)},
{P0_2, PWM_16b_1, CY_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1, PCLK_TCPWM1_CLOCKS1)},
{P0_4, PWM_16b_2, CY_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2, PCLK_TCPWM1_CLOCKS2)},
{P1_0, PWM_16b_3, CY_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3, PCLK_TCPWM1_CLOCKS3)},
{P1_2, PWM_16b_12, CY_PIN_OUT_FUNCTION(P1_2_TCPWM1_LINE12, PCLK_TCPWM1_CLOCKS12)},
{P1_4, PWM_16b_13, CY_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13, PCLK_TCPWM1_CLOCKS13)},
{P5_0, PWM_16b_4, CY_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4, PCLK_TCPWM1_CLOCKS4)},
{P5_2, PWM_16b_5, CY_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5, PCLK_TCPWM1_CLOCKS5)},
{P5_4, PWM_16b_6, CY_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6, PCLK_TCPWM1_CLOCKS6)},
{P5_6, PWM_16b_7, CY_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7, PCLK_TCPWM1_CLOCKS7)},
{P6_0, PWM_16b_8, CY_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8, PCLK_TCPWM1_CLOCKS8)},
{P6_2, PWM_16b_9, CY_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9, PCLK_TCPWM1_CLOCKS9)},
{P6_4, PWM_16b_10, CY_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10, PCLK_TCPWM1_CLOCKS10)},
{P6_6, PWM_16b_11, CY_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11, PCLK_TCPWM1_CLOCKS11)},
{P7_0, PWM_16b_12, CY_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12, PCLK_TCPWM1_CLOCKS12)},
{P7_2, PWM_16b_13, CY_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13, PCLK_TCPWM1_CLOCKS13)},
{P7_4, PWM_16b_14, CY_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14, PCLK_TCPWM1_CLOCKS14)},
{P7_6, PWM_16b_15, CY_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15, PCLK_TCPWM1_CLOCKS15)},
{P8_0, PWM_16b_16, CY_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16, PCLK_TCPWM1_CLOCKS16)},
{P8_2, PWM_16b_17, CY_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17, PCLK_TCPWM1_CLOCKS17)},
{P8_4, PWM_16b_18, CY_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18, PCLK_TCPWM1_CLOCKS18)},
{P8_6, PWM_16b_19, CY_PIN_OUT_FUNCTION(P8_6_TCPWM1_LINE19, PCLK_TCPWM1_CLOCKS19)},
{P9_0, PWM_16b_20, CY_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20, PCLK_TCPWM1_CLOCKS20)},
{P9_2, PWM_16b_21, CY_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21, PCLK_TCPWM1_CLOCKS21)},
{P9_4, PWM_16b_0, CY_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0, PCLK_TCPWM1_CLOCKS0)},
{P9_6, PWM_16b_1, CY_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1, PCLK_TCPWM1_CLOCKS1)},
{P10_0, PWM_16b_22, CY_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22, PCLK_TCPWM1_CLOCKS22)},
{P10_2, PWM_16b_23, CY_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23, PCLK_TCPWM1_CLOCKS23)},
{P10_4, PWM_16b_0, CY_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0, PCLK_TCPWM1_CLOCKS0)},
{P10_6, PWM_16b_2, CY_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2, PCLK_TCPWM1_CLOCKS2)},
{P11_0, PWM_16b_1, CY_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1, PCLK_TCPWM1_CLOCKS1)},
{P11_2, PWM_16b_2, CY_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2, PCLK_TCPWM1_CLOCKS2)},
{P11_4, PWM_16b_3, CY_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3, PCLK_TCPWM1_CLOCKS3)},
{P12_0, PWM_16b_4, CY_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4, PCLK_TCPWM1_CLOCKS4)},
{P12_2, PWM_16b_5, CY_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5, PCLK_TCPWM1_CLOCKS5)},
{P12_4, PWM_16b_6, CY_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6, PCLK_TCPWM1_CLOCKS6)},
{P12_6, PWM_16b_7, CY_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7, PCLK_TCPWM1_CLOCKS7)},
{P13_0, PWM_16b_8, CY_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8, PCLK_TCPWM1_CLOCKS8)},
{P13_6, PWM_16b_11, CY_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11, PCLK_TCPWM1_CLOCKS11)},
// 16-bit PWM inverted outputs
{P0_1, PWM_16b_0, CY_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0, PCLK_TCPWM1_CLOCKS0)},
{P0_3, PWM_16b_1, CY_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1, PCLK_TCPWM1_CLOCKS1)},
{P0_5, PWM_16b_2, CY_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2, PCLK_TCPWM1_CLOCKS2)},
{P1_1, PWM_16b_3, CY_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3, PCLK_TCPWM1_CLOCKS3)},
{P1_3, PWM_16b_12, CY_PIN_OUT_FUNCTION(P1_3_TCPWM1_LINE_COMPL12, PCLK_TCPWM1_CLOCKS12)},
{P1_5, PWM_16b_14, CY_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14, PCLK_TCPWM1_CLOCKS14)},
{P5_1, PWM_16b_4, CY_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4, PCLK_TCPWM1_CLOCKS4)},
{P5_3, PWM_16b_5, CY_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5, PCLK_TCPWM1_CLOCKS5)},
{P5_5, PWM_16b_6, CY_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6, PCLK_TCPWM1_CLOCKS6)},
{P6_1, PWM_16b_8, CY_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8, PCLK_TCPWM1_CLOCKS8)},
{P6_3, PWM_16b_9, CY_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9, PCLK_TCPWM1_CLOCKS9)},
{P6_5, PWM_16b_10, CY_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10, PCLK_TCPWM1_CLOCKS10)},
{P6_7, PWM_16b_11, CY_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11, PCLK_TCPWM1_CLOCKS11)},
{P7_1, PWM_16b_12, CY_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12, PCLK_TCPWM1_CLOCKS12)},
{P7_3, PWM_16b_13, CY_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13, PCLK_TCPWM1_CLOCKS13)},
{P7_5, PWM_16b_14, CY_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14, PCLK_TCPWM1_CLOCKS14)},
{P7_7, PWM_16b_15, CY_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15, PCLK_TCPWM1_CLOCKS15)},
{P8_1, PWM_16b_16, CY_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16, PCLK_TCPWM1_CLOCKS16)},
{P8_3, PWM_16b_17, CY_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17, PCLK_TCPWM1_CLOCKS17)},
{P8_5, PWM_16b_18, CY_PIN_OUT_FUNCTION(P8_5_TCPWM1_LINE_COMPL18, PCLK_TCPWM1_CLOCKS18)},
{P8_7, PWM_16b_19, CY_PIN_OUT_FUNCTION(P8_7_TCPWM1_LINE_COMPL19, PCLK_TCPWM1_CLOCKS19)},
{P9_1, PWM_16b_20, CY_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20, PCLK_TCPWM1_CLOCKS20)},
{P9_3, PWM_16b_21, CY_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21, PCLK_TCPWM1_CLOCKS21)},
{P9_5, PWM_16b_0, CY_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0, PCLK_TCPWM1_CLOCKS0)},
{P9_7, PWM_16b_1, CY_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1, PCLK_TCPWM1_CLOCKS1)},
{P10_1, PWM_16b_22, CY_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22, PCLK_TCPWM1_CLOCKS22)},
{P10_3, PWM_16b_23, CY_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23, PCLK_TCPWM1_CLOCKS23)},
{P10_5, PWM_16b_0, CY_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0, PCLK_TCPWM1_CLOCKS0)},
{P11_1, PWM_16b_1, CY_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1, PCLK_TCPWM1_CLOCKS1)},
{P11_3, PWM_16b_2, CY_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2, PCLK_TCPWM1_CLOCKS2)},
{P11_5, PWM_16b_3, CY_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3, PCLK_TCPWM1_CLOCKS3)},
{P12_1, PWM_16b_4, CY_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4, PCLK_TCPWM1_CLOCKS4)},
{P12_3, PWM_16b_5, CY_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5, PCLK_TCPWM1_CLOCKS5)},
{P12_5, PWM_16b_6, CY_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6, PCLK_TCPWM1_CLOCKS6)},
{P12_7, PWM_16b_7, CY_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7, PCLK_TCPWM1_CLOCKS7)},
{P13_1, PWM_16b_8, CY_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8, PCLK_TCPWM1_CLOCKS8)},
{P13_7, PWM_16b_11, CY_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11, PCLK_TCPWM1_CLOCKS11)},
// 32-bit PWM outputs
{PWM32(P0_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
{PWM32(P0_2), PWM_32b_1, CY_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)},
{PWM32(P0_4), PWM_32b_2, CY_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)},
{PWM32(P1_0), PWM_32b_3, CY_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)},
{PWM32(P1_2), PWM_32b_4, CY_PIN_OUT_FUNCTION(P1_2_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)},
{PWM32(P1_4), PWM_32b_5, CY_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)},
{PWM32(P5_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)},
{PWM32(P5_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)},
{PWM32(P5_4), PWM_32b_6, CY_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)},
{PWM32(P5_6), PWM_32b_7, CY_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)},
{PWM32(P6_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
{PWM32(P6_2), PWM_32b_1, CY_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)},
{PWM32(P6_4), PWM_32b_2, CY_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)},
{PWM32(P6_6), PWM_32b_3, CY_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)},
{PWM32(P7_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)},
{PWM32(P7_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)},
{PWM32(P7_4), PWM_32b_6, CY_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)},
{PWM32(P7_6), PWM_32b_7, CY_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)},
{PWM32(P8_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
{PWM32(P8_2), PWM_32b_1, CY_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)},
{PWM32(P8_4), PWM_32b_2, CY_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)},
{PWM32(P8_6), PWM_32b_3, CY_PIN_OUT_FUNCTION(P8_6_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)},
{PWM32(P9_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)},
{PWM32(P9_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)},
{PWM32(P9_4), PWM_32b_7, CY_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)},
{PWM32(P9_6), PWM_32b_0, CY_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
{PWM32(P10_0), PWM_32b_6, CY_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)},
{PWM32(P10_2), PWM_32b_7, CY_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)},
{PWM32(P10_4), PWM_32b_0, CY_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
{PWM32(P10_6), PWM_32b_1, CY_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)},
{PWM32(P11_0), PWM_32b_1, CY_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)},
{PWM32(P11_2), PWM_32b_2, CY_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)},
{PWM32(P11_4), PWM_32b_3, CY_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)},
{PWM32(P12_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)},
{PWM32(P12_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)},
{PWM32(P12_4), PWM_32b_6, CY_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)},
{PWM32(P12_6), PWM_32b_7, CY_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)},
{PWM32(P13_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
{PWM32(P13_6), PWM_32b_3, CY_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)},
// 32-bit PWM inverted outputs
{PWM32(P0_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
{PWM32(P0_3), PWM_32b_1, CY_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)},
{PWM32(P0_5), PWM_32b_2, CY_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)},
{PWM32(P1_1), PWM_32b_3, CY_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)},
{PWM32(P1_3), PWM_32b_4, CY_PIN_OUT_FUNCTION(P1_3_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)},
{PWM32(P1_5), PWM_32b_5, CY_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)},
{PWM32(P5_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)},
{PWM32(P5_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)},
{PWM32(P5_5), PWM_32b_6, CY_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)},
{PWM32(P6_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
{PWM32(P6_3), PWM_32b_1, CY_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)},
{PWM32(P6_5), PWM_32b_2, CY_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)},
{PWM32(P6_7), PWM_32b_3, CY_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)},
{PWM32(P7_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)},
{PWM32(P7_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)},
{PWM32(P7_5), PWM_32b_6, CY_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)},
{PWM32(P7_7), PWM_32b_7, CY_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)},
{PWM32(P8_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
{PWM32(P8_3), PWM_32b_1, CY_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)},
{PWM32(P8_5), PWM_32b_2, CY_PIN_OUT_FUNCTION(P8_5_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)},
{PWM32(P8_7), PWM_32b_3, CY_PIN_OUT_FUNCTION(P8_7_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)},
{PWM32(P9_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)},
{PWM32(P9_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)},
{PWM32(P9_5), PWM_32b_7, CY_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)},
{PWM32(P9_7), PWM_32b_0, CY_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
{PWM32(P10_1), PWM_32b_6, CY_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)},
{PWM32(P10_3), PWM_32b_7, CY_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)},
{PWM32(P10_5), PWM_32b_0, CY_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
{PWM32(P11_1), PWM_32b_1, CY_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)},
{PWM32(P11_3), PWM_32b_2, CY_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)},
{PWM32(P11_5), PWM_32b_3, CY_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)},
{PWM32(P12_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)},
{PWM32(P12_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)},
{PWM32(P12_5), PWM_32b_6, CY_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)},
{PWM32(P12_7), PWM_32b_7, CY_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)},
{PWM32(P13_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
{PWM32(P13_7), PWM_32b_3, CY_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)},
{NC, NC, 0}
};
#endif // DEVICE_PWMOUT
#if DEVICE_ANALOGIN
const PinMap PinMap_ADC[] = {
{P10_0, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
{P10_1, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
{P10_2, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
{P10_3, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
{P10_4, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
{P10_5, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
{P10_6, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
{P10_7, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
{NC, NC, 0}
};
#endif // DEVICE_ANALOGIN
#if DEVICE_ANALOGOUT
const PinMap PinMap_DAC[] = {
{P9_6, DAC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_CTDAC)},
{NC, NC, 0}
};
#endif // DEVICE_ANALOGIN

209
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/cy8c6xx7_cm0plus.sct Normal file
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@ -0,0 +1,209 @@
#! armcc -E
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file cy8c6xx7_cm0plus.scat
;* \version 2.10
;*
;* Linker file for the ARMCC.
;*
;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory
;* layout of the output file.
;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there.
;*
;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker
;* file.
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
;* You may use this file only in accordance with the license, terms, conditions,
;* disclaimers, and limitations in the end user license agreement accompanying
;* the software package with which this file was provided.
;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
; RAM
; RAM
#define RAM_START 0x08000000
#define RAM_SIZE 0x00010000
; Flash
; Flash
#define FLASH_START 0x10000000
#define FLASH_SIZE 0x00078000
; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200
; External memory
#define XIP_START 0x18000000
#define XIP_SIZE 0x08000000
; eFuse
#define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000
LR_IROM1 FLASH_START FLASH_SIZE
{
.cy_app_header +0
{
* (.cy_app_header)
}
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}
ER_FLASH_CODE +0 FIXED
{
* (InRoot$$Sections)
* (+RO)
}
ER_RAM_VECTORS RAM_START UNINIT
{
* (RESET_RAM, +FIRST)
}
RW_RAM_DATA +0
{
* (.cy_ramfunc)
.ANY (+RW, +ZI)
}
; Place variables in the section that should not be initialized during the
; device startup.
RW_IRAM1 +0 UNINIT
{
* (.noinit)
}
}
; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{
.cy_em_eeprom +0
{
* (.cy_em_eeprom)
}
}
; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{
.cy_sflash_user_data +0
{
* (.cy_sflash_user_data)
}
}
; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{
.cy_sflash_nar +0
{
* (.cy_sflash_nar)
}
}
; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{
.cy_sflash_public_key +0
{
* (.cy_sflash_public_key)
}
}
; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{
.cy_toc_part2 +0
{
* (.cy_toc_part2)
}
}
; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{
.cy_rtoc_part2 +0
{
* (.cy_rtoc_part2)
}
}
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE
{
.cy_xip +0
{
* (.cy_xip)
}
}
; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE
{
.cy_efuse +0
{
* (.cy_efuse)
}
}
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000
{
.cymeta +0 { * (.cymeta) }
}
/* [] END OF FILE */

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targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/device/TOOLCHAIN_ARM_STD/cy_ble_stack_mdk_controller_ipc_cm0p.a → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/libcy_ble_stack_mdk_controller_ipc_cm0p.a
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targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/device/TOOLCHAIN_ARM_STD/cy_ble_stack_mdk_controller_uart_cm0p.a → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/libcy_ble_stack_mdk_controller_uart_cm0p.a
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targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/libcy_ble_stack_mdk_radio_max_cm0p.a Normal file
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targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/libcy_crypto_client_mdk.a Normal file
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targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/libcy_crypto_server_mdk_base.a Normal file
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279
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/startup_psoc63_cm0plus.s Normal file
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@ -0,0 +1,279 @@
;/**************************************************************************//**
; * @file startup_psoc63_cm0plus.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0plus Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
__initial_sp EQU 0x08010000
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External interrupts Description
DCD NvicMux0_IRQHandler ; CM0 + NVIC Mux input 0
DCD NvicMux1_IRQHandler ; CM0 + NVIC Mux input 1
DCD NvicMux2_IRQHandler ; CM0 + NVIC Mux input 2
DCD NvicMux3_IRQHandler ; CM0 + NVIC Mux input 3
DCD NvicMux4_IRQHandler ; CM0 + NVIC Mux input 4
DCD NvicMux5_IRQHandler ; CM0 + NVIC Mux input 5
DCD NvicMux6_IRQHandler ; CM0 + NVIC Mux input 6
DCD NvicMux7_IRQHandler ; CM0 + NVIC Mux input 7
DCD NvicMux8_IRQHandler ; CM0 + NVIC Mux input 8
DCD NvicMux9_IRQHandler ; CM0 + NVIC Mux input 9
DCD NvicMux10_IRQHandler ; CM0 + NVIC Mux input 10
DCD NvicMux11_IRQHandler ; CM0 + NVIC Mux input 11
DCD NvicMux12_IRQHandler ; CM0 + NVIC Mux input 12
DCD NvicMux13_IRQHandler ; CM0 + NVIC Mux input 13
DCD NvicMux14_IRQHandler ; CM0 + NVIC Mux input 14
DCD NvicMux15_IRQHandler ; CM0 + NVIC Mux input 15
DCD NvicMux16_IRQHandler ; CM0 + NVIC Mux input 16
DCD NvicMux17_IRQHandler ; CM0 + NVIC Mux input 17
DCD NvicMux18_IRQHandler ; CM0 + NVIC Mux input 18
DCD NvicMux19_IRQHandler ; CM0 + NVIC Mux input 19
DCD NvicMux20_IRQHandler ; CM0 + NVIC Mux input 20
DCD NvicMux21_IRQHandler ; CM0 + NVIC Mux input 21
DCD NvicMux22_IRQHandler ; CM0 + NVIC Mux input 22
DCD NvicMux23_IRQHandler ; CM0 + NVIC Mux input 23
DCD NvicMux24_IRQHandler ; CM0 + NVIC Mux input 24
DCD NvicMux25_IRQHandler ; CM0 + NVIC Mux input 25
DCD NvicMux26_IRQHandler ; CM0 + NVIC Mux input 26
DCD NvicMux27_IRQHandler ; CM0 + NVIC Mux input 27
DCD NvicMux28_IRQHandler ; CM0 + NVIC Mux input 28
DCD NvicMux29_IRQHandler ; CM0 + NVIC Mux input 29
DCD NvicMux30_IRQHandler ; CM0 + NVIC Mux input 30
DCD NvicMux31_IRQHandler ; CM0 + NVIC Mux input 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
EXPORT __ramVectors
AREA RESET_RAM, READWRITE, NOINIT
__ramVectors SPACE __Vectors_Size
AREA |.text|, CODE, READONLY
; Saves and disables the interrupts
Cy_SaveIRQ PROC
EXPORT Cy_SaveIRQ
MRS r0, PRIMASK
CPSID I
BX LR
ENDP
; Restores the interrupts
Cy_RestoreIRQ PROC
EXPORT Cy_RestoreIRQ
MSR PRIMASK, r0
BX LR
ENDP
; Weak function for startup customization
Cy_OnResetUser PROC
EXPORT Cy_OnResetUser [WEAK]
BX LR
ENDP
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
; Define strong function for startup customization
BL Cy_OnResetUser
; Copy vectors from ROM to RAM
LDR r1, =__Vectors
LDR r0, =__ramVectors
LDR r2, =__Vectors_Size
Vectors_Copy
LDR r3, [r1]
STR r3, [r0]
ADDS r0, r0, #4
ADDS r1, r1, #4
SUBS r2, r2, #1
CMP r2, #0
BNE Vectors_Copy
; Update Vector Table Offset Register. */
LDR r0, =__ramVectors
LDR r1, =0xE000ED08
STR r0, [r1]
dsb 0xF
LDR R0, =__main
BLX R0
; Should never get here
B .
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
Cy_SysLib_FaultHandler PROC
EXPORT Cy_SysLib_FaultHandler [WEAK]
B .
ENDP
HardFault_Handler PROC
EXPORT HardFault_Handler [WEAK]
movs r0, #4
mov r1, LR
tst r0, r1
beq L_MSP
mrs r0, PSP
bl L_API_call
L_MSP
mrs r0, MSP
L_API_call
bl Cy_SysLib_FaultHandler
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT Default_Handler [WEAK]
EXPORT NvicMux0_IRQHandler [WEAK]
EXPORT NvicMux1_IRQHandler [WEAK]
EXPORT NvicMux2_IRQHandler [WEAK]
EXPORT NvicMux3_IRQHandler [WEAK]
EXPORT NvicMux4_IRQHandler [WEAK]
EXPORT NvicMux5_IRQHandler [WEAK]
EXPORT NvicMux6_IRQHandler [WEAK]
EXPORT NvicMux7_IRQHandler [WEAK]
EXPORT NvicMux8_IRQHandler [WEAK]
EXPORT NvicMux9_IRQHandler [WEAK]
EXPORT NvicMux10_IRQHandler [WEAK]
EXPORT NvicMux11_IRQHandler [WEAK]
EXPORT NvicMux12_IRQHandler [WEAK]
EXPORT NvicMux13_IRQHandler [WEAK]
EXPORT NvicMux14_IRQHandler [WEAK]
EXPORT NvicMux15_IRQHandler [WEAK]
EXPORT NvicMux16_IRQHandler [WEAK]
EXPORT NvicMux17_IRQHandler [WEAK]
EXPORT NvicMux18_IRQHandler [WEAK]
EXPORT NvicMux19_IRQHandler [WEAK]
EXPORT NvicMux20_IRQHandler [WEAK]
EXPORT NvicMux21_IRQHandler [WEAK]
EXPORT NvicMux22_IRQHandler [WEAK]
EXPORT NvicMux23_IRQHandler [WEAK]
EXPORT NvicMux24_IRQHandler [WEAK]
EXPORT NvicMux25_IRQHandler [WEAK]
EXPORT NvicMux26_IRQHandler [WEAK]
EXPORT NvicMux27_IRQHandler [WEAK]
EXPORT NvicMux28_IRQHandler [WEAK]
EXPORT NvicMux29_IRQHandler [WEAK]
EXPORT NvicMux30_IRQHandler [WEAK]
EXPORT NvicMux31_IRQHandler [WEAK]
NvicMux0_IRQHandler
NvicMux1_IRQHandler
NvicMux2_IRQHandler
NvicMux3_IRQHandler
NvicMux4_IRQHandler
NvicMux5_IRQHandler
NvicMux6_IRQHandler
NvicMux7_IRQHandler
NvicMux8_IRQHandler
NvicMux9_IRQHandler
NvicMux10_IRQHandler
NvicMux11_IRQHandler
NvicMux12_IRQHandler
NvicMux13_IRQHandler
NvicMux14_IRQHandler
NvicMux15_IRQHandler
NvicMux16_IRQHandler
NvicMux17_IRQHandler
NvicMux18_IRQHandler
NvicMux19_IRQHandler
NvicMux20_IRQHandler
NvicMux21_IRQHandler
NvicMux22_IRQHandler
NvicMux23_IRQHandler
NvicMux24_IRQHandler
NvicMux25_IRQHandler
NvicMux26_IRQHandler
NvicMux27_IRQHandler
NvicMux28_IRQHandler
NvicMux29_IRQHandler
NvicMux30_IRQHandler
NvicMux31_IRQHandler
B .
ENDP
ALIGN
END
; [] END OF FILE

125
targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
View File

@ -1,9 +1,13 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy8c6xx7_cm0plus.ld * \file cy8c6xx7_cm0plus.ld
* \version 2.0 * \version 2.10
* *
* Linker file for the GNU C compiler. * Linker file for the GNU C compiler.
* *
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point location is fixed and starts at 0x10000000. The valid * \note The entry point location is fixed and starts at 0x10000000. The valid
* application image should be placed there. * application image should be placed there.
* *
@ -15,7 +19,7 @@
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -35,22 +39,36 @@ ENTRY(Reset_Handler)
*/ */
EXTERN(Reset_Handler) EXTERN(Reset_Handler)
/* The MEMORY section below describes the location and size of blocks of memory in the target.
/* Linker script to configure memory regions. */ * Use this section to specify the memory regions available for allocation.
*/
MEMORY MEMORY
{ {
flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x80000 /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
wflash (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ * You can change the memory allocation by editing the 'ram' and 'flash' regions.
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 */
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x400 ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x10000
flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x78000
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
/* The following regions define device specific memory regions and must not be changed. */
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x24000
} }
/* Library configurations */ /* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a) GROUP(libgcc.a libc.a libm.a libnosys.a)
@ -129,6 +147,34 @@ SECTIONS
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*)) KEEP(*(.eh_frame*))
/* To copy multiple ROM to RAM sections,
* uncomment copy table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc63_cm4.S */
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy interrupt vectors from flash to RAM */
LONG (__Vectors) /* From */
LONG (__ram_vectors_start__) /* To */
LONG (__Vectors_End - __Vectors) /* Size */
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG (__data_end__ - __data_start__) /* Size */
__copy_table_end__ = .;
/* To clear multiple BSS sections,
* uncomment zero table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc63_cm4.S */
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > flash } > flash
@ -145,41 +191,6 @@ SECTIONS
} > flash } > flash
__exidx_end = .; __exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc63_cm0plus.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy interrupt vectors from flash to RAM */
LONG (__Vectors) /* From */
LONG (__ram_vectors_start__) /* To */
LONG (__Vectors_End - __Vectors) /* Size */
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG (__data_end__ - __data_start__) /* Size */
__copy_table_end__ = .;
} > flash
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc63_cm0plus.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > flash
__etext = . ; __etext = . ;
@ -211,7 +222,6 @@ SECTIONS
KEEP(*(.init_array)) KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .); PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4); . = ALIGN(4);
/* finit data */ /* finit data */
PROVIDE_HIDDEN (__fini_array_start = .); PROVIDE_HIDDEN (__fini_array_start = .);
@ -291,11 +301,11 @@ SECTIONS
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Work Flash */ /* Emulated EEPROM Flash area */
.cy_wflash : .cy_em_eeprom :
{ {
KEEP(*(.cy_wflash)) KEEP(*(.cy_em_eeprom))
} > wflash } > em_eeprom
/* Supervisory Flash: User data */ /* Supervisory Flash: User data */
@ -326,6 +336,13 @@ SECTIONS
} > sflash_toc_2 } > sflash_toc_2
/* Supervisory Flash: Table of Content # 2 Copy */
.cy_rtoc_part2 :
{
KEEP(*(.cy_rtoc_part2))
} > sflash_rtoc_2
/* Places the code in the Execute in Place (XIP) section. See the smif driver /* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details. * documentation for details.
*/ */
@ -349,13 +366,13 @@ SECTIONS
} }
/* The following symbols used by the cypdlelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
__cy_memory_0_start = 0x10000000; __cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x00100000; __cy_memory_0_length = 0x00100000;
__cy_memory_0_row_size = 0x200; __cy_memory_0_row_size = 0x200;
/* Working Flash */ /* Emulated EEPROM Flash area */
__cy_memory_1_start = 0x14000000; __cy_memory_1_start = 0x14000000;
__cy_memory_1_length = 0x8000; __cy_memory_1_length = 0x8000;
__cy_memory_1_row_size = 0x200; __cy_memory_1_row_size = 0x200;

BIN
targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/TOOLCHAIN_GCC_ARM/libcy_crypto_client_gcc.a → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/libcy_crypto_client_gcc.a
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BIN
targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/TOOLCHAIN_GCC_ARM/libcy_crypto_server_gcc_base.a → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/libcy_crypto_server_gcc_base.a
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BIN
targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/TOOLCHAIN_GCC_ARM/libcy_crypto_server_gcc_extra.a → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/libcy_crypto_server_gcc_extra.a
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7
targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/device/TOOLCHAIN_GCC_ARM/startup_psoc63_cm0plus.S → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/startup_psoc63_cm0plus.S
View File

@ -178,7 +178,6 @@ Cy_RestoreIRQ:
Reset_Handler: Reset_Handler:
bl Cy_OnResetUser bl Cy_OnResetUser
cpsid i
/* Firstly it copies data from read only memory to RAM. There are two schemes /* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy * to copy. One can copy more than one sections. Another can only copy
@ -313,11 +312,7 @@ Reset_Handler:
str r0, [r1] str r0, [r1]
dsb 0xF dsb 0xF
#ifndef __NO_SYSTEM_INIT bl _start
bl SystemInit
#endif
bl main
/* Should never get here */ /* Should never get here */
b . b .

218
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf Normal file
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@ -0,0 +1,218 @@
/***************************************************************************//**
* \file cy8c6xx7_cm0plus.icf
* \version 2.10
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM0+ core.
* You can change the memory allocation by editing RAM and Flash symbols.
* Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x08010000;
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x10078000;
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = 0x1000;
} else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
}
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x4000;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block RO {first section .intvec, readonly};
/*-Initializations-*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash */
".cy_app_header" : place at start of IROM1_region { section .cy_app_header };
place in IROM1_region { block RO };
/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */
".cy_xip" : place at start of EROM1_region { section .cy_xip };
/* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_app_header,
section .cy_em_eeprom,
section .cy_sflash_user_data,
section .cy_sflash_nar,
section .cy_sflash_public_key,
section .cy_toc_part2,
section .cy_rtoc_part2,
section .cy_efuse,
section .cy_xip,
section .cymeta,
};
/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00100000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */
define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;
/* EOF */

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targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/libcy_crypto_server_mdk_extra.a Normal file
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417
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/startup_psoc63_cm0plus.s Normal file
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@ -0,0 +1,417 @@
;/**************************************************************************//**
; * @file startup_psoc63_cm0plus.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0plus Device Series
; * @version V5.00
; * @date 08. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec_ram:DATA:NOROOT(2)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
PUBLIC __ramVectors
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD 0x0000000D ; NMI_Handler is defined in ROM code
DCD HardFault_Handler
DCD 0
DCD 0
DCD 0
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD 0
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External interrupts Power Mode Description
DCD NvicMux0_IRQHandler ; CM0 + NVIC Mux input 0
DCD NvicMux1_IRQHandler ; CM0 + NVIC Mux input 1
DCD NvicMux2_IRQHandler ; CM0 + NVIC Mux input 2
DCD NvicMux3_IRQHandler ; CM0 + NVIC Mux input 3
DCD NvicMux4_IRQHandler ; CM0 + NVIC Mux input 4
DCD NvicMux5_IRQHandler ; CM0 + NVIC Mux input 5
DCD NvicMux6_IRQHandler ; CM0 + NVIC Mux input 6
DCD NvicMux7_IRQHandler ; CM0 + NVIC Mux input 7
DCD NvicMux8_IRQHandler ; CM0 + NVIC Mux input 8
DCD NvicMux9_IRQHandler ; CM0 + NVIC Mux input 9
DCD NvicMux10_IRQHandler ; CM0 + NVIC Mux input 10
DCD NvicMux11_IRQHandler ; CM0 + NVIC Mux input 11
DCD NvicMux12_IRQHandler ; CM0 + NVIC Mux input 12
DCD NvicMux13_IRQHandler ; CM0 + NVIC Mux input 13
DCD NvicMux14_IRQHandler ; CM0 + NVIC Mux input 14
DCD NvicMux15_IRQHandler ; CM0 + NVIC Mux input 15
DCD NvicMux16_IRQHandler ; CM0 + NVIC Mux input 16
DCD NvicMux17_IRQHandler ; CM0 + NVIC Mux input 17
DCD NvicMux18_IRQHandler ; CM0 + NVIC Mux input 18
DCD NvicMux19_IRQHandler ; CM0 + NVIC Mux input 19
DCD NvicMux20_IRQHandler ; CM0 + NVIC Mux input 20
DCD NvicMux21_IRQHandler ; CM0 + NVIC Mux input 21
DCD NvicMux22_IRQHandler ; CM0 + NVIC Mux input 22
DCD NvicMux23_IRQHandler ; CM0 + NVIC Mux input 23
DCD NvicMux24_IRQHandler ; CM0 + NVIC Mux input 24
DCD NvicMux25_IRQHandler ; CM0 + NVIC Mux input 25
DCD NvicMux26_IRQHandler ; CM0 + NVIC Mux input 26
DCD NvicMux27_IRQHandler ; CM0 + NVIC Mux input 27
DCD NvicMux28_IRQHandler ; CM0 + NVIC Mux input 28
DCD NvicMux29_IRQHandler ; CM0 + NVIC Mux input 29
DCD NvicMux30_IRQHandler ; CM0 + NVIC Mux input 30
DCD NvicMux31_IRQHandler ; CM0 + NVIC Mux input 31
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
SECTION .intvec_ram:DATA:REORDER:NOROOT(2)
__ramVectors
DS32 __Vectors_Size
THUMB
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default handlers
;;
PUBWEAK Default_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Default_Handler
B Default_Handler
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Saves and disables the interrupts
;;
PUBLIC Cy_SaveIRQ
SECTION .text:CODE:REORDER:NOROOT(2)
Cy_SaveIRQ
MRS r0, PRIMASK
CPSID I
BX LR
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Restores the interrupts
;;
PUBLIC Cy_RestoreIRQ
SECTION .text:CODE:REORDER:NOROOT(2)
Cy_RestoreIRQ
MSR PRIMASK, r0
BX LR
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Weak function for startup customization
;;
PUBWEAK Cy_OnResetUser
SECTION .text:CODE:REORDER:NOROOT(2)
Cy_OnResetUser
BX LR
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
; Define strong function for startup customization
LDR R0, =Cy_OnResetUser
BLX R0
; Copy vectors from ROM to RAM
LDR r1, =__vector_table
LDR r0, =__ramVectors
LDR r2, =__Vectors_Size
intvec_copy
LDR r3, [r1]
STR r3, [r0]
ADDS r0, r0, #4
ADDS r1, r1, #4
SUBS r2, r2, #1
CMP r2, #0
BNE intvec_copy
; Update Vector Table Offset Register
LDR r0, =__ramVectors
LDR r1, =0xE000ED08
STR r0, [r1]
dsb
LDR R0, =__iar_program_start
BLX R0
; Should never get here
Cy_Main_Exited
B Cy_Main_Exited
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK Cy_SysLib_FaultHandler
SECTION .text:CODE:REORDER:NOROOT(1)
Cy_SysLib_FaultHandler
B Cy_SysLib_FaultHandler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
IMPORT Cy_SysLib_FaultHandler
movs r0, #4
mov r1, LR
tst r0, r1
beq L_MSP
mrs r0, PSP
b L_API_call
L_MSP
mrs r0, MSP
L_API_call
; Storing LR content for Creator call stack trace
push {LR}
bl Cy_SysLib_FaultHandler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
; External interrupts
PUBWEAK NvicMux0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux0_IRQHandler
B NvicMux0_IRQHandler
PUBWEAK NvicMux1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux1_IRQHandler
B NvicMux1_IRQHandler
PUBWEAK NvicMux2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux2_IRQHandler
B NvicMux2_IRQHandler
PUBWEAK NvicMux3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux3_IRQHandler
B NvicMux3_IRQHandler
PUBWEAK NvicMux4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux4_IRQHandler
B NvicMux4_IRQHandler
PUBWEAK NvicMux5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux5_IRQHandler
B NvicMux5_IRQHandler
PUBWEAK NvicMux6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux6_IRQHandler
B NvicMux6_IRQHandler
PUBWEAK NvicMux7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux7_IRQHandler
B NvicMux7_IRQHandler
PUBWEAK NvicMux8_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux8_IRQHandler
B NvicMux8_IRQHandler
PUBWEAK NvicMux9_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux9_IRQHandler
B NvicMux9_IRQHandler
PUBWEAK NvicMux10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux10_IRQHandler
B NvicMux10_IRQHandler
PUBWEAK NvicMux11_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux11_IRQHandler
B NvicMux11_IRQHandler
PUBWEAK NvicMux12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux12_IRQHandler
B NvicMux12_IRQHandler
PUBWEAK NvicMux13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux13_IRQHandler
B NvicMux13_IRQHandler
PUBWEAK NvicMux14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux14_IRQHandler
B NvicMux14_IRQHandler
PUBWEAK NvicMux15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux15_IRQHandler
B NvicMux15_IRQHandler
PUBWEAK NvicMux16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux16_IRQHandler
B NvicMux16_IRQHandler
PUBWEAK NvicMux17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux17_IRQHandler
B NvicMux17_IRQHandler
PUBWEAK NvicMux18_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux18_IRQHandler
B NvicMux18_IRQHandler
PUBWEAK NvicMux19_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux19_IRQHandler
B NvicMux19_IRQHandler
PUBWEAK NvicMux20_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux20_IRQHandler
B NvicMux20_IRQHandler
PUBWEAK NvicMux21_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux21_IRQHandler
B NvicMux21_IRQHandler
PUBWEAK NvicMux22_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux22_IRQHandler
B NvicMux22_IRQHandler
PUBWEAK NvicMux23_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux23_IRQHandler
B NvicMux23_IRQHandler
PUBWEAK NvicMux24_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux24_IRQHandler
B NvicMux24_IRQHandler
PUBWEAK NvicMux25_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux25_IRQHandler
B NvicMux25_IRQHandler
PUBWEAK NvicMux26_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux26_IRQHandler
B NvicMux26_IRQHandler
PUBWEAK NvicMux27_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux27_IRQHandler
B NvicMux27_IRQHandler
PUBWEAK NvicMux28_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux28_IRQHandler
B NvicMux28_IRQHandler
PUBWEAK NvicMux29_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux29_IRQHandler
B NvicMux29_IRQHandler
PUBWEAK NvicMux30_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux30_IRQHandler
B NvicMux30_IRQHandler
PUBWEAK NvicMux31_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux31_IRQHandler
B NvicMux31_IRQHandler
END
; [] END OF FILE

41
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/ipc_rpc_m0.c Normal file
View File

@ -0,0 +1,41 @@
/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "psoc6_utils.h"
#include "ipc_rpc.h"
#include "rpc_defs.h"
#include "cy_ipc_config.h"
#include "ipc/cy_ipc_pipe.h"
#undef RPC_GEN
#define RPC_GEN RPC_GEN_IMPLEMENTATION
#include "rpc_defs.h"
#include "rpc_api.h"
#undef RPC_GEN
#define RPC_GEN RPC_GEN_INITIALIZATION
void ipcrpc_init(void)
{
uint32_t rpc_counter = 0;
#include "rpc_defs.h"
#include "rpc_api.h"
}
/* [] END OF FILE */

109
targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/system_psoc63_cm0plus.c → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/system_psoc63_cm0plus.c
View File

@ -1,26 +1,35 @@
/***************************************************************************//** /***************************************************************************//**
* \file system_psoc63_cm0plus.c * \file system_psoc63_cm0plus.c
* \version 2.0 * \version 2.10
* *
* The device system-source file. * The device system-source file.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
*******************************************************************************/ *******************************************************************************/
/*
* Copyright (c) 20017-2018 Future Electronics
*/
#include <stdint.h> #include <stdint.h>
#include <stdbool.h> #include <stdbool.h>
#include "device.h"
#include "system_psoc63.h" #include "system_psoc63.h"
#include "cy_device_headers.h" #include "cy_device_headers.h"
#if defined(CY_DEVICE_PSOC6ABLE2)
#if !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
#include "syslib/cy_syslib.h"
#endif /* !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) #if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#include "ipc/cy_ipc_pipe.h" #include "ipc/cy_ipc_drv.h"
#include "ipc/cy_ipc_sema.h" #include "flash/cy_flash.h"
#endif /* CY_IPC_DEFAULT_CFG_DISABLE */ #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
/******************************************************************************* /*******************************************************************************
@ -28,41 +37,28 @@
*******************************************************************************/ *******************************************************************************/
/** Default HFClk frequency in Hz */ /** Default HFClk frequency in Hz */
#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT ( 8000000UL) #define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT CY_CLK_HFCLK0_FREQ_HZ
/** Default PeriClk frequency in Hz */ /** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT CY_CLK_PERICLK_FREQ_HZ
/** Default SlowClk system core frequency in Hz */ /** Default SlowClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT CY_CLK_SLOWCLK_FREQ_HZ
/** IMO frequency in Hz */ /**
#define CY_CLK_IMO_FREQ_HZ (8000000UL) * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
* which is the system clock frequency supplied to the SysTick timer and the
/** HVILO frequency in Hz */ * processor core clock.
#define CY_CLK_HVILO_FREQ_HZ (32000UL) * This variable implements CMSIS Core global variable.
* Refer to the [CMSIS documentation]
#if (SRSS_PILO_PRESENT == 1U) || defined(CY_DOXYGEN) * (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
/** PILO frequency in Hz */ * for more details.
#define CY_CLK_PILO_FREQ_HZ (32768UL) * This variable can be used by debuggers to query the frequency
#endif /* (SRSS_PILO_PRESENT == 1U) || defined(CY_DOXYGEN) */ * of the debug timer or to configure the trace clock speed.
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ (32768UL)
#if (SRSS_ALTLF_PRESENT == 1U) || defined(CY_DOXYGEN)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
#endif /* (SRSS_ALTLF_PRESENT == 1U) || defined(CY_DOXYGEN) */
/** Holds the SlowClk system core clock, which is the system clock frequency supplied to the SysTick timer and the
* processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure
* the trace clock speed.
* *
* \attention Compilers must be configured to avoid removing this variable in case the application program is not using * \attention Compilers must be configured to avoid removing this variable in case
* it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure * the application program is not using it. Debugging systems require the variable
* the debugger. */ * to be physically present in memory so that it can be examined to configure the debugger. */
uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ /** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
@ -137,6 +133,29 @@ uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL) #define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL)
/*******************************************************************************
* Function Name: mbed_sdk_init
****************************************************************************//**
*
* Mbed's post-memory-initialization function.
* Used here to initialize common parts of the Cypress libraries.
*
*******************************************************************************/
void mbed_sdk_init(void)
{
/* Initialize shared resource manager */
cy_srm_initialize();
/* Initialize system and clocks. */
/* Placed here as it must be done after proper LIBC initialization. */
SystemInit();
/* Allocate and initialize semaphores for the system operations. */
Cy_IPC_SystemSemaInit();
Cy_IPC_SystemPipeInit();
Cy_Flash_Init();
ipcrpc_init();
}
/******************************************************************************* /*******************************************************************************
* Function Name: SystemInit * Function Name: SystemInit
****************************************************************************//** ****************************************************************************//**
@ -164,27 +183,33 @@ void SystemInit(void)
SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
/* Unlock and disable WDT */ /* Unlock and disable WDT */
SRSS->WDT_CTL = ((SRSS->WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_WDT_LOCK_BIT0); SRSS->WDT_CTL = ((SRSS->WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_WDT_LOCK_BIT0);
SRSS->WDT_CTL = (SRSS->WDT_CTL | CY_WDT_LOCK_BIT1); SRSS->WDT_CTL = (SRSS->WDT_CTL | CY_WDT_LOCK_BIT1);
SRSS->WDT_CTL &= (~ (uint32_t) SRSS_WDT_CTL_WDT_EN_Msk); SRSS->WDT_CTL &= (~ (uint32_t) SRSS_WDT_CTL_WDT_EN_Msk);
Cy_SystemInit(); Cy_SystemInit();
SystemCoreClockUpdate(); SystemCoreClockUpdate();
#if defined(CY_DEVICE_PSOC6ABLE2)
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) #if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/* Allocate and initialize semaphores for the system operations. */ /* Allocate and initialize semaphores for the system operations. */
Cy_IPC_SystemSemaInit(); Cy_IPC_SystemSemaInit();
Cy_IPC_SystemPipeInit(); Cy_IPC_SystemPipeInit();
Cy_Flash_Init();
#endif /* CY_IPC_DEFAULT_CFG_DISABLE */ #endif /* CY_IPC_DEFAULT_CFG_DISABLE */
/* Clear data register of IPC structure #7, reserved for the Deep Sleep operations. */ #if !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
{
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
IPC_STRUCT7->DATA = 0UL; IPC_STRUCT7->DATA = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep Sleep entering. */ /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
IPC_STRUCT7->RELEASE = 0UL; IPC_STRUCT7->RELEASE = 0UL;
} }
#endif /* !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
#endif /* CY_DEVICE_PSOC6ABLE2 */
}
/******************************************************************************* /*******************************************************************************
@ -550,7 +575,7 @@ void Cy_SysResetCM4(void)
* *
* The intention of the function is to declare boundaries of the memories for the * The intention of the function is to declare boundaries of the memories for the
* MDK compilers. For the rest of the supported compilers, this is done using * MDK compilers. For the rest of the supported compilers, this is done using
* linker configuration files. The following symbols used by the cypdlelftool. * linker configuration files. The following symbols used by the cymcuelftool.
* *
*******************************************************************************/ *******************************************************************************/
#if defined (__ARMCC_VERSION) #if defined (__ARMCC_VERSION)
@ -587,9 +612,9 @@ __cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) __cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
__cy_memory_0_row_size EQU 0x200 __cy_memory_0_row_size EQU 0x200
/* Working Flash */ /* Flash region for EEPROM emulation */
__cy_memory_1_start EQU __cpp(CY_WFLASH_BASE) __cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
__cy_memory_1_length EQU __cpp(CY_WFLASH_SIZE) __cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
__cy_memory_1_row_size EQU 0x200 __cy_memory_1_row_size EQU 0x200
/* Supervisory Flash */ /* Supervisory Flash */

214
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_ARM_STD/cy8c6xx7_cm4_dual.sct Normal file
View File

@ -0,0 +1,214 @@
#! armcc -E
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file cy8c6xx7_cm4_dual.scat
;* \version 2.10
;*
;* Linker file for the ARMCC.
;*
;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory
;* layout of the output file.
;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there.
;*
;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker
;* file.
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
;* You may use this file only in accordance with the license, terms, conditions,
;* disclaimers, and limitations in the end user license agreement accompanying
;* the software package with which this file was provided.
;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM
; RAM
#define RAM_START 0x08010000
#define RAM_SIZE 0x00037800
; Flash
; Flash
#define FLASH_START 0x10080000
#define FLASH_SIZE 0x00078000
; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200
; External memory
#define XIP_START 0x18000000
#define XIP_SIZE 0x08000000
; eFuse
#define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000
LR_IROM1 FLASH_START FLASH_SIZE
{
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}
ER_FLASH_CODE +0 FIXED
{
* (InRoot$$Sections)
* (+RO)
}
ER_RAM_VECTORS RAM_START UNINIT
{
* (RESET_RAM, +FIRST)
}
RW_RAM_DATA +0
{
* (.cy_ramfunc)
.ANY (+RW, +ZI)
}
; Place variables in the section that should not be initialized during the
; device startup.
RW_IRAM1 +0 UNINIT
{
* (.noinit)
}
; Used for the digital signature of the secure application and the
; Bootloader SDK appication. The size of the section depends on the required
; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{
* (.cy_app_signature)
}
}
; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{
.cy_em_eeprom +0
{
* (.cy_em_eeprom)
}
}
; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{
.cy_sflash_user_data +0
{
* (.cy_sflash_user_data)
}
}
; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{
.cy_sflash_nar +0
{
* (.cy_sflash_nar)
}
}
; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{
.cy_sflash_public_key +0
{
* (.cy_sflash_public_key)
}
}
; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{
.cy_toc_part2 +0
{
* (.cy_toc_part2)
}
}
; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{
.cy_rtoc_part2 +0
{
* (.cy_rtoc_part2)
}
}
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE
{
.cy_xip +0
{
* (.cy_xip)
}
}
; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE
{
.cy_efuse +0
{
* (.cy_efuse)
}
}
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000
{
.cymeta +0 { * (.cymeta) }
}
/* [] END OF FILE */

654
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_ARM_STD/startup_psoc63_cm4.s Normal file
View File

@ -0,0 +1,654 @@
;/**************************************************************************//**
; * @file startup_psoc63_cm4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
__initial_sp EQU 0x08047800
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External interrupts Power Mode Description
DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0
DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1
DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2
DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3
DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4
DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5
DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6
DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7
DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8
DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9
DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10
DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11
DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12
DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13
DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14
DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports
DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt
DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt
DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable)
DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)
DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms)
DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt
DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0
DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1
DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2
DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3
DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4
DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5
DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6
DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7
DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8
DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9
DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10
DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11
DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12
DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13
DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14
DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15
DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0
DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1
DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2
DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3
DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4
DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5
DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6
DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7
DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0
DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1
DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2
DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3
DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4
DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5
DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6
DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7
DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8
DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9
DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10
DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11
DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12
DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13
DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14
DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15
DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0
DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1
DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2
DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3
DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4
DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5
DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6
DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7
DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8
DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9
DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10
DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11
DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12
DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13
DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14
DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15
DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0
DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1
DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt
DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt
DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0
DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1
DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0
DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1
DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0
DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1
DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2
DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3
DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4
DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5
DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6
DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7
DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0
DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1
DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2
DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3
DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4
DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5
DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6
DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7
DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8
DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9
DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10
DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11
DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12
DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13
DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14
DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15
DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16
DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17
DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18
DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19
DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20
DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21
DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22
DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23
DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0
DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1
DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2
DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3
DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4
DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5
DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6
DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7
DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8
DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9
DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10
DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11
DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12
DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13
DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14
DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15
DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt
DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt
DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt
DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
DCD usb_interrupt_hi_IRQHandler ; USB Interrupt
DCD usb_interrupt_med_IRQHandler ; USB Interrupt
DCD usb_interrupt_lo_IRQHandler ; USB Interrupt
DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
EXPORT __ramVectors
AREA RESET_RAM, READWRITE, NOINIT
__ramVectors SPACE __Vectors_Size
AREA |.text|, CODE, READONLY
; Saves and disables the interrupts
Cy_SaveIRQ PROC
EXPORT Cy_SaveIRQ
MRS r0, PRIMASK
CPSID I
BX LR
ENDP
; Restores the interrupts
Cy_RestoreIRQ PROC
EXPORT Cy_RestoreIRQ
MSR PRIMASK, r0
BX LR
ENDP
; Weak function for startup customization
Cy_OnResetUser PROC
EXPORT Cy_OnResetUser [WEAK]
BX LR
ENDP
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT Cy_SystemInitFpuEnable
IMPORT __main
; Define strong function for startup customization
BL Cy_OnResetUser
; Copy vectors from ROM to RAM
LDR r1, =__Vectors
LDR r0, =__ramVectors
LDR r2, =__Vectors_Size
Vectors_Copy
LDR r3, [r1]
STR r3, [r0]
ADDS r0, r0, #4
ADDS r1, r1, #4
SUBS r2, r2, #1
CMP r2, #0
BNE Vectors_Copy
; Update Vector Table Offset Register. */
LDR r0, =__ramVectors
LDR r1, =0xE000ED08
STR r0, [r1]
dsb 0xF
; Enable the FPU if used
LDR R0, =Cy_SystemInitFpuEnable
BLX R0
LDR R0, =__main
BLX R0
; Should never get here
B .
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
Cy_SysLib_FaultHandler PROC
EXPORT Cy_SysLib_FaultHandler [WEAK]
B .
ENDP
HardFault_Wrapper\
PROC
EXPORT HardFault_Wrapper [WEAK]
movs r0, #4
mov r1, LR
tst r0, r1
beq L_MSP
mrs r0, PSP
bl L_API_call
L_MSP
mrs r0, MSP
L_API_call
bl Cy_SysLib_FaultHandler
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B HardFault_Wrapper
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B HardFault_Wrapper
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B HardFault_Wrapper
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B HardFault_Wrapper
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT Default_Handler [WEAK]
EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK]
EXPORT ioss_interrupt_gpio_IRQHandler [WEAK]
EXPORT ioss_interrupt_vdd_IRQHandler [WEAK]
EXPORT lpcomp_interrupt_IRQHandler [WEAK]
EXPORT scb_8_interrupt_IRQHandler [WEAK]
EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK]
EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK]
EXPORT srss_interrupt_backup_IRQHandler [WEAK]
EXPORT srss_interrupt_IRQHandler [WEAK]
EXPORT pass_interrupt_ctbs_IRQHandler [WEAK]
EXPORT bless_interrupt_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK]
EXPORT scb_0_interrupt_IRQHandler [WEAK]
EXPORT scb_1_interrupt_IRQHandler [WEAK]
EXPORT scb_2_interrupt_IRQHandler [WEAK]
EXPORT scb_3_interrupt_IRQHandler [WEAK]
EXPORT scb_4_interrupt_IRQHandler [WEAK]
EXPORT scb_5_interrupt_IRQHandler [WEAK]
EXPORT scb_6_interrupt_IRQHandler [WEAK]
EXPORT scb_7_interrupt_IRQHandler [WEAK]
EXPORT csd_interrupt_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK]
EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK]
EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK]
EXPORT cpuss_interrupt_fm_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK]
EXPORT udb_interrupts_0_IRQHandler [WEAK]
EXPORT udb_interrupts_1_IRQHandler [WEAK]
EXPORT udb_interrupts_2_IRQHandler [WEAK]
EXPORT udb_interrupts_3_IRQHandler [WEAK]
EXPORT udb_interrupts_4_IRQHandler [WEAK]
EXPORT udb_interrupts_5_IRQHandler [WEAK]
EXPORT udb_interrupts_6_IRQHandler [WEAK]
EXPORT udb_interrupts_7_IRQHandler [WEAK]
EXPORT udb_interrupts_8_IRQHandler [WEAK]
EXPORT udb_interrupts_9_IRQHandler [WEAK]
EXPORT udb_interrupts_10_IRQHandler [WEAK]
EXPORT udb_interrupts_11_IRQHandler [WEAK]
EXPORT udb_interrupts_12_IRQHandler [WEAK]
EXPORT udb_interrupts_13_IRQHandler [WEAK]
EXPORT udb_interrupts_14_IRQHandler [WEAK]
EXPORT udb_interrupts_15_IRQHandler [WEAK]
EXPORT pass_interrupt_sar_IRQHandler [WEAK]
EXPORT audioss_interrupt_i2s_IRQHandler [WEAK]
EXPORT audioss_interrupt_pdm_IRQHandler [WEAK]
EXPORT profile_interrupt_IRQHandler [WEAK]
EXPORT smif_interrupt_IRQHandler [WEAK]
EXPORT usb_interrupt_hi_IRQHandler [WEAK]
EXPORT usb_interrupt_med_IRQHandler [WEAK]
EXPORT usb_interrupt_lo_IRQHandler [WEAK]
EXPORT pass_interrupt_dacs_IRQHandler [WEAK]
ioss_interrupts_gpio_0_IRQHandler
ioss_interrupts_gpio_1_IRQHandler
ioss_interrupts_gpio_2_IRQHandler
ioss_interrupts_gpio_3_IRQHandler
ioss_interrupts_gpio_4_IRQHandler
ioss_interrupts_gpio_5_IRQHandler
ioss_interrupts_gpio_6_IRQHandler
ioss_interrupts_gpio_7_IRQHandler
ioss_interrupts_gpio_8_IRQHandler
ioss_interrupts_gpio_9_IRQHandler
ioss_interrupts_gpio_10_IRQHandler
ioss_interrupts_gpio_11_IRQHandler
ioss_interrupts_gpio_12_IRQHandler
ioss_interrupts_gpio_13_IRQHandler
ioss_interrupts_gpio_14_IRQHandler
ioss_interrupt_gpio_IRQHandler
ioss_interrupt_vdd_IRQHandler
lpcomp_interrupt_IRQHandler
scb_8_interrupt_IRQHandler
srss_interrupt_mcwdt_0_IRQHandler
srss_interrupt_mcwdt_1_IRQHandler
srss_interrupt_backup_IRQHandler
srss_interrupt_IRQHandler
pass_interrupt_ctbs_IRQHandler
bless_interrupt_IRQHandler
cpuss_interrupts_ipc_0_IRQHandler
cpuss_interrupts_ipc_1_IRQHandler
cpuss_interrupts_ipc_2_IRQHandler
cpuss_interrupts_ipc_3_IRQHandler
cpuss_interrupts_ipc_4_IRQHandler
cpuss_interrupts_ipc_5_IRQHandler
cpuss_interrupts_ipc_6_IRQHandler
cpuss_interrupts_ipc_7_IRQHandler
cpuss_interrupts_ipc_8_IRQHandler
cpuss_interrupts_ipc_9_IRQHandler
cpuss_interrupts_ipc_10_IRQHandler
cpuss_interrupts_ipc_11_IRQHandler
cpuss_interrupts_ipc_12_IRQHandler
cpuss_interrupts_ipc_13_IRQHandler
cpuss_interrupts_ipc_14_IRQHandler
cpuss_interrupts_ipc_15_IRQHandler
scb_0_interrupt_IRQHandler
scb_1_interrupt_IRQHandler
scb_2_interrupt_IRQHandler
scb_3_interrupt_IRQHandler
scb_4_interrupt_IRQHandler
scb_5_interrupt_IRQHandler
scb_6_interrupt_IRQHandler
scb_7_interrupt_IRQHandler
csd_interrupt_IRQHandler
cpuss_interrupts_dw0_0_IRQHandler
cpuss_interrupts_dw0_1_IRQHandler
cpuss_interrupts_dw0_2_IRQHandler
cpuss_interrupts_dw0_3_IRQHandler
cpuss_interrupts_dw0_4_IRQHandler
cpuss_interrupts_dw0_5_IRQHandler
cpuss_interrupts_dw0_6_IRQHandler
cpuss_interrupts_dw0_7_IRQHandler
cpuss_interrupts_dw0_8_IRQHandler
cpuss_interrupts_dw0_9_IRQHandler
cpuss_interrupts_dw0_10_IRQHandler
cpuss_interrupts_dw0_11_IRQHandler
cpuss_interrupts_dw0_12_IRQHandler
cpuss_interrupts_dw0_13_IRQHandler
cpuss_interrupts_dw0_14_IRQHandler
cpuss_interrupts_dw0_15_IRQHandler
cpuss_interrupts_dw1_0_IRQHandler
cpuss_interrupts_dw1_1_IRQHandler
cpuss_interrupts_dw1_2_IRQHandler
cpuss_interrupts_dw1_3_IRQHandler
cpuss_interrupts_dw1_4_IRQHandler
cpuss_interrupts_dw1_5_IRQHandler
cpuss_interrupts_dw1_6_IRQHandler
cpuss_interrupts_dw1_7_IRQHandler
cpuss_interrupts_dw1_8_IRQHandler
cpuss_interrupts_dw1_9_IRQHandler
cpuss_interrupts_dw1_10_IRQHandler
cpuss_interrupts_dw1_11_IRQHandler
cpuss_interrupts_dw1_12_IRQHandler
cpuss_interrupts_dw1_13_IRQHandler
cpuss_interrupts_dw1_14_IRQHandler
cpuss_interrupts_dw1_15_IRQHandler
cpuss_interrupts_fault_0_IRQHandler
cpuss_interrupts_fault_1_IRQHandler
cpuss_interrupt_crypto_IRQHandler
cpuss_interrupt_fm_IRQHandler
cpuss_interrupts_cm0_cti_0_IRQHandler
cpuss_interrupts_cm0_cti_1_IRQHandler
cpuss_interrupts_cm4_cti_0_IRQHandler
cpuss_interrupts_cm4_cti_1_IRQHandler
tcpwm_0_interrupts_0_IRQHandler
tcpwm_0_interrupts_1_IRQHandler
tcpwm_0_interrupts_2_IRQHandler
tcpwm_0_interrupts_3_IRQHandler
tcpwm_0_interrupts_4_IRQHandler
tcpwm_0_interrupts_5_IRQHandler
tcpwm_0_interrupts_6_IRQHandler
tcpwm_0_interrupts_7_IRQHandler
tcpwm_1_interrupts_0_IRQHandler
tcpwm_1_interrupts_1_IRQHandler
tcpwm_1_interrupts_2_IRQHandler
tcpwm_1_interrupts_3_IRQHandler
tcpwm_1_interrupts_4_IRQHandler
tcpwm_1_interrupts_5_IRQHandler
tcpwm_1_interrupts_6_IRQHandler
tcpwm_1_interrupts_7_IRQHandler
tcpwm_1_interrupts_8_IRQHandler
tcpwm_1_interrupts_9_IRQHandler
tcpwm_1_interrupts_10_IRQHandler
tcpwm_1_interrupts_11_IRQHandler
tcpwm_1_interrupts_12_IRQHandler
tcpwm_1_interrupts_13_IRQHandler
tcpwm_1_interrupts_14_IRQHandler
tcpwm_1_interrupts_15_IRQHandler
tcpwm_1_interrupts_16_IRQHandler
tcpwm_1_interrupts_17_IRQHandler
tcpwm_1_interrupts_18_IRQHandler
tcpwm_1_interrupts_19_IRQHandler
tcpwm_1_interrupts_20_IRQHandler
tcpwm_1_interrupts_21_IRQHandler
tcpwm_1_interrupts_22_IRQHandler
tcpwm_1_interrupts_23_IRQHandler
udb_interrupts_0_IRQHandler
udb_interrupts_1_IRQHandler
udb_interrupts_2_IRQHandler
udb_interrupts_3_IRQHandler
udb_interrupts_4_IRQHandler
udb_interrupts_5_IRQHandler
udb_interrupts_6_IRQHandler
udb_interrupts_7_IRQHandler
udb_interrupts_8_IRQHandler
udb_interrupts_9_IRQHandler
udb_interrupts_10_IRQHandler
udb_interrupts_11_IRQHandler
udb_interrupts_12_IRQHandler
udb_interrupts_13_IRQHandler
udb_interrupts_14_IRQHandler
udb_interrupts_15_IRQHandler
pass_interrupt_sar_IRQHandler
audioss_interrupt_i2s_IRQHandler
audioss_interrupt_pdm_IRQHandler
profile_interrupt_IRQHandler
smif_interrupt_IRQHandler
usb_interrupt_hi_IRQHandler
usb_interrupt_med_IRQHandler
usb_interrupt_lo_IRQHandler
pass_interrupt_dacs_IRQHandler
B .
ENDP
ALIGN
END
; [] END OF FILE

126
targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
View File

@ -1,9 +1,13 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy8c6xx7_cm4_dual.ld * \file cy8c6xx7_cm4_dual.ld
* \version 2.0 * \version 2.10
* *
* Linker file for the GNU C compiler. * Linker file for the GNU C compiler.
* *
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point location is fixed and starts at 0x10000000. The valid * \note The entry point location is fixed and starts at 0x10000000. The valid
* application image should be placed there. * application image should be placed there.
* *
@ -15,7 +19,7 @@
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -35,22 +39,38 @@ ENTRY(Reset_Handler)
*/ */
EXTERN(Reset_Handler) EXTERN(Reset_Handler)
/* The MEMORY section below describes the location and size of blocks of memory in the target.
/* Linker script to configure memory regions. */ * Use this section to specify the memory regions available for allocation.
*/
MEMORY MEMORY
{ {
flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x80000 /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
wflash (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ * You can change the memory allocation by editing the 'ram' and 'flash' regions.
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 * Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use.
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 * Using this memory region for other purposes will lead to unexpected behavior.
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x400 * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
ram (rwx) : ORIGIN = 0x08010000, LENGTH = 0x37800
flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x78000
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
/* The following regions define device specific memory regions and must not be changed. */
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x23800
} }
/* Library configurations */ /* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a) GROUP(libgcc.a libc.a libm.a libnosys.a)
@ -124,6 +144,34 @@ SECTIONS
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*)) KEEP(*(.eh_frame*))
/* To copy multiple ROM to RAM sections,
* uncomment copy table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc63_cm4.S */
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy interrupt vectors from flash to RAM */
LONG (__Vectors) /* From */
LONG (__ram_vectors_start__) /* To */
LONG (__Vectors_End - __Vectors) /* Size */
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG (__data_end__ - __data_start__) /* Size */
__copy_table_end__ = .;
/* To clear multiple BSS sections,
* uncomment zero table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc63_cm4.S */
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > flash } > flash
@ -140,41 +188,6 @@ SECTIONS
} > flash } > flash
__exidx_end = .; __exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc63_cm4.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy interrupt vectors from flash to RAM */
LONG (__Vectors) /* From */
LONG (__ram_vectors_start__) /* To */
LONG (__Vectors_End - __Vectors) /* Size */
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG (__data_end__ - __data_start__) /* Size */
__copy_table_end__ = .;
} > flash
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc63_cm4.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > flash
__etext = . ; __etext = . ;
@ -294,11 +307,11 @@ SECTIONS
} > flash } > flash
/* Work Flash */ /* Emulated EEPROM Flash area */
.cy_wflash : .cy_em_eeprom :
{ {
KEEP(*(.cy_wflash)) KEEP(*(.cy_em_eeprom))
} > wflash } > em_eeprom
/* Supervisory Flash: User data */ /* Supervisory Flash: User data */
@ -329,6 +342,13 @@ SECTIONS
} > sflash_toc_2 } > sflash_toc_2
/* Supervisory Flash: Table of Content # 2 Copy */
.cy_rtoc_part2 :
{
KEEP(*(.cy_rtoc_part2))
} > sflash_rtoc_2
/* Places the code in the Execute in Place (XIP) section. See the smif driver /* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details. * documentation for details.
*/ */
@ -352,13 +372,13 @@ SECTIONS
} }
/* The following symbols used by the cypdlelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
__cy_memory_0_start = 0x10000000; __cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x00100000; __cy_memory_0_length = 0x00100000;
__cy_memory_0_row_size = 0x200; __cy_memory_0_row_size = 0x200;
/* Working Flash */ /* Emulated EEPROM Flash area */
__cy_memory_1_start = 0x14000000; __cy_memory_1_start = 0x14000000;
__cy_memory_1_length = 0x8000; __cy_memory_1_length = 0x8000;
__cy_memory_1_row_size = 0x200; __cy_memory_1_row_size = 0x200;

7
targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/device/TOOLCHAIN_GCC_ARM/startup_psoc63_cm4.S → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_GCC_ARM/startup_psoc63_cm4.S
View File

@ -293,7 +293,6 @@ Cy_RestoreIRQ:
Reset_Handler: Reset_Handler:
bl Cy_OnResetUser bl Cy_OnResetUser
cpsid i
/* Firstly it copies data from read only memory to RAM. There are two schemes /* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy * to copy. One can copy more than one sections. Another can only copy
@ -421,11 +420,7 @@ Reset_Handler:
/* Enable the FPU if used */ /* Enable the FPU if used */
bl Cy_SystemInitFpuEnable bl Cy_SystemInitFpuEnable
#ifndef __NO_SYSTEM_INIT bl _start
bl SystemInit
#endif
bl main
/* Should never get here */ /* Should never get here */
b . b .

219
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf Normal file
View File

@ -0,0 +1,219 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.icf
* \version 2.10
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = 0x08010000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x100F8000;
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = 0x1000;
} else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
}
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x3800;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block RO {first section .intvec, readonly};
/*-Initializations-*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash */
place at start of IROM1_region { block RO };
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */
".cy_xip" : place at start of EROM1_region { section .cy_xip };
/* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_app_signature,
section .cy_em_eeprom,
section .cy_sflash_user_data,
section .cy_sflash_nar,
section .cy_sflash_public_key,
section .cy_toc_part2,
section .cy_rtoc_part2,
section .cy_efuse,
section .cy_xip,
section .cymeta,
};
/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00100000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */
define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;
/* EOF */

1148
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_IAR/startup_psoc63_cm4.s Normal file
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File diff suppressed because it is too large Load Diff

198
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/psoc63_m0_default_1.0.hex Normal file
View File

@ -0,0 +1,198 @@
:020000041000EA
:4000000000000108310100100D00000095010010000000000000000000000000000000000000000000000000000000009101001000000000000000009101001091010010DC
:400040009101001095090010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001054
:400080009101001091010010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001020
:4000C00010B5064C2378002B07D1054B002B02D0044800E000BF0123237010BD8C04000800000000C82A0010084B10B5002B03D00749084800E000BF07480368002B00D1EA
:4001000010BD064B002BFBD09847F9E70000000090040008C82A001024010008000000007047EFF3108072B6704780F310887047FFF7F6FF72B6104C104DAC4209DA216831
:400140006268A368043B02DBC858D050FAE70C34F3E70B490B4A0020521A02DD043A8850FCDC094809490860BFF34F8F00F00EF900F01EF8FEE70000CC2A0010E42A0010B0
:400180008C0400089C0700080000000808ED00E0FEE7FEE700B504207146084202D0EFF3098001E0EFF30880043001F0DFFEFEE710B500F0CBF962B6064B5B689B0301D5F3
:4001C00001F084FE044800F055F9002001F0F6FDFBE7C046000026400000081070B56249E0239B00CB580F2213401A00D0329200525807210A40032A05D0042A06D0002A89
:4002000012D15A4814E05A4A106811E01A00C0329200554952581F210A40112A06D0132A04D0FA20C00103E0524801E080200002002B36D14C4BB222D2009A5801211140F7
:40024000B125ED005A59120F032422405B591B0F1C4207D0444C63591B0F03242340012B02D102E0012300E00023002B01D0002901D1032A4BD13C4BB022D2009D58AD0333
:40028000AD0B3D495958C904C90C9C58240E01231C40013402F0BCF96843210002F0B8F935E0012B33D1304BC822D2009A5801251540C024E4001A59120F03210A401B5995
:4002C0001B0F194207D028490B591B0F03210B40012B02D102E0012300E00023002B01D0002D01D1032A12D11F4DC022D200AB587F210B40A958090A1F263140AC58240C15
:400300003440584302F084F9210002F081F9E0239B00154AD3581B0903221340D840144C6060164B1D692D0AFC32154001351969090E013102F06CF9A060290002F068F941
:400340000500E06020610E4BC0180E4902F060F920750D4BE818FA21890002F059F9A061C003E06170BDC0460000264000127A00C000000800366E0184050000000021408E
:400380003F420F0040420F00E703000010B5234BB021C9005A58520052085A50E02080001A583024A2431A50802252045A501C491C4A9950A021890104329950FF211A4A84
:4003C000995081315A58920092088020C00502435A505A588020000602435A505A58012082435A5000F0E0FBFFF7F8FE00F0DAFA00F0E2FA01F050F9B0235B055B78002BF5
:4004000004D0B0235B055B78DBB200E02123212B03D1064B0022DA605A6010BD0000264001000200840500008C050000E00023408023024AD358032018407047000021406A
:4004400010B5FFF76EFE084980228C58074B2340074C23438B508823034AD358DB06FAD5FFF763FE10BDC04600002140FCFF00000100FA0570B50500FFF753FE0400FFF771
:40048000D7FF032801D1FFF7DBFF0A4AB0239B00D55080215058084B03400848034353508823044AD358DB06FAD52000FFF73DFE70BDC04600002140FCFF00000300FA05E4
:4004C00010B50400007B00F057F9606010BDC04610B50400007B216900F0DCF8606010BD10B50169007B00F00FF910BD10B50400C06800F09BF9606010BDC04610B5C06862
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125
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/ipc_rpc.cpp Normal file
View File

@ -0,0 +1,125 @@
/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ipc_rpc.h"
#include "Mutex.h"
#include "Semaphore.h"
#include "mbed_assert.h"
#include "cy_ipc_config.h"
#include "ipc/cy_ipc_pipe.h"
#include <stdarg.h>
#include "platform/SingletonPtr.h"
using namespace rtos;
static SingletonPtr<Mutex> msg_mutex;
static SingletonPtr<Semaphore> msg_semaphore;
#define RPC_GEN RPC_GEN_INTERFACE_IDS
#include "rpc_defs.h"
#include "rpc_api.h"
#undef RPC_GEN
extern "C" {
void ipcrpc_release(void)
{
// Just signal on semaphore that we are done with a call.
msg_semaphore->release();
}
uint32_t ipcrpc_call(uint32_t call_id, uint32_t args_num, ...)
{
va_list ap;
static IpcRpcMessage message;
cy_en_ipc_pipe_status_t status;
ScopedMutexLock lock(*msg_mutex.get());
// Make sure semaphore is initialized.
(void)msg_semaphore.get();
// Copy data to the buffer.
message.client_id = call_id;
message.args_num = args_num;
message.result = 0; // default result
va_start(ap, args_num);
for (uint32_t i = 0; i < args_num; ++i) {
message.args[i] = va_arg (ap, uint32_t);
}
va_end (ap);
// send message
status = Cy_IPC_Pipe_SendMessage(CY_IPC_EP_RPCPIPE_DEST,
CY_IPC_EP_RPCPIPE_ADDR,
&message,
ipcrpc_release);
// We are using dedicated IPC channel here and have locked global mutex
// so this had to succeed.
MBED_ASSERT(status == CY_IPC_PIPE_SUCCESS);
// Now wait for the response;
msg_semaphore->wait();
return message.result;
}
#define RPC_GEN RPC_GEN_INTERFACE_IDS_INIT
void ipcrpc_init(void)
{
uint32_t rpc_counter = 0;
#include "rpc_defs.h"
#include "rpc_api.h"
}
#undef RPC_GEN
#define RPC_GEN RPC_GEN_INTERFACE
#include "rpc_defs.h"
#include "rpc_api.h"
/////////
#undef RPC_GEN
#define RPC_GEN RPC_GEN_IMPLEMENTATION
#include "rpc_defs.h"
#include "rpc_api.h"
#undef RPC_GEN
#define RPC_GEN RPC_GEN_INITIALIZATION
void ipcrpc_init2(void)
{
uint32_t rpc_counter = 0;
#include "rpc_defs.h"
#include "rpc_api.h"
}
} /* extern "C" */
/* [] END OF FILE */

118
targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/system_psoc63_cm4.c → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/system_psoc63_cm4.c
View File

@ -1,26 +1,31 @@
/***************************************************************************//** /***************************************************************************//**
* \file system_psoc63_cm4.c * \file system_psoc63_cm4.c
* \version 2.0 * \version 2.10
* *
* The device system-source file. * The device system-source file.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
*******************************************************************************/ *******************************************************************************/
/*
* Copyright (c) 20017-2018 Future Electronics
*/
#include <stdint.h> #include <stdint.h>
#include <stdbool.h> #include <stdbool.h>
#include "device.h"
#include "system_psoc63.h" #include "system_psoc63.h"
#include "cy_device_headers.h" #include "cy_device_headers.h"
#include "ipc_rpc.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) #if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#include "ipc/cy_ipc_pipe.h" #include "ipc/cy_ipc_drv.h"
#include "ipc/cy_ipc_sema.h" #include "flash/cy_flash.h"
#endif /* CY_IPC_DEFAULT_CFG_DISABLE */ #endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
/******************************************************************************* /*******************************************************************************
@ -28,41 +33,28 @@
*******************************************************************************/ *******************************************************************************/
/** Default HFClk frequency in Hz */ /** Default HFClk frequency in Hz */
#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT ( 8000000UL) #define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT CY_CLK_HFCLK0_FREQ_HZ
/** Default PeriClk frequency in Hz */ /** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT CY_CLK_PERICLK_FREQ_HZ
/** Default SlowClk system core frequency in Hz */ /** Default SlowClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT CY_CLK_HFCLK0_FREQ_HZ
/** IMO frequency in Hz */
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
/** HVILO frequency in Hz */
#define CY_CLK_HVILO_FREQ_HZ (32000UL)
#if (SRSS_PILO_PRESENT == 1U) || defined(CY_DOXYGEN)
/** PILO frequency in Hz */
#define CY_CLK_PILO_FREQ_HZ (32768UL)
#endif /* (SRSS_PILO_PRESENT == 1U) || defined(CY_DOXYGEN) */
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ (32768UL)
#if (SRSS_ALTLF_PRESENT == 1U) || defined(CY_DOXYGEN)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
#endif /* (SRSS_ALTLF_PRESENT == 1U) || defined(CY_DOXYGEN) */
/** Holds the FastClk system core clock, which is the system clock frequency supplied to the SysTick timer and the /*
* processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure * Holds the FastClk system core clock, which is the system clock frequency
* the trace clock speed. * supplied to the SysTick timer and the processor core clock.
* This variable implements CMSIS Core global variable.
* Refer to the [CMSIS documentation]
* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
* for more details.
* This variable can be used by debuggers to query the frequency
* of the debug timer or to configure the trace clock speed.
* *
* \attention Compilers must be configured to avoid removing this variable in case the application program is not using * \attention Compilers must be configured to avoid removing this variable in case
* it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure * the application program is not using it. Debugging systems require the variable
* the debugger. */ * to be physically present in memory so that it can be examined to configure the debugger. */
uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ /** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
@ -88,6 +80,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
#define CY_WDT_LOCK_BIT0 ((uint32_t)0x01u << 30u) #define CY_WDT_LOCK_BIT0 ((uint32_t)0x01u << 30u)
#define CY_WDT_LOCK_BIT1 ((uint32_t)0x01u << 31u) #define CY_WDT_LOCK_BIT1 ((uint32_t)0x01u << 31u)
#if (__CM0P_PRESENT == 0)
/* CLK_FLL_CONFIG default values */
#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
#endif /* (__CM0P_PRESENT == 0) */
/******************************************************************************* /*******************************************************************************
* SystemCoreClockUpdate (void) * SystemCoreClockUpdate (void)
@ -131,15 +131,32 @@ uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
/******************************************************************************* /*******************************************************************************
* Function Name: SystemInit * Function Name: SystemInit
****************************************************************************//** ****************************************************************************//**
* * \cond
* Initializes the system: * Initializes the system:
* - Restores FLL registers to the default state for single core devices.
* - Unlocks and disables WDT. * - Unlocks and disables WDT.
* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
* - Calls \ref SystemCoreClockUpdate(). * - Calls \ref SystemCoreClockUpdate().
* * \endcond
*******************************************************************************/ *******************************************************************************/
void SystemInit(void) void SystemInit(void)
{ {
#if (__CM0P_PRESENT == 0)
/* Restore FLL registers to the default state as they are not restored by the ROM code */
uint32_t copy = SRSS->CLK_FLL_CONFIG;
copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
SRSS->CLK_FLL_CONFIG = copy;
copy = SRSS->CLK_ROOT_SELECT[0u];
copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
SRSS->CLK_ROOT_SELECT[0u] = copy;
SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
#endif /* (__CM0P_PRESENT == 0) */
/* Unlock and disable WDT */ /* Unlock and disable WDT */
SRSS->WDT_CTL = ((SRSS->WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_WDT_LOCK_BIT0); SRSS->WDT_CTL = ((SRSS->WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_WDT_LOCK_BIT0);
SRSS->WDT_CTL = (SRSS->WDT_CTL | CY_WDT_LOCK_BIT1); SRSS->WDT_CTL = (SRSS->WDT_CTL | CY_WDT_LOCK_BIT1);
@ -147,12 +164,29 @@ void SystemInit(void)
Cy_SystemInit(); Cy_SystemInit();
SystemCoreClockUpdate(); SystemCoreClockUpdate();
}
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/*******************************************************************************
* Function Name: mbed_sdk_init
****************************************************************************//**
*
* Mbed's post-memory-initialization function.
* Used here to initialize common parts of the Cypress libraries.
*
*******************************************************************************/
void mbed_sdk_init(void)
{
/* Initialize shared resource manager */
cy_srm_initialize();
/* Initialize system and clocks. */
/* Placed here as it must be done after proper LIBC initialization. */
SystemInit();
/* Allocate and initialize semaphores for the system operations. */ /* Allocate and initialize semaphores for the system operations. */
Cy_IPC_SystemSemaInit(); Cy_IPC_SystemSemaInit();
Cy_IPC_SystemPipeInit(); Cy_IPC_SystemPipeInit();
#endif /* CY_IPC_DEFAULT_CFG_DISABLE */ Cy_Flash_Init();
ipcrpc_init();
} }
@ -368,7 +402,7 @@ void Cy_SystemInitFpuEnable(void)
* *
* The intention of the function is to declare boundaries of the memories for the * The intention of the function is to declare boundaries of the memories for the
* MDK compilers. For the rest of the supported compilers, this is done using * MDK compilers. For the rest of the supported compilers, this is done using
* linker configuration files. The following symbols used by the cypdlelftool. * linker configuration files. The following symbols used by the cymcuelftool.
* *
*******************************************************************************/ *******************************************************************************/
#if defined (__ARMCC_VERSION) #if defined (__ARMCC_VERSION)
@ -404,9 +438,9 @@ __cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) __cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
__cy_memory_0_row_size EQU 0x200 __cy_memory_0_row_size EQU 0x200
/* Working Flash */ /* Flash region for EEPROM emulation */
__cy_memory_1_start EQU __cpp(CY_WFLASH_BASE) __cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
__cy_memory_1_length EQU __cpp(CY_WFLASH_SIZE) __cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
__cy_memory_1_row_size EQU 0x200 __cy_memory_1_row_size EQU 0x200
/* Supervisory Flash */ /* Supervisory Flash */

81
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device.h Normal file
View File

@ -0,0 +1,81 @@
/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
/*----------------------------------------------------------------------------*/
/** Config options. */
/*----------------------------------------------------------------------------*/
/** ALTHF (BLE ECO) frequency in Hz */
#define CYDEV_CLK_ALTHF__HZ ( 8000000UL)
/*----------------------------------------------------------------------------*/
#include "cmsis.h"
#include "objects.h"
/*
* Board clocks.
*/
/** IMO frequency in Hz */
#define CY_CLK_IMO_FREQ_HZ ( 8000000UL)
/** PILO frequency in Hz */
#define CY_CLK_PILO_FREQ_HZ ( 32768UL)
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ ( 32768UL)
/** HVILO frequency in Hz */
#define CY_CLK_HVILO_FREQ_HZ ( 32000UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ ( 32768UL)
/** Default HFClk frequency in Hz */
#ifndef CY_CLK_HFCLK0_FREQ_HZ
#define CY_CLK_HFCLK0_FREQ_HZ (100000000UL)
#endif
/** Default PeriClk frequency in Hz */
#ifndef CY_CLK_PERICLK_FREQ_HZ
#define CY_CLK_PERICLK_FREQ_HZ (CY_CLK_HFCLK0_FREQ_HZ / 2)
#endif
/** Default SlowClk system core frequency in Hz */
#ifndef CY_CLK_SYSTEM_FREQ_HZ
#define CY_CLK_SYSTEM_FREQ_HZ (CY_CLK_PERICLK_FREQ_HZ)
#endif
/** Interrupt assignment for CM0+ core.
* On PSoC6 CM0+ core physical interrupt are routed into NVIC through a programmable
* multiplexer. This requires that we define which of the 32 NVIC channels is used
* by which interrupt. This is done here.
*/
#define CY_M0_CORE_IRQ_CHANNEL_US_TICKER ((IRQn_Type)0)
#define CY_M0_CORE_IRQ_CHANNEL_SERIAL ((IRQn_Type)4)
#define CY_M0_CORE_IRQ_CHANNEL_BLE ((IRQn_Type)3)
/** Identifiers used in allocation of NVIC channels.
*/
#define CY_US_TICKER_IRQN_ID (0x100)
#define CY_SERIAL_IRQN_ID (0x200)
#define CY_BLE_IRQN_ID (0x300)
#define CY_GPIO_IRQN_ID (0x400)
#define CY_LP_TICKER_IRQN_ID (0x500)
#endif

1
targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/cmsis.h → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cmsis.h
View File

@ -33,5 +33,6 @@
#define MBED_CMSIS_H #define MBED_CMSIS_H
#include "cy_device_headers.h" #include "cy_device_headers.h"
#undef BLE
#endif #endif

37
targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/cy8c6347bzi_bld53.h → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy8c6347bzi_bld53.h
View File

@ -5,12 +5,12 @@
* CY8C6347BZI-BLD53 device header * CY8C6347BZI-BLD53 device header
* *
* \note * \note
* Generated 9/21/2017 by CyDeviceHeaderGenerator v1.2.0.101 * Generator version: 1.2.0.117
* from the register map configuration rev#1007711 * Database revision: rev#1034984
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -433,6 +433,7 @@ typedef enum {
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __MPU_PRESENT 1 /*!< MPU present or not */ #define __MPU_PRESENT 1 /*!< MPU present or not */
#define __FPU_PRESENT 1 /*!< FPU present or not */ #define __FPU_PRESENT 1 /*!< FPU present or not */
#define __CM0P_PRESENT 1 /*!< CM0P present or not */
/** \} Configuration_of_CMSIS */ /** \} Configuration_of_CMSIS */
@ -451,8 +452,8 @@ typedef enum {
#define CY_SRAM0_SIZE 0x00048000UL #define CY_SRAM0_SIZE 0x00048000UL
#define CY_FLASH_BASE 0x10000000UL #define CY_FLASH_BASE 0x10000000UL
#define CY_FLASH_SIZE 0x00100000UL #define CY_FLASH_SIZE 0x00100000UL
#define CY_WFLASH_BASE 0x14000000UL #define CY_EM_EEPROM_BASE 0x14000000UL
#define CY_WFLASH_SIZE 0x00008000UL #define CY_EM_EEPROM_SIZE 0x00008000UL
#define CY_XIP_BASE 0x18000000UL #define CY_XIP_BASE 0x18000000UL
#define CY_XIP_SIZE 0x08000000UL #define CY_XIP_SIZE 0x08000000UL
#define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_BASE 0x16000000UL
@ -460,27 +461,18 @@ typedef enum {
#define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_BASE 0x402C0800UL
#define CY_EFUSE_SIZE 0x000000C8UL #define CY_EFUSE_SIZE 0x000000C8UL
#define CY_DEVICE_PSOC6ABLE2
#define CY_SILICON_ID 0xE2072100UL #define CY_SILICON_ID 0xE2072100UL
#define CY_HF_CLK_MAX_FREQ 150000000UL #define CY_HF_CLK_MAX_FREQ 150000000UL
/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL
CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
256 B are used. This is because the EZ mode uses 8-bit addresses. */
#define SCB_GET_EZ_DATA_NR(base) 256u #define SCB_GET_EZ_DATA_NR(base) 256u
/* I2C slave support? ('0': no, '1': yes) */
#define SCB_IS_I2C_SLAVE_CAPABLE(base) true #define SCB_IS_I2C_SLAVE_CAPABLE(base) true
/* I2C master support? ('0': no, '1': yes) */
#define SCB_IS_I2C_MASTER_CAPABLE(base) ((base) != SCB8) #define SCB_IS_I2C_MASTER_CAPABLE(base) ((base) != SCB8)
/* DeepSleep support ('0':no, '1': yes) */
#define SCB_IS_I2C_DS_CAPABLE(base) ((base) == SCB8) #define SCB_IS_I2C_DS_CAPABLE(base) ((base) == SCB8)
/* SPI slave support? ('0': no, '1': yes) */
#define SCB_IS_SPI_SLAVE_CAPABLE(base) true #define SCB_IS_SPI_SLAVE_CAPABLE(base) true
/* SPI master support? ('0': no, '1': yes) */
#define SCB_IS_SPI_MASTER_CAPABLE(base) ((base) != SCB8) #define SCB_IS_SPI_MASTER_CAPABLE(base) ((base) != SCB8)
/* DeepSleep support ('0':no, '1': yes) */
#define SCB_IS_SPI_DS_CAPABLE(base) ((base) == SCB8) #define SCB_IS_SPI_DS_CAPABLE(base) ((base) == SCB8)
/* UART support? ('0': no, '1': yes) */
#define SCB_IS_UART_CAPABLE(base) ((base) != SCB8) #define SCB_IS_UART_CAPABLE(base) ((base) != SCB8)
/* IP List */ /* IP List */
@ -570,6 +562,7 @@ typedef enum {
#include "cyip_backup.h" #include "cyip_backup.h"
#include "cyip_dw.h" #include "cyip_dw.h"
#include "cyip_efuse.h" #include "cyip_efuse.h"
#include "cyip_efuse_data.h"
#include "cyip_profile.h" #include "cyip_profile.h"
#include "cyip_hsiom.h" #include "cyip_hsiom.h"
#include "cyip_gpio.h" #include "cyip_gpio.h"
@ -1267,15 +1260,19 @@ typedef enum {
* I2S * I2S
*******************************************************************************/ *******************************************************************************/
#define I2S_BASE 0x42A10000UL #define I2S0_BASE 0x42A10000UL
#define I2S ((I2S_Type*) I2S_BASE) /* 0x42A10000 */ #define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */
/******************************************************************************* /*******************************************************************************
* PDM * PDM
*******************************************************************************/ *******************************************************************************/
#define PDM_BASE 0x42A20000UL #define PDM0_BASE 0x42A20000UL
#define PDM ((PDM_Type*) PDM_BASE) /* 0x42A20000 */ #define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */
/* Backward compabitility definitions */
#define I2S I2S0
#define PDM PDM0
/** \} CY8C6347BZI-BLD53 */ /** \} CY8C6347BZI-BLD53 */

16
targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/cy_device_headers.h → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_device_headers.h
View File

@ -5,12 +5,12 @@
* Common header file to be included by the drivers. * Common header file to be included by the drivers.
* *
* \note * \note
* Generated 9/21/2017 by CyDeviceHeaderGenerator v1.2.0.101 * Generator version: 1.2.0.117
* from the register map configuration rev#1007711 * Database revision: rev#1034984
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -51,6 +51,16 @@
#include "cy8c68237bz_ble.h" #include "cy8c68237bz_ble.h"
#elif defined (CY8C68237FM_BLE) #elif defined (CY8C68237FM_BLE)
#include "cy8c68237fm_ble.h" #include "cy8c68237fm_ble.h"
#elif defined (CY8C6336BZI_BUD13)
#include "cy8c6336bzi_bud13.h"
#elif defined (CY8C6347BZI_BUD43)
#include "cy8c6347bzi_bud43.h"
#elif defined (CY8C6347BZI_BUD33)
#include "cy8c6347bzi_bud33.h"
#elif defined (CY8C6347BZI_BUD53)
#include "cy8c6347bzi_bud53.h"
#elif defined (CY8C6337BZI_BLF13)
#include "cy8c6337bzi_blf13.h"
#else #else
#error Undefined part number #error Undefined part number
#endif #endif

135
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_config.c → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_ipc_config.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_ipc_config.c * \file cy_ipc_config.c
* \version 1.10 * \version 1.10.1
* *
* Description: * Description:
* This C file is not intended to be part of the IPC driver. It is the code * This C file is not intended to be part of the IPC driver. It is the code
@ -8,22 +8,18 @@
* and pipes. * and pipes.
* *
******************************************************************************** ********************************************************************************
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
*******************************************************************************/ *******************************************************************************/
#include "flash/cy_flash.h"
#include "ipc/cy_ipc_drv.h" #include "ipc/cy_ipc_drv.h"
#include "ipc/cy_ipc_pipe.h" #include "ipc/cy_ipc_pipe.h"
#include "ipc/cy_ipc_sema.h" #include "ipc/cy_ipc_sema.h"
#include "sysint/cy_sysint.h"
#include "cy_ipc_config.h" #include "cy_ipc_config.h"
static void Cy_Flash_NotifyHandler(uint32_t * msgPtr);
/* Create an array of endpoint structures */ /* Create an array of endpoint structures */
static cy_stc_ipc_pipe_ep_t cy_ipc_pipe_sysEpArray[CY_IPC_MAX_ENDPOINTS]; static cy_stc_ipc_pipe_ep_t cy_ipc_pipe_sysEpArray[CY_IPC_MAX_ENDPOINTS];
@ -48,11 +44,21 @@ static cy_stc_ipc_pipe_ep_t cy_ipc_pipe_sysEpArray[CY_IPC_MAX_ENDPOINTS];
/* .userPipeIsrHandler */ &Cy_IPC_SystemPipeIsr\ /* .userPipeIsrHandler */ &Cy_IPC_SystemPipeIsr\
} }
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_IPC_SystemSemaInit * Function Name: Cy_IPC_SystemSemaInit
****************************************************************************//** ****************************************************************************//**
* *
* Initializes the system semaphores. * Initializes the system semaphores. The system semaphores are used by Flash.
*
* This function is called in the SystemInit() function. If the default startup
* file is not used, or SystemInit() is not called in your project,
* call the following three functions prior to executing any flash or EmEEPROM
* write or erase operation:
* -# Cy_IPC_SystemSemaInit()
* -# Cy_IPC_SystemPipeInit()
* -# Cy_Flash_Init()
* *
*******************************************************************************/ *******************************************************************************/
void Cy_IPC_SystemSemaInit(void) void Cy_IPC_SystemSemaInit(void)
@ -66,13 +72,49 @@ void Cy_IPC_SystemSemaInit(void)
#endif #endif
} }
/*******************************************************************************
* Function Name: Cy_IPC_UserPipeIsr
****************************************************************************//**
*
* This is the interrupt service routine for the user pipe.
*
*******************************************************************************/
void Cy_IPC_UserPipeIsr(void)
{
Cy_IPC_Pipe_ExecCallback(&cy_ipc_pipe_sysEpArray[CY_IPC_EP_USRPIPE_ADDR]);
}
/*******************************************************************************
* Function Name: Cy_IPC_RpcPipeIsr
****************************************************************************//**
*
* This is the interrupt service routine for the RPC pipe.
*
*******************************************************************************/
void Cy_IPC_RpcPipeIsr(void)
{
Cy_IPC_Pipe_ExecCallback(&cy_ipc_pipe_sysEpArray[CY_IPC_EP_RPCPIPE_ADDR]);
}
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_IPC_SystemPipeInit * Function Name: Cy_IPC_SystemPipeInit
****************************************************************************//** ****************************************************************************//**
* *
* Initializes the system pipes. The system pipes are used by BLE. * Initializes the system pipes. The system pipes are used by BLE and Flash.
* \note The function should be called on all CPUs. * \note The function should be called on all CPUs.
* *
* This function is called in the SystemInit() function. If the default startup
* file is not used, or SystemInit() is not called in your project,
* call the following three functions prior to executing any flash or EmEEPROM
* write or erase operation:
* -# Cy_IPC_SystemSemaInit()
* -# Cy_IPC_SystemPipeInit()
* -# Cy_Flash_Init()
*
* Also this function is called to support BLE host/controller communication.
*
*******************************************************************************/ *******************************************************************************/
void Cy_IPC_SystemPipeInit(void) void Cy_IPC_SystemPipeInit(void)
{ {
@ -81,14 +123,54 @@ void Cy_IPC_SystemPipeInit(void)
intr = Cy_SysLib_EnterCriticalSection(); intr = Cy_SysLib_EnterCriticalSection();
static cy_ipc_pipe_callback_ptr_t cy_ipc_pipe_sysCbArray[CY_IPC_CYPIPE_CLIENT_CNT]; static cy_ipc_pipe_callback_ptr_t cy_ipc_pipe_sysCbArray[CY_IPC_CYPIPE_CLIENT_CNT];
static cy_ipc_pipe_callback_ptr_t cy_ipc_pipe_userCbArray[CY_IPC_USRPIPE_CLIENT_CNT];
static cy_ipc_pipe_callback_ptr_t cy_ipc_pipe_rpcCbArray[CY_IPC_RPCPIPE_CLIENT_CNT];
static const cy_stc_ipc_pipe_config_t systemPipeConfig = CY_CYPIPE_DEFAULT_CONFIG; static const cy_stc_ipc_pipe_config_t systemPipeConfig = CY_CYPIPE_DEFAULT_CONFIG;
static const cy_stc_ipc_pipe_config_t userPipeConfig = {
.ep0ConfigData = {
.ipcNotifierNumber = CY_IPC_INTR_USRPIPE_CM0,
.ipcNotifierPriority = CY_IPC_INTR_USRPIPE_PRIOR_EP0,
.ipcNotifierMuxNumber = CY_IPC_INTR_USRPIPE_MUX_EP0,
.epAddress = CY_IPC_EP_USRPIPE_CM0_ADDR,
.epConfig = CY_IPC_USRPIPE_CONFIG_EP0
},
.ep1ConfigData = {
.ipcNotifierNumber = CY_IPC_INTR_USRPIPE_CM4,
.ipcNotifierPriority = CY_IPC_INTR_USRPIPE_PRIOR_EP1,
.ipcNotifierMuxNumber = 0u,
.epAddress = CY_IPC_EP_USRPIPE_CM4_ADDR,
.epConfig = CY_IPC_USRPIPE_CONFIG_EP1
},
.endpointClientsCount = CY_IPC_USRPIPE_CLIENT_CNT,
.endpointsCallbacksArray = cy_ipc_pipe_userCbArray,
.userPipeIsrHandler = &Cy_IPC_UserPipeIsr
};
static const cy_stc_ipc_pipe_config_t rpcPipeConfig = {
.ep0ConfigData = {
.ipcNotifierNumber = CY_IPC_INTR_RPCPIPE_CM0,
.ipcNotifierPriority = CY_IPC_INTR_RPCPIPE_PRIOR_EP0,
.ipcNotifierMuxNumber = CY_IPC_INTR_RPCPIPE_MUX_EP0,
.epAddress = CY_IPC_EP_RPCPIPE_CM0_ADDR,
.epConfig = CY_IPC_RPCPIPE_CONFIG_EP0
},
.ep1ConfigData = {
.ipcNotifierNumber = CY_IPC_INTR_RPCPIPE_CM4,
.ipcNotifierPriority = CY_IPC_INTR_RPCPIPE_PRIOR_EP1,
.ipcNotifierMuxNumber = 0u,
.epAddress = CY_IPC_EP_RPCPIPE_CM4_ADDR,
.epConfig = CY_IPC_RPCPIPE_CONFIG_EP1
},
.endpointClientsCount = CY_IPC_RPCPIPE_CLIENT_CNT,
.endpointsCallbacksArray = cy_ipc_pipe_rpcCbArray,
.userPipeIsrHandler = &Cy_IPC_RpcPipeIsr
};
Cy_IPC_Pipe_Config(cy_ipc_pipe_sysEpArray); Cy_IPC_Pipe_Config(cy_ipc_pipe_sysEpArray);
Cy_IPC_Pipe_Init(&systemPipeConfig); Cy_IPC_Pipe_Init(&systemPipeConfig);
Cy_IPC_Pipe_Init(&userPipeConfig);
(void)Cy_IPC_Pipe_RegisterCallback(CY_IPC_EP_CYPIPE_ADDR, &Cy_Flash_NotifyHandler, (uint32_t)CY_FLASH_IPC_CLIENT_ID); Cy_IPC_Pipe_Init(&rpcPipeConfig);
Cy_SysLib_ExitCriticalSection(intr); Cy_SysLib_ExitCriticalSection(intr);
} }
@ -105,39 +187,6 @@ void Cy_IPC_SystemPipeIsr(void)
Cy_IPC_Pipe_ExecCallback(&cy_ipc_pipe_sysEpArray[CY_IPC_EP_CYPIPE_ADDR]); Cy_IPC_Pipe_ExecCallback(&cy_ipc_pipe_sysEpArray[CY_IPC_EP_CYPIPE_ADDR]);
} }
/*******************************************************************************
* Function Name: Cy_Flash_NotifyHandler
****************************************************************************//**
*
* This is the interrupt service routine for the pipe notifications.
*
*******************************************************************************/
#if defined (__ICCARM__)
__ramfunc
#else
CY_SECTION(".cy_ramfunc")
#endif
static void Cy_Flash_NotifyHandler(uint32_t * msgPtr)
{
uint32_t intr;
IPC_MSG *ipcMsgPtr = (IPC_MSG *)msgPtr;
if (CY_FLASH_ENTER_WAIT_LOOP == ipcMsgPtr->pktType)
{
intr = Cy_SysLib_EnterCriticalSection();
/* Notification to the Flash driver to start the current operation */
(void) Cy_IPC_Sema_Set(CY_FLASH_WAIT_SEMA, true);
/* Notification to me about the end of the operation */
while (CY_IPC_SEMA_STATUS_LOCKED == Cy_IPC_Sema_Status(CY_FLASH_WAIT_SEMA))
{
}
Cy_SysLib_ExitCriticalSection(intr);
}
}
/* [] END OF FILE */ /* [] END OF FILE */

100
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_config.h → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_ipc_config.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_ipc_config.h * \file cy_ipc_config.h
* \version 1.10 * \version 1.10.1
* *
* \brief * \brief
* This header file is not intended to be part of the IPC driver since it defines * This header file is not intended to be part of the IPC driver since it defines
@ -8,7 +8,7 @@
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -51,12 +51,6 @@
This will allow 128 (4*32) semaphores */ This will allow 128 (4*32) semaphores */
#define CY_IPC_SEMA_COUNT (uint32_t)(128u) #define CY_IPC_SEMA_COUNT (uint32_t)(128u)
/* System IPC Notify Masks */
#define CY_IPC_SEMA_NOTIFY_MASK (uint32_t)(0x0001ul << CY_IPC_CHAN_SEMA)
/* System IPC channel release Masks */
#define CY_IPC_SEM_RELEASE_MASK (uint32_t)(0x0001ul << CY_IPC_CHAN_SEMA)
/* IPC Pipe definitions */ /* IPC Pipe definitions */
#define CY_IPC_MAX_ENDPOINTS (uint32_t)(8u) #define CY_IPC_MAX_ENDPOINTS (uint32_t)(8u)
@ -65,6 +59,7 @@
*******************************************************************************/ *******************************************************************************/
#define CY_IPC_CYPIPE_CLIENT_CNT (uint32_t)(8u) #define CY_IPC_CYPIPE_CLIENT_CNT (uint32_t)(8u)
#define CY_IPC_USRPIPE_CLIENT_CNT (uint32_t)(8u) #define CY_IPC_USRPIPE_CLIENT_CNT (uint32_t)(8u)
#define CY_IPC_RPCPIPE_CLIENT_CNT (uint32_t)(16u)
#if (CY_CPU_CORTEX_M0P) #if (CY_CPU_CORTEX_M0P)
#define CY_IPC_EP_CYPIPE_ADDR CY_IPC_EP_CYPIPE_CM0_ADDR #define CY_IPC_EP_CYPIPE_ADDR CY_IPC_EP_CYPIPE_CM0_ADDR
@ -119,12 +114,101 @@
#define CY_IPC_EP_USRPIPE_ADDR_EP0 (uint32_t)(2u) #define CY_IPC_EP_USRPIPE_ADDR_EP0 (uint32_t)(2u)
#define CY_IPC_EP_USRPIPE_ADDR_EP1 (uint32_t)(3u) #define CY_IPC_EP_USRPIPE_ADDR_EP1 (uint32_t)(3u)
/* Endpoint indexes in the pipe array */
#define CY_IPC_EP_USRPIPE_CM0_ADDR (uint32_t)(2u)
#define CY_IPC_EP_USRPIPE_CM4_ADDR (uint32_t)(3u)
#if (CY_CPU_CORTEX_M0P)
#define CY_IPC_EP_USRPIPE_ADDR CY_IPC_EP_USRPIPE_CM0_ADDR
#define CY_IPC_EP_USRPIPE_DEST CY_IPC_EP_USRPIPE_CM4_ADDR
#else
#define CY_IPC_EP_USRPIPE_ADDR CY_IPC_EP_USRPIPE_CM4_ADDR
#define CY_IPC_EP_USRPIPE_DEST CY_IPC_EP_USRPIPE_CM0_ADDR
#endif /* (CY_CPU_CORTEX_M0P) */
#define CY_IPC_INTR_USRPIPE_MUX_EP0 (uint32_t)(2u)
#define CY_IPC_INTR_USRPIPE_EP0 CY_IPC_INTR_USRPIPE_CM0
#define CY_IPC_INTR_USRPIPE_PRIOR_EP0 (uint32_t)(1u) /* Notifier Priority */
#define CY_IPC_INTR_USRPIPE_EP1 CY_IPC_INTR_USRPIPE_CM4
#define CY_IPC_INTR_USRPIPE_PRIOR_EP1 (uint32_t)(1u) /* Notifier Priority */
#define CY_IPC_USRPIPE_CHAN_MASK_EP0 (uint32_t)(0x0001ul << CY_IPC_CHAN_USRPIPE_CM0)
#define CY_IPC_USRPIPE_CHAN_MASK_EP1 (uint32_t)(0x0001ul << CY_IPC_CHAN_USRPIPE_CM4)
#define CY_IPC_USRPIPE_CONFIG_EP0 (uint32_t)( (CY_IPC_USRPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_USRPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_USRPIPE_CM0)
#define CY_IPC_USRPIPE_CONFIG_EP1 (uint32_t)( (CY_IPC_USRPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_USRPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_USRPIPE_CM4)
#define CY_IPC_USRPIPE_INTR_MASK (uint32_t)( CY_IPC_USRPIPE_CHAN_MASK_EP0 | CY_IPC_USRPIPE_CHAN_MASK_EP1 )
/******************************************************************************/
#define CY_IPC_CHAN_RPCPIPE_CM0 (uint32_t)(10u)
#define CY_IPC_CHAN_RPCPIPE_CM4 (uint32_t)(11u)
#define CY_IPC_INTR_RPCPIPE_CM0 (uint32_t)(10u)
#define CY_IPC_INTR_RPCPIPE_CM4 (uint32_t)(11u)
#define CY_IPC_EP_RPCPIPE_ADDR_EP0 (uint32_t)(4u)
#define CY_IPC_EP_RPCPIPE_ADDR_EP1 (uint32_t)(5u)
/* Endpoint indexes in the pipe array */
#define CY_IPC_EP_RPCPIPE_CM0_ADDR (uint32_t)(4u)
#define CY_IPC_EP_RPCPIPE_CM4_ADDR (uint32_t)(5u)
#if (CY_CPU_CORTEX_M0P)
#define CY_IPC_EP_RPCPIPE_ADDR CY_IPC_EP_RPCPIPE_CM0_ADDR
#define CY_IPC_EP_RPCPIPE_DEST CY_IPC_EP_RPCPIPE_CM4_ADDR
#else
#define CY_IPC_EP_RPCPIPE_ADDR CY_IPC_EP_RPCPIPE_CM4_ADDR
#define CY_IPC_EP_RPCPIPE_DEST CY_IPC_EP_RPCPIPE_CM0_ADDR
#endif /* (CY_CPU_CORTEX_M0P) */
#define CY_IPC_INTR_RPCPIPE_MUX_EP0 (uint32_t)(4u)
#define CY_IPC_INTR_RPCPIPE_EP0 CY_IPC_INTR_RPCPIPE_CM0
#define CY_IPC_INTR_RPCPIPE_PRIOR_EP0 (uint32_t)(1u) /* Notifier Priority */
#define CY_IPC_INTR_RPCPIPE_EP1 CY_IPC_INTR_RPCPIPE_CM4
#define CY_IPC_INTR_RPCPIPE_PRIOR_EP1 (uint32_t)(1u) /* Notifier Priority */
#define CY_IPC_RPCPIPE_CHAN_MASK_EP0 (uint32_t)(0x0001ul << CY_IPC_CHAN_RPCPIPE_CM0)
#define CY_IPC_RPCPIPE_CHAN_MASK_EP1 (uint32_t)(0x0001ul << CY_IPC_CHAN_RPCPIPE_CM4)
#define CY_IPC_RPCPIPE_CONFIG_EP0 (uint32_t)( (CY_IPC_RPCPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_RPCPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_RPCPIPE_CM0)
#define CY_IPC_RPCPIPE_CONFIG_EP1 (uint32_t)( (CY_IPC_RPCPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_RPCPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_RPCPIPE_CM4)
#define CY_IPC_RPCPIPE_INTR_MASK (uint32_t)( CY_IPC_RPCPIPE_CHAN_MASK_EP0 | CY_IPC_RPCPIPE_CHAN_MASK_EP1 )
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/*
* \addtogroup group_ipc_configuration_sema
* \{
*/
void Cy_IPC_SystemSemaInit(void); void Cy_IPC_SystemSemaInit(void);
/* \} group_ipc_configuration_sema */
/*
* \addtogroup group_ipc_configuration_cypipe
* \{
*/
void Cy_IPC_SystemPipeInit(void); void Cy_IPC_SystemPipeInit(void);
/* \} group_ipc_configuration_cypipe */
void Cy_IPC_SystemPipeIsr(void); void Cy_IPC_SystemPipeIsr(void);
#ifdef __cplusplus #ifdef __cplusplus

58
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cymetadata.c Normal file
View File

@ -0,0 +1,58 @@
/*******************************************************************************
* File Name: cymetadata.c
*
* PSoC Creator 4.1
*
* Description:
* This file defines all extra memory spaces that need to be included.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#include "stdint.h"
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
#ifndef CY_META_SECTION
#define CY_META_SECTION __attribute__ ((__section__(".cymeta"), used))
#endif
CY_META_SECTION
#elif defined(__ICCARM__)
#pragma location=".cymeta"
#else
#error "Unsupported toolchain"
#endif
const uint8_t cy_metadata[] = {
#if defined(CY8C637BZI_BLD74)
0x00u, 0x05u, 0xE2u, 0x01u, 0x11u, 0x00u, 0x00u, 0x01u,
0x00u, 0x00u, 0x00u, 0x00u
#elif defined(CY8C6347BZI_BLD53)
0x00u, 0x05u, 0xE2u, 0x07u, 0x21u, 0x00u, 0x21u, 0x01u,
0x00u, 0x00u, 0x00u, 0x00u
#else
#error "Unknown target device"
#endif
};
#if defined(CY8C637BZI_BLD74)
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
#ifndef CY_CHIP_PROT_SECTION
#define CY_CHIP_PROT_SECTION __attribute__ ((__section__(".cychipprotect"), used))
#endif
CY_CHIP_PROT_SECTION
#elif defined(__ICCARM__)
#pragma location=".cychipprotect"
#else
#error "Unsupported toolchain"
#endif
const uint8_t cy_meta_chipprotect[] = {
0x01u
};
#endif

84
targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/gpio_psoc63_116_bga_ble.h → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/gpio_psoc63_116_bga_ble.h
View File

@ -5,12 +5,12 @@
* PSoC 63 device GPIO header for 116-BGA-BLE package * PSoC 63 device GPIO header for 116-BGA-BLE package
* *
* \note * \note
* Generated 9/21/2017 by CyDeviceHeaderGenerator v1.2.0.101 * Generator version: 1.2.0.117
* from the register map configuration rev#1007711 * Database revision: rev#1034984
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -34,180 +34,258 @@ enum
/* Port List */ /* Port List */
/* PORT 0 (GPIO) */ /* PORT 0 (GPIO) */
#define P0_0_PORT GPIO_PRT0 #define P0_0_PORT GPIO_PRT0
#define P0_0_PIN 0u
#define P0_0_NUM 0u #define P0_0_NUM 0u
#define P0_1_PORT GPIO_PRT0 #define P0_1_PORT GPIO_PRT0
#define P0_1_PIN 1u
#define P0_1_NUM 1u #define P0_1_NUM 1u
#define P0_2_PORT GPIO_PRT0 #define P0_2_PORT GPIO_PRT0
#define P0_2_PIN 2u
#define P0_2_NUM 2u #define P0_2_NUM 2u
#define P0_3_PORT GPIO_PRT0 #define P0_3_PORT GPIO_PRT0
#define P0_3_PIN 3u
#define P0_3_NUM 3u #define P0_3_NUM 3u
#define P0_4_PORT GPIO_PRT0 #define P0_4_PORT GPIO_PRT0
#define P0_4_PIN 4u
#define P0_4_NUM 4u #define P0_4_NUM 4u
#define P0_5_PORT GPIO_PRT0 #define P0_5_PORT GPIO_PRT0
#define P0_5_PIN 5u
#define P0_5_NUM 5u #define P0_5_NUM 5u
/* PORT 1 (GPIO_OVT) */ /* PORT 1 (GPIO_OVT) */
#define P1_0_PORT GPIO_PRT1 #define P1_0_PORT GPIO_PRT1
#define P1_0_PIN 0u
#define P1_0_NUM 0u #define P1_0_NUM 0u
#define P1_1_PORT GPIO_PRT1 #define P1_1_PORT GPIO_PRT1
#define P1_1_PIN 1u
#define P1_1_NUM 1u #define P1_1_NUM 1u
#define P1_2_PORT GPIO_PRT1 #define P1_2_PORT GPIO_PRT1
#define P1_2_PIN 2u
#define P1_2_NUM 2u #define P1_2_NUM 2u
#define P1_3_PORT GPIO_PRT1 #define P1_3_PORT GPIO_PRT1
#define P1_3_PIN 3u
#define P1_3_NUM 3u #define P1_3_NUM 3u
#define P1_4_PORT GPIO_PRT1 #define P1_4_PORT GPIO_PRT1
#define P1_4_PIN 4u
#define P1_4_NUM 4u #define P1_4_NUM 4u
#define P1_5_PORT GPIO_PRT1 #define P1_5_PORT GPIO_PRT1
#define P1_5_PIN 5u
#define P1_5_NUM 5u #define P1_5_NUM 5u
/* PORT 5 (GPIO) */ /* PORT 5 (GPIO) */
#define P5_0_PORT GPIO_PRT5 #define P5_0_PORT GPIO_PRT5
#define P5_0_PIN 0u
#define P5_0_NUM 0u #define P5_0_NUM 0u
#define P5_1_PORT GPIO_PRT5 #define P5_1_PORT GPIO_PRT5
#define P5_1_PIN 1u
#define P5_1_NUM 1u #define P5_1_NUM 1u
#define P5_2_PORT GPIO_PRT5 #define P5_2_PORT GPIO_PRT5
#define P5_2_PIN 2u
#define P5_2_NUM 2u #define P5_2_NUM 2u
#define P5_3_PORT GPIO_PRT5 #define P5_3_PORT GPIO_PRT5
#define P5_3_PIN 3u
#define P5_3_NUM 3u #define P5_3_NUM 3u
#define P5_4_PORT GPIO_PRT5 #define P5_4_PORT GPIO_PRT5
#define P5_4_PIN 4u
#define P5_4_NUM 4u #define P5_4_NUM 4u
#define P5_5_PORT GPIO_PRT5 #define P5_5_PORT GPIO_PRT5
#define P5_5_PIN 5u
#define P5_5_NUM 5u #define P5_5_NUM 5u
#define P5_6_PORT GPIO_PRT5 #define P5_6_PORT GPIO_PRT5
#define P5_6_PIN 6u
#define P5_6_NUM 6u #define P5_6_NUM 6u
/* PORT 6 (GPIO) */ /* PORT 6 (GPIO) */
#define P6_0_PORT GPIO_PRT6 #define P6_0_PORT GPIO_PRT6
#define P6_0_PIN 0u
#define P6_0_NUM 0u #define P6_0_NUM 0u
#define P6_1_PORT GPIO_PRT6 #define P6_1_PORT GPIO_PRT6
#define P6_1_PIN 1u
#define P6_1_NUM 1u #define P6_1_NUM 1u
#define P6_2_PORT GPIO_PRT6 #define P6_2_PORT GPIO_PRT6
#define P6_2_PIN 2u
#define P6_2_NUM 2u #define P6_2_NUM 2u
#define P6_3_PORT GPIO_PRT6 #define P6_3_PORT GPIO_PRT6
#define P6_3_PIN 3u
#define P6_3_NUM 3u #define P6_3_NUM 3u
#define P6_4_PORT GPIO_PRT6 #define P6_4_PORT GPIO_PRT6
#define P6_4_PIN 4u
#define P6_4_NUM 4u #define P6_4_NUM 4u
#define P6_5_PORT GPIO_PRT6 #define P6_5_PORT GPIO_PRT6
#define P6_5_PIN 5u
#define P6_5_NUM 5u #define P6_5_NUM 5u
#define P6_6_PORT GPIO_PRT6 #define P6_6_PORT GPIO_PRT6
#define P6_6_PIN 6u
#define P6_6_NUM 6u #define P6_6_NUM 6u
#define P6_7_PORT GPIO_PRT6 #define P6_7_PORT GPIO_PRT6
#define P6_7_PIN 7u
#define P6_7_NUM 7u #define P6_7_NUM 7u
/* PORT 7 (GPIO) */ /* PORT 7 (GPIO) */
#define P7_0_PORT GPIO_PRT7 #define P7_0_PORT GPIO_PRT7
#define P7_0_PIN 0u
#define P7_0_NUM 0u #define P7_0_NUM 0u
#define P7_1_PORT GPIO_PRT7 #define P7_1_PORT GPIO_PRT7
#define P7_1_PIN 1u
#define P7_1_NUM 1u #define P7_1_NUM 1u
#define P7_2_PORT GPIO_PRT7 #define P7_2_PORT GPIO_PRT7
#define P7_2_PIN 2u
#define P7_2_NUM 2u #define P7_2_NUM 2u
#define P7_3_PORT GPIO_PRT7 #define P7_3_PORT GPIO_PRT7
#define P7_3_PIN 3u
#define P7_3_NUM 3u #define P7_3_NUM 3u
#define P7_4_PORT GPIO_PRT7 #define P7_4_PORT GPIO_PRT7
#define P7_4_PIN 4u
#define P7_4_NUM 4u #define P7_4_NUM 4u
#define P7_5_PORT GPIO_PRT7 #define P7_5_PORT GPIO_PRT7
#define P7_5_PIN 5u
#define P7_5_NUM 5u #define P7_5_NUM 5u
#define P7_6_PORT GPIO_PRT7 #define P7_6_PORT GPIO_PRT7
#define P7_6_PIN 6u
#define P7_6_NUM 6u #define P7_6_NUM 6u
#define P7_7_PORT GPIO_PRT7 #define P7_7_PORT GPIO_PRT7
#define P7_7_PIN 7u
#define P7_7_NUM 7u #define P7_7_NUM 7u
/* PORT 8 (GPIO) */ /* PORT 8 (GPIO) */
#define P8_0_PORT GPIO_PRT8 #define P8_0_PORT GPIO_PRT8
#define P8_0_PIN 0u
#define P8_0_NUM 0u #define P8_0_NUM 0u
#define P8_1_PORT GPIO_PRT8 #define P8_1_PORT GPIO_PRT8
#define P8_1_PIN 1u
#define P8_1_NUM 1u #define P8_1_NUM 1u
#define P8_2_PORT GPIO_PRT8 #define P8_2_PORT GPIO_PRT8
#define P8_2_PIN 2u
#define P8_2_NUM 2u #define P8_2_NUM 2u
#define P8_3_PORT GPIO_PRT8 #define P8_3_PORT GPIO_PRT8
#define P8_3_PIN 3u
#define P8_3_NUM 3u #define P8_3_NUM 3u
#define P8_4_PORT GPIO_PRT8 #define P8_4_PORT GPIO_PRT8
#define P8_4_PIN 4u
#define P8_4_NUM 4u #define P8_4_NUM 4u
#define P8_5_PORT GPIO_PRT8 #define P8_5_PORT GPIO_PRT8
#define P8_5_PIN 5u
#define P8_5_NUM 5u #define P8_5_NUM 5u
#define P8_6_PORT GPIO_PRT8 #define P8_6_PORT GPIO_PRT8
#define P8_6_PIN 6u
#define P8_6_NUM 6u #define P8_6_NUM 6u
#define P8_7_PORT GPIO_PRT8 #define P8_7_PORT GPIO_PRT8
#define P8_7_PIN 7u
#define P8_7_NUM 7u #define P8_7_NUM 7u
/* PORT 9 (GPIO) */ /* PORT 9 (GPIO) */
#define P9_0_PORT GPIO_PRT9 #define P9_0_PORT GPIO_PRT9
#define P9_0_PIN 0u
#define P9_0_NUM 0u #define P9_0_NUM 0u
#define P9_1_PORT GPIO_PRT9 #define P9_1_PORT GPIO_PRT9
#define P9_1_PIN 1u
#define P9_1_NUM 1u #define P9_1_NUM 1u
#define P9_2_PORT GPIO_PRT9 #define P9_2_PORT GPIO_PRT9
#define P9_2_PIN 2u
#define P9_2_NUM 2u #define P9_2_NUM 2u
#define P9_3_PORT GPIO_PRT9 #define P9_3_PORT GPIO_PRT9
#define P9_3_PIN 3u
#define P9_3_NUM 3u #define P9_3_NUM 3u
#define P9_4_PORT GPIO_PRT9 #define P9_4_PORT GPIO_PRT9
#define P9_4_PIN 4u
#define P9_4_NUM 4u #define P9_4_NUM 4u
#define P9_5_PORT GPIO_PRT9 #define P9_5_PORT GPIO_PRT9
#define P9_5_PIN 5u
#define P9_5_NUM 5u #define P9_5_NUM 5u
#define P9_6_PORT GPIO_PRT9 #define P9_6_PORT GPIO_PRT9
#define P9_6_PIN 6u
#define P9_6_NUM 6u #define P9_6_NUM 6u
#define P9_7_PORT GPIO_PRT9 #define P9_7_PORT GPIO_PRT9
#define P9_7_PIN 7u
#define P9_7_NUM 7u #define P9_7_NUM 7u
/* PORT 10 (GPIO) */ /* PORT 10 (GPIO) */
#define P10_0_PORT GPIO_PRT10 #define P10_0_PORT GPIO_PRT10
#define P10_0_PIN 0u
#define P10_0_NUM 0u #define P10_0_NUM 0u
#define P10_1_PORT GPIO_PRT10 #define P10_1_PORT GPIO_PRT10
#define P10_1_PIN 1u
#define P10_1_NUM 1u #define P10_1_NUM 1u
#define P10_2_PORT GPIO_PRT10 #define P10_2_PORT GPIO_PRT10
#define P10_2_PIN 2u
#define P10_2_NUM 2u #define P10_2_NUM 2u
#define P10_3_PORT GPIO_PRT10 #define P10_3_PORT GPIO_PRT10
#define P10_3_PIN 3u
#define P10_3_NUM 3u #define P10_3_NUM 3u
#define P10_4_PORT GPIO_PRT10 #define P10_4_PORT GPIO_PRT10
#define P10_4_PIN 4u
#define P10_4_NUM 4u #define P10_4_NUM 4u
#define P10_5_PORT GPIO_PRT10 #define P10_5_PORT GPIO_PRT10
#define P10_5_PIN 5u
#define P10_5_NUM 5u #define P10_5_NUM 5u
#define P10_6_PORT GPIO_PRT10 #define P10_6_PORT GPIO_PRT10
#define P10_6_PIN 6u
#define P10_6_NUM 6u #define P10_6_NUM 6u
/* PORT 11 (GPIO) */ /* PORT 11 (GPIO) */
#define P11_0_PORT GPIO_PRT11 #define P11_0_PORT GPIO_PRT11
#define P11_0_PIN 0u
#define P11_0_NUM 0u #define P11_0_NUM 0u
#define P11_1_PORT GPIO_PRT11 #define P11_1_PORT GPIO_PRT11
#define P11_1_PIN 1u
#define P11_1_NUM 1u #define P11_1_NUM 1u
#define P11_2_PORT GPIO_PRT11 #define P11_2_PORT GPIO_PRT11
#define P11_2_PIN 2u
#define P11_2_NUM 2u #define P11_2_NUM 2u
#define P11_3_PORT GPIO_PRT11 #define P11_3_PORT GPIO_PRT11
#define P11_3_PIN 3u
#define P11_3_NUM 3u #define P11_3_NUM 3u
#define P11_4_PORT GPIO_PRT11 #define P11_4_PORT GPIO_PRT11
#define P11_4_PIN 4u
#define P11_4_NUM 4u #define P11_4_NUM 4u
#define P11_5_PORT GPIO_PRT11 #define P11_5_PORT GPIO_PRT11
#define P11_5_PIN 5u
#define P11_5_NUM 5u #define P11_5_NUM 5u
#define P11_6_PORT GPIO_PRT11 #define P11_6_PORT GPIO_PRT11
#define P11_6_PIN 6u
#define P11_6_NUM 6u #define P11_6_NUM 6u
#define P11_7_PORT GPIO_PRT11 #define P11_7_PORT GPIO_PRT11
#define P11_7_PIN 7u
#define P11_7_NUM 7u #define P11_7_NUM 7u
/* PORT 12 (GPIO) */ /* PORT 12 (GPIO) */
#define P12_0_PORT GPIO_PRT12 #define P12_0_PORT GPIO_PRT12
#define P12_0_PIN 0u
#define P12_0_NUM 0u #define P12_0_NUM 0u
#define P12_1_PORT GPIO_PRT12 #define P12_1_PORT GPIO_PRT12
#define P12_1_PIN 1u
#define P12_1_NUM 1u #define P12_1_NUM 1u
#define P12_2_PORT GPIO_PRT12 #define P12_2_PORT GPIO_PRT12
#define P12_2_PIN 2u
#define P12_2_NUM 2u #define P12_2_NUM 2u
#define P12_3_PORT GPIO_PRT12 #define P12_3_PORT GPIO_PRT12
#define P12_3_PIN 3u
#define P12_3_NUM 3u #define P12_3_NUM 3u
#define P12_4_PORT GPIO_PRT12 #define P12_4_PORT GPIO_PRT12
#define P12_4_PIN 4u
#define P12_4_NUM 4u #define P12_4_NUM 4u
#define P12_5_PORT GPIO_PRT12 #define P12_5_PORT GPIO_PRT12
#define P12_5_PIN 5u
#define P12_5_NUM 5u #define P12_5_NUM 5u
#define P12_6_PORT GPIO_PRT12 #define P12_6_PORT GPIO_PRT12
#define P12_6_PIN 6u
#define P12_6_NUM 6u #define P12_6_NUM 6u
#define P12_7_PORT GPIO_PRT12 #define P12_7_PORT GPIO_PRT12
#define P12_7_PIN 7u
#define P12_7_NUM 7u #define P12_7_NUM 7u
/* PORT 13 (GPIO) */ /* PORT 13 (GPIO) */
#define P13_0_PORT GPIO_PRT13 #define P13_0_PORT GPIO_PRT13
#define P13_0_PIN 0u
#define P13_0_NUM 0u #define P13_0_NUM 0u
#define P13_1_PORT GPIO_PRT13 #define P13_1_PORT GPIO_PRT13
#define P13_1_PIN 1u
#define P13_1_NUM 1u #define P13_1_NUM 1u
#define P13_6_PORT GPIO_PRT13 #define P13_6_PORT GPIO_PRT13
#define P13_6_PIN 6u
#define P13_6_NUM 6u #define P13_6_NUM 6u
#define P13_7_PORT GPIO_PRT13 #define P13_7_PORT GPIO_PRT13
#define P13_7_PIN 7u
#define P13_7_NUM 7u #define P13_7_NUM 7u
/* Analog Connections */ /* Analog Connections */

642
targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/psoc63_config.h → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/psoc63_config.h
View File

@ -5,12 +5,12 @@
* PSoC 63 device configuration header * PSoC 63 device configuration header
* *
* \note * \note
* Generated 9/21/2017 by CyDeviceHeaderGenerator v1.2.0.101 * Generator version: 1.2.0.117
* from the register map configuration rev#1007711 * Database revision: rev#1034984
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -1617,8 +1617,12 @@ typedef enum
#define SRSS_HARD_ECOMUX_PRESENT 1u #define SRSS_HARD_ECOMUX_PRESENT 1u
/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ /* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */
#define SRSS_HARD_ALTHFMUX_PRESENT 1u #define SRSS_HARD_ALTHFMUX_PRESENT 1u
/* Width of MCWDT Subcounters 0 and 1. Applies to all MCWDT. */ /* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT
#define SRSS_MCWDT_CTR_WIDTH 32u or SIMOBUCK_PRESENT. */
#define SRSS_BUCKCTL_PRESENT 1u
/* Low-current SISO buck core regulator is present. Only compatible with ULP
linear regulator system (ULPLINREG_PRESENT==1). */
#define SRSS_S40S_SISOBUCKLC_PRESENT 0u
/* Backup memory is present (only used when BACKUP_PRESENT==1) */ /* Backup memory is present (only used when BACKUP_PRESENT==1) */
#define SRSS_BACKUP_BMEM_PRESENT 0u #define SRSS_BACKUP_BMEM_PRESENT 0u
/* Number of Backup registers to include (each is 32b). Only used when /* Number of Backup registers to include (each is 32b). Only used when
@ -1628,18 +1632,6 @@ typedef enum
#define IOSS_HSIOM_AMUX_SPLIT_NR 9u #define IOSS_HSIOM_AMUX_SPLIT_NR 9u
/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ /* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */
#define IOSS_HSIOM_HSIOM_PORT_NR 15u #define IOSS_HSIOM_HSIOM_PORT_NR 15u
/* Number of PWR/GND MONITOR CELLs in the device */
#define IOSS_HSIOM_MONITOR_NR 0u
/* Number of PWR/GND MONITOR CELLs in range 0..31 */
#define IOSS_HSIOM_MONITOR_NR_0_31 0u
/* Number of PWR/GND MONITOR CELLs in range 32..63 */
#define IOSS_HSIOM_MONITOR_NR_32_63 0u
/* Number of PWR/GND MONITOR CELLs in range 64..95 */
#define IOSS_HSIOM_MONITOR_NR_64_95 0u
/* Number of PWR/GND MONITOR CELLs in range 96..127 */
#define IOSS_HSIOM_MONITOR_NR_96_127 0u
/* Indicates the presence of alternate JTAG interface */
#define IOSS_HSIOM_ALTJTAG_PRESENT 0u
/* Number of GPIO ports in range 0..31 */ /* Number of GPIO ports in range 0..31 */
#define IOSS_GPIO_GPIO_PORT_NR_0_31 15u #define IOSS_GPIO_GPIO_PORT_NR_0_31 15u
/* Number of GPIO ports in range 32..63 */ /* Number of GPIO ports in range 32..63 */
@ -1660,6 +1652,550 @@ typedef enum
#define PERI_MS_PPU_COMBINATORIAL 1u #define PERI_MS_PPU_COMBINATORIAL 1u
/* The number of programmable PPU structures for PERI (all peripherals) */ /* The number of programmable PPU structures for PERI (all peripherals) */
#define PERI_MS_PPU_PROG_STRUCT_NR 16u #define PERI_MS_PPU_PROG_STRUCT_NR 16u
/* Presence of a timeout functionality (1: Yes, 0:No) */
#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u
/* Presence of a timeout functionality (1: Yes, 0:No) */
#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u
/* Presence of a timeout functionality (1: Yes, 0:No) */
#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u
/* Presence of a timeout functionality (1: Yes, 0:No) */
#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 0u
/* Presence of a timeout functionality (1: Yes, 0:No) */
#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u
/* Presence of a timeout functionality (1: Yes, 0:No) */
#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u
/* Presence of a timeout functionality (1: Yes, 0:No) */
#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u
/* Presence of a timeout functionality (1: Yes, 0:No) */
#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u
/* Presence of a timeout functionality (1: Yes, 0:No) */
#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u
/* Presence of a timeout functionality (1: Yes, 0:No) */
#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u
/* Presence of a timeout functionality (1: Yes, 0:No) */
#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u
/* Presence of a timeout functionality (1: Yes, 0:No) */
#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u
/* Presence of a timeout functionality (1: Yes, 0:No) */
#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u
/* Presence of a timeout functionality (1: Yes, 0:No) */
#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u
/* Presence of a timeout functionality (1: Yes, 0:No) */
#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u
/* Presence of a timeout functionality (1: Yes, 0:No) */
#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u
/* Slave present (0:No, 1:Yes) */
#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u
/* Number of programmable clocks (outputs) */ /* Number of programmable clocks (outputs) */
#define PERI_CLOCK_NR 59u #define PERI_CLOCK_NR 59u
/* Number of 8.0 dividers */ /* Number of 8.0 dividers */
@ -2388,6 +2924,78 @@ typedef enum
/* PDM capable? (0=No,1=Yes) */ /* PDM capable? (0=No,1=Yes) */
#define AUDIOSS_PDM 1u #define AUDIOSS_PDM 1u
/* MMIO Targets Defines */
#define CY_MMIO_CRYPTO_GROUP_NR 1u
#define CY_MMIO_CRYPTO_SLAVE_NR 1u
#define CY_MMIO_CPUSS_GROUP_NR 2u
#define CY_MMIO_CPUSS_SLAVE_NR 1u
#define CY_MMIO_FAULT_GROUP_NR 2u
#define CY_MMIO_FAULT_SLAVE_NR 2u
#define CY_MMIO_IPC_GROUP_NR 2u
#define CY_MMIO_IPC_SLAVE_NR 3u
#define CY_MMIO_PROT_GROUP_NR 2u
#define CY_MMIO_PROT_SLAVE_NR 4u
#define CY_MMIO_FLASHC_GROUP_NR 2u
#define CY_MMIO_FLASHC_SLAVE_NR 5u
#define CY_MMIO_SRSS_GROUP_NR 2u
#define CY_MMIO_SRSS_SLAVE_NR 6u
#define CY_MMIO_BACKUP_GROUP_NR 2u
#define CY_MMIO_BACKUP_SLAVE_NR 7u
#define CY_MMIO_DW_GROUP_NR 2u
#define CY_MMIO_DW_SLAVE_NR 8u
#define CY_MMIO_EFUSE_GROUP_NR 2u
#define CY_MMIO_EFUSE_SLAVE_NR 12u
#define CY_MMIO_PROFILE_GROUP_NR 2u
#define CY_MMIO_PROFILE_SLAVE_NR 13u
#define CY_MMIO_HSIOM_GROUP_NR 3u
#define CY_MMIO_HSIOM_SLAVE_NR 1u
#define CY_MMIO_GPIO_GROUP_NR 3u
#define CY_MMIO_GPIO_SLAVE_NR 2u
#define CY_MMIO_SMARTIO_GROUP_NR 3u
#define CY_MMIO_SMARTIO_SLAVE_NR 3u
#define CY_MMIO_UDB_GROUP_NR 3u
#define CY_MMIO_UDB_SLAVE_NR 4u
#define CY_MMIO_LPCOMP_GROUP_NR 3u
#define CY_MMIO_LPCOMP_SLAVE_NR 5u
#define CY_MMIO_CSD0_GROUP_NR 3u
#define CY_MMIO_CSD0_SLAVE_NR 6u
#define CY_MMIO_TCPWM0_GROUP_NR 3u
#define CY_MMIO_TCPWM0_SLAVE_NR 8u
#define CY_MMIO_TCPWM1_GROUP_NR 3u
#define CY_MMIO_TCPWM1_SLAVE_NR 9u
#define CY_MMIO_LCD0_GROUP_NR 3u
#define CY_MMIO_LCD0_SLAVE_NR 10u
#define CY_MMIO_BLE_GROUP_NR 3u
#define CY_MMIO_BLE_SLAVE_NR 11u
#define CY_MMIO_USBFS0_GROUP_NR 3u
#define CY_MMIO_USBFS0_SLAVE_NR 12u
#define CY_MMIO_SMIF0_GROUP_NR 4u
#define CY_MMIO_SMIF0_SLAVE_NR 2u
#define CY_MMIO_SCB0_GROUP_NR 6u
#define CY_MMIO_SCB0_SLAVE_NR 1u
#define CY_MMIO_SCB1_GROUP_NR 6u
#define CY_MMIO_SCB1_SLAVE_NR 2u
#define CY_MMIO_SCB2_GROUP_NR 6u
#define CY_MMIO_SCB2_SLAVE_NR 3u
#define CY_MMIO_SCB3_GROUP_NR 6u
#define CY_MMIO_SCB3_SLAVE_NR 4u
#define CY_MMIO_SCB4_GROUP_NR 6u
#define CY_MMIO_SCB4_SLAVE_NR 5u
#define CY_MMIO_SCB5_GROUP_NR 6u
#define CY_MMIO_SCB5_SLAVE_NR 6u
#define CY_MMIO_SCB6_GROUP_NR 6u
#define CY_MMIO_SCB6_SLAVE_NR 7u
#define CY_MMIO_SCB7_GROUP_NR 6u
#define CY_MMIO_SCB7_SLAVE_NR 8u
#define CY_MMIO_SCB8_GROUP_NR 6u
#define CY_MMIO_SCB8_SLAVE_NR 9u
#define CY_MMIO_PASS_GROUP_NR 9u
#define CY_MMIO_PASS_SLAVE_NR 1u
#define CY_MMIO_I2S0_GROUP_NR 10u
#define CY_MMIO_I2S0_SLAVE_NR 1u
#define CY_MMIO_PDM0_GROUP_NR 10u
#define CY_MMIO_PDM0_SLAVE_NR 2u
#endif /* _PSOC63_CONFIG_H_ */ #endif /* _PSOC63_CONFIG_H_ */

244
targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/system_psoc63.h → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/system_psoc63.h
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file system_psoc63.h * \file system_psoc63.h
* \version 2.0 * \version 2.10
* *
* \brief Device system header file. * \brief Device system header file.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -24,9 +24,7 @@
* - See \ref group_system_config_device_initialization for the: * - See \ref group_system_config_device_initialization for the:
* * \ref group_system_config_dual_core_device_initialization * * \ref group_system_config_dual_core_device_initialization
* * \ref group_system_config_single_core_device_initialization * * \ref group_system_config_single_core_device_initialization
* - See \ref group_system_config_device_memory_definition for the: * - \ref group_system_config_device_memory_definition
* * \ref group_system_config_device_memory_dual_core_definition
* * \ref group_system_config_device_memory_single_core_definition
* - \ref group_system_config_heap_stack_config * - \ref group_system_config_heap_stack_config
* - \ref group_system_config_merge_apps * - \ref group_system_config_merge_apps
* - Default interrupt handlers definition * - Default interrupt handlers definition
@ -36,99 +34,126 @@
* \section group_system_config_configuration Configuration Considerations * \section group_system_config_configuration Configuration Considerations
* *
* \subsection group_system_config_device_memory_definition Device Memory Definition * \subsection group_system_config_device_memory_definition Device Memory Definition
* The physical flash and RAM memory is shared between the CPU cores. The flash * The flash and RAM allocation for each CPU is defined by the linker scripts.
* and RAM allocation for each * For dual-core devices, the physical flash and RAM memory is shared between the CPU cores.
* CPU is defined by the linker scripts. * 2 KB of RAM (allocated at the end of RAM) are reserved for system use.
* For Single-Core devices the system reserves additional 80 bytes of RAM.
* Using the reserved memory area for other purposes will lead to unexpected behavior.
* *
* \subsubsection group_system_config_device_memory_dual_core_definition Dual-Core Devices * \note The linker files provided with the PDL are generic and handle all common
* By default, the flash and RAM memory is equally divided between two cores. * use cases. Your project may not use every section defined in the linker files.
* This proportion can be changed by editing * In that case you may see warnings during the build process. To eliminate build
* the linker configuration files. * warnings in your project, you can simply comment out or remove the relevant
* code in the linker file.
* *
* <b>ARM GCC</b>\n * <b>ARM GCC</b>\n
* The flash and RAM sections for the CPU are defined in the linker files: * The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for * 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* example, 'cy8c6x7_cm0plus.ld' and 'cy8c6x7_cm4_dual.ld'. * 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.
* Note: if the start of the Cortex-M4 application image is changed, the value * \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the
* Cy_SysEnableCM4() function call. * Cy_SysEnableCM4() function call.
* *
* The flash and RAM sizes can be changed by editing the LENGTH value in the * Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs: * linker files for both CPUs:
* - 'xx_cm0plus.ld', where 'xx' is the device group: * - 'xx_cm0plus.ld', where 'xx' is the device group:
* * \code rom (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 \endcode * \code
* * \code ram_cm0p (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 \endcode * flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000
* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000
* \endcode
* - 'xx_cm4_dual.ld', where 'xx' is the device group: * - 'xx_cm4_dual.ld', where 'xx' is the device group:
* * \code rom (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 \endcode * \code
* * \code ram_cm4 (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00024000 \endcode * flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000
* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's
* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this * value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this
* by either: * by either:
* - Passing the following commands to the compiler:\n * - Passing the following commands to the compiler:\n
* * \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode * \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n
* * \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode * \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
* *
* <b>ARM MDK</b>\n * <b>ARM MDK</b>\n
* The flash and RAM sections for the CPU are defined in the linker files: * The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for * 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* example, 'cy8c6x7_cm0plus.scat' and 'cy8c6x7_cm4_dual.scat'. * 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'.
* Note: if the start of the Cortex-M4 application image is changed, the value * \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
* Cy_SysEnableCM4() function call. * Cy_SysEnableCM4() function call.
* *
* The flash and RAM sizes can be changed by editing the macros value in the * \note The linker files provided with the PDL are generic and handle all common
* use cases. Your project may not use every section defined in the linker files.
* In that case you may see the warnings during the build process:
* L6314W (no section matches pattern) and/or L6329W
* (pattern only matches removed unused sections). In your project, you can
* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
* the linker. You can also comment out or remove the relevant code in the linker
* file.
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs: * linker files for both CPUs:
* - 'xx_cm0plus.scat', where 'xx' is the device group: * - 'xx_cm0plus.scat', where 'xx' is the device group:
* * \code #define FLASH_START 0x10000000 \endcode * \code
* * \code #define FLASH_SIZE 0x00080000 \endcode * #define FLASH_START 0x10000000
* #define FLASH_SIZE 0x00080000
* #define RAM_START 0x08000000
* #define RAM_SIZE 0x00024000
* \endcode
* - 'xx_cm4_dual.scat', where 'xx' is the device group: * - 'xx_cm4_dual.scat', where 'xx' is the device group:
* * \code #define FLASH_START 0x10080000 \endcode * \code
* * \code #define FLASH_SIZE 0x00080000 \endcode * #define FLASH_START 0x10080000
* #define FLASH_SIZE 0x00080000
* #define RAM_START 0x08024000
* #define RAM_SIZE 0x00023800
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
* value in the 'xx_cm4_dual.scat' file, * value in the 'xx_cm4_dual.scat' file,
* where 'xx' is the device group. Do this by either: * where 'xx' is the device group. Do this by either:
* - Passing the following commands to the compiler:\n * - Passing the following commands to the compiler:\n
* * \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode * \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
* 'xx' is device family:\n * 'xx' is device family:\n
* * \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode * \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
* *
* <b>IAR</b>\n * <b>IAR</b>\n
* The flash and RAM sections for the CPU are defined in the linker files: * The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for * 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* example, 'cy8c6x7_cm0plus.icf' and 'cy8c6x7_cm4_dual.icf'. * 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'.
* Note: if the start of the Cortex-M4 application image is changed, the value * \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
* Cy_SysEnableCM4() function call. * Cy_SysEnableCM4() function call.
* *
* The flash and RAM sizes can be changed by editing the macros value in the * Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs: * linker files for both CPUs:
* - 'xx_cm0plus.icf', where 'xx' is the device group: * - 'xx_cm0plus.icf', where 'xx' is the device group:
* * \code define symbol __ICFEDIT_region_IROM_start__ = 0x10000000; \endcode * \code
* * \code define symbol __ICFEDIT_region_IROM_end__ = 0x10080000; \endcode * define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
* * \code define symbol __ICFEDIT_region_IRAM_CM0P_start__ = 0x08000000; \endcode * define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000;
* * \code define symbol __ICFEDIT_region_IRAM_CM0P_end__ = 0x08024000; \endcode * define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000;
* \endcode
* - 'xx_cm4_dual.icf', where 'xx' is the device group: * - 'xx_cm4_dual.icf', where 'xx' is the device group:
* * \code define symbol __ICFEDIT_region_IROM_start__ = 0x10080000; \endcode * \code
* * \code define symbol __ICFEDIT_region_IROM_end__ = 0x10100000; \endcode * define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
* * \code define symbol __ICFEDIT_region_IRAM_CM4_start__ = 0x08024000; \endcode * define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
* * \code define symbol __ICFEDIT_region_IRAM_CM4_end__ = 0x08048000; \endcode * define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
* __ICFEDIT_region_IROM_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' * __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx'
* is the device group. Do this by either: * is the device group. Do this by either:
* - Passing the following commands to the compiler:\n * - Passing the following commands to the compiler:\n
* * \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode * \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
* 'xx' is device family:\n * 'xx' is device family:\n
* * \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode * \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
*
* \subsubsection group_system_config_device_memory_single_core_definition Single-Core Devices
* For single-core devices, 8 KB of flash and RAM are reserved for the pre-build
* Cortex-M0+ application that is loaded for the hidden Cortex-M0+.
* *
* \subsection group_system_config_device_initialization Device Initialization * \subsection group_system_config_device_initialization Device Initialization
* After a power-on-reset (POR), the boot process is handled by the boot code * After a power-on-reset (POR), the boot process is handled by the boot code
@ -140,23 +165,14 @@
* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled * SystemInit() and then calls the main() function. The Cortex-M4 core is disabled
* by default. Enable the core using the \ref Cy_SysEnableCM4() function. * by default. Enable the core using the \ref Cy_SysEnableCM4() function.
* See \ref group_system_config_cm4_functions for more details. * See \ref group_system_config_cm4_functions for more details.
* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores.
* The function has a separate implementation on each core.
* Both function implementations unlock and disable the WDT.
* Therefore enable the WDT after both cores have been initialized.
* *
* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices * \subsubsection group_system_config_single_core_device_initialization Single-Core Devices
* The Cortex-M0+ core is not user-accessible on these devices. In this case the * The Cortex-M0+ core is not user-accessible on these devices. In this case the
* Cortex-M0+ pre-built application image handles setup of the CM0+ core and * Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core.
* starts the Cortex-M4 core.
*
* CM0+ NVIC IRQn channels 26-31 are reserved for system use. Other IRQn channels
* are available to the user application. The pre-built application configures:
* * IRQn 26-27 for the IPC driver
* * IRQn 28-30 for the Crypto driver
* * IRQn 31 for system communication
*
* The Cortex-M0+ application image performs the following tasks:
* * Enables global interrupts on the Cortex-M0+ core.
* * Starts the crypto server. See [Cryptography (Crypto)](\ref group_crypto) for details.
* * Enables the Cortex-M4 core by calling \ref Cy_SysEnableCM4().
* * Requests Deep Sleep mode entry with wakeup on interrupt in the infinite loop.
* *
* \subsection group_system_config_heap_stack_config Heap and Stack Configuration * \subsection group_system_config_heap_stack_config Heap and Stack Configuration
* There are two ways to adjust heap and stack configurations: * There are two ways to adjust heap and stack configurations:
@ -171,13 +187,13 @@
* 'startup_xx_yy.S', where 'xx' is the device family, and 'yy' is the target CPU; * 'startup_xx_yy.S', where 'xx' is the device family, and 'yy' is the target CPU;
* for example, startup_psoc63_cm0plus.s and startup_psoc63_cm4.s. * for example, startup_psoc63_cm0plus.s and startup_psoc63_cm4.s.
* Change the heap and stack sizes by modifying the following lines:\n * Change the heap and stack sizes by modifying the following lines:\n
* * \code .equ Stack_Size, 0x00001000 \endcode * \code .equ Stack_Size, 0x00001000 \endcode
* * \code .equ Heap_Size, 0x00000400 \endcode * \code .equ Heap_Size, 0x00000400 \endcode
* *
* - <b>Specifying via command line</b>\n * - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the compiler:\n * Change the heap and stack sizes passing the following commands to the compiler:\n
* * \code -D __STACK_SIZE=0x000000400 \endcode * \code -D __STACK_SIZE=0x000000400 \endcode
* * \code -D __HEAP_SIZE=0x000000100 \endcode * \code -D __HEAP_SIZE=0x000000100 \endcode
* *
* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK * \subsubsection group_system_config_heap_stack_config_mdk ARM MDK
* - <b>Editing source code files</b>\n * - <b>Editing source code files</b>\n
@ -185,40 +201,40 @@
* 'startup_xx_yy.s', where 'xx' is the device family, and 'yy' is the target * 'startup_xx_yy.s', where 'xx' is the device family, and 'yy' is the target
* CPU; for example, startup_psoc63_cm0plus.s and startup_psoc63_cm4.s. * CPU; for example, startup_psoc63_cm0plus.s and startup_psoc63_cm4.s.
* Change the heap and stack sizes by modifying the following lines:\n * Change the heap and stack sizes by modifying the following lines:\n
* * \code Stack_Size EQU 0x00001000 \endcode * \code Stack_Size EQU 0x00001000 \endcode
* * \code Heap_Size EQU 0x00000400 \endcode * \code Heap_Size EQU 0x00000400 \endcode
* *
* - <b>Specifying via command line</b>\n * - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the assembler:\n * Change the heap and stack sizes passing the following commands to the assembler:\n
* * \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode * \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode
* * \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode * \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode
* *
* \subsubsection group_system_config_heap_stack_config_iar IAR * \subsubsection group_system_config_heap_stack_config_iar IAR
* - <b>Editing source code files</b>\n * - <b>Editing source code files</b>\n
* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', * The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf',
* where 'xx' is the device family, and 'yy' is the target CPU; for example, * where 'xx' is the device family, and 'yy' is the target CPU; for example,
* cy8c6x7_cm0plus.icf and cy8c6x7_cm4_dual.icf. * cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
* Change the heap and stack sizes by modifying the following lines:\n * Change the heap and stack sizes by modifying the following lines:\n
* * \code Stack_Size EQU 0x00001000 \endcode * \code Stack_Size EQU 0x00001000 \endcode
* * \code Heap_Size EQU 0x00000400 \endcode * \code Heap_Size EQU 0x00000400 \endcode
* *
* - <b>Specifying via command line</b>\n * - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the * Change the heap and stack sizes passing the following commands to the
* linker (including quotation marks):\n * linker (including quotation marks):\n
* * \code --define_symbol __STACK_SIZE=0x000000400 \endcode * \code --define_symbol __STACK_SIZE=0x000000400 \endcode
* * \code --define_symbol __HEAP_SIZE=0x000000100 \endcode * \code --define_symbol __HEAP_SIZE=0x000000100 \endcode
* *
* - \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables * \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables
* The CM0+ project and linker script build the CM0+ application image. Similarly, * The CM0+ project and linker script build the CM0+ application image. Similarly,
* the CM4 linker script builds the CM4 application image. Each specifies * the CM4 linker script builds the CM4 application image. Each specifies
* locations, sizes, and contents of sections in memory. See * locations, sizes, and contents of sections in memory. See
* \ref group_system_config_device_memory_definition for the symbols and default * \ref group_system_config_device_memory_definition for the symbols and default
* values. * values.
* *
* The cypdlelftool is invoked by a post-build command. The precise project * The cymcuelftool is invoked by a post-build command. The precise project
* setting is IDE-specific. * setting is IDE-specific.
* *
* The cypdlelftool combines the two executables. The tool examines the * The cymcuelftool combines the two executables. The tool examines the
* executables to ensure that memory regions either do not overlap, or contain * executables to ensure that memory regions either do not overlap, or contain
* identical bytes (shared). If there are no problems, it creates a new ELF file * identical bytes (shared). If there are no problems, it creates a new ELF file
* with the merged image, without changing any of the addresses or data. * with the merged image, without changing any of the addresses or data.
@ -228,7 +244,7 @@
* code actually defines the contents of the vector table and performs the copy. * code actually defines the contents of the vector table and performs the copy.
* \subsubsection group_system_config_device_vector_table_gcc ARM GCC * \subsubsection group_system_config_device_vector_table_gcc ARM GCC
* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and * The linker script file is 'xx_yy.ld', where 'xx' is the device family, and
* 'yy' is the target CPU; for example, cy8c6x7_cm0plus.ld and cy8c6x7_cm4_dual.ld. * 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
* It defines sections and locations in memory.\n * It defines sections and locations in memory.\n
* Copy interrupt vectors from flash to RAM: \n * Copy interrupt vectors from flash to RAM: \n
* From: \code LONG (__Vectors) \endcode * From: \code LONG (__Vectors) \endcode
@ -241,8 +257,8 @@
* Flash to RAM. * Flash to RAM.
* \subsubsection group_system_config_device_vector_table_mdk ARM MDK * \subsubsection group_system_config_device_vector_table_mdk ARM MDK
* The linker script file is 'xx_yy.scat', where 'xx' is the device family, * The linker script file is 'xx_yy.scat', where 'xx' is the device family,
* and 'yy' is the target CPU; for example, cy8c6x7_cm0plus.scat and * and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and
* cy8c6x7_cm4_dual.scat. The linker script specifies that the vector table * cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table
* (RESET_RAM) shall be first in the RAM section.\n * (RESET_RAM) shall be first in the RAM section.\n
* RESET_RAM represents the vector table. It is defined in the assembler startup * RESET_RAM represents the vector table. It is defined in the assembler startup
* files: 'startup_xx_yy.s', where 'xx' is the device family, and 'yy' is the * files: 'startup_xx_yy.s', where 'xx' is the device family, and 'yy' is the
@ -251,7 +267,7 @@
* *
* \subsubsection group_system_config_device_vector_table_iar IAR * \subsubsection group_system_config_device_vector_table_iar IAR
* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and * The linker script file is 'xx_yy.icf', where 'xx' is the device family, and
* 'yy' is the target CPU; for example, cy8c6x7_cm0plus.icf and cy8c6x7_cm4_dual.icf. * 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
* This file defines the .intvec_ram section and its location. * This file defines the .intvec_ram section and its location.
* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode * \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode
* The vector table address (and the vector table itself) are defined in the * The vector table address (and the vector table itself) are defined in the
@ -265,7 +281,6 @@
* more details. * more details.
* *
* \section group_system_config_MISRA MISRA Compliance * \section group_system_config_MISRA MISRA Compliance
* The drivers violates the following MISRA-C:2004 rules:
* *
* <table class="doxtable"> * <table class="doxtable">
* <tr> * <tr>
@ -274,9 +289,14 @@
* <th>Rule Description</th> * <th>Rule Description</th>
* <th>Description of Deviation(s)</th> * <th>Description of Deviation(s)</th>
* </tr> * </tr>
* <tr>
* <td>2.3</td>
* <td>R</td>
* <td>The character sequence // shall not be used within a comment.</td>
* <td>The comments provide a useful WEB link to the documentation.</td>
* </tr>
* </table> * </table>
* *
*
* \section group_system_config_changelog Changelog * \section group_system_config_changelog Changelog
* <table class="doxtable"> * <table class="doxtable">
* <tr> * <tr>
@ -285,6 +305,39 @@
* <th>Reason for Change</th> * <th>Reason for Change</th>
* </tr> * </tr>
* <tr> * <tr>
* <td rowspan="2"> 2.10</td>
* <td>Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n
* Removed $Sub$$main symbol for ARM MDK compiler.
* </td>
* <td>uVision Debugger support.</td>
* </tr>
* <tr>
* <td>Updated description of the Startup behavior for Single-Core Devices. \n
* Added note about WDT disabling by SystemInit() function.
* </td>
* <td>Documentation improvement.</td>
* </tr>
* <tr>
* <td rowspan="4"> 2.0</td>
* <td>Added restoring of FLL registers to the default state in SystemInit() API for single core devices.
* Single core device support.
* </td>
* </tr>
* <tr>
* <td>Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n
* Renamed 'wflash' memory region to 'em_eeprom'.
* </td>
* <td>Linker scripts usability improvement.</td>
* </tr>
* <tr>
* <td>Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.</td>
* <td>Reserved system resources for internal operations.</td>
* </tr>
* <tr>
* <td>Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.</td>
* <td>To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.</td>
* </tr>
* <tr>
* <td>1.0</td> * <td>1.0</td>
* <td>Initial version</td> * <td>Initial version</td>
* <td></td> * <td></td>
@ -308,6 +361,17 @@
* \} * \}
*/ */
/**
* \addtogroup group_system_config_system_functions
* \{
* \details
* The following system functions implement CMSIS Core functions.
* Refer to the [CMSIS documentation]
* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
* for more details.
* \}
*/
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
@ -414,12 +478,12 @@ extern "C" {
#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
/** The Cortex-M0+ startup driver identifier */ /** The Cortex-M0+ startup driver identifier */
#define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0Eu) & 0x3FFFu) << 18u)) #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0Eu) & 0x3FFFu) << 18u))
#endif #endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) #if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN)
/** The Cortex-M4 startup driver identifier */ /** The Cortex-M4 startup driver identifier */
#define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0Fu) & 0x3FFFu) << 18u)) #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0Fu) & 0x3FFFu) << 18u))
#endif #endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */
/** \} group_system_config_system_macro */ /** \} group_system_config_system_macro */
@ -471,7 +535,7 @@ extern uint32_t cy_delay32kMs;
#define CY_SYS_CM4_STATUS_RESET (1u) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ #define CY_SYS_CM4_STATUS_RESET (1u) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */
/** \} group_system_config_cm4_status_macro */ /** \} group_system_config_cm4_status_macro */
#endif #endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
/** \addtogroup group_system_config_globals /** \addtogroup group_system_config_globals
* \{ * \{

64
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/ipc_rpc.h Normal file
View File

@ -0,0 +1,64 @@
/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef IPC_RPC_H
#define IPC_RPC_H
#include <stdint.h>
#if defined(__MBED__)
#define IPCPIPE_ASSERT MBED_ASSERT
#include "mbed_assert.h"
#else
#include "project.h"
#define IPCPIPE_ASSERT CY_ASSERT
#endif
#define IPCRPC_MAX_ARGUMENTS 8
/* IPC Pipe message data structure */
typedef struct
{
uint32_t client_id;
uint32_t result;
uint32_t args_num;
uint32_t args[IPCRPC_MAX_ARGUMENTS];
} IpcRpcMessage;
typedef struct
{
volatile uint8_t busy_flag;
IpcRpcMessage message;
} IpcRpcBuffer;
#if defined(__cplusplus)
extern "C" {
#endif
void ipcrpc_init(void);
uint32_t ipcrpc_call(uint32_t call_id, uint32_t args_num, ...);
#if defined(__cplusplus)
}
#endif
#endif /* IPC_RPC_H */
/* [] END OF FILE */

74
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/psoc6_static_srm.h Normal file
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@ -0,0 +1,74 @@
/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file defines hardware resources statically allocated to M0 core
* when static resource managemnt is used.
*
* There are 4 classes of resources that must be declared here:
* - M0_ASSIGNED_PORTS macro defines which ports and pins are reserved
* for M0 core use.
* You define these as a colon separated list of ports and pins reserved
* using macro SRM_PORT(port_num, pins), one time for each reserved port.
* SRM_PORT macro arguments are port number, in the range 0 .. 14 and
* pins is a hex value with a bit set for each reserved pin on a port.
*
* - M0_ASSIGNED_DIVIDERS macro defines which clock dividers are reserved
* for M0 core use.
* You define these as a colon separated list of dividers reserved
* using macro SRM_DIVIDER(type, reservations), one time for each required
* devider type.
* SRM_DIVIDER arguments are divider type, one of cy_en_divider_types_t
* values and reservations is a hex mask value with a bit set for each
* reserved divider of a given type.
*
* - M0_ASSIGNED_SCBS macro defines which SCB blocks are reserved
* for M0 core use.
* You define these as a colon separated list of SCBs reserved using
* macro SRM_SCB(n), which argument is SCB number in a range 0 .. 7.
*
* - M0_ASSIGNED_TCPWM macro defines which TCPWM blocks are reserved
* for M0 core use.
* You define these as a colon separated list of TCPWMs reserved using
* macro SRM_TCPWM(n), which argument is TCPWM number in a range 0 .. 31.
*
* If a particular resource class is not used at all by M0 core you can
* skip defining relevant M0_ASSIGNED_* macro or define it as an empty one.
*
* Examples:
* #define M0_ASSIGNED_PORTS SRM_PORT(0, 0x30), SRM_PORT(5, 0x03)
*
* #define M0_ASSIGNED_DIVIDERS SRM_DIVIDER(CY_SYSCLK_DIV_8_BIT, 0x01)
*
* #define M0_ASSIGNED_SCBS SRM_SCB(2)
*
* #define M0_ASSIGNED_TCPWMS
*
*/
// Reservations below apply to default M0 hex image.
// P0_0 and p0_1 reserved for WCO, P6-6 and P6_7 reserved for SWD
#define M0_ASSIGNED_PORTS SRM_PORT(0, 0x03), SRM_PORT(6, 0xc0), SRM_PORT(11, 0x02)
// 8-bit divider 0 reserved for us ticker.
#define M0_ASSIGNED_DIVIDERS SRM_DIVIDER(CY_SYSCLK_DIV_8_BIT, 0x01), \
SRM_DIVIDER(CY_SYSCLK_DIV_16_BIT, 0x01)
#define M0_ASSIGNED_SCBS
#define M0_ASSIGNED_TCPWMS
/* End of File */

160
targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/PinNames.h → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA/PinNames.h
View File

@ -1,31 +1,18 @@
/* mbed Microcontroller Library /*
******************************************************************************* * mbed Microcontroller Library
* Copyright (c) XXX * Copyright (c) 2017-2018 Future Electronics
* All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Licensed under the Apache License, Version 2.0 (the "License");
* modification, are permitted provided that the following conditions are met: * you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* *
* 1. Redistributions of source code must retain the above copyright notice, * http://www.apache.org/licenses/LICENSE-2.0
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * Unless required by applicable law or agreed to in writing, software
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * distributed under the License is distributed on an "AS IS" BASIS,
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * See the License for the specific language governing permissions and
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * limitations under the License.
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/ */
#ifndef MBED_PINNAMES_H #ifndef MBED_PINNAMES_H
@ -35,12 +22,20 @@
#include "PinNamesTypes.h" #include "PinNamesTypes.h"
#include "PortNames.h" #include "PortNames.h"
#ifdef __cplusplus #if PSOC6_ENABLE_M0_M4_DEBUG
extern "C" {
#endif
#define CY_UART_RX P5_0 #define CY_STDIO_UART_RX P9_0
#define CY_UART_TX P5_1 #define CY_STDIO_UART_TX P9_1
#define CY_STDIO_UART_CTS P9_2
#define CY_STDIO_UART_RTS P9_3
#else
#define CY_STDIO_UART_RX P5_0
#define CY_STDIO_UART_TX P5_1
#define CY_STDIO_UART_CTS P5_2
#define CY_STDIO_UART_RTS P5_3
#endif // PSOC6_ENABLE_M0_M4_DEBUG
// PinName[15-0] = Port[15-8] + Pin[7-0] // PinName[15-0] = Port[15-8] + Pin[7-0]
typedef enum { typedef enum {
@ -179,73 +174,80 @@ typedef enum {
P14_6 = (Port14 << 8) + 0x06, P14_6 = (Port14 << 8) + 0x06,
P14_7 = (Port14 << 8) + 0x07, P14_7 = (Port14 << 8) + 0x07,
P15_0 = (Port15 << 8) + 0x00,
P15_1 = (Port15 << 8) + 0x01,
P15_2 = (Port15 << 8) + 0x02,
P15_3 = (Port15 << 8) + 0x03,
P15_4 = (Port15 << 8) + 0x04,
P15_5 = (Port15 << 8) + 0x05,
P15_6 = (Port15 << 8) + 0x06,
P15_7 = (Port15 << 8) + 0x07,
// Arduino connector namings // Arduino connector namings
A0 = P10_0, A0 = P10_4,
A1 = P10_1, A1 = P10_5,
A2 = P10_2, A2 = P10_2,
A3 = P10_3, A3 = P10_3,
A4 = P10_4, A4 = P10_1,
A5 = P10_5, A5 = P10_0,
D0 = P5_0, D0 = P6_4,
D1 = P5_1, D1 = P6_5,
D2 = P5_2, D2 = P10_6,
D3 = P5_3, D3 = P12_6,
D4 = P5_4, D4 = P12_7,
D5 = P5_5, D5 = P6_2,
D6 = P5_6, D6 = P6_3,
D7 = P0_2, D7 = P7_2,
D8 = P13_0, D8 = P7_1,
D9 = P13_1, D9 = P7_7,
D10 = P12_3, D10 = P9_4,
D11 = P12_0, D11 = P9_0,
D12 = P12_1, D12 = P9_1,
D13 = P12_2, D13 = P9_2,
D14 = P10_1,
D15 = P10_0,
// Generic signals namings // Generic signal names
LED_RED = P0_3, I2C_SCL = P10_0,
LED_GREEN = P1_1, I2C_SDA = P10_1,
LED_BLUE = P11_1, SPI_MOSI = P9_0,
SPI_MISO = P9_1,
SPI_CLK = P9_2,
SPI_CS = P9_3,
UART_RX = P6_4,
UART_TX = P6_5,
SWITCH2 = P0_4, SWITCH2 = P0_4,
LED1 = P6_2,
LED1 = LED_RED, LED2 = P6_3,
LED2 = LED_GREEN, LED3 = P7_2,
LED3 = LED_BLUE, LED4 = P6_2,
LED4 = LED_RED, LED_RED = LED1,
USER_BUTTON = SWITCH2, USER_BUTTON = SWITCH2,
BUTTON1 = USER_BUTTON, BUTTON1 = USER_BUTTON,
// Standardized interfaces names // Standardized interfaces names
SERIAL_TX = CY_UART_TX, STDIO_UART_TX = CY_STDIO_UART_TX,
SERIAL_RX = CY_UART_RX, STDIO_UART_RX = CY_STDIO_UART_RX,
USBTX = CY_UART_TX, STDIO_UART_CTS = CY_STDIO_UART_CTS,
USBRX = CY_UART_RX, STDIO_UART_RTS = CY_STDIO_UART_RTS,
// I2C_SCL = PB_8, USBTX = CY_STDIO_UART_TX,
// I2C_SDA = PB_9, USBRX = CY_STDIO_UART_RX,
// SPI_MOSI = PA_7,
// SPI_MISO = PA_6,
// SPI_SCK = PA_5,
// SPI_CS = PB_6,
// PWM_OUT = PB_3,
// Not connected // Not connected
NC = (int)0xFFFFFFFF NC = (int)0xFFFFFFFF
} PinName; } PinName;
#ifdef __cplusplus // PinName[15-0] = Port[15-8] + Pin[4-0]
static inline unsigned CY_PIN(PinName pin)
{
return pin & 0x07;
} }
#endif
static inline unsigned CY_PORT(PinName pin)
{
return (pin >> 8) & 0xFF;
}
// Because MBED pin mapping API does not allow to map multiple instances of the PWM
// to be mapped to the same pin, we create special pin names to force 32-bit PWM unit
// usage instead of standard 16-bit PWM.
#define PWM32(pin) CY_PIN_FORCE_PWM_32(pin)
#endif #endif

335
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA/TARGET_FUTURE_SEQUANA_M0/board_config.c Normal file
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@ -0,0 +1,335 @@
/*******************************************************************************
* File Name: cyfitter_cfg.c
*
* PSoC Creator 4.2
*
* Description:
* This file contains device initialization code.
* Except for the user defined sections in CyClockStartupError(), this file should not be modified.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
/*
* Copyright (c) 20017-2018 Future Electronics
*/
#include <string.h>
#include "device.h"
#include "gpio/cy_gpio.h"
#include "syslib/cy_syslib.h"
#include "sysclk/cy_sysclk.h"
#include "systick/cy_systick.h"
#include "sysanalog/cy_sysanalog.h"
#if FEATURE_BLE
#include "ble/cy_ble_clk.h"
#endif // FEATURE_BLE
#define CY_NEED_CYCLOCKSTARTUPERROR 1
#include "syspm/cy_syspm.h"
#include "psoc6_utils.h"
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
#define CYPACKED
#define CYPACKED_ATTR __attribute__ ((packed))
#define CYALIGNED __attribute__ ((aligned))
#define CY_CFG_UNUSED __attribute__ ((unused))
#ifndef CY_CFG_SECTION
#define CY_CFG_SECTION __attribute__ ((section(".psocinit")))
#endif
#if defined(__ARMCC_VERSION)
#define CY_CFG_MEMORY_BARRIER() __memory_changed()
#else
#define CY_CFG_MEMORY_BARRIER() __sync_synchronize()
#endif
#elif defined(__ICCARM__)
#include <intrinsics.h>
#define CYPACKED __packed
#define CYPACKED_ATTR
#define CYALIGNED _Pragma("data_alignment=4")
#define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177")
#define CY_CFG_SECTION _Pragma("location=\".psocinit\"")
#define CY_CFG_MEMORY_BARRIER() __DMB()
#else
#error Unsupported toolchain
#endif
#ifndef CYCODE
#define CYCODE
#endif
#ifndef CYDATA
#define CYDATA
#endif
#ifndef CYFAR
#define CYFAR
#endif
#ifndef CYXDATA
#define CYXDATA
#endif
CY_CFG_UNUSED
static void CYMEMZERO(void *s, size_t n);
CY_CFG_UNUSED
static void CYMEMZERO(void *s, size_t n)
{
(void)memset(s, 0, n);
}
CY_CFG_UNUSED
static void CYCONFIGCPY(void *dest, const void *src, size_t n);
CY_CFG_UNUSED
static void CYCONFIGCPY(void *dest, const void *src, size_t n)
{
(void)memcpy(dest, src, n);
}
CY_CFG_UNUSED
static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);
CY_CFG_UNUSED
static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)
{
(void)memcpy(dest, src, n);
}
/* Clock startup error codes */
#define CYCLOCKSTART_NO_ERROR 0u
#define CYCLOCKSTART_XTAL_ERROR 1u
#define CYCLOCKSTART_32KHZ_ERROR 2u
#define CYCLOCKSTART_PLL_ERROR 3u
#define CYCLOCKSTART_FLL_ERROR 4u
#define CYCLOCKSTART_WCO_ERROR 5u
#ifdef CY_NEED_CYCLOCKSTARTUPERROR
/*******************************************************************************
* Function Name: CyClockStartupError
********************************************************************************
* Summary:
* If an error is encountered during clock configuration (crystal startup error,
* PLL lock error, etc.), the system will end up here. Unless reimplemented by
* the customer, this function will stop in an infinite loop.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_UNUSED
static void CyClockStartupError(uint8 errorCode);
CY_CFG_UNUSED
static void CyClockStartupError(uint8 errorCode)
{
/* To remove the compiler warning if errorCode not used. */
errorCode = errorCode;
/* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */
/* we will end up here to allow the customer to implement something to */
/* deal with the clock condition. */
#ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK
CY_CFG_Clock_Startup_ErrorCallback();
#else
while(1) {}
#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */
}
#endif
static void ClockInit(void)
{
uint32_t status;
/* Enable all source clocks */
status = Cy_SysClk_WcoEnable(500000u);
if (CY_RET_SUCCESS != status)
{
CyClockStartupError(CYCLOCKSTART_WCO_ERROR);
}
Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
#if FEATURE_BLE
{
cy_stc_ble_bless_eco_cfg_params_t bleCfg = {
.ecoXtalStartUpTime = (785 / 31.25),
.loadCap = ((9.9 - 7.5) / 0.075),
.ecoFreq = CY_BLE_BLESS_ECO_FREQ_32MHZ,
.ecoSysDiv = CY_BLE_SYS_ECO_CLK_DIV_4
};
Cy_BLE_EcoStart(&bleCfg);
}
#endif // FEATURE_BLE
/* Configure CPU clock dividers */
Cy_SysClk_ClkFastSetDivider(0u);
Cy_SysClk_ClkPeriSetDivider((CY_CLK_HFCLK0_FREQ_HZ / CY_CLK_PERICLK_FREQ_HZ) - 1);
Cy_SysClk_ClkSlowSetDivider((CY_CLK_PERICLK_FREQ_HZ / CY_CLK_SYSTEM_FREQ_HZ) - 1);
/* Configure LF & HF clocks */
Cy_SysClk_ClkHfSetSource(0u, CY_SYSCLK_CLKHF_IN_CLKPATH1);
Cy_SysClk_ClkHfSetDivider(0u, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(0u);
/* Configure Path Clocks */
/* PLL path is used to clock HF domain from BLE ECO */
Cy_SysClk_ClkPathSetSource(2, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkPathSetSource(3, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkPathSetSource(4, CY_SYSCLK_CLKPATH_IN_IMO);
#if FEATURE_BLE
Cy_SysClk_ClkPathSetSource(0, CY_SYSCLK_CLKPATH_IN_ALTHF);
Cy_SysClk_ClkPathSetSource(1, CY_SYSCLK_CLKPATH_IN_ALTHF);
{
const cy_stc_pll_config_t pllConfig = {
.inputFreq = CY_CLK_ALTHF_FREQ_HZ,
.outputFreq = CY_CLK_HFCLK0_FREQ_HZ,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO
};
#else
Cy_SysClk_ClkPathSetSource(0, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkPathSetSource(1, CY_SYSCLK_CLKPATH_IN_IMO);
{
const cy_stc_pll_config_t pllConfig = {
.inputFreq = CY_CLK_IMO_FREQ_HZ,
.outputFreq = CY_CLK_HFCLK0_FREQ_HZ,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO
};
#endif // FEATURE_BLE
status = Cy_SysClk_PllConfigure(1u, &pllConfig);
if (CY_SYSCLK_SUCCESS != status) {
CyClockStartupError(CYCLOCKSTART_PLL_ERROR);
}
}
status = Cy_SysClk_PllEnable(1u, 10000u);
if (CY_SYSCLK_SUCCESS != status) {
CyClockStartupError(CYCLOCKSTART_PLL_ERROR);
}
/* Configure miscellaneous clocks */
Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_HF0_NODIV);
Cy_SysClk_ClkTimerSetDivider(0);
Cy_SysClk_ClkTimerEnable();
Cy_SysClk_ClkPumpSetSource(CY_SYSCLK_PUMP_IN_CLKPATH0);
Cy_SysClk_ClkPumpSetDivider(CY_SYSCLK_PUMP_DIV_4);
Cy_SysClk_ClkPumpEnable();
Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
/* Disable unused clocks started by default */
Cy_SysClk_IloDisable();
/* Set memory wait states based on HFClk[0] */
Cy_SysLib_SetWaitStates(false, (CY_CLK_HFCLK0_FREQ_HZ + 990000) / 1000000UL);
}
/* Analog API Functions */
/*******************************************************************************
* Function Name: AnalogSetDefault
********************************************************************************
*
* Summary:
* Sets up the analog portions of the chip to default values based on chip
* configuration options from the project.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
static void AnalogSetDefault(void)
{
const cy_stc_sysanalog_config_t config = {
.startup = CY_SYSANALOG_STARTUP_NORMAL,
.iztat = CY_SYSANALOG_IZTAT_SOURCE_LOCAL,
.vref = CY_SYSANALOG_VREF_SOURCE_LOCAL_1_2V,
.deepSleep = CY_SYSANALOG_DEEPSLEEP_IPTAT_1
};
Cy_SysAnalog_Init(&config);
Cy_SysAnalog_Enable();
}
/*******************************************************************************
* Function Name: Cy_SystemInit
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
void Cy_SystemInit(void)
{
/* Set worst case memory wait states (150 MHz), ClockInit() will update */
Cy_SysLib_SetWaitStates(false, 150);
if(0u == Cy_SysLib_GetResetReason()) { /* POR, XRES, or BOD */
Cy_SysLib_ResetBackupDomain();
}
/* Power Mode */
Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_1_1V);
/* PMIC Control */
Cy_SysPm_UnlockPmic();
Cy_SysPm_DisablePmicOutput();
/* Pin0_0 and Pin0_1 drive WCO, configure as analog before configuring clock */
cy_reserve_io_pin(P0_0);
cy_reserve_io_pin(P0_1);
Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0, CY_GPIO_DM_ANALOG, 0, P0_0_GPIO);
Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1, CY_GPIO_DM_ANALOG, 0, P0_1_GPIO);
/* Clock */
ClockInit();
/******* Pre-defined port configuration section ********/
{
/* RGB LED is P_0_3 (R), P_1_1 (G) and P_11_1 (B) */
const uint32_t led_off = 1;
Cy_GPIO_Pin_FastInit(GPIO_PRT0, 3, CY_GPIO_DM_STRONG_IN_OFF, led_off, P0_3_GPIO);
Cy_GPIO_Pin_FastInit(GPIO_PRT1, 1, CY_GPIO_DM_STRONG_IN_OFF, led_off, P1_1_GPIO);
Cy_GPIO_Pin_FastInit(GPIO_PRT11, 1, CY_GPIO_DM_STRONG_IN_OFF, led_off, P11_1_GPIO);
/* USER BUTTON is P_0_4 */
Cy_GPIO_Pin_FastInit(GPIO_PRT0, 4, CY_GPIO_DM_PULLUP, 1, P0_4_GPIO);
/* Configure hw debug interface on port 6 */
cy_reserve_io_pin(P6_6);
cy_reserve_io_pin(P6_7);
Cy_GPIO_Pin_FastInit(GPIO_PRT6, 6, CY_GPIO_DM_PULLUP, 0, P6_6_CPUSS_SWJ_SWDIO_TMS);
Cy_GPIO_Pin_FastInit(GPIO_PRT6, 7, CY_GPIO_DM_PULLDOWN, 0, P6_7_CPUSS_SWJ_SWCLK_TCLK);
}
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}

31
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA/stdio_init.cpp Normal file
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@ -0,0 +1,31 @@
/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed.h"
/*
* This makes sure, stdio serial is initialized on M4 core at the very beging
* and outside of any critical context, so printf is usable anyware, including
* interrupt and fault handlers.
* Hardware devices cannot be initialized in the interrupt or critical section context
* on PSoC 6 M4 core.
*/
#ifndef TARGET_MCU_PSOC6_M0
Serial _stdio_uart_object(STDIO_UART_TX, STDIO_UART_RX);
#endif

190
targets/TARGET_Cypress/TARGET_PSOC6/analogin_api.c Normal file
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@ -0,0 +1,190 @@
/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "device.h"
#include "analogin_api.h"
#include "cy_sar.h"
#include "psoc6_utils.h"
#include "mbed_assert.h"
#include "mbed_error.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include "platform/mbed_error.h"
#if DEVICE_ANALOGIN
const uint16_t ADC_MAX_VALUE = 0x0fff;
const uint32_t SAR_BASE_CLOCK_HZ = 18000000; // 18 MHz or less
/** Default SAR channel configuration.
* Notice, that because dynamic SAR MUX switching is disabled,
* per-channel MUX configuration is ignored, thus not configured here.
*/
#define DEFAULT_CHANNEL_CONFIG ( \
CY_SAR_CHAN_SINGLE_ENDED | \
CY_SAR_CHAN_AVG_ENABLE | \
CY_SAR_CHAN_SAMPLE_TIME_0 \
)
/** Global SAR configuration data, modified as channels are configured.
*/
static cy_stc_sar_config_t sar_config = {
.ctrl = CY_SAR_VREF_SEL_VDDA_DIV_2 |
CY_SAR_NEG_SEL_VREF |
CY_SAR_CTRL_COMP_DLY_12 |
CY_SAR_COMP_PWR_50 |
CY_SAR_SARSEQ_SWITCH_DISABLE, /**< Control register */
.sampleCtrl = CY_SAR_RIGHT_ALIGN |
CY_SAR_SINGLE_ENDED_UNSIGNED |
CY_SAR_AVG_CNT_16 |
CY_SAR_AVG_MODE_SEQUENTIAL_FIXED |
CY_SAR_TRIGGER_MODE_FW_ONLY, /**< Sample control register */
.sampleTime01 = (4uL << CY_SAR_SAMPLE_TIME0_SHIFT) |
(4uL << CY_SAR_SAMPLE_TIME1_SHIFT), /**< Sample time in ADC clocks for ST0 and ST1 */
.sampleTime23 = (4uL << CY_SAR_SAMPLE_TIME2_SHIFT) |
(4uL << CY_SAR_SAMPLE_TIME3_SHIFT), /**< Sample time in ADC clocks for ST2 and ST3 */
.rangeThres = 0, /**< Range detect threshold register for all channels (unused)*/
.rangeCond = 0, /**< Range detect mode for all channels (unused)*/
.chanEn = 0, /**< Enable bits for the channels */
.chanConfig = { /**< Channel configuration registers */
DEFAULT_CHANNEL_CONFIG, // chn 0
DEFAULT_CHANNEL_CONFIG, // chn 1
DEFAULT_CHANNEL_CONFIG, // chn 2
DEFAULT_CHANNEL_CONFIG, // chn 3
DEFAULT_CHANNEL_CONFIG, // chn 4
DEFAULT_CHANNEL_CONFIG, // chn 5
DEFAULT_CHANNEL_CONFIG, // chn 6
DEFAULT_CHANNEL_CONFIG, // chn 7
DEFAULT_CHANNEL_CONFIG, // chn 8
DEFAULT_CHANNEL_CONFIG, // chn 9
DEFAULT_CHANNEL_CONFIG, // chn 10
DEFAULT_CHANNEL_CONFIG, // chn 11
DEFAULT_CHANNEL_CONFIG, // chn 12
DEFAULT_CHANNEL_CONFIG, // chn 13
DEFAULT_CHANNEL_CONFIG, // chn 14
DEFAULT_CHANNEL_CONFIG, // chn 15
},
.intrMask = 0, /**< Interrupt enable mask */
.satIntrMask = 0, /**< Saturate interrupt mask register */
.rangeIntrMask = 0, /**< Range interrupt mask register */
.muxSwitch = 0, /**< SARMUX firmware switches to connect analog signals to SAR */
.muxSwitchSqCtrl = 0, /**< SARMUX Switch SAR sequencer control */
.configRouting = false, /**< Configure or ignore routing related registers (muxSwitch, muxSwitchSqCtrl) */
.vrefMvValue = 0, /**< Reference voltage in millivolts used in counts to volts conversion */
};
static bool sar_initialized = false;
static void sar_init(analogin_t *obj)
{
if (!sar_initialized) {
uint32_t sar_clock_divider = CY_INVALID_DIVIDER;
sar_initialized = true;
// Allocate and setup clock.
sar_clock_divider = cy_clk_allocate_divider(CY_SYSCLK_DIV_8_BIT);
if (sar_clock_divider == CY_INVALID_DIVIDER) {
error("SAR clock divider allocation failed.");
return;
}
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT,
sar_clock_divider,
((CY_CLK_PERICLK_FREQ_HZ + SAR_BASE_CLOCK_HZ / 2) / SAR_BASE_CLOCK_HZ) - 1);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, sar_clock_divider);
Cy_SysClk_PeriphAssignDivider(obj->clock, CY_SYSCLK_DIV_8_BIT, sar_clock_divider);
Cy_SAR_Init(obj->base, &sar_config);
Cy_SAR_Enable(obj->base);
}
}
/** Initialize the analogin peripheral
*
* Configures the pin used by analogin.
* @param obj The analogin object to initialize
* @param pin The analogin pin name
*/
void analogin_init(analogin_t *obj, PinName pin)
{
uint32_t sar = 0;
uint32_t sar_function = 0;
MBED_ASSERT(obj);
MBED_ASSERT(pin != (PinName)NC);
sar = pinmap_peripheral(pin, PinMap_ADC);
if (sar != (uint32_t)NC) {
if (cy_reserve_io_pin(pin)) {
error("ANALOG IN pin reservation conflict.");
}
obj->base = (SAR_Type*)CY_PERIPHERAL_BASE(sar);
obj->pin = pin;
obj->channel_mask = 1 << CY_PIN(pin);
// Configure clock.
sar_function = pinmap_function(pin, PinMap_ADC);
obj->clock = CY_PIN_CLOCK(sar_function);
sar_init(obj);
pin_function(pin, sar_function);
} else {
error("ANALOG IN pinout mismatch.");
}
}
/** Read the input voltage, represented as a float in the range [0.0, 1.0]
*
* @param obj The analogin object
* @return A floating value representing the current input voltage
*/
float analogin_read(analogin_t *obj)
{
uint16_t result = analogin_read_u16(obj);
return (float)result * (1.0 / ADC_MAX_VALUE);
}
/** Read the value from analogin pin, represented as an unsigned 16bit value
*
* @param obj The analogin object
* @return An unsigned 16bit value representing the current input voltage
*/
uint16_t analogin_read_u16(analogin_t *obj)
{
uint32_t result = 0;
Cy_SAR_SetChanMask(obj->base, obj->channel_mask);
Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, obj->channel_mask, CY_SAR_SWITCH_CLOSE);
Cy_SAR_StartConvert(obj->base, CY_SAR_START_CONVERT_SINGLE_SHOT);
if (Cy_SAR_IsEndConversion(obj->base, CY_SAR_WAIT_FOR_RESULT) == CY_SAR_SUCCESS) {
result = Cy_SAR_GetResult32(obj->base, CY_PIN(obj->pin));
} else {
error("ANALOG IN: measurement failed!");
}
Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, obj->channel_mask, CY_SAR_SWITCH_OPEN);
// We are running 16x oversampling extending results to 16 bits.
return (uint16_t)(result);
}
#endif // DEVICE_ANALOGIN

185
targets/TARGET_Cypress/TARGET_PSOC6/analogout_api.c Normal file
View File

@ -0,0 +1,185 @@
/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "device.h"
#include "analogout_api.h"
#include "cy_ctdac.h"
#include "psoc6_utils.h"
#include "mbed_assert.h"
#include "mbed_error.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include "platform/mbed_error.h"
#if DEVICE_ANALOGOUT
#define CTDAC_NUM_BITS 12
const uint16_t CTDAC_MAX_VALUE = (uint16_t)((1UL << CTDAC_NUM_BITS) - 1);
const uint32_t CTDAC_BASE_CLOCK_HZ = 500000; // 500 kHz or less
#define CTDAC_DEGLITCH_CYCLES 35
/** Global CTDAC configuration data.
*/
static cy_stc_ctdac_config_t ctdac_config = {
.refSource = CY_CTDAC_REFSOURCE_VDDA, /**< Reference source: Vdda or externally through Opamp1 of CTB */
.formatMode = CY_CTDAC_FORMAT_UNSIGNED, /**< Format of DAC value: signed or unsigned */
.updateMode = CY_CTDAC_UPDATE_BUFFERED_WRITE, /**< Update mode: direct or buffered writes or hardware, edge or level */
.deglitchMode = CY_CTDAC_DEGLITCHMODE_UNBUFFERED, /**< Deglitch mode: disabled, buffered, unbuffered, or both */
.outputMode = CY_CTDAC_OUTPUT_VALUE, /**< Output mode: enabled (value or value + 1), high-z, Vssa, or Vdda */
.outputBuffer = CY_CTDAC_OUTPUT_UNBUFFERED, /**< Output path: Buffered through Opamp0 of CTB or connected directly to Pin 6 */
.deepSleep = CY_CTDAC_DEEPSLEEP_DISABLE, /**< Enable or disable the CTDAC during Deep Sleep */
.deglitchCycles = CTDAC_DEGLITCH_CYCLES, /**< Number of deglitch cycles from 0 to 63 */
.value = 0, /**< Current DAC value */
.nextValue = 0, /**< Next DAC value for double buffering */
.enableInterrupt = false, /**< If true, enable interrupt when next value register is transferred to value register */
.configClock = false, /**< Configure or ignore clock information */
};
static bool ctdac_initialized = 0;
static void ctdac_init(dac_t *obj)
{
if (!ctdac_initialized) {
uint32_t dac_clock_divider = CY_INVALID_DIVIDER;
ctdac_initialized = true;
// Allocate and setup clock.
dac_clock_divider = cy_clk_allocate_divider(CY_SYSCLK_DIV_8_BIT);
if (dac_clock_divider == CY_INVALID_DIVIDER) {
error("CTDAC clock divider allocation failed.");
return;
}
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT,
dac_clock_divider,
((CY_CLK_PERICLK_FREQ_HZ + CTDAC_BASE_CLOCK_HZ / 2) / CTDAC_BASE_CLOCK_HZ) - 1);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, dac_clock_divider);
Cy_SysClk_PeriphAssignDivider(obj->clock, CY_SYSCLK_DIV_8_BIT, dac_clock_divider);
Cy_CTDAC_Init(obj->base, &ctdac_config);
Cy_CTDAC_Enable(obj->base);
}
}
/** Initialize the analogout peripheral
*
* Configures the pin used by analogout.
* @param obj The analogout object to initialize
* @param pin The analogout pin name
*/
void analogout_init(dac_t *obj, PinName pin)
{
uint32_t dac = 0;
uint32_t dac_function = 0;
MBED_ASSERT(obj);
MBED_ASSERT(pin != (PinName)NC);
dac = pinmap_peripheral(pin, PinMap_DAC);
if (dac != (uint32_t)NC) {
if (cy_reserve_io_pin(pin)) {
error("ANALOG OUT pin reservation conflict.");
}
obj->base = (CTDAC_Type*)CY_PERIPHERAL_BASE(dac);
obj->pin = pin;
// Configure clock.
dac_function = pinmap_function(pin, PinMap_DAC);
obj->clock = CY_PIN_CLOCK(dac_function);
pin_function(pin, dac_function);
ctdac_init(obj);
} else {
error("ANALOG OUT pinout mismatch.");
}
}
/** Release the analogout object
*
* Note: This is not currently used in the mbed-drivers
* @param obj The analogout object
*/
void analogout_free(dac_t *obj)
{
}
/** Set the output voltage, specified as a percentage (float)
*
* @param obj The analogout object
* @param value The floating-point output voltage to be set
*/
void analogout_write(dac_t *obj, float value)
{
uint32_t val = 0;
if (value > 1.0) {
val = CTDAC_MAX_VALUE;
} else if (value > 0.0) {
val = value * CTDAC_MAX_VALUE;
}
Cy_CTDAC_SetValueBuffered(obj->base, val);
}
/** Set the output voltage, specified as unsigned 16-bit
*
* @param obj The analogout object
* @param value The unsigned 16-bit output voltage to be set
*/
void analogout_write_u16(dac_t *obj, uint16_t value)
{
uint32_t val = 0;
val = (value >> (16 - CTDAC_NUM_BITS)); // Convert from 16-bit range.
Cy_CTDAC_SetValueBuffered(obj->base, val);
}
/** Read the current voltage value on the pin
*
* @param obj The analogout object
* @return A floating-point value representing the current voltage on the pin,
* measured as a percentage
*/
float analogout_read(dac_t *obj)
{
return (float)analogout_read_u16(obj) / 0xffff;
}
/** Read the current voltage value on the pin, as a normalized unsigned 16bit value
*
* @param obj The analogout object
* @return An unsigned 16-bit value representing the current voltage on the pin
*/
uint16_t analogout_read_u16(dac_t *obj)
{
uint16_t value = (obj->base->CTDAC_VAL_NXT >> CTDAC_CTDAC_VAL_NXT_VALUE_Pos) & CTDAC_CTDAC_VAL_NXT_VALUE_Msk;
value <<= (16 - CTDAC_NUM_BITS); // Convert to 16-bit range.
return value;
}
#endif // DEVICE_ANALOGIN

105
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/crypto/cy_crypto.h
View File

@ -7,7 +7,7 @@
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -35,14 +35,14 @@
* \section group_crypto_overview Overview * \section group_crypto_overview Overview
* The Crypto driver uses a client-server architecture. * The Crypto driver uses a client-server architecture.
* *
* Firmware initializes and starts the Crypto server. The server runs only on the * Firmware initializes and starts the Crypto server. The server can run on
* CM0+ core, and works with the Crypto hardware. The Crypto server is implemented * either core and works with the Crypto hardware. The Crypto server is
* as a secure block. It performs all cryptographic operations for the client. * implemented as a secure block. It performs all cryptographic operations for
* Access to the server is through the Inter Process Communication (IPC) driver. * the client. Access to the server is through the Inter Process Communication
* Direct access is not allowed. * (IPC) driver. Direct access is not allowed.
* *
* The Crypto client can run on either core. Firmware initializes and starts the * The Crypto client can run on either core too. Firmware initializes and starts
* client. The firmware then provides the configuration data required for the * the client. The firmware then provides the configuration data required for the
* desired cryptographic technique, and requests that the server run the * desired cryptographic technique, and requests that the server run the
* cryptographic operation. * cryptographic operation.
* *
@ -152,13 +152,13 @@
* </tr> * </tr>
* </table> * </table>
* *
* On the CM0+, the error, release, and notify interrupts are assigned to * On the CM0+, the notify, release and error interrupts are assigned to
* NVIC IRQn 28-30 respectively. Do not modify these values. * NVIC IRQn <b>2, 30, 31</b> respectively. Do not modify these values.
* See System Interrupt (SysInt) for background on CM0+ interrupts. * See System Interrupt (SysInt) for background on CM0+ interrupts.
* *
* \section group_crypto_server_init Server Initialization * \section group_crypto_server_init Server Initialization
* *
* Use \ref Cy_Crypto_Server_Start. This call must be made from the CM0+ core only. * Use \ref Cy_Crypto_Server_Start.
* Provide the configuration parameters (cy_stc_crypto_config_t) and a pointer * Provide the configuration parameters (cy_stc_crypto_config_t) and a pointer
* to the server context (cy_stc_crypto_server_context_t). * to the server context (cy_stc_crypto_server_context_t).
* Do not fill in the values for the context structure. * Do not fill in the values for the context structure.
@ -266,6 +266,11 @@
* mandatory, and represent the data for either the public or private key as * mandatory, and represent the data for either the public or private key as
* appropriate. * appropriate.
* *
* \note The <b>modulus</b> and <b>exponent</b> values in the
* \ref cy_stc_crypto_rsa_pub_key_t must be in little-endian order.<br>
* Use the \ref Cy_Crypto_Rsa_InvertEndianness function to convert to or from
* little-endian order.
*
* The remaining fields represent three pre-calculated coefficients that can * The remaining fields represent three pre-calculated coefficients that can
* reduce execution time by up to 5x. The fields are: coefficient for Barrett * reduce execution time by up to 5x. The fields are: coefficient for Barrett
* reduction, binary inverse of the modulus, and the result of * reduction, binary inverse of the modulus, and the result of
@ -447,6 +452,24 @@
* <table class="doxtable"> * <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr> * <tr>
* <td rowspan="2">2.0</td>
* <td>Clarified what parameters must be 4-byte aligned for the functions:
* \ref Cy_Crypto_Aes_Cmac_Run, \ref Cy_Crypto_Sha_Run,
* \ref Cy_Crypto_Hmac_Run, \ref Cy_Crypto_Str_MemCmp,
* \ref Cy_Crypto_Trng_Generate, \ref Cy_Crypto_Des_Run,
* \ref Cy_Crypto_Tdes_Run, \ref Cy_Crypto_Rsa_Proc
* </td>
* <td>Documentation update and clarification</td>
* </tr>
* <tr>
* <td>
* Changed crypto IP power control<br>
* Enhanced Vector Unit functionality for RSA crypto algorithm<br>
* Added support of the single-core devices
* </td>
* <td>New device support</td>
* </tr>
* <tr>
* <td>1.0</td> * <td>1.0</td>
* <td>Initial version</td> * <td>Initial version</td>
* <td></td> * <td></td>
@ -457,21 +480,21 @@
* \defgroup group_crypto_common Configuration * \defgroup group_crypto_common Configuration
* \{ * \{
* \defgroup group_crypto_config_macros Macros * \defgroup group_crypto_config_macros Macros
* \defgroup group_crypto_config_structure Structure * \defgroup group_crypto_config_structure Data Structures
* \} * \}
* *
* \defgroup group_crypto_client Crypto Client * \defgroup group_crypto_client Crypto Client
* \{ * \{
* \defgroup group_crypto_macros Macros * \defgroup group_crypto_macros Macros
* \defgroup group_crypto_enums Enumerated Types
* \defgroup group_crypto_cli_data_structures Data Structures
* \defgroup group_crypto_cli_functions Functions * \defgroup group_crypto_cli_functions Functions
* \defgroup group_crypto_cli_data_structures Data Structures
* \defgroup group_crypto_enums Enumerated Types
* \} * \}
* *
* \defgroup group_crypto_server Crypto Server * \defgroup group_crypto_server Crypto Server
* \{ * \{
* \defgroup group_crypto_srv_data_structures Data Structures
* \defgroup group_crypto_srv_functions Functions * \defgroup group_crypto_srv_functions Functions
* \defgroup group_crypto_srv_data_structures Data Structures
* \} * \}
*/ */
@ -846,19 +869,19 @@ cy_en_crypto_status_t Cy_Crypto_Aes_Ctr_Run(cy_en_crypto_dir_mode_t dirMode,
* the context structure when making this function call. * the context structure when making this function call.
* *
* \param src * \param src
* The pointer to a source plain text. Must be 4-Byte aligned. * The pointer to a source plain text. Must be 4-byte aligned.
* *
* \param srcSize * \param srcSize
* The size of a source plain text. * The size of a source plain text.
* *
* \param key * \param key
* The pointer to the encryption key. * The pointer to the encryption key. Must be 4-byte aligned.
* *
* \param keyLength * \param keyLength
* \ref cy_en_crypto_aes_key_length_t * \ref cy_en_crypto_aes_key_length_t
* *
* \param cmacPtr * \param cmacPtr
* The pointer to the calculated CMAC. * The pointer to the calculated CMAC. Must be 4-byte aligned.
* *
* \param cfContext * \param cfContext
* The pointer to the \ref cy_stc_crypto_context_aes_t structure that stores all * The pointer to the \ref cy_stc_crypto_context_aes_t structure that stores all
@ -892,12 +915,13 @@ cy_en_crypto_status_t Cy_Crypto_Aes_Cmac_Run(uint32_t *src,
* *
* \param message * \param message
* The pointer to a message whose hash value is being computed. * The pointer to a message whose hash value is being computed.
* Must be 4-byte aligned.
* *
* \param messageSize * \param messageSize
* The size of a message. * The size of a message.
* *
* \param digest * \param digest
* The pointer to the hash digest. * The pointer to the hash digest. Must be 4-byte aligned.
* *
* \param cfContext * \param cfContext
* the pointer to the \ref cy_stc_crypto_context_sha_t structure that stores all * the pointer to the \ref cy_stc_crypto_context_sha_t structure that stores all
@ -926,16 +950,17 @@ cy_en_crypto_status_t Cy_Crypto_Sha_Run(uint32_t *message,
* preparation, calculation, and finalization steps. * preparation, calculation, and finalization steps.
* *
* \param hmac * \param hmac
* The pointer to the calculated HMAC. * The pointer to the calculated HMAC. Must be 4-byte aligned.
* *
* \param message * \param message
* The pointer to a message whose hash value is being computed. * The pointer to a message whose hash value is being computed.
* Must be 4-byte aligned.
* *
* \param messageSize * \param messageSize
* The size of a message. * The size of a message.
* *
* \param key * \param key
* The pointer to the key. * The pointer to the key. Must be 4-byte aligned.
* *
* \param keyLength * \param keyLength
* The length of the key. * The length of the key.
@ -965,7 +990,7 @@ cy_en_crypto_status_t Cy_Crypto_Hmac_Run(uint32_t *hmac,
* Function Name: Cy_Crypto_Str_MemCpy * Function Name: Cy_Crypto_Str_MemCpy
****************************************************************************//** ****************************************************************************//**
* *
* This function copy memory block. It operates data in the user SRAM and doesn't * This function copies a memory block. It operates on data in the user SRAM and doesn't
* use Crypto internal SRAM. * use Crypto internal SRAM.
* *
* \note Memory blocks should not overlap. * \note Memory blocks should not overlap.
@ -999,7 +1024,7 @@ cy_en_crypto_status_t Cy_Crypto_Str_MemCpy(void *dst,
* Function Name: Cy_Crypto_Str_MemSet * Function Name: Cy_Crypto_Str_MemSet
****************************************************************************//** ****************************************************************************//**
* *
* This function sets the memory block. It operates data in the user SRAM and * This function sets the memory block. It operates on data in the user SRAM and
* doesn't use Crypto internal SRAM. * doesn't use Crypto internal SRAM.
* *
* There is no alignment restriction. * There is no alignment restriction.
@ -1031,7 +1056,7 @@ cy_en_crypto_status_t Cy_Crypto_Str_MemSet(void *dst,
* Function Name: Cy_Crypto_Str_MemCmp * Function Name: Cy_Crypto_Str_MemCmp
****************************************************************************//** ****************************************************************************//**
* *
* This function compares memory blocks. It operates data in the user SRAM and * This function compares memory blocks. It operates on data in the user SRAM and
* doesn't use Crypto internal SRAM. * doesn't use Crypto internal SRAM.
* *
* There is no alignment restriction. * There is no alignment restriction.
@ -1047,7 +1072,7 @@ cy_en_crypto_status_t Cy_Crypto_Str_MemSet(void *dst,
* The size in bytes of the compare operation. Maximum size is 65535 Bytes. * The size in bytes of the compare operation. Maximum size is 65535 Bytes.
* *
* \param resultPtr * \param resultPtr
* The pointer to the result of compare: * The pointer to the result of compare (must be 4-byte aligned):
* - 0 - if Source 1 equal Source 2 * - 0 - if Source 1 equal Source 2
* - 1 - if Source 1 not equal Source 2 * - 1 - if Source 1 not equal Source 2
* *
@ -1069,7 +1094,7 @@ cy_en_crypto_status_t Cy_Crypto_Str_MemCmp(void const *src0,
* Function Name: Crypto_Str_MemXor * Function Name: Crypto_Str_MemXor
****************************************************************************//** ****************************************************************************//**
* *
* This function calculate XOR of two memory blocks. It operates data in the user * This function calculates the XOR of two memory blocks. It operates on data in the user
* SRAM and doesn't use Crypto internal SRAM. * SRAM and doesn't use Crypto internal SRAM.
* *
* \note Memory structures should not overlap. * \note Memory structures should not overlap.
@ -1373,7 +1398,7 @@ cy_en_crypto_status_t Cy_Crypto_Crc_Init(uint32_t polynomial,
* The size of a message in bytes. * The size of a message in bytes.
* *
* \param crc * \param crc
* The pointer to a computed CRC value. * The pointer to a computed CRC value. Must be 4-byte aligned.
* *
* \param lfsrInitState * \param lfsrInitState
* The initial state of the LFSR. * The initial state of the LFSR.
@ -1410,7 +1435,7 @@ cy_en_crypto_status_t Cy_Crypto_Crc_Run(void *data,
* The maximum length of a random number, in the range [0, 32] bits. * The maximum length of a random number, in the range [0, 32] bits.
* *
* \param randomNum * \param randomNum
* The pointer to a generated true random number. * The pointer to a generated true random number. Must be 4-byte aligned.
* *
* \param cfContext * \param cfContext
* The pointer to the \ref cy_stc_crypto_context_trng_t structure that stores * The pointer to the \ref cy_stc_crypto_context_trng_t structure that stores
@ -1442,13 +1467,13 @@ cy_en_crypto_status_t Cy_Crypto_Trng_Generate(uint32_t GAROPol,
* Can be CRYPTO_ENCRYPT or CRYPTO_DECRYPT (\ref cy_en_crypto_dir_mode_t) * Can be CRYPTO_ENCRYPT or CRYPTO_DECRYPT (\ref cy_en_crypto_dir_mode_t)
* *
* \param key * \param key
* The pointer to the encryption/decryption key. * The pointer to the encryption/decryption key. Must be 4-byte aligned.
* *
* \param srcBlock * \param srcBlock
* The pointer to a source block. Must be 4-byte aligned. * The pointer to a source block. Must be 4-byte aligned. Must be 4-byte aligned.
* *
* \param dstBlock * \param dstBlock
* The pointer to a destination cipher block. * The pointer to a destination cipher block. Must be 4-byte aligned.
* *
* \param cfContext * \param cfContext
* The pointer to the cy_stc_crypto_context_des_t structure that stores * The pointer to the cy_stc_crypto_context_des_t structure that stores
@ -1478,13 +1503,13 @@ cy_en_crypto_status_t Cy_Crypto_Des_Run(cy_en_crypto_dir_mode_t dirMode,
* Can be CRYPTO_ENCRYPT or CRYPTO_DECRYPT (\ref cy_en_crypto_dir_mode_t) * Can be CRYPTO_ENCRYPT or CRYPTO_DECRYPT (\ref cy_en_crypto_dir_mode_t)
* *
* \param key * \param key
* The pointer to the encryption/decryption key. * The pointer to the encryption/decryption key. Must be 4-byte aligned.
* *
* \param srcBlock * \param srcBlock
* The pointer to a source block. Must be 4-vyte aligned. * The pointer to a source block. Must be 4-vyte aligned. Must be 4-byte aligned.
* *
* \param dstBlock * \param dstBlock
* The pointer to a destination cipher block. * The pointer to a destination cipher block. Must be 4-byte aligned.
* *
* \param cfContext * \param cfContext
* The pointer to the cy_stc_crypto_context_des_t structure that stores * The pointer to the cy_stc_crypto_context_des_t structure that stores
@ -1525,10 +1550,12 @@ cy_en_crypto_status_t Cy_Crypto_Tdes_Run(cy_en_crypto_dir_mode_t dirMode,
* *
* Returns the processed value and a success value. * Returns the processed value and a success value.
* *
* \note Incoming message and result processed message are little-endianess big * \note <b>Incoming message</b> and <b>result processed message</b> must be in
* integer values. To convert it from (to) binary (octet) strings use the \ref * little-endian order.<br>
* Cy_Crypto_Rsa_InvertEndianness function. * The <b>modulus</b> and <b>exponent</b> values in the \ref cy_stc_crypto_rsa_pub_key_t
* * must also be in little-endian order.<br>
* Use \ref Cy_Crypto_Rsa_InvertEndianness function to convert to or from
* little-endian order.
* *
* \param pubKey * \param pubKey
* The pointer to the \ref cy_stc_crypto_rsa_pub_key_t structure that stores * The pointer to the \ref cy_stc_crypto_rsa_pub_key_t structure that stores
@ -1541,7 +1568,7 @@ cy_en_crypto_status_t Cy_Crypto_Tdes_Run(cy_en_crypto_dir_mode_t dirMode,
* The length of the message to be processed. * The length of the message to be processed.
* *
* \param processedMessage * \param processedMessage
* The pointer to processed message. * The pointer to processed message. Must be 4-byte aligned.
* *
* \param cfContext * \param cfContext
* The pointer to the \ref cy_stc_crypto_context_rsa_t structure that stores * The pointer to the \ref cy_stc_crypto_context_rsa_t structure that stores

16
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_common.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/crypto/cy_crypto_common.h
View File

@ -8,7 +8,7 @@
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -64,13 +64,13 @@
/** Defines the Crypto AES block size (in bytes) */ /** Defines the Crypto AES block size (in bytes) */
#define CY_CRYPTO_AES_BLOCK_SIZE (16u) #define CY_CRYPTO_AES_BLOCK_SIZE (16u)
/** Defines the Crypto AES key maximum size (in bytes) */ /** Defines the Crypto AES_128 key maximum size (in bytes) */
#define CY_CRYPTO_AES_128_KEY_SIZE (16u) #define CY_CRYPTO_AES_128_KEY_SIZE (16u)
/** Defines the Crypto AES key maximum size (in bytes) */ /** Defines the Crypto AES_192 key maximum size (in bytes) */
#define CY_CRYPTO_AES_192_KEY_SIZE (24u) #define CY_CRYPTO_AES_192_KEY_SIZE (24u)
/** Defines the Crypto AES key maximum size (in bytes) */ /** Defines the Crypto AES_256 key maximum size (in bytes) */
#define CY_CRYPTO_AES_256_KEY_SIZE (32u) #define CY_CRYPTO_AES_256_KEY_SIZE (32u)
/** Defines size of the AES block, in four-byte words */ /** Defines size of the AES block, in four-byte words */
@ -157,7 +157,7 @@ typedef struct
Note: In the second case user should process data separately and Note: In the second case user should process data separately and
clear interrupt by calling \ref Cy_Crypto_Server_Process. clear interrupt by calling \ref Cy_Crypto_Server_Process.
This model is used in the This model is used in the
multitasking environment (e.g. CyOS). */ multitasking environment. */
cy_israddress userGetDataHandler; cy_israddress userGetDataHandler;
/** Server-side user IRQ handler function, called when a Crypto hardware /** Server-side user IRQ handler function, called when a Crypto hardware
@ -200,6 +200,12 @@ typedef struct
* *
* Other fields are accelerating coefficients and can be calculated by * Other fields are accelerating coefficients and can be calculated by
* \ref Cy_Crypto_Rsa_CalcCoefs. * \ref Cy_Crypto_Rsa_CalcCoefs.
*
* \note The <b>modulus</b> and <b>exponent</b> values in the
* \ref cy_stc_crypto_rsa_pub_key_t must also be in little-endian order.<br>
* Use \ref Cy_Crypto_Rsa_InvertEndianness function to convert to or from
* little-endian order.
*
*/ */
typedef struct typedef struct
{ {

2
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_config.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/crypto/cy_crypto_config.c
View File

@ -7,7 +7,7 @@
* required to configure the crypto driver by user. * required to configure the crypto driver by user.
* *
******************************************************************************** ********************************************************************************
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.

2
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_config.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/crypto/cy_crypto_config.h
View File

@ -7,7 +7,7 @@
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.

2
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_server.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/crypto/cy_crypto_server.h
View File

@ -8,7 +8,7 @@
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.

350
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctb/cy_ctb.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctb/cy_ctb.c
View File

@ -7,7 +7,7 @@
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -138,17 +138,28 @@ const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5 =
* Function Name: Cy_CTB_Init * Function Name: Cy_CTB_Init
****************************************************************************//** ****************************************************************************//**
* *
* Initializes or restores the CTB and both Opamps according to the * Initialize or restore the CTB and both opamps according to the
* provided settings. Parameters are usually set only once, at initialization. * provided settings. Parameters are usually set only once, at initialization.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param config * \param config
* Pointer to structure containing configuration data * Pointer to structure containing configuration data for entire CTB
* *
* \return cy_en_ctb_status_t * \return
* Status of initialization, CY_CTB_SUCCESS or CY_CTB_BAD_PARAM * Status of initialization, \ref CY_CTB_SUCCESS or \ref CY_CTB_BAD_PARAM
*
* \funcusage
*
* The following code snippet configures Opamp0 as a comparator
* and Opamp1 as an opamp follower with 10x drive. The terminals
* are routed to external pins by closing the switches shown.
*
* \image html ctb_init_funcusage.png
* \image latex ctb_init_funcusage.png
*
* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_CTBINIT
* *
*******************************************************************************/ *******************************************************************************/
cy_en_ctb_status_t Cy_CTB_Init(CTBM_Type *base, const cy_stc_ctb_config_t *config) cy_en_ctb_status_t Cy_CTB_Init(CTBM_Type *base, const cy_stc_ctb_config_t *config)
@ -221,11 +232,6 @@ cy_en_ctb_status_t Cy_CTB_Init(CTBM_Type *base, const cy_stc_ctb_config_t *confi
base->CTD_SW = config->ctdSwitchCtrl; base->CTD_SW = config->ctdSwitchCtrl;
} }
if (config->enable)
{
Cy_CTB_Enable(base);
}
result = CY_CTB_SUCCESS; result = CY_CTB_SUCCESS;
} }
@ -236,24 +242,28 @@ cy_en_ctb_status_t Cy_CTB_Init(CTBM_Type *base, const cy_stc_ctb_config_t *confi
* Function Name: Cy_CTB_OpampInit * Function Name: Cy_CTB_OpampInit
****************************************************************************//** ****************************************************************************//**
* *
* Initializes each Opamp separately without impacting analog routing. * Initialize each opamp separately without impacting analog routing.
* Intended for use by automatic analog routing and configuration tools * Intended for use by automatic analog routing and configuration tools
* to configure each Opamp without having to integrate the settings with * to configure each opamp without having to integrate the settings with
* those of the other Opamp first. * those of the other opamp first.
* *
* Can also be used to configure both Opamps to have the same settings. * Can also be used to configure both opamps to have the same settings.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param opampNum * \param opampNum
* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
* *
* \param config * \param config
* Pointer to structure containing configuration data * Pointer to structure containing configuration data
* *
* \return cy_en_ctb_status_t * \return
* Status of initialization, CY_CTB_SUCCESS or CY_CTB_BAD_PARAM * Status of initialization, \ref CY_CTB_SUCCESS or \ref CY_CTB_BAD_PARAM
*
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_OPAMPINIT
* *
*******************************************************************************/ *******************************************************************************/
cy_en_ctb_status_t Cy_CTB_OpampInit(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, const cy_stc_ctb_opamp_config_t *config) cy_en_ctb_status_t Cy_CTB_OpampInit(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, const cy_stc_ctb_opamp_config_t *config)
@ -282,7 +292,7 @@ cy_en_ctb_status_t Cy_CTB_OpampInit(CTBM_Type *base, cy_en_ctb_opamp_sel_t opamp
base->CTB_CTRL = (uint32_t) config->deepSleep; base->CTB_CTRL = (uint32_t) config->deepSleep;
/* The two Opamp control registers are symmetrical */ /* The two opamp control registers are symmetrical */
oaResCtrl = (uint32_t) config->oaPower \ oaResCtrl = (uint32_t) config->oaPower \
| (uint32_t) config->oaMode \ | (uint32_t) config->oaMode \
| (uint32_t) config->oaPump \ | (uint32_t) config->oaPump \
@ -297,7 +307,7 @@ cy_en_ctb_status_t Cy_CTB_OpampInit(CTBM_Type *base, cy_en_ctb_opamp_sel_t opamp
base->OA_RES0_CTRL = oaResCtrl; base->OA_RES0_CTRL = oaResCtrl;
base->OA0_COMP_TRIM = (uint32_t) ((config->oaMode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); base->OA0_COMP_TRIM = (uint32_t) ((config->oaMode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
/* The INTR_MASK register is shared between the two Opamps */ /* The INTR_MASK register is shared between the two opamps */
base->INTR_MASK |= (config->oaCompIntrEn ? CTBM_INTR_MASK_COMP0_MASK_Msk : CY_CTB_DEINIT); base->INTR_MASK |= (config->oaCompIntrEn ? CTBM_INTR_MASK_COMP0_MASK_Msk : CY_CTB_DEINIT);
} }
@ -306,16 +316,10 @@ cy_en_ctb_status_t Cy_CTB_OpampInit(CTBM_Type *base, cy_en_ctb_opamp_sel_t opamp
base->OA_RES1_CTRL = oaResCtrl; base->OA_RES1_CTRL = oaResCtrl;
base->OA1_COMP_TRIM = (uint32_t) ((config->oaMode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); base->OA1_COMP_TRIM = (uint32_t) ((config->oaMode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
/* The INTR_MASK register is shared between the two Opamps */ /* The INTR_MASK register is shared between the two opamps */
base->INTR_MASK |= (config->oaCompIntrEn ? CTBM_INTR_MASK_COMP1_MASK_Msk : CY_CTB_DEINIT); base->INTR_MASK |= (config->oaCompIntrEn ? CTBM_INTR_MASK_COMP1_MASK_Msk : CY_CTB_DEINIT);
} }
if (config->enable)
{
Cy_CTB_Enable(base);
}
result = CY_CTB_SUCCESS; result = CY_CTB_SUCCESS;
} }
@ -335,8 +339,8 @@ cy_en_ctb_status_t Cy_CTB_OpampInit(CTBM_Type *base, cy_en_ctb_opamp_sel_t opamp
* If true, all analog routing switches are reset to their default state. * If true, all analog routing switches are reset to their default state.
* If false, analog switch registers are untouched. * If false, analog switch registers are untouched.
* *
* \return cy_en_ctb_status_t * \return
* Status of initialization, CY_CTB_SUCCESS or CY_CTB_BAD_PARAM * Status of initialization, \ref CY_CTB_SUCCESS or \ref CY_CTB_BAD_PARAM
* *
*******************************************************************************/ *******************************************************************************/
cy_en_ctb_status_t Cy_CTB_DeInit(CTBM_Type *base, bool deInitRouting) cy_en_ctb_status_t Cy_CTB_DeInit(CTBM_Type *base, bool deInitRouting)
@ -373,20 +377,24 @@ cy_en_ctb_status_t Cy_CTB_DeInit(CTBM_Type *base, bool deInitRouting)
* Function Name: Cy_CTB_FastInit * Function Name: Cy_CTB_FastInit
****************************************************************************//** ****************************************************************************//**
* *
* Initializes each Opamp of the CTB to one of the common use modes. * Initialize each opamp of the CTB to one of the common use modes.
* These provide a quick and easy method of configuring the CTB when using
* the PDL driver for device configuration. Only routing switches required for
* the selected mode are configured, leaving final input and output connections
* to the user. Additional use modes are provided. These correspond with VDAC
* driver modes to support easy configuration of VDAC output buffer and input
* reference buffer options when used with the VDAC PDL driver.
* *
* Other configuration options are set to: * This function provides a quick and easy method of configuring the CTB
* - .oaPump = CY_CTB_PUMP_ENABLE * using pre-defined configurations.
* - .oaCompEdge = CY_CTB_COMP_EDGE_BOTH * Only routing switches required for the selected mode are configured, leaving final input and output connections
* - .oaCompLevel = CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE * to the user.
* - .oaCompBypass = CY_CTB_COMP_BYPASS_SYNC * Additional use modes that relate to the \ref group_ctdac "CTDAC"
* - .oaCompHyst = CY_CTB_COMP_HYST_10MV * are provided to support easy configuration of the CTDAC output buffer and input
* reference buffer.
*
* The fast configuration structures define the opamp power, mode, and routing.
* This function sets the other configuration options of the CTB to:
* - .deepSleep = CY_CTB_DEEPSLEEP_DISABLE
* - .oaPump = \ref CY_CTB_PUMP_ENABLE
* - .oaCompEdge = \ref CY_CTB_COMP_EDGE_BOTH
* - .oaCompLevel = \ref CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL
* - .oaCompBypass = \ref CY_CTB_COMP_BYPASS_SYNC
* - .oaCompHyst = \ref CY_CTB_COMP_HYST_10MV
* - .oaCompIntrEn = true * - .oaCompIntrEn = true
* \param base * \param base
@ -394,7 +402,7 @@ cy_en_ctb_status_t Cy_CTB_DeInit(CTBM_Type *base, bool deInitRouting)
* *
* \param config0 * \param config0
* Pointer to structure containing configuration data for quick initialization * Pointer to structure containing configuration data for quick initialization
* of Opamp0. Use one of the provided structures or define your own. * of Opamp0. Defined your own or use one of the provided structures:
* - \ref Cy_CTB_Fast_Opamp0_Unused * - \ref Cy_CTB_Fast_Opamp0_Unused
* - \ref Cy_CTB_Fast_Opamp0_Comp * - \ref Cy_CTB_Fast_Opamp0_Comp
* - \ref Cy_CTB_Fast_Opamp0_Opamp1x * - \ref Cy_CTB_Fast_Opamp0_Opamp1x
@ -405,7 +413,7 @@ cy_en_ctb_status_t Cy_CTB_DeInit(CTBM_Type *base, bool deInitRouting)
* *
* \param config1 * \param config1
* Pointer to structure containing configuration data for quick initialization * Pointer to structure containing configuration data for quick initialization
* of Opamp1. Use one of the provided structures or define your own. * of Opamp1. Defined your own or use one of the provided structures:
* - \ref Cy_CTB_Fast_Opamp1_Unused * - \ref Cy_CTB_Fast_Opamp1_Unused
* - \ref Cy_CTB_Fast_Opamp1_Comp * - \ref Cy_CTB_Fast_Opamp1_Comp
* - \ref Cy_CTB_Fast_Opamp1_Opamp1x * - \ref Cy_CTB_Fast_Opamp1_Opamp1x
@ -414,8 +422,12 @@ cy_en_ctb_status_t Cy_CTB_DeInit(CTBM_Type *base, bool deInitRouting)
* - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref * - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref
* - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5 * - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5
* *
* \return cy_en_ctb_status_t * \return
* Status of initialization, CY_CTB_SUCCESS or CY_CTB_BAD_PARAM * Status of initialization, \ref CY_CTB_SUCCESS or \ref CY_CTB_BAD_PARAM
*
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_FASTINIT
* *
*******************************************************************************/ *******************************************************************************/
cy_en_ctb_status_t Cy_CTB_FastInit(CTBM_Type *base, const cy_stc_ctb_fast_config_oa0_t *config0, const cy_stc_ctb_fast_config_oa1_t *config1) cy_en_ctb_status_t Cy_CTB_FastInit(CTBM_Type *base, const cy_stc_ctb_fast_config_oa0_t *config0, const cy_stc_ctb_fast_config_oa1_t *config1)
@ -450,7 +462,7 @@ cy_en_ctb_status_t Cy_CTB_FastInit(CTBM_Type *base, const cy_stc_ctb_fast_config
| (uint32_t) config0->oa0Mode \ | (uint32_t) config0->oa0Mode \
| (uint32_t) CY_CTB_PUMP_ENABLE \ | (uint32_t) CY_CTB_PUMP_ENABLE \
| (uint32_t) CY_CTB_COMP_EDGE_BOTH \ | (uint32_t) CY_CTB_COMP_EDGE_BOTH \
| (uint32_t) CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE \ | (uint32_t) CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL \
| (uint32_t) CY_CTB_COMP_BYPASS_SYNC \ | (uint32_t) CY_CTB_COMP_BYPASS_SYNC \
| (uint32_t) CY_CTB_COMP_HYST_10MV \ | (uint32_t) CY_CTB_COMP_HYST_10MV \
| ((CY_CTB_MODE_OPAMP1X == config0->oa0Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE); | ((CY_CTB_MODE_OPAMP1X == config0->oa0Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE);
@ -459,7 +471,7 @@ cy_en_ctb_status_t Cy_CTB_FastInit(CTBM_Type *base, const cy_stc_ctb_fast_config
| (uint32_t) config1->oa1Mode \ | (uint32_t) config1->oa1Mode \
| (uint32_t) CY_CTB_PUMP_ENABLE \ | (uint32_t) CY_CTB_PUMP_ENABLE \
| (uint32_t) CY_CTB_COMP_EDGE_BOTH \ | (uint32_t) CY_CTB_COMP_EDGE_BOTH \
| (uint32_t) CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE \ | (uint32_t) CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL \
| (uint32_t) CY_CTB_COMP_BYPASS_SYNC \ | (uint32_t) CY_CTB_COMP_BYPASS_SYNC \
| (uint32_t) CY_CTB_COMP_HYST_10MV \ | (uint32_t) CY_CTB_COMP_HYST_10MV \
| ((CY_CTB_MODE_OPAMP1X == config1->oa1Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE); | ((CY_CTB_MODE_OPAMP1X == config1->oa1Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE);
@ -483,9 +495,9 @@ cy_en_ctb_status_t Cy_CTB_FastInit(CTBM_Type *base, const cy_stc_ctb_fast_config
* Function Name: Cy_CTB_SetCurrentMode * Function Name: Cy_CTB_SetCurrentMode
****************************************************************************//** ****************************************************************************//**
* *
* High level API function for configuring the current modes of the Opamps. * High level function to configure the current modes of the opamps.
* This API configures all Opamps of the CTB to the same current mode. * This function configures all opamps of the CTB to the same current mode.
* These modes are differentiated by the IPTAT current level, the Opamp * These modes are differentiated by the reference current level, the opamp
* input range, and the Deep Sleep mode operation. * input range, and the Deep Sleep mode operation.
* *
* - The reference current level is set using \ref Cy_CTB_SetIptatLevel * - The reference current level is set using \ref Cy_CTB_SetIptatLevel
@ -494,13 +506,14 @@ cy_en_ctb_status_t Cy_CTB_FastInit(CTBM_Type *base, const cy_stc_ctb_fast_config
* \ref Cy_SysAnalog_SetDeepSleepMode is called with CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF. * \ref Cy_SysAnalog_SetDeepSleepMode is called with CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF.
* - When 100 nA current level is used, * - When 100 nA current level is used,
* - \ref Cy_CTB_EnableRedirect is called to route the AREF IPTAT reference * - \ref Cy_CTB_EnableRedirect is called to route the AREF IPTAT reference
* to the Opamp IZTAT and disable the Opamps IPTAT. * to the opamp IZTAT and disable the opamps IPTAT.
* - The IPTAT generator is enabled in Deep Sleep. That is, * - The IPTAT generator is enabled in Deep Sleep. That is,
* \ref Cy_SysAnalog_SetDeepSleepMode is called with CY_SYSANALOG_DEEPSLEEP_IPTAT_2 * \ref Cy_SysAnalog_SetDeepSleepMode is called with CY_SYSANALOG_DEEPSLEEP_IPTAT_2
* unless it is already configured for CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF. * unless it is already configured for CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF.
* *
* Note that the IPTAT level is a chip wide configuration so multiple * \note
* Opamps cannot operate at different IPTAT levels. * The IPTAT level is a chip wide configuration so multiple
* opamps cannot operate at different IPTAT levels.
* When calling \ref Cy_CTB_SetCurrentMode for a CTB instance on the device, * When calling \ref Cy_CTB_SetCurrentMode for a CTB instance on the device,
* it should be called for all other CTB instances as well. * it should be called for all other CTB instances as well.
* *
@ -512,35 +525,40 @@ cy_en_ctb_status_t Cy_CTB_FastInit(CTBM_Type *base, const cy_stc_ctb_fast_config
* <th>Deep Sleep Operation</th> * <th>Deep Sleep Operation</th>
* </tr> * </tr>
* <tr> * <tr>
* <td>CY_CTB_CURRENT_HIGH_ACTIVE</td> * <td>\ref CY_CTB_CURRENT_HIGH_ACTIVE</td>
* <td>1 uA</td> * <td>1 uA</td>
* <td>Rail-to-Rail (charge pump enabled)</td> * <td>Rail-to-Rail (charge pump enabled)</td>
* <td>Disabled in Deep Sleep</td> * <td>Disabled in Deep Sleep</td>
* </tr> * </tr>
* <tr> * <tr>
* <td>CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP</td> * <td>\ref CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP</td>
* <td>1 uA</td> * <td>1 uA</td>
* <td>0 - VDDA-1.5 V (charge pump disabled)</td> * <td>0 - VDDA-1.5 V (charge pump disabled)</td>
* <td>Enabled in Deep Sleep</td> * <td>Enabled in Deep Sleep</td>
* </tr> * </tr>
* <tr> * <tr>
* <td>CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP</td> * <td>\ref CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP</td>
* <td>100 nA</td> * <td>100 nA</td>
* <td>0 - VDDA-1.5 V (charge pump disabled)</td> * <td>0 - VDDA-1.5 V (charge pump disabled)</td>
* <td>Enabled in Deep Sleep</td> * <td>Enabled in Deep Sleep</td>
* </tr> * </tr>
* </table> * </table>
* *
* NOTE: The output range of the Opamp is 0.2 V to VDDA-0.2 V (depending on output load). * \note
* The output range of the opamp is 0.2 V to VDDA - 0.2 V (depending on output load).
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param currentMode * \param currentMode
* Enable or disable CTB in Deep Sleep. * Current mode selection
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_CURRENT_MODE
*
*******************************************************************************/ *******************************************************************************/
void Cy_CTB_SetCurrentMode(CTBM_Type *base, cy_en_ctb_current_mode_t currentMode) void Cy_CTB_SetCurrentMode(CTBM_Type *base, cy_en_ctb_current_mode_t currentMode)
{ {
@ -558,7 +576,7 @@ void Cy_CTB_SetCurrentMode(CTBM_Type *base, cy_en_ctb_current_mode_t currentMode
Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_NORMAL); Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_NORMAL);
Cy_CTB_DisableRedirect(); Cy_CTB_DisableRedirect();
/* Disable Deep Sleep mode for the CTB - not Opamp specific */ /* Disable Deep Sleep mode for the CTB - not opamp specific */
Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_DISABLE); Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_DISABLE);
/* Enable Opamp0 pump */ /* Enable Opamp0 pump */
@ -577,7 +595,7 @@ void Cy_CTB_SetCurrentMode(CTBM_Type *base, cy_en_ctb_current_mode_t currentMode
Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_NORMAL); Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_NORMAL);
Cy_CTB_DisableRedirect(); Cy_CTB_DisableRedirect();
/* Enable Deep Sleep mode for the CTB - not Opamp specific */ /* Enable Deep Sleep mode for the CTB - not opamp specific */
Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_ENABLE); Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_ENABLE);
/* Disable Opamp0 pump */ /* Disable Opamp0 pump */
@ -590,7 +608,7 @@ void Cy_CTB_SetCurrentMode(CTBM_Type *base, cy_en_ctb_current_mode_t currentMode
case CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP: case CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP:
default: default:
/* The AREF IPTAT output for the Opamps must be enabled in Deep Sleep. /* The AREF IPTAT output for the opamps must be enabled in Deep Sleep.
* This means a minimum Deep Sleep mode setting of CY_SYSANALOG_DEEPSLEEP_IPTAT_2. */ * This means a minimum Deep Sleep mode setting of CY_SYSANALOG_DEEPSLEEP_IPTAT_2. */
arefDeepSleep = Cy_SysAnalog_GetDeepSleepMode(); arefDeepSleep = Cy_SysAnalog_GetDeepSleepMode();
if ((arefDeepSleep == CY_SYSANALOG_DEEPSLEEP_DISABLE) || (arefDeepSleep == CY_SYSANALOG_DEEPSLEEP_IPTAT_1)) if ((arefDeepSleep == CY_SYSANALOG_DEEPSLEEP_DISABLE) || (arefDeepSleep == CY_SYSANALOG_DEEPSLEEP_IPTAT_1))
@ -602,7 +620,7 @@ void Cy_CTB_SetCurrentMode(CTBM_Type *base, cy_en_ctb_current_mode_t currentMode
Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_LOW); Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_LOW);
Cy_CTB_EnableRedirect(); Cy_CTB_EnableRedirect();
/* Enable Deep Sleep mode for the CTB - not Opamp specific */ /* Enable Deep Sleep mode for the CTB - not opamp specific */
Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_ENABLE); Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_ENABLE);
/* Disable Opamp0 pump */ /* Disable Opamp0 pump */
@ -618,27 +636,31 @@ void Cy_CTB_SetCurrentMode(CTBM_Type *base, cy_en_ctb_current_mode_t currentMode
* Function Name: Cy_CTB_SetDeepSleepMode * Function Name: Cy_CTB_SetDeepSleepMode
****************************************************************************//** ****************************************************************************//**
* *
* Sets whether to allow the CTB to continue to stay powered in Deep Sleep mode. * Enable or disable the entire CTB (not per opamp) in Deep Sleep mode.
*
* If enabled, the AREF block must also be enabled for Deep Sleep (see
* \ref Cy_SysAnalog_SetDeepSleepMode).
* Also, if any of the COS, CA0, CHD, CH6, COB, COR, CRS, or CRD switches
* are used in Deep Sleep, the CTDAC must also be enabled for Deep Sleep (see
* \ref Cy_CTDAC_SetDeepSleepMode).
* *
* If enabled, the AREF block must also be enabled for Deep Sleep to provide
* the needed reference currents to the opamps (see \ref Cy_SysAnalog_SetDeepSleepMode).
* Additionally, ensure that only internal CTB switches are used for routing.
* Switches on AMUXBUSA and AMUXBUSB are not enabled in Deep Sleep.
* See the \ref group_ctb_dependencies section for more information. * See the \ref group_ctb_dependencies section for more information.
* *
* Note that in Deep Sleep mode, the charge pump is disabled so the input * \note
* range is reduced to 0 - VDDA-1.5 V. * In Deep Sleep mode, the charge pumps are disabled so the input
* range of the opamps is reduced to 0 V to VDDA - 1.5 V.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param deepSleep * \param deepSleep
* Enable or disable CTB in Deep Sleep. * \ref CY_CTB_DEEPSLEEP_DISABLE or \ref CY_CTB_DEEPSLEEP_ENABLE from
* \ref cy_en_ctb_deep_sleep_t.
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_DEEPSLEEP_MODE
*
*******************************************************************************/ *******************************************************************************/
void Cy_CTB_SetDeepSleepMode(CTBM_Type *base, cy_en_ctb_deep_sleep_t deepSleep) void Cy_CTB_SetDeepSleepMode(CTBM_Type *base, cy_en_ctb_deep_sleep_t deepSleep)
{ {
@ -655,19 +677,23 @@ void Cy_CTB_SetDeepSleepMode(CTBM_Type *base, cy_en_ctb_deep_sleep_t deepSleep)
* Function Name: Cy_CTB_SetOutputMode * Function Name: Cy_CTB_SetOutputMode
****************************************************************************//** ****************************************************************************//**
* *
* Sets the Opamp output mode to 1x drive, 10x drive, or comparator mode. * Set the opamp output mode to 1x drive, 10x drive, or comparator mode.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param opampNum * \param opampNum
* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
* *
* \param mode * \param mode
* Opamp mode selection * Opamp mode selection. Select a value from \ref cy_en_ctb_mode_t.
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_OUTPUT_MODE
*
*******************************************************************************/ *******************************************************************************/
void Cy_CTB_SetOutputMode(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_mode_t mode) void Cy_CTB_SetOutputMode(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_mode_t mode)
{ {
@ -697,24 +723,33 @@ void Cy_CTB_SetOutputMode(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en
* Function Name: Cy_CTB_SetPower * Function Name: Cy_CTB_SetPower
****************************************************************************//** ****************************************************************************//**
* *
* Sets the Opamp power mode to one of three levels to trade off power for * Configure the power level and charge pump for a specific opamp.
* gain bandwidth. Also enable or disable voltage pump to increase input *
* range to supply rails. * At higher power levels, the opamp consumes more current but provides more
* gain bandwidth.
* Enabling the charge pump increases current but provides
* rail-to-rail input range. Disabling the charge pump limits the input range to
* VDDA - 1.5 V.
* See the device datasheet for performance specifications.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param opampNum * \param opampNum
* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
* *
* \param power * \param power
* Power mode selection * Power mode selection. Select a value from \ref cy_en_ctb_power_t.
* *
* \param pump * \param pump
* Enable or disable the charge pump for increased input range * Enable or disable the charge pump. Select a value from \ref cy_en_ctb_pump_t.
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_POWER
*
*******************************************************************************/ *******************************************************************************/
void Cy_CTB_SetPower(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_power_t power, cy_en_ctb_pump_t pump) void Cy_CTB_SetPower(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_power_t power, cy_en_ctb_pump_t pump)
{ {
@ -743,7 +778,7 @@ void Cy_CTB_SetPower(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_
* Function Name: Cy_CTB_DACSampleAndHold * Function Name: Cy_CTB_DACSampleAndHold
****************************************************************************//** ****************************************************************************//**
* *
* Performs sampling and holding of the CTDAC output. * Perform sampling and holding of the CTDAC output.
* To perform a sample or a hold, a preparation step must first be executed to * To perform a sample or a hold, a preparation step must first be executed to
* open the required switches. Because of this, each sample or hold * open the required switches. Because of this, each sample or hold
* requires three function calls: * requires three function calls:
@ -752,22 +787,9 @@ void Cy_CTB_SetPower(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_
* -# Enable or disable the CTDAC output * -# Enable or disable the CTDAC output
* -# Call this function again to perform a sample or hold * -# Call this function again to perform a sample or hold
* *
* For example,
*
* To sample the CTDAC output voltage:
* -# Cy_CTB_DACSampleAndHold(CTBM0, CY_CTB_SH_PREPARE_SAMPLE);
* -# Cy_CTDAC_SetOutputMode(CTDAC0, CY_CTDAC_OUTPUT_VALUE);
* -# Cy_CTB_DACSampleAndHold(CTBM0, CY_CTB_SH_SAMPLE);
* -# Cy_SysLib_DelayUs(10);
*
* It takes 10 us to perform a sample of the CTDAC output to provide * It takes 10 us to perform a sample of the CTDAC output to provide
* time for the capacitor to settle to the new value. * time for the capacitor to settle to the new value.
* *
* To hold the CTDAC output voltage:
* -# Cy_CTB_DACSampleAndHold(CTBM0, CY_CTB_SH_PREPARE_HOLD);
* -# Cy_CTDAC_SetOutputMode(CTDAC0, CY_CTDAC_OUTPUT_HIGHZ);
* -# Cy_CTB_DACSampleAndHold(CTBM0, CY_CTB_SH_HOLD);
*
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
@ -776,6 +798,14 @@ void Cy_CTB_SetPower(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SAMPLE_CODE_SNIPPET
*
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_HOLD_CODE_SNIPPET
*
*******************************************************************************/ *******************************************************************************/
void Cy_CTB_DACSampleAndHold(CTBM_Type *base, cy_en_ctb_sample_hold_mode_t mode) void Cy_CTB_DACSampleAndHold(CTBM_Type *base, cy_en_ctb_sample_hold_mode_t mode)
{ {
@ -815,7 +845,7 @@ void Cy_CTB_DACSampleAndHold(CTBM_Type *base, cy_en_ctb_sample_hold_mode_t mode)
* Function Name: Cy_CTB_OpampSetOffset * Function Name: Cy_CTB_OpampSetOffset
****************************************************************************//** ****************************************************************************//**
* *
* Overrides the CTB opamp offset factory trim. * Override the CTB opamp offset factory trim.
* The trim is a six bit value and the MSB is a direction bit. * The trim is a six bit value and the MSB is a direction bit.
* *
* <table class="doxtable"> * <table class="doxtable">
@ -850,13 +880,17 @@ void Cy_CTB_DACSampleAndHold(CTBM_Type *base, cy_en_ctb_sample_hold_mode_t mode)
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param opampNum * \param opampNum
* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
* *
* \param trim * \param trim
* Trim value from 0 to 63 * Trim value from 0 to 63
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_OFFSET_TRIM
*
*******************************************************************************/ *******************************************************************************/
void Cy_CTB_OpampSetOffset(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim) void Cy_CTB_OpampSetOffset(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim)
{ {
@ -878,16 +912,20 @@ void Cy_CTB_OpampSetOffset(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint
* Function Name: Cy_CTB_OpampGetOffset * Function Name: Cy_CTB_OpampGetOffset
****************************************************************************//** ****************************************************************************//**
* *
* Returns the current CTB Opamp offset trim value. * Return the current CTB opamp offset trim value.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param opampNum * \param opampNum
* CY_CTB_OPAMP_0 or CY_CTB_OPAMP_1 * \ref CY_CTB_OPAMP_0 or \ref CY_CTB_OPAMP_1
* *
* \return Offset trim value * \return Offset trim value
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_GET_OFFSET_TRIM
*
*******************************************************************************/ *******************************************************************************/
uint32_t Cy_CTB_OpampGetOffset(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum) uint32_t Cy_CTB_OpampGetOffset(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum)
{ {
@ -911,8 +949,8 @@ uint32_t Cy_CTB_OpampGetOffset(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opam
* Function Name: Cy_CTB_OpampSetSlope * Function Name: Cy_CTB_OpampSetSlope
****************************************************************************//** ****************************************************************************//**
* *
* Override the CTB Opamp slope factory trim. * Override the CTB opamp slope factory trim.
* The offset of the Opamp will vary across temperature. * The offset of the opamp will vary across temperature.
* This trim compensates for the slope of the offset across temperature. * This trim compensates for the slope of the offset across temperature.
* This compensation uses a bias current from the Analaog Reference block. * This compensation uses a bias current from the Analaog Reference block.
* To disable it, set the trim to 0. * To disable it, set the trim to 0.
@ -951,13 +989,17 @@ uint32_t Cy_CTB_OpampGetOffset(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opam
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param opampNum * \param opampNum
* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
* *
* \param trim * \param trim
* Trim value from 0 to 63 * Trim value from 0 to 63
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_SLOPE_TRIM
*
*******************************************************************************/ *******************************************************************************/
void Cy_CTB_OpampSetSlope(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim) void Cy_CTB_OpampSetSlope(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim)
{ {
@ -979,16 +1021,20 @@ void Cy_CTB_OpampSetSlope(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint3
* Function Name: Cy_CTB_OpampGetSlope * Function Name: Cy_CTB_OpampGetSlope
****************************************************************************//** ****************************************************************************//**
* *
* Returns the current CTB Opamp slope trim value. * Return the CTB opamp slope trim value.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param opampNum * \param opampNum
* CY_CTB_OPAMP_0 or CY_CTB_OPAMP_1 * \ref CY_CTB_OPAMP_0 or \ref CY_CTB_OPAMP_1
* *
* \return Slope trim value * \return Slope trim value
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_GET_SLOPE_TRIM
*
*******************************************************************************/ *******************************************************************************/
uint32_t Cy_CTB_OpampGetSlope(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum) uint32_t Cy_CTB_OpampGetSlope(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum)
{ {
@ -1012,7 +1058,7 @@ uint32_t Cy_CTB_OpampGetSlope(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opamp
* Function Name: Cy_CTB_SetAnalogSwitch * Function Name: Cy_CTB_SetAnalogSwitch
****************************************************************************//** ****************************************************************************//**
* *
* Provides firmware control of the CTB switches. Each call to this function * Provide firmware control of the CTB switches. Each call to this function
* can open a set of switches or close a set of switches in one register. * can open a set of switches or close a set of switches in one register.
* *
* \param base * \param base
@ -1026,18 +1072,17 @@ uint32_t Cy_CTB_OpampGetSlope(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opamp
* The mask of the switches to either open or close. * The mask of the switches to either open or close.
* The switch masks can be found in the following enums: \ref cy_en_ctb_oa0_switches_t, * The switch masks can be found in the following enums: \ref cy_en_ctb_oa0_switches_t,
* \ref cy_en_ctb_oa1_switches_t, and \ref cy_en_ctb_ctd_switches_t. * \ref cy_en_ctb_oa1_switches_t, and \ref cy_en_ctb_ctd_switches_t.
* Use the enum that is consistent with the provided register.
* *
* \param state * \param state
* CY_CTB_SWITCH_OPEN or CY_CTB_SWITCH_CLOSE * \ref CY_CTB_SWITCH_OPEN or \ref CY_CTB_SWITCH_CLOSE
*
* For example, to route the non-inverting input of opamp0 to Pin 0 of the CTB port,
* and the inverting input of opamp0 to Pin 1:
* switchSelect = CY_CTB_SWITCH_OA0_SW;
* switchMask = CY_CTB_SW_OA0_POS_PIN0_MASK | CY_CTB_SW_OA0_NEG_PIN1_MASK;
* state = CY_CTB_SWITCH_CLOSE;
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_ANALOG_SWITCH
*
*******************************************************************************/ *******************************************************************************/
void Cy_CTB_SetAnalogSwitch(CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect, uint32_t switchMask, cy_en_ctb_switch_state_t state) void Cy_CTB_SetAnalogSwitch(CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect, uint32_t switchMask, cy_en_ctb_switch_state_t state)
{ {
@ -1081,7 +1126,7 @@ void Cy_CTB_SetAnalogSwitch(CTBM_Type *base, cy_en_ctb_switch_register_sel_t swi
* Function Name: Cy_CTB_GetAnalogSwitch * Function Name: Cy_CTB_GetAnalogSwitch
****************************************************************************//** ****************************************************************************//**
* *
* Returns the open or closed state of the specified analog switch. * Return the open or closed state of the specified analog switch.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
@ -1090,10 +1135,15 @@ void Cy_CTB_SetAnalogSwitch(CTBM_Type *base, cy_en_ctb_switch_register_sel_t swi
* A value of the enum \ref cy_en_ctb_switch_register_sel_t to select the switch * A value of the enum \ref cy_en_ctb_switch_register_sel_t to select the switch
* register * register
* *
* \return uint32_t * \return
* The state of the switches in the provided register.
* Compare this value to the switch masks in the following enums: * Compare this value to the switch masks in the following enums:
* \ref cy_en_ctb_oa0_switches_t, \ref cy_en_ctb_oa1_switches_t, and \ref cy_en_ctb_ctd_switches_t. * \ref cy_en_ctb_oa0_switches_t, \ref cy_en_ctb_oa1_switches_t, and \ref cy_en_ctb_ctd_switches_t.
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_GET_ANALOG_SWITCH
*
*******************************************************************************/ *******************************************************************************/
uint32_t Cy_CTB_GetAnalogSwitch(const CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect) uint32_t Cy_CTB_GetAnalogSwitch(const CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect)
{ {
@ -1118,41 +1168,18 @@ uint32_t Cy_CTB_GetAnalogSwitch(const CTBM_Type *base, cy_en_ctb_switch_register
return switchRegValue; return switchRegValue;
} }
/*******************************************************************************
* Function Name: Cy_CTB_OpenAllSwitches
****************************************************************************//**
*
* Open all the switches and disable all hardware control of the switches.
* Primarily used as a quick method of reconfiguring all analog connections
* that are sparsely closed.
*
* \param base
* Pointer to structure describing registers
*
* \return None
*
*******************************************************************************/
void Cy_CTB_OpenAllSwitches(CTBM_Type *base)
{
base->OA0_SW_CLEAR = CY_CTB_DEINIT_OA0_SW;
base->OA1_SW_CLEAR = CY_CTB_DEINIT_OA1_SW;
base->CTD_SW_CLEAR = CY_CTB_DEINIT_CTD_SW;
base->CTB_SW_DS_CTRL = CY_CTB_DEINIT;
base->CTB_SW_SQ_CTRL = CY_CTB_DEINIT;
}
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_CTB_CompSetConfig * Function Name: Cy_CTB_CompSetConfig
****************************************************************************//** ****************************************************************************//**
* *
* Configures the CTB comparator for pulse or level output, to bypass clock * Configure the CTB comparator for pulse or level output, to bypass clock
* synchronization, and to enable hysteresis. * synchronization, and to enable hysteresis.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param compNum * \param compNum
* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
* *
* \param level * \param level
* Configure output to produce a pulse or level output signal * Configure output to produce a pulse or level output signal
@ -1165,6 +1192,10 @@ void Cy_CTB_OpenAllSwitches(CTBM_Type *base)
* \return None * \return None
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_COMP_SET_CONFIG
*
*******************************************************************************/ *******************************************************************************/
void Cy_CTB_CompSetConfig(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_level_t level, cy_en_ctb_comp_bypass_t bypass, cy_en_ctb_comp_hyst_t hyst) void Cy_CTB_CompSetConfig(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_level_t level, cy_en_ctb_comp_bypass_t bypass, cy_en_ctb_comp_hyst_t hyst)
{ {
@ -1192,18 +1223,23 @@ void Cy_CTB_CompSetConfig(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_
* Function Name: Cy_CTB_CompGetConfig * Function Name: Cy_CTB_CompGetConfig
****************************************************************************//** ****************************************************************************//**
* *
* Returns the CTB comparator operating configuration. * Return the CTB comparator operating configuration as set by \ref Cy_CTB_CompSetConfig.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param compNum * \param compNum
* CY_CTB_OPAMP_0 or CY_CTB_OPAMP_1 * \ref CY_CTB_OPAMP_0 or \ref CY_CTB_OPAMP_1
* *
* \return comparator status * \return
* The comparator configuration.
* Compare the register value with the masks in \ref cy_en_ctb_comp_level_t, * Compare the register value with the masks in \ref cy_en_ctb_comp_level_t,
* \ref cy_en_ctb_comp_bypass_t, and \ref cy_en_ctb_comp_hyst_t. * \ref cy_en_ctb_comp_bypass_t, and \ref cy_en_ctb_comp_hyst_t.
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_COMP_GET_CONFIG
*
*******************************************************************************/ *******************************************************************************/
uint32_t Cy_CTB_CompGetConfig(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) uint32_t Cy_CTB_CompGetConfig(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
{ {
@ -1227,19 +1263,23 @@ uint32_t Cy_CTB_CompGetConfig(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compN
* Function Name: Cy_CTB_CompSetInterruptEdgeType * Function Name: Cy_CTB_CompSetInterruptEdgeType
****************************************************************************//** ****************************************************************************//**
* *
* Configures the type of edge that will trigger a comparator interrupt. * Configure the type of edge that will trigger a comparator interrupt.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param compNum * \param compNum
* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
* *
* \param edge * \param edge
* Edge type * Edge type that will trigger an interrupt. Select a value from \ref cy_en_ctb_comp_edge_t.
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_COMP_SET_INTERRUPT_EDGE_TYPE
*
*******************************************************************************/ *******************************************************************************/
void Cy_CTB_CompSetInterruptEdgeType(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_edge_t edge) void Cy_CTB_CompSetInterruptEdgeType(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_edge_t edge)
{ {
@ -1265,20 +1305,26 @@ void Cy_CTB_CompSetInterruptEdgeType(CTBM_Type *base, cy_en_ctb_opamp_sel_t comp
* Function Name: Cy_CTB_CompGetStatus * Function Name: Cy_CTB_CompGetStatus
****************************************************************************//** ****************************************************************************//**
* *
* Returns status of the indicated comparator output. * Return the comparator output status.
* When the positive input voltage is greater than the negative input voltage,
* the comparator status is high. Otherwise, the status is low.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param compNum * \param compNum
* CY_CTB_OPAMP_0 or CY_CTB_OPAMP_1 * \ref CY_CTB_OPAMP_0 or \ref CY_CTB_OPAMP_1.
* \ref CY_CTB_OPAMP_NONE and \ref CY_CTB_OPAMP_BOTH are invalid options.
* *
* \return comparator status * \return
* 0 - Comparator output low * The comparator status.
* 1 - Comparator output high * A value of 0 is returned if compNum is invalid.
* - 0: Status is low
* - 1: Status is high
* *
* A value of 0 is returned if compNum is an invalid value, CY_CTB_OPAMP_NONE * \funcusage
* or CY_CTB_OPAMP_BOTH. *
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_COMP_GET_STATUS
* *
*******************************************************************************/ *******************************************************************************/
uint32_t Cy_CTB_CompGetStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) uint32_t Cy_CTB_CompGetStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)

494
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctb/cy_ctb.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctb/cy_ctb.h
View File

@ -6,7 +6,7 @@
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -16,37 +16,32 @@
* \defgroup group_ctb Continuous Time Block (CTB) * \defgroup group_ctb Continuous Time Block (CTB)
* \{ * \{
* This driver provides API functions to configure and use the analog CTB. * This driver provides API functions to configure and use the analog CTB.
* The CTB comprises two identical Opamps, a switch routing matrix, * The CTB comprises two identical opamps, a switch routing matrix,
* and a sample and hold circuit. The high level features are: * and a sample and hold (SH) circuit. The high level features are:
* *
* - Two highly configurable Opamps * - Two highly configurable opamps
* - Each Opamp has programmable power and output drive strength * - Each opamp has programmable power and output drive strength
* - Each Opamp can be configured as a voltage follower using internal routing * - Each opamp can be configured as a voltage follower using internal routing
* - Each Opamp can be configured as a comparator with optional 10 mV hysteresis * - Each opamp can be configured as a comparator with optional 10 mV hysteresis
* - Flexible input and output routing * - Flexible input and output routing
* - Works as a buffer or amplifier for SAR ADC inputs * - Works as a buffer or amplifier for SAR ADC inputs
* - Works as a buffer, amplifier, or sample-and-hold for the CTDAC output * - Works as a buffer, amplifier, or sample and hold (SH) for the CTDAC output
* - Can operate in Deep Sleep power mode * - Can operate in Deep Sleep power mode
* *
* Each Opamp, marked OA0 and OA1, has one input and three output stages, * Each opamp, marked OA0 and OA1, has one input and three output stages,
* all of which share the common input stage. * all of which share the common input stage.
* Note that only one output stage can be selected at a time. * Note that only one output stage can be selected at a time.
* The output stage can operate as a low-drive strength Opamp (1X), a high-drive strength * The output stage can operate as a low-drive strength opamp for internal connections (1X), a high-drive strength
* Opamp (10X), or a comparator. * opamp for driving a device pin (10X), or a comparator.
* *
* The input range of the Opamp can be rail-to-rail if the charge pump is enabled. * Using the switching matrix, the opamp inputs and outputs
* Without the charge pump, the input range is 0 - VDDA-1.5 V. The output range
* of the Opamp is 0.2 V to VDDA-0.2 V, but this depends on the load. See the
* device datasheet for more detail.
*
* Using the switching matrix, the Opamp inputs and outputs
* can be connected to dedicated general-purpose I/Os or other internal analog * can be connected to dedicated general-purpose I/Os or other internal analog
* blocks. See the device datasheet for the dedicated CTB port. * blocks. See the device datasheet for the dedicated CTB port.
* *
* \image html ctb_block_diagram.png * \image html ctb_block_diagram.png "CTB Switch Diagram" width=1000px
* \image latex ctb_block_diagram.png * \image latex ctb_block_diagram.png
* *
* \section group_ctb_init Initialization * \section group_ctb_init Initialization and Enable
* *
* Before enabling the CTB, set up any external components (such as resistors) * Before enabling the CTB, set up any external components (such as resistors)
* that are needed for the design. To configure the entire hardware block, call \ref Cy_CTB_Init. * that are needed for the design. To configure the entire hardware block, call \ref Cy_CTB_Init.
@ -75,23 +70,80 @@
* *
* After initialization, call \ref Cy_CTB_Enable to enable the hardware. * After initialization, call \ref Cy_CTB_Enable to enable the hardware.
* *
* \section group_ctb_io_connections Input/Output Connections
*
* The CTB has internal switches to support flexible input and output routing. If these switches
* have not been configured during initialization, call \ref Cy_CTB_SetAnalogSwitch to
* make the input and output connections.
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_ANALOG_SWITCH
*
* As shown in the CTB switch diagram, the 10x output of OA0 and OA1 have dedicated
* connections to Pin 2 and Pin 3, respectively, of the CTB port. If different output
* connections are required, the other CTB switches and/or AMUXBUX A/B switches can be used.
*
* \section group_ctb_comparator Comparator Mode * \section group_ctb_comparator Comparator Mode
* *
* Each Opamp can be configured as a comparator. Note that when used as a * Each opamp can be configured as a comparator. Note that when used as a
* comparator, the hardware shuts down the 1X and 10X output drivers. * comparator, the hardware shuts down the 1X and 10X output drivers.
* Specific to the comparator mode, there is an optional 10 mV input hysteresis * Specific to the comparator mode, there is an optional 10 mV input hysteresis
* and configurable edge detection interrupt handling. * and configurable edge detection interrupt handling.
*
* - Negative input terminal: This input is usually connected to the reference voltage.
* - Positive input terminal: This input is usually connected to the voltage that is being compared.
* - Comparator digital output: This output goes high when the positive input voltage
* is greater than the negative input voltage.
*
* The comparator output can be routed to a pin or other components using HSIOM or trigger muxes.
*
* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_COMP_OUT_ROUTING
*
* \subsection group_ctb_comparator_handling_interrupts Handling interrupts
*
* The comparator output is connected to an edge detector * The comparator output is connected to an edge detector
* block, which is used to detect the edge (rising, falling, both, or disabled) * block, which is used to detect the edge (rising, falling, both, or disabled)
* for interrupt generation. * for interrupt generation.
* *
* The following code snippet demonstrates how to implement a routine to handle the interrupt.
* The routine gets called when any comparator on the device generates an interrupt.
*
* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_COMP_ISR
*
* The following code snippet demonstrates how to configure and enable the interrupt.
*
* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_COMP_INTR_SETUP
*
* \section group_ctb_opamp_range Opamp Input and Output Range
*
* The input range of the opamp can be rail-to-rail if the charge pump is enabled.
* Without the charge pump, the input range is 0 V to VDDA - 1.5 V. The output range
* of the opamp is typically 0.2 V to VDDA - 0.2 V and will depend on the load. See the
* device datasheet for more detail.
*
* <table class="doxtable">
* <tr>
* <th>Charge Pump</th>
* <th>Input Range</th></tr>
* <th>Output Range</th></tr>
* <tr>
* <td>Enabled</td>
* <td>0 V to VDDA</td>
* <td>0.2 V to VDDA - 0.2 V</td>
* </tr>
* <tr>
* <td>Disabled</td>
* <td>0 V to VDDA - 1.5 V</td>
* <td>0.2 V to VDDA - 0.2 V</td>
* </tr>
* </table>
*
* \section group_ctb_sample_hold Sample and Hold Mode * \section group_ctb_sample_hold Sample and Hold Mode
* *
* The CTB has a sample and hold (S/H) circuit at the non-inverting input of Opamp0. * The CTB has a sample and hold (SH) circuit at the non-inverting input of Opamp0.
* The circuit includes a hold capacitor, Chold, with a firmware controlled switch, CHD. * The circuit includes a hold capacitor, Chold, with a firmware controlled switch, CHD.
* Sampling and holding the source voltage is performed * Sampling and holding the source voltage is performed
* by closing and opening appropriate switches in the CTB using firmware. * by closing and opening appropriate switches in the CTB using firmware.
* If the S/H circuit is used for the CTDAC, the \ref Cy_CTB_DACSampleAndHold function * If the SH circuit is used for the CTDAC, the \ref Cy_CTB_DACSampleAndHold function
* should be called. * should be called.
* *
* \image html ctb_fast_config_vdac_sh.png * \image html ctb_fast_config_vdac_sh.png
@ -102,10 +154,10 @@
* The CTB relies on other blocks to function properly. The dependencies * The CTB relies on other blocks to function properly. The dependencies
* are documented here. * are documented here.
* *
*<b>Charge Pump Configuration</b> * \subsection group_ctb_dependencies_charge_pump Charge Pump Configuration
* *
* Each Opamp of the CTB has a charge pump that when enabled increases the * Each opamp of the CTB has a charge pump that when enabled increases the
* input range to the supply rails. When disabled, the Opamp input range is 0 - VDDA - 1.5 V. * input range to the supply rails. When disabled, the opamp input range is 0 - VDDA - 1.5 V.
* When enabled, the pump requires a clock. * When enabled, the pump requires a clock.
* Call the \ref Cy_CTB_SetClkPumpSource function in the \ref group_sysanalog driver to * Call the \ref Cy_CTB_SetClkPumpSource function in the \ref group_sysanalog driver to
* set the clock source for all CTBs. This clock can come from one of two sources: * set the clock source for all CTBs. This clock can come from one of two sources:
@ -116,6 +168,9 @@
* - \ref Cy_SysClk_ClkPumpSetSource * - \ref Cy_SysClk_ClkPumpSetSource
* - \ref Cy_SysClk_ClkPumpSetDivider * - \ref Cy_SysClk_ClkPumpSetDivider
* - \ref Cy_SysClk_ClkPumpEnable * - \ref Cy_SysClk_ClkPumpEnable
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_CLK_PUMP_SOURCE_SRSS
*
* -# One of the Peri Clock dividers * -# One of the Peri Clock dividers
* *
* Call the following functions to configure a Peri Clock divider as the * Call the following functions to configure a Peri Clock divider as the
@ -124,10 +179,12 @@
* - \ref Cy_SysClk_PeriphSetDivider * - \ref Cy_SysClk_PeriphSetDivider
* - \ref Cy_SysClk_PeriphEnableDivider * - \ref Cy_SysClk_PeriphEnableDivider
* *
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_CLK_PUMP_SOURCE_PERI
*
* When the charge pump is enabled, the clock frequency should be set as follows: * When the charge pump is enabled, the clock frequency should be set as follows:
* *
* <table class="doxtable"> * <table class="doxtable">
* <tr><th>Opamp Power</th><th>Pump Clock Freq</th></tr> * <tr><th>Opamp Power Level</th><th>Pump Clock Freq</th></tr>
* <tr> * <tr>
* <td>Low or Medium</td> * <td>Low or Medium</td>
* <td>8 - 24 MHz</td> * <td>8 - 24 MHz</td>
@ -138,18 +195,19 @@
* </tr> * </tr>
* </table> * </table>
* *
* The High power level of the Opamp requires a 24 MHz pump clock. * The High power level of the opamp requires a 24 MHz pump clock.
* In Deep Sleep mode, all high frequency clocks are * In Deep Sleep mode, all high frequency clocks are
* disabled and the charge pump will be disabled. * disabled and the charge pump will be disabled.
* *
* Note that the same pump clock is used by all Opamps on the device. Be aware of this * \note
* when configuring different Opamps to different power levels. * The same pump clock is used by all opamps on the device. Be aware of this
* when configuring different opamps to different power levels.
* *
* <b>Reference Current Configurations</b> * \subsection group_ctb_dependencies_reference_current Reference Current Configurations
* *
* The CTB uses two reference current generators, IPTAT and IZTAT, from * The CTB uses two reference current generators, IPTAT and IZTAT, from
* the AREF block (see \ref group_sysanalog driver). The IPTAT current is * the AREF block (see \ref group_sysanalog driver). The IPTAT current is
* used to trim the slope of the Opamp offset across temperature. * used to trim the slope of the opamp offset across temperature.
* The AREF must be initialized and enabled for the CTB to function properly. * The AREF must be initialized and enabled for the CTB to function properly.
* *
* If the CTB is configured to operate in Deep Sleep mode, * If the CTB is configured to operate in Deep Sleep mode,
@ -184,38 +242,23 @@
* while consuming the most current. * while consuming the most current.
* For Deep Sleep operation, use the other two configurations with the charge pump disabled. * For Deep Sleep operation, use the other two configurations with the charge pump disabled.
* For ultra low power, use the 100 nA current level. * For ultra low power, use the 100 nA current level.
* To configure the Opamps to operate in one of these options, call \ref Cy_CTB_SetCurrentMode. * To configure the opamps to operate in one of these options, call \ref Cy_CTB_SetCurrentMode.
* *
* <b>Sample and Hold Switch Control</b> * \subsection group_ctb_dependencies_sample_hold Sample and Hold Switch Control
* *
* The following eight switches that are contained in the CTB are enabled by the CTDAC IP * If you are using rev-08 of the CY8CKIT-062, the following eight switches
* block: * in the CTB are enabled by the CTDAC IP block:
* *
* - COS, CA0, CHD, CH6, COB, COR, CRS and CRD * - COS, CA0, CHD, CH6, COB, COR, CRS, and CRD
* *
* If any of the above switches are used, the \ref Cy_CTDAC_Enable function must be called. * On the rev-08 board, if any of the above switches are used, you must call \ref Cy_CTDAC_Enable
* Additionally, if any of the switches are used in Deep Sleep mode, the CTDAC must also * to enable these switches.
* be configured to operate in Deep Sleep (see \ref Cy_CTDAC_SetDeepSleepMode).
* *
* \section group_ctb_code_example Complete Code Example * Additionally, on the rev-08 board, if any of the switches are used in Deep Sleep mode,
* the CTDAC must also be configured to operate in Deep Sleep (see \ref Cy_CTDAC_SetDeepSleepMode).
* *
* The following example code demonstrates how to configure Opamp0 * In later revisions of the board, the switches are enabled by the CTB block so
* as a comparator and Opamp1 as a voltage follower. The terminals * calls to the CTDAC IP block are not necessary.
* are routed to external pins by closing the switches shown.
*
* \image html ctb_code_example.png
* \image latex ctb_code_example.png
*
* The example code also shows how to handle the comparator interrupt.
*
* \code
* #include "ctb/cy_ctb.h"
* #include "sysanalog/cy_sysanalog.h"
* #include "sysint/cy_sysint.h"
* #include "gpio/cy_gpio.h"
* \endcode
*
* \snippet ctb_sut_01.cydsn/main_cm0p.c CTB_CODE_EXAMPLE
* *
* \section group_ctb_more_information More Information * \section group_ctb_more_information More Information
* *
@ -248,7 +291,7 @@
* \defgroup group_ctb_functions_aref Reference Current Mode Functions * \defgroup group_ctb_functions_aref Reference Current Mode Functions
* \} * \}
* \defgroup group_ctb_globals Global Variables * \defgroup group_ctb_globals Global Variables
* \defgroup group_ctb_data_structures Data structures * \defgroup group_ctb_data_structures Data Structures
* \defgroup group_ctb_enums Enumerated Types * \defgroup group_ctb_enums Enumerated Types
*/ */
@ -360,6 +403,9 @@ extern "C" {
#define CY_CTB_SWITCHMASK(select,mask) (((select) == CY_CTB_SWITCH_OA0_SW) ? (((mask) & (~CY_CTB_DEINIT_OA0_SW)) == 0uL) : \ #define CY_CTB_SWITCHMASK(select,mask) (((select) == CY_CTB_SWITCH_OA0_SW) ? (((mask) & (~CY_CTB_DEINIT_OA0_SW)) == 0uL) : \
(((select) == CY_CTB_SWITCH_OA1_SW) ? (((mask) & (~CY_CTB_DEINIT_OA1_SW)) == 0uL) : \ (((select) == CY_CTB_SWITCH_OA1_SW) ? (((mask) & (~CY_CTB_DEINIT_OA1_SW)) == 0uL) : \
(((mask) & (~CY_CTB_DEINIT_CTD_SW)) == 0uL))) (((mask) & (~CY_CTB_DEINIT_CTD_SW)) == 0uL)))
#define CY_CTB_SARSEQCTRL(mask) (((mask) == CY_CTB_SW_SEQ_CTRL_D51_MASK) \
|| ((mask) == CY_CTB_SW_SEQ_CTRL_D52_D62_MASK) \
|| ((mask) == CY_CTB_SW_SEQ_CTRL_D51_D52_D62_MASK))
/** \endcond */ /** \endcond */
@ -376,7 +422,7 @@ extern "C" {
/** /**
* Most functions allow you to configure a single opamp or both opamps at once. * Most functions allow you to configure a single opamp or both opamps at once.
* The \ref Cy_CTB_SetInterruptMask function can be called with CY_CTB_OPAMP_NONE * The \ref Cy_CTB_SetInterruptMask function can be called with \ref CY_CTB_OPAMP_NONE
* and interrupts will be disabled. * and interrupts will be disabled.
*/ */
typedef enum{ typedef enum{
@ -431,17 +477,17 @@ typedef enum {
}cy_en_ctb_power_t; }cy_en_ctb_power_t;
/** /**
* The output stage of each Opamp can be configured for low-drive strength (1X) to drive internal circuits, * The output stage of each opamp can be configured for low-drive strength (1X) to drive internal circuits,
* for high-drive strength (10X) to drive external circuits, or as a comparator. * for high-drive strength (10X) to drive external circuits, or as a comparator.
*/ */
typedef enum { typedef enum {
CY_CTB_MODE_OPAMP1X = 0u, /**< Configure Opamp for low drive strength (1x) */ CY_CTB_MODE_OPAMP1X = 0u, /**< Configure opamp for low drive strength for internal connections (1x) */
CY_CTB_MODE_OPAMP10X = 1u << CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Pos, /**< Configure Opamp high drive strength (10x) */ CY_CTB_MODE_OPAMP10X = 1u << CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Pos, /**< Configure opamp high drive strength for driving a device pin (10x) */
CY_CTB_MODE_COMP = 1u << CTBM_OA_RES0_CTRL_OA0_COMP_EN_Pos, /**< Configure Opamp as a comparator */ CY_CTB_MODE_COMP = 1u << CTBM_OA_RES0_CTRL_OA0_COMP_EN_Pos, /**< Configure opamp as a comparator */
}cy_en_ctb_mode_t; }cy_en_ctb_mode_t;
/** /**
* Each Opamp has a charge pump to increase the input range to the rails. * Each opamp has a charge pump to increase the input range to the rails.
* When the charge pump is enabled, the input range is 0 to VDDA. * When the charge pump is enabled, the input range is 0 to VDDA.
* When disabled, the input range is 0 to VDDA - 1.5 V. * When disabled, the input range is 0 to VDDA - 1.5 V.
* *
@ -547,34 +593,45 @@ typedef enum
}cy_en_ctb_oa1_switches_t; }cy_en_ctb_oa1_switches_t;
/** /**
* Switch masks for CTDAC routing to be used in \ref Cy_CTB_SetAnalogSwitch. * Switch masks for CTDAC to CTB routing to be used in \ref Cy_CTB_SetAnalogSwitch.
*
* Eight of the 10 switches are enabled by the CTDAC IP block. That is,
* \ref Cy_CTDAC_Enable must also be called to close these switches.
* The CTDAC output should be high-z in order to not interfere with the CTB.
*
* The two switches that do not require the CTDAC are:
* - CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK (switch CIS)
* - CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK (switch ILR)
*/ */
typedef enum typedef enum
{ {
CY_CTB_SW_CTD_REF_OA1_OUT_MASK = CTBM_CTD_SW_CTDD_CRD_Msk, /**< Switch CRD: Opamp1 output to CTDAC reference. <b>CTDAC must be enabled</b> */ CY_CTB_SW_CTD_REF_OA1_OUT_MASK = CTBM_CTD_SW_CTDD_CRD_Msk, /**< Switch CRD: Opamp1 output to CTDAC reference. */
CY_CTB_SW_CTD_REFSENSE_OA1_NEG_MASK = CTBM_CTD_SW_CTDS_CRS_Msk, /**< Switch CRS: CTDAC reference sense to Opamp1 inverting input. <b>CTDAC must be enabled</b> */ CY_CTB_SW_CTD_REFSENSE_OA1_NEG_MASK = CTBM_CTD_SW_CTDS_CRS_Msk, /**< Switch CRS: CTDAC reference sense to Opamp1 inverting input. */
CY_CTB_SW_CTD_OUT_OA1_NEG_MASK = CTBM_CTD_SW_CTDS_COR_Msk, /**< Switch COR: CTDAC output to Opamp1 inverting input. <b>CTDAC must be enabled</b> */ CY_CTB_SW_CTD_OUT_OA1_NEG_MASK = CTBM_CTD_SW_CTDS_COR_Msk, /**< Switch COR: CTDAC output to Opamp1 inverting input. */
CY_CTB_SW_CTD_OUT_PIN6_MASK = CTBM_CTD_SW_CTDO_C6H_Msk, /**< Switch C6H: CTDAC output to P6 of CTB device port. <b>CTDAC must be enabled</b> */ CY_CTB_SW_CTD_OUT_PIN6_MASK = CTBM_CTD_SW_CTDO_C6H_Msk, /**< Switch C6H: CTDAC output to P6 of CTB device port. */
CY_CTB_SW_CTD_OUT_CHOLD_MASK = CTBM_CTD_SW_CTDO_COS_Msk, /**< Switch COS: CTDAC output to hold cap (deglitch capable). <b>CTDAC must be enabled</b> */ CY_CTB_SW_CTD_OUT_CHOLD_MASK = CTBM_CTD_SW_CTDO_COS_Msk, /**< Switch COS: CTDAC output to hold cap (deglitch capable). */
CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK = CTBM_CTD_SW_CTDH_COB_Msk, /**< Switch COB: Drive CTDAC output with opamp0 1x output during hold mode. <b>CTDAC must be enabled</b> */ CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK = CTBM_CTD_SW_CTDH_COB_Msk, /**< Switch COB: Drive CTDAC output with opamp0 1x output during hold mode. */
CY_CTB_SW_CTD_CHOLD_CONNECT_MASK = CTBM_CTD_SW_CTDH_CHD_Msk, /**< Switch CHD: Hold cap connection. <b>CTDAC must be enabled</b> */ CY_CTB_SW_CTD_CHOLD_CONNECT_MASK = CTBM_CTD_SW_CTDH_CHD_Msk, /**< Switch CHD: Hold cap connection. */
CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK = CTBM_CTD_SW_CTDH_CA0_Msk, /**< Switch CA0: Hold cap to Opamp0 non-inverting input. <b>CTDAC must be enabled</b> */ CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK = CTBM_CTD_SW_CTDH_CA0_Msk, /**< Switch CA0: Hold cap to Opamp0 non-inverting input. */
CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK = CTBM_CTD_SW_CTDH_CIS_Msk, /**< Switch CIS: Opamp0 non-inverting input isolation (for hold cap) */ CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK = CTBM_CTD_SW_CTDH_CIS_Msk, /**< Switch CIS: Opamp0 non-inverting input isolation (for hold cap) */
CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK = CTBM_CTD_SW_CTDH_ILR_Msk, /**< Switch ILR: Hold cap leakage reduction (drives far side of isolation switch CIS) */ CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK = CTBM_CTD_SW_CTDH_ILR_Msk, /**< Switch ILR: Hold cap leakage reduction (drives far side of isolation switch CIS) */
}cy_en_ctb_ctd_switches_t; }cy_en_ctb_ctd_switches_t;
/** /**
* Each Opamp also has a programmable compensation capacitor block, * Masks for CTB switches that can be controlled by the SAR sequencer.
* that optimizes the stability of the Opamp performance based on output load. * These masks are used in \ref Cy_CTB_EnableSarSeqCtrl and \ref Cy_CTB_DisableSarSeqCtrl.
* The compensation cap will be set by the driver based on the Opamp drive strength (1x or 10x) selection. *
* The SAR ADC subsystem supports analog routes through three CTB switches on SARBUS0 and SARBUS1.
* This control allows for pins on the CTB dedicated port to route to the SAR ADC input channels:
*
* - D51: Connects the inverting terminal of OA0 to SARBUS0
* - D52: Connects the inverting terminal of OA1 to SARBUS0
* - D62: Connects the inverting terminal of OA1 to SARBUS1
*/
typedef enum
{
CY_CTB_SW_SEQ_CTRL_D51_MASK = CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk, /**< Enable SAR sequencer control of the D51 switch */
CY_CTB_SW_SEQ_CTRL_D52_D62_MASK = CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk, /**< Enable SAR sequencer control of the D52 and D62 switches */
CY_CTB_SW_SEQ_CTRL_D51_D52_D62_MASK = CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk | CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk, /**< Enable SAR sequency control of all three switches */
}cy_en_ctb_switch_sar_seq_t;
/**
* Each opamp also has a programmable compensation capacitor block,
* that optimizes the stability of the opamp performance based on output load.
* The compensation cap will be set by the driver based on the opamp drive strength (1x or 10x) selection.
*/ */
typedef enum typedef enum
{ {
@ -585,7 +642,7 @@ typedef enum
}cy_en_ctb_compensation_cap_t; }cy_en_ctb_compensation_cap_t;
/** Enable or disable the gain booster. /** Enable or disable the gain booster.
* The gain booster will be set by the driver based on the Opamp drive strength (1x or 10x) selection. * The gain booster will be set by the driver based on the opamp drive strength (1x or 10x) selection.
*/ */
typedef enum typedef enum
{ {
@ -598,9 +655,9 @@ typedef enum
* To perform a sample or a hold, a preparation step must first be executed to * To perform a sample or a hold, a preparation step must first be executed to
* open the required switches. * open the required switches.
* *
* -# Call \ref Cy_CTB_DACSampleAndHold with CY_CTB_SH_PREPARE_SAMPLE or CY_CTB_SH_PREPARE_HOLD * -# Call \ref Cy_CTB_DACSampleAndHold with \ref CY_CTB_SH_PREPARE_SAMPLE or \ref CY_CTB_SH_PREPARE_HOLD
* -# Enable or disable CTDAC output * -# Enable or disable CTDAC output
* -# Call \ref Cy_CTB_DACSampleAndHold with CY_CTB_SH_SAMPLE or CY_CTB_SH_HOLD * -# Call \ref Cy_CTB_DACSampleAndHold with \ref CY_CTB_SH_SAMPLE or \ref CY_CTB_SH_HOLD
*/ */
typedef enum typedef enum
{ {
@ -662,8 +719,7 @@ typedef enum {
* Configuration structure to set up the entire CTB to be used with \ref Cy_CTB_Init. * Configuration structure to set up the entire CTB to be used with \ref Cy_CTB_Init.
*/ */
typedef struct { typedef struct {
cy_en_ctb_deep_sleep_t deepSleep; /**< Enable or disable the CTDAC during Deep Sleep */ cy_en_ctb_deep_sleep_t deepSleep; /**< Enable or disable the CTB during Deep Sleep */
bool enable; /**< Enable hardware after initialization. If disabled, call \ref Cy_CTB_Enable after initialization */
/* Opamp0 configuration */ /* Opamp0 configuration */
cy_en_ctb_power_t oa0Power; /**< Opamp0 power mode: off, low, medium, or high */ cy_en_ctb_power_t oa0Power; /**< Opamp0 power mode: off, low, medium, or high */
@ -693,12 +749,11 @@ typedef struct {
}cy_stc_ctb_config_t; }cy_stc_ctb_config_t;
/** /**
* This configuration structure is used to initialize only one Opamp of the CTB * This configuration structure is used to initialize only one opamp of the CTB
* without impacting analog routing. This structure is used with \ref Cy_CTB_OpampInit. * without impacting analog routing. This structure is used with \ref Cy_CTB_OpampInit.
*/ */
typedef struct { typedef struct {
cy_en_ctb_deep_sleep_t deepSleep; /**< Enable or disable the CTDAC during Deep Sleep */ cy_en_ctb_deep_sleep_t deepSleep; /**< Enable or disable the CTB during Deep Sleep */
bool enable; /**< Enable hardware after initialization. If disabled, call \ref Cy_CTB_Enable after initialization */
/* Opamp configuration */ /* Opamp configuration */
cy_en_ctb_power_t oaPower; /**< Opamp power mode: off, low, medium, or high */ cy_en_ctb_power_t oaPower; /**< Opamp power mode: off, low, medium, or high */
@ -714,11 +769,11 @@ typedef struct {
/** This configuration structure is used to quickly initialize Opamp0 for the most commonly used configurations. /** This configuration structure is used to quickly initialize Opamp0 for the most commonly used configurations.
* *
* Other configuration options are set to: * Other configuration options are set to:
* - .oa0Pump = CY_CTB_PUMP_ENABLE * - .oa0Pump = \ref CY_CTB_PUMP_ENABLE
* - .oa0CompEdge = CY_CTB_COMP_EDGE_BOTH * - .oa0CompEdge = \ref CY_CTB_COMP_EDGE_BOTH
* - .oa0CompLevel = CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE * - .oa0CompLevel = \ref CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL
* - .oa0CompBypass = CY_CTB_COMP_BYPASS_SYNC * - .oa0CompBypass = \ref CY_CTB_COMP_BYPASS_SYNC
* - .oa0CompHyst = CY_CTB_COMP_HYST_10MV * - .oa0CompHyst = \ref CY_CTB_COMP_HYST_10MV
* - .oa0CompIntrEn = true * - .oa0CompIntrEn = true
*/ */
typedef struct typedef struct
@ -732,11 +787,11 @@ typedef struct
/** This configuration structure is used to quickly initialize Opamp1 for the most commonly used configurations. /** This configuration structure is used to quickly initialize Opamp1 for the most commonly used configurations.
* *
* Other configuration options are set to: * Other configuration options are set to:
* - .oa1Pump = CY_CTB_PUMP_ENABLE * - .oa1Pump = \ref CY_CTB_PUMP_ENABLE
* - .oa1CompEdge = CY_CTB_COMP_EDGE_BOTH * - .oa1CompEdge = \ref CY_CTB_COMP_EDGE_BOTH
* - .oa1CompLevel = CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE * - .oa1CompLevel = \ref CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL
* - .oa1CompBypass = CY_CTB_COMP_BYPASS_SYNC * - .oa1CompBypass = \ref CY_CTB_COMP_BYPASS_SYNC
* - .oa1CompHyst = CY_CTB_COMP_HYST_10MV * - .oa1CompHyst = \ref CY_CTB_COMP_HYST_10MV
* - .oa1CompIntrEn = true * - .oa1CompIntrEn = true
*/ */
typedef struct typedef struct
@ -752,12 +807,6 @@ typedef struct
/** \addtogroup group_ctb_globals /** \addtogroup group_ctb_globals
* \{ * \{
* The \ref Cy_CTB_FastInit function allows for fast and easy initialization of the CTB
* based on commonly used configurations. Only routing switches required for
* the selected mode are configured, leaving final input and output connections
* to the user. Additional use modes are provided to easily configure the CTB as
* an output buffer or reference buffer for the CTDAC. These modes are used
* along with the CTDAC PDL driver.
*/ */
/*************************************** /***************************************
* Global Variables * Global Variables
@ -775,7 +824,7 @@ extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Unused;
*/ */
extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Comp; extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Comp;
/** Configure Opamp0 as an Opamp with 1x drive. No routing is configured. /** Configure Opamp0 as an opamp with 1x drive. No routing is configured.
* *
* \image html ctb_fast_config_opamp1x.png * \image html ctb_fast_config_opamp1x.png
* \image latex ctb_fast_config_opamp1x.png width=100px * \image latex ctb_fast_config_opamp1x.png width=100px
@ -784,7 +833,7 @@ extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Comp;
*/ */
extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp1x; extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp1x;
/** Configure Opamp0 as an Opamp with 10x drive. No routing is configured. /** Configure Opamp0 as an opamp with 10x drive. No routing is configured.
* *
* \image html ctb_fast_config_opamp10x.png * \image html ctb_fast_config_opamp10x.png
* \image latex ctb_fast_config_opamp10x.png width=100px * \image latex ctb_fast_config_opamp10x.png width=100px
@ -794,7 +843,7 @@ extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp1x;
extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp10x; extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp10x;
/** Configure Opamp0 as one stage of a differential amplifier. /** Configure Opamp0 as one stage of a differential amplifier.
* The Opamp is in 10x drive and the switches shown are closed. * The opamp is in 10x drive and the switches shown are closed.
* *
* \image html ctb_fast_config_oa0_diffamp.png * \image html ctb_fast_config_oa0_diffamp.png
* \image latex ctb_fast_config_oa0_diffamp.png width=100px * \image latex ctb_fast_config_oa0_diffamp.png width=100px
@ -845,7 +894,7 @@ extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Unused;
*/ */
extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Comp; extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Comp;
/** Configure Opamp1 as an Opamp with 1x drive. No routing is configured. /** Configure Opamp1 as an opamp with 1x drive. No routing is configured.
* *
* \image html ctb_fast_config_opamp1x.png * \image html ctb_fast_config_opamp1x.png
* \image latex ctb_fast_config_opamp1x.png width=100px * \image latex ctb_fast_config_opamp1x.png width=100px
@ -864,7 +913,7 @@ extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp1x;
extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp10x; extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp10x;
/** Configure Opamp1 as one stage of a differential amplifier. /** Configure Opamp1 as one stage of a differential amplifier.
* The Opamp is in 10x drive and the switches shown are closed. * The opamp is in 10x drive and the switches shown are closed.
* *
* \image html ctb_fast_config_oa1_diffamp.png * \image html ctb_fast_config_oa1_diffamp.png
* \image latex ctb_fast_config_oa1_diffamp.png width=100px * \image latex ctb_fast_config_oa1_diffamp.png width=100px
@ -960,7 +1009,7 @@ uint32_t Cy_CTB_CompGetStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compN
/** /**
* \addtogroup group_ctb_functions_trim * \addtogroup group_ctb_functions_trim
* These are advanced functions for trimming the offset and slope of the Opamps. * These are advanced functions for trimming the offset and slope of the opamps.
* Most users do not need to call these functions and can use the factory trimmed values. * Most users do not need to call these functions and can use the factory trimmed values.
* \{ * \{
*/ */
@ -977,7 +1026,9 @@ uint32_t Cy_CTB_OpampGetSlope(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opamp
*/ */
void Cy_CTB_SetAnalogSwitch(CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect, uint32_t switchMask, cy_en_ctb_switch_state_t state); void Cy_CTB_SetAnalogSwitch(CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect, uint32_t switchMask, cy_en_ctb_switch_state_t state);
uint32_t Cy_CTB_GetAnalogSwitch(const CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect); uint32_t Cy_CTB_GetAnalogSwitch(const CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect);
void Cy_CTB_OpenAllSwitches(CTBM_Type *base); __STATIC_INLINE void Cy_CTB_OpenAllSwitches(CTBM_Type *base);
__STATIC_INLINE void Cy_CTB_EnableSarSeqCtrl(CTBM_Type *base, cy_en_ctb_switch_sar_seq_t switchMask);
__STATIC_INLINE void Cy_CTB_DisableSarSeqCtrl(CTBM_Type *base, cy_en_ctb_switch_sar_seq_t switchMask);
/** \} */ /** \} */
/** /**
@ -987,7 +1038,7 @@ void Cy_CTB_OpenAllSwitches(CTBM_Type *base);
*/ */
__STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); __STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
__STATIC_INLINE void Cy_CTB_ClearInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); __STATIC_INLINE void Cy_CTB_ClearInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
__STATIC_INLINE void Cy_CTB_SetSwInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); __STATIC_INLINE void Cy_CTB_SetInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
__STATIC_INLINE void Cy_CTB_SetInterruptMask(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); __STATIC_INLINE void Cy_CTB_SetInterruptMask(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
__STATIC_INLINE uint32_t Cy_CTB_GetInterruptMask(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); __STATIC_INLINE uint32_t Cy_CTB_GetInterruptMask(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
__STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatusMasked(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); __STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatusMasked(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
@ -995,7 +1046,7 @@ __STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatusMasked(const CTBM_Type *base,
/** /**
* \addtogroup group_ctb_functions_aref * \addtogroup group_ctb_functions_aref
* This set of functions impacts all Opamps on the chip. * This set of functions impacts all opamps on the chip.
* Notice how some of these functions do not take a base address input. * Notice how some of these functions do not take a base address input.
* When calling \ref Cy_CTB_SetCurrentMode for a CTB instance on the device, * When calling \ref Cy_CTB_SetCurrentMode for a CTB instance on the device,
* it should be called for all other CTB instances as well. This is because * it should be called for all other CTB instances as well. This is because
@ -1018,7 +1069,7 @@ __STATIC_INLINE void Cy_CTB_DisableRedirect(void);
* Function Name: Cy_CTB_Enable * Function Name: Cy_CTB_Enable
****************************************************************************//** ****************************************************************************//**
* *
* Powers up the hardware block necessary for the operation of the CTB. * Power up the CTB hardware block.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
@ -1035,7 +1086,7 @@ __STATIC_INLINE void Cy_CTB_Enable(CTBM_Type *base)
* Function Name: Cy_CTB_Disable * Function Name: Cy_CTB_Disable
****************************************************************************//** ****************************************************************************//**
* *
* Powers down the hardware block necessary for the operation of the CTB. * Power down the CTB hardware block.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
@ -1050,6 +1101,100 @@ __STATIC_INLINE void Cy_CTB_Disable(CTBM_Type *base)
/** \} */ /** \} */
/**
* \addtogroup group_ctb_functions_switches
* \{
*/
/*******************************************************************************
* Function Name: Cy_CTB_OpenAllSwitches
****************************************************************************//**
*
* Open all the switches and disable all hardware (SAR Sequencer and DSI) control of the switches.
* Primarily used as a quick method of re-configuring all analog connections
* that are sparsely closed.
*
* \param base
* Pointer to structure describing registers
*
* \return None
*
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_OPEN_ALL_SWITCHES
*
*******************************************************************************/
__STATIC_INLINE void Cy_CTB_OpenAllSwitches(CTBM_Type *base)
{
base->OA0_SW_CLEAR = CY_CTB_DEINIT_OA0_SW;
base->OA1_SW_CLEAR = CY_CTB_DEINIT_OA1_SW;
base->CTD_SW_CLEAR = CY_CTB_DEINIT_CTD_SW;
base->CTB_SW_DS_CTRL = CY_CTB_DEINIT;
base->CTB_SW_SQ_CTRL = CY_CTB_DEINIT;
}
/*******************************************************************************
* Function Name: Cy_CTB_EnableSarSeqCtrl
****************************************************************************//**
*
* Enable SAR sequencer control of specified switch(es).
*
* This allows the SAR ADC to use routes through the CTB when configuring its channels.
*
* There are three switches in the CTB that can be enabled by the SAR sequencer.
* - D51: This switch connects the negative input of Opamp0 to the SARBUS0
* - D52: This switch connects the positive input of Opamp1 to the SARBUS0
* - D62: This switch connects the positive input of Opamp1 to the SARBUS1
*
* \param base
* Pointer to structure describing registers
*
* \param switchMask
* The switch or switches in which to enable SAR sequencer control.
* Use an enumerated value from \ref cy_en_ctb_switch_sar_seq_t.
*
* \return None
*
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_ENABLE_SAR_SEQ_CTRL
*
*******************************************************************************/
__STATIC_INLINE void Cy_CTB_EnableSarSeqCtrl(CTBM_Type *base, cy_en_ctb_switch_sar_seq_t switchMask)
{
CY_ASSERT_L3(CY_CTB_SARSEQCTRL(switchMask));
base->CTB_SW_SQ_CTRL |= (uint32_t) switchMask;
}
/*******************************************************************************
* Function Name: Cy_CTB_DisableSarSeqCtrl
****************************************************************************//**
*
* Disable SAR sequencer control of specified switch(es).
*
* \param base
* Pointer to structure describing registers
*
* \param switchMask
* The switch or switches in which to disable SAR sequencer control.
* Use an enumerated value from \ref cy_en_ctb_switch_sar_seq_t.
*
* \return None
*
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_DISABLE_SAR_SEQ_CTRL
*
*******************************************************************************/
__STATIC_INLINE void Cy_CTB_DisableSarSeqCtrl(CTBM_Type *base, cy_en_ctb_switch_sar_seq_t switchMask)
{
CY_ASSERT_L3(CY_CTB_SARSEQCTRL(switchMask));
base->CTB_SW_SQ_CTRL &= ~((uint32_t) switchMask);
}
/** \} */
/** /**
* \addtogroup group_ctb_functions_interrupts * \addtogroup group_ctb_functions_interrupts
* \{ * \{
@ -1059,22 +1204,26 @@ __STATIC_INLINE void Cy_CTB_Disable(CTBM_Type *base)
* Function Name: Cy_CTB_GetInterruptStatus * Function Name: Cy_CTB_GetInterruptStatus
****************************************************************************//** ****************************************************************************//**
* *
* Returns status of the interrupt that happens when the configured comparator * Return the status of the interrupt when the configured comparator
* edge is detected. * edge is detected.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param compNum * \param compNum
* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
* *
* \return Interrupt status * \return
* 0 - Edge was not detected * The interrupt status.
* Non-zero - Configured edge type was detected * If compNum is \ref CY_CTB_OPAMP_BOTH, cast the returned status
* * to \ref cy_en_ctb_opamp_sel_t to determine which comparator edge (or both)
* If compNum is CY_CTB_OPAMP_BOTH, cast the returned status
* to cy_en_ctb_opamp_sel_t to determine which comparator edge (or both)
* was detected. * was detected.
* - 0: Edge was not detected
* - Non-zero: Configured edge type was detected
*
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_COMP_GETINTERRUPTSTATUS
* *
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) __STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
@ -1088,7 +1237,7 @@ __STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatus(const CTBM_Type *base, cy_en_
* Function Name: Cy_CTB_ClearInterrupt * Function Name: Cy_CTB_ClearInterrupt
****************************************************************************//** ****************************************************************************//**
* *
* Clears the CTB comparator triggered interrupt. * Clear the CTB comparator triggered interrupt.
* The interrupt must be cleared with this function so that the hardware * The interrupt must be cleared with this function so that the hardware
* can set subsequent interrupts and those interrupts can be forwarded * can set subsequent interrupts and those interrupts can be forwarded
* to the interrupt controller, if enabled. * to the interrupt controller, if enabled.
@ -1097,7 +1246,7 @@ __STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatus(const CTBM_Type *base, cy_en_
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param compNum * \param compNum
* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
* *
* \return None * \return None
* *
@ -1107,24 +1256,27 @@ __STATIC_INLINE void Cy_CTB_ClearInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_
CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum));
base->INTR = (uint32_t) compNum; base->INTR = (uint32_t) compNum;
/* Dummy read for buffered writes. */
(void) base->INTR;
} }
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_CTB_SetSwInterrupt * Function Name: Cy_CTB_SetInterrupt
****************************************************************************//** ****************************************************************************//**
* *
* Forces the CTB interrupt to trigger using software. * Force the CTB interrupt to trigger using software.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param compNum * \param compNum
* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
* *
* \return None * \return None
* *
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_CTB_SetSwInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) __STATIC_INLINE void Cy_CTB_SetInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
{ {
CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum));
@ -1142,13 +1294,15 @@ __STATIC_INLINE void Cy_CTB_SetSwInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param compNum * \param compNum
* CY_CTB_OPAMP_NONE, CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH * \ref CY_CTB_OPAMP_NONE, \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH.
* * Calling this function with CY_CTB_OPAMP_NONE will disable all interrupt requests.
* Calling this function with CY_CTB_OPAMP_NONE will disable all
* interrupt requests.
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_INTERRUPT_MASK
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_CTB_SetInterruptMask(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) __STATIC_INLINE void Cy_CTB_SetInterruptMask(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
{ {
@ -1161,7 +1315,7 @@ __STATIC_INLINE void Cy_CTB_SetInterruptMask(CTBM_Type *base, cy_en_ctb_opamp_se
* Function Name: Cy_CTB_GetInterruptMask * Function Name: Cy_CTB_GetInterruptMask
****************************************************************************//** ****************************************************************************//**
* *
* Returns whether the CTB comparator edge interrupt output is * Return whether the CTB comparator edge interrupt output is
* forwarded to the CPU interrupt controller as configured by * forwarded to the CPU interrupt controller as configured by
* \ref Cy_CTB_SetInterruptMask. * \ref Cy_CTB_SetInterruptMask.
* *
@ -1169,15 +1323,19 @@ __STATIC_INLINE void Cy_CTB_SetInterruptMask(CTBM_Type *base, cy_en_ctb_opamp_se
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param compNum * \param compNum
* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
* *
* \return Interrupt mask * \return
* 0 - Interrupt output not forwarded to interrupt controller * The interrupt mask.
* Non-zero - Interrupt output forwarded to interrupt controller * If compNum is \ref CY_CTB_OPAMP_BOTH, cast the returned mask
* * to \ref cy_en_ctb_opamp_sel_t to determine which comparator interrupt
* If compNum is CY_CTB_OPAMP_BOTH, cast the returned mask
* to cy_en_ctb_opamp_sel_t to determine which comparator interrupt
* output (or both) is forwarded. * output (or both) is forwarded.
* - 0: Interrupt output not forwarded to interrupt controller
* - Non-zero: Interrupt output forwarded to interrupt controller
*
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_GET_INTERRUPT_MASK
* *
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_CTB_GetInterruptMask(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) __STATIC_INLINE uint32_t Cy_CTB_GetInterruptMask(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
@ -1191,22 +1349,21 @@ __STATIC_INLINE uint32_t Cy_CTB_GetInterruptMask(const CTBM_Type *base, cy_en_ct
* Function Name: Cy_CTB_GetInterruptStatusMasked * Function Name: Cy_CTB_GetInterruptStatusMasked
****************************************************************************//** ****************************************************************************//**
* *
* Returns the CTB comparator edge output interrupt state after being masked. * Return the CTB comparator edge output interrupt state after being masked.
* This is the bitwise AND of \ref Cy_CTB_GetInterruptStatus and \ref Cy_CTB_GetInterruptMask. * This is the bitwise AND of \ref Cy_CTB_GetInterruptStatus and \ref Cy_CTB_GetInterruptMask.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param compNum * \param compNum
* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
* *
* \return Interrupt masked * \return
* 0 - Edge not detected or not masked * If compNum is \ref CY_CTB_OPAMP_BOTH, cast the returned value
* Non-zero - Configured edge type detected and masked * to \ref cy_en_ctb_opamp_sel_t to determine which comparator interrupt
*
* If compNum is CY_CTB_OPAMP_BOTH, cast the returned value
* to cy_en_ctb_opamp_sel_t to determine which comparator interrupt
* output (or both) is detected and masked. * output (or both) is detected and masked.
* - 0: Configured edge not detected or not masked
* - Non-zero: Configured edge type detected and masked
* *
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatusMasked(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) __STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatusMasked(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
@ -1226,7 +1383,7 @@ __STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatusMasked(const CTBM_Type *base,
* Function Name: Cy_CTB_SetIptatLevel * Function Name: Cy_CTB_SetIptatLevel
****************************************************************************//** ****************************************************************************//**
* *
* Set the IPTAT level to 1uA or 100nA. The IPTAT generator is used by the CTB * Set the IPTAT reference level to 1 uA or 100 nA. The IPTAT generator is used by the CTB
* for slope offset drift. * for slope offset drift.
* *
* \param iptat * \param iptat
@ -1234,6 +1391,10 @@ __STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatusMasked(const CTBM_Type *base,
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_IPTAT_LEVEL
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_CTB_SetIptatLevel(cy_en_ctb_iptat_t iptat) __STATIC_INLINE void Cy_CTB_SetIptatLevel(cy_en_ctb_iptat_t iptat)
{ {
@ -1246,13 +1407,15 @@ __STATIC_INLINE void Cy_CTB_SetIptatLevel(cy_en_ctb_iptat_t iptat)
* Function Name: Cy_CTB_SetClkPumpSource * Function Name: Cy_CTB_SetClkPumpSource
****************************************************************************//** ****************************************************************************//**
* *
* Set the clock source for the CTB charge pump. The clock can come from: * Set the clock source for both charge pumps in the CTB. Recall that each opamp
* - a dedicated divider off of one of the CLK_PATH in the SRSS * has its own charge pump. The clock can come from:
*
* - A dedicated divider off of one of the CLK_PATH in the SRSS.
* Call the following functions to configure the pump clock from the SRSS: * Call the following functions to configure the pump clock from the SRSS:
* - \ref Cy_SysClk_ClkPumpSetSource * - \ref Cy_SysClk_ClkPumpSetSource
* - \ref Cy_SysClk_ClkPumpSetDivider * - \ref Cy_SysClk_ClkPumpSetDivider
* - \ref Cy_SysClk_ClkPumpEnable * - \ref Cy_SysClk_ClkPumpEnable
* - one of the Peri Clock dividers * - One of the Peri Clock dividers.
* Call the following functions to configure a Peri Clock divider as the * Call the following functions to configure a Peri Clock divider as the
* pump clock: * pump clock:
* - \ref Cy_SysClk_PeriphAssignDivider with the IP block set to PCLK_PASS_CLOCK_PUMP_PERI * - \ref Cy_SysClk_PeriphAssignDivider with the IP block set to PCLK_PASS_CLOCK_PUMP_PERI
@ -1260,10 +1423,19 @@ __STATIC_INLINE void Cy_CTB_SetIptatLevel(cy_en_ctb_iptat_t iptat)
* - \ref Cy_SysClk_PeriphEnableDivider * - \ref Cy_SysClk_PeriphEnableDivider
* *
* \param clkPump * \param clkPump
* Value from enum \ref cy_en_ctb_clk_pump_source_t * Clock source selection (SRSS or PeriClk) for the pump. Select a value from
* \ref cy_en_ctb_clk_pump_source_t
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_CLK_PUMP_SOURCE_SRSS
*
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_CLK_PUMP_SOURCE_PERI
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_CTB_SetClkPumpSource(cy_en_ctb_clk_pump_source_t clkPump) __STATIC_INLINE void Cy_CTB_SetClkPumpSource(cy_en_ctb_clk_pump_source_t clkPump)
{ {
@ -1292,11 +1464,15 @@ __STATIC_INLINE void Cy_CTB_SetClkPumpSource(cy_en_ctb_clk_pump_source_t clkPump
* should be used when the IPTAT bias level is set to 100 nA * should be used when the IPTAT bias level is set to 100 nA
* (see \ref Cy_CTB_SetIptatLevel). * (see \ref Cy_CTB_SetIptatLevel).
* *
* Without the IPTAT reference, the CTB cannot compensate for the slope of * When the CTB.IPTAT is HiZ, the CTB cannot compensate for the slope of
* the offset across temperature. * the offset across temperature.
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_ENABLE_REDIRECT
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_CTB_EnableRedirect(void) __STATIC_INLINE void Cy_CTB_EnableRedirect(void)
{ {

165
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctdac/cy_ctdac.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctdac/cy_ctdac.c
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_ctdac.c * \file cy_ctdac.c
* \version 1.0 * \version 1.0.1
* *
* Provides the public functions for the API for the CTDAC driver. * Provides the public functions for the API for the CTDAC driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -58,8 +58,12 @@ const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_OA1Ref_BufferedOut =
* \param config * \param config
* Pointer to structure containing configuration data * Pointer to structure containing configuration data
* *
* \return cy_en_ctdac_status_t * \return
* Status of initialization, CY_CTDAC_SUCCESS or CY_CTDAC_BAD_PARAM * Status of initialization, \ref CY_CTDAC_SUCCESS or \ref CY_CTDAC_BAD_PARAM
*
* \funcusage
*
* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_INIT_CUSTOM
* *
*******************************************************************************/ *******************************************************************************/
cy_en_ctdac_status_t Cy_CTDAC_Init(CTDAC_Type *base, const cy_stc_ctdac_config_t *config) cy_en_ctdac_status_t Cy_CTDAC_Init(CTDAC_Type *base, const cy_stc_ctdac_config_t *config)
@ -116,9 +120,6 @@ cy_en_ctdac_status_t Cy_CTDAC_Init(CTDAC_Type *base, const cy_stc_ctdac_config_t
/* Handle the output mode */ /* Handle the output mode */
ctdacCtrl |= (uint32_t)config->outputMode; ctdacCtrl |= (uint32_t)config->outputMode;
/* Handle enable bit */
ctdacCtrl |= ((uint32_t)config->enable) << CTDAC_CTDAC_CTRL_ENABLED_Pos;
/* Handle the reference source */ /* Handle the reference source */
switch(config->refSource) switch(config->refSource)
{ {
@ -171,8 +172,8 @@ cy_en_ctdac_status_t Cy_CTDAC_Init(CTDAC_Type *base, const cy_stc_ctdac_config_t
* *
* Reset CTDAC registers back to power on reset defaults. * Reset CTDAC registers back to power on reset defaults.
* *
* Does not disable or configure the clock. Call \ref Cy_CTDAC_Init or \ref Cy_CTDAC_FastInit * \note
* to configure the CTDAC and clock. * Does not disable the clock.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
@ -181,8 +182,12 @@ cy_en_ctdac_status_t Cy_CTDAC_Init(CTDAC_Type *base, const cy_stc_ctdac_config_t
* If true, all switches are reset to their default state. * If true, all switches are reset to their default state.
* If false, switch registers are untouched. * If false, switch registers are untouched.
* *
* \return cy_en_ctdac_status_t * \return
* Status of initialization, CY_CTDAC_SUCCESS, or CY_CTDAC_BAD_PARAM * Status of initialization, \ref CY_CTDAC_SUCCESS, or \ref CY_CTDAC_BAD_PARAM
*
* \funcusage
*
* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_DEINIT
* *
*******************************************************************************/ *******************************************************************************/
cy_en_ctdac_status_t Cy_CTDAC_DeInit(CTDAC_Type *base, bool deInitRouting) cy_en_ctdac_status_t Cy_CTDAC_DeInit(CTDAC_Type *base, bool deInitRouting)
@ -217,39 +222,61 @@ cy_en_ctdac_status_t Cy_CTDAC_DeInit(CTDAC_Type *base, bool deInitRouting)
* Function Name: Cy_CTDAC_FastInit * Function Name: Cy_CTDAC_FastInit
****************************************************************************//** ****************************************************************************//**
* *
* Initializes the CTDAC to one of the common use modes. * Initialize the CTDAC to one of the common use modes.
* These provide a quick and easy method of configuring the CTDAC when using * This function provides a quick and easy method of configuring the CTDAC when using
* the PDL driver for device configuration. * the PDL driver for device configuration.
* *
* The other configuration options are set to: * The other configuration options are set to:
* - .formatMode = CY_CTDAC_FORMAT_UNSIGNED * - .formatMode = \ref CY_CTDAC_FORMAT_UNSIGNED
* - .updateMode = CY_CTDAC_UPDATE_BUFFERED_WRITE * - .updateMode = \ref CY_CTDAC_UPDATE_BUFFERED_WRITE
* - .deglitchMode = CY_CTDAC_DEGLITCHMODE_NONE * - .deglitchMode = \ref CY_CTDAC_DEGLITCHMODE_NONE
* - .outputMode = CY_CTDAC_OUTPUT_VALUE * - .outputMode = \ref CY_CTDAC_OUTPUT_VALUE
* - .deepSleep = CY_CTDAC_DEEPSLEEP_DISABLE * - .deepSleep = \ref CY_CTDAC_DEEPSLEEP_DISABLE
* - .deglitchCycles = CY_CTDAC_DEINIT * - .deglitchCycles = \ref CY_CTDAC_DEINIT
* - .value = CY_CTDAC_UNSIGNED_MID_CODE_VALUE * - .value = \ref CY_CTDAC_UNSIGNED_MID_CODE_VALUE
* - .nextValue = CY_CTDAC_UNSIGNED_MID_CODE_VALUE * - .nextValue = \ref CY_CTDAC_UNSIGNED_MID_CODE_VALUE
* - .enableInterrupt = true * - .enableInterrupt = true
* - .configClock = true * - .configClock = true
* - .dividerType = CY_CTDAC_FAST_CLKCFG_TYPE * - .dividerType = \ref CY_CTDAC_FAST_CLKCFG_TYPE
* - .dividerNum = CY_CTDAC_FAST_CLKCFG_NUM * - .dividerNum = \ref CY_CTDAC_FAST_CLKCFG_NUM
* - .dividerInitValue = CY_CTDAC_FAST_CLKCFG_DIV * - .dividerInitValue = \ref CY_CTDAC_FAST_CLKCFG_DIV
* - .dividerFracValue = CY_CTDAC_DEINIT * - .dividerFracValue = \ref CY_CTDAC_DEINIT
*
* A separate call to \ref Cy_CTDAC_Enable is needed to turn on the hardware.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param config * \param config
* Pointer to structure containing configuration data for quick initialization * Pointer to structure containing configuration data for quick initialization.
* Use one of the provided structures or define your own. * Define your own or use one of the provided structures:
* - \ref Cy_CTDAC_Fast_VddaRef_UnbufferedOut * - \ref Cy_CTDAC_Fast_VddaRef_UnbufferedOut
* - \ref Cy_CTDAC_Fast_VddaRef_BufferedOut * - \ref Cy_CTDAC_Fast_VddaRef_BufferedOut
* - \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut * - \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut
* - \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut * - \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut
* *
* \return cy_en_ctdac_status_t * \return
* Status of initialization, CY_CTDAC_SUCCESS or CY_CTDAC_BAD_PARAM * Status of initialization, \ref CY_CTDAC_SUCCESS or \ref CY_CTDAC_BAD_PARAM
*
* \funcusage
*
* The following code snippets configures VDDA as the reference source and
* routes the output directly to Pin 6 (unbuffered).
*
* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_FAST_INIT
*
* \funcusage
*
* The following code snippet shows how the CTDAC and CTB blocks can
* quickly be configured to work together. The code
* configures the CTDAC to use a buffered output,
* a buffered reference source from the internal bandgap voltage, and closes
* all required analog routing switches.
*
* \image html ctdac_fast_init_funcusage.png
* \image latex ctdac_fast_init_funcusage.png
*
* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_FAST_INIT_CTB
* *
*******************************************************************************/ *******************************************************************************/
cy_en_ctdac_status_t Cy_CTDAC_FastInit(CTDAC_Type *base, const cy_stc_ctdac_fast_config_t *config) cy_en_ctdac_status_t Cy_CTDAC_FastInit(CTDAC_Type *base, const cy_stc_ctdac_fast_config_t *config)
@ -311,7 +338,7 @@ cy_en_ctdac_status_t Cy_CTDAC_FastInit(CTDAC_Type *base, const cy_stc_ctdac_fast
base->CTDAC_VAL = CY_CTDAC_UNSIGNED_MID_CODE_VALUE; base->CTDAC_VAL = CY_CTDAC_UNSIGNED_MID_CODE_VALUE;
base->CTDAC_VAL_NXT = CY_CTDAC_UNSIGNED_MID_CODE_VALUE; base->CTDAC_VAL_NXT = CY_CTDAC_UNSIGNED_MID_CODE_VALUE;
/* For fast configuration, the DAC clock is the Peri clock divided by 100 */ /* For fast configuration, the DAC clock is the Peri clock divided by 100. */
Cy_CTDAC_ConfigureClock(CY_CTDAC_UPDATE_BUFFERED_WRITE, CY_CTDAC_FAST_CLKCFG_TYPE, CY_CTDAC_FAST_CLKCFG_NUM, CY_CTDAC_FAST_CLKCFG_DIV, CY_CTDAC_DEINIT); Cy_CTDAC_ConfigureClock(CY_CTDAC_UPDATE_BUFFERED_WRITE, CY_CTDAC_FAST_CLKCFG_TYPE, CY_CTDAC_FAST_CLKCFG_NUM, CY_CTDAC_FAST_CLKCFG_DIV, CY_CTDAC_DEINIT);
base->CTDAC_CTRL = ctdacCtrl; base->CTDAC_CTRL = ctdacCtrl;
@ -384,7 +411,7 @@ static void Cy_CTDAC_ConfigureClock(cy_en_ctdac_update_t updateMode, cy_en_divid
* Function Name: Cy_CTDAC_SetSignMode * Function Name: Cy_CTDAC_SetSignMode
****************************************************************************//** ****************************************************************************//**
* *
* Sets whether to interpret the DAC value as signed or unsigned. * Set whether to interpret the DAC value as signed or unsigned.
* In unsigned mode, the DAC value register is used without any decoding. * In unsigned mode, the DAC value register is used without any decoding.
* In signed mode, the MSB is inverted by adding 0x800 to the DAC value. * In signed mode, the MSB is inverted by adding 0x800 to the DAC value.
* This converts the lowest signed number, 0x800, to the lowest unsigned * This converts the lowest signed number, 0x800, to the lowest unsigned
@ -398,6 +425,10 @@ static void Cy_CTDAC_ConfigureClock(cy_en_ctdac_update_t updateMode, cy_en_divid
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_SIGN_MODE
*
*******************************************************************************/ *******************************************************************************/
void Cy_CTDAC_SetSignMode(CTDAC_Type *base, cy_en_ctdac_format_t formatMode) void Cy_CTDAC_SetSignMode(CTDAC_Type *base, cy_en_ctdac_format_t formatMode)
{ {
@ -415,17 +446,20 @@ void Cy_CTDAC_SetSignMode(CTDAC_Type *base, cy_en_ctdac_format_t formatMode)
* Function Name: Cy_CTDAC_SetDeepSleepMode * Function Name: Cy_CTDAC_SetDeepSleepMode
****************************************************************************//** ****************************************************************************//**
* *
* Sets whether to allow the DAC hardware to continue to stay powered in * Enable or disable the DAC hardware operation in Deep Sleep mode.
* Deep Sleep mode.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param deepSleep * \param deepSleep
* Enabled or disabled. See \ref cy_en_ctdac_deep_sleep_t for values. * Enable or disable Deep Sleep operation. Select value from \ref cy_en_ctdac_deep_sleep_t.
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_DEEPSLEEP_MODE
*
*******************************************************************************/ *******************************************************************************/
void Cy_CTDAC_SetDeepSleepMode(CTDAC_Type *base, cy_en_ctdac_deep_sleep_t deepSleep) void Cy_CTDAC_SetDeepSleepMode(CTDAC_Type *base, cy_en_ctdac_deep_sleep_t deepSleep)
{ {
@ -442,16 +476,27 @@ void Cy_CTDAC_SetDeepSleepMode(CTDAC_Type *base, cy_en_ctdac_deep_sleep_t deepSl
* Function Name: Cy_CTDAC_SetOutputMode * Function Name: Cy_CTDAC_SetOutputMode
****************************************************************************//** ****************************************************************************//**
* *
* Set the output mode to one of the supported options. * Set the output mode of the CTDAC:
* - \ref CY_CTDAC_OUTPUT_HIGHZ : Disable the output
* - \ref CY_CTDAC_OUTPUT_VALUE : Enable the output and drive the value
* stored in the CTDAC_VAL register.
* - \ref CY_CTDAC_OUTPUT_VALUE_PLUS1 : Enable the output and drive the
* value stored in the CTDAC_VAL register plus 1.
* - \ref CY_CTDAC_OUTPUT_VSSA : Output pulled to VSSA through 1.1 MOhm (typ) resistor.
* - \ref CY_CTDAC_OUTPUT_VREF : Output pulled to VREF through 1.1 MOhm (typ) resistor.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param outputMode * \param outputMode
* Output drive mode. See \ref cy_en_ctdac_output_mode_t for values. * Select a value from \ref cy_en_ctdac_output_mode_t.
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_OUTPUT_MODE
*
*******************************************************************************/ *******************************************************************************/
void Cy_CTDAC_SetOutputMode(CTDAC_Type *base, cy_en_ctdac_output_mode_t outputMode) void Cy_CTDAC_SetOutputMode(CTDAC_Type *base, cy_en_ctdac_output_mode_t outputMode)
{ {
@ -469,7 +514,8 @@ void Cy_CTDAC_SetOutputMode(CTDAC_Type *base, cy_en_ctdac_output_mode_t outputMo
* Function Name: Cy_CTDAC_SetDeglitchMode * Function Name: Cy_CTDAC_SetDeglitchMode
****************************************************************************//** ****************************************************************************//**
* *
* Set the deglitch mode or disable deglitching completely. * Enable deglitching on the unbuffered path, buffered path, both, or
* disable deglitching. The deglitch mode should match the configured output path.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
@ -479,6 +525,10 @@ void Cy_CTDAC_SetOutputMode(CTDAC_Type *base, cy_en_ctdac_output_mode_t outputMo
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_DEGLITCH_MODE
*
*******************************************************************************/ *******************************************************************************/
void Cy_CTDAC_SetDeglitchMode(CTDAC_Type *base, cy_en_ctdac_deglitch_t deglitchMode) void Cy_CTDAC_SetDeglitchMode(CTDAC_Type *base, cy_en_ctdac_deglitch_t deglitchMode)
{ {
@ -497,7 +547,10 @@ void Cy_CTDAC_SetDeglitchMode(CTDAC_Type *base, cy_en_ctdac_deglitch_t deglitchM
****************************************************************************//** ****************************************************************************//**
* *
* Set the number of deglitch cycles (0 to 63) that will be used. * Set the number of deglitch cycles (0 to 63) that will be used.
* To calculate the deglitch time, (DEGLITCH_CNT + 1) / PERI_CLOCK_FREQ. * To calculate the deglitch time:
*
* (DEGLITCH_CNT + 1) / PERI_CLOCK_FREQ
*
* The optimal deglitch time is 700 ns. * The optimal deglitch time is 700 ns.
* *
* \param base * \param base
@ -508,6 +561,10 @@ void Cy_CTDAC_SetDeglitchMode(CTDAC_Type *base, cy_en_ctdac_deglitch_t deglitchM
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_DEGLITCH_CYCLES
*
*******************************************************************************/ *******************************************************************************/
void Cy_CTDAC_SetDeglitchCycles(CTDAC_Type *base, uint32_t deglitchCycles) void Cy_CTDAC_SetDeglitchCycles(CTDAC_Type *base, uint32_t deglitchCycles)
{ {
@ -531,10 +588,14 @@ void Cy_CTDAC_SetDeglitchCycles(CTDAC_Type *base, uint32_t deglitchCycles)
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param refSource * \param refSource
* The reference source. See \ref cy_en_ctdac_ref_source_t for values. * The reference source. Select a value from \ref cy_en_ctdac_ref_source_t.
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_REF
*
*******************************************************************************/ *******************************************************************************/
void Cy_CTDAC_SetRef(CTDAC_Type *base, cy_en_ctdac_ref_source_t refSource) void Cy_CTDAC_SetRef(CTDAC_Type *base, cy_en_ctdac_ref_source_t refSource)
{ {
@ -558,27 +619,29 @@ void Cy_CTDAC_SetRef(CTDAC_Type *base, cy_en_ctdac_ref_source_t refSource)
* Function Name: Cy_CTDAC_SetAnalogSwitch * Function Name: Cy_CTDAC_SetAnalogSwitch
****************************************************************************//** ****************************************************************************//**
* *
* Provides firmware control of the CTDAC switches. Each call to this function * Provide firmware control of the CTDAC switches. Each call to this function
* can open a set of switches or close a set of switches. * can open a set of switches or close a set of switches.
* *
* This is an advanced function. The switches will be managed by the reference * \note
* source and output mode selections when initializing the hardware. * The switches are configured by the reference
* source and output mode selections during initialization.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param switchMask * \param switchMask
* The mask of the switches to either open or close. * The mask of the switches to either open or close.
* The switches can be found in the \ref cy_en_ctdac_switches_t enum. * Select one or more values from \ref cy_en_ctdac_switches_t and "OR" them together.
*
* For example, to close both CVD and CO6 switches:
* switchMask = CY_CTDAC_SWITCH_CVD_MASK | CY_CTDAC_SWITCH_CO6_MASK;
* *
* \param state * \param state
* Open or close the switches, see enum \ref cy_en_ctdac_switch_state_t. * Open or close the switche(s). Select a value from \ref cy_en_ctdac_switch_state_t.
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_ANALOG_SWITCH
*
*******************************************************************************/ *******************************************************************************/
void Cy_CTDAC_SetAnalogSwitch(CTDAC_Type *base, uint32_t switchMask, cy_en_ctdac_switch_state_t state) void Cy_CTDAC_SetAnalogSwitch(CTDAC_Type *base, uint32_t switchMask, cy_en_ctdac_switch_state_t state)
{ {
@ -612,13 +675,17 @@ void Cy_CTDAC_SetAnalogSwitch(CTDAC_Type *base, uint32_t switchMask, cy_en_ctdac
* \param callbackParams * \param callbackParams
* Pointer to structure of type \ref cy_stc_syspm_callback_params_t * Pointer to structure of type \ref cy_stc_syspm_callback_params_t
* *
* \return cy_en_syspm_status_t * \return
* See \ref cy_en_syspm_status_t * See \ref cy_en_syspm_status_t
* *
* \funcusage
*
* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_DEEP_SLEEP_CALLBACK
*
*******************************************************************************/ *******************************************************************************/
cy_en_syspm_status_t Cy_CTDAC_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams) cy_en_syspm_status_t Cy_CTDAC_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams)
{ {
/** Static variable preserved between function calls. /* Static variable preserved between function calls.
* Tracks the state of the deglitch mode before sleep so that it can be re-enabled after wakeup */ * Tracks the state of the deglitch mode before sleep so that it can be re-enabled after wakeup */
static uint32_t deglitchModeBeforeSleep; static uint32_t deglitchModeBeforeSleep;

434
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctdac/cy_ctdac.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctdac/cy_ctdac.h
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_ctdac.h * \file cy_ctdac.h
* \version 1.0 * \version 1.0.1
* *
* Header file for the CTDAC driver * Header file for the CTDAC driver
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -16,6 +16,26 @@
* \defgroup group_ctdac Continuous Time Digital to Analog Converter (CTDAC) * \defgroup group_ctdac Continuous Time Digital to Analog Converter (CTDAC)
* \{ * \{
* The CTDAC driver provides APIs to configure the 12-bit Continuous-Time DAC. * The CTDAC driver provides APIs to configure the 12-bit Continuous-Time DAC.
*
* - 12-bit continuous time output
* - 2 us settling time for a 25 pF load when output buffered through Opamp0 of \ref group_ctb "CTB"
* - Can be enabled in Deep Sleep power mode
* - Selectable voltage reference:
* - VDDA
* - Internal analog reference buffered through Opamp1 of \ref group_ctb "CTB"
* - External reference buffered through Opamp1 of \ref group_ctb "CTB"
* - Selectable output paths:
* - Direct DAC output to a pin
* - Buffered DAC output through Opamp0 of \ref group_ctb "CTB"
* - Sample and hold output path through Opamp0 of \ref group_ctb "CTB"
* - Selectable input modes:
* - Unsigned 12-bit mode
* - Virtual signed 12-bit mode
* - Configurable update rate using clock or strobe signal
* - Double buffered DAC voltage control register
* - Interrupt and DMA trigger on DAC buffer empty
* - Configurable as PGA along with Opamp1 of the \ref group_ctb "CTB"
*
* The CTDAC generates a 12-bit DAC output voltage from the reference. * The CTDAC generates a 12-bit DAC output voltage from the reference.
* The DAC reference can come from VDDA or from any signal buffered through Opamp0 * The DAC reference can come from VDDA or from any signal buffered through Opamp0
* of the CTB. This can be an external signal through a GPIO or from the internal * of the CTB. This can be an external signal through a GPIO or from the internal
@ -29,27 +49,6 @@
* \image html ctdac_block_diagram.png * \image html ctdac_block_diagram.png
* \image latex ctdac_block_diagram.png * \image latex ctdac_block_diagram.png
* *
* <b> Features </b>
*
* - 12-bit continuous time output
* - 2 us settling time for a 25 pF load
* - Can be enabled in Deep Sleep power mode
* - Selectable voltage reference:
* - VDDA
* - Internal analog reference buffered through Opamp1 of CTB
* - External reference buffered through Opamp1 of CTB
* - Selectable output paths:
* - Direct DAC output to a pin
* - Buffered DAC output through Opamp0 of CTB
* - Sample and hold output path through Opamp0 of CTB
* - Selectable input modes:
* - Unsigned 12-bit mode
* - Virtual signed 12-bit mode
* - Configurable update rate using clock or strobe signal
* - Double buffered DAC voltage control register
* - Interrupt and DMA trigger on DAC buffer empty
* - Configurable as PGA along with Opamp1 of the CTB
*
* The CTDAC has two switches, CO6 for configuring the output path and * The CTDAC has two switches, CO6 for configuring the output path and
* CVD for the reference source. * CVD for the reference source.
* *
@ -65,13 +64,15 @@
* enable the CTB block before enabling the CTDAC block. * enable the CTB block before enabling the CTDAC block.
* *
* The driver also provides a \ref Cy_CTDAC_FastInit function for fast and easy initialization of the CTDAC. * The driver also provides a \ref Cy_CTDAC_FastInit function for fast and easy initialization of the CTDAC.
* There are four configurations that cover the four combinations of the reference and output buffers. * The driver has pre-defined configuration structures for the four combinations of the reference and output buffers.
* *
* - \ref Cy_CTDAC_Fast_VddaRef_UnbufferedOut * - \ref Cy_CTDAC_Fast_VddaRef_UnbufferedOut
* - \ref Cy_CTDAC_Fast_VddaRef_BufferedOut * - \ref Cy_CTDAC_Fast_VddaRef_BufferedOut
* - \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut * - \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut
* - \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut * - \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut
* *
* After initialization, call \ref Cy_CTDAC_Enable to enable the hardware.
*
* \section group_ctdac_updatemode Update Modes * \section group_ctdac_updatemode Update Modes
* The CTDAC contains two registers: * The CTDAC contains two registers:
* -# CTDAC_VAL * -# CTDAC_VAL
@ -80,8 +81,8 @@
* This register is written with \ref Cy_CTDAC_SetValue. * This register is written with \ref Cy_CTDAC_SetValue.
* -# CTDAC_VAL_NXT * -# CTDAC_VAL_NXT
* *
* For buffered writes that can be configured to update the DAC at a * For buffered writes to update the DAC value at a
* selected periodic rate or with a strobe trigger. * periodic rate or with a strobe trigger input.
* This register is written with \ref Cy_CTDAC_SetValueBuffered. * This register is written with \ref Cy_CTDAC_SetValueBuffered.
* *
* The update mode is * The update mode is
@ -93,9 +94,9 @@
* This allows control of the buffered update timing from an external source, for example, by another * This allows control of the buffered update timing from an external source, for example, by another
* chip peripheral or from an off-chip source. * chip peripheral or from an off-chip source.
* *
* <b>Direct write</b> * \subsection group_ctdac_updatemode_direct_write Direct write
* *
* In this mode, this user writes directly into the CTDAC_VAL register * In this mode, the user writes directly into the CTDAC_VAL register
* using \ref Cy_CTDAC_SetValue. The action of writing to this register * using \ref Cy_CTDAC_SetValue. The action of writing to this register
* will update the DAC output. This mode does not generate an interrupt * will update the DAC output. This mode does not generate an interrupt
* or trigger signal. * or trigger signal.
@ -105,7 +106,7 @@
* \image html ctdac_update_mode_direct_write.png * \image html ctdac_update_mode_direct_write.png
* \image latex ctdac_update_mode_direct_write.png * \image latex ctdac_update_mode_direct_write.png
* *
* <b>Buffered write</b> * \subsection group_ctdac_updatemode_buffered_write Buffered write
* *
* In this mode, the user writes to the CTDAC_VAL_NXT register using * In this mode, the user writes to the CTDAC_VAL_NXT register using
* \ref Cy_CTDAC_SetValueBuffered. The rising edge of the clock * \ref Cy_CTDAC_SetValueBuffered. The rising edge of the clock
@ -113,26 +114,26 @@
* *
* Whenever data is transferred from the CTDAC_VAL_NXT register, * Whenever data is transferred from the CTDAC_VAL_NXT register,
* an interrupt is asserted the same time as the trigger. But while * an interrupt is asserted the same time as the trigger. But while
* the trigger is automatically cleared after two Peri Clock cycles, the * the trigger is automatically cleared after two PeriClk cycles, the
* user must clear the interrupt with \ref Cy_CTDAC_ClearInterrupt. * user must clear the interrupt with \ref Cy_CTDAC_ClearInterrupt.
* *
* \image html ctdac_update_mode_buffered_write.png * \image html ctdac_update_mode_buffered_write.png
* \image latex ctdac_update_mode_buffered_write.png * \image latex ctdac_update_mode_buffered_write.png
* *
* <b>Strobe edge sync</b> * \subsection group_ctdac_updatemode_strobe_edge_sync Strobe edge sync
* *
* In this mode, the user writes to the CTDAC_VAL_NXT register using * In this mode, the user writes to the CTDAC_VAL_NXT register using
* \ref Cy_CTDAC_SetValueBuffered. * \ref Cy_CTDAC_SetValueBuffered.
* Each rising edge of the DSI strobe input enables * Each rising edge of the DSI strobe input enables
* one subsequent update from the next rising edge of the clock. The DSI * one subsequent update from the next rising edge of the clock. The DSI
* input must remain high for two Peri Clock cycles and go low for * input must remain high for two PeriClk cycles and go low for
* another two Peri Clock cycles to allow for the next update. * another two PeriClk cycles to allow for the next update.
* This restricts the DSI strobe input frequency to the PeriClk frequency divided by four. * This restricts the DSI strobe input frequency to the PeriClk frequency divided by four.
* *
* \image html ctdac_update_mode_strobe_edge_sync.png * \image html ctdac_update_mode_strobe_edge_sync.png
* \image latex ctdac_update_mode_strobe_edge_sync.png * \image latex ctdac_update_mode_strobe_edge_sync.png
* *
* <b>Strobe edge immediate</b> * \subsection group_ctdac_updatemode_strobe_edge_immediate Strobe edge immediate
* *
* In this mode, the user writes to the CTDAC_VAL_NXT register using * In this mode, the user writes to the CTDAC_VAL_NXT register using
* \ref Cy_CTDAC_SetValueBuffered. * \ref Cy_CTDAC_SetValueBuffered.
@ -143,7 +144,7 @@
* \image html ctdac_update_mode_strobe_edge_immediate.png * \image html ctdac_update_mode_strobe_edge_immediate.png
* \image latex ctdac_update_mode_strobe_edge_immediate.png * \image latex ctdac_update_mode_strobe_edge_immediate.png
* *
* <b>Strobe level</b> * \subsection group_ctdac_updatemode_strobe_level Strobe level
* *
* In this mode, the user writes to the CTDAC_VAL_NXT register using * In this mode, the user writes to the CTDAC_VAL_NXT register using
* \ref Cy_CTDAC_SetValueBuffered. * \ref Cy_CTDAC_SetValueBuffered.
@ -155,35 +156,127 @@
* \image html ctdac_update_mode_strobe_level.png * \image html ctdac_update_mode_strobe_level.png
* \image latex ctdac_update_mode_strobe_level.png * \image latex ctdac_update_mode_strobe_level.png
* *
* \section group_ctdac_trigger DMA Trigger * \section group_ctdac_dacmode DAC Modes
* When data is transferred from the CTDAC_VAL_NXT to the CTDAC_VAL register *
* an interrupt and an output trigger signal are generated. * The format of code stored in the CTDAC_VAL register can either be unsigned
* The trigger signal can be routed to DMA using the \ref group_trigmux. * or signed two's complemented.
* Only the first 12 bits of the register are used by the DAC so there is
* no need for sign extension. With the signed format, the DAC decodes
* the code in the register by adding 0x800.
* The DAC can output the register value or the register value plus 1 (see \ref Cy_CTDAC_SetOutputMode).
*
* <table class="doxtable">
* <tr>
* <th>12-bit unsigned code</th>
* <th>12-bit two's complement signed code</th>
* <th>Vout (for \ref CY_CTDAC_OUTPUT_VALUE )</th>
* <th>Vout (for \ref CY_CTDAC_OUTPUT_VALUE_PLUS1 )</th>
* </tr>
* <tr>
* <td>0x000</td>
* <td>0x800</td>
* <td>0</td>
* <td>Vref/4096</td>
* </tr>
* <tr>
* <td>0x800</td>
* <td>0x000</td>
* <td>0.5 * Vref</td>
* <td>Vref * 2049 / 4096</td>
* </tr>
* <tr>
* <td>0xFFF</td>
* <td>0x7FF</td>
* <td>Vref * 4095 / 4096</td>
* <td>Vref</td>
* </tr>
* </table>
*
* The expressions in the above table are based on an unbuffered DAC output.
* When the output is buffered, the input and output range of the buffer will affect the
* output voltage. See \ref group_ctb_opamp_range in the CTB driver for more information.
*
* \section group_ctdac_trigger Interrupts and Trigger
*
* When data from the CTDAC_VAL_NXT is transferred to the CTDAC_VAL register,
* an interrupt and trigger output are generated. The trigger output can be
* used with a DMA block to update the CTDAC value register at high speeds without any CPU intervention.
* Alternatively, the interrupt output can be used when DMA is not available
* to update the CTDAC value register, but at a slower speed.
*
* Recall with the \ref group_ctdac_updatemode, the interrupt and trigger output are available in all modes except
* \ref group_ctdac_updatemode_direct_write.
*
* \subsection group_ctdac_dma_trigger DMA Trigger
*
* The CTDAC trigger output signal can be routed to a DMA block using the \ref group_trigmux
* to trigger an update to the CTDAC_VAL_NXT register.
* When making the required \ref Cy_TrigMux_Connect calls, use the pre-defined enums, TRIG14_IN_PASS_TR_CTDAC_EMPTY * When making the required \ref Cy_TrigMux_Connect calls, use the pre-defined enums, TRIG14_IN_PASS_TR_CTDAC_EMPTY
* and TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY. For example, * and TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY.
* *
* \code * \subsection group_ctdac_handling_interrupts Handling Interrupts
* (void)Cy_TrigMux_Connect(TRIG14_IN_PASS_TR_CTDAC_EMPTY, TRIG14_OUT_TR_GROUP0_INPUT50, CY_TR_MUX_TR_INV_DISABLE, TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY);
* (void)Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT7, TRIG0_OUT_CPUSS_DW0_TR_IN1, CY_TR_MUX_TR_INV_DISABLE, TRIGGER_TYPE_TR_GROUP_OUTPUT__LEVEL);
* \endcode
* *
* \section group_ctdac_code_example Complete Code Example * The following code snippet demonstrates how to implement a routine to handle the interrupt.
* The routine gets called when any CTDAC on the device generates an interrupt.
* *
* The following example code demonstrates how to generate a continuous * \snippet ctdac_sut_01.cydsn/main_cm0p.c SNIPPET_CTDAC_ISR
* sine wave using the CTDAC. The CTDAC uses both Opamps of the CTB
* to buffer the analog reference and to buffer the output to an external Pin 2.
* *
* \image html ctdac_code_example.png * The following code snippet demonstrates how to configure and enable the interrupt.
* \image latex ctdac_code_example.png
* *
* \code * \snippet ctdac_sut_01.cydsn/main_cm0p.c SNIPPET_CTDAC_INTR_SETUP
* #include "ctdac/cy_ctdac.h"
* #include "ctb/cy_ctb.h"
* #include "sysanalog/cy_sysanalog.h"
* #include "sysint/cy_sysint.h"
* \endcode
* *
* \snippet ctdac_sut_01.cydsn/main_cm0p.c CTDAC_CODE_EXAMPLE * \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_DMA_TRIGGER
*
* \section group_ctdac_deglitch Deglitch
*
* The hardware has the ability to deglitch the output value every time it is updated.
* This prevents small glitches in the DAC output during an update to propagate to
* the pin or opamp input. When deglitch is enabled, a switch on the output path
* is forced open for a configurable number of PeriClk cycles. This deglitch time
* is calculated as:
*
* (DEGLITCH_CNT + 1) / PERI_CLOCK_FREQ
*
* The optimal and recommended deglitch time is 700 ns. Call \ref Cy_CTDAC_SetDeglitchCycles to set DEGLITCH_CNT.
*
* There are two switches used for deglitching.
* - Switch COS in the CTB between the DAC output and the Opamp0 input
* - Switch CO6 in the CTDAC between the DAC output and external pin
*
* Call \ref Cy_CTDAC_SetDeglitchMode to set the deglitch path. Match this with the output buffer selection.
* If the output is buffered through the CTB, select \ref CY_CTDAC_DEGLITCHMODE_BUFFERED.
* If the output is unbuffered to a direct pin, select \ref CY_CTDAC_DEGLITCHMODE_UNBUFFERED.
*
* \note
* If deglitching is enabled, the hardware does not force the deglitch switches into a closed
* state during Deep Sleep mode. Therefore, there is a chance that the device enters
* Deep Sleep mode while the hardware is deglitching and the switches on the output path remain open.
* To ensure the DAC will operate properly in Deep Sleep when enabled, make sure to
* register the \ref Cy_CTDAC_DeepSleepCallback before entering Deep Sleep mode.
*
* \section group_ctdac_sample_hold Sample and Hold
*
* When buffering the DAC output, the CTB has a Sample and Hold (SH) feature that can be used for saving power.
* The DAC output voltage is retained on an internal capacitor for a duration of time while the
* DAC output can be turned off. The DAC hardware needs to be turned on in a periodic fashion
* to recharge the hold capacitor. This feature is firmware controlled using a sequence of function calls.
* See \ref Cy_CTB_DACSampleAndHold in the \ref group_ctb_sample_hold "CTB" driver.
*
* The hold time depends on the supply and reference voltages. The following hold times are based on the
* time it takes for the buffered output to change by 1 LSB.
*
* - Hold time = 750 us @ Vref = VDDA , VDDA = 1.7 V
* - Hold time = 525 us @ Vref = VDDA , VDDA = 3.6 V
* - Hold time = 200 us @ Vref = 1.2 V, VDDA = 3.6 V
*
* \section group_ctdac_low_power Low Power Support
*
* The CTDAC driver provides a callback function to handle power mode transitions.
* If the CTDAC is configured for Deep Sleep operation and \ref group_ctdac_deglitch "deglitching" is enabled,
* the callback \ref Cy_CTDAC_DeepSleepCallback must be registered before calling
* \ref Cy_SysPm_DeepSleep.
* Refer to \ref group_syspm driver for more information about power mode transitions and
* callback registration.
* *
* \section group_ctdac_more_information More Information * \section group_ctdac_more_information More Information
* *
@ -215,6 +308,11 @@
* <table class="doxtable"> * <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr> * <tr>
* <td>1.0.1</td>
* <td>Added low power support section. Minor documentation edits.</td>
* <td>Documentation update and clarification</td>
* </tr>
* <tr>
* <td>1.0</td> * <td>1.0</td>
* <td>Initial version</td> * <td>Initial version</td>
* <td></td> * <td></td>
@ -224,12 +322,14 @@
* \defgroup group_ctdac_macros Macros * \defgroup group_ctdac_macros Macros
* \defgroup group_ctdac_functions Functions * \defgroup group_ctdac_functions Functions
* \{ * \{
* \defgroup group_ctdac_functions_init Initialization Functions
* \defgroup group_ctdac_functions_basic Basic Configuration Functions
* \defgroup group_ctdac_functions_switches Switch Control Functions * \defgroup group_ctdac_functions_switches Switch Control Functions
* \defgroup group_ctdac_functions_interrupts Interrupt Functions * \defgroup group_ctdac_functions_interrupts Interrupt Functions
* \defgroup group_ctdac_functions_syspm_callback SysPm Deep Sleep Callback * \defgroup group_ctdac_functions_syspm_callback Low Power Callback
* \} * \}
* \defgroup group_ctdac_globals Global Variables * \defgroup group_ctdac_globals Global Variables
* \defgroup group_ctdac_data_structures Data structures * \defgroup group_ctdac_data_structures Data Structures
* \defgroup group_ctdac_enums Enumerated Types * \defgroup group_ctdac_enums Enumerated Types
*/ */
@ -265,16 +365,17 @@ extern "C" {
/** CTDAC driver identifier */ /** CTDAC driver identifier */
#define CY_CTDAC_ID CY_PDL_DRV_ID(0x19u) #define CY_CTDAC_ID CY_PDL_DRV_ID(0x19u)
/** \cond INTERNAL */
#define CY_CTDAC_DEINIT (0uL) /**< De-init value for CTDAC registers */ #define CY_CTDAC_DEINIT (0uL) /**< De-init value for CTDAC registers */
#define CY_CTDAC_DEINT_CTDAC_SW (CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk | CTDAC_CTDAC_SW_CLEAR_CTDO_CO6_Msk) /**< Mask for de-initializing the CTDAC switch control register */ #define CY_CTDAC_UNSIGNED_MID_CODE_VALUE (0x800uL) /**< Middle code value for unsigned values */
#define CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV (0uL) /**< Clock divider value for the Strobe Edge Immediate update mode */ #define CY_CTDAC_UNSIGNED_MAX_CODE_VALUE (0xFFFuL) /**< Maximum code value for unsigned values */
#define CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV_FRAC (0uL) /**< Clock fractional divider value for the Strobe Edge Immediate update mode */
#define CY_CTDAC_FAST_CLKCFG_TYPE CY_SYSCLK_DIV_8_BIT /**< Clock divider type for quick clock setup */ #define CY_CTDAC_FAST_CLKCFG_TYPE CY_SYSCLK_DIV_8_BIT /**< Clock divider type for quick clock setup */
#define CY_CTDAC_FAST_CLKCFG_NUM (0uL) /**< Clock divider number for quick clock setup */ #define CY_CTDAC_FAST_CLKCFG_NUM (0uL) /**< Clock divider number for quick clock setup */
#define CY_CTDAC_FAST_CLKCFG_DIV (99uL) /**< Clock divider integer value for quick clock setup. Divides PERI clock by 100. */ #define CY_CTDAC_FAST_CLKCFG_DIV (99uL) /**< Clock divider integer value for quick clock setup. Divides PERI clock by 100. */
#define CY_CTDAC_UNSIGNED_MID_CODE_VALUE (0x800uL) /**< Middle code value for unsigned values */
#define CY_CTDAC_UNSIGNED_MAX_CODE_VALUE (0xFFFuL) /**< Maximum code value for unsigned values */ /** \cond INTERNAL */
#define CY_CTDAC_DEINT_CTDAC_SW (CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk | CTDAC_CTDAC_SW_CLEAR_CTDO_CO6_Msk) /**< Mask for de-initializing the CTDAC switch control register */
#define CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV (0uL) /**< Clock divider value for the Strobe Edge Immediate update mode */
#define CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV_FRAC (0uL) /**< Clock fractional divider value for the Strobe Edge Immediate update mode */
#define CY_CTDAC_DEGLITCH_CYCLES_MAX (63uL) #define CY_CTDAC_DEGLITCH_CYCLES_MAX (63uL)
/**< Macros for conditions used by CY_ASSERT calls */ /**< Macros for conditions used by CY_ASSERT calls */
@ -311,7 +412,7 @@ extern "C" {
/** /**
* Configure the mode for how the DAC value is updated. * Configure the mode for how the DAC value is updated.
* All the modes require a CTDAC clock except for CY_CTDAC_UPDATE_DIRECT_WRITE. * All the modes require a CTDAC clock except for \ref group_ctdac_updatemode_direct_write.
*/ */
typedef enum { typedef enum {
CY_CTDAC_UPDATE_DIRECT_WRITE = 0uL, /**< DAC value is updated with a direct write by calling to \ref Cy_CTDAC_SetValue */ CY_CTDAC_UPDATE_DIRECT_WRITE = 0uL, /**< DAC value is updated with a direct write by calling to \ref Cy_CTDAC_SetValue */
@ -351,19 +452,8 @@ typedef enum {
}cy_en_ctdac_output_mode_t; }cy_en_ctdac_output_mode_t;
/** /**
* The CTDAC provides an option to deglitch the output value every time it is updated. * Configure the deglitch mode. See the \ref group_ctdac_deglitch section for
* This prevents small glitches in the DAC output during an update to propagate to * more information on how deglitching works.
* the pin or Opamp input. When deglitch is enabled, a switch on the output path
* is forced open for a configurable number of Peri Clock cycles. To calculate the deglitch
* time, (DEGLITCH_CNT + 1) / PERI_CLOCK_FREQ.
*
* There are two switches used for deglitching.
* - Switch COS in the CTB between the DAC output and the Opamp0 input
* - Switch CO6 in the CTDAC between the DAC output and external pin
*
* Match the deglitch path with the output buffer selection.
* If the output is buffered through the CTB, select CY_CTDAC_DEGLITCHMODE_BUFFERED.
* If the output is unbuffered to a direct pin, select CY_CTDAC_DEGLITCHMODE_UNBUFFERED.
*/ */
typedef enum { typedef enum {
CY_CTDAC_DEGLITCHMODE_NONE = 0uL, /**< Disable deglitch */ CY_CTDAC_DEGLITCHMODE_NONE = 0uL, /**< Disable deglitch */
@ -379,7 +469,7 @@ typedef enum {
* The CVD switch is closed when Vdda is the reference source. * The CVD switch is closed when Vdda is the reference source.
*/ */
typedef enum { typedef enum {
CY_CTDAC_REFSOURCE_EXTERNAL = 0uL, /**< Use an external source as the reference. CVD switch is open. */ CY_CTDAC_REFSOURCE_EXTERNAL = 0uL, /**< Use an external source from Opamp1 of the CTB as the reference. CVD switch is open. */
CY_CTDAC_REFSOURCE_VDDA = 1uL /**< Use Vdda as the reference. CVD switch is closed. */ CY_CTDAC_REFSOURCE_VDDA = 1uL /**< Use Vdda as the reference. CVD switch is closed. */
}cy_en_ctdac_ref_source_t; }cy_en_ctdac_ref_source_t;
@ -439,34 +529,33 @@ typedef struct
int32_t value; /**< Current DAC value */ int32_t value; /**< Current DAC value */
int32_t nextValue; /**< Next DAC value for double buffering */ int32_t nextValue; /**< Next DAC value for double buffering */
bool enableInterrupt; /**< If true, enable interrupt when next value register is transferred to value register */ bool enableInterrupt; /**< If true, enable interrupt when next value register is transferred to value register */
bool enable; /**< Enable or disable hardware after initialization */
/* Configuring the clock */ /* Configuring the clock */
bool configClock; /**< Configure or ignore clock information */ bool configClock; /**< Configure or ignore clock information */
cy_en_divider_types_t dividerType; /**< Specifies which type of divider to use. Can be integer or fractional divider. Not used if updateMode is CY_CTDAC_UPDATE_DIRECT_WRITE */ cy_en_divider_types_t dividerType; /**< Specifies which type of divider to use. Can be integer or fractional divider. Not used if updateMode is \ref CY_CTDAC_UPDATE_DIRECT_WRITE */
uint32_t dividerNum; /**< Specifies which divider of the selected type to configure. Not used if updateMode is CY_CTDAC_UPDATE_DIRECT_WRITE */ uint32_t dividerNum; /**< Specifies which divider of the selected type to configure. Not used if updateMode is \ref CY_CTDAC_UPDATE_DIRECT_WRITE */
uint32_t dividerIntValue; /**< The integer divider value. The divider value causes integer division of (divider value + 1). Not used if updateMode is CY_CTDAC_UPDATE_DIRECT_WRITE or CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE */ uint32_t dividerIntValue; /**< The integer divider value. The divider value causes integer division of (divider value + 1). Not used if updateMode is \ref CY_CTDAC_UPDATE_DIRECT_WRITE or \ref CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE */
uint32_t dividerFracValue; /**< The fractional divider value if using a fractional clock. Not used if updateMode is CY_CTDAC_UPDATE_DIRECT_WRITE or CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE */ uint32_t dividerFracValue; /**< The fractional divider value if using a fractional clock. Not used if updateMode is \ref CY_CTDAC_UPDATE_DIRECT_WRITE or \ref CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE */
}cy_stc_ctdac_config_t; }cy_stc_ctdac_config_t;
/** Configuration structure to quickly set up the CTDAC to be used with \ref Cy_CTDAC_FastInit /** Configuration structure to quickly set up the CTDAC to be used with \ref Cy_CTDAC_FastInit
* This structure provides a selection for the CTDAC reference source and output path. * This structure provides a selection for the CTDAC reference source and output path.
* *
* The other configuration options are set to: * The other configuration options are set to:
* - .formatMode = CY_CTDAC_FORMAT_UNSIGNED * - .formatMode = \ref CY_CTDAC_FORMAT_UNSIGNED
* - .updateMode = CY_CTDAC_UPDATE_BUFFERED_WRITE * - .updateMode = \ref CY_CTDAC_UPDATE_BUFFERED_WRITE
* - .deglitchMode = CY_CTDAC_DEGLITCHMODE_NONE * - .deglitchMode = \ref CY_CTDAC_DEGLITCHMODE_NONE
* - .outputMode = CY_CTDAC_OUTPUT_VALUE * - .outputMode = \ref CY_CTDAC_OUTPUT_VALUE
* - .deepSleep = CY_CTDAC_DEEPSLEEP_DISABLE * - .deepSleep = \ref CY_CTDAC_DEEPSLEEP_DISABLE
* - .deglitchCycles = CY_CTDAC_DEINIT * - .deglitchCycles = \ref CY_CTDAC_DEINIT
* - .value = CY_CTDAC_UNSIGNED_MID_CODE_VALUE * - .value = \ref CY_CTDAC_UNSIGNED_MID_CODE_VALUE
* - .nextValue = CY_CTDAC_UNSIGNED_MID_CODE_VALUE * - .nextValue = \ref CY_CTDAC_UNSIGNED_MID_CODE_VALUE
* - .enableInterrupt = true * - .enableInterrupt = true
* - .configClock = true * - .configClock = true
* - .dividerType = CY_CTDAC_FAST_CLKCFG_TYPE * - .dividerType = \ref CY_CTDAC_FAST_CLKCFG_TYPE
* - .dividerNum = CY_CTDAC_FAST_CLKCFG_NUM * - .dividerNum = \ref CY_CTDAC_FAST_CLKCFG_NUM
* - .dividerInitValue = CY_CTDAC_FAST_CLKCFG_DIV * - .dividerInitValue = \ref CY_CTDAC_FAST_CLKCFG_DIV
* - .dividerFracValue = CY_CTDAC_DEINIT * - .dividerFracValue = \ref CY_CTDAC_DEINIT
*/ */
typedef struct typedef struct
{ {
@ -530,11 +619,24 @@ extern const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_OA1Ref_BufferedOut;
* \addtogroup group_ctdac_functions * \addtogroup group_ctdac_functions
* \{ * \{
*/ */
/**
* \addtogroup group_ctdac_functions_init
* This set of functions are for initializing, enabling, and disabling the CTDAC.
* \{
*/
cy_en_ctdac_status_t Cy_CTDAC_Init(CTDAC_Type *base, const cy_stc_ctdac_config_t *config); cy_en_ctdac_status_t Cy_CTDAC_Init(CTDAC_Type *base, const cy_stc_ctdac_config_t *config);
cy_en_ctdac_status_t Cy_CTDAC_DeInit(CTDAC_Type *base, bool deInitRouting); cy_en_ctdac_status_t Cy_CTDAC_DeInit(CTDAC_Type *base, bool deInitRouting);
cy_en_ctdac_status_t Cy_CTDAC_FastInit(CTDAC_Type *base, const cy_stc_ctdac_fast_config_t *config); cy_en_ctdac_status_t Cy_CTDAC_FastInit(CTDAC_Type *base, const cy_stc_ctdac_fast_config_t *config);
__STATIC_INLINE void Cy_CTDAC_Enable(CTDAC_Type *base); __STATIC_INLINE void Cy_CTDAC_Enable(CTDAC_Type *base);
__STATIC_INLINE void Cy_CTDAC_Disable(CTDAC_Type *base); __STATIC_INLINE void Cy_CTDAC_Disable(CTDAC_Type *base);
/** \} */
/**
* \addtogroup group_ctdac_functions_basic
* This set of functions are for configuring basic usage of the CTDAC.
* \{
*/
__STATIC_INLINE void Cy_CTDAC_SetValue(CTDAC_Type *base, int32_t value); __STATIC_INLINE void Cy_CTDAC_SetValue(CTDAC_Type *base, int32_t value);
__STATIC_INLINE void Cy_CTDAC_SetValueBuffered(CTDAC_Type *base, int32_t value); __STATIC_INLINE void Cy_CTDAC_SetValueBuffered(CTDAC_Type *base, int32_t value);
void Cy_CTDAC_SetSignMode(CTDAC_Type *base, cy_en_ctdac_format_t formatMode); void Cy_CTDAC_SetSignMode(CTDAC_Type *base, cy_en_ctdac_format_t formatMode);
@ -543,6 +645,7 @@ void Cy_CTDAC_SetOutputMode(CTDAC_Type *base, cy_en_ctdac_output_mode_t outputMo
void Cy_CTDAC_SetDeglitchMode(CTDAC_Type *base, cy_en_ctdac_deglitch_t deglitchMode); void Cy_CTDAC_SetDeglitchMode(CTDAC_Type *base, cy_en_ctdac_deglitch_t deglitchMode);
void Cy_CTDAC_SetDeglitchCycles(CTDAC_Type *base, uint32_t deglitchCycles); void Cy_CTDAC_SetDeglitchCycles(CTDAC_Type *base, uint32_t deglitchCycles);
void Cy_CTDAC_SetRef(CTDAC_Type *base, cy_en_ctdac_ref_source_t refSource); void Cy_CTDAC_SetRef(CTDAC_Type *base, cy_en_ctdac_ref_source_t refSource);
/** \} */
/** \addtogroup group_ctdac_functions_switches /** \addtogroup group_ctdac_functions_switches
* *
@ -558,12 +661,12 @@ __STATIC_INLINE void Cy_CTDAC_OpenAllSwitches(CTDAC_Type *base);
/** \} */ /** \} */
/** \addtogroup group_ctdac_functions_interrupts /** \addtogroup group_ctdac_functions_interrupts
* This set of functions is related to the VDAC_EMPTY interrupt * This set of functions is related to the CTDAC interrupt
* \{ * \{
*/ */
__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatus(const CTDAC_Type *base); __STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatus(const CTDAC_Type *base);
__STATIC_INLINE void Cy_CTDAC_ClearInterrupt(CTDAC_Type *base); __STATIC_INLINE void Cy_CTDAC_ClearInterrupt(CTDAC_Type *base);
__STATIC_INLINE void Cy_CTDAC_SetSwInterrupt(CTDAC_Type *base); __STATIC_INLINE void Cy_CTDAC_SetInterrupt(CTDAC_Type *base);
__STATIC_INLINE void Cy_CTDAC_SetInterruptMask(CTDAC_Type *base, uint32_t mask); __STATIC_INLINE void Cy_CTDAC_SetInterruptMask(CTDAC_Type *base, uint32_t mask);
__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptMask(const CTDAC_Type *base); __STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptMask(const CTDAC_Type *base);
__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatusMasked(const CTDAC_Type *base); __STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatusMasked(const CTDAC_Type *base);
@ -576,11 +679,15 @@ __STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatusMasked(const CTDAC_Type *bas
cy_en_syspm_status_t Cy_CTDAC_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams); cy_en_syspm_status_t Cy_CTDAC_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams);
/** \} */ /** \} */
/**
* \addtogroup group_ctdac_functions_init
* \{
*/
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_CTDAC_Enable * Function Name: Cy_CTDAC_Enable
****************************************************************************//** ****************************************************************************//**
* *
* Powers up the CTDAC hardware block * Power up the CTDAC hardware block.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
@ -609,17 +716,26 @@ __STATIC_INLINE void Cy_CTDAC_Disable(CTDAC_Type *base)
{ {
base->CTDAC_CTRL &= ~CTDAC_CTDAC_CTRL_ENABLED_Msk; base->CTDAC_CTRL &= ~CTDAC_CTDAC_CTRL_ENABLED_Msk;
} }
/** \} */
/**
* \addtogroup group_ctdac_functions_basic
* \{
*/
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_CTDAC_SetValue * Function Name: Cy_CTDAC_SetValue
****************************************************************************//** ****************************************************************************//**
* *
* Set the CTDAC_VAL register (DAC hardware is * Set the CTDAC_VAL register (DAC hardware is
* updated on the next Peri clock cycle). Only the least significant 12 bits * updated on the next PeriClk cycle). Only the least significant 12 bits
* have an effect. Sign extension of negative values is unnecessary and is * have an effect. Sign extension of negative values is unnecessary and is
* ignored by the hardware. The way in which the CTDAC interprets the 12-bit * ignored by the hardware. The way in which the CTDAC interprets the 12-bit
* data is controlled by \ref Cy_CTDAC_SetSignMode. * data is controlled by \ref Cy_CTDAC_SetSignMode.
* *
* \note
* Call this function only when the update mode is set to \ref group_ctdac_updatemode_direct_write.
* Calling this function for any other update mode will not have the intended effect.
*
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
@ -628,6 +744,10 @@ __STATIC_INLINE void Cy_CTDAC_Disable(CTDAC_Type *base)
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_VALUE
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_CTDAC_SetValue(CTDAC_Type *base, int32_t value) __STATIC_INLINE void Cy_CTDAC_SetValue(CTDAC_Type *base, int32_t value)
{ {
@ -645,6 +765,10 @@ __STATIC_INLINE void Cy_CTDAC_SetValue(CTDAC_Type *base, int32_t value)
* ignored by the hardware. The way in which the CTDAC interprets the 12-bit * ignored by the hardware. The way in which the CTDAC interprets the 12-bit
* data is controlled by \ref Cy_CTDAC_SetSignMode. * data is controlled by \ref Cy_CTDAC_SetSignMode.
* *
* \note
* Calling this function in \ref group_ctdac_updatemode_direct_write mode will not update the DAC output.
* Call this function for all modes that use buffered values (i.e. uses a clock).
*
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
@ -653,30 +777,36 @@ __STATIC_INLINE void Cy_CTDAC_SetValue(CTDAC_Type *base, int32_t value)
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_VALUE_BUFFERED
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_CTDAC_SetValueBuffered(CTDAC_Type *base, int32_t value){ __STATIC_INLINE void Cy_CTDAC_SetValueBuffered(CTDAC_Type *base, int32_t value)
{
base->CTDAC_VAL_NXT = (((uint32_t)value) << CTDAC_CTDAC_VAL_NXT_VALUE_Pos) & CTDAC_CTDAC_VAL_NXT_VALUE_Msk; base->CTDAC_VAL_NXT = (((uint32_t)value) << CTDAC_CTDAC_VAL_NXT_VALUE_Pos) & CTDAC_CTDAC_VAL_NXT_VALUE_Msk;
} }
/** \} */
/** /**
* \addtogroup group_ctdac_functions_switches * \addtogroup group_ctdac_functions_switches
* \{ * \{
*/ */
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_CTDAC_GetAnalogSwitch * Function Name: Cy_CTDAC_GetAnalogSwitch
****************************************************************************//** ****************************************************************************//**
* *
* Gets the state (open or close) of CTDAC switches as a uint32_t value. * Return the state (open or close) of the CTDAC switches.
* *
* This is an advanced function. The switches will be managed by the reference * \note
* The switches will be managed by the reference
* source and output mode selections when initializing the hardware. * source and output mode selections when initializing the hardware.
*
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \return uint32_t * \return
* Compare the value to the switch masks found in \ref cy_en_ctdac_switches_t. * Switch state. Compare this value to the masks found in \ref cy_en_ctdac_switches_t.
* *
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_CTDAC_GetAnalogSwitch(const CTDAC_Type *base) __STATIC_INLINE uint32_t Cy_CTDAC_GetAnalogSwitch(const CTDAC_Type *base)
@ -689,14 +819,16 @@ __STATIC_INLINE uint32_t Cy_CTDAC_GetAnalogSwitch(const CTDAC_Type *base)
****************************************************************************//** ****************************************************************************//**
* *
* Open or close switch CO6 that controls whether the output gets routed * Open or close switch CO6 that controls whether the output gets routed
* directly to a pin or through Opamp0 of the CTB. * directly to a pin or through Opamp0 of the CTB. This function calls
* \ref Cy_CTDAC_SetAnalogSwitch with the switchMask set to \ref CY_CTDAC_SWITCH_CO6_MASK.
* *
* Note that this switch will temporarily * \note
* be opened for deglitching if DEGLITCHMODE_UNBUFFERED or DEGLITCHMODE_BOTH * The switches is configured by the output mode selections during initialization.
* is set in \ref Cy_CTDAC_SetDeglitchMode.
* *
* This is an advanced function. The switches will be managed by the reference * \note
* source and output mode selections when initializing the hardware. * This switch will temporarily
* be opened for deglitching if the degitch mode is \ref CY_CTDAC_DEGLITCHMODE_UNBUFFERED or
* \ref CY_CTDAC_DEGLITCHMODE_BOTH.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
@ -706,6 +838,10 @@ __STATIC_INLINE uint32_t Cy_CTDAC_GetAnalogSwitch(const CTDAC_Type *base)
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_SWITCH_CO6
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_CTDAC_SetSwitchCO6(CTDAC_Type *base, cy_en_ctdac_switch_state_t state) __STATIC_INLINE void Cy_CTDAC_SetSwitchCO6(CTDAC_Type *base, cy_en_ctdac_switch_state_t state)
{ {
@ -716,16 +852,17 @@ __STATIC_INLINE void Cy_CTDAC_SetSwitchCO6(CTDAC_Type *base, cy_en_ctdac_switch_
* Function Name: Cy_CTDAC_OpenAllSwitches * Function Name: Cy_CTDAC_OpenAllSwitches
****************************************************************************//** ****************************************************************************//**
* *
* Open all switches. * Open all switches in the CTDAC (CO6 and CVD).
*
* This is an advanced function. The switches will be managed by the reference
* source and output mode selections when initializing the hardware.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_OPEN_ALL_SWITCHES
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_CTDAC_OpenAllSwitches(CTDAC_Type *base) __STATIC_INLINE void Cy_CTDAC_OpenAllSwitches(CTDAC_Type *base)
{ {
@ -742,18 +879,23 @@ __STATIC_INLINE void Cy_CTDAC_OpenAllSwitches(CTDAC_Type *base)
* Function Name: Cy_CTDAC_GetInterruptStatus * Function Name: Cy_CTDAC_GetInterruptStatus
****************************************************************************//** ****************************************************************************//**
* *
* Returns the interrupt status which gets set by the hardware * Return the interrupt status which gets set by the hardware
* when the CTDAC_VAL_NXT register value is transferred to the CTDAC_VAL register. * when the CTDAC_VAL_NXT register value is transferred to the CTDAC_VAL register.
* Once set, the CTDAC_VAL_NXT register is ready to accept a new value. * Once set, the CTDAC_VAL_NXT register is ready to accept a new value.
* *
* Interrupts are available in all update modes except \ref CY_CTDAC_UPDATE_DIRECT_WRITE. * \note
* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \return * \return
* 0 = Value not moved from CTDAC_VAL_NXT to CTDAC_VAL * - 0: Value not moved from CTDAC_VAL_NXT to CTDAC_VAL
* 1 = Value moved from CTDAC_VAL_NXT to CTDAC_VAL * - 1: Value moved from CTDAC_VAL_NXT to CTDAC_VAL
*
* \funcusage
*
* \snippet ctdac_sut_01.cydsn/main_cm0p.c SNIPPET_CTDAC_GET_INTERRUPT_STATUS
* *
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatus(const CTDAC_Type *base) __STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatus(const CTDAC_Type *base)
@ -765,13 +907,14 @@ __STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatus(const CTDAC_Type *base)
* Function Name: Cy_CTDAC_ClearInterrupt * Function Name: Cy_CTDAC_ClearInterrupt
****************************************************************************//** ****************************************************************************//**
* *
* Clears the interrupt that was set by the hardware when the * Clear the interrupt that was set by the hardware when the
* CTDAC_VAL_NXT register value is transferred to the CTDAC_VAL register. * CTDAC_VAL_NXT register value is transferred to the CTDAC_VAL register.
* The interrupt must be cleared with this function so that * The interrupt must be cleared with this function so that
* the hardware can set subsequent interrupts and those interrupts * the hardware can set subsequent interrupts and those interrupts
* can be forwarded to the interrupt controller, if enabled. * can be forwarded to the interrupt controller, if enabled.
* *
* Interrupts are available in all update modes except \ref CY_CTDAC_UPDATE_DIRECT_WRITE. * \note
* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
@ -782,15 +925,19 @@ __STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatus(const CTDAC_Type *base)
__STATIC_INLINE void Cy_CTDAC_ClearInterrupt(CTDAC_Type *base) __STATIC_INLINE void Cy_CTDAC_ClearInterrupt(CTDAC_Type *base)
{ {
base->INTR = CTDAC_INTR_VDAC_EMPTY_Msk; base->INTR = CTDAC_INTR_VDAC_EMPTY_Msk;
/* Dummy read for buffered writes. */
(void) base->INTR;
} }
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_CTDAC_SetSwInterrupt * Function Name: Cy_CTDAC_SetInterrupt
****************************************************************************//** ****************************************************************************//**
* *
* Forces the CTDAC interrupt to trigger using software. * Force the CTDAC interrupt to trigger using software.
* *
* Interrupts are available in all update modes except \ref CY_CTDAC_UPDATE_DIRECT_WRITE. * \note
* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
@ -798,7 +945,7 @@ __STATIC_INLINE void Cy_CTDAC_ClearInterrupt(CTDAC_Type *base)
* \return None * \return None
* *
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_CTDAC_SetSwInterrupt(CTDAC_Type *base) __STATIC_INLINE void Cy_CTDAC_SetInterrupt(CTDAC_Type *base)
{ {
base->INTR_SET = CTDAC_INTR_SET_VDAC_EMPTY_SET_Msk; base->INTR_SET = CTDAC_INTR_SET_VDAC_EMPTY_SET_Msk;
} }
@ -810,17 +957,23 @@ __STATIC_INLINE void Cy_CTDAC_SetSwInterrupt(CTDAC_Type *base)
* Configure the CTDAC interrupt to be forwarded to the CPU interrupt * Configure the CTDAC interrupt to be forwarded to the CPU interrupt
* controller. * controller.
* *
* Interrupts are available in all update modes except \ref CY_CTDAC_UPDATE_DIRECT_WRITE. * \note
* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param mask * \param mask
* 0: Disable CTDAC interrupt request (will not be forwarded to CPU interrupt controller) * The CTDAC only has one interrupt so the mask is one bit.
* 1: Enable CTDAC interrupt request (will be forwarded to CPU interrupt controller) * - 0: Disable CTDAC interrupt request (will not be forwarded to CPU interrupt controller)
* - 1: Enable CTDAC interrupt request (will be forwarded to CPU interrupt controller)
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet ctdac_sut_01.cydsn/main_cm0p.c SNIPPET_CTDAC_SET_INTERRUPT_MASK
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_CTDAC_SetInterruptMask(CTDAC_Type *base, uint32_t mask) __STATIC_INLINE void Cy_CTDAC_SetInterruptMask(CTDAC_Type *base, uint32_t mask)
{ {
@ -833,18 +986,20 @@ __STATIC_INLINE void Cy_CTDAC_SetInterruptMask(CTDAC_Type *base, uint32_t mask)
* Function Name: Cy_CTDAC_GetInterruptMask * Function Name: Cy_CTDAC_GetInterruptMask
****************************************************************************//** ****************************************************************************//**
* *
* Returns whether the CTDAC interrupt is * Return whether the CTDAC interrupt is
* forwarded to the CPU interrupt controller * forwarded to the CPU interrupt controller
* as configured by \ref Cy_CTDAC_SetInterruptMask. * as configured by \ref Cy_CTDAC_SetInterruptMask.
* *
* Interrupts are available in all update modes except \ref CY_CTDAC_UPDATE_DIRECT_WRITE. * \note
* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \return * \return
* 0 = Interrupt output not forwarded to CPU interrupt controller * The CTDAC only has one interrupt so the return value is either 0 or 1.
* 1 = Interrupt output forwarded to CPU interrupt controller * - 0: Interrupt output not forwarded to CPU interrupt controller
* - 1: Interrupt output forwarded to CPU interrupt controller
* *
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptMask(const CTDAC_Type *base) __STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptMask(const CTDAC_Type *base)
@ -856,19 +1011,20 @@ __STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptMask(const CTDAC_Type *base)
* Function Name: Cy_CTDAC_GetInterruptStatusMasked * Function Name: Cy_CTDAC_GetInterruptStatusMasked
****************************************************************************//** ****************************************************************************//**
* *
* Returns the bitwise AND of \ref Cy_CTDAC_GetInterruptStatus and * Return the bitwise AND of \ref Cy_CTDAC_GetInterruptStatus and
* \ref Cy_CTDAC_SetInterruptMask. When high, the DAC interrupt is * \ref Cy_CTDAC_SetInterruptMask. When high, the DAC interrupt is
* asserted and the interrupt is forwarded to the CPU interrupt * asserted and the interrupt is forwarded to the CPU interrupt
* controller. * controller.
* *
* Interrupts are available in all update modes except \ref CY_CTDAC_UPDATE_DIRECT_WRITE. * \note
* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \return * \return
* 0 = Value not moved from CTDAC_VAL_NXT to CTDAC_VAL or not masked * - 0: Value not moved from CTDAC_VAL_NXT to CTDAC_VAL or not masked
* 1 = Value moved from CTDAC_VAL_NXT to CTDAC_VAL and masked * - 1: Value moved from CTDAC_VAL_NXT to CTDAC_VAL and masked
* *
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatusMasked(const CTDAC_Type *base){ __STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatusMasked(const CTDAC_Type *base){

103
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/dma/cy_dma.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/dma/cy_dma.c
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@ -1,13 +1,13 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_dma.c * \file cy_dma.c
* \version 2.0 * \version 2.0.1
* *
* \brief * \brief
* The source code file for the DMA driver. * The source code file for the DMA driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -24,12 +24,12 @@ extern "C" {
* Function Name: Cy_DMA_Descriptor_Init * Function Name: Cy_DMA_Descriptor_Init
****************************************************************************//** ****************************************************************************//**
* *
* Initializes descriptor structure in SRAM from a pre-initialized * Initializes the descriptor structure in SRAM from a pre-initialized
* configuration structure. * configuration structure.
* This function initializes only the descriptor and not the channel. * This function initializes only the descriptor and not the channel.
* *
* \param descriptor * \param descriptor
* A descriptor structure instance declared by user/component. * The descriptor structure instance declared by the user/component.
* *
* \param config * \param config
* This is a configuration structure that has all initialization information for * This is a configuration structure that has all initialization information for
@ -86,6 +86,7 @@ cy_en_dma_status_t Cy_DMA_Descriptor_Init(cy_stc_dma_descriptor_t * descriptor,
descriptor->xCtl = descriptor->xCtl =
_VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcXincrement) | _VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcXincrement) |
_VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstXincrement) | _VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstXincrement) |
/* Convert the data count from the user's range (1-256) into the machine range (0-255). */
_VAL2FLD(CY_DMA_CTL_COUNT, config->xCount - 1UL); _VAL2FLD(CY_DMA_CTL_COUNT, config->xCount - 1UL);
descriptor->yCtl = (uint32_t)config->nextDescriptor; descriptor->yCtl = (uint32_t)config->nextDescriptor;
@ -103,11 +104,13 @@ cy_en_dma_status_t Cy_DMA_Descriptor_Init(cy_stc_dma_descriptor_t * descriptor,
descriptor->xCtl = descriptor->xCtl =
_VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcXincrement) | _VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcXincrement) |
_VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstXincrement) | _VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstXincrement) |
/* Convert the data count from the user's range (1-256) into the machine range (0-255). */
_VAL2FLD(CY_DMA_CTL_COUNT, config->xCount - 1UL); _VAL2FLD(CY_DMA_CTL_COUNT, config->xCount - 1UL);
descriptor->yCtl = descriptor->yCtl =
_VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcYincrement) | _VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcYincrement) |
_VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstYincrement) | _VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstYincrement) |
/* Convert the data count from the user's range (1-256) into the machine range (0-255). */
_VAL2FLD(CY_DMA_CTL_COUNT, config->yCount - 1UL); _VAL2FLD(CY_DMA_CTL_COUNT, config->yCount - 1UL);
descriptor->nextPtr = (uint32_t)config->nextDescriptor; descriptor->nextPtr = (uint32_t)config->nextDescriptor;
@ -115,7 +118,7 @@ cy_en_dma_status_t Cy_DMA_Descriptor_Init(cy_stc_dma_descriptor_t * descriptor,
} }
default: default:
{ {
/* Unsupported type of descriptor */ /* An unsupported type of a descriptor */
break; break;
} }
} }
@ -131,10 +134,10 @@ cy_en_dma_status_t Cy_DMA_Descriptor_Init(cy_stc_dma_descriptor_t * descriptor,
* Function Name: Cy_DMA_Descriptor_DeInit * Function Name: Cy_DMA_Descriptor_DeInit
****************************************************************************//** ****************************************************************************//**
* *
* Clears all the content of the specified descriptor. * Clears the content of the specified descriptor.
* *
* \param descriptor * \param descriptor
* A descriptor structure instance declared by user/component. * The descriptor structure instance declared by the user/component.
* *
*******************************************************************************/ *******************************************************************************/
void Cy_DMA_Descriptor_DeInit(cy_stc_dma_descriptor_t * descriptor) void Cy_DMA_Descriptor_DeInit(cy_stc_dma_descriptor_t * descriptor)
@ -155,13 +158,13 @@ void Cy_DMA_Descriptor_DeInit(cy_stc_dma_descriptor_t * descriptor)
* Initializes the DMA channel with a descriptor and other parameters. * Initializes the DMA channel with a descriptor and other parameters.
* *
* \param base * \param base
* A pointer to the hardware DMA block. * The pointer to the hardware DMA block.
* *
* \param channel * \param channel
* A channel number. * A channel number.
* *
* \param channelConfig * \param channelConfig
* A structure that has the initialization information for the * The structure that has the initialization information for the
* channel. * channel.
* *
* \return * \return
@ -174,22 +177,16 @@ cy_en_dma_status_t Cy_DMA_Channel_Init(DW_Type * base, uint32_t channel, cy_stc_
if (((CY_DMA_IS_DW_CH_NR_VALID(base, channel)) && (NULL != channelConfig) && (NULL != channelConfig->descriptor))) if (((CY_DMA_IS_DW_CH_NR_VALID(base, channel)) && (NULL != channelConfig) && (NULL != channelConfig->descriptor)))
{ {
uint32_t regVal;
CY_ASSERT_L2(CY_DMA_IS_PRIORITY_VALID(channelConfig->priority)); CY_ASSERT_L2(CY_DMA_IS_PRIORITY_VALID(channelConfig->priority));
/* Set current descriptor */ /* Set the current descriptor */
base->CH_STRUCT[channel].CH_CURR_PTR = (uint32_t)channelConfig->descriptor; base->CH_STRUCT[channel].CH_CURR_PTR = (uint32_t)channelConfig->descriptor;
/* Set if the channel is preemtable */ /* Set the channel configuration */
regVal = base->CH_STRUCT[channel].CH_CTL & ((uint32_t) ~(DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Msk | base->CH_STRUCT[channel].CH_CTL = _BOOL2FLD(DW_CH_STRUCT_CH_CTL_PREEMPTABLE, channelConfig->preemptable) |
DW_CH_STRUCT_CH_CTL_PRIO_Msk |
DW_CH_STRUCT_CH_CTL_ENABLED_Msk));
base->CH_STRUCT[channel].CH_CTL = regVal | _BOOL2FLD(DW_CH_STRUCT_CH_CTL_PREEMPTABLE, channelConfig->preemptable) |
_VAL2FLD(DW_CH_STRUCT_CH_CTL_PRIO, channelConfig->priority) | _VAL2FLD(DW_CH_STRUCT_CH_CTL_PRIO, channelConfig->priority) |
_BOOL2FLD(DW_CH_STRUCT_CH_CTL_ENABLED, channelConfig->enable); _BOOL2FLD(DW_CH_STRUCT_CH_CTL_ENABLED, channelConfig->enable) |
_BOOL2FLD(DW_CH_STRUCT_CH_CTL_B, channelConfig->bufferable);
retVal = CY_DMA_SUCCESS; retVal = CY_DMA_SUCCESS;
} }
@ -201,10 +198,10 @@ cy_en_dma_status_t Cy_DMA_Channel_Init(DW_Type * base, uint32_t channel, cy_stc_
* Function Name: Cy_DMA_Channel_DeInit * Function Name: Cy_DMA_Channel_DeInit
****************************************************************************//** ****************************************************************************//**
* *
* Clears all the content of registers corresponding to the channel. * Clears the content of registers corresponding to the channel.
* *
* \param base * \param base
* A pointer to the hardware DMA block. * The pointer to the hardware DMA block.
* *
* \param channel * \param channel
* A channel number. * A channel number.
@ -227,13 +224,13 @@ void Cy_DMA_Channel_DeInit(DW_Type * base, uint32_t channel)
* *
* Sets a Next Descriptor parameter for the specified descriptor. * Sets a Next Descriptor parameter for the specified descriptor.
* *
* Based on descriptor type the offset of address for the next descriptor may * Based on the descriptor type, the offset of the address for the next descriptor may
* vary. For a single transfer descriptor type, this register is at offset 0x0c. * vary. For the single-transfer descriptor type, this register is at offset 0x0c.
* For a 1D transfer descriptor type, this register is at offset 0x10. For a 2D * For the 1D-transfer descriptor type, this register is at offset 0x10.
* transfer descriptor type, this register is at offset 0x14. * For the 2D-transfer descriptor type, this register is at offset 0x14.
* *
* \param descriptor * \param descriptor
* A descriptor structure instance declared by user/component. * The descriptor structure instance declared by the user/component.
* *
* \param nextDescriptor * \param nextDescriptor
* The pointer to the next descriptor. * The pointer to the next descriptor.
@ -270,13 +267,13 @@ void Cy_DMA_Descriptor_SetNextDescriptor(cy_stc_dma_descriptor_t * descriptor, c
* *
* Returns a next descriptor address of the specified descriptor. * Returns a next descriptor address of the specified descriptor.
* *
* Based on descriptor type the offset of address for the next descriptor may * Based on the descriptor type, the offset of the address for the next descriptor may
* vary. For a single transfer descriptor type, this register is at offset 0x0c. * vary. For a single-transfer descriptor type, this register is at offset 0x0c.
* For a 1D transfer descriptor type, this register is at offset 0x10. For a 2D * For the 1D-transfer descriptor type, this register is at offset 0x10.
* transfer descriptor type, this register is at offset 0x14. * For the 2D-transfer descriptor type, this register is at offset 0x14.
* *
* \param descriptor * \param descriptor
* A descriptor structure instance declared by user/component. * The descriptor structure instance declared by the user/component.
* *
* \return * \return
* The pointer to the next descriptor. * The pointer to the next descriptor.
@ -303,7 +300,7 @@ cy_stc_dma_descriptor_t * Cy_DMA_Descriptor_GetNextDescriptor(cy_stc_dma_descrip
break; break;
default: default:
/* Unsupported type of descriptor */ /* An unsupported type of the descriptor */
break; break;
} }
@ -311,6 +308,46 @@ cy_stc_dma_descriptor_t * Cy_DMA_Descriptor_GetNextDescriptor(cy_stc_dma_descrip
} }
/*******************************************************************************
* Function Name: Cy_DMA_Descriptor_SetDescriptorType
****************************************************************************//**
*
* Sets the descriptor's type for the specified descriptor.
* Moves the next descriptor register value into the proper place in accordance
* to the actual descriptor type.
* During the descriptor's type changing, the Xloop and Yloop settings, such as
* data count and source/destination increment (i.e. the content of the
* xCtl and yCtl descriptor registers) might be lost (overriden by the
* next descriptor value) because of the different descriptor registers structures
* for different descriptor types. Set up carefully the Xloop
* (and Yloop, if used) data count and source/destination increment if the
* descriptor type is changed from a simpler to a more complicated type
* ("single transfer" -> "1D", "1D" -> "2D", etc.).
*
* \param descriptor
* The descriptor structure instance declared by the user/component.
*
* \param descriptorType
* The descriptor type \ref cy_en_dma_descriptor_type_t.
*
*******************************************************************************/
void Cy_DMA_Descriptor_SetDescriptorType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_descriptor_type_t descriptorType)
{
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L3(CY_DMA_IS_TYPE_VALID(descriptorType));
if (descriptorType != Cy_DMA_Descriptor_GetDescriptorType(descriptor)) /* Don't perform if the type is not changed */
{
/* Store the current nextDescriptor pointer. */
cy_stc_dma_descriptor_t * locNextDescriptor = Cy_DMA_Descriptor_GetNextDescriptor(descriptor);
/* Change the descriptor type. */
descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_TYPE, descriptorType);
/* Restore the nextDescriptor pointer into the proper place. */
Cy_DMA_Descriptor_SetNextDescriptor(descriptor, locNextDescriptor);
}
}
#if defined(__cplusplus) #if defined(__cplusplus)
} }
#endif #endif

455
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/dma/cy_dma.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/dma/cy_dma.h
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File diff suppressed because it is too large Load Diff

227
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/efuse/cy_efuse.c Normal file
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@ -0,0 +1,227 @@
/***************************************************************************//**
* \file cy_efuse.c
* \version 1.0
*
* \brief
* Provides API implementation of the eFuse driver.
*
********************************************************************************
* \copyright
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cy_efuse.h"
#include "ipc/cy_ipc_drv.h"
/** \cond INTERNAL */
#define CY_EFUSE_OPCODE_SUCCESS (0xA0000000UL) /**< The command completed with no errors */
#define CY_EFUSE_OPCODE_STS_Msk (0xF0000000UL) /**< The status mask of the SROM API return value */
#define CY_EFUSE_OPCODE_INV_PROT (0xF0000001UL) /**< The API is not available in the current protection state */
#define CY_EFUSE_OPCODE_INV_ADDR (0xF0000002UL) /**< An attempt to read byte from the out-of-bond or protected eFuse region */
#define CY_EFUSE_OPCODE_READ_FUSE_BYTE (0x03000000UL) /**< The SROM API opcode for Read fuse byte operation */
#define CY_EFUSE_OPCODE_OFFSET_Pos (8UL) /**< A fuse byte offset position in an opcode */
#define CY_EFUSE_OPCODE_DATA_Msk (0xFFUL) /**< The mask for extracting data from the SROM API return value */
#define CY_EFUSE_IPC_STRUCT (Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL)) /**< IPC structure to be used */
#define CY_EFUSE_IPC_NOTIFY_STRUCT0 (0x1UL << CY_IPC_INTR_SYSCALL1) /**< IPC notify bit for IPC_STRUCT0 (dedicated to System Call) */
/** \endcond */
static volatile uint32_t opcode;
static cy_en_efuse_status_t ProcessOpcode(void);
/*******************************************************************************
* Function Name: Cy_EFUSE_GetEfuseBit
****************************************************************************//**
*
* Reports the current state of a given eFuse bit-number. Consult the device TRM
* to determine the target fuse bit number.
*
* \note An attempt to read an eFuse data from a protected memory region
* will generate a HardFault.
*
* \param bitNum
* The number of the bit to read. The valid range of the bit number is
* from 0 to EFUSE_EFUSE_NR * 32 * 8 - 1 where:
* - EFUSE_EFUSE_NR is number of efuse macros in the selected device series,
* - 32 is a number of fuse bytes in one efuse macro,
* - 8 is a number of fuse bits in the byte.
*
* The EFUSE_EFUSE_NR macro is defined in the series-specific header file, e.g
* \e \<PDL_DIR\>/devices/psoc6/psoc63/include/psoc63_config.\e h
*
* \param bitVal
* The pointer to the location to store the bit value.
*
* \return
* \ref cy_en_efuse_status_t
*
* \funcusage
* The example below shows how to read device life-cycle register bits in
* PSoC 6:
* \snippet eFuse_v1_0_sut_00.cydsn/main_cm0p.c SNIPPET_EFUSE_READ_BIT
*
*******************************************************************************/
cy_en_efuse_status_t Cy_EFUSE_GetEfuseBit(uint32_t bitNum, bool *bitVal)
{
cy_en_efuse_status_t result = CY_EFUSE_BAD_PARAM;
if (bitVal != NULL)
{
uint32_t offset = bitNum / CY_EFUSE_BITS_PER_BYTE;
uint8_t byteVal;
*bitVal = false;
/* Read the eFuse byte */
result = Cy_EFUSE_GetEfuseByte(offset, &byteVal);
if (result == CY_EFUSE_SUCCESS)
{
uint32_t bitPos = bitNum % CY_EFUSE_BITS_PER_BYTE;
/* Extract the bit from the byte */
*bitVal = (((byteVal >> bitPos) & 0x01U) != 0U);
}
}
return (result);
}
/*******************************************************************************
* Function Name: Cy_EFUSE_GetEfuseByte
****************************************************************************//**
*
* Reports the current state of the eFuse byte.
* If the offset parameter is beyond the available quantities,
* zeroes will be stored to the byteVal parameter. Consult the device TRM
* to determine the target fuse byte offset.
*
* \note An attempt to read an eFuse data from a protected memory region
* will generate a HardFault.
*
* \param offset
* The offset of the byte to read. The valid range of the byte offset is
* from 0 to EFUSE_EFUSE_NR * 32 - 1 where:
* - EFUSE_EFUSE_NR is a number of efuse macros in the selected device series,
* - 32 is a number of fuse bytes in one efuse macro.
*
* The EFUSE_EFUSE_NR macro is defined in the series-specific header file, e.g
* \e \<PDL_DIR\>/devices/psoc6/psoc63/include/psoc63_config.\e h
*
* \param byteVal
* The pointer to the location to store eFuse data.
*
* \return
* \ref cy_en_efuse_status_t
*
* \funcusage
* The example below shows how to read a device life-cycle stage register in
* PSoC 6:
* \snippet eFuse_v1_0_sut_00.cydsn/main_cm0p.c SNIPPET_EFUSE_READ_LIFECYCLE
*
*******************************************************************************/
cy_en_efuse_status_t Cy_EFUSE_GetEfuseByte(uint32_t offset, uint8_t *byteVal)
{
cy_en_efuse_status_t result = CY_EFUSE_BAD_PARAM;
if (byteVal != NULL)
{
/* Prepare opcode before calling the SROM API */
opcode = CY_EFUSE_OPCODE_READ_FUSE_BYTE | (offset << CY_EFUSE_OPCODE_OFFSET_Pos);
/* Send the IPC message */
if (Cy_IPC_Drv_SendMsgPtr(CY_EFUSE_IPC_STRUCT, CY_EFUSE_IPC_NOTIFY_STRUCT0, (void*)&opcode) == CY_IPC_DRV_SUCCESS)
{
/* Wait until the IPC structure is locked */
while(Cy_IPC_Drv_IsLockAcquired(CY_EFUSE_IPC_STRUCT) != false)
{
}
/* The result of the SROM API call is returned to the opcode variable */
if ((opcode & CY_EFUSE_OPCODE_STS_Msk) == CY_EFUSE_OPCODE_SUCCESS)
{
*byteVal = (uint8_t)(opcode & CY_EFUSE_OPCODE_DATA_Msk);
result = CY_EFUSE_SUCCESS;
}
else
{
result = ProcessOpcode();
*byteVal = 0U;
}
}
else
{
result = CY_EFUSE_IPC_BUSY;
}
}
return (result);
}
/*******************************************************************************
* Function Name: Cy_EFUSE_GetExternalStatus
****************************************************************************//**
*
* This function handles the case where a module such as a security image captures
* a system call from this driver and reports its own status or error code,
* for example, protection violation. In that case, a function from this
* driver returns an unknown error (see \ref cy_en_efuse_status_t). After receipt
* of an unknown error, the user may call this function to get the status
* of the capturing module.
*
* The user is responsible for parsing the content of the returned value
* and casting it to the appropriate enumeration.
*
* \return
* The error code of the previous efuse operation.
*
*******************************************************************************/
uint32_t Cy_EFUSE_GetExternalStatus(void)
{
return (opcode);
}
/*******************************************************************************
* Function Name: ProcessOpcode
****************************************************************************//**
*
* Converts System Call returns to the eFuse driver return defines. If
* an unknown error was returned, the error code can be accessed via the
* Cy_EFUSE_GetExternalStatus() function.
*
* \param opcode The value returned by a System Call.
*
* \return
* \ref cy_en_efuse_status_t
*
*******************************************************************************/
static cy_en_efuse_status_t ProcessOpcode(void)
{
cy_en_efuse_status_t result;
switch(opcode)
{
case CY_EFUSE_OPCODE_INV_PROT :
{
result = CY_EFUSE_INVALID_PROTECTION;
break;
}
case CY_EFUSE_OPCODE_INV_ADDR :
{
result = CY_EFUSE_INVALID_FUSE_ADDR;
break;
}
default :
{
result = CY_EFUSE_ERR_UNC;
break;
}
}
return (result);
}
/* [] END OF FILE */

180
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/efuse/cy_efuse.h Normal file
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@ -0,0 +1,180 @@
/***************************************************************************//**
* \file cy_efuse.h
* \version 1.0
*
* Provides the API declarations of the eFuse driver.
*
********************************************************************************
* \copyright
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_EFUSE_H)
#define CY_EFUSE_H
/**
* \defgroup group_efuse Electronic Fuses (eFuse)
* \{
*
* Electronic Fuses (eFuses) - non-volatile memory whose
* each bit is one-time programmable (OTP). One eFuse macro consists of
* 256 bits (32 * 8). The PSoC devices have up to 16 eFuse macros; consult the
* device-specific datasheet to determine how many macros for a particular device.
* These are implemented as a regular Advanced High-performance Bus (AHB)
* peripheral with the following characteristics:
* - eFuses are used to control the device life-cycle stage (NORMAL, SECURE,
* and SECURE_WITH_DEBUG) and the protection settings;
* - eFuse memory can be programmed (eFuse bit value changed from '0' to '1')
* only once; if an eFuse bit is blown, it cannot be cleared again;
* - programming fuses requires the associated I/O supply to be at a specific
* level: the VDDIO0 (or VDDIO if only one VDDIO is present in the package)
* supply of the device should be set to 2.5 V (&plusmn;5%);
* - fuses are programmed via the PSoC Programmer tool that parses the hex file
* and extracts the necessary information; the fuse data must be located at the
* dedicated section in the hex file. For more details see
* [PSoC 6 Programming Specifications](http://www.cypress.com/documentation/programming-specifications/psoc-6-programming-specifications)
*
* \section group_efuse_configuration Configuration Considerations
*
* Efuse memory can have different organization depending on the selected device.
* Consult the device TRM to determine the efuse memory organization and
* registers bitmap on the selected device.
*
* To read fuse data use the driver [functions] (\ref group_efuse_functions).
*
* To blow fuses, define a data structure of \ref cy_stc_efuse_data_t type in the
* firmware. The structure must be placed in the special memory section, for
* this use a compiler attribute.
* Each byte in the structure corresponds to the one fuse bit in the
* device. It allows the PSoC Programmer tool to distinguish bytes that are
* being set from bytes we don't care about or with unknown values. Fill the
* structure with the following values:
* - 0x00 - Not blown;
* - 0x01 - Blown;
* - 0xFF - Ignore.
*
* After the structure is defined and the values are set, build the project and
* download the firmware. To blow fuses, the firmware must be downloaded by the
* PSoC Programmer tool. Before you download firmware, ensure that the
* conditions from the PSoC 6 Programming Specification are met.
*
* The code below shows an example of the efuse data structure
* definition to blow SECURE bit of the life-cycle stage register.
* The bits to blow are set to the EFUSE_STATE_SET value.
* \snippet eFuse_v1_0_sut_00.cydsn/main_cm0p.c SNIPPET_EFUSE_DATA_STC
*
* \section group_efuse_more_information More Information
*
* Refer to the technical reference manual (TRM) and the device datasheet.
*
* \section group_efuse_MISRA MISRA-C Compliance
*
* <table class="doxtable">
* <tr>
* <th>MISRA Rule</th>
* <th>Rule Class (Required/Advisory)</th>
* <th>Rule Description</th>
* <th>Description of Deviation(s)</th>
* </tr>
* <tr>
* <td>2.3</td>
* <td>R</td>
* <td>The character sequence // shall not be used within a comment.</td>
* <td>The comments provide a useful WEB link to the documentation.</td>
* </tr>
* <tr>
* <td>11.5</td>
* <td>R</td>
* <td>Dangerous pointer cast results in loss of volatile qualification.</td>
* <td>The removal of the volatile qualification inside the function has no
* side effects.</td>
* </tr>
* </table>
*
* \section group_efuse_changelog Changelog
* <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr>
* <td>1.0</td>
* <td>Initial version</td>
* <td></td>
* </tr>
* </table>
*
* \defgroup group_efuse_macros Macros
* \defgroup group_efuse_functions Functions
* \defgroup group_efuse_data_structures Data Structures
* \defgroup group_efuse_enumerated_types Enumerated Types
*/
#include "cy_device_headers.h"
#include "syslib/cy_syslib.h"
/***************************************
* Macro Definitions
***************************************/
/**
* \addtogroup group_efuse_macros
* \{
*/
/** The driver major version */
#define CY_EFUSE_DRV_VERSION_MAJOR 1
/** The driver minor version */
#define CY_EFUSE_DRV_VERSION_MINOR 0
/** The eFuse driver identifier */
#define CY_EFUSE_ID (CY_PDL_DRV_ID(0x1AUL))
/** The number of bits in the byte */
#define CY_EFUSE_BITS_PER_BYTE (8UL)
/** \} group_efuse_macros */
/***************************************
* Enumerated Types
***************************************/
/**
* \addtogroup group_efuse_enumerated_types
* \{
*/
/** This enum has the return values of the eFuse driver */
typedef enum
{
CY_EFUSE_SUCCESS = 0x00UL, /**< Success */
CY_EFUSE_INVALID_PROTECTION = CY_EFUSE_ID | CY_PDL_STATUS_ERROR | 0x01UL, /**< Invalid access in the current protection state */
CY_EFUSE_INVALID_FUSE_ADDR = CY_EFUSE_ID | CY_PDL_STATUS_ERROR | 0x02UL, /**< Invalid eFuse address */
CY_EFUSE_BAD_PARAM = CY_EFUSE_ID | CY_PDL_STATUS_ERROR | 0x03UL, /**< One or more invalid parameters */
CY_EFUSE_IPC_BUSY = CY_EFUSE_ID | CY_PDL_STATUS_ERROR | 0x04UL, /**< The IPC structure is already locked by another process */
CY_EFUSE_ERR_UNC = CY_EFUSE_ID | CY_PDL_STATUS_ERROR | 0xFFUL /**< Unknown error code. See Cy_EFUSE_GetExternalStatus() */
} cy_en_efuse_status_t;
/** \} group_efuse_data_structure */
#if defined(__cplusplus)
extern "C" {
#endif
/***************************************
* Function Prototypes
***************************************/
/**
* \addtogroup group_efuse_functions
* \{
*/
cy_en_efuse_status_t Cy_EFUSE_GetEfuseBit(uint32_t bitNum, bool *bitVal);
cy_en_efuse_status_t Cy_EFUSE_GetEfuseByte(uint32_t offset, uint8_t *byteVal);
uint32_t Cy_EFUSE_GetExternalStatus(void);
/** \} group_efuse_functions */
#if defined(__cplusplus)
}
#endif
#endif /* #if !defined(CY_EFUSE_H) */
/** \} group_efuse */
/* [] END OF FILE */

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/***************************************************************************//**
* \file cy_flash.h
* \version 3.0
*
* Provides the API declarations of the Flash driver.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_FLASH_H)
#define CY_FLASH_H
/**
* \defgroup group_flash Flash System Routine (Flash)
* \{
* Internal flash memory programming
*
* Flash memory in PSoC devices provides non-volatile storage for user firmware,
* user configuration data, and bulk data storage.
*
* Flash operations are implemented as system calls. System calls are executed
* out of SROM in the privileged mode of operation. Users have no access to read
* or modify the SROM code. The driver API requests the system call by acquiring
* the Inter-processor communication (IPC) and writing the SROM function opcode
* and parameters to its input registers. As a result, an NMI interrupt is invoked
* and the requested SROM API is executed. The operation status is returned to the
* driver context and a release interrupt is triggered.
*
* Writing to flash can take up to 20 milliseconds. During this time,
* the device should not be reset (including XRES pin, software reset, and
* watchdog) or unexpected changes may be made to portions of the flash.
* Also, the low-voltage detect circuits should be configured to generate an
* interrupt instead of a reset.
*
* A Read while Write violation occurs when a flash Read operation is initiated
* in the same or neighboring flash sector where the flash Write, Erase, or
* Program operation is working. This violation may cause a HardFault exception.
* To avoid the Read while Write violation, the user must carefully split the
* Read and Write operation on flash sectors which are not neighboring,
* considering both cores in the multi-processor device. The flash is divided
* into four equal sectors. You may edit the linker script to place the code
* into neighboring sectors. For example, use sectors number 0 and 1 for code
* and sectors 2 and 3 for data storage.
*
* \section group_flash_configuration Configuration Considerations
*
* \subsection group_flash_config_intro Introduction:
* The PSoC 6 MCU user-programmable Flash consists of:
* - Up to four User Flash sectors (0 through 3) - 256KB each.
* - EEPROM emulation sector - 32KB.
*
* Write operations are performed on a per-sector basis and may be done as
* Blocking or Partially Blocking, defined as follows:
*
* \subsection group_flash_config_blocking Blocking:
* In this case, the entire Flash block is not available for the duration of the
* Write (up to 20 milliseconds). Therefore, no Flash accesses
* (from any Bus Master) can occur during that time. CPU execution can be
* performed from SRAM. All pre-fetching must be disabled. Application code
* execution from Flash is blocked for the Flash Write duration for both cores.
*
* \subsection group_flash_config_block_const Constraints for Blocking Flash operations:
* -# During write to flash, the device should not be reset (including XRES pin,
* software reset, and watchdog), or unexpected changes may be made to portions
* of the flash.
* -# The low-voltage detect circuits should be configured to generate an
* interrupt instead of a reset.
* -# Flash write operation is allowed only in one of the following CM4 states:
* -# CM4 is Active and initialized:<br>
* call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)".
* <b>Note:</b> If desired user may put CM4 core in Deep Sleep any time
* after calling Cy_SysEnableCM4().
* -# CM4 is Off:<br>
* call Cy_SysDisableCM4(). <b>Note:</b> In this state Debug mode is not
* supported.
* .
* -# Flash write cannot be performed in ULP (core voltage 0.9V) mode.
* -# Interrupts must be enabled on both active cores. Do not enter a critical
* section during flash operation.
* -# User must guarantee that system pipe interrupts (IPC interrupts 3 and 4)
* have the highest priority, or at least that pipe interrupts are not
* interrupted or in a pending state for more than 700 &micro;s.
* -# User must guarantee that during flash write operation no flash read
* operations are performed by bus masters other than CM0+ and CM4 (DMA and
* Crypto).
* -# If you do not use the default startup, ensure that firmware calls the
* following functions before any flash write/erase operations:
* \snippet Flash_sut_01.cydsn/main_cm0p.c Flash Initialization
*
* \subsection group_flash_config_rww Partially Blocking:
* This method has a much shorter time window during which Flash accesses are not
* allowed. Application code execution from Flash is blocked for only a part of
* Flash Write duration, for both cores. Blocking duration depends upon the API
* sequence used.
*
* For API sequence Cy_Flash_StartErase() + Cy_Flash_StartProgram() there are
* four block-out regions during which the read is blocked using the software
* driver (PDL). See <b>Figure 1</b>.
*
* <center>
* <table class="doxtable">
* <caption>Table 1 - Block-out periods</caption>
* <tr>
* <th>Block-out</th>
* <th>Phase</th>
* <th>Duration</th>
* </tr>
* <tr>
* <td>A</td>
* <td>The beginning of the Erase operation</td>
* <td>2ms + 9500 SlowClk cycles</td>
* </tr>
* <tr>
* <td>B</td>
* <td>The end of the Erase operation</td>
* <td>0.13ms + 1000 SlowClk cycles</td>
* </tr>
* <tr>
* <td>C</td>
* <td>The beginning of the Program operation</td>
* <td>0.8ms + 6000 SlowClk cycles</td>
* </tr>
* <tr>
* <td>D</td>
* <td>The end of the Program operation</td>
* <td>0.13ms + 1000 SlowClk cycles</td>
* </tr>
* </table>
* </center>
*
* This allows both cores to execute an application for about 80% of Flash Write
* operation - see <b>Figure 1</b>.
* This capability is important for communication protocols that rely on fast
* response.
*
* \image html flash-rww-diagram.png "Figure 1 - Blocking Intervals in Flash Write operation" width=70%
*
* For the Cy_Flash_StartWrite() function, the block-out period is different for
* the two cores. The core that initiates Cy_Flash_StartWrite() is blocked for
* two periods:
* - From start of Erase operation (start of A on Figure 1) till the start of
* Program operation (end of C on Figure 1).
* - During D period on <b>Figure 1</b>.
*
* The core that performs read/execute is blocked identically to the
* Cy_Flash_StartErase() + Cy_Flash_StartProgram() sequence - see <b>Figure 1</b>.
*
* This allows the core that initiates Cy_Flash_StartWrite() to execute an
* application for about 20% of the Flash Write operation. The other core executes
* the application for about 80% of the Flash Write operation.
*
* Some constraints must be planned for in the Partially Blocking mode which are
* described in detail below.
*
* \subsection group_flash_config_rww_const Constraints for Partially Blocking Flash operations:
* -# During write to flash, the device should not be reset (including XRES pin,
* software reset, and watchdog) or unexpected changes may be made to portions
* of the flash.
* -# The low-voltage detect circuits should be configured to generate an
* interrupt instead of a reset.
* -# During write to flash, application code should not change the clock
* settings. Use Cy_Flash_IsOperationComplete() to ensure flash write
* operation is finished.
* -# Flash write operation is allowed only in one of the following CM4 states:
* -# CM4 is Active and initialized:<br>
* call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)".
* <b>Note:</b> If desired user may put CM4 core in Deep Sleep any time
* after calling Cy_SysEnableCM4().
* -# CM4 is Off:<br>
* call Cy_SysDisableCM4(). <b>Note:</b> In this state Debug mode is not
* supported.
* .
* -# Use the following rules for split by sectors. (In this context, read means
* read of any bus master: CM0+, CM4, DMA, Crypto, etc.)
* -# Do not write to and read/execute from the same flash sector at the same
* time. This is true for all sectors.
* -# Writing rules in User Flash:
* -# Any bus master can read/execute from UFLASH S0 and/or S1, during
* flash write to UFLASH S2 or S3.
* -# Any bus master can read/execute from UFLASH S2 and/or S3, during
* flash write to UFLASH S0 or S1.
*
* <b>Suggestion:</b> in case of bootloading, it is recommended to place
* code for CM4 in either S0 or S1. CM0+ code resides in S0. Write data
* to S2 and S3 sections.
* .
* -# Flash write cannot be performed in ULP mode (core voltage 0.9V).
* -# Interrupts must be enabled on both active cores. Do not enter a critical
* section during flash operation.
* -# User must guarantee that system pipe interrupts (IPC interrupts 3 and 4)
* have the highest priority, or at least that pipe interrupts are not
* interrupted or in a pending state for more than 700 &micro;s.
* -# User must guarantee that during flash write operation no flash read
* operations are performed by bus masters other than CM0+ and CM4
* (DMA and Crypto).
* -# If you do not use the default startup, ensure that firmware calls the
* following functions before any flash write/erase operations:
* \snippet Flash_sut_01.cydsn/main_cm0p.c Flash Initialization
*
* \subsection group_flash_config_emeeprom EEPROM section use:
* If you plan to use "cy_em_eeprom" section for different purposes for both of
* device cores or use <b>Em_EEPROM Middleware</b> together with flash driver
* write operations you must modify the linker scripts.<br>
* For more information, refer to the <b>Middleware/Cypress Em_EEPROM Middleware
* Library</b> section of the PDL documentation.
*
* \section group_flash_more_information More Information
*
* See the technical reference manual (TRM) for more information about the Flash
* architecture.
*
* \section group_flash_MISRA MISRA-C Compliance
*
* <table class="doxtable">
* <tr>
* <th>MISRA Rule</th>
* <th>Rule Class (Required/Advisory)</th>
* <th>Rule Description</th>
* <th style="width: 50%;">Description of Deviation(s)</th>
* </tr>
* <tr>
* <td>11.4</td>
* <td>A</td>
* <td>Casting to different object pointer type.</td>
* <td>The cast of the uint32_t pointer to pipe message structure pointer
* is used to get transmitted data via the \ref group_ipc channel.
* We cast only one pointer, so there is no way to avoid this cast.</td>
* </tr>
* <tr>
* <td>11.5</td>
* <td>R</td>
* <td>Not performed, the cast that removes any const or volatile qualification from the type addressed by a pointer.</td>
* <td>The removal of the volatile qualification inside the function has no side effects.</td>
* </tr>
* </table>
*
* \section group_flash_changelog Changelog
*
* <table class="doxtable">
* <tr><th>Version</th><th style="width: 52%;">Changes</th><th>Reason for Change</th></tr>
* <tr>
* <td>3.0</td>
* <td>New function - Cy_Flash_ProgramRow();<br>
* Updated Cy_Flash_RowChecksum(): changed input parameter to take the
* <b>row address</b> (rowAddr) instead of the <b>row number</b>
* (rowNum);<br>
* Renamed macro for disabling RWW support in driver to
* <b>CY_FLASH_RWW_DRV_SUPPORT_DISABLED</b>.<br>
* Updated \ref group_flash_configuration documentation section with
* flash usage constraints.</td>
* <td>Improvements made based on usability feedback to use a common
* interface</td>
* </tr>
* <tr>
* <td rowspan="3">2.0</td>
* <td>Added non-blocking erase function - Cy_Flash_StartErase().
* Removed the clear cache function call.</td>
* <td>The clear cache operation is removed from the blocking Write/Erase
* function because in this case it is performed by the hardware.
* Otherwise it is documented that it is the user's responsibility to
* clear the cache after executing the non-blocking Write/Erase flash
* operation.</td>
* </tr>
* <tr>
* <td>Added new Cy_Flash_IsOperationComplete() function to check completeness.
* Obsoleted Cy_Flash_IsWriteComplete(), Cy_Flash_IsProgramComplete(),
* and Cy_Flash_IsEraseComplete() functions.<br>
* Added Cy_Flash_GetExternalStatus() function to get unparsed status where
* flash driver will be used in security applications with other modules
* as SecureImage.<br>
* Added Cy_Flash_Init() function to initialize all needed prerequisites
* for Erase/Write operations.</td>
* <td>Updated driver design to improve user experience.</td>
* </tr>
* <tr>
* <td>Updated driver implementation to remove MISRA rules deviations.</td>
* <td>Driver implementation quality improvement.</td>
* </tr>
* <tr>
* <td>1.0</td>
* <td>Initial version</td>
* <td></td>
* </tr>
* </table>
*
* \defgroup group_flash_macros Macros
* \{
* \defgroup group_flash_general_macros Flash general parameters
* Provides general information about flash
* \}
* \defgroup group_flash_functions Functions
* \defgroup group_flash_enumerated_types Enumerated Types
*/
#include <cy_device_headers.h>
#include "syslib/cy_syslib.h"
#if defined(__cplusplus)
extern "C" {
#endif
/***************************************
* Macro definitions
***************************************/
/**
* \addtogroup group_flash_macros
* \{
*/
/** Driver major version */
#define CY_FLASH_DRV_VERSION_MAJOR 3
/** Driver minor version */
#define CY_FLASH_DRV_VERSION_MINOR 0
#define CY_FLASH_ID (CY_PDL_DRV_ID(0x14UL)) /**< FLASH PDL ID */
#define CY_FLASH_ID_INFO (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_INFO ) /**< Return prefix for FLASH driver function status codes */
#define CY_FLASH_ID_WARNING (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_WARNING) /**< Return prefix for FLASH driver function warning return values */
#define CY_FLASH_ID_ERROR (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_ERROR) /**< Return prefix for FLASH driver function error return values */
/** \} group_flash_macros */
/**
* \addtogroup group_flash_general_macros
* \{
*/
/** Flash row size */
#define CY_FLASH_SIZEOF_ROW (CPUSS_FLASHC_PA_SIZE * 4u)
/** Number of flash rows */
#define CY_FLASH_NUMBER_ROWS (CY_FLASH_SIZE / CY_FLASH_SIZEOF_ROW)
/** Long words flash row size */
#define CY_FLASH_SIZEOF_ROW_LONG_UNITS (CY_FLASH_SIZEOF_ROW / sizeof(uint32_t))
/** \} group_flash_general_macros */
/**
* \addtogroup group_flash_enumerated_types
* \{
*/
/** This enum has the return values of the Flash driver */
typedef enum cy_en_flashdrv_status
{
CY_FLASH_DRV_SUCCESS = 0x00UL, /**< Success */
CY_FLASH_DRV_INV_PROT = ( CY_FLASH_ID_ERROR + 0x0UL), /**< Invalid device protection state */
CY_FLASH_DRV_INVALID_FM_PL = ( CY_FLASH_ID_ERROR + 0x1UL), /**< Invalid flash page latch address */
CY_FLASH_DRV_INVALID_FLASH_ADDR = ( CY_FLASH_ID_ERROR + 0x2UL), /**< Invalid flash address */
CY_FLASH_DRV_ROW_PROTECTED = ( CY_FLASH_ID_ERROR + 0x3UL), /**< Row is write protected */
CY_FLASH_DRV_IPC_BUSY = ( CY_FLASH_ID_ERROR + 0x5UL), /**< IPC structure is already locked by another process */
CY_FLASH_DRV_INVALID_INPUT_PARAMETERS = ( CY_FLASH_ID_ERROR + 0x6UL), /**< Input parameters passed to Flash API are not valid */
CY_FLASH_DRV_PL_ROW_COMP_FA = ( CY_FLASH_ID_ERROR + 0x22UL), /**< Comparison between Page Latches and FM row failed */
CY_FLASH_DRV_ERR_UNC = ( CY_FLASH_ID_ERROR + 0xFFUL), /**< Unknown error code. See \ref Cy_Flash_GetExternalStatus() */
CY_FLASH_DRV_PROGRESS_NO_ERROR = ( CY_FLASH_ID_INFO + 0x0UL), /**< Command in progress; no error */
CY_FLASH_DRV_OPERATION_STARTED = ( CY_FLASH_ID_INFO + 0x1UL), /**< Flash operation is successfully initiated */
CY_FLASH_DRV_OPCODE_BUSY = ( CY_FLASH_ID_INFO + 0x2UL) /**< Flash is under operation */
} cy_en_flashdrv_status_t;
/** \} group_flash_enumerated_types */
/***************************************
* Function Prototypes
***************************************/
/**
* \addtogroup group_flash_functions
* \{
*/
void Cy_Flash_Init(void);
cy_en_flashdrv_status_t Cy_Flash_EraseRow(uint32_t rowAddr);
cy_en_flashdrv_status_t Cy_Flash_ProgramRow(uint32_t rowAddr, const uint32_t* data);
cy_en_flashdrv_status_t Cy_Flash_WriteRow(uint32_t rowAddr, const uint32_t* data);
cy_en_flashdrv_status_t Cy_Flash_StartWrite(uint32_t rowAddr, const uint32_t* data);
cy_en_flashdrv_status_t Cy_Flash_StartProgram(uint32_t rowAddr, const uint32_t* data);
cy_en_flashdrv_status_t Cy_Flash_StartErase(uint32_t rowAddr);
cy_en_flashdrv_status_t Cy_Flash_IsOperationComplete(void);
cy_en_flashdrv_status_t Cy_Flash_RowChecksum(uint32_t rowAddr, uint32_t* checksumPtr);
cy_en_flashdrv_status_t Cy_Flash_CalculateHash(const uint32_t* data, uint32_t numberOfBytes, uint32_t* hashPtr);
uint32_t Cy_Flash_GetExternalStatus(void);
/** \} group_flash_functions */
/** \cond INTERNAL */
/* Macros to backward compatibility */
#define Cy_Flash_IsWriteComplete(...) Cy_Flash_IsOperationComplete()
#define Cy_Flash_IsProgramComplete(...) Cy_Flash_IsOperationComplete()
#define Cy_Flash_IsEraseComplete(...) Cy_Flash_IsOperationComplete()
/** \endcond */
#if defined(__cplusplus)
}
#endif
#endif /* #if !defined(CY_FLASH_H) */
/** \} group_flash */
/* [] END OF FILE */

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/***************************************************************************//**
* \file cy_gpio.c
* \version 1.10.1
*
* \brief
* Provides an API implementation of the GPIO driver
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cy_gpio.h"
#if defined(__cplusplus)
extern "C" {
#endif
/*******************************************************************************
* Function Name: Cy_GPIO_Pin_Init
****************************************************************************//**
*
* \brief Initializes all pin configuration settings for the specified pin.
*
* \param base
* Pointer to the pin's port register base address
*
* \param pinNum
* Position of the pin bit-field within the port register
*
* \param config
* Pointer to the pin config structure base address
*
* \return
* Initialization status
*
* \note
* This function modifies port registers in read-modify-write operations. It is
* not thread safe as the resource is shared among multiple pins on a port.
*
* \funcusage
* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Pin_Init
*
*******************************************************************************/
cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const cy_stc_gpio_pin_config_t *config)
{
cy_en_gpio_status_t status = CY_GPIO_SUCCESS;
uint32_t maskCfgOut;
uint32_t tempReg;
if((NULL != base) && (NULL != config))
{
CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->outVal));
CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(config->driveMode));
CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(config->hsiom));
CY_ASSERT_L2(CY_GPIO_IS_INT_EDGE_VALID(config->intEdge));
CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->intMask));
CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtrip));
CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->slewRate));
CY_ASSERT_L2(CY_GPIO_IS_DRIVE_SEL_VALID(config->driveSel));
CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vregEn));
CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->ibufMode));
CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtripSel));
CY_ASSERT_L2(CY_GPIO_IS_VREF_SEL_VALID(config->vrefSel));
CY_ASSERT_L2(CY_GPIO_IS_VOH_SEL_VALID(config->vohSel));
Cy_GPIO_Write(base, pinNum, config->outVal);
Cy_GPIO_SetDrivemode(base, pinNum, config->driveMode);
Cy_GPIO_SetHSIOM(base, pinNum, config->hsiom);
Cy_GPIO_SetInterruptEdge(base, pinNum, config->intEdge);
Cy_GPIO_SetInterruptMask(base, pinNum, config->intMask);
Cy_GPIO_SetVtrip(base, pinNum, config->vtrip);
/* Slew rate and Driver strength */
maskCfgOut = (CY_GPIO_CFG_OUT_SLOW_MASK << pinNum)
| (CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << ((uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET));
tempReg = base->CFG_OUT & ~(maskCfgOut);
base->CFG_OUT = tempReg | ((config->slewRate & CY_GPIO_CFG_OUT_SLOW_MASK) << pinNum)
| ((config->driveSel & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK) << ((uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET));
/* SIO specific configuration */
tempReg = base->CFG_SIO & ~(CY_GPIO_SIO_PIN_MASK);
base->CFG_SIO = tempReg | (((config->vregEn & CY_GPIO_VREG_EN_MASK)
| ((config->ibufMode & CY_GPIO_IBUF_MASK) << CY_GPIO_IBUF_SHIFT)
| ((config->vtripSel & CY_GPIO_VTRIP_SEL_MASK) << CY_GPIO_VTRIP_SEL_SHIFT)
| ((config->vrefSel & CY_GPIO_VREF_SEL_MASK) << CY_GPIO_VREF_SEL_SHIFT)
| ((config->vohSel & CY_GPIO_VOH_SEL_MASK) << CY_GPIO_VOH_SEL_SHIFT))
<< ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET));
}
else
{
status = CY_GPIO_BAD_PARAM;
}
return(status);
}
/*******************************************************************************
* Function Name: Cy_GPIO_Port_Init
****************************************************************************//**
*
* \brief Initialize a complete port of pins from a single init structure.
*
* The configuration structure used in this function has a 1:1 mapping to the
* GPIO and HSIOM registers. Refer to the device Technical Reference Manual (TRM)
* for the register details on how to populate them.
*
* \param base
* Pointer to the pin's port register base address
*
* \param config
* Pointer to the pin config structure base address
*
* \return
* Initialization status
*
* \note
* If using the PSoC Creator IDE, there is no need to initialize the pins when
* using the GPIO component on the schematic. Ports are configured in
* Cy_SystemInit() before main() entry.
*
* \funcusage
* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Port_Init
*
*******************************************************************************/
cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt_config_t *config)
{
cy_en_gpio_status_t status = CY_GPIO_SUCCESS;
uint32_t portNum;
HSIOM_PRT_Type* baseHSIOM;
if((NULL != base) && (NULL != config))
{
CY_ASSERT_L2(CY_GPIO_IS_PIN_BIT_VALID(config->out));
CY_ASSERT_L2(CY_GPIO_IS_PIN_BIT_VALID(config->cfgIn));
CY_ASSERT_L2(CY_GPIO_IS_INTR_CFG_VALID(config->intrCfg));
CY_ASSERT_L2(CY_GPIO_IS_INTR_MASK_VALID(config->intrMask));
CY_ASSERT_L2(CY_GPIO_IS_SEL_ACT_VALID(config->sel0Active));
CY_ASSERT_L2(CY_GPIO_IS_SEL_ACT_VALID(config->sel1Active));
portNum = ((uint32_t)(base) - GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
baseHSIOM = (HSIOM_PRT_Type*)(HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
base->OUT = config->out;
base->CFG = config->cfg;
base->CFG_IN = config->cfgIn;
base->CFG_OUT = config->cfgOut;
base->INTR_CFG = config->intrCfg;
base->INTR_MASK = config->intrMask;
base->CFG_SIO = config->cfgSIO;
baseHSIOM->PORT_SEL0 = config->sel0Active;
baseHSIOM->PORT_SEL1 = config->sel1Active;
}
else
{
status = CY_GPIO_BAD_PARAM;
}
return(status);
}
/*******************************************************************************
* Function Name: Cy_GPIO_Pin_FastInit
****************************************************************************//**
*
* \brief Initialize the most common configuration settings for all pin types.
*
* These include, drive mode, initial output value, and HSIOM connection.
*
* \param base
* Pointer to the pin's port register base address
*
* \param pinNum
* Position of the pin bit-field within the port register
*
* \param driveMode
* Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros
*
* \param outVal
* Logic state of the output buffer driven to the pin (1 or 0)
*
* \param hsiom
* HSIOM input selection
*
* \return
* void
*
* \note
* This function modifies port registers in read-modify-write operations. It is
* not thread safe as the resource is shared among multiple pins on a port.
*
* \funcusage
* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Pin_FastInit
*
*******************************************************************************/
void Cy_GPIO_Pin_FastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode,
uint32_t outVal, en_hsiom_sel_t hsiom)
{
uint32_t tempReg;
CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(driveMode));
CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(outVal));
CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(hsiom));
tempReg = (base->OUT & ~(CY_GPIO_OUT_MASK << pinNum));
base->OUT = tempReg | ((outVal & CY_GPIO_OUT_MASK) << pinNum);
tempReg = (base->CFG & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)));
base->CFG = tempReg | ((driveMode & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
Cy_GPIO_SetHSIOM(base, pinNum, hsiom);
}
/*******************************************************************************
* Function Name: Cy_GPIO_Port_Deinit
****************************************************************************//**
*
* \brief Reset a complete port of pins back to power on reset defaults.
*
* \param base
* Pointer to the pin's port register base address
*
* \return
* void
*
* \funcusage
* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Port_Deinit
*
*******************************************************************************/
void Cy_GPIO_Port_Deinit(GPIO_PRT_Type* base)
{
uint32_t portNum;
HSIOM_PRT_Type* portAddrHSIOM;
portNum = ((uint32_t)(base) - GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
portAddrHSIOM = (HSIOM_PRT_Type*)(HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
base->OUT = CY_GPIO_PRT_DEINIT;
base->CFG = CY_GPIO_PRT_DEINIT;
base->CFG_IN = CY_GPIO_PRT_DEINIT;
base->CFG_OUT = CY_GPIO_PRT_DEINIT;
base->INTR_CFG = CY_GPIO_PRT_DEINIT;
base->INTR_MASK = CY_GPIO_PRT_DEINIT;
base->CFG_SIO = CY_GPIO_PRT_DEINIT;
portAddrHSIOM->PORT_SEL0 = CY_GPIO_PRT_DEINIT;
portAddrHSIOM->PORT_SEL1 = CY_GPIO_PRT_DEINIT;
}
#if defined(__cplusplus)
}
#endif
/* [] END OF FILE */

480
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/gpio/cy_gpio.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/gpio/cy_gpio.h
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File diff suppressed because it is too large Load Diff

72
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/i2s/cy_i2s.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/i2s/cy_i2s.c
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_i2s.c * \file cy_i2s.c
* \version 2.0 * \version 2.0.1
* *
* The source code file for the I2S driver. * The source code file for the I2S driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -29,30 +29,33 @@ extern "C" {
* must be called before calling this function. * must be called before calling this function.
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
*
* \param config The pointer to a configuration structure. * \param config The pointer to a configuration structure.
*
* \return error / status code. See \ref cy_en_i2s_status_t. * \return error / status code. See \ref cy_en_i2s_status_t.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_Init
*
*******************************************************************************/ *******************************************************************************/
cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config) cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config)
{ {
cy_en_i2s_status_t ret = CY_I2S_BAD_PARAM; cy_en_i2s_status_t ret = CY_I2S_BAD_PARAM;
cy_en_i2s_ws_pw_t wsPulseWidth;
uint32_t channels, clockDiv;
cy_en_i2s_len_t channelLength;
if((NULL != base) && (NULL != config)) if((NULL != base) && (NULL != config))
{ {
ret = CY_I2S_SUCCESS; cy_en_i2s_ws_pw_t wsPulseWidth;
cy_en_i2s_len_t channelLength;
/* Clock setting */ uint32_t channels;
clockDiv = (uint32_t)config->clkDiv - 1U; uint32_t clockDiv = (uint32_t)config->clkDiv - 1U;
CY_ASSERT_L2(CY_I2S_IS_CLK_DIV_VALID(clockDiv)); CY_ASSERT_L2(CY_I2S_IS_CLK_DIV_VALID(clockDiv));
/* The clock setting */
base->CLOCK_CTL = _VAL2FLD(I2S_CLOCK_CTL_CLOCK_DIV, clockDiv) | base->CLOCK_CTL = _VAL2FLD(I2S_CLOCK_CTL_CLOCK_DIV, clockDiv) |
_BOOL2FLD(I2S_CLOCK_CTL_CLOCK_SEL, config->extClk); _BOOL2FLD(I2S_CLOCK_CTL_CLOCK_SEL, config->extClk);
/* Tx setting */ /* The Tx setting */
if (config->txEnabled) if (config->txEnabled)
{ {
CY_ASSERT_L3(CY_I2S_IS_ALIGNMENT_VALID(config->txAlignment)); CY_ASSERT_L3(CY_I2S_IS_ALIGNMENT_VALID(config->txAlignment));
@ -61,19 +64,19 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf
if ((CY_I2S_TDM_MODE_A == config->txAlignment) || (CY_I2S_TDM_MODE_B == config->txAlignment)) if ((CY_I2S_TDM_MODE_A == config->txAlignment) || (CY_I2S_TDM_MODE_B == config->txAlignment))
{ {
channels = (uint32_t)config->txChannels - 1UL; channels = (uint32_t)config->txChannels - 1UL;
wsPulseWidth = CY_I2S_WS_ONE_CHANNEL_LENGTH; wsPulseWidth = config->txWsPulseWidth;
channelLength = CY_I2S_LEN32; channelLength = CY_I2S_LEN32;
CY_ASSERT_L2(CY_I2S_IS_CHANNELS_VALID(channels)); CY_ASSERT_L2(CY_I2S_IS_CHANNELS_VALID(channels));
CY_ASSERT_L3(CY_I2S_IS_WSPULSE_VALID(wsPulseWidth));
CY_ASSERT_L3(CY_I2S_IS_LEN_VALID(config->txWordLength)); CY_ASSERT_L3(CY_I2S_IS_LEN_VALID(config->txWordLength));
} }
else else
{ {
channels = 1UL; channels = 1UL;
wsPulseWidth = config->txWsPulseWidth; wsPulseWidth = CY_I2S_WS_ONE_CHANNEL_LENGTH;
channelLength = config->txChannelLength; channelLength = config->txChannelLength;
CY_ASSERT_L3(CY_I2S_IS_WSPULSE_VALID(wsPulseWidth));
CY_ASSERT_L3(CY_I2S_IS_CHAN_WORD_VALID(channelLength, config->txWordLength)); CY_ASSERT_L3(CY_I2S_IS_CHAN_WORD_VALID(channelLength, config->txWordLength));
} }
@ -94,7 +97,7 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf
_VAL2FLD(I2S_TX_CTL_OVHDATA, config->txOverheadValue); _VAL2FLD(I2S_TX_CTL_OVHDATA, config->txOverheadValue);
} }
/* Rx setting */ /* The Rx setting */
if (config->rxEnabled) if (config->rxEnabled)
{ {
CY_ASSERT_L3(CY_I2S_IS_ALIGNMENT_VALID(config->rxAlignment)); CY_ASSERT_L3(CY_I2S_IS_ALIGNMENT_VALID(config->rxAlignment));
@ -102,19 +105,19 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf
if ((CY_I2S_TDM_MODE_A == config->rxAlignment) || (CY_I2S_TDM_MODE_B == config->rxAlignment)) if ((CY_I2S_TDM_MODE_A == config->rxAlignment) || (CY_I2S_TDM_MODE_B == config->rxAlignment))
{ {
channels = (uint32_t)config->rxChannels - 1UL; channels = (uint32_t)config->rxChannels - 1UL;
wsPulseWidth = CY_I2S_WS_ONE_CHANNEL_LENGTH; wsPulseWidth = config->rxWsPulseWidth;
channelLength = CY_I2S_LEN32; channelLength = CY_I2S_LEN32;
CY_ASSERT_L2(CY_I2S_IS_CHANNELS_VALID(channels)); CY_ASSERT_L2(CY_I2S_IS_CHANNELS_VALID(channels));
CY_ASSERT_L3(CY_I2S_IS_WSPULSE_VALID(wsPulseWidth));
CY_ASSERT_L3(CY_I2S_IS_LEN_VALID(config->rxWordLength)); CY_ASSERT_L3(CY_I2S_IS_LEN_VALID(config->rxWordLength));
} }
else else
{ {
channels = 1UL; channels = 1UL;
wsPulseWidth = config->rxWsPulseWidth; wsPulseWidth = CY_I2S_WS_ONE_CHANNEL_LENGTH;
channelLength = config->rxChannelLength; channelLength = config->rxChannelLength;
CY_ASSERT_L3(CY_I2S_IS_WSPULSE_VALID(wsPulseWidth));
CY_ASSERT_L3(CY_I2S_IS_CHAN_WORD_VALID(channelLength, config->rxWordLength)); CY_ASSERT_L3(CY_I2S_IS_CHAN_WORD_VALID(channelLength, config->rxWordLength));
} }
@ -135,7 +138,7 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf
_BOOL2FLD(I2S_RX_CTL_BIT_EXTENSION, config->rxSignExtension); _BOOL2FLD(I2S_RX_CTL_BIT_EXTENSION, config->rxSignExtension);
} }
/* I2S enable setting */ /* The I2S enable setting */
if (config->txEnabled) if (config->txEnabled)
{ {
base->CTL |= I2S_CTL_TX_ENABLED_Msk; base->CTL |= I2S_CTL_TX_ENABLED_Msk;
@ -146,7 +149,7 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf
base->CTL |= I2S_CTL_RX_ENABLED_Msk; base->CTL |= I2S_CTL_RX_ENABLED_Msk;
} }
/* FIFO setting */ /* The FIFO setting */
if (config->txEnabled) if (config->txEnabled)
{ {
base->TX_FIFO_CTL = _VAL2FLD(I2S_TX_FIFO_CTL_TRIGGER_LEVEL, config->txFifoTriggerLevel); base->TX_FIFO_CTL = _VAL2FLD(I2S_TX_FIFO_CTL_TRIGGER_LEVEL, config->txFifoTriggerLevel);
@ -160,6 +163,8 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf
base->TR_CTL |= _BOOL2FLD(I2S_TR_CTL_RX_REQ_EN, config->rxDmaTrigger); base->TR_CTL |= _BOOL2FLD(I2S_TR_CTL_RX_REQ_EN, config->rxDmaTrigger);
} }
ret = CY_I2S_SUCCESS;
} }
return (ret); return (ret);
@ -174,6 +179,9 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_DeInit
*
*******************************************************************************/ *******************************************************************************/
void Cy_I2S_DeInit(I2S_Type * base) void Cy_I2S_DeInit(I2S_Type * base)
{ {
@ -195,12 +203,14 @@ void Cy_I2S_DeInit(I2S_Type * base)
* Function Name: Cy_I2S_DeepSleepCallback * Function Name: Cy_I2S_DeepSleepCallback
****************************************************************************//** ****************************************************************************//**
* *
* This is a callback function that can be used at the application layer to * This is a callback function to be used at the application layer to
* manage an I2S operation before entering into/after exiting from the Deep Sleep * manage an I2S operation during the Deep-Sleep cycle. It stores the I2S state
* mode. * (Tx/Rx enabled/disabled/paused) into the context structure and stops the
* communication before entering into Deep-Sleep power mode and restores the I2S
* state after waking up.
* *
* \param * \param
* callbackParams - A pointer to the callback parameters structure, * callbackParams - The pointer to the callback parameters structure,
* see \ref cy_stc_syspm_callback_params_t. * see \ref cy_stc_syspm_callback_params_t.
* *
* \return the SysPm callback status \ref cy_en_syspm_status_t. * \return the SysPm callback status \ref cy_en_syspm_status_t.
@ -208,6 +218,9 @@ void Cy_I2S_DeInit(I2S_Type * base)
* \note Use the \ref cy_stc_i2s_context_t data type for definition of the * \note Use the \ref cy_stc_i2s_context_t data type for definition of the
* *context element of the \ref cy_stc_syspm_callback_params_t strusture. * *context element of the \ref cy_stc_syspm_callback_params_t strusture.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_DeepSleepCallback
*
*******************************************************************************/ *******************************************************************************/
cy_en_syspm_status_t Cy_I2S_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams) cy_en_syspm_status_t Cy_I2S_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams)
{ {
@ -225,7 +238,6 @@ cy_en_syspm_status_t Cy_I2S_DeepSleepCallback(cy_stc_syspm_callback_params_t * c
case CY_SYSPM_BEFORE_TRANSITION: case CY_SYSPM_BEFORE_TRANSITION:
*locInterruptMask = Cy_I2S_GetInterruptMask(locBase); /* Store I2S interrupts */ *locInterruptMask = Cy_I2S_GetInterruptMask(locBase); /* Store I2S interrupts */
Cy_I2S_SetInterruptMask(locBase, 0UL); /* Disable I2S interrupts */
*locState = Cy_I2S_GetCurrentState(locBase); /* Store I2S state */ *locState = Cy_I2S_GetCurrentState(locBase); /* Store I2S state */
if (0UL != (*locState & I2S_CMD_TX_START_Msk)) if (0UL != (*locState & I2S_CMD_TX_START_Msk))
{ {
@ -235,26 +247,28 @@ cy_en_syspm_status_t Cy_I2S_DeepSleepCallback(cy_stc_syspm_callback_params_t * c
{ {
Cy_I2S_DisableRx(locBase); /* Stop RX operation */ Cy_I2S_DisableRx(locBase); /* Stop RX operation */
} }
/* Unload FIFOs to do not lost any data (if needed) */ Cy_I2S_SetInterruptMask(locBase, 0UL); /* Disable I2S interrupts */
/* Unload FIFOs in order not to lose data (if needed) */
break; break;
case CY_SYSPM_AFTER_TRANSITION: case CY_SYSPM_AFTER_TRANSITION:
if (0UL != (*locState & I2S_CMD_RX_START_Msk)) if (0UL != (*locState & I2S_CMD_RX_START_Msk))
{ {
Cy_I2S_ClearRxFifo (locBase); /* Clear RX FIFO */ Cy_I2S_ClearRxFifo(locBase); /* Clear the RX FIFO */
Cy_I2S_EnableRx(locBase); /* Start RX operation */ Cy_I2S_EnableRx(locBase); /* Start RX operation */
} }
if (0UL != (*locState & I2S_CMD_TX_START_Msk)) if (0UL != (*locState & I2S_CMD_TX_START_Msk))
{ {
Cy_I2S_ClearTxFifo (locBase); /* Clear TX FIFO */ Cy_I2S_ClearTxFifo(locBase); /* Clear the TX FIFO */
Cy_I2S_WriteTxData (locBase, 0UL); /* Fill first TX frame */ Cy_I2S_WriteTxData(locBase, 0UL); /* Fill at least one TX frame */
Cy_I2S_WriteTxData(locBase, 0UL); Cy_I2S_WriteTxData(locBase, 0UL);
if (0UL != (*locState & I2S_CMD_TX_PAUSE_Msk)) if (0UL != (*locState & I2S_CMD_TX_PAUSE_Msk))
{ {
Cy_I2S_PauseTx(locBase); /* Restore TX paused state */ Cy_I2S_PauseTx(locBase); /* Restore the TX paused state */
} }
Cy_I2S_EnableTx(locBase); /* Start TX operation */ Cy_I2S_EnableTx(locBase); /* Start TX operation */
} }
Cy_I2S_ClearInterrupt(locBase, *locInterruptMask); /* Clear possible pending I2S interrupts */
Cy_I2S_SetInterruptMask(locBase, *locInterruptMask); /* Restore I2S interrupts */ Cy_I2S_SetInterruptMask(locBase, *locInterruptMask); /* Restore I2S interrupts */
break; break;

203
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/i2s/cy_i2s.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/i2s/cy_i2s.h
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_i2s.h * \file cy_i2s.h
* \version 2.0 * \version 2.0.1
* *
* The header file of the I2S driver. * The header file of the I2S driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -20,10 +20,10 @@
* codecs or simple DACs. It can also receive digital audio streaming data. * codecs or simple DACs. It can also receive digital audio streaming data.
* *
* Features: * Features:
* * An industry-standard NXP I2S interface * * An industry standard NXP I2S interface.
* * Supports master/slave TX/RX operation * * Supports master/slave TX/RX operation.
* * Programmable Channel/Word Lengths * * Programmable Channel/Word Lengths.
* * Supports External Clock operation * * Supports External Clock operation.
* *
* The I2S bus is an industry standard. The hardware interface was * The I2S bus is an industry standard. The hardware interface was
* developed by Philips Semiconductors (now NXP Semiconductors). * developed by Philips Semiconductors (now NXP Semiconductors).
@ -33,36 +33,36 @@
* To set up an I2S, provide the configuration parameters in the * To set up an I2S, provide the configuration parameters in the
* \ref cy_stc_i2s_config_t structure. * \ref cy_stc_i2s_config_t structure.
* *
* For example, for TX configuration, set txEnabled to true, configure * For example, for Tx configuration, set txEnabled to true, configure
* txDmaTrigger (depending on whether DMA is going to be used or not), set * txDmaTrigger (depending on whether DMA is going to be used or not), set
* extClk (if an external clock is used), provide clkDiv, txMasterMode, * extClk (if an external clock is used), provide clkDiv, txMasterMode,
* txAlignment, txChannels (only 2 is supported in I2S and Left Justified modes) * txAlignment, txChannels (only 2 is supported in I2S and Left Justified modes)
* txSdoLatchingTime (for slave mode only), txChannelLength, txWordLength, * txSdoLatchingTime (for slave mode only), txChannelLength, txWordLength,
* txWsPulseWidth (for TMD modes only), txWatchdogEnable and txWatchdogValue * txWsPulseWidth (for TMD modes only), txWatchdogEnable and txWatchdogValue
* (both for slave mode only, and when the watchdog interrupt will be used), * (both for Slave mode only, and when the watchdog interrupt will be used),
* either txSckoInversion or txSckiInversion (based on txMasterMode setting), * either txSckoInversion or txSckiInversion (based on txMasterMode setting),
* txFifoTriggerLevel (when the Trig interrupt will be used) and txOverheadValue * txFifoTriggerLevel (when the Trig interrupt will be used) and txOverheadValue
* (only when word length is less than channel length). * (only when the word length is less than channel length).
* The similar setup is for RX configuration. * A similar setup is for the Rx configuration.
* *
* To initialize the I2S block, call the \ref Cy_I2S_Init function, providing the * To initialize the I2S block, call the \ref Cy_I2S_Init function, providing the
* filled \ref cy_stc_i2s_config_t structure. * filled \ref cy_stc_i2s_config_t structure.
* Before starting the transmission, clear the FIFO \ref Cy_I2S_ClearTxFifo, then * Before starting the transmission, clear the FIFO \ref Cy_I2S_ClearTxFifo, then
* fill the first TX data frame by calling \ref Cy_I2S_WriteTxData once for each * fill the first Tx data frame by calling \ref Cy_I2S_WriteTxData once for each
* channel (e.g. twice for I2S mode with only two channels) with zero data. Then * channel (e.g. twice for I2S mode with only two channels) with zero data. Then
* call the \ref Cy_I2S_EnableTx itself. * call the \ref Cy_I2S_EnableTx itself.
* For the reception the sequence is the same except of filling the first data * For the reception the sequence is the same except for filling the first data
* frame, just RX FIFO clearing is enough. * frame, just RX FIFO clearing is enough.
* *
* For example: * For example:
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c Cy_I2S_Snippet * \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_Init
* *
* If you use DMA, the DMA channel should be previously configured. I2S interrupts * If you use a DMA, the DMA channel should be previously configured. The I2S interrupts
* (if applicable) can be enabled by calling \ref Cy_I2S_SetInterruptMask. * (if applicable) can be enabled by calling \ref Cy_I2S_SetInterruptMask.
* *
* For example, if the trigger interrupt is used, during operation the ISR * For example, if the trigger interrupt is used, during operation the ISR
* should call the \ref Cy_I2S_WriteTxData as many times as required for your * should call the \ref Cy_I2S_WriteTxData as many times as required for your
* FIFO payload, but not more than FIFO size. Then call \ref Cy_I2S_ClearInterrupt * FIFO payload, but not more than the FIFO size. Then call \ref Cy_I2S_ClearInterrupt
* with appropriate parameters. * with appropriate parameters.
* *
* The I2S/Left Justified data formats always contains two data channels. * The I2S/Left Justified data formats always contains two data channels.
@ -73,19 +73,20 @@
* left channel will finally sound, for right-only case zero should go first). * left channel will finally sound, for right-only case zero should go first).
* The TDM frame word order in FIFOs is similar, one-by-one. * The TDM frame word order in FIFOs is similar, one-by-one.
* *
* If DMA is used and a DMA channel is properly configured - no CPU activity * If a DMA is used and the DMA channel is properly configured - no CPU activity
* (or any application code) is needed for I2S operation. * (or any application code) is needed for I2S operation.
* *
* The I2S frame looks like the next: * The I2S frame appears as:
* \image html i2s_frame.png * \image html i2s_frame.png
* This is an example for channel length = 32. The similar is for all the rest * This is an example for the channel length = 32. A similar is for all the rest
* channel lengths, with only limitation: the word length could be less or equal * channel lengths, with one limitation: the word length could be less or equal
* to the channel length. See the device Technical Reference Manual (TRM) * to the channel length. See the device Technical Reference Manual (TRM)
* for more details. * for more details.
* *
* \section group_i2s_more_information More Information * \section group_i2s_more_information More Information
* See the the I2S chapter of the device technical reference manual (TRM). * See: the the I2S chapter of the device technical reference manual (TRM);
* Also, see I2S_PDL Component datasheet. * I2S_PDL Component datasheet;
* CE218636 - PSOC 6 MCU INTER-IC SOUND (I2S) EXAMPLE.
* *
* \section group_i2s_MISRA MISRA-C Compliance * \section group_i2s_MISRA MISRA-C Compliance
* The I2S driver has the following specific deviations: * The I2S driver has the following specific deviations:
@ -99,12 +100,12 @@
* <tr> * <tr>
* <td>11.4</td> * <td>11.4</td>
* <td>A</td> * <td>A</td>
* <td>A cast should not be performed between a pointer to object type and * <td>A cast should not be performed between a pointer to the object type and
* a different pointer to object type.</td> * a different pointer to the object type.</td>
* <td>The function \ref Cy_I2S_DeepSleepCallback is a callback of * <td>The function \ref Cy_I2S_DeepSleepCallback is a callback of
* \ref cy_en_syspm_status_t type. The cast operation safety in this * \ref cy_en_syspm_status_t type. The cast operation safety in this
* function becomes the user responsibility because pointer are * function becomes the user responsibility because the pointer is
* initialized when callback is registered in SysPm driver.</td> * initialized when a callback is registered in the SysPm driver.</td>
* </tr> * </tr>
* </table> * </table>
* *
@ -112,21 +113,29 @@
* <table class="doxtable"> * <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr> * <tr>
* <td>1.0</td> * <td>2.0.1</td>
* <td>Initial version</td> * <td>Added Low Power Callback section</td>
* <td></td> * <td>Documentation update and clarification</td>
* </tr> * </tr>
* <tr> * <tr>
* <td>2.0</td> * <td>2.0</td>
* <td>The slave operation is added, Left Justified and TDM modes are added</td> * <td>The slave operation is added, Left Justified and TDM modes are added</td>
* <td></td> * <td></td>
* </tr> * </tr>
* <tr>
* <td>1.0</td>
* <td>Initial version</td>
* <td></td>
* </tr>
* </table> * </table>
* *
* \defgroup group_i2s_macros Macros * \defgroup group_i2s_macros Macros
* \defgroup group_i2s_functions Functions * \defgroup group_i2s_functions Functions
* \{
* \defgroup group_i2s_functions_syspm_callback Low Power Callback
* \}
* \defgroup group_i2s_data_structures Data Structures * \defgroup group_i2s_data_structures Data Structures
* \defgroup group_i2s_enums Enumerated types * \defgroup group_i2s_enums Enumerated Types
*/ */
@ -150,13 +159,13 @@ extern "C" {
* \{ * \{
*/ */
/** Driver major version */ /** The driver major version */
#define CY_I2S_DRV_VERSION_MAJOR 2 #define CY_I2S_DRV_VERSION_MAJOR 2
/** Driver minor version */ /** The driver minor version */
#define CY_I2S_DRV_VERSION_MINOR 0 #define CY_I2S_DRV_VERSION_MINOR 0
/** I2S driver identifier */ /** The I2S driver identifier */
#define CY_I2S_ID (CY_PDL_DRV_ID(0x20U)) #define CY_I2S_ID (CY_PDL_DRV_ID(0x20U))
/** /**
@ -288,8 +297,8 @@ typedef struct
bool txMasterMode; /**< 'false': TX in slave mode, 'true': TX in master mode. */ bool txMasterMode; /**< 'false': TX in slave mode, 'true': TX in master mode. */
cy_en_i2s_alignment_t txAlignment; /**< TX data alignment, see: #cy_en_i2s_alignment_t. */ cy_en_i2s_alignment_t txAlignment; /**< TX data alignment, see: #cy_en_i2s_alignment_t. */
cy_en_i2s_ws_pw_t txWsPulseWidth; /**< TX Word Select pulse width. cy_en_i2s_ws_pw_t txWsPulseWidth; /**< TX Word Select pulse width.
The value of this parameter is ignored in TDM modes - the WS pulse The value of this parameter is ignored in I2S and Left Justified modes
width is always "one channel length" is these modes. */ the WS pulse width is always "one channel length" in these modes. */
bool txWatchdogEnable; /**< 'false': TX watchdog disabled, 'true': TX watchdog enabled. */ bool txWatchdogEnable; /**< 'false': TX watchdog disabled, 'true': TX watchdog enabled. */
uint32_t txWatchdogValue; /**< TX watchdog counter value (32 bit). */ uint32_t txWatchdogValue; /**< TX watchdog counter value (32 bit). */
bool txSdoLatchingTime; /**< 'false': SDO bit starts at falling edge (accordingly to the I2S bool txSdoLatchingTime; /**< 'false': SDO bit starts at falling edge (accordingly to the I2S
@ -328,8 +337,8 @@ typedef struct
bool rxMasterMode; /**< 'false': RX in slave mode, 'true': RX in master mode. */ bool rxMasterMode; /**< 'false': RX in slave mode, 'true': RX in master mode. */
cy_en_i2s_alignment_t rxAlignment; /**< RX data alignment, see: #cy_en_i2s_alignment_t. */ cy_en_i2s_alignment_t rxAlignment; /**< RX data alignment, see: #cy_en_i2s_alignment_t. */
cy_en_i2s_ws_pw_t rxWsPulseWidth; /**< RX Word Select pulse width. cy_en_i2s_ws_pw_t rxWsPulseWidth; /**< RX Word Select pulse width.
The value of this parameter is ignored in TDM modes - the WS pulse The value of this parameter is ignored in I2S and Left Justified modes
width is always "one channel length" is these modes. */ the WS pulse width is always "one channel length" in these modes. */
bool rxWatchdogEnable; /**< 'false': RX watchdog disabled, 'true': RX watchdog enabled. */ bool rxWatchdogEnable; /**< 'false': RX watchdog disabled, 'true': RX watchdog enabled. */
uint32_t rxWatchdogValue; /**< RX watchdog counter value (32 bit). */ uint32_t rxWatchdogValue; /**< RX watchdog counter value (32 bit). */
bool rxSdiLatchingTime; /**< 'false': SDI bit starts at falling edge (accordingly to the I2S bool rxSdiLatchingTime; /**< 'false': SDI bit starts at falling edge (accordingly to the I2S
@ -371,17 +380,17 @@ typedef struct
/** /**
* I2S backup structure type to be used for SysPm callback * The I2S backup structure type to be used for the SysPm callback.
* \ref Cy_I2S_DeepSleepCallback context definition. * \ref Cy_I2S_DeepSleepCallback context definition.
* *
* \cond Also can be used for another purposes to store the current TX/RX * \cond Also can be used for other purposes to store the current Tx/Rx
* operation state and interrupt settings - the factors that are usually * operation state and interrupt settings - the factors that are usually
* being changed on the fly. \endcond * changed on the fly. \endcond
*/ */
typedef struct typedef struct
{ {
uint32_t enableState; /**< Stores I2S state */ uint32_t enableState; /**< Stores the I2S state */
uint32_t interruptMask; /**< Stores I2S interrupt mask */ uint32_t interruptMask; /**< Stores the I2S interrupt mask */
} cy_stc_i2s_context_t; } cy_stc_i2s_context_t;
/** \} group_i2s_data_structures */ /** \} group_i2s_data_structures */
@ -467,7 +476,13 @@ typedef struct
cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config); cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config);
void Cy_I2S_DeInit(I2S_Type * base); void Cy_I2S_DeInit(I2S_Type * base);
/** \addtogroup group_i2s_functions_syspm_callback
* The driver supports SysPm callback for Deep Sleep transition.
* \{
*/
cy_en_syspm_status_t Cy_I2S_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams); cy_en_syspm_status_t Cy_I2S_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams);
/** \} */
__STATIC_INLINE void Cy_I2S_EnableTx(I2S_Type * base); __STATIC_INLINE void Cy_I2S_EnableTx(I2S_Type * base);
__STATIC_INLINE void Cy_I2S_PauseTx(I2S_Type * base); __STATIC_INLINE void Cy_I2S_PauseTx(I2S_Type * base);
@ -513,6 +528,9 @@ __STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatusMasked(I2S_Type const * base);
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_EnableTx
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_I2S_EnableTx(I2S_Type * base) __STATIC_INLINE void Cy_I2S_EnableTx(I2S_Type * base)
{ {
@ -528,6 +546,9 @@ __STATIC_INLINE void Cy_I2S_EnableTx(I2S_Type * base)
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_PauseTx
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_I2S_PauseTx(I2S_Type * base) __STATIC_INLINE void Cy_I2S_PauseTx(I2S_Type * base)
{ {
@ -543,6 +564,9 @@ __STATIC_INLINE void Cy_I2S_PauseTx(I2S_Type * base)
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ResumeTx
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_I2S_ResumeTx(I2S_Type * base) __STATIC_INLINE void Cy_I2S_ResumeTx(I2S_Type * base)
{ {
@ -561,6 +585,9 @@ __STATIC_INLINE void Cy_I2S_ResumeTx(I2S_Type * base)
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_DisableTx
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_I2S_DisableTx(I2S_Type * base) __STATIC_INLINE void Cy_I2S_DisableTx(I2S_Type * base)
{ {
@ -580,6 +607,9 @@ __STATIC_INLINE void Cy_I2S_DisableTx(I2S_Type * base)
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_EnableRx
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_I2S_EnableRx(I2S_Type * base) __STATIC_INLINE void Cy_I2S_EnableRx(I2S_Type * base)
{ {
@ -598,6 +628,9 @@ __STATIC_INLINE void Cy_I2S_EnableRx(I2S_Type * base)
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_DisableRx
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_I2S_DisableRx(I2S_Type * base) __STATIC_INLINE void Cy_I2S_DisableRx(I2S_Type * base)
{ {
@ -612,8 +645,12 @@ __STATIC_INLINE void Cy_I2S_DisableRx(I2S_Type * base)
* Returns the current I2S state (TX/RX running/paused/stopped). * Returns the current I2S state (TX/RX running/paused/stopped).
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
*
* \return The current state \ref group_i2s_macros_current_state. * \return The current state \ref group_i2s_macros_current_state.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetCurrentState
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_I2S_GetCurrentState(I2S_Type const * base) __STATIC_INLINE uint32_t Cy_I2S_GetCurrentState(I2S_Type const * base)
{ {
@ -625,10 +662,13 @@ __STATIC_INLINE uint32_t Cy_I2S_GetCurrentState(I2S_Type const * base)
* Function Name: Cy_I2S_ClearTxFifo * Function Name: Cy_I2S_ClearTxFifo
****************************************************************************//** ****************************************************************************//**
* *
* Clears TX FIFO (resets the Read/Write FIFO pointers). * Clears the TX FIFO (resets the Read/Write FIFO pointers).
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ClearTxFifo
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_I2S_ClearTxFifo(I2S_Type * base) __STATIC_INLINE void Cy_I2S_ClearTxFifo(I2S_Type * base)
{ {
@ -645,7 +685,11 @@ __STATIC_INLINE void Cy_I2S_ClearTxFifo(I2S_Type * base)
* Gets the number of used words in the TX FIFO. * Gets the number of used words in the TX FIFO.
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
* \return The current number of used words in rge TX FIFO. *
* \return The current number of used words in the TX FIFO.
*
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetNumInTxFifo
* *
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_I2S_GetNumInTxFifo(I2S_Type const * base) __STATIC_INLINE uint32_t Cy_I2S_GetNumInTxFifo(I2S_Type const * base)
@ -661,8 +705,12 @@ __STATIC_INLINE uint32_t Cy_I2S_GetNumInTxFifo(I2S_Type const * base)
* Writes data to the TX FIFO. Increases the TX FIFO level. * Writes data to the TX FIFO. Increases the TX FIFO level.
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
*
* \param data Data to be written to the TX FIFO. * \param data Data to be written to the TX FIFO.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_WriteTxData
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_I2S_WriteTxData(I2S_Type * base, uint32_t data) __STATIC_INLINE void Cy_I2S_WriteTxData(I2S_Type * base, uint32_t data)
{ {
@ -677,8 +725,12 @@ __STATIC_INLINE void Cy_I2S_WriteTxData(I2S_Type * base, uint32_t data)
* Gets the TX FIFO Read pointer. This function is rather for debug purposes. * Gets the TX FIFO Read pointer. This function is rather for debug purposes.
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
*
* \return The current TX Read pointer value. * \return The current TX Read pointer value.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetTxReadPointer
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint8_t Cy_I2S_GetTxReadPointer(I2S_Type const * base) __STATIC_INLINE uint8_t Cy_I2S_GetTxReadPointer(I2S_Type const * base)
{ {
@ -693,8 +745,12 @@ __STATIC_INLINE uint8_t Cy_I2S_GetTxReadPointer(I2S_Type const * base)
* Gets the TX FIFO Write pointer. This function is rather for debug purposes. * Gets the TX FIFO Write pointer. This function is rather for debug purposes.
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
*
* \return The current TX Write pointer value. * \return The current TX Write pointer value.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetTxWritePointer
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint8_t Cy_I2S_GetTxWritePointer(I2S_Type const * base) __STATIC_INLINE uint8_t Cy_I2S_GetTxWritePointer(I2S_Type const * base)
{ {
@ -710,6 +766,9 @@ __STATIC_INLINE uint8_t Cy_I2S_GetTxWritePointer(I2S_Type const * base)
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_FreezeTxFifo
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_I2S_FreezeTxFifo(I2S_Type * base) __STATIC_INLINE void Cy_I2S_FreezeTxFifo(I2S_Type * base)
{ {
@ -725,6 +784,9 @@ __STATIC_INLINE void Cy_I2S_FreezeTxFifo(I2S_Type * base)
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_UnfreezeTxFifo
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_I2S_UnfreezeTxFifo(I2S_Type * base) __STATIC_INLINE void Cy_I2S_UnfreezeTxFifo(I2S_Type * base)
{ {
@ -740,6 +802,9 @@ __STATIC_INLINE void Cy_I2S_UnfreezeTxFifo(I2S_Type * base)
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ClearRxFifo
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_I2S_ClearRxFifo(I2S_Type * base) __STATIC_INLINE void Cy_I2S_ClearRxFifo(I2S_Type * base)
{ {
@ -756,8 +821,12 @@ __STATIC_INLINE void Cy_I2S_ClearRxFifo(I2S_Type * base)
* Gets the number of used words in the RX FIFO. * Gets the number of used words in the RX FIFO.
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
*
* \return The current number of used words in rge RX FIFO. * \return The current number of used words in rge RX FIFO.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetNumInRxFifo
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_I2S_GetNumInRxFifo(I2S_Type const * base) __STATIC_INLINE uint32_t Cy_I2S_GetNumInRxFifo(I2S_Type const * base)
{ {
@ -769,11 +838,15 @@ __STATIC_INLINE uint32_t Cy_I2S_GetNumInRxFifo(I2S_Type const * base)
* Function Name: Cy_I2S_ReadRxData * Function Name: Cy_I2S_ReadRxData
****************************************************************************//** ****************************************************************************//**
* *
* Reads data from the RX FIFO. Decreases the TX FIFO level. * Reads data from the RX FIFO. Decreases the RX FIFO level.
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
*
* \return The read data. * \return The read data.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ReadRxData
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_I2S_ReadRxData(I2S_Type const * base) __STATIC_INLINE uint32_t Cy_I2S_ReadRxData(I2S_Type const * base)
{ {
@ -789,8 +862,12 @@ __STATIC_INLINE uint32_t Cy_I2S_ReadRxData(I2S_Type const * base)
* This function is rather for debug purposes. * This function is rather for debug purposes.
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
*
* \return The read data. * \return The read data.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ReadRxDataSilent
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_I2S_ReadRxDataSilent(I2S_Type const * base) __STATIC_INLINE uint32_t Cy_I2S_ReadRxDataSilent(I2S_Type const * base)
{ {
@ -805,8 +882,12 @@ __STATIC_INLINE uint32_t Cy_I2S_ReadRxDataSilent(I2S_Type const * base)
* Gets the RX FIFO Read pointer. This function is rather for debug purposes. * Gets the RX FIFO Read pointer. This function is rather for debug purposes.
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
*
* \return The current RX Read pointer value. * \return The current RX Read pointer value.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetRxReadPointer
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint8_t Cy_I2S_GetRxReadPointer(I2S_Type const * base) __STATIC_INLINE uint8_t Cy_I2S_GetRxReadPointer(I2S_Type const * base)
{ {
@ -821,8 +902,12 @@ __STATIC_INLINE uint8_t Cy_I2S_GetRxReadPointer(I2S_Type const * base)
* Gets the RX FIFO Write pointer. This function is rather for debug purposes. * Gets the RX FIFO Write pointer. This function is rather for debug purposes.
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
*
* \return The current RX Write pointer value. * \return The current RX Write pointer value.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetRxWritePointer
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint8_t Cy_I2S_GetRxWritePointer(I2S_Type const * base) __STATIC_INLINE uint8_t Cy_I2S_GetRxWritePointer(I2S_Type const * base)
{ {
@ -838,6 +923,9 @@ __STATIC_INLINE uint8_t Cy_I2S_GetRxWritePointer(I2S_Type const * base)
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_FreezeRxFifo
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_I2S_FreezeRxFifo(I2S_Type * base) __STATIC_INLINE void Cy_I2S_FreezeRxFifo(I2S_Type * base)
{ {
@ -853,6 +941,9 @@ __STATIC_INLINE void Cy_I2S_FreezeRxFifo(I2S_Type * base)
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_UnfreezeRxFifo
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_I2S_UnfreezeRxFifo(I2S_Type * base) __STATIC_INLINE void Cy_I2S_UnfreezeRxFifo(I2S_Type * base)
{ {
@ -867,8 +958,12 @@ __STATIC_INLINE void Cy_I2S_UnfreezeRxFifo(I2S_Type * base)
* Gets an interrupt status (returns a content of the INTR register). * Gets an interrupt status (returns a content of the INTR register).
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
*
* \return The interrupt bit mask \ref group_i2s_macros_intrerrupt_masks. * \return The interrupt bit mask \ref group_i2s_macros_intrerrupt_masks.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetInterruptStatus
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatus(I2S_Type const * base) __STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatus(I2S_Type const * base)
{ {
@ -883,8 +978,12 @@ __STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatus(I2S_Type const * base)
* Clears one or more interrupt factors (sets the INTR register). * Clears one or more interrupt factors (sets the INTR register).
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
*
* \param interrupt Interrupt bit mask \ref group_i2s_macros_intrerrupt_masks. * \param interrupt Interrupt bit mask \ref group_i2s_macros_intrerrupt_masks.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ClearInterrupt
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_I2S_ClearInterrupt(I2S_Type * base, uint32_t interrupt) __STATIC_INLINE void Cy_I2S_ClearInterrupt(I2S_Type * base, uint32_t interrupt)
{ {
@ -901,8 +1000,12 @@ __STATIC_INLINE void Cy_I2S_ClearInterrupt(I2S_Type * base, uint32_t interrupt)
* Sets one or more interrupt factors (sets the INTR_SET register). * Sets one or more interrupt factors (sets the INTR_SET register).
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
*
* \param interrupt Interrupt bit mask \ref group_i2s_macros_intrerrupt_masks. * \param interrupt Interrupt bit mask \ref group_i2s_macros_intrerrupt_masks.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_SetInterrupt
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_I2S_SetInterrupt(I2S_Type * base, uint32_t interrupt) __STATIC_INLINE void Cy_I2S_SetInterrupt(I2S_Type * base, uint32_t interrupt)
{ {
@ -918,8 +1021,12 @@ __STATIC_INLINE void Cy_I2S_SetInterrupt(I2S_Type * base, uint32_t interrupt)
* Returns the interrupt mask (a content of the INTR_MASK register). * Returns the interrupt mask (a content of the INTR_MASK register).
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
*
* \return The interrupt bit mask \ref group_i2s_macros_intrerrupt_masks. * \return The interrupt bit mask \ref group_i2s_macros_intrerrupt_masks.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetInterruptMask
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_I2S_GetInterruptMask(I2S_Type const * base) __STATIC_INLINE uint32_t Cy_I2S_GetInterruptMask(I2S_Type const * base)
{ {
@ -934,8 +1041,12 @@ __STATIC_INLINE uint32_t Cy_I2S_GetInterruptMask(I2S_Type const * base)
* Sets one or more interrupt factor masks (the INTR_MASK register). * Sets one or more interrupt factor masks (the INTR_MASK register).
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
*
* \param interrupt Interrupt bit mask \ref group_i2s_macros_intrerrupt_masks. * \param interrupt Interrupt bit mask \ref group_i2s_macros_intrerrupt_masks.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_SetInterruptMask
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_I2S_SetInterruptMask(I2S_Type * base, uint32_t interrupt) __STATIC_INLINE void Cy_I2S_SetInterruptMask(I2S_Type * base, uint32_t interrupt)
{ {
@ -951,8 +1062,12 @@ __STATIC_INLINE void Cy_I2S_SetInterruptMask(I2S_Type * base, uint32_t interrupt
* Returns the interrupt status masked (a content of the INTR_MASKED register). * Returns the interrupt status masked (a content of the INTR_MASKED register).
* *
* \param base The pointer to the I2S instance address. * \param base The pointer to the I2S instance address.
*
* \return The interrupt bit mask(s) \ref group_i2s_macros_intrerrupt_masks. * \return The interrupt bit mask(s) \ref group_i2s_macros_intrerrupt_masks.
* *
* \funcusage
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ClearInterrupt
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatusMasked(I2S_Type const * base) __STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatusMasked(I2S_Type const * base)
{ {

25
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_drv.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_drv.c
View File

@ -1,13 +1,13 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_ipc_drv.c * \file cy_ipc_drv.c
* \version 1.10 * \version 1.10.1
* *
* \breif * \breif
* IPC Driver - This source file contains the low-level driver code for * IPC Driver - This source file contains the low-level driver code for
* the IPC hardware. * the IPC hardware.
* *
******************************************************************************** ********************************************************************************
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -24,8 +24,6 @@
* The function also has a way to specify through a parameter which IPC * The function also has a way to specify through a parameter which IPC
* interrupts must be notified during the release event. * interrupts must be notified during the release event.
* *
* This function is internal and should not be called directly by user software.
*
* \param base * \param base
* This parameter is a handle that represents the base address of the registers * This parameter is a handle that represents the base address of the registers
* of the IPC channel. * of the IPC channel.
@ -41,12 +39,10 @@
* \retval CY_IPC_DRV_ERROR: The IPC channel was not acquired before the * \retval CY_IPC_DRV_ERROR: The IPC channel was not acquired before the
* function call. * function call.
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_ReadMsgPtr
*
*******************************************************************************/ *******************************************************************************/
#if defined (__ICCARM__)
__ramfunc
#else
CY_SECTION(".cy_ramfunc")
#endif
cy_en_ipcdrv_status_t Cy_IPC_Drv_LockRelease (IPC_STRUCT_Type* base, uint32_t releaseEventIntr) cy_en_ipcdrv_status_t Cy_IPC_Drv_LockRelease (IPC_STRUCT_Type* base, uint32_t releaseEventIntr)
{ {
cy_en_ipcdrv_status_t retStatus; cy_en_ipcdrv_status_t retStatus;
@ -67,6 +63,7 @@ cy_en_ipcdrv_status_t Cy_IPC_Drv_LockRelease (IPC_STRUCT_Type* base, uint32_t re
return (retStatus); return (retStatus);
} }
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_IPC_Drv_SendMsgWord * Function Name: Cy_IPC_Drv_SendMsgWord
****************************************************************************//** ****************************************************************************//**
@ -77,8 +74,6 @@ cy_en_ipcdrv_status_t Cy_IPC_Drv_LockRelease (IPC_STRUCT_Type* base, uint32_t re
* remains locked after the function returns. The receiver of the message should * remains locked after the function returns. The receiver of the message should
* release the channel. * release the channel.
* *
* This function is internal and should not be called directly by user software.
*
* \param base * \param base
* This parameter is a handle that represents the base address of the registers * This parameter is a handle that represents the base address of the registers
* of the IPC channel. * of the IPC channel.
@ -95,6 +90,9 @@ cy_en_ipcdrv_status_t Cy_IPC_Drv_LockRelease (IPC_STRUCT_Type* base, uint32_t re
* \retval CY_IPC_DRV_SUCCESS: The send operation was successful. * \retval CY_IPC_DRV_SUCCESS: The send operation was successful.
* \retval CY_IPC_DRV_ERROR: The IPC channel is unavailable because it is already locked. * \retval CY_IPC_DRV_ERROR: The IPC channel is unavailable because it is already locked.
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_SendMsgWord
*
*******************************************************************************/ *******************************************************************************/
cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgWord (IPC_STRUCT_Type* base, uint32_t notifyEventIntr, uint32_t message) cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgWord (IPC_STRUCT_Type* base, uint32_t notifyEventIntr, uint32_t message)
{ {
@ -128,8 +126,6 @@ cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgWord (IPC_STRUCT_Type* base, uint32_t n
* Cy_IPC_Drv_Release() function after reading the message to release the * Cy_IPC_Drv_Release() function after reading the message to release the
* IPC channel. * IPC channel.
* *
* This function is internal and should not be called directly by user software.
*
* \param base * \param base
* This parameter is a handle that represents the base address of the registers * This parameter is a handle that represents the base address of the registers
* of the IPC channel. * of the IPC channel.
@ -146,6 +142,9 @@ cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgWord (IPC_STRUCT_Type* base, uint32_t n
* channel was already in a released state, meaning the data * channel was already in a released state, meaning the data
* may be invalid. * may be invalid.
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_ReadMsgWord
*
*******************************************************************************/ *******************************************************************************/
cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgWord (IPC_STRUCT_Type const * base, uint32_t * message) cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgWord (IPC_STRUCT_Type const * base, uint32_t * message)
{ {

146
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_drv.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_drv.h
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_ipc_drv.h * \file cy_ipc_drv.h
* \version 1.10 * \version 1.10.1
* *
* Provides an API declaration of the IPC driver. * Provides an API declaration of the IPC driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -34,12 +34,6 @@
* Firmware does not need to use the DRV API. It can implement IPC functionality * Firmware does not need to use the DRV API. It can implement IPC functionality
* entirely with the PIPE and SEMA APIs. * entirely with the PIPE and SEMA APIs.
* *
* \note "Warning[Ta023]: Call to a non __ramfunc function." - The warning may
* appear during the build process while using IAR IDE. The reason - some
* functions in RAM memory that use the __ramfunc keyword, may invoke
* functions located in the ROM memory. You can ignore this warning or
* disable it by adding the --diag_suppress=Ta023 option to the compiler.
*
* \section group_ipc_background Background * \section group_ipc_background Background
* *
* IPC is implemented in hardware as a collection of individual communication * IPC is implemented in hardware as a collection of individual communication
@ -170,9 +164,14 @@
* duplex communication between cores. On the CM0+ the notify interrupt is * duplex communication between cores. On the CM0+ the notify interrupt is
* assigned to NVIC IRQn 27. See System Interrupt (SysInt) for background. * assigned to NVIC IRQn 27. See System Interrupt (SysInt) for background.
* *
* To create your own pipe you should make 3 steps:
* -# Define pipe callbacks processing interrupt handler
* -# Define your pipe configuration by cy_stc_ipc_pipe_config_t type structure
* -# Call Cy_IPC_Pipe_Init() to initialize your pipe on both cores
*
* \section group_ipc_configuration_sema Configuration Considerations - SEMA * \section group_ipc_configuration_sema Configuration Considerations - SEMA
* *
* Startup code calls Cy_IPC_SystemSemaInit (in cy_ipc_config.c) to set up * Startup code calls Cy_IPC_SystemSemaInit() (in cy_ipc_config.c) to set up
* semaphore functionality. This function calls the PDL init function * semaphore functionality. This function calls the PDL init function
* Cy_IPC_Sema_Init() with default values. By default the semaphore system * Cy_IPC_Sema_Init() with default values. By default the semaphore system
* uses IPC channel 4, and creates 128 semaphores. Do <b>not</b> change the IPC * uses IPC channel 4, and creates 128 semaphores. Do <b>not</b> change the IPC
@ -191,6 +190,17 @@
* *
* \section group_ipc_more_information More Information * \section group_ipc_more_information More Information
* *
* Cy_IPC_SystemSemaInit() and Cy_IPC_SystemPipeInit() functions are called in the
* SystemInit function. If the default startup file is not used, or SystemInit is
* not called in your project, call the following three functions prior to
* executing any flash or EmEEPROM write or erase operation. For example:
* -# Cy_IPC_SystemSemaInit()
* -# Cy_IPC_SystemPipeInit()
* -# Cy_Flash_Init()
*
* Also Cy_IPC_SystemPipeInit function is called to support BLE host/controller
* communication.
*
* See the technical reference manual(TRM) for more information on the IPC. * See the technical reference manual(TRM) for more information on the IPC.
* *
* \section group_ipc_MISRA MISRA-C Compliance * \section group_ipc_MISRA MISRA-C Compliance
@ -223,6 +233,30 @@
* </tr> * </tr>
* </table> * </table>
* *
* \section group_ipc_changelog Changelog
*
* <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr>
* <td>1.10.1</td>
* <td>Updated description of the \ref Cy_IPC_Pipe_Init,
* \ref Cy_IPC_Pipe_EndpointInit, \ref Cy_IPC_Sema_Set functions.
* Added / updated code snippets.
* </td>
* <td>Documentation update and clarification</td>
* </tr>
* <tr>
* <td>1.10</td>
* <td>Added support for more IPC structures</td>
* <td>New device support</td>
* </tr>
* <tr>
* <td>1.0</td>
* <td>Initial version</td>
* <td></td>
* </tr>
* </table>
*
* \defgroup group_ipc_drv IPC driver layer (IPC_DRV) * \defgroup group_ipc_drv IPC driver layer (IPC_DRV)
* \{ * \{
* The functions of this layer are used in the higher IPC levels * The functions of this layer are used in the higher IPC levels
@ -316,7 +350,6 @@ extern "C" {
__STATIC_INLINE void Cy_IPC_Drv_WriteDataValue (IPC_STRUCT_Type* base, uint32_t dataValue); __STATIC_INLINE void Cy_IPC_Drv_WriteDataValue (IPC_STRUCT_Type* base, uint32_t dataValue);
__STATIC_INLINE uint32_t Cy_IPC_Drv_ReadDataValue (IPC_STRUCT_Type const * base); __STATIC_INLINE uint32_t Cy_IPC_Drv_ReadDataValue (IPC_STRUCT_Type const * base);
__STATIC_INLINE void Cy_IPC_Drv_ReleaseNotify (IPC_STRUCT_Type* base, uint32_t notifyEventIntr);
__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractAcquireMask (uint32_t intMask); __STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractAcquireMask (uint32_t intMask);
__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractReleaseMask (uint32_t intMask); __STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractReleaseMask (uint32_t intMask);
@ -332,6 +365,7 @@ __STATIC_INLINE IPC_STRUCT_Type* Cy_IPC_Drv_GetIpcBaseAddress (uint32_t ip
__STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_Drv_GetIntrBaseAddr (uint32_t ipcIntrIndex); __STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_Drv_GetIntrBaseAddr (uint32_t ipcIntrIndex);
__STATIC_INLINE void Cy_IPC_Drv_AcquireNotify (IPC_STRUCT_Type * base, uint32_t notifyEventIntr); __STATIC_INLINE void Cy_IPC_Drv_AcquireNotify (IPC_STRUCT_Type * base, uint32_t notifyEventIntr);
__STATIC_INLINE void Cy_IPC_Drv_ReleaseNotify (IPC_STRUCT_Type * base, uint32_t notifyEventIntr);
__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_LockAcquire (IPC_STRUCT_Type const * base); __STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_LockAcquire (IPC_STRUCT_Type const * base);
cy_en_ipcdrv_status_t Cy_IPC_Drv_LockRelease (IPC_STRUCT_Type * base, uint32_t releaseEventIntr); cy_en_ipcdrv_status_t Cy_IPC_Drv_LockRelease (IPC_STRUCT_Type * base, uint32_t releaseEventIntr);
@ -360,9 +394,6 @@ __STATIC_INLINE void Cy_IPC_Drv_ClearInterrupt (IPC_INTR_STRUCT_Type * base,
* This function takes an IPC channel index as a parameter and returns the base * This function takes an IPC channel index as a parameter and returns the base
* address the IPC registers corresponding to the IPC channel. * address the IPC registers corresponding to the IPC channel.
* *
* This function is internal and should not be called directly by user
* software.
*
* \note The user is responsible for ensuring that ipcIndex does not exceed the * \note The user is responsible for ensuring that ipcIndex does not exceed the
* limits. * limits.
* *
@ -373,6 +404,9 @@ __STATIC_INLINE void Cy_IPC_Drv_ClearInterrupt (IPC_INTR_STRUCT_Type * base,
* \return * \return
* Returns a pointer to the base of the IPC registers. * Returns a pointer to the base of the IPC registers.
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_SendMsgWord
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE IPC_STRUCT_Type* Cy_IPC_Drv_GetIpcBaseAddress (uint32_t ipcIndex) __STATIC_INLINE IPC_STRUCT_Type* Cy_IPC_Drv_GetIpcBaseAddress (uint32_t ipcIndex)
{ {
@ -387,9 +421,6 @@ __STATIC_INLINE IPC_STRUCT_Type* Cy_IPC_Drv_GetIpcBaseAddress (uint32_t ipcIndex
* This function takes an IPC interrupt structure index and returns the base * This function takes an IPC interrupt structure index and returns the base
* address of the IPC interrupt registers corresponding to the IPC Interrupt. * address of the IPC interrupt registers corresponding to the IPC Interrupt.
* *
* This function is internal and should not be called directly by user
* software.
*
* \note The user is responsible for ensuring that ipcIntrIndex does not exceed the * \note The user is responsible for ensuring that ipcIntrIndex does not exceed the
* limits. * limits.
* *
@ -400,6 +431,9 @@ __STATIC_INLINE IPC_STRUCT_Type* Cy_IPC_Drv_GetIpcBaseAddress (uint32_t ipcIndex
* \return * \return
* Returns a pointer to the base of the IPC interrupt registers. * Returns a pointer to the base of the IPC interrupt registers.
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatus
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_Drv_GetIntrBaseAddr (uint32_t ipcIntrIndex) __STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_Drv_GetIntrBaseAddr (uint32_t ipcIntrIndex)
{ {
@ -414,9 +448,6 @@ __STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_Drv_GetIntrBaseAddr (uint32_t ipcIn
* This function is used to set the interrupt mask for an IPC Interrupt. * This function is used to set the interrupt mask for an IPC Interrupt.
* The mask sets release or acquire notification events for all IPC channels. * The mask sets release or acquire notification events for all IPC channels.
* *
* This function is internal and should not be called directly by user
* software.
*
* \param base * \param base
* This is a handle to the IPC interrupt. This handle can be calculated from the * This is a handle to the IPC interrupt. This handle can be calculated from the
* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr. * IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr.
@ -429,6 +460,9 @@ __STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_Drv_GetIntrBaseAddr (uint32_t ipcIn
* An encoded list of all IPC channels that can trigger the interrupt on a * An encoded list of all IPC channels that can trigger the interrupt on a
* notify event. * notify event.
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_IPC_Drv_SetInterruptMask (IPC_INTR_STRUCT_Type* base, __STATIC_INLINE void Cy_IPC_Drv_SetInterruptMask (IPC_INTR_STRUCT_Type* base,
uint32_t ipcReleaseMask, uint32_t ipcNotifyMask) uint32_t ipcReleaseMask, uint32_t ipcNotifyMask)
@ -446,9 +480,6 @@ __STATIC_INLINE void Cy_IPC_Drv_SetInterruptMask (IPC_INTR_STRUCT_Type* base,
* *
* This function is used to read the interrupt mask. * This function is used to read the interrupt mask.
* *
* This function is internal and should not be called directly by user
* software.
*
* \param base * \param base
* This is a handle to the IPC interrupt. This handle can be calculated from * This is a handle to the IPC interrupt. This handle can be calculated from
* the IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr. * the IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr.
@ -461,6 +492,9 @@ __STATIC_INLINE void Cy_IPC_Drv_SetInterruptMask (IPC_INTR_STRUCT_Type* base,
* <tr><td>Ipc_PORTX_NOTIFY <td>X+16th bit set * <tr><td>Ipc_PORTX_NOTIFY <td>X+16th bit set
* </table> * </table>
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptMask(IPC_INTR_STRUCT_Type const * base) __STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptMask(IPC_INTR_STRUCT_Type const * base)
{ {
@ -475,9 +509,6 @@ __STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptMask(IPC_INTR_STRUCT_Type const
* can be used in the interrupt service routine to find which source triggered * can be used in the interrupt service routine to find which source triggered
* the interrupt. * the interrupt.
* *
* This function is internal and should not be called directly by user
* software.
*
* \param base * \param base
* This is a handle to the IPC interrupt. This handle can be calculated from the * This is a handle to the IPC interrupt. This handle can be calculated from the
* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr. * IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr.
@ -490,6 +521,9 @@ __STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptMask(IPC_INTR_STRUCT_Type const
* <tr><td>Ipc_PORTX_NOTIFY <td>X+16th bit set * <tr><td>Ipc_PORTX_NOTIFY <td>X+16th bit set
* </table> * </table>
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatusMasked (IPC_INTR_STRUCT_Type const * base) __STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatusMasked (IPC_INTR_STRUCT_Type const * base)
{ {
@ -503,9 +537,6 @@ __STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatusMasked (IPC_INTR_STRUCT_Ty
* This function is used to read the pending interrupts. Note that this read is * This function is used to read the pending interrupts. Note that this read is
* an unmasked read of the interrupt status. Interrupt sources read as active by * an unmasked read of the interrupt status. Interrupt sources read as active by
* this function would generate interrupts only if they were not masked. * this function would generate interrupts only if they were not masked.
* This function is internal and should not be called directly by user
* software.
* *
* \param base * \param base
* This is a handle to the IPC interrupt. This handle can be calculated from the * This is a handle to the IPC interrupt. This handle can be calculated from the
@ -519,6 +550,9 @@ __STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatusMasked (IPC_INTR_STRUCT_Ty
* <tr><td>Ipc_PORTX_NOTIFY <td>X+16th bit set * <tr><td>Ipc_PORTX_NOTIFY <td>X+16th bit set
* </table> * </table>
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatus
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatus(IPC_INTR_STRUCT_Type const * base) __STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatus(IPC_INTR_STRUCT_Type const * base)
{ {
@ -534,9 +568,6 @@ __STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatus(IPC_INTR_STRUCT_Type cons
* \note That interrupt sources set using this interrupt would generate interrupts * \note That interrupt sources set using this interrupt would generate interrupts
* only if they are not masked. * only if they are not masked.
* *
* This function is internal and should not be called directly by user
* software.
*
* \param base * \param base
* This is a handle to the IPC interrupt. This handle can be calculated from the * This is a handle to the IPC interrupt. This handle can be calculated from the
* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr. * IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr.
@ -549,6 +580,9 @@ __STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatus(IPC_INTR_STRUCT_Type cons
* An encoded list of all IPC channels that can trigger the interrupt on a * An encoded list of all IPC channels that can trigger the interrupt on a
* notify event. * notify event.
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_SetInterrupt
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_IPC_Drv_SetInterrupt(IPC_INTR_STRUCT_Type* base, uint32_t ipcReleaseMask, uint32_t ipcNotifyMask) __STATIC_INLINE void Cy_IPC_Drv_SetInterrupt(IPC_INTR_STRUCT_Type* base, uint32_t ipcReleaseMask, uint32_t ipcNotifyMask)
{ {
@ -565,9 +599,6 @@ __STATIC_INLINE void Cy_IPC_Drv_SetInterrupt(IPC_INTR_STRUCT_Type* base, uint32
* This function is used to clear the interrupt source. Use this function to clear * This function is used to clear the interrupt source. Use this function to clear
* a pending interrupt source in the interrupt status. * a pending interrupt source in the interrupt status.
* *
* This function is internal and should not be called directly by user
* software.
*
* \param base * \param base
* This is a handle to the IPC interrupt. This handle can be calculated from the * This is a handle to the IPC interrupt. This handle can be calculated from the
* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr. * IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr.
@ -580,6 +611,9 @@ __STATIC_INLINE void Cy_IPC_Drv_SetInterrupt(IPC_INTR_STRUCT_Type* base, uint32
* An encoded list of all IPC channels that can trigger the interrupt on a * An encoded list of all IPC channels that can trigger the interrupt on a
* notify event. * notify event.
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_IPC_Drv_ClearInterrupt(IPC_INTR_STRUCT_Type* base, uint32_t ipcReleaseMask, uint32_t ipcNotifyMask) __STATIC_INLINE void Cy_IPC_Drv_ClearInterrupt(IPC_INTR_STRUCT_Type* base, uint32_t ipcReleaseMask, uint32_t ipcNotifyMask)
{ {
@ -600,9 +634,6 @@ __STATIC_INLINE void Cy_IPC_Drv_ClearInterrupt(IPC_INTR_STRUCT_Type* base, uint
* *
* The function generates a notify event by IPC interrupt structures. * The function generates a notify event by IPC interrupt structures.
* *
* This function is internal and should not be called directly by user
* software.
*
* \param base * \param base
* This parameter is a handle that represents the base address of the registers * This parameter is a handle that represents the base address of the registers
* of the IPC channel. * of the IPC channel.
@ -614,6 +645,9 @@ __STATIC_INLINE void Cy_IPC_Drv_ClearInterrupt(IPC_INTR_STRUCT_Type* base, uint
* by a notification. Bit number correspond to number of the IPC interrupt * by a notification. Bit number correspond to number of the IPC interrupt
* structure. * structure.
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_LockAcquire
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_IPC_Drv_AcquireNotify (IPC_STRUCT_Type* base, uint32_t notifyEventIntr) __STATIC_INLINE void Cy_IPC_Drv_AcquireNotify (IPC_STRUCT_Type* base, uint32_t notifyEventIntr)
{ {
@ -627,9 +661,6 @@ __STATIC_INLINE void Cy_IPC_Drv_AcquireNotify (IPC_STRUCT_Type* base, uint32_t
* *
* The function generates a notify event to an IPC interrupt structure. * The function generates a notify event to an IPC interrupt structure.
* *
* This function is internal and should not be called directly by user
* software.
*
* \param base * \param base
* This parameter is a handle that represents the base address of the registers * This parameter is a handle that represents the base address of the registers
* of the IPC channel. * of the IPC channel.
@ -639,6 +670,9 @@ __STATIC_INLINE void Cy_IPC_Drv_AcquireNotify (IPC_STRUCT_Type* base, uint32_t
* \param notifyEventIntr * \param notifyEventIntr
* Bit encoded list of IPC interrupt lines that are triggered by a notification. * Bit encoded list of IPC interrupt lines that are triggered by a notification.
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_ReadMsgWord
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_IPC_Drv_ReleaseNotify (IPC_STRUCT_Type* base, uint32_t notifyEventIntr) __STATIC_INLINE void Cy_IPC_Drv_ReleaseNotify (IPC_STRUCT_Type* base, uint32_t notifyEventIntr)
{ {
@ -689,11 +723,6 @@ __STATIC_INLINE void Cy_IPC_Drv_WriteDataValue (IPC_STRUCT_Type* base, uint3
* Value from DATA register. * Value from DATA register.
* *
*******************************************************************************/ *******************************************************************************/
#if defined (__ICCARM__)
__ramfunc
#else
CY_SECTION(".cy_ramfunc")
#endif
__STATIC_INLINE uint32_t Cy_IPC_Drv_ReadDataValue (IPC_STRUCT_Type const * base) __STATIC_INLINE uint32_t Cy_IPC_Drv_ReadDataValue (IPC_STRUCT_Type const * base)
{ {
return (base->DATA); return (base->DATA);
@ -706,9 +735,6 @@ __STATIC_INLINE uint32_t Cy_IPC_Drv_ReadDataValue (IPC_STRUCT_Type const * base)
* The function is used to test the status of an IPC channel. The function * The function is used to test the status of an IPC channel. The function
* tells the reader if the IPC channel was in the locked or released state. * tells the reader if the IPC channel was in the locked or released state.
* *
* This function is internal and should not be called directly by user
* software.
*
* \param base * \param base
* This parameter is a handle that represents the base address of the registers * This parameter is a handle that represents the base address of the registers
* of the IPC channel. * of the IPC channel.
@ -720,6 +746,9 @@ __STATIC_INLINE uint32_t Cy_IPC_Drv_ReadDataValue (IPC_STRUCT_Type const * base)
* true: The IPC channel is in the Locked state. * true: The IPC channel is in the Locked state.
* false: The IPC channel is in the Released state. * false: The IPC channel is in the Released state.
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_LockAcquire
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE bool Cy_IPC_Drv_IsLockAcquired (IPC_STRUCT_Type const * base) __STATIC_INLINE bool Cy_IPC_Drv_IsLockAcquired (IPC_STRUCT_Type const * base)
{ {
@ -732,9 +761,6 @@ __STATIC_INLINE bool Cy_IPC_Drv_IsLockAcquired (IPC_STRUCT_Type const * base)
* *
* The function is used to get the status of an IPC channel. * The function is used to get the status of an IPC channel.
* *
* This function is internal and should not be called directly by user
* software.
*
* \param base * \param base
* This parameter is a handle that represents the base address of the registers * This parameter is a handle that represents the base address of the registers
* of the IPC channel. * of the IPC channel.
@ -744,6 +770,9 @@ __STATIC_INLINE bool Cy_IPC_Drv_IsLockAcquired (IPC_STRUCT_Type const * base)
* \return * \return
* Value from LOCK_STATUS register. * Value from LOCK_STATUS register.
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetLockStatus
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_IPC_Drv_GetLockStatus (IPC_STRUCT_Type const * base) __STATIC_INLINE uint32_t Cy_IPC_Drv_GetLockStatus (IPC_STRUCT_Type const * base)
{ {
@ -806,8 +835,6 @@ __STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractReleaseMask (uint32_t intMask)
* The function also has an associated notification field that will let the * The function also has an associated notification field that will let the
* message notify one or multiple interrupts. * message notify one or multiple interrupts.
* *
* This function is internal and should not be called directly by user software.
*
* \param base * \param base
* This parameter is a handle that represents the base address of the registers * This parameter is a handle that represents the base address of the registers
* of the IPC channel. * of the IPC channel.
@ -826,6 +853,9 @@ __STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractReleaseMask (uint32_t intMask)
* \retval CY_IPC_DRV_ERROR: The IPC channel is unavailable because * \retval CY_IPC_DRV_ERROR: The IPC channel is unavailable because
* it is already locked. * it is already locked.
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_SendMsgPtr
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgPtr(IPC_STRUCT_Type* base, uint32_t notifyEventIntr, void const * msgPtr) __STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgPtr(IPC_STRUCT_Type* base, uint32_t notifyEventIntr, void const * msgPtr)
{ {
@ -839,8 +869,6 @@ __STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgPtr(IPC_STRUCT_Type* ba
* *
* This function is used to read a 32-bit pointer message through an IPC channel. * This function is used to read a 32-bit pointer message through an IPC channel.
* *
* This function is internal and should not be called directly by user software.
*
* \param base * \param base
* This parameter is a handle that represents the base address of the registers * This parameter is a handle that represents the base address of the registers
* of the IPC channel. * of the IPC channel.
@ -859,6 +887,9 @@ __STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgPtr(IPC_STRUCT_Type* ba
* channel was already in a released state meaning the data * channel was already in a released state meaning the data
* in it is invalid. * in it is invalid.
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_ReadMsgPtr
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgPtr (IPC_STRUCT_Type const * base, void ** msgPtr) __STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgPtr (IPC_STRUCT_Type const * base, void ** msgPtr)
{ {
@ -872,8 +903,6 @@ __STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgPtr (IPC_STRUCT_Type c
* *
* This function is used to acquire the IPC channel. * This function is used to acquire the IPC channel.
* *
* This function is internal and should not be called directly by user software
*
* \param base * \param base
* This parameter is a handle that represents the base address of the registers * This parameter is a handle that represents the base address of the registers
* of the IPC channel. * of the IPC channel.
@ -885,6 +914,9 @@ __STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgPtr (IPC_STRUCT_Type c
* \retval CY_IPC_DRV_ERROR: The IPC was not acquired because it was already acquired * \retval CY_IPC_DRV_ERROR: The IPC was not acquired because it was already acquired
* by another master * by another master
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_LockAcquire
*
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_LockAcquire (IPC_STRUCT_Type const * base) __STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_LockAcquire (IPC_STRUCT_Type const * base)
{ {

59
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_pipe.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_pipe.c
View File

@ -1,13 +1,13 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_ipc_pipe.c * \file cy_ipc_pipe.c
* \version 1.10 * \version 1.10.1
* *
* Description: * Description:
* IPC Pipe Driver - This source file includes code for the Pipe layer on top * IPC Pipe Driver - This source file includes code for the Pipe layer on top
* of the IPC driver. * of the IPC driver.
* *
******************************************************************************** ********************************************************************************
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -25,10 +25,18 @@ static cy_stc_ipc_pipe_ep_t * cy_ipc_pipe_epArray = NULL;
* This function stores a copy of a pointer to the array of endpoints. All * This function stores a copy of a pointer to the array of endpoints. All
* access to endpoints will be via the index of the endpoint in this array. * access to endpoints will be via the index of the endpoint in this array.
* *
* \note In general case, this function is called in the default startup code,
* so user doesn't need to call it anywhere.
* However, it may be useful in case of some pipe customizations.
*
* \param theEpArray * \param theEpArray
* This is the pointer to an array of endpoint structures that the designer * This is the pointer to an array of endpoint structures that the designer
* created and will be used to reference all endpoints. * created and will be used to reference all endpoints.
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeEpArray
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_Config
*
*******************************************************************************/ *******************************************************************************/
void Cy_IPC_Pipe_Config(cy_stc_ipc_pipe_ep_t * theEpArray) void Cy_IPC_Pipe_Config(cy_stc_ipc_pipe_ep_t * theEpArray)
{ {
@ -46,9 +54,18 @@ void Cy_IPC_Pipe_Config(cy_stc_ipc_pipe_ep_t * theEpArray)
* Initializes the system pipes. The system pipes are used by BLE. * Initializes the system pipes. The system pipes are used by BLE.
* \note The function should be called on all CPUs. * \note The function should be called on all CPUs.
* *
* \note In general case, this function is called in the default startup code,
* so user doesn't need to call it anywhere.
* However, it may be useful in case of some pipe customizations.
*
* \param config * \param config
* This is the pointer to the pipe configuration structure * This is the pointer to the pipe configuration structure
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeCbArray
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeEpConfig
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_Init
*
*******************************************************************************/ *******************************************************************************/
void Cy_IPC_Pipe_Init(cy_stc_ipc_pipe_config_t const *config) void Cy_IPC_Pipe_Init(cy_stc_ipc_pipe_config_t const *config)
{ {
@ -123,6 +140,10 @@ void Cy_IPC_Pipe_Init(cy_stc_ipc_pipe_config_t const *config)
* with the callback functions for that endpoint using the * with the callback functions for that endpoint using the
* Cy_IPC_Pipe_RegisterCallback() function. * Cy_IPC_Pipe_RegisterCallback() function.
* *
* \note In general case, this function is called within \ref Cy_IPC_Pipe_Init,
* so user doesn't need to call it anywhere.
* However, it may be useful in case of some pipe/endpoint customizations.
*
* \param epAddr * \param epAddr
* This parameter is the address (or index in the array of endpoint structures) * This parameter is the address (or index in the array of endpoint structures)
* that designates the endpoint you want to initialize. * that designates the endpoint you want to initialize.
@ -145,6 +166,11 @@ void Cy_IPC_Pipe_Init(cy_stc_ipc_pipe_config_t const *config)
* \param epInterrupt * \param epInterrupt
* This is a pointer to the endpoint interrupt description structure. * This is a pointer to the endpoint interrupt description structure.
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeCbArray
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeEpConfig
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_EndpointInit
*
*******************************************************************************/ *******************************************************************************/
void Cy_IPC_Pipe_EndpointInit(uint32_t epAddr, cy_ipc_pipe_callback_array_ptr_t cbArray, void Cy_IPC_Pipe_EndpointInit(uint32_t epAddr, cy_ipc_pipe_callback_array_ptr_t cbArray,
uint32_t cbCnt, uint32_t epConfig, cy_stc_sysint_t const *epInterrupt) uint32_t cbCnt, uint32_t epConfig, cy_stc_sysint_t const *epInterrupt)
@ -208,6 +234,10 @@ void Cy_IPC_Pipe_EndpointInit(uint32_t epAddr, cy_ipc_pipe_callback_array_ptr_t
* CY_IPC_PIPE_ERROR_BAD_HANDLE: The handle provided for the pipe was not valid * CY_IPC_PIPE_ERROR_BAD_HANDLE: The handle provided for the pipe was not valid
* CY_IPC_PIPE_ERROR_SEND_BUSY: The pipe is already busy sending a message * CY_IPC_PIPE_ERROR_SEND_BUSY: The pipe is already busy sending a message
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myReleaseCallback
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_SendMessage
*
*******************************************************************************/ *******************************************************************************/
cy_en_ipc_pipe_status_t Cy_IPC_Pipe_SendMessage(uint32_t toAddr, uint32_t fromAddr, cy_en_ipc_pipe_status_t Cy_IPC_Pipe_SendMessage(uint32_t toAddr, uint32_t fromAddr,
void * msgPtr, cy_ipc_pipe_relcallback_ptr_t callBackPtr) void * msgPtr, cy_ipc_pipe_relcallback_ptr_t callBackPtr)
@ -299,6 +329,7 @@ cy_en_ipc_pipe_status_t Cy_IPC_Pipe_SendMessage(uint32_t toAddr, uint32_t fromAd
* *
* \param callBackPtr * \param callBackPtr
* Pointer to the callback function called when the endpoint has received a message. * Pointer to the callback function called when the endpoint has received a message.
* If this parameters is NULL current callback will be unregistered.
* *
* \param clientId * \param clientId
* The index in the callback array (Client ID) where the function pointer is saved. * The index in the callback array (Client ID) where the function pointer is saved.
@ -306,13 +337,17 @@ cy_en_ipc_pipe_status_t Cy_IPC_Pipe_SendMessage(uint32_t toAddr, uint32_t fromAd
* \return * \return
* CY_IPC_PIPE_SUCCESS: Callback registered successfully * CY_IPC_PIPE_SUCCESS: Callback registered successfully
* CY_IPC_PIPE_ERROR_BAD_CLIENT: Client ID out of range, callback not registered. * CY_IPC_PIPE_ERROR_BAD_CLIENT: Client ID out of range, callback not registered.
*
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myAcquireCallback
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_RegisterCallback
*
*******************************************************************************/ *******************************************************************************/
cy_en_ipc_pipe_status_t Cy_IPC_Pipe_RegisterCallback(uint32_t epAddr, cy_ipc_pipe_callback_ptr_t callBackPtr, uint32_t clientId) cy_en_ipc_pipe_status_t Cy_IPC_Pipe_RegisterCallback(uint32_t epAddr, cy_ipc_pipe_callback_ptr_t callBackPtr, uint32_t clientId)
{ {
cy_en_ipc_pipe_status_t returnStatus; cy_en_ipc_pipe_status_t returnStatus;
cy_stc_ipc_pipe_ep_t * thisEp; cy_stc_ipc_pipe_ep_t * thisEp;
CY_ASSERT_L1(NULL != callBackPtr);
CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr); CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr);
thisEp = &cy_ipc_pipe_epArray[epAddr]; thisEp = &cy_ipc_pipe_epArray[epAddr];
@ -346,15 +381,20 @@ cy_en_ipc_pipe_status_t Cy_IPC_Pipe_RegisterCallback(uint32_t epAddr, cy_ipc_pip
* *
* \param callBackPtr * \param callBackPtr
* Pointer to the callback executed when the endpoint has received a message. * Pointer to the callback executed when the endpoint has received a message.
* If this parameters is NULL current callback will be unregistered.
* *
* \return * \return
* None * None
*
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myDefaultReleaseCallback
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_RegisterCallbackRel
*
*******************************************************************************/ *******************************************************************************/
void Cy_IPC_Pipe_RegisterCallbackRel(uint32_t epAddr, cy_ipc_pipe_relcallback_ptr_t callBackPtr) void Cy_IPC_Pipe_RegisterCallbackRel(uint32_t epAddr, cy_ipc_pipe_relcallback_ptr_t callBackPtr)
{ {
cy_stc_ipc_pipe_ep_t * endpoint; cy_stc_ipc_pipe_ep_t * endpoint;
CY_ASSERT_L1(NULL != callBackPtr);
CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr); CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr);
endpoint = &cy_ipc_pipe_epArray[epAddr]; endpoint = &cy_ipc_pipe_epArray[epAddr];
@ -375,6 +415,11 @@ void Cy_IPC_Pipe_RegisterCallbackRel(uint32_t epAddr, cy_ipc_pipe_relcallback_pt
* *
* \return * \return
* None * None
*
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeEpArray
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_ExecCallback
*
*******************************************************************************/ *******************************************************************************/
void Cy_IPC_Pipe_ExecCallback(cy_stc_ipc_pipe_ep_t * endpoint) void Cy_IPC_Pipe_ExecCallback(cy_stc_ipc_pipe_ep_t * endpoint)
{ {
@ -467,6 +512,9 @@ void Cy_IPC_Pipe_ExecCallback(cy_stc_ipc_pipe_ep_t * endpoint)
* \return * \return
* CY_IPC_PIPE_SUCCESS: Callback registered successfully * CY_IPC_PIPE_SUCCESS: Callback registered successfully
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_EndpointPauseResume
*
*******************************************************************************/ *******************************************************************************/
cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointPause(uint32_t epAddr) cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointPause(uint32_t epAddr)
{ {
@ -495,6 +543,9 @@ cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointPause(uint32_t epAddr)
* \return * \return
* CY_IPC_PIPE_SUCCESS: Callback registered successfully * CY_IPC_PIPE_SUCCESS: Callback registered successfully
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_EndpointPauseResume
*
*******************************************************************************/ *******************************************************************************/
cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointResume(uint32_t epAddr) cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointResume(uint32_t epAddr)
{ {

4
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_pipe.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_pipe.h
View File

@ -1,13 +1,13 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_ipc_pipe.h * \file cy_ipc_pipe.h
* \version 1.10 * \version 1.10.1
* *
* Description: * Description:
* IPC Pipe Driver - This header file contains all the function prototypes, * IPC Pipe Driver - This header file contains all the function prototypes,
* structure definitions, pipe constants, and pipe endpoint address definitions. * structure definitions, pipe constants, and pipe endpoint address definitions.
* *
******************************************************************************** ********************************************************************************
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.

52
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_sema.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_sema.c
View File

@ -1,13 +1,13 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_ipc_sema.c * \file cy_ipc_sema.c
* \version 1.10 * \version 1.10.1
* *
* Description: * Description:
* IPC Semaphore Driver - This source file contains the source code for the * IPC Semaphore Driver - This source file contains the source code for the
* semaphore level APIs for the IPC interface. * semaphore level APIs for the IPC interface.
* *
******************************************************************************** ********************************************************************************
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -27,7 +27,8 @@ static IPC_STRUCT_Type* cy_semaIpcStruct;
/* /*
* Internal IPC semaphore control data structure. * Internal IPC semaphore control data structure.
*/ */
typedef struct { typedef struct
{
uint32_t maxSema; /* Maximum semaphores in system */ uint32_t maxSema; /* Maximum semaphores in system */
uint32_t *arrayPtr; /* Pointer to semaphores array */ uint32_t *arrayPtr; /* Pointer to semaphores array */
} cy_stc_ipc_sema_t; } cy_stc_ipc_sema_t;
@ -56,12 +57,15 @@ typedef struct {
* \param memPtr * \param memPtr
* This points to the array of (count/32) words that contain the semaphore data. * This points to the array of (count/32) words that contain the semaphore data.
* *
* \return * \return Status of the operation
* \retval CY_IPC_SEMA_SUCCESS: Successfully initialized * \retval CY_IPC_SEMA_SUCCESS: Successfully initialized
* \retval CY_IPC_SEMA_BAD_PARAM: Memory pointer is NULL and count is not zero, * \retval CY_IPC_SEMA_BAD_PARAM: Memory pointer is NULL and count is not zero,
* or count not multiple of 32 * or count not multiple of 32
* \retval CY_IPC_SEMA_ERROR_LOCKED: Could not acquire semaphores IPC channel * \retval CY_IPC_SEMA_ERROR_LOCKED: Could not acquire semaphores IPC channel
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_Init
*
*******************************************************************************/ *******************************************************************************/
cy_en_ipcsema_status_t Cy_IPC_Sema_Init(uint32_t ipcChannel, cy_en_ipcsema_status_t Cy_IPC_Sema_Init(uint32_t ipcChannel,
uint32_t count, uint32_t memPtr[]) uint32_t count, uint32_t memPtr[])
@ -144,7 +148,8 @@ cy_en_ipcsema_status_t Cy_IPC_Sema_Init(uint32_t ipcChannel,
* CY_IPC_SEMA_LOCKED. * CY_IPC_SEMA_LOCKED.
* *
* It first acquires the IPC channel that is used for all the semaphores, sets * It first acquires the IPC channel that is used for all the semaphores, sets
* the semaphore if it is cleared, then releases the IPC channel used for the semaphore. * the semaphore if it is cleared, then releases the IPC channel used for the
* semaphore.
* *
* \param semaNumber * \param semaNumber
* The semaphore number to acquire. * The semaphore number to acquire.
@ -153,13 +158,22 @@ cy_en_ipcsema_status_t Cy_IPC_Sema_Init(uint32_t ipcChannel,
* When this parameter is enabled the function can be preempted by another * When this parameter is enabled the function can be preempted by another
* task or other forms of context switching in an RTOS environment. * task or other forms of context switching in an RTOS environment.
* *
* \return * \note
* If <b>preemptable</b> is enabled (true), the user must ensure that there are
* no deadlocks in the system, which can be caused by an interrupt that occurs
* after the IPC channel is locked. Unless the user is ready to handle IPC
* channel locks correctly at the application level, set <b>premptable</b> to
* false.
*
* \return Status of the operation
* \retval CY_IPC_SEMA_SUCCESS: The semaphore was set successfully * \retval CY_IPC_SEMA_SUCCESS: The semaphore was set successfully
* \retval CY_IPC_SEMA_LOCKED: The semaphore channel is busy or locked * \retval CY_IPC_SEMA_LOCKED: The semaphore channel is busy or locked
* by another process * by another process
* \retval CY_IPC_SEMA_NOT_ACQUIRED: Semaphore was already set * \retval CY_IPC_SEMA_NOT_ACQUIRED: Semaphore was already set
* \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid * \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_Set
* *
*******************************************************************************/ *******************************************************************************/
cy_en_ipcsema_status_t Cy_IPC_Sema_Set(uint32_t semaNumber, bool preemptable) cy_en_ipcsema_status_t Cy_IPC_Sema_Set(uint32_t semaNumber, bool preemptable)
@ -223,7 +237,8 @@ cy_en_ipcsema_status_t Cy_IPC_Sema_Set(uint32_t semaNumber, bool preemptable)
* This functions tries to releases a semaphore. * This functions tries to releases a semaphore.
* *
* It first acquires the IPC channel that is used for all the semaphores, clears * It first acquires the IPC channel that is used for all the semaphores, clears
* the semaphore if it is set, then releases the IPC channel used for the semaphores. * the semaphore if it is set, then releases the IPC channel used for the
* semaphores.
* *
* \param semaNumber * \param semaNumber
* The index of the semaphore to release. * The index of the semaphore to release.
@ -232,12 +247,21 @@ cy_en_ipcsema_status_t Cy_IPC_Sema_Set(uint32_t semaNumber, bool preemptable)
* When this parameter is enabled the function can be preempted by another * When this parameter is enabled the function can be preempted by another
* task or other forms of context switching in an RTOS environment. * task or other forms of context switching in an RTOS environment.
* *
* \return * \note
* If <b>preemptable</b> is enabled (true), the user must ensure that there are
* no deadlocks in the system, which can be caused by an interrupt that occurs
* after the IPC channel is locked. Unless the user is ready to handle IPC
* channel locks correctly at the application level, set <b>premptable</b> to
* false.
*
* \return Status of the operation
* \retval CY_IPC_SEMA_SUCCESS: The semaphore was cleared successfully * \retval CY_IPC_SEMA_SUCCESS: The semaphore was cleared successfully
* \retval CY_IPC_SEMA_NOT_ACQUIRED: The semaphore was already cleared * \retval CY_IPC_SEMA_NOT_ACQUIRED: The semaphore was already cleared
* \retval CY_IPC_SEMA_LOCKED: The semaphore channel was semaphored or busy * \retval CY_IPC_SEMA_LOCKED: The semaphore channel was semaphored or busy
* \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid * \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_Clear
* *
*******************************************************************************/ *******************************************************************************/
cy_en_ipcsema_status_t Cy_IPC_Sema_Clear(uint32_t semaNumber, bool preemptable) cy_en_ipcsema_status_t Cy_IPC_Sema_Clear(uint32_t semaNumber, bool preemptable)
@ -301,18 +325,15 @@ cy_en_ipcsema_status_t Cy_IPC_Sema_Clear(uint32_t semaNumber, bool preemptable)
* \param semaNumber * \param semaNumber
* The index of the semaphore to return status. * The index of the semaphore to return status.
* *
* \return * \return Status of the operation
* \retval CY_IPC_SEMA_STATUS_LOCKED: The semaphore is in the set state. * \retval CY_IPC_SEMA_STATUS_LOCKED: The semaphore is in the set state.
* \retval CY_IPC_SEMA_STATUS_UNLOCKED: The semaphore is in the cleared state. * \retval CY_IPC_SEMA_STATUS_UNLOCKED: The semaphore is in the cleared state.
* \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid * \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_Status
* *
*******************************************************************************/ *******************************************************************************/
#if defined (__ICCARM__)
__ramfunc
#else
CY_SECTION(".cy_ramfunc")
#endif
cy_en_ipcsema_status_t Cy_IPC_Sema_Status(uint32_t semaNumber) cy_en_ipcsema_status_t Cy_IPC_Sema_Status(uint32_t semaNumber)
{ {
cy_en_ipcsema_status_t retStatus; cy_en_ipcsema_status_t retStatus;
@ -355,6 +376,9 @@ cy_en_ipcsema_status_t Cy_IPC_Sema_Status(uint32_t semaNumber)
* \return * \return
* Returns the semaphores quantity. * Returns the semaphores quantity.
* *
* \funcusage
* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_GetMaxSems
*
*******************************************************************************/ *******************************************************************************/
uint32_t Cy_IPC_Sema_GetMaxSems(void) uint32_t Cy_IPC_Sema_GetMaxSems(void)
{ {

4
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_sema.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_sema.h
View File

@ -1,13 +1,13 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_ipc_sema.h * \file cy_ipc_sema.h
* \version 1.10 * \version 1.10.1
* *
* \brief * \brief
* Header file for IPC SEM functions * Header file for IPC SEM functions
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.

104
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lpcomp/cy_lpcomp.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lpcomp/cy_lpcomp.c
View File

@ -1,6 +1,6 @@
/******************************************************************************* /*******************************************************************************
* \file cy_lpcomp.c * \file cy_lpcomp.c
* \version 1.10 * \version 1.10.1
* *
* \brief * \brief
* This file provides the driver code to the API for the Low Power Comparator * This file provides the driver code to the API for the Low Power Comparator
@ -8,7 +8,7 @@
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -19,6 +19,7 @@
extern "C" { extern "C" {
#endif #endif
static cy_stc_lpcomp_context_t cy_lpcomp_context;
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_LPComp_Init * Function Name: Cy_LPComp_Init
@ -46,6 +47,8 @@ cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type* base, cy_en_lpcomp_channel_t c
CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
CY_ASSERT_L3(CY_LPCOMP_IS_OUT_MODE_VALID(config->outputMode)); CY_ASSERT_L3(CY_LPCOMP_IS_OUT_MODE_VALID(config->outputMode));
CY_ASSERT_L3(CY_LPCOMP_IS_HYSTERESIS_VALID(config->hysteresis)); CY_ASSERT_L3(CY_LPCOMP_IS_HYSTERESIS_VALID(config->hysteresis));
CY_ASSERT_L3(CY_LPCOMP_IS_POWER_VALID(config->power));
CY_ASSERT_L3(CY_LPCOMP_IS_INTR_MODE_VALID(config->intType));
if ((base != NULL) && (config != NULL)) if ((base != NULL) && (config != NULL))
{ {
@ -64,6 +67,12 @@ cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type* base, cy_en_lpcomp_channel_t c
_VAL2FLD(LPCOMP_CMP1_CTRL_DSI_LEVEL1, (uint32_t)config->outputMode >> 1u); _VAL2FLD(LPCOMP_CMP1_CTRL_DSI_LEVEL1, (uint32_t)config->outputMode >> 1u);
} }
/* Save intType to use it in the Cy_LPComp_Enable() function */
cy_lpcomp_context.intType[(uint8_t)channel - 1u] = config->intType;
/* Save power to use it in the Cy_LPComp_Enable() function */
cy_lpcomp_context.power[(uint8_t)channel - 1u] = config->power;
ret = CY_LPCOMP_SUCCESS; ret = CY_LPCOMP_SUCCESS;
} }
@ -71,13 +80,85 @@ cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type* base, cy_en_lpcomp_channel_t c
} }
/*******************************************************************************
* Function Name: Cy_LPComp_Enable
****************************************************************************//**
*
* Enables the LPCOMP and sets the LPCOMP interrupt mode.
*
* \param *base
* The LPCOMP register structure pointer.
*
* \param channel
* The LPCOMP channel index.
*
* \return None
*
*******************************************************************************/
void Cy_LPComp_Enable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel)
{
cy_en_lpcomp_pwr_t powerSpeed;
CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
powerSpeed = cy_lpcomp_context.power[(uint8_t)channel - 1u];
/* Set power */
Cy_LPComp_SetPower(base, channel, powerSpeed);
/* Make delay before enabling the comparator interrupt to prevent false triggering */
if (CY_LPCOMP_MODE_ULP == powerSpeed)
{
Cy_SysLib_DelayUs(CY_LPCOMP_ULP_POWER_DELAY);
}
else if (CY_LPCOMP_MODE_LP == powerSpeed)
{
Cy_SysLib_DelayUs(CY_LPCOMP_LP_POWER_DELAY);
}
else
{
Cy_SysLib_DelayUs(CY_LPCOMP_NORMAL_POWER_DELAY);
}
/* Enable the comparator interrupt */
Cy_LPComp_SetInterruptTriggerMode(base, channel, cy_lpcomp_context.intType[(uint8_t)channel - 1u]);
}
/*******************************************************************************
* Function Name: Cy_LPComp_Disable
****************************************************************************//**
*
* Disables the LPCOMP power and sets the interrupt mode to disabled.
*
* \param *base
* The LPCOMP register structure pointer.
*
* \param channel
* The LPCOMP channel index.
*
* \return None
*
*******************************************************************************/
void Cy_LPComp_Disable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel)
{
CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
/* Disable the comparator interrupt */
Cy_LPComp_SetInterruptTriggerMode(base, channel, CY_LPCOMP_INTR_DISABLE);
/* Set power off */
Cy_LPComp_SetPower(base, channel, CY_LPCOMP_MODE_OFF);
}
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_LPComp_SetInterruptTriggerMode * Function Name: Cy_LPComp_SetInterruptTriggerMode
****************************************************************************//** ****************************************************************************//**
* *
* Sets the interrupt edge-detect mode. * Sets the interrupt edge-detect mode.
* This also controls the value provided on the output. * This also controls the value provided on the output.
* Note: Interrupts can be enabled after the block is enabled and the appropriate * \note Interrupts can be enabled after the block is enabled and the appropriate
* start-up time has elapsed: * start-up time has elapsed:
* 3 us for the normal power mode; * 3 us for the normal power mode;
* 6 us for the LP mode; * 6 us for the LP mode;
@ -112,6 +193,9 @@ void Cy_LPComp_SetInterruptTriggerMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t
{ {
base->CMP1_CTRL = _CLR_SET_FLD32U(base->CMP1_CTRL, LPCOMP_CMP1_CTRL_INTTYPE1, (uint32_t)intType); base->CMP1_CTRL = _CLR_SET_FLD32U(base->CMP1_CTRL, LPCOMP_CMP1_CTRL_INTTYPE1, (uint32_t)intType);
} }
/* Save interrupt type to use it in the Cy_LPComp_Enable() function */
cy_lpcomp_context.intType[(uint8_t)channel - 1u] = intType;
} }
@ -120,8 +204,12 @@ void Cy_LPComp_SetInterruptTriggerMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t
****************************************************************************//** ****************************************************************************//**
* *
* Sets the drive power and speeds to one of the four settings. * Sets the drive power and speeds to one of the four settings.
* Note: The comparator interrupt should be enabled after enabling of the * \note Interrupts can be enabled after the block is enabled and the appropriate
* comparator itself. Otherwise, unexpected interrupts events can occur. * start-up time has elapsed:
* 3 us for the normal power mode;
* 6 us for the LP mode;
* 50 us for the ULP mode.
* Otherwise, unexpected interrupts events can occur.
* *
* \param *base * \param *base
* The LPCOMP register structure pointer. * The LPCOMP register structure pointer.
@ -200,7 +288,7 @@ void Cy_LPComp_SetHysteresis(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel,
* comparator input can be connected to the local VREF. * comparator input can be connected to the local VREF.
* At least one unconnected input causes a comparator undefined output. * At least one unconnected input causes a comparator undefined output.
* *
* Note: Connection to AMUXBUSA/AMUXBUSB requires closing the additional * \note Connection to AMUXBUSA/AMUXBUSB requires closing the additional
* switches which are a part of the IO system. These switches can be configured * switches which are a part of the IO system. These switches can be configured
* using the HSIOM->AMUX_SPLIT_CTL[3] register. * using the HSIOM->AMUX_SPLIT_CTL[3] register.
* Refer to the appropriate Technical Reference Manual (TRM) of a device * Refer to the appropriate Technical Reference Manual (TRM) of a device
@ -347,8 +435,6 @@ void Cy_LPComp_SetOutputMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel,
* It stores the state of the LPComp enable and then disables the LPComp block * It stores the state of the LPComp enable and then disables the LPComp block
* before going to the low power modes, and recovers the LPComp power state after * before going to the low power modes, and recovers the LPComp power state after
* wake-up using the stored value. * wake-up using the stored value.
* The function attribution has a weak linkage, so the user can override this
* function for a custom lower-power callback.
* *
* \param *callbackParams * \param *callbackParams
* The \ref cy_stc_syspm_callback_params_t structure with the callback * The \ref cy_stc_syspm_callback_params_t structure with the callback
@ -458,8 +544,6 @@ cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t
* *
* This function checks the current power mode of LPComp and then disable the * This function checks the current power mode of LPComp and then disable the
* LPComp block, if there is no wake-up source from LPComp in the hibernate mode. * LPComp block, if there is no wake-up source from LPComp in the hibernate mode.
* The function attribution has a weak linkage, so the user can override this
* function for a custom lower-power callback.
* *
* \param *callbackParams * \param *callbackParams
* The \ref cy_stc_syspm_callback_params_t structure with the callback * The \ref cy_stc_syspm_callback_params_t structure with the callback

72
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lpcomp/cy_lpcomp.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lpcomp/cy_lpcomp.h
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_lpcomp.h * \file cy_lpcomp.h
* \version 1.10 * \version 1.10.1
* *
* This file provides constants and parameter values for the Low Power Comparator driver. * This file provides constants and parameter values for the Low Power Comparator driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -50,27 +50,19 @@
* to the dedicated IO pins, AMUXBUSA/AMUXBUSB or Vref: * to the dedicated IO pins, AMUXBUSA/AMUXBUSB or Vref:
* \image html lpcomp_inputs.png * \image html lpcomp_inputs.png
* *
* 4) Power on the comparator using the Cy_LPComp_SetPower() function. * 4) Power on the comparator using the Cy_LPComp_Enable() function.
* *
* 5) Optionally, enable the comparator interrupt using * 5) The comparator output can be monitored using
* Cy_LPComp_SetInterruptTriggerMode() with the corresponding parameter
* for the interrupt mode (Rising edge, Falling edge, or Both edges).
*
* 6) The comparator output can be monitored using
* the Cy_LPComp_GetCompare() function or using the LPComp interrupt * the Cy_LPComp_GetCompare() function or using the LPComp interrupt
* (if the interrupt is enabled). * (if the interrupt is enabled).
* *
* NOTE 1: To prevent false triggering, a delay before enabling * \note The interrupt is not cleared automatically.
* the comparator interrupt is required. The recommended delay is
* 10 us for the Normal power mode and 50 us for the Ultra low-power mode.
*
* NOTE 2: The interrupt is not cleared automatically.
* It is the user's responsibility to do that. * It is the user's responsibility to do that.
* The interrupt is cleared by writing a 1 in the corresponding interrupt * The interrupt is cleared by writing a 1 in the corresponding interrupt
* register bit position. The preferred way to clear interrupt sources * register bit position. The preferred way to clear interrupt sources
* is using the Cy_LPComp_ClearInterrupt() function. * is using the Cy_LPComp_ClearInterrupt() function.
* *
* NOTE 3: Individual comparator interrupt outputs are ORed together * \note Individual comparator interrupt outputs are ORed together
* as a single asynchronous interrupt source before it is sent out and * as a single asynchronous interrupt source before it is sent out and
* used to wake up the system in the low-power mode. * used to wake up the system in the low-power mode.
* For PSoC 6 devices, the individual comparator interrupt is masked * For PSoC 6 devices, the individual comparator interrupt is masked
@ -78,6 +70,17 @@
* the INTR_MASKED register. * the INTR_MASKED register.
* Writing a 1 to the INTR register bit will clear the interrupt. * Writing a 1 to the INTR register bit will clear the interrupt.
* *
* \section group_lpcomp_lp Low Power Support
* The LPComp provides the callback functions to facilitate
* the low-power mode transition. The callback
* \ref Cy_LPComp_DeepSleepCallback must be called during execution
* of \ref Cy_SysPm_DeepSleep; \ref Cy_LPComp_HibernateCallback must be
* called during execution of \ref Cy_SysPm_Hibernate.
* To trigger the callback execution, the callback must be registered
* before calling the mode transition function.
* Refer to \ref group_syspm driver for more
* information about low-power mode transitions.
*
* \section group_lpcomp_more_information More Information * \section group_lpcomp_more_information More Information
* *
* Refer to the appropriate device technical reference manual (TRM) for * Refer to the appropriate device technical reference manual (TRM) for
@ -112,9 +115,9 @@
* <table class="doxtable"> * <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr> * <tr>
* <td>1.0</td> * <td>1.10.1</td>
* <td>Initial version</td> * <td>Added Low Power Callback section</td>
* <td></td> * <td>Documentation update and clarification</td>
* </tr> * </tr>
* <tr> * <tr>
* <td>1.10</td> * <td>1.10</td>
@ -123,11 +126,19 @@
* Added input parameter validation to the API functions.</td> * Added input parameter validation to the API functions.</td>
* <td></td> * <td></td>
* </tr> * </tr>
* <tr>
* <td>1.0</td>
* <td>Initial version</td>
* <td></td>
* </tr>
* </table> * </table>
* *
* \defgroup group_lpcomp_macros Macros * \defgroup group_lpcomp_macros Macros
* \defgroup group_lpcomp_functions Functions * \defgroup group_lpcomp_functions Functions
* \defgroup group_lpcomp_data_structures Data structures * \{
* \defgroup group_lpcomp_functions_syspm_callback Low Power Callback
* \}
* \defgroup group_lpcomp_data_structures Data Structures
* \defgroup group_lpcomp_enums Enumerated Types * \defgroup group_lpcomp_enums Enumerated Types
*/ */
@ -232,6 +243,11 @@ extern "C"
#define CY_LPCOMP_WAKEUP_PIN0_Msk CY_SYSPM_WAKEUP_LPCOMP0 #define CY_LPCOMP_WAKEUP_PIN0_Msk CY_SYSPM_WAKEUP_LPCOMP0
#define CY_LPCOMP_WAKEUP_PIN1_Msk CY_SYSPM_WAKEUP_LPCOMP1 #define CY_LPCOMP_WAKEUP_PIN1_Msk CY_SYSPM_WAKEUP_LPCOMP1
/* Internal constants for Cy_LPComp_Enable() */
#define CY_LPCOMP_NORMAL_POWER_DELAY (3u)
#define CY_LPCOMP_LP_POWER_DELAY (6u)
#define CY_LPCOMP_ULP_POWER_DELAY (50u)
/** \endcond */ /** \endcond */
/** \} group_lpcomp_macros */ /** \} group_lpcomp_macros */
@ -319,8 +335,19 @@ typedef struct {
cy_en_lpcomp_out_t outputMode; /**< The LPCOMP's outputMode: Direct output, cy_en_lpcomp_out_t outputMode; /**< The LPCOMP's outputMode: Direct output,
Synchronized output or Pulse output */ Synchronized output or Pulse output */
cy_en_lpcomp_hyst_t hysteresis; /**< Enables or disables the LPCOMP's hysteresis */ cy_en_lpcomp_hyst_t hysteresis; /**< Enables or disables the LPCOMP's hysteresis */
cy_en_lpcomp_pwr_t power; /**< Sets the LPCOMP power mode */
cy_en_lpcomp_int_t intType; /**< Sets the LPCOMP interrupt mode */
} cy_stc_lpcomp_config_t; } cy_stc_lpcomp_config_t;
/** \cond CONTEXT_STRUCTURE */
typedef struct {
cy_en_lpcomp_int_t intType[CY_LPCOMP_MAX_CHANNEL_NUM];
cy_en_lpcomp_pwr_t power[CY_LPCOMP_MAX_CHANNEL_NUM];
} cy_stc_lpcomp_context_t;
/** \endcond */
/** \} group_lpcomp_data_structures */ /** \} group_lpcomp_data_structures */
/** \cond INTERNAL_MACROS */ /** \cond INTERNAL_MACROS */
@ -366,6 +393,8 @@ typedef struct {
*******************************************************************************/ *******************************************************************************/
cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type *base, cy_en_lpcomp_channel_t channel, const cy_stc_lpcomp_config_t *config); cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type *base, cy_en_lpcomp_channel_t channel, const cy_stc_lpcomp_config_t *config);
void Cy_LPComp_Enable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel);
void Cy_LPComp_Disable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel);
__STATIC_INLINE void Cy_LPComp_GlobalEnable(LPCOMP_Type *base); __STATIC_INLINE void Cy_LPComp_GlobalEnable(LPCOMP_Type *base);
__STATIC_INLINE void Cy_LPComp_GlobalDisable(LPCOMP_Type *base); __STATIC_INLINE void Cy_LPComp_GlobalDisable(LPCOMP_Type *base);
__STATIC_INLINE void Cy_LPComp_UlpReferenceEnable(LPCOMP_Type *base); __STATIC_INLINE void Cy_LPComp_UlpReferenceEnable(LPCOMP_Type *base);
@ -383,8 +412,13 @@ __STATIC_INLINE uint32_t Cy_LPComp_GetInterruptMask(LPCOMP_Type const * base);
__STATIC_INLINE void Cy_LPComp_SetInterruptMask(LPCOMP_Type* base, uint32_t interrupt); __STATIC_INLINE void Cy_LPComp_SetInterruptMask(LPCOMP_Type* base, uint32_t interrupt);
__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatusMasked(LPCOMP_Type const * base); __STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatusMasked(LPCOMP_Type const * base);
__STATIC_INLINE void Cy_LPComp_ConnectULPReference(LPCOMP_Type *base, cy_en_lpcomp_channel_t channel); __STATIC_INLINE void Cy_LPComp_ConnectULPReference(LPCOMP_Type *base, cy_en_lpcomp_channel_t channel);
/** \addtogroup group_lpcomp_functions_syspm_callback
* The driver supports SysPm callback for Deep Sleep and Hibernate transition.
* \{
*/
cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams); cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams);
cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams); cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams);
/** \} */
/******************************************************************************* /*******************************************************************************
@ -472,8 +506,6 @@ __STATIC_INLINE void Cy_LPComp_UlpReferenceDisable(LPCOMP_Type *base)
* *
* This function returns a nonzero value when the voltage connected to the * This function returns a nonzero value when the voltage connected to the
* positive input is greater than the negative input voltage. * positive input is greater than the negative input voltage.
* This function reads the direct (unflopped) comparator output, which can
* also be metastable (since it may result in incorrect data).
* *
* \param *base * \param *base
* The LPComp register structure pointer. * The LPComp register structure pointer.

8
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lvd/cy_lvd.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lvd/cy_lvd.c
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_lvd.c * \file cy_lvd.c
* \version 1.0 * \version 1.0.1
* *
* The source code file for the LVD driver. * The source code file for the LVD driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -24,9 +24,9 @@ extern "C" {
****************************************************************************//** ****************************************************************************//**
* *
* When this function is registered by \ref Cy_SysPm_RegisterCallback - it * When this function is registered by \ref Cy_SysPm_RegisterCallback - it
* automatically enables the LVD after wake up from DeepSleep mode. * automatically enables the LVD after wake up from Deep-Sleep mode.
* *
* \param callbackParams a pointer to the callback parameters structure, * \param callbackParams The pointer to the callback parameters structure,
* see \ref cy_stc_syspm_callback_params_t. * see \ref cy_stc_syspm_callback_params_t.
* *
* \return the SysPm callback status \ref cy_en_syspm_status_t. * \return the SysPm callback status \ref cy_en_syspm_status_t.

28
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lvd/cy_lvd.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lvd/cy_lvd.h
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_lvd.h * \file cy_lvd.h
* \version 1.0 * \version 1.0.1
* *
* The header file of the LVD driver. * The header file of the LVD driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -29,7 +29,7 @@
* Then configure interrupts by the \ref Cy_LVD_SetInterruptConfig function, do * Then configure interrupts by the \ref Cy_LVD_SetInterruptConfig function, do
* not forget to initialise an interrupt handler (the interrupt source number * not forget to initialise an interrupt handler (the interrupt source number
* is srss_interrupt_IRQn). * is srss_interrupt_IRQn).
* Then enable LVD by the \ref Cy_LVD_Enable function, then wait for at least 8us * Then enable LVD by the \ref Cy_LVD_Enable function, then wait for at least 20us
* to get the circuit stabilized and clear the possible false interrupts by the * to get the circuit stabilized and clear the possible false interrupts by the
* \ref Cy_LVD_ClearInterrupt, and finally the LVD interrupt can be enabled by * \ref Cy_LVD_ClearInterrupt, and finally the LVD interrupt can be enabled by
* the \ref Cy_LVD_SetInterruptMask function. * the \ref Cy_LVD_SetInterruptMask function.
@ -84,6 +84,11 @@
* <table class="doxtable"> * <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason of Change</th></tr> * <tr><th>Version</th><th>Changes</th><th>Reason of Change</th></tr>
* <tr> * <tr>
* <td>1.0.1</td>
* <td>Added Low Power Callback section</td>
* <td>Documentation update and clarification</td>
* </tr>
* <tr>
* <td>1.0</td> * <td>1.0</td>
* <td>Initial Version</td> * <td>Initial Version</td>
* <td></td> * <td></td>
@ -92,7 +97,10 @@
* *
* \defgroup group_lvd_macros Macros * \defgroup group_lvd_macros Macros
* \defgroup group_lvd_functions Functions * \defgroup group_lvd_functions Functions
* \defgroup group_lvd_enums Enumerated types * \{
* \defgroup group_lvd_functions_syspm_callback Low Power Callback
* \}
* \defgroup group_lvd_enums Enumerated Types
*/ */
@ -109,13 +117,13 @@ extern "C" {
* \{ * \{
*/ */
/** Driver major version */ /** The driver major version */
#define CY_LVD_DRV_VERSION_MAJOR 1 #define CY_LVD_DRV_VERSION_MAJOR 1
/** Driver minor version */ /** The driver minor version */
#define CY_LVD_DRV_VERSION_MINOR 0 #define CY_LVD_DRV_VERSION_MINOR 0
/** LVD driver identifier */ /** The LVD driver identifier */
#define CY_LVD_ID (CY_PDL_DRV_ID(0x39U)) #define CY_LVD_ID (CY_PDL_DRV_ID(0x39U))
/** Interrupt mask for \ref Cy_LVD_GetInterruptStatus(), /** Interrupt mask for \ref Cy_LVD_GetInterruptStatus(),
@ -217,8 +225,12 @@ __STATIC_INLINE void Cy_LVD_SetInterruptMask(void);
__STATIC_INLINE void Cy_LVD_ClearInterruptMask(void); __STATIC_INLINE void Cy_LVD_ClearInterruptMask(void);
__STATIC_INLINE uint32_t Cy_LVD_GetInterruptStatusMasked(void); __STATIC_INLINE uint32_t Cy_LVD_GetInterruptStatusMasked(void);
__STATIC_INLINE void Cy_LVD_SetInterruptConfig(cy_en_lvd_intr_config_t lvdInterruptConfig); __STATIC_INLINE void Cy_LVD_SetInterruptConfig(cy_en_lvd_intr_config_t lvdInterruptConfig);
/** \addtogroup group_lvd_functions_syspm_callback
* The driver supports SysPm callback for Deep Sleep transition.
* \{
*/
cy_en_syspm_status_t Cy_LVD_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams); cy_en_syspm_status_t Cy_LVD_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams);
/** \} */
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_LVD_Enable * Function Name: Cy_LVD_Enable

192
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/mcwdt/cy_mcwdt.c Normal file
View File

@ -0,0 +1,192 @@
/***************************************************************************//**
* \file cy_mcwdt.c
* \version 1.10.1
*
* Description:
* Provides a system API for the MCWDT driver.
*
********************************************************************************
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cy_mcwdt.h"
#if defined(__cplusplus)
extern "C" {
#endif
/*******************************************************************************
* Function Name: Cy_MCWDT_Init
****************************************************************************//**
*
* Initializes the MCWDT block.
*
* \param base
* The base pointer to a structure that describes the registers.
*
* \param config
* The pointer to a structure that contains component configuration data.
*
* \return cy_en_mcwdt_status_t
* *base checking result. If the pointer is NULL, returns error.
*
* \note
* This API should not be called when the counters are running. Prior to calling
* this API the counter should be disabled.
*
*******************************************************************************/
cy_en_mcwdt_status_t Cy_MCWDT_Init(MCWDT_STRUCT_Type *base, cy_stc_mcwdt_config_t const *config)
{
cy_en_mcwdt_status_t ret = CY_MCWDT_BAD_PARAM;
if ((base != NULL) && (config != NULL))
{
CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID(config->c0ClearOnMatch, config->c0Match));
CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID(config->c1ClearOnMatch, config->c1Match));
CY_ASSERT_L2(CY_MCWDT_IS_BIT_VALID(config->c2ToggleBit));
CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID((cy_en_mcwdtmode_t)config->c0Mode));
CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID((cy_en_mcwdtmode_t)config->c1Mode));
CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID((cy_en_mcwdtmode_t)config->c2Mode));
base->MCWDT_MATCH = _VAL2FLD(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1, config->c1Match) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0, config->c0Match);
base->MCWDT_CONFIG = _VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, config->c2ToggleBit) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2, config->c2Mode) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, config->c0ClearOnMatch) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, config->c1ClearOnMatch) |
(config->c1c2Cascade ? MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Msk : 0UL) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1, config->c1Mode) |
(config->c0c1Cascade ? MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Msk : 0UL) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0, config->c0Mode);
ret = CY_MCWDT_SUCCESS;
}
return (ret);
}
/*******************************************************************************
* Function Name: Cy_MCWDT_DeInit
****************************************************************************//**
*
* De-initializes the MCWDT block, returns register values to their default state.
*
* \param base
* The base pointer to a structure that describes the registers.
*
* \note
* This API should not be called when the counters are running. Prior to calling
* this API the counter should be disabled.
*
*******************************************************************************/
void Cy_MCWDT_DeInit(MCWDT_STRUCT_Type *base)
{
Cy_MCWDT_Unlock(base);
base->MCWDT_CNTLOW = 0UL;
base->MCWDT_CNTHIGH = 0UL;
base->MCWDT_MATCH = 0UL;
base->MCWDT_CONFIG = 0UL;
base->MCWDT_CTL = 0UL;
base->MCWDT_INTR = 0UL;
base->MCWDT_INTR_SET = 0UL;
base->MCWDT_INTR_MASK = 0UL;
}
/*******************************************************************************
* Function Name: Cy_MCWDT_GetCountCascaded
****************************************************************************//**
*
* Reports the current value of combined C1-C0 cascaded counters.
*
* \param base
* The base pointer to a structure that describes the registers.
*
* \note
* The user must enable both counters, and cascade C0 to C1,
* before calling this function. C2 is not reported.
* Instead, to get a 64-bit C2-C1-C0 cascaded value, the
* user must call this function followed by
* Cy_MCWDT_GetCount(base, CY_MCWDT_COUNTER2), and then combine the results.
* \note This function does not return the correct result when it is called
* after the Cy_MCWDT_Enable() or Cy_MCWDT_ResetCounters() function with
* a delay less than two lf_clk cycles. The recommended waitUs parameter
* value is 100 us.
*
*******************************************************************************/
uint32_t Cy_MCWDT_GetCountCascaded(MCWDT_STRUCT_Type const *base)
{
uint32_t countVal = base->MCWDT_CNTLOW;
uint32_t counter1 = countVal >> MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Pos;
uint32_t counter0 = countVal & MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Msk;
uint32_t match0 = _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0, base->MCWDT_MATCH);
uint32_t match1 = _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1, base->MCWDT_MATCH);
/*
* The counter counter0 goes to zero when it reaches the match0
* value (c0ClearOnMatch = 1) or reaches the maximum
* value (c0ClearOnMatch = 0). The counter counter1 increments on
* the next rising edge of the MCWDT clock after
* the Clear On Match event takes place.
* The software increments counter1 to eliminate the case
* when the both counter0 and counter1 counters have zeros.
*/
if (0u == counter0)
{
counter1++;
}
/* Check if the counter0 is Free running */
if (0u == _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, base->MCWDT_CONFIG))
{
/* Save match0 value with the correction when counter0
* goes to zero when it reaches the match0 value.
*/
countVal = match0 + 1u;
if (0u < counter1)
{
/* Set match to the maximum value */
match0 = MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Msk;
}
if (countVal < counter0)
{
/* Decrement counter1 when the counter0 is great than match0 value */
counter1--;
}
}
/* Add the correction to counter0 */
counter0 += counter1;
/* Set counter1 match value to 65535 when the counter1 is free running */
if (0u == _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, base->MCWDT_CONFIG))
{
match1 = MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Msk >> MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Pos;
}
/* Check for overflow */
if (match1 < counter1)
{
counter1 = 0u;
}
/* Calculate the combined value for C1-C0 cascaded counters */
countVal = counter0 + (counter1 * match0);
return (countVal);
}
#if defined(__cplusplus)
}
#endif
/* [] END OF FILE */

121
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/mcwdt/cy_mcwdt.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/mcwdt/cy_mcwdt.h
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_mcwdt.h * \file cy_mcwdt.h
* \version 1.0 * \version 1.10.1
* *
* Provides an API declaration of the Cypress PDL 3.0 MCWDT driver * Provides an API declaration of the Cypress PDL 3.0 MCWDT driver
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -15,7 +15,7 @@
/** /**
* \defgroup group_mcwdt Multi-Counter Watchdog (MCWDT) * \defgroup group_mcwdt Multi-Counter Watchdog (MCWDT)
* \{ * \{
* MCWDT has two 16-bit counters and one 32-bit counter. * A MCWDT has two 16-bit counters and one 32-bit counter.
* You can use this driver to create a free-running * You can use this driver to create a free-running
* timer or generate periodic interrupts. The driver also * timer or generate periodic interrupts. The driver also
* includes support for the watchdog function to recover from CPU or * includes support for the watchdog function to recover from CPU or
@ -64,7 +64,8 @@
* *
* You can also set the mode of operation for any counter. If you choose * You can also set the mode of operation for any counter. If you choose
* interrupt mode, use Cy_MCWDT_SetInterruptMask() with the * interrupt mode, use Cy_MCWDT_SetInterruptMask() with the
* parameter for the masks described in Macro Section. * parameter for the masks described in Macro Section. All counter interrupts
* are OR'd together to from a single combined MCWDT interrupt.
* Additionally, enable the Global interrupts and initialize the referenced * Additionally, enable the Global interrupts and initialize the referenced
* interrupt by setting the priority and the interrupt vector using * interrupt by setting the priority and the interrupt vector using
* \ref Cy_SysInt_Init() of the sysint driver. * \ref Cy_SysInt_Init() of the sysint driver.
@ -89,6 +90,17 @@
* <table class="doxtable"> * <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr> * <tr>
* <td>1.10.1</td>
* <td>Updated description of the \ref cy_stc_mcwdt_config_t structure type</td>
* <td>Documentation update and clarification</td>
* </tr>
* <tr>
* <td>1.10</td>
* <td>Added input parameter validation to the API functions.<br>
* Added API function GetCountCascaded()</td>
* <td></td>
* </tr>
* <tr>
* <td>1.0</td> * <td>1.0</td>
* <td>Initial version</td> * <td>Initial version</td>
* <td></td> * <td></td>
@ -97,7 +109,7 @@
* *
* \defgroup group_mcwdt_macros Macros * \defgroup group_mcwdt_macros Macros
* \defgroup group_mcwdt_functions Functions * \defgroup group_mcwdt_functions Functions
* \defgroup group_mcwdt_data_structures Data structures * \defgroup group_mcwdt_data_structures Data Structures
* \defgroup group_mcwdt_enums Enumerated Types * \defgroup group_mcwdt_enums Enumerated Types
*/ */
@ -139,14 +151,10 @@ typedef struct
Range: 0 - 31. */ Range: 0 - 31. */
uint8_t c2Mode; /**< The sub-counter#2 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE uint8_t c2Mode; /**< The sub-counter#2 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE
and \ref CY_MCWDT_MODE_INT. */ and \ref CY_MCWDT_MODE_INT. */
bool c0ClearOnMatch; /**< The sub-counter#0 Clear On Match parameter enabled/disabled. bool c0ClearOnMatch; /**< The sub-counter#0 Clear On Match parameter enabled/disabled. */
Range: FALSE - TRUE. */ bool c1ClearOnMatch; /**< The sub-counter#1 Clear On Match parameter enabled/disabled. */
bool c1ClearOnMatch; /**< The sub-counter#1 Clear On Match parameter enabled/disabled. bool c0c1Cascade; /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade. */
Range: FALSE - TRUE. */ bool c1c2Cascade; /**< The sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade. */
bool c0c1Cascade; /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade.
Range: FALSE - TRUE. */
bool c1c2Cascade; /**< The sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade.
Range: FALSE - TRUE. */
} cy_stc_mcwdt_config_t; } cy_stc_mcwdt_config_t;
/** \} group_mcwdt_data_structures */ /** \} group_mcwdt_data_structures */
@ -160,7 +168,7 @@ typedef struct
#define CY_MCWDT_DRV_VERSION_MAJOR 1 #define CY_MCWDT_DRV_VERSION_MAJOR 1
/** Driver minor version */ /** Driver minor version */
#define CY_MCWDT_DRV_VERSION_MINOR 0 #define CY_MCWDT_DRV_VERSION_MINOR 10
/** \cond INTERNAL_MACROS */ /** \cond INTERNAL_MACROS */
@ -189,6 +197,8 @@ typedef struct
#define CY_MCWDT_CTR2_Pos (2u) #define CY_MCWDT_CTR2_Pos (2u)
#define CY_MCWDT_CTR_Pos (0UL) #define CY_MCWDT_CTR_Pos (0UL)
#define CY_MCWDT_C2_MODE_MASK (1u)
/** \endcond */ /** \endcond */
#define CY_MCWDT_ID CY_PDL_DRV_ID(0x35u) /**< MCWDT PDL ID */ #define CY_MCWDT_ID CY_PDL_DRV_ID(0x35u) /**< MCWDT PDL ID */
@ -255,6 +265,36 @@ typedef enum
/** \} group_mcwdt_enums */ /** \} group_mcwdt_enums */
/** \cond PARAM_CHECK_MACROS */
/** Parameter check macros */
#define CY_MCWDT_IS_CNTS_MASK_VALID(counters) (0U == ((counters) & (uint32_t)~CY_MCWDT_CTR_Msk))
#define CY_MCWDT_IS_CNT_NUM_VALID(counter) ((CY_MCWDT_COUNTER0 == (counter)) || \
(CY_MCWDT_COUNTER1 == (counter)) || \
(CY_MCWDT_COUNTER2 == (counter)))
#define CY_MCWDT_IS_MODE_VALID(mode) ((CY_MCWDT_MODE_NONE == (mode)) || \
(CY_MCWDT_MODE_INT == (mode)) || \
(CY_MCWDT_MODE_RESET == (mode)) || \
(CY_MCWDT_MODE_INT_RESET == (mode)))
#define CY_MCWDT_IS_ENABLE_VALID(enable) (1UL >= (enable))
#define CY_MCWDT_IS_CASCADE_VALID(cascade) ((CY_MCWDT_CASCADE_NONE == (cascade)) || \
(CY_MCWDT_CASCADE_C0C1 == (cascade)) || \
(CY_MCWDT_CASCADE_C1C2 == (cascade)) || \
(CY_MCWDT_CASCADE_BOTH == (cascade)))
#define CY_MCWDT_IS_MATCH_VALID(clearOnMatch, match) ((clearOnMatch) ? (1UL <= (match)) : true)
#define CY_MCWDT_IS_BIT_VALID(bit) (31UL >= (bit))
/** \endcond */
/******************************************************************************* /*******************************************************************************
* Function Prototypes * Function Prototypes
*******************************************************************************/ *******************************************************************************/
@ -289,6 +329,7 @@ __STATIC_INLINE void Cy_MCWDT_SetInterrupt(MCWDT_STRUCT_Type *base, uint32_t
__STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const *base); __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const *base);
__STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t counters); __STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t counters);
__STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatusMasked(MCWDT_STRUCT_Type const *base); __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatusMasked(MCWDT_STRUCT_Type const *base);
uint32_t Cy_MCWDT_GetCountCascaded(MCWDT_STRUCT_Type const *base);
/******************************************************************************* /*******************************************************************************
@ -319,6 +360,8 @@ __STATIC_INLINE void Cy_MCWDT_Enable(MCWDT_STRUCT_Type *base, uint32_t counters,
{ {
uint32_t enableCounters; uint32_t enableCounters;
CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
/* Extract particular counters for enable */ /* Extract particular counters for enable */
enableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) | enableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) |
((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) | ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) |
@ -358,6 +401,8 @@ __STATIC_INLINE void Cy_MCWDT_Disable(MCWDT_STRUCT_Type *base, uint32_t counters
{ {
uint32_t disableCounters; uint32_t disableCounters;
CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
/* Extract particular counters for disable */ /* Extract particular counters for disable */
disableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) | disableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) |
((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) | ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) |
@ -389,6 +434,8 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetEnabledStatus(MCWDT_STRUCT_Type const *base
{ {
uint32_t status = 0u; uint32_t status = 0u;
CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
switch (counter) switch (counter)
{ {
case CY_MCWDT_COUNTER0: case CY_MCWDT_COUNTER0:
@ -501,6 +548,9 @@ __STATIC_INLINE void Cy_MCWDT_SetMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t
{ {
uint32_t mask, shift; uint32_t mask, shift;
CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID(mode));
shift = CY_MCWDT_BYTE_SHIFT * counter; shift = CY_MCWDT_BYTE_SHIFT * counter;
mask = (counter == CY_MCWDT_COUNTER2) ? CY_MCWDT_C2_MODE_MASK : CY_MCWDT_C0C1_MODE_MASK; mask = (counter == CY_MCWDT_COUNTER2) ? CY_MCWDT_C2_MODE_MASK : CY_MCWDT_C0C1_MODE_MASK;
mask = mask << shift; mask = mask << shift;
@ -529,6 +579,8 @@ __STATIC_INLINE cy_en_mcwdtmode_t Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const *base
{ {
uint32_t mode, mask; uint32_t mode, mask;
CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
mask = (counter == CY_MCWDT_COUNTER2) ? CY_MCWDT_C2_MODE_MASK : CY_MCWDT_C0C1_MODE_MASK; mask = (counter == CY_MCWDT_COUNTER2) ? CY_MCWDT_C2_MODE_MASK : CY_MCWDT_C0C1_MODE_MASK;
mode = (base->MCWDT_CONFIG >> (CY_MCWDT_BYTE_SHIFT * counter)) & mask; mode = (base->MCWDT_CONFIG >> (CY_MCWDT_BYTE_SHIFT * counter)) & mask;
@ -561,6 +613,9 @@ __STATIC_INLINE cy_en_mcwdtmode_t Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const *base
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_MCWDT_SetClearOnMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable) __STATIC_INLINE void Cy_MCWDT_SetClearOnMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable)
{ {
CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
CY_ASSERT_L2(CY_MCWDT_IS_ENABLE_VALID(enable));
if (CY_MCWDT_COUNTER0 == counter) if (CY_MCWDT_COUNTER0 == counter)
{ {
base->MCWDT_CONFIG = _CLR_SET_FLD32U(base->MCWDT_CONFIG, MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, enable); base->MCWDT_CONFIG = _CLR_SET_FLD32U(base->MCWDT_CONFIG, MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, enable);
@ -595,6 +650,8 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetClearOnMatch(MCWDT_STRUCT_Type const *base,
{ {
uint32_t getClear; uint32_t getClear;
CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
if (CY_MCWDT_COUNTER0 == counter) if (CY_MCWDT_COUNTER0 == counter)
{ {
getClear = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, base->MCWDT_CONFIG); getClear = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, base->MCWDT_CONFIG);
@ -627,6 +684,8 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetClearOnMatch(MCWDT_STRUCT_Type const *base,
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_MCWDT_SetCascade(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t cascade) __STATIC_INLINE void Cy_MCWDT_SetCascade(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t cascade)
{ {
CY_ASSERT_L3(CY_MCWDT_IS_CASCADE_VALID(cascade));
base->MCWDT_CONFIG = _CLR_SET_FLD32U(base->MCWDT_CONFIG, MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1, base->MCWDT_CONFIG = _CLR_SET_FLD32U(base->MCWDT_CONFIG, MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1,
(uint32_t) cascade); (uint32_t) cascade);
base->MCWDT_CONFIG = _CLR_SET_FLD32U(base->MCWDT_CONFIG, MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2, base->MCWDT_CONFIG = _CLR_SET_FLD32U(base->MCWDT_CONFIG, MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2,
@ -672,8 +731,8 @@ __STATIC_INLINE cy_en_mcwdtcascade_t Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const
* *
* \param match * \param match
* The value to match against the counter. * The value to match against the counter.
* The valid range is [0-65535] for c0ClearOnMatch = 0 and [1-65535] for * The valid range is [0-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 0
* c0ClearOnMatch = 1. * and [1-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 1.
* *
* \note * \note
* The match value is not supported by Counter 2. * The match value is not supported by Counter 2.
@ -693,6 +752,12 @@ __STATIC_INLINE cy_en_mcwdtcascade_t Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_MCWDT_SetMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t match, uint16_t waitUs) __STATIC_INLINE void Cy_MCWDT_SetMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t match, uint16_t waitUs)
{ {
CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID((CY_MCWDT_COUNTER0 == counter) ?
((base->MCWDT_CONFIG & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Msk) > 0U) :
((base->MCWDT_CONFIG & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Msk) > 0U),
match));
base->MCWDT_MATCH = (counter == CY_MCWDT_COUNTER0) ? base->MCWDT_MATCH = (counter == CY_MCWDT_COUNTER0) ?
_CLR_SET_FLD32U(base->MCWDT_MATCH, MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0, _CLR_SET_FLD32U(base->MCWDT_MATCH, MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0,
(match & MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk)) : (match & MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk)) :
@ -726,6 +791,8 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetMatch(MCWDT_STRUCT_Type const *base, cy_en_
{ {
uint32_t match; uint32_t match;
CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
match = (counter == CY_MCWDT_COUNTER0) ? _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0, base->MCWDT_MATCH) : match = (counter == CY_MCWDT_COUNTER0) ? _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0, base->MCWDT_MATCH) :
_FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1, base->MCWDT_MATCH); _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1, base->MCWDT_MATCH);
@ -752,6 +819,8 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetMatch(MCWDT_STRUCT_Type const *base, cy_en_
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type *base, uint32_t bit) __STATIC_INLINE void Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type *base, uint32_t bit)
{ {
CY_ASSERT_L2(CY_MCWDT_IS_BIT_VALID(bit));
base->MCWDT_CONFIG = _CLR_SET_FLD32U(base->MCWDT_CONFIG, MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, bit); base->MCWDT_CONFIG = _CLR_SET_FLD32U(base->MCWDT_CONFIG, MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, bit);
} }
@ -796,6 +865,8 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const *base, cy_en_
{ {
uint32_t countVal = 0u; uint32_t countVal = 0u;
CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
switch (counter) switch (counter)
{ {
case CY_MCWDT_COUNTER0: case CY_MCWDT_COUNTER0:
@ -833,6 +904,11 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const *base, cy_en_
* \param waitUs * \param waitUs
* The function waits for some delay in microseconds before returning, because * The function waits for some delay in microseconds before returning, because
* a reset occurs after one lf_clk cycle passes. The recommended value is 62 us. * a reset occurs after one lf_clk cycle passes. The recommended value is 62 us.
* \note This function resets the counters two times to prevent the case when
* the Counter 1 is not reset when the counters are cascaded. The delay waitUs
* must be greater than 100 us when the counters are cascaded.
* The total delay is greater than 2*waitUs because the function has
* the delay after the first reset.
* \note * \note
* Setting this parameter to a zero means No wait. In this case, it is the * Setting this parameter to a zero means No wait. In this case, it is the
* user's responsibility to check whether the selected counters were reset * user's responsibility to check whether the selected counters were reset
@ -844,6 +920,8 @@ __STATIC_INLINE void Cy_MCWDT_ResetCounters(MCWDT_STRUCT_Type *base, uint32_t co
{ {
uint32_t resetCounters; uint32_t resetCounters;
CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
/* Extract particular counters for reset */ /* Extract particular counters for reset */
resetCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Msk : 0UL) | resetCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Msk : 0UL) |
((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Msk : 0UL) | ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Msk : 0UL) |
@ -852,6 +930,10 @@ __STATIC_INLINE void Cy_MCWDT_ResetCounters(MCWDT_STRUCT_Type *base, uint32_t co
base->MCWDT_CTL |= resetCounters; base->MCWDT_CTL |= resetCounters;
Cy_SysLib_DelayUs(waitUs); Cy_SysLib_DelayUs(waitUs);
base->MCWDT_CTL |= resetCounters;
Cy_SysLib_DelayUs(waitUs);
} }
@ -894,6 +976,8 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatus(MCWDT_STRUCT_Type const *ba
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters) __STATIC_INLINE void Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters)
{ {
CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
base->MCWDT_INTR = counters; base->MCWDT_INTR = counters;
(void) base->MCWDT_INTR; (void) base->MCWDT_INTR;
} }
@ -915,6 +999,8 @@ __STATIC_INLINE void Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type *base, uint32_t c
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_MCWDT_SetInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters) __STATIC_INLINE void Cy_MCWDT_SetInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters)
{ {
CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
base->MCWDT_INTR_SET = counters; base->MCWDT_INTR_SET = counters;
} }
@ -957,6 +1043,8 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const *base
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t counters) __STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t counters)
{ {
CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
base->MCWDT_INTR_MASK = counters; base->MCWDT_INTR_MASK = counters;
} }
@ -984,6 +1072,7 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatusMasked(MCWDT_STRUCT_Type con
return (base->MCWDT_INTR_MASKED); return (base->MCWDT_INTR_MASKED);
} }
/** \} group_mcwdt_functions */ /** \} group_mcwdt_functions */
#if defined(__cplusplus) #if defined(__cplusplus)

42
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/pdm_pcm/cy_pdm_pcm.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/pdm_pcm/cy_pdm_pcm.c
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_pdm_pcm.c * \file cy_pdm_pcm.c
* \version 2.0 * \version 2.10
* *
* The source code file for the PDM_PCM driver. * The source code file for the PDM_PCM driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -14,7 +14,7 @@
#include "cy_pdm_pcm.h" #include "cy_pdm_pcm.h"
/* C binding of definitions if building with C++ compiler */ /* The C binding of definitions if building with the C++ compiler */
#ifdef __cplusplus #ifdef __cplusplus
extern "C" extern "C"
{ {
@ -29,16 +29,16 @@ extern "C"
* Function Name: Cy_PDM_PCM_Init * Function Name: Cy_PDM_PCM_Init
***************************************************************************//** ***************************************************************************//**
* *
* Initialize PDM-PCM module * Initialize the PDM-PCM module
* *
* \pre If the PDM-PCM module is initialized previously, the * \pre If the PDM-PCM module is initialized previously, the
* \ref Cy_PDM_PCM_DeInit() must be called before calling this function. * \ref Cy_PDM_PCM_DeInit() must be called before calling this function.
* *
* \param base Pointer to PDM-PCM instance address * \param base The pointer to the PDM-PCM instance address
* \param config Pointer to configuration structure * \param config The pointer to a configuration structure.
* \return error / status code. See \ref cy_en_pdm_pcm_status_t. * \return error / status code. See \ref cy_en_pdm_pcm_status_t.
* *
* Example of the configuration structure: * An example of a configuration structure:
* \snippet PDM_PCM_PDL_sut_00.cydsn/main_cm4.c PDM_PCM Configuration * \snippet PDM_PCM_PDL_sut_00.cydsn/main_cm4.c PDM_PCM Configuration
* *
*******************************************************************************/ *******************************************************************************/
@ -64,15 +64,15 @@ cy_en_pdm_pcm_status_t Cy_PDM_PCM_Init(PDM_Type * base, cy_stc_pdm_pcm_config_t
ret = CY_PDM_PCM_SUCCESS; ret = CY_PDM_PCM_SUCCESS;
base->CTL &= (uint32_t) ~PDM_CTL_ENABLED_Msk; /* Disable PDM_PCM block */ base->CTL &= (uint32_t) ~PDM_CTL_ENABLED_Msk; /* Disable the PDM_PCM block */
/* Clock setting */ /* The clock setting */
base->CLOCK_CTL = _VAL2FLD(PDM_CLOCK_CTL_CLK_CLOCK_DIV, config->clkDiv) | base->CLOCK_CTL = _VAL2FLD(PDM_CLOCK_CTL_CLK_CLOCK_DIV, config->clkDiv) |
_VAL2FLD(PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV, config->mclkDiv) | _VAL2FLD(PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV, config->mclkDiv) |
_VAL2FLD(PDM_CLOCK_CTL_CKO_CLOCK_DIV, config->ckoDiv) | _VAL2FLD(PDM_CLOCK_CTL_CKO_CLOCK_DIV, config->ckoDiv) |
_VAL2FLD(PDM_CLOCK_CTL_SINC_RATE, config->sincDecRate); _VAL2FLD(PDM_CLOCK_CTL_SINC_RATE, config->sincDecRate);
/* Enable PDM-PCM block */ /* Enable the PDM-PCM block */
base->CTL = _VAL2FLD(PDM_CTL_PGA_R, config->gainRight) | base->CTL = _VAL2FLD(PDM_CTL_PGA_R, config->gainRight) |
_VAL2FLD(PDM_CTL_PGA_L, config->gainLeft) | _VAL2FLD(PDM_CTL_PGA_L, config->gainLeft) |
_VAL2FLD(PDM_CTL_STEP_SEL, config->softMuteFineGain) | _VAL2FLD(PDM_CTL_STEP_SEL, config->softMuteFineGain) |
@ -117,21 +117,21 @@ void Cy_PDM_PCM_DeInit(PDM_Type * base)
base->TR_CTL = 0UL; base->TR_CTL = 0UL;
base->DATA_CTL = 0UL; base->DATA_CTL = 0UL;
base->MODE_CTL = CY_PDM_PCM_MODE_CTL_DEFAULT; base->MODE_CTL = CY_PDM_PCM_MODE_CTL_DEFAULT;
base->CTL = CY_PDM_PCM_CTL_DEFAULT; /* Disable PDM_PCM IP block */ base->CTL = CY_PDM_PCM_CTL_DEFAULT; /* Disable the PDM_PCM IP block */
base->CLOCK_CTL = CY_PDM_PCM_CLOCK_CTL_DEFAULT; /* Default clock settings */ base->CLOCK_CTL = CY_PDM_PCM_CLOCK_CTL_DEFAULT; /* The default clock settings */
} }
/****************************************************************************** /******************************************************************************
* Function Name: Cy_PDM_PCM_SetGain * Function Name: Cy_PDM_PCM_SetGain
***************************************************************************//** ***************************************************************************//**
* *
* Sets the gain factor to left or right channel. * Sets the gain factor to the left or right channel.
* *
* \param base * \param base
* Pointer to PDM-PCM instance address * The pointer to the PDM-PCM instance address.
* *
* \param chan * \param chan
* Channel selector for gain setting \ref cy_en_pdm_pcm_chan_select_t. * The channel selector for gain setting \ref cy_en_pdm_pcm_chan_select_t.
* *
* \param gain * \param gain
* Gain for the selected channel \ref cy_en_pdm_pcm_gain_t. * Gain for the selected channel \ref cy_en_pdm_pcm_gain_t.
@ -156,13 +156,13 @@ void Cy_PDM_PCM_SetGain(PDM_Type * base, cy_en_pdm_pcm_chan_select_t chan, cy_en
* Function Name: Cy_PDM_PCM_GetGain * Function Name: Cy_PDM_PCM_GetGain
***************************************************************************//** ***************************************************************************//**
* *
* Retrieve the current gain factor of left or right channel. * Retrieves the current gain factor of the left or right channel.
* *
* \param base * \param base
* Pointer to PDM-PCM instance address * the pointer to the PDM-PCM instance address.
* *
* \param chan * \param chan
* Channel selector for gain setting \ref cy_en_pdm_pcm_chan_select_t. * The channel selector for gain setting \ref cy_en_pdm_pcm_chan_select_t.
* *
* \return * \return
* Gain of the selected channel \ref cy_en_pdm_pcm_gain_t. * Gain of the selected channel \ref cy_en_pdm_pcm_gain_t.
@ -191,11 +191,11 @@ cy_en_pdm_pcm_gain_t Cy_PDM_PCM_GetGain(PDM_Type const * base, cy_en_pdm_pcm_cha
* Function Name: Cy_PDM_PCM_DeepSleepCallback * Function Name: Cy_PDM_PCM_DeepSleepCallback
****************************************************************************//** ****************************************************************************//**
* *
* This is an example callback function that can be used the application layer to * This is an example callback function that can be used at the application layer to
* manage PDM-PCM operation before entering and after exiting Deep-Sleep mode. * manage the PDM-PCM operation before entering and after exiting Deep-Sleep mode.
* *
* \param callbackParams * \param callbackParams
* structure with the syspm callback parameters, * The structure with the syspm callback parameters,
* see \ref cy_stc_syspm_callback_params_t. * see \ref cy_stc_syspm_callback_params_t.
* *
* \return * \return

152
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/pdm_pcm/cy_pdm_pcm.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/pdm_pcm/cy_pdm_pcm.h
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_pdm_pcm.h * \file cy_pdm_pcm.h
* \version 2.0 * \version 2.10
* *
* The header file of the PDM_PCM driver. * The header file of the PDM_PCM driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -33,7 +33,7 @@
* to the analog signal's amplitude. The output of a 1-bit DAC is the same * to the analog signal's amplitude. The output of a 1-bit DAC is the same
* as the PDM encoding of the signal. * as the PDM encoding of the signal.
* *
* Pulse-code modulation (PCM) is a method used to digitally represent sampled analog signals. * Pulse-code modulation (PCM) is the method used to digitally represent sampled analog signals.
* It is the standard form of digital audio in computers, compact discs, digital telephony, * It is the standard form of digital audio in computers, compact discs, digital telephony,
* and other digital audio applications. In a PCM stream, the amplitude of the analog signal * and other digital audio applications. In a PCM stream, the amplitude of the analog signal
* is sampled regularly at uniform intervals, and each sample is quantized * is sampled regularly at uniform intervals, and each sample is quantized
@ -53,19 +53,20 @@
* To initialize the PDM-PCM block, call the \ref Cy_PDM_PCM_Init function, providing the * To initialize the PDM-PCM block, call the \ref Cy_PDM_PCM_Init function, providing the
* filled \ref cy_stc_pdm_pcm_config_t structure. * filled \ref cy_stc_pdm_pcm_config_t structure.
* *
* If you use DMA, the DMA channel should be previously configured. PDM-PCM interrupts * If you use a DMA, the DMA channel should be previously configured. PDM-PCM interrupts
* (if applicable) can be enabled by calling \ref Cy_PDM_PCM_SetInterruptMask. * (if applicable) can be enabled by calling \ref Cy_PDM_PCM_SetInterruptMask.
* *
* For example, if the trigger interrupt is used during operation, the ISR * For example, if the trigger interrupt is used during operation, the ISR
* should call the \ref Cy_PDM_PCM_ReadFifo as many times as required for your * should call the \ref Cy_PDM_PCM_ReadFifo as many times as required for your
* FIFO payload. Then call \ref Cy_PDM_PCM_ClearInterrupt with appropriate parameters. * FIFO payload. Then call \ref Cy_PDM_PCM_ClearInterrupt with appropriate parameters.
* *
* If DMA is used and a DMA channel is properly configured, no CPU activity * If a DMA is used and the DMA channel is properly configured, no CPU activity
* (or application code) is needed for PDM-PCM operation. * (or application code) is needed for PDM-PCM operation.
* *
* \section group_pdm_pcm_more_information More Information * \section group_pdm_pcm_more_information More Information
* See the PDM_PCM_PDL Component datasheet. * See: the PDM-PCM chapter of the device technical reference manual (TRM);
* Also, see the PDM-PCM chapter of the device technical reference manual (TRM). * the PDM_PCM_PDL Component datasheet;
* CE219431 - PSOC 6 MCU PDM-TO-PCM EXAMPLE.
* *
* \section group_pdm_pcm_MISRA MISRA-C Compliance * \section group_pdm_pcm_MISRA MISRA-C Compliance
* The PDM-PCM driver has the following specific deviations: * The PDM-PCM driver has the following specific deviations:
@ -79,20 +80,20 @@
* <tr> * <tr>
* <td>10.3</td> * <td>10.3</td>
* <td>R</td> * <td>R</td>
* <td>A composite expression of 'essentially unsigned' type is being * <td>A composite expression of the "essentially unsigned" type is
* cast to a different type category.</td> * cast to a different type category.</td>
* <td>The value got from the bitfield physically can't exceed the enumeration * <td>The value got from the bitfield physically can't exceed the enumeration
* that describes this bitfield. So the code is safety by design.</td> * that describes this bitfield. So the code is safe by design.</td>
* </tr> * </tr>
* <tr> * <tr>
* <td>11.4</td> * <td>11.4</td>
* <td>A</td> * <td>A</td>
* <td>A cast should not be performed between a pointer to object type and * <td>A cast should not be performed between a pointer to the object type and
* a different pointer to object type.</td> * a different pointer to the object type.</td>
* <td>The function \ref Cy_I2S_DeepSleepCallback is a callback of * <td>The function \ref Cy_I2S_DeepSleepCallback is a callback of
* \ref cy_en_syspm_status_t type. The cast operation safety in this * \ref cy_en_syspm_status_t type. The cast operation safety in this
* function becomes the user responsibility because pointer are * function becomes the user responsibility because the pointer is
* initialized when callback is registered in SysPm driver.</td> * initialized when a callback is registered in SysPm driver.</td>
* </tr> * </tr>
* </table> * </table>
* *
@ -100,20 +101,56 @@
* <table class="doxtable"> * <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr> * <tr>
* <td>1.0</td> * <td>2.10</td>
* <td>Initial version</td> * <td>The gain values in range +4.5...+10.5dB (5 items) of /ref cy_en_pdm_pcm_gain_t are corrected.
* <td></td> * Added Low Power Callback section.</td>
* <td>Incorrect setting of gain values in limited range.
* Documentation update and clarification.</td>
* </tr> * </tr>
* <tr> * <tr>
* <td>2.0</td> * <td>2.0</td>
* <td>User-friendliness enhancement</td> * <td>Enumeration types for gain and soft mute cycles are added.<br>
* Function parameter checks are added.<br>
* The next functions are removed:
* * Cy_PDM_PCM_EnterLowPowerCallback
* * Cy_PDM_PCM_ExitLowPowerCallback
* * Cy_PDM_PCM_EnableDataStream
* * Cy_PDM_PCM_DisableDataStream
* * Cy_PDM_PCM_SetFifoLevel
* * Cy_PDM_PCM_GetFifoLevel
* * Cy_PDM_PCM_EnableDmaRequest
* * Cy_PDM_PCM_DisableDmaRequest
*
* The next functions behaviour are modified:
* * Cy_PDM_PCM_Enable
* * Cy_PDM_PCM_Disable
* * Cy_PDM_PCM_SetInterruptMask
* * Cy_PDM_PCM_GetInterruptMask
* * Cy_PDM_PCM_GetInterruptStatusMasked
* * Cy_PDM_PCM_GetInterruptStatus
* * Cy_PDM_PCM_ClearInterrupt
* * Cy_PDM_PCM_SetInterrupt
*
* The Cy_PDM_PCM_GetFifoNumWords function is renamed to Cy_PDM_PCM_GetNumInFifo.<br>
* The Cy_PDM_PCM_GetCurrentState function is added.
* </td>
* <td>Improvements based on usability feedbacks.<br>
* API is reworked for consistency within the PDL.
* </td>
* </tr>
* <tr>
* <td>1.0</td>
* <td>Initial version</td>
* <td></td> * <td></td>
* </tr> * </tr>
* </table> * </table>
* *
* \defgroup group_pdm_pcm_macros Macros * \defgroup group_pdm_pcm_macros Macros
* \defgroup group_pdm_pcm_functions Functions * \defgroup group_pdm_pcm_functions Functions
* \defgroup group_pdm_pcm_data_structures Data structures * \{
* \defgroup group_pdm_pcm_functions_syspm_callback Low Power Callback
* \}
* \defgroup group_pdm_pcm_data_structures Data Structures
* \defgroup group_pdm_pcm_enums Enumerated Types * \defgroup group_pdm_pcm_enums Enumerated Types
* *
*/ */
@ -135,7 +172,7 @@
#error "The PDM-PCM driver is not supported on this device" #error "The PDM-PCM driver is not supported on this device"
#endif #endif
/* C binding of definitions if building with C++ compiler */ /* The C binding of definitions if building with the C++ compiler */
#ifdef __cplusplus #ifdef __cplusplus
extern "C" extern "C"
{ {
@ -151,13 +188,13 @@ extern "C"
* \{ * \{
*/ */
/** Driver major version */ /** The driver major version */
#define CY_PDM_PCM_DRV_VERSION_MAJOR 2 #define CY_PDM_PCM_DRV_VERSION_MAJOR 2
/** Driver minor version */ /** The driver minor version */
#define CY_PDM_PCM_DRV_VERSION_MINOR 0 #define CY_PDM_PCM_DRV_VERSION_MINOR 10
/** PDM-PCM driver identifier */ /** The PDM-PCM driver identifier */
#define CY_PDM_PCM_ID CY_PDL_DRV_ID(0x26u) #define CY_PDM_PCM_ID CY_PDL_DRV_ID(0x26u)
/** /**
@ -230,11 +267,11 @@ typedef enum
CY_PDM_PCM_BYPASS = 8U, /**< 0 dB (bypass). */ CY_PDM_PCM_BYPASS = 8U, /**< 0 dB (bypass). */
CY_PDM_PCM_GAIN_1_5_DB = 9U, /**< +1.5 dB (amplification). */ CY_PDM_PCM_GAIN_1_5_DB = 9U, /**< +1.5 dB (amplification). */
CY_PDM_PCM_GAIN_3_DB = 10U, /**< +3 dB (amplification). */ CY_PDM_PCM_GAIN_3_DB = 10U, /**< +3 dB (amplification). */
CY_PDM_PCM_GAIN_4_5_DB = 12U, /**< +4.5 dB (amplification). */ CY_PDM_PCM_GAIN_4_5_DB = 11U, /**< +4.5 dB (amplification). */
CY_PDM_PCM_GAIN_6_DB = 13U, /**< +6 dB (amplification). */ CY_PDM_PCM_GAIN_6_DB = 12U, /**< +6 dB (amplification). */
CY_PDM_PCM_GAIN_7_5_DB = 14U, /**< +7.5 dB (amplification). */ CY_PDM_PCM_GAIN_7_5_DB = 13U, /**< +7.5 dB (amplification). */
CY_PDM_PCM_GAIN_9_DB = 15U, /**< +9 dB (amplification). */ CY_PDM_PCM_GAIN_9_DB = 14U, /**< +9 dB (amplification). */
CY_PDM_PCM_GAIN_10_5_DB = 16U /**< +10.5 dB (amplification). */ CY_PDM_PCM_GAIN_10_5_DB = 15U /**< +10.5 dB (amplification). */
} cy_en_pdm_pcm_gain_t; } cy_en_pdm_pcm_gain_t;
@ -417,7 +454,12 @@ cy_en_pdm_pcm_status_t Cy_PDM_PCM_Init(PDM_Type * base, cy_stc_pdm_pcm_config_
void Cy_PDM_PCM_SetGain(PDM_Type * base, cy_en_pdm_pcm_chan_select_t chan, cy_en_pdm_pcm_gain_t gain); void Cy_PDM_PCM_SetGain(PDM_Type * base, cy_en_pdm_pcm_chan_select_t chan, cy_en_pdm_pcm_gain_t gain);
cy_en_pdm_pcm_gain_t Cy_PDM_PCM_GetGain(PDM_Type const * base, cy_en_pdm_pcm_chan_select_t chan); cy_en_pdm_pcm_gain_t Cy_PDM_PCM_GetGain(PDM_Type const * base, cy_en_pdm_pcm_chan_select_t chan);
/** \addtogroup group_pdm_pcm_functions_syspm_callback
* The driver supports SysPm callback for Deep Sleep transition.
* \{
*/
cy_en_syspm_status_t Cy_PDM_PCM_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams); cy_en_syspm_status_t Cy_PDM_PCM_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams);
/** \} */
__STATIC_INLINE void Cy_PDM_PCM_Enable(PDM_Type * base); __STATIC_INLINE void Cy_PDM_PCM_Enable(PDM_Type * base);
__STATIC_INLINE void Cy_PDM_PCM_Disable(PDM_Type * base); __STATIC_INLINE void Cy_PDM_PCM_Disable(PDM_Type * base);
@ -450,7 +492,7 @@ __STATIC_INLINE uint32_t Cy_PDM_PCM_ReadFifoSilent(PDM_Type const * base);
* *
* Enables the PDM-PCM data conversion. * Enables the PDM-PCM data conversion.
* *
* \param base Pointer to PDM-PCM instance address * \param base The pointer to the PDM-PCM instance address.
* *
******************************************************************************/ ******************************************************************************/
__STATIC_INLINE void Cy_PDM_PCM_Enable(PDM_Type * base) __STATIC_INLINE void Cy_PDM_PCM_Enable(PDM_Type * base)
@ -464,7 +506,7 @@ __STATIC_INLINE void Cy_PDM_PCM_Enable(PDM_Type * base)
* *
* Disables the PDM-PCM data conversion. * Disables the PDM-PCM data conversion.
* *
* \param base Pointer to PDM-PCM instance address * \param base The pointer to the PDM-PCM instance address.
* *
******************************************************************************/ ******************************************************************************/
__STATIC_INLINE void Cy_PDM_PCM_Disable(PDM_Type * base) __STATIC_INLINE void Cy_PDM_PCM_Disable(PDM_Type * base)
@ -479,7 +521,7 @@ __STATIC_INLINE void Cy_PDM_PCM_Disable(PDM_Type * base)
* *
* Returns the current PDM-PCM state (running/stopped). * Returns the current PDM-PCM state (running/stopped).
* *
* \param base Pointer to PDM-PCM instance address. * \param base The pointer to the PDM-PCM instance address.
* \return The current state (CMD register). * \return The current state (CMD register).
* *
******************************************************************************/ ******************************************************************************/
@ -495,7 +537,7 @@ __STATIC_INLINE uint32_t Cy_PDM_PCM_GetCurrentState(PDM_Type const * base)
* *
* Sets one or more PDM-PCM interrupt factor bits (sets the INTR_MASK register). * Sets one or more PDM-PCM interrupt factor bits (sets the INTR_MASK register).
* *
* \param base Pointer to PDM-PCM instance address * \param base The pointer to the PDM-PCM instance address
* \param interrupt Interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks. * \param interrupt Interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks.
* *
******************************************************************************/ ******************************************************************************/
@ -512,7 +554,7 @@ __STATIC_INLINE void Cy_PDM_PCM_SetInterruptMask(PDM_Type * base, uint32_t inter
* *
* Returns the PDM-PCM interrupt mask (a content of the INTR_MASK register). * Returns the PDM-PCM interrupt mask (a content of the INTR_MASK register).
* *
* \param base Pointer to PDM-PCM instance address * \param base The pointer to the PDM-PCM instance address.
* \return The interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks. * \return The interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks.
* *
******************************************************************************/ ******************************************************************************/
@ -526,10 +568,10 @@ __STATIC_INLINE uint32_t Cy_PDM_PCM_GetInterruptMask(PDM_Type const * base)
* Function Name: Cy_PDM_PCM_GetInterruptStatusMasked * Function Name: Cy_PDM_PCM_GetInterruptStatusMasked
***************************************************************************//** ***************************************************************************//**
* *
* Reports status of enabled (masked) PDM-PCM interrupt sources * Reports the status of enabled (masked) PDM-PCM interrupt sources.
* (an INTR_MASKED register). * (an INTR_MASKED register).
* *
* \param base Pointer to PDM-PCM instance address * \param base The pointer to the PDM-PCM instance address.
* \return The interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks. * \return The interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks.
* *
*****************************************************************************/ *****************************************************************************/
@ -543,9 +585,9 @@ __STATIC_INLINE uint32_t Cy_PDM_PCM_GetInterruptStatusMasked(PDM_Type const * ba
* Function Name: Cy_PDM_PCM_GetInterruptStatus * Function Name: Cy_PDM_PCM_GetInterruptStatus
***************************************************************************//** ***************************************************************************//**
* *
* Reports status of PDM-PCM interrupt sources (an INTR register). * Reports the status of PDM-PCM interrupt sources (an INTR register).
* *
* \param base Pointer to PDM-PCM instance address * \param base The pointer to the PDM-PCM instance address.
* \return The interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks. * \return The interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks.
* *
******************************************************************************/ ******************************************************************************/
@ -559,9 +601,9 @@ __STATIC_INLINE uint32_t Cy_PDM_PCM_GetInterruptStatus(PDM_Type const * base)
* Function Name: Cy_PDM_PCM_ClearInterrupt * Function Name: Cy_PDM_PCM_ClearInterrupt
***************************************************************************//** ***************************************************************************//**
* *
* Clears one or more PDM-PCM interrupt status (sets an INTR register's bits). * Clears one or more PDM-PCM interrupt statuses (sets an INTR register's bits).
* *
* \param base Pointer to PDM-PCM instance address * \param base The pointer to the PDM-PCM instance address
* \param interrupt * \param interrupt
* The interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks. * The interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks.
* *
@ -578,9 +620,9 @@ __STATIC_INLINE void Cy_PDM_PCM_ClearInterrupt(PDM_Type * base, uint32_t interru
* Function Name: Cy_PDM_PCM_SetInterrupt * Function Name: Cy_PDM_PCM_SetInterrupt
***************************************************************************//** ***************************************************************************//**
* *
* Sets one or more interrupt source status (sets an INTR_SET register). * Sets one or more interrupt source statuses (sets an INTR_SET register).
* *
* \param base Pointer to PDM-PCM instance address * \param base The pointer to the PDM-PCM instance address.
* \param interrupt * \param interrupt
* The interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks. * The interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks.
* *
@ -598,8 +640,8 @@ __STATIC_INLINE void Cy_PDM_PCM_SetInterrupt(PDM_Type * base, uint32_t interrupt
* *
* Reports the current number of used words in the output data FIFO. * Reports the current number of used words in the output data FIFO.
* *
* \param base Pointer to PDM-PCM instance address * \param base The pointer to the PDM-PCM instance address.
* \return Current number of used FIFO words (range is 0 - 254) * \return The current number of used FIFO words (range is 0 - 254).
* *
******************************************************************************/ ******************************************************************************/
__STATIC_INLINE uint8_t Cy_PDM_PCM_GetNumInFifo(PDM_Type const * base) __STATIC_INLINE uint8_t Cy_PDM_PCM_GetNumInFifo(PDM_Type const * base)
@ -614,7 +656,7 @@ __STATIC_INLINE uint8_t Cy_PDM_PCM_GetNumInFifo(PDM_Type const * base)
* *
* Resets the output data FIFO, removing all data words from the FIFO. * Resets the output data FIFO, removing all data words from the FIFO.
* *
* \param base Pointer to PDM-PCM instance address * \param base The pointer to the PDM-PCM instance address.
* *
******************************************************************************/ ******************************************************************************/
__STATIC_INLINE void Cy_PDM_PCM_ClearFifo(PDM_Type * base) __STATIC_INLINE void Cy_PDM_PCM_ClearFifo(PDM_Type * base)
@ -630,8 +672,8 @@ __STATIC_INLINE void Cy_PDM_PCM_ClearFifo(PDM_Type * base)
* *
* Reads ("pops") one word from the output data FIFO. * Reads ("pops") one word from the output data FIFO.
* *
* \param base Pointer to PDM-PCM instance address. * \param base The pointer to the PDM-PCM instance address.
* \return Data word. * \return The data word.
* *
******************************************************************************/ ******************************************************************************/
__STATIC_INLINE uint32_t Cy_PDM_PCM_ReadFifo(PDM_Type const * base) __STATIC_INLINE uint32_t Cy_PDM_PCM_ReadFifo(PDM_Type const * base)
@ -644,9 +686,9 @@ __STATIC_INLINE uint32_t Cy_PDM_PCM_ReadFifo(PDM_Type const * base)
* Function Name: Cy_PDM_PCM_EnableSoftMute * Function Name: Cy_PDM_PCM_EnableSoftMute
***************************************************************************//** ***************************************************************************//**
* *
* Enables soft mute * Enables soft mute.
* *
* \param base Pointer to PDM-PCM instance address * \param base The pointer to the PDM-PCM instance address.
* *
******************************************************************************/ ******************************************************************************/
__STATIC_INLINE void Cy_PDM_PCM_EnableSoftMute(PDM_Type * base) __STATIC_INLINE void Cy_PDM_PCM_EnableSoftMute(PDM_Type * base)
@ -659,9 +701,9 @@ __STATIC_INLINE void Cy_PDM_PCM_EnableSoftMute(PDM_Type * base)
* Function Name: Cy_PDM_PCM_DisableSoftMute * Function Name: Cy_PDM_PCM_DisableSoftMute
***************************************************************************//** ***************************************************************************//**
* *
* Disables soft mute * Disables soft mute.
* *
* \param base Pointer to PDM-PCM instance address * \param base The pointer to the PDM-PCM instance address.
* *
******************************************************************************/ ******************************************************************************/
__STATIC_INLINE void Cy_PDM_PCM_DisableSoftMute(PDM_Type * base) __STATIC_INLINE void Cy_PDM_PCM_DisableSoftMute(PDM_Type * base)
@ -674,9 +716,9 @@ __STATIC_INLINE void Cy_PDM_PCM_DisableSoftMute(PDM_Type * base)
* Function Name: Cy_PDM_PCM_FreezeFifo * Function Name: Cy_PDM_PCM_FreezeFifo
***************************************************************************//** ***************************************************************************//**
* *
* Freezes RX FIFO (Debug purpose) * Freezes the RX FIFO (Debug purpose).
* *
* \param base Pointer to PDM-PCM instance address * \param base The pointer to the PDM-PCM instance address.
* *
******************************************************************************/ ******************************************************************************/
__STATIC_INLINE void Cy_PDM_PCM_FreezeFifo(PDM_Type * base) __STATIC_INLINE void Cy_PDM_PCM_FreezeFifo(PDM_Type * base)
@ -689,9 +731,9 @@ __STATIC_INLINE void Cy_PDM_PCM_FreezeFifo(PDM_Type * base)
* Function Name: Cy_PDM_PCM_UnfreezeFifo * Function Name: Cy_PDM_PCM_UnfreezeFifo
***************************************************************************//** ***************************************************************************//**
* *
* Unfreezes RX FIFO (Debug purpose) * Unfreezes the RX FIFO (Debug purpose).
* *
* \param base Pointer to PDM-PCM instance address * \param base The pointer to the PDM-PCM instance address.
* *
******************************************************************************/ ******************************************************************************/
__STATIC_INLINE void Cy_PDM_PCM_UnfreezeFifo(PDM_Type * base) __STATIC_INLINE void Cy_PDM_PCM_UnfreezeFifo(PDM_Type * base)
@ -704,7 +746,7 @@ __STATIC_INLINE void Cy_PDM_PCM_UnfreezeFifo(PDM_Type * base)
* Function Name: Cy_PDM_PCM_ReadFifoSilent * Function Name: Cy_PDM_PCM_ReadFifoSilent
***************************************************************************//** ***************************************************************************//**
* *
* Reads RX FIFO silent (without touching the FIFO function) * Reads the RX FIFO silent (without touching the FIFO function).
* *
* \param base Pointer to PDM-PCM instance address. * \param base Pointer to PDM-PCM instance address.
* \return FIFO value. * \return FIFO value.

148
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/profile/cy_profile.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/profile/cy_profile.c
View File

@ -6,7 +6,7 @@
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -19,17 +19,17 @@
extern "C" { extern "C" {
#endif /* __cplusplus */ #endif /* __cplusplus */
/* # of elements in an array */ /* Number of elements in an array */
#define CY_N_ELMTS(a) (sizeof(a)/sizeof((a)[0])) #define CY_N_ELMTS(a) (sizeof(a)/sizeof((a)[0]))
static cy_en_profile_status_t Cy_Profile_IsPtrValid(const cy_stc_profile_ctr_ptr_t ctrAddr); static cy_en_profile_status_t Cy_Profile_IsPtrValid(const cy_stc_profile_ctr_ptr_t ctrAddr);
/* control and status information for each counter */ /* Internal structure - Control and status information for each counter */
static cy_stc_profile_ctr_t cy_ep_ctrs[PROFILE_PRFL_CNT_NR]; static cy_stc_profile_ctr_t cy_ep_ctrs[PROFILE_PRFL_CNT_NR];
/* ========================================================================== */ /* ========================================================================== */
/* ===================== LOCAL FUNCTIONS SECTION ====================== */ /* ===================== LOCAL FUNCTION SECTION ====================== */
/* ========================================================================== */ /* ========================================================================== */
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_Profile_IsPtrValid * Function Name: Cy_Profile_IsPtrValid
@ -104,15 +104,22 @@ void Cy_Profile_ISR(void)
/* ========================================================================== */ /* ========================================================================== */
/* ================== GENERAL EP FUNCTIONS SECTION ==================== */ /* ================== GENERAL PROFILE FUNCTIONS ==================== */
/* ========================================================================== */ /* ========================================================================== */
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_Profile_StartProfiling * Function Name: Cy_Profile_StartProfiling
****************************************************************************//** ****************************************************************************//**
* *
* Starts profiling. * Starts the profiling/measurement window.
*
* This operation allows the enabled profile counters to start counting.
*
* \note The profile interrupt should be enabled before calling this function
* in order for the firmware to be notified when a counter overflow occurs.
*
* \funcusage
* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_StartProfiling
* *
* \note Before calling this function, the user must enable the profiler interrupt.
*******************************************************************************/ *******************************************************************************/
void Cy_Profile_StartProfiling(void) void Cy_Profile_StartProfiling(void)
{ {
@ -132,8 +139,11 @@ void Cy_Profile_StartProfiling(void)
* Function Name: Cy_Profile_ClearConfiguration * Function Name: Cy_Profile_ClearConfiguration
****************************************************************************//** ****************************************************************************//**
* *
* Clears all counter configuration and sets all counters and overflow counters to 0. * Clears all counter configurations and sets all counters and overflow counters
* Calls Cy_Profile_ClearCounters() to clear counter registers. * to 0. Calls Cy_Profile_ClearCounters() to clear counter registers.
*
* \funcusage
* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_ClearConfiguration
* *
*******************************************************************************/ *******************************************************************************/
void Cy_Profile_ClearConfiguration(void) void Cy_Profile_ClearConfiguration(void)
@ -142,31 +152,32 @@ void Cy_Profile_ClearConfiguration(void)
Cy_Profile_ClearCounters(); Cy_Profile_ClearCounters();
} }
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_Profile_ConfigureCounter * Function Name: Cy_Profile_ConfigureCounter
****************************************************************************//** ****************************************************************************//**
* *
* Assigns a given monitor source to a counter, and loads the CTL register * Configures and assigns a hardware profile counter to the list of used counters.
* bitfields of an assigned counter.
* *
* The available monitor sources vary per device series. Refer to the series-specific * This function assigns an available profile counter to a slot in the internal
* configuration header file for the list of available monitor sources. * software data structure and returns the handle for that slot location. The data
* structure is used to keep track of the counter status and to implement a 64-bit
* profile counter. If no counter slots are available, the function returns a
* NULL pointer.
* *
* \param monitor The monitor source # * \param monitor The monitor source number
* *
* \param duration Events are monitored (0), or duration is monitored (1) * \param duration Events are monitored (0), or duration is monitored (1)
* *
* \param refClk The reference clock to use; see \ref cy_en_profile_ref_clk_t. * \param refClk Counter reference clock
* In general, it is recommended to use CY_PROFILE_CLK_HF to maximize resolution.
* *
* \param weight Weighting factor for the counter value * \param weight Weighting factor for the counter value
* *
* \return A pointer to the counter data structure. NULL if no counter is * \return A pointer to the counter data structure. NULL if no counter is
* available. * available.
* *
* \note The counter is not enabled by this function. See functions * \funcusage
* \ref Cy_Profile_EnableCounter() and \ref Cy_Profile_DisableCounter(). See the * \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_ConfigureCounter
* Technical Reference Manual (TRM) chapter on the EP for reference clock considerations.
* *
*******************************************************************************/ *******************************************************************************/
cy_stc_profile_ctr_ptr_t Cy_Profile_ConfigureCounter(en_ep_mon_sel_t monitor, cy_en_profile_duration_t duration, cy_stc_profile_ctr_ptr_t Cy_Profile_ConfigureCounter(en_ep_mon_sel_t monitor, cy_en_profile_duration_t duration,
@ -199,21 +210,27 @@ cy_stc_profile_ctr_ptr_t Cy_Profile_ConfigureCounter(en_ep_mon_sel_t monitor, cy
return (retVal); return (retVal);
} }
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_Profile_FreeCounter * Function Name: Cy_Profile_FreeCounter
****************************************************************************//** ****************************************************************************//**
* *
* Frees up a counter from a previously-assigned monitor source. * Frees up a counter from a previously-assigned monitor source.
* \ref Cy_Profile_ConfigureCounter() must have been called for this counter before
* calling this function.
* *
* \param ctrAddr The handle to (address of) the assigned counter, which is * \ref Cy_Profile_ConfigureCounter() must have been called for this counter
* obtained by a call to \ref Cy_Profile_ConfigureCounter(). * before calling this function.
* *
* \return \ref CY_PROFILE_SUCCESS, or \ref CY_PROFILE_BAD_PARAM for counter not in use. * \param ctrAddr The handle to the assigned counter (returned by calling
* \ref Cy_Profile_ConfigureCounter()).
*
* \return
* Status of the operation.
*
* \note The counter is not disabled by this function.
*
* \funcusage
* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_FreeCounter
* *
* \note The counter is not disabled by this function. See functions
* \ref Cy_Profile_EnableCounter() and \ref Cy_Profile_DisableCounter().
*******************************************************************************/ *******************************************************************************/
cy_en_profile_status_t Cy_Profile_FreeCounter(cy_stc_profile_ctr_ptr_t ctrAddr) cy_en_profile_status_t Cy_Profile_FreeCounter(cy_stc_profile_ctr_ptr_t ctrAddr)
{ {
@ -227,17 +244,24 @@ cy_en_profile_status_t Cy_Profile_FreeCounter(cy_stc_profile_ctr_ptr_t ctrAddr)
return (retStatus); return (retStatus);
} }
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_Profile_EnableCounter * Function Name: Cy_Profile_EnableCounter
****************************************************************************//** ****************************************************************************//**
* *
* Enables an assigned counter. \ref Cy_Profile_ConfigureCounter() must have been * Enables an assigned counter.
* called for this counter before calling this function.
* *
* \param ctrAddr The handle to (address of) the assigned counter, which is * \ref Cy_Profile_ConfigureCounter() must have been called for this counter
* obtained by a call to \ref Cy_Profile_ConfigureCounter(). * before calling this function.
* *
* \return \ref CY_PROFILE_SUCCESS, or \ref CY_PROFILE_BAD_PARAM for counter not in use. * \param ctrAddr The handle to the assigned counter, (returned by calling
* \ref Cy_Profile_ConfigureCounter()).
*
* \return
* Status of the operation.
*
* \funcusage
* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_EnableCounter
* *
*******************************************************************************/ *******************************************************************************/
cy_en_profile_status_t Cy_Profile_EnableCounter(cy_stc_profile_ctr_ptr_t ctrAddr) cy_en_profile_status_t Cy_Profile_EnableCounter(cy_stc_profile_ctr_ptr_t ctrAddr)
@ -255,17 +279,24 @@ cy_en_profile_status_t Cy_Profile_EnableCounter(cy_stc_profile_ctr_ptr_t ctrAddr
return (retStatus); return (retStatus);
} }
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_Profile_DisableCounter * Function Name: Cy_Profile_DisableCounter
****************************************************************************//** ****************************************************************************//**
* *
* Disables an assigned counter. \ref Cy_Profile_ConfigureCounter() must have been * Disables an assigned counter.
* called for this counter before calling this function.
* *
* \param ctrAddr The handle to (address of) the assigned counter, which is * \ref Cy_Profile_ConfigureCounter() must have been called for this counter
* obtained by a call to \ref Cy_Profile_ConfigureCounter(). * before calling this function.
* *
* \return \ref CY_PROFILE_SUCCESS, or \ref CY_PROFILE_BAD_PARAM for counter not in use. * \param ctrAddr The handle to the assigned counter, (returned by calling
* \ref Cy_Profile_ConfigureCounter()).
*
* \return
* Status of the operation.
*
* \funcusage
* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_DisableCounter
* *
*******************************************************************************/ *******************************************************************************/
cy_en_profile_status_t Cy_Profile_DisableCounter(cy_stc_profile_ctr_ptr_t ctrAddr) cy_en_profile_status_t Cy_Profile_DisableCounter(cy_stc_profile_ctr_ptr_t ctrAddr)
@ -289,14 +320,18 @@ cy_en_profile_status_t Cy_Profile_DisableCounter(cy_stc_profile_ctr_ptr_t ctrAdd
* Function Name: Cy_Profile_GetRawCount * Function Name: Cy_Profile_GetRawCount
****************************************************************************//** ****************************************************************************//**
* *
* Reports the count value for a specified counter. * Reports the raw count value for a specified counter.
* *
* \param ctrAddr the handle to (address of) the assigned counter, which is * \param ctrAddr The handle to the assigned counter, (returned by calling
* obtained by a call to \ref Cy_Profile_ConfigureCounter(). * \ref Cy_Profile_ConfigureCounter()).
* *
* \param result The address to which to write the result. * \param result Output parameter used to write in the result.
* *
* \return \ref CY_PROFILE_SUCCESS, or \ref CY_PROFILE_BAD_PARAM for counter not in use. * \return
* Status of the operation.
*
* \funcusage
* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_GetRawCount
* *
*******************************************************************************/ *******************************************************************************/
cy_en_profile_status_t Cy_Profile_GetRawCount(cy_stc_profile_ctr_ptr_t ctrAddr, uint64_t *result) cy_en_profile_status_t Cy_Profile_GetRawCount(cy_stc_profile_ctr_ptr_t ctrAddr, uint64_t *result)
@ -319,14 +354,18 @@ cy_en_profile_status_t Cy_Profile_GetRawCount(cy_stc_profile_ctr_ptr_t ctrAddr,
****************************************************************************//** ****************************************************************************//**
* *
* Reports the count value for a specified counter, multiplied by the weight * Reports the count value for a specified counter, multiplied by the weight
* factor set in \ref Cy_Profile_ConfigureCounter() for that counter. * factor for that counter.
* *
* \param ctrAddr the handle to (address of) the assigned counter, which is * \param ctrAddr The handle to the assigned counter, (returned by calling
* obtained by a call to \ref Cy_Profile_ConfigureCounter(). * \ref Cy_Profile_ConfigureCounter()).
* *
* \param result The address to which to write the result. * \param result Output parameter used to write in the result.
* *
* \return \ref CY_PROFILE_SUCCESS, or \ref CY_PROFILE_BAD_PARAM for counter not in use. * \return
* Status of the operation.
*
* \funcusage
* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_GetWeightedCount
* *
*******************************************************************************/ *******************************************************************************/
cy_en_profile_status_t Cy_Profile_GetWeightedCount(cy_stc_profile_ctr_ptr_t ctrAddr, uint64_t *result) cy_en_profile_status_t Cy_Profile_GetWeightedCount(cy_stc_profile_ctr_ptr_t ctrAddr, uint64_t *result)
@ -345,14 +384,21 @@ cy_en_profile_status_t Cy_Profile_GetWeightedCount(cy_stc_profile_ctr_ptr_t ctrA
* Function Name: Cy_Profile_GetSumWeightedCounts * Function Name: Cy_Profile_GetSumWeightedCounts
****************************************************************************//** ****************************************************************************//**
* *
* Calls \ref Cy_Profile_GetWeightedCount() for all specified counters. Reports the sum * Reports the weighted sum result of the first n number of counter count values
* across all valid counters. * starting from the specified profile counter data structure base address.
* *
* \param ptrsArray Array of handles to (addresses of) assigned counters * Each count value is multiplied by its weighing factor before the summing
* operation is performed.
* *
* \param numCounters Number of scanned elements in ptrsArray[] * \param ptrsArray Base address of the profile counter data structure
* *
* \return The sum * \param numCounters Number of measured counters in ptrsArray[]
*
* \return
* The weighted sum of the specified counters
*
* \funcusage
* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_GetSumWeightedCounts
* *
*******************************************************************************/ *******************************************************************************/
uint64_t Cy_Profile_GetSumWeightedCounts(cy_stc_profile_ctr_ptr_t ptrsArray[], uint64_t Cy_Profile_GetSumWeightedCounts(cy_stc_profile_ctr_ptr_t ptrsArray[],

458
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/profile/cy_profile.h Normal file
View File

@ -0,0 +1,458 @@
/***************************************************************************//**
* \file cy_profile.h
* \version 1.0
*
* Provides an API declaration of the energy profiler driver.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
/**
* \defgroup group_energy_profiler Energy Profiler (Profile)
* \{
*
* The energy profiler driver is an API for configuring and using the profile
* hardware block. The profile block enables measurement of the signal activity
* of select peripherals and monitor sources during a measurement window. Using
* these measurements, it is possible to construct a profile of the energy consumed
* in the device by scaling the individual peripheral actvities with appropriate
* scaling (weight) factors. This gives the application the ability to monitor
* the energy consumed by the internal resources with minimal CPU overhead and
* without external monitoring hardware.
*
* \section group_profile_details Details
*
* \subsection group_profile_hardware Profile Hardware
*
* The profile hardware consists of a number of profile counters that accept specific
* triggers for incrementing the count value. This allows the events of the source
* (such as the number of SCB0 bus accesses or the duration of time the BLE RX radio
* is active) to be counted during the measurement window. The available monitor
* sources in the device can be found in the en_ep_mon_sel_t enum in the device
* configuration file (e.g. psoc62_config.h). These can be sourced to any of the
* profile counters as triggers. There are two methods of using the monitor sources
* in a profile counter.
*
* - Event: The count value is incremented when a pulse event signal is seen by the
* counter. This type of monitoring is suitable when the monitoring source of
* interest needs to count the discrete events (such as the number of Flash read
* accesses) happening in the measurement window.
*
* - Duration: The count value is incremented at every clock edge while the monitor
* signal is high. This type of monitoring is suitable when a signal is active for
* a finite amount of time (such as the time the BLE TX radio is active) and the
* duration needs to be expressed as number of clock cycles in the measurement window.
*
* Many of the available monitor sources are suitable for event type monitoring.
* Using a duration type on these signals may not give valuable information. Review
* the device TRM for more information on the monitor sources and details on how they
* should be used.
*
* \subsection group_profile_measurement_types Measurement Types
*
* Depending on the item of interest, energy measurement can be performed by using
* the following methods.
*
* - Continuous measurement: A profile counter can be assigned a monitor signal of
* constant 1 (PROFILE_ONE), which sets the counter to increment at every (assigned)
* clock cycle. This can be used to give a reference time for the measurement window
* and also allows the construction of time stamps. For example, a software controlled
* GPIO can be "timestamped" by reading the counter value (on the fly) before it is
* toggled. When the measurement window ends, the energy contribution caused by the
* GPIO toggle can be incorporated into the final calculation.
*
* - Event measurement: Monitored events happening in a measurement window can be
* used to increment a profile counter. This gives the activity numbers, which can
* then be multiplied by the instantaneous power numbers associated with the source
* to give the average energy consumption (Energy = Power x time). For example, the
* energy consumped by an Operating System (OS) task can be estimated by monitoring
* the processor's active cycle count (E.g. CPUSS_MONITOR_CM4) and the Flash read
* accesses (CPUSS_MONITOR_FLASH). Note that these activity numbers can also be
* timestamped using the continuous measurement method to differentiate between the
* different task switches. The activity numbers are then multiplied by the associated
* processor and flash access power numbers to give the average energy consumed by
* that task.
*
* - Duration measurement: A peripheral event such as the SMIF select signal can be
* used by a profile counter to measure the time spent on XIP communication through the
* SPI interface. This activity number can then be multiplied by the power associated
* with that activity to give the average energy consumed by that block during the
* measurement window. This type of monitoring should only be performed for signals
* that are difficult to track in software. For example, a combination of interrupts
* and time stamps can be used to track the activity of many peripherals in a continuous
* monitoring model. However tracking the activity of signals such the BLE radio
* should be done using the duration measurement method.
*
* - Low power measurement: The profile counters do not support measurement during chip
* deep-sleep, hibernate and off states. i.e. the profile counters are meant for active
* run-time measurements only. In order to measure the time spent in low power modes (LPM),
* a real-time clock (RTC) should be used. Take a timestamp before LPM entry and a
* timestamp upon LPM exit in a continuous measurement model. Then multiply the difference
* by the appropriate LPM power numbers.
*
* \subsection group_profile_usage Driver Usage
*
* At the highest level, the energy profiler must perform the following steps to
* obtain a measurement:
*
* 1. Initialize the profile hardware block.
* 2. Initialize the profile interrupt (profile_interrupt_IRQn).
* 3. Configure, initialize, and enable the profile counters.
* 4. Enable the profile interrupt and start the profiling/measurement window.
* 5. Perform run-time reads of the counters (if needed).
* 6. Disable the profile interrupt and stop the profiling/measurement window.
* 7. Read the counters and gather the results.
* 8. Calculate the energy consumption.
*
* Refer to the SysInt driver on the details of configuring the profile hardware interrupt.
*
* The profile interrupt triggers when a counter overflow event is detected on any of the
* enabled profile counters. A sample interrupt service routine Cy_Profile_ISR() is provided,
* which can be used to update the internal counter states stored in RAM. Refer to the
* Configuration Considerations for more information.
*
* \section group_profile_configuration Configuration Considerations
*
* Each counter is a 32-bit register that counts either a number of clock cycles,
* or a number of events. It is possible to overflow the 32-bit register. To address
* this issue, the driver implements a 32-bit overflow counter. Combined with the 32-bit
* register, this gives a 64-bit counter for each monitored source.
*
* When an overflow occurs, the profile hardware generates an interrupt. The interrupt is
* configured using the SysInt driver, where the sample interrupt handler Cy_Profile_ISR()
* can be used as the ISR. The ISR increments the overflow counter for each profiling counter
* and clears the interrupt.
*
* \section group_profile_more_information More Information
*
* See the profiler chapter of the device technical reference manual (TRM).
*
* \section group_profile_MISRA MISRA-C Compliance
* <table class="doxtable">
* <tr>
* <th>MISRA Rule</th>
* <th>Rule Class (Required/Advisory)</th>
* <th>Rule Description</th>
* <th>Description of Deviation(s)</th>
* </tr>
* <tr>
* <td>12.4</td>
* <td>R</td>
* <td>Right hand operand of '&&' or '||' is an expression with possible side effects.</td>
* <td>Function-like macros are used to achieve more efficient code.</td>
* </tr>
* <tr>
* <td>16.7</td>
* <td>A</td>
* <td>A pointer parameter can be of type 'pointer to const'.</td>
* <td>The pointer is cast for comparison purposes and thus can't be a const.</td>
* </tr>
* </table>
*
* \section group_profile_changelog Changelog
* <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr>
* <td>1.0</td>
* <td>Initial version</td>
* <td></td>
* </tr>
* </table>
*
* \defgroup group_profile_macros Macros
* \defgroup group_profile_functions Functions
* \{
* \defgroup group_profile_functions_interrupt Interrupt Functions
* \defgroup group_profile_functions_general General Functions
* \defgroup group_profile_functions_counter Counter Functions
* \defgroup group_profile_functions_calculation Calculation Functions
* \}
* \defgroup group_profile_data_structures Data Structures
* \defgroup group_profile_enums Enumerated Types
*/
#if !defined(CY_PROFILE_H)
#define CY_PROFILE_H
#include "cy_device_headers.h"
#include "syslib/cy_syslib.h"
#include <stddef.h>
#ifndef CY_IP_MXPROFILE
#error "The PROFILE driver is not supported on this device"
#endif
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/** \addtogroup group_profile_macros
* \{
*/
/** Driver major version */
#define CY_PROFILE_DRV_VERSION_MAJOR 1
/** Driver minor version */
#define CY_PROFILE_DRV_VERSION_MINOR 0
/** Profile driver identifier */
#define CY_PROFILE_ID CY_PDL_DRV_ID(0x1EU)
/** Start profiling command for the CMD register */
#define CY_PROFILE_START_TR 1UL
/** Stop profiling command for the CMD register */
#define CY_PROFILE_STOP_TR 2UL
/** Command to clear all counter registers to 0 */
#define CY_PROFILE_CLR_ALL_CNT 0x100UL
/** \} group_profile_macros */
/**
* \addtogroup group_profile_enums
* \{
*/
/**
* Profile counter reference clock source. Used when duration monitoring.
*/
typedef enum
{
CY_PROFILE_CLK_TIMER = 0, /**< Timer clock (TimerClk) */
CY_PROFILE_CLK_IMO = 1, /**< Internal main oscillator (IMO) */
CY_PROFILE_CLK_ECO = 2, /**< External crystal oscillator (ECO) */
CY_PROFILE_CLK_LF = 3, /**< Low-frequency clock (LFCLK) */
CY_PROFILE_CLK_HF = 4, /**< High-Frequency clock (HFCLK0) */
CY_PROFILE_CLK_PERI = 5, /**< Peripheral clock (PeriClk) */
} cy_en_profile_ref_clk_t;
/**
* Monitor method type.
*/
typedef enum
{
CY_PROFILE_EVENT = 0, /**< Count (edge-detected) module events */
CY_PROFILE_DURATION = 1, /**< Count (level) duration in clock cycles */
} cy_en_profile_duration_t;
/** Profiler status codes */
typedef enum
{
CY_PROFILE_SUCCESS = 0x00U, /**< Operation completed successfully */
CY_PROFILE_BAD_PARAM = CY_PROFILE_ID | CY_PDL_STATUS_ERROR | 1UL /**< Invalid input parameters */
} cy_en_profile_status_t;
/** \} group_profile_enums */
/**
* \addtogroup group_profile_data_structures
* \{
*/
/**
* Profile counter control register structure. For each counter, holds the CTL register fields.
*/
typedef struct
{
cy_en_profile_duration_t cntDuration; /**< 0 = event; 1 = duration */
cy_en_profile_ref_clk_t refClkSel; /**< The reference clock used by the counter */
en_ep_mon_sel_t monSel; /**< The monitor signal to be observed by the counter */
} cy_stc_profile_ctr_ctl_t;
/**
* Software structure for holding a profile counter status and configuration information.
*/
typedef struct
{
uint8_t ctrNum; /**< Profile counter number */
uint8_t used; /**< 0 = available; 1 = used */
cy_stc_profile_ctr_ctl_t ctlRegVals; /**< Initial counter CTL register settings */
PROFILE_CNT_STRUCT_Type * cntAddr; /**< Base address of the counter instance registers */
uint32_t ctlReg; /**< Current CTL register value */
uint32_t cntReg; /**< Current CNT register value */
uint32_t overflow; /**< Extension of cntReg to form a 64-bit counter value */
uint32_t weight; /**< Weighting factor for the counter */
} cy_stc_profile_ctr_t;
/**
* Pointer to a structure holding the status information for a profile counter.
*/
typedef cy_stc_profile_ctr_t * cy_stc_profile_ctr_ptr_t;
/** \} group_profile_data_structures */
/**
* \addtogroup group_profile_functions
* \{
*/
/**
* \addtogroup group_profile_functions_interrupt
* \{
*/
/* ========================================================================== */
/* ==================== INTERRUPT FUNCTION SECTION ==================== */
/* ========================================================================== */
void Cy_Profile_ISR(void);
/** \} group_profile_functions_interrupt */
/**
* \addtogroup group_profile_functions_general
* \{
*/
__STATIC_INLINE void Cy_Profile_Init(void);
__STATIC_INLINE void Cy_Profile_DeInit(void);
void Cy_Profile_StartProfiling(void);
__STATIC_INLINE void Cy_Profile_DeInit(void);
__STATIC_INLINE void Cy_Profile_StopProfiling(void);
__STATIC_INLINE uint32_t Cy_Profile_IsProfiling(void);
/* ========================================================================== */
/* =============== GENERAL PROFILE FUNCTIONS SECTION ================= */
/* ========================================================================== */
/*******************************************************************************
* Function Name: Cy_Profile_Init
****************************************************************************//**
*
* Initializes and enables the profile hardware.
*
* This function must be called once when energy profiling is desired. The
* operation does not start a profiling session.
*
* \note The profile interrupt must also be configured. \ref Cy_Profile_ISR()
* can be used as its handler.
*
* \funcusage
* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_Init
*
*******************************************************************************/
__STATIC_INLINE void Cy_Profile_Init(void)
{
PROFILE->CTL = _VAL2FLD(PROFILE_CTL_ENABLED, 1UL/*enabled */) |
_VAL2FLD(PROFILE_CTL_WIN_MODE, 0UL/*start/stop mode*/);
PROFILE->INTR_MASK = 0UL; /* clear all counter interrupt mask bits */
}
/*******************************************************************************
* Function Name: Cy_Profile_DeInit
****************************************************************************//**
*
* Clears the interrupt mask and disables the profile hardware.
*
* This function should be called when energy profiling is no longer desired.
*
* \note The profile interrupt is not disabled by this operation and must be
* disabled separately.
*
* \funcusage
* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_DeInit
*
*******************************************************************************/
__STATIC_INLINE void Cy_Profile_DeInit(void)
{
PROFILE->CTL = _VAL2FLD(PROFILE_CTL_ENABLED, 0UL/*disabled */);
PROFILE->INTR_MASK = 0UL; /* clear all counter interrupt mask bits */
}
/*******************************************************************************
* Function Name: Cy_Profile_StopProfiling
****************************************************************************//**
*
* Stops the profiling/measurement window.
*
* This operation prevents the enabled profile counters from counting.
*
* \note The profile interrupt should be disabled before calling this function.
*
* \funcusage
* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_StopProfiling
*
*******************************************************************************/
__STATIC_INLINE void Cy_Profile_StopProfiling(void)
{
PROFILE->CMD = CY_PROFILE_STOP_TR;
}
/*******************************************************************************
* Function Name: Cy_Profile_IsProfiling
****************************************************************************//**
*
* Reports the active status of the profiling window.
*
* \return 0 = profiling is not active; 1 = profiling is active
*
* \funcusage
* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_IsProfiling
*
*******************************************************************************/
__STATIC_INLINE uint32_t Cy_Profile_IsProfiling(void)
{
return _FLD2VAL(PROFILE_STATUS_WIN_ACTIVE, PROFILE->STATUS);
}
/** \} group_profile_functions_general */
/**
* \addtogroup group_profile_functions_counter
* \{
*/
void Cy_Profile_ClearConfiguration(void);
__STATIC_INLINE void Cy_Profile_ClearCounters(void);
cy_stc_profile_ctr_ptr_t Cy_Profile_ConfigureCounter(en_ep_mon_sel_t monitor, cy_en_profile_duration_t duration, cy_en_profile_ref_clk_t refClk, uint32_t weight);
cy_en_profile_status_t Cy_Profile_FreeCounter(cy_stc_profile_ctr_ptr_t ctrAddr);
cy_en_profile_status_t Cy_Profile_EnableCounter(cy_stc_profile_ctr_ptr_t ctrAddr);
cy_en_profile_status_t Cy_Profile_DisableCounter(cy_stc_profile_ctr_ptr_t ctrAddr);
/* ========================================================================== */
/* =================== COUNTER FUNCTIONS SECTION ====================== */
/* ========================================================================== */
/*******************************************************************************
* Function Name: Cy_Profile_ClearCounters
****************************************************************************//**
*
* Clears all hardware counters to 0.
*
* \funcusage
* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_ClearCounters
*
*******************************************************************************/
__STATIC_INLINE void Cy_Profile_ClearCounters(void)
{
PROFILE->CMD = CY_PROFILE_CLR_ALL_CNT;
}
/** \} group_profile_functions_counter */
/**
* \addtogroup group_profile_functions_calculation
* \{
*/
/* ========================================================================== */
/* ================== CALCULATION FUNCTIONS SECTION =================== */
/* ========================================================================== */
cy_en_profile_status_t Cy_Profile_GetRawCount(cy_stc_profile_ctr_ptr_t ctrAddr, uint64_t *result);
cy_en_profile_status_t Cy_Profile_GetWeightedCount(cy_stc_profile_ctr_ptr_t ctrAddr, uint64_t *result);
uint64_t Cy_Profile_GetSumWeightedCounts(cy_stc_profile_ctr_ptr_t ptrsArray[], uint32_t numCounters);
/** \} group_profile_functions_calculation */
/** \} group_profile_functions */
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* CY_PROFILE_H */
/** \} group_profile */
/* [] END OF FILE */

335
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/prot/cy_prot.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/prot/cy_prot.c
View File

@ -1,13 +1,13 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_prot.c * \file cy_prot.c
* \version 1.0 * \version 1.10
* *
* \brief * \brief
* Provides an API implementation of the Protection Unit driver * Provides an API implementation of the Protection Unit driver
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -28,7 +28,7 @@ extern "C" {
* and privilege level of the bus transaction created by the specified master. * and privilege level of the bus transaction created by the specified master.
* *
* \param busMaster * \param busMaster
* Indicates which master needs to be configured. Refer to the CY_PROT_MASTER_X * Indicates which master needs to be configured. Refer to the CPUSS_MS_ID_X
* defines. * defines.
* *
* \param privileged * \param privileged
@ -53,19 +53,59 @@ extern "C" {
* CY_PROT_FAILURE | The resource is locked * CY_PROT_FAILURE | The resource is locked
* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed * CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigBusMaster
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool privileged, bool secure, uint32_t pcMask) cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool privileged, bool secure, uint32_t pcMask)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
uint32_t regVal; uint32_t regVal;
uint32_t * addrMsCtl = (uint32_t *)(PROT_BASE + (uint32_t)((uint32_t)busMaster << CY_PROT_MSX_CTL_SHIFT)); uint32_t * addrMsCtl;
if((uint32_t)(pcMask & CY_PROT_MPU_PC_LIMIT_MASK) != 0UL) CY_ASSERT_L1(CY_PROT_IS_BUS_MASTER_VALID(busMaster));
addrMsCtl = (uint32_t *)(PROT_BASE + (uint32_t)((uint32_t)busMaster << CY_PROT_MSX_CTL_SHIFT));
/* Check if PC mask is in supported range */
switch (busMaster)
{ {
/* PC mask out of range - not supported in device */ case (CPUSS_MS_ID_CM0):
status = CY_PROT_BAD_PARAM; {
status = ((uint32_t)(pcMask & CY_PROT_MS0_PC_LIMIT_MASK) != 0UL) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
break;
} }
else case (CPUSS_MS_ID_CRYPTO):
{
status = ((uint32_t)(pcMask & CY_PROT_MS1_PC_LIMIT_MASK) != 0UL) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
break;
}
case (CPUSS_MS_ID_DW0):
{
status = ((uint32_t)(pcMask & CY_PROT_MS2_PC_LIMIT_MASK) != 0UL) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
break;
}
case (CPUSS_MS_ID_DW1):
{
status = ((uint32_t)(pcMask & CY_PROT_MS3_PC_LIMIT_MASK) != 0UL) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
break;
}
case (CPUSS_MS_ID_CM4):
{
status = ((uint32_t)(pcMask & CY_PROT_MS14_PC_LIMIT_MASK) != 0UL) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
break;
}
case (CPUSS_MS_ID_TC):
{
status = ((uint32_t)(pcMask & CY_PROT_MS15_PC_LIMIT_MASK) != 0UL) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
break;
}
default:
status = CY_PROT_BAD_PARAM;
break;
}
if(status != CY_PROT_BAD_PARAM)
{ {
regVal = _VAL2FLD(PROT_SMPU_MS0_CTL_NS, !secure) regVal = _VAL2FLD(PROT_SMPU_MS0_CTL_NS, !secure)
| _VAL2FLD(PROT_SMPU_MS0_CTL_P, privileged) | _VAL2FLD(PROT_SMPU_MS0_CTL_P, privileged)
@ -88,7 +128,7 @@ cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool pri
* master, the value set through this function is used. * master, the value set through this function is used.
* *
* \param busMaster * \param busMaster
* The bus master to configure. Refer to the CY_PROT_MASTER_X defines. * The bus master to configure. Refer to the CPUSS_MS_ID_X defines.
* *
* \param pc * \param pc
* Active protection context of the specified master. Note that only those * Active protection context of the specified master. Note that only those
@ -103,18 +143,58 @@ cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool pri
* CY_PROT_FAILURE | The resource is locked * CY_PROT_FAILURE | The resource is locked
* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed * CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_SetActivePC
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_SetActivePC(en_prot_master_t busMaster, uint32_t pc) cy_en_prot_status_t Cy_Prot_SetActivePC(en_prot_master_t busMaster, uint32_t pc)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
PROT_MPU_Type* addrMpu = (PROT_MPU_Type*)(&PROT->CYMPU[busMaster]); PROT_MPU_Type* addrMpu;
if(pc >= (uint32_t)CY_PROT_MS_PC_NR_MAX) CY_ASSERT_L1(CY_PROT_IS_BUS_MASTER_VALID(busMaster));
addrMpu = (PROT_MPU_Type*)(&PROT->CYMPU[busMaster]);
/* Check if PC value is in supported range */
switch (busMaster)
{ {
/* Invalid PC value - not supported in device */ case (CPUSS_MS_ID_CM0):
status = CY_PROT_BAD_PARAM; {
status = (pc > CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
break;
} }
else case (CPUSS_MS_ID_CRYPTO):
{
status = (pc > CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
break;
}
case (CPUSS_MS_ID_DW0):
{
status = (pc > CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
break;
}
case (CPUSS_MS_ID_DW1):
{
status = (pc > CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
break;
}
case (CPUSS_MS_ID_CM4):
{
status = (pc > CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
break;
}
case (CPUSS_MS_ID_TC):
{
status = (pc > CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
break;
}
default:
status = CY_PROT_BAD_PARAM;
break;
}
if(status != CY_PROT_BAD_PARAM)
{ {
addrMpu->MS_CTL = _VAL2FLD(PROT_MPU_MS_CTL_PC, pc) | _VAL2FLD(PROT_MPU_MS_CTL_PC_SAVED, pc); addrMpu->MS_CTL = _VAL2FLD(PROT_MPU_MS_CTL_PC, pc) | _VAL2FLD(PROT_MPU_MS_CTL_PC_SAVED, pc);
status = (_FLD2VAL(PROT_MPU_MS_CTL_PC, addrMpu->MS_CTL) != pc) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; status = (_FLD2VAL(PROT_MPU_MS_CTL_PC, addrMpu->MS_CTL) != pc) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
@ -132,15 +212,22 @@ cy_en_prot_status_t Cy_Prot_SetActivePC(en_prot_master_t busMaster, uint32_t pc)
* *
* \param busMaster * \param busMaster
* The bus master, whose protection context is being read. Refer to the * The bus master, whose protection context is being read. Refer to the
* CY_PROT_MASTER_X defines. * CPUSS_MS_ID_X defines.
* *
* \return * \return
* Active protection context of the master * Active protection context of the master
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_SetActivePC
*
*******************************************************************************/ *******************************************************************************/
uint32_t Cy_Prot_GetActivePC(en_prot_master_t busMaster) uint32_t Cy_Prot_GetActivePC(en_prot_master_t busMaster)
{ {
PROT_MPU_Type* addrMpu = (PROT_MPU_Type*)(&PROT->CYMPU[busMaster]); PROT_MPU_Type* addrMpu;
CY_ASSERT_L1(CY_PROT_IS_BUS_MASTER_VALID(busMaster));
addrMpu = (PROT_MPU_Type*)(&PROT->CYMPU[busMaster]);
return ((uint32_t)_FLD2VAL(PROT_MPU_MS_CTL_PC, addrMpu->MS_CTL)); return ((uint32_t)_FLD2VAL(PROT_MPU_MS_CTL_PC, addrMpu->MS_CTL));
} }
@ -170,13 +257,21 @@ uint32_t Cy_Prot_GetActivePC(en_prot_master_t busMaster)
* CY_PROT_SUCCESS | The MPU struct was configured * CY_PROT_SUCCESS | The MPU struct was configured
* CY_PROT_FAILURE | Configuration failed due to a protection violation * CY_PROT_FAILURE | Configuration failed due to a protection violation
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigMpuStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_ConfigMpuStruct(PROT_MPU_MPU_STRUCT_Type* base, const cy_stc_mpu_cfg_t* config) cy_en_prot_status_t Cy_Prot_ConfigMpuStruct(PROT_MPU_MPU_STRUCT_Type* base, const cy_stc_mpu_cfg_t* config)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
uint32_t addrReg; uint32_t addrReg;
uint32_t attReg; uint32_t attReg;
CY_ASSERT_L1(NULL != base);
CY_ASSERT_L3(CY_PROT_IS_MPU_PERM_VALID(config->userPermission));
CY_ASSERT_L3(CY_PROT_IS_MPU_PERM_VALID(config->privPermission));
CY_ASSERT_L3(CY_PROT_IS_REGION_SIZE_VALID(config->regionSize));
addrReg = _VAL2FLD(PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE, config->subregions) addrReg = _VAL2FLD(PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE, config->subregions)
| _VAL2FLD(PROT_MPU_MPU_STRUCT_ADDR_ADDR24, (uint32_t)((uint32_t)config->address >> CY_PROT_ADDR_SHIFT)); | _VAL2FLD(PROT_MPU_MPU_STRUCT_ADDR_ADDR24, (uint32_t)((uint32_t)config->address >> CY_PROT_ADDR_SHIFT));
attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK) attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
@ -209,10 +304,13 @@ cy_en_prot_status_t Cy_Prot_ConfigMpuStruct(PROT_MPU_MPU_STRUCT_Type* base, cons
* CY_PROT_SUCCESS | The MPU struct was enabled * CY_PROT_SUCCESS | The MPU struct was enabled
* CY_PROT_FAILURE | The MPU struct is disabled and possibly locked * CY_PROT_FAILURE | The MPU struct is disabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnableMpuStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_EnableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base) cy_en_prot_status_t Cy_Prot_EnableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT |= _VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT |= _VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PROT_MPU_MPU_STRUCT_ATT_ENABLED, base->ATT) != CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PROT_MPU_MPU_STRUCT_ATT_ENABLED, base->ATT) != CY_PROT_STRUCT_ENABLE) ?
@ -240,10 +338,13 @@ cy_en_prot_status_t Cy_Prot_EnableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base)
* CY_PROT_SUCCESS | The MPU struct was disabled * CY_PROT_SUCCESS | The MPU struct was disabled
* CY_PROT_FAILURE | The MPU struct is enabled and possibly locked * CY_PROT_FAILURE | The MPU struct is enabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisableMpuStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_DisableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base) cy_en_prot_status_t Cy_Prot_DisableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT &= ~_VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT &= ~_VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PROT_MPU_MPU_STRUCT_ATT_ENABLED, base->ATT) == CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PROT_MPU_MPU_STRUCT_ATT_ENABLED, base->ATT) == CY_PROT_STRUCT_ENABLE) ?
@ -283,12 +384,19 @@ cy_en_prot_status_t Cy_Prot_DisableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base)
* CY_PROT_FAILURE | The resource is locked * CY_PROT_FAILURE | The resource is locked
* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed * CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigSmpuMasterStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_ConfigSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config) cy_en_prot_status_t Cy_Prot_ConfigSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
uint32_t attReg; uint32_t attReg;
CY_ASSERT_L1(NULL != base);
CY_ASSERT_L3(CY_PROT_IS_SMPU_MS_PERM_VALID(config->userPermission));
CY_ASSERT_L3(CY_PROT_IS_SMPU_MS_PERM_VALID(config->privPermission));
if(((uint32_t)config->pcMask & CY_PROT_SMPU_PC_LIMIT_MASK) != 0UL) if(((uint32_t)config->pcMask & CY_PROT_SMPU_PC_LIMIT_MASK) != 0UL)
{ {
/* PC mask out of range - not supported in device */ /* PC mask out of range - not supported in device */
@ -343,13 +451,21 @@ cy_en_prot_status_t Cy_Prot_ConfigSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* b
* CY_PROT_FAILURE | The resource is locked * CY_PROT_FAILURE | The resource is locked
* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed * CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigSmpuSlaveStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_ConfigSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config) cy_en_prot_status_t Cy_Prot_ConfigSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
uint32_t addrReg; uint32_t addrReg;
uint32_t attReg; uint32_t attReg;
CY_ASSERT_L1(NULL != base);
CY_ASSERT_L3(CY_PROT_IS_SMPU_SL_PERM_VALID(config->userPermission));
CY_ASSERT_L3(CY_PROT_IS_SMPU_SL_PERM_VALID(config->privPermission));
CY_ASSERT_L3(CY_PROT_IS_REGION_SIZE_VALID(config->regionSize));
if(((uint32_t)config->pcMask & CY_PROT_SMPU_PC_LIMIT_MASK) != 0UL) if(((uint32_t)config->pcMask & CY_PROT_SMPU_PC_LIMIT_MASK) != 0UL)
{ {
/* PC mask out of range - not supported in device */ /* PC mask out of range - not supported in device */
@ -395,10 +511,13 @@ cy_en_prot_status_t Cy_Prot_ConfigSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* ba
* CY_PROT_SUCCESS | The Master PU struct was enabled * CY_PROT_SUCCESS | The Master PU struct was enabled
* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked * CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnableSmpuMasterStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_EnableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base) cy_en_prot_status_t Cy_Prot_EnableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT1 |= _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT1 |= _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ?
@ -428,10 +547,13 @@ cy_en_prot_status_t Cy_Prot_EnableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* b
* CY_PROT_SUCCESS | The Master PU struct was disabled * CY_PROT_SUCCESS | The Master PU struct was disabled
* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked * CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisableSmpuMasterStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_DisableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base) cy_en_prot_status_t Cy_Prot_DisableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT1 &= ~_VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT1 &= ~_VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ?
@ -461,10 +583,13 @@ cy_en_prot_status_t Cy_Prot_DisableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type*
* CY_PROT_SUCCESS | The Slave PU struct was enabled * CY_PROT_SUCCESS | The Slave PU struct was enabled
* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked * CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnableSmpuSlaveStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_EnableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base) cy_en_prot_status_t Cy_Prot_EnableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT0 |= _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT0 |= _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ?
@ -494,10 +619,13 @@ cy_en_prot_status_t Cy_Prot_EnableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* ba
* CY_PROT_SUCCESS | The Slave PU struct was disabled * CY_PROT_SUCCESS | The Slave PU struct was disabled
* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked * CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisableSmpuSlaveStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_DisableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base) cy_en_prot_status_t Cy_Prot_DisableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT0 &= ~_VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT0 &= ~_VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ?
@ -537,12 +665,19 @@ cy_en_prot_status_t Cy_Prot_DisableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* b
* CY_PROT_FAILURE | The resource is locked * CY_PROT_FAILURE | The resource is locked
* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed * CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigPpuProgMasterStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config) cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
uint32_t attReg; uint32_t attReg;
CY_ASSERT_L1(NULL != base);
CY_ASSERT_L3(CY_PROT_IS_PROG_MS_PERM_VALID(config->userPermission));
CY_ASSERT_L3(CY_PROT_IS_PROG_MS_PERM_VALID(config->privPermission));
if(((uint32_t)config->pcMask & CY_PROT_PPU_PROG_PC_LIMIT_MASK) != 0UL) if(((uint32_t)config->pcMask & CY_PROT_PPU_PROG_PC_LIMIT_MASK) != 0UL)
{ {
/* PC mask out of range - not supported in device */ /* PC mask out of range - not supported in device */
@ -601,13 +736,21 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterStruct(PERI_PPU_PR_Type* base, co
* CY_PROT_FAILURE | The resource is locked * CY_PROT_FAILURE | The resource is locked
* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed * CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigPpuProgSlaveStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config) cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
uint32_t addrReg; uint32_t addrReg;
uint32_t attReg; uint32_t attReg;
CY_ASSERT_L1(NULL != base);
CY_ASSERT_L3(CY_PROT_IS_PROG_SL_PERM_VALID(config->userPermission));
CY_ASSERT_L3(CY_PROT_IS_PROG_SL_PERM_VALID(config->privPermission));
CY_ASSERT_L3(CY_PROT_IS_REGION_SIZE_VALID(config->regionSize));
if(((uint32_t)config->pcMask & CY_PROT_PPU_PROG_PC_LIMIT_MASK) != 0UL) if(((uint32_t)config->pcMask & CY_PROT_PPU_PROG_PC_LIMIT_MASK) != 0UL)
{ {
/* PC mask out of range - not supported in device */ /* PC mask out of range - not supported in device */
@ -661,10 +804,13 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, con
* CY_PROT_SUCCESS | The Master PU struct was enabled * CY_PROT_SUCCESS | The Master PU struct was enabled
* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked * CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnablePpuProgMasterStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_EnablePpuProgMasterStruct(PERI_PPU_PR_Type* base) cy_en_prot_status_t Cy_Prot_EnablePpuProgMasterStruct(PERI_PPU_PR_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT1 |= _VAL2FLD(PERI_PPU_PR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT1 |= _VAL2FLD(PERI_PPU_PR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PERI_PPU_PR_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PERI_PPU_PR_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ?
@ -695,10 +841,13 @@ cy_en_prot_status_t Cy_Prot_EnablePpuProgMasterStruct(PERI_PPU_PR_Type* base)
* CY_PROT_SUCCESS | The Master PU struct was disabled * CY_PROT_SUCCESS | The Master PU struct was disabled
* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked * CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisablePpuProgMasterStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_DisablePpuProgMasterStruct(PERI_PPU_PR_Type* base) cy_en_prot_status_t Cy_Prot_DisablePpuProgMasterStruct(PERI_PPU_PR_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT1 &= ~_VAL2FLD(PERI_PPU_PR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT1 &= ~_VAL2FLD(PERI_PPU_PR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PERI_PPU_PR_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PERI_PPU_PR_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ?
@ -728,10 +877,13 @@ cy_en_prot_status_t Cy_Prot_DisablePpuProgMasterStruct(PERI_PPU_PR_Type* base)
* CY_PROT_SUCCESS | The Slave PU struct was enabled * CY_PROT_SUCCESS | The Slave PU struct was enabled
* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked * CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnablePpuProgSlaveStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveStruct(PERI_PPU_PR_Type* base) cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveStruct(PERI_PPU_PR_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT0 |= _VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT0 |= _VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PERI_PPU_PR_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PERI_PPU_PR_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ?
@ -762,10 +914,13 @@ cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveStruct(PERI_PPU_PR_Type* base)
* CY_PROT_SUCCESS | The Slave PU struct was disabled * CY_PROT_SUCCESS | The Slave PU struct was disabled
* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked * CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisablePpuProgSlaveStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveStruct(PERI_PPU_PR_Type* base) cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveStruct(PERI_PPU_PR_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT0 &= ~_VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT0 &= ~_VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PERI_PPU_PR_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PERI_PPU_PR_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ?
@ -805,12 +960,19 @@ cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveStruct(PERI_PPU_PR_Type* base)
* CY_PROT_FAILURE | The resource is locked * CY_PROT_FAILURE | The resource is locked
* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed * CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigPpuFixedGrMasterStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrMasterStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config) cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrMasterStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
uint32_t attReg; uint32_t attReg;
CY_ASSERT_L1(NULL != base);
CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->userPermission));
CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->privPermission));
if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
{ {
/* PC mask out of range - not supported in device */ /* PC mask out of range - not supported in device */
@ -874,12 +1036,19 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrMasterStruct(PERI_PPU_GR_Type* base,
* CY_PROT_FAILURE | The resource is locked * CY_PROT_FAILURE | The resource is locked
* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed * CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigPpuFixedGrSlaveStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config) cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
uint32_t attReg; uint32_t attReg;
CY_ASSERT_L1(NULL != base);
CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->userPermission));
CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->privPermission));
if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
{ {
/* PC mask out of range - not supported in device */ /* PC mask out of range - not supported in device */
@ -929,10 +1098,13 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base,
* CY_PROT_SUCCESS | The Master PU struct was enabled * CY_PROT_SUCCESS | The Master PU struct was enabled
* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked * CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnablePpuFixedGrMasterStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base) cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT1 |= _VAL2FLD(PERI_PPU_GR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT1 |= _VAL2FLD(PERI_PPU_GR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PERI_PPU_GR_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PERI_PPU_GR_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ?
@ -963,10 +1135,13 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base)
* CY_PROT_SUCCESS | The Master PU struct was disabled * CY_PROT_SUCCESS | The Master PU struct was disabled
* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked * CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisablePpuFixedGrMasterStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base) cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT1 &= ~_VAL2FLD(PERI_PPU_GR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT1 &= ~_VAL2FLD(PERI_PPU_GR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PERI_PPU_GR_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PERI_PPU_GR_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ?
@ -996,10 +1171,13 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base
* CY_PROT_SUCCESS | The Slave PU struct was enabled * CY_PROT_SUCCESS | The Slave PU struct was enabled
* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked * CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnablePpuFixedGrSlaveStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base) cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT0 |= _VAL2FLD(PERI_PPU_GR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT0 |= _VAL2FLD(PERI_PPU_GR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PERI_PPU_GR_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PERI_PPU_GR_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ?
@ -1030,10 +1208,13 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base)
* CY_PROT_SUCCESS | The Slave PU struct was disabled * CY_PROT_SUCCESS | The Slave PU struct was disabled
* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked * CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisablePpuFixedGrSlaveStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base) cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT0 &= ~_VAL2FLD(PERI_PPU_GR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT0 &= ~_VAL2FLD(PERI_PPU_GR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PERI_PPU_GR_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PERI_PPU_GR_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ?
@ -1073,12 +1254,19 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base)
* CY_PROT_FAILURE | The resource is locked * CY_PROT_FAILURE | The resource is locked
* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed * CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigPpuFixedSlMasterStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config) cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
uint32_t attReg; uint32_t attReg;
CY_ASSERT_L1(NULL != base);
CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->userPermission));
CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->privPermission));
if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
{ {
/* PC mask out of range - not supported in device */ /* PC mask out of range - not supported in device */
@ -1141,12 +1329,19 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* ba
* CY_PROT_FAILURE | The resource is locked * CY_PROT_FAILURE | The resource is locked
* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed * CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigPpuFixedSlSlaveStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config) cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
uint32_t attReg; uint32_t attReg;
CY_ASSERT_L1(NULL != base);
CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->userPermission));
CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->privPermission));
if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
{ {
/* PC mask out of range - not supported in device */ /* PC mask out of range - not supported in device */
@ -1197,10 +1392,13 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* bas
* CY_PROT_SUCCESS | The Master PU struct was enabled * CY_PROT_SUCCESS | The Master PU struct was enabled
* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked * CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnablePpuFixedSlMasterStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base) cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT1 |= _VAL2FLD(PERI_GR_PPU_SL_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT1 |= _VAL2FLD(PERI_GR_PPU_SL_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PERI_GR_PPU_SL_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PERI_GR_PPU_SL_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ?
@ -1231,10 +1429,13 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* ba
* CY_PROT_SUCCESS | The Master PU struct was disabled * CY_PROT_SUCCESS | The Master PU struct was disabled
* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked * CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisablePpuFixedSlMasterStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base) cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT1 &= ~_VAL2FLD(PERI_GR_PPU_SL_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT1 &= ~_VAL2FLD(PERI_GR_PPU_SL_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PERI_GR_PPU_SL_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PERI_GR_PPU_SL_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ?
@ -1264,10 +1465,13 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* b
* CY_PROT_SUCCESS | The Slave PU struct was enabled * CY_PROT_SUCCESS | The Slave PU struct was enabled
* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked * CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnablePpuFixedSlSlaveStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base) cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT0 |= _VAL2FLD(PERI_GR_PPU_SL_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT0 |= _VAL2FLD(PERI_GR_PPU_SL_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PERI_GR_PPU_SL_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PERI_GR_PPU_SL_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ?
@ -1298,10 +1502,13 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* bas
* CY_PROT_SUCCESS | The Slave PU struct was disabled * CY_PROT_SUCCESS | The Slave PU struct was disabled
* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked * CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisablePpuFixedSlSlaveStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base) cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT0 &= ~_VAL2FLD(PERI_GR_PPU_SL_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT0 &= ~_VAL2FLD(PERI_GR_PPU_SL_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PERI_GR_PPU_SL_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PERI_GR_PPU_SL_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ?
@ -1341,12 +1548,19 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* ba
* CY_PROT_FAILURE | The resource is locked * CY_PROT_FAILURE | The resource is locked
* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed * CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigPpuFixedRgMasterStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config) cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
uint32_t attReg; uint32_t attReg;
CY_ASSERT_L1(NULL != base);
CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->userPermission));
CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->privPermission));
if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
{ {
/* PC mask out of range - not supported in device */ /* PC mask out of range - not supported in device */
@ -1409,12 +1623,19 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* ba
* CY_PROT_FAILURE | The resource is locked * CY_PROT_FAILURE | The resource is locked
* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed * CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigPpuFixedRgSlaveStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config) cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
uint32_t attReg; uint32_t attReg;
CY_ASSERT_L1(NULL != base);
CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->userPermission));
CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->privPermission));
if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
{ {
/* PC mask out of range - not supported in device */ /* PC mask out of range - not supported in device */
@ -1465,10 +1686,13 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* bas
* CY_PROT_SUCCESS | The Master PU struct was enabled * CY_PROT_SUCCESS | The Master PU struct was enabled
* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked * CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnablePpuFixedRgMasterStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base) cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT1 |= _VAL2FLD(PERI_GR_PPU_RG_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT1 |= _VAL2FLD(PERI_GR_PPU_RG_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PERI_GR_PPU_RG_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PERI_GR_PPU_RG_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ?
@ -1499,10 +1723,13 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* ba
* CY_PROT_SUCCESS | The Master PU struct was disabled * CY_PROT_SUCCESS | The Master PU struct was disabled
* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked * CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisablePpuFixedRgMasterStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base) cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT1 &= ~_VAL2FLD(PERI_GR_PPU_RG_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT1 &= ~_VAL2FLD(PERI_GR_PPU_RG_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PERI_GR_PPU_RG_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PERI_GR_PPU_RG_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ?
@ -1532,10 +1759,13 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* b
* CY_PROT_SUCCESS | The Slave PU struct was enabled * CY_PROT_SUCCESS | The Slave PU struct was enabled
* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked * CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnablePpuFixedRgSlaveStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base) cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT0 |= _VAL2FLD(PERI_GR_PPU_RG_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT0 |= _VAL2FLD(PERI_GR_PPU_RG_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PERI_GR_PPU_RG_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PERI_GR_PPU_RG_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ?
@ -1566,10 +1796,13 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* bas
* CY_PROT_SUCCESS | The Slave PU struct was disabled * CY_PROT_SUCCESS | The Slave PU struct was disabled
* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked * CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked
* *
* \funcusage
* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisablePpuFixedRgSlaveStruct
*
*******************************************************************************/ *******************************************************************************/
cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base) cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base)
{ {
cy_en_prot_status_t status = CY_PROT_SUCCESS; cy_en_prot_status_t status;
base->ATT0 &= ~_VAL2FLD(PERI_GR_PPU_RG_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); base->ATT0 &= ~_VAL2FLD(PERI_GR_PPU_RG_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
status = (_FLD2VAL(PERI_GR_PPU_RG_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ? status = (_FLD2VAL(PERI_GR_PPU_RG_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ?

895
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/prot/cy_prot.h Normal file
View File

@ -0,0 +1,895 @@
/***************************************************************************//**
* \file cy_prot.h
* \version 1.10
*
* \brief
* Provides an API declaration of the Protection Unit driver
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
/**
* \defgroup group_prot Protection Unit (Prot)
* \{
*
* The Protection Unit driver provides an API to configure the Memory Protection
* Units (MPU), Shared Memory Protection Units (SMPU), and Peripheral Protection
* Units (PPU). These are separate from the ARM Core MPUs and provide additional
* mechanisms for securing resource accesses. The Protection units address the
* following concerns in an embedded design:
* - <b>Security requirements:</b> This includes the prevention of malicious attacks
* to access secure memory or peripherals.
* - <b>Safety requirements:</b> This includes detection of accidental (non-malicious)
* SW errors and random HW errors. It is important to enable failure analysis
* to investigate the root cause of a safety violation.
*
* \section group_prot_protection_type Protection Types
*
* Protection units are hardware configuration structures that control bus accesses
* to the resources that they protect. By combining these individual configuration
* structures, a system is built to allow strict restrictions on the capabilities
* of individual bus masters (e.g. CM0+, CM4, Crypt) and their operating modes.
* This architecture can then be integrated into the overall security system
* of the end application. To build this system, 3 main protection unit types
* are available; MPU, SMPU and PPU. When a resource is accessed (memory/register),
* it must pass the evaluation performed for each category. These access evaluations
* are prioritized, where MPU has the highest priority, followed by SMPU, followed
* by PPU. i.e. if an SMPU and a PPU protect the same resource and if access is
* denied by the SMPU, then the PPU access evaluation is skipped. This can lead to a
* denial-of-service scenario and the application should pay special attention in
* taking ownership of the protection unit configurations.
*
* \subsection group_prot_memory_protection Memory Protection
*
* Memory access control for a bus master is controlled using an MPU. These are
* most often used to distinguish user and privileged accesses from a single bus
* master such as task switching in an OS/kernel. For ARM cores (CM0+, CM4), the
* core MPUs are used to perform this task. For other non-ARM bus masters such
* as Crypto, MPU structs are available, which can be used in a similar manner
* as the ARM core MPUs. These MPUs however must be configured by the ARM cores.
* Other bus masters that do not have an MPU, such as DMA (DW), inherit the access
* control attributes of the bus master that configured the channel. Also note
* that unlike other protection units, MPUs do not support protection context
* evaluation. MPU structs have a descending priority, where larger index struct
* has higher priority access evaluation over lower index structs. E.g. MPU_STRUCT15
* has higher priority than MPU_STRUCT14 and its access will be evaluated before
* MPU_STRUCT14. If both target the same memory, then the higher index (MPU_STRUCT15)
* will be used, and the lower index (MPU_STRUCT14) will be ignored.
*
* \subsection group_prot_shared_memory_protection Shared Memory Protection
*
* In order to protect a region of memory from all bus masters, an SMPU is used.
* This protection effectively allows only those with correct bus master access
* settings to read/write/execute the memory region. This type of protection
* is used in general memory such as Flash and SRAM. Peripheral registers are
* best configured using the peripheral protection units instead. SMPU structs
* have a descending priority, where larger index struct has higher priority
* access evaluation over lower index structs. E.g. SMPU_STRUCT15 has higher priority
* than SMPU_STRUCT14 and its access will be evaluated before SMPU_STRUCT14.
* If both target the same memory, then the higher index (MPU_STRUCT15) will be
* used, and the lower index (SMPU_STRUCT14) will be ignored.
*
* \subsection group_prot_peripheral_protection Peripheral Protection
*
* Peripheral protection is provided by PPUs and allow control of peripheral
* register accesses by bus masters. Four types of PPUs are available.
* - <b>Fixed Group (GR) PPUs</b> are used to protect an entire peripheral MMIO group
* from invalid bus master accesses. The MMIO grouping information and which
* resource belongs to which group is device specific and can be obtained
* from the device technical reference manual (TRM). Group PPUs have the highest
* priority in the PPU category. Therefore their access evaluations take precedence
* over the other types of PPUs.
* - <b>Programmable (PROG) PPUs</b> are used to protect any peripheral memory region
* in a device from invalid bus master accesses. It is the most versatile
* type of peripheral protection unit. Programmable PPUs have the second highest
* priority and take precedence over Region PPUs and Slave PPUs. Similar to SMPUs,
* higher index PROG PPUs have higher priority than lower indexes PROG PPUs.
* - <b>Fixed Region (RG) PPUs</b> are used to protect an entire peripheral slave
* instance from invalid bus master accesses. For example, TCPWM0, TCPWM1,
* SCB0, and SCB1, etc. Region PPUs have the third highest priority and take precedence
* over Slave PPUs.
* - <b>Fixed Slave (SL) PPUs</b> are used to protect specified regions of peripheral
* instances. For example, individual DW channel structs, SMPU structs, and
* IPC structs, etc. Slave PPUs have the lowest priority in the PPU category and
* therefore are evaluated last.
*
* \section group_prot_protection_context Protection Context
*
* Protection context (PC) attribute is present in all bus masters and is evaluated
* when accessing memory protected by an SMPU or a PPU. There are no limitations
* to how the PC values are allocated to the bus masters and this makes it
* possible for multiple bus masters to essentially share protection context
* values. The exception to this rule is the PC value 0.
*
* \subsection group_prot_pc0 PC=0
*
* Protection context 0 is a hardware controlled protection context update
* mechanism that allows only a single entry point for transitioning into PC=0
* value. This mechanism is only present for the secure CM0+ core and is a
* fundamental feature in defining a security solution. While all bus masters
* are configured to PC=0 at device boot, it is up to the security solution
* to transition these bus masters to PC!=0 values. Once this is done, those
* bus masters can no longer revert back to PC=0 and can no longer access
* resources protected at PC=0.
*
* In order to enter PC=0, the CM0+ core must assign an interrupt vector or
* an exception handler address to the CPUSS.CM0_PC0_HANDLER register. This
* allows the hardware to check whether the executing code address matches the
* value in this register. If they match, the current PC value is saved and
* the CM0+ bus master automatically transitions to PC=0. It is then up to
* the executing code to decide if and when it will revert to a PC!=0 value.
* At that point, the only way to re-transition to PC=0 is through the defined
* exception/interrupt handler.
*
* \section group_prot_access_evaluation Access Evaluation
*
* Each protection unit is capable of evaluating several access types. These can
* be used to build a system of logical evaluations for different kinds of
* bus master modes of operations. These access types can be divided into
* three broad access categories.
*
* - <b>User/Privileged access:</b> The ARM convention of user mode versus privileged
* mode is applied in the protection units. For ARM cores, switching between
* user and privileged modes is handled by updating its Control register or
* by exception entries. Other bus masters such as Crypto have their own
* user/privileged settings bit in the bus master control register. This is
* then controlled by the ARM cores. Bus masters that do not have
* user/privileged access controls, such as DMA, inherit their attributes
* from the bus master that configured it. The user/privileged distinction
* is used mainly in the MPUs for single bus master accesses but they can
* also be used in all other protection units.
* - <b>Secure/Non-secure access:</b> The secure/non-secure attribute is another
* identifier to distinguish between two separate modes of operations. Much
* like the user/privileged access, the secure/non-secure mode flag is present
* in the bus master control register. The ARM core does not have this
* attribute in its control register and must use the bus master control
* register instead. Bus masters that inherit their attributes, such as DMA,
* inherit the secure/non-secure attribute. The primary use-case for this
* access evaluation is to define a region to be secure or non-secure using
* an SMPU or a PPU. A bus master with a secure attribute can access
* both secure and non-secure regions, whereas a bus master with non-secure
* attribute can only access non-secure regions.
* - <b>Protection Context access:</b> Protection Context is an attribute
* that serves two purposes; To enter the hardware controlled secure PC=0
* mode of operation from non-secure modes and to provide finer granularity
* to the bus master access definitions. It is used in SMPU and PPU configuration
* to control which bus master protection context can access the resources
* that they protect.
*
* \section group_prot_protection_structure Protection Structure
*
* Each protection unit is comprised of a master struct and a slave struct pair.
* The exception to this rule is MPU structs, which only have the slave struct
* equivalent. The protection units apply their access evaluations in a decreasing
* index order. For example, if SMPU1 and SMPU2 both protect a specific memory region,
* the the higher index (SMPU2) will be evaluated first. In a secure system, the
* higher index protection structs would then provide the high level of security
* and the lower indexes would provide the lower level of security. Refer to the
* \ref group_prot_protection_type section for more information.
*
* \subsection group_prot_slave_struct Slave Struct
*
* The slave struct is used to configure the protection settings for the resource
* of interest (memory/registers). Depending on the type of protection unit,
* the available attributes differ. However all Slave protection units have the
* following general format.
*
* \subsubsection group_prot_slave_addr Slave Struct Address Definition
*
* - Address: For MPU, SMPU and PROG PPU, the address field is used to define
* the base memory region to apply the protection. This field has a dependency
* on the region size, which dictates the alignment of the protection unit. E.g.
* if the region size is 64KB, the address field is aligned to 64KB. Hence
* the lowest bits [15:0] are ignored. For instance, if the address is defined
* at 0x0800FFFF, the protection unit would apply its protection settings from
* 0x08000000. Thus alignment must be checked before defining the protection
* address. The address field for other PPUs are not used, as they are bound
* to their respective peripheral memory locations.
* - Region Size: For MPU, SMPU and PROG PPU, the region size is used to define
* the memory block size to apply the protection settings, starting from the
* defined base address. It is also used to define the 8 sub-regions for the
* chosen memory block. E.g. If the region size is 64KB, each subregion would
* be 8KB. This information can then be used to disable the protection
* settings for select subregions, which gives finer granularity to the
* memory regions. PPUs do not have region size definitions as they are bound
* to their respective peripheral memory locations.
* - Subregions: The memory block defined by the address and region size fields
* is divided into 8 (0 to 7) equally spaced subregions. The protection settings
* of the protection unit can be disabled for these subregions. E.g. for a
* given 64KB of memory block starting from address 0x08000000, disabling
* subregion 0 would result in the protection settings not affecting the memory
* located between 0x08000000 to 0x08001FFF. PPUs do not have subregion
* definitions as they are bound to their respective peripheral memory locations.
*
* \subsubsection group_prot_slave_attr Slave Struct Attribute Definition
*
* - User Permission: Protection units can control the access restrictions
* of the read (R), write (W) and execute (X) (subject to their availability
* depending on the type of protection unit) operations on the memory block
* when the bus master is operating in user mode. PPU structs do not provide
* execute attributes.
* - Privileged Permission: Similar to the user permission, protection units can
* control the access restrictions of the read (R), write (W) and execute (X)
* (subject to their availability depending on the type of protection unit)
* operations on the memory block when the bus master is operating in
* privileged mode. PPU structs do not provide execute attributes.
* - Secure/Non-secure: Applies the secure/non-secure protection settings to
* the defined memory region. Secure protection allows only bus masters that
* access the memory with secure attribute. Non-secure protection allows
* bus masters that have either secure or non-secure attributes.
* - PC match: This attribute allows the protection unit to either apply the
* 3 access evaluations (user/privileged, secure/non-secure, protection context)
* or to only provide an address range match. This is useful when multiple
* protection units protect an overlapping memory region and it's desirable
* to only have access evaluations applied from only one of these protection
* units. For example, SMPU1 protects memory A and SMPU2 protects memory B.
* There exists a region where A and B intersect and this is accessed by a
* bus master. Both SMPU1 and SMPU2 are configured to operate in "match" mode.
* In this scenario, the access evaluation will only be applied by the higher
* index protection unit (i.e. SMPU2) and the access attributes of SMPU1 will
* be ignored. If the bus master then tries to access a memory region A (that
* does not intersect with B), the access evaluation from SMPU1 will be used.
* Note that the PC match functionality is only available in SMPUs.
* - PC mask: Defines the allowed protection context values that can access the
* protected memory. The bus master attribute must be operating in one of the
* protection context values allowed by the protection unit. E.g. If SMPU1 is
* configured to allow only PC=1 and PC=5, a bus master (such as CM4) must
* be operating at PC=1 or PC=5 when accessing the protected memory region.
*
* \subsection group_prot_master_struct Master Struct
*
* The master struct protects its slave struct in the protection unit. This
* architecture makes possible for the slave configuration to be protected from
* reconfiguration by an unauthorized bus master. The configuration attributes
* and the format are similar to that of the slave structs.
*
* \subsubsection group_prot_master_addr Master Struct Address Definition
*
* - Address: The address definition for master struct is fixed to the slave
* struct that it protects.
* - Region Size: The region size is fixed to 256B region.
* - Subregion: This value is fixed to only enable the first 64B subregions,
* which applies the protection settings to the entire protection unit.
*
* \subsubsection group_prot_master_attr Master Struct Attribute Definition
*
* - User Permission: Only the write (W) access attribute is allowed for
* master structs, which controls whether a bus master operating in user
* mode has the write access.
* - Privileged Permission: Only the write (W) access attribute is allowed for
* master structs, which controls whether a bus master operating in privileged
* mode has the write access.
* - Secure/Non-Secure: Same behavior as slave struct.
* - PC match: Same behavior as slave struct.
* - PC mask: Same behavior as slave struct.
*
* \section group_prot_driver_usage Driver Usage
*
* Setting up and using protection units can be summed up in four stages:
*
* - Configure the bus master attributes. This defines the capabilities of
* the bus master when trying to access the protected resources.
* - Configure the slave struct of a given protection unit. This defines
* the protection attributes to be applied to the bus master accessing
* the protected resource and also defines the size and location of the
* memory block to protect.
* - Configure the master struct of the protection unit. This defines the
* attributes to be checked against the bus master that is trying to
* reconfigure the slave struct.
* - Set the active PC value of the bus master and place it in the correct
* mode of operation (user/privileged, secure/non-secure). Then access
* the protected memory.
*
* For example, by configuring the CM0+ bus master configuration to allow
* only protection contexts 2 and 3, the bus master will be able to
* set its protection context only to 2 or 3. During runtime, the CM0+ core
* can set its protection context to 2 by calling Cy_Prot_SetActivePC()
* and access all regions of protected memory that allow PC=2. A fault will
* be triggered if a resource is protected with different protection settings.
*
* Note that each protection unit is distinguished by its type (e.g.
* PROT_MPU_MPU_STRUCT_Type). The list of supported protection units can be
* obtained from the device definition header file. Choose a protection unit
* of interest, and call its corresponding Cy_Prot_Config<X>Struct() function
* with its software protection unit configuration structure populated. Then
* enable the protection unit by calling the Cy_Prot_Enable<X>Struct() function.
*
* Note that the bus master ID (en_prot_master_t) is defined in the device
* config header file.
*
* \section group_prot_configuration Configuration Considerations
*
* When a resource (memory/register) is accessed, it must pass evaluation of
* all three protection unit categories in the following order: MPU->SMPU->PPU.
* The application should ensure that a denial-of-service attack cannot be
* made on the PPU by the SMPU. For this reason, it is recommended that the
* application's security policy limit the ability for the non-secure client
* from configuring the SMPUs.
*
* Within each category, the priority hierarchy must be carefully considered
* to ensure that a higher priority protection unit cannot be configured to
* override the security configuration of a lower index protection unit.
* Therefore if a lower index protection unit is configured, relevant higher
* priority indexes should be configured (or protected from unwanted
* reconfiguration). E.g. If a PPU_SL is configured, PPU_RG and PPU_GR that
* overlaps with the protected registers should also be configured. SImilar
* to SMPUs, it is recommended that the configuration of PPU_PROG be limited.
* Otherwise they can be used to override the protection settings of PPU_RG
* and PPU_SL structs.
*
* All bus masters are set to PC=0 value at device reset and therefore have full
* access to all resources. It is up to the security solution to implement
* what privileges each bus master has. Once transitioned to a PC!=0 value,
* only the CM0+ core is capable of re-entering the PC=0 via the user-defined
* exception entry in the CPUSS.CM0_PC0_HANDLER register.
*
* - SMPU 15 and 14 are configured and enabled to only allow PC=0 accesses at
* device boot.
* - PROG PPU 15, 14, 13 and 12 are configured to only allow PC=0 accesses at
* device boot.
* - GR PPU 0 and 2 are configured to only allow PC=0 accesses at device boot.
*
* \section group_prot_more_information More Information
*
* Refer to Technical Reference Manual (TRM) and the device datasheet.
*
* \section group_prot_MISRA MISRA-C Compliance]
* The Prot driver does not have any driver-specific deviations.
*
* \section group_prot_changelog Changelog
* <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr>
* <td rowspan="2">1.10</td>
* <td>Added input parameter validation to the API functions.<br>
* cy_en_prot_pcmask_t, cy_en_prot_subreg_t and cy_en_prot_pc_t
* types are set to typedef enum</td>
* <td>Improved debugging capability</td>
* </tr>
* <tr>
* <td>Expanded documentation</td>
* <td></td>
* </tr>
* <tr>
* <td>1.0</td>
* <td>Initial version</td>
* <td></td>
* </tr>
* </table>
*
* \defgroup group_prot_macros Macros
* \defgroup group_prot_functions Functions
* \{
* \defgroup group_prot_functions_busmaster Bus Master and PC Functions
* \defgroup group_prot_functions_mpu MPU Functions
* \defgroup group_prot_functions_smpu SMPU Functions
* \defgroup group_prot_functions_ppu_prog PPU Programmable (PROG) Functions
* \defgroup group_prot_functions_ppu_gr PPU Group (GR) Functions
* \defgroup group_prot_functions_ppu_sl PPU Slave (SL) Functions
* \defgroup group_prot_functions_ppu_rg PPU Region (RG) Functions
* \}
* \defgroup group_prot_data_structures Data Structures
* \defgroup group_prot_enums Enumerated Types
*/
#if !defined(__CY_PROT_H__)
#define __CY_PROT_H__
#include <stdbool.h>
#include <stddef.h>
#include "syslib/cy_syslib.h"
#include "cy_device_headers.h"
#if defined(__cplusplus)
extern "C" {
#endif
/** \addtogroup group_prot_macros
* \{
*/
/** Driver major version */
#define CY_PROT_DRV_VERSION_MAJOR 1
/** Driver minor version */
#define CY_PROT_DRV_VERSION_MINOR 10
/** Prot driver ID */
#define CY_PROT_ID CY_PDL_DRV_ID(0x30u)
/** \} group_prot_macros */
/**
* \addtogroup group_prot_enums
* \{
*/
/**
* Prot Driver error codes
*/
typedef enum
{
CY_PROT_SUCCESS = 0x00u, /**< Returned successful */
CY_PROT_BAD_PARAM = CY_PROT_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< Bad parameter was passed */
CY_PROT_FAILURE = CY_PROT_ID | CY_PDL_STATUS_ERROR | 0x03u /**< The resource is locked */
} cy_en_prot_status_t;
/**
* User/Privileged permission
*/
typedef enum
{
CY_PROT_PERM_DISABLED = 0x00u, /**< Read, Write and Execute disabled */
CY_PROT_PERM_R = 0x01u, /**< Read enabled */
CY_PROT_PERM_W = 0x02u, /**< Write enabled */
CY_PROT_PERM_RW = 0x03u, /**< Read and Write enabled */
CY_PROT_PERM_X = 0x04u, /**< Execute enabled */
CY_PROT_PERM_RX = 0x05u, /**< Read and Execute enabled */
CY_PROT_PERM_WX = 0x06u, /**< Write and Execute enabled */
CY_PROT_PERM_RWX = 0x07u /**< Read, Write and Execute enabled */
}cy_en_prot_perm_t;
/**
* Memory region size
*/
typedef enum
{
CY_PROT_SIZE_256B = 7u, /**< 256 bytes */
CY_PROT_SIZE_512B = 8u, /**< 512 bytes */
CY_PROT_SIZE_1KB = 9u, /**< 1 Kilobyte */
CY_PROT_SIZE_2KB = 10u, /**< 2 Kilobytes */
CY_PROT_SIZE_4KB = 11u, /**< 4 Kilobytes */
CY_PROT_SIZE_8KB = 12u, /**< 8 Kilobytes */
CY_PROT_SIZE_16KB = 13u, /**< 16 Kilobytes */
CY_PROT_SIZE_32KB = 14u, /**< 32 Kilobytes */
CY_PROT_SIZE_64KB = 15u, /**< 64 Kilobytes */
CY_PROT_SIZE_128KB = 16u, /**< 128 Kilobytes */
CY_PROT_SIZE_256KB = 17u, /**< 256 Kilobytes */
CY_PROT_SIZE_512KB = 18u, /**< 512 Kilobytes */
CY_PROT_SIZE_1MB = 19u, /**< 1 Megabyte */
CY_PROT_SIZE_2MB = 20u, /**< 2 Megabytes */
CY_PROT_SIZE_4MB = 21u, /**< 4 Megabytes */
CY_PROT_SIZE_8MB = 22u, /**< 8 Megabytes */
CY_PROT_SIZE_16MB = 23u, /**< 16 Megabytes */
CY_PROT_SIZE_32MB = 24u, /**< 32 Megabytes */
CY_PROT_SIZE_64MB = 25u, /**< 64 Megabytes */
CY_PROT_SIZE_128MB = 26u, /**< 128 Megabytes */
CY_PROT_SIZE_256MB = 27u, /**< 256 Megabytes */
CY_PROT_SIZE_512MB = 28u, /**< 512 Megabytes */
CY_PROT_SIZE_1GB = 29u, /**< 1 Gigabyte */
CY_PROT_SIZE_2GB = 30u, /**< 2 Gigabytes */
CY_PROT_SIZE_4GB = 31u /**< 4 Gigabytes */
}cy_en_prot_size_t;
/**
* Protection Context (PC)
*/
enum cy_en_prot_pc_t
{
CY_PROT_PC1 = 1u, /**< PC = 1 */
CY_PROT_PC2 = 2u, /**< PC = 2 */
CY_PROT_PC3 = 3u, /**< PC = 3 */
CY_PROT_PC4 = 4u, /**< PC = 4 */
CY_PROT_PC5 = 5u, /**< PC = 5 */
CY_PROT_PC6 = 6u, /**< PC = 6 */
CY_PROT_PC7 = 7u, /**< PC = 7 */
CY_PROT_PC8 = 8u, /**< PC = 8 */
CY_PROT_PC9 = 9u, /**< PC = 9 */
CY_PROT_PC10 = 10u, /**< PC = 10 */
CY_PROT_PC11 = 11u, /**< PC = 11 */
CY_PROT_PC12 = 12u, /**< PC = 12 */
CY_PROT_PC13 = 13u, /**< PC = 13 */
CY_PROT_PC14 = 14u, /**< PC = 14 */
CY_PROT_PC15 = 15u /**< PC = 15 */
};
/**
* Subregion disable (0-7)
*/
enum cy_en_prot_subreg_t
{
CY_PROT_SUBREGION_DIS0 = 0x01u, /**< Disable subregion 0 */
CY_PROT_SUBREGION_DIS1 = 0x02u, /**< Disable subregion 1 */
CY_PROT_SUBREGION_DIS2 = 0x04u, /**< Disable subregion 2 */
CY_PROT_SUBREGION_DIS3 = 0x08u, /**< Disable subregion 3 */
CY_PROT_SUBREGION_DIS4 = 0x10u, /**< Disable subregion 4 */
CY_PROT_SUBREGION_DIS5 = 0x20u, /**< Disable subregion 5 */
CY_PROT_SUBREGION_DIS6 = 0x40u, /**< Disable subregion 6 */
CY_PROT_SUBREGION_DIS7 = 0x80u /**< Disable subregion 7 */
};
/**
* Protection context mask (PC_MASK)
*/
enum cy_en_prot_pcmask_t
{
CY_PROT_PCMASK1 = 0x0001u, /**< Mask to allow PC = 1 */
CY_PROT_PCMASK2 = 0x0002u, /**< Mask to allow PC = 2 */
CY_PROT_PCMASK3 = 0x0004u, /**< Mask to allow PC = 3 */
CY_PROT_PCMASK4 = 0x0008u, /**< Mask to allow PC = 4 */
CY_PROT_PCMASK5 = 0x0010u, /**< Mask to allow PC = 5 */
CY_PROT_PCMASK6 = 0x0020u, /**< Mask to allow PC = 6 */
CY_PROT_PCMASK7 = 0x0040u, /**< Mask to allow PC = 7 */
CY_PROT_PCMASK8 = 0x0080u, /**< Mask to allow PC = 8 */
CY_PROT_PCMASK9 = 0x0100u, /**< Mask to allow PC = 9 */
CY_PROT_PCMASK10 = 0x0200u, /**< Mask to allow PC = 10 */
CY_PROT_PCMASK11 = 0x0400u, /**< Mask to allow PC = 11 */
CY_PROT_PCMASK12 = 0x0800u, /**< Mask to allow PC = 12 */
CY_PROT_PCMASK13 = 0x1000u, /**< Mask to allow PC = 13 */
CY_PROT_PCMASK14 = 0x2000u, /**< Mask to allow PC = 14 */
CY_PROT_PCMASK15 = 0x4000u /**< Mask to allow PC = 15 */
};
/** \} group_prot_enums */
/***************************************
* Constants
***************************************/
/** \cond INTERNAL */
/* Helper function for finding max */
#define CY_PROT_MAX(x,y) (((x)>(y))?(x):(y))
/* General Masks and shifts */
#define CY_PROT_MSX_CTL_SHIFT (0x02UL) /**< Shift for MSx_CTL register */
#define CY_PROT_STRUCT_ENABLE (0x01UL) /**< Enable protection unit struct */
#define CY_PROT_ADDR_SHIFT (8UL) /**< Address shift for MPU, SMPU and PROG PPU structs */
/* Permission masks and shifts */
#define CY_PROT_ATT_PERMISSION_MASK (0x07UL) /**< Protection Unit attribute permission mask */
#define CY_PROT_ATT_USER_PERMISSION_SHIFT (0x00UL) /**< Protection Unit user attribute permission shift */
#define CY_PROT_ATT_PRIV_PERMISSION_SHIFT (0x03UL) /**< Protection Unit priliged attribute permission shift */
/* Maximum Master Protection Context */
#define CY_PROT_MS_PC_NR_MAX CY_PROT_MAX(CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1, \
CY_PROT_MAX(CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1, \
CY_PROT_MAX(CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1, \
CY_PROT_MAX(CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1, \
CY_PROT_MAX(CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1, \
CY_PROT_MAX(CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1, \
CY_PROT_MAX(CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1, \
CY_PROT_MAX(CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1, \
CY_PROT_MAX(CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1, \
CY_PROT_MAX(CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1, \
CY_PROT_MAX(CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1, \
CY_PROT_MAX(CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1, \
CY_PROT_MAX(CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1, \
CY_PROT_MAX(CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1, \
CY_PROT_MAX(CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1, \
CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1)))))))))))))))
/* Protection Context limit masks */
#define CY_PROT_MS0_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1)
#define CY_PROT_MS1_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1)
#define CY_PROT_MS2_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1)
#define CY_PROT_MS3_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1)
#define CY_PROT_MS4_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1)
#define CY_PROT_MS5_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1)
#define CY_PROT_MS6_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1)
#define CY_PROT_MS7_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1)
#define CY_PROT_MS8_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1)
#define CY_PROT_MS9_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1)
#define CY_PROT_MS10_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1)
#define CY_PROT_MS11_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1)
#define CY_PROT_MS12_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1)
#define CY_PROT_MS13_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1)
#define CY_PROT_MS14_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1)
#define CY_PROT_MS15_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1)
#define CY_PROT_MPU_PC_LIMIT_MASK (0xFFFFFFFFUL << CY_PROT_MS_PC_NR_MAX)
#define CY_PROT_SMPU_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_SMPU_STRUCT_PC_NR_MINUS1)
#define CY_PROT_PPU_PROG_PC_LIMIT_MASK (0xFFFFFFFFUL << PERI_PPU_PROG_STRUCT_PC_NR_MINUS1)
#define CY_PROT_PPU_FIXED_PC_LIMIT_MASK (0xFFFFFFFFUL << PERI_PPU_FIXED_STRUCT_PC_NR_MINUS1)
/* Parameter validation masks to check for read-only values */
#define CY_PROT_SMPU_ATT0_MASK ((uint32_t)~(PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Msk))
#define CY_PROT_SMPU_ATT1_MASK ((uint32_t)~(PROT_SMPU_SMPU_STRUCT_ATT1_UX_Msk \
| PROT_SMPU_SMPU_STRUCT_ATT1_PX_Msk \
| PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Msk \
| PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Msk \
))
#define CY_PROT_PPU_PROG_ATT0_MASK ((uint32_t)~(PERI_PPU_PR_ATT0_UX_Msk \
| PERI_PPU_PR_ATT0_PX_Msk \
| PERI_PPU_PR_ATT0_PC_MASK_0_Msk \
))
#define CY_PROT_PPU_PROG_ATT1_MASK ((uint32_t)~(PERI_PPU_PR_ATT1_UX_Msk \
| PERI_PPU_PR_ATT1_PX_Msk \
| PERI_PPU_PR_ATT1_PC_MASK_0_Msk \
| PERI_PPU_PR_ATT1_REGION_SIZE_Msk \
))
#define CY_PROT_PPU_GR_ATT0_MASK ((uint32_t)~(PERI_PPU_GR_ATT0_UX_Msk \
| PERI_PPU_GR_ATT0_PX_Msk \
| PERI_PPU_GR_ATT0_PC_MASK_0_Msk \
| PERI_PPU_GR_ATT0_REGION_SIZE_Msk \
))
#define CY_PROT_PPU_GR_ATT1_MASK ((uint32_t)~(PERI_PPU_GR_ATT1_UX_Msk \
| PERI_PPU_GR_ATT1_PX_Msk \
| PERI_PPU_GR_ATT1_PC_MASK_0_Msk \
| PERI_PPU_GR_ATT1_REGION_SIZE_Msk \
))
#define CY_PROT_PPU_SL_ATT0_MASK ((uint32_t)~(PERI_PPU_GR_ATT0_UX_Msk \
| PERI_PPU_GR_ATT0_PX_Msk \
| PERI_PPU_GR_ATT0_PC_MASK_0_Msk \
| PERI_PPU_GR_ATT0_REGION_SIZE_Msk \
))
#define CY_PROT_PPU_SL_ATT1_MASK ((uint32_t)~(PERI_PPU_GR_ATT1_UX_Msk \
| PERI_PPU_GR_ATT1_PX_Msk \
| PERI_PPU_GR_ATT1_PC_MASK_0_Msk \
| PERI_PPU_GR_ATT1_REGION_SIZE_Msk \
))
#define CY_PROT_PPU_RG_ATT0_MASK ((uint32_t)~(PERI_PPU_GR_ATT0_UX_Msk \
| PERI_PPU_GR_ATT0_PX_Msk \
| PERI_PPU_GR_ATT0_PC_MASK_0_Msk \
| PERI_PPU_GR_ATT0_REGION_SIZE_Msk \
))
#define CY_PROT_PPU_RG_ATT1_MASK ((uint32_t)~(PERI_PPU_GR_ATT1_UX_Msk \
| PERI_PPU_GR_ATT1_PX_Msk \
| PERI_PPU_GR_ATT1_PC_MASK_0_Msk \
| PERI_PPU_GR_ATT1_REGION_SIZE_Msk \
))
/* Parameter check macros */
#define CY_PROT_BUS_MASTER_MAX (16UL)
#define CY_PROT_IS_BUS_MASTER_VALID(busMaster) (CY_PROT_BUS_MASTER_MAX > ((uint32_t)(busMaster)))
#define CY_PROT_IS_MPU_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
((permission) == CY_PROT_PERM_R) || \
((permission) == CY_PROT_PERM_W) || \
((permission) == CY_PROT_PERM_RW) || \
((permission) == CY_PROT_PERM_X) || \
((permission) == CY_PROT_PERM_RX) || \
((permission) == CY_PROT_PERM_WX) || \
((permission) == CY_PROT_PERM_RWX))
#define CY_PROT_IS_SMPU_MS_PERM_VALID(permission) (((permission) == CY_PROT_PERM_R) || \
((permission) == CY_PROT_PERM_RW))
#define CY_PROT_IS_SMPU_SL_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
((permission) == CY_PROT_PERM_R) || \
((permission) == CY_PROT_PERM_W) || \
((permission) == CY_PROT_PERM_RW) || \
((permission) == CY_PROT_PERM_X) || \
((permission) == CY_PROT_PERM_RX) || \
((permission) == CY_PROT_PERM_WX) || \
((permission) == CY_PROT_PERM_RWX))
#define CY_PROT_IS_PROG_MS_PERM_VALID(permission) (((permission) == CY_PROT_PERM_R) || \
((permission) == CY_PROT_PERM_RW))
#define CY_PROT_IS_PROG_SL_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
((permission) == CY_PROT_PERM_R) || \
((permission) == CY_PROT_PERM_W) || \
((permission) == CY_PROT_PERM_RW))
#define CY_PROT_IS_FIXED_MS_PERM_VALID(permission) (((permission) == CY_PROT_PERM_R) || \
((permission) == CY_PROT_PERM_RW))
#define CY_PROT_IS_FIXED_SL_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
((permission) == CY_PROT_PERM_R) || \
((permission) == CY_PROT_PERM_W) || \
((permission) == CY_PROT_PERM_RW))
#define CY_PROT_IS_REGION_SIZE_VALID(regionSize) (((regionSize) == CY_PROT_SIZE_256B) || \
((regionSize) == CY_PROT_SIZE_512B) || \
((regionSize) == CY_PROT_SIZE_1KB) || \
((regionSize) == CY_PROT_SIZE_2KB) || \
((regionSize) == CY_PROT_SIZE_4KB) || \
((regionSize) == CY_PROT_SIZE_8KB) || \
((regionSize) == CY_PROT_SIZE_16KB) || \
((regionSize) == CY_PROT_SIZE_32KB) || \
((regionSize) == CY_PROT_SIZE_64KB) || \
((regionSize) == CY_PROT_SIZE_128KB) || \
((regionSize) == CY_PROT_SIZE_256KB) || \
((regionSize) == CY_PROT_SIZE_512KB) || \
((regionSize) == CY_PROT_SIZE_1MB) || \
((regionSize) == CY_PROT_SIZE_2MB) || \
((regionSize) == CY_PROT_SIZE_4MB) || \
((regionSize) == CY_PROT_SIZE_8MB) || \
((regionSize) == CY_PROT_SIZE_16MB) || \
((regionSize) == CY_PROT_SIZE_32MB) || \
((regionSize) == CY_PROT_SIZE_64MB) || \
((regionSize) == CY_PROT_SIZE_128MB) || \
((regionSize) == CY_PROT_SIZE_256MB) || \
((regionSize) == CY_PROT_SIZE_512MB) || \
((regionSize) == CY_PROT_SIZE_1GB) || \
((regionSize) == CY_PROT_SIZE_2GB) || \
((regionSize) == CY_PROT_SIZE_4GB))
/** \endcond */
/***************************************
* Configuration Structures
***************************************/
/**
* \addtogroup group_prot_data_structures
* \{
*/
/** Configuration structure for MPU Struct initialization */
typedef struct
{
uint32_t* address; /**< Base address of the memory region */
cy_en_prot_size_t regionSize; /**< Size of the memory region */
uint8_t subregions; /**< Mask of the 8 subregions to disable */
cy_en_prot_perm_t userPermission; /**< User permissions for the region */
cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
bool secure; /**< Non Secure = 0, Secure = 1 */
} cy_stc_mpu_cfg_t;
/** Configuration structure for SMPU struct initialization */
typedef struct
{
uint32_t* address; /**< Base address of the memory region (Only applicable to slave) */
cy_en_prot_size_t regionSize; /**< Size of the memory region (Only applicable to slave) */
uint8_t subregions; /**< Mask of the 8 subregions to disable (Only applicable to slave) */
cy_en_prot_perm_t userPermission; /**< User permissions for the region */
cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
bool secure; /**< Non Secure = 0, Secure = 1 */
bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
uint16_t pcMask; /**< Mask of allowed protection context(s) */
} cy_stc_smpu_cfg_t;
/** Configuration structure for Programmable (PROG) PPU (PPU_PR) struct initialization */
typedef struct
{
uint32_t* address; /**< Base address of the memory region (Only applicable to slave) */
cy_en_prot_size_t regionSize; /**< Size of the memory region (Only applicable to slave) */
uint8_t subregions; /**< Mask of the 8 subregions to disable (Only applicable to slave) */
cy_en_prot_perm_t userPermission; /**< User permissions for the region */
cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
bool secure; /**< Non Secure = 0, Secure = 1 */
bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
uint16_t pcMask; /**< Mask of allowed protection context(s) */
} cy_stc_ppu_prog_cfg_t;
/** Configuration structure for Fixed Group (GR) PPU (PPU_GR) struct initialization */
typedef struct
{
cy_en_prot_perm_t userPermission; /**< User permissions for the region */
cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
bool secure; /**< Non Secure = 0, Secure = 1 */
bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
uint16_t pcMask; /**< Mask of allowed protection context(s) */
} cy_stc_ppu_gr_cfg_t;
/** Configuration structure for Fixed Slave (SL) PPU (PPU_SL) struct initialization */
typedef struct
{
cy_en_prot_perm_t userPermission; /**< User permissions for the region */
cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
bool secure; /**< Non Secure = 0, Secure = 1 */
bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
uint16_t pcMask; /**< Mask of allowed protection context(s) */
} cy_stc_ppu_sl_cfg_t;
/** Configuration structure for Fixed Region (RG) PPU (PPU_RG) struct initialization */
typedef struct
{
cy_en_prot_perm_t userPermission; /**< User permissions for the region */
cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
bool secure; /**< Non Secure = 0, Secure = 1 */
bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
uint16_t pcMask; /**< Mask of allowed protection context(s) */
} cy_stc_ppu_rg_cfg_t;
/** \} group_prot_data_structures */
/***************************************
* Function Prototypes
***************************************/
/**
* \addtogroup group_prot_functions
* \{
*/
/**
* \addtogroup group_prot_functions_busmaster
* \{
*/
cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool privileged, bool secure, uint32_t pcMask);
cy_en_prot_status_t Cy_Prot_SetActivePC(en_prot_master_t busMaster, uint32_t pc);
uint32_t Cy_Prot_GetActivePC(en_prot_master_t busMaster);
/** \} group_prot_functions_busmaster */
/**
* \addtogroup group_prot_functions_mpu
* \{
*/
cy_en_prot_status_t Cy_Prot_ConfigMpuStruct(PROT_MPU_MPU_STRUCT_Type* base, const cy_stc_mpu_cfg_t* config);
cy_en_prot_status_t Cy_Prot_EnableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base);
cy_en_prot_status_t Cy_Prot_DisableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base);
/** \} group_prot_functions_mpu */
/**
* \addtogroup group_prot_functions_smpu
* \{
*/
cy_en_prot_status_t Cy_Prot_ConfigSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config);
cy_en_prot_status_t Cy_Prot_ConfigSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config);
cy_en_prot_status_t Cy_Prot_EnableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
cy_en_prot_status_t Cy_Prot_DisableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
cy_en_prot_status_t Cy_Prot_EnableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
cy_en_prot_status_t Cy_Prot_DisableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
/** \} group_prot_functions_smpu */
/**
* \addtogroup group_prot_functions_ppu_prog
* \{
*/
cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config);
cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config);
cy_en_prot_status_t Cy_Prot_EnablePpuProgMasterStruct(PERI_PPU_PR_Type* base);
cy_en_prot_status_t Cy_Prot_DisablePpuProgMasterStruct(PERI_PPU_PR_Type* base);
cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveStruct(PERI_PPU_PR_Type* base);
cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveStruct(PERI_PPU_PR_Type* base);
/** \} group_prot_functions_ppu_prog */
/**
* \addtogroup group_prot_functions_ppu_gr
* \{
*/
cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrMasterStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config);
cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config);
cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base);
cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base);
cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base);
cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base);
/** \} group_prot_functions_ppu_gr */
/**
* \addtogroup group_prot_functions_ppu_sl
* \{
*/
cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config);
cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config);
cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base);
cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base);
cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base);
cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base);
/** \} group_prot_functions_ppu_sl */
/**
* \addtogroup group_prot_functions_ppu_rg
* \{
*/
cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config);
cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config);
cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base);
cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base);
cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base);
cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base);
/** \} group_prot_functions_ppu_rg */
/** \} group_prot_functions */
/** \} group_prot */
#if defined(__cplusplus)
}
#endif
#endif /* CY_PROT_H */

43
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/rtc/cy_rtc.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/rtc/cy_rtc.c
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_rtc.c * \file cy_rtc.c
* \version 2.0 * \version 2.10
* *
* This file provides constants and parameter values for the APIs for the * This file provides constants and parameter values for the APIs for the
* Real-Time Clock (RTC). * Real-Time Clock (RTC).
* *
******************************************************************************** ********************************************************************************
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -523,7 +523,7 @@ cy_en_rtc_status_t Cy_RTC_SetDateAndTimeDirect(uint32_t sec, uint32_t min, uint3
curTimeAndDate.amPm = CY_RTC_AM; curTimeAndDate.amPm = CY_RTC_AM;
} }
} }
curTimeAndDate.dayOfWeek = Cy_RTC_ConvertDayOfWeek(date, month, year); curTimeAndDate.dayOfWeek = Cy_RTC_ConvertDayOfWeek(date, month, (year + CY_RTC_TWO_THOUSAND_YEARS));
curTimeAndDate.date = date; curTimeAndDate.date = date;
curTimeAndDate.month = month; curTimeAndDate.month = month;
curTimeAndDate.year = year; curTimeAndDate.year = year;
@ -772,41 +772,47 @@ cy_en_rtc_status_t Cy_RTC_SetHoursFormat(cy_en_rtc_hours_format_t hoursFormat)
* Function Name: Cy_RTC_SelectFrequencyPrescaler() * Function Name: Cy_RTC_SelectFrequencyPrescaler()
****************************************************************************//** ****************************************************************************//**
* *
* Selects the RTC pre-scaler value and changes its clock frequency. Under * Selects the RTC pre-scaler value and changes its clock frequency.
* condition that the external 32.768 kHz WCO is absent on the board, the RTC can * If the external 32.768 kHz WCO is absent on the board, the RTC can
* be driven by 32.768kHz square clock source or an external 50-Hz or 60-Hz * be driven by a 32.768kHz square clock source or an external 50-Hz or 60-Hz
* sine-wave clock source, for example the wall AC frequency. * sine-wave clock source, for example the wall AC frequency.
* *
* \param clkSel clock frequency, see \ref cy_en_rtc_clock_freq_t. * \param clkSel clock frequency, see \ref cy_en_rtc_clock_freq_t.
* *
* In addition to generating the 32.768 kHz clock from external crystals, the WCO * In addition to generating the 32.768 kHz clock from external crystals, the WCO
* can be sourced by an external clock source (50 Hz or 60Hz), even the wall AC * can be sourced by an external clock source (50 Hz or 60Hz), even the wall AC
* frequency as a timebase, to drive the RTC using wco_out and wco_in pins. * frequency as a timebase. The API helps select between the RTC sources:
* The API helps select between the RTC sources: * * A 32.768 kHz digital clock source <br>
* * An 32.768 kHz digital clock source <br>
* * An external 50-Hz or 60-Hz sine-wave clock source * * An external 50-Hz or 60-Hz sine-wave clock source
* *
* If you want to use an external 50-Hz or 60-Hz sine-wave clock source to * If you want to use an external 50-Hz or 60-Hz sine-wave clock source to
* drive the WCO, the next procedure is required: <br> * drive the RTC, the next procedure is required: <br>
* 1) Disable the WCO <br> * 1) Disable the WCO <br>
* 2) Drive the wco_out and wco_in pins to an external signal source* <br> * 2) Bypass the WCO using the Cy_SysClk_WcoBypass() function <br>
* 3) Call Cy_RTC_SelectFrequencyPrescaler(CY_RTC_FREQ_60_HZ) if you want to * 3) Configure both wco_out and wco_in pins. Note that only one of the wco pins
* drive the WCO, for example, with 60 Hz source <br> * should be driven and the other wco pin should be floating, which depends on
* 4) Enable the WCO <br> * the source that drives the RTC (*1) <br>
* 4) Call Cy_RTC_SelectFrequencyPrescaler(CY_RTC_FREQ_60_HZ), if you want to
* drive the WCO, for example, with a 60 Hz source <br>
* 5) Enable the WCO <br>
* *
* If you want to use the WCO after using an external 50-Hz or 60-Hz sine-wave * If you want to use the WCO after using an external 50-Hz or 60-Hz sine-wave
* clock source: <br> * clock source: <br>
* 1) Disable the WCO <br> * 1) Disable the WCO <br>
* 2) Drive off wco_out and wco_in pins with external signal source <br> * 2) Switch-off the WCO bypass using the Cy_SysClk_WcoBypass() function <br>
* 3) Call Cy_RTC_SelectFrequencyPrescaler(CY_RTC_FREQ_WCO_32768_HZ) <br> * 3) Drive off the wco pin with an external signal source <br>
* 4) Enable the WCO <br> * 4) Call Cy_RTC_SelectFrequencyPrescaler(CY_RTC_FREQ_WCO_32768_HZ) <br>
* 5) Enable the WCO <br>
*
* (1) - Refer to the device TRM to know how to configure the wco pins properly
* and which wco pin should be driven/floating.
* *
* \warning * \warning
* There is a limitation to the external clock source frequencies. Only two * There is a limitation to the external clock source frequencies. Only two
* frequencies are allowed - 50 Hz or 60 Hz. Note that this limitation is related * frequencies are allowed - 50 Hz or 60 Hz. Note that this limitation is related
* to the RTC pre-scaling feature presented in this function. This * to the RTC pre-scaling feature presented in this function. This
* limitation is not related to WCO external clock sources which can drive the * limitation is not related to WCO external clock sources which can drive the
* WCO in the bypass mode. * WCO in Bypass mode.
* *
*******************************************************************************/ *******************************************************************************/
void Cy_RTC_SelectFrequencyPrescaler(cy_en_rtc_clock_freq_t clkSel) void Cy_RTC_SelectFrequencyPrescaler(cy_en_rtc_clock_freq_t clkSel)
@ -897,6 +903,7 @@ cy_en_rtc_status_t Cy_RTC_SetNextDstTime(cy_stc_rtc_dst_format_t const *nextDst)
dstAlarmTimeAndDate.minEn = CY_RTC_ALARM_ENABLE; dstAlarmTimeAndDate.minEn = CY_RTC_ALARM_ENABLE;
dstAlarmTimeAndDate.hour = nextDst->hour; dstAlarmTimeAndDate.hour = nextDst->hour;
dstAlarmTimeAndDate.hourEn = CY_RTC_ALARM_ENABLE; dstAlarmTimeAndDate.hourEn = CY_RTC_ALARM_ENABLE;
dstAlarmTimeAndDate.dayOfWeek = nextDst->dayOfWeek;
dstAlarmTimeAndDate.dayOfWeekEn = CY_RTC_ALARM_DISABLE; dstAlarmTimeAndDate.dayOfWeekEn = CY_RTC_ALARM_DISABLE;
/* Calculate a day-of-month value for the relative DST start structure */ /* Calculate a day-of-month value for the relative DST start structure */

58
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/rtc/cy_rtc.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/rtc/cy_rtc.h
View File

@ -1,13 +1,13 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_rtc.h * \file cy_rtc.h
* \version 2.0 * \version 2.10
* *
* This file provides constants and parameter values for the APIs for the * This file provides constants and parameter values for the APIs for the
* Real-Time Clock (RTC). * Real-Time Clock (RTC).
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -59,20 +59,20 @@
* therefore can run without vddd/vccd present. This can be used to wake the chip * therefore can run without vddd/vccd present. This can be used to wake the chip
* from Hibernate mode. * from Hibernate mode.
* *
* * The Internal Low-speed Oscillator (ILO) routed from LFClk or directly * * The Internal Low-speed Oscillator (ILO) routed from Clk_LF or directly
* (as alternate backup domain clock source). Depending on the device power * (as alternate backup domain clock source). Depending on the device power
* mode the alternate backup domain clock source is set. For example, for * mode the alternate backup domain clock source is set. For example, for
* DeepSleep mode the ILO is routed through LFClk. But for Hibernate * DeepSleep mode the ILO is routed through Clk_LF. But for Hibernate
* power mode the ILO is set directly. Note that, the ILO should be configured to * power mode the ILO is set directly. Note that, the ILO should be configured to
* work in the Hibernate mode. For more info refer to the System Clock * work in the Hibernate mode. For more info refer to the \ref group_sysclk
* (sysclk) driver. The ILO is a low-accuracy RC-oscillator that does not require * driver. The ILO is a low-accuracy RC-oscillator that does not require
* any external elements on the board. Its poor accuracy (+/- 30%) means it is * any external elements on the board. Its poor accuracy (+/- 30%) means it is
* less useful for the RTC. However, current can be supplied by an internal * less useful for the RTC. However, current can be supplied by an internal
* power supply (Vback) and therefore it can run without Vddd/Vccd present. * power supply (Vback) and therefore it can run without Vddd/Vccd present.
* This also can be used to wake the chip from Hibernate mode using RTC alarm * This also can be used to wake the chip from Hibernate mode using RTC alarm
* interrupt. For more details refer to Power Modes (syspm) driver description. * interrupt. For more details refer to Power Modes (syspm) driver description.
* *
* * The Precision Internal Low-speed Oscillator (PILO), routed from LFClk * * The Precision Internal Low-speed Oscillator (PILO), routed from Clk_LF
* (alternate backup domain clock source). This is an RC-oscillator (ILO) that * (alternate backup domain clock source). This is an RC-oscillator (ILO) that
* can achieve accuracy of +/- 2% with periodic calibration. It is not expected * can achieve accuracy of +/- 2% with periodic calibration. It is not expected
* to be accurate enough for good RTC capability. The PILO requires * to be accurate enough for good RTC capability. The PILO requires
@ -88,11 +88,11 @@
* *
* The WCO is the recommended clock source for the RTC, if it is present * The WCO is the recommended clock source for the RTC, if it is present
* in design. For setting the Backup domain clock source, refer to the * in design. For setting the Backup domain clock source, refer to the
* System Clock (sysclk) driver. * \ref group_sysclk driver.
* *
* \note If the WCO is enabled, it should source the Backup domain directly. * \note If the WCO is enabled, it should source the Backup domain directly.
* Do not route the WCO through the LFClk. This is because LFClk is not available * Do not route the WCO through the Clk_LF. This is because Clk_LF is not
* in all low-power modes. * available in all low-power modes.
* *
* \section group_rtc_section_configuration Configuration Considerations * \section group_rtc_section_configuration Configuration Considerations
* *
@ -186,6 +186,17 @@
* *
* After the cy_stc_rtc_dst_t structure is filled, call Cy_RTC_EnableDstTime() * After the cy_stc_rtc_dst_t structure is filled, call Cy_RTC_EnableDstTime()
* *
* \section group_rtc_lp Low Power Support
* The RTC provides the callback functions to facilitate
* the low-power mode transition. The callback
* \ref Cy_RTC_DeepSleepCallback must be called during execution
* of \ref Cy_SysPm_DeepSleep; \ref Cy_RTC_HibernateCallback must be
* called during execution of \ref Cy_SysPm_Hibernate.
* To trigger the callback execution, the callback must be registered
* before calling the mode transition function.
* Refer to \ref group_syspm driver for more
* information about low-power mode transitions.
*
* \section group_rtc_section_more_information More Information * \section group_rtc_section_more_information More Information
* *
* For more information on the RTC peripheral, refer to the technical reference * For more information on the RTC peripheral, refer to the technical reference
@ -222,9 +233,15 @@
* <table class="doxtable"> * <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr> * <tr>
* <td>1.0</td> * <td>2.10</td>
* <td>Initial version</td> * <td> Corrected Cy_RTC_SetDateAndTimeDirect(), Cy_RTC_SetNextDstTime()
* <td></td> * function <br>
* Corrected internal macro <br>
* Documentation updates</td>
* <td> Incorrect behavior of \ref Cy_RTC_SetDateAndTimeDirect() and
* \ref Cy_RTC_SetNextDstTime() work in debug mode <br>
* Debug assert correction in \ref Cy_RTC_ConvertDayOfWeek,
* \ref Cy_RTC_IsLeapYear, \ref Cy_RTC_DaysInMonth </td>
* </tr> * </tr>
* <tr> * <tr>
* <td>2.0</td> * <td>2.0</td>
@ -237,6 +254,11 @@
* </td> * </td>
* <td></td> * <td></td>
* </tr> * </tr>
* <tr>
* <td>1.0</td>
* <td>Initial version</td>
* <td></td>
* </tr>
* </table> * </table>
* *
* \defgroup group_rtc_macros Macros * \defgroup group_rtc_macros Macros
@ -250,7 +272,7 @@
* \defgroup group_rtc_low_power_functions Low Power Callbacks * \defgroup group_rtc_low_power_functions Low Power Callbacks
* \} * \}
* \defgroup group_rtc_data_structures Data Structures * \defgroup group_rtc_data_structures Data Structures
* \defgroup group_rtc_enums Enumerated types * \defgroup group_rtc_enums Enumerated Types
*/ */
#if !defined (_CY_RTC_H_) #if !defined (_CY_RTC_H_)
@ -284,7 +306,7 @@ extern "C" {
#define CY_RTC_DRV_VERSION_MAJOR 2 #define CY_RTC_DRV_VERSION_MAJOR 2
/** Driver minor version */ /** Driver minor version */
#define CY_RTC_DRV_VERSION_MINOR 0 #define CY_RTC_DRV_VERSION_MINOR 10
/** \} group_rtc_macros */ /** \} group_rtc_macros */
/******************************************************************************* /*******************************************************************************
@ -782,7 +804,7 @@ extern uint8_t const cy_RTC_daysInMonthTbl[CY_RTC_MONTHS_PER_YEAR];
#define CY_RTC_IS_YEAR_SHORT_VALID(year) ((year) <= CY_RTC_MAX_YEAR) #define CY_RTC_IS_YEAR_SHORT_VALID(year) ((year) <= CY_RTC_MAX_YEAR)
/* Internal macro to validate the year value in the Cy_RTC_ConvertDayOfWeek() */ /* Internal macro to validate the year value in the Cy_RTC_ConvertDayOfWeek() */
#define CY_RTC_IS_YEAR_LONG_VALID(year) (((year) >= CY_RTC_TWO_THOUSAND_YEARS) || \ #define CY_RTC_IS_YEAR_LONG_VALID(year) (((year) >= CY_RTC_TWO_THOUSAND_YEARS) && \
((year) <= CY_RTC_TWENTY_ONE_HUNDRED_YEARS)) ((year) <= CY_RTC_TWENTY_ONE_HUNDRED_YEARS))
/* Internal macro to validate RTC alarm parameter */ /* Internal macro to validate RTC alarm parameter */
@ -884,7 +906,7 @@ __STATIC_INLINE uint32_t Cy_RTC_ConvertDayOfWeek(uint32_t day, uint32_t month, u
* function call. Leap year is identified as a year that is a multiple of 4 * function call. Leap year is identified as a year that is a multiple of 4
* or 400 but not 100. * or 400 but not 100.
* *
* \param year The year to be checked. * \param year The year to be checked. Valid range - 2000...2100.
* *
* \return * \return
* false - The year is not leap; true - The year is leap. * false - The year is not leap; true - The year is leap.
@ -910,7 +932,7 @@ __STATIC_INLINE bool Cy_RTC_IsLeapYear(uint32_t year)
* *
* \param month The month of the year, see \ref group_rtc_month. * \param month The month of the year, see \ref group_rtc_month.
* *
* \param year A year value. * \param year A year value. Valid range - 2000...2100.
* *
* \return A number of days in a month in the year passed through the parameters. * \return A number of days in a month in the year passed through the parameters.
* *

416
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/sar/cy_sar.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/sar/cy_sar.c
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_sar.c * \file cy_sar.c
* \version 1.0 * \version 1.10
* *
* Provides the public functions for the API for the SAR driver. * Provides the public functions for the API for the SAR driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -31,18 +31,23 @@ volatile int32_t Cy_SAR_countsPer10Volt[CY_SAR_MAX_NUM_CHANNELS];
****************************************************************************//** ****************************************************************************//**
* *
* Initialize all SAR configuration registers. * Initialize all SAR configuration registers.
* If the enable data field of the config structure is true, * If routing is to be configured, all switches will be cleared before
* a call to \ref Cy_SAR_Enable is made after all registers are initialized. * being initialized.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param config * \param config
* Pointer to structure containing configuration data. See \ref cy_stc_sar_config_t * Pointer to structure containing configuration data. See \ref cy_stc_sar_config_t
* and guidance in the \ref group_sar_initialization section.
* *
* \return cy_en_sar_status_t * \return
* - CY_SAR_SUCCESS: initialization complete * - \ref CY_SAR_SUCCESS : initialization complete
* - CY_SAR_BAD_PARAM: input pointers are null, initialization incomplete * - \ref CY_SAR_BAD_PARAM : input pointers are null, initialization incomplete
*
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_INIT_CUSTOM
* *
*******************************************************************************/ *******************************************************************************/
cy_en_sar_status_t Cy_SAR_Init(SAR_Type *base, const cy_stc_sar_config_t *config) cy_en_sar_status_t Cy_SAR_Init(SAR_Type *base, const cy_stc_sar_config_t *config)
@ -67,13 +72,12 @@ cy_en_sar_status_t Cy_SAR_Init(SAR_Type *base, const cy_stc_sar_config_t *config
CY_ASSERT_L2(CY_SAR_SAMPLE_CTRL(config->sampleCtrl)); CY_ASSERT_L2(CY_SAR_SAMPLE_CTRL(config->sampleCtrl));
CY_ASSERT_L2(CY_SAR_SAMPLE_TIME(config->sampleTime01)); CY_ASSERT_L2(CY_SAR_SAMPLE_TIME(config->sampleTime01));
CY_ASSERT_L2(CY_SAR_SAMPLE_TIME(config->sampleTime23)); CY_ASSERT_L2(CY_SAR_SAMPLE_TIME(config->sampleTime23));
CY_ASSERT_L3(CY_SAR_LIMITCOND(config->rangeCond)); CY_ASSERT_L3(CY_SAR_RANGECOND(config->rangeCond));
CY_ASSERT_L2(CY_SAR_CHANMASK(config->chanEn)); CY_ASSERT_L2(CY_SAR_CHANMASK(config->chanEn));
CY_ASSERT_L2(CY_SAR_INTRMASK(config->intrMask)); CY_ASSERT_L2(CY_SAR_INTRMASK(config->intrMask));
CY_ASSERT_L2(CY_SAR_CHANMASK(config->satIntrMask)); CY_ASSERT_L2(CY_SAR_CHANMASK(config->satIntrMask));
CY_ASSERT_L2(CY_SAR_CHANMASK(config->rangeIntrMask)); CY_ASSERT_L2(CY_SAR_CHANMASK(config->rangeIntrMask));
base->CTRL = (config->ctrl & ~SAR_CTRL_ENABLED_Msk);
base->SAMPLE_CTRL = config->sampleCtrl; base->SAMPLE_CTRL = config->sampleCtrl;
base->SAMPLE_TIME01 = config->sampleTime01; base->SAMPLE_TIME01 = config->sampleTime01;
base->SAMPLE_TIME23 = config->sampleTime23; base->SAMPLE_TIME23 = config->sampleTime23;
@ -119,17 +123,22 @@ cy_en_sar_status_t Cy_SAR_Init(SAR_Type *base, const cy_stc_sar_config_t *config
CY_ASSERT_L2(CY_SAR_SWITCHMASK(config->muxSwitch)); CY_ASSERT_L2(CY_SAR_SWITCHMASK(config->muxSwitch));
CY_ASSERT_L2(CY_SAR_SQMASK(config->muxSwitchSqCtrl)); CY_ASSERT_L2(CY_SAR_SQMASK(config->muxSwitchSqCtrl));
/* Clear out all the switches so that only the desired switches in the config structure are set. */
base->MUX_SWITCH_CLEAR0 = CY_SAR_CLEAR_ALL_SWITCHES;
base->MUX_SWITCH0 = config->muxSwitch; base->MUX_SWITCH0 = config->muxSwitch;
base->MUX_SWITCH_SQ_CTRL = config->muxSwitchSqCtrl; base->MUX_SWITCH_SQ_CTRL = config->muxSwitchSqCtrl;
} }
/* Write to the CTRL register last so that if the enable bit is set, /* Set the Cap trim if it was trimmed out of range from sflash */
* it will be written last */ if ((CY_SAR_CAP_TRIM_MAX == base->ANA_TRIM0) || (CY_SAR_CAP_TRIM_MIN == base->ANA_TRIM0))
if (true == config->enable)
{ {
Cy_SAR_Enable(base); base->ANA_TRIM0 = CY_SAR_CAP_TRIM;
} }
/* Set the REFBUF_EN bit as this is required for proper operation. */
base->CTRL = config->ctrl | SAR_CTRL_REFBUF_EN_Msk;
result = CY_SAR_SUCCESS; result = CY_SAR_SUCCESS;
} }
@ -150,8 +159,13 @@ cy_en_sar_status_t Cy_SAR_Init(SAR_Type *base, const cy_stc_sar_config_t *config
* If true, all SARMUX switches are opened and switch control registers are reset * If true, all SARMUX switches are opened and switch control registers are reset
* to zero. If false, switch registers are untouched. * to zero. If false, switch registers are untouched.
* *
* \return cy_en_sar_status_t * \return
* CY_SAR_SUCCESS or CY_SAR_BAD_PARAM if input pointers are null * - \ref CY_SAR_SUCCESS : de-initialization complete
* - \ref CY_SAR_BAD_PARAM : input pointers are null, de-initialization incomplete
*
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_DEINIT
* *
*******************************************************************************/ *******************************************************************************/
cy_en_sar_status_t Cy_SAR_DeInit(SAR_Type *base, bool deInitRouting) cy_en_sar_status_t Cy_SAR_DeInit(SAR_Type *base, bool deInitRouting)
@ -197,7 +211,7 @@ cy_en_sar_status_t Cy_SAR_DeInit(SAR_Type *base, bool deInitRouting)
* Function Name: Cy_SAR_Enable * Function Name: Cy_SAR_Enable
****************************************************************************//** ****************************************************************************//**
* *
* Powers up the SAR ADC subsystem block. The hardware is ready to use * Power up the SAR ADC subsystem block. The hardware is ready to use
* after 2 us, which is included in this function. * after 2 us, which is included in this function.
* *
* \param base * \param base
@ -226,18 +240,23 @@ void Cy_SAR_Enable(SAR_Type *base)
* Function Name: Cy_SAR_Sleep * Function Name: Cy_SAR_Sleep
****************************************************************************//** ****************************************************************************//**
* *
* This is the preferred routine to prepare the hardware for sleep. * This is the preferred routine to prepare the hardware for Deep sleep.
* It will stop continuous conversions, if enabled. Once the SAR BUSY bit is low,
* the hardware block will be turned off. The reference buffer (REFBUF) will
* also be disabled.
* *
* Call this function before putting the device into Deep Sleep mode. * It will call \ref Cy_SAR_StopConvert to disable continuous conversions
* and wait for SAR conversions to stop before entering Deep Sleep.
* If the SARMUX is not configured for Deep Sleep operation, the entire SAR hardware
* block will be turned off.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \return None * \return None
* *
* \funcusage
*
* This function is used in the \ref Cy_SAR_DeepSleepCallback. There is no
* need to call this function directly.
*
*******************************************************************************/ *******************************************************************************/
void Cy_SAR_Sleep(SAR_Type *base) void Cy_SAR_Sleep(SAR_Type *base)
{ {
@ -261,7 +280,12 @@ void Cy_SAR_Sleep(SAR_Type *base)
/* Wait for SAR to stop conversions before entering low power */ /* Wait for SAR to stop conversions before entering low power */
} }
ctrlReg &= ~SAR_CTRL_ENABLED_Msk; /* Turn off the entire hardware block only if the SARMUX is not
* enabled for Deep Sleep operation. */
if (SAR_CTRL_DEEPSLEEP_ON_Msk != (ctrlReg & SAR_CTRL_DEEPSLEEP_ON_Msk))
{
base->CTRL &= ~SAR_CTRL_ENABLED_Msk;
}
} }
base->CTRL = ctrlReg; base->CTRL = ctrlReg;
@ -273,7 +297,7 @@ void Cy_SAR_Sleep(SAR_Type *base)
* *
* This is the preferred routine to restore the hardware to the state after calling * This is the preferred routine to restore the hardware to the state after calling
* \ref Cy_SAR_Sleep. Restoring the hardware involves re-enabling the hardware, * \ref Cy_SAR_Sleep. Restoring the hardware involves re-enabling the hardware,
* the reference buffer, and start continuous scanning if it was previously * the reference buffer, and continuous scanning if it was previously
* enabled before entering sleep. * enabled before entering sleep.
* *
* \param base * \param base
@ -285,6 +309,11 @@ void Cy_SAR_Sleep(SAR_Type *base)
* *
* \return None * \return None
* *
* \funcusage
*
* This function is used in the \ref Cy_SAR_DeepSleepCallback. There is no
* need to call this function directly.
*
*******************************************************************************/ *******************************************************************************/
void Cy_SAR_Wakeup(SAR_Type *base) void Cy_SAR_Wakeup(SAR_Type *base)
{ {
@ -318,6 +347,10 @@ void Cy_SAR_Wakeup(SAR_Type *base)
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_START_CONVERT
*
*******************************************************************************/ *******************************************************************************/
void Cy_SAR_StartConvert(SAR_Type *base, cy_en_sar_start_convert_sel_t startSelect) void Cy_SAR_StartConvert(SAR_Type *base, cy_en_sar_start_convert_sel_t startSelect)
{ {
@ -339,7 +372,7 @@ void Cy_SAR_StartConvert(SAR_Type *base, cy_en_sar_start_convert_sel_t startSele
* Function Name: Cy_SAR_StopConvert * Function Name: Cy_SAR_StopConvert
****************************************************************************//** ****************************************************************************//**
* *
* Stops continuous scanning of enabled channels. * Stop continuous scanning of enabled channels.
* If a conversion is currently executing, that conversion will complete, * If a conversion is currently executing, that conversion will complete,
* but no further conversions will occur until the next call to * but no further conversions will occur until the next call to
* \ref Cy_SAR_StartConvert or the next hardware trigger, if enabled. * \ref Cy_SAR_StartConvert or the next hardware trigger, if enabled.
@ -349,6 +382,10 @@ void Cy_SAR_StartConvert(SAR_Type *base, cy_en_sar_start_convert_sel_t startSele
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_STOP_CONVERT
*
*******************************************************************************/ *******************************************************************************/
void Cy_SAR_StopConvert(SAR_Type *base) void Cy_SAR_StopConvert(SAR_Type *base)
{ {
@ -362,13 +399,15 @@ void Cy_SAR_StopConvert(SAR_Type *base)
* Function Name: Cy_SAR_SetConvertMode * Function Name: Cy_SAR_SetConvertMode
****************************************************************************//** ****************************************************************************//**
* *
* Sets the mode in which conversions are triggered. This function does * Set the mode in which conversions are triggered. This function does
* not start any conversions; it only configures the mode for subsequent conversions. * not start any conversions; it only configures the mode for subsequent conversions.
*
* There are three modes: * There are three modes:
* - firmware only; hardware triggering is disabled * - firmware only; hardware triggering is disabled
* - firmware and edge sensitive hardware triggering * - firmware and edge sensitive hardware triggering
* - firmware and level sensitive hardware triggering * - firmware and level sensitive hardware triggering
* Notice that firmware triggering is always enabled. *
* Note that firmware triggering is always enabled.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
@ -378,6 +417,10 @@ void Cy_SAR_StopConvert(SAR_Type *base)
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm4.c SAR_SNIPPET_SET_CONVERT_MODE
*
*******************************************************************************/ *******************************************************************************/
void Cy_SAR_SetConvertMode(SAR_Type *base, cy_en_sar_sample_ctrl_trigger_mode_t mode) void Cy_SAR_SetConvertMode(SAR_Type *base, cy_en_sar_sample_ctrl_trigger_mode_t mode)
{ {
@ -393,7 +436,7 @@ void Cy_SAR_SetConvertMode(SAR_Type *base, cy_en_sar_sample_ctrl_trigger_mode_t
* Function Name: Cy_SAR_IsEndConversion * Function Name: Cy_SAR_IsEndConversion
****************************************************************************//** ****************************************************************************//**
* *
* Immediately returns the status of the conversion or does not return (blocking) * Immediately return the status of the conversion or does not return (blocking)
* until the conversion completes, depending on the retMode parameter. * until the conversion completes, depending on the retMode parameter.
* In blocking mode, there is a time out of about 10 seconds for a CPU speed of * In blocking mode, there is a time out of about 10 seconds for a CPU speed of
* 100 MHz. * 100 MHz.
@ -404,13 +447,18 @@ void Cy_SAR_SetConvertMode(SAR_Type *base, cy_en_sar_sample_ctrl_trigger_mode_t
* \param retMode * \param retMode
* A value of the enum \ref cy_en_sar_return_mode_t * A value of the enum \ref cy_en_sar_return_mode_t
* *
* \return cy_en_sar_status_t * \return
* - CY_SAR_SUCCESS: the last conversion is complete * - \ref CY_SAR_SUCCESS : the last conversion is complete
* - CY_SAR_CONVERSION_NOT_COMPLETE: the conversion has not completed * - \ref CY_SAR_CONVERSION_NOT_COMPLETE : the conversion has not completed
* - CY_SAR_TIMEOUT: the watchdog timer has expired in blocking mode * - \ref CY_SAR_TIMEOUT : the watchdog timer has expired in blocking mode
*
* \sideeffect
* This function reads the end of conversion status and clears it after.
*
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_IS_END_CONVERSION
* *
* \sideeffect This function reads the end of conversion status and clears
* it after.
*******************************************************************************/ *******************************************************************************/
cy_en_sar_status_t Cy_SAR_IsEndConversion(SAR_Type *base, cy_en_sar_return_mode_t retMode) cy_en_sar_status_t Cy_SAR_IsEndConversion(SAR_Type *base, cy_en_sar_return_mode_t retMode)
{ {
@ -459,7 +507,7 @@ cy_en_sar_status_t Cy_SAR_IsEndConversion(SAR_Type *base, cy_en_sar_return_mode_
* Function Name: Cy_SAR_IsChannelSigned * Function Name: Cy_SAR_IsChannelSigned
****************************************************************************//** ****************************************************************************//**
* *
* Returns true if channel result is configured for signed format, else false. * Return true if channel result is configured for signed format, else false.
* The formats for single-ended and differential channels are independent. * The formats for single-ended and differential channels are independent.
* This function will first check whether the channel is single-ended or differential. * This function will first check whether the channel is single-ended or differential.
* *
@ -467,11 +515,15 @@ cy_en_sar_status_t Cy_SAR_IsEndConversion(SAR_Type *base, cy_en_sar_return_mode_
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param chan * \param chan
* The channel to check, between 0 and CY_SAR_MAX_NUM_CHANNELS - 1 * The channel to check, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1
* *
* \return bool * \return
* If channel number is invalid, false is returned * If channel number is invalid, false is returned
* *
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_IS_CHANNEL_SIGNED
*
*******************************************************************************/ *******************************************************************************/
bool Cy_SAR_IsChannelSigned(const SAR_Type *base, uint32_t chan) bool Cy_SAR_IsChannelSigned(const SAR_Type *base, uint32_t chan)
{ {
@ -506,17 +558,21 @@ bool Cy_SAR_IsChannelSigned(const SAR_Type *base, uint32_t chan)
* Function Name: Cy_SAR_IsChannelSingleEnded * Function Name: Cy_SAR_IsChannelSingleEnded
****************************************************************************//** ****************************************************************************//**
* *
* Returns true if channel is single ended, else false * Return true if channel is single ended, else false
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param chan * \param chan
* The channel to check, between 0 and CY_SAR_MAX_NUM_CHANNELS - 1 * The channel to check, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1
* *
* \return bool * \return
* If channel number is invalid, false is returned * If channel number is invalid, false is returned
* *
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_IS_CHANNEL_SE
*
*******************************************************************************/ *******************************************************************************/
bool Cy_SAR_IsChannelSingleEnded(const SAR_Type *base, uint32_t chan) bool Cy_SAR_IsChannelSingleEnded(const SAR_Type *base, uint32_t chan)
{ {
@ -538,19 +594,23 @@ bool Cy_SAR_IsChannelSingleEnded(const SAR_Type *base, uint32_t chan)
* Function Name: Cy_SAR_GetResult16 * Function Name: Cy_SAR_GetResult16
****************************************************************************//** ****************************************************************************//**
* *
* Gets the data available in the channel result data register as a signed * Return the data available in the channel result data register as a signed
* 16-bit integer. * 16-bit integer.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param chan * \param chan
* The channel to read the result from, between 0 and CY_SAR_MAX_NUM_CHANNELS - 1 * The channel to read the result from, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1
* *
* \return int16_t * \return
* Data is returned as a signed 16-bit integer. * Data is returned as a signed 16-bit integer.
* If channel number is invalid, 0 is returned. * If channel number is invalid, 0 is returned.
* *
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_GET_RESULT16
*
*******************************************************************************/ *******************************************************************************/
int16_t Cy_SAR_GetResult16(const SAR_Type *base, uint32_t chan) int16_t Cy_SAR_GetResult16(const SAR_Type *base, uint32_t chan)
{ {
@ -570,19 +630,23 @@ int16_t Cy_SAR_GetResult16(const SAR_Type *base, uint32_t chan)
* Function Name: Cy_SAR_GetResult32 * Function Name: Cy_SAR_GetResult32
****************************************************************************//** ****************************************************************************//**
* *
* Gets the data available in the channel result data register as a signed * Return the data available in the channel result data register as a signed
* 32-bit integer. * 32-bit integer.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param chan * \param chan
* The channel to read the result from, between 0 and CY_SAR_MAX_NUM_CHANNELS - 1 * The channel to read the result from, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1
* *
* \return int16_t * \return
* Data is returned as a signed 32-bit integer. * Data is returned as a signed 32-bit integer.
* If channel number is invalid, 0 is returned. * If channel number is invalid, 0 is returned.
* *
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_GET_RESULT32
*
*******************************************************************************/ *******************************************************************************/
int32_t Cy_SAR_GetResult32(const SAR_Type *base, uint32_t chan) int32_t Cy_SAR_GetResult32(const SAR_Type *base, uint32_t chan)
{ {
@ -614,7 +678,7 @@ int32_t Cy_SAR_GetResult32(const SAR_Type *base, uint32_t chan)
* Function Name: Cy_SAR_SetLowLimit * Function Name: Cy_SAR_SetLowLimit
****************************************************************************//** ****************************************************************************//**
* *
* Sets the low threshold for range detection. The values are interpreted * Set the low threshold for range detection. The values are interpreted
* as signed or unsigned according to the channel configuration. Range * as signed or unsigned according to the channel configuration. Range
* detection is done on the value stored in the result register. That is, after * detection is done on the value stored in the result register. That is, after
* averaging, shifting sign extension, and left/right alignment. * averaging, shifting sign extension, and left/right alignment.
@ -627,10 +691,14 @@ int32_t Cy_SAR_GetResult32(const SAR_Type *base, uint32_t chan)
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_SET_LOWHIGH_LIMIT
*
*******************************************************************************/ *******************************************************************************/
void Cy_SAR_SetLowLimit(SAR_Type *base, uint32_t lowLimit) void Cy_SAR_SetLowLimit(SAR_Type *base, uint32_t lowLimit)
{ {
CY_ASSERT_L2(CY_SAR_LIMIT(lowLimit)); CY_ASSERT_L2(CY_SAR_RANGE_LIMIT(lowLimit));
uint32_t rangeThresReg; uint32_t rangeThresReg;
@ -644,7 +712,7 @@ void Cy_SAR_SetLowLimit(SAR_Type *base, uint32_t lowLimit)
* Function Name: Cy_SAR_SetHighLimit * Function Name: Cy_SAR_SetHighLimit
****************************************************************************//** ****************************************************************************//**
* *
* Sets the high threshold for range detection. The values are interpreted * Set the high threshold for range detection. The values are interpreted
* as signed or unsigned according to the channel configuration. Range * as signed or unsigned according to the channel configuration. Range
* detection is done on the value stored in the result register. That is, after * detection is done on the value stored in the result register. That is, after
* averaging, shifting sign extension, and left/right alignment. * averaging, shifting sign extension, and left/right alignment.
@ -657,10 +725,14 @@ void Cy_SAR_SetLowLimit(SAR_Type *base, uint32_t lowLimit)
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_SET_LOWHIGH_LIMIT
*
*******************************************************************************/ *******************************************************************************/
void Cy_SAR_SetHighLimit(SAR_Type *base, uint32_t highLimit) void Cy_SAR_SetHighLimit(SAR_Type *base, uint32_t highLimit)
{ {
CY_ASSERT_L2(CY_SAR_LIMIT(highLimit)); CY_ASSERT_L2(CY_SAR_RANGE_LIMIT(highLimit));
uint32_t rangeThresReg; uint32_t rangeThresReg;
@ -673,27 +745,26 @@ void Cy_SAR_SetHighLimit(SAR_Type *base, uint32_t highLimit)
* Function Name: Cy_SAR_SetOffset * Function Name: Cy_SAR_SetOffset
****************************************************************************//** ****************************************************************************//**
* *
* Sets the offset that is used by the functions \ref Cy_SAR_CountsTo_uVolts, * Override the channel offset stored in the \ref Cy_SAR_offset array
* \ref Cy_SAR_CountsTo_mVolts, and \ref Cy_SAR_CountsTo_Volts. * for the voltage conversion functions.
* *
* Offset is applied to counts before unit scaling and gain. All CountsTo_[mV, uV, V]olts() * Offset is applied to counts before unit scaling and gain.
* functions use the following equation:
* V = (Counts/AvgDivider - Offset)*TEN_VOLT/Gain
* See \ref Cy_SAR_CountsTo_Volts for more about this formula. * See \ref Cy_SAR_CountsTo_Volts for more about this formula.
* *
* To set channel 0's offset based on known V_offset_mV, use: * To change channel 0's offset based on a known V_offset_mV, use:
* Cy_SAR_SetOffset(0uL, -1 * V_offset_mV * (1uL << (Resolution - 1)) / V_ref_mV); *
* Cy_SAR_SetOffset(0uL, -1 * V_offset_mV * (1uL << Resolution) / (2 * V_ref_mV));
* *
* \param chan * \param chan
* The channel number, between 0 and CY_SAR_MAX_NUM_CHANNELS - 1. * The channel number, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1.
* *
* \param offset * \param offset
* This value is a measured value when the inputs are shorted or * The count value measured when the inputs are shorted or
* connected to the same input voltage. * connected to the same input voltage.
* *
* \return cy_en_sar_status_t * \return
* - CY_SAR_BAD_PARAM: channel number is equal to or greater than CY_SAR_MAX_NUM_CHANNELS * - \ref CY_SAR_SUCCESS : offset was set successfully
* - CY_SAR_SUCCESS: offset was set successfully * - \ref CY_SAR_BAD_PARAM : channel number is equal to or greater than \ref CY_SAR_MAX_NUM_CHANNELS
* *
*******************************************************************************/ *******************************************************************************/
cy_en_sar_status_t Cy_SAR_SetOffset(uint32_t chan, int16_t offset) cy_en_sar_status_t Cy_SAR_SetOffset(uint32_t chan, int16_t offset)
@ -715,25 +786,26 @@ cy_en_sar_status_t Cy_SAR_SetOffset(uint32_t chan, int16_t offset)
* Function Name: Cy_SAR_SetGain * Function Name: Cy_SAR_SetGain
****************************************************************************//** ****************************************************************************//**
* *
* Sets the gain in counts per 10 volt for the voltage conversion functions. * Override the gain stored in the \ref Cy_SAR_countsPer10Volt array for the voltage conversion functions.
* This value is set by default by the reference and * The gain is configured at initialization in \ref Cy_SAR_Init
* input range settings. Gain is applied after offset and unit scaling. All * based on the SARADC resolution and voltage reference.
* CountsTo_[mV, uV, V]olts() functions use the following equation: *
* V = (Counts/AvgDivider - Offset)*TEN_VOLT/Gain * Gain is applied after offset and unit scaling.
* See \ref Cy_SAR_CountsTo_Volts for more about this formula. * See \ref Cy_SAR_CountsTo_Volts for more about this formula.
* *
* To set channel 0's gain based on known V_ref_mV, use: * To change channel 0's gain based on a known V_ref_mV, use:
* Cy_SAR_SetGain(0uL, 10000 * (1uL << (Resolution - 1)) / V_ref_mV); *
* Cy_SAR_SetGain(0uL, 10000 * (1uL << Resolution) / (2 * V_ref_mV));
* *
* \param chan * \param chan
* The channel number, between 0 and CY_SAR_MAX_NUM_CHANNELS - 1. * The channel number, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1.
* *
* \param adcGain * \param adcGain
* The gain in counts per 10 volt. * The gain in counts per 10 volt.
* *
* \return cy_en_sar_status_t * \return
* - CY_SAR_BAD_PARAM: channel number is equal to or greater than CY_SAR_MAX_NUM_CHANNELS * - \ref CY_SAR_SUCCESS : gain was set successfully
* - CY_SAR_SUCCESS: gain was set successfully * - \ref CY_SAR_BAD_PARAM : channel number is equal to or greater than \ref CY_SAR_MAX_NUM_CHANNELS
* *
*******************************************************************************/ *******************************************************************************/
cy_en_sar_status_t Cy_SAR_SetGain(uint32_t chan, int32_t adcGain) cy_en_sar_status_t Cy_SAR_SetGain(uint32_t chan, int32_t adcGain)
@ -755,16 +827,26 @@ cy_en_sar_status_t Cy_SAR_SetGain(uint32_t chan, int32_t adcGain)
* Function Name: Cy_SAR_RawCounts2Counts * Function Name: Cy_SAR_RawCounts2Counts
****************************************************************************//** ****************************************************************************//**
* *
* Converts the channel result to a consistent result after accounting for * Convert the channel result to a consistent result after accounting for
* averaging and subtracting the offset. * averaging and subtracting the offset.
* If using interleaved or sequential accumulate and dump, * The equation used is:
* the channel result will be divided by the averaging amount. *
* Counts = (RawCounts/AvgDivider - Offset)
*
* where,
* - RawCounts: Raw counts from SAR 16-bit CHAN_RESULT register
* - AvgDivider: divider based on averaging mode (\ref cy_en_sar_sample_ctrl_avg_mode_t) and number of samples averaged
* (\ref cy_en_sar_sample_ctrl_avg_cnt_t)
* - \ref CY_SAR_AVG_MODE_SEQUENTIAL_ACCUM : AvgDivider is the number of samples averaged or 16, whichever is smaller
* - \ref CY_SAR_AVG_MODE_SEQUENTIAL_FIXED : AvgDivider is 1
* - \ref CY_SAR_AVG_MODE_INTERLEAVED : AvgDivider is the number of samples averaged
* - Offset: Value from \ref Cy_SAR_offset
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param chan * \param chan
* The channel number, between 0 and CY_SAR_MAX_NUM_CHANNELS - 1 * The channel number, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1
* *
* \param adcCounts * \param adcCounts
* Conversion result from \ref Cy_SAR_GetResult16 * Conversion result from \ref Cy_SAR_GetResult16
@ -773,6 +855,12 @@ cy_en_sar_status_t Cy_SAR_SetGain(uint32_t chan, int32_t adcGain)
* adcCounts after averaging and offset adjustments. * adcCounts after averaging and offset adjustments.
* If channel number is invalid, adcCounts is returned unmodified. * If channel number is invalid, adcCounts is returned unmodified.
* *
* \funcusage
*
* This function is used by \ref Cy_SAR_CountsTo_Volts, \ref Cy_SAR_CountsTo_mVolts,
* and \ref Cy_SAR_CountsTo_uVolts. Calling this function directly is usually
* not needed.
*
*******************************************************************************/ *******************************************************************************/
int16_t Cy_SAR_RawCounts2Counts(const SAR_Type *base, uint32_t chan, int16_t adcCounts) int16_t Cy_SAR_RawCounts2Counts(const SAR_Type *base, uint32_t chan, int16_t adcCounts)
{ {
@ -829,37 +917,45 @@ int16_t Cy_SAR_RawCounts2Counts(const SAR_Type *base, uint32_t chan, int16_t adc
* Function Name: Cy_SAR_CountsTo_Volts * Function Name: Cy_SAR_CountsTo_Volts
****************************************************************************//** ****************************************************************************//**
* *
* Converts the ADC output to Volts as a float32. For example, if the ADC * Convert the ADC output to Volts as a float32. For example, if the ADC
* measured 0.534 volts, the return value would be 0.534. * measured 0.534 volts, the return value would be 0.534.
* The calculation of voltage depends on the contents of \ref Cy_SAR_offset, * The calculation of voltage depends on the contents of \ref Cy_SAR_offset,
* \ref Cy_SAR_countsPer10Volt, and other parameters. * \ref Cy_SAR_countsPer10Volt, and other parameters.
* The equation used is: * The equation used is:
* *
* V = (Counts/AvgDivider - Offset)*TEN_VOLT/Gain * V = (RawCounts/AvgDivider - Offset)*TEN_VOLT/Gain
* *
* -Counts = Raw Counts from SAR register * where,
* -AvgDivider = divider based on averaging mode * - RawCounts: Raw counts from SAR 16-bit CHAN_RESULT register
* -Sequential, Sum: AvgDivider = number averaged * - AvgDivider: divider based on averaging mode (\ref cy_en_sar_sample_ctrl_avg_mode_t) and number of samples averaged
* Note: The divider should be a maximum of 16. If using more averages, * (\ref cy_en_sar_sample_ctrl_avg_cnt_t)
* pre-scale Counts by (number averaged / 16) * - \ref CY_SAR_AVG_MODE_SEQUENTIAL_ACCUM : AvgDivider is the number of samples averaged or 16, whichever is smaller
* -Interleaved, Sum: AvgDivider = number averaged * - \ref CY_SAR_AVG_MODE_SEQUENTIAL_FIXED : AvgDivider is 1
* -Sequential, Fixed: AvgDivider = 1 * - \ref CY_SAR_AVG_MODE_INTERLEAVED : AvgDivider is the number of samples averaged
* -Offset = Value from \ref Cy_SAR_offset * - Offset: Value from \ref Cy_SAR_offset
* -TEN_VOLT = 10 V constant and unit scalar. * - TEN_VOLT: 10 V constant since the gain is in counts per 10 volts.
* -Gain = Value from \ref Cy_SAR_countsPer10Volt * - Gain: Value from \ref Cy_SAR_countsPer10Volt
*
* \note
* This funtion is only valid when result alignment is right aligned.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param chan * \param chan
* The channel number, between 0 and CY_SAR_MAX_NUM_CHANNELS - 1 * The channel number, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1
* *
* \param adcCounts * \param adcCounts
* Conversion result from \ref Cy_SAR_GetResult16 * Conversion result from \ref Cy_SAR_GetResult16
* *
* \return * \return
* Result in Volts. * Result in Volts.
* If channel number is invalid, 0 is returned. * - If channel number is invalid, 0 is returned.
* - If channel is left aligned, 0 is returned.
*
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_COUNTSTO_VOLTS
* *
*******************************************************************************/ *******************************************************************************/
float32_t Cy_SAR_CountsTo_Volts(const SAR_Type *base, uint32_t chan, int16_t adcCounts) float32_t Cy_SAR_CountsTo_Volts(const SAR_Type *base, uint32_t chan, int16_t adcCounts)
@ -886,37 +982,46 @@ float32_t Cy_SAR_CountsTo_Volts(const SAR_Type *base, uint32_t chan, int16_t adc
* Function Name: Cy_SAR_CountsTo_mVolts * Function Name: Cy_SAR_CountsTo_mVolts
****************************************************************************//** ****************************************************************************//**
* *
* Converts the ADC output to millivolts as an int16. For example, if the ADC * Convert the ADC output to millivolts as an int16. For example, if the ADC
* measured 0.534 volts, the return value would be 534. * measured 0.534 volts, the return value would be 534.
* The calculation of voltage depends on the contents of \ref Cy_SAR_offset, * The calculation of voltage depends on the contents of \ref Cy_SAR_offset,
* \ref Cy_SAR_countsPer10Volt, and other parameters. * \ref Cy_SAR_countsPer10Volt, and other parameters.
* The equation used is: * The equation used is:
* *
* V = (Counts/AvgDivider - Offset)*TEN_VOLT/Gain * V = (RawCounts/AvgDivider - Offset)*TEN_VOLT/Gain
* mV = V * 1000
* *
* -Counts = Raw Counts from SAR register * where,
* -AvgDivider = divider based on averaging mode * - RawCounts: Raw counts from SAR 16-bit CHAN_RESULT register
* -Sequential, Sum: AvgDivider = number averaged * - AvgDivider: divider based on averaging mode (\ref cy_en_sar_sample_ctrl_avg_mode_t) and number of samples averaged
* Note: The divider should be a maximum of 16. If using more averages, * (\ref cy_en_sar_sample_ctrl_avg_cnt_t)
* pre-scale Counts by (number averaged / 16) * - \ref CY_SAR_AVG_MODE_SEQUENTIAL_ACCUM : AvgDivider is the number of samples averaged or 16, whichever is smaller
* -Interleaved, Sum: AvgDivider = number averaged * - \ref CY_SAR_AVG_MODE_SEQUENTIAL_FIXED : AvgDivider is 1
* -Sequential, Fixed: AvgDivider = 1 * - \ref CY_SAR_AVG_MODE_INTERLEAVED : AvgDivider is the number of samples averaged
* -Offset = Value from \ref Cy_SAR_offset * - Offset: Value from \ref Cy_SAR_offset
* -TEN_VOLT = 10V constant and unit scalar * - TEN_VOLT: 10 V constant since the gain is in counts per 10 volts.
* -Gain = Value from \ref Cy_SAR_countsPer10Volt * - Gain: Value from \ref Cy_SAR_countsPer10Volt
*
* \note
* This funtion is only valid when result alignment is right aligned.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param chan * \param chan
* The channel number, between 0 and CY_SAR_MAX_NUM_CHANNELS - 1 * The channel number, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1
* *
* \param adcCounts * \param adcCounts
* Conversion result from \ref Cy_SAR_GetResult16 * Conversion result from \ref Cy_SAR_GetResult16
* *
* \return * \return
* Result in millivolts. * Result in millivolts.
* If channel number is invalid, 0 is returned. * - If channel number is invalid, 0 is returned.
* - If channel is left aligned, 0 is returned.
*
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_COUNTSTO_MVOLTS
* *
*******************************************************************************/ *******************************************************************************/
int16_t Cy_SAR_CountsTo_mVolts(const SAR_Type *base, uint32_t chan, int16_t adcCounts) int16_t Cy_SAR_CountsTo_mVolts(const SAR_Type *base, uint32_t chan, int16_t adcCounts)
@ -951,37 +1056,46 @@ int16_t Cy_SAR_CountsTo_mVolts(const SAR_Type *base, uint32_t chan, int16_t adcC
* Function Name: Cy_SAR_CountsTo_uVolts * Function Name: Cy_SAR_CountsTo_uVolts
****************************************************************************//** ****************************************************************************//**
* *
* Converts the ADC output to microvolts as a int32. For example, if the ADC * Convert the ADC output to microvolts as a int32. For example, if the ADC
* measured 0.534 volts, the return value would be 534000. * measured 0.534 volts, the return value would be 534000.
* The calculation of voltage depends on the contents of \ref Cy_SAR_offset, * The calculation of voltage depends on the contents of \ref Cy_SAR_offset,
* \ref Cy_SAR_countsPer10Volt, and other parameters. * \ref Cy_SAR_countsPer10Volt, and other parameters.
* The equation used is: * The equation used is:
* *
* V = (Counts/AvgDivider - Offset)*TEN_VOLT/Gain * V = (RawCounts/AvgDivider - Offset)*TEN_VOLT/Gain
* uV = V * 1000000
* *
* -Counts = Raw Counts from SAR register * where,
* -AvgDivider = divider based on averaging mode * - RawCounts: Raw counts from SAR 16-bit CHAN_RESULT register
* -Sequential, Sum: AvgDivider = number averaged * - AvgDivider: divider based on averaging mode (\ref cy_en_sar_sample_ctrl_avg_mode_t) and number of samples averaged
* Note: The divider should be a maximum of 16. If using more averages, * (\ref cy_en_sar_sample_ctrl_avg_cnt_t)
* pre-scale Counts by (number averaged / 16) * - \ref CY_SAR_AVG_MODE_SEQUENTIAL_ACCUM : AvgDivider is the number of samples averaged or 16, whichever is smaller
* -Interleaved, Sum: AvgDivider = number averaged * - \ref CY_SAR_AVG_MODE_SEQUENTIAL_FIXED : AvgDivider is 1
* -Sequential, Fixed: AvgDivider = 1 * - \ref CY_SAR_AVG_MODE_INTERLEAVED : AvgDivider is the number of samples averaged
* -Offset = Value from \ref Cy_SAR_offset * - Offset: Value from \ref Cy_SAR_offset
* -TEN_VOLT = 10V constant and unit scalar. * - TEN_VOLT: 10 V constant since the gain is in counts per 10 volts.
* -Gain = Value from \ref Cy_SAR_countsPer10Volt * - Gain: Value from \ref Cy_SAR_countsPer10Volt
*
* \note
* This funtion is only valid when result alignment is right aligned.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param chan * \param chan
* The channel number, between 0 and CY_SAR_MAX_NUM_CHANNELS - 1 * The channel number, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1
* *
* \param adcCounts * \param adcCounts
* Conversion result from \ref Cy_SAR_GetResult16 * Conversion result from \ref Cy_SAR_GetResult16
* *
* \return * \return
* Result in microvolts. * Result in microvolts.
* If channel number is valid, 0 is returned. * - If channel number is valid, 0 is returned.
* - If channel is left aligned, 0 is returned.
*
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_COUNTSTO_UVOLTS
* *
*******************************************************************************/ *******************************************************************************/
int32_t Cy_SAR_CountsTo_uVolts(const SAR_Type *base, uint32_t chan, int16_t adcCounts) int32_t Cy_SAR_CountsTo_uVolts(const SAR_Type *base, uint32_t chan, int16_t adcCounts)
@ -1007,32 +1121,33 @@ int32_t Cy_SAR_CountsTo_uVolts(const SAR_Type *base, uint32_t chan, int16_t adcC
* Function Name: Cy_SAR_SetAnalogSwitch * Function Name: Cy_SAR_SetAnalogSwitch
****************************************************************************//** ****************************************************************************//**
* *
* Provides firmware control of the SARMUX switches. Each call to this function * Provide firmware control of the SARMUX switches for firmware sequencing.
* can open a set of switches or close a set of switches. * Each call to this function can open or close a set of switches.
* Previously configured switches are untouched.
* *
* When the SAR sequencer is controlling the SARMUX switches, * If the SARSEQ is enabled, there is no need to use this function.
* there is no need to use this function.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param switchSelect * \param switchSelect
* A value of the enum \ref cy_en_sar_switch_register_sel_t to select the switch * The switch register that contains the desired switches. Select a value
* register * from \ref cy_en_sar_switch_register_sel_t.
* *
* \param switchMask * \param switchMask
* The mask of the switches to either open or close. * The mask of the switches to either open or close.
* The switches can be found in the \ref cy_en_sar_mux_switch_fw_ctrl_t enum. * Select one or more values from the \ref cy_en_sar_mux_switch_fw_ctrl_t enum
* * and "OR" them together.
* For example, to control the switch between SARMUX P0 and Vplus and the switch between SARMUX P1 and Vminus,
* call this function with:
* switchMask = CY_SAR_MUX_FW_P0_VPLUS | CY_SAR_MUX_FW_P1_VMINUS;
* *
* \param state * \param state
* A value of the enum \ref cy_en_sar_switch_state_t. * Open or close the desired swithces. Select a value from \ref cy_en_sar_switch_state_t.
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm4.c SAR_SNIPPET_SET_ANALOG_SWITCH
*
*******************************************************************************/ *******************************************************************************/
void Cy_SAR_SetAnalogSwitch(SAR_Type *base, cy_en_sar_switch_register_sel_t switchSelect, uint32_t switchMask, cy_en_sar_switch_state_t state) void Cy_SAR_SetAnalogSwitch(SAR_Type *base, cy_en_sar_switch_register_sel_t switchSelect, uint32_t switchMask, cy_en_sar_switch_state_t state)
{ {
@ -1060,7 +1175,7 @@ void Cy_SAR_SetAnalogSwitch(SAR_Type *base, cy_en_sar_switch_register_sel_t swit
case CY_SAR_SWITCH_OPEN: case CY_SAR_SWITCH_OPEN:
default: default:
/** Unlike the close case, we are not OR'ing the register. Set 1 to clear.*/ /* Unlike the close case, we are not OR'ing the register. Set 1 to clear.*/
*switchClearReg = switchMask; *switchClearReg = switchMask;
break; break;
} }
@ -1070,19 +1185,19 @@ void Cy_SAR_SetAnalogSwitch(SAR_Type *base, cy_en_sar_switch_register_sel_t swit
* Function Name: Cy_SAR_GetAnalogSwitch * Function Name: Cy_SAR_GetAnalogSwitch
****************************************************************************//** ****************************************************************************//**
* *
* Gets the state (open or close) of SARMUX switches as a uint32_t value. * Return the state (open or close) of SARMUX switches.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param switchSelect * \param switchSelect
* A value of the enum \ref cy_en_sar_switch_register_sel_t to select the switch * The switch register that contains the desired switches. Select a value
* register * from \ref cy_en_sar_switch_register_sel_t.
* *
* \return uint32_t * \return
* Each bit corresponds to a single switch, where a bit value of 0 is open * Each bit corresponds to a single switch, where a bit value of 0 is open
* and 1 is closed. * and 1 is closed.
* The switch masks can be found in the \ref cy_en_sar_mux_switch_fw_ctrl_t enum. * Compare this value to the switch masks in \ref cy_en_sar_mux_switch_fw_ctrl_t.
* *
*******************************************************************************/ *******************************************************************************/
uint32_t Cy_SAR_GetAnalogSwitch(const SAR_Type *base, cy_en_sar_switch_register_sel_t switchSelect) uint32_t Cy_SAR_GetAnalogSwitch(const SAR_Type *base, cy_en_sar_switch_register_sel_t switchSelect)
@ -1106,31 +1221,26 @@ uint32_t Cy_SAR_GetAnalogSwitch(const SAR_Type *base, cy_en_sar_switch_register_
* Function Name: Cy_SAR_SetSwitchSarSeqCtrl * Function Name: Cy_SAR_SetSwitchSarSeqCtrl
****************************************************************************//** ****************************************************************************//**
* *
* Sets which switches are controlled by the SAR sequencer. * Enable or disable SARSEQ control of one or more switches.
* Previously configured switches are untouched.
* *
* \param base * \param base
* Pointer to structure describing registers * Pointer to structure describing registers
* *
* \param switchMask * \param switchMask
* The mask of the switches. * The mask of the switches.
* The switches can be found in the \ref cy_en_sar_mux_switch_sq_ctrl_t enum. * Select one or more values from the \ref cy_en_sar_mux_switch_sq_ctrl_t enum
* For example, to give control of all SARMUX pin switches to the sequencer, * and "OR" them together.
* call this function with:
* switchMask = CY_SAR_MUX_SQ_CTRL_P0 | \
* CY_SAR_MUX_SQ_CTRL_P1 | \
* CY_SAR_MUX_SQ_CTRL_P2 | \
* CY_SAR_MUX_SQ_CTRL_P3 | \
* CY_SAR_MUX_SQ_CTRL_P4 | \
* CY_SAR_MUX_SQ_CTRL_P5 | \
* CY_SAR_MUX_SQ_CTRL_P6 | \
* CY_SAR_MUX_SQ_CTRL_P7;
* ctrl = CY_SAR_SWITCH_SEQ_CTRL_ENABLE;
* *
* \param ctrl * \param ctrl
* A value of the enum \ref cy_en_sar_switch_sar_seq_ctrl_t. * Enable or disable SARSEQ control. Select a value from \ref cy_en_sar_switch_sar_seq_ctrl_t.
* *
* \return None * \return None
* *
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm4.c SAR_SNIPPET_SET_SWITCH_SAR_SEQ_CTRL
*
*******************************************************************************/ *******************************************************************************/
void Cy_SAR_SetSwitchSarSeqCtrl(SAR_Type *base, uint32_t switchMask, cy_en_sar_switch_sar_seq_ctrl_t ctrl) void Cy_SAR_SetSwitchSarSeqCtrl(SAR_Type *base, uint32_t switchMask, cy_en_sar_switch_sar_seq_ctrl_t ctrl)
{ {
@ -1159,9 +1269,13 @@ void Cy_SAR_SetSwitchSarSeqCtrl(SAR_Type *base, uint32_t switchMask, cy_en_sar_s
* \param callbackParams * \param callbackParams
* Pointer to structure of type \ref cy_stc_syspm_callback_params_t * Pointer to structure of type \ref cy_stc_syspm_callback_params_t
* *
* \return cy_en_syspm_status_t * \return
* See \ref cy_en_syspm_status_t * See \ref cy_en_syspm_status_t
* *
* \funcusage
*
* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_DEEPSLEEP_CALLBACK
*
*******************************************************************************/ *******************************************************************************/
cy_en_syspm_status_t Cy_SAR_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams) cy_en_syspm_status_t Cy_SAR_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams)
{ {

1308
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/sar/cy_sar.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/sar/cy_sar.h
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File diff suppressed because it is too large Load Diff

30
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/scb/cy_scb_common.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_common.c
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_scb_common.c * \file cy_scb_common.c
* \version 2.0 * \version 2.10
* *
* Provides common API implementation of the SCB driver. * Provides common API implementation of the SCB driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -70,7 +70,7 @@ void Cy_SCB_ReadArrayNoCheck(CySCB_Type const *base, void *buffer, uint32_t size
****************************************************************************//** ****************************************************************************//**
* *
* Reads an array of data out of the SCB receive FIFO. * Reads an array of data out of the SCB receive FIFO.
* This function does not block, it returns how many data elements were * This function does not block; it returns how many data elements are
* read from the receive FIFO. * read from the receive FIFO.
* *
* \param base * \param base
@ -78,7 +78,7 @@ void Cy_SCB_ReadArrayNoCheck(CySCB_Type const *base, void *buffer, uint32_t size
* *
* \param buffer * \param buffer
* The pointer to location to place data read from receive FIFO. * The pointer to location to place data read from receive FIFO.
* The item size is defined by the data type which depends on the configured * The item size is defined by the data type, which depends on the configured
* data width. * data width.
* *
* \param size * \param size
@ -93,7 +93,7 @@ uint32_t Cy_SCB_ReadArray(CySCB_Type const *base, void *buffer, uint32_t size)
/* Get available items in RX FIFO */ /* Get available items in RX FIFO */
uint32_t numToCopy = Cy_SCB_GetNumInRxFifo(base); uint32_t numToCopy = Cy_SCB_GetNumInRxFifo(base);
/* Adjust items which will be read */ /* Adjust items that will be read */
if (numToCopy > size) if (numToCopy > size)
{ {
numToCopy = size; numToCopy = size;
@ -118,8 +118,8 @@ uint32_t Cy_SCB_ReadArray(CySCB_Type const *base, void *buffer, uint32_t size)
* The pointer to the SCB instance. * The pointer to the SCB instance.
* *
* \param buffer * \param buffer
* The pointer to location to place data read from receive FIFO. * The pointer to the location to place data read from the receive FIFO.
* The item size is defined by the data type which depends on the configured * The item size is defined by the data type, which depends on the configured
* data width. * data width.
* *
* \param size * \param size
@ -148,7 +148,7 @@ void Cy_SCB_ReadArrayBlocking(CySCB_Type const *base, void *buffer, uint32_t siz
****************************************************************************//** ****************************************************************************//**
* *
* Places a single data element in the SCB transmit FIFO. * Places a single data element in the SCB transmit FIFO.
* This function does not block and returns how many data elements were placed * This function does not block. It returns how many data elements are placed
* in the transmit FIFO. * in the transmit FIFO.
* *
* \param base * \param base
@ -156,7 +156,7 @@ void Cy_SCB_ReadArrayBlocking(CySCB_Type const *base, void *buffer, uint32_t siz
* *
* \param data * \param data
* Data to put in the transmit FIFO. * Data to put in the transmit FIFO.
* The item size is defined by the data type which depends on the configured * The item size is defined by the data type, which depends on the configured
* data width. * data width.
* *
* \return * \return
@ -182,7 +182,7 @@ uint32_t Cy_SCB_Write(CySCB_Type *base, uint32_t data)
* Function Name: Cy_SCB_WriteArrayNoCheck * Function Name: Cy_SCB_WriteArrayNoCheck
****************************************************************************//** ****************************************************************************//**
* *
* Places an array of data in the SCB transmit FIFO without checking if the * Places an array of data in the SCB transmit FIFO without checking whether the
* transmit FIFO has enough space. * transmit FIFO has enough space.
* Before calling this function, make sure that the transmit FIFO has enough * Before calling this function, make sure that the transmit FIFO has enough
* space to put all requested data elements. * space to put all requested data elements.
@ -192,7 +192,7 @@ uint32_t Cy_SCB_Write(CySCB_Type *base, uint32_t data)
* *
* \param buffer * \param buffer
* The pointer to data to place in the transmit FIFO. * The pointer to data to place in the transmit FIFO.
* The item size is defined by the data type which depends on the configured * The item size is defined by the data type, which depends on the configured
* TX data width. * TX data width.
* *
* \param size * \param size
@ -234,7 +234,7 @@ void Cy_SCB_WriteArrayNoCheck(CySCB_Type *base, void *buffer, uint32_t size)
****************************************************************************//** ****************************************************************************//**
* *
* Places an array of data in the SCB transmit FIFO. * Places an array of data in the SCB transmit FIFO.
* This function does not block and it returns how many data elements were * This function does not block. It returns how many data elements were
* placed in the transmit FIFO. * placed in the transmit FIFO.
* *
* \param base * \param base
@ -282,7 +282,7 @@ uint32_t Cy_SCB_WriteArray(CySCB_Type *base, void *buffer, uint32_t size)
* *
* \param buffer * \param buffer
* The pointer to data to place in transmit FIFO. * The pointer to data to place in transmit FIFO.
* The item size is defined by the data type which depends on the configured * The item size is defined by the data type, which depends on the configured
* data width. * data width.
* *
* \param size * \param size
@ -344,9 +344,9 @@ void Cy_SCB_WriteString(CySCB_Type *base, char_t const string[])
****************************************************************************//** ****************************************************************************//**
* *
* Places a number of the same data elements in the SCB transmit FIFO without * Places a number of the same data elements in the SCB transmit FIFO without
* checking if the transmit FIFO has enough space. The data elements is equal * checking whether the transmit FIFO has enough space. The data elements is equal
* to txData parameter. * to txData parameter.
* Before calling this function make sure that transmit FIFO has enough space * Before calling this function, make sure that transmit FIFO has enough space
* to put all requested data elements. * to put all requested data elements.
* *
* \param base * \param base

49
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/scb/cy_scb_common.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_common.h
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_scb_common.h * \file cy_scb_common.h
* \version 2.0 * \version 2.10
* *
* Provides common API declarations of the SCB driver. * Provides common API declarations of the SCB driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -67,6 +67,11 @@
* <table class="doxtable"> * <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr> * <tr>
* <td>2.10</td>
* <td>None.</td>
* <td>SCB I2C driver updated.</td>
* </tr>
* <tr>
* <td rowspan="2"> 2.0</td> * <td rowspan="2"> 2.0</td>
* <td>Added parameters validation for public API. * <td>Added parameters validation for public API.
* <td></td> * <td></td>
@ -212,7 +217,7 @@ __STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel (CySCB_Type const *base);
#define CY_SCB_DRV_VERSION_MAJOR (2) #define CY_SCB_DRV_VERSION_MAJOR (2)
/** Driver minor version */ /** Driver minor version */
#define CY_SCB_DRV_VERSION_MINOR (0) #define CY_SCB_DRV_VERSION_MINOR (10)
/** SCB driver identifier */ /** SCB driver identifier */
#define CY_SCB_ID CY_PDL_DRV_ID(0x2AU) #define CY_SCB_ID CY_PDL_DRV_ID(0x2AU)
@ -371,7 +376,7 @@ __STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel (CySCB_Type const *base);
* \defgroup group_scb_common_macros_master_intr Master Interrupt Statuses * \defgroup group_scb_common_macros_master_intr Master Interrupt Statuses
* \{ * \{
*/ */
/** The I2C master's lost arbitration */ /** The I2C master lost arbitration */
#define CY_SCB_MASTER_INTR_I2C_ARB_LOST SCB_INTR_M_I2C_ARB_LOST_Msk #define CY_SCB_MASTER_INTR_I2C_ARB_LOST SCB_INTR_M_I2C_ARB_LOST_Msk
/** The I2C master received a NACK */ /** The I2C master received a NACK */
@ -410,7 +415,7 @@ __STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel (CySCB_Type const *base);
* \{ * \{
*/ */
/** /**
* Wake up request: the SPI slave detected an active edge of the slave select * Wake up request: the SPI slave detects an active edge of the slave select
* signal. Note that this interrupt source triggers in active mode. * signal. Note that this interrupt source triggers in active mode.
*/ */
#define CY_SCB_SPI_INTR_WAKEUP SCB_INTR_SPI_EC_WAKE_UP_Msk #define CY_SCB_SPI_INTR_WAKEUP SCB_INTR_SPI_EC_WAKE_UP_Msk
@ -467,6 +472,12 @@ __STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel (CySCB_Type const *base);
#define CY_SCB_I2C_CTRL_MODE_Pos SCB_I2C_CTRL_SLAVE_MODE_Pos #define CY_SCB_I2C_CTRL_MODE_Pos SCB_I2C_CTRL_SLAVE_MODE_Pos
#define CY_SCB_I2C_CTRL_MODE_Msk (SCB_I2C_CTRL_SLAVE_MODE_Msk | \ #define CY_SCB_I2C_CTRL_MODE_Msk (SCB_I2C_CTRL_SLAVE_MODE_Msk | \
SCB_I2C_CTRL_MASTER_MODE_Msk) SCB_I2C_CTRL_MASTER_MODE_Msk)
/* Cypress ID #282226:
* SCB_I2C_CFG_SDA_IN_FILT_TRIM[1]: SCB clock enable (1), clock disable (0).
*/
#define CY_SCB_I2C_CFG_CLK_ENABLE_Msk (_VAL2FLD(SCB_I2C_CFG_SDA_IN_FILT_TRIM, 2UL))
/* I2C has fixed data width */ /* I2C has fixed data width */
#define CY_SCB_I2C_DATA_WIDTH (7UL) #define CY_SCB_I2C_DATA_WIDTH (7UL)
@ -561,7 +572,7 @@ __STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel (CySCB_Type const *base);
****************************************************************************//** ****************************************************************************//**
* *
* Reads a data element directly out of the RX FIFO. * Reads a data element directly out of the RX FIFO.
* This function does not check if the RX FIFO has data before reading it. * This function does not check whether the RX FIFO has data before reading it.
* *
* \param base * \param base
* The pointer to the SCB instance. * The pointer to the SCB instance.
@ -627,7 +638,7 @@ __STATIC_INLINE uint32_t Cy_SCB_GetNumInRxFifo(CySCB_Type const *base)
* The pointer to the SCB instance. * The pointer to the SCB instance.
* *
* \return * \return
* 1 - RX shift register valid, 0 - RX shift register not valid. * 1 - RX shift register valid; 0 - RX shift register not valid.
* *
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_SCB_GetRxSrValid(CySCB_Type const *base) __STATIC_INLINE uint32_t Cy_SCB_GetRxSrValid(CySCB_Type const *base)
@ -646,7 +657,7 @@ __STATIC_INLINE uint32_t Cy_SCB_GetRxSrValid(CySCB_Type const *base)
* The pointer to the SCB instance. * The pointer to the SCB instance.
* *
* \note * \note
* If there is partial data in the shifter, it gets cleared and lost. * If there is partial data in the shifter, it is cleared and lost.
* *
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE void Cy_SCB_ClearRxFifo(CySCB_Type* base) __STATIC_INLINE void Cy_SCB_ClearRxFifo(CySCB_Type* base)
@ -663,7 +674,7 @@ __STATIC_INLINE void Cy_SCB_ClearRxFifo(CySCB_Type* base)
****************************************************************************//** ****************************************************************************//**
* *
* Writes data directly into the TX FIFO. * Writes data directly into the TX FIFO.
* This function does not check if the TX FIFO is not full before writing * This function does not check whether the TX FIFO is not full before writing
* into it. * into it.
* *
* \param base * \param base
@ -683,7 +694,7 @@ __STATIC_INLINE void Cy_SCB_WriteTxFifo(CySCB_Type* base, uint32_t data)
* Function Name: Cy_SCB_SetTxFifoLevel * Function Name: Cy_SCB_SetTxFifoLevel
****************************************************************************//** ****************************************************************************//**
* *
* Sets the TX FIFO level, when there are fewer data elements in the TX FIFO than * Sets the TX FIFO level. When there are fewer data elements in the TX FIFO than
* this level, the TX FIFO level interrupt is triggered. * this level, the TX FIFO level interrupt is triggered.
* *
* \param base * \param base
@ -731,7 +742,7 @@ __STATIC_INLINE uint32_t Cy_SCB_GetNumInTxFifo(CySCB_Type const *base)
* The pointer to the SCB instance. * The pointer to the SCB instance.
* *
* \return * \return
* 1 - TX shift register valid, 0 - TX shift register not valid. * 1 - TX shift register valid; 0 - TX shift register not valid.
* *
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE uint32_t Cy_SCB_GetTxSrValid(CySCB_Type const *base) __STATIC_INLINE uint32_t Cy_SCB_GetTxSrValid(CySCB_Type const *base)
@ -744,7 +755,7 @@ __STATIC_INLINE uint32_t Cy_SCB_GetTxSrValid(CySCB_Type const *base)
* Function Name: Cy_SCB_IsTxComplete * Function Name: Cy_SCB_IsTxComplete
****************************************************************************//** ****************************************************************************//**
* *
* Checks if the TX FIFO and Shifter are empty and there is no more data to send. * Checks whether the TX FIFO and Shifter are empty and there is no more data to send.
* *
* \param base * \param base
* Pointer to SPI the SCB instance. * Pointer to SPI the SCB instance.
@ -769,8 +780,8 @@ __STATIC_INLINE bool Cy_SCB_IsTxComplete(CySCB_Type const *base)
* The pointer to the SCB instance. * The pointer to the SCB instance.
* *
* \note * \note
* The TX FIFO clear operation also clears the shift register, thus the shifter * The TX FIFO clear operation also clears the shift register. Thus the shifter
* could be cleared in the middle of a data element transfer; resulting in * could be cleared in the middle of a data element transfer. Thia results in
* "ones" being sent on the bus for the remainder of the transfer. * "ones" being sent on the bus for the remainder of the transfer.
* *
*******************************************************************************/ *******************************************************************************/
@ -789,7 +800,7 @@ __STATIC_INLINE void Cy_SCB_ClearTxFifo(CySCB_Type *base)
* *
* Sets whether the RX and TX FIFOs are in byte mode. * Sets whether the RX and TX FIFOs are in byte mode.
* The FIFOs are either 16-bit wide or 8-bit wide (byte mode). * The FIFOs are either 16-bit wide or 8-bit wide (byte mode).
* When the FIFO is in byte mode it is twice as deep, see device datasheet * When the FIFO is in byte mode it is twice as deep. See the device datasheet
* for FIFO depths. * for FIFO depths.
* *
* \param base * \param base
@ -1084,7 +1095,7 @@ __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatusMasked(CySCB_Type const *bas
* *
* \note * \note
* - CY_SCB_INTR_TX_FIFO_LEVEL interrupt source is not cleared when the * - CY_SCB_INTR_TX_FIFO_LEVEL interrupt source is not cleared when the
* TX FIFO has less entries than the TX level. * TX FIFO has fewer entries than the TX level.
* - CY_SCB_INTR_TX_NOT_FULL interrupt source is not cleared when the * - CY_SCB_INTR_TX_NOT_FULL interrupt source is not cleared when the
* TX FIFO has empty entries in the TX FIFO. * TX FIFO has empty entries in the TX FIFO.
* - CY_SCB_INTR_TX_EMPTY interrupt source is not cleared when the * - CY_SCB_INTR_TX_EMPTY interrupt source is not cleared when the
@ -1626,7 +1637,7 @@ __STATIC_INLINE void Cy_SCB_ClearSpiInterrupt(CySCB_Type *base, uint32_t interru
(void) base->INTR_SPI_EC; (void) base->INTR_SPI_EC;
} }
/** \cond INTERNAL */
/******************************************************************************* /*******************************************************************************
* Function Name: Cy_SCB_GetFifoSize * Function Name: Cy_SCB_GetFifoSize
****************************************************************************//** ****************************************************************************//**
@ -1676,7 +1687,7 @@ __STATIC_INLINE bool Cy_SCB_IsRxDataWidthByte(CySCB_Type const *base)
* The pointer to the SCB instance. * The pointer to the SCB instance.
* *
* \return * \return
* If ture, the TX data width is a byte (8 bits). Otherwise, false. * If true, the TX data width is a byte (8 bits). Otherwise, false.
* *
*******************************************************************************/ *******************************************************************************/
__STATIC_INLINE bool Cy_SCB_IsTxDataWidthByte(CySCB_Type const *base) __STATIC_INLINE bool Cy_SCB_IsTxDataWidthByte(CySCB_Type const *base)
@ -1728,6 +1739,8 @@ __STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel(CySCB_Type const *base)
{ {
return _FLD2VAL(SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, base->RX_FIFO_CTRL); return _FLD2VAL(SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, base->RX_FIFO_CTRL);
} }
/** \endcond */
/** \} group_scb_common_functions */ /** \} group_scb_common_functions */
#if defined(__cplusplus) #if defined(__cplusplus)

158
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/scb/cy_scb_ezi2c.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_ezi2c.c
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_scb_ezi2c.c * \file cy_scb_ezi2c.c
* \version 2.0 * \version 2.10
* *
* Provides EZI2C API implementation of the SCB driver. * Provides EZI2C API implementation of the SCB driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -47,7 +47,7 @@ static void UpdateAddressMask (CySCB_Type *base, cy_stc_scb_ezi2c_context_t cons
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t * The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
* allocated by the user. The structure is used during the EZI2C operation for * allocated by the user. The structure is used during the EZI2C operation for
* internal configuration and data keeping. The user must not modify anything * internal configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
* \return * \return
@ -61,7 +61,7 @@ cy_en_scb_ezi2c_status_t Cy_SCB_EZI2C_Init(CySCB_Type *base, cy_stc_scb_ezi2c_co
cy_stc_scb_ezi2c_context_t *context) cy_stc_scb_ezi2c_context_t *context)
{ {
/* Input parameters verification */ /* Input parameters verification */
if ((NULL == base) && (NULL == config) && (NULL == context)) if ((NULL == base) || (NULL == config) || (NULL == context))
{ {
return CY_SCB_EZI2C_BAD_PARAM; return CY_SCB_EZI2C_BAD_PARAM;
} }
@ -150,7 +150,7 @@ cy_en_scb_ezi2c_status_t Cy_SCB_EZI2C_Init(CySCB_Type *base, cy_stc_scb_ezi2c_co
*******************************************************************************/ *******************************************************************************/
void Cy_SCB_EZI2C_DeInit(CySCB_Type *base) void Cy_SCB_EZI2C_DeInit(CySCB_Type *base)
{ {
/* Returns the block registers into the default state */ /* Return the block registers into the default state */
base->CTRL = CY_SCB_CTRL_DEF_VAL; base->CTRL = CY_SCB_CTRL_DEF_VAL;
base->I2C_CTRL = CY_SCB_I2C_CTRL_DEF_VAL; base->I2C_CTRL = CY_SCB_I2C_CTRL_DEF_VAL;
@ -185,11 +185,11 @@ void Cy_SCB_EZI2C_DeInit(CySCB_Type *base)
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t * The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
* allocated by the user. The structure is used during the EZI2C operation for * allocated by the user. The structure is used during the EZI2C operation for
* internal configuration and data keeping. The user must not modify anything * internal configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
* \note * \note
* Calling this function when EZI2C is busy (the slave was addressed and is * Calling this function while EZI2C is busy (the slave has been addressed and is
* communicating with the master), may cause transaction corruption because * communicating with the master), may cause transaction corruption because
* the hardware stops driving the output and ignores the input. Ensure that * the hardware stops driving the output and ignores the input. Ensure that
* the EZI2C slave is not busy before calling this function. * the EZI2C slave is not busy before calling this function.
@ -210,37 +210,38 @@ void Cy_SCB_EZI2C_Disable(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context)
****************************************************************************//** ****************************************************************************//**
* *
* This function handles the transition of the EZI2C SCB into and out of * This function handles the transition of the EZI2C SCB into and out of
* Deep-Sleep mode. It prevents the device from entering Deep-Sleep mode * Deep Sleep mode. It prevents the device from entering Deep Sleep mode if
* if the EZI2C slave is actively communicating. * the EZI2C slave is actively communicating.
* The following behavior of the EZI2C depends on if the SCB block is * The following behavior of the EZI2C depends on whether the SCB block is
* wakeup-capable or not: * wakeup-capable:
* * The SCB wakeup-capable: on the incoming EZI2C slave address, the slave * * The SCB <b>wakeup-capable</b>: on the incoming EZI2C slave address, the slave
* receives address and stretches the clock until the device is awoken from * receives the address and stretches the clock until the device is woken from
* Deep-Sleep mode. If the slave address occurs before the device enters * Deep Sleep mode. If the slave address occurs before the device enters
* Deep-Sleep mode, the device will not enter Deep-Sleep mode. * Deep Sleep mode, the device will not enter Deep Sleep mode.
* * The SCB is not wakeup-capable: the EZI2C is disabled. It is enabled when * * The SCB is <b>not wakeup-capable</b>: the EZI2C is disabled. It is enabled
* the device failed to enter Deep-Sleep mode or it is awaken from Deep-Sleep * when the device fails to enter Deep Sleep mode or it is woken from Deep Sleep
* mode. During the EZI2C is disabled, it stops driving the outputs and * mode. While the EZI2C is disabled, it stops driving the outputs and
* ignores the input lines. The slave NACKs all incoming addresses. * ignores the input lines. The slave NACKs all incoming addresses.
* *
* This function can be called during execution of \ref Cy_SysPm_DeepSleep, * This function must be called during execution of \ref Cy_SysPm_DeepSleep.
* to do it, register this function as a callback before calling * To do this, register this function as a callback before calling
* \ref Cy_SysPm_DeepSleep : specify \ref CY_SYSPM_DEEPSLEEP as the callback * \ref Cy_SysPm_DeepSleep : specify \ref CY_SYSPM_DEEPSLEEP as the callback
* type and call \ref Cy_SysPm_RegisterCallback. * type and call \ref Cy_SysPm_RegisterCallback.
* *
* \param callbackParams * \param callbackParams
* The pointer to the callback parameters structure * The pointer to the callback parameters structure.
* \ref cy_stc_syspm_callback_params_t. * \ref cy_stc_syspm_callback_params_t.
* *
* \return * \return
* \ref cy_en_syspm_status_t * \ref cy_en_syspm_status_t
* *
* \warning * \note
* Only applicable for <b>rev-08 of the CY8CKIT-062-BLE</b>.
* For proper operation, when the EZI2C slave is configured to be a wakeup source * For proper operation, when the EZI2C slave is configured to be a wakeup source
* from Deep-Sleep mode, this function must be copied and modified by the user. * from Deep Sleep mode, this function must be copied and modified by the user.
* The EZI2C clock disable code must be inserted in the * The EZI2C clock disable code must be inserted in the
* \ref CY_SYSPM_BEFORE_TRANSITION and enable code in the \ref CY_SYSPM_AFTER_TRANSITION * \ref CY_SYSPM_BEFORE_TRANSITION and clock enable code in the
* mode processing. * \ref CY_SYSPM_AFTER_TRANSITION mode processing.
* *
*******************************************************************************/ *******************************************************************************/
cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams) cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams)
@ -257,8 +258,8 @@ cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params
/* Disable the slave interrupt sources to protect the state */ /* Disable the slave interrupt sources to protect the state */
Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_CLEAR_ALL_INTR_SRC); Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_CLEAR_ALL_INTR_SRC);
/* If the EZI2C is in the IDLE state, it is ready for Deep-Sleep /* If the EZI2C is in the IDLE state, it is ready for Deep Sleep
* mode, otherwise return fail and restore the slave interrupt * mode. Otherwise, it returns fail and restores the slave interrupt
* sources. * sources.
*/ */
if (CY_SCB_EZI2C_STATE_IDLE == locContext->state) if (CY_SCB_EZI2C_STATE_IDLE == locContext->state)
@ -267,7 +268,7 @@ cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params
{ {
/* The SCB is wakeup-capable: do not restore the address /* The SCB is wakeup-capable: do not restore the address
* match interrupt source. The next transaction intended * match interrupt source. The next transaction intended
* for the slave will be paused (SCL is stretched) before * for the slave will be paused (the SCL is stretched) before
* the address is ACKed because the corresponding interrupt * the address is ACKed because the corresponding interrupt
* source is disabled. * source is disabled.
*/ */
@ -277,8 +278,8 @@ cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params
{ {
/* The SCB is NOT wakeup-capable: disable the EZI2C. /* The SCB is NOT wakeup-capable: disable the EZI2C.
* The slave stops responding to the master until the * The slave stops responding to the master until the
* EZI2C is enabled. This happens when the device is failed * EZI2C is enabled. This happens when the device fails
* to enter Deep-Sleep mode or it is awaken from Deep-Sleep * to enter Deep Sleep mode or it is woken from Deep Sleep
* mode. * mode.
*/ */
Cy_SCB_EZI2C_Disable(locBase, locContext); Cy_SCB_EZI2C_Disable(locBase, locContext);
@ -297,20 +298,20 @@ cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params
case CY_SYSPM_CHECK_FAIL: case CY_SYSPM_CHECK_FAIL:
{ {
/* The other driver is not ready for Deep-Sleep mode. Restore /* The other driver is not ready for Deep Sleep mode. Restore
* Active mode configuration. * Active mode configuration.
*/ */
if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL)) if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL))
{ {
/* The SCB is wakeup-capable: restore the slave interrupt /* The SCB is wakeup-capable: restore the slave interrupt
* sources * sources.
*/ */
Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_EZI2C_SLAVE_INTR); Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_EZI2C_SLAVE_INTR);
} }
else else
{ {
/* The SCB is NOT wakeup-capable: enable the slave to operate */ /* The SCB is NOT wakeup-capable: enable the slave to operate. */
Cy_SCB_EZI2C_Enable(locBase); Cy_SCB_EZI2C_Enable(locBase);
} }
@ -331,16 +332,19 @@ cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params
{ {
/* The SCB is wakeup-capable: enable the I2C wakeup interrupt /* The SCB is wakeup-capable: enable the I2C wakeup interrupt
* source. If any transaction was paused the the EZI2C interrupt * source. If any transaction was paused the the EZI2C interrupt
* becomes pending and prevents entering Deep-Sleep mode. * becomes pending and prevents entering Deep Sleep mode.
* The transaction continues as soon as the global interrupts * The transaction continues as soon as the global interrupts
* are enabled. * are enabled.
*/ */
Cy_SCB_SetI2CInterruptMask(locBase, CY_SCB_I2C_INTR_WAKEUP); Cy_SCB_SetI2CInterruptMask(locBase, CY_SCB_I2C_INTR_WAKEUP);
/* IMPORTANT (insert code below): for proper entering Deep /* Disable SCB clock */
* Sleep the EZI2C clock must be disabled. This code must be locBase->I2C_CFG &= (uint32_t) ~CY_SCB_I2C_CFG_CLK_ENABLE_Msk;
* inserted by the user because the driver does not have access
* to the clock. /* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
* for proper entering Deep Sleep mode the I2C clock must be disabled.
* This code must be inserted by the user because the driver
* does not have access to the clock.
*/ */
} }
@ -352,10 +356,13 @@ cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params
{ {
if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL)) if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL))
{ {
/* IMPORTANT (insert code below): for proper exiting Deep /* Enable SCB clock */
* Sleep, the EZI2C clock must be enabled. This code must be locBase->I2C_CFG |= CY_SCB_I2C_CFG_CLK_ENABLE_Msk;
* inserted by the user because the driver does not have access
* to the clock. /* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
* for proper exiting Deep Sleep mode, the I2C clock must be enabled.
* This code must be inserted by the user because the driver
* does not have access to the clock.
*/ */
/* The SCB is wakeup-capable: disable the I2C wakeup interrupt /* The SCB is wakeup-capable: disable the I2C wakeup interrupt
@ -390,12 +397,12 @@ cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params
* mode. It prevents the device from entering Hibernate mode if the EZI2C slave * mode. It prevents the device from entering Hibernate mode if the EZI2C slave
* is actively communicating. * is actively communicating.
* If the EZI2C is ready to enter Hibernate mode, it is disabled. If the device * If the EZI2C is ready to enter Hibernate mode, it is disabled. If the device
* failed to enter Hibernate mode, the EZI2C is enabled. During the EZI2C * fails to enter Hibernate mode, the EZI2C is enabled. While the EZI2C
* is disabled, it does stops driving the output and ignores the inputs. * is disabled, it stops driving the output and ignores the inputs.
* The slave NACKs all incoming addresses. * The slave NACKs all incoming addresses.
* *
* This function can be called during execution of \ref Cy_SysPm_Hibernate, * This function must be called during execution of \ref Cy_SysPm_Hibernate.
* to do it, register this function as a callback before calling * To do this, register this function as a callback before calling
* \ref Cy_SysPm_Hibernate : specify \ref CY_SYSPM_HIBERNATE as the callback * \ref Cy_SysPm_Hibernate : specify \ref CY_SYSPM_HIBERNATE as the callback
* type and call \ref Cy_SysPm_RegisterCallback. * type and call \ref Cy_SysPm_RegisterCallback.
* *
@ -421,13 +428,13 @@ cy_en_syspm_status_t Cy_SCB_EZI2C_HibernateCallback(cy_stc_syspm_callback_params
/* Disable the slave interrupt sources to protect the state */ /* Disable the slave interrupt sources to protect the state */
Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_CLEAR_ALL_INTR_SRC); Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_CLEAR_ALL_INTR_SRC);
/* If the EZI2C is in the IDLE state, it is ready for Hibernate mode, /* If the EZI2C is in the IDLE state, it is ready for Hibernate mode.
* otherwise return fail and restore the slave interrupt sources. * Otherwise, returns fail and restores the slave interrupt sources.
*/ */
if (CY_SCB_EZI2C_STATE_IDLE == locContext->state) if (CY_SCB_EZI2C_STATE_IDLE == locContext->state)
{ {
/* Disable the EZI2C. It stops responding to the master until /* Disable the EZI2C. It stops responding to the master until
* the EZI2C is enabled. This happens if the device failed to * the EZI2C is enabled. This happens if the device fails to
* enter Hibernate mode. * enter Hibernate mode.
*/ */
Cy_SCB_EZI2C_Disable(locBase, locContext); Cy_SCB_EZI2C_Disable(locBase, locContext);
@ -483,7 +490,7 @@ cy_en_syspm_status_t Cy_SCB_EZI2C_HibernateCallback(cy_stc_syspm_callback_params
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t * The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
* allocated by the user. The structure is used during the EZI2C operation for * allocated by the user. The structure is used during the EZI2C operation for
* internal configuration and data keeping. The user must not modify anything * internal configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
* \return * \return
@ -524,7 +531,7 @@ uint32_t Cy_SCB_EZI2C_GetActivity(CySCB_Type const *base, cy_stc_scb_ezi2c_conte
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t * The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
* allocated by the user. The structure is used during the EZI2C operation for * allocated by the user. The structure is used during the EZI2C operation for
* internal configuration and data keeping. The user must not modify anything * internal configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
*******************************************************************************/ *******************************************************************************/
@ -553,7 +560,7 @@ void Cy_SCB_EZI2C_SetAddress1(CySCB_Type *base, uint8_t addr, cy_stc_scb_ezi2c_c
* * \param context * * \param context
* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t * The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
* allocated by the user. The structure is used during the EZI2C operation for * allocated by the user. The structure is used during the EZI2C operation for
* internal configuration and data keeping. The user must not modify anything * internal configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
* \return * \return
@ -592,11 +599,11 @@ uint32_t Cy_SCB_EZI2C_GetAddress1(CySCB_Type const *base, cy_stc_scb_ezi2c_conte
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t * The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
* allocated by the user. The structure is used during the EZI2C operation for * allocated by the user. The structure is used during the EZI2C operation for
* internal configuration and data keeping. The user must not modify anything * internal configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
* \note * \note
* * This fucntion is not interrupt-protected and to prevent a race condition, * * This function is not interrupt-protected and to prevent a race condition,
* it must be protected from the EZI2C interruption in the place where it * it must be protected from the EZI2C interruption in the place where it
* is called. * is called.
* * Calling this function in the middle of a transaction intended for the * * Calling this function in the middle of a transaction intended for the
@ -633,7 +640,7 @@ void Cy_SCB_EZI2C_SetBuffer1(CySCB_Type const *base, uint8_t *buffer, uint32_t s
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t * The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
* allocated by the user. The structure is used during the EZI2C operation for * allocated by the user. The structure is used during the EZI2C operation for
* internal configuration and data keeping. The user must not modify anything * internal configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
* \note * \note
@ -664,7 +671,7 @@ void Cy_SCB_EZI2C_SetAddress2(CySCB_Type *base, uint8_t addr, cy_stc_scb_ezi2c_c
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t * The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
* allocated by the user. The structure is used during the EZI2C operation for * allocated by the user. The structure is used during the EZI2C operation for
* internal configuration and data keeping. The user must not modify anything * internal configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
* \return * \return
@ -703,11 +710,11 @@ uint32_t Cy_SCB_EZI2C_GetAddress2(CySCB_Type const *base, cy_stc_scb_ezi2c_conte
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t * The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
* allocated by the user. The structure is used during the EZI2C operation for * allocated by the user. The structure is used during the EZI2C operation for
* internal configuration and data keeping. The user must not modify anything * internal configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
* \note * \note
* * This fucntion is not interrupt-protected and to prevent a race condition, * * This function is not interrupt-protected. To prevent a race condition,
* it must be protected from the EZI2C interruption in the place where it * it must be protected from the EZI2C interruption in the place where it
* is called. * is called.
* * Calling this function in the middle of a transaction intended for the * * Calling this function in the middle of a transaction intended for the
@ -735,7 +742,7 @@ void Cy_SCB_EZI2C_SetBuffer2(CySCB_Type const *base, uint8_t *buffer, uint32_t s
* *
* This is the interrupt function for the SCB configured in the EZI2C mode. * This is the interrupt function for the SCB configured in the EZI2C mode.
* This function must be called inside the user-defined interrupt service * This function must be called inside the user-defined interrupt service
* routine to make the EZI2C slave to work. * routine to make the EZI2C slave work.
* *
* \param base * \param base
* The pointer to the EZI2C SCB instance. * The pointer to the EZI2C SCB instance.
@ -743,7 +750,7 @@ void Cy_SCB_EZI2C_SetBuffer2(CySCB_Type const *base, uint8_t *buffer, uint32_t s
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated * The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated
* by the user. The structure is used during the EZI2C operation for internal * by the user. The structure is used during the EZI2C operation for internal
* configuration and data keeping. The user must not modify anything * configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
*******************************************************************************/ *******************************************************************************/
@ -754,6 +761,11 @@ void Cy_SCB_EZI2C_Interrupt(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *contex
/* Handle an I2C wake-up event */ /* Handle an I2C wake-up event */
if (0UL != (CY_SCB_I2C_INTR_WAKEUP & Cy_SCB_GetI2CInterruptStatusMasked(base))) if (0UL != (CY_SCB_I2C_INTR_WAKEUP & Cy_SCB_GetI2CInterruptStatusMasked(base)))
{ {
/* Move from IDLE state, the slave was addressed. Following address match
* interrupt continue transfer.
*/
context->state = CY_SCB_EZI2C_STATE_ADDR;
Cy_SCB_ClearI2CInterrupt(base, CY_SCB_I2C_INTR_WAKEUP); Cy_SCB_ClearI2CInterrupt(base, CY_SCB_I2C_INTR_WAKEUP);
} }
@ -832,7 +844,7 @@ void Cy_SCB_EZI2C_Interrupt(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *contex
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated * The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated
* by the user. The structure is used during the EZI2C operation for internal * by the user. The structure is used during the EZI2C operation for internal
* configuration and data keeping. The user must not modify anything * configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
*******************************************************************************/ *******************************************************************************/
@ -862,7 +874,7 @@ static void HandleErrors(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context)
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated * The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated
* by the user. The structure is used during the EZI2C operation for internal * by the user. The structure is used during the EZI2C operation for internal
* configuration and data keeping. The user must not modify anything * configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
*******************************************************************************/ *******************************************************************************/
@ -878,7 +890,7 @@ static void HandleAddress(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context)
uint32_t address = (Cy_SCB_ReadRxFifo(base) >> 1UL); uint32_t address = (Cy_SCB_ReadRxFifo(base) >> 1UL);
Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL); Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL);
/* Decide if the address matches */ /* Decide whether the address matches */
if ((address == context->address1) || (address == context->address2)) if ((address == context->address1) || (address == context->address2))
{ {
/* ACK the address */ /* ACK the address */
@ -901,7 +913,7 @@ static void HandleAddress(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context)
} }
} }
/* Clear the TX FIFO before continue the transaction */ /* Clear the TX FIFO before continuing the transaction */
Cy_SCB_ClearTxFifo(base); Cy_SCB_ClearTxFifo(base);
/* Set the command to an ACK or NACK address */ /* Set the command to an ACK or NACK address */
@ -949,7 +961,7 @@ static void HandleAddress(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context)
* Function Name: HandleDataReceive * Function Name: HandleDataReceive
****************************************************************************//** ****************************************************************************//**
* *
* Updates RX FIFO level to trigger the next read from it. It also manages * Updates the RX FIFO level to trigger the next read from it. It also manages
* the auto-data NACK feature. * the auto-data NACK feature.
* *
* \param base * \param base
@ -997,7 +1009,7 @@ static void UpdateRxFifoLevel(CySCB_Type *base, uint32_t bufSize)
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated * The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated
* by the user. The structure is used during the EZI2C operation for internal * by the user. The structure is used during the EZI2C operation for internal
* configuration and data keeping. The user must not modify anything * configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
*******************************************************************************/ *******************************************************************************/
@ -1035,12 +1047,12 @@ static void HandleDataReceive(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *cont
} }
} }
/* Check if the received base address is valid */ /* Check whether the received base address is valid */
if (checkBaseAddr) if (checkBaseAddr)
{ {
uint32_t cmd = SCB_I2C_S_CMD_S_ACK_Msk; uint32_t cmd = SCB_I2C_S_CMD_S_ACK_Msk;
/* Decide if the base address within the buffer range */ /* Decide whether the base address within the buffer range */
if (baseAddr < context->bufSize) if (baseAddr < context->bufSize)
{ {
/* Accept the new base address */ /* Accept the new base address */
@ -1107,7 +1119,7 @@ static void HandleDataReceive(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *cont
{ {
uint32_t byte = Cy_SCB_ReadRxFifo(base); uint32_t byte = Cy_SCB_ReadRxFifo(base);
/* Check if there is space to store the byte */ /* Check whether there is space to store the byte */
if (context->bufSize > 0UL) if (context->bufSize > 0UL)
{ {
/* Continue the transfer: send an ACK */ /* Continue the transfer: send an ACK */
@ -1166,7 +1178,7 @@ static void HandleDataReceive(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *cont
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated * The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated
* by the user. The structure is used during the EZI2C operation for internal * by the user. The structure is used during the EZI2C operation for internal
* configuration and data keeping. The user must not modify anything * configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
*******************************************************************************/ *******************************************************************************/
@ -1201,7 +1213,7 @@ static void HandleDataTransmit(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *con
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated * The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated
* by the user. The structure is used during the EZI2C operation for internal * by the user. The structure is used during the EZI2C operation for internal
* configuration and data keeping. The user must not modify anything * configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
*******************************************************************************/ *******************************************************************************/
@ -1259,7 +1271,7 @@ static void HandleStop(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context)
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated * The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated
* by the user. The structure is used during the EZI2C operation for internal * by the user. The structure is used during the EZI2C operation for internal
* configuration and data keeping. The user must not modify anything * configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
*******************************************************************************/ *******************************************************************************/
@ -1270,7 +1282,7 @@ static void UpdateAddressMask(CySCB_Type *base, cy_stc_scb_ezi2c_context_t const
/* Check how many addresses are used: */ /* Check how many addresses are used: */
if (0U != context->address2) if (0U != context->address2)
{ {
/* If (addr1 and addr2) bit matches - mask bit equals 1, otherwise 0 */ /* If (addr1 and addr2) bits match - mask bit equals 1; otherwise 0 */
addrMask = (uint32_t) ~((uint32_t) context->address1 ^ (uint32_t) context->address2); addrMask = (uint32_t) ~((uint32_t) context->address1 ^ (uint32_t) context->address2);
} }
else else

183
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/scb/cy_scb_ezi2c.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_ezi2c.h
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_scb_ezi2c.h * \file cy_scb_ezi2c.h
* \version 2.0 * \version 2.10
* *
* Provides EZI2C API declarations of the SCB driver. * Provides EZI2C API declarations of the SCB driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -15,7 +15,7 @@
/** /**
* \addtogroup group_scb_ezi2c * \addtogroup group_scb_ezi2c
* \{ * \{
* Driver API for EZI2C slave Peripheral * Driver API for EZI2C Slave Peripheral
* *
* I2C - The Inter-Integrated Circuit (I2C) bus is an industry-standard. * I2C - The Inter-Integrated Circuit (I2C) bus is an industry-standard.
* The two-wire hardware interface was developed by Philips Semiconductors * The two-wire hardware interface was developed by Philips Semiconductors
@ -25,7 +25,7 @@
* device based on the SCB hardware block. This slave device emulates a common * device based on the SCB hardware block. This slave device emulates a common
* I2C EEPROM interface that acts like dual-port memory between the external * I2C EEPROM interface that acts like dual-port memory between the external
* master and your code. I2C devices based on the SCB hardware are compatible * master and your code. I2C devices based on the SCB hardware are compatible
* with the I2C Standard mode, Fast mode, and Fast mode Plus specifications as * with the I2C Standard mode, Fast mode, and Fast mode Plus specifications, as
* defined in the I2C bus specification. * defined in the I2C bus specification.
* *
* Features: * Features:
@ -36,66 +36,141 @@
* * Supports Hardware Address Match * * Supports Hardware Address Match
* * Supports two hardware addresses with separate buffers * * Supports two hardware addresses with separate buffers
* * Supports Wake from Deep Sleep on address match * * Supports Wake from Deep Sleep on address match
* * Simple to set up and use, does not require calling EZI2C API * * Simple to set up and use; does not require calling EZI2C API
* at run time. * at run time.
* *
* \section group_scb_ezi2c_configuration Configuration Considerations * \section group_scb_ezi2c_configuration Configuration Considerations
* The EZI2C slave driver configuration can be divided to number of sequential
* steps listed below:
* * \ref group_scb_ezi2c_config
* * \ref group_scb_ezi2c_pins
* * \ref group_scb_ezi2c_clock
* * \ref group_scb_ezi2c_data_rate
* * \ref group_scb_ezi2c_intr
* * \ref group_scb_ezi2c_enable
* *
* \note
* EZI2C slave driver is built on top of the SCB hardware block. The SCB3
* instance is used as an example for all code snippets. Modify the code to
* match your design.
*
* \subsection group_scb_ezi2c_config Configure EZI2C slave
* To set up the EZI2C slave driver, provide the configuration parameters in the * To set up the EZI2C slave driver, provide the configuration parameters in the
* \ref cy_stc_scb_ezi2c_config_t structure. For the slave, the primary slave * \ref cy_stc_scb_ezi2c_config_t structure. The primary slave address
* address slaveAddress1 must be provided. The other parameters are optional * slaveAddress1 must be provided. The other parameters are optional for
* for operation. * operation. To initialize the driver, call \ref Cy_SCB_EZI2C_Init
* To get EZI2C slave operate with desired data rate the SCB clock frequency * function providing a pointer to the filled \ref cy_stc_scb_ezi2c_config_t
* must be configured. Use the SysClk driver API to do that. Refer to the * structure and allocated \ref cy_stc_scb_ezi2c_context_t.
* technical reference manual (TRM) to get information how to select SCB
* frequency in I2C mode to support desired data rate.
* To initialize the driver, call the \ref Cy_SCB_EZI2C_Init function providing
* a pointer to the filled \ref cy_stc_scb_ezi2c_config_t structure and
* allocated \ref cy_stc_scb_ezi2c_context_t. The \ref Cy_SCB_EZI2C_Interrupt
* function must be called in the interrupt handler for the selected
* SCB instance and this interrupt must be enabled in the NVIC. Set up the
* EZI2C slave buffers before calling \ref Cy_SCB_EZI2C_Enable using
* \ref Cy_SCB_EZI2C_SetBuffer1 for the primary slave address and
* \ref Cy_SCB_EZI2C_SetBuffer2 for the secondary if it is enabled. Finally,
* enable the EZI2C slave operation calling \ref Cy_SCB_EZI2C_Enable.
* *
* The following operation might not require calling any EZI2C slave function * \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_CFG
* because the I2C master is able to access the slave buffer and the application *
* can directly access it as well. Note that this is an application level task * Set up the EZI2C slave buffer before enabling its
* operation by using \ref Cy_SCB_EZI2C_SetBuffer1 for the primary slave address
* and \ref Cy_SCB_EZI2C_SetBuffer2 for the secondary (if the secondary is enabled).
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_CFG_BUFFER
*
* \subsection group_scb_ezi2c_pins Assign and Configure Pins
* Only dedicated SCB pins can be used for I2C operation. The HSIOM
* register must be configured to connect the block to the pins. Also the I2C pins
* must be configured in Open-Drain, Drives Low mode (this pin configuration
* implies usage of external pull-up resistors):
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_CFG_PINS
*
* \note
* The alternative pins configuration is Resistive Pull-ups which implies usage
* internal pull-up resistors. This configuration is not recommended because
* resistor value is fixed and cannot be used for all supported data rates.
* Refer to device datasheet parameter RPULLUP for resistor value specifications.
*
* \subsection group_scb_ezi2c_clock Assign Clock Divider
* The clock source must be connected to the SCB block to oversample input and
* output signals. You must use one of the 8-bit or 16-bit dividers <em><b>(the
* source clock of this divider must be Clk_Peri)</b></em>. Use the
* \ref group_sysclk driver API to do that.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_CFG_ASSIGN_CLOCK
*
* \subsection group_scb_ezi2c_data_rate Configure Data Rate
* To get EZI2C slave to operate at the desired data rate, the source clock must be
* fast enough to provide sufficient oversampling. Therefore, the clock divider
* must be configured to provide desired clock frequency. Use the
* \ref group_sysclk driver API to do that.
* Refer to the technical reference manual (TRM) section I2C sub-section
* Oversampling and Bit Rate to get information about how to configure the I2C to run
* at the desired data rate.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_CFG_DATA_RATE
*
* \subsection group_scb_ezi2c_intr Configure Interrupt
* The interrupt is mandatory for the EZI2C slave operation.
* The \ref Cy_SCB_EZI2C_Interrupt function must be called in the interrupt
* handler for the selected SCB instance. Also, this interrupt must be enabled
* in the NVIC or it will not work.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_INTR_A
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_INTR_B
*
* \subsection group_scb_ezi2c_enable Enable EZI2C slave
* Finally, enable the EZI2C slave operation by calling \ref Cy_SCB_EZI2C_Enable.
* Now the I2C device responds to the assigned address.
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_ENABLE
*
* \section group_scb_ezi2c_use_cases Common Use Cases
* The EZI2C slave operation might not require calling any EZI2C slave function
* because the I2C master is able to access the slave buffer. The application
* can directly access it as well. Note that this is an application-level task
* to ensure the buffer content integrity. * to ensure the buffer content integrity.
* *
* The master can access the buffer: * \subsection group_scb_ezi2c_master_wr Master Write operation
* * Master Write operation starts with sending a base address which is 1 * This operation starts with sending a base address that is one
* or 2 bytes depending on the sub-address size configuration. This base * or two bytes, depending on the sub-address size configuration. This base
* address is retained and will be used for later read operations. Following * address is retained and will be used for later read operations. Following
* the base address, there is a sequence of bytes written into the buffer * the base address, there is a sequence of bytes written into the buffer
* starting from the base address location. The buffer index is incremented * starting from the base address location. The buffer index is incremented
* for each written byte, but this does not affect the base address which is * for each written byte, but this does not affect the base address that is
* retained. The length of a write operation is limited by the maximum buffer * retained. The length of a write operation is limited by the maximum buffer
* read/write region size.\n * read/write region size.\n
* When a master attempts to write outside the read/write region or past the * When a master attempts to write outside the read/write region or past the
* end of the buffer, the last byte is NACKed. * end of the buffer, the last byte is NACKed.
* * Master Read operation always starts from the base address set by the most *
* recent Write operation. The buffer index is incremented for each read byte. * \image html scb_ezi2c_write.png
*
* \subsection group_scb_ezi2c_master_rd Master Read operation
* This operation always starts from the base address set by the most
* recent write operation. The buffer index is incremented for each read byte.
* Two sequential read operations start from the same base address no matter * Two sequential read operations start from the same base address no matter
* how many bytes were read. The length of a read operation is not limited by * how many bytes are read. The length of a read operation is not limited by
* the maximum size of the data buffer. The EZI2C slave returns 0xFF bytes * the maximum size of the data buffer. The EZI2C slave returns 0xFF bytes
* if the read operation passes the end of the buffer.\n * if the read operation passes the end of the buffer.\n
* Typically, a read operation requires the base address to be updated before * Typically, a read operation requires the base address to be updated before
* starting the read. In this case, the write and read operations must be * starting the read. In this case, the write and read operations must be
* combined together. The I2C master may use the ReStart or Stop/Start * combined together.
* conditions to combine the operations. The write operation sets only the
* base address and the following read operation will start from the new base
* address. In cases where the base address remains the same, there is no need
* for a write operation.
* *
* The EZI2C driver provides the callback functions to facilitate the low-power * \image html scb_ezi2c_read.png
* mode transition. The callback \ref Cy_SCB_EZI2C_DeepSleepCallback can be called *
* during execution of \ref Cy_SysPm_DeepSleep; \ref Cy_SCB_EZI2C_HibernateCallback * The I2C master may use the ReStart or Stop/Start conditions to combine the
* can be called during execution of \ref Cy_SysPm_Hibernate. To trigger the * operations. The write operation sets only the base address and the following
* callback execution, the callback must be registered before calling the * read operation will start from the new base address. In cases where the base
* mode transition function. Refer to SysPm driver for more information about * address remains the same, there is no need for a write operation.
* low-power mode transitions. * \image html scb_ezi2c_set_ba_read.png
*
* \section group_scb_ezi2c_lp Low Power Support
* The EZI2C slave provides the callback functions to handle power mode
* transition. The callback \ref Cy_SCB_EZI2C_DeepSleepCallback must be called
* during execution of \ref Cy_SysPm_DeepSleep;
* \ref Cy_SCB_EZI2C_HibernateCallback must be called during execution of
* \ref Cy_SysPm_Hibernate. To trigger the callback execution, the callback must
* be registered before calling the power mode transition function. Refer to
* \ref group_syspm driver for more information about power mode transitions and
* callback registration.
*
* \note
* Only applicable for <b>rev-08 of the CY8CKIT-062-BLE</b>.
* For proper operation, when the EZI2C slave is configured to be a wakeup
* source from Deep Sleep mode, the \ref Cy_SCB_EZI2C_DeepSleepCallback must
* be copied and modified. Refer to the function description to get the details.
* *
* \section group_scb_ezi2c_more_information More Information * \section group_scb_ezi2c_more_information More Information
* *
@ -125,7 +200,7 @@
* <td>14.1</td> * <td>14.1</td>
* <td>R</td> * <td>R</td>
* <td>There shall be no unreachable code.</td> * <td>There shall be no unreachable code.</td>
* <td>The SCB block parameters can be a constant false or true depends on * <td>The SCB block parameters can be a constant false or true depending on
* the selected device and cause code to be unreachable.</td> * the selected device and cause code to be unreachable.</td>
* </tr> * </tr>
* <tr> * <tr>
@ -142,8 +217,8 @@
* <td>A function shall have a single point of exit at the end of the * <td>A function shall have a single point of exit at the end of the
* function.</td> * function.</td>
* <td>The functions can return from several points. This is done to improve * <td>The functions can return from several points. This is done to improve
* code clarity when returning error status code if input parameters * code clarity when returning error status code if input parameter
* validation is failed.</td> * validation fails.</td>
* </tr> * </tr>
* </table> * </table>
* *
@ -151,12 +226,17 @@
* <table class="doxtable"> * <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr> * <tr>
* <td>2.10</td>
* <td>None.</td>
* <td>SCB I2C driver updated.</td>
* </tr>
* <tr>
* <td rowspan="2"> 2.0</td> * <td rowspan="2"> 2.0</td>
* <td>Added parameters validation for public API.</td> * <td>Added parameters validation for public API.</td>
* <td></td> * <td></td>
* </tr> * </tr>
* <tr> * <tr>
* <td>Replaced variables which have limited range of values with enumerated * <td>Replaced variables that have limited range of values with enumerated
* types.</td> * types.</td>
* <td></td> * <td></td>
* </tr> * </tr>
@ -225,6 +305,7 @@ typedef enum
typedef enum typedef enum
{ {
CY_SCB_EZI2C_STATE_IDLE, CY_SCB_EZI2C_STATE_IDLE,
CY_SCB_EZI2C_STATE_ADDR,
CY_SCB_EZI2C_STATE_RX_OFFSET_MSB, CY_SCB_EZI2C_STATE_RX_OFFSET_MSB,
CY_SCB_EZI2C_STATE_RX_OFFSET_LSB, CY_SCB_EZI2C_STATE_RX_OFFSET_LSB,
CY_SCB_EZI2C_STATE_RX_DATA0, CY_SCB_EZI2C_STATE_RX_DATA0,
@ -260,7 +341,7 @@ typedef struct cy_stc_scb_ezi2c_config
cy_en_scb_ezi2c_sub_addr_size_t subAddressSize; cy_en_scb_ezi2c_sub_addr_size_t subAddressSize;
/** /**
* When set, the slave will wake the device from deep sleep on an address * When set, the slave will wake the device from Deep Sleep on an address
* match (The device datasheet must be consulted to determine which SCBs * match (The device datasheet must be consulted to determine which SCBs
* support this mode) * support this mode)
*/ */
@ -271,7 +352,7 @@ typedef struct cy_stc_scb_ezi2c_config
* All fields for the context structure are internal. Firmware never reads or * All fields for the context structure are internal. Firmware never reads or
* writes these values. Firmware allocates the structure and provides the * writes these values. Firmware allocates the structure and provides the
* address of the structure to the driver in function calls. Firmware must * address of the structure to the driver in function calls. Firmware must
* ensure that the defined instance of this structure remains in scope while * ensure that the defined instance of this structure remains in scope
* while the drive is in use. * while the drive is in use.
*/ */
typedef struct cy_stc_scb_ezi2c_context typedef struct cy_stc_scb_ezi2c_context
@ -406,14 +487,14 @@ cy_en_syspm_status_t Cy_SCB_EZI2C_HibernateCallback(cy_stc_syspm_callback_params
* slave address. The sources of the error are: a misplaced Start or Stop * slave address. The sources of the error are: a misplaced Start or Stop
* condition or lost arbitration while the slave drives SDA. * condition or lost arbitration while the slave drives SDA.
* When CY_SCB_EZI2C_STATUS_ERR is set, the slave buffer may contain an * When CY_SCB_EZI2C_STATUS_ERR is set, the slave buffer may contain an
* invalid byte. It is recommended to discard the buffer content in this case. * invalid byte. Discard the buffer content in this case.
*/ */
#define CY_SCB_EZI2C_STATUS_ERR (0x20UL) #define CY_SCB_EZI2C_STATUS_ERR (0x20UL)
/** \} group_scb_ezi2c_macros_get_activity */ /** \} group_scb_ezi2c_macros_get_activity */
/** /**
* This value is returned by the slave when the buffer is not configured or * This value is returned by the slave when the buffer is not configured or
* the master requests more bytes than available in the buffer. * the master requests more bytes than are available in the buffer.
*/ */
#define CY_SCB_EZI2C_DEFAULT_TX (0xFFUL) #define CY_SCB_EZI2C_DEFAULT_TX (0xFFUL)

470
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/scb/cy_scb_i2c.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_i2c.c
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File diff suppressed because it is too large Load Diff

308
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/scb/cy_scb_i2c.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_i2c.h
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_scb_i2c.h * \file cy_scb_i2c.h
* \version 2.0 * \version 2.10
* *
* Provides I2C API declarations of the SCB driver. * Provides I2C API declarations of the SCB driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -35,60 +35,168 @@
* * Wake From Deep Sleep on Address Match * * Wake From Deep Sleep on Address Match
* *
* \section group_scb_i2c_configuration Configuration Considerations * \section group_scb_i2c_configuration Configuration Considerations
* The I2C driver configuration can be divided to number of sequential
* steps listed below:
* * \ref group_scb_i2c_config
* * \ref group_scb_i2c_pins
* * \ref group_scb_i2c_clock
* * \ref group_scb_i2c_data_rate
* * \ref group_scb_i2c_intr
* * \ref group_scb_i2c_enable
* *
* To set up the I2C driver, provide the configuration parameters in the * \note
* I2C driver is built on top of the SCB hardware block. The SCB3 instance is
* used as an example for all code snippets. Modify the code to match your
* design.
*
* \subsection group_scb_i2c_config Configure I2C
* To set up the I2C slave driver, provide the configuration parameters in the
* \ref cy_stc_scb_i2c_config_t structure. Provide i2cMode to the select * \ref cy_stc_scb_i2c_config_t structure. Provide i2cMode to the select
* operation mode slave, master or master-slave. For master modes, provide * operation mode slave, master or master-slave. For master modes, provide
* useRxFifo and useTxFifo. For slave mode, also provide the slaveAddress and * useRxFifo and useTxFifo parameters. For slave mode, also provide the
* slaveAddressMask. The other parameters are optional for operation. * slaveAddress and slaveAddressMask. The other parameters are optional for
* To initialize the driver, call the \ref Cy_SCB_I2C_Init function providing * operation. To initialize the driver, call \ref Cy_SCB_I2C_Init
* the pointer to filled configuration structure \ref cy_stc_scb_i2c_config_t * function providing a pointer to the filled \ref cy_stc_scb_i2c_config_t
* and the pointer to allocated context structure \ref cy_stc_scb_i2c_context_t. * structure and allocated \ref cy_stc_scb_i2c_context_t.
* To get I2C operate with the desired data rate, the SCB clock and SCL duration
* (only applicable for master mode) must be configured. Use the SysClk driver
* API to configure SCB clock frequency and \ref Cy_SCB_I2C_SetDataRate to set
* the SCL low phase and high phase duration. Refer to the technical reference
* manual (TRM) to get more information on how to configure the I2C to operate
* with the desired data rate. Call \ref Cy_SCB_I2C_Enable to start the I2C
* operation after configuration is completed.
* *
* Master mode operation: \n * \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_CFG
*
* \subsection group_scb_i2c_pins Assign and Configure Pins
* Only dedicated SCB pins can be used for I2C operation. The HSIOM
* register must be configured to connect block to the pins. Also the I2C pins
* must be configured in Open-Drain, Drives Low mode (this pins configuration
* implies usage of external pull-up resistors):
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_CFG_PINS
*
* \note
* The alternative pins configuration is Resistive Pull-ups which implies usage
* internal pull-up resistors. This configuration is not recommended because
* resistor value is fixed and cannot be used for all supported data rates.
* Refer to the device datasheet parameter RPULLUP for resistor value specifications.
*
* \subsection group_scb_i2c_clock Assign Clock Divider
* The clock source must be connected to the SCB block to oversample input and
* output signals. You must use one of the 8-bit or 16-bit dividers <em><b>(the
* source clock of this divider must be Clk_Peri)</b></em>. Use the
* \ref group_sysclk driver API to do that.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_CFG_ASSIGN_CLOCK
*
* Set up I2C slave read and write buffer before enabling its
* operation using \ref Cy_SCB_I2C_SlaveConfigReadBuf and \ref
* Cy_SCB_I2C_SlaveConfigWriteBuf appropriately. Note that the master reads
* data from the slave read buffer and writes data into the slave write buffer.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_CFG_BUFFER
*
* \subsection group_scb_i2c_data_rate Configure Data Rate
* To get I2C slave operation with the desired data rate, the source clock must be
* fast enough to provide sufficient oversampling. Therefore, the clock divider
* must be configured to provide desired clock frequency. Use the
* \ref group_sysclk driver API to do that.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_CFG_DATA_RATE_SLAVE
*
* To get I2C master operation with the desired data rate, the source clock
* frequency and SCL low and high phase duration must be configured. Use the
* \ref group_sysclk driver API to configure source clock frequency. Then call
* \ref Cy_SCB_I2C_SetDataRate to set the SCL low and high phase duration.
* This function reach for SCL low and high phase settings based on source clock
* frequency.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_CFG_DATA_RATE_MASTER
*
* Alternatively, the low and high phase can be set directly using
* \ref Cy_SCB_I2C_MasterSetLowPhaseDutyCycle and
* \ref Cy_SCB_I2C_MasterSetHighPhaseDutyCycle functions. \n
* Refer to the technical reference manual (TRM) section I2C sub-section
* Oversampling and Bit Rate to get information how to configure I2C to run with
* the desired data rate.
*
* \note
* For I2C slave, the analog filter is used for all supported data rates. \n
* For I2C master, the analog filter is used for Standard and Fast modes and the
* digital filter for Fast Plus mode.
*
* \subsection group_scb_i2c_intr Configure Interrupt
* The interrupt is mandatory for I2C operation. The exception is the I2C master,
* which uses only the \ref group_scb_i2c_master_low_level_functions functions.
* The driver provides three interrupt functions: \ref Cy_SCB_I2C_Interrupt,
* \ref Cy_SCB_I2C_SlaveInterrupt, and \ref Cy_SCB_I2C_MasterInterrupt. One of
* these functions must be called in the interrupt handler for the selected SCB
* instance. Call \ref Cy_SCB_I2C_SlaveInterrupt when I2C is configured to
* operate as a slave, \ref Cy_SCB_I2C_MasterInterrupt when I2C is configured
* to operate as a master and \ref Cy_SCB_I2C_Interrupt when I2C is configured
* to operate as master and slave. Using the slave- or master-specific interrupt
* function allows reducing the flash consumed by the I2C driver. Also this
* interrupt must be enabled in the NVIC otherwise it will not work.
* \note
* The I2C driver documentation refers to the \ref Cy_SCB_I2C_Interrupt function
* when interrupt processing is mandatory for the operation. This is done to
* simplify the readability of the driver's documentation. The application should
* call the slave- or master-specific interrupt functions \ref Cy_SCB_I2C_SlaveInterrupt
* or \ref Cy_SCB_I2C_MasterInterrupt, when appropriate.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_INTR_A
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_INTR_B
*
* \subsection group_scb_i2c_enable Enable I2C
* Finally, enable the I2C operation calling \ref Cy_SCB_I2C_Enable. Then I2C
* slave starts respond to the assigned address and I2C master ready to execute
* transfers.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_ENABLE
*
* \section group_scb_i2c_use_cases Common Use Cases
*
* \subsection group_scb_i2c_master_mode Master Operation
* The master API is divided into two categories: * The master API is divided into two categories:
* \ref group_scb_i2c_master_high_level_functions and * \ref group_scb_i2c_master_high_level_functions and
* \ref group_scb_i2c_master_low_level_functions. Therefore there are two * \ref group_scb_i2c_master_low_level_functions. Therefore, there are two
* methods for initiating I2C master transactions using either low-level or * methods for initiating I2C master transactions using either <b>Low-Level or
* high-level API. These two methods are described below. Only one method should * High-Level</b> API. These two methods are described below. Only one method
* be used at a time. They should not be mixed. * should be used at a time. They should not be mixed.
* *
* * Call \ref Cy_SCB_I2C_MasterRead or \ref Cy_SCB_I2C_MasterWrite to * \subsubsection group_scb_i2c_master_hl Use High-Level Functions
* communicate with the slave. These functions do not block and only * Call \ref Cy_SCB_I2C_MasterRead or \ref Cy_SCB_I2C_MasterWrite to
* start a transaction. After a transfer is started, the * communicate with the slave. These functions do not block and only start a
* \ref Cy_SCB_I2C_Interrupt handles the further data transfer until its * transaction. After a transaction starts, the \ref Cy_SCB_I2C_Interrupt
* completion. Therefore, \ref Cy_SCB_I2C_Interrupt must be called inside the * handles the further data transaction until its completion (successfully or with an error
* user interrupt handler to make the API above work. To monitor the transfer, * occurring). Therefore, \ref Cy_SCB_I2C_Interrupt must be called inside the
* use \ref Cy_SCB_I2C_MasterGetStatus or \ref Cy_SCB_I2C_RegisterEventCallback * interrupt handler to make the functions above work. To monitor the transaction,
* to register callback function to be notified about * use \ref Cy_SCB_I2C_MasterGetStatus or register callback function using
* \ref Cy_SCB_I2C_RegisterEventCallback to be notified about
* \ref group_scb_i2c_macros_callback_events. * \ref group_scb_i2c_macros_callback_events.
* *
* * Call \ref Cy_SCB_I2C_MasterSendStart to generate a start, send an address * \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_MASTER_WRITE_READ_INT
*
* \subsubsection group_scb_i2c_master_ll Use Low-Level Functions
* Call \ref Cy_SCB_I2C_MasterSendStart to generate a start, send an address
* with the Read/Write direction bit, and receive acknowledgment. After the * with the Read/Write direction bit, and receive acknowledgment. After the
* address is ACKed by the slave, the transaction can be continued by calling * address is ACKed by the slave, the transaction can be continued by calling
* \ref Cy_SCB_I2C_MasterReadByte or \ref Cy_SCB_I2C_MasterWriteByte depending * \ref Cy_SCB_I2C_MasterReadByte or \ref Cy_SCB_I2C_MasterWriteByte depending
* on its direction. These functions handle one byte per call, therefore * on its direction. These functions handle one byte per call. Therefore,
* they should be called for each byte in the transaction. Note that for the * they should be called for each byte in the transaction. Note that for the
* Read transaction the last byte must be NAKed. To complete the current * Read transaction, the last byte must be NAKed. To complete the current
* transaction, call \ref Cy_SCB_I2C_MasterSendStop or call * transaction, call \ref Cy_SCB_I2C_MasterSendStop or call
* \ref Cy_SCB_I2C_MasterSendReStart to complete the current transaction and * \ref Cy_SCB_I2C_MasterSendReStart to complete the current transaction and
* start a new one. Typically, do a restart to change the transaction * start a new one. Typically, do a restart to change the transaction
* direction without releasing the bus from the master control. * direction without releasing the bus from the master control.
* Note that these functions are blocking and do not require calling * The Low-Level functions are blocking and do not require calling
* \ref Cy_SCB_I2C_Interrupt inside the user interrupt handler. Using these * \ref Cy_SCB_I2C_Interrupt inside the interrupt handler. Using these
* functions requires extensive knowledge of the I2C protocol to execute * functions requires extensive knowledge of the I2C protocol to execute
* transactions correctly. * transactions correctly.
* *
* Slave mode operation: \n * <b>Master Write Operation</b>
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_MASTER_WRITE_MANUAL
*
* <b>Master Read Operation</b>
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_MASTER_READ_MANUAL
*
* \subsection group_scb_i2c_slave Slave Operation
* The slave operation is based on the \ref Cy_SCB_I2C_Interrupt that must be * The slave operation is based on the \ref Cy_SCB_I2C_Interrupt that must be
* called inside the user interrupt handler. The Read and Write buffer must * called inside the interrupt handler. The Read and Write buffer must
* be provided for the slave to enable communication with the master. Use * be provided for the slave to enable communication with the master. Use
* \ref Cy_SCB_I2C_SlaveConfigReadBuf and \ref Cy_SCB_I2C_SlaveConfigWriteBuf * \ref Cy_SCB_I2C_SlaveConfigReadBuf and \ref Cy_SCB_I2C_SlaveConfigWriteBuf
* for this purpose. Note that after transaction completion the buffer must be * for this purpose. Note that after transaction completion the buffer must be
@ -97,26 +205,39 @@
* For example: The Read buffer is configured to be 10 bytes and the master Read * For example: The Read buffer is configured to be 10 bytes and the master Read
* is 8 bytes. If the Read buffer is not configured again, the next master Read * is 8 bytes. If the Read buffer is not configured again, the next master Read
* will start from the 9th byte. * will start from the 9th byte.
* To monitor the transfer status, use \ref Cy_SCB_I2C_SlaveGetStatus or * To monitor the transaction status, use \ref Cy_SCB_I2C_SlaveGetStatus or
* use \ref Cy_SCB_I2C_RegisterEventCallback to register a callback function * use \ref Cy_SCB_I2C_RegisterEventCallback to register a callback function
* to be notified about \ref group_scb_i2c_macros_callback_events. * to be notified about \ref group_scb_i2c_macros_callback_events.
* *
* <b>Get Slave Events Notification</b>
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_SLAVE_REG_CALLBACK
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_SLAVE_NOTIFICATION
*
* <b>Polling Slave Completion Events</b>
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_SLAVE_POLLING
*
* \note * \note
* All slave API (except \ref Cy_SCB_I2C_SlaveAbortRead and * All slave API (except \ref Cy_SCB_I2C_SlaveAbortRead and
* \ref Cy_SCB_I2C_SlaveAbortWrite) are not interrupt-protected and to * \ref Cy_SCB_I2C_SlaveAbortWrite) <b>are not interrupt-protected</b> and to
* prevent a race condition, they should be protected from the I2C interruption * prevent a race condition, they should be protected from the I2C interruption
* in the place where they are called. * in the place where they are called.
* *
* The I2C driver provides the callback functions to facilitate the low-power * \section group_scb_i2c_lp Low Power Support
* mode transition. The callback \ref Cy_SCB_I2C_DeepSleepCallback can be called * The I2C driver provides the callback functions to handle power mode transition.
* The callback \ref Cy_SCB_I2C_DeepSleepCallback must be called
* during execution of \ref Cy_SysPm_DeepSleep; \ref Cy_SCB_I2C_HibernateCallback * during execution of \ref Cy_SysPm_DeepSleep; \ref Cy_SCB_I2C_HibernateCallback
* can be called during execution of \ref Cy_SysPm_Hibernate. To trigger the * must be called during execution of \ref Cy_SysPm_Hibernate. To trigger the
* callback execution, the callback must be registered before calling the * callback execution, the callback must be registered before calling the
* mode transition function. Refer to SysPm driver for more information about * power mode transition function. Refer to \ref group_syspm driver for more
* low-power mode transitions. * information about power mode transitions and callback registration.
*
* \note
* Only applicable for <b>rev-08 of the CY8CKIT-062-BLE</b>.
* For proper operation, when the I2C slave is configured to be a wakeup
* source from Deep Sleep mode, the \ref Cy_SCB_I2C_DeepSleepCallback must be
* copied and modified. Refer to the function description to get the details.
* *
* \section group_scb_i2c_more_information More Information * \section group_scb_i2c_more_information More Information
*
* For more information on the SCB peripheral, refer to the technical reference * For more information on the SCB peripheral, refer to the technical reference
* manual (TRM). * manual (TRM).
* *
@ -136,7 +257,7 @@
* <td>The functions \ref Cy_SCB_I2C_DeepSleepCallback and * <td>The functions \ref Cy_SCB_I2C_DeepSleepCallback and
* \ref Cy_SCB_I2C_HibernateCallback are callback of * \ref Cy_SCB_I2C_HibernateCallback are callback of
* \ref cy_en_syspm_status_t type. The cast operation safety in these * \ref cy_en_syspm_status_t type. The cast operation safety in these
* functions becomes the user responsibility because pointers are * functions becomes the user's responsibility because pointers are
* initialized when callback is registered in SysPm driver.</td> * initialized when callback is registered in SysPm driver.</td>
* </tr> * </tr>
* <tr> * <tr>
@ -173,7 +294,7 @@
* function.</td> * function.</td>
* <td>The functions can return from several points. This is done to improve * <td>The functions can return from several points. This is done to improve
* code clarity when returning error status code if input parameters * code clarity when returning error status code if input parameters
* validation is failed.</td> * validation fails.</td>
* </tr> * </tr>
* </table> * </table>
* *
@ -181,7 +302,56 @@
* <table class="doxtable"> * <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr> * <tr>
* <td rowspan="3"> 2.0</td> * <td rowspan="4"> 2.10</td>
* <td>Fixed the ReStart condition generation sequence for a write
* transaction in the \ref Cy_SCB_I2C_MasterWrite function.</td>
* <td>The driver can notify about a zero length write transaction completion
* before the address byte is sent if the \ref Cy_SCB_I2C_MasterWrite
* function execution was interrupted between setting the restart
* generation command and writing the address byte into the TX FIFO.</td>
* </tr>
* <tr>
* <td>Added the slave- and master-specific interrupt functions:
* \ref Cy_SCB_I2C_SlaveInterrupt and \ref Cy_SCB_I2C_MasterInterrupt.
* </td>
* <td>Improved the interrupt configuration options for the I2C slave and
* master mode configurations.</td>
* </tr>
* <tr>
* <td>Updated the Start condition generation sequence in the \ref
* Cy_SCB_I2C_MasterWrite and \ref Cy_SCB_I2C_MasterRead.</td>
* <td></td>
* </tr>
* <tr>
* <td>Updated the ReStart condition generation sequence for a write
* transaction in the \ref Cy_SCB_I2C_MasterSendReStart function.</td>
* <td></td>
* </tr>
* <tr>
* <td rowspan="5"> 2.0</td>
* <td>Fixed the \ref Cy_SCB_I2C_MasterSendReStart function to properly
* generate the ReStart condition when the previous transaction was
* a write.</td>
* <td>The master interpreted the address byte written into the TX FIFO as a
* data byte and continued a write transaction. The ReStart condition was
* generated after the master completed transferring the data byte.
* The SCL line was stretched by the master waiting for the address byte
* to be written into the TX FIFO after the ReStart condition generation.
* The following timeout detection released the bus from the master
* control.</td>
* </tr>
* <tr>
* <td>Fixed the slave operation after the address byte was NACKed by the
* firmware.</td>
* <td>The observed slave operation failure depends on whether Level 2 assert
* is enabled or not. Enabled: the device stuck in the fault handler due
* to the assert assignment in the \ref Cy_SCB_I2C_Interrupt. Disabled:
* the slave sets the transaction completion status and notifies on the
* transaction completion event after the address was NACKed. The failure
* is observed only when the slave is configured to accept an address in
* the RX FIFO.</td>
* </tr>
* <tr>
* <td>Added parameters validation for public API.</td> * <td>Added parameters validation for public API.</td>
* <td></td> * <td></td>
* </tr> * </tr>
@ -245,8 +415,8 @@ typedef enum
/** /**
* The master is not ready to start a new transaction. * The master is not ready to start a new transaction.
* Either the master is still processing a previous transaction or in the * Either the master is still processing a previous transaction or in the
* master-slave mode the slave operation is in progress. Call this function * master-slave mode, the slave operation is in progress. Call this function
* again once that operation is completed or aborted. * again after that operation is completed or aborted.
*/ */
CY_SCB_I2C_MASTER_NOT_READY = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 2U), CY_SCB_I2C_MASTER_NOT_READY = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 2U),
@ -334,7 +504,7 @@ typedef void (* cy_cb_scb_i2c_handle_events_t)(uint32_t event);
* \ref group_scb_i2c_macros_addr_callback_events. * \ref group_scb_i2c_macros_addr_callback_events.
* This callback must return a decision to ACK (continue transaction) or * This callback must return a decision to ACK (continue transaction) or
* NAK (end transaction) the received address. * NAK (end transaction) the received address.
* Note if the slave configured to accept an address in RX FIFO, it must read * Note if the slave is configured to accept an address in RX FIFO, it must read
* from it using the \ref Cy_SCB_ReadRxFifo function. * from it using the \ref Cy_SCB_ReadRxFifo function.
*/ */
typedef cy_en_scb_i2c_command_t (* cy_cb_scb_i2c_handle_addr_t)(uint32_t event); typedef cy_en_scb_i2c_command_t (* cy_cb_scb_i2c_handle_addr_t)(uint32_t event);
@ -354,20 +524,20 @@ typedef struct cy_stc_scb_i2c_config
* FIFO when it has some number of bytes (typically, when it is half full). * FIFO when it has some number of bytes (typically, when it is half full).
* * If this option is disabled, the interrupt is enabled to take data out of * * If this option is disabled, the interrupt is enabled to take data out of
* the RX FIFO when a byte is available. Also, hardware does not * the RX FIFO when a byte is available. Also, hardware does not
* automatically ACK the data, firmware must tell the hardware to ACK * automatically ACK the data. Firmware must tell the hardware to ACK
* the byte (so each byte requires interrupt processing). * the byte (so each byte requires interrupt processing).
* \n <b>Typically, this option should be enabled</b> to configure hardware to * \n <b>Typically, this option should be enabled</b> to configure hardware to
* automatically ACK incoming data. Otherwise hardware might not get the command * automatically ACK incoming data. Otherwise hardware might not get the command
* to ACK or NACK a byte fast enough, and clock stretching is applied * to ACK or NACK a byte fast enough, and clock stretching is applied
* (the transaction is delayed) until command is set. When this option is * (the transaction is delayed) until the command is set. When this option is
* enabled the number of interrupts required to process the transaction * enabled, the number of interrupts required to process the transaction
* is significantly reduced because several bytes are handled at once. * is significantly reduced because several bytes are handled at once.
* \n <b>However, there is a side effect:</b> * \n <b>However, there is a side effect:</b>
* * For master mode, the drawback is that the master may receive more * * For master mode, the drawback is that the master may receive more
* data than desired due to the interrupt latency. An interrupt fires * data than desired due to the interrupt latency. An interrupt fires
* when the second-to-last byte has been received. This interrupt tells * when the second-to-last byte has been received. This interrupt tells
* the hardware to stop receiving data. If the latency of this interrupt * the hardware to stop receiving data. If the latency of this interrupt
* is longer than one transfer of the byte on the I2C bus, then the * is longer than one transaction of the byte on the I2C bus, then the
* hardware automatically ACKs the following bytes until the interrupt * hardware automatically ACKs the following bytes until the interrupt
* is serviced or the RX FIFO becomes full. * is serviced or the RX FIFO becomes full.
* * For slave mode, the drawback is that the slave only NACKs * * For slave mode, the drawback is that the slave only NACKs
@ -389,14 +559,14 @@ typedef struct cy_stc_scb_i2c_config
* (so each byte requires interrupt processing). * (so each byte requires interrupt processing).
* \n <b>Typically, this option should be enabled</b> to keep the TX FIFO loaded with * \n <b>Typically, this option should be enabled</b> to keep the TX FIFO loaded with
* data and reduce the probability of clock stretching. When there is no data * data and reduce the probability of clock stretching. When there is no data
* to transfer, clock stretching is applied (the transaction is delayed) until * to transaction, clock stretching is applied (the transaction is delayed) until
* data is loaded. When this option is enabled the number of interrupts required * the data is loaded. When this option is enabled, the number of interrupts required
* to process the transaction is significantly reduced because several * to process the transaction is significantly reduced because several
* bytes are handled at once. * bytes are handled at once.
* \n <b>The drawback of enabling useTxFifo</b> is that the abort operation clears * \n <b>The drawback of enabling useTxFifo</b> is that the abort operation clears
* the TX FIFO. The TX FIFO clear operation also clears the shift * the TX FIFO. The TX FIFO clear operation also clears the shift
* register. As a result the shifter may be cleared in the middle of a byte * register. As a result the shifter may be cleared in the middle of a byte
* transfer, corrupting it. The remaining bits to transfer within the * transaction, corrupting it. The remaining bits to transaction within the
* corrupted byte are complemented with 1s. If this is an issue, * corrupted byte are complemented with 1s. If this is an issue,
* then do not enable this option. * then do not enable this option.
*/ */
@ -426,7 +596,7 @@ typedef struct cy_stc_scb_i2c_config
bool ackGeneralAddr; bool ackGeneralAddr;
/** /**
* When set, the slave will wake the device from deep sleep on an address * When set, the slave will wake the device from Deep Sleep on an address
* match (the device datasheet must be consulted to determine which SCBs * match (the device datasheet must be consulted to determine which SCBs
* support this mode) * support this mode)
*/ */
@ -437,7 +607,7 @@ typedef struct cy_stc_scb_i2c_config
* All fields for the context structure are internal. Firmware never reads or * All fields for the context structure are internal. Firmware never reads or
* writes these values. Firmware allocates the structure and provides the * writes these values. Firmware allocates the structure and provides the
* address of the structure to the driver in function calls. Firmware must * address of the structure to the driver in function calls. Firmware must
* ensure that the defined instance of this structure remains in scope while * ensure that the defined instance of this structure remains in scope
* while the drive is in use. * while the drive is in use.
*/ */
typedef struct cy_stc_scb_i2c_context typedef struct cy_stc_scb_i2c_context
@ -449,8 +619,8 @@ typedef struct cy_stc_scb_i2c_context
volatile uint32_t state; /**< The driver state */ volatile uint32_t state; /**< The driver state */
volatile uint32_t masterStatus; /**< The master status */ volatile uint32_t masterStatus; /**< The master status */
bool masterPause; /**< Stores how the master ends the transfer */ bool masterPause; /**< Stores how the master ends the transaction */
bool masterRdDir; /**< The direction of the master transfer */ bool masterRdDir; /**< The direction of the master transaction */
uint8_t *masterBuffer; /**< The pointer to the master buffer (either for a transmit or a receive operation) */ uint8_t *masterBuffer; /**< The pointer to the master buffer (either for a transmit or a receive operation) */
uint32_t masterBufferSize; /**< The current master buffer size */ uint32_t masterBufferSize; /**< The current master buffer size */
@ -590,6 +760,8 @@ cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterWriteByte (CySCB_Type *base, uint8_t by
* \{ * \{
*/ */
void Cy_SCB_I2C_Interrupt (CySCB_Type *base, cy_stc_scb_i2c_context_t *context); void Cy_SCB_I2C_Interrupt (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
void Cy_SCB_I2C_SlaveInterrupt (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
void Cy_SCB_I2C_MasterInterrupt (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
__STATIC_INLINE void Cy_SCB_I2C_RegisterEventCallback(CySCB_Type const *base, cy_cb_scb_i2c_handle_events_t callback, __STATIC_INLINE void Cy_SCB_I2C_RegisterEventCallback(CySCB_Type const *base, cy_cb_scb_i2c_handle_events_t callback,
cy_stc_scb_i2c_context_t *context); cy_stc_scb_i2c_context_t *context);
@ -621,7 +793,7 @@ cy_en_syspm_status_t Cy_SCB_I2C_HibernateCallback(cy_stc_syspm_callback_params_t
* may be set to indicate the current status. * may be set to indicate the current status.
* \{ * \{
*/ */
/** There is a Read transaction in progress */ /** There is a read transaction in progress */
#define CY_SCB_I2C_SLAVE_RD_BUSY (0x00000001UL) #define CY_SCB_I2C_SLAVE_RD_BUSY (0x00000001UL)
/** /**
@ -642,7 +814,7 @@ cy_en_syspm_status_t Cy_SCB_I2C_HibernateCallback(cy_stc_syspm_callback_params_t
*/ */
#define CY_SCB_I2C_SLAVE_RD_UNDRFL (0x00000008UL) #define CY_SCB_I2C_SLAVE_RD_UNDRFL (0x00000008UL)
/** There is a Write transaction in progress */ /** There is a write transaction in progress */
#define CY_SCB_I2C_SLAVE_WR_BUSY (0x00000010UL) #define CY_SCB_I2C_SLAVE_WR_BUSY (0x00000010UL)
/** /**
@ -656,11 +828,11 @@ cy_en_syspm_status_t Cy_SCB_I2C_HibernateCallback(cy_stc_syspm_callback_params_t
*/ */
#define CY_SCB_I2C_SLAVE_WR_OVRFL (0x00000040UL) #define CY_SCB_I2C_SLAVE_WR_OVRFL (0x00000040UL)
/** The slave lost arbitration, the transaction was aborted */ /** The slave lost arbitration, and the transaction was aborted */
#define CY_SCB_I2C_SLAVE_ARB_LOST (0x00000080UL) #define CY_SCB_I2C_SLAVE_ARB_LOST (0x00000080UL)
/** /**
* The slave captured an error on the bus during a master transaction (sources * The slave captured an error on the bus during a master transaction (source
* of error is misplaced Start or Stop). * of error is misplaced Start or Stop).
*/ */
#define CY_SCB_I2C_SLAVE_BUS_ERR (0x00000100UL) #define CY_SCB_I2C_SLAVE_BUS_ERR (0x00000100UL)
@ -770,7 +942,7 @@ cy_en_syspm_status_t Cy_SCB_I2C_HibernateCallback(cy_stc_syspm_callback_params_t
#define CY_SCB_I2C_MASTER_RD_CMPLT_EVENT (0x00040000UL) #define CY_SCB_I2C_MASTER_RD_CMPLT_EVENT (0x00040000UL)
/** /**
* Indicates the I2C hardware detected an error. It occurs together with * Indicates the I2C hardware has detected an error. It occurs together with
* \ref CY_SCB_I2C_MASTER_RD_CMPLT_EVENT or \ref CY_SCB_I2C_MASTER_WR_CMPLT_EVENT * \ref CY_SCB_I2C_MASTER_RD_CMPLT_EVENT or \ref CY_SCB_I2C_MASTER_WR_CMPLT_EVENT
* depends on the direction of the transfer. * depends on the direction of the transfer.
* Check \ref Cy_SCB_I2C_MasterGetStatus to determine the source of the error. * Check \ref Cy_SCB_I2C_MasterGetStatus to determine the source of the error.
@ -995,7 +1167,7 @@ __STATIC_INLINE void Cy_SCB_I2C_Enable(CySCB_Type *base)
* Function Name: Cy_SCB_I2C_IsBusBusy * Function Name: Cy_SCB_I2C_IsBusBusy
****************************************************************************//** ****************************************************************************//**
* *
* Checks if the I2C bus is busy. * Checks whether the I2C bus is busy.
* *
* \param base * \param base
* The pointer to the I2C SCB instance. * The pointer to the I2C SCB instance.
@ -1182,7 +1354,7 @@ __STATIC_INLINE void Cy_SCB_I2C_MasterSetHighPhaseDutyCycle(CySCB_Type *base, ui
* \param context * \param context
* The pointer to context structure \ref cy_stc_scb_i2c_context_t allocated by * The pointer to context structure \ref cy_stc_scb_i2c_context_t allocated by
* the user. The structure is used while the I2C operation for internal * the user. The structure is used while the I2C operation for internal
* configuration and data keeping. The user should not modify anything in * configuration and data retention. The user should not modify anything in
* this structure. * this structure.
* *
* \note * \note
@ -1217,7 +1389,7 @@ __STATIC_INLINE void Cy_SCB_I2C_RegisterEventCallback(CySCB_Type const *base,
* \param context * \param context
* The pointer to context structure \ref cy_stc_scb_i2c_context_t allocated by * The pointer to context structure \ref cy_stc_scb_i2c_context_t allocated by
* the user. The structure is used during the I2C operation for internal * the user. The structure is used during the I2C operation for internal
* configuration and data keeping. The user should not modify anything in * configuration and data retention. The user should not modify anything in
* this structure. * this structure.
* *
* \note * \note

166
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/scb/cy_scb_spi.c → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_spi.c
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_scb_spi.c * \file cy_scb_spi.c
* \version 2.0 * \version 2.10
* *
* Provides SPI API implementation of the SCB driver. * Provides SPI API implementation of the SCB driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -38,9 +38,9 @@ static void DiscardArrayNoCheck(CySCB_Type const *base, uint32_t size);
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated * The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
* by the user. The structure is used during the SPI operation for internal * by the user. The structure is used during the SPI operation for internal
* configuration and data keeping. The user must not modify anything * configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* If only SPI functions which do not require context will be used pass NULL * If only SPI functions that do not require context will be used to pass NULL
* as pointer to context. * as pointer to context.
* *
* \return * \return
@ -53,7 +53,7 @@ static void DiscardArrayNoCheck(CySCB_Type const *base, uint32_t size);
cy_en_scb_spi_status_t Cy_SCB_SPI_Init(CySCB_Type *base, cy_stc_scb_spi_config_t const *config, cy_stc_scb_spi_context_t *context) cy_en_scb_spi_status_t Cy_SCB_SPI_Init(CySCB_Type *base, cy_stc_scb_spi_config_t const *config, cy_stc_scb_spi_context_t *context)
{ {
/* Input parameters verification */ /* Input parameters verification */
if ((NULL == base) && (NULL == config)) if ((NULL == base) || (NULL == config))
{ {
return CY_SCB_SPI_BAD_PARAM; return CY_SCB_SPI_BAD_PARAM;
} }
@ -156,7 +156,7 @@ cy_en_scb_spi_status_t Cy_SCB_SPI_Init(CySCB_Type *base, cy_stc_scb_spi_config_t
* Function Name: Cy_SCB_SPI_DeInit * Function Name: Cy_SCB_SPI_DeInit
****************************************************************************//** ****************************************************************************//**
* *
* De-initializes the SCB block, returns the register values to default. * De-initializes the SCB block; returns the register values to default.
* *
* \param base * \param base
* The pointer to the SPI SCB instance. * The pointer to the SPI SCB instance.
@ -193,9 +193,9 @@ void Cy_SCB_SPI_DeInit(CySCB_Type *base)
* Function Name: Cy_SCB_SPI_Disable * Function Name: Cy_SCB_SPI_Disable
****************************************************************************//** ****************************************************************************//**
* *
* Disables the SCB block, clears context statuses and disables * Disables the SCB block, clears context statuses, and disables
* TX and RX interrupt sources. * TX and RX interrupt sources.
* Note that after the block is disabled the TX and RX FIFOs and * Note that after the block is disabled, the TX and RX FIFOs and
* hardware statuses are cleared. Also, the hardware stops driving the output * hardware statuses are cleared. Also, the hardware stops driving the output
* and ignores the input. * and ignores the input.
* *
@ -205,16 +205,16 @@ void Cy_SCB_SPI_DeInit(CySCB_Type *base)
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated * The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
* by the user. The structure is used during the SPI operation for internal * by the user. The structure is used during the SPI operation for internal
* configuration and data keeping. The user must not modify anything * configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* If only SPI functions which do not require context will be used pass NULL * If only SPI functions that do not require context will be used to pass NULL
* as pointer to context. * as pointer to context.
* *
* \note * \note
* Calling this function when the SPI is busy (master preforms data transfer or * Calling this function when the SPI is busy (master preforms data transfer or
* slave communicates with the master) may cause transfer corruption because the * slave communicates with the master) may cause transfer corruption because the
* hardware stops driving the outputs and ignores the inputs. * hardware stops driving the outputs and ignores the inputs.
* It is recommenced to ensure that the SPI is not busy before calling this * Ensure that the SPI is not busy before calling this
* function. * function.
* *
*******************************************************************************/ *******************************************************************************/
@ -247,25 +247,34 @@ void Cy_SCB_SPI_Disable(CySCB_Type *base, cy_stc_scb_spi_context_t *context)
****************************************************************************//** ****************************************************************************//**
* *
* This function handles the transition of the SCB SPI into and out of * This function handles the transition of the SCB SPI into and out of
* Deep-Sleep mode. It prevents the device from entering Deep-Sleep if the * Deep Sleep mode. It prevents the device from entering Deep Sleep mode
* SPI slave or master is actively communicating, or there is any data in the * if the SPI slave or master is actively communicating, or there is any data
* TX or RX FIFOs. * in the TX or RX FIFOs.
* The following behavior of the SPI SCB depends on if the SCB block is * The following behavior of the SPI SCB depends on whether the SCB block is
* wakeup-capable or not: * wakeup-capable or not:
* * The SCB wakeup-capable: any transfer intended to the slave wakes up the * * The SCB is <b>wakeup-capable</b>: any transfer intended to the slave wakes up
* device from Deep-Sleep mode. The slave responds with 0xFF to the transfer. * the device from Deep Sleep mode. The slave responds with 0xFF to the transfer
* If the transfer occurs before the device enters Deep-Sleep mode, the device * and incoming data is ignored.
* will not enter Deep-Sleep mode and incoming data is stored in the RX FIFO, * If the transfer occurs before the device enters Deep Sleep mode, the device
* otherwise incoming data is ignored. * will not enter Deep Sleep mode and incoming data is stored in the RX FIFO.
* Only the SPI slave can be configured to be a wakeup source from Deep-Sleep * The SCB clock is disabled before entering Deep Sleep and enabled after the
* device exits Deep Sleep mode. The SCB clock must be enabled after exiting
* Deep Sleep mode and after the source of hf_clk[0] gets stable, this includes
* the FLL/PLL. The SysClk callback ensures that hf_clk[0] gets stable and
* it must be called before Cy_SCB_SPI_DeepSleepCallback. The SCB clock
* disabling may lead to corrupted data in the RX FIFO. Clear the RX FIFO
* after this callback is executed. If the transfer occurs before the device
* enters Deep Sleep mode, the device will not enter Deep Sleep mode and
* incoming data will be stored in the RX FIFO. \n
* Only the SPI slave can be configured to be a wakeup source from Deep Sleep
* mode. * mode.
* * The SCB is not wakeup-capable: the SPI is disabled. It is enabled when the * * The SCB is not <b>wakeup-capable</b>: the SPI is disabled. It is enabled when
* device failed to enter Deep-Sleep mode or it is awaken from Deep-Sleep mode. * the device fails to enter Deep Sleep mode or it is awakened from Deep Sleep
* During the SPI is disabled, it stops driving the outputs and ignores the * mode. While the SPI is disabled, it stops driving the outputs and ignores the
* inputs. Any incoming data is ignored. * inputs. Any incoming data is ignored.
* *
* This function can be called during execution of \ref Cy_SysPm_DeepSleep, * This function must be called during execution of \ref Cy_SysPm_DeepSleep.
* to do it, register this function as a callback before calling * To do it, register this function as a callback before calling
* \ref Cy_SysPm_DeepSleep : specify \ref CY_SYSPM_DEEPSLEEP as the callback * \ref Cy_SysPm_DeepSleep : specify \ref CY_SYSPM_DEEPSLEEP as the callback
* type and call \ref Cy_SysPm_RegisterCallback. * type and call \ref Cy_SysPm_RegisterCallback.
* *
@ -276,6 +285,13 @@ void Cy_SCB_SPI_Disable(CySCB_Type *base, cy_stc_scb_spi_context_t *context)
* \return * \return
* \ref cy_en_syspm_status_t * \ref cy_en_syspm_status_t
* *
* \note
* Only applicable for <b>rev-08 of the CY8CKIT-062-BLE</b>.
* For proper operation, when the SPI slave is configured to be a wakeup source
* from Deep Sleep mode, this function must be copied and modified by the user.
* The SPI clock disable code must be inserted in the \ref CY_SYSPM_BEFORE_TRANSITION
* and clock enable code in the \ref CY_SYSPM_AFTER_TRANSITION mode processing.
*
*******************************************************************************/ *******************************************************************************/
cy_en_syspm_status_t Cy_SCB_SPI_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams) cy_en_syspm_status_t Cy_SCB_SPI_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams)
{ {
@ -288,14 +304,14 @@ cy_en_syspm_status_t Cy_SCB_SPI_DeepSleepCallback(cy_stc_syspm_callback_params_t
{ {
case CY_SYSPM_CHECK_READY: case CY_SYSPM_CHECK_READY:
{ {
/* Check if the High-level API is not busy executing the transfer /* Check whether the High-level API is not busy executing the transfer
* operation. * operation.
*/ */
if (0UL == (CY_SCB_SPI_TRANSFER_ACTIVE & Cy_SCB_SPI_GetTransferStatus(locBase, locContext))) if (0UL == (CY_SCB_SPI_TRANSFER_ACTIVE & Cy_SCB_SPI_GetTransferStatus(locBase, locContext)))
{ {
/* If the SPI bus is not busy, all data elements are transferred /* If the SPI bus is not busy, all data elements are transferred
* on the bus from the TX FIFO and shifter and the RX FIFOs are * on the bus from the TX FIFO and shifter and the RX FIFOs are
* empty - the SPI is ready to enter Deep-Sleep mode. * empty - the SPI is ready to enter Deep Sleep mode.
*/ */
if (!Cy_SCB_SPI_IsBusBusy(locBase)) if (!Cy_SCB_SPI_IsBusBusy(locBase))
{ {
@ -323,8 +339,8 @@ cy_en_syspm_status_t Cy_SCB_SPI_DeepSleepCallback(cy_stc_syspm_callback_params_t
/* The SCB is NOT wakeup-capable: disable the /* The SCB is NOT wakeup-capable: disable the
* SPI. The master and slave stop driving the * SPI. The master and slave stop driving the
* bus until the SPI is enabled. This happens * bus until the SPI is enabled. This happens
* when the device failed to enter Deep-Sleep * when the device fails to enter Deep Sleep
* mode or it is awaken from Deep-Sleep mode. * mode or it is awakened from Deep Sleep mode.
*/ */
Cy_SCB_SPI_Disable(locBase, locContext); Cy_SCB_SPI_Disable(locBase, locContext);
@ -339,7 +355,7 @@ cy_en_syspm_status_t Cy_SCB_SPI_DeepSleepCallback(cy_stc_syspm_callback_params_t
case CY_SYSPM_CHECK_FAIL: case CY_SYSPM_CHECK_FAIL:
{ {
/* The other driver is not ready for Deep-Sleep mode. Restore /* The other driver is not ready for Deep Sleep mode. Restore
* Active mode configuration. * Active mode configuration.
*/ */
@ -357,7 +373,7 @@ cy_en_syspm_status_t Cy_SCB_SPI_DeepSleepCallback(cy_stc_syspm_callback_params_t
{ {
/* This code executes inside the critical section and enabling the /* This code executes inside the critical section and enabling the
* active interrupt source makes the interrupt pending in the NVIC. * active interrupt source makes the interrupt pending in the NVIC.
* However, the interrupt processing is delayed until the code exists * However, the interrupt processing is delayed until the code exits
* the critical section. The pending interrupt force WFI instruction * the critical section. The pending interrupt force WFI instruction
* does nothing and the device remains in Active mode. * does nothing and the device remains in Active mode.
*/ */
@ -365,10 +381,19 @@ cy_en_syspm_status_t Cy_SCB_SPI_DeepSleepCallback(cy_stc_syspm_callback_params_t
if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL)) if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL))
{ {
/* The SCB is wakeup-capable: enable the SPI wakeup interrupt /* The SCB is wakeup-capable: enable the SPI wakeup interrupt
* source. If any transaction happened, the wakeup interrupt * source. If any transaction happens, the wakeup interrupt
* becomes pending and prevents entering Deep-Sleep mode. * becomes pending and prevents entering Deep Sleep mode.
*/ */
Cy_SCB_SetSpiInterruptMask(locBase, CY_SCB_I2C_INTR_WAKEUP); Cy_SCB_SetSpiInterruptMask(locBase, CY_SCB_I2C_INTR_WAKEUP);
/* Disable SCB clock */
locBase->I2C_CFG &= (uint32_t) ~CY_SCB_I2C_CFG_CLK_ENABLE_Msk;
/* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
* for proper entering Deep Sleep mode the SPI clock must be disabled.
* This code must be inserted by the user because the driver
* does not have access to the clock.
*/
} }
retStatus = CY_SYSPM_SUCCESS; retStatus = CY_SYSPM_SUCCESS;
@ -379,6 +404,15 @@ cy_en_syspm_status_t Cy_SCB_SPI_DeepSleepCallback(cy_stc_syspm_callback_params_t
{ {
if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL)) if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL))
{ {
/* Enable SCB clock */
locBase->I2C_CFG |= CY_SCB_I2C_CFG_CLK_ENABLE_Msk;
/* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
* for proper exiting Deep Sleep mode, the SPI clock must be enabled.
* This code must be inserted by the user because the driver
* does not have access to the clock.
*/
/* The SCB is wakeup-capable: disable the SPI wakeup interrupt /* The SCB is wakeup-capable: disable the SPI wakeup interrupt
* source * source
*/ */
@ -407,15 +441,15 @@ cy_en_syspm_status_t Cy_SCB_SPI_DeepSleepCallback(cy_stc_syspm_callback_params_t
****************************************************************************//** ****************************************************************************//**
* *
* This function handles the transition of the SCB SPI into Hibernate mode. * This function handles the transition of the SCB SPI into Hibernate mode.
* It prevents the device from entering Hibernate mode if the SPI slave or master * It prevents the device from entering Hibernate mode if the SPI slave or
* is actively communicating, or there is any data in the TX or RX FIFOs. * master is actively communicating, or there is any data in the TX or RX FIFOs.
* If the SPI is ready to enter Hibernate mode, it is disabled. If the device * If the SPI is ready to enter Hibernate mode, it is disabled. If the device
* failed to enter Hibernate mode, the SPI is enabled. During the SPI is * failed to enter Hibernate mode, the SPI is enabled. While the SPI is
* disabled, it stops driving the outputs and ignores the inputs. * disabled, it stops driving the outputs and ignores the inputs.
* Any incoming data is ignored. * Any incoming data is ignored.
* *
* This function can be called during execution of \ref Cy_SysPm_Hibernate, * This function must be called during execution of \ref Cy_SysPm_Hibernate.
* to do it, register this function as a callback before calling * To do it, register this function as a callback before calling
* \ref Cy_SysPm_Hibernate : specify \ref CY_SYSPM_HIBERNATE as the callback * \ref Cy_SysPm_Hibernate : specify \ref CY_SYSPM_HIBERNATE as the callback
* type and call \ref Cy_SysPm_RegisterCallback. * type and call \ref Cy_SysPm_RegisterCallback.
* *
@ -438,7 +472,7 @@ cy_en_syspm_status_t Cy_SCB_SPI_HibernateCallback(cy_stc_syspm_callback_params_t
{ {
case CY_SYSPM_CHECK_READY: case CY_SYSPM_CHECK_READY:
{ {
/* Check if the High-level API is not busy executing the transfer /* Check whether the High-level API is not busy executing the transfer
* operation. * operation.
*/ */
if (0UL == (CY_SCB_SPI_TRANSFER_ACTIVE & Cy_SCB_SPI_GetTransferStatus(locBase, locContext))) if (0UL == (CY_SCB_SPI_TRANSFER_ACTIVE & Cy_SCB_SPI_GetTransferStatus(locBase, locContext)))
@ -470,7 +504,7 @@ cy_en_syspm_status_t Cy_SCB_SPI_HibernateCallback(cy_stc_syspm_callback_params_t
case CY_SYSPM_CHECK_FAIL: case CY_SYSPM_CHECK_FAIL:
{ {
/* The other driver is not ready for Deep-Sleep mode. Restore Active /* The other driver is not ready for Hibernate mode. Restore Active
* mode configuration. * mode configuration.
*/ */
@ -516,14 +550,14 @@ cy_en_syspm_status_t Cy_SCB_SPI_HibernateCallback(cy_stc_syspm_callback_params_t
* If the data that will be received is not important, pass NULL as rxBuffer. * If the data that will be received is not important, pass NULL as rxBuffer.
* If the data that will be transmitted is not important, pass NULL as txBuffer * If the data that will be transmitted is not important, pass NULL as txBuffer
* and then the \ref CY_SCB_SPI_DEFAULT_TX is sent out as each data element. * and then the \ref CY_SCB_SPI_DEFAULT_TX is sent out as each data element.
* Note that passing NULL as rxBuffer and txBuffer considered invalid case. * Note that passing NULL as rxBuffer and txBuffer are considered invalid cases.
* *
* After the function configures TX and RX interrupt sources, it returns and * After the function configures TX and RX interrupt sources, it returns and
* \ref Cy_SCB_SPI_Interrupt manages further data transfer. * \ref Cy_SCB_SPI_Interrupt manages further data transfer.
* *
* * In the master mode, the transfer operation is started after calling this * * In the master mode, the transfer operation starts after calling this
* function * function
* * In the slave mode, the transfer is registered and will be started when * * In the slave mode, the transfer registers and will start when
* the master request arrives. * the master request arrives.
* *
* When the transfer operation is completed (requested number of data elements * When the transfer operation is completed (requested number of data elements
@ -535,12 +569,12 @@ cy_en_syspm_status_t Cy_SCB_SPI_HibernateCallback(cy_stc_syspm_callback_params_t
* *
* \param txBuffer * \param txBuffer
* The pointer of the buffer with data to transmit. * The pointer of the buffer with data to transmit.
* The item size is defined by the data type which depends on the configured * The item size is defined by the data type that depends on the configured
* TX data width. * TX data width.
* *
* \param rxBuffer * \param rxBuffer
* The pointer to the buffer to store received data. * The pointer to the buffer to store received data.
* The item size is defined by the data type which depends on the configured * The item size is defined by the data type that depends on the configured
* RX data width. * RX data width.
* *
* \param size * \param size
@ -549,14 +583,14 @@ cy_en_syspm_status_t Cy_SCB_SPI_HibernateCallback(cy_stc_syspm_callback_params_t
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated * The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
* by the user. The structure is used during the SPI operation for internal * by the user. The structure is used during the SPI operation for internal
* configuration and data keeping. The user must not modify anything * configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
* \return * \return
* \ref cy_en_scb_spi_status_t * \ref cy_en_scb_spi_status_t
* *
* \note * \note
* * The buffers must not be modified and stay allocated until the end of the * * The buffers must not be modified and must stay allocated until the end of the
* transfer. * transfer.
* * This function overrides all RX and TX FIFO interrupt sources and changes * * This function overrides all RX and TX FIFO interrupt sources and changes
* the RX and TX FIFO level. * the RX and TX FIFO level.
@ -571,7 +605,7 @@ cy_en_scb_spi_status_t Cy_SCB_SPI_Transfer(CySCB_Type *base, void *txBuffer, voi
cy_en_scb_spi_status_t retStatus = CY_SCB_SPI_TRANSFER_BUSY; cy_en_scb_spi_status_t retStatus = CY_SCB_SPI_TRANSFER_BUSY;
/* Check if there are no active transfer requests */ /* Check whether there are no active transfer requests */
if (0UL == (CY_SCB_SPI_TRANSFER_ACTIVE & context->status)) if (0UL == (CY_SCB_SPI_TRANSFER_ACTIVE & context->status))
{ {
uint32_t fifoSize = Cy_SCB_GetFifoSize(base); uint32_t fifoSize = Cy_SCB_GetFifoSize(base);
@ -640,20 +674,20 @@ cy_en_scb_spi_status_t Cy_SCB_SPI_Transfer(CySCB_Type *base, void *txBuffer, voi
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated * The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
* by the user. The structure is used during the SPI operation for internal * by the user. The structure is used during the SPI operation for internal
* configuration and data keeping. The user must not modify anything * configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
* \note * \note
* In the slave mode and after abort of transfer operation master continue * In the slave mode and after abort of transfer operation master continue
* sending data it gets into RX FIFO and TX FIFO is underflow as there is * sending data it gets into RX FIFO and TX FIFO is underflow as there is
* nothing to send. To drop this data, RX FIFO has to be cleared when * nothing to send. To drop this data, RX FIFO must be cleared when
* the transfer is completed. Otherwise, received data will be kept and * the transfer is complete. Otherwise, received data will be kept and
* copied to the buffer when \ref Cy_SCB_SPI_Transfer is called. * copied to the buffer when \ref Cy_SCB_SPI_Transfer is called.
* *
* \sideeffect * \sideeffect
* The transmit FIFO clear operation also clears the shift register, so that * The transmit FIFO clear operation also clears the shift register, so that
* the shifter could be cleared in the middle of a data element transfer, * the shifter can be cleared in the middle of a data element transfer,
* corrupting it. The data element corruption means that all bits which has * corrupting it. The data element corruption means that all bits that have
* not been transmitted are transmitted as "ones" on the bus. * not been transmitted are transmitted as "ones" on the bus.
* *
*******************************************************************************/ *******************************************************************************/
@ -695,7 +729,7 @@ void Cy_SCB_SPI_AbortTransfer(CySCB_Type *base, cy_stc_scb_spi_context_t *contex
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated * The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
* by the user. The structure is used during the SPI operation for internal * by the user. The structure is used during the SPI operation for internal
* configuration and data keeping. The user must not modify anything * configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
* \return * \return
@ -725,7 +759,7 @@ uint32_t Cy_SCB_SPI_GetNumTransfered(CySCB_Type const *base, cy_stc_scb_spi_cont
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated * The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
* by the user. The structure is used during the SPI operation for internal * by the user. The structure is used during the SPI operation for internal
* configuration and data keeping. The user must not modify anything * configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
* \return * \return
@ -751,7 +785,7 @@ uint32_t Cy_SCB_SPI_GetTransferStatus(CySCB_Type const *base, cy_stc_scb_spi_con
* *
* This is the interrupt function for the SCB configured in the SPI mode. * This is the interrupt function for the SCB configured in the SPI mode.
* This function must be called inside the user-defined interrupt service * This function must be called inside the user-defined interrupt service
* routine in order for \ref Cy_SCB_SPI_Transfer to work. * routine for \ref Cy_SCB_SPI_Transfer to work.
* *
* \param base * \param base
* The pointer to the SPI SCB instance. * The pointer to the SPI SCB instance.
@ -759,13 +793,13 @@ uint32_t Cy_SCB_SPI_GetTransferStatus(CySCB_Type const *base, cy_stc_scb_spi_con
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated * The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
* by the user. The structure is used during the SPI operation for internal * by the user. The structure is used during the SPI operation for internal
* configuration and data keeping. The user must not modify anything * configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
*******************************************************************************/ *******************************************************************************/
void Cy_SCB_SPI_Interrupt(CySCB_Type *base, cy_stc_scb_spi_context_t *context) void Cy_SCB_SPI_Interrupt(CySCB_Type *base, cy_stc_scb_spi_context_t *context)
{ {
uint32 locXferErr = 0UL; bool locXferErr = false;
/* Wake up on the slave select condition */ /* Wake up on the slave select condition */
if (0UL != (CY_SCB_SPI_INTR_WAKEUP & Cy_SCB_GetSpiInterruptStatusMasked(base))) if (0UL != (CY_SCB_SPI_INTR_WAKEUP & Cy_SCB_GetSpiInterruptStatusMasked(base)))
@ -776,7 +810,7 @@ void Cy_SCB_SPI_Interrupt(CySCB_Type *base, cy_stc_scb_spi_context_t *context)
/* The slave error condition */ /* The slave error condition */
if (0UL != (CY_SCB_SLAVE_INTR_SPI_BUS_ERROR & Cy_SCB_GetSlaveInterruptStatusMasked(base))) if (0UL != (CY_SCB_SLAVE_INTR_SPI_BUS_ERROR & Cy_SCB_GetSlaveInterruptStatusMasked(base)))
{ {
locXferErr = CY_SCB_SPI_TRANSFER_ERR; locXferErr = true;
context->status |= CY_SCB_SPI_SLAVE_TRANSFER_ERR; context->status |= CY_SCB_SPI_SLAVE_TRANSFER_ERR;
Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_SLAVE_INTR_SPI_BUS_ERROR); Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_SLAVE_INTR_SPI_BUS_ERROR);
@ -785,7 +819,7 @@ void Cy_SCB_SPI_Interrupt(CySCB_Type *base, cy_stc_scb_spi_context_t *context)
/* The RX overflow error condition */ /* The RX overflow error condition */
if (0UL != (CY_SCB_RX_INTR_OVERFLOW & Cy_SCB_GetRxInterruptStatusMasked(base))) if (0UL != (CY_SCB_RX_INTR_OVERFLOW & Cy_SCB_GetRxInterruptStatusMasked(base)))
{ {
locXferErr = CY_SCB_SPI_TRANSFER_ERR; locXferErr = true;
context->status |= CY_SCB_SPI_TRANSFER_OVERFLOW; context->status |= CY_SCB_SPI_TRANSFER_OVERFLOW;
Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_OVERFLOW); Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_OVERFLOW);
@ -794,18 +828,18 @@ void Cy_SCB_SPI_Interrupt(CySCB_Type *base, cy_stc_scb_spi_context_t *context)
/* The TX underflow error condition or slave complete data transfer */ /* The TX underflow error condition or slave complete data transfer */
if (0UL != (CY_SCB_TX_INTR_UNDERFLOW & Cy_SCB_GetTxInterruptStatusMasked(base))) if (0UL != (CY_SCB_TX_INTR_UNDERFLOW & Cy_SCB_GetTxInterruptStatusMasked(base)))
{ {
locXferErr = CY_SCB_SPI_TRANSFER_ERR; locXferErr = true;
context->status |= CY_SCB_SPI_TRANSFER_UNDERFLOW; context->status |= CY_SCB_SPI_TRANSFER_UNDERFLOW;
Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UNDERFLOW); Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UNDERFLOW);
} }
/* Report an error, use a callback */ /* Report an error, use a callback */
if (0UL != locXferErr) if (locXferErr)
{ {
if (NULL != context->cbEvents) if (NULL != context->cbEvents)
{ {
context->cbEvents(CY_SCB_SPI_TRANSFER_ERR); context->cbEvents(CY_SCB_SPI_TRANSFER_ERR_EVENT);
} }
} }
@ -854,7 +888,7 @@ void Cy_SCB_SPI_Interrupt(CySCB_Type *base, cy_stc_scb_spi_context_t *context)
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated * The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
* by the user. The structure is used during the SPI operation for internal * by the user. The structure is used during the SPI operation for internal
* configuration and data keeping. The user must not modify anything * configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
*******************************************************************************/ *******************************************************************************/
@ -919,7 +953,7 @@ static void HandleReceive(CySCB_Type *base, cy_stc_scb_spi_context_t *context)
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated * The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
* by the user. The structure is used during the SPI operation for internal * by the user. The structure is used during the SPI operation for internal
* configuration and data keeping. The user must not modify anything * configuration and data retention. The user must not modify anything
* in this structure. * in this structure.
* *
*******************************************************************************/ *******************************************************************************/

241
targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/scb/cy_scb_spi.h → targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_spi.h
View File

@ -1,12 +1,12 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy_scb_spi.h * \file cy_scb_spi.h
* \version 2.0 * \version 2.10
* *
* Provides SPI API declarations of the SCB driver. * Provides SPI API declarations of the SCB driver.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, * You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying * disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided. * the software package with which this file was provided.
@ -27,31 +27,101 @@
* data widths. * data widths.
* *
* \section group_scb_spi_configuration Configuration Considerations * \section group_scb_spi_configuration Configuration Considerations
* The SPI driver configuration can be divided to number of sequential
* steps listed below:
* * \ref group_scb_spi_config
* * \ref group_scb_spi_pins
* * \ref group_scb_spi_clock
* * \ref group_scb_spi_data_rate
* * \ref group_scb_spi_intr
* * \ref group_scb_spi_enable
* *
* To set up an SPI, provide configuration parameters in the * \note
* The SPI driver is built on top of the SCB hardware block. The SCB1 instance is
* used as an example for all code snippets. Modify the code to match your
* design.
*
* \subsection group_scb_spi_config Configure SPI
* To set up the SPI slave driver, provide the configuration parameters in the
* \ref cy_stc_scb_spi_config_t structure. For example: provide spiMode, * \ref cy_stc_scb_spi_config_t structure. For example: provide spiMode,
* subMode, sclkMode, oversample, rxDataWidth, and txDataWidth. The other * subMode, sclkMode, oversample, rxDataWidth, and txDataWidth. The other
* parameters are optional for operation. To initialize the driver, * parameters are optional for operation. To initialize the driver, call
* call the \ref Cy_SCB_SPI_Init function providing the filled * \ref Cy_SCB_SPI_Init function providing a pointer to the filled
* \ref cy_stc_scb_spi_config_t structure and allocated * \ref cy_stc_scb_spi_config_t structure and allocated \ref cy_stc_scb_spi_context_t.
* \ref cy_stc_scb_spi_context_t. To get the SPI operate with the desired data rate
* the SCB clock and SCLK duration (only applicable for master mode) must be
* configured. Use the SysClk driver API to configure the SCB clock frequency and
* initialize the oversample parameter in the \ref cy_stc_scb_spi_config_t
* structure to set SCLK duration. Refer to the technical reference
* manual (TRM) to get more information on how to configure the SPI to operate
* with the desired data rate. Call \ref Cy_SCB_SPI_Enable to start the SPI
* operation after configuration is completed.
* *
* The SPI API are the same for the master and slave mode operation and * \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_CFG
* are divided into two categories: \ref group_scb_spi_low_level_functions
* and \ref group_scb_spi_high_level_functions. Do not mix high-level and
* low-level API because a low-level API can adversely affect the operation
* of a higher level API.
* *
* The \ref group_scb_spi_low_level_functions API's functions allow * \subsection group_scb_spi_pins Assign and Configure Pins
* interacting directly with the hardware and do not use interrupts. * Only dedicated SCB pins can be used for SPI operation. The HSIOM
* These functions do not require context for operation, thus NULL can be * register must be configured to connect block to the pins. Also the SPI output
* pins must be configured in Strong Drive mode and SPI input pins in
* Digital High-Z:
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_CFG_PINS
*
* \note
* The SCB stops driving pins when it is disabled or enters low power mode (except
* Alternate Active or Sleep). To keep the pins' states, they should be reconfigured or
* be frozen.
*
* \subsection group_scb_spi_clock Assign Clock Divider
* The clock source must be connected to the SCB block to oversample input and
* output signals. You must use one of the 8-bit or 16-bit dividers <em><b>(the
* source clock of this divider must be Clk_Peri)</b></em>. Use the
* \ref group_sysclk driver API to do that.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_CFG_ASSIGN_CLOCK
*
* \subsection group_scb_spi_data_rate Configure Data Rate
* To get the SPI slave to operate with the desired data rate, the source clock must be
* fast enough to provide sufficient oversampling. Therefore, the clock divider
* must be configured to provide desired clock frequency. Use the
* \ref group_sysclk driver API to do that.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_CFG_DATA_RATE_SLAVE
*
* To get the SPI master to operate with the desired data rate, the source clock frequency
* and the SCLK (SPI clock) period must be configured. Use the
* \ref group_sysclk driver API to configure source clock frequency. Set the
* <em><b>oversample parameter in configuration structure</b></em> to define number of SCB
* clocks in one SCLK period. When this value is even, the first and second phases
* of the SCLK period are the same. Otherwise, the first phase is one SCB clock
* cycle longer than the second phase. The level of the first phase of the clock
* period depends on CPOL settings: 0 - low level and 1 - high level.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_CFG_DATA_RATE_MASTER
*
* Refer to the technical reference manual (TRM) section SPI sub-section
* Oversampling and Bit Rate to get information about how to configure SPI to run with
* desired data rate.
*
* \subsection group_scb_spi_intr Configure Interrupt
* The interrupt is optional for the SPI operation. To configure the interrupt,
* the \ref Cy_SCB_SPI_Interrupt function must be called in the interrupt
* handler for the selected SCB instance. Also, this interrupt must be enabled
* in the NVIC.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_INTR_A
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_INTR_B
*
* \subsection group_scb_spi_enable Enable SPI
* Finally, enable the SPI operation calling \ref Cy_SCB_SPI_Enable.
* For the slave, this means that SPI device starts respond to the transfers.
* For the master, it is ready to execute transfers.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_ENABLE
*
* \section group_scb_spi_use_cases Common Use Cases
* The SPI API is the same for the master and slave mode operation and
* is divided into two categories: \ref group_scb_spi_low_level_functions
* and \ref group_scb_spi_high_level_functions. \n
* <em>Do not mix <b>High-Level</b> and <b>Low-Level</b> API because a Low-Level
* API can adversely affect the operation of a High-Level API.</em>
*
* \subsection group_scb_spi_ll Low-Level API
* The \ref group_scb_spi_low_level_functions API allows
* interacting directly with the hardware and do not use interrupt.
* These functions do not require context for operation. Thus, NULL can be
* passed in \ref Cy_SCB_SPI_Init and \ref Cy_SCB_SPI_Disable instead of * passed in \ref Cy_SCB_SPI_Init and \ref Cy_SCB_SPI_Disable instead of
* a pointer to the context structure. * a pointer to the context structure.
* *
@ -66,37 +136,99 @@
* *
* * The statuses can be polled using: \ref Cy_SCB_SPI_GetRxFifoStatus, * * The statuses can be polled using: \ref Cy_SCB_SPI_GetRxFifoStatus,
* \ref Cy_SCB_SPI_GetTxFifoStatus and \ref Cy_SCB_SPI_GetSlaveMasterStatus. * \ref Cy_SCB_SPI_GetTxFifoStatus and \ref Cy_SCB_SPI_GetSlaveMasterStatus.
* The statuses are W1C (Write 1 to Clear) and after a status is set, * <em>The statuses are <b>W1C (Write 1 to Clear)</b> and after a status
* it must be cleared. Note that there are statuses evaluated as level. These * is set, it must be cleared.</em> Note that there are statuses evaluated as level.
* statuses remain set when an event is true. Therefore, after the clear * These statuses remain set until an event is true. Therefore, after the clear
* operation, the status is cleared but then it is restored (if event is still * operation, the status is cleared but then it is restored (if the event is still
* true). * true).
* For example: the TX FIFO empty interrupt source can be cleared when the * For example: the TX FIFO empty interrupt source can be cleared when the
* TX FIFO is not empty. Put at least two data elements (one goes to the * TX FIFO is not empty. Put at least two data elements (one goes to the
* shifter and next to FIFO) before clearing this status. * shifter and next to FIFO) before clearing this status. \n
* Also, following functions can be used for polling as well
* \ref Cy_SCB_SPI_IsBusBusy, \ref Cy_SCB_SPI_IsTxComplete,
* \ref Cy_SCB_SPI_GetNumInRxFifo and \ref Cy_SCB_SPI_GetNumInTxFifo.
* *
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_TRANFER_DATA_LL
*
* \subsection group_scb_spi_hl High-Level API
* The \ref group_scb_spi_high_level_functions API uses an interrupt to execute * The \ref group_scb_spi_high_level_functions API uses an interrupt to execute
* a transfer. Call \ref Cy_SCB_SPI_Transfer to start communication: for the * a transfer. Call \ref Cy_SCB_SPI_Transfer to start communication: for the
* master mode a transfer to the slave is started while for the slave mode * master mode, a transfer to the slave starts but for the slave mode,
* the Read and Write buffers are prepared for the following communication * the Read and Write buffers are prepared for the following communication
* with the master. * with the master.
* After a transfer is started, the \ref Cy_SCB_SPI_Interrupt handles the * After a transfer is started, the \ref Cy_SCB_SPI_Interrupt handles the
* transfer until its completion. Therefore it must be called inside the * transfer until its completion. Therefore, it must be called inside the
* user interrupt handler to make the high-level API work. To monitor the status * user interrupt handler to make the High-Level API work. To monitor the status
* of the transfer operation, use \ref Cy_SCB_SPI_GetTransferStatus. * of the transfer operation, use \ref Cy_SCB_SPI_GetTransferStatus.
* Alternately, use \ref Cy_SCB_SPI_RegisterCallback to register a callback * Alternatively, use \ref Cy_SCB_SPI_RegisterCallback to register a callback
* function to be notified about \ref group_scb_spi_macros_callback_events. * function to be notified about \ref group_scb_spi_macros_callback_events.
* *
* The SPI driver provides the callback functions to facilitate the low-power * \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_TRANFER_DATA
* mode transition. The callback \ref Cy_SCB_SPI_DeepSleepCallback can be called *
* \section group_scb_spi_dma_trig DMA Trigger
* The SCB provides TX and RX output trigger signals that can be routed to the
* DMA controller inputs. These signals are assigned based on the data availability
* in the TX and RX FIFOs appropriately.
*
* * The RX trigger signal remains active until the number of data
* elements in the RX FIFO is greater than the value of RX FIFO level. Use
* function \ref Cy_SCB_SetRxFifoLevel or set configuration structure
* rxFifoTriggerLevel parameter to configure RX FIFO level value. \n
* <em>For example, the RX FIFO has 8 data elements and the RX FIFO level is 0.
* The RX trigger signal remains active until DMA does not read all data from
* the RX FIFO.</em>
*
* * The TX trigger signal remains active until the number of data elements
* in the TX FIFO is less than the value of TX FIFO level. Use function
* \ref Cy_SCB_SetTxFifoLevel or set configuration structure txFifoTriggerLevel
* parameter to configure TX FIFO level value. \n
* <em>For example, the TX FIFO has 0 data elements (empty) and the TX FIFO level
* is 7. The TX trigger signal remains active until DMA does not load TX FIFO
* with 7 data elements (note that after the first TX load operation, the data
* element goes to the shift register and TX FIFO remains empty).</em>
*
* To route SCB TX or RX trigger signals to the DMA controller, use \ref group_trigmux
* driver API.
*
* \note
* To properly handle DMA level request signal activation and de-activation from the SCB
* peripheral block the DMA Descriptor typically must be configured to re-trigger
* after 16 Clk_Slow cycles.
*
* \section group_scb_spi_lp Low Power Support
* The SPI driver provides the callback functions to handle power mode transition.
* The callback \ref Cy_SCB_SPI_DeepSleepCallback must be called
* during execution of \ref Cy_SysPm_DeepSleep; \ref Cy_SCB_SPI_HibernateCallback * during execution of \ref Cy_SysPm_DeepSleep; \ref Cy_SCB_SPI_HibernateCallback
* can be called during execution of \ref Cy_SysPm_Hibernate. To trigger the * must be called during execution of \ref Cy_SysPm_Hibernate. To trigger the
* callback execution, the callback must be registered before calling the * callback execution, the callback must be registered before calling the
* mode transition function. Refer to SysPm driver for more information about * power mode transition function. Refer to \ref group_syspm driver for more
* low-power mode transitions. * information about power mode transitions and callback registration.
*
* The SPI master is disabled during Deep Sleep and Hibernate and stops driving
* the output pins. The state of the SPI master output pins SCLK, SS, and MOSI is
* High-Z, which can cause unexpected behavior of the SPI Slave due to possible
* glitches on these lines. These pins must be set to the inactive state before
* entering Deep Sleep or Hibernate mode. To do that, configure the SPI master
* pins output to drive the inactive state and High-Speed Input Output
* Multiplexer (HSIOM) to control output by GPIO (use \ref group_gpio
* driver API). The pins configuration must be restored after exiting Deep Sleep
* mode to return the SPI master control of the pins (after exiting Hibernate
* mode, the system init code does the same).
* Note that the SPI master must be enabled to drive the pins during
* configuration change not to cause glitches on the lines. Copy either or
* both \ref Cy_SCB_SPI_DeepSleepCallback and \ref Cy_SCB_SPI_HibernateCallback
* as appropriate, and make the changes described above inside the function.
* Alternately, external pull-up or pull-down resistors can be connected
* to the appropriate SPI lines to keep them inactive during Deep-Sleep or
* Hibernate.
*
* \note
* Only applicable for <b>rev-08 of the CY8CKIT-062-BLE</b>.
* For proper operation, when the SPI slave is configured to be a wakeup
* source from Deep Sleep mode, the \ref Cy_SCB_SPI_DeepSleepCallback must be
* copied and modified. Refer to the function description to get the details.
* *
* \section group_scb_spi_more_information More Information * \section group_scb_spi_more_information More Information
*
* For more information on the SCB peripheral, refer to the technical reference * For more information on the SCB peripheral, refer to the technical reference
* manual (TRM). * manual (TRM).
* *
@ -114,7 +246,7 @@
* <td>A cast should not be performed between a pointer to object type and * <td>A cast should not be performed between a pointer to object type and
* a different pointer to object type.</td> * a different pointer to object type.</td>
* <td> * <td>
* * The pointer to the buffer memory is void to allow handling different * * The pointer to the buffer memory is void to allow handling
* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits). * different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits).
* The cast operation is safe because the configuration is verified * The cast operation is safe because the configuration is verified
* before operation is performed. * before operation is performed.
@ -162,12 +294,21 @@
* <table class="doxtable"> * <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr> * <tr>
* <td rowspan="3"> 2.0</td> * <td>2.10</td>
* <td>None.</td>
* <td>SCB I2C driver updated.</td>
* </tr>
* <tr>
* <td rowspan="4"> 2.0</td>
* <td>Fixed SPI callback notification when error event occurred.</td>
* <td>The SPI callback passed incorrect event value if error event occurred.</td>
* </tr>
* <tr>
* <td>Added parameters validation for public API.</td> * <td>Added parameters validation for public API.</td>
* <td></td> * <td></td>
* </tr> * </tr>
* <tr> * <tr>
* <td>Replaced variables which have limited range of values with enumerated * <td>Replaced variables that have limited range of values with enumerated
* types.</td> * types.</td>
* <td></td> * <td></td>
* </tr> * </tr>
@ -385,7 +526,7 @@ typedef struct cy_stc_scb_spi_config
* When set, the slave will wake the device when the slave select line * When set, the slave will wake the device when the slave select line
* becomes active. * becomes active.
* Note that not all SCBs support this mode. Consult the device * Note that not all SCBs support this mode. Consult the device
* datasheet to determine which SCBs support wake from deep sleep. * datasheet to determine which SCBs support wake from Deep Sleep.
*/ */
bool enableWakeFromSleep; bool enableWakeFromSleep;
@ -430,7 +571,7 @@ typedef struct cy_stc_scb_spi_config
* All fields for the context structure are internal. Firmware never reads or * All fields for the context structure are internal. Firmware never reads or
* writes these values. Firmware allocates the structure and provides the * writes these values. Firmware allocates the structure and provides the
* address of the structure to the driver in function calls. Firmware must * address of the structure to the driver in function calls. Firmware must
* ensure that the defined instance of this structure remains in scope while * ensure that the defined instance of this structure remains in scope
* while the drive is in use. * while the drive is in use.
*/ */
typedef struct cy_stc_scb_spi_context typedef struct cy_stc_scb_spi_context
@ -778,11 +919,11 @@ __STATIC_INLINE void Cy_SCB_SPI_Enable(CySCB_Type *base)
* The pointer to the SPI SCB instance. * The pointer to the SPI SCB instance.
* *
* \return * \return
* True - the bus is busy, false - the bus is idle. * True - the bus is busy; false - the bus is idle.
* *
* \note * \note
* * The SPI master does not assign the slave select line immediately after * * The SPI master does not assign the slave select line immediately after
* the 1st data element is written into the TX FIFO. It takes up to 2 SCLK * the first data element is written into the TX FIFO. It takes up to two SCLK
* clocks to assign the slave select line. Before this happens, the bus * clocks to assign the slave select line. Before this happens, the bus
* is considered idle. * is considered idle.
* * If the SPI master is configured to separate a data elements transfer, * * If the SPI master is configured to separate a data elements transfer,
@ -1034,7 +1175,7 @@ __STATIC_INLINE uint32_t Cy_SCB_SPI_GetNumInTxFifo(CySCB_Type const *base)
* Function Name: Cy_SCB_SPI_IsTxComplete * Function Name: Cy_SCB_SPI_IsTxComplete
****************************************************************************//** ****************************************************************************//**
* *
* Checks if the TX FIFO and Shifter are empty and there is no more data to send * Checks whether the TX FIFO and Shifter are empty and there is no more data to send
* *
* \param base * \param base
* Pointer to the SPI SCB instance. * Pointer to the SPI SCB instance.
@ -1060,8 +1201,8 @@ __STATIC_INLINE bool Cy_SCB_SPI_IsTxComplete(CySCB_Type const *base)
* *
* \sideeffect * \sideeffect
* The TX FIFO clear operation also clears the shift register, so that * The TX FIFO clear operation also clears the shift register, so that
* the shifter could be cleared in the middle of a data element transfer, * the shifter can be cleared in the middle of a data element transfer,
* corrupting it. The data element corruption means that all bits which has * corrupting it. The data element corruption means that all bits that have
* not been transmitted are transmitted as 1s on the bus. * not been transmitted are transmitted as 1s on the bus.
* *
*******************************************************************************/ *******************************************************************************/
@ -1139,7 +1280,7 @@ __STATIC_INLINE void Cy_SCB_SPI_ClearSlaveMasterStatus(CySCB_Type *base, uint32_
****************************************************************************//** ****************************************************************************//**
* *
* Reads a single data element from the SPI RX FIFO. * Reads a single data element from the SPI RX FIFO.
* This function does not check if the RX FIFO has data before reading it. * This function does not check whether the RX FIFO has data before reading it.
* If the RX FIFO is empty, the function returns \ref CY_SCB_SPI_RX_NO_DATA. * If the RX FIFO is empty, the function returns \ref CY_SCB_SPI_RX_NO_DATA.
* *
* \param base * \param base
@ -1175,7 +1316,7 @@ __STATIC_INLINE uint32_t Cy_SCB_SPI_Read(CySCB_Type const *base)
* *
* \param buffer * \param buffer
* The pointer to the location to place data read from the RX FIFO. * The pointer to the location to place data read from the RX FIFO.
* The item size is defined by the data type which depends on the configured * The item size is defined by the data type, which depends on the configured
* RX data width. * RX data width.
* *
* \param size * \param size
@ -1336,7 +1477,7 @@ __STATIC_INLINE void Cy_SCB_SPI_WriteArrayBlocking(CySCB_Type *base, void *buffe
* \param context * \param context
* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated * The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
* by the user. The structure is used during the SPI operation for internal * by the user. The structure is used during the SPI operation for internal
* configuration and data keeping. The user should not modify anything * configuration and data retention. The user should not modify anything
* in this structure. * in this structure.
* *
* \note * \note

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