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Provide option to user to drive SS pin too 

Signed-off-by: Sadik.Ozer <Sadik.Ozer@maximintegrated.com>
pull/15263/head
Sadik.Ozer 2022-03-08 22:02:45 +03:00
parent f1bce7389f
commit 24f4738f24
5 changed files with 48 additions and 35 deletions
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2
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_spi.h
View File

@ -173,7 +173,7 @@ struct _mxc_spi_req_t {
* \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPI_Init (mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
unsigned ssPolarity, unsigned int hz);
unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel);
/**
* @brief Disable and shutdown SPI peripheral.

4
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_me15.c
View File

@ -49,7 +49,7 @@
/* **** Functions **** */
int MXC_SPI_Init(mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
unsigned ssPolarity, unsigned int hz)
unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel)
{
int spi_num;
@ -87,7 +87,7 @@ int MXC_SPI_Init(mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numS
return E_NO_DEVICE;
}
return MXC_SPI_RevA_Init ((mxc_spi_reva_regs_t*) spi, masterMode, quadModeUsed, numSlaves, ssPolarity, hz);
return MXC_SPI_RevA_Init ((mxc_spi_reva_regs_t*) spi, masterMode, quadModeUsed, numSlaves, ssPolarity, hz, drv_ssel);
}
int MXC_SPI_Shutdown(mxc_spi_regs_t* spi)

65
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c
View File

@ -61,6 +61,7 @@ typedef struct {
int channelRx;
bool txrx_req;
uint8_t req_done;
unsigned drv_ssel;
} spi_req_reva_state_t;
/* states whether to use call back or not */
@ -76,7 +77,7 @@ static int MXC_SPI_RevA_TransSetup (mxc_spi_reva_req_t * req);
int MXC_SPI_RevA_Init (mxc_spi_reva_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
unsigned ssPolarity, unsigned int hz)
unsigned ssPolarity, unsigned int hz, unsigned drv_ssel)
{
int spi_num;
@ -87,6 +88,7 @@ int MXC_SPI_RevA_Init (mxc_spi_reva_regs_t* spi, int masterMode, int quadModeUse
states[spi_num].last_size = 0;
states[spi_num].ssDeassert = 1;
states[spi_num].defaultTXData = 0;
states[spi_num].drv_ssel = drv_ssel;
spi->ctrl0 = (MXC_F_SPI_REVA_CTRL0_EN);
spi->sstime = ( (0x1 << MXC_F_SPI_REVA_SSTIME_PRE_POS) |
@ -109,22 +111,25 @@ int MXC_SPI_RevA_Init (mxc_spi_reva_regs_t* spi, int masterMode, int quadModeUse
// Clear the interrupts
spi->intfl = spi->intfl;
if (numSlaves == 1) {
spi->ctrl0 |= MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0;
// Driver will drive SS pin?
if (states[spi_num].drv_ssel) {
if (numSlaves == 1) {
spi->ctrl0 |= MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0;
}
else if (numSlaves == 2) {
spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1);
}
else if (numSlaves == 3) {
spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2);
}
else if (numSlaves == 4) {
spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS3);
}
}
if (numSlaves == 2) {
spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1);
}
if (numSlaves == 3) {
spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2);
}
if (numSlaves == 4) {
spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS3);
}
//set quad mode
if (quadModeUsed) {
spi->ctrl2 |= MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_QUAD;
@ -308,11 +313,13 @@ int MXC_SPI_RevA_SetSlave (mxc_spi_reva_regs_t* spi, int ssIdx)
MXC_ASSERT (spi_num >= 0);
(void)spi_num;
// Setup the slave select
// Activate chosen SS pin
spi->ctrl0 |= (1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS;
// Deactivate all unchosen pins
spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_ACTIVE | ((1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS);
if (states[spi_num].drv_ssel) {
// Setup the slave select
// Activate chosen SS pin
spi->ctrl0 |= (1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS;
// Deactivate all unchosen pins
spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_ACTIVE | ((1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS);
}
return E_NO_ERROR;
}
@ -761,10 +768,12 @@ uint32_t MXC_SPI_RevA_MasterTransHandler (mxc_spi_reva_regs_t *spi, mxc_spi_reva
spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi);
// Leave slave select asserted at the end of the transaction
if (!req->ssDeassert) {
spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL;
if (states[spi_num].drv_ssel) {
if (!req->ssDeassert) {
spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL;
}
}
retval = MXC_SPI_RevA_TransHandler(spi, req);
if (!states[spi_num].started) {
@ -773,10 +782,12 @@ uint32_t MXC_SPI_RevA_MasterTransHandler (mxc_spi_reva_regs_t *spi, mxc_spi_reva
}
// Deassert slave select at the end of the transaction
if (req->ssDeassert) {
spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL;
if (states[spi_num].drv_ssel) {
if (req->ssDeassert) {
spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL;
}
}
return retval;
}

2
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.h
View File

@ -74,7 +74,7 @@ struct _mxc_spi_reva_req_t {
};
int MXC_SPI_RevA_Init (mxc_spi_reva_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
unsigned ssPolarity, unsigned int hz);
unsigned ssPolarity, unsigned int hz, unsigned drv_ssel);
int MXC_SPI_RevA_Shutdown (mxc_spi_reva_regs_t* spi);
int MXC_SPI_RevA_ReadyForSleep (mxc_spi_reva_regs_t* spi);
int MXC_SPI_RevA_SetFrequency (mxc_spi_reva_regs_t* spi, unsigned int hz);

10
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/pins_me15.c
View File

@ -74,12 +74,14 @@ const mxc_gpio_cfg_t gpio_cfg_uart3_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN
const mxc_gpio_cfg_t gpio_cfg_i2s0 = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9 | MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_spi0 = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3 | MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_spi0 = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3 | MXC_GPIO_PIN_4), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_spi0_ss = { MXC_GPIO0, (MXC_GPIO_PIN_5), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
// NOTE: SPI1 definied here with SS0 only
const mxc_gpio_cfg_t gpio_cfg_spi1 = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15 | MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_spi1 = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15 | MXC_GPIO_PIN_16), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_spi1_ss = { MXC_GPIO0, (MXC_GPIO_PIN_17), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
// NOTE: SPI2 defined here with SS0 only, and NOT SS1 and SS2
const mxc_gpio_cfg_t gpio_cfg_spi2 = { MXC_GPIO1, (MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3 | MXC_GPIO_PIN_4), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_spi2 = { MXC_GPIO1, (MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_spi2_ss = { MXC_GPIO1, (MXC_GPIO_PIN_4), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
// Timers are only defined once, depending on package, each timer could be mapped to other pins
const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, (MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO};