From 632892d355ba7899921b07ae16eee2035554c0ed Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Tue, 22 May 2018 09:48:01 -0500 Subject: [PATCH] MIMXRT1050: Update to EVK Rev B 1. Add the IVT header to the binary as this is required for boot up This was earlier added by the DAPLink firmware. As it is no longer handled in DAPLink, the header needs to be added inside mbed. 2. Update drivers Signed-off-by: Mahesh Mahadevan --- .../TARGET_MIMXRT1050/TARGET_EVK/device.h | 1 + .../TARGET_EVK/fsl_clock_config.c | 308 +- .../TARGET_EVK/fsl_clock_config.h | 56 +- .../TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.c | 8 +- .../TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.h | 8 +- .../TARGET_EVK/mbed_overrides.c | 69 +- .../xip/evkbimxrt1050_flexspi_nor_config.c | 76 + .../xip/evkbimxrt1050_flexspi_nor_config.h | 296 ++ .../xip/evkbimxrt1050_sdram_ini_dcd.c | 1126 ++++++ .../xip/evkbimxrt1050_sdram_ini_dcd.h | 47 + .../TARGET_MIMXRT1050/device/MIMXRT1052.h | 3076 +++++++++++++++-- .../device/MIMXRT1052_features.h | 512 +-- .../TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct | 108 +- .../TOOLCHAIN_ARM_STD/startup_MIMXRT1052.S | 55 +- .../TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld | 103 +- .../TOOLCHAIN_GCC_ARM/startup_MIMXRT1052.S | 77 +- .../device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf | 99 +- .../device/TOOLCHAIN_IAR/startup_MIMXRT1052.S | 55 +- .../device/fsl_device_registers.h | 52 +- .../device/system_MIMXRT1052.c | 126 +- .../device/system_MIMXRT1052.h | 74 +- .../TARGET_MIMXRT1050/drivers/fsl_adc.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_adc.h | 8 +- .../TARGET_MIMXRT1050/drivers/fsl_adc_etc.c | 20 +- .../TARGET_MIMXRT1050/drivers/fsl_adc_etc.h | 22 +- .../TARGET_MIMXRT1050/drivers/fsl_aipstz.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_aipstz.h | 12 +- .../TARGET_MIMXRT1050/drivers/fsl_aoi.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_aoi.h | 8 +- .../TARGET_MIMXRT1050/drivers/fsl_bee.c | 12 +- .../TARGET_MIMXRT1050/drivers/fsl_bee.h | 6 +- .../TARGET_MIMXRT1050/drivers/fsl_cache.c | 36 +- .../TARGET_MIMXRT1050/drivers/fsl_cache.h | 20 +- .../TARGET_MIMXRT1050/drivers/fsl_clock.c | 341 +- .../TARGET_MIMXRT1050/drivers/fsl_clock.h | 1282 ++++--- .../TARGET_MIMXRT1050/drivers/fsl_cmp.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_cmp.h | 8 +- .../TARGET_MIMXRT1050/drivers/fsl_common.c | 60 +- .../TARGET_MIMXRT1050/drivers/fsl_common.h | 90 +- .../TARGET_MIMXRT1050/drivers/fsl_csi.c | 12 +- .../TARGET_MIMXRT1050/drivers/fsl_csi.h | 6 +- .../TARGET_MIMXRT1050/drivers/fsl_dcdc.c | 17 +- .../TARGET_MIMXRT1050/drivers/fsl_dcdc.h | 6 +- .../TARGET_MIMXRT1050/drivers/fsl_dcp.c | 12 +- .../TARGET_MIMXRT1050/drivers/fsl_dcp.h | 6 +- .../TARGET_MIMXRT1050/drivers/fsl_dmamux.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_dmamux.h | 8 +- .../TARGET_MIMXRT1050/drivers/fsl_edma.c | 19 +- .../TARGET_MIMXRT1050/drivers/fsl_edma.h | 41 +- .../TARGET_MIMXRT1050/drivers/fsl_elcdif.c | 16 +- .../TARGET_MIMXRT1050/drivers/fsl_elcdif.h | 6 +- .../TARGET_MIMXRT1050/drivers/fsl_enc.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_enc.h | 24 +- .../TARGET_MIMXRT1050/drivers/fsl_enet.c | 211 +- .../TARGET_MIMXRT1050/drivers/fsl_enet.h | 53 +- .../TARGET_MIMXRT1050/drivers/fsl_ewm.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_ewm.h | 8 +- .../TARGET_MIMXRT1050/drivers/fsl_flexcan.c | 528 ++- .../TARGET_MIMXRT1050/drivers/fsl_flexcan.h | 86 +- .../TARGET_MIMXRT1050/drivers/fsl_flexio.c | 31 +- .../TARGET_MIMXRT1050/drivers/fsl_flexio.h | 35 +- .../drivers/fsl_flexio_i2c_master.c | 24 +- .../drivers/fsl_flexio_i2c_master.h | 12 +- .../drivers/fsl_flexio_i2s.c | 24 +- .../drivers/fsl_flexio_i2s.h | 12 +- .../drivers/fsl_flexio_i2s_edma.c | 16 +- .../drivers/fsl_flexio_i2s_edma.h | 17 +- .../drivers/fsl_flexio_spi.c | 24 +- .../drivers/fsl_flexio_spi.h | 12 +- .../drivers/fsl_flexio_spi_edma.c | 16 +- .../drivers/fsl_flexio_spi_edma.h | 17 +- .../drivers/fsl_flexio_uart.c | 24 +- .../drivers/fsl_flexio_uart.h | 12 +- .../drivers/fsl_flexio_uart_edma.c | 17 +- .../drivers/fsl_flexio_uart_edma.h | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_flexram.c | 19 +- .../TARGET_MIMXRT1050/drivers/fsl_flexram.h | 10 +- .../TARGET_MIMXRT1050/drivers/fsl_flexspi.c | 77 +- .../TARGET_MIMXRT1050/drivers/fsl_flexspi.h | 22 +- .../drivers/fsl_flexspi_nor_boot.c | 72 + .../drivers/fsl_flexspi_nor_boot.h | 131 + .../TARGET_MIMXRT1050/drivers/fsl_gpc.c | 12 +- .../TARGET_MIMXRT1050/drivers/fsl_gpc.h | 6 +- .../TARGET_MIMXRT1050/drivers/fsl_gpio.c | 38 +- .../TARGET_MIMXRT1050/drivers/fsl_gpio.h | 111 +- .../TARGET_MIMXRT1050/drivers/fsl_gpt.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_gpt.h | 8 +- .../TARGET_MIMXRT1050/drivers/fsl_iomuxc.h | 91 +- .../TARGET_MIMXRT1050/drivers/fsl_kpp.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_kpp.h | 8 +- .../TARGET_MIMXRT1050/drivers/fsl_lpi2c.c | 88 +- .../TARGET_MIMXRT1050/drivers/fsl_lpi2c.h | 31 +- .../drivers/fsl_lpi2c_edma.c | 32 +- .../drivers/fsl_lpi2c_edma.h | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_lpspi.c | 63 +- .../TARGET_MIMXRT1050/drivers/fsl_lpspi.h | 91 +- .../drivers/fsl_lpspi_edma.c | 32 +- .../drivers/fsl_lpspi_edma.h | 31 +- .../TARGET_MIMXRT1050/drivers/fsl_lpuart.c | 99 +- .../TARGET_MIMXRT1050/drivers/fsl_lpuart.h | 14 +- .../drivers/fsl_lpuart_edma.c | 21 +- .../drivers/fsl_lpuart_edma.h | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_pit.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_pit.h | 8 +- .../TARGET_MIMXRT1050/drivers/fsl_pmu.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_pmu.h | 8 +- .../TARGET_MIMXRT1050/drivers/fsl_pwm.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_pwm.h | 8 +- .../TARGET_MIMXRT1050/drivers/fsl_pxp.c | 12 +- .../TARGET_MIMXRT1050/drivers/fsl_pxp.h | 6 +- .../TARGET_MIMXRT1050/drivers/fsl_qtmr.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_qtmr.h | 8 +- .../TARGET_MIMXRT1050/drivers/fsl_rtwdog.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_rtwdog.h | 8 +- .../TARGET_MIMXRT1050/drivers/fsl_sai.c | 327 +- .../TARGET_MIMXRT1050/drivers/fsl_sai.h | 135 +- .../TARGET_MIMXRT1050/drivers/fsl_sai_edma.c | 39 +- .../TARGET_MIMXRT1050/drivers/fsl_sai_edma.h | 37 +- .../TARGET_MIMXRT1050/drivers/fsl_semc.c | 113 +- .../TARGET_MIMXRT1050/drivers/fsl_semc.h | 58 +- .../TARGET_MIMXRT1050/drivers/fsl_snvs_hp.c | 101 +- .../TARGET_MIMXRT1050/drivers/fsl_snvs_hp.h | 67 +- .../TARGET_MIMXRT1050/drivers/fsl_snvs_lp.c | 44 +- .../TARGET_MIMXRT1050/drivers/fsl_snvs_lp.h | 63 +- .../TARGET_MIMXRT1050/drivers/fsl_spdif.c | 12 +- .../TARGET_MIMXRT1050/drivers/fsl_spdif.h | 8 +- .../drivers/fsl_spdif_edma.c | 12 +- .../drivers/fsl_spdif_edma.h | 11 +- .../TARGET_MIMXRT1050/drivers/fsl_src.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_src.h | 8 +- .../TARGET_MIMXRT1050/drivers/fsl_trng.c | 18 +- .../TARGET_MIMXRT1050/drivers/fsl_trng.h | 18 +- .../TARGET_MIMXRT1050/drivers/fsl_tsc.c | 16 +- .../TARGET_MIMXRT1050/drivers/fsl_tsc.h | 15 +- .../TARGET_MIMXRT1050/drivers/fsl_usdhc.c | 298 +- .../TARGET_MIMXRT1050/drivers/fsl_usdhc.h | 50 +- .../TARGET_MIMXRT1050/drivers/fsl_wdog.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_wdog.h | 8 +- .../TARGET_MIMXRT1050/drivers/fsl_xbara.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_xbara.h | 10 +- .../TARGET_MIMXRT1050/drivers/fsl_xbarb.c | 14 +- .../TARGET_MIMXRT1050/drivers/fsl_xbarb.h | 8 +- targets/TARGET_NXP/mbed_rtx.h | 28 +- targets/targets.json | 2 +- tools/export/iar/iar_definitions.json | 5 +- 145 files changed, 9358 insertions(+), 3221 deletions(-) create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.h create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.h create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.c create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/device.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/device.h index c0c27f101a..c6a2cc471f 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/device.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/device.h @@ -19,6 +19,7 @@ #define MBED_DEVICE_H #define DEVICE_ID_LENGTH 24 +#define BOARD_FLASH_SIZE (0x4000000U) #include "objects.h" diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.c index 058525b33b..743522f0a4 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.c @@ -1,8 +1,11 @@ /* + * The Clear BSD License * Copyright 2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -15,6 +18,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -26,21 +30,36 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v4.1 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 0.0.0 +board: IMXRT1050-EVKB + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -#include "fsl_common.h" #include "fsl_clock_config.h" /******************************************************************************* * Definitions ******************************************************************************/ -/* ARM PLL configuration for RUN mode */ -const clock_arm_pll_config_t armPllConfig = {.loopDivider = 100U}; - -/* SYS PLL configuration for RUN mode */ -const clock_sys_pll_config_t sysPllConfig = {.loopDivider = 1U}; - -/* USB1 PLL configuration for RUN mode */ -const clock_usb_pll_config_t usb1PllConfig = {.loopDivider = 0U}; /******************************************************************************* * Variables @@ -49,59 +68,240 @@ const clock_usb_pll_config_t usb1PllConfig = {.loopDivider = 0U}; extern uint32_t SystemCoreClock; /******************************************************************************* - * Code + ************************ BOARD_InitBootClocks function ************************ ******************************************************************************/ -static void BOARD_BootClockGate(void) +void BOARD_InitBootClocks(void) { - /* Disable all unused peripheral clock */ - CCM->CCGR0 = 0x00C0000FU; - CCM->CCGR1 = 0x30000000U; - CCM->CCGR2 = 0xFF3F303FU; - CCM->CCGR3 = 0xF0000330U; - CCM->CCGR4 = 0x0000FF3CU; - CCM->CCGR5 = 0xF003330FU; - CCM->CCGR6 = 0x00FC0F00U; + BOARD_BootClockRUN(); } +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 37.5 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} +- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} +- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL5.denom, value: '1'} +- {id: CCM_ANALOG.PLL5.div, value: '40'} +- {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +sources: +- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true} +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ +}; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ +}; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ +}; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ void BOARD_BootClockRUN(void) { - /* Boot ROM did initialize the XTAL, here we only sets external XTAL OSC freq */ - CLOCK_SetXtalFreq(24000000U); + /* Init RTC OSC clock frequency. */ CLOCK_SetRtcXtalFreq(32768U); - - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - - /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz */ + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz. */ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); - - CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */ + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* Init System PLL. */ #ifndef SKIP_SYSCLK_INIT - CLOCK_InitSysPll(&sysPllConfig); /* Configure SYS PLL to 528M */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); #endif -#ifndef SKIP_USB_PLL_INIT - CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */ + /* Init Usb1 PLL. */ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); #endif - CLOCK_SetDiv(kCLOCK_ArmDiv, 0x1); /* Set ARM PODF to 0, divide by 2 */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */ - - CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); /* Set PRE_PERIPH_CLK to PLL1, 1200M */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */ - - /* Disable unused clock */ - BOARD_BootClockGate(); - - /* Power down all unused PLL */ - CLOCK_DeinitAudioPll(); - CLOCK_DeinitVideoPll(); - CLOCK_DeinitEnetPll(); - CLOCK_DeinitUsb2Pll(); - - /* Configure UART divider to default */ - CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */ - - /* Update core clock */ - SystemCoreClockUpdate(); + /* Enbale Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Enbale Video PLL output. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Enable ENET PLL output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); +#ifndef SKIP_SYSCLK_INIT + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 0); +#endif + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 2); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 2); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = + (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.h index 9c1c74c98e..ba3e33d0c0 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.h @@ -1,8 +1,11 @@ /* + * The Clear BSD License * Copyright 2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -15,6 +18,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -26,21 +30,64 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - #ifndef _CLOCK_CONFIG_H_ #define _CLOCK_CONFIG_H_ +#include "fsl_common.h" + /******************************************************************************* * Definitions ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ /******************************************************************************* - * API + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t g_armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t g_usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t g_sysPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration ******************************************************************************/ #if defined(__cplusplus) extern "C" { #endif /* __cplusplus*/ +/*! + * @brief This function executes configuration of clocks. + * + */ void BOARD_BootClockRUN(void); #if defined(__cplusplus) @@ -48,3 +95,4 @@ void BOARD_BootClockRUN(void); #endif /* __cplusplus*/ #endif /* _CLOCK_CONFIG_H_ */ + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.c index ec8443244b..79b79138af 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.h index ed096e63e0..f5d9e6c3f1 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/mbed_overrides.c index 0d58a9aad8..ca9b6e10a1 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/mbed_overrides.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/mbed_overrides.c @@ -27,49 +27,94 @@ void mbed_default_mac_address(char *mac); void BOARD_ConfigMPU(void) { /* Disable I cache and D cache */ - SCB_DisableICache(); - SCB_DisableDCache(); + if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) { + SCB_DisableICache(); + } + if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) { + SCB_DisableDCache(); + } /* Disable MPU */ ARM_MPU_Disable(); - /* Region 0 setting */ + /* MPU configure: + * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) + * API in core_cm7.h. + * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches disabled. + * param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. + * Use MACROS defined in core_cm7.h: ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO + * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. + * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache + * 0 x 0 0 Strongly Ordered shareable + * 0 x 0 1 Device shareable + * 0 0 1 0 Normal not shareable Outer and inner write through no write allocate + * 0 0 1 1 Normal not shareable Outer and inner write back no write allocate + * 0 1 1 0 Normal shareable Outer and inner write through no write allocate + * 0 1 1 1 Normal shareable Outer and inner write back no write allocate + * 1 0 0 0 Normal not shareable outer and inner noncache + * 1 1 0 0 Normal shareable outer and inner noncache + * 1 0 1 1 Normal not shareable outer and inner write back write/read acllocate + * 1 1 1 1 Normal shareable outer and inner write back write/read acllocate + * 2 x 0 0 Device not shareable + * Above are normal use settings, if your want to see more details or want to config different inner/outter cache policy. + * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide + * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. + * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in core_cm7.h. + */ + + /* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */ MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); - /* Region 1 setting */ + /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); /* Region 2 setting */ +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) + /* Setting Memory with Normal type, not shareable, outer/inner write back. */ MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512MB); +#else + /* Setting Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); +#endif - /* Region 3 setting */ + /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */ MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); - /* Region 4 setting */ + /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */ MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); - /* Region 5 setting */ + /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); - /* Region 6 setting */ + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); -#if defined(SDRAM_MPU_INIT) - /* Region 7 setting */ + /* The define sets the cacheable memory to shareable, + * this suggestion is referred from chapter 2.2.1 Memory regions, + * types and attributes in Cortex-M7 Devices, Generic User Guide */ +#if defined(SDRAM_IS_SHAREABLE) + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); +#else + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); +#endif - /* Region 8 setting */ + /* Region 8 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be + * accessed by cache can be put here */ + /* Memory with Normal type, not shareable, non-cacheable */ MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); -#endif /* Enable MPU */ ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c new file mode 100644 index 0000000000..24fe770b11 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c @@ -0,0 +1,76 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "evkbimxrt1050_flexspi_nor_config.h" + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const flexspi_nor_config_t hyperflash_config = { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .columnAddressWidth = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) | + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable), + .sflashPadType = kSerialFlash_8Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 64u * 1024u * 1024u, + .dataValidTime = {16u, 16u}, + .lookupTable = + { + // Read LUTs + FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18), + FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06), + FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 512u, + .sectorSize = 256u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = true, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.h new file mode 100644 index 0000000000..67e93b3920 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.h @@ -0,0 +1,296 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this + * list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, + * this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ +#define __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c new file mode 100644 index 0000000000..452e76e503 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c @@ -0,0 +1,1126 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "evkbimxrt1050_sdram_ini_dcd.h" + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif +/************************************* + * DCD Data + *************************************/ +const uint8_t dcd_data[] = { + /*0000*/ DCD_TAG_HEADER, + 0x04, + 0x30, + 0x41, + 0xCC, + 0x03, + 0xAC, + 0x04, + 0x40, + 0x0F, + 0xC0, + 0x68, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0010*/ 0x40, + 0x0F, + 0xC0, + 0x6C, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x70, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0020*/ 0x40, + 0x0F, + 0xC0, + 0x74, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x78, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0030*/ 0x40, + 0x0F, + 0xC0, + 0x7C, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x80, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0040*/ 0x40, + 0x0D, + 0x80, + 0x30, + 0x00, + 0x00, + 0x20, + 0x01, + 0x40, + 0x0D, + 0x81, + 0x00, + 0x00, + 0x1D, + 0x00, + 0x00, + /*0050*/ 0x40, + 0x0F, + 0xC0, + 0x14, + 0x00, + 0x01, + 0x0D, + 0x40, + 0x40, + 0x1F, + 0x80, + 0x14, + 0x00, + 0x00, + 0x00, + 0x00, + /*0060*/ 0x40, + 0x1F, + 0x80, + 0x18, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x1C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0070*/ 0x40, + 0x1F, + 0x80, + 0x20, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x24, + 0x00, + 0x00, + 0x00, + 0x00, + /*0080*/ 0x40, + 0x1F, + 0x80, + 0x28, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x2C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0090*/ 0x40, + 0x1F, + 0x80, + 0x30, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x34, + 0x00, + 0x00, + 0x00, + 0x00, + /*00a0*/ 0x40, + 0x1F, + 0x80, + 0x38, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00b0*/ 0x40, + 0x1F, + 0x80, + 0x40, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x44, + 0x00, + 0x00, + 0x00, + 0x00, + /*00c0*/ 0x40, + 0x1F, + 0x80, + 0x48, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x4C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00d0*/ 0x40, + 0x1F, + 0x80, + 0x50, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x54, + 0x00, + 0x00, + 0x00, + 0x00, + /*00e0*/ 0x40, + 0x1F, + 0x80, + 0x58, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x5C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00f0*/ 0x40, + 0x1F, + 0x80, + 0x60, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x64, + 0x00, + 0x00, + 0x00, + 0x00, + /*0100*/ 0x40, + 0x1F, + 0x80, + 0x68, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x6C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0110*/ 0x40, + 0x1F, + 0x80, + 0x70, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x74, + 0x00, + 0x00, + 0x00, + 0x00, + /*0120*/ 0x40, + 0x1F, + 0x80, + 0x78, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x7C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0130*/ 0x40, + 0x1F, + 0x80, + 0x80, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x84, + 0x00, + 0x00, + 0x00, + 0x00, + /*0140*/ 0x40, + 0x1F, + 0x80, + 0x88, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x8C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0150*/ 0x40, + 0x1F, + 0x80, + 0x90, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x94, + 0x00, + 0x00, + 0x00, + 0x00, + /*0160*/ 0x40, + 0x1F, + 0x80, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x9C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0170*/ 0x40, + 0x1F, + 0x80, + 0xA0, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0xA4, + 0x00, + 0x00, + 0x00, + 0x00, + /*0180*/ 0x40, + 0x1F, + 0x80, + 0xA8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0xAC, + 0x00, + 0x00, + 0x00, + 0x00, + /*0190*/ 0x40, + 0x1F, + 0x80, + 0xB0, + 0x00, + 0x00, + 0x00, + 0x10, + 0x40, + 0x1F, + 0x80, + 0xB4, + 0x00, + 0x00, + 0x00, + 0x00, + /*01a0*/ 0x40, + 0x1F, + 0x80, + 0xB8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x82, + 0x04, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01b0*/ 0x40, + 0x1F, + 0x82, + 0x08, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x0C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01c0*/ 0x40, + 0x1F, + 0x82, + 0x10, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x14, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01d0*/ 0x40, + 0x1F, + 0x82, + 0x18, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x1C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01e0*/ 0x40, + 0x1F, + 0x82, + 0x20, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x24, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01f0*/ 0x40, + 0x1F, + 0x82, + 0x28, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x2C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0200*/ 0x40, + 0x1F, + 0x82, + 0x30, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x34, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0210*/ 0x40, + 0x1F, + 0x82, + 0x38, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x3C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0220*/ 0x40, + 0x1F, + 0x82, + 0x40, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x44, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0230*/ 0x40, + 0x1F, + 0x82, + 0x48, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x4C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0240*/ 0x40, + 0x1F, + 0x82, + 0x50, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x54, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0250*/ 0x40, + 0x1F, + 0x82, + 0x58, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x5C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0260*/ 0x40, + 0x1F, + 0x82, + 0x60, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x64, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0270*/ 0x40, + 0x1F, + 0x82, + 0x68, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x6C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0280*/ 0x40, + 0x1F, + 0x82, + 0x70, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x74, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0290*/ 0x40, + 0x1F, + 0x82, + 0x78, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x7C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02a0*/ 0x40, + 0x1F, + 0x82, + 0x80, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x84, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02b0*/ 0x40, + 0x1F, + 0x82, + 0x88, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x8C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02c0*/ 0x40, + 0x1F, + 0x82, + 0x90, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x94, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02d0*/ 0x40, + 0x1F, + 0x82, + 0x98, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x9C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02e0*/ 0x40, + 0x1F, + 0x82, + 0xA0, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0xA4, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02f0*/ 0x40, + 0x1F, + 0x82, + 0xA8, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x2F, + 0x00, + 0x00, + 0x10, + 0x00, + 0x00, + 0x04, + /*0300*/ 0x40, + 0x2F, + 0x00, + 0x08, + 0x00, + 0x03, + 0x05, + 0x24, + 0x40, + 0x2F, + 0x00, + 0x0C, + 0x06, + 0x03, + 0x05, + 0x24, + /*0310*/ 0x40, + 0x2F, + 0x00, + 0x10, + 0x80, + 0x00, + 0x00, + 0x1B, + 0x40, + 0x2F, + 0x00, + 0x14, + 0x82, + 0x00, + 0x00, + 0x1B, + /*0320*/ 0x40, + 0x2F, + 0x00, + 0x18, + 0x84, + 0x00, + 0x00, + 0x1B, + 0x40, + 0x2F, + 0x00, + 0x1C, + 0x86, + 0x00, + 0x00, + 0x1B, + /*0330*/ 0x40, + 0x2F, + 0x00, + 0x20, + 0x90, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x24, + 0xA0, + 0x00, + 0x00, + 0x19, + /*0340*/ 0x40, + 0x2F, + 0x00, + 0x28, + 0xA8, + 0x00, + 0x00, + 0x17, + 0x40, + 0x2F, + 0x00, + 0x2C, + 0xA9, + 0x00, + 0x00, + 0x1B, + /*0350*/ 0x40, + 0x2F, + 0x00, + 0x30, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x04, + 0x00, + 0x00, + 0x79, + 0xA8, + /*0360*/ 0x40, + 0x2F, + 0x00, + 0x40, + 0x00, + 0x00, + 0x0F, + 0x31, + 0x40, + 0x2F, + 0x00, + 0x44, + 0x00, + 0x65, + 0x29, + 0x22, + /*0370*/ 0x40, + 0x2F, + 0x00, + 0x48, + 0x00, + 0x01, + 0x09, + 0x20, + 0x40, + 0x2F, + 0x00, + 0x4C, + 0x50, + 0x21, + 0x0A, + 0x08, + /*0380*/ 0x40, + 0x2F, + 0x00, + 0x80, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x84, + 0x00, + 0x88, + 0x88, + 0x88, + /*0390*/ 0x40, + 0x2F, + 0x00, + 0x94, + 0x00, + 0x00, + 0x00, + 0x02, + 0x40, + 0x2F, + 0x00, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + /*03a0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0F, + /*03b0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x14, + 0x04, + /*03c0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0C, + /*03d0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x14, + 0x04, + /*03e0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0C, + /*03f0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x1C, + 0x04, + /*0400*/ 0x40, + 0x2F, + 0x00, + 0xA0, + 0x00, + 0x00, + 0x00, + 0x33, + 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + /*0410*/ 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0A, + 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + /*0420*/ 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x0C, + 0x04, + 0x40, + 0x2F, + 0x00, + 0x4C, + 0x50, + 0x21, + 0x0A, + 0x09, +}; +#else +/************************************* + * DCD Data + *************************************/ +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.h new file mode 100644 index 0000000000..51fa34e599 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.h @@ -0,0 +1,47 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __EVKBIMXRT1050_DCD_SDRAM_INIT__ +#define __EVKBIMXRT1050_DCD_SDRAM_INIT__ + +#include + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_VERSION (0x40) +#define DCD_ARRAY_SIZE 1 + +#endif /* __EVKBIMXRT1050_DCD_SDRAM_INIT__ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052.h index 1051560b70..09e8044a63 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052.h @@ -1,7 +1,9 @@ /* ** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B ** ** Compilers: Keil ARM C/C++ Compiler ** Freescale C/C++ for Embedded ARM @@ -9,39 +11,46 @@ ** IAR ANSI C/C++ Compiler for ARM ** MCUXpresso Compiler ** -** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Reference manual: IMXRT1050RM Rev.1, 03/2018 ** Version: rev. 0.1, 2017-01-10 -** Build: b171011 +** Build: b180509 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1052 ** +** The Clear BSD License ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2018 NXP +** All rights reserved. ** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: ** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. ** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. ** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.nxp.com ** mail: support@nxp.com @@ -433,6 +442,8 @@ typedef enum _dma_request_source kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer0Cmpld2Timer1 = 123|0x100U, /**< QTIMER4 capture timer 3, cmpld1 in timer 0 or cmpld2 in timer 1 */ } dma_request_source_t; +/* @} */ + /*! * @addtogroup iomuxc_pads * @{ */ @@ -574,6 +585,8 @@ typedef enum _iomuxc_sw_mux_ctl_pad kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */ } iomuxc_sw_mux_ctl_pad_t; +/* @} */ + /*! * @addtogroup iomuxc_pads * @{ */ @@ -715,6 +728,8 @@ typedef enum _iomuxc_sw_pad_ctl_pad kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */ } iomuxc_sw_pad_ctl_pad_t; +/* @} */ + /*! * @brief Enumeration for the IOMUXC select input * @@ -878,8 +893,6 @@ typedef enum _iomuxc_select_input kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U, /**< IOMUXC select input index */ } iomuxc_select_input_t; -/* @} */ - typedef enum _xbar_input_signal { kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */ @@ -1276,8 +1289,12 @@ typedef enum _xbar_output_signal */ #if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif #elif defined(__CWCC__) #pragma push #pragma cpp_extensions on @@ -1321,30 +1338,37 @@ typedef struct { */ /*! @name HC - Control register for hardware triggers */ +/*! @{ */ #define ADC_HC_ADCH_MASK (0x1FU) #define ADC_HC_ADCH_SHIFT (0U) #define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) #define ADC_HC_AIEN_MASK (0x80U) #define ADC_HC_AIEN_SHIFT (7U) #define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) +/*! @} */ /* The count of ADC_HC */ #define ADC_HC_COUNT (8U) /*! @name HS - Status register for HW triggers */ +/*! @{ */ #define ADC_HS_COCO0_MASK (0x1U) #define ADC_HS_COCO0_SHIFT (0U) #define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) +/*! @} */ /*! @name R - Data result register for HW triggers */ +/*! @{ */ #define ADC_R_CDATA_MASK (0xFFFU) #define ADC_R_CDATA_SHIFT (0U) #define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) +/*! @} */ /* The count of ADC_R */ #define ADC_R_COUNT (8U) /*! @name CFG - Configuration register */ +/*! @{ */ #define ADC_CFG_ADICLK_MASK (0x3U) #define ADC_CFG_ADICLK_SHIFT (0U) #define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) @@ -1378,8 +1402,10 @@ typedef struct { #define ADC_CFG_OVWREN_MASK (0x10000U) #define ADC_CFG_OVWREN_SHIFT (16U) #define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) +/*! @} */ /*! @name GC - General control register */ +/*! @{ */ #define ADC_GC_ADACKEN_MASK (0x1U) #define ADC_GC_ADACKEN_SHIFT (0U) #define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) @@ -1404,8 +1430,10 @@ typedef struct { #define ADC_GC_CAL_MASK (0x80U) #define ADC_GC_CAL_SHIFT (7U) #define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) +/*! @} */ /*! @name GS - General status register */ +/*! @{ */ #define ADC_GS_ADACT_MASK (0x1U) #define ADC_GS_ADACT_SHIFT (0U) #define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) @@ -1415,27 +1443,34 @@ typedef struct { #define ADC_GS_AWKST_MASK (0x4U) #define ADC_GS_AWKST_SHIFT (2U) #define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) +/*! @} */ /*! @name CV - Compare value register */ +/*! @{ */ #define ADC_CV_CV1_MASK (0xFFFU) #define ADC_CV_CV1_SHIFT (0U) #define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) #define ADC_CV_CV2_MASK (0xFFF0000U) #define ADC_CV_CV2_SHIFT (16U) #define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) +/*! @} */ /*! @name OFS - Offset correction value register */ +/*! @{ */ #define ADC_OFS_OFS_MASK (0xFFFU) #define ADC_OFS_OFS_SHIFT (0U) #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) #define ADC_OFS_SIGN_MASK (0x1000U) #define ADC_OFS_SIGN_SHIFT (12U) #define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) +/*! @} */ /*! @name CAL - Calibration value register */ +/*! @{ */ #define ADC_CAL_CAL_CODE_MASK (0xFU) #define ADC_CAL_CAL_CODE_SHIFT (0U) #define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) +/*! @} */ /*! @@ -1480,16 +1515,8 @@ typedef struct { __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */ __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */ struct { /* offset: 0x10, array step: 0x28 */ - __IO uint32_t TRIGn_CTRL; /**< - ETC_TRIG0 Control Register - .. - ETC_TRIG7 Control Register - , array offset: 0x10, array step: 0x28 */ - __IO uint32_t TRIGn_COUNTER; /**< - ETC_TRIG0 Counter Register - .. - ETC_TRIG7 Counter Register - , array offset: 0x14, array step: 0x28 */ + __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG0 Control Register..ETC_TRIG7 Control Register, array offset: 0x10, array step: 0x28 */ + __IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register, array offset: 0x14, array step: 0x28 */ __IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */ __IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */ __IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */ @@ -1511,6 +1538,7 @@ typedef struct { */ /*! @name CTRL - ADC_ETC Global Control Register */ +/*! @{ */ #define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) #define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) #define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) @@ -1529,14 +1557,19 @@ typedef struct { #define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) #define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) #define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) +#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U) +#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U) +#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK) #define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) #define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) #define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) #define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) #define ADC_ETC_CTRL_SOFTRST_SHIFT (31U) #define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) +/*! @} */ /*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */ +/*! @{ */ #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) @@ -1585,8 +1618,10 @@ typedef struct { #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) +/*! @} */ /*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */ +/*! @{ */ #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) @@ -1635,8 +1670,10 @@ typedef struct { #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) +/*! @} */ /*! @name DMA_CTRL - ETC DMA control Register */ +/*! @{ */ #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) @@ -1685,12 +1722,10 @@ typedef struct { #define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) #define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) #define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) +/*! @} */ -/*! @name TRIGn_CTRL - - ETC_TRIG0 Control Register - .. - ETC_TRIG7 Control Register - */ +/*! @name TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register */ +/*! @{ */ #define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) #define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) #define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) @@ -1706,26 +1741,26 @@ typedef struct { #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) #define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_CTRL */ #define ADC_ETC_TRIGn_CTRL_COUNT (8U) -/*! @name TRIGn_COUNTER - - ETC_TRIG0 Counter Register - .. - ETC_TRIG7 Counter Register - */ +/*! @name TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register */ +/*! @{ */ #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_COUNTER */ #define ADC_ETC_TRIGn_COUNTER_COUNT (8U) /*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) @@ -1750,11 +1785,13 @@ typedef struct { #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) #define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_CHAIN_1_0 */ #define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U) /*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) @@ -1779,11 +1816,13 @@ typedef struct { #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) #define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_CHAIN_3_2 */ #define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U) /*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) @@ -1808,11 +1847,13 @@ typedef struct { #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U) #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U) #define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_CHAIN_5_4 */ #define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U) /*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU) #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U) #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK) @@ -1837,50 +1878,59 @@ typedef struct { #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U) #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U) #define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_CHAIN_7_6 */ #define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U) /*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU) #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U) #define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK) #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U) #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U) #define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_RESULT_1_0 */ #define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U) /*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU) #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U) #define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK) #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U) #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U) #define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_RESULT_3_2 */ #define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U) /*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU) #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U) #define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK) #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U) #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U) #define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_RESULT_5_4 */ #define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U) /*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU) #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U) #define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK) #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U) #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U) #define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_RESULT_7_6 */ #define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U) @@ -1939,6 +1989,7 @@ typedef struct { */ /*! @name MPR - Master Priviledge Registers */ +/*! @{ */ #define AIPSTZ_MPR_MPROT5_MASK (0xF00U) #define AIPSTZ_MPR_MPROT5_SHIFT (8U) #define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) @@ -1954,8 +2005,10 @@ typedef struct { #define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) #define AIPSTZ_MPR_MPROT0_SHIFT (28U) #define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) +/*! @} */ /*! @name OPACR - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ #define AIPSTZ_OPACR_OPAC7_MASK (0xFU) #define AIPSTZ_OPACR_OPAC7_SHIFT (0U) #define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) @@ -1980,8 +2033,10 @@ typedef struct { #define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) #define AIPSTZ_OPACR_OPAC0_SHIFT (28U) #define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) +/*! @} */ /*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ #define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) #define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) #define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) @@ -2006,8 +2061,10 @@ typedef struct { #define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) #define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) #define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) +/*! @} */ /*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ #define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) #define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) #define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) @@ -2032,8 +2089,10 @@ typedef struct { #define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) #define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) #define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) +/*! @} */ /*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ #define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) #define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) #define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) @@ -2058,14 +2117,17 @@ typedef struct { #define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) #define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) #define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) +/*! @} */ /*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ #define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) #define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) #define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) #define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) #define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) #define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) +/*! @} */ /*! @@ -2127,6 +2189,7 @@ typedef struct { */ /*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */ +/*! @{ */ #define AOI_BFCRT01_PT1_DC_MASK (0x3U) #define AOI_BFCRT01_PT1_DC_SHIFT (0U) #define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) @@ -2151,11 +2214,13 @@ typedef struct { #define AOI_BFCRT01_PT0_AC_MASK (0xC000U) #define AOI_BFCRT01_PT0_AC_SHIFT (14U) #define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK) +/*! @} */ /* The count of AOI_BFCRT01 */ #define AOI_BFCRT01_COUNT (4U) /*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */ +/*! @{ */ #define AOI_BFCRT23_PT3_DC_MASK (0x3U) #define AOI_BFCRT23_PT3_DC_SHIFT (0U) #define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) @@ -2180,6 +2245,7 @@ typedef struct { #define AOI_BFCRT23_PT2_AC_MASK (0xC000U) #define AOI_BFCRT23_PT2_AC_SHIFT (14U) #define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK) +/*! @} */ /* The count of AOI_BFCRT23 */ #define AOI_BFCRT23_COUNT (4U) @@ -2250,6 +2316,7 @@ typedef struct { */ /*! @name CTRL - BEE Control Register */ +/*! @{ */ #define BEE_CTRL_BEE_ENABLE_MASK (0x1U) #define BEE_CTRL_BEE_ENABLE_SHIFT (0U) #define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK) @@ -2325,100 +2392,135 @@ typedef struct { #define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U) #define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U) #define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK) +/*! @} */ /*! @name ADDR_OFFSET0 - */ +/*! @{ */ #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU) #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U) #define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK) #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U) #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U) #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK) +/*! @} */ /*! @name ADDR_OFFSET1 - */ +/*! @{ */ #define BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK (0xFFFFU) #define BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT (0U) #define BEE_ADDR_OFFSET1_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK) #define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U) #define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT (16U) #define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK) +/*! @} */ /*! @name AES_KEY0_W0 - */ +/*! @{ */ #define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU) #define BEE_AES_KEY0_W0_KEY0_SHIFT (0U) #define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK) +/*! @} */ /*! @name AES_KEY0_W1 - */ +/*! @{ */ #define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU) #define BEE_AES_KEY0_W1_KEY1_SHIFT (0U) #define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK) +/*! @} */ /*! @name AES_KEY0_W2 - */ +/*! @{ */ #define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU) #define BEE_AES_KEY0_W2_KEY2_SHIFT (0U) #define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK) +/*! @} */ /*! @name AES_KEY0_W3 - */ +/*! @{ */ #define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU) #define BEE_AES_KEY0_W3_KEY3_SHIFT (0U) #define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK) +/*! @} */ /*! @name STATUS - */ +/*! @{ */ #define BEE_STATUS_IRQ_VEC_MASK (0xFFU) #define BEE_STATUS_IRQ_VEC_SHIFT (0U) #define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK) #define BEE_STATUS_BEE_IDLE_MASK (0x100U) #define BEE_STATUS_BEE_IDLE_SHIFT (8U) #define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK) +/*! @} */ /*! @name CTR_NONCE0_W0 - */ +/*! @{ */ #define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U) #define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK) +/*! @} */ /*! @name CTR_NONCE0_W1 - */ +/*! @{ */ #define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U) #define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK) +/*! @} */ /*! @name CTR_NONCE0_W2 - */ +/*! @{ */ #define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U) #define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK) +/*! @} */ /*! @name CTR_NONCE0_W3 - */ +/*! @{ */ #define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U) #define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK) +/*! @} */ /*! @name CTR_NONCE1_W0 - */ +/*! @{ */ #define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U) #define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK) +/*! @} */ /*! @name CTR_NONCE1_W1 - */ +/*! @{ */ #define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U) #define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK) +/*! @} */ /*! @name CTR_NONCE1_W2 - */ +/*! @{ */ #define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U) #define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK) +/*! @} */ /*! @name CTR_NONCE1_W3 - */ +/*! @{ */ #define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U) #define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK) +/*! @} */ /*! @name REGION1_TOP - */ +/*! @{ */ #define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU) #define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U) #define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK) +/*! @} */ /*! @name REGION1_BOT - */ +/*! @{ */ #define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU) #define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U) #define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK) +/*! @} */ /*! @@ -2494,6 +2596,7 @@ typedef struct { */ /*! @name MCR - Module Configuration Register */ +/*! @{ */ #define CAN_MCR_MAXMB_MASK (0x7FU) #define CAN_MCR_MAXMB_SHIFT (0U) #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) @@ -2551,8 +2654,10 @@ typedef struct { #define CAN_MCR_MDIS_MASK (0x80000000U) #define CAN_MCR_MDIS_SHIFT (31U) #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) +/*! @} */ /*! @name CTRL1 - Control 1 Register */ +/*! @{ */ #define CAN_CTRL1_PROPSEG_MASK (0x7U) #define CAN_CTRL1_PROPSEG_SHIFT (0U) #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) @@ -2598,36 +2703,48 @@ typedef struct { #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) #define CAN_CTRL1_PRESDIV_SHIFT (24U) #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) +/*! @} */ /*! @name TIMER - Free Running Timer Register */ +/*! @{ */ #define CAN_TIMER_TIMER_MASK (0xFFFFU) #define CAN_TIMER_TIMER_SHIFT (0U) #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) +/*! @} */ /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ +/*! @{ */ #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) #define CAN_RXMGMASK_MG_SHIFT (0U) #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) +/*! @} */ /*! @name RX14MASK - Rx Buffer 14 Mask Register */ +/*! @{ */ #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) #define CAN_RX14MASK_RX14M_SHIFT (0U) #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) +/*! @} */ /*! @name RX15MASK - Rx Buffer 15 Mask Register */ +/*! @{ */ #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) #define CAN_RX15MASK_RX15M_SHIFT (0U) #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) +/*! @} */ /*! @name ECR - Error Counter Register */ +/*! @{ */ #define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU) #define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U) #define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK) #define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U) #define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U) #define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK) +/*! @} */ /*! @name ESR1 - Error and Status 1 Register */ +/*! @{ */ #define CAN_ESR1_WAKINT_MASK (0x1U) #define CAN_ESR1_WAKINT_SHIFT (0U) #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) @@ -2682,23 +2799,31 @@ typedef struct { #define CAN_ESR1_SYNCH_MASK (0x40000U) #define CAN_ESR1_SYNCH_SHIFT (18U) #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) +/*! @} */ /*! @name IMASK2 - Interrupt Masks 2 Register */ +/*! @{ */ #define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU) #define CAN_IMASK2_BUFHM_SHIFT (0U) #define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK) +/*! @} */ /*! @name IMASK1 - Interrupt Masks 1 Register */ +/*! @{ */ #define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) #define CAN_IMASK1_BUFLM_SHIFT (0U) #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) +/*! @} */ /*! @name IFLAG2 - Interrupt Flags 2 Register */ +/*! @{ */ #define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU) #define CAN_IFLAG2_BUFHI_SHIFT (0U) #define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK) +/*! @} */ /*! @name IFLAG1 - Interrupt Flags 1 Register */ +/*! @{ */ #define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU) #define CAN_IFLAG1_BUF4TO0I_SHIFT (0U) #define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK) @@ -2714,8 +2839,10 @@ typedef struct { #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) +/*! @} */ /*! @name CTRL2 - Control 2 Register */ +/*! @{ */ #define CAN_CTRL2_EACEN_MASK (0x10000U) #define CAN_CTRL2_EACEN_SHIFT (16U) #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) @@ -2734,8 +2861,10 @@ typedef struct { #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) #define CAN_CTRL2_WRMFRZ_SHIFT (28U) #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) +/*! @} */ /*! @name ESR2 - Error and Status 2 Register */ +/*! @{ */ #define CAN_ESR2_IMB_MASK (0x2000U) #define CAN_ESR2_IMB_SHIFT (13U) #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) @@ -2745,26 +2874,34 @@ typedef struct { #define CAN_ESR2_LPTM_MASK (0x7F0000U) #define CAN_ESR2_LPTM_SHIFT (16U) #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) +/*! @} */ /*! @name CRCR - CRC Register */ +/*! @{ */ #define CAN_CRCR_TXCRC_MASK (0x7FFFU) #define CAN_CRCR_TXCRC_SHIFT (0U) #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) #define CAN_CRCR_MBCRC_MASK (0x7F0000U) #define CAN_CRCR_MBCRC_SHIFT (16U) #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) +/*! @} */ /*! @name RXFGMASK - Rx FIFO Global Mask Register */ +/*! @{ */ #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) #define CAN_RXFGMASK_FGM_SHIFT (0U) #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) +/*! @} */ /*! @name RXFIR - Rx FIFO Information Register */ +/*! @{ */ #define CAN_RXFIR_IDHIT_MASK (0x1FFU) #define CAN_RXFIR_IDHIT_SHIFT (0U) #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) +/*! @} */ /*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */ +/*! @{ */ #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) #define CAN_CS_TIME_STAMP_SHIFT (0U) #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) @@ -2783,11 +2920,13 @@ typedef struct { #define CAN_CS_CODE_MASK (0xF000000U) #define CAN_CS_CODE_SHIFT (24U) #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) +/*! @} */ /* The count of CAN_CS */ #define CAN_CS_COUNT (64U) /*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */ +/*! @{ */ #define CAN_ID_EXT_MASK (0x3FFFFU) #define CAN_ID_EXT_SHIFT (0U) #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) @@ -2797,11 +2936,13 @@ typedef struct { #define CAN_ID_PRIO_MASK (0xE0000000U) #define CAN_ID_PRIO_SHIFT (29U) #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) +/*! @} */ /* The count of CAN_ID */ #define CAN_ID_COUNT (64U) /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */ +/*! @{ */ #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) @@ -2814,11 +2955,13 @@ typedef struct { #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) +/*! @} */ /* The count of CAN_WORD0 */ #define CAN_WORD0_COUNT (64U) /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */ +/*! @{ */ #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) @@ -2831,22 +2974,27 @@ typedef struct { #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) +/*! @} */ /* The count of CAN_WORD1 */ #define CAN_WORD1_COUNT (64U) /*! @name RXIMR - Rx Individual Mask Registers */ +/*! @{ */ #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) #define CAN_RXIMR_MI_SHIFT (0U) #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) +/*! @} */ /* The count of CAN_RXIMR */ #define CAN_RXIMR_COUNT (64U) /*! @name GFWR - Glitch Filter Width Registers */ +/*! @{ */ #define CAN_GFWR_GFWR_MASK (0xFFU) #define CAN_GFWR_GFWR_SHIFT (0U) #define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK) +/*! @} */ /*! @@ -2944,6 +3092,7 @@ typedef struct { */ /*! @name CCR - CCM Control Register */ +/*! @{ */ #define CCM_CCR_OSCNT_MASK (0xFFU) #define CCM_CCR_OSCNT_SHIFT (0U) #define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK) @@ -2956,8 +3105,10 @@ typedef struct { #define CCM_CCR_RBC_EN_MASK (0x8000000U) #define CCM_CCR_RBC_EN_SHIFT (27U) #define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK) +/*! @} */ /*! @name CSR - CCM Status Register */ +/*! @{ */ #define CCM_CSR_REF_EN_B_MASK (0x1U) #define CCM_CSR_REF_EN_B_SHIFT (0U) #define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK) @@ -2967,18 +3118,24 @@ typedef struct { #define CCM_CSR_COSC_READY_MASK (0x20U) #define CCM_CSR_COSC_READY_SHIFT (5U) #define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK) +/*! @} */ /*! @name CCSR - CCM Clock Switcher Register */ +/*! @{ */ #define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U) #define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U) #define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) +/*! @} */ /*! @name CACRR - CCM Arm Clock Root Register */ +/*! @{ */ #define CCM_CACRR_ARM_PODF_MASK (0x7U) #define CCM_CACRR_ARM_PODF_SHIFT (0U) #define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK) +/*! @} */ /*! @name CBCDR - CCM Bus Clock Divider Register */ +/*! @{ */ #define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U) #define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U) #define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK) @@ -3000,8 +3157,10 @@ typedef struct { #define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U) #define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U) #define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) +/*! @} */ /*! @name CBCMR - CCM Bus Clock Multiplexer Register */ +/*! @{ */ #define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U) #define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U) #define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK) @@ -3020,8 +3179,10 @@ typedef struct { #define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U) #define CCM_CBCMR_LPSPI_PODF_SHIFT (26U) #define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK) +/*! @} */ /*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */ +/*! @{ */ #define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU) #define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U) #define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK) @@ -3049,8 +3210,10 @@ typedef struct { #define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U) #define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U) #define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK) +/*! @} */ /*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */ +/*! @{ */ #define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU) #define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U) #define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK) @@ -3060,8 +3223,10 @@ typedef struct { #define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U) #define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U) #define CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK) +/*! @} */ /*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */ +/*! @{ */ #define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU) #define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U) #define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK) @@ -3074,11 +3239,13 @@ typedef struct { #define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U) #define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U) #define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK) -#define CCM_CSCDR1_TRACE_PODF_MASK (0xE000000U) +#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U) #define CCM_CSCDR1_TRACE_PODF_SHIFT (25U) #define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK) +/*! @} */ /*! @name CS1CDR - CCM Clock Divider Register */ +/*! @{ */ #define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU) #define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U) #define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK) @@ -3097,16 +3264,20 @@ typedef struct { #define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U) #define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U) #define CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK) +/*! @} */ /*! @name CS2CDR - CCM Clock Divider Register */ +/*! @{ */ #define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU) #define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U) #define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK) #define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U) #define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U) #define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK) +/*! @} */ /*! @name CDCDR - CCM D1 Clock Divider Register */ +/*! @{ */ #define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U) #define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U) #define CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK) @@ -3125,11 +3296,10 @@ typedef struct { #define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U) #define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U) #define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK) +/*! @} */ /*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */ -#define CCM_CSCDR2_LCDIF_CLK_SEL_MASK (0xE00U) -#define CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT (9U) -#define CCM_CSCDR2_LCDIF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_CLK_SEL_MASK) +/*! @{ */ #define CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U) #define CCM_CSCDR2_LCDIF_PRED_SHIFT (12U) #define CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK) @@ -3142,16 +3312,20 @@ typedef struct { #define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U) #define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U) #define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK) +/*! @} */ /*! @name CSCDR3 - CCM Serial Clock Divider Register 3 */ +/*! @{ */ #define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U) #define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U) #define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK) #define CCM_CSCDR3_CSI_PODF_MASK (0x3800U) #define CCM_CSCDR3_CSI_PODF_SHIFT (11U) #define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK) +/*! @} */ /*! @name CDHIPR - CCM Divider Handshake In-Process Register */ +/*! @{ */ #define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U) #define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U) #define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK) @@ -3167,8 +3341,10 @@ typedef struct { #define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U) #define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U) #define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK) +/*! @} */ /*! @name CLPCR - CCM Low Power Control Register */ +/*! @{ */ #define CCM_CLPCR_LPM_MASK (0x3U) #define CCM_CLPCR_LPM_SHIFT (0U) #define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK) @@ -3205,8 +3381,10 @@ typedef struct { #define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U) #define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U) #define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK) +/*! @} */ /*! @name CISR - CCM Interrupt Status Register */ +/*! @{ */ #define CCM_CISR_LRF_PLL_MASK (0x1U) #define CCM_CISR_LRF_PLL_SHIFT (0U) #define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK) @@ -3228,8 +3406,10 @@ typedef struct { #define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U) #define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U) #define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK) +/*! @} */ /*! @name CIMR - CCM Interrupt Mask Register */ +/*! @{ */ #define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U) #define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U) #define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK) @@ -3251,8 +3431,10 @@ typedef struct { #define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U) #define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U) #define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK) +/*! @} */ /*! @name CCOSR - CCM Clock Output Source Register */ +/*! @{ */ #define CCM_CCOSR_CLKO1_SEL_MASK (0xFU) #define CCM_CCOSR_CLKO1_SEL_SHIFT (0U) #define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK) @@ -3274,8 +3456,10 @@ typedef struct { #define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U) #define CCM_CCOSR_CLKO2_EN_SHIFT (24U) #define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK) +/*! @} */ /*! @name CGPR - CCM General Purpose Register */ +/*! @{ */ #define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U) #define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U) #define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK) @@ -3291,8 +3475,10 @@ typedef struct { #define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U) #define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U) #define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK) +/*! @} */ /*! @name CCGR0 - CCM Clock Gating Register 0 */ +/*! @{ */ #define CCM_CCGR0_CG0_MASK (0x3U) #define CCM_CCGR0_CG0_SHIFT (0U) #define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK) @@ -3341,8 +3527,10 @@ typedef struct { #define CCM_CCGR0_CG15_MASK (0xC0000000U) #define CCM_CCGR0_CG15_SHIFT (30U) #define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK) +/*! @} */ /*! @name CCGR1 - CCM Clock Gating Register 1 */ +/*! @{ */ #define CCM_CCGR1_CG0_MASK (0x3U) #define CCM_CCGR1_CG0_SHIFT (0U) #define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK) @@ -3391,8 +3579,10 @@ typedef struct { #define CCM_CCGR1_CG15_MASK (0xC0000000U) #define CCM_CCGR1_CG15_SHIFT (30U) #define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK) +/*! @} */ /*! @name CCGR2 - CCM Clock Gating Register 2 */ +/*! @{ */ #define CCM_CCGR2_CG0_MASK (0x3U) #define CCM_CCGR2_CG0_SHIFT (0U) #define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK) @@ -3441,8 +3631,10 @@ typedef struct { #define CCM_CCGR2_CG15_MASK (0xC0000000U) #define CCM_CCGR2_CG15_SHIFT (30U) #define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK) +/*! @} */ /*! @name CCGR3 - CCM Clock Gating Register 3 */ +/*! @{ */ #define CCM_CCGR3_CG0_MASK (0x3U) #define CCM_CCGR3_CG0_SHIFT (0U) #define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK) @@ -3491,8 +3683,10 @@ typedef struct { #define CCM_CCGR3_CG15_MASK (0xC0000000U) #define CCM_CCGR3_CG15_SHIFT (30U) #define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK) +/*! @} */ /*! @name CCGR4 - CCM Clock Gating Register 4 */ +/*! @{ */ #define CCM_CCGR4_CG0_MASK (0x3U) #define CCM_CCGR4_CG0_SHIFT (0U) #define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK) @@ -3541,8 +3735,10 @@ typedef struct { #define CCM_CCGR4_CG15_MASK (0xC0000000U) #define CCM_CCGR4_CG15_SHIFT (30U) #define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK) +/*! @} */ /*! @name CCGR5 - CCM Clock Gating Register 5 */ +/*! @{ */ #define CCM_CCGR5_CG0_MASK (0x3U) #define CCM_CCGR5_CG0_SHIFT (0U) #define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK) @@ -3591,8 +3787,10 @@ typedef struct { #define CCM_CCGR5_CG15_MASK (0xC0000000U) #define CCM_CCGR5_CG15_SHIFT (30U) #define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK) +/*! @} */ /*! @name CCGR6 - CCM Clock Gating Register 6 */ +/*! @{ */ #define CCM_CCGR6_CG0_MASK (0x3U) #define CCM_CCGR6_CG0_SHIFT (0U) #define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK) @@ -3641,8 +3839,10 @@ typedef struct { #define CCM_CCGR6_CG15_MASK (0xC0000000U) #define CCM_CCGR6_CG15_SHIFT (30U) #define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK) +/*! @} */ /*! @name CMEOR - CCM Module Enable Overide Register */ +/*! @{ */ #define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U) #define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U) #define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK) @@ -3661,6 +3861,7 @@ typedef struct { #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U) #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U) #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK) +/*! @} */ /*! @@ -3771,6 +3972,7 @@ typedef struct { */ /*! @name PLL_ARM - Analog ARM PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) @@ -3792,8 +3994,10 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK) +/*! @} */ /*! @name PLL_ARM_SET - Analog ARM PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK) @@ -3815,8 +4019,10 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_ARM_CLR - Analog ARM PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK) @@ -3838,8 +4044,10 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_ARM_TOG - Analog ARM PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK) @@ -3861,10 +4069,12 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U) @@ -3884,10 +4094,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK) +/*! @} */ /*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U) @@ -3907,10 +4119,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U) @@ -3930,10 +4144,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U) @@ -3953,10 +4169,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U) @@ -3976,10 +4194,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK) +/*! @} */ /*! @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U) @@ -3999,10 +4219,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U) @@ -4022,10 +4244,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U) @@ -4045,8 +4269,10 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_SYS - Analog System PLL Control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U) #define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) @@ -4068,8 +4294,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK) +/*! @} */ /*! @name PLL_SYS_SET - Analog System PLL Control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U) #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK) @@ -4091,8 +4319,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_SYS_CLR - Analog System PLL Control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U) #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK) @@ -4114,8 +4344,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_SYS_TOG - Analog System PLL Control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U) #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK) @@ -4137,8 +4369,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU) #define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK) @@ -4148,18 +4382,24 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U) #define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U) #define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK) +/*! @} */ /*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK) +/*! @} */ /*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK) +/*! @} */ /*! @name PLL_AUDIO - Analog Audio PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) @@ -4184,8 +4424,10 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) +/*! @} */ /*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) @@ -4210,8 +4452,10 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) @@ -4236,8 +4480,10 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) @@ -4262,18 +4508,24 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) +/*! @} */ /*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) +/*! @} */ /*! @name PLL_VIDEO - Analog Video PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) @@ -4298,8 +4550,10 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) +/*! @} */ /*! @name PLL_VIDEO_SET - Analog Video PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) @@ -4324,8 +4578,10 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_VIDEO_CLR - Analog Video PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) @@ -4350,8 +4606,10 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_VIDEO_TOG - Analog Video PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) @@ -4376,30 +4634,33 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) +/*! @} */ /*! @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) +/*! @} */ /*! @name PLL_ENET - Analog ENET PLL Control Register */ -#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0xCU) -#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2U) -#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK) +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U) #define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U) #define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK (0x2000U) -#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT (13U) -#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK) #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U) #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK) @@ -4409,32 +4670,25 @@ typedef struct { #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U) #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U) #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK (0x80000U) -#define CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT (19U) -#define CCM_ANALOG_PLL_ENET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK) -#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK (0x100000U) -#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT (20U) -#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK) #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U) #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U) #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK) #define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK) +/*! @} */ /*! @name PLL_ENET_SET - Analog ENET PLL Control Register */ -#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK (0xCU) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT (2U) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK) +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U) #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U) #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK (0x2000U) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT (13U) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK) #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U) #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK) @@ -4444,32 +4698,25 @@ typedef struct { #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U) #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U) #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK (0x80000U) -#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT (19U) -#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK) -#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK (0x100000U) -#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT (20U) -#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK) #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U) #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U) #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK) #define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */ -#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK (0xCU) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT (2U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK) +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U) #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U) #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK (0x2000U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT (13U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK) #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U) #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK) @@ -4479,32 +4726,25 @@ typedef struct { #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U) #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U) #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK (0x80000U) -#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT (19U) -#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK (0x100000U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT (20U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK) #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U) #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U) #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK) #define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */ -#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK (0xCU) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT (2U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK) +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U) #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U) #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK (0x2000U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT (13U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK) #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U) #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK) @@ -4514,20 +4754,16 @@ typedef struct { #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U) #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U) #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK (0x80000U) -#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT (19U) -#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK (0x100000U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT (20U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK) #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U) #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U) #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK) #define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK) +/*! @} */ /*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) @@ -4564,8 +4800,10 @@ typedef struct { #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK) @@ -4602,8 +4840,10 @@ typedef struct { #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK) @@ -4640,8 +4880,10 @@ typedef struct { #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) @@ -4678,8 +4920,10 @@ typedef struct { #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) @@ -4716,8 +4960,10 @@ typedef struct { #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK) @@ -4754,8 +5000,10 @@ typedef struct { #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK) @@ -4792,8 +5040,10 @@ typedef struct { #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK) @@ -4830,8 +5080,10 @@ typedef struct { #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ #define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U) #define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U) #define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK) @@ -4871,11 +5123,10 @@ typedef struct { #define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U) #define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U) #define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK) -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT (31U) -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U) #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U) #define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK) @@ -4915,11 +5166,10 @@ typedef struct { #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK) -#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) -#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) -#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U) #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U) #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK) @@ -4959,11 +5209,10 @@ typedef struct { #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK) -#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) -#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) -#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U) #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U) #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK) @@ -5003,11 +5252,10 @@ typedef struct { #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK) -#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) -#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) -#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC1 - Miscellaneous Register 1 */ +/*! @{ */ #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U) #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK) @@ -5038,8 +5286,10 @@ typedef struct { #define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U) #define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U) #define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_SET - Miscellaneous Register 1 */ +/*! @{ */ #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK) @@ -5070,8 +5320,10 @@ typedef struct { #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_CLR - Miscellaneous Register 1 */ +/*! @{ */ #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK) @@ -5102,8 +5354,10 @@ typedef struct { #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_TOG - Miscellaneous Register 1 */ +/*! @{ */ #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK) @@ -5134,8 +5388,10 @@ typedef struct { #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC2 - Miscellaneous Register 2 */ +/*! @{ */ #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U) #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U) #define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK) @@ -5193,8 +5449,10 @@ typedef struct { #define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U) #define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U) #define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_SET - Miscellaneous Register 2 */ +/*! @{ */ #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK) @@ -5252,8 +5510,10 @@ typedef struct { #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U) #define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_CLR - Miscellaneous Register 2 */ +/*! @{ */ #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK) @@ -5311,8 +5571,10 @@ typedef struct { #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U) #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_TOG - Miscellaneous Register 2 */ +/*! @{ */ #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK) @@ -5370,6 +5632,7 @@ typedef struct { #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U) #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK) +/*! @} */ /*! @@ -5421,14 +5684,17 @@ typedef struct { */ /*! @name CR0 - CMP Control Register 0 */ +/*! @{ */ #define CMP_CR0_HYSTCTR_MASK (0x3U) #define CMP_CR0_HYSTCTR_SHIFT (0U) #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) #define CMP_CR0_FILTER_CNT_MASK (0x70U) #define CMP_CR0_FILTER_CNT_SHIFT (4U) #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) +/*! @} */ /*! @name CR1 - CMP Control Register 1 */ +/*! @{ */ #define CMP_CR1_EN_MASK (0x1U) #define CMP_CR1_EN_SHIFT (0U) #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) @@ -5450,13 +5716,17 @@ typedef struct { #define CMP_CR1_SE_MASK (0x80U) #define CMP_CR1_SE_SHIFT (7U) #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) +/*! @} */ /*! @name FPR - CMP Filter Period Register */ +/*! @{ */ #define CMP_FPR_FILT_PER_MASK (0xFFU) #define CMP_FPR_FILT_PER_SHIFT (0U) #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) +/*! @} */ /*! @name SCR - CMP Status and Control Register */ +/*! @{ */ #define CMP_SCR_COUT_MASK (0x1U) #define CMP_SCR_COUT_SHIFT (0U) #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) @@ -5475,8 +5745,10 @@ typedef struct { #define CMP_SCR_DMAEN_MASK (0x40U) #define CMP_SCR_DMAEN_SHIFT (6U) #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) +/*! @} */ /*! @name DACCR - DAC Control Register */ +/*! @{ */ #define CMP_DACCR_VOSEL_MASK (0x3FU) #define CMP_DACCR_VOSEL_SHIFT (0U) #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) @@ -5486,14 +5758,17 @@ typedef struct { #define CMP_DACCR_DACEN_MASK (0x80U) #define CMP_DACCR_DACEN_SHIFT (7U) #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) +/*! @} */ /*! @name MUXCR - MUX Control Register */ +/*! @{ */ #define CMP_MUXCR_MSEL_MASK (0x7U) #define CMP_MUXCR_MSEL_SHIFT (0U) #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) #define CMP_MUXCR_PSEL_MASK (0x38U) #define CMP_MUXCR_PSEL_SHIFT (3U) #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) +/*! @} */ /*! @@ -5570,6 +5845,7 @@ typedef struct { */ /*! @name CSICR1 - CSI Control Register 1 */ +/*! @{ */ #define CSI_CSICR1_PIXEL_BIT_MASK (0x1U) #define CSI_CSICR1_PIXEL_BIT_SHIFT (0U) #define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK) @@ -5648,8 +5924,10 @@ typedef struct { #define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U) #define CSI_CSICR1_SWAP16_EN_SHIFT (31U) #define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK) +/*! @} */ /*! @name CSICR2 - CSI Control Register 2 */ +/*! @{ */ #define CSI_CSICR2_HSC_MASK (0xFFU) #define CSI_CSICR2_HSC_SHIFT (0U) #define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK) @@ -5677,8 +5955,10 @@ typedef struct { #define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U) #define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U) #define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK) +/*! @} */ /*! @name CSICR3 - CSI Control Register 3 */ +/*! @{ */ #define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U) #define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U) #define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK) @@ -5718,23 +5998,31 @@ typedef struct { #define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U) #define CSI_CSICR3_FRMCNT_SHIFT (16U) #define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK) +/*! @} */ /*! @name CSISTATFIFO - CSI Statistic FIFO Register */ +/*! @{ */ #define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU) #define CSI_CSISTATFIFO_STAT_SHIFT (0U) #define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK) +/*! @} */ /*! @name CSIRFIFO - CSI RX FIFO Register */ +/*! @{ */ #define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU) #define CSI_CSIRFIFO_IMAGE_SHIFT (0U) #define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK) +/*! @} */ /*! @name CSIRXCNT - CSI RX Count Register */ +/*! @{ */ #define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU) #define CSI_CSIRXCNT_RXCNT_SHIFT (0U) #define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK) +/*! @} */ /*! @name CSISR - CSI Status Register */ +/*! @{ */ #define CSI_CSISR_DRDY_MASK (0x1U) #define CSI_CSISR_DRDY_SHIFT (0U) #define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK) @@ -5789,44 +6077,58 @@ typedef struct { #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U) #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U) #define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK) +/*! @} */ /*! @name CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */ +/*! @{ */ #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU) #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U) #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK) +/*! @} */ /*! @name CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */ +/*! @{ */ #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU) #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U) #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK) +/*! @} */ /*! @name CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */ +/*! @{ */ #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU) #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U) #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK) +/*! @} */ /*! @name CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */ +/*! @{ */ #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU) #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U) #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK) +/*! @} */ /*! @name CSIFBUF_PARA - CSI Frame Buffer Parameter Register */ +/*! @{ */ #define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU) #define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U) #define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK) #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U) #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U) #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK) +/*! @} */ /*! @name CSIIMAG_PARA - CSI Image Parameter Register */ +/*! @{ */ #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU) #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U) #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK) #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U) #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U) #define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK) +/*! @} */ /*! @name CSICR18 - CSI Control Register 18 */ +/*! @{ */ #define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U) #define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U) #define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK) @@ -5857,20 +6159,20 @@ typedef struct { #define CSI_CSICR18_AHB_HPROT_MASK (0xF000U) #define CSI_CSICR18_AHB_HPROT_SHIFT (12U) #define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK) -#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK (0x30000U) -#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT (16U) -#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT)) & CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK) #define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U) #define CSI_CSICR18_MASK_OPTION_SHIFT (18U) #define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK) #define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U) #define CSI_CSICR18_CSI_ENABLE_SHIFT (31U) #define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK) +/*! @} */ /*! @name CSICR19 - CSI Control Register 19 */ +/*! @{ */ #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU) #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U) #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK) +/*! @} */ /*! @@ -5925,6 +6227,7 @@ typedef struct { */ /*! @name CSL - Config security level register */ +/*! @{ */ #define CSU_CSL_SUR_S2_MASK (0x1U) #define CSU_CSL_SUR_S2_SHIFT (0U) #define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK) @@ -5979,11 +6282,13 @@ typedef struct { #define CSU_CSL_LOCK_S1_MASK (0x1000000U) #define CSU_CSL_LOCK_S1_SHIFT (24U) #define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK) +/*! @} */ /* The count of CSU_CSL */ #define CSU_CSL_COUNT (32U) /*! @name HP0 - HP0 register */ +/*! @{ */ #define CSU_HP0_HP_DMA_MASK (0x4U) #define CSU_HP0_HP_DMA_SHIFT (2U) #define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK) @@ -6044,8 +6349,10 @@ typedef struct { #define CSU_HP0_L_USB_MASK (0x800000U) #define CSU_HP0_L_USB_SHIFT (23U) #define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK) +/*! @} */ /*! @name SA - Secure access register */ +/*! @{ */ #define CSU_SA_NSA_DMA_MASK (0x4U) #define CSU_SA_NSA_DMA_SHIFT (2U) #define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK) @@ -6106,8 +6413,10 @@ typedef struct { #define CSU_SA_L_USB_MASK (0x800000U) #define CSU_SA_L_USB_SHIFT (23U) #define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK) +/*! @} */ /*! @name HPCONTROL0 - HPCONTROL0 register */ +/*! @{ */ #define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U) #define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U) #define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK) @@ -6168,6 +6477,7 @@ typedef struct { #define CSU_HPCONTROL0_L_USB_MASK (0x800000U) #define CSU_HPCONTROL0_L_USB_SHIFT (23U) #define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK) +/*! @} */ /*! @@ -6217,6 +6527,7 @@ typedef struct { */ /*! @name REG0 - DCDC Register 0 */ +/*! @{ */ #define DCDC_REG0_PWD_ZCD_MASK (0x1U) #define DCDC_REG0_PWD_ZCD_SHIFT (0U) #define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK) @@ -6277,8 +6588,10 @@ typedef struct { #define DCDC_REG0_STS_DC_OK_MASK (0x80000000U) #define DCDC_REG0_STS_DC_OK_SHIFT (31U) #define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK) +/*! @} */ /*! @name REG1 - DCDC Register 1 */ +/*! @{ */ #define DCDC_REG1_REG_FBK_SEL_MASK (0x180U) #define DCDC_REG1_REG_FBK_SEL_SHIFT (7U) #define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK) @@ -6297,8 +6610,10 @@ typedef struct { #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) #define DCDC_REG1_VBG_TRIM_SHIFT (24U) #define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK) +/*! @} */ /*! @name REG2 - DCDC Register 2 */ +/*! @{ */ #define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U) #define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U) #define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK) @@ -6323,8 +6638,10 @@ typedef struct { #define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U) #define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U) #define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK) +/*! @} */ /*! @name REG3 - DCDC Register 3 */ +/*! @{ */ #define DCDC_REG3_TRG_MASK (0x1FU) #define DCDC_REG3_TRG_SHIFT (0U) #define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK) @@ -6343,6 +6660,7 @@ typedef struct { #define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U) #define DCDC_REG3_DISABLE_STEP_SHIFT (30U) #define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK) +/*! @} */ /*! @@ -6459,6 +6777,7 @@ typedef struct { */ /*! @name CTRL - DCP control register 0 */ +/*! @{ */ #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK) @@ -6486,8 +6805,10 @@ typedef struct { #define DCP_CTRL_SFTRST_MASK (0x80000000U) #define DCP_CTRL_SFTRST_SHIFT (31U) #define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK) +/*! @} */ /*! @name STAT - DCP status register */ +/*! @{ */ #define DCP_STAT_IRQ_MASK (0xFU) #define DCP_STAT_IRQ_SHIFT (0U) #define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK) @@ -6503,8 +6824,10 @@ typedef struct { #define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U) #define DCP_STAT_OTP_KEY_READY_SHIFT (28U) #define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK) +/*! @} */ /*! @name CHANNELCTRL - DCP channel control register */ +/*! @{ */ #define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU) #define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U) #define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK) @@ -6517,8 +6840,10 @@ typedef struct { #define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U) #define DCP_CHANNELCTRL_RSVD_SHIFT (17U) #define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK) +/*! @} */ /*! @name CAPABILITY0 - DCP capability 0 register */ +/*! @{ */ #define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU) #define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U) #define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK) @@ -6534,21 +6859,27 @@ typedef struct { #define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U) #define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U) #define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK) +/*! @} */ /*! @name CAPABILITY1 - DCP capability 1 register */ +/*! @{ */ #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU) #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U) #define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK) #define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U) #define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U) #define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK) +/*! @} */ /*! @name CONTEXT - DCP context buffer pointer */ +/*! @{ */ #define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU) #define DCP_CONTEXT_ADDR_SHIFT (0U) #define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK) +/*! @} */ /*! @name KEY - DCP key index */ +/*! @{ */ #define DCP_KEY_SUBWORD_MASK (0x3U) #define DCP_KEY_SUBWORD_SHIFT (0U) #define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK) @@ -6564,18 +6895,24 @@ typedef struct { #define DCP_KEY_RSVD_MASK (0xFFFFFF00U) #define DCP_KEY_RSVD_SHIFT (8U) #define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK) +/*! @} */ /*! @name KEYDATA - DCP key data */ +/*! @{ */ #define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU) #define DCP_KEYDATA_DATA_SHIFT (0U) #define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK) +/*! @} */ /*! @name PACKET0 - DCP work packet 0 status register */ +/*! @{ */ #define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU) #define DCP_PACKET0_ADDR_SHIFT (0U) #define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK) +/*! @} */ /*! @name PACKET1 - DCP work packet 1 status register */ +/*! @{ */ #define DCP_PACKET1_INTERRUPT_MASK (0x1U) #define DCP_PACKET1_INTERRUPT_SHIFT (0U) #define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK) @@ -6651,8 +6988,10 @@ typedef struct { #define DCP_PACKET1_TAG_MASK (0xFF000000U) #define DCP_PACKET1_TAG_SHIFT (24U) #define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK) +/*! @} */ /*! @name PACKET2 - DCP work packet 2 status register */ +/*! @{ */ #define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU) #define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U) #define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK) @@ -6671,41 +7010,55 @@ typedef struct { #define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U) #define DCP_PACKET2_CIPHER_CFG_SHIFT (24U) #define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK) +/*! @} */ /*! @name PACKET3 - DCP work packet 3 status register */ +/*! @{ */ #define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU) #define DCP_PACKET3_ADDR_SHIFT (0U) #define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK) +/*! @} */ /*! @name PACKET4 - DCP work packet 4 status register */ +/*! @{ */ #define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU) #define DCP_PACKET4_ADDR_SHIFT (0U) #define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK) +/*! @} */ /*! @name PACKET5 - DCP work packet 5 status register */ +/*! @{ */ #define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU) #define DCP_PACKET5_COUNT_SHIFT (0U) #define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK) +/*! @} */ /*! @name PACKET6 - DCP work packet 6 status register */ +/*! @{ */ #define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU) #define DCP_PACKET6_ADDR_SHIFT (0U) #define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK) +/*! @} */ /*! @name CH0CMDPTR - DCP channel 0 command pointer address register */ +/*! @{ */ #define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU) #define DCP_CH0CMDPTR_ADDR_SHIFT (0U) #define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK) +/*! @} */ /*! @name CH0SEMA - DCP channel 0 semaphore register */ +/*! @{ */ #define DCP_CH0SEMA_INCREMENT_MASK (0xFFU) #define DCP_CH0SEMA_INCREMENT_SHIFT (0U) #define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK) #define DCP_CH0SEMA_VALUE_MASK (0xFF0000U) #define DCP_CH0SEMA_VALUE_SHIFT (16U) #define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK) +/*! @} */ /*! @name CH0STAT - DCP channel 0 status register */ +/*! @{ */ #define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U) #define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U) #define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK) @@ -6733,29 +7086,37 @@ typedef struct { #define DCP_CH0STAT_TAG_MASK (0xFF000000U) #define DCP_CH0STAT_TAG_SHIFT (24U) #define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK) +/*! @} */ /*! @name CH0OPTS - DCP channel 0 options register */ +/*! @{ */ #define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU) #define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U) #define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK) #define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U) #define DCP_CH0OPTS_RSVD_SHIFT (16U) #define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK) +/*! @} */ /*! @name CH1CMDPTR - DCP channel 1 command pointer address register */ +/*! @{ */ #define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU) #define DCP_CH1CMDPTR_ADDR_SHIFT (0U) #define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK) +/*! @} */ /*! @name CH1SEMA - DCP channel 1 semaphore register */ +/*! @{ */ #define DCP_CH1SEMA_INCREMENT_MASK (0xFFU) #define DCP_CH1SEMA_INCREMENT_SHIFT (0U) #define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK) #define DCP_CH1SEMA_VALUE_MASK (0xFF0000U) #define DCP_CH1SEMA_VALUE_SHIFT (16U) #define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK) +/*! @} */ /*! @name CH1STAT - DCP channel 1 status register */ +/*! @{ */ #define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U) #define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U) #define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK) @@ -6783,29 +7144,37 @@ typedef struct { #define DCP_CH1STAT_TAG_MASK (0xFF000000U) #define DCP_CH1STAT_TAG_SHIFT (24U) #define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK) +/*! @} */ /*! @name CH1OPTS - DCP channel 1 options register */ +/*! @{ */ #define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU) #define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U) #define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK) #define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U) #define DCP_CH1OPTS_RSVD_SHIFT (16U) #define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK) +/*! @} */ /*! @name CH2CMDPTR - DCP channel 2 command pointer address register */ +/*! @{ */ #define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU) #define DCP_CH2CMDPTR_ADDR_SHIFT (0U) #define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK) +/*! @} */ /*! @name CH2SEMA - DCP channel 2 semaphore register */ +/*! @{ */ #define DCP_CH2SEMA_INCREMENT_MASK (0xFFU) #define DCP_CH2SEMA_INCREMENT_SHIFT (0U) #define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK) #define DCP_CH2SEMA_VALUE_MASK (0xFF0000U) #define DCP_CH2SEMA_VALUE_SHIFT (16U) #define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK) +/*! @} */ /*! @name CH2STAT - DCP channel 2 status register */ +/*! @{ */ #define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U) #define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U) #define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK) @@ -6833,29 +7202,37 @@ typedef struct { #define DCP_CH2STAT_TAG_MASK (0xFF000000U) #define DCP_CH2STAT_TAG_SHIFT (24U) #define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK) +/*! @} */ /*! @name CH2OPTS - DCP channel 2 options register */ +/*! @{ */ #define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU) #define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U) #define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK) #define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U) #define DCP_CH2OPTS_RSVD_SHIFT (16U) #define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK) +/*! @} */ /*! @name CH3CMDPTR - DCP channel 3 command pointer address register */ +/*! @{ */ #define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU) #define DCP_CH3CMDPTR_ADDR_SHIFT (0U) #define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK) +/*! @} */ /*! @name CH3SEMA - DCP channel 3 semaphore register */ +/*! @{ */ #define DCP_CH3SEMA_INCREMENT_MASK (0xFFU) #define DCP_CH3SEMA_INCREMENT_SHIFT (0U) #define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK) #define DCP_CH3SEMA_VALUE_MASK (0xFF0000U) #define DCP_CH3SEMA_VALUE_SHIFT (16U) #define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK) +/*! @} */ /*! @name CH3STAT - DCP channel 3 status register */ +/*! @{ */ #define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U) #define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U) #define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK) @@ -6883,29 +7260,37 @@ typedef struct { #define DCP_CH3STAT_TAG_MASK (0xFF000000U) #define DCP_CH3STAT_TAG_SHIFT (24U) #define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK) +/*! @} */ /*! @name CH3OPTS - DCP channel 3 options register */ +/*! @{ */ #define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU) #define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U) #define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK) #define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U) #define DCP_CH3OPTS_RSVD_SHIFT (16U) #define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK) +/*! @} */ /*! @name DBGSELECT - DCP debug select register */ +/*! @{ */ #define DCP_DBGSELECT_INDEX_MASK (0xFFU) #define DCP_DBGSELECT_INDEX_SHIFT (0U) #define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK) #define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U) #define DCP_DBGSELECT_RSVD_SHIFT (8U) #define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK) +/*! @} */ /*! @name DBGDATA - DCP debug data register */ +/*! @{ */ #define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU) #define DCP_DBGDATA_DATA_SHIFT (0U) #define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK) +/*! @} */ /*! @name PAGETABLE - DCP page table register */ +/*! @{ */ #define DCP_PAGETABLE_ENABLE_MASK (0x1U) #define DCP_PAGETABLE_ENABLE_SHIFT (0U) #define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK) @@ -6915,8 +7300,10 @@ typedef struct { #define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU) #define DCP_PAGETABLE_BASE_SHIFT (2U) #define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK) +/*! @} */ /*! @name VERSION - DCP version register */ +/*! @{ */ #define DCP_VERSION_STEP_MASK (0xFFFFU) #define DCP_VERSION_STEP_SHIFT (0U) #define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK) @@ -6926,6 +7313,7 @@ typedef struct { #define DCP_VERSION_MAJOR_MASK (0xFF000000U) #define DCP_VERSION_MAJOR_SHIFT (24U) #define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK) +/*! @} */ /*! @@ -7053,6 +7441,7 @@ typedef struct { */ /*! @name CR - Control Register */ +/*! @{ */ #define DMA_CR_EDBG_MASK (0x2U) #define DMA_CR_EDBG_SHIFT (1U) #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) @@ -7089,8 +7478,10 @@ typedef struct { #define DMA_CR_ACTIVE_MASK (0x80000000U) #define DMA_CR_ACTIVE_SHIFT (31U) #define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) +/*! @} */ /*! @name ES - Error Status Register */ +/*! @{ */ #define DMA_ES_DBE_MASK (0x1U) #define DMA_ES_DBE_SHIFT (0U) #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) @@ -7130,8 +7521,10 @@ typedef struct { #define DMA_ES_VLD_MASK (0x80000000U) #define DMA_ES_VLD_SHIFT (31U) #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) +/*! @} */ /*! @name ERQ - Enable Request Register */ +/*! @{ */ #define DMA_ERQ_ERQ0_MASK (0x1U) #define DMA_ERQ_ERQ0_SHIFT (0U) #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) @@ -7228,8 +7621,10 @@ typedef struct { #define DMA_ERQ_ERQ31_MASK (0x80000000U) #define DMA_ERQ_ERQ31_SHIFT (31U) #define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK) +/*! @} */ /*! @name EEI - Enable Error Interrupt Register */ +/*! @{ */ #define DMA_EEI_EEI0_MASK (0x1U) #define DMA_EEI_EEI0_SHIFT (0U) #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) @@ -7326,8 +7721,10 @@ typedef struct { #define DMA_EEI_EEI31_MASK (0x80000000U) #define DMA_EEI_EEI31_SHIFT (31U) #define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK) +/*! @} */ /*! @name CEEI - Clear Enable Error Interrupt Register */ +/*! @{ */ #define DMA_CEEI_CEEI_MASK (0x1FU) #define DMA_CEEI_CEEI_SHIFT (0U) #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) @@ -7337,8 +7734,10 @@ typedef struct { #define DMA_CEEI_NOP_MASK (0x80U) #define DMA_CEEI_NOP_SHIFT (7U) #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) +/*! @} */ /*! @name SEEI - Set Enable Error Interrupt Register */ +/*! @{ */ #define DMA_SEEI_SEEI_MASK (0x1FU) #define DMA_SEEI_SEEI_SHIFT (0U) #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) @@ -7348,8 +7747,10 @@ typedef struct { #define DMA_SEEI_NOP_MASK (0x80U) #define DMA_SEEI_NOP_SHIFT (7U) #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) +/*! @} */ /*! @name CERQ - Clear Enable Request Register */ +/*! @{ */ #define DMA_CERQ_CERQ_MASK (0x1FU) #define DMA_CERQ_CERQ_SHIFT (0U) #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) @@ -7359,8 +7760,10 @@ typedef struct { #define DMA_CERQ_NOP_MASK (0x80U) #define DMA_CERQ_NOP_SHIFT (7U) #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) +/*! @} */ /*! @name SERQ - Set Enable Request Register */ +/*! @{ */ #define DMA_SERQ_SERQ_MASK (0x1FU) #define DMA_SERQ_SERQ_SHIFT (0U) #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) @@ -7370,8 +7773,10 @@ typedef struct { #define DMA_SERQ_NOP_MASK (0x80U) #define DMA_SERQ_NOP_SHIFT (7U) #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) +/*! @} */ /*! @name CDNE - Clear DONE Status Bit Register */ +/*! @{ */ #define DMA_CDNE_CDNE_MASK (0x1FU) #define DMA_CDNE_CDNE_SHIFT (0U) #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) @@ -7381,8 +7786,10 @@ typedef struct { #define DMA_CDNE_NOP_MASK (0x80U) #define DMA_CDNE_NOP_SHIFT (7U) #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) +/*! @} */ /*! @name SSRT - Set START Bit Register */ +/*! @{ */ #define DMA_SSRT_SSRT_MASK (0x1FU) #define DMA_SSRT_SSRT_SHIFT (0U) #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) @@ -7392,8 +7799,10 @@ typedef struct { #define DMA_SSRT_NOP_MASK (0x80U) #define DMA_SSRT_NOP_SHIFT (7U) #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) +/*! @} */ /*! @name CERR - Clear Error Register */ +/*! @{ */ #define DMA_CERR_CERR_MASK (0x1FU) #define DMA_CERR_CERR_SHIFT (0U) #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) @@ -7403,8 +7812,10 @@ typedef struct { #define DMA_CERR_NOP_MASK (0x80U) #define DMA_CERR_NOP_SHIFT (7U) #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) +/*! @} */ /*! @name CINT - Clear Interrupt Request Register */ +/*! @{ */ #define DMA_CINT_CINT_MASK (0x1FU) #define DMA_CINT_CINT_SHIFT (0U) #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) @@ -7414,8 +7825,10 @@ typedef struct { #define DMA_CINT_NOP_MASK (0x80U) #define DMA_CINT_NOP_SHIFT (7U) #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) +/*! @} */ /*! @name INT - Interrupt Request Register */ +/*! @{ */ #define DMA_INT_INT0_MASK (0x1U) #define DMA_INT_INT0_SHIFT (0U) #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) @@ -7512,8 +7925,10 @@ typedef struct { #define DMA_INT_INT31_MASK (0x80000000U) #define DMA_INT_INT31_SHIFT (31U) #define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK) +/*! @} */ /*! @name ERR - Error Register */ +/*! @{ */ #define DMA_ERR_ERR0_MASK (0x1U) #define DMA_ERR_ERR0_SHIFT (0U) #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) @@ -7610,8 +8025,10 @@ typedef struct { #define DMA_ERR_ERR31_MASK (0x80000000U) #define DMA_ERR_ERR31_SHIFT (31U) #define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK) +/*! @} */ /*! @name HRS - Hardware Request Status Register */ +/*! @{ */ #define DMA_HRS_HRS0_MASK (0x1U) #define DMA_HRS_HRS0_SHIFT (0U) #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) @@ -7708,8 +8125,10 @@ typedef struct { #define DMA_HRS_HRS31_MASK (0x80000000U) #define DMA_HRS_HRS31_SHIFT (31U) #define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK) +/*! @} */ /*! @name EARS - Enable Asynchronous Request in Stop Register */ +/*! @{ */ #define DMA_EARS_EDREQ_0_MASK (0x1U) #define DMA_EARS_EDREQ_0_SHIFT (0U) #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) @@ -7806,8 +8225,10 @@ typedef struct { #define DMA_EARS_EDREQ_31_MASK (0x80000000U) #define DMA_EARS_EDREQ_31_SHIFT (31U) #define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK) +/*! @} */ /*! @name DCHPRI3 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI3_CHPRI_MASK (0xFU) #define DMA_DCHPRI3_CHPRI_SHIFT (0U) #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) @@ -7820,8 +8241,10 @@ typedef struct { #define DMA_DCHPRI3_ECP_MASK (0x80U) #define DMA_DCHPRI3_ECP_SHIFT (7U) #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) +/*! @} */ /*! @name DCHPRI2 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI2_CHPRI_MASK (0xFU) #define DMA_DCHPRI2_CHPRI_SHIFT (0U) #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) @@ -7834,8 +8257,10 @@ typedef struct { #define DMA_DCHPRI2_ECP_MASK (0x80U) #define DMA_DCHPRI2_ECP_SHIFT (7U) #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) +/*! @} */ /*! @name DCHPRI1 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI1_CHPRI_MASK (0xFU) #define DMA_DCHPRI1_CHPRI_SHIFT (0U) #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) @@ -7848,8 +8273,10 @@ typedef struct { #define DMA_DCHPRI1_ECP_MASK (0x80U) #define DMA_DCHPRI1_ECP_SHIFT (7U) #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) +/*! @} */ /*! @name DCHPRI0 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI0_CHPRI_MASK (0xFU) #define DMA_DCHPRI0_CHPRI_SHIFT (0U) #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) @@ -7862,8 +8289,10 @@ typedef struct { #define DMA_DCHPRI0_ECP_MASK (0x80U) #define DMA_DCHPRI0_ECP_SHIFT (7U) #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) +/*! @} */ /*! @name DCHPRI7 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI7_CHPRI_MASK (0xFU) #define DMA_DCHPRI7_CHPRI_SHIFT (0U) #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) @@ -7876,8 +8305,10 @@ typedef struct { #define DMA_DCHPRI7_ECP_MASK (0x80U) #define DMA_DCHPRI7_ECP_SHIFT (7U) #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) +/*! @} */ /*! @name DCHPRI6 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI6_CHPRI_MASK (0xFU) #define DMA_DCHPRI6_CHPRI_SHIFT (0U) #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) @@ -7890,8 +8321,10 @@ typedef struct { #define DMA_DCHPRI6_ECP_MASK (0x80U) #define DMA_DCHPRI6_ECP_SHIFT (7U) #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) +/*! @} */ /*! @name DCHPRI5 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI5_CHPRI_MASK (0xFU) #define DMA_DCHPRI5_CHPRI_SHIFT (0U) #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) @@ -7904,8 +8337,10 @@ typedef struct { #define DMA_DCHPRI5_ECP_MASK (0x80U) #define DMA_DCHPRI5_ECP_SHIFT (7U) #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) +/*! @} */ /*! @name DCHPRI4 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI4_CHPRI_MASK (0xFU) #define DMA_DCHPRI4_CHPRI_SHIFT (0U) #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) @@ -7918,8 +8353,10 @@ typedef struct { #define DMA_DCHPRI4_ECP_MASK (0x80U) #define DMA_DCHPRI4_ECP_SHIFT (7U) #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) +/*! @} */ /*! @name DCHPRI11 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI11_CHPRI_MASK (0xFU) #define DMA_DCHPRI11_CHPRI_SHIFT (0U) #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) @@ -7932,8 +8369,10 @@ typedef struct { #define DMA_DCHPRI11_ECP_MASK (0x80U) #define DMA_DCHPRI11_ECP_SHIFT (7U) #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) +/*! @} */ /*! @name DCHPRI10 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI10_CHPRI_MASK (0xFU) #define DMA_DCHPRI10_CHPRI_SHIFT (0U) #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) @@ -7946,8 +8385,10 @@ typedef struct { #define DMA_DCHPRI10_ECP_MASK (0x80U) #define DMA_DCHPRI10_ECP_SHIFT (7U) #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) +/*! @} */ /*! @name DCHPRI9 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI9_CHPRI_MASK (0xFU) #define DMA_DCHPRI9_CHPRI_SHIFT (0U) #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) @@ -7960,8 +8401,10 @@ typedef struct { #define DMA_DCHPRI9_ECP_MASK (0x80U) #define DMA_DCHPRI9_ECP_SHIFT (7U) #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) +/*! @} */ /*! @name DCHPRI8 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI8_CHPRI_MASK (0xFU) #define DMA_DCHPRI8_CHPRI_SHIFT (0U) #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) @@ -7974,8 +8417,10 @@ typedef struct { #define DMA_DCHPRI8_ECP_MASK (0x80U) #define DMA_DCHPRI8_ECP_SHIFT (7U) #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) +/*! @} */ /*! @name DCHPRI15 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI15_CHPRI_MASK (0xFU) #define DMA_DCHPRI15_CHPRI_SHIFT (0U) #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) @@ -7988,8 +8433,10 @@ typedef struct { #define DMA_DCHPRI15_ECP_MASK (0x80U) #define DMA_DCHPRI15_ECP_SHIFT (7U) #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) +/*! @} */ /*! @name DCHPRI14 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI14_CHPRI_MASK (0xFU) #define DMA_DCHPRI14_CHPRI_SHIFT (0U) #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) @@ -8002,8 +8449,10 @@ typedef struct { #define DMA_DCHPRI14_ECP_MASK (0x80U) #define DMA_DCHPRI14_ECP_SHIFT (7U) #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) +/*! @} */ /*! @name DCHPRI13 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI13_CHPRI_MASK (0xFU) #define DMA_DCHPRI13_CHPRI_SHIFT (0U) #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) @@ -8016,8 +8465,10 @@ typedef struct { #define DMA_DCHPRI13_ECP_MASK (0x80U) #define DMA_DCHPRI13_ECP_SHIFT (7U) #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) +/*! @} */ /*! @name DCHPRI12 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI12_CHPRI_MASK (0xFU) #define DMA_DCHPRI12_CHPRI_SHIFT (0U) #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) @@ -8030,8 +8481,10 @@ typedef struct { #define DMA_DCHPRI12_ECP_MASK (0x80U) #define DMA_DCHPRI12_ECP_SHIFT (7U) #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) +/*! @} */ /*! @name DCHPRI19 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI19_CHPRI_MASK (0xFU) #define DMA_DCHPRI19_CHPRI_SHIFT (0U) #define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK) @@ -8044,8 +8497,10 @@ typedef struct { #define DMA_DCHPRI19_ECP_MASK (0x80U) #define DMA_DCHPRI19_ECP_SHIFT (7U) #define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK) +/*! @} */ /*! @name DCHPRI18 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI18_CHPRI_MASK (0xFU) #define DMA_DCHPRI18_CHPRI_SHIFT (0U) #define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK) @@ -8058,8 +8513,10 @@ typedef struct { #define DMA_DCHPRI18_ECP_MASK (0x80U) #define DMA_DCHPRI18_ECP_SHIFT (7U) #define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK) +/*! @} */ /*! @name DCHPRI17 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI17_CHPRI_MASK (0xFU) #define DMA_DCHPRI17_CHPRI_SHIFT (0U) #define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK) @@ -8072,8 +8529,10 @@ typedef struct { #define DMA_DCHPRI17_ECP_MASK (0x80U) #define DMA_DCHPRI17_ECP_SHIFT (7U) #define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK) +/*! @} */ /*! @name DCHPRI16 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI16_CHPRI_MASK (0xFU) #define DMA_DCHPRI16_CHPRI_SHIFT (0U) #define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK) @@ -8086,8 +8545,10 @@ typedef struct { #define DMA_DCHPRI16_ECP_MASK (0x80U) #define DMA_DCHPRI16_ECP_SHIFT (7U) #define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK) +/*! @} */ /*! @name DCHPRI23 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI23_CHPRI_MASK (0xFU) #define DMA_DCHPRI23_CHPRI_SHIFT (0U) #define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK) @@ -8100,8 +8561,10 @@ typedef struct { #define DMA_DCHPRI23_ECP_MASK (0x80U) #define DMA_DCHPRI23_ECP_SHIFT (7U) #define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK) +/*! @} */ /*! @name DCHPRI22 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI22_CHPRI_MASK (0xFU) #define DMA_DCHPRI22_CHPRI_SHIFT (0U) #define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK) @@ -8114,8 +8577,10 @@ typedef struct { #define DMA_DCHPRI22_ECP_MASK (0x80U) #define DMA_DCHPRI22_ECP_SHIFT (7U) #define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK) +/*! @} */ /*! @name DCHPRI21 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI21_CHPRI_MASK (0xFU) #define DMA_DCHPRI21_CHPRI_SHIFT (0U) #define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK) @@ -8128,8 +8593,10 @@ typedef struct { #define DMA_DCHPRI21_ECP_MASK (0x80U) #define DMA_DCHPRI21_ECP_SHIFT (7U) #define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK) +/*! @} */ /*! @name DCHPRI20 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI20_CHPRI_MASK (0xFU) #define DMA_DCHPRI20_CHPRI_SHIFT (0U) #define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK) @@ -8142,8 +8609,10 @@ typedef struct { #define DMA_DCHPRI20_ECP_MASK (0x80U) #define DMA_DCHPRI20_ECP_SHIFT (7U) #define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK) +/*! @} */ /*! @name DCHPRI27 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI27_CHPRI_MASK (0xFU) #define DMA_DCHPRI27_CHPRI_SHIFT (0U) #define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK) @@ -8156,8 +8625,10 @@ typedef struct { #define DMA_DCHPRI27_ECP_MASK (0x80U) #define DMA_DCHPRI27_ECP_SHIFT (7U) #define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK) +/*! @} */ /*! @name DCHPRI26 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI26_CHPRI_MASK (0xFU) #define DMA_DCHPRI26_CHPRI_SHIFT (0U) #define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK) @@ -8170,8 +8641,10 @@ typedef struct { #define DMA_DCHPRI26_ECP_MASK (0x80U) #define DMA_DCHPRI26_ECP_SHIFT (7U) #define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK) +/*! @} */ /*! @name DCHPRI25 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI25_CHPRI_MASK (0xFU) #define DMA_DCHPRI25_CHPRI_SHIFT (0U) #define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK) @@ -8184,8 +8657,10 @@ typedef struct { #define DMA_DCHPRI25_ECP_MASK (0x80U) #define DMA_DCHPRI25_ECP_SHIFT (7U) #define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK) +/*! @} */ /*! @name DCHPRI24 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI24_CHPRI_MASK (0xFU) #define DMA_DCHPRI24_CHPRI_SHIFT (0U) #define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK) @@ -8198,8 +8673,10 @@ typedef struct { #define DMA_DCHPRI24_ECP_MASK (0x80U) #define DMA_DCHPRI24_ECP_SHIFT (7U) #define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK) +/*! @} */ /*! @name DCHPRI31 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI31_CHPRI_MASK (0xFU) #define DMA_DCHPRI31_CHPRI_SHIFT (0U) #define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK) @@ -8212,8 +8689,10 @@ typedef struct { #define DMA_DCHPRI31_ECP_MASK (0x80U) #define DMA_DCHPRI31_ECP_SHIFT (7U) #define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK) +/*! @} */ /*! @name DCHPRI30 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI30_CHPRI_MASK (0xFU) #define DMA_DCHPRI30_CHPRI_SHIFT (0U) #define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK) @@ -8226,8 +8705,10 @@ typedef struct { #define DMA_DCHPRI30_ECP_MASK (0x80U) #define DMA_DCHPRI30_ECP_SHIFT (7U) #define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK) +/*! @} */ /*! @name DCHPRI29 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI29_CHPRI_MASK (0xFU) #define DMA_DCHPRI29_CHPRI_SHIFT (0U) #define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK) @@ -8240,8 +8721,10 @@ typedef struct { #define DMA_DCHPRI29_ECP_MASK (0x80U) #define DMA_DCHPRI29_ECP_SHIFT (7U) #define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK) +/*! @} */ /*! @name DCHPRI28 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI28_CHPRI_MASK (0xFU) #define DMA_DCHPRI28_CHPRI_SHIFT (0U) #define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK) @@ -8254,24 +8737,30 @@ typedef struct { #define DMA_DCHPRI28_ECP_MASK (0x80U) #define DMA_DCHPRI28_ECP_SHIFT (7U) #define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK) +/*! @} */ /*! @name SADDR - TCD Source Address */ +/*! @{ */ #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) #define DMA_SADDR_SADDR_SHIFT (0U) #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) +/*! @} */ /* The count of DMA_SADDR */ #define DMA_SADDR_COUNT (32U) /*! @name SOFF - TCD Signed Source Address Offset */ +/*! @{ */ #define DMA_SOFF_SOFF_MASK (0xFFFFU) #define DMA_SOFF_SOFF_SHIFT (0U) #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) +/*! @} */ /* The count of DMA_SOFF */ #define DMA_SOFF_COUNT (32U) /*! @name ATTR - TCD Transfer Attributes */ +/*! @{ */ #define DMA_ATTR_DSIZE_MASK (0x7U) #define DMA_ATTR_DSIZE_SHIFT (0U) #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) @@ -8284,19 +8773,23 @@ typedef struct { #define DMA_ATTR_SMOD_MASK (0xF800U) #define DMA_ATTR_SMOD_SHIFT (11U) #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) +/*! @} */ /* The count of DMA_ATTR */ #define DMA_ATTR_COUNT (32U) /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ +/*! @{ */ #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) +/*! @} */ /* The count of DMA_NBYTES_MLNO */ #define DMA_NBYTES_MLNO_COUNT (32U) /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ +/*! @{ */ #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) @@ -8306,11 +8799,13 @@ typedef struct { #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ /* The count of DMA_NBYTES_MLOFFNO */ #define DMA_NBYTES_MLOFFNO_COUNT (32U) /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ +/*! @{ */ #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) @@ -8323,46 +8818,56 @@ typedef struct { #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ /* The count of DMA_NBYTES_MLOFFYES */ #define DMA_NBYTES_MLOFFYES_COUNT (32U) /*! @name SLAST - TCD Last Source Address Adjustment */ +/*! @{ */ #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) #define DMA_SLAST_SLAST_SHIFT (0U) #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) +/*! @} */ /* The count of DMA_SLAST */ #define DMA_SLAST_COUNT (32U) /*! @name DADDR - TCD Destination Address */ +/*! @{ */ #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) #define DMA_DADDR_DADDR_SHIFT (0U) #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) +/*! @} */ /* The count of DMA_DADDR */ #define DMA_DADDR_COUNT (32U) /*! @name DOFF - TCD Signed Destination Address Offset */ +/*! @{ */ #define DMA_DOFF_DOFF_MASK (0xFFFFU) #define DMA_DOFF_DOFF_SHIFT (0U) #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) +/*! @} */ /* The count of DMA_DOFF */ #define DMA_DOFF_COUNT (32U) /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) #define DMA_CITER_ELINKNO_CITER_SHIFT (0U) #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) +/*! @} */ /* The count of DMA_CITER_ELINKNO */ #define DMA_CITER_ELINKNO_COUNT (32U) /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) #define DMA_CITER_ELINKYES_CITER_SHIFT (0U) #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) @@ -8372,19 +8877,23 @@ typedef struct { #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) +/*! @} */ /* The count of DMA_CITER_ELINKYES */ #define DMA_CITER_ELINKYES_COUNT (32U) /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ +/*! @{ */ #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) +/*! @} */ /* The count of DMA_DLAST_SGA */ #define DMA_DLAST_SGA_COUNT (32U) /*! @name CSR - TCD Control and Status */ +/*! @{ */ #define DMA_CSR_START_MASK (0x1U) #define DMA_CSR_START_SHIFT (0U) #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) @@ -8415,22 +8924,26 @@ typedef struct { #define DMA_CSR_BWC_MASK (0xC000U) #define DMA_CSR_BWC_SHIFT (14U) #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) +/*! @} */ /* The count of DMA_CSR */ #define DMA_CSR_COUNT (32U) /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) #define DMA_BITER_ELINKNO_BITER_SHIFT (0U) #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) +/*! @} */ /* The count of DMA_BITER_ELINKNO */ #define DMA_BITER_ELINKNO_COUNT (32U) /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) #define DMA_BITER_ELINKYES_BITER_SHIFT (0U) #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) @@ -8440,6 +8953,7 @@ typedef struct { #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) +/*! @} */ /* The count of DMA_BITER_ELINKYES */ #define DMA_BITER_ELINKYES_COUNT (32U) @@ -8479,11 +8993,7 @@ typedef struct { /** DMAMUX - Register Layout Typedef */ typedef struct { - __IO uint32_t CHCFG[32]; /**< - Channel 0 Configuration Register - .. - Channel 31 Configuration Register - , array offset: 0x0, array step: 0x4 */ + __IO uint32_t CHCFG[32]; /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */ } DMAMUX_Type; /* ---------------------------------------------------------------------------- @@ -8495,11 +9005,8 @@ typedef struct { * @{ */ -/*! @name CHCFG - - Channel 0 Configuration Register - .. - Channel 31 Configuration Register - */ +/*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */ +/*! @{ */ #define DMAMUX_CHCFG_SOURCE_MASK (0x7FU) #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) #define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) @@ -8512,6 +9019,7 @@ typedef struct { #define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) #define DMAMUX_CHCFG_ENBL_SHIFT (31U) #define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) +/*! @} */ /* The count of DMAMUX_CHCFG */ #define DMAMUX_CHCFG_COUNT (32U) @@ -8580,6 +9088,7 @@ typedef struct { */ /*! @name CTRL - Control Register */ +/*! @{ */ #define ENC_CTRL_CMPIE_MASK (0x1U) #define ENC_CTRL_CMPIE_SHIFT (0U) #define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK) @@ -8628,71 +9137,97 @@ typedef struct { #define ENC_CTRL_HIRQ_MASK (0x8000U) #define ENC_CTRL_HIRQ_SHIFT (15U) #define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK) +/*! @} */ /*! @name FILT - Input Filter Register */ +/*! @{ */ #define ENC_FILT_FILT_PER_MASK (0xFFU) #define ENC_FILT_FILT_PER_SHIFT (0U) #define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK) #define ENC_FILT_FILT_CNT_MASK (0x700U) #define ENC_FILT_FILT_CNT_SHIFT (8U) #define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK) +/*! @} */ /*! @name WTR - Watchdog Timeout Register */ +/*! @{ */ #define ENC_WTR_WDOG_MASK (0xFFFFU) #define ENC_WTR_WDOG_SHIFT (0U) #define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK) +/*! @} */ /*! @name POSD - Position Difference Counter Register */ +/*! @{ */ #define ENC_POSD_POSD_MASK (0xFFFFU) #define ENC_POSD_POSD_SHIFT (0U) #define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK) +/*! @} */ /*! @name POSDH - Position Difference Hold Register */ +/*! @{ */ #define ENC_POSDH_POSDH_MASK (0xFFFFU) #define ENC_POSDH_POSDH_SHIFT (0U) #define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK) +/*! @} */ /*! @name REV - Revolution Counter Register */ +/*! @{ */ #define ENC_REV_REV_MASK (0xFFFFU) #define ENC_REV_REV_SHIFT (0U) #define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK) +/*! @} */ /*! @name REVH - Revolution Hold Register */ +/*! @{ */ #define ENC_REVH_REVH_MASK (0xFFFFU) #define ENC_REVH_REVH_SHIFT (0U) #define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK) +/*! @} */ /*! @name UPOS - Upper Position Counter Register */ +/*! @{ */ #define ENC_UPOS_POS_MASK (0xFFFFU) #define ENC_UPOS_POS_SHIFT (0U) #define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK) +/*! @} */ /*! @name LPOS - Lower Position Counter Register */ +/*! @{ */ #define ENC_LPOS_POS_MASK (0xFFFFU) #define ENC_LPOS_POS_SHIFT (0U) #define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK) +/*! @} */ /*! @name UPOSH - Upper Position Hold Register */ +/*! @{ */ #define ENC_UPOSH_POSH_MASK (0xFFFFU) #define ENC_UPOSH_POSH_SHIFT (0U) #define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK) +/*! @} */ /*! @name LPOSH - Lower Position Hold Register */ +/*! @{ */ #define ENC_LPOSH_POSH_MASK (0xFFFFU) #define ENC_LPOSH_POSH_SHIFT (0U) #define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK) +/*! @} */ /*! @name UINIT - Upper Initialization Register */ +/*! @{ */ #define ENC_UINIT_INIT_MASK (0xFFFFU) #define ENC_UINIT_INIT_SHIFT (0U) #define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK) +/*! @} */ /*! @name LINIT - Lower Initialization Register */ +/*! @{ */ #define ENC_LINIT_INIT_MASK (0xFFFFU) #define ENC_LINIT_INIT_SHIFT (0U) #define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK) +/*! @} */ /*! @name IMR - Input Monitor Register */ +/*! @{ */ #define ENC_IMR_HOME_MASK (0x1U) #define ENC_IMR_HOME_SHIFT (0U) #define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK) @@ -8717,8 +9252,10 @@ typedef struct { #define ENC_IMR_FPHA_MASK (0x80U) #define ENC_IMR_FPHA_SHIFT (7U) #define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK) +/*! @} */ /*! @name TST - Test Register */ +/*! @{ */ #define ENC_TST_TEST_COUNT_MASK (0xFFU) #define ENC_TST_TEST_COUNT_SHIFT (0U) #define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK) @@ -8734,8 +9271,10 @@ typedef struct { #define ENC_TST_TEN_MASK (0x8000U) #define ENC_TST_TEN_SHIFT (15U) #define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK) +/*! @} */ /*! @name CTRL2 - Control 2 Register */ +/*! @{ */ #define ENC_CTRL2_UPDHLD_MASK (0x1U) #define ENC_CTRL2_UPDHLD_SHIFT (0U) #define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK) @@ -8772,26 +9311,35 @@ typedef struct { #define ENC_CTRL2_SABIRQ_MASK (0x800U) #define ENC_CTRL2_SABIRQ_SHIFT (11U) #define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK) +/*! @} */ /*! @name UMOD - Upper Modulus Register */ +/*! @{ */ #define ENC_UMOD_MOD_MASK (0xFFFFU) #define ENC_UMOD_MOD_SHIFT (0U) #define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK) +/*! @} */ /*! @name LMOD - Lower Modulus Register */ +/*! @{ */ #define ENC_LMOD_MOD_MASK (0xFFFFU) #define ENC_LMOD_MOD_SHIFT (0U) #define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK) +/*! @} */ /*! @name UCOMP - Upper Position Compare Register */ +/*! @{ */ #define ENC_UCOMP_COMP_MASK (0xFFFFU) #define ENC_UCOMP_COMP_SHIFT (0U) #define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK) +/*! @} */ /*! @name LCOMP - Lower Position Compare Register */ +/*! @{ */ #define ENC_LCOMP_COMP_MASK (0xFFFFU) #define ENC_LCOMP_COMP_SHIFT (0U) #define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK) +/*! @} */ /*! @@ -8973,6 +9521,7 @@ typedef struct { */ /*! @name EIR - Interrupt Event Register */ +/*! @{ */ #define ENET_EIR_TS_TIMER_MASK (0x8000U) #define ENET_EIR_TS_TIMER_SHIFT (15U) #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) @@ -9021,8 +9570,10 @@ typedef struct { #define ENET_EIR_BABR_MASK (0x40000000U) #define ENET_EIR_BABR_SHIFT (30U) #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) +/*! @} */ /*! @name EIMR - Interrupt Mask Register */ +/*! @{ */ #define ENET_EIMR_TS_TIMER_MASK (0x8000U) #define ENET_EIMR_TS_TIMER_SHIFT (15U) #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) @@ -9071,18 +9622,24 @@ typedef struct { #define ENET_EIMR_BABR_MASK (0x40000000U) #define ENET_EIMR_BABR_SHIFT (30U) #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) +/*! @} */ /*! @name RDAR - Receive Descriptor Active Register */ +/*! @{ */ #define ENET_RDAR_RDAR_MASK (0x1000000U) #define ENET_RDAR_RDAR_SHIFT (24U) #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) +/*! @} */ /*! @name TDAR - Transmit Descriptor Active Register */ +/*! @{ */ #define ENET_TDAR_TDAR_MASK (0x1000000U) #define ENET_TDAR_TDAR_SHIFT (24U) #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) +/*! @} */ /*! @name ECR - Ethernet Control Register */ +/*! @{ */ #define ENET_ECR_RESET_MASK (0x1U) #define ENET_ECR_RESET_SHIFT (0U) #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) @@ -9104,8 +9661,10 @@ typedef struct { #define ENET_ECR_DBSWP_MASK (0x100U) #define ENET_ECR_DBSWP_SHIFT (8U) #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) +/*! @} */ /*! @name MMFR - MII Management Frame Register */ +/*! @{ */ #define ENET_MMFR_DATA_MASK (0xFFFFU) #define ENET_MMFR_DATA_SHIFT (0U) #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) @@ -9124,8 +9683,10 @@ typedef struct { #define ENET_MMFR_ST_MASK (0xC0000000U) #define ENET_MMFR_ST_SHIFT (30U) #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) +/*! @} */ /*! @name MSCR - MII Speed Control Register */ +/*! @{ */ #define ENET_MSCR_MII_SPEED_MASK (0x7EU) #define ENET_MSCR_MII_SPEED_SHIFT (1U) #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) @@ -9135,8 +9696,10 @@ typedef struct { #define ENET_MSCR_HOLDTIME_MASK (0x700U) #define ENET_MSCR_HOLDTIME_SHIFT (8U) #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) +/*! @} */ /*! @name MIBC - MIB Control Register */ +/*! @{ */ #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) #define ENET_MIBC_MIB_CLEAR_SHIFT (29U) #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) @@ -9146,8 +9709,10 @@ typedef struct { #define ENET_MIBC_MIB_DIS_MASK (0x80000000U) #define ENET_MIBC_MIB_DIS_SHIFT (31U) #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) +/*! @} */ /*! @name RCR - Receive Control Register */ +/*! @{ */ #define ENET_RCR_LOOP_MASK (0x1U) #define ENET_RCR_LOOP_SHIFT (0U) #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) @@ -9193,8 +9758,10 @@ typedef struct { #define ENET_RCR_GRS_MASK (0x80000000U) #define ENET_RCR_GRS_SHIFT (31U) #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) +/*! @} */ /*! @name TCR - Transmit Control Register */ +/*! @{ */ #define ENET_TCR_GTS_MASK (0x1U) #define ENET_TCR_GTS_SHIFT (0U) #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) @@ -9216,29 +9783,37 @@ typedef struct { #define ENET_TCR_CRCFWD_MASK (0x200U) #define ENET_TCR_CRCFWD_SHIFT (9U) #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) +/*! @} */ /*! @name PALR - Physical Address Lower Register */ +/*! @{ */ #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) #define ENET_PALR_PADDR1_SHIFT (0U) #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) +/*! @} */ /*! @name PAUR - Physical Address Upper Register */ +/*! @{ */ #define ENET_PAUR_TYPE_MASK (0xFFFFU) #define ENET_PAUR_TYPE_SHIFT (0U) #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) #define ENET_PAUR_PADDR2_SHIFT (16U) #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) +/*! @} */ /*! @name OPD - Opcode/Pause Duration Register */ +/*! @{ */ #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) #define ENET_OPD_PAUSE_DUR_SHIFT (0U) #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) #define ENET_OPD_OPCODE_MASK (0xFFFF0000U) #define ENET_OPD_OPCODE_SHIFT (16U) #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) +/*! @} */ /*! @name TXIC - Transmit Interrupt Coalescing Register */ +/*! @{ */ #define ENET_TXIC_ICTT_MASK (0xFFFFU) #define ENET_TXIC_ICTT_SHIFT (0U) #define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) @@ -9251,8 +9826,10 @@ typedef struct { #define ENET_TXIC_ICEN_MASK (0x80000000U) #define ENET_TXIC_ICEN_SHIFT (31U) #define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) +/*! @} */ /*! @name RXIC - Receive Interrupt Coalescing Register */ +/*! @{ */ #define ENET_RXIC_ICTT_MASK (0xFFFFU) #define ENET_RXIC_ICTT_SHIFT (0U) #define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) @@ -9265,99 +9842,135 @@ typedef struct { #define ENET_RXIC_ICEN_MASK (0x80000000U) #define ENET_RXIC_ICEN_SHIFT (31U) #define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) +/*! @} */ /*! @name IAUR - Descriptor Individual Upper Address Register */ +/*! @{ */ #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) #define ENET_IAUR_IADDR1_SHIFT (0U) #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) +/*! @} */ /*! @name IALR - Descriptor Individual Lower Address Register */ +/*! @{ */ #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) #define ENET_IALR_IADDR2_SHIFT (0U) #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) +/*! @} */ /*! @name GAUR - Descriptor Group Upper Address Register */ +/*! @{ */ #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) #define ENET_GAUR_GADDR1_SHIFT (0U) #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) +/*! @} */ /*! @name GALR - Descriptor Group Lower Address Register */ +/*! @{ */ #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) #define ENET_GALR_GADDR2_SHIFT (0U) #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) +/*! @} */ /*! @name TFWR - Transmit FIFO Watermark Register */ +/*! @{ */ #define ENET_TFWR_TFWR_MASK (0x3FU) #define ENET_TFWR_TFWR_SHIFT (0U) #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) #define ENET_TFWR_STRFWD_MASK (0x100U) #define ENET_TFWR_STRFWD_SHIFT (8U) #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) +/*! @} */ /*! @name RDSR - Receive Descriptor Ring Start Register */ +/*! @{ */ #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) #define ENET_RDSR_R_DES_START_SHIFT (3U) #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) +/*! @} */ /*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */ +/*! @{ */ #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) #define ENET_TDSR_X_DES_START_SHIFT (3U) #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) +/*! @} */ /*! @name MRBR - Maximum Receive Buffer Size Register */ +/*! @{ */ #define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) +/*! @} */ /*! @name RSFL - Receive FIFO Section Full Threshold */ +/*! @{ */ #define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU) #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) +/*! @} */ /*! @name RSEM - Receive FIFO Section Empty Threshold */ +/*! @{ */ #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU) #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) +/*! @} */ /*! @name RAEM - Receive FIFO Almost Empty Threshold */ +/*! @{ */ #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU) #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) +/*! @} */ /*! @name RAFL - Receive FIFO Almost Full Threshold */ +/*! @{ */ #define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU) #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) +/*! @} */ /*! @name TSEM - Transmit FIFO Section Empty Threshold */ +/*! @{ */ #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU) #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) +/*! @} */ /*! @name TAEM - Transmit FIFO Almost Empty Threshold */ +/*! @{ */ #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU) #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) +/*! @} */ /*! @name TAFL - Transmit FIFO Almost Full Threshold */ +/*! @{ */ #define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU) #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) +/*! @} */ /*! @name TIPG - Transmit Inter-Packet Gap */ +/*! @{ */ #define ENET_TIPG_IPG_MASK (0x1FU) #define ENET_TIPG_IPG_SHIFT (0U) #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) +/*! @} */ /*! @name FTRL - Frame Truncation Length */ +/*! @{ */ #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) #define ENET_FTRL_TRUNC_FL_SHIFT (0U) #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) +/*! @} */ /*! @name TACC - Transmit Accelerator Function Configuration */ +/*! @{ */ #define ENET_TACC_SHIFT16_MASK (0x1U) #define ENET_TACC_SHIFT16_SHIFT (0U) #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) @@ -9367,8 +9980,10 @@ typedef struct { #define ENET_TACC_PROCHK_MASK (0x10U) #define ENET_TACC_PROCHK_SHIFT (4U) #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) +/*! @} */ /*! @name RACC - Receive Accelerator Function Configuration */ +/*! @{ */ #define ENET_RACC_PADREM_MASK (0x1U) #define ENET_RACC_PADREM_SHIFT (0U) #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) @@ -9384,263 +9999,367 @@ typedef struct { #define ENET_RACC_SHIFT16_MASK (0x80U) #define ENET_RACC_SHIFT16_SHIFT (7U) #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) +/*! @} */ /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ +/*! @{ */ #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_COL - Tx Collision Count Statistic Register */ +/*! @{ */ #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) +/*! @} */ /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_SQE - Reserved Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) #define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) +/*! @} */ /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ +/*! @{ */ #define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) +/*! @} */ /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) +/*! @} */ /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) +/*! @} */ /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) +/*! @} */ /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) +/*! @} */ /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) +/*! @} */ /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) +/*! @} */ /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_JAB_COUNT_SHIFT (0U) #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P64_COUNT_SHIFT (0U) #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) +/*! @} */ /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) #define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) +/*! @} */ /*! @name ATCR - Adjustable Timer Control Register */ +/*! @{ */ #define ENET_ATCR_EN_MASK (0x1U) #define ENET_ATCR_EN_SHIFT (0U) #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) @@ -9665,41 +10384,55 @@ typedef struct { #define ENET_ATCR_SLAVE_MASK (0x2000U) #define ENET_ATCR_SLAVE_SHIFT (13U) #define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) +/*! @} */ /*! @name ATVR - Timer Value Register */ +/*! @{ */ #define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) #define ENET_ATVR_ATIME_SHIFT (0U) #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) +/*! @} */ /*! @name ATOFF - Timer Offset Register */ +/*! @{ */ #define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) #define ENET_ATOFF_OFFSET_SHIFT (0U) #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) +/*! @} */ /*! @name ATPER - Timer Period Register */ +/*! @{ */ #define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) #define ENET_ATPER_PERIOD_SHIFT (0U) #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) +/*! @} */ /*! @name ATCOR - Timer Correction Register */ +/*! @{ */ #define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) #define ENET_ATCOR_COR_SHIFT (0U) #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) +/*! @} */ /*! @name ATINC - Time-Stamping Clock Period Register */ +/*! @{ */ #define ENET_ATINC_INC_MASK (0x7FU) #define ENET_ATINC_INC_SHIFT (0U) #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) #define ENET_ATINC_INC_CORR_MASK (0x7F00U) #define ENET_ATINC_INC_CORR_SHIFT (8U) #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) +/*! @} */ /*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +/*! @{ */ #define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) #define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) +/*! @} */ /*! @name TGSR - Timer Global Status Register */ +/*! @{ */ #define ENET_TGSR_TF0_MASK (0x1U) #define ENET_TGSR_TF0_SHIFT (0U) #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) @@ -9712,8 +10445,10 @@ typedef struct { #define ENET_TGSR_TF3_MASK (0x8U) #define ENET_TGSR_TF3_SHIFT (3U) #define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) +/*! @} */ /*! @name TCSR - Timer Control Status Register */ +/*! @{ */ #define ENET_TCSR_TDRE_MASK (0x1U) #define ENET_TCSR_TDRE_SHIFT (0U) #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) @@ -9729,14 +10464,17 @@ typedef struct { #define ENET_TCSR_TPWC_MASK (0xF800U) #define ENET_TCSR_TPWC_SHIFT (11U) #define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK) +/*! @} */ /* The count of ENET_TCSR */ #define ENET_TCSR_COUNT (4U) /*! @name TCCR - Timer Compare Capture Register */ +/*! @{ */ #define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) #define ENET_TCCR_TCC_SHIFT (0U) #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) +/*! @} */ /* The count of ENET_TCCR */ #define ENET_TCCR_COUNT (4U) @@ -9799,6 +10537,7 @@ typedef struct { */ /*! @name CTRL - Control Register */ +/*! @{ */ #define EWM_CTRL_EWMEN_MASK (0x1U) #define EWM_CTRL_EWMEN_SHIFT (0U) #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) @@ -9811,31 +10550,42 @@ typedef struct { #define EWM_CTRL_INTEN_MASK (0x8U) #define EWM_CTRL_INTEN_SHIFT (3U) #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) +/*! @} */ /*! @name SERV - Service Register */ +/*! @{ */ #define EWM_SERV_SERVICE_MASK (0xFFU) #define EWM_SERV_SERVICE_SHIFT (0U) #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) +/*! @} */ /*! @name CMPL - Compare Low Register */ +/*! @{ */ #define EWM_CMPL_COMPAREL_MASK (0xFFU) #define EWM_CMPL_COMPAREL_SHIFT (0U) #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) +/*! @} */ /*! @name CMPH - Compare High Register */ +/*! @{ */ #define EWM_CMPH_COMPAREH_MASK (0xFFU) #define EWM_CMPH_COMPAREH_SHIFT (0U) #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) +/*! @} */ /*! @name CLKCTRL - Clock Control Register */ +/*! @{ */ #define EWM_CLKCTRL_CLKSEL_MASK (0x3U) #define EWM_CLKCTRL_CLKSEL_SHIFT (0U) #define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK) +/*! @} */ /*! @name CLKPRESCALER - Clock Prescaler Register */ +/*! @{ */ #define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) #define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) +/*! @} */ /*! @@ -9922,6 +10672,7 @@ typedef struct { */ /*! @name VERID - Version ID Register */ +/*! @{ */ #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) #define FLEXIO_VERID_FEATURE_SHIFT (0U) #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) @@ -9931,8 +10682,10 @@ typedef struct { #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) #define FLEXIO_VERID_MAJOR_SHIFT (24U) #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) +/*! @} */ /*! @name PARAM - Parameter Register */ +/*! @{ */ #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) #define FLEXIO_PARAM_SHIFTER_SHIFT (0U) #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) @@ -9945,8 +10698,10 @@ typedef struct { #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) #define FLEXIO_PARAM_TRIGGER_SHIFT (24U) #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) +/*! @} */ /*! @name CTRL - FlexIO Control Register */ +/*! @{ */ #define FLEXIO_CTRL_FLEXEN_MASK (0x1U) #define FLEXIO_CTRL_FLEXEN_SHIFT (0U) #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) @@ -9962,53 +10717,73 @@ typedef struct { #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) #define FLEXIO_CTRL_DOZEN_SHIFT (31U) #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) +/*! @} */ /*! @name PIN - Pin State Register */ +/*! @{ */ #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) #define FLEXIO_PIN_PDI_SHIFT (0U) #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) +/*! @} */ /*! @name SHIFTSTAT - Shifter Status Register */ +/*! @{ */ #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU) #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) +/*! @} */ /*! @name SHIFTERR - Shifter Error Register */ +/*! @{ */ #define FLEXIO_SHIFTERR_SEF_MASK (0xFU) #define FLEXIO_SHIFTERR_SEF_SHIFT (0U) #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) +/*! @} */ /*! @name TIMSTAT - Timer Status Register */ +/*! @{ */ #define FLEXIO_TIMSTAT_TSF_MASK (0xFU) #define FLEXIO_TIMSTAT_TSF_SHIFT (0U) #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) +/*! @} */ /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ +/*! @{ */ #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU) #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) +/*! @} */ /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ +/*! @{ */ #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU) #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) +/*! @} */ /*! @name TIMIEN - Timer Interrupt Enable Register */ +/*! @{ */ #define FLEXIO_TIMIEN_TEIE_MASK (0xFU) #define FLEXIO_TIMIEN_TEIE_SHIFT (0U) #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) +/*! @} */ /*! @name SHIFTSDEN - Shifter Status DMA Enable */ +/*! @{ */ #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU) #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) +/*! @} */ /*! @name SHIFTSTATE - Shifter State Register */ +/*! @{ */ #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) #define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) #define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) +/*! @} */ /*! @name SHIFTCTL - Shifter Control N Register */ +/*! @{ */ #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) @@ -10027,11 +10802,13 @@ typedef struct { #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U) #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTCTL */ #define FLEXIO_SHIFTCTL_COUNT (4U) /*! @name SHIFTCFG - Shifter Configuration N Register */ +/*! @{ */ #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) @@ -10044,43 +10821,53 @@ typedef struct { #define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) #define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTCFG */ #define FLEXIO_SHIFTCFG_COUNT (4U) /*! @name SHIFTBUF - Shifter Buffer N Register */ +/*! @{ */ #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUF */ #define FLEXIO_SHIFTBUF_COUNT (4U) /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFBIS */ #define FLEXIO_SHIFTBUFBIS_COUNT (4U) /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFBYS */ #define FLEXIO_SHIFTBUFBYS_COUNT (4U) /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFBBS */ #define FLEXIO_SHIFTBUFBBS_COUNT (4U) /*! @name TIMCTL - Timer Control N Register */ +/*! @{ */ #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) @@ -10102,11 +10889,13 @@ typedef struct { #define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) +/*! @} */ /* The count of FLEXIO_TIMCTL */ #define FLEXIO_TIMCTL_COUNT (4U) /*! @name TIMCFG - Timer Configuration N Register */ +/*! @{ */ #define FLEXIO_TIMCFG_TSTART_MASK (0x2U) #define FLEXIO_TIMCFG_TSTART_SHIFT (1U) #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) @@ -10128,38 +10917,47 @@ typedef struct { #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) +/*! @} */ /* The count of FLEXIO_TIMCFG */ #define FLEXIO_TIMCFG_COUNT (4U) /*! @name TIMCMP - Timer Compare N Register */ +/*! @{ */ #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) #define FLEXIO_TIMCMP_CMP_SHIFT (0U) #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) +/*! @} */ /* The count of FLEXIO_TIMCMP */ #define FLEXIO_TIMCMP_COUNT (4U) /*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFNBS */ #define FLEXIO_SHIFTBUFNBS_COUNT (4U) /*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFHWS */ #define FLEXIO_SHIFTBUFHWS_COUNT (4U) /*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFNIS */ #define FLEXIO_SHIFTBUFNIS_COUNT (4U) @@ -10221,6 +11019,7 @@ typedef struct { */ /*! @name TCM_CTRL - TCM CRTL Register */ +/*! @{ */ #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U) #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U) #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK) @@ -10233,8 +11032,10 @@ typedef struct { #define FLEXRAM_TCM_CTRL_Reserved_MASK (0xFFFFFFF8U) #define FLEXRAM_TCM_CTRL_Reserved_SHIFT (3U) #define FLEXRAM_TCM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK) +/*! @} */ /*! @name OCRAM_MAGIC_ADDR - OCRAM Magic Address Register */ +/*! @{ */ #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U) #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U) #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK) @@ -10244,8 +11045,10 @@ typedef struct { #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT (17U) #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK) +/*! @} */ /*! @name DTCM_MAGIC_ADDR - DTCM Magic Address Register */ +/*! @{ */ #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U) #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U) #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK) @@ -10255,8 +11058,10 @@ typedef struct { #define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) #define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT (17U) #define FLEXRAM_DTCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK) +/*! @} */ /*! @name ITCM_MAGIC_ADDR - ITCM Magic Address Register */ +/*! @{ */ #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U) #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U) #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK) @@ -10266,8 +11071,10 @@ typedef struct { #define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) #define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT (17U) #define FLEXRAM_ITCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK) +/*! @} */ /*! @name INT_STATUS - Interrupt Status Register */ +/*! @{ */ #define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK (0x1U) #define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U) #define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK) @@ -10289,8 +11096,10 @@ typedef struct { #define FLEXRAM_INT_STATUS_Reserved_MASK (0xFFFFFFC0U) #define FLEXRAM_INT_STATUS_Reserved_SHIFT (6U) #define FLEXRAM_INT_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK) +/*! @} */ /*! @name INT_STAT_EN - Interrupt Status Enable Register */ +/*! @{ */ #define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U) #define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U) #define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK) @@ -10312,8 +11121,10 @@ typedef struct { #define FLEXRAM_INT_STAT_EN_Reserved_MASK (0xFFFFFFC0U) #define FLEXRAM_INT_STAT_EN_Reserved_SHIFT (6U) #define FLEXRAM_INT_STAT_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK) +/*! @} */ /*! @name INT_SIG_EN - Interrupt Enable Register */ +/*! @{ */ #define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK (0x1U) #define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U) #define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK) @@ -10335,6 +11146,7 @@ typedef struct { #define FLEXRAM_INT_SIG_EN_Reserved_MASK (0xFFFFFFC0U) #define FLEXRAM_INT_SIG_EN_Reserved_SHIFT (6U) #define FLEXRAM_INT_SIG_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK) +/*! @} */ /*! @@ -10417,6 +11229,7 @@ typedef struct { */ /*! @name MCR0 - Module Control Register 0 */ +/*! @{ */ #define FLEXSPI_MCR0_SWRESET_MASK (0x1U) #define FLEXSPI_MCR0_SWRESET_SHIFT (0U) #define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) @@ -10450,16 +11263,20 @@ typedef struct { #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) #define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) +/*! @} */ /*! @name MCR1 - Module Control Register 1 */ +/*! @{ */ #define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) #define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) #define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) #define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) #define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) +/*! @} */ /*! @name MCR2 - Module Control Register 2 */ +/*! @{ */ #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) #define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) @@ -10475,8 +11292,10 @@ typedef struct { #define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) #define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) +/*! @} */ /*! @name AHBCR - AHB Bus Control Register */ +/*! @{ */ #define FLEXSPI_AHBCR_APAREN_MASK (0x1U) #define FLEXSPI_AHBCR_APAREN_SHIFT (0U) #define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) @@ -10492,8 +11311,10 @@ typedef struct { #define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) #define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) #define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) +/*! @} */ /*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ #define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) #define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) @@ -10527,8 +11348,10 @@ typedef struct { #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) #define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) +/*! @} */ /*! @name INTR - Interrupt Register */ +/*! @{ */ #define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) #define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) #define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) @@ -10562,21 +11385,27 @@ typedef struct { #define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) #define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) +/*! @} */ /*! @name LUTKEY - LUT Key Register */ +/*! @{ */ #define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) #define FLEXSPI_LUTKEY_KEY_SHIFT (0U) #define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) +/*! @} */ /*! @name LUTCR - LUT Control Register */ +/*! @{ */ #define FLEXSPI_LUTCR_LOCK_MASK (0x1U) #define FLEXSPI_LUTCR_LOCK_SHIFT (0U) #define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) #define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) #define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) #define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) +/*! @} */ /*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0 */ +/*! @{ */ #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU) #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) @@ -10586,19 +11415,26 @@ typedef struct { #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U) #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) +/*! @} */ /* The count of FLEXSPI_AHBRXBUFCR0 */ #define FLEXSPI_AHBRXBUFCR0_COUNT (4U) /*! @name FLSHCR0 - Flash A1 Control Register 0..Flash B2 Control Register 0 */ +/*! @{ */ #define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) #define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) +/*! @} */ /* The count of FLEXSPI_FLSHCR0 */ #define FLEXSPI_FLSHCR0_COUNT (4U) /*! @name FLSHCR1 - Flash A1 Control Register 1..Flash B2 Control Register 1 */ +/*! @{ */ #define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) #define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) #define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) @@ -10617,11 +11453,13 @@ typedef struct { #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) +/*! @} */ /* The count of FLEXSPI_FLSHCR1 */ #define FLEXSPI_FLSHCR1_COUNT (4U) /*! @name FLSHCR2 - Flash A1 Control Register 2..Flash B2 Control Register 2 */ +/*! @{ */ #define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU) #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) #define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) @@ -10643,11 +11481,13 @@ typedef struct { #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) +/*! @} */ /* The count of FLEXSPI_FLSHCR2 */ #define FLEXSPI_FLSHCR2_COUNT (4U) /*! @name FLSHCR4 - Flash Control Register 4 */ +/*! @{ */ #define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) #define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) @@ -10657,13 +11497,17 @@ typedef struct { #define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) #define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) #define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) +/*! @} */ /*! @name IPCR0 - IP Control Register 0 */ +/*! @{ */ #define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) #define FLEXSPI_IPCR0_SFAR_SHIFT (0U) #define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) +/*! @} */ /*! @name IPCR1 - IP Control Register 1 */ +/*! @{ */ #define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) #define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) #define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) @@ -10676,13 +11520,17 @@ typedef struct { #define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) #define FLEXSPI_IPCR1_IPAREN_SHIFT (31U) #define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) +/*! @} */ /*! @name IPCMD - IP Command Register */ +/*! @{ */ #define FLEXSPI_IPCMD_TRG_MASK (0x1U) #define FLEXSPI_IPCMD_TRG_SHIFT (0U) #define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) +/*! @} */ /*! @name IPRXFCR - IP RX FIFO Control Register */ +/*! @{ */ #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) #define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) @@ -10692,8 +11540,10 @@ typedef struct { #define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU) #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) #define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) +/*! @} */ /*! @name IPTXFCR - IP TX FIFO Control Register */ +/*! @{ */ #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) #define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) @@ -10703,8 +11553,10 @@ typedef struct { #define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU) #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) #define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) +/*! @} */ /*! @name DLLCR - DLL Control Register 0 */ +/*! @{ */ #define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) #define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) #define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) @@ -10720,11 +11572,13 @@ typedef struct { #define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) #define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) +/*! @} */ /* The count of FLEXSPI_DLLCR */ #define FLEXSPI_DLLCR_COUNT (2U) /*! @name STS0 - Status Register 0 */ +/*! @{ */ #define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) #define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) #define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) @@ -10734,8 +11588,10 @@ typedef struct { #define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) #define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) #define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) +/*! @} */ /*! @name STS1 - Status Register 1 */ +/*! @{ */ #define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU) #define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) #define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) @@ -10748,8 +11604,10 @@ typedef struct { #define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) #define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) +/*! @} */ /*! @name STS2 - Status Register 2 */ +/*! @{ */ #define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) #define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) #define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) @@ -10774,8 +11632,10 @@ typedef struct { #define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) #define FLEXSPI_STS2_BREFSEL_SHIFT (24U) #define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) +/*! @} */ /*! @name AHBSPNDSTS - AHB Suspend Status Register */ +/*! @{ */ #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) #define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) @@ -10785,40 +11645,50 @@ typedef struct { #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) #define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) +/*! @} */ /*! @name IPRXFSTS - IP RX FIFO Status Register */ +/*! @{ */ #define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) #define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) #define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) #define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) #define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) +/*! @} */ /*! @name IPTXFSTS - IP TX FIFO Status Register */ +/*! @{ */ #define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) #define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) #define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) #define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) #define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) +/*! @} */ /*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */ +/*! @{ */ #define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) #define FLEXSPI_RFDR_RXDATA_SHIFT (0U) #define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) +/*! @} */ /* The count of FLEXSPI_RFDR */ #define FLEXSPI_RFDR_COUNT (32U) /*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */ +/*! @{ */ #define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) #define FLEXSPI_TFDR_TXDATA_SHIFT (0U) #define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) +/*! @} */ /* The count of FLEXSPI_TFDR */ #define FLEXSPI_TFDR_COUNT (32U) /*! @name LUT - LUT 0..LUT 63 */ +/*! @{ */ #define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) #define FLEXSPI_LUT_OPERAND0_SHIFT (0U) #define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) @@ -10837,6 +11707,7 @@ typedef struct { #define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) #define FLEXSPI_LUT_OPCODE1_SHIFT (26U) #define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) +/*! @} */ /* The count of FLEXSPI_LUT */ #define FLEXSPI_LUT_COUNT (64U) @@ -10903,6 +11774,7 @@ typedef struct { */ /*! @name CNTR - GPC Interface control register */ +/*! @{ */ #define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U) #define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U) #define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK) @@ -10912,8 +11784,10 @@ typedef struct { #define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U) #define GPC_CNTR_PDRAM0_PGE_SHIFT (22U) #define GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK) +/*! @} */ /*! @name IMR - IRQ masking register 1..IRQ masking register 4 */ +/*! @{ */ #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) #define GPC_IMR_IMR1_SHIFT (0U) #define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK) @@ -10926,11 +11800,13 @@ typedef struct { #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) #define GPC_IMR_IMR4_SHIFT (0U) #define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK) +/*! @} */ /* The count of GPC_IMR */ #define GPC_IMR_COUNT (4U) /*! @name ISR - IRQ status resister 1..IRQ status resister 4 */ +/*! @{ */ #define GPC_ISR_ISR1_MASK (0xFFFFFFFFU) #define GPC_ISR_ISR1_SHIFT (0U) #define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK) @@ -10943,19 +11819,24 @@ typedef struct { #define GPC_ISR_ISR4_MASK (0xFFFFFFFFU) #define GPC_ISR_ISR4_SHIFT (0U) #define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK) +/*! @} */ /* The count of GPC_ISR */ #define GPC_ISR_COUNT (4U) /*! @name IMR5 - IRQ masking register 5 */ +/*! @{ */ #define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU) #define GPC_IMR5_IMR5_SHIFT (0U) #define GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK) +/*! @} */ /*! @name ISR5 - IRQ status resister 5 */ +/*! @{ */ #define GPC_ISR5_ISR4_MASK (0xFFFFFFFFU) #define GPC_ISR5_ISR4_SHIFT (0U) #define GPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK) +/*! @} */ /*! @@ -10999,6 +11880,10 @@ typedef struct { __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ + uint8_t RESERVED_0[100]; + __O uint32_t DR_SET; /**< GPIO data register SET, offset: 0x84 */ + __O uint32_t DR_CLEAR; /**< GPIO data register CLEAR, offset: 0x88 */ + __O uint32_t DR_TOGGLE; /**< GPIO data register TOGGLE, offset: 0x8C */ } GPIO_Type; /* ---------------------------------------------------------------------------- @@ -11011,21 +11896,28 @@ typedef struct { */ /*! @name DR - GPIO data register */ +/*! @{ */ #define GPIO_DR_DR_MASK (0xFFFFFFFFU) #define GPIO_DR_DR_SHIFT (0U) #define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) +/*! @} */ /*! @name GDIR - GPIO direction register */ +/*! @{ */ #define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) #define GPIO_GDIR_GDIR_SHIFT (0U) #define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) +/*! @} */ /*! @name PSR - GPIO pad status register */ +/*! @{ */ #define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) #define GPIO_PSR_PSR_SHIFT (0U) #define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) +/*! @} */ /*! @name ICR1 - GPIO interrupt configuration register1 */ +/*! @{ */ #define GPIO_ICR1_ICR0_MASK (0x3U) #define GPIO_ICR1_ICR0_SHIFT (0U) #define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) @@ -11074,8 +11966,10 @@ typedef struct { #define GPIO_ICR1_ICR15_MASK (0xC0000000U) #define GPIO_ICR1_ICR15_SHIFT (30U) #define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) +/*! @} */ /*! @name ICR2 - GPIO interrupt configuration register2 */ +/*! @{ */ #define GPIO_ICR2_ICR16_MASK (0x3U) #define GPIO_ICR2_ICR16_SHIFT (0U) #define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) @@ -11124,21 +12018,49 @@ typedef struct { #define GPIO_ICR2_ICR31_MASK (0xC0000000U) #define GPIO_ICR2_ICR31_SHIFT (30U) #define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) +/*! @} */ /*! @name IMR - GPIO interrupt mask register */ +/*! @{ */ #define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) #define GPIO_IMR_IMR_SHIFT (0U) #define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) +/*! @} */ /*! @name ISR - GPIO interrupt status register */ +/*! @{ */ #define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) #define GPIO_ISR_ISR_SHIFT (0U) #define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) +/*! @} */ /*! @name EDGE_SEL - GPIO edge select register */ +/*! @{ */ #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) +/*! @} */ + +/*! @name DR_SET - GPIO data register SET */ +/*! @{ */ +#define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU) +#define GPIO_DR_SET_DR_SET_SHIFT (0U) +#define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK) +/*! @} */ + +/*! @name DR_CLEAR - GPIO data register CLEAR */ +/*! @{ */ +#define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU) +#define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U) +#define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK) +/*! @} */ + +/*! @name DR_TOGGLE - GPIO data register TOGGLE */ +/*! @{ */ +#define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU) +#define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U) +#define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK) +/*! @} */ /*! @@ -11210,6 +12132,7 @@ typedef struct { */ /*! @name CR - GPT Control Register */ +/*! @{ */ #define GPT_CR_EN_MASK (0x1U) #define GPT_CR_EN_SHIFT (0U) #define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) @@ -11264,16 +12187,20 @@ typedef struct { #define GPT_CR_FO3_MASK (0x80000000U) #define GPT_CR_FO3_SHIFT (31U) #define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) +/*! @} */ /*! @name PR - GPT Prescaler Register */ +/*! @{ */ #define GPT_PR_PRESCALER_MASK (0xFFFU) #define GPT_PR_PRESCALER_SHIFT (0U) #define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) #define GPT_PR_PRESCALER24M_MASK (0xF000U) #define GPT_PR_PRESCALER24M_SHIFT (12U) #define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) +/*! @} */ /*! @name SR - GPT Status Register */ +/*! @{ */ #define GPT_SR_OF1_MASK (0x1U) #define GPT_SR_OF1_SHIFT (0U) #define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) @@ -11292,8 +12219,10 @@ typedef struct { #define GPT_SR_ROV_MASK (0x20U) #define GPT_SR_ROV_SHIFT (5U) #define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) +/*! @} */ /*! @name IR - GPT Interrupt Register */ +/*! @{ */ #define GPT_IR_OF1IE_MASK (0x1U) #define GPT_IR_OF1IE_SHIFT (0U) #define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) @@ -11312,27 +12241,34 @@ typedef struct { #define GPT_IR_ROVIE_MASK (0x20U) #define GPT_IR_ROVIE_SHIFT (5U) #define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) +/*! @} */ /*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ +/*! @{ */ #define GPT_OCR_COMP_MASK (0xFFFFFFFFU) #define GPT_OCR_COMP_SHIFT (0U) #define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) +/*! @} */ /* The count of GPT_OCR */ #define GPT_OCR_COUNT (3U) /*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ +/*! @{ */ #define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) #define GPT_ICR_CAPT_SHIFT (0U) #define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) +/*! @} */ /* The count of GPT_ICR */ #define GPT_ICR_COUNT (2U) /*! @name CNT - GPT Counter Register */ +/*! @{ */ #define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) #define GPT_CNT_COUNT_SHIFT (0U) #define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) +/*! @} */ /*! @@ -11409,6 +12345,7 @@ typedef struct { */ /*! @name VERID - Version ID Register */ +/*! @{ */ #define I2S_VERID_FEATURE_MASK (0xFFFFU) #define I2S_VERID_FEATURE_SHIFT (0U) #define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) @@ -11418,8 +12355,10 @@ typedef struct { #define I2S_VERID_MAJOR_MASK (0xFF000000U) #define I2S_VERID_MAJOR_SHIFT (24U) #define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) +/*! @} */ /*! @name PARAM - Parameter Register */ +/*! @{ */ #define I2S_PARAM_DATALINE_MASK (0xFU) #define I2S_PARAM_DATALINE_SHIFT (0U) #define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) @@ -11429,8 +12368,10 @@ typedef struct { #define I2S_PARAM_FRAME_MASK (0xF0000U) #define I2S_PARAM_FRAME_SHIFT (16U) #define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) +/*! @} */ /*! @name TCSR - SAI Transmit Control Register */ +/*! @{ */ #define I2S_TCSR_FRDE_MASK (0x1U) #define I2S_TCSR_FRDE_SHIFT (0U) #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) @@ -11485,13 +12426,17 @@ typedef struct { #define I2S_TCSR_TE_MASK (0x80000000U) #define I2S_TCSR_TE_SHIFT (31U) #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) +/*! @} */ /*! @name TCR1 - SAI Transmit Configuration 1 Register */ +/*! @{ */ #define I2S_TCR1_TFW_MASK (0x1FU) #define I2S_TCR1_TFW_SHIFT (0U) #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) +/*! @} */ /*! @name TCR2 - SAI Transmit Configuration 2 Register */ +/*! @{ */ #define I2S_TCR2_DIV_MASK (0xFFU) #define I2S_TCR2_DIV_SHIFT (0U) #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) @@ -11513,8 +12458,10 @@ typedef struct { #define I2S_TCR2_SYNC_MASK (0xC0000000U) #define I2S_TCR2_SYNC_SHIFT (30U) #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) +/*! @} */ /*! @name TCR3 - SAI Transmit Configuration 3 Register */ +/*! @{ */ #define I2S_TCR3_WDFL_MASK (0x1FU) #define I2S_TCR3_WDFL_SHIFT (0U) #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) @@ -11524,8 +12471,10 @@ typedef struct { #define I2S_TCR3_CFR_MASK (0xF000000U) #define I2S_TCR3_CFR_SHIFT (24U) #define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) +/*! @} */ /*! @name TCR4 - SAI Transmit Configuration 4 Register */ +/*! @{ */ #define I2S_TCR4_FSD_MASK (0x1U) #define I2S_TCR4_FSD_SHIFT (0U) #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) @@ -11559,8 +12508,10 @@ typedef struct { #define I2S_TCR4_FCONT_MASK (0x10000000U) #define I2S_TCR4_FCONT_SHIFT (28U) #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) +/*! @} */ /*! @name TCR5 - SAI Transmit Configuration 5 Register */ +/*! @{ */ #define I2S_TCR5_FBT_MASK (0x1F00U) #define I2S_TCR5_FBT_SHIFT (8U) #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) @@ -11570,16 +12521,20 @@ typedef struct { #define I2S_TCR5_WNW_MASK (0x1F000000U) #define I2S_TCR5_WNW_SHIFT (24U) #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) +/*! @} */ /*! @name TDR - SAI Transmit Data Register */ +/*! @{ */ #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) #define I2S_TDR_TDR_SHIFT (0U) #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) +/*! @} */ /* The count of I2S_TDR */ #define I2S_TDR_COUNT (4U) /*! @name TFR - SAI Transmit FIFO Register */ +/*! @{ */ #define I2S_TFR_RFP_MASK (0x3FU) #define I2S_TFR_RFP_SHIFT (0U) #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) @@ -11589,16 +12544,20 @@ typedef struct { #define I2S_TFR_WCP_MASK (0x80000000U) #define I2S_TFR_WCP_SHIFT (31U) #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) +/*! @} */ /* The count of I2S_TFR */ #define I2S_TFR_COUNT (4U) /*! @name TMR - SAI Transmit Mask Register */ +/*! @{ */ #define I2S_TMR_TWM_MASK (0xFFFFFFFFU) #define I2S_TMR_TWM_SHIFT (0U) #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) +/*! @} */ /*! @name RCSR - SAI Receive Control Register */ +/*! @{ */ #define I2S_RCSR_FRDE_MASK (0x1U) #define I2S_RCSR_FRDE_SHIFT (0U) #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) @@ -11653,13 +12612,17 @@ typedef struct { #define I2S_RCSR_RE_MASK (0x80000000U) #define I2S_RCSR_RE_SHIFT (31U) #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) +/*! @} */ /*! @name RCR1 - SAI Receive Configuration 1 Register */ +/*! @{ */ #define I2S_RCR1_RFW_MASK (0x1FU) #define I2S_RCR1_RFW_SHIFT (0U) #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) +/*! @} */ /*! @name RCR2 - SAI Receive Configuration 2 Register */ +/*! @{ */ #define I2S_RCR2_DIV_MASK (0xFFU) #define I2S_RCR2_DIV_SHIFT (0U) #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) @@ -11681,8 +12644,10 @@ typedef struct { #define I2S_RCR2_SYNC_MASK (0xC0000000U) #define I2S_RCR2_SYNC_SHIFT (30U) #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) +/*! @} */ /*! @name RCR3 - SAI Receive Configuration 3 Register */ +/*! @{ */ #define I2S_RCR3_WDFL_MASK (0x1FU) #define I2S_RCR3_WDFL_SHIFT (0U) #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) @@ -11692,8 +12657,10 @@ typedef struct { #define I2S_RCR3_CFR_MASK (0xF000000U) #define I2S_RCR3_CFR_SHIFT (24U) #define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) +/*! @} */ /*! @name RCR4 - SAI Receive Configuration 4 Register */ +/*! @{ */ #define I2S_RCR4_FSD_MASK (0x1U) #define I2S_RCR4_FSD_SHIFT (0U) #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) @@ -11724,8 +12691,10 @@ typedef struct { #define I2S_RCR4_FCONT_MASK (0x10000000U) #define I2S_RCR4_FCONT_SHIFT (28U) #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) +/*! @} */ /*! @name RCR5 - SAI Receive Configuration 5 Register */ +/*! @{ */ #define I2S_RCR5_FBT_MASK (0x1F00U) #define I2S_RCR5_FBT_SHIFT (8U) #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) @@ -11735,16 +12704,20 @@ typedef struct { #define I2S_RCR5_WNW_MASK (0x1F000000U) #define I2S_RCR5_WNW_SHIFT (24U) #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) +/*! @} */ /*! @name RDR - SAI Receive Data Register */ +/*! @{ */ #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) #define I2S_RDR_RDR_SHIFT (0U) #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) +/*! @} */ /* The count of I2S_RDR */ #define I2S_RDR_COUNT (4U) /*! @name RFR - SAI Receive FIFO Register */ +/*! @{ */ #define I2S_RFR_RFP_MASK (0x3FU) #define I2S_RFR_RFP_SHIFT (0U) #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) @@ -11754,14 +12727,17 @@ typedef struct { #define I2S_RFR_WFP_MASK (0x3F0000U) #define I2S_RFR_WFP_SHIFT (16U) #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) +/*! @} */ /* The count of I2S_RFR */ #define I2S_RFR_COUNT (4U) /*! @name RMR - SAI Receive Mask Register */ +/*! @{ */ #define I2S_RMR_RWM_MASK (0xFFFFFFFFU) #define I2S_RMR_RWM_SHIFT (0U) #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) +/*! @} */ /*! @@ -11822,17 +12798,20 @@ typedef struct { */ /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register */ +/*! @{ */ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U) #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) #define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) +/*! @} */ /* The count of IOMUXC_SW_MUX_CTL_PAD */ #define IOMUXC_SW_MUX_CTL_PAD_COUNT (124U) /*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U) #define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U) #define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) @@ -11857,14 +12836,17 @@ typedef struct { #define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U) #define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U) #define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK) +/*! @} */ /* The count of IOMUXC_SW_PAD_CTL_PAD */ #define IOMUXC_SW_PAD_CTL_PAD_COUNT (124U) /*! @name SELECT_INPUT - ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register */ +/*! @{ */ #define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ #define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) #define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ +/*! @} */ /* The count of IOMUXC_SELECT_INPUT */ #define IOMUXC_SELECT_INPUT_COUNT (154U) @@ -11939,6 +12921,7 @@ typedef struct { */ /*! @name GPR1 - GPR1 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U) #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U) #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK) @@ -11984,8 +12967,10 @@ typedef struct { #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U) #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U) #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK) +/*! @} */ /*! @name GPR2 - GPR2 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U) #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U) #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK) @@ -12016,8 +13001,10 @@ typedef struct { #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U) #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U) #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK) +/*! @} */ /*! @name GPR3 - GPR3 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU) #define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U) #define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK) @@ -12027,8 +13014,10 @@ typedef struct { #define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U) #define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U) #define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK) +/*! @} */ /*! @name GPR4 - GPR4 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U) #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U) #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK) @@ -12107,8 +13096,10 @@ typedef struct { #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U) #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U) #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK) +/*! @} */ /*! @name GPR5 - GPR5 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U) #define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U) #define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK) @@ -12118,9 +13109,6 @@ typedef struct { #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U) #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U) #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK) -#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK (0x1000000U) -#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT (24U) -#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK) #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U) #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U) #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK) @@ -12130,8 +13118,10 @@ typedef struct { #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U) #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U) #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK) +/*! @} */ /*! @name GPR6 - GPR6 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U) #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U) #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK) @@ -12228,8 +13218,10 @@ typedef struct { #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK) +/*! @} */ /*! @name GPR7 - GPR7 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U) #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U) #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK) @@ -12326,8 +13318,10 @@ typedef struct { #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U) #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U) #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK) +/*! @} */ /*! @name GPR8 - GPR8 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U) #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U) #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK) @@ -12424,8 +13418,10 @@ typedef struct { #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U) #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U) #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK) +/*! @} */ /*! @name GPR10 - GPR10 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U) #define IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U) #define IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK) @@ -12462,8 +13458,10 @@ typedef struct { #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U) #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U) #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK) +/*! @} */ /*! @name GPR11 - GPR11 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U) #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U) #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK) @@ -12494,8 +13492,10 @@ typedef struct { #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U) #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U) #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK) +/*! @} */ /*! @name GPR12 - GPR12 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U) #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U) #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK) @@ -12511,8 +13511,10 @@ typedef struct { #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U) #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U) #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK) +/*! @} */ /*! @name GPR13 - GPR13 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U) #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U) #define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK) @@ -12525,8 +13527,10 @@ typedef struct { #define IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U) #define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U) #define IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK) +/*! @} */ /*! @name GPR14 - GPR14 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U) #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U) #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK) @@ -12563,14 +13567,16 @@ typedef struct { #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U) #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U) #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_MASK (0xF0000U) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_SHIFT (16U) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_MASK) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_MASK (0xF00000U) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_SHIFT (20U) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_MASK) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK) +/*! @} */ /*! @name GPR16 - GPR16 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U) #define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U) #define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK) @@ -12583,75 +13589,94 @@ typedef struct { #define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK (0xFFFFFF80U) #define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT (7U) #define IOMUXC_GPR_GPR16_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK) +/*! @} */ /*! @name GPR17 - GPR17 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU) #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U) #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK) +/*! @} */ /*! @name GPR18 - GPR18 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U) #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U) #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK) #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U) #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK) +/*! @} */ /*! @name GPR19 - GPR19 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U) #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U) #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK) #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U) #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK) +/*! @} */ /*! @name GPR20 - GPR20 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U) #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U) #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK) #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U) #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK) +/*! @} */ /*! @name GPR21 - GPR21 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U) #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U) #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK) #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U) #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK) +/*! @} */ /*! @name GPR22 - GPR22 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U) #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U) #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK) #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U) #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK) +/*! @} */ /*! @name GPR23 - GPR23 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U) #define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U) #define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK) #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U) #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK) +/*! @} */ /*! @name GPR24 - GPR24 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U) #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U) #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK) #define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT (3U) #define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK) +/*! @} */ /*! @name GPR25 - GPR25 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U) #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U) #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK) #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U) #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK) +/*! @} */ /*! @@ -12706,30 +13731,37 @@ typedef struct { */ /*! @name SW_MUX_CTL_PAD_WAKEUP - SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK) +/*! @} */ /*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK) +/*! @} */ /*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_TEST_MODE - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK) @@ -12754,8 +13786,10 @@ typedef struct { #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_POR_B - SW_PAD_CTL_PAD_POR_B SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK) @@ -12780,8 +13814,10 @@ typedef struct { #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_ONOFF - SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK) @@ -12806,8 +13842,10 @@ typedef struct { #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_WAKEUP - SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK) @@ -12832,8 +13870,10 @@ typedef struct { #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_PMIC_ON_REQ - SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK) @@ -12858,8 +13898,10 @@ typedef struct { #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_PMIC_STBY_REQ - SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK) @@ -12884,6 +13926,7 @@ typedef struct { #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK) +/*! @} */ /*! @@ -12933,6 +13976,7 @@ typedef struct { */ /*! @name GPR3 - GPR3 General Purpose Register */ +/*! @{ */ #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U) #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U) #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK) @@ -12942,9 +13986,9 @@ typedef struct { #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU) #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U) #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_MASK (0x10000U) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_SHIFT (16U) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK) #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U) #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U) #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK) @@ -12954,6 +13998,7 @@ typedef struct { #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U) #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U) #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK) +/*! @} */ /*! @@ -13003,14 +14048,17 @@ typedef struct { */ /*! @name KPCR - Keypad Control Register */ +/*! @{ */ #define KPP_KPCR_KRE_MASK (0xFFU) #define KPP_KPCR_KRE_SHIFT (0U) #define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK) #define KPP_KPCR_KCO_MASK (0xFF00U) #define KPP_KPCR_KCO_SHIFT (8U) #define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK) +/*! @} */ /*! @name KPSR - Keypad Status Register */ +/*! @{ */ #define KPP_KPSR_KPKD_MASK (0x1U) #define KPP_KPSR_KPKD_SHIFT (0U) #define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK) @@ -13029,22 +14077,27 @@ typedef struct { #define KPP_KPSR_KRIE_MASK (0x200U) #define KPP_KPSR_KRIE_SHIFT (9U) #define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK) +/*! @} */ /*! @name KDDR - Keypad Data Direction Register */ +/*! @{ */ #define KPP_KDDR_KRDD_MASK (0xFFU) #define KPP_KDDR_KRDD_SHIFT (0U) #define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK) #define KPP_KDDR_KCDD_MASK (0xFF00U) #define KPP_KDDR_KCDD_SHIFT (8U) #define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK) +/*! @} */ /*! @name KPDR - Keypad Data Register */ +/*! @{ */ #define KPP_KPDR_KRD_MASK (0xFFU) #define KPP_KPDR_KRD_SHIFT (0U) #define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK) #define KPP_KPDR_KCD_MASK (0xFF00U) #define KPP_KPDR_KCD_SHIFT (8U) #define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) +/*! @} */ /*! @@ -13080,35 +14133,35 @@ typedef struct { /** LCDIF - Register Layout Typedef */ typedef struct { - __IO uint32_t CTRL; /**< eLCDIF General Control Register, offset: 0x0 */ - __IO uint32_t CTRL_SET; /**< eLCDIF General Control Register, offset: 0x4 */ - __IO uint32_t CTRL_CLR; /**< eLCDIF General Control Register, offset: 0x8 */ - __IO uint32_t CTRL_TOG; /**< eLCDIF General Control Register, offset: 0xC */ - __IO uint32_t CTRL1; /**< eLCDIF General Control1 Register, offset: 0x10 */ - __IO uint32_t CTRL1_SET; /**< eLCDIF General Control1 Register, offset: 0x14 */ - __IO uint32_t CTRL1_CLR; /**< eLCDIF General Control1 Register, offset: 0x18 */ - __IO uint32_t CTRL1_TOG; /**< eLCDIF General Control1 Register, offset: 0x1C */ - __IO uint32_t CTRL2; /**< eLCDIF General Control2 Register, offset: 0x20 */ - __IO uint32_t CTRL2_SET; /**< eLCDIF General Control2 Register, offset: 0x24 */ - __IO uint32_t CTRL2_CLR; /**< eLCDIF General Control2 Register, offset: 0x28 */ - __IO uint32_t CTRL2_TOG; /**< eLCDIF General Control2 Register, offset: 0x2C */ - __IO uint32_t TRANSFER_COUNT; /**< eLCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ + __IO uint32_t CTRL; /**< LCDIF General Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< LCDIF General Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< LCDIF General Control Register, offset: 0xC */ + __IO uint32_t CTRL1; /**< LCDIF General Control1 Register, offset: 0x10 */ + __IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x14 */ + __IO uint32_t CTRL1_CLR; /**< LCDIF General Control1 Register, offset: 0x18 */ + __IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1C */ + __IO uint32_t CTRL2; /**< LCDIF General Control2 Register, offset: 0x20 */ + __IO uint32_t CTRL2_SET; /**< LCDIF General Control2 Register, offset: 0x24 */ + __IO uint32_t CTRL2_CLR; /**< LCDIF General Control2 Register, offset: 0x28 */ + __IO uint32_t CTRL2_TOG; /**< LCDIF General Control2 Register, offset: 0x2C */ + __IO uint32_t TRANSFER_COUNT; /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ uint8_t RESERVED_0[12]; __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ uint8_t RESERVED_1[12]; __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ uint8_t RESERVED_2[28]; - __IO uint32_t VDCTRL0; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ - __IO uint32_t VDCTRL0_SET; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ - __IO uint32_t VDCTRL0_CLR; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ - __IO uint32_t VDCTRL0_TOG; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ - __IO uint32_t VDCTRL1; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ + __IO uint32_t VDCTRL0; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ + __IO uint32_t VDCTRL0_SET; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ + __IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ + __IO uint32_t VDCTRL0_TOG; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ + __IO uint32_t VDCTRL1; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ uint8_t RESERVED_3[12]; __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ uint8_t RESERVED_4[12]; - __IO uint32_t VDCTRL3; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ + __IO uint32_t VDCTRL3; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ uint8_t RESERVED_5[12]; - __IO uint32_t VDCTRL4; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ + __IO uint32_t VDCTRL4; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ uint8_t RESERVED_6[220]; __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ uint8_t RESERVED_7[12]; @@ -13116,7 +14169,7 @@ typedef struct { uint8_t RESERVED_8[12]; __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ uint8_t RESERVED_9[76]; - __IO uint32_t THRES; /**< eLCDIF Threshold Register, offset: 0x200 */ + __IO uint32_t THRES; /**< LCDIF Threshold Register, offset: 0x200 */ uint8_t RESERVED_10[380]; __IO uint32_t PIGEONCTRL0; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x380 */ __IO uint32_t PIGEONCTRL0_SET; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x384 */ @@ -13159,7 +14212,8 @@ typedef struct { * @{ */ -/*! @name CTRL - eLCDIF General Control Register */ +/*! @name CTRL - LCDIF General Control Register */ +/*! @{ */ #define LCDIF_CTRL_RUN_MASK (0x1U) #define LCDIF_CTRL_RUN_SHIFT (0U) #define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) @@ -13211,8 +14265,10 @@ typedef struct { #define LCDIF_CTRL_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_SFTRST_SHIFT (31U) #define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) +/*! @} */ -/*! @name CTRL_SET - eLCDIF General Control Register */ +/*! @name CTRL_SET - LCDIF General Control Register */ +/*! @{ */ #define LCDIF_CTRL_SET_RUN_MASK (0x1U) #define LCDIF_CTRL_SET_RUN_SHIFT (0U) #define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) @@ -13264,8 +14320,10 @@ typedef struct { #define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) #define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) +/*! @} */ -/*! @name CTRL_CLR - eLCDIF General Control Register */ +/*! @name CTRL_CLR - LCDIF General Control Register */ +/*! @{ */ #define LCDIF_CTRL_CLR_RUN_MASK (0x1U) #define LCDIF_CTRL_CLR_RUN_SHIFT (0U) #define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) @@ -13317,8 +14375,10 @@ typedef struct { #define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) #define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) +/*! @} */ -/*! @name CTRL_TOG - eLCDIF General Control Register */ +/*! @name CTRL_TOG - LCDIF General Control Register */ +/*! @{ */ #define LCDIF_CTRL_TOG_RUN_MASK (0x1U) #define LCDIF_CTRL_TOG_RUN_SHIFT (0U) #define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) @@ -13370,8 +14430,10 @@ typedef struct { #define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) #define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) +/*! @} */ -/*! @name CTRL1 - eLCDIF General Control1 Register */ +/*! @name CTRL1 - LCDIF General Control1 Register */ +/*! @{ */ #define LCDIF_CTRL1_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) @@ -13429,8 +14491,10 @@ typedef struct { #define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U) #define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U) #define LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK) +/*! @} */ -/*! @name CTRL1_SET - eLCDIF General Control1 Register */ +/*! @name CTRL1_SET - LCDIF General Control1 Register */ +/*! @{ */ #define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) @@ -13488,8 +14552,10 @@ typedef struct { #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U) #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U) #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK) +/*! @} */ -/*! @name CTRL1_CLR - eLCDIF General Control1 Register */ +/*! @name CTRL1_CLR - LCDIF General Control1 Register */ +/*! @{ */ #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) @@ -13547,8 +14613,10 @@ typedef struct { #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U) #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U) #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK) +/*! @} */ -/*! @name CTRL1_TOG - eLCDIF General Control1 Register */ +/*! @name CTRL1_TOG - LCDIF General Control1 Register */ +/*! @{ */ #define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) @@ -13606,8 +14674,10 @@ typedef struct { #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U) #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U) #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK) +/*! @} */ -/*! @name CTRL2 - eLCDIF General Control2 Register */ +/*! @name CTRL2 - LCDIF General Control2 Register */ +/*! @{ */ #define LCDIF_CTRL2_RSRVD0_MASK (0xFFFU) #define LCDIF_CTRL2_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) @@ -13632,8 +14702,10 @@ typedef struct { #define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) +/*! @} */ -/*! @name CTRL2_SET - eLCDIF General Control2 Register */ +/*! @name CTRL2_SET - LCDIF General Control2 Register */ +/*! @{ */ #define LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU) #define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) @@ -13658,8 +14730,10 @@ typedef struct { #define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) +/*! @} */ -/*! @name CTRL2_CLR - eLCDIF General Control2 Register */ +/*! @name CTRL2_CLR - LCDIF General Control2 Register */ +/*! @{ */ #define LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU) #define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) @@ -13684,8 +14758,10 @@ typedef struct { #define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) +/*! @} */ -/*! @name CTRL2_TOG - eLCDIF General Control2 Register */ +/*! @name CTRL2_TOG - LCDIF General Control2 Register */ +/*! @{ */ #define LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU) #define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) @@ -13710,26 +14786,34 @@ typedef struct { #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) +/*! @} */ -/*! @name TRANSFER_COUNT - eLCDIF Horizontal and Vertical Valid Data Count Register */ +/*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */ +/*! @{ */ #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU) #define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) #define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U) #define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) #define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) +/*! @} */ /*! @name CUR_BUF - LCD Interface Current Buffer Address Register */ +/*! @{ */ #define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_CUR_BUF_ADDR_SHIFT (0U) #define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) +/*! @} */ /*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */ +/*! @{ */ #define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) #define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) +/*! @} */ -/*! @name VDCTRL0 - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) @@ -13766,8 +14850,10 @@ typedef struct { #define LCDIF_VDCTRL0_RSRVD2_MASK (0xE0000000U) #define LCDIF_VDCTRL0_RSRVD2_SHIFT (29U) #define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) +/*! @} */ -/*! @name VDCTRL0_SET - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) @@ -13804,8 +14890,10 @@ typedef struct { #define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xE0000000U) #define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (29U) #define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) +/*! @} */ -/*! @name VDCTRL0_CLR - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) @@ -13842,8 +14930,10 @@ typedef struct { #define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xE0000000U) #define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (29U) #define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) +/*! @} */ -/*! @name VDCTRL0_TOG - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) @@ -13880,21 +14970,27 @@ typedef struct { #define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xE0000000U) #define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (29U) #define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) +/*! @} */ -/*! @name VDCTRL1 - eLCDIF VSYNC Mode and Dotclk Mode Control Register1 */ +/*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */ +/*! @{ */ #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU) #define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) #define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) +/*! @} */ /*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ +/*! @{ */ #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU) #define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) #define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) +/*! @} */ -/*! @name VDCTRL3 - eLCDIF VSYNC Mode and Dotclk Mode Control Register3 */ +/*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */ +/*! @{ */ #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU) #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) @@ -13910,8 +15006,10 @@ typedef struct { #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) #define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) #define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) +/*! @} */ -/*! @name VDCTRL4 - eLCDIF VSYNC Mode and Dotclk Mode Control Register4 */ +/*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */ +/*! @{ */ #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU) #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) @@ -13924,18 +15022,24 @@ typedef struct { #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) +/*! @} */ /*! @name BM_ERROR_STAT - Bus Master Error Status Register */ +/*! @{ */ #define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) #define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) +/*! @} */ /*! @name CRC_STAT - CRC Status Register */ +/*! @{ */ #define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU) #define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) #define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) +/*! @} */ /*! @name STAT - LCD Interface Status Register */ +/*! @{ */ #define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU) #define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) #define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) @@ -13960,8 +15064,10 @@ typedef struct { #define LCDIF_STAT_PRESENT_MASK (0x80000000U) #define LCDIF_STAT_PRESENT_SHIFT (31U) #define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) +/*! @} */ -/*! @name THRES - eLCDIF Threshold Register */ +/*! @name THRES - LCDIF Threshold Register */ +/*! @{ */ #define LCDIF_THRES_PANIC_MASK (0x1FFU) #define LCDIF_THRES_PANIC_SHIFT (0U) #define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK) @@ -13974,104 +15080,130 @@ typedef struct { #define LCDIF_THRES_RSRVD2_MASK (0xFE000000U) #define LCDIF_THRES_RSRVD2_SHIFT (25U) #define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) +/*! @} */ /*! @name PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK) #define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U) #define LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK) +/*! @} */ /*! @name PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK) #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U) #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK) +/*! @} */ /*! @name PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK) #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U) #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK) +/*! @} */ /*! @name PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK) #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U) #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK) +/*! @} */ /*! @name PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK) #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U) #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK) +/*! @} */ /*! @name PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK) +/*! @} */ /*! @name PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK) +/*! @} */ /*! @name PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK) +/*! @} */ /*! @name PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U) #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U) #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK) #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U) #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U) #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK) +/*! @} */ /*! @name PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U) #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U) #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK) #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U) #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U) #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK) +/*! @} */ /*! @name PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK) +/*! @} */ /*! @name PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK) +/*! @} */ /*! @name PIGEON_0 - Panel Interface Signal Generator Register */ +/*! @{ */ #define LCDIF_PIGEON_0_EN_MASK (0x1U) #define LCDIF_PIGEON_0_EN_SHIFT (0U) #define LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK) @@ -14093,22 +15225,26 @@ typedef struct { #define LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U) #define LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U) #define LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK) +/*! @} */ /* The count of LCDIF_PIGEON_0 */ #define LCDIF_PIGEON_0_COUNT (12U) /*! @name PIGEON_1 - Panel Interface Signal Generator Register */ +/*! @{ */ #define LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU) #define LCDIF_PIGEON_1_SET_CNT_SHIFT (0U) #define LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK) #define LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U) #define LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U) #define LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK) +/*! @} */ /* The count of LCDIF_PIGEON_1 */ #define LCDIF_PIGEON_1_COUNT (12U) /*! @name PIGEON_2 - Panel Interface Signal Generator Register */ +/*! @{ */ #define LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU) #define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U) #define LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK) @@ -14118,34 +15254,45 @@ typedef struct { #define LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U) #define LCDIF_PIGEON_2_RSVD_SHIFT (9U) #define LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK) +/*! @} */ /* The count of LCDIF_PIGEON_2 */ #define LCDIF_PIGEON_2_COUNT (12U) /*! @name LUT_CTRL - Lookup Table Data Register. */ +/*! @{ */ #define LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U) #define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U) #define LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK) +/*! @} */ /*! @name LUT0_ADDR - Lookup Table Control Register. */ +/*! @{ */ #define LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU) #define LCDIF_LUT0_ADDR_ADDR_SHIFT (0U) #define LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK) +/*! @} */ /*! @name LUT0_DATA - Lookup Table Data Register. */ +/*! @{ */ #define LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU) #define LCDIF_LUT0_DATA_DATA_SHIFT (0U) #define LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK) +/*! @} */ /*! @name LUT1_ADDR - Lookup Table Control Register. */ +/*! @{ */ #define LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU) #define LCDIF_LUT1_ADDR_ADDR_SHIFT (0U) #define LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK) +/*! @} */ /*! @name LUT1_DATA - Lookup Table Data Register. */ +/*! @{ */ #define LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU) #define LCDIF_LUT1_DATA_DATA_SHIFT (0U) #define LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK) +/*! @} */ /*! @@ -14233,6 +15380,7 @@ typedef struct { */ /*! @name VERID - Version ID Register */ +/*! @{ */ #define LPI2C_VERID_FEATURE_MASK (0xFFFFU) #define LPI2C_VERID_FEATURE_SHIFT (0U) #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) @@ -14242,16 +15390,20 @@ typedef struct { #define LPI2C_VERID_MAJOR_MASK (0xFF000000U) #define LPI2C_VERID_MAJOR_SHIFT (24U) #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) +/*! @} */ /*! @name PARAM - Parameter Register */ +/*! @{ */ #define LPI2C_PARAM_MTXFIFO_MASK (0xFU) #define LPI2C_PARAM_MTXFIFO_SHIFT (0U) #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) #define LPI2C_PARAM_MRXFIFO_SHIFT (8U) #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) +/*! @} */ /*! @name MCR - Master Control Register */ +/*! @{ */ #define LPI2C_MCR_MEN_MASK (0x1U) #define LPI2C_MCR_MEN_SHIFT (0U) #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) @@ -14270,8 +15422,10 @@ typedef struct { #define LPI2C_MCR_RRF_MASK (0x200U) #define LPI2C_MCR_RRF_SHIFT (9U) #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) +/*! @} */ /*! @name MSR - Master Status Register */ +/*! @{ */ #define LPI2C_MSR_TDF_MASK (0x1U) #define LPI2C_MSR_TDF_SHIFT (0U) #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) @@ -14305,8 +15459,10 @@ typedef struct { #define LPI2C_MSR_BBF_MASK (0x2000000U) #define LPI2C_MSR_BBF_SHIFT (25U) #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) +/*! @} */ /*! @name MIER - Master Interrupt Enable Register */ +/*! @{ */ #define LPI2C_MIER_TDIE_MASK (0x1U) #define LPI2C_MIER_TDIE_SHIFT (0U) #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) @@ -14334,16 +15490,20 @@ typedef struct { #define LPI2C_MIER_DMIE_MASK (0x4000U) #define LPI2C_MIER_DMIE_SHIFT (14U) #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) +/*! @} */ /*! @name MDER - Master DMA Enable Register */ +/*! @{ */ #define LPI2C_MDER_TDDE_MASK (0x1U) #define LPI2C_MDER_TDDE_SHIFT (0U) #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) #define LPI2C_MDER_RDDE_MASK (0x2U) #define LPI2C_MDER_RDDE_SHIFT (1U) #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) +/*! @} */ /*! @name MCFGR0 - Master Configuration Register 0 */ +/*! @{ */ #define LPI2C_MCFGR0_HREN_MASK (0x1U) #define LPI2C_MCFGR0_HREN_SHIFT (0U) #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) @@ -14359,8 +15519,10 @@ typedef struct { #define LPI2C_MCFGR0_RDMO_MASK (0x200U) #define LPI2C_MCFGR0_RDMO_SHIFT (9U) #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) +/*! @} */ /*! @name MCFGR1 - Master Configuration Register 1 */ +/*! @{ */ #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) @@ -14379,8 +15541,10 @@ typedef struct { #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) #define LPI2C_MCFGR1_PINCFG_SHIFT (24U) #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) +/*! @} */ /*! @name MCFGR2 - Master Configuration Register 2 */ +/*! @{ */ #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) @@ -14390,21 +15554,27 @@ typedef struct { #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) +/*! @} */ /*! @name MCFGR3 - Master Configuration Register 3 */ +/*! @{ */ #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) #define LPI2C_MCFGR3_PINLOW_SHIFT (8U) #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) +/*! @} */ /*! @name MDMR - Master Data Match Register */ +/*! @{ */ #define LPI2C_MDMR_MATCH0_MASK (0xFFU) #define LPI2C_MDMR_MATCH0_SHIFT (0U) #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) #define LPI2C_MDMR_MATCH1_SHIFT (16U) #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) +/*! @} */ /*! @name MCCR0 - Master Clock Configuration Register 0 */ +/*! @{ */ #define LPI2C_MCCR0_CLKLO_MASK (0x3FU) #define LPI2C_MCCR0_CLKLO_SHIFT (0U) #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) @@ -14417,8 +15587,10 @@ typedef struct { #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR0_DATAVD_SHIFT (24U) #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) +/*! @} */ /*! @name MCCR1 - Master Clock Configuration Register 1 */ +/*! @{ */ #define LPI2C_MCCR1_CLKLO_MASK (0x3FU) #define LPI2C_MCCR1_CLKLO_SHIFT (0U) #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) @@ -14431,40 +15603,50 @@ typedef struct { #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR1_DATAVD_SHIFT (24U) #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) +/*! @} */ /*! @name MFCR - Master FIFO Control Register */ +/*! @{ */ #define LPI2C_MFCR_TXWATER_MASK (0x3U) #define LPI2C_MFCR_TXWATER_SHIFT (0U) #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) #define LPI2C_MFCR_RXWATER_MASK (0x30000U) #define LPI2C_MFCR_RXWATER_SHIFT (16U) #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) +/*! @} */ /*! @name MFSR - Master FIFO Status Register */ +/*! @{ */ #define LPI2C_MFSR_TXCOUNT_MASK (0x7U) #define LPI2C_MFSR_TXCOUNT_SHIFT (0U) #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) #define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) #define LPI2C_MFSR_RXCOUNT_SHIFT (16U) #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) +/*! @} */ /*! @name MTDR - Master Transmit Data Register */ +/*! @{ */ #define LPI2C_MTDR_DATA_MASK (0xFFU) #define LPI2C_MTDR_DATA_SHIFT (0U) #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) #define LPI2C_MTDR_CMD_MASK (0x700U) #define LPI2C_MTDR_CMD_SHIFT (8U) #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) +/*! @} */ /*! @name MRDR - Master Receive Data Register */ +/*! @{ */ #define LPI2C_MRDR_DATA_MASK (0xFFU) #define LPI2C_MRDR_DATA_SHIFT (0U) #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_MRDR_RXEMPTY_SHIFT (14U) #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) +/*! @} */ /*! @name SCR - Slave Control Register */ +/*! @{ */ #define LPI2C_SCR_SEN_MASK (0x1U) #define LPI2C_SCR_SEN_SHIFT (0U) #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) @@ -14483,8 +15665,10 @@ typedef struct { #define LPI2C_SCR_RRF_MASK (0x200U) #define LPI2C_SCR_RRF_SHIFT (9U) #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) +/*! @} */ /*! @name SSR - Slave Status Register */ +/*! @{ */ #define LPI2C_SSR_TDF_MASK (0x1U) #define LPI2C_SSR_TDF_SHIFT (0U) #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) @@ -14527,8 +15711,10 @@ typedef struct { #define LPI2C_SSR_BBF_MASK (0x2000000U) #define LPI2C_SSR_BBF_SHIFT (25U) #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) +/*! @} */ /*! @name SIER - Slave Interrupt Enable Register */ +/*! @{ */ #define LPI2C_SIER_TDIE_MASK (0x1U) #define LPI2C_SIER_TDIE_SHIFT (0U) #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) @@ -14565,8 +15751,10 @@ typedef struct { #define LPI2C_SIER_SARIE_MASK (0x8000U) #define LPI2C_SIER_SARIE_SHIFT (15U) #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) +/*! @} */ /*! @name SDER - Slave DMA Enable Register */ +/*! @{ */ #define LPI2C_SDER_TDDE_MASK (0x1U) #define LPI2C_SDER_TDDE_SHIFT (0U) #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) @@ -14576,8 +15764,10 @@ typedef struct { #define LPI2C_SDER_AVDE_MASK (0x4U) #define LPI2C_SDER_AVDE_SHIFT (2U) #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) +/*! @} */ /*! @name SCFGR1 - Slave Configuration Register 1 */ +/*! @{ */ #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) @@ -14611,8 +15801,10 @@ typedef struct { #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) +/*! @} */ /*! @name SCFGR2 - Slave Configuration Register 2 */ +/*! @{ */ #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) @@ -14625,34 +15817,44 @@ typedef struct { #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) +/*! @} */ /*! @name SAMR - Slave Address Match Register */ +/*! @{ */ #define LPI2C_SAMR_ADDR0_MASK (0x7FEU) #define LPI2C_SAMR_ADDR0_SHIFT (1U) #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) #define LPI2C_SAMR_ADDR1_SHIFT (17U) #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) +/*! @} */ /*! @name SASR - Slave Address Status Register */ +/*! @{ */ #define LPI2C_SASR_RADDR_MASK (0x7FFU) #define LPI2C_SASR_RADDR_SHIFT (0U) #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) #define LPI2C_SASR_ANV_MASK (0x4000U) #define LPI2C_SASR_ANV_SHIFT (14U) #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) +/*! @} */ /*! @name STAR - Slave Transmit ACK Register */ +/*! @{ */ #define LPI2C_STAR_TXNACK_MASK (0x1U) #define LPI2C_STAR_TXNACK_SHIFT (0U) #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) +/*! @} */ /*! @name STDR - Slave Transmit Data Register */ +/*! @{ */ #define LPI2C_STDR_DATA_MASK (0xFFU) #define LPI2C_STDR_DATA_SHIFT (0U) #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) +/*! @} */ /*! @name SRDR - Slave Receive Data Register */ +/*! @{ */ #define LPI2C_SRDR_DATA_MASK (0xFFU) #define LPI2C_SRDR_DATA_SHIFT (0U) #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) @@ -14662,6 +15864,7 @@ typedef struct { #define LPI2C_SRDR_SOF_MASK (0x8000U) #define LPI2C_SRDR_SOF_SHIFT (15U) #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) +/*! @} */ /*! @@ -14743,6 +15946,7 @@ typedef struct { */ /*! @name VERID - Version ID Register */ +/*! @{ */ #define LPSPI_VERID_FEATURE_MASK (0xFFFFU) #define LPSPI_VERID_FEATURE_SHIFT (0U) #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) @@ -14752,8 +15956,10 @@ typedef struct { #define LPSPI_VERID_MAJOR_MASK (0xFF000000U) #define LPSPI_VERID_MAJOR_SHIFT (24U) #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) +/*! @} */ /*! @name PARAM - Parameter Register */ +/*! @{ */ #define LPSPI_PARAM_TXFIFO_MASK (0xFFU) #define LPSPI_PARAM_TXFIFO_SHIFT (0U) #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) @@ -14763,8 +15969,10 @@ typedef struct { #define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) #define LPSPI_PARAM_PCSNUM_SHIFT (16U) #define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) +/*! @} */ /*! @name CR - Control Register */ +/*! @{ */ #define LPSPI_CR_MEN_MASK (0x1U) #define LPSPI_CR_MEN_SHIFT (0U) #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) @@ -14783,8 +15991,10 @@ typedef struct { #define LPSPI_CR_RRF_MASK (0x200U) #define LPSPI_CR_RRF_SHIFT (9U) #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) +/*! @} */ /*! @name SR - Status Register */ +/*! @{ */ #define LPSPI_SR_TDF_MASK (0x1U) #define LPSPI_SR_TDF_SHIFT (0U) #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) @@ -14812,8 +16022,10 @@ typedef struct { #define LPSPI_SR_MBF_MASK (0x1000000U) #define LPSPI_SR_MBF_SHIFT (24U) #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) +/*! @} */ /*! @name IER - Interrupt Enable Register */ +/*! @{ */ #define LPSPI_IER_TDIE_MASK (0x1U) #define LPSPI_IER_TDIE_SHIFT (0U) #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) @@ -14838,16 +16050,20 @@ typedef struct { #define LPSPI_IER_DMIE_MASK (0x2000U) #define LPSPI_IER_DMIE_SHIFT (13U) #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) +/*! @} */ /*! @name DER - DMA Enable Register */ +/*! @{ */ #define LPSPI_DER_TDDE_MASK (0x1U) #define LPSPI_DER_TDDE_SHIFT (0U) #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) #define LPSPI_DER_RDDE_MASK (0x2U) #define LPSPI_DER_RDDE_SHIFT (1U) #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) +/*! @} */ /*! @name CFGR0 - Configuration Register 0 */ +/*! @{ */ #define LPSPI_CFGR0_HREN_MASK (0x1U) #define LPSPI_CFGR0_HREN_SHIFT (0U) #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) @@ -14863,8 +16079,10 @@ typedef struct { #define LPSPI_CFGR0_RDMO_MASK (0x200U) #define LPSPI_CFGR0_RDMO_SHIFT (9U) #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) +/*! @} */ /*! @name CFGR1 - Configuration Register 1 */ +/*! @{ */ #define LPSPI_CFGR1_MASTER_MASK (0x1U) #define LPSPI_CFGR1_MASTER_SHIFT (0U) #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) @@ -14892,18 +16110,24 @@ typedef struct { #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) #define LPSPI_CFGR1_PCSCFG_SHIFT (27U) #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) +/*! @} */ /*! @name DMR0 - Data Match Register 0 */ +/*! @{ */ #define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) #define LPSPI_DMR0_MATCH0_SHIFT (0U) #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) +/*! @} */ /*! @name DMR1 - Data Match Register 1 */ +/*! @{ */ #define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) #define LPSPI_DMR1_MATCH1_SHIFT (0U) #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) +/*! @} */ /*! @name CCR - Clock Configuration Register */ +/*! @{ */ #define LPSPI_CCR_SCKDIV_MASK (0xFFU) #define LPSPI_CCR_SCKDIV_SHIFT (0U) #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) @@ -14916,24 +16140,30 @@ typedef struct { #define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) #define LPSPI_CCR_SCKPCS_SHIFT (24U) #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) +/*! @} */ /*! @name FCR - FIFO Control Register */ +/*! @{ */ #define LPSPI_FCR_TXWATER_MASK (0xFU) #define LPSPI_FCR_TXWATER_SHIFT (0U) #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) #define LPSPI_FCR_RXWATER_MASK (0xF0000U) #define LPSPI_FCR_RXWATER_SHIFT (16U) #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) +/*! @} */ /*! @name FSR - FIFO Status Register */ +/*! @{ */ #define LPSPI_FSR_TXCOUNT_MASK (0x1FU) #define LPSPI_FSR_TXCOUNT_SHIFT (0U) #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) #define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U) #define LPSPI_FSR_RXCOUNT_SHIFT (16U) #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) +/*! @} */ /*! @name TCR - Transmit Command Register */ +/*! @{ */ #define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) #define LPSPI_TCR_FRAMESZ_SHIFT (0U) #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) @@ -14970,24 +16200,31 @@ typedef struct { #define LPSPI_TCR_CPOL_MASK (0x80000000U) #define LPSPI_TCR_CPOL_SHIFT (31U) #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) +/*! @} */ /*! @name TDR - Transmit Data Register */ +/*! @{ */ #define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_TDR_DATA_SHIFT (0U) #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) +/*! @} */ /*! @name RSR - Receive Status Register */ +/*! @{ */ #define LPSPI_RSR_SOF_MASK (0x1U) #define LPSPI_RSR_SOF_SHIFT (0U) #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) #define LPSPI_RSR_RXEMPTY_MASK (0x2U) #define LPSPI_RSR_RXEMPTY_SHIFT (1U) #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) +/*! @} */ /*! @name RDR - Receive Data Register */ +/*! @{ */ #define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_RDR_DATA_SHIFT (0U) #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) +/*! @} */ /*! @@ -15059,6 +16296,7 @@ typedef struct { */ /*! @name VERID - Version ID Register */ +/*! @{ */ #define LPUART_VERID_FEATURE_MASK (0xFFFFU) #define LPUART_VERID_FEATURE_SHIFT (0U) #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) @@ -15068,26 +16306,34 @@ typedef struct { #define LPUART_VERID_MAJOR_MASK (0xFF000000U) #define LPUART_VERID_MAJOR_SHIFT (24U) #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) +/*! @} */ /*! @name PARAM - Parameter Register */ +/*! @{ */ #define LPUART_PARAM_TXFIFO_MASK (0xFFU) #define LPUART_PARAM_TXFIFO_SHIFT (0U) #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) #define LPUART_PARAM_RXFIFO_MASK (0xFF00U) #define LPUART_PARAM_RXFIFO_SHIFT (8U) #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) +/*! @} */ /*! @name GLOBAL - LPUART Global Register */ +/*! @{ */ #define LPUART_GLOBAL_RST_MASK (0x2U) #define LPUART_GLOBAL_RST_SHIFT (1U) #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) +/*! @} */ /*! @name PINCFG - LPUART Pin Configuration Register */ +/*! @{ */ #define LPUART_PINCFG_TRGSEL_MASK (0x3U) #define LPUART_PINCFG_TRGSEL_SHIFT (0U) #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) +/*! @} */ /*! @name BAUD - LPUART Baud Rate Register */ +/*! @{ */ #define LPUART_BAUD_SBR_MASK (0x1FFFU) #define LPUART_BAUD_SBR_SHIFT (0U) #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) @@ -15109,6 +16355,9 @@ typedef struct { #define LPUART_BAUD_MATCFG_MASK (0xC0000U) #define LPUART_BAUD_MATCFG_SHIFT (18U) #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) +#define LPUART_BAUD_RIDMAE_MASK (0x100000U) +#define LPUART_BAUD_RIDMAE_SHIFT (20U) +#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) #define LPUART_BAUD_RDMAE_MASK (0x200000U) #define LPUART_BAUD_RDMAE_SHIFT (21U) #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) @@ -15127,8 +16376,10 @@ typedef struct { #define LPUART_BAUD_MAEN1_MASK (0x80000000U) #define LPUART_BAUD_MAEN1_SHIFT (31U) #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) +/*! @} */ /*! @name STAT - LPUART Status Register */ +/*! @{ */ #define LPUART_STAT_MA2F_MASK (0x4000U) #define LPUART_STAT_MA2F_SHIFT (14U) #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) @@ -15183,8 +16434,10 @@ typedef struct { #define LPUART_STAT_LBKDIF_MASK (0x80000000U) #define LPUART_STAT_LBKDIF_SHIFT (31U) #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) +/*! @} */ /*! @name CTRL - LPUART Control Register */ +/*! @{ */ #define LPUART_CTRL_PT_MASK (0x1U) #define LPUART_CTRL_PT_SHIFT (0U) #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) @@ -15269,8 +16522,10 @@ typedef struct { #define LPUART_CTRL_R8T9_MASK (0x80000000U) #define LPUART_CTRL_R8T9_SHIFT (31U) #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) +/*! @} */ /*! @name DATA - LPUART Data Register */ +/*! @{ */ #define LPUART_DATA_R0T0_MASK (0x1U) #define LPUART_DATA_R0T0_SHIFT (0U) #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) @@ -15316,16 +16571,20 @@ typedef struct { #define LPUART_DATA_NOISY_MASK (0x8000U) #define LPUART_DATA_NOISY_SHIFT (15U) #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) +/*! @} */ /*! @name MATCH - LPUART Match Address Register */ +/*! @{ */ #define LPUART_MATCH_MA1_MASK (0x3FFU) #define LPUART_MATCH_MA1_SHIFT (0U) #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) #define LPUART_MATCH_MA2_MASK (0x3FF0000U) #define LPUART_MATCH_MA2_SHIFT (16U) #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) +/*! @} */ /*! @name MODIR - LPUART Modem IrDA Register */ +/*! @{ */ #define LPUART_MODIR_TXCTSE_MASK (0x1U) #define LPUART_MODIR_TXCTSE_SHIFT (0U) #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) @@ -15353,8 +16612,10 @@ typedef struct { #define LPUART_MODIR_IREN_MASK (0x40000U) #define LPUART_MODIR_IREN_SHIFT (18U) #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) +/*! @} */ /*! @name FIFO - LPUART FIFO Register */ +/*! @{ */ #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) @@ -15394,8 +16655,10 @@ typedef struct { #define LPUART_FIFO_TXEMPT_MASK (0x800000U) #define LPUART_FIFO_TXEMPT_SHIFT (23U) #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) +/*! @} */ /*! @name WATER - LPUART Watermark Register */ +/*! @{ */ #define LPUART_WATER_TXWATER_MASK (0x3U) #define LPUART_WATER_TXWATER_SHIFT (0U) #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) @@ -15408,6 +16671,7 @@ typedef struct { #define LPUART_WATER_RXCOUNT_MASK (0x7000000U) #define LPUART_WATER_RXCOUNT_SHIFT (24U) #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) +/*! @} */ /*! @@ -15583,6 +16847,7 @@ typedef struct { */ /*! @name CTRL - OTP Controller Control Register */ +/*! @{ */ #define OCOTP_CTRL_ADDR_MASK (0x3FU) #define OCOTP_CTRL_ADDR_SHIFT (0U) #define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) @@ -15598,8 +16863,10 @@ typedef struct { #define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) #define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) #define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) +/*! @} */ /*! @name CTRL_SET - OTP Controller Control Register */ +/*! @{ */ #define OCOTP_CTRL_SET_ADDR_MASK (0x3FU) #define OCOTP_CTRL_SET_ADDR_SHIFT (0U) #define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) @@ -15615,8 +16882,10 @@ typedef struct { #define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) #define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) #define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) +/*! @} */ /*! @name CTRL_CLR - OTP Controller Control Register */ +/*! @{ */ #define OCOTP_CTRL_CLR_ADDR_MASK (0x3FU) #define OCOTP_CTRL_CLR_ADDR_SHIFT (0U) #define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) @@ -15632,8 +16901,10 @@ typedef struct { #define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) #define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) #define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) +/*! @} */ /*! @name CTRL_TOG - OTP Controller Control Register */ +/*! @{ */ #define OCOTP_CTRL_TOG_ADDR_MASK (0x3FU) #define OCOTP_CTRL_TOG_ADDR_SHIFT (0U) #define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) @@ -15649,8 +16920,10 @@ typedef struct { #define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) #define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) #define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) +/*! @} */ /*! @name TIMING - OTP Controller Timing Register */ +/*! @{ */ #define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU) #define OCOTP_TIMING_STROBE_PROG_SHIFT (0U) #define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK) @@ -15663,23 +16936,31 @@ typedef struct { #define OCOTP_TIMING_WAIT_MASK (0xFC00000U) #define OCOTP_TIMING_WAIT_SHIFT (22U) #define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK) +/*! @} */ /*! @name DATA - OTP Controller Write Data Register */ +/*! @{ */ #define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) #define OCOTP_DATA_DATA_SHIFT (0U) #define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) +/*! @} */ /*! @name READ_CTRL - OTP Controller Write Data Register */ +/*! @{ */ #define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) #define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) #define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) +/*! @} */ /*! @name READ_FUSE_DATA - OTP Controller Read Data Register */ +/*! @{ */ #define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) #define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) #define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) +/*! @} */ /*! @name SW_STICKY - Sticky bit Register */ +/*! @{ */ #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U) #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U) #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK) @@ -15695,8 +16976,10 @@ typedef struct { #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U) #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U) #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK) +/*! @} */ /*! @name SCS - Software Controllable Signals Register */ +/*! @{ */ #define OCOTP_SCS_HAB_JDE_MASK (0x1U) #define OCOTP_SCS_HAB_JDE_SHIFT (0U) #define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK) @@ -15706,8 +16989,10 @@ typedef struct { #define OCOTP_SCS_LOCK_MASK (0x80000000U) #define OCOTP_SCS_LOCK_SHIFT (31U) #define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK) +/*! @} */ /*! @name SCS_SET - Software Controllable Signals Register */ +/*! @{ */ #define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U) #define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U) #define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK) @@ -15717,8 +17002,10 @@ typedef struct { #define OCOTP_SCS_SET_LOCK_MASK (0x80000000U) #define OCOTP_SCS_SET_LOCK_SHIFT (31U) #define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK) +/*! @} */ /*! @name SCS_CLR - Software Controllable Signals Register */ +/*! @{ */ #define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U) #define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U) #define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK) @@ -15728,8 +17015,10 @@ typedef struct { #define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U) #define OCOTP_SCS_CLR_LOCK_SHIFT (31U) #define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK) +/*! @} */ /*! @name SCS_TOG - Software Controllable Signals Register */ +/*! @{ */ #define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U) #define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U) #define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK) @@ -15739,8 +17028,10 @@ typedef struct { #define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U) #define OCOTP_SCS_TOG_LOCK_SHIFT (31U) #define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK) +/*! @} */ /*! @name VERSION - OTP Controller Version Register */ +/*! @{ */ #define OCOTP_VERSION_STEP_MASK (0xFFFFU) #define OCOTP_VERSION_STEP_SHIFT (0U) #define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) @@ -15750,8 +17041,10 @@ typedef struct { #define OCOTP_VERSION_MAJOR_MASK (0xFF000000U) #define OCOTP_VERSION_MAJOR_SHIFT (24U) #define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) +/*! @} */ /*! @name TIMING2 - OTP Controller Timing Register 2 */ +/*! @{ */ #define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU) #define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U) #define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK) @@ -15761,8 +17054,10 @@ typedef struct { #define OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U) #define OCOTP_TIMING2_RELAX1_SHIFT (22U) #define OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK) +/*! @} */ /*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */ +/*! @{ */ #define OCOTP_LOCK_TESTER_MASK (0x3U) #define OCOTP_LOCK_TESTER_SHIFT (0U) #define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK) @@ -15817,196 +17112,273 @@ typedef struct { #define OCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U) #define OCOTP_LOCK_FIELD_RETURN_SHIFT (28U) #define OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK) +/*! @} */ /*! @name CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG0_BITS_SHIFT (0U) #define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK) +/*! @} */ /*! @name CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG1_BITS_SHIFT (0U) #define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK) +/*! @} */ /*! @name CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG2_BITS_SHIFT (0U) #define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK) +/*! @} */ /*! @name CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG3_BITS_SHIFT (0U) #define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK) +/*! @} */ /*! @name CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG4_BITS_SHIFT (0U) #define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK) +/*! @} */ /*! @name CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG5_BITS_SHIFT (0U) #define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK) +/*! @} */ /*! @name CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG6_BITS_SHIFT (0U) #define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK) +/*! @} */ /*! @name MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) */ +/*! @{ */ #define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MEM0_BITS_SHIFT (0U) #define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK) +/*! @} */ /*! @name MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) */ +/*! @{ */ #define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MEM1_BITS_SHIFT (0U) #define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK) +/*! @} */ /*! @name MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) */ +/*! @{ */ #define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MEM2_BITS_SHIFT (0U) #define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK) +/*! @} */ /*! @name MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) */ +/*! @{ */ #define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MEM3_BITS_SHIFT (0U) #define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK) +/*! @} */ /*! @name MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) */ +/*! @{ */ #define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MEM4_BITS_SHIFT (0U) #define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK) +/*! @} */ /*! @name ANA0 - Value of OTP Bank1 Word5 (Analog Info.) */ +/*! @{ */ #define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_ANA0_BITS_SHIFT (0U) #define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK) +/*! @} */ /*! @name ANA1 - Value of OTP Bank1 Word6 (Analog Info.) */ +/*! @{ */ #define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_ANA1_BITS_SHIFT (0U) #define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK) +/*! @} */ /*! @name ANA2 - Value of OTP Bank1 Word7 (Analog Info.) */ +/*! @{ */ #define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_ANA2_BITS_SHIFT (0U) #define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK) +/*! @} */ /*! @name SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK0_BITS_SHIFT (0U) #define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK) +/*! @} */ /*! @name SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK1_BITS_SHIFT (0U) #define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK) +/*! @} */ /*! @name SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK2_BITS_SHIFT (0U) #define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK) +/*! @} */ /*! @name SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK3_BITS_SHIFT (0U) #define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK) +/*! @} */ /*! @name SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK4_BITS_SHIFT (0U) #define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK) +/*! @} */ /*! @name SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK5_BITS_SHIFT (0U) #define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK) +/*! @} */ /*! @name SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK6_BITS_SHIFT (0U) #define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK) +/*! @} */ /*! @name SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK7_BITS_SHIFT (0U) #define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK) +/*! @} */ /*! @name SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) */ +/*! @{ */ #define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SJC_RESP0_BITS_SHIFT (0U) #define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK) +/*! @} */ /*! @name SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) */ +/*! @{ */ #define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SJC_RESP1_BITS_SHIFT (0U) #define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK) +/*! @} */ /*! @name MAC0 - Value of OTP Bank4 Word2 (MAC Address) */ +/*! @{ */ #define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MAC0_BITS_SHIFT (0U) #define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK) +/*! @} */ /*! @name MAC1 - Value of OTP Bank4 Word3 (MAC Address) */ +/*! @{ */ #define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MAC1_BITS_SHIFT (0U) #define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK) +/*! @} */ /*! @name GP3 - Value of OTP Bank4 Word4 (MAC Address) */ +/*! @{ */ #define OCOTP_GP3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_GP3_BITS_SHIFT (0U) #define OCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK) +/*! @} */ /*! @name GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) */ +/*! @{ */ #define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_GP1_BITS_SHIFT (0U) #define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK) +/*! @} */ /*! @name GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) */ +/*! @{ */ #define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_GP2_BITS_SHIFT (0U) #define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK) +/*! @} */ /*! @name SW_GP1 - Value of OTP Bank5 Word0 (SW GP1) */ +/*! @{ */ #define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SW_GP1_BITS_SHIFT (0U) #define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK) +/*! @} */ /*! @name SW_GP20 - Value of OTP Bank5 Word1 (SW GP2) */ +/*! @{ */ #define OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SW_GP20_BITS_SHIFT (0U) #define OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK) +/*! @} */ /*! @name SW_GP21 - Value of OTP Bank5 Word2 (SW GP2) */ +/*! @{ */ #define OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SW_GP21_BITS_SHIFT (0U) #define OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK) +/*! @} */ /*! @name SW_GP22 - Value of OTP Bank5 Word3 (SW GP2) */ +/*! @{ */ #define OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SW_GP22_BITS_SHIFT (0U) #define OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK) +/*! @} */ /*! @name SW_GP23 - Value of OTP Bank5 Word4 (SW GP2) */ +/*! @{ */ #define OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SW_GP23_BITS_SHIFT (0U) #define OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK) +/*! @} */ /*! @name MISC_CONF0 - Value of OTP Bank5 Word5 (Misc Conf) */ +/*! @{ */ #define OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MISC_CONF0_BITS_SHIFT (0U) #define OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK) +/*! @} */ /*! @name MISC_CONF1 - Value of OTP Bank5 Word6 (Misc Conf) */ +/*! @{ */ #define OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MISC_CONF1_BITS_SHIFT (0U) #define OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK) +/*! @} */ /*! @name SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke) */ +/*! @{ */ #define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK_REVOKE_BITS_SHIFT (0U) #define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK) +/*! @} */ /*! @@ -16062,56 +17434,72 @@ typedef struct { */ /*! @name MEGA_CTRL - PGC Mega Control Register */ +/*! @{ */ #define PGC_MEGA_CTRL_PCR_MASK (0x1U) #define PGC_MEGA_CTRL_PCR_SHIFT (0U) #define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK) +/*! @} */ /*! @name MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register */ +/*! @{ */ #define PGC_MEGA_PUPSCR_SW_MASK (0x3FU) #define PGC_MEGA_PUPSCR_SW_SHIFT (0U) #define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK) #define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U) #define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U) #define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK) +/*! @} */ /*! @name MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register */ +/*! @{ */ #define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU) #define PGC_MEGA_PDNSCR_ISO_SHIFT (0U) #define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK) #define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U) #define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U) #define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK) +/*! @} */ /*! @name MEGA_SR - PGC Mega Power Gating Controller Status Register */ +/*! @{ */ #define PGC_MEGA_SR_PSR_MASK (0x1U) #define PGC_MEGA_SR_PSR_SHIFT (0U) #define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK) +/*! @} */ /*! @name CPU_CTRL - PGC CPU Control Register */ +/*! @{ */ #define PGC_CPU_CTRL_PCR_MASK (0x1U) #define PGC_CPU_CTRL_PCR_SHIFT (0U) #define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK) +/*! @} */ /*! @name CPU_PUPSCR - PGC CPU Power Up Sequence Control Register */ +/*! @{ */ #define PGC_CPU_PUPSCR_SW_MASK (0x3FU) #define PGC_CPU_PUPSCR_SW_SHIFT (0U) #define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK) #define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) #define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U) #define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK) +/*! @} */ /*! @name CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register */ +/*! @{ */ #define PGC_CPU_PDNSCR_ISO_MASK (0x3FU) #define PGC_CPU_PDNSCR_ISO_SHIFT (0U) #define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK) #define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) #define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U) #define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK) +/*! @} */ /*! @name CPU_SR - PGC CPU Power Gating Controller Status Register */ +/*! @{ */ #define PGC_CPU_SR_PSR_MASK (0x1U) #define PGC_CPU_SR_PSR_SHIFT (0U) #define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK) +/*! @} */ /*! @@ -16168,40 +17556,51 @@ typedef struct { */ /*! @name MCR - PIT Module Control Register */ +/*! @{ */ #define PIT_MCR_FRZ_MASK (0x1U) #define PIT_MCR_FRZ_SHIFT (0U) #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) #define PIT_MCR_MDIS_MASK (0x2U) #define PIT_MCR_MDIS_SHIFT (1U) #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) +/*! @} */ /*! @name LTMR64H - PIT Upper Lifetime Timer Register */ +/*! @{ */ #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) #define PIT_LTMR64H_LTH_SHIFT (0U) #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) +/*! @} */ /*! @name LTMR64L - PIT Lower Lifetime Timer Register */ +/*! @{ */ #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) #define PIT_LTMR64L_LTL_SHIFT (0U) #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) +/*! @} */ /*! @name LDVAL - Timer Load Value Register */ +/*! @{ */ #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) #define PIT_LDVAL_TSV_SHIFT (0U) #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) +/*! @} */ /* The count of PIT_LDVAL */ #define PIT_LDVAL_COUNT (4U) /*! @name CVAL - Current Timer Value Register */ +/*! @{ */ #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) #define PIT_CVAL_TVL_SHIFT (0U) #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) +/*! @} */ /* The count of PIT_CVAL */ #define PIT_CVAL_COUNT (4U) /*! @name TCTRL - Timer Control Register */ +/*! @{ */ #define PIT_TCTRL_TEN_MASK (0x1U) #define PIT_TCTRL_TEN_SHIFT (0U) #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) @@ -16211,14 +17610,17 @@ typedef struct { #define PIT_TCTRL_CHN_MASK (0x4U) #define PIT_TCTRL_CHN_SHIFT (2U) #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) +/*! @} */ /* The count of PIT_TCTRL */ #define PIT_TCTRL_COUNT (4U) /*! @name TFLG - Timer Flag Register */ +/*! @{ */ #define PIT_TFLG_TIF_MASK (0x1U) #define PIT_TFLG_TIF_SHIFT (0U) #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) +/*! @} */ /* The count of PIT_TFLG */ #define PIT_TFLG_COUNT (4U) @@ -16298,6 +17700,7 @@ typedef struct { */ /*! @name REG_1P1 - Regulator 1P1 Register */ +/*! @{ */ #define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK) @@ -16328,8 +17731,10 @@ typedef struct { #define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U) #define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U) #define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_1P1_SET - Regulator 1P1 Register */ +/*! @{ */ #define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK) @@ -16360,8 +17765,10 @@ typedef struct { #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U) #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U) #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_1P1_CLR - Regulator 1P1 Register */ +/*! @{ */ #define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK) @@ -16392,8 +17799,10 @@ typedef struct { #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U) #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U) #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_1P1_TOG - Regulator 1P1 Register */ +/*! @{ */ #define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK) @@ -16424,8 +17833,10 @@ typedef struct { #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U) #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U) #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_3P0 - Regulator 3P0 Register */ +/*! @{ */ #define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK) @@ -16450,8 +17861,10 @@ typedef struct { #define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U) #define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U) #define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK) +/*! @} */ /*! @name REG_3P0_SET - Regulator 3P0 Register */ +/*! @{ */ #define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK) @@ -16476,8 +17889,10 @@ typedef struct { #define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U) #define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U) #define PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK) +/*! @} */ /*! @name REG_3P0_CLR - Regulator 3P0 Register */ +/*! @{ */ #define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK) @@ -16502,8 +17917,10 @@ typedef struct { #define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U) #define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U) #define PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK) +/*! @} */ /*! @name REG_3P0_TOG - Regulator 3P0 Register */ +/*! @{ */ #define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK) @@ -16528,8 +17945,10 @@ typedef struct { #define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U) #define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U) #define PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK) +/*! @} */ /*! @name REG_2P5 - Regulator 2P5 Register */ +/*! @{ */ #define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK) @@ -16557,8 +17976,10 @@ typedef struct { #define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U) #define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U) #define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_2P5_SET - Regulator 2P5 Register */ +/*! @{ */ #define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK) @@ -16586,8 +18007,10 @@ typedef struct { #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U) #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U) #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_2P5_CLR - Regulator 2P5 Register */ +/*! @{ */ #define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK) @@ -16615,8 +18038,10 @@ typedef struct { #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U) #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U) #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_2P5_TOG - Regulator 2P5 Register */ +/*! @{ */ #define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK) @@ -16644,64 +18069,122 @@ typedef struct { #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U) #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U) #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_CORE - Digital Regulator Core Register */ +/*! @{ */ #define PMU_REG_CORE_REG0_TARG_MASK (0x1FU) #define PMU_REG_CORE_REG0_TARG_SHIFT (0U) #define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK) +#define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_REG0_ADJ_SHIFT (5U) +#define PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK) +#define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_REG1_TARG_SHIFT (9U) +#define PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK) +#define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_REG1_ADJ_SHIFT (14U) +#define PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK) #define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U) #define PMU_REG_CORE_REG2_TARG_SHIFT (18U) #define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK) +#define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_REG2_ADJ_SHIFT (23U) +#define PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK) #define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U) #define PMU_REG_CORE_RAMP_RATE_SHIFT (27U) #define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK) #define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U) #define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U) #define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK) +/*! @} */ /*! @name REG_CORE_SET - Digital Regulator Core Register */ +/*! @{ */ #define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU) #define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U) #define PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK) +#define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U) +#define PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK) +#define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U) +#define PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK) +#define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U) +#define PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK) #define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U) #define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U) #define PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK) +#define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U) +#define PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK) #define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U) #define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U) #define PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK) #define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U) #define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U) #define PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK) +/*! @} */ /*! @name REG_CORE_CLR - Digital Regulator Core Register */ +/*! @{ */ #define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU) #define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U) #define PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK) +#define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U) +#define PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK) +#define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U) +#define PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK) +#define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U) +#define PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK) #define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U) #define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U) #define PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK) +#define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U) +#define PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK) #define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U) #define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U) #define PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK) #define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U) #define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U) #define PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK) +/*! @} */ /*! @name REG_CORE_TOG - Digital Regulator Core Register */ +/*! @{ */ #define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU) #define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U) #define PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK) +#define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U) +#define PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK) +#define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U) +#define PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK) +#define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U) +#define PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK) #define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U) #define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U) #define PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK) +#define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U) +#define PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK) #define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U) #define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U) #define PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK) #define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U) #define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U) #define PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK) +/*! @} */ /*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ #define PMU_MISC0_REFTOP_PWD_MASK (0x1U) #define PMU_MISC0_REFTOP_PWD_SHIFT (0U) #define PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK) @@ -16744,8 +18227,10 @@ typedef struct { #define PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) #define PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U) #define PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ #define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U) #define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U) #define PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK) @@ -16788,8 +18273,10 @@ typedef struct { #define PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) #define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) #define PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ #define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U) #define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U) #define PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK) @@ -16832,8 +18319,10 @@ typedef struct { #define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) #define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) #define PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ #define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U) #define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U) #define PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK) @@ -16876,17 +18365,28 @@ typedef struct { #define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) #define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) #define PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC1 - Miscellaneous Register 1 */ +/*! @{ */ #define PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) #define PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U) #define PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U) +#define PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK) #define PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U) #define PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U) #define PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK) #define PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U) #define PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U) #define PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK) #define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) #define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) #define PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK) @@ -16908,17 +18408,28 @@ typedef struct { #define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U) #define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U) #define PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_SET - Miscellaneous Register 1 */ +/*! @{ */ #define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) #define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) #define PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U) +#define PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK) #define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) #define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) #define PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK) #define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U) #define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U) #define PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK) #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) @@ -16940,17 +18451,28 @@ typedef struct { #define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) #define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) #define PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_CLR - Miscellaneous Register 1 */ +/*! @{ */ #define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) #define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) #define PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U) +#define PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK) #define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) #define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) #define PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK) #define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U) #define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U) #define PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK) #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) @@ -16972,17 +18494,28 @@ typedef struct { #define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) #define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) #define PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_TOG - Miscellaneous Register 1 */ +/*! @{ */ #define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) #define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) #define PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U) +#define PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK) #define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) #define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) #define PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK) #define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U) #define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U) #define PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK) #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) @@ -17004,8 +18537,10 @@ typedef struct { #define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) #define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) #define PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC2 - Miscellaneous Control Register */ +/*! @{ */ #define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U) #define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U) #define PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK) @@ -17018,6 +18553,15 @@ typedef struct { #define PMU_MISC2_PLL3_disable_MASK (0x80U) #define PMU_MISC2_PLL3_disable_SHIFT (7U) #define PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK) +#define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U) +#define PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U) +#define PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK) +#define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK) #define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) #define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U) #define PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK) @@ -17039,14 +18583,19 @@ typedef struct { #define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U) #define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U) #define PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK) +#define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U) +#define PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK) #define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U) #define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U) #define PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK) #define PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U) #define PMU_MISC2_VIDEO_DIV_SHIFT (30U) #define PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_SET - Miscellaneous Control Register */ +/*! @{ */ #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) #define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) #define PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK) @@ -17059,6 +18608,15 @@ typedef struct { #define PMU_MISC2_SET_PLL3_disable_MASK (0x80U) #define PMU_MISC2_SET_PLL3_disable_SHIFT (7U) #define PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK) +#define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +#define PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +#define PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK) #define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) #define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) #define PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK) @@ -17080,14 +18638,19 @@ typedef struct { #define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) #define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) #define PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK) +#define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +#define PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK) #define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) #define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) #define PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK) #define PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) #define PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U) #define PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_CLR - Miscellaneous Control Register */ +/*! @{ */ #define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) #define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) #define PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK) @@ -17100,6 +18663,15 @@ typedef struct { #define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U) #define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U) #define PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK) +#define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +#define PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +#define PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK) #define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) #define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) #define PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK) @@ -17121,14 +18693,19 @@ typedef struct { #define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) #define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) #define PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK) +#define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +#define PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK) #define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) #define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) #define PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK) #define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) #define PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U) #define PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_TOG - Miscellaneous Control Register */ +/*! @{ */ #define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) #define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) #define PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK) @@ -17141,6 +18718,15 @@ typedef struct { #define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U) #define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U) #define PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK) +#define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +#define PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +#define PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK) #define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) #define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) #define PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK) @@ -17162,12 +18748,16 @@ typedef struct { #define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) #define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) #define PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK) +#define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +#define PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK) #define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) #define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) #define PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK) #define PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) #define PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U) #define PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK) +/*! @} */ /*! @@ -17270,22 +18860,27 @@ typedef struct { */ /*! @name CNT - Counter Register */ +/*! @{ */ #define PWM_CNT_CNT_MASK (0xFFFFU) #define PWM_CNT_CNT_SHIFT (0U) #define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) +/*! @} */ /* The count of PWM_CNT */ #define PWM_CNT_COUNT (4U) /*! @name INIT - Initial Count Register */ +/*! @{ */ #define PWM_INIT_INIT_MASK (0xFFFFU) #define PWM_INIT_INIT_SHIFT (0U) #define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) +/*! @} */ /* The count of PWM_INIT */ #define PWM_INIT_COUNT (4U) /*! @name CTRL2 - Control 2 Register */ +/*! @{ */ #define PWM_CTRL2_CLK_SEL_MASK (0x3U) #define PWM_CTRL2_CLK_SEL_SHIFT (0U) #define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) @@ -17322,11 +18917,13 @@ typedef struct { #define PWM_CTRL2_DBGEN_MASK (0x8000U) #define PWM_CTRL2_DBGEN_SHIFT (15U) #define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) +/*! @} */ /* The count of PWM_CTRL2 */ #define PWM_CTRL2_COUNT (4U) /*! @name CTRL - Control Register */ +/*! @{ */ #define PWM_CTRL_DBLEN_MASK (0x1U) #define PWM_CTRL_DBLEN_SHIFT (0U) #define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) @@ -17357,99 +18954,123 @@ typedef struct { #define PWM_CTRL_LDFQ_MASK (0xF000U) #define PWM_CTRL_LDFQ_SHIFT (12U) #define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) +/*! @} */ /* The count of PWM_CTRL */ #define PWM_CTRL_COUNT (4U) /*! @name VAL0 - Value Register 0 */ +/*! @{ */ #define PWM_VAL0_VAL0_MASK (0xFFFFU) #define PWM_VAL0_VAL0_SHIFT (0U) #define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) +/*! @} */ /* The count of PWM_VAL0 */ #define PWM_VAL0_COUNT (4U) /*! @name FRACVAL1 - Fractional Value Register 1 */ +/*! @{ */ #define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U) #define PWM_FRACVAL1_FRACVAL1_SHIFT (11U) #define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK) +/*! @} */ /* The count of PWM_FRACVAL1 */ #define PWM_FRACVAL1_COUNT (4U) /*! @name VAL1 - Value Register 1 */ +/*! @{ */ #define PWM_VAL1_VAL1_MASK (0xFFFFU) #define PWM_VAL1_VAL1_SHIFT (0U) #define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) +/*! @} */ /* The count of PWM_VAL1 */ #define PWM_VAL1_COUNT (4U) /*! @name FRACVAL2 - Fractional Value Register 2 */ +/*! @{ */ #define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U) #define PWM_FRACVAL2_FRACVAL2_SHIFT (11U) #define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK) +/*! @} */ /* The count of PWM_FRACVAL2 */ #define PWM_FRACVAL2_COUNT (4U) /*! @name VAL2 - Value Register 2 */ +/*! @{ */ #define PWM_VAL2_VAL2_MASK (0xFFFFU) #define PWM_VAL2_VAL2_SHIFT (0U) #define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) +/*! @} */ /* The count of PWM_VAL2 */ #define PWM_VAL2_COUNT (4U) /*! @name FRACVAL3 - Fractional Value Register 3 */ +/*! @{ */ #define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U) #define PWM_FRACVAL3_FRACVAL3_SHIFT (11U) #define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK) +/*! @} */ /* The count of PWM_FRACVAL3 */ #define PWM_FRACVAL3_COUNT (4U) /*! @name VAL3 - Value Register 3 */ +/*! @{ */ #define PWM_VAL3_VAL3_MASK (0xFFFFU) #define PWM_VAL3_VAL3_SHIFT (0U) #define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) +/*! @} */ /* The count of PWM_VAL3 */ #define PWM_VAL3_COUNT (4U) /*! @name FRACVAL4 - Fractional Value Register 4 */ +/*! @{ */ #define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U) #define PWM_FRACVAL4_FRACVAL4_SHIFT (11U) #define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK) +/*! @} */ /* The count of PWM_FRACVAL4 */ #define PWM_FRACVAL4_COUNT (4U) /*! @name VAL4 - Value Register 4 */ +/*! @{ */ #define PWM_VAL4_VAL4_MASK (0xFFFFU) #define PWM_VAL4_VAL4_SHIFT (0U) #define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) +/*! @} */ /* The count of PWM_VAL4 */ #define PWM_VAL4_COUNT (4U) /*! @name FRACVAL5 - Fractional Value Register 5 */ +/*! @{ */ #define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U) #define PWM_FRACVAL5_FRACVAL5_SHIFT (11U) #define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK) +/*! @} */ /* The count of PWM_FRACVAL5 */ #define PWM_FRACVAL5_COUNT (4U) /*! @name VAL5 - Value Register 5 */ +/*! @{ */ #define PWM_VAL5_VAL5_MASK (0xFFFFU) #define PWM_VAL5_VAL5_SHIFT (0U) #define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) +/*! @} */ /* The count of PWM_VAL5 */ #define PWM_VAL5_COUNT (4U) /*! @name FRCTRL - Fractional Control Register */ +/*! @{ */ #define PWM_FRCTRL_FRAC1_EN_MASK (0x2U) #define PWM_FRCTRL_FRAC1_EN_SHIFT (1U) #define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK) @@ -17465,11 +19086,13 @@ typedef struct { #define PWM_FRCTRL_TEST_MASK (0x8000U) #define PWM_FRCTRL_TEST_SHIFT (15U) #define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK) +/*! @} */ /* The count of PWM_FRCTRL */ #define PWM_FRCTRL_COUNT (4U) /*! @name OCTRL - Output Control Register */ +/*! @{ */ #define PWM_OCTRL_PWMXFS_MASK (0x3U) #define PWM_OCTRL_PWMXFS_SHIFT (0U) #define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) @@ -17497,11 +19120,13 @@ typedef struct { #define PWM_OCTRL_PWMA_IN_MASK (0x8000U) #define PWM_OCTRL_PWMA_IN_SHIFT (15U) #define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) +/*! @} */ /* The count of PWM_OCTRL */ #define PWM_OCTRL_COUNT (4U) /*! @name STS - Status Register */ +/*! @{ */ #define PWM_STS_CMPF_MASK (0x3FU) #define PWM_STS_CMPF_SHIFT (0U) #define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) @@ -17532,11 +19157,13 @@ typedef struct { #define PWM_STS_RUF_MASK (0x4000U) #define PWM_STS_RUF_SHIFT (14U) #define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) +/*! @} */ /* The count of PWM_STS */ #define PWM_STS_COUNT (4U) /*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ #define PWM_INTEN_CMPIE_MASK (0x3FU) #define PWM_INTEN_CMPIE_SHIFT (0U) #define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) @@ -17564,11 +19191,13 @@ typedef struct { #define PWM_INTEN_REIE_MASK (0x2000U) #define PWM_INTEN_REIE_SHIFT (13U) #define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) +/*! @} */ /* The count of PWM_INTEN */ #define PWM_INTEN_COUNT (4U) /*! @name DMAEN - DMA Enable Register */ +/*! @{ */ #define PWM_DMAEN_CX0DE_MASK (0x1U) #define PWM_DMAEN_CX0DE_SHIFT (0U) #define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) @@ -17596,11 +19225,13 @@ typedef struct { #define PWM_DMAEN_VALDE_MASK (0x200U) #define PWM_DMAEN_VALDE_SHIFT (9U) #define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) +/*! @} */ /* The count of PWM_DMAEN */ #define PWM_DMAEN_COUNT (4U) /*! @name TCTRL - Output Trigger Control Register */ +/*! @{ */ #define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) #define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) #define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) @@ -17613,11 +19244,13 @@ typedef struct { #define PWM_TCTRL_PWAOT0_MASK (0x8000U) #define PWM_TCTRL_PWAOT0_SHIFT (15U) #define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) +/*! @} */ /* The count of PWM_TCTRL */ #define PWM_TCTRL_COUNT (4U) /*! @name DISMAP - Fault Disable Mapping Register 0..Fault Disable Mapping Register 1 */ +/*! @{ */ #define PWM_DISMAP_DIS0A_MASK (0xFU) #define PWM_DISMAP_DIS0A_SHIFT (0U) #define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) @@ -17630,12 +19263,13 @@ typedef struct { #define PWM_DISMAP_DIS1B_MASK (0xF0U) #define PWM_DISMAP_DIS1B_SHIFT (4U) #define PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK) -#define PWM_DISMAP_DIS1X_MASK (0xF00U) -#define PWM_DISMAP_DIS1X_SHIFT (8U) -#define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK) #define PWM_DISMAP_DIS0X_MASK (0xF00U) #define PWM_DISMAP_DIS0X_SHIFT (8U) #define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) +#define PWM_DISMAP_DIS1X_MASK (0xF00U) +#define PWM_DISMAP_DIS1X_SHIFT (8U) +#define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK) +/*! @} */ /* The count of PWM_DISMAP */ #define PWM_DISMAP_COUNT (4U) @@ -17644,22 +19278,27 @@ typedef struct { #define PWM_DISMAP_COUNT2 (2U) /*! @name DTCNT0 - Deadtime Count Register 0 */ +/*! @{ */ #define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU) #define PWM_DTCNT0_DTCNT0_SHIFT (0U) #define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) +/*! @} */ /* The count of PWM_DTCNT0 */ #define PWM_DTCNT0_COUNT (4U) /*! @name DTCNT1 - Deadtime Count Register 1 */ +/*! @{ */ #define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU) #define PWM_DTCNT1_DTCNT1_SHIFT (0U) #define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) +/*! @} */ /* The count of PWM_DTCNT1 */ #define PWM_DTCNT1_COUNT (4U) /*! @name CAPTCTRLA - Capture Control A Register */ +/*! @{ */ #define PWM_CAPTCTRLA_ARMA_MASK (0x1U) #define PWM_CAPTCTRLA_ARMA_SHIFT (0U) #define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) @@ -17687,22 +19326,26 @@ typedef struct { #define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U) #define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U) #define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK) +/*! @} */ /* The count of PWM_CAPTCTRLA */ #define PWM_CAPTCTRLA_COUNT (4U) /*! @name CAPTCOMPA - Capture Compare A Register */ +/*! @{ */ #define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU) #define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U) #define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK) #define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U) #define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U) #define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK) +/*! @} */ /* The count of PWM_CAPTCOMPA */ #define PWM_CAPTCOMPA_COUNT (4U) /*! @name CAPTCTRLB - Capture Control B Register */ +/*! @{ */ #define PWM_CAPTCTRLB_ARMB_MASK (0x1U) #define PWM_CAPTCTRLB_ARMB_SHIFT (0U) #define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) @@ -17730,22 +19373,26 @@ typedef struct { #define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U) #define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U) #define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK) +/*! @} */ /* The count of PWM_CAPTCTRLB */ #define PWM_CAPTCTRLB_COUNT (4U) /*! @name CAPTCOMPB - Capture Compare B Register */ +/*! @{ */ #define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU) #define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U) #define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK) #define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U) #define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U) #define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK) +/*! @} */ /* The count of PWM_CAPTCOMPB */ #define PWM_CAPTCOMPB_COUNT (4U) /*! @name CAPTCTRLX - Capture Control X Register */ +/*! @{ */ #define PWM_CAPTCTRLX_ARMX_MASK (0x1U) #define PWM_CAPTCTRLX_ARMX_SHIFT (0U) #define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) @@ -17773,118 +19420,146 @@ typedef struct { #define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) #define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) #define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) +/*! @} */ /* The count of PWM_CAPTCTRLX */ #define PWM_CAPTCTRLX_COUNT (4U) /*! @name CAPTCOMPX - Capture Compare X Register */ +/*! @{ */ #define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) #define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) #define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) #define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) #define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) #define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) +/*! @} */ /* The count of PWM_CAPTCOMPX */ #define PWM_CAPTCOMPX_COUNT (4U) /*! @name CVAL0 - Capture Value 0 Register */ +/*! @{ */ #define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) #define PWM_CVAL0_CAPTVAL0_SHIFT (0U) #define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) +/*! @} */ /* The count of PWM_CVAL0 */ #define PWM_CVAL0_COUNT (4U) /*! @name CVAL0CYC - Capture Value 0 Cycle Register */ +/*! @{ */ #define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) #define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) #define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) +/*! @} */ /* The count of PWM_CVAL0CYC */ #define PWM_CVAL0CYC_COUNT (4U) /*! @name CVAL1 - Capture Value 1 Register */ +/*! @{ */ #define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) #define PWM_CVAL1_CAPTVAL1_SHIFT (0U) #define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) +/*! @} */ /* The count of PWM_CVAL1 */ #define PWM_CVAL1_COUNT (4U) /*! @name CVAL1CYC - Capture Value 1 Cycle Register */ +/*! @{ */ #define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) #define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) #define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) +/*! @} */ /* The count of PWM_CVAL1CYC */ #define PWM_CVAL1CYC_COUNT (4U) /*! @name CVAL2 - Capture Value 2 Register */ +/*! @{ */ #define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU) #define PWM_CVAL2_CAPTVAL2_SHIFT (0U) #define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK) +/*! @} */ /* The count of PWM_CVAL2 */ #define PWM_CVAL2_COUNT (4U) /*! @name CVAL2CYC - Capture Value 2 Cycle Register */ +/*! @{ */ #define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU) #define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U) #define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK) +/*! @} */ /* The count of PWM_CVAL2CYC */ #define PWM_CVAL2CYC_COUNT (4U) /*! @name CVAL3 - Capture Value 3 Register */ +/*! @{ */ #define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU) #define PWM_CVAL3_CAPTVAL3_SHIFT (0U) #define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK) +/*! @} */ /* The count of PWM_CVAL3 */ #define PWM_CVAL3_COUNT (4U) /*! @name CVAL3CYC - Capture Value 3 Cycle Register */ +/*! @{ */ #define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU) #define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U) #define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK) +/*! @} */ /* The count of PWM_CVAL3CYC */ #define PWM_CVAL3CYC_COUNT (4U) /*! @name CVAL4 - Capture Value 4 Register */ +/*! @{ */ #define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU) #define PWM_CVAL4_CAPTVAL4_SHIFT (0U) #define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK) +/*! @} */ /* The count of PWM_CVAL4 */ #define PWM_CVAL4_COUNT (4U) /*! @name CVAL4CYC - Capture Value 4 Cycle Register */ +/*! @{ */ #define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU) #define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U) #define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK) +/*! @} */ /* The count of PWM_CVAL4CYC */ #define PWM_CVAL4CYC_COUNT (4U) /*! @name CVAL5 - Capture Value 5 Register */ +/*! @{ */ #define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU) #define PWM_CVAL5_CAPTVAL5_SHIFT (0U) #define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK) +/*! @} */ /* The count of PWM_CVAL5 */ #define PWM_CVAL5_COUNT (4U) /*! @name CVAL5CYC - Capture Value 5 Cycle Register */ +/*! @{ */ #define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU) #define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U) #define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK) +/*! @} */ /* The count of PWM_CVAL5CYC */ #define PWM_CVAL5CYC_COUNT (4U) /*! @name OUTEN - Output Enable Register */ +/*! @{ */ #define PWM_OUTEN_PWMX_EN_MASK (0xFU) #define PWM_OUTEN_PWMX_EN_SHIFT (0U) #define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) @@ -17894,8 +19569,10 @@ typedef struct { #define PWM_OUTEN_PWMA_EN_MASK (0xF00U) #define PWM_OUTEN_PWMA_EN_SHIFT (8U) #define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) +/*! @} */ /*! @name MASK - Mask Register */ +/*! @{ */ #define PWM_MASK_MASKX_MASK (0xFU) #define PWM_MASK_MASKX_SHIFT (0U) #define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) @@ -17908,8 +19585,10 @@ typedef struct { #define PWM_MASK_UPDATE_MASK_MASK (0xF000U) #define PWM_MASK_UPDATE_MASK_SHIFT (12U) #define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) +/*! @} */ /*! @name SWCOUT - Software Controlled Output Register */ +/*! @{ */ #define PWM_SWCOUT_SM0OUT45_MASK (0x1U) #define PWM_SWCOUT_SM0OUT45_SHIFT (0U) #define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) @@ -17934,8 +19613,10 @@ typedef struct { #define PWM_SWCOUT_SM3OUT23_MASK (0x80U) #define PWM_SWCOUT_SM3OUT23_SHIFT (7U) #define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) +/*! @} */ /*! @name DTSRCSEL - PWM Source Select Register */ +/*! @{ */ #define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) #define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) #define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) @@ -17960,8 +19641,10 @@ typedef struct { #define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) #define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) #define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) +/*! @} */ /*! @name MCTRL - Master Control Register */ +/*! @{ */ #define PWM_MCTRL_LDOK_MASK (0xFU) #define PWM_MCTRL_LDOK_SHIFT (0U) #define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) @@ -17974,13 +19657,17 @@ typedef struct { #define PWM_MCTRL_IPOL_MASK (0xF000U) #define PWM_MCTRL_IPOL_SHIFT (12U) #define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) +/*! @} */ /*! @name MCTRL2 - Master Control 2 Register */ +/*! @{ */ #define PWM_MCTRL2_MONPLL_MASK (0x3U) #define PWM_MCTRL2_MONPLL_SHIFT (0U) #define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK) +/*! @} */ /*! @name FCTRL - Fault Control Register */ +/*! @{ */ #define PWM_FCTRL_FIE_MASK (0xFU) #define PWM_FCTRL_FIE_SHIFT (0U) #define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) @@ -17993,8 +19680,10 @@ typedef struct { #define PWM_FCTRL_FLVL_MASK (0xF000U) #define PWM_FCTRL_FLVL_SHIFT (12U) #define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) +/*! @} */ /*! @name FSTS - Fault Status Register */ +/*! @{ */ #define PWM_FSTS_FFLAG_MASK (0xFU) #define PWM_FSTS_FFLAG_SHIFT (0U) #define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) @@ -18007,8 +19696,10 @@ typedef struct { #define PWM_FSTS_FHALF_MASK (0xF000U) #define PWM_FSTS_FHALF_SHIFT (12U) #define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) +/*! @} */ /*! @name FFILT - Fault Filter Register */ +/*! @{ */ #define PWM_FFILT_FILT_PER_MASK (0xFFU) #define PWM_FFILT_FILT_PER_SHIFT (0U) #define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) @@ -18018,16 +19709,21 @@ typedef struct { #define PWM_FFILT_GSTR_MASK (0x8000U) #define PWM_FFILT_GSTR_SHIFT (15U) #define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) +/*! @} */ /*! @name FTST - Fault Test Register */ +/*! @{ */ #define PWM_FTST_FTEST_MASK (0x1U) #define PWM_FTST_FTEST_SHIFT (0U) #define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) +/*! @} */ /*! @name FCTRL2 - Fault Control 2 Register */ +/*! @{ */ #define PWM_FCTRL2_NOCOMB_MASK (0xFU) #define PWM_FCTRL2_NOCOMB_SHIFT (0U) #define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) +/*! @} */ /*! @@ -18162,6 +19858,7 @@ typedef struct { */ /*! @name CTRL - Control Register 0 */ +/*! @{ */ #define PXP_CTRL_ENABLE_MASK (0x1U) #define PXP_CTRL_ENABLE_SHIFT (0U) #define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK) @@ -18210,8 +19907,10 @@ typedef struct { #define PXP_CTRL_SFTRST_MASK (0x80000000U) #define PXP_CTRL_SFTRST_SHIFT (31U) #define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK) +/*! @} */ /*! @name CTRL_SET - Control Register 0 */ +/*! @{ */ #define PXP_CTRL_SET_ENABLE_MASK (0x1U) #define PXP_CTRL_SET_ENABLE_SHIFT (0U) #define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK) @@ -18260,8 +19959,10 @@ typedef struct { #define PXP_CTRL_SET_SFTRST_MASK (0x80000000U) #define PXP_CTRL_SET_SFTRST_SHIFT (31U) #define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK) +/*! @} */ /*! @name CTRL_CLR - Control Register 0 */ +/*! @{ */ #define PXP_CTRL_CLR_ENABLE_MASK (0x1U) #define PXP_CTRL_CLR_ENABLE_SHIFT (0U) #define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK) @@ -18310,8 +20011,10 @@ typedef struct { #define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U) #define PXP_CTRL_CLR_SFTRST_SHIFT (31U) #define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK) +/*! @} */ /*! @name CTRL_TOG - Control Register 0 */ +/*! @{ */ #define PXP_CTRL_TOG_ENABLE_MASK (0x1U) #define PXP_CTRL_TOG_ENABLE_SHIFT (0U) #define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK) @@ -18360,8 +20063,10 @@ typedef struct { #define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U) #define PXP_CTRL_TOG_SFTRST_SHIFT (31U) #define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK) +/*! @} */ /*! @name STAT - Status Register */ +/*! @{ */ #define PXP_STAT_IRQ_MASK (0x1U) #define PXP_STAT_IRQ_SHIFT (0U) #define PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK) @@ -18389,8 +20094,10 @@ typedef struct { #define PXP_STAT_BLOCKX_MASK (0xFF000000U) #define PXP_STAT_BLOCKX_SHIFT (24U) #define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK) +/*! @} */ /*! @name STAT_SET - Status Register */ +/*! @{ */ #define PXP_STAT_SET_IRQ_MASK (0x1U) #define PXP_STAT_SET_IRQ_SHIFT (0U) #define PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK) @@ -18418,8 +20125,10 @@ typedef struct { #define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U) #define PXP_STAT_SET_BLOCKX_SHIFT (24U) #define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK) +/*! @} */ /*! @name STAT_CLR - Status Register */ +/*! @{ */ #define PXP_STAT_CLR_IRQ_MASK (0x1U) #define PXP_STAT_CLR_IRQ_SHIFT (0U) #define PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK) @@ -18447,8 +20156,10 @@ typedef struct { #define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U) #define PXP_STAT_CLR_BLOCKX_SHIFT (24U) #define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK) +/*! @} */ /*! @name STAT_TOG - Status Register */ +/*! @{ */ #define PXP_STAT_TOG_IRQ_MASK (0x1U) #define PXP_STAT_TOG_IRQ_SHIFT (0U) #define PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK) @@ -18476,8 +20187,10 @@ typedef struct { #define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U) #define PXP_STAT_TOG_BLOCKX_SHIFT (24U) #define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK) +/*! @} */ /*! @name OUT_CTRL - Output Buffer Control Register */ +/*! @{ */ #define PXP_OUT_CTRL_FORMAT_MASK (0x1FU) #define PXP_OUT_CTRL_FORMAT_SHIFT (0U) #define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK) @@ -18496,8 +20209,10 @@ typedef struct { #define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U) #define PXP_OUT_CTRL_ALPHA_SHIFT (24U) #define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK) +/*! @} */ /*! @name OUT_CTRL_SET - Output Buffer Control Register */ +/*! @{ */ #define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU) #define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U) #define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK) @@ -18516,8 +20231,10 @@ typedef struct { #define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U) #define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U) #define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK) +/*! @} */ /*! @name OUT_CTRL_CLR - Output Buffer Control Register */ +/*! @{ */ #define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU) #define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U) #define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK) @@ -18536,8 +20253,10 @@ typedef struct { #define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U) #define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U) #define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK) +/*! @} */ /*! @name OUT_CTRL_TOG - Output Buffer Control Register */ +/*! @{ */ #define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU) #define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U) #define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK) @@ -18556,26 +20275,34 @@ typedef struct { #define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U) #define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U) #define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK) +/*! @} */ /*! @name OUT_BUF - Output Frame Buffer Pointer */ +/*! @{ */ #define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU) #define PXP_OUT_BUF_ADDR_SHIFT (0U) #define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK) +/*! @} */ /*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */ +/*! @{ */ #define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU) #define PXP_OUT_BUF2_ADDR_SHIFT (0U) #define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK) +/*! @} */ /*! @name OUT_PITCH - Output Buffer Pitch */ +/*! @{ */ #define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU) #define PXP_OUT_PITCH_PITCH_SHIFT (0U) #define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK) #define PXP_OUT_PITCH_RSVD_MASK (0xFFFF0000U) #define PXP_OUT_PITCH_RSVD_SHIFT (16U) #define PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_RSVD_SHIFT)) & PXP_OUT_PITCH_RSVD_MASK) +/*! @} */ /*! @name OUT_LRC - Output Surface Lower Right Coordinate */ +/*! @{ */ #define PXP_OUT_LRC_Y_MASK (0x3FFFU) #define PXP_OUT_LRC_Y_SHIFT (0U) #define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK) @@ -18588,8 +20315,10 @@ typedef struct { #define PXP_OUT_LRC_RSVD1_MASK (0xC0000000U) #define PXP_OUT_LRC_RSVD1_SHIFT (30U) #define PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD1_SHIFT)) & PXP_OUT_LRC_RSVD1_MASK) +/*! @} */ /*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */ +/*! @{ */ #define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU) #define PXP_OUT_PS_ULC_Y_SHIFT (0U) #define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK) @@ -18602,8 +20331,10 @@ typedef struct { #define PXP_OUT_PS_ULC_RSVD1_MASK (0xC0000000U) #define PXP_OUT_PS_ULC_RSVD1_SHIFT (30U) #define PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD1_SHIFT)) & PXP_OUT_PS_ULC_RSVD1_MASK) +/*! @} */ /*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */ +/*! @{ */ #define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU) #define PXP_OUT_PS_LRC_Y_SHIFT (0U) #define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK) @@ -18616,8 +20347,10 @@ typedef struct { #define PXP_OUT_PS_LRC_RSVD1_MASK (0xC0000000U) #define PXP_OUT_PS_LRC_RSVD1_SHIFT (30U) #define PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD1_SHIFT)) & PXP_OUT_PS_LRC_RSVD1_MASK) +/*! @} */ /*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */ +/*! @{ */ #define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU) #define PXP_OUT_AS_ULC_Y_SHIFT (0U) #define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK) @@ -18630,8 +20363,10 @@ typedef struct { #define PXP_OUT_AS_ULC_RSVD1_MASK (0xC0000000U) #define PXP_OUT_AS_ULC_RSVD1_SHIFT (30U) #define PXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD1_SHIFT)) & PXP_OUT_AS_ULC_RSVD1_MASK) +/*! @} */ /*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */ +/*! @{ */ #define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU) #define PXP_OUT_AS_LRC_Y_SHIFT (0U) #define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK) @@ -18644,8 +20379,10 @@ typedef struct { #define PXP_OUT_AS_LRC_RSVD1_MASK (0xC0000000U) #define PXP_OUT_AS_LRC_RSVD1_SHIFT (30U) #define PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD1_SHIFT)) & PXP_OUT_AS_LRC_RSVD1_MASK) +/*! @} */ /*! @name PS_CTRL - Processed Surface (PS) Control Register */ +/*! @{ */ #define PXP_PS_CTRL_FORMAT_MASK (0x1FU) #define PXP_PS_CTRL_FORMAT_SHIFT (0U) #define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK) @@ -18664,8 +20401,10 @@ typedef struct { #define PXP_PS_CTRL_RSVD1_MASK (0xFFFFF000U) #define PXP_PS_CTRL_RSVD1_SHIFT (12U) #define PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD1_SHIFT)) & PXP_PS_CTRL_RSVD1_MASK) +/*! @} */ /*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */ +/*! @{ */ #define PXP_PS_CTRL_SET_FORMAT_MASK (0x1FU) #define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U) #define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK) @@ -18684,8 +20423,10 @@ typedef struct { #define PXP_PS_CTRL_SET_RSVD1_MASK (0xFFFFF000U) #define PXP_PS_CTRL_SET_RSVD1_SHIFT (12U) #define PXP_PS_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD1_SHIFT)) & PXP_PS_CTRL_SET_RSVD1_MASK) +/*! @} */ /*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */ +/*! @{ */ #define PXP_PS_CTRL_CLR_FORMAT_MASK (0x1FU) #define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U) #define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK) @@ -18704,8 +20445,10 @@ typedef struct { #define PXP_PS_CTRL_CLR_RSVD1_MASK (0xFFFFF000U) #define PXP_PS_CTRL_CLR_RSVD1_SHIFT (12U) #define PXP_PS_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD1_SHIFT)) & PXP_PS_CTRL_CLR_RSVD1_MASK) +/*! @} */ /*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */ +/*! @{ */ #define PXP_PS_CTRL_TOG_FORMAT_MASK (0x1FU) #define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U) #define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK) @@ -18724,39 +20467,51 @@ typedef struct { #define PXP_PS_CTRL_TOG_RSVD1_MASK (0xFFFFF000U) #define PXP_PS_CTRL_TOG_RSVD1_SHIFT (12U) #define PXP_PS_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD1_SHIFT)) & PXP_PS_CTRL_TOG_RSVD1_MASK) +/*! @} */ /*! @name PS_BUF - PS Input Buffer Address */ +/*! @{ */ #define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU) #define PXP_PS_BUF_ADDR_SHIFT (0U) #define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK) +/*! @} */ /*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */ +/*! @{ */ #define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU) #define PXP_PS_UBUF_ADDR_SHIFT (0U) #define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK) +/*! @} */ /*! @name PS_VBUF - PS V/Cr Input Buffer Address */ +/*! @{ */ #define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU) #define PXP_PS_VBUF_ADDR_SHIFT (0U) #define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK) +/*! @} */ /*! @name PS_PITCH - Processed Surface Pitch */ +/*! @{ */ #define PXP_PS_PITCH_PITCH_MASK (0xFFFFU) #define PXP_PS_PITCH_PITCH_SHIFT (0U) #define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK) #define PXP_PS_PITCH_RSVD_MASK (0xFFFF0000U) #define PXP_PS_PITCH_RSVD_SHIFT (16U) #define PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_RSVD_SHIFT)) & PXP_PS_PITCH_RSVD_MASK) +/*! @} */ /*! @name PS_BACKGROUND - PS Background Color */ +/*! @{ */ #define PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU) #define PXP_PS_BACKGROUND_COLOR_SHIFT (0U) #define PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK) #define PXP_PS_BACKGROUND_RSVD_MASK (0xFF000000U) #define PXP_PS_BACKGROUND_RSVD_SHIFT (24U) #define PXP_PS_BACKGROUND_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_RSVD_SHIFT)) & PXP_PS_BACKGROUND_RSVD_MASK) +/*! @} */ /*! @name PS_SCALE - PS Scale Factor Register */ +/*! @{ */ #define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU) #define PXP_PS_SCALE_XSCALE_SHIFT (0U) #define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK) @@ -18769,8 +20524,10 @@ typedef struct { #define PXP_PS_SCALE_RSVD2_MASK (0x80000000U) #define PXP_PS_SCALE_RSVD2_SHIFT (31U) #define PXP_PS_SCALE_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD2_SHIFT)) & PXP_PS_SCALE_RSVD2_MASK) +/*! @} */ /*! @name PS_OFFSET - PS Scale Offset Register */ +/*! @{ */ #define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU) #define PXP_PS_OFFSET_XOFFSET_SHIFT (0U) #define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK) @@ -18783,24 +20540,30 @@ typedef struct { #define PXP_PS_OFFSET_RSVD2_MASK (0xF0000000U) #define PXP_PS_OFFSET_RSVD2_SHIFT (28U) #define PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD2_SHIFT)) & PXP_PS_OFFSET_RSVD2_MASK) +/*! @} */ /*! @name PS_CLRKEYLOW - PS Color Key Low */ +/*! @{ */ #define PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) #define PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U) #define PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK) #define PXP_PS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) #define PXP_PS_CLRKEYLOW_RSVD1_SHIFT (24U) #define PXP_PS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_PS_CLRKEYLOW_RSVD1_MASK) +/*! @} */ /*! @name PS_CLRKEYHIGH - PS Color Key High */ +/*! @{ */ #define PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) #define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U) #define PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK) #define PXP_PS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) #define PXP_PS_CLRKEYHIGH_RSVD1_SHIFT (24U) #define PXP_PS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_PS_CLRKEYHIGH_RSVD1_MASK) +/*! @} */ /*! @name AS_CTRL - Alpha Surface Control */ +/*! @{ */ #define PXP_AS_CTRL_RSVD0_MASK (0x1U) #define PXP_AS_CTRL_RSVD0_SHIFT (0U) #define PXP_AS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD0_SHIFT)) & PXP_AS_CTRL_RSVD0_MASK) @@ -18825,37 +20588,47 @@ typedef struct { #define PXP_AS_CTRL_RSVD1_MASK (0xFFE00000U) #define PXP_AS_CTRL_RSVD1_SHIFT (21U) #define PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD1_SHIFT)) & PXP_AS_CTRL_RSVD1_MASK) +/*! @} */ /*! @name AS_BUF - Alpha Surface Buffer Pointer */ +/*! @{ */ #define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU) #define PXP_AS_BUF_ADDR_SHIFT (0U) #define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK) +/*! @} */ /*! @name AS_PITCH - Alpha Surface Pitch */ +/*! @{ */ #define PXP_AS_PITCH_PITCH_MASK (0xFFFFU) #define PXP_AS_PITCH_PITCH_SHIFT (0U) #define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK) #define PXP_AS_PITCH_RSVD_MASK (0xFFFF0000U) #define PXP_AS_PITCH_RSVD_SHIFT (16U) #define PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_RSVD_SHIFT)) & PXP_AS_PITCH_RSVD_MASK) +/*! @} */ /*! @name AS_CLRKEYLOW - Overlay Color Key Low */ +/*! @{ */ #define PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) #define PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U) #define PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK) #define PXP_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) #define PXP_AS_CLRKEYLOW_RSVD1_SHIFT (24U) #define PXP_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_AS_CLRKEYLOW_RSVD1_MASK) +/*! @} */ /*! @name AS_CLRKEYHIGH - Overlay Color Key High */ +/*! @{ */ #define PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) #define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U) #define PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK) #define PXP_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) #define PXP_AS_CLRKEYHIGH_RSVD1_SHIFT (24U) #define PXP_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_AS_CLRKEYHIGH_RSVD1_MASK) +/*! @} */ /*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */ +/*! @{ */ #define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU) #define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U) #define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK) @@ -18874,8 +20647,10 @@ typedef struct { #define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U) #define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U) #define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK) +/*! @} */ /*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */ +/*! @{ */ #define PXP_CSC1_COEF1_C4_MASK (0x7FFU) #define PXP_CSC1_COEF1_C4_SHIFT (0U) #define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK) @@ -18888,8 +20663,10 @@ typedef struct { #define PXP_CSC1_COEF1_RSVD1_MASK (0xF8000000U) #define PXP_CSC1_COEF1_RSVD1_SHIFT (27U) #define PXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD1_SHIFT)) & PXP_CSC1_COEF1_RSVD1_MASK) +/*! @} */ /*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */ +/*! @{ */ #define PXP_CSC1_COEF2_C3_MASK (0x7FFU) #define PXP_CSC1_COEF2_C3_SHIFT (0U) #define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK) @@ -18902,16 +20679,20 @@ typedef struct { #define PXP_CSC1_COEF2_RSVD1_MASK (0xF8000000U) #define PXP_CSC1_COEF2_RSVD1_SHIFT (27U) #define PXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD1_SHIFT)) & PXP_CSC1_COEF2_RSVD1_MASK) +/*! @} */ /*! @name POWER - PXP Power Control Register */ +/*! @{ */ #define PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U) #define PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U) #define PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK) #define PXP_POWER_CTRL_MASK (0xFFFFF000U) #define PXP_POWER_CTRL_SHIFT (12U) #define PXP_POWER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_CTRL_SHIFT)) & PXP_POWER_CTRL_MASK) +/*! @} */ /*! @name NEXT - Next Frame Pointer */ +/*! @{ */ #define PXP_NEXT_ENABLED_MASK (0x1U) #define PXP_NEXT_ENABLED_SHIFT (0U) #define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK) @@ -18921,8 +20702,10 @@ typedef struct { #define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU) #define PXP_NEXT_POINTER_SHIFT (2U) #define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK) +/*! @} */ /*! @name PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register. */ +/*! @{ */ #define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK (0x1U) #define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT (0U) #define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK) @@ -18956,6 +20739,7 @@ typedef struct { #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U) #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U) #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK) +/*! @} */ /*! @@ -19011,44 +20795,54 @@ typedef struct { */ /*! @name ROMPATCHD - ROMC Data Registers */ +/*! @{ */ #define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) #define ROMC_ROMPATCHD_DATAX_SHIFT (0U) #define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK) +/*! @} */ /* The count of ROMC_ROMPATCHD */ #define ROMC_ROMPATCHD_COUNT (8U) /*! @name ROMPATCHCNTL - ROMC Control Register */ +/*! @{ */ #define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) #define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U) #define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) #define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U) #define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U) #define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) +/*! @} */ /*! @name ROMPATCHENL - ROMC Enable Register Low */ +/*! @{ */ #define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU) #define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U) #define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) +/*! @} */ /*! @name ROMPATCHA - ROMC Address Registers */ +/*! @{ */ #define ROMC_ROMPATCHA_THUMBX_MASK (0x1U) #define ROMC_ROMPATCHA_THUMBX_SHIFT (0U) #define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) #define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) #define ROMC_ROMPATCHA_ADDRX_SHIFT (1U) #define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK) +/*! @} */ /* The count of ROMC_ROMPATCHA */ #define ROMC_ROMPATCHA_COUNT (16U) /*! @name ROMPATCHSR - ROMC Status Register */ +/*! @{ */ #define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU) #define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U) #define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) #define ROMC_ROMPATCHSR_SW_MASK (0x20000U) #define ROMC_ROMPATCHSR_SW_SHIFT (17U) #define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) +/*! @} */ /*! @@ -19098,6 +20892,7 @@ typedef struct { */ /*! @name CS - Watchdog Control and Status Register */ +/*! @{ */ #define RTWDOG_CS_STOP_MASK (0x1U) #define RTWDOG_CS_STOP_SHIFT (0U) #define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK) @@ -19140,30 +20935,37 @@ typedef struct { #define RTWDOG_CS_WIN_MASK (0x8000U) #define RTWDOG_CS_WIN_SHIFT (15U) #define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK) +/*! @} */ /*! @name CNT - Watchdog Counter Register */ +/*! @{ */ #define RTWDOG_CNT_CNTLOW_MASK (0xFFU) #define RTWDOG_CNT_CNTLOW_SHIFT (0U) #define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK) #define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U) #define RTWDOG_CNT_CNTHIGH_SHIFT (8U) #define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK) +/*! @} */ /*! @name TOVAL - Watchdog Timeout Value Register */ +/*! @{ */ #define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU) #define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U) #define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK) #define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) #define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U) #define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK) +/*! @} */ /*! @name WIN - Watchdog Window Register */ +/*! @{ */ #define RTWDOG_WIN_WINLOW_MASK (0xFFU) #define RTWDOG_WIN_WINLOW_SHIFT (0U) #define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK) #define RTWDOG_WIN_WINHIGH_MASK (0xFF00U) #define RTWDOG_WIN_WINHIGH_SHIFT (8U) #define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) +/*! @} */ /*! @@ -19266,6 +21068,7 @@ typedef struct { */ /*! @name MCR - Module Control Register */ +/*! @{ */ #define SEMC_MCR_SWRST_MASK (0x1U) #define SEMC_MCR_SWRST_SHIFT (0U) #define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) @@ -19287,8 +21090,10 @@ typedef struct { #define SEMC_MCR_BTO_MASK (0x1F000000U) #define SEMC_MCR_BTO_SHIFT (24U) #define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK) +/*! @} */ /*! @name IOCR - IO Mux Control Register */ +/*! @{ */ #define SEMC_IOCR_MUX_A8_MASK (0x7U) #define SEMC_IOCR_MUX_A8_SHIFT (0U) #define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK) @@ -19307,8 +21112,10 @@ typedef struct { #define SEMC_IOCR_MUX_RDY_MASK (0x38000U) #define SEMC_IOCR_MUX_RDY_SHIFT (15U) #define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK) +/*! @} */ /*! @name BMCR0 - Master Bus (AXI) Control Register 0 */ +/*! @{ */ #define SEMC_BMCR0_WQOS_MASK (0xFU) #define SEMC_BMCR0_WQOS_SHIFT (0U) #define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK) @@ -19321,8 +21128,10 @@ typedef struct { #define SEMC_BMCR0_WRWS_MASK (0xFF0000U) #define SEMC_BMCR0_WRWS_SHIFT (16U) #define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK) +/*! @} */ /*! @name BMCR1 - Master Bus (AXI) Control Register 1 */ +/*! @{ */ #define SEMC_BMCR1_WQOS_MASK (0xFU) #define SEMC_BMCR1_WQOS_SHIFT (0U) #define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK) @@ -19338,8 +21147,10 @@ typedef struct { #define SEMC_BMCR1_WBR_MASK (0xFF000000U) #define SEMC_BMCR1_WBR_SHIFT (24U) #define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK) +/*! @} */ /*! @name BR - Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device) */ +/*! @{ */ #define SEMC_BR_VLD_MASK (0x1U) #define SEMC_BR_VLD_SHIFT (0U) #define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK) @@ -19349,11 +21160,13 @@ typedef struct { #define SEMC_BR_BA_MASK (0xFFFFF000U) #define SEMC_BR_BA_SHIFT (12U) #define SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK) +/*! @} */ /* The count of SEMC_BR */ #define SEMC_BR_COUNT (9U) /*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ #define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U) #define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U) #define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) @@ -19372,8 +21185,10 @@ typedef struct { #define SEMC_INTEN_NDNOPENDEN_MASK (0x20U) #define SEMC_INTEN_NDNOPENDEN_SHIFT (5U) #define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) +/*! @} */ /*! @name INTR - Interrupt Enable Register */ +/*! @{ */ #define SEMC_INTR_IPCMDDONE_MASK (0x1U) #define SEMC_INTR_IPCMDDONE_SHIFT (0U) #define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) @@ -19392,8 +21207,10 @@ typedef struct { #define SEMC_INTR_NDNOPEND_MASK (0x20U) #define SEMC_INTR_NDNOPEND_SHIFT (5U) #define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) +/*! @} */ /*! @name SDRAMCR0 - SDRAM control register 0 */ +/*! @{ */ #define SEMC_SDRAMCR0_PS_MASK (0x1U) #define SEMC_SDRAMCR0_PS_SHIFT (0U) #define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) @@ -19406,8 +21223,10 @@ typedef struct { #define SEMC_SDRAMCR0_CL_MASK (0xC00U) #define SEMC_SDRAMCR0_CL_SHIFT (10U) #define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK) +/*! @} */ /*! @name SDRAMCR1 - SDRAM control register 1 */ +/*! @{ */ #define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU) #define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U) #define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK) @@ -19426,8 +21245,10 @@ typedef struct { #define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U) #define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U) #define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK) +/*! @} */ /*! @name SDRAMCR2 - SDRAM control register 2 */ +/*! @{ */ #define SEMC_SDRAMCR2_SRRC_MASK (0xFFU) #define SEMC_SDRAMCR2_SRRC_SHIFT (0U) #define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK) @@ -19440,8 +21261,10 @@ typedef struct { #define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U) #define SEMC_SDRAMCR2_ITO_SHIFT (24U) #define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK) +/*! @} */ /*! @name SDRAMCR3 - SDRAM control register 3 */ +/*! @{ */ #define SEMC_SDRAMCR3_REN_MASK (0x1U) #define SEMC_SDRAMCR3_REN_SHIFT (0U) #define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK) @@ -19457,8 +21280,10 @@ typedef struct { #define SEMC_SDRAMCR3_UT_MASK (0xFF000000U) #define SEMC_SDRAMCR3_UT_SHIFT (24U) #define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK) +/*! @} */ /*! @name NANDCR0 - NAND control register 0 */ +/*! @{ */ #define SEMC_NANDCR0_PS_MASK (0x1U) #define SEMC_NANDCR0_PS_SHIFT (0U) #define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK) @@ -19471,8 +21296,10 @@ typedef struct { #define SEMC_NANDCR0_COL_MASK (0x700U) #define SEMC_NANDCR0_COL_SHIFT (8U) #define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK) +/*! @} */ /*! @name NANDCR1 - NAND control register 1 */ +/*! @{ */ #define SEMC_NANDCR1_CES_MASK (0xFU) #define SEMC_NANDCR1_CES_SHIFT (0U) #define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK) @@ -19497,8 +21324,10 @@ typedef struct { #define SEMC_NANDCR1_CEITV_MASK (0xF0000000U) #define SEMC_NANDCR1_CEITV_SHIFT (28U) #define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK) +/*! @} */ /*! @name NANDCR2 - NAND control register 2 */ +/*! @{ */ #define SEMC_NANDCR2_TWHR_MASK (0x3FU) #define SEMC_NANDCR2_TWHR_SHIFT (0U) #define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK) @@ -19514,8 +21343,10 @@ typedef struct { #define SEMC_NANDCR2_TWB_MASK (0x3F000000U) #define SEMC_NANDCR2_TWB_SHIFT (24U) #define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK) +/*! @} */ /*! @name NANDCR3 - NAND control register 3 */ +/*! @{ */ #define SEMC_NANDCR3_NDOPT1_MASK (0x1U) #define SEMC_NANDCR3_NDOPT1_SHIFT (0U) #define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK) @@ -19525,8 +21356,10 @@ typedef struct { #define SEMC_NANDCR3_NDOPT3_MASK (0x4U) #define SEMC_NANDCR3_NDOPT3_SHIFT (2U) #define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK) +/*! @} */ /*! @name NORCR0 - NOR control register 0 */ +/*! @{ */ #define SEMC_NORCR0_PS_MASK (0x1U) #define SEMC_NORCR0_PS_SHIFT (0U) #define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK) @@ -19542,8 +21375,10 @@ typedef struct { #define SEMC_NORCR0_COL_MASK (0xF000U) #define SEMC_NORCR0_COL_SHIFT (12U) #define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK) +/*! @} */ /*! @name NORCR1 - NOR control register 1 */ +/*! @{ */ #define SEMC_NORCR1_CES_MASK (0xFU) #define SEMC_NORCR1_CES_SHIFT (0U) #define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK) @@ -19568,8 +21403,10 @@ typedef struct { #define SEMC_NORCR1_REH_MASK (0xF0000000U) #define SEMC_NORCR1_REH_SHIFT (28U) #define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK) +/*! @} */ /*! @name NORCR2 - NOR control register 2 */ +/*! @{ */ #define SEMC_NORCR2_WDS_MASK (0xFU) #define SEMC_NORCR2_WDS_SHIFT (0U) #define SEMC_NORCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDS_SHIFT)) & SEMC_NORCR2_WDS_MASK) @@ -19591,8 +21428,10 @@ typedef struct { #define SEMC_NORCR2_CEITV_MASK (0xF000000U) #define SEMC_NORCR2_CEITV_SHIFT (24U) #define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK) +/*! @} */ /*! @name SRAMCR0 - SRAM control register 0 */ +/*! @{ */ #define SEMC_SRAMCR0_PS_MASK (0x1U) #define SEMC_SRAMCR0_PS_SHIFT (0U) #define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK) @@ -19608,8 +21447,10 @@ typedef struct { #define SEMC_SRAMCR0_COL_MASK (0xF000U) #define SEMC_SRAMCR0_COL_SHIFT (12U) #define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK) +/*! @} */ /*! @name SRAMCR1 - SRAM control register 1 */ +/*! @{ */ #define SEMC_SRAMCR1_CES_MASK (0xFU) #define SEMC_SRAMCR1_CES_SHIFT (0U) #define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK) @@ -19634,8 +21475,10 @@ typedef struct { #define SEMC_SRAMCR1_REH_MASK (0xF0000000U) #define SEMC_SRAMCR1_REH_SHIFT (28U) #define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK) +/*! @} */ /*! @name SRAMCR2 - SRAM control register 2 */ +/*! @{ */ #define SEMC_SRAMCR2_WDS_MASK (0xFU) #define SEMC_SRAMCR2_WDS_SHIFT (0U) #define SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK) @@ -19657,8 +21500,10 @@ typedef struct { #define SEMC_SRAMCR2_CEITV_MASK (0xF000000U) #define SEMC_SRAMCR2_CEITV_SHIFT (24U) #define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK) +/*! @} */ /*! @name DBICR0 - DBI-B control register 0 */ +/*! @{ */ #define SEMC_DBICR0_PS_MASK (0x1U) #define SEMC_DBICR0_PS_SHIFT (0U) #define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) @@ -19668,8 +21513,10 @@ typedef struct { #define SEMC_DBICR0_COL_MASK (0xF000U) #define SEMC_DBICR0_COL_SHIFT (12U) #define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK) +/*! @} */ /*! @name DBICR1 - DBI-B control register 1 */ +/*! @{ */ #define SEMC_DBICR1_CES_MASK (0xFU) #define SEMC_DBICR1_CES_SHIFT (0U) #define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK) @@ -19691,18 +21538,30 @@ typedef struct { #define SEMC_DBICR1_CEITV_MASK (0xF000000U) #define SEMC_DBICR1_CEITV_SHIFT (24U) #define SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK) +#define SEMC_DBICR1_REL2_MASK (0x30000000U) +#define SEMC_DBICR1_REL2_SHIFT (28U) +#define SEMC_DBICR1_REL2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL2_SHIFT)) & SEMC_DBICR1_REL2_MASK) +#define SEMC_DBICR1_REH2_MASK (0xC0000000U) +#define SEMC_DBICR1_REH2_SHIFT (30U) +#define SEMC_DBICR1_REH2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH2_SHIFT)) & SEMC_DBICR1_REH2_MASK) +/*! @} */ /*! @name IPCR0 - IP Command control register 0 */ +/*! @{ */ #define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU) #define SEMC_IPCR0_SA_SHIFT (0U) #define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK) +/*! @} */ /*! @name IPCR1 - IP Command control register 1 */ +/*! @{ */ #define SEMC_IPCR1_DATSZ_MASK (0x7U) #define SEMC_IPCR1_DATSZ_SHIFT (0U) #define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK) +/*! @} */ /*! @name IPCR2 - IP Command control register 2 */ +/*! @{ */ #define SEMC_IPCR2_BM0_MASK (0x1U) #define SEMC_IPCR2_BM0_SHIFT (0U) #define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK) @@ -19715,42 +21574,55 @@ typedef struct { #define SEMC_IPCR2_BM3_MASK (0x8U) #define SEMC_IPCR2_BM3_SHIFT (3U) #define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK) +/*! @} */ /*! @name IPCMD - IP Command register */ +/*! @{ */ #define SEMC_IPCMD_CMD_MASK (0xFFFFU) #define SEMC_IPCMD_CMD_SHIFT (0U) #define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK) #define SEMC_IPCMD_KEY_MASK (0xFFFF0000U) #define SEMC_IPCMD_KEY_SHIFT (16U) #define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK) +/*! @} */ /*! @name IPTXDAT - TX DATA register (for IP Command) */ +/*! @{ */ #define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU) #define SEMC_IPTXDAT_DAT_SHIFT (0U) #define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK) +/*! @} */ /*! @name IPRXDAT - RX DATA register (for IP Command) */ +/*! @{ */ #define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU) #define SEMC_IPRXDAT_DAT_SHIFT (0U) #define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK) +/*! @} */ /*! @name STS0 - Status register 0 */ +/*! @{ */ #define SEMC_STS0_IDLE_MASK (0x1U) #define SEMC_STS0_IDLE_SHIFT (0U) #define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) #define SEMC_STS0_NARDY_MASK (0x2U) #define SEMC_STS0_NARDY_SHIFT (1U) #define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) +/*! @} */ /*! @name STS2 - Status register 2 */ +/*! @{ */ #define SEMC_STS2_NDWRPEND_MASK (0x8U) #define SEMC_STS2_NDWRPEND_SHIFT (3U) #define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) +/*! @} */ /*! @name STS12 - Status register 12 */ +/*! @{ */ #define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU) #define SEMC_STS12_NDADDR_SHIFT (0U) #define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) +/*! @} */ /*! @@ -19817,8 +21689,8 @@ typedef struct { uint8_t RESERVED_1[4]; __IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */ uint8_t RESERVED_2[96]; - __IO uint32_t LPGPR[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x100, array step: 0x4 */ - uint8_t RESERVED_3[2792]; + __IO uint32_t LPGPR[8]; /**< SNVS_LP General Purpose Registers 0 .. 7, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_3[2776]; __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ } SNVS_Type; @@ -19833,6 +21705,7 @@ typedef struct { */ /*! @name HPLR - SNVS_HP Lock Register */ +/*! @{ */ #define SNVS_HPLR_ZMK_WSL_MASK (0x1U) #define SNVS_HPLR_ZMK_WSL_SHIFT (0U) #define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK) @@ -19869,8 +21742,10 @@ typedef struct { #define SNVS_HPLR_HAC_L_MASK (0x40000U) #define SNVS_HPLR_HAC_L_SHIFT (18U) #define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK) +/*! @} */ /*! @name HPCOMR - SNVS_HP Command Register */ +/*! @{ */ #define SNVS_HPCOMR_SSM_ST_MASK (0x1U) #define SNVS_HPCOMR_SSM_ST_SHIFT (0U) #define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK) @@ -19916,14 +21791,19 @@ typedef struct { #define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) #define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) #define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) +/*! @} */ /*! @name HPCR - SNVS_HP Control Register */ +/*! @{ */ #define SNVS_HPCR_RTC_EN_MASK (0x1U) #define SNVS_HPCR_RTC_EN_SHIFT (0U) #define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) #define SNVS_HPCR_HPTA_EN_MASK (0x2U) #define SNVS_HPCR_HPTA_EN_SHIFT (1U) #define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) +#define SNVS_HPCR_DIS_PI_MASK (0x4U) +#define SNVS_HPCR_DIS_PI_SHIFT (2U) +#define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK) #define SNVS_HPCR_PI_EN_MASK (0x8U) #define SNVS_HPCR_PI_EN_SHIFT (3U) #define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) @@ -19945,8 +21825,10 @@ typedef struct { #define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) #define SNVS_HPCR_BTN_MASK_SHIFT (27U) #define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) +/*! @} */ /*! @name HPSICR - SNVS_HP Security Interrupt Control Register */ +/*! @{ */ #define SNVS_HPSICR_SV0_EN_MASK (0x1U) #define SNVS_HPSICR_SV0_EN_SHIFT (0U) #define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK) @@ -19968,8 +21850,10 @@ typedef struct { #define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U) #define SNVS_HPSICR_LPSVI_EN_SHIFT (31U) #define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK) +/*! @} */ /*! @name HPSVCR - SNVS_HP Security Violation Control Register */ +/*! @{ */ #define SNVS_HPSVCR_SV0_CFG_MASK (0x1U) #define SNVS_HPSVCR_SV0_CFG_SHIFT (0U) #define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK) @@ -19991,8 +21875,10 @@ typedef struct { #define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U) #define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U) #define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK) +/*! @} */ /*! @name HPSR - SNVS_HP Status Register */ +/*! @{ */ #define SNVS_HPSR_HPTA_MASK (0x1U) #define SNVS_HPSR_HPTA_SHIFT (0U) #define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK) @@ -20011,12 +21897,9 @@ typedef struct { #define SNVS_HPSR_SSM_STATE_MASK (0xF00U) #define SNVS_HPSR_SSM_STATE_SHIFT (8U) #define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK) -#define SNVS_HPSR_SYS_SECURITY_CFG_MASK (0x7000U) -#define SNVS_HPSR_SYS_SECURITY_CFG_SHIFT (12U) -#define SNVS_HPSR_SYS_SECURITY_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK) -#define SNVS_HPSR_SYS_SECURE_BOOT_MASK (0x8000U) -#define SNVS_HPSR_SYS_SECURE_BOOT_SHIFT (15U) -#define SNVS_HPSR_SYS_SECURE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK) +#define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U) +#define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U) +#define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK) #define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U) #define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U) #define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK) @@ -20026,8 +21909,10 @@ typedef struct { #define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U) #define SNVS_HPSR_ZMK_ZERO_SHIFT (31U) #define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK) +/*! @} */ /*! @name HPSVSR - SNVS_HP Security Violation Status Register */ +/*! @{ */ #define SNVS_HPSVSR_SV0_MASK (0x1U) #define SNVS_HPSVSR_SV0_SHIFT (0U) #define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK) @@ -20064,38 +21949,52 @@ typedef struct { #define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U) #define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U) #define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK) +/*! @} */ /*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */ +/*! @{ */ #define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU) #define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U) #define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK) +/*! @} */ /*! @name HPHACR - SNVS_HP High Assurance Counter Register */ +/*! @{ */ #define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU) #define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U) #define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK) +/*! @} */ /*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */ +/*! @{ */ #define SNVS_HPRTCMR_RTC_MASK (0x7FFFU) #define SNVS_HPRTCMR_RTC_SHIFT (0U) #define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) +/*! @} */ /*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */ +/*! @{ */ #define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) #define SNVS_HPRTCLR_RTC_SHIFT (0U) #define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) +/*! @} */ /*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ +/*! @{ */ #define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU) #define SNVS_HPTAMR_HPTA_MS_SHIFT (0U) #define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK) +/*! @} */ /*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ +/*! @{ */ #define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU) #define SNVS_HPTALR_HPTA_LS_SHIFT (0U) #define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK) +/*! @} */ /*! @name LPLR - SNVS_LP Lock Register */ +/*! @{ */ #define SNVS_LPLR_ZMK_WHL_MASK (0x1U) #define SNVS_LPLR_ZMK_WHL_SHIFT (0U) #define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK) @@ -20123,8 +22022,10 @@ typedef struct { #define SNVS_LPLR_MKS_HL_MASK (0x200U) #define SNVS_LPLR_MKS_HL_SHIFT (9U) #define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK) +/*! @} */ /*! @name LPCR - SNVS_LP Control Register */ +/*! @{ */ #define SNVS_LPCR_SRTC_ENV_MASK (0x1U) #define SNVS_LPCR_SRTC_ENV_SHIFT (0U) #define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK) @@ -20173,8 +22074,10 @@ typedef struct { #define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U) #define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U) #define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK) +/*! @} */ /*! @name LPMKCR - SNVS_LP Master Key Control Register */ +/*! @{ */ #define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U) #define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U) #define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK) @@ -20190,8 +22093,10 @@ typedef struct { #define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U) #define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U) #define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK) +/*! @} */ /*! @name LPSVCR - SNVS_LP Security Violation Control Register */ +/*! @{ */ #define SNVS_LPSVCR_SV0_EN_MASK (0x1U) #define SNVS_LPSVCR_SV0_EN_SHIFT (0U) #define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK) @@ -20210,8 +22115,10 @@ typedef struct { #define SNVS_LPSVCR_SV5_EN_MASK (0x20U) #define SNVS_LPSVCR_SV5_EN_SHIFT (5U) #define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK) +/*! @} */ /*! @name LPTDCR - SNVS_LP Tamper Detectors Configuration Register */ +/*! @{ */ #define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U) #define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U) #define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK) @@ -20233,8 +22140,10 @@ typedef struct { #define SNVS_LPTDCR_OSCB_MASK (0x10000000U) #define SNVS_LPTDCR_OSCB_SHIFT (28U) #define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK) +/*! @} */ /*! @name LPSR - SNVS_LP Status Register */ +/*! @{ */ #define SNVS_LPSR_LPTA_MASK (0x1U) #define SNVS_LPSR_LPTA_SHIFT (0U) #define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK) @@ -20268,70 +22177,92 @@ typedef struct { #define SNVS_LPSR_LPS_MASK (0x80000000U) #define SNVS_LPSR_LPS_SHIFT (31U) #define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK) +/*! @} */ /*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */ +/*! @{ */ #define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU) #define SNVS_LPSRTCMR_SRTC_SHIFT (0U) #define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK) +/*! @} */ /*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */ +/*! @{ */ #define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU) #define SNVS_LPSRTCLR_SRTC_SHIFT (0U) #define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK) +/*! @} */ /*! @name LPTAR - SNVS_LP Time Alarm Register */ +/*! @{ */ #define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU) #define SNVS_LPTAR_LPTA_SHIFT (0U) #define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK) +/*! @} */ /*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ +/*! @{ */ #define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) #define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) #define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) #define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) #define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) +/*! @} */ /*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ +/*! @{ */ #define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) #define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) #define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) +/*! @} */ /*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */ +/*! @{ */ #define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU) #define SNVS_LPPGDR_PGD_SHIFT (0U) #define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK) +/*! @} */ /*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */ +/*! @{ */ #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U) #define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK) +/*! @} */ /*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */ +/*! @{ */ #define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU) #define SNVS_LPZMKR_ZMK_SHIFT (0U) #define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK) +/*! @} */ /* The count of SNVS_LPZMKR */ #define SNVS_LPZMKR_COUNT (8U) /*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */ +/*! @{ */ #define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U) #define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK) +/*! @} */ /* The count of SNVS_LPGPR_ALIAS */ #define SNVS_LPGPR_ALIAS_COUNT (4U) -/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 3 */ +/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 7 */ +/*! @{ */ #define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR_GPR_SHIFT (0U) #define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) +/*! @} */ /* The count of SNVS_LPGPR */ -#define SNVS_LPGPR_COUNT (4U) +#define SNVS_LPGPR_COUNT (8U) /*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ +/*! @{ */ #define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) #define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) #define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) @@ -20341,8 +22272,10 @@ typedef struct { #define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) #define SNVS_HPVIDR1_IP_ID_SHIFT (16U) #define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) +/*! @} */ /*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ +/*! @{ */ #define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) #define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) #define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) @@ -20355,6 +22288,7 @@ typedef struct { #define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) #define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) #define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) +/*! @} */ /*! @@ -20426,6 +22360,7 @@ typedef struct { */ /*! @name SCR - SPDIF Configuration Register */ +/*! @{ */ #define SPDIF_SCR_USRC_SEL_MASK (0x3U) #define SPDIF_SCR_USRC_SEL_SHIFT (0U) #define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) @@ -20471,13 +22406,17 @@ typedef struct { #define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) #define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) #define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK) +/*! @} */ /*! @name SRCD - CDText Control Register */ +/*! @{ */ #define SPDIF_SRCD_USYNCMODE_MASK (0x2U) #define SPDIF_SRCD_USYNCMODE_SHIFT (1U) #define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) +/*! @} */ /*! @name SRPC - PhaseConfig Register */ +/*! @{ */ #define SPDIF_SRPC_GAINSEL_MASK (0x38U) #define SPDIF_SRPC_GAINSEL_SHIFT (3U) #define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) @@ -20487,8 +22426,10 @@ typedef struct { #define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) #define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) #define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK) +/*! @} */ /*! @name SIE - InterruptEn Register */ +/*! @{ */ #define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) #define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) #define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) @@ -20543,8 +22484,10 @@ typedef struct { #define SPDIF_SIE_LOCK_MASK (0x100000U) #define SPDIF_SIE_LOCK_SHIFT (20U) #define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) +/*! @} */ /*! @name SIC - InterruptClear Register */ +/*! @{ */ #define SPDIF_SIC_LOCKLOSS_MASK (0x4U) #define SPDIF_SIC_LOCKLOSS_SHIFT (2U) #define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) @@ -20587,8 +22530,10 @@ typedef struct { #define SPDIF_SIC_LOCK_MASK (0x100000U) #define SPDIF_SIC_LOCK_SHIFT (20U) #define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) +/*! @} */ /*! @name SIS - InterruptStat Register */ +/*! @{ */ #define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) #define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) #define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) @@ -20643,63 +22588,87 @@ typedef struct { #define SPDIF_SIS_LOCK_MASK (0x100000U) #define SPDIF_SIS_LOCK_SHIFT (20U) #define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) +/*! @} */ /*! @name SRL - SPDIFRxLeft Register */ +/*! @{ */ #define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) #define SPDIF_SRL_RXDATALEFT_SHIFT (0U) #define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) +/*! @} */ /*! @name SRR - SPDIFRxRight Register */ +/*! @{ */ #define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) #define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) #define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) +/*! @} */ /*! @name SRCSH - SPDIFRxCChannel_h Register */ +/*! @{ */ #define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) #define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) #define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) +/*! @} */ /*! @name SRCSL - SPDIFRxCChannel_l Register */ +/*! @{ */ #define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) #define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) #define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) +/*! @} */ /*! @name SRU - UchannelRx Register */ +/*! @{ */ #define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) #define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) #define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) +/*! @} */ /*! @name SRQ - QchannelRx Register */ +/*! @{ */ #define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) #define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) #define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) +/*! @} */ /*! @name STL - SPDIFTxLeft Register */ +/*! @{ */ #define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) #define SPDIF_STL_TXDATALEFT_SHIFT (0U) #define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) +/*! @} */ /*! @name STR - SPDIFTxRight Register */ +/*! @{ */ #define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) #define SPDIF_STR_TXDATARIGHT_SHIFT (0U) #define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) +/*! @} */ /*! @name STCSCH - SPDIFTxCChannelCons_h Register */ +/*! @{ */ #define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) #define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) #define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) +/*! @} */ /*! @name STCSCL - SPDIFTxCChannelCons_l Register */ +/*! @{ */ #define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) #define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) #define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) +/*! @} */ /*! @name SRFM - FreqMeas Register */ +/*! @{ */ #define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) #define SPDIF_SRFM_FREQMEAS_SHIFT (0U) #define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) +/*! @} */ /*! @name STC - SPDIFTxClk Register */ +/*! @{ */ #define SPDIF_STC_TXCLK_DF_MASK (0x7FU) #define SPDIF_STC_TXCLK_DF_SHIFT (0U) #define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) @@ -20712,6 +22681,7 @@ typedef struct { #define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) #define SPDIF_STC_SYSCLK_DF_SHIFT (11U) #define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) +/*! @} */ /*! @@ -20765,9 +22735,7 @@ typedef struct { */ /*! @name SCR - SRC Control Register */ -#define SRC_SCR_LOCKUP_RST_MASK (0x10U) -#define SRC_SCR_LOCKUP_RST_SHIFT (4U) -#define SRC_SCR_LOCKUP_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_LOCKUP_RST_SHIFT)) & SRC_SCR_LOCKUP_RST_MASK) +/*! @{ */ #define SRC_SCR_MASK_WDOG_RST_MASK (0x780U) #define SRC_SCR_MASK_WDOG_RST_SHIFT (7U) #define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK) @@ -20783,8 +22751,10 @@ typedef struct { #define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U) #define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U) #define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK) +/*! @} */ /*! @name SBMR1 - SRC Boot Mode Register 1 */ +/*! @{ */ #define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU) #define SRC_SBMR1_BOOT_CFG1_SHIFT (0U) #define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK) @@ -20797,8 +22767,10 @@ typedef struct { #define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U) #define SRC_SBMR1_BOOT_CFG4_SHIFT (24U) #define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK) +/*! @} */ /*! @name SRSR - SRC Reset Status Register */ +/*! @{ */ #define SRC_SRSR_IPP_RESET_B_MASK (0x1U) #define SRC_SRSR_IPP_RESET_B_SHIFT (0U) #define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK) @@ -20826,8 +22798,10 @@ typedef struct { #define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U) #define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U) #define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK) +/*! @} */ /*! @name SBMR2 - SRC Boot Mode Register 2 */ +/*! @{ */ #define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) #define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) #define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) @@ -20840,14 +22814,17 @@ typedef struct { #define SRC_SBMR2_BMOD_MASK (0x3000000U) #define SRC_SBMR2_BMOD_SHIFT (24U) #define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) +/*! @} */ /*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */ -#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) -#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) -#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) +/*! @{ */ #define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU) #define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U) #define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK) +#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) +/*! @} */ /* The count of SRC_GPR */ #define SRC_GPR_COUNT (10U) @@ -20938,6 +22915,7 @@ typedef struct { */ /*! @name TEMPSENSE0 - Tempsensor Control Register 0 */ +/*! @{ */ #define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U) #define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U) #define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK) @@ -20953,8 +22931,10 @@ typedef struct { #define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U) #define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U) #define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE0_SET - Tempsensor Control Register 0 */ +/*! @{ */ #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U) #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U) #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK) @@ -20970,8 +22950,10 @@ typedef struct { #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U) #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U) #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE0_CLR - Tempsensor Control Register 0 */ +/*! @{ */ #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U) #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U) #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK) @@ -20987,8 +22969,10 @@ typedef struct { #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U) #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U) #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE0_TOG - Tempsensor Control Register 0 */ +/*! @{ */ #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U) #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U) #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK) @@ -21004,58 +22988,75 @@ typedef struct { #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U) #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U) #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE1 - Tempsensor Control Register 1 */ +/*! @{ */ #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU) #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U) #define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK) +/*! @} */ /*! @name TEMPSENSE1_SET - Tempsensor Control Register 1 */ +/*! @{ */ #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU) #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U) #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK) +/*! @} */ /*! @name TEMPSENSE1_CLR - Tempsensor Control Register 1 */ +/*! @{ */ #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU) #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U) #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) +/*! @} */ /*! @name TEMPSENSE1_TOG - Tempsensor Control Register 1 */ +/*! @{ */ #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU) #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U) #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) +/*! @} */ /*! @name TEMPSENSE2 - Tempsensor Control Register 2 */ +/*! @{ */ #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU) #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U) #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK) #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U) #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U) #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE2_SET - Tempsensor Control Register 2 */ +/*! @{ */ #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU) #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U) #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK) #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U) #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U) #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE2_CLR - Tempsensor Control Register 2 */ +/*! @{ */ #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU) #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U) #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK) #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U) #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U) #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE2_TOG - Tempsensor Control Register 2 */ +/*! @{ */ #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU) #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U) #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK) #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U) #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U) #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK) +/*! @} */ /*! @@ -21118,54 +23119,67 @@ typedef struct { */ /*! @name COMP1 - Timer Channel Compare Register 1 */ +/*! @{ */ #define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU) #define TMR_COMP1_COMPARISON_1_SHIFT (0U) #define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK) +/*! @} */ /* The count of TMR_COMP1 */ #define TMR_COMP1_COUNT (4U) /*! @name COMP2 - Timer Channel Compare Register 2 */ +/*! @{ */ #define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU) #define TMR_COMP2_COMPARISON_2_SHIFT (0U) #define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK) +/*! @} */ /* The count of TMR_COMP2 */ #define TMR_COMP2_COUNT (4U) /*! @name CAPT - Timer Channel Capture Register */ +/*! @{ */ #define TMR_CAPT_CAPTURE_MASK (0xFFFFU) #define TMR_CAPT_CAPTURE_SHIFT (0U) #define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK) +/*! @} */ /* The count of TMR_CAPT */ #define TMR_CAPT_COUNT (4U) /*! @name LOAD - Timer Channel Load Register */ +/*! @{ */ #define TMR_LOAD_LOAD_MASK (0xFFFFU) #define TMR_LOAD_LOAD_SHIFT (0U) #define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK) +/*! @} */ /* The count of TMR_LOAD */ #define TMR_LOAD_COUNT (4U) /*! @name HOLD - Timer Channel Hold Register */ +/*! @{ */ #define TMR_HOLD_HOLD_MASK (0xFFFFU) #define TMR_HOLD_HOLD_SHIFT (0U) #define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK) +/*! @} */ /* The count of TMR_HOLD */ #define TMR_HOLD_COUNT (4U) /*! @name CNTR - Timer Channel Counter Register */ +/*! @{ */ #define TMR_CNTR_COUNTER_MASK (0xFFFFU) #define TMR_CNTR_COUNTER_SHIFT (0U) #define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK) +/*! @} */ /* The count of TMR_CNTR */ #define TMR_CNTR_COUNT (4U) /*! @name CTRL - Timer Channel Control Register */ +/*! @{ */ #define TMR_CTRL_OUTMODE_MASK (0x7U) #define TMR_CTRL_OUTMODE_SHIFT (0U) #define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK) @@ -21190,11 +23204,13 @@ typedef struct { #define TMR_CTRL_CM_MASK (0xE000U) #define TMR_CTRL_CM_SHIFT (13U) #define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK) +/*! @} */ /* The count of TMR_CTRL */ #define TMR_CTRL_COUNT (4U) /*! @name SCTRL - Timer Channel Status and Control Register */ +/*! @{ */ #define TMR_SCTRL_OEN_MASK (0x1U) #define TMR_SCTRL_OEN_SHIFT (0U) #define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK) @@ -21240,27 +23256,33 @@ typedef struct { #define TMR_SCTRL_TCF_MASK (0x8000U) #define TMR_SCTRL_TCF_SHIFT (15U) #define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK) +/*! @} */ /* The count of TMR_SCTRL */ #define TMR_SCTRL_COUNT (4U) /*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */ +/*! @{ */ #define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU) #define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U) #define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK) +/*! @} */ /* The count of TMR_CMPLD1 */ #define TMR_CMPLD1_COUNT (4U) /*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */ +/*! @{ */ #define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU) #define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U) #define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK) +/*! @} */ /* The count of TMR_CMPLD2 */ #define TMR_CMPLD2_COUNT (4U) /*! @name CSCTRL - Timer Channel Comparator Status and Control Register */ +/*! @{ */ #define TMR_CSCTRL_CL1_MASK (0x3U) #define TMR_CSCTRL_CL1_SHIFT (0U) #define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK) @@ -21297,22 +23319,26 @@ typedef struct { #define TMR_CSCTRL_DBG_EN_MASK (0xC000U) #define TMR_CSCTRL_DBG_EN_SHIFT (14U) #define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK) +/*! @} */ /* The count of TMR_CSCTRL */ #define TMR_CSCTRL_COUNT (4U) /*! @name FILT - Timer Channel Input Filter Register */ +/*! @{ */ #define TMR_FILT_FILT_PER_MASK (0xFFU) #define TMR_FILT_FILT_PER_SHIFT (0U) #define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK) #define TMR_FILT_FILT_CNT_MASK (0x700U) #define TMR_FILT_FILT_CNT_SHIFT (8U) #define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK) +/*! @} */ /* The count of TMR_FILT */ #define TMR_FILT_COUNT (4U) /*! @name DMA - Timer Channel DMA Enable Register */ +/*! @{ */ #define TMR_DMA_IEFDE_MASK (0x1U) #define TMR_DMA_IEFDE_SHIFT (0U) #define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK) @@ -21322,14 +23348,17 @@ typedef struct { #define TMR_DMA_CMPLD2DE_MASK (0x4U) #define TMR_DMA_CMPLD2DE_SHIFT (2U) #define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK) +/*! @} */ /* The count of TMR_DMA */ #define TMR_DMA_COUNT (4U) /*! @name ENBL - Timer Channel Enable Register */ +/*! @{ */ #define TMR_ENBL_ENBL_MASK (0xFU) #define TMR_ENBL_ENBL_SHIFT (0U) #define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK) +/*! @} */ /* The count of TMR_ENBL */ #define TMR_ENBL_COUNT (4U) @@ -21454,6 +23483,7 @@ typedef struct { */ /*! @name MCTL - Miscellaneous Control Register */ +/*! @{ */ #define TRNG_MCTL_SAMP_MODE_MASK (0x3U) #define TRNG_MCTL_SAMP_MODE_SHIFT (0U) #define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK) @@ -21496,173 +23526,223 @@ typedef struct { #define TRNG_MCTL_PRGM_MASK (0x10000U) #define TRNG_MCTL_PRGM_SHIFT (16U) #define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) +/*! @} */ /*! @name SCMISC - Statistical Check Miscellaneous Register */ +/*! @{ */ #define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) #define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) #define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) #define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) #define TRNG_SCMISC_RTY_CT_SHIFT (16U) #define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) +/*! @} */ /*! @name PKRRNG - Poker Range Register */ +/*! @{ */ #define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU) #define TRNG_PKRRNG_PKR_RNG_SHIFT (0U) #define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK) +/*! @} */ /*! @name PKRMAX - Poker Maximum Limit Register */ +/*! @{ */ #define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU) #define TRNG_PKRMAX_PKR_MAX_SHIFT (0U) #define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK) +/*! @} */ /*! @name PKRSQ - Poker Square Calculation Result Register */ +/*! @{ */ #define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU) #define TRNG_PKRSQ_PKR_SQ_SHIFT (0U) #define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK) +/*! @} */ /*! @name SDCTL - Seed Control Register */ +/*! @{ */ #define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) #define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) #define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) #define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) #define TRNG_SDCTL_ENT_DLY_SHIFT (16U) #define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) +/*! @} */ /*! @name SBLIM - Sparse Bit Limit Register */ +/*! @{ */ #define TRNG_SBLIM_SB_LIM_MASK (0x3FFU) #define TRNG_SBLIM_SB_LIM_SHIFT (0U) #define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK) +/*! @} */ /*! @name TOTSAM - Total Samples Register */ +/*! @{ */ #define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU) #define TRNG_TOTSAM_TOT_SAM_SHIFT (0U) #define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK) +/*! @} */ /*! @name FRQMIN - Frequency Count Minimum Limit Register */ +/*! @{ */ #define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) #define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) #define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) +/*! @} */ /*! @name FRQCNT - Frequency Count Register */ +/*! @{ */ #define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) #define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) #define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) +/*! @} */ /*! @name FRQMAX - Frequency Count Maximum Limit Register */ +/*! @{ */ #define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) #define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) #define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) +/*! @} */ /*! @name SCMC - Statistical Check Monobit Count Register */ +/*! @{ */ #define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) #define TRNG_SCMC_MONO_CT_SHIFT (0U) #define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) +/*! @} */ /*! @name SCML - Statistical Check Monobit Limit Register */ +/*! @{ */ #define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) #define TRNG_SCML_MONO_MAX_SHIFT (0U) #define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) #define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) #define TRNG_SCML_MONO_RNG_SHIFT (16U) #define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) +/*! @} */ /*! @name SCR1C - Statistical Check Run Length 1 Count Register */ +/*! @{ */ #define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) #define TRNG_SCR1C_R1_0_CT_SHIFT (0U) #define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) #define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) #define TRNG_SCR1C_R1_1_CT_SHIFT (16U) #define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) +/*! @} */ /*! @name SCR1L - Statistical Check Run Length 1 Limit Register */ +/*! @{ */ #define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) #define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) #define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) #define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) #define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) #define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) +/*! @} */ /*! @name SCR2C - Statistical Check Run Length 2 Count Register */ +/*! @{ */ #define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) #define TRNG_SCR2C_R2_0_CT_SHIFT (0U) #define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) #define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) #define TRNG_SCR2C_R2_1_CT_SHIFT (16U) #define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) +/*! @} */ /*! @name SCR2L - Statistical Check Run Length 2 Limit Register */ +/*! @{ */ #define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) #define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) #define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) #define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) #define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) #define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) +/*! @} */ /*! @name SCR3C - Statistical Check Run Length 3 Count Register */ +/*! @{ */ #define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) #define TRNG_SCR3C_R3_0_CT_SHIFT (0U) #define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) #define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) #define TRNG_SCR3C_R3_1_CT_SHIFT (16U) #define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) +/*! @} */ /*! @name SCR3L - Statistical Check Run Length 3 Limit Register */ +/*! @{ */ #define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) #define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) #define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) #define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) #define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) #define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) +/*! @} */ /*! @name SCR4C - Statistical Check Run Length 4 Count Register */ +/*! @{ */ #define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU) #define TRNG_SCR4C_R4_0_CT_SHIFT (0U) #define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK) #define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U) #define TRNG_SCR4C_R4_1_CT_SHIFT (16U) #define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK) +/*! @} */ /*! @name SCR4L - Statistical Check Run Length 4 Limit Register */ +/*! @{ */ #define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU) #define TRNG_SCR4L_RUN4_MAX_SHIFT (0U) #define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK) #define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U) #define TRNG_SCR4L_RUN4_RNG_SHIFT (16U) #define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK) +/*! @} */ /*! @name SCR5C - Statistical Check Run Length 5 Count Register */ +/*! @{ */ #define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU) #define TRNG_SCR5C_R5_0_CT_SHIFT (0U) #define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK) #define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) #define TRNG_SCR5C_R5_1_CT_SHIFT (16U) #define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK) +/*! @} */ /*! @name SCR5L - Statistical Check Run Length 5 Limit Register */ +/*! @{ */ #define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU) #define TRNG_SCR5L_RUN5_MAX_SHIFT (0U) #define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK) #define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U) #define TRNG_SCR5L_RUN5_RNG_SHIFT (16U) #define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK) +/*! @} */ /*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */ +/*! @{ */ #define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU) #define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U) #define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK) #define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U) #define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U) #define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK) +/*! @} */ /*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */ +/*! @{ */ #define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU) #define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U) #define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK) #define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U) #define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U) #define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK) +/*! @} */ /*! @name STATUS - Status Register */ +/*! @{ */ #define TRNG_STATUS_TF1BR0_MASK (0x1U) #define TRNG_STATUS_TF1BR0_SHIFT (0U) #define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) @@ -21714,80 +23794,100 @@ typedef struct { #define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) #define TRNG_STATUS_RETRY_CT_SHIFT (16U) #define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) +/*! @} */ /*! @name ENT - Entropy Read Register */ +/*! @{ */ #define TRNG_ENT_ENT_MASK (0xFFFFFFFFU) #define TRNG_ENT_ENT_SHIFT (0U) #define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK) +/*! @} */ /* The count of TRNG_ENT */ #define TRNG_ENT_COUNT (16U) /*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */ +/*! @{ */ #define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU) #define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U) #define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK) #define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U) #define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK) +/*! @} */ /*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */ +/*! @{ */ #define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU) #define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U) #define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK) #define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U) #define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK) +/*! @} */ /*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */ +/*! @{ */ #define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU) #define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U) #define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK) #define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U) #define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK) +/*! @} */ /*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */ +/*! @{ */ #define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU) #define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U) #define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK) #define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U) #define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK) +/*! @} */ /*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */ +/*! @{ */ #define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU) #define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U) #define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK) #define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U) #define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK) +/*! @} */ /*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */ +/*! @{ */ #define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU) #define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U) #define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK) #define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U) #define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK) +/*! @} */ /*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */ +/*! @{ */ #define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU) #define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U) #define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK) #define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U) #define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK) +/*! @} */ /*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */ +/*! @{ */ #define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU) #define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U) #define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK) #define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U) #define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK) +/*! @} */ /*! @name SEC_CFG - Security Configuration Register */ +/*! @{ */ #define TRNG_SEC_CFG_UNUSED0_MASK (0x1U) #define TRNG_SEC_CFG_UNUSED0_SHIFT (0U) #define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK) @@ -21797,8 +23897,10 @@ typedef struct { #define TRNG_SEC_CFG_UNUSED2_MASK (0x4U) #define TRNG_SEC_CFG_UNUSED2_SHIFT (2U) #define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK) +/*! @} */ /*! @name INT_CTRL - Interrupt Control Register */ +/*! @{ */ #define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) #define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) #define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) @@ -21811,8 +23913,10 @@ typedef struct { #define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U) #define TRNG_INT_CTRL_UNUSED_SHIFT (3U) #define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK) +/*! @} */ /*! @name INT_MASK - Mask Register */ +/*! @{ */ #define TRNG_INT_MASK_HW_ERR_MASK (0x1U) #define TRNG_INT_MASK_HW_ERR_SHIFT (0U) #define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) @@ -21822,8 +23926,10 @@ typedef struct { #define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) #define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) #define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) +/*! @} */ /*! @name INT_STATUS - Interrupt Status Register */ +/*! @{ */ #define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) #define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) #define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) @@ -21833,8 +23939,10 @@ typedef struct { #define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) #define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) #define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) +/*! @} */ /*! @name VID1 - Version ID Register (MS) */ +/*! @{ */ #define TRNG_VID1_MIN_REV_MASK (0xFFU) #define TRNG_VID1_MIN_REV_SHIFT (0U) #define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK) @@ -21844,8 +23952,10 @@ typedef struct { #define TRNG_VID1_IP_ID_MASK (0xFFFF0000U) #define TRNG_VID1_IP_ID_SHIFT (16U) #define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK) +/*! @} */ /*! @name VID2 - Version ID Register (LS) */ +/*! @{ */ #define TRNG_VID2_CONFIG_OPT_MASK (0xFFU) #define TRNG_VID2_CONFIG_OPT_SHIFT (0U) #define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK) @@ -21858,6 +23968,7 @@ typedef struct { #define TRNG_VID2_ERA_MASK (0xFF000000U) #define TRNG_VID2_ERA_SHIFT (24U) #define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) +/*! @} */ /*! @@ -21893,9 +24004,9 @@ typedef struct { /** TSC - Register Layout Typedef */ typedef struct { - __IO uint32_t BASIC_SETTING; /**< PS Input Buffer Address, offset: 0x0 */ + __IO uint32_t BASIC_SETTING; /**< , offset: 0x0 */ uint8_t RESERVED_0[12]; - __IO uint32_t PS_INPUT_BUFFER_ADDR; /**< PS Input Buffer Address, offset: 0x10 */ + __IO uint32_t PRE_CHARGE_TIME; /**< , offset: 0x10 */ uint8_t RESERVED_1[12]; __IO uint32_t FLOW_CONTROL; /**< Flow Control, offset: 0x20 */ uint8_t RESERVED_2[12]; @@ -21921,7 +24032,8 @@ typedef struct { * @{ */ -/*! @name BASIC_SETTING - PS Input Buffer Address */ +/*! @name BASIC_SETTING - */ +/*! @{ */ #define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U) #define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U) #define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK) @@ -21931,13 +24043,17 @@ typedef struct { #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U) #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U) #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK) +/*! @} */ -/*! @name PS_INPUT_BUFFER_ADDR - PS Input Buffer Address */ -#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU) -#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT (0U) -#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT)) & TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK) +/*! @name PRE_CHARGE_TIME - */ +/*! @{ */ +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU) +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT (0U) +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT)) & TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK) +/*! @} */ /*! @name FLOW_CONTROL - Flow Control */ +/*! @{ */ #define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U) #define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U) #define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK) @@ -21953,16 +24069,20 @@ typedef struct { #define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U) #define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U) #define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK) +/*! @} */ /*! @name MEASEURE_VALUE - Measure Value */ +/*! @{ */ #define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU) #define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U) #define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK) #define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U) #define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U) #define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK) +/*! @} */ /*! @name INT_EN - Interrupt Enable */ +/*! @{ */ #define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U) #define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U) #define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK) @@ -21972,8 +24092,10 @@ typedef struct { #define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U) #define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U) #define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK) +/*! @} */ /*! @name INT_SIG_EN - Interrupt Signal Enable */ +/*! @{ */ #define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U) #define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U) #define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK) @@ -21986,8 +24108,10 @@ typedef struct { #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U) #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U) #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK) +/*! @} */ /*! @name INT_STATUS - Intterrupt Status */ +/*! @{ */ #define TSC_INT_STATUS_MEASURE_MASK (0x1U) #define TSC_INT_STATUS_MEASURE_SHIFT (0U) #define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK) @@ -22000,8 +24124,10 @@ typedef struct { #define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U) #define TSC_INT_STATUS_IDLE_SW_SHIFT (12U) #define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK) +/*! @} */ /*! @name DEBUG_MODE - */ +/*! @{ */ #define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU) #define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U) #define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK) @@ -22023,8 +24149,10 @@ typedef struct { #define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U) #define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U) #define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK) +/*! @} */ /*! @name DEBUG_MODE2 - */ +/*! @{ */ #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U) #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U) #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK) @@ -22091,6 +24219,7 @@ typedef struct { #define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U) #define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U) #define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK) +/*! @} */ /*! @@ -22197,6 +24326,7 @@ typedef struct { */ /*! @name ID - Identification register */ +/*! @{ */ #define USB_ID_ID_MASK (0x3FU) #define USB_ID_ID_SHIFT (0U) #define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) @@ -22206,8 +24336,10 @@ typedef struct { #define USB_ID_REVISION_MASK (0xFF0000U) #define USB_ID_REVISION_SHIFT (16U) #define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) +/*! @} */ /*! @name HWGENERAL - Hardware General */ +/*! @{ */ #define USB_HWGENERAL_PHYW_MASK (0x30U) #define USB_HWGENERAL_PHYW_SHIFT (4U) #define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) @@ -22217,45 +24349,57 @@ typedef struct { #define USB_HWGENERAL_SM_MASK (0x600U) #define USB_HWGENERAL_SM_SHIFT (9U) #define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) +/*! @} */ /*! @name HWHOST - Host Hardware Parameters */ +/*! @{ */ #define USB_HWHOST_HC_MASK (0x1U) #define USB_HWHOST_HC_SHIFT (0U) #define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) #define USB_HWHOST_NPORT_MASK (0xEU) #define USB_HWHOST_NPORT_SHIFT (1U) #define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) +/*! @} */ /*! @name HWDEVICE - Device Hardware Parameters */ +/*! @{ */ #define USB_HWDEVICE_DC_MASK (0x1U) #define USB_HWDEVICE_DC_SHIFT (0U) #define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) #define USB_HWDEVICE_DEVEP_MASK (0x3EU) #define USB_HWDEVICE_DEVEP_SHIFT (1U) #define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) +/*! @} */ /*! @name HWTXBUF - TX Buffer Hardware Parameters */ +/*! @{ */ #define USB_HWTXBUF_TXBURST_MASK (0xFFU) #define USB_HWTXBUF_TXBURST_SHIFT (0U) #define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) #define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) #define USB_HWTXBUF_TXCHANADD_SHIFT (16U) #define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) +/*! @} */ /*! @name HWRXBUF - RX Buffer Hardware Parameters */ +/*! @{ */ #define USB_HWRXBUF_RXBURST_MASK (0xFFU) #define USB_HWRXBUF_RXBURST_SHIFT (0U) #define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) #define USB_HWRXBUF_RXADD_MASK (0xFF00U) #define USB_HWRXBUF_RXADD_SHIFT (8U) #define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) +/*! @} */ /*! @name GPTIMER0LD - General Purpose Timer #0 Load */ +/*! @{ */ #define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) #define USB_GPTIMER0LD_GPTLD_SHIFT (0U) #define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) +/*! @} */ /*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ +/*! @{ */ #define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) #define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) #define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) @@ -22268,13 +24412,17 @@ typedef struct { #define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) #define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) #define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) +/*! @} */ /*! @name GPTIMER1LD - General Purpose Timer #1 Load */ +/*! @{ */ #define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) #define USB_GPTIMER1LD_GPTLD_SHIFT (0U) #define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) +/*! @} */ /*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ +/*! @{ */ #define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) #define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) #define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) @@ -22287,23 +24435,31 @@ typedef struct { #define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) #define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) #define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) +/*! @} */ /*! @name SBUSCFG - System Bus Config */ +/*! @{ */ #define USB_SBUSCFG_AHBBRST_MASK (0x7U) #define USB_SBUSCFG_AHBBRST_SHIFT (0U) #define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) +/*! @} */ /*! @name CAPLENGTH - Capability Registers Length */ +/*! @{ */ #define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) #define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) #define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) +/*! @} */ /*! @name HCIVERSION - Host Controller Interface Version */ +/*! @{ */ #define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) #define USB_HCIVERSION_HCIVERSION_SHIFT (0U) #define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) +/*! @} */ /*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ #define USB_HCSPARAMS_N_PORTS_MASK (0xFU) #define USB_HCSPARAMS_N_PORTS_SHIFT (0U) #define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) @@ -22325,8 +24481,10 @@ typedef struct { #define USB_HCSPARAMS_N_TT_MASK (0xF000000U) #define USB_HCSPARAMS_N_TT_SHIFT (24U) #define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) +/*! @} */ /*! @name HCCPARAMS - Host Controller Capability Parameters */ +/*! @{ */ #define USB_HCCPARAMS_ADC_MASK (0x1U) #define USB_HCCPARAMS_ADC_SHIFT (0U) #define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) @@ -22342,13 +24500,17 @@ typedef struct { #define USB_HCCPARAMS_EECP_MASK (0xFF00U) #define USB_HCCPARAMS_EECP_SHIFT (8U) #define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) +/*! @} */ /*! @name DCIVERSION - Device Controller Interface Version */ +/*! @{ */ #define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) #define USB_DCIVERSION_DCIVERSION_SHIFT (0U) #define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) +/*! @} */ /*! @name DCCPARAMS - Device Controller Capability Parameters */ +/*! @{ */ #define USB_DCCPARAMS_DEN_MASK (0x1FU) #define USB_DCCPARAMS_DEN_SHIFT (0U) #define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) @@ -22358,8 +24520,10 @@ typedef struct { #define USB_DCCPARAMS_HC_MASK (0x100U) #define USB_DCCPARAMS_HC_SHIFT (8U) #define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) +/*! @} */ /*! @name USBCMD - USB Command Register */ +/*! @{ */ #define USB_USBCMD_RS_MASK (0x1U) #define USB_USBCMD_RS_SHIFT (0U) #define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) @@ -22396,8 +24560,10 @@ typedef struct { #define USB_USBCMD_ITC_MASK (0xFF0000U) #define USB_USBCMD_ITC_SHIFT (16U) #define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) +/*! @} */ /*! @name USBSTS - USB Status Register */ +/*! @{ */ #define USB_USBSTS_UI_MASK (0x1U) #define USB_USBSTS_UI_SHIFT (0U) #define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) @@ -22449,8 +24615,10 @@ typedef struct { #define USB_USBSTS_TI1_MASK (0x2000000U) #define USB_USBSTS_TI1_SHIFT (25U) #define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) +/*! @} */ /*! @name USBINTR - Interrupt Enable Register */ +/*! @{ */ #define USB_USBINTR_UE_MASK (0x1U) #define USB_USBINTR_UE_SHIFT (0U) #define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) @@ -22496,44 +24664,58 @@ typedef struct { #define USB_USBINTR_TIE1_MASK (0x2000000U) #define USB_USBINTR_TIE1_SHIFT (25U) #define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) +/*! @} */ /*! @name FRINDEX - USB Frame Index */ +/*! @{ */ #define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) #define USB_FRINDEX_FRINDEX_SHIFT (0U) #define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) +/*! @} */ /*! @name DEVICEADDR - Device Address */ +/*! @{ */ #define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) #define USB_DEVICEADDR_USBADRA_SHIFT (24U) #define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) #define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) #define USB_DEVICEADDR_USBADR_SHIFT (25U) #define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) +/*! @} */ /*! @name PERIODICLISTBASE - Frame List Base Address */ +/*! @{ */ #define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) #define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) #define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) +/*! @} */ /*! @name ASYNCLISTADDR - Next Asynch. Address */ +/*! @{ */ #define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) #define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) #define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) +/*! @} */ /*! @name ENDPTLISTADDR - Endpoint List Address */ +/*! @{ */ #define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) #define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) #define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) +/*! @} */ /*! @name BURSTSIZE - Programmable Burst Size */ +/*! @{ */ #define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) #define USB_BURSTSIZE_RXPBURST_SHIFT (0U) #define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) #define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) #define USB_BURSTSIZE_TXPBURST_SHIFT (8U) #define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) +/*! @} */ /*! @name TXFILLTUNING - TX FIFO Fill Tuning */ +/*! @{ */ #define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) #define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) #define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) @@ -22543,29 +24725,37 @@ typedef struct { #define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) #define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) #define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) +/*! @} */ /*! @name ENDPTNAK - Endpoint NAK */ +/*! @{ */ #define USB_ENDPTNAK_EPRN_MASK (0xFFU) #define USB_ENDPTNAK_EPRN_SHIFT (0U) #define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) #define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) #define USB_ENDPTNAK_EPTN_SHIFT (16U) #define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) +/*! @} */ /*! @name ENDPTNAKEN - Endpoint NAK Enable */ +/*! @{ */ #define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) #define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) #define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) #define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) #define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) #define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) +/*! @} */ /*! @name CONFIGFLAG - Configure Flag Register */ +/*! @{ */ #define USB_CONFIGFLAG_CF_MASK (0x1U) #define USB_CONFIGFLAG_CF_SHIFT (0U) #define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) +/*! @} */ /*! @name PORTSC1 - Port Status & Control */ +/*! @{ */ #define USB_PORTSC1_CCS_MASK (0x1U) #define USB_PORTSC1_CCS_SHIFT (0U) #define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) @@ -22641,8 +24831,10 @@ typedef struct { #define USB_PORTSC1_PTS_1_MASK (0xC0000000U) #define USB_PORTSC1_PTS_1_SHIFT (30U) #define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) +/*! @} */ /*! @name OTGSC - On-The-Go Status & control */ +/*! @{ */ #define USB_OTGSC_VD_MASK (0x1U) #define USB_OTGSC_VD_SHIFT (0U) #define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) @@ -22721,8 +24913,10 @@ typedef struct { #define USB_OTGSC_DPIE_MASK (0x40000000U) #define USB_OTGSC_DPIE_SHIFT (30U) #define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) +/*! @} */ /*! @name USBMODE - USB Device Mode */ +/*! @{ */ #define USB_USBMODE_CM_MASK (0x3U) #define USB_USBMODE_CM_SHIFT (0U) #define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) @@ -22735,45 +24929,57 @@ typedef struct { #define USB_USBMODE_SDIS_MASK (0x10U) #define USB_USBMODE_SDIS_SHIFT (4U) #define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) +/*! @} */ /*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ +/*! @{ */ #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) +/*! @} */ /*! @name ENDPTPRIME - Endpoint Prime */ +/*! @{ */ #define USB_ENDPTPRIME_PERB_MASK (0xFFU) #define USB_ENDPTPRIME_PERB_SHIFT (0U) #define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) #define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) #define USB_ENDPTPRIME_PETB_SHIFT (16U) #define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) +/*! @} */ /*! @name ENDPTFLUSH - Endpoint Flush */ +/*! @{ */ #define USB_ENDPTFLUSH_FERB_MASK (0xFFU) #define USB_ENDPTFLUSH_FERB_SHIFT (0U) #define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) #define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) #define USB_ENDPTFLUSH_FETB_SHIFT (16U) #define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) +/*! @} */ /*! @name ENDPTSTAT - Endpoint Status */ +/*! @{ */ #define USB_ENDPTSTAT_ERBR_MASK (0xFFU) #define USB_ENDPTSTAT_ERBR_SHIFT (0U) #define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) #define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) #define USB_ENDPTSTAT_ETBR_SHIFT (16U) #define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) +/*! @} */ /*! @name ENDPTCOMPLETE - Endpoint Complete */ +/*! @{ */ #define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) #define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) #define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) #define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) #define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) #define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) +/*! @} */ /*! @name ENDPTCTRL0 - Endpoint Control0 */ +/*! @{ */ #define USB_ENDPTCTRL0_RXS_MASK (0x1U) #define USB_ENDPTCTRL0_RXS_SHIFT (0U) #define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) @@ -22792,8 +24998,10 @@ typedef struct { #define USB_ENDPTCTRL0_TXE_MASK (0x800000U) #define USB_ENDPTCTRL0_TXE_SHIFT (23U) #define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) +/*! @} */ /*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ +/*! @{ */ #define USB_ENDPTCTRL_RXS_MASK (0x1U) #define USB_ENDPTCTRL_RXS_SHIFT (0U) #define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) @@ -22830,6 +25038,7 @@ typedef struct { #define USB_ENDPTCTRL_TXE_MASK (0x800000U) #define USB_ENDPTCTRL_TXE_SHIFT (23U) #define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) +/*! @} */ /* The count of USB_ENDPTCTRL */ #define USB_ENDPTCTRL_COUNT (7U) @@ -23459,6 +25668,7 @@ typedef struct { */ /*! @name USB_OTGn_CTRL - USB OTG1 Control Register..USB OTG2 Control Register */ +/*! @{ */ #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U) #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U) #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK) @@ -23489,11 +25699,14 @@ typedef struct { #define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U) #define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U) #define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK) +/*! @} */ /*! @name USB_OTGn_PHY_CTRL_0 - OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register */ +/*! @{ */ #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U) #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U) #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK) +/*! @} */ /*! @@ -23572,6 +25785,7 @@ typedef struct { */ /*! @name PWD - USB PHY Power-Down Register */ +/*! @{ */ #define USBPHY_PWD_RSVD0_MASK (0x3FFU) #define USBPHY_PWD_RSVD0_SHIFT (0U) #define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK) @@ -23602,8 +25816,10 @@ typedef struct { #define USBPHY_PWD_RSVD2_MASK (0xFFE00000U) #define USBPHY_PWD_RSVD2_SHIFT (21U) #define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK) +/*! @} */ /*! @name PWD_SET - USB PHY Power-Down Register */ +/*! @{ */ #define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU) #define USBPHY_PWD_SET_RSVD0_SHIFT (0U) #define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK) @@ -23634,8 +25850,10 @@ typedef struct { #define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U) #define USBPHY_PWD_SET_RSVD2_SHIFT (21U) #define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK) +/*! @} */ /*! @name PWD_CLR - USB PHY Power-Down Register */ +/*! @{ */ #define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU) #define USBPHY_PWD_CLR_RSVD0_SHIFT (0U) #define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK) @@ -23666,8 +25884,10 @@ typedef struct { #define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U) #define USBPHY_PWD_CLR_RSVD2_SHIFT (21U) #define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK) +/*! @} */ /*! @name PWD_TOG - USB PHY Power-Down Register */ +/*! @{ */ #define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU) #define USBPHY_PWD_TOG_RSVD0_SHIFT (0U) #define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK) @@ -23698,8 +25918,10 @@ typedef struct { #define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U) #define USBPHY_PWD_TOG_RSVD2_SHIFT (21U) #define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK) +/*! @} */ /*! @name TX - USB PHY Transmitter Control Register */ +/*! @{ */ #define USBPHY_TX_D_CAL_MASK (0xFU) #define USBPHY_TX_D_CAL_SHIFT (0U) #define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) @@ -23724,8 +25946,10 @@ typedef struct { #define USBPHY_TX_RSVD5_MASK (0xE0000000U) #define USBPHY_TX_RSVD5_SHIFT (29U) #define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK) +/*! @} */ /*! @name TX_SET - USB PHY Transmitter Control Register */ +/*! @{ */ #define USBPHY_TX_SET_D_CAL_MASK (0xFU) #define USBPHY_TX_SET_D_CAL_SHIFT (0U) #define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) @@ -23750,8 +25974,10 @@ typedef struct { #define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U) #define USBPHY_TX_SET_RSVD5_SHIFT (29U) #define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK) +/*! @} */ /*! @name TX_CLR - USB PHY Transmitter Control Register */ +/*! @{ */ #define USBPHY_TX_CLR_D_CAL_MASK (0xFU) #define USBPHY_TX_CLR_D_CAL_SHIFT (0U) #define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) @@ -23776,8 +26002,10 @@ typedef struct { #define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U) #define USBPHY_TX_CLR_RSVD5_SHIFT (29U) #define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK) +/*! @} */ /*! @name TX_TOG - USB PHY Transmitter Control Register */ +/*! @{ */ #define USBPHY_TX_TOG_D_CAL_MASK (0xFU) #define USBPHY_TX_TOG_D_CAL_SHIFT (0U) #define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) @@ -23802,8 +26030,10 @@ typedef struct { #define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U) #define USBPHY_TX_TOG_RSVD5_SHIFT (29U) #define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK) +/*! @} */ /*! @name RX - USB PHY Receiver Control Register */ +/*! @{ */ #define USBPHY_RX_ENVADJ_MASK (0x7U) #define USBPHY_RX_ENVADJ_SHIFT (0U) #define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) @@ -23822,8 +26052,10 @@ typedef struct { #define USBPHY_RX_RSVD2_MASK (0xFF800000U) #define USBPHY_RX_RSVD2_SHIFT (23U) #define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK) +/*! @} */ /*! @name RX_SET - USB PHY Receiver Control Register */ +/*! @{ */ #define USBPHY_RX_SET_ENVADJ_MASK (0x7U) #define USBPHY_RX_SET_ENVADJ_SHIFT (0U) #define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) @@ -23842,8 +26074,10 @@ typedef struct { #define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U) #define USBPHY_RX_SET_RSVD2_SHIFT (23U) #define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK) +/*! @} */ /*! @name RX_CLR - USB PHY Receiver Control Register */ +/*! @{ */ #define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) #define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) #define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) @@ -23862,8 +26096,10 @@ typedef struct { #define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U) #define USBPHY_RX_CLR_RSVD2_SHIFT (23U) #define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK) +/*! @} */ /*! @name RX_TOG - USB PHY Receiver Control Register */ +/*! @{ */ #define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) #define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) #define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) @@ -23882,8 +26118,10 @@ typedef struct { #define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U) #define USBPHY_RX_TOG_RSVD2_SHIFT (23U) #define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK) +/*! @} */ /*! @name CTRL - USB PHY General Control Register */ +/*! @{ */ #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) @@ -23977,8 +26215,10 @@ typedef struct { #define USBPHY_CTRL_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SFTRST_SHIFT (31U) #define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ /*! @name CTRL_SET - USB PHY General Control Register */ +/*! @{ */ #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) @@ -24072,8 +26312,10 @@ typedef struct { #define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) #define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ /*! @name CTRL_CLR - USB PHY General Control Register */ +/*! @{ */ #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) @@ -24167,8 +26409,10 @@ typedef struct { #define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) #define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ /*! @name CTRL_TOG - USB PHY General Control Register */ +/*! @{ */ #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) @@ -24262,8 +26506,10 @@ typedef struct { #define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) #define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ /*! @name STATUS - USB PHY Status Register */ +/*! @{ */ #define USBPHY_STATUS_RSVD0_MASK (0x7U) #define USBPHY_STATUS_RSVD0_SHIFT (0U) #define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK) @@ -24291,8 +26537,10 @@ typedef struct { #define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U) #define USBPHY_STATUS_RSVD4_SHIFT (11U) #define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK) +/*! @} */ /*! @name DEBUG - USB PHY Debug Register */ +/*! @{ */ #define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK) @@ -24338,8 +26586,10 @@ typedef struct { #define USBPHY_DEBUG_RSVD3_MASK (0x80000000U) #define USBPHY_DEBUG_RSVD3_SHIFT (31U) #define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK) +/*! @} */ /*! @name DEBUG_SET - USB PHY Debug Register */ +/*! @{ */ #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK) @@ -24385,8 +26635,10 @@ typedef struct { #define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U) #define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U) #define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK) +/*! @} */ /*! @name DEBUG_CLR - USB PHY Debug Register */ +/*! @{ */ #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK) @@ -24432,8 +26684,10 @@ typedef struct { #define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U) #define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U) #define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK) +/*! @} */ /*! @name DEBUG_TOG - USB PHY Debug Register */ +/*! @{ */ #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK) @@ -24479,8 +26733,10 @@ typedef struct { #define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U) #define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U) #define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK) +/*! @} */ /*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */ +/*! @{ */ #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU) #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U) #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) @@ -24490,8 +26746,10 @@ typedef struct { #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U) #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U) #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) +/*! @} */ /*! @name DEBUG1 - UTMI Debug Status Register 1 */ +/*! @{ */ #define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU) #define USBPHY_DEBUG1_RSVD0_SHIFT (0U) #define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK) @@ -24501,8 +26759,10 @@ typedef struct { #define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U) #define USBPHY_DEBUG1_RSVD1_SHIFT (15U) #define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK) +/*! @} */ /*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ +/*! @{ */ #define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU) #define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U) #define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK) @@ -24512,8 +26772,10 @@ typedef struct { #define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U) #define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U) #define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK) +/*! @} */ /*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ +/*! @{ */ #define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU) #define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U) #define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK) @@ -24523,8 +26785,10 @@ typedef struct { #define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U) #define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U) #define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK) +/*! @} */ /*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ +/*! @{ */ #define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU) #define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U) #define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK) @@ -24534,8 +26798,10 @@ typedef struct { #define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U) #define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U) #define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK) +/*! @} */ /*! @name VERSION - UTMI RTL Version */ +/*! @{ */ #define USBPHY_VERSION_STEP_MASK (0xFFFFU) #define USBPHY_VERSION_STEP_SHIFT (0U) #define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) @@ -24545,6 +26811,7 @@ typedef struct { #define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) #define USBPHY_VERSION_MAJOR_SHIFT (24U) #define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) +/*! @} */ /*! @@ -24624,6 +26891,7 @@ typedef struct { */ /*! @name VBUS_DETECT - USB VBUS Detect Register */ +/*! @{ */ #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK) @@ -24636,11 +26904,13 @@ typedef struct { #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U) #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U) #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK) +/*! @} */ /* The count of USB_ANALOG_VBUS_DETECT */ #define USB_ANALOG_VBUS_DETECT_COUNT (2U) /*! @name VBUS_DETECT_SET - USB VBUS Detect Register */ +/*! @{ */ #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) @@ -24653,11 +26923,13 @@ typedef struct { #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U) #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U) #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK) +/*! @} */ /* The count of USB_ANALOG_VBUS_DETECT_SET */ #define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U) /*! @name VBUS_DETECT_CLR - USB VBUS Detect Register */ +/*! @{ */ #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) @@ -24670,11 +26942,13 @@ typedef struct { #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U) #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U) #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK) +/*! @} */ /* The count of USB_ANALOG_VBUS_DETECT_CLR */ #define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U) /*! @name VBUS_DETECT_TOG - USB VBUS Detect Register */ +/*! @{ */ #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) @@ -24687,11 +26961,13 @@ typedef struct { #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U) #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U) #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK) +/*! @} */ /* The count of USB_ANALOG_VBUS_DETECT_TOG */ #define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U) /*! @name CHRG_DETECT - USB Charger Detect Register */ +/*! @{ */ #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK) @@ -24701,11 +26977,13 @@ typedef struct { #define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U) #define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U) #define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK) +/*! @} */ /* The count of USB_ANALOG_CHRG_DETECT */ #define USB_ANALOG_CHRG_DETECT_COUNT (2U) /*! @name CHRG_DETECT_SET - USB Charger Detect Register */ +/*! @{ */ #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK) @@ -24715,11 +26993,13 @@ typedef struct { #define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U) #define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U) #define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK) +/*! @} */ /* The count of USB_ANALOG_CHRG_DETECT_SET */ #define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U) /*! @name CHRG_DETECT_CLR - USB Charger Detect Register */ +/*! @{ */ #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK) @@ -24729,11 +27009,13 @@ typedef struct { #define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) #define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U) #define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK) +/*! @} */ /* The count of USB_ANALOG_CHRG_DETECT_CLR */ #define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U) /*! @name CHRG_DETECT_TOG - USB Charger Detect Register */ +/*! @{ */ #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK) @@ -24743,11 +27025,13 @@ typedef struct { #define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) #define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U) #define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK) +/*! @} */ /* The count of USB_ANALOG_CHRG_DETECT_TOG */ #define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U) /*! @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */ +/*! @{ */ #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U) #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U) #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK) @@ -24760,11 +27044,13 @@ typedef struct { #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U) #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U) #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK) +/*! @} */ /* The count of USB_ANALOG_VBUS_DETECT_STAT */ #define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U) /*! @name CHRG_DETECT_STAT - USB Charger Detect Status Register */ +/*! @{ */ #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U) #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U) #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK) @@ -24777,11 +27063,13 @@ typedef struct { #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U) #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U) #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK) +/*! @} */ /* The count of USB_ANALOG_CHRG_DETECT_STAT */ #define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U) /*! @name MISC - USB Misc Register */ +/*! @{ */ #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U) #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U) #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK) @@ -24791,11 +27079,13 @@ typedef struct { #define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U) #define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U) #define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK) +/*! @} */ /* The count of USB_ANALOG_MISC */ #define USB_ANALOG_MISC_COUNT (2U) /*! @name MISC_SET - USB Misc Register */ +/*! @{ */ #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U) #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U) #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK) @@ -24805,11 +27095,13 @@ typedef struct { #define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U) #define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U) #define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK) +/*! @} */ /* The count of USB_ANALOG_MISC_SET */ #define USB_ANALOG_MISC_SET_COUNT (2U) /*! @name MISC_CLR - USB Misc Register */ +/*! @{ */ #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U) #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U) #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK) @@ -24819,11 +27111,13 @@ typedef struct { #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U) #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U) #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK) +/*! @} */ /* The count of USB_ANALOG_MISC_CLR */ #define USB_ANALOG_MISC_CLR_COUNT (2U) /*! @name MISC_TOG - USB Misc Register */ +/*! @{ */ #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U) #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U) #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK) @@ -24833,20 +27127,17 @@ typedef struct { #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U) #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U) #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK) +/*! @} */ /* The count of USB_ANALOG_MISC_TOG */ #define USB_ANALOG_MISC_TOG_COUNT (2U) /*! @name DIGPROG - Chip Silicon Version */ -#define USB_ANALOG_DIGPROG_MINOR_MASK (0xFFU) -#define USB_ANALOG_DIGPROG_MINOR_SHIFT (0U) -#define USB_ANALOG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MINOR_SHIFT)) & USB_ANALOG_DIGPROG_MINOR_MASK) -#define USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U) -#define USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT (8U) -#define USB_ANALOG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK) -#define USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U) -#define USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT (16U) -#define USB_ANALOG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK) +/*! @{ */ +#define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU) +#define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U) +#define USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK) +/*! @} */ /*! @@ -24924,24 +27215,31 @@ typedef struct { */ /*! @name DS_ADDR - DMA System Address */ +/*! @{ */ #define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) #define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) #define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) +/*! @} */ /*! @name BLK_ATT - Block Attributes */ +/*! @{ */ #define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) #define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) #define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) #define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) #define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) #define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) +/*! @} */ /*! @name CMD_ARG - Command Argument */ +/*! @{ */ #define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) #define USDHC_CMD_ARG_CMDARG_SHIFT (0U) #define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) +/*! @} */ /*! @name CMD_XFR_TYP - Command Transfer Type */ +/*! @{ */ #define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) #define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) @@ -24960,33 +27258,45 @@ typedef struct { #define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) #define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) +/*! @} */ /*! @name CMD_RSP0 - Command Response0 */ +/*! @{ */ #define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) #define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) +/*! @} */ /*! @name CMD_RSP1 - Command Response1 */ +/*! @{ */ #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) #define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) +/*! @} */ /*! @name CMD_RSP2 - Command Response2 */ +/*! @{ */ #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) #define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) +/*! @} */ /*! @name CMD_RSP3 - Command Response3 */ +/*! @{ */ #define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) #define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) +/*! @} */ /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ +/*! @{ */ #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) +/*! @} */ /*! @name PRES_STATE - Present State */ +/*! @{ */ #define USDHC_PRES_STATE_CIHB_MASK (0x1U) #define USDHC_PRES_STATE_CIHB_SHIFT (0U) #define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) @@ -25044,8 +27354,10 @@ typedef struct { #define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) #define USDHC_PRES_STATE_DLSL_SHIFT (24U) #define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) +/*! @} */ /*! @name PROT_CTRL - Protocol Control */ +/*! @{ */ #define USDHC_PROT_CTRL_LCTL_MASK (0x1U) #define USDHC_PROT_CTRL_LCTL_SHIFT (0U) #define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) @@ -25097,8 +27409,10 @@ typedef struct { #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) +/*! @} */ /*! @name SYS_CTRL - System Control */ +/*! @{ */ #define USDHC_SYS_CTRL_DVS_MASK (0xF0U) #define USDHC_SYS_CTRL_DVS_SHIFT (4U) #define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) @@ -25126,8 +27440,10 @@ typedef struct { #define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) #define USDHC_SYS_CTRL_RSTT_SHIFT (28U) #define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) +/*! @} */ /*! @name INT_STATUS - Interrupt Status */ +/*! @{ */ #define USDHC_INT_STATUS_CC_MASK (0x1U) #define USDHC_INT_STATUS_CC_SHIFT (0U) #define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) @@ -25191,8 +27507,10 @@ typedef struct { #define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) #define USDHC_INT_STATUS_DMAE_SHIFT (28U) #define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) +/*! @} */ /*! @name INT_STATUS_EN - Interrupt Status Enable */ +/*! @{ */ #define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) #define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) #define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) @@ -25256,8 +27574,10 @@ typedef struct { #define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) #define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) +/*! @} */ /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ +/*! @{ */ #define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) #define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) @@ -25321,8 +27641,10 @@ typedef struct { #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) #define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) +/*! @} */ /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ +/*! @{ */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) @@ -25347,8 +27669,10 @@ typedef struct { #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) +/*! @} */ /*! @name HOST_CTRL_CAP - Host Controller Capabilities */ +/*! @{ */ #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) @@ -25391,8 +27715,10 @@ typedef struct { #define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) #define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) #define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) +/*! @} */ /*! @name WTMK_LVL - Watermark Level */ +/*! @{ */ #define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) #define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) #define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) @@ -25405,8 +27731,10 @@ typedef struct { #define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) #define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) #define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) +/*! @} */ /*! @name MIX_CTRL - Mixer Control */ +/*! @{ */ #define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) #define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) #define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) @@ -25443,8 +27771,10 @@ typedef struct { #define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) #define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) +/*! @} */ /*! @name FORCE_EVENT - Force Event */ +/*! @{ */ #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) #define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) @@ -25496,8 +27826,10 @@ typedef struct { #define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) #define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) +/*! @} */ /*! @name ADMA_ERR_STATUS - ADMA Error Status Register */ +/*! @{ */ #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) #define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) @@ -25507,13 +27839,17 @@ typedef struct { #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) #define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) +/*! @} */ /*! @name ADMA_SYS_ADDR - ADMA System Address */ +/*! @{ */ #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) +/*! @} */ /*! @name DLL_CTRL - DLL (Delay Line) Control */ +/*! @{ */ #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) @@ -25544,8 +27880,10 @@ typedef struct { #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) +/*! @} */ /*! @name DLL_STATUS - DLL Status */ +/*! @{ */ #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) @@ -25558,8 +27896,10 @@ typedef struct { #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) +/*! @} */ /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ +/*! @{ */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) @@ -25584,8 +27924,10 @@ typedef struct { #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) +/*! @} */ /*! @name VEND_SPEC - Vendor Specific Register */ +/*! @{ */ #define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) #define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) #define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) @@ -25604,8 +27946,10 @@ typedef struct { #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) #define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) +/*! @} */ /*! @name MMC_BOOT - MMC Boot Register */ +/*! @{ */ #define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) #define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) @@ -25627,8 +27971,10 @@ typedef struct { #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) +/*! @} */ /*! @name VEND_SPEC2 - Vendor Specific 2 Register */ +/*! @{ */ #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) @@ -25644,11 +27990,16 @@ typedef struct { #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) -#define USDHC_VEND_SPEC2_AHB_RST_MASK (0x4000U) -#define USDHC_VEND_SPEC2_AHB_RST_SHIFT (14U) -#define USDHC_VEND_SPEC2_AHB_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_AHB_RST_SHIFT)) & USDHC_VEND_SPEC2_AHB_RST_MASK) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK (0x2000U) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT (13U) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK) +#define USDHC_VEND_SPEC2_BUS_RST_MASK (0x4000U) +#define USDHC_VEND_SPEC2_BUS_RST_SHIFT (14U) +#define USDHC_VEND_SPEC2_BUS_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK) +/*! @} */ /*! @name TUNING_CTRL - Tuning Control Register */ +/*! @{ */ #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU) #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) #define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) @@ -25664,6 +28015,7 @@ typedef struct { #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) #define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) +/*! @} */ /*! @@ -25720,6 +28072,7 @@ typedef struct { */ /*! @name WCR - Watchdog Control Register */ +/*! @{ */ #define WDOG_WCR_WDZST_MASK (0x1U) #define WDOG_WCR_WDZST_SHIFT (0U) #define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) @@ -25747,13 +28100,17 @@ typedef struct { #define WDOG_WCR_WT_MASK (0xFF00U) #define WDOG_WCR_WT_SHIFT (8U) #define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) +/*! @} */ /*! @name WSR - Watchdog Service Register */ +/*! @{ */ #define WDOG_WSR_WSR_MASK (0xFFFFU) #define WDOG_WSR_WSR_SHIFT (0U) #define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) +/*! @} */ /*! @name WRSR - Watchdog Reset Status Register */ +/*! @{ */ #define WDOG_WRSR_SFTW_MASK (0x1U) #define WDOG_WRSR_SFTW_SHIFT (0U) #define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) @@ -25763,8 +28120,10 @@ typedef struct { #define WDOG_WRSR_POR_MASK (0x10U) #define WDOG_WRSR_POR_SHIFT (4U) #define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) +/*! @} */ /*! @name WICR - Watchdog Interrupt Control Register */ +/*! @{ */ #define WDOG_WICR_WICT_MASK (0xFFU) #define WDOG_WICR_WICT_SHIFT (0U) #define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) @@ -25774,11 +28133,14 @@ typedef struct { #define WDOG_WICR_WIE_MASK (0x8000U) #define WDOG_WICR_WIE_SHIFT (15U) #define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) +/*! @} */ /*! @name WMCR - Watchdog Miscellaneous Control Register */ +/*! @{ */ #define WDOG_WMCR_PDE_MASK (0x1U) #define WDOG_WMCR_PDE_SHIFT (0U) #define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) +/*! @} */ /*! @@ -25898,534 +28260,667 @@ typedef struct { */ /*! @name SEL0 - Crossbar A Select Register 0 */ +/*! @{ */ #define XBARA_SEL0_SEL0_MASK (0x7FU) #define XBARA_SEL0_SEL0_SHIFT (0U) #define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK) #define XBARA_SEL0_SEL1_MASK (0x7F00U) #define XBARA_SEL0_SEL1_SHIFT (8U) #define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK) +/*! @} */ /*! @name SEL1 - Crossbar A Select Register 1 */ +/*! @{ */ #define XBARA_SEL1_SEL2_MASK (0x7FU) #define XBARA_SEL1_SEL2_SHIFT (0U) #define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK) #define XBARA_SEL1_SEL3_MASK (0x7F00U) #define XBARA_SEL1_SEL3_SHIFT (8U) #define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK) +/*! @} */ /*! @name SEL2 - Crossbar A Select Register 2 */ +/*! @{ */ #define XBARA_SEL2_SEL4_MASK (0x7FU) #define XBARA_SEL2_SEL4_SHIFT (0U) #define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK) #define XBARA_SEL2_SEL5_MASK (0x7F00U) #define XBARA_SEL2_SEL5_SHIFT (8U) #define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK) +/*! @} */ /*! @name SEL3 - Crossbar A Select Register 3 */ +/*! @{ */ #define XBARA_SEL3_SEL6_MASK (0x7FU) #define XBARA_SEL3_SEL6_SHIFT (0U) #define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK) #define XBARA_SEL3_SEL7_MASK (0x7F00U) #define XBARA_SEL3_SEL7_SHIFT (8U) #define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK) +/*! @} */ /*! @name SEL4 - Crossbar A Select Register 4 */ +/*! @{ */ #define XBARA_SEL4_SEL8_MASK (0x7FU) #define XBARA_SEL4_SEL8_SHIFT (0U) #define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK) #define XBARA_SEL4_SEL9_MASK (0x7F00U) #define XBARA_SEL4_SEL9_SHIFT (8U) #define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK) +/*! @} */ /*! @name SEL5 - Crossbar A Select Register 5 */ +/*! @{ */ #define XBARA_SEL5_SEL10_MASK (0x7FU) #define XBARA_SEL5_SEL10_SHIFT (0U) #define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK) #define XBARA_SEL5_SEL11_MASK (0x7F00U) #define XBARA_SEL5_SEL11_SHIFT (8U) #define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK) +/*! @} */ /*! @name SEL6 - Crossbar A Select Register 6 */ +/*! @{ */ #define XBARA_SEL6_SEL12_MASK (0x7FU) #define XBARA_SEL6_SEL12_SHIFT (0U) #define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK) #define XBARA_SEL6_SEL13_MASK (0x7F00U) #define XBARA_SEL6_SEL13_SHIFT (8U) #define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK) +/*! @} */ /*! @name SEL7 - Crossbar A Select Register 7 */ +/*! @{ */ #define XBARA_SEL7_SEL14_MASK (0x7FU) #define XBARA_SEL7_SEL14_SHIFT (0U) #define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK) #define XBARA_SEL7_SEL15_MASK (0x7F00U) #define XBARA_SEL7_SEL15_SHIFT (8U) #define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK) +/*! @} */ /*! @name SEL8 - Crossbar A Select Register 8 */ +/*! @{ */ #define XBARA_SEL8_SEL16_MASK (0x7FU) #define XBARA_SEL8_SEL16_SHIFT (0U) #define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK) #define XBARA_SEL8_SEL17_MASK (0x7F00U) #define XBARA_SEL8_SEL17_SHIFT (8U) #define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK) +/*! @} */ /*! @name SEL9 - Crossbar A Select Register 9 */ +/*! @{ */ #define XBARA_SEL9_SEL18_MASK (0x7FU) #define XBARA_SEL9_SEL18_SHIFT (0U) #define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK) #define XBARA_SEL9_SEL19_MASK (0x7F00U) #define XBARA_SEL9_SEL19_SHIFT (8U) #define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK) +/*! @} */ /*! @name SEL10 - Crossbar A Select Register 10 */ +/*! @{ */ #define XBARA_SEL10_SEL20_MASK (0x7FU) #define XBARA_SEL10_SEL20_SHIFT (0U) #define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK) #define XBARA_SEL10_SEL21_MASK (0x7F00U) #define XBARA_SEL10_SEL21_SHIFT (8U) #define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK) +/*! @} */ /*! @name SEL11 - Crossbar A Select Register 11 */ +/*! @{ */ #define XBARA_SEL11_SEL22_MASK (0x7FU) #define XBARA_SEL11_SEL22_SHIFT (0U) #define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK) #define XBARA_SEL11_SEL23_MASK (0x7F00U) #define XBARA_SEL11_SEL23_SHIFT (8U) #define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK) +/*! @} */ /*! @name SEL12 - Crossbar A Select Register 12 */ +/*! @{ */ #define XBARA_SEL12_SEL24_MASK (0x7FU) #define XBARA_SEL12_SEL24_SHIFT (0U) #define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK) #define XBARA_SEL12_SEL25_MASK (0x7F00U) #define XBARA_SEL12_SEL25_SHIFT (8U) #define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK) +/*! @} */ /*! @name SEL13 - Crossbar A Select Register 13 */ +/*! @{ */ #define XBARA_SEL13_SEL26_MASK (0x7FU) #define XBARA_SEL13_SEL26_SHIFT (0U) #define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK) #define XBARA_SEL13_SEL27_MASK (0x7F00U) #define XBARA_SEL13_SEL27_SHIFT (8U) #define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK) +/*! @} */ /*! @name SEL14 - Crossbar A Select Register 14 */ +/*! @{ */ #define XBARA_SEL14_SEL28_MASK (0x7FU) #define XBARA_SEL14_SEL28_SHIFT (0U) #define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK) #define XBARA_SEL14_SEL29_MASK (0x7F00U) #define XBARA_SEL14_SEL29_SHIFT (8U) #define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK) +/*! @} */ /*! @name SEL15 - Crossbar A Select Register 15 */ +/*! @{ */ #define XBARA_SEL15_SEL30_MASK (0x7FU) #define XBARA_SEL15_SEL30_SHIFT (0U) #define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK) #define XBARA_SEL15_SEL31_MASK (0x7F00U) #define XBARA_SEL15_SEL31_SHIFT (8U) #define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK) +/*! @} */ /*! @name SEL16 - Crossbar A Select Register 16 */ +/*! @{ */ #define XBARA_SEL16_SEL32_MASK (0x7FU) #define XBARA_SEL16_SEL32_SHIFT (0U) #define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK) #define XBARA_SEL16_SEL33_MASK (0x7F00U) #define XBARA_SEL16_SEL33_SHIFT (8U) #define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK) +/*! @} */ /*! @name SEL17 - Crossbar A Select Register 17 */ +/*! @{ */ #define XBARA_SEL17_SEL34_MASK (0x7FU) #define XBARA_SEL17_SEL34_SHIFT (0U) #define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK) #define XBARA_SEL17_SEL35_MASK (0x7F00U) #define XBARA_SEL17_SEL35_SHIFT (8U) #define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK) +/*! @} */ /*! @name SEL18 - Crossbar A Select Register 18 */ +/*! @{ */ #define XBARA_SEL18_SEL36_MASK (0x7FU) #define XBARA_SEL18_SEL36_SHIFT (0U) #define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK) #define XBARA_SEL18_SEL37_MASK (0x7F00U) #define XBARA_SEL18_SEL37_SHIFT (8U) #define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK) +/*! @} */ /*! @name SEL19 - Crossbar A Select Register 19 */ +/*! @{ */ #define XBARA_SEL19_SEL38_MASK (0x7FU) #define XBARA_SEL19_SEL38_SHIFT (0U) #define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK) #define XBARA_SEL19_SEL39_MASK (0x7F00U) #define XBARA_SEL19_SEL39_SHIFT (8U) #define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK) +/*! @} */ /*! @name SEL20 - Crossbar A Select Register 20 */ +/*! @{ */ #define XBARA_SEL20_SEL40_MASK (0x7FU) #define XBARA_SEL20_SEL40_SHIFT (0U) #define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK) #define XBARA_SEL20_SEL41_MASK (0x7F00U) #define XBARA_SEL20_SEL41_SHIFT (8U) #define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK) +/*! @} */ /*! @name SEL21 - Crossbar A Select Register 21 */ +/*! @{ */ #define XBARA_SEL21_SEL42_MASK (0x7FU) #define XBARA_SEL21_SEL42_SHIFT (0U) #define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK) #define XBARA_SEL21_SEL43_MASK (0x7F00U) #define XBARA_SEL21_SEL43_SHIFT (8U) #define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK) +/*! @} */ /*! @name SEL22 - Crossbar A Select Register 22 */ +/*! @{ */ #define XBARA_SEL22_SEL44_MASK (0x7FU) #define XBARA_SEL22_SEL44_SHIFT (0U) #define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK) #define XBARA_SEL22_SEL45_MASK (0x7F00U) #define XBARA_SEL22_SEL45_SHIFT (8U) #define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK) +/*! @} */ /*! @name SEL23 - Crossbar A Select Register 23 */ +/*! @{ */ #define XBARA_SEL23_SEL46_MASK (0x7FU) #define XBARA_SEL23_SEL46_SHIFT (0U) #define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK) #define XBARA_SEL23_SEL47_MASK (0x7F00U) #define XBARA_SEL23_SEL47_SHIFT (8U) #define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK) +/*! @} */ /*! @name SEL24 - Crossbar A Select Register 24 */ +/*! @{ */ #define XBARA_SEL24_SEL48_MASK (0x7FU) #define XBARA_SEL24_SEL48_SHIFT (0U) #define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK) #define XBARA_SEL24_SEL49_MASK (0x7F00U) #define XBARA_SEL24_SEL49_SHIFT (8U) #define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK) +/*! @} */ /*! @name SEL25 - Crossbar A Select Register 25 */ +/*! @{ */ #define XBARA_SEL25_SEL50_MASK (0x7FU) #define XBARA_SEL25_SEL50_SHIFT (0U) #define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK) #define XBARA_SEL25_SEL51_MASK (0x7F00U) #define XBARA_SEL25_SEL51_SHIFT (8U) #define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK) +/*! @} */ /*! @name SEL26 - Crossbar A Select Register 26 */ +/*! @{ */ #define XBARA_SEL26_SEL52_MASK (0x7FU) #define XBARA_SEL26_SEL52_SHIFT (0U) #define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK) #define XBARA_SEL26_SEL53_MASK (0x7F00U) #define XBARA_SEL26_SEL53_SHIFT (8U) #define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK) +/*! @} */ /*! @name SEL27 - Crossbar A Select Register 27 */ +/*! @{ */ #define XBARA_SEL27_SEL54_MASK (0x7FU) #define XBARA_SEL27_SEL54_SHIFT (0U) #define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK) #define XBARA_SEL27_SEL55_MASK (0x7F00U) #define XBARA_SEL27_SEL55_SHIFT (8U) #define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK) +/*! @} */ /*! @name SEL28 - Crossbar A Select Register 28 */ +/*! @{ */ #define XBARA_SEL28_SEL56_MASK (0x7FU) #define XBARA_SEL28_SEL56_SHIFT (0U) #define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK) #define XBARA_SEL28_SEL57_MASK (0x7F00U) #define XBARA_SEL28_SEL57_SHIFT (8U) #define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK) +/*! @} */ /*! @name SEL29 - Crossbar A Select Register 29 */ +/*! @{ */ #define XBARA_SEL29_SEL58_MASK (0x7FU) #define XBARA_SEL29_SEL58_SHIFT (0U) #define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK) #define XBARA_SEL29_SEL59_MASK (0x7F00U) #define XBARA_SEL29_SEL59_SHIFT (8U) #define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK) +/*! @} */ /*! @name SEL30 - Crossbar A Select Register 30 */ +/*! @{ */ #define XBARA_SEL30_SEL60_MASK (0x7FU) #define XBARA_SEL30_SEL60_SHIFT (0U) #define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK) #define XBARA_SEL30_SEL61_MASK (0x7F00U) #define XBARA_SEL30_SEL61_SHIFT (8U) #define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK) +/*! @} */ /*! @name SEL31 - Crossbar A Select Register 31 */ +/*! @{ */ #define XBARA_SEL31_SEL62_MASK (0x7FU) #define XBARA_SEL31_SEL62_SHIFT (0U) #define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK) #define XBARA_SEL31_SEL63_MASK (0x7F00U) #define XBARA_SEL31_SEL63_SHIFT (8U) #define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK) +/*! @} */ /*! @name SEL32 - Crossbar A Select Register 32 */ +/*! @{ */ #define XBARA_SEL32_SEL64_MASK (0x7FU) #define XBARA_SEL32_SEL64_SHIFT (0U) #define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK) #define XBARA_SEL32_SEL65_MASK (0x7F00U) #define XBARA_SEL32_SEL65_SHIFT (8U) #define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK) +/*! @} */ /*! @name SEL33 - Crossbar A Select Register 33 */ +/*! @{ */ #define XBARA_SEL33_SEL66_MASK (0x7FU) #define XBARA_SEL33_SEL66_SHIFT (0U) #define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK) #define XBARA_SEL33_SEL67_MASK (0x7F00U) #define XBARA_SEL33_SEL67_SHIFT (8U) #define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK) +/*! @} */ /*! @name SEL34 - Crossbar A Select Register 34 */ +/*! @{ */ #define XBARA_SEL34_SEL68_MASK (0x7FU) #define XBARA_SEL34_SEL68_SHIFT (0U) #define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK) #define XBARA_SEL34_SEL69_MASK (0x7F00U) #define XBARA_SEL34_SEL69_SHIFT (8U) #define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK) +/*! @} */ /*! @name SEL35 - Crossbar A Select Register 35 */ +/*! @{ */ #define XBARA_SEL35_SEL70_MASK (0x7FU) #define XBARA_SEL35_SEL70_SHIFT (0U) #define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK) #define XBARA_SEL35_SEL71_MASK (0x7F00U) #define XBARA_SEL35_SEL71_SHIFT (8U) #define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK) +/*! @} */ /*! @name SEL36 - Crossbar A Select Register 36 */ +/*! @{ */ #define XBARA_SEL36_SEL72_MASK (0x7FU) #define XBARA_SEL36_SEL72_SHIFT (0U) #define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK) #define XBARA_SEL36_SEL73_MASK (0x7F00U) #define XBARA_SEL36_SEL73_SHIFT (8U) #define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK) +/*! @} */ /*! @name SEL37 - Crossbar A Select Register 37 */ +/*! @{ */ #define XBARA_SEL37_SEL74_MASK (0x7FU) #define XBARA_SEL37_SEL74_SHIFT (0U) #define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK) #define XBARA_SEL37_SEL75_MASK (0x7F00U) #define XBARA_SEL37_SEL75_SHIFT (8U) #define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK) +/*! @} */ /*! @name SEL38 - Crossbar A Select Register 38 */ +/*! @{ */ #define XBARA_SEL38_SEL76_MASK (0x7FU) #define XBARA_SEL38_SEL76_SHIFT (0U) #define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK) #define XBARA_SEL38_SEL77_MASK (0x7F00U) #define XBARA_SEL38_SEL77_SHIFT (8U) #define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK) +/*! @} */ /*! @name SEL39 - Crossbar A Select Register 39 */ +/*! @{ */ #define XBARA_SEL39_SEL78_MASK (0x7FU) #define XBARA_SEL39_SEL78_SHIFT (0U) #define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK) #define XBARA_SEL39_SEL79_MASK (0x7F00U) #define XBARA_SEL39_SEL79_SHIFT (8U) #define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK) +/*! @} */ /*! @name SEL40 - Crossbar A Select Register 40 */ +/*! @{ */ #define XBARA_SEL40_SEL80_MASK (0x7FU) #define XBARA_SEL40_SEL80_SHIFT (0U) #define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK) #define XBARA_SEL40_SEL81_MASK (0x7F00U) #define XBARA_SEL40_SEL81_SHIFT (8U) #define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK) +/*! @} */ /*! @name SEL41 - Crossbar A Select Register 41 */ +/*! @{ */ #define XBARA_SEL41_SEL82_MASK (0x7FU) #define XBARA_SEL41_SEL82_SHIFT (0U) #define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK) #define XBARA_SEL41_SEL83_MASK (0x7F00U) #define XBARA_SEL41_SEL83_SHIFT (8U) #define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK) +/*! @} */ /*! @name SEL42 - Crossbar A Select Register 42 */ +/*! @{ */ #define XBARA_SEL42_SEL84_MASK (0x7FU) #define XBARA_SEL42_SEL84_SHIFT (0U) #define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK) #define XBARA_SEL42_SEL85_MASK (0x7F00U) #define XBARA_SEL42_SEL85_SHIFT (8U) #define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK) +/*! @} */ /*! @name SEL43 - Crossbar A Select Register 43 */ +/*! @{ */ #define XBARA_SEL43_SEL86_MASK (0x7FU) #define XBARA_SEL43_SEL86_SHIFT (0U) #define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK) #define XBARA_SEL43_SEL87_MASK (0x7F00U) #define XBARA_SEL43_SEL87_SHIFT (8U) #define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK) +/*! @} */ /*! @name SEL44 - Crossbar A Select Register 44 */ +/*! @{ */ #define XBARA_SEL44_SEL88_MASK (0x7FU) #define XBARA_SEL44_SEL88_SHIFT (0U) #define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK) #define XBARA_SEL44_SEL89_MASK (0x7F00U) #define XBARA_SEL44_SEL89_SHIFT (8U) #define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK) +/*! @} */ /*! @name SEL45 - Crossbar A Select Register 45 */ +/*! @{ */ #define XBARA_SEL45_SEL90_MASK (0x7FU) #define XBARA_SEL45_SEL90_SHIFT (0U) #define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK) #define XBARA_SEL45_SEL91_MASK (0x7F00U) #define XBARA_SEL45_SEL91_SHIFT (8U) #define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK) +/*! @} */ /*! @name SEL46 - Crossbar A Select Register 46 */ +/*! @{ */ #define XBARA_SEL46_SEL92_MASK (0x7FU) #define XBARA_SEL46_SEL92_SHIFT (0U) #define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK) #define XBARA_SEL46_SEL93_MASK (0x7F00U) #define XBARA_SEL46_SEL93_SHIFT (8U) #define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK) +/*! @} */ /*! @name SEL47 - Crossbar A Select Register 47 */ +/*! @{ */ #define XBARA_SEL47_SEL94_MASK (0x7FU) #define XBARA_SEL47_SEL94_SHIFT (0U) #define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK) #define XBARA_SEL47_SEL95_MASK (0x7F00U) #define XBARA_SEL47_SEL95_SHIFT (8U) #define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK) +/*! @} */ /*! @name SEL48 - Crossbar A Select Register 48 */ +/*! @{ */ #define XBARA_SEL48_SEL96_MASK (0x7FU) #define XBARA_SEL48_SEL96_SHIFT (0U) #define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK) #define XBARA_SEL48_SEL97_MASK (0x7F00U) #define XBARA_SEL48_SEL97_SHIFT (8U) #define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK) +/*! @} */ /*! @name SEL49 - Crossbar A Select Register 49 */ +/*! @{ */ #define XBARA_SEL49_SEL98_MASK (0x7FU) #define XBARA_SEL49_SEL98_SHIFT (0U) #define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK) #define XBARA_SEL49_SEL99_MASK (0x7F00U) #define XBARA_SEL49_SEL99_SHIFT (8U) #define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK) +/*! @} */ /*! @name SEL50 - Crossbar A Select Register 50 */ +/*! @{ */ #define XBARA_SEL50_SEL100_MASK (0x7FU) #define XBARA_SEL50_SEL100_SHIFT (0U) #define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK) #define XBARA_SEL50_SEL101_MASK (0x7F00U) #define XBARA_SEL50_SEL101_SHIFT (8U) #define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK) +/*! @} */ /*! @name SEL51 - Crossbar A Select Register 51 */ +/*! @{ */ #define XBARA_SEL51_SEL102_MASK (0x7FU) #define XBARA_SEL51_SEL102_SHIFT (0U) #define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK) #define XBARA_SEL51_SEL103_MASK (0x7F00U) #define XBARA_SEL51_SEL103_SHIFT (8U) #define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK) +/*! @} */ /*! @name SEL52 - Crossbar A Select Register 52 */ +/*! @{ */ #define XBARA_SEL52_SEL104_MASK (0x7FU) #define XBARA_SEL52_SEL104_SHIFT (0U) #define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK) #define XBARA_SEL52_SEL105_MASK (0x7F00U) #define XBARA_SEL52_SEL105_SHIFT (8U) #define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK) +/*! @} */ /*! @name SEL53 - Crossbar A Select Register 53 */ +/*! @{ */ #define XBARA_SEL53_SEL106_MASK (0x7FU) #define XBARA_SEL53_SEL106_SHIFT (0U) #define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK) #define XBARA_SEL53_SEL107_MASK (0x7F00U) #define XBARA_SEL53_SEL107_SHIFT (8U) #define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK) +/*! @} */ /*! @name SEL54 - Crossbar A Select Register 54 */ +/*! @{ */ #define XBARA_SEL54_SEL108_MASK (0x7FU) #define XBARA_SEL54_SEL108_SHIFT (0U) #define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK) #define XBARA_SEL54_SEL109_MASK (0x7F00U) #define XBARA_SEL54_SEL109_SHIFT (8U) #define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK) +/*! @} */ /*! @name SEL55 - Crossbar A Select Register 55 */ +/*! @{ */ #define XBARA_SEL55_SEL110_MASK (0x7FU) #define XBARA_SEL55_SEL110_SHIFT (0U) #define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK) #define XBARA_SEL55_SEL111_MASK (0x7F00U) #define XBARA_SEL55_SEL111_SHIFT (8U) #define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK) +/*! @} */ /*! @name SEL56 - Crossbar A Select Register 56 */ +/*! @{ */ #define XBARA_SEL56_SEL112_MASK (0x7FU) #define XBARA_SEL56_SEL112_SHIFT (0U) #define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK) #define XBARA_SEL56_SEL113_MASK (0x7F00U) #define XBARA_SEL56_SEL113_SHIFT (8U) #define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK) +/*! @} */ /*! @name SEL57 - Crossbar A Select Register 57 */ +/*! @{ */ #define XBARA_SEL57_SEL114_MASK (0x7FU) #define XBARA_SEL57_SEL114_SHIFT (0U) #define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK) #define XBARA_SEL57_SEL115_MASK (0x7F00U) #define XBARA_SEL57_SEL115_SHIFT (8U) #define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK) +/*! @} */ /*! @name SEL58 - Crossbar A Select Register 58 */ +/*! @{ */ #define XBARA_SEL58_SEL116_MASK (0x7FU) #define XBARA_SEL58_SEL116_SHIFT (0U) #define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK) #define XBARA_SEL58_SEL117_MASK (0x7F00U) #define XBARA_SEL58_SEL117_SHIFT (8U) #define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK) +/*! @} */ /*! @name SEL59 - Crossbar A Select Register 59 */ +/*! @{ */ #define XBARA_SEL59_SEL118_MASK (0x7FU) #define XBARA_SEL59_SEL118_SHIFT (0U) #define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK) #define XBARA_SEL59_SEL119_MASK (0x7F00U) #define XBARA_SEL59_SEL119_SHIFT (8U) #define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK) +/*! @} */ /*! @name SEL60 - Crossbar A Select Register 60 */ +/*! @{ */ #define XBARA_SEL60_SEL120_MASK (0x7FU) #define XBARA_SEL60_SEL120_SHIFT (0U) #define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK) #define XBARA_SEL60_SEL121_MASK (0x7F00U) #define XBARA_SEL60_SEL121_SHIFT (8U) #define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK) +/*! @} */ /*! @name SEL61 - Crossbar A Select Register 61 */ +/*! @{ */ #define XBARA_SEL61_SEL122_MASK (0x7FU) #define XBARA_SEL61_SEL122_SHIFT (0U) #define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK) #define XBARA_SEL61_SEL123_MASK (0x7F00U) #define XBARA_SEL61_SEL123_SHIFT (8U) #define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK) +/*! @} */ /*! @name SEL62 - Crossbar A Select Register 62 */ +/*! @{ */ #define XBARA_SEL62_SEL124_MASK (0x7FU) #define XBARA_SEL62_SEL124_SHIFT (0U) #define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK) #define XBARA_SEL62_SEL125_MASK (0x7F00U) #define XBARA_SEL62_SEL125_SHIFT (8U) #define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK) +/*! @} */ /*! @name SEL63 - Crossbar A Select Register 63 */ +/*! @{ */ #define XBARA_SEL63_SEL126_MASK (0x7FU) #define XBARA_SEL63_SEL126_SHIFT (0U) #define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK) #define XBARA_SEL63_SEL127_MASK (0x7F00U) #define XBARA_SEL63_SEL127_SHIFT (8U) #define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK) +/*! @} */ /*! @name SEL64 - Crossbar A Select Register 64 */ +/*! @{ */ #define XBARA_SEL64_SEL128_MASK (0x7FU) #define XBARA_SEL64_SEL128_SHIFT (0U) #define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK) #define XBARA_SEL64_SEL129_MASK (0x7F00U) #define XBARA_SEL64_SEL129_SHIFT (8U) #define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK) +/*! @} */ /*! @name SEL65 - Crossbar A Select Register 65 */ +/*! @{ */ #define XBARA_SEL65_SEL130_MASK (0x7FU) #define XBARA_SEL65_SEL130_SHIFT (0U) #define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK) #define XBARA_SEL65_SEL131_MASK (0x7F00U) #define XBARA_SEL65_SEL131_SHIFT (8U) #define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK) +/*! @} */ /*! @name CTRL0 - Crossbar A Control Register 0 */ +/*! @{ */ #define XBARA_CTRL0_DEN0_MASK (0x1U) #define XBARA_CTRL0_DEN0_SHIFT (0U) #define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK) @@ -26450,8 +28945,10 @@ typedef struct { #define XBARA_CTRL0_STS1_MASK (0x1000U) #define XBARA_CTRL0_STS1_SHIFT (12U) #define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK) +/*! @} */ /*! @name CTRL1 - Crossbar A Control Register 1 */ +/*! @{ */ #define XBARA_CTRL1_DEN2_MASK (0x1U) #define XBARA_CTRL1_DEN2_SHIFT (0U) #define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK) @@ -26476,6 +28973,7 @@ typedef struct { #define XBARA_CTRL1_STS3_MASK (0x1000U) #define XBARA_CTRL1_STS3_SHIFT (12U) #define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK) +/*! @} */ /*! @@ -26529,68 +29027,84 @@ typedef struct { */ /*! @name SEL0 - Crossbar B Select Register 0 */ +/*! @{ */ #define XBARB_SEL0_SEL0_MASK (0x3FU) #define XBARB_SEL0_SEL0_SHIFT (0U) #define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK) #define XBARB_SEL0_SEL1_MASK (0x3F00U) #define XBARB_SEL0_SEL1_SHIFT (8U) #define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK) +/*! @} */ /*! @name SEL1 - Crossbar B Select Register 1 */ +/*! @{ */ #define XBARB_SEL1_SEL2_MASK (0x3FU) #define XBARB_SEL1_SEL2_SHIFT (0U) #define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK) #define XBARB_SEL1_SEL3_MASK (0x3F00U) #define XBARB_SEL1_SEL3_SHIFT (8U) #define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK) +/*! @} */ /*! @name SEL2 - Crossbar B Select Register 2 */ +/*! @{ */ #define XBARB_SEL2_SEL4_MASK (0x3FU) #define XBARB_SEL2_SEL4_SHIFT (0U) #define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK) #define XBARB_SEL2_SEL5_MASK (0x3F00U) #define XBARB_SEL2_SEL5_SHIFT (8U) #define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK) +/*! @} */ /*! @name SEL3 - Crossbar B Select Register 3 */ +/*! @{ */ #define XBARB_SEL3_SEL6_MASK (0x3FU) #define XBARB_SEL3_SEL6_SHIFT (0U) #define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK) #define XBARB_SEL3_SEL7_MASK (0x3F00U) #define XBARB_SEL3_SEL7_SHIFT (8U) #define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK) +/*! @} */ /*! @name SEL4 - Crossbar B Select Register 4 */ +/*! @{ */ #define XBARB_SEL4_SEL8_MASK (0x3FU) #define XBARB_SEL4_SEL8_SHIFT (0U) #define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK) #define XBARB_SEL4_SEL9_MASK (0x3F00U) #define XBARB_SEL4_SEL9_SHIFT (8U) #define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK) +/*! @} */ /*! @name SEL5 - Crossbar B Select Register 5 */ +/*! @{ */ #define XBARB_SEL5_SEL10_MASK (0x3FU) #define XBARB_SEL5_SEL10_SHIFT (0U) #define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK) #define XBARB_SEL5_SEL11_MASK (0x3F00U) #define XBARB_SEL5_SEL11_SHIFT (8U) #define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK) +/*! @} */ /*! @name SEL6 - Crossbar B Select Register 6 */ +/*! @{ */ #define XBARB_SEL6_SEL12_MASK (0x3FU) #define XBARB_SEL6_SEL12_SHIFT (0U) #define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK) #define XBARB_SEL6_SEL13_MASK (0x3F00U) #define XBARB_SEL6_SEL13_SHIFT (8U) #define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK) +/*! @} */ /*! @name SEL7 - Crossbar B Select Register 7 */ +/*! @{ */ #define XBARB_SEL7_SEL14_MASK (0x3FU) #define XBARB_SEL7_SEL14_SHIFT (0U) #define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK) #define XBARB_SEL7_SEL15_MASK (0x3F00U) #define XBARB_SEL7_SEL15_SHIFT (8U) #define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK) +/*! @} */ /*! @@ -26663,6 +29177,7 @@ typedef struct { */ /*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ #define XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U) #define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U) #define XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK) @@ -26705,8 +29220,10 @@ typedef struct { #define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) #define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U) #define XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ #define XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U) #define XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U) #define XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK) @@ -26749,8 +29266,10 @@ typedef struct { #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ #define XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U) #define XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U) #define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK) @@ -26793,8 +29312,10 @@ typedef struct { #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ #define XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U) #define XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U) #define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK) @@ -26837,14 +29358,13 @@ typedef struct { #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name LOWPWR_CTRL - XTAL OSC (LP) Control Register */ +/*! @{ */ #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U) #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U) #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK) -#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_MASK (0xEU) -#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_SHIFT (1U) -#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_MASK) #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U) #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U) #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) @@ -26881,14 +29401,16 @@ typedef struct { #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U) #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U) #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK) +/*! @} */ /*! @name LOWPWR_CTRL_SET - XTAL OSC (LP) Control Register */ +/*! @{ */ #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U) #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U) #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK) -#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK (0xEU) -#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT (1U) -#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK) #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U) #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U) #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK) @@ -26925,14 +29447,16 @@ typedef struct { #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U) #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U) #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK) +/*! @} */ /*! @name LOWPWR_CTRL_CLR - XTAL OSC (LP) Control Register */ +/*! @{ */ #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U) #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U) #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK) -#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK (0xEU) -#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT (1U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK) #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U) #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U) #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK) @@ -26969,14 +29493,16 @@ typedef struct { #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U) #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U) #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK) +/*! @} */ /*! @name LOWPWR_CTRL_TOG - XTAL OSC (LP) Control Register */ +/*! @{ */ #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U) #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U) #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK) -#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK (0xEU) -#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT (1U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK) #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U) #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U) #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK) @@ -27013,8 +29539,13 @@ typedef struct { #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U) #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U) #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK) +/*! @} */ /*! @name OSC_CONFIG0 - XTAL OSC Configuration 0 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U) #define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK) @@ -27039,8 +29570,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U) #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U) #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U) #define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK) @@ -27065,8 +29598,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U) #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U) #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U) #define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK) @@ -27091,8 +29626,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U) #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U) #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U) #define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK) @@ -27117,40 +29654,50 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U) #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U) #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG1 - XTAL OSC Configuration 1 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK) #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U) #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U) #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK) #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U) #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U) #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK) #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U) #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U) #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK) #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U) #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U) #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG2 - XTAL OSC Configuration 2 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK) @@ -27163,8 +29710,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U) #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U) #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK) +/*! @} */ /*! @name OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK) @@ -27177,8 +29726,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U) #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U) #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK) +/*! @} */ /*! @name OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK) @@ -27191,8 +29742,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U) #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U) #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK) +/*! @} */ /*! @name OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK) @@ -27205,6 +29758,7 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U) #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U) #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK) +/*! @} */ /*! @@ -27232,7 +29786,11 @@ typedef struct { */ #if defined(__ARMCC_VERSION) - #pragma pop + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif #elif defined(__CWCC__) #pragma pop #elif defined(__GNUC__) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052_features.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052_features.h index 9d00377b19..765ebaddda 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052_features.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052_features.h @@ -1,37 +1,44 @@ /* ** ################################################################### ** Version: rev. 0.1, 2017-01-10 -** Build: b171017 +** Build: b180509 ** ** Abstract: ** Chip specific module features. ** +** The Clear BSD License ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2018 NXP +** All rights reserved. ** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: ** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. ** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. ** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.nxp.com ** mail: support@nxp.com @@ -48,532 +55,110 @@ /* SOC module features */ -/* @brief ACMP availability on the SoC. */ -#define FSL_FEATURE_SOC_ACMP_COUNT (0) /* @brief ADC availability on the SoC. */ #define FSL_FEATURE_SOC_ADC_COUNT (2) -/* @brief ADC12 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC12_COUNT (0) -/* @brief ADC16 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC16_COUNT (0) -/* @brief ADC_5HC availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC_5HC_COUNT (0) -/* @brief AES availability on the SoC. */ -#define FSL_FEATURE_SOC_AES_COUNT (0) -/* @brief AFE availability on the SoC. */ -#define FSL_FEATURE_SOC_AFE_COUNT (0) -/* @brief AGC availability on the SoC. */ -#define FSL_FEATURE_SOC_AGC_COUNT (0) -/* @brief AIPS availability on the SoC. */ -#define FSL_FEATURE_SOC_AIPS_COUNT (0) /* @brief AIPSTZ availability on the SoC. */ #define FSL_FEATURE_SOC_AIPSTZ_COUNT (4) -/* @brief ANATOP availability on the SoC. */ -#define FSL_FEATURE_SOC_ANATOP_COUNT (0) /* @brief AOI availability on the SoC. */ #define FSL_FEATURE_SOC_AOI_COUNT (2) -/* @brief APBH availability on the SoC. */ -#define FSL_FEATURE_SOC_APBH_COUNT (0) -/* @brief ASMC availability on the SoC. */ -#define FSL_FEATURE_SOC_ASMC_COUNT (0) -/* @brief ASRC availability on the SoC. */ -#define FSL_FEATURE_SOC_ASRC_COUNT (0) -/* @brief ASYNC_SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (0) -/* @brief ATX availability on the SoC. */ -#define FSL_FEATURE_SOC_ATX_COUNT (0) -/* @brief AXBS availability on the SoC. */ -#define FSL_FEATURE_SOC_AXBS_COUNT (0) -/* @brief BCH availability on the SoC. */ -#define FSL_FEATURE_SOC_BCH_COUNT (0) -/* @brief BLEDP availability on the SoC. */ -#define FSL_FEATURE_SOC_BLEDP_COUNT (0) -/* @brief BOD availability on the SoC. */ -#define FSL_FEATURE_SOC_BOD_COUNT (0) -/* @brief CAAM availability on the SoC. */ -#define FSL_FEATURE_SOC_CAAM_COUNT (0) -/* @brief CADC availability on the SoC. */ -#define FSL_FEATURE_SOC_CADC_COUNT (0) -/* @brief CALIB availability on the SoC. */ -#define FSL_FEATURE_SOC_CALIB_COUNT (0) -/* @brief CAN availability on the SoC. */ -#define FSL_FEATURE_SOC_CAN_COUNT (0) -/* @brief CAU availability on the SoC. */ -#define FSL_FEATURE_SOC_CAU_COUNT (0) -/* @brief CAU3 availability on the SoC. */ -#define FSL_FEATURE_SOC_CAU3_COUNT (0) /* @brief CCM availability on the SoC. */ #define FSL_FEATURE_SOC_CCM_COUNT (1) /* @brief CCM_ANALOG availability on the SoC. */ #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) -/* @brief CHRG availability on the SoC. */ -#define FSL_FEATURE_SOC_CHRG_COUNT (0) -/* @brief CLKCTL0 availability on the SoC. */ -#define FSL_FEATURE_SOC_CLKCTL0_COUNT (0) -/* @brief CLKCTL1 availability on the SoC. */ -#define FSL_FEATURE_SOC_CLKCTL1_COUNT (0) /* @brief CMP availability on the SoC. */ #define FSL_FEATURE_SOC_CMP_COUNT (4) -/* @brief CMT availability on the SoC. */ -#define FSL_FEATURE_SOC_CMT_COUNT (0) -/* @brief CNC availability on the SoC. */ -#define FSL_FEATURE_SOC_CNC_COUNT (0) -/* @brief COP availability on the SoC. */ -#define FSL_FEATURE_SOC_COP_COUNT (0) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (0) -/* @brief CS availability on the SoC. */ -#define FSL_FEATURE_SOC_CS_COUNT (0) /* @brief CSI availability on the SoC. */ #define FSL_FEATURE_SOC_CSI_COUNT (1) -/* @brief CT32B availability on the SoC. */ -#define FSL_FEATURE_SOC_CT32B_COUNT (0) -/* @brief CTI availability on the SoC. */ -#define FSL_FEATURE_SOC_CTI_COUNT (0) -/* @brief CTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_CTIMER_COUNT (0) -/* @brief DAC availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC_COUNT (0) -/* @brief DAC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC32_COUNT (0) /* @brief DCDC availability on the SoC. */ #define FSL_FEATURE_SOC_DCDC_COUNT (1) /* @brief DCP availability on the SoC. */ #define FSL_FEATURE_SOC_DCP_COUNT (1) -/* @brief DDR availability on the SoC. */ -#define FSL_FEATURE_SOC_DDR_COUNT (0) -/* @brief DDRC availability on the SoC. */ -#define FSL_FEATURE_SOC_DDRC_COUNT (0) -/* @brief DDRC_MP availability on the SoC. */ -#define FSL_FEATURE_SOC_DDRC_MP_COUNT (0) -/* @brief DDR_PHY availability on the SoC. */ -#define FSL_FEATURE_SOC_DDR_PHY_COUNT (0) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (0) /* @brief DMAMUX availability on the SoC. */ #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) -/* @brief DMIC availability on the SoC. */ -#define FSL_FEATURE_SOC_DMIC_COUNT (0) -/* @brief DRY availability on the SoC. */ -#define FSL_FEATURE_SOC_DRY_COUNT (0) -/* @brief DSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_DSPI_COUNT (0) -/* @brief ECSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_ECSPI_COUNT (0) /* @brief EDMA availability on the SoC. */ #define FSL_FEATURE_SOC_EDMA_COUNT (1) -/* @brief EEPROM availability on the SoC. */ -#define FSL_FEATURE_SOC_EEPROM_COUNT (0) -/* @brief EIM availability on the SoC. */ -#define FSL_FEATURE_SOC_EIM_COUNT (0) -/* @brief EMC availability on the SoC. */ -#define FSL_FEATURE_SOC_EMC_COUNT (0) -/* @brief EMVSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) /* @brief ENC availability on the SoC. */ #define FSL_FEATURE_SOC_ENC_COUNT (4) /* @brief ENET availability on the SoC. */ #define FSL_FEATURE_SOC_ENET_COUNT (1) -/* @brief EPDC availability on the SoC. */ -#define FSL_FEATURE_SOC_EPDC_COUNT (0) -/* @brief EPIT availability on the SoC. */ -#define FSL_FEATURE_SOC_EPIT_COUNT (0) -/* @brief ESAI availability on the SoC. */ -#define FSL_FEATURE_SOC_ESAI_COUNT (0) /* @brief EWM availability on the SoC. */ #define FSL_FEATURE_SOC_EWM_COUNT (1) -/* @brief FB availability on the SoC. */ -#define FSL_FEATURE_SOC_FB_COUNT (0) -/* @brief FGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FGPIO_COUNT (0) -/* @brief FLASH availability on the SoC. */ -#define FSL_FEATURE_SOC_FLASH_COUNT (0) /* @brief FLEXCAN availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) -/* @brief FLEXCOMM availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (0) /* @brief FLEXIO availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXIO_COUNT (2) /* @brief FLEXRAM availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXRAM_COUNT (1) /* @brief FLEXSPI availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) -/* @brief FMC availability on the SoC. */ -#define FSL_FEATURE_SOC_FMC_COUNT (0) -/* @brief FREQME availability on the SoC. */ -#define FSL_FEATURE_SOC_FREQME_COUNT (0) -/* @brief FSKDT availability on the SoC. */ -#define FSL_FEATURE_SOC_FSKDT_COUNT (0) -/* @brief FSP availability on the SoC. */ -#define FSL_FEATURE_SOC_FSP_COUNT (0) -/* @brief FTFA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFA_COUNT (0) -/* @brief FTFE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFE_COUNT (0) -/* @brief FTFL availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFL_COUNT (0) -/* @brief FTM availability on the SoC. */ -#define FSL_FEATURE_SOC_FTM_COUNT (0) -/* @brief FTMRA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRA_COUNT (0) -/* @brief FTMRE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRE_COUNT (0) -/* @brief FTMRH availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRH_COUNT (0) -/* @brief GINT availability on the SoC. */ -#define FSL_FEATURE_SOC_GINT_COUNT (0) /* @brief GPC availability on the SoC. */ #define FSL_FEATURE_SOC_GPC_COUNT (1) -/* @brief GPC_PGC availability on the SoC. */ -#define FSL_FEATURE_SOC_GPC_PGC_COUNT (0) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (0) -/* @brief GPMI availability on the SoC. */ -#define FSL_FEATURE_SOC_GPMI_COUNT (0) /* @brief GPT availability on the SoC. */ #define FSL_FEATURE_SOC_GPT_COUNT (2) -/* @brief HASH availability on the SoC. */ -#define FSL_FEATURE_SOC_HASH_COUNT (0) -/* @brief HSADC availability on the SoC. */ -#define FSL_FEATURE_SOC_HSADC_COUNT (0) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (0) /* @brief I2S availability on the SoC. */ #define FSL_FEATURE_SOC_I2S_COUNT (3) -/* @brief ICS availability on the SoC. */ -#define FSL_FEATURE_SOC_ICS_COUNT (0) -/* @brief IEE availability on the SoC. */ -#define FSL_FEATURE_SOC_IEE_COUNT (0) -/* @brief IEER availability on the SoC. */ -#define FSL_FEATURE_SOC_IEER_COUNT (0) /* @brief IGPIO availability on the SoC. */ #define FSL_FEATURE_SOC_IGPIO_COUNT (5) -/* @brief II2C availability on the SoC. */ -#define FSL_FEATURE_SOC_II2C_COUNT (0) -/* @brief INPUTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INPUTMUX_COUNT (0) -/* @brief INTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INTMUX_COUNT (0) -/* @brief IOCON availability on the SoC. */ -#define FSL_FEATURE_SOC_IOCON_COUNT (0) /* @brief IOMUXC availability on the SoC. */ #define FSL_FEATURE_SOC_IOMUXC_COUNT (1) /* @brief IOMUXC_GPR availability on the SoC. */ #define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) -/* @brief IOMUXC_LPSR availability on the SoC. */ -#define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (0) -/* @brief IOMUXC_LPSR_GPR availability on the SoC. */ -#define FSL_FEATURE_SOC_IOMUXC_LPSR_GPR_COUNT (0) /* @brief IOMUXC_SNVS availability on the SoC. */ #define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1) -/* @brief IOPCTL availability on the SoC. */ -#define FSL_FEATURE_SOC_IOPCTL_COUNT (0) -/* @brief IPWM availability on the SoC. */ -#define FSL_FEATURE_SOC_IPWM_COUNT (0) -/* @brief IRQ availability on the SoC. */ -#define FSL_FEATURE_SOC_IRQ_COUNT (0) -/* @brief IUART availability on the SoC. */ -#define FSL_FEATURE_SOC_IUART_COUNT (0) -/* @brief KBI availability on the SoC. */ -#define FSL_FEATURE_SOC_KBI_COUNT (0) /* @brief KPP availability on the SoC. */ #define FSL_FEATURE_SOC_KPP_COUNT (1) -/* @brief L2CACHEC availability on the SoC. */ -#define FSL_FEATURE_SOC_L2CACHEC_COUNT (0) -/* @brief LCD availability on the SoC. */ -#define FSL_FEATURE_SOC_LCD_COUNT (0) -/* @brief LCDC availability on the SoC. */ -#define FSL_FEATURE_SOC_LCDC_COUNT (0) /* @brief LCDIF availability on the SoC. */ #define FSL_FEATURE_SOC_LCDIF_COUNT (1) -/* @brief LDO availability on the SoC. */ -#define FSL_FEATURE_SOC_LDO_COUNT (0) -/* @brief LLWU availability on the SoC. */ -#define FSL_FEATURE_SOC_LLWU_COUNT (0) -/* @brief LMEM availability on the SoC. */ -#define FSL_FEATURE_SOC_LMEM_COUNT (0) -/* @brief LPADC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPADC_COUNT (0) -/* @brief LPCMP availability on the SoC. */ -#define FSL_FEATURE_SOC_LPCMP_COUNT (0) -/* @brief LPDAC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPDAC_COUNT (0) /* @brief LPI2C availability on the SoC. */ #define FSL_FEATURE_SOC_LPI2C_COUNT (4) -/* @brief LPIT availability on the SoC. */ -#define FSL_FEATURE_SOC_LPIT_COUNT (0) -/* @brief LPSCI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSCI_COUNT (0) /* @brief LPSPI availability on the SoC. */ #define FSL_FEATURE_SOC_LPSPI_COUNT (4) -/* @brief LPTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTMR_COUNT (0) -/* @brief LPTPM availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTPM_COUNT (0) /* @brief LPUART availability on the SoC. */ #define FSL_FEATURE_SOC_LPUART_COUNT (8) -/* @brief LTC availability on the SoC. */ -#define FSL_FEATURE_SOC_LTC_COUNT (0) -/* @brief MAILBOX availability on the SoC. */ -#define FSL_FEATURE_SOC_MAILBOX_COUNT (0) -/* @brief MC availability on the SoC. */ -#define FSL_FEATURE_SOC_MC_COUNT (0) -/* @brief MCG availability on the SoC. */ -#define FSL_FEATURE_SOC_MCG_COUNT (0) -/* @brief MCGLITE availability on the SoC. */ -#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) -/* @brief MCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MCM_COUNT (0) -/* @brief MIPI_CSI2 availability on the SoC. */ -#define FSL_FEATURE_SOC_MIPI_CSI2_COUNT (0) -/* @brief MIPI_CSI2RX availability on the SoC. */ -#define FSL_FEATURE_SOC_MIPI_CSI2RX_COUNT (0) -/* @brief MIPI_DSI availability on the SoC. */ -#define FSL_FEATURE_SOC_MIPI_DSI_COUNT (0) -/* @brief MIPI_DSI_HOST availability on the SoC. */ -#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (0) -/* @brief MMAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMAU_COUNT (0) -/* @brief MMCAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMCAU_COUNT (0) -/* @brief MMDC availability on the SoC. */ -#define FSL_FEATURE_SOC_MMDC_COUNT (0) -/* @brief MMDVSQ availability on the SoC. */ -#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) -/* @brief MPU availability on the SoC. */ -#define FSL_FEATURE_SOC_MPU_COUNT (0) -/* @brief MRT availability on the SoC. */ -#define FSL_FEATURE_SOC_MRT_COUNT (0) -/* @brief MSCAN availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCAN_COUNT (0) -/* @brief MSCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCM_COUNT (0) -/* @brief MTB availability on the SoC. */ -#define FSL_FEATURE_SOC_MTB_COUNT (0) -/* @brief MTBDWT availability on the SoC. */ -#define FSL_FEATURE_SOC_MTBDWT_COUNT (0) -/* @brief MU availability on the SoC. */ -#define FSL_FEATURE_SOC_MU_COUNT (0) -/* @brief NFC availability on the SoC. */ -#define FSL_FEATURE_SOC_NFC_COUNT (0) /* @brief OCOTP availability on the SoC. */ #define FSL_FEATURE_SOC_OCOTP_COUNT (1) -/* @brief OPAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_OPAMP_COUNT (0) -/* @brief OTPC availability on the SoC. */ -#define FSL_FEATURE_SOC_OTPC_COUNT (0) -/* @brief OSC availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC_COUNT (0) -/* @brief OSC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC32_COUNT (0) -/* @brief OTFAD availability on the SoC. */ -#define FSL_FEATURE_SOC_OTFAD_COUNT (0) -/* @brief PCC availability on the SoC. */ -#define FSL_FEATURE_SOC_PCC_COUNT (0) -/* @brief PCIE_PHY_CMN availability on the SoC. */ -#define FSL_FEATURE_SOC_PCIE_PHY_CMN_COUNT (0) -/* @brief PCIE_PHY_TRSV availability on the SoC. */ -#define FSL_FEATURE_SOC_PCIE_PHY_TRSV_COUNT (0) -/* @brief PDB availability on the SoC. */ -#define FSL_FEATURE_SOC_PDB_COUNT (0) -/* @brief PGA availability on the SoC. */ -#define FSL_FEATURE_SOC_PGA_COUNT (0) -/* @brief PIMCTL availability on the SoC. */ -#define FSL_FEATURE_SOC_PIMCTL_COUNT (0) -/* @brief PINT availability on the SoC. */ -#define FSL_FEATURE_SOC_PINT_COUNT (0) /* @brief PIT availability on the SoC. */ #define FSL_FEATURE_SOC_PIT_COUNT (1) -/* @brief PMC availability on the SoC. */ -#define FSL_FEATURE_SOC_PMC_COUNT (0) /* @brief PMU availability on the SoC. */ #define FSL_FEATURE_SOC_PMU_COUNT (1) -/* @brief POWERQUAD availability on the SoC. */ -#define FSL_FEATURE_SOC_POWERQUAD_COUNT (0) -/* @brief PORT availability on the SoC. */ -#define FSL_FEATURE_SOC_PORT_COUNT (0) -/* @brief PROP availability on the SoC. */ -#define FSL_FEATURE_SOC_PROP_COUNT (0) /* @brief PWM availability on the SoC. */ #define FSL_FEATURE_SOC_PWM_COUNT (4) -/* @brief PWT availability on the SoC. */ -#define FSL_FEATURE_SOC_PWT_COUNT (0) /* @brief PXP availability on the SoC. */ #define FSL_FEATURE_SOC_PXP_COUNT (1) -/* @brief QDDKEY availability on the SoC. */ -#define FSL_FEATURE_SOC_QDDKEY_COUNT (0) -/* @brief QDEC availability on the SoC. */ -#define FSL_FEATURE_SOC_QDEC_COUNT (0) -/* @brief QuadSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) -/* @brief RCM availability on the SoC. */ -#define FSL_FEATURE_SOC_RCM_COUNT (0) -/* @brief RDC availability on the SoC. */ -#define FSL_FEATURE_SOC_RDC_COUNT (0) -/* @brief RDC_SEMAPHORE availability on the SoC. */ -#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (0) -/* @brief RFSYS availability on the SoC. */ -#define FSL_FEATURE_SOC_RFSYS_COUNT (0) -/* @brief RFVBAT availability on the SoC. */ -#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) -/* @brief RIT availability on the SoC. */ -#define FSL_FEATURE_SOC_RIT_COUNT (0) -/* @brief RNG availability on the SoC. */ -#define FSL_FEATURE_SOC_RNG_COUNT (0) -/* @brief RNGB availability on the SoC. */ -#define FSL_FEATURE_SOC_RNGB_COUNT (0) -/* @brief ROM availability on the SoC. */ -#define FSL_FEATURE_SOC_ROM_COUNT (0) /* @brief ROMC availability on the SoC. */ #define FSL_FEATURE_SOC_ROMC_COUNT (1) -/* @brief RSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_RSIM_COUNT (0) -/* @brief RSTCTL0 availability on the SoC. */ -#define FSL_FEATURE_SOC_RSTCTL0_COUNT (0) -/* @brief RSTCTL1 availability on the SoC. */ -#define FSL_FEATURE_SOC_RSTCTL1_COUNT (0) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (0) -/* @brief SCG availability on the SoC. */ -#define FSL_FEATURE_SOC_SCG_COUNT (0) -/* @brief SCI availability on the SoC. */ -#define FSL_FEATURE_SOC_SCI_COUNT (0) -/* @brief SCT availability on the SoC. */ -#define FSL_FEATURE_SOC_SCT_COUNT (0) -/* @brief SDHC availability on the SoC. */ -#define FSL_FEATURE_SOC_SDHC_COUNT (0) -/* @brief SDIF availability on the SoC. */ -#define FSL_FEATURE_SOC_SDIF_COUNT (0) -/* @brief SDIO availability on the SoC. */ -#define FSL_FEATURE_SOC_SDIO_COUNT (0) -/* @brief SDMA availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMA_COUNT (0) -/* @brief SDMAARM availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMAARM_COUNT (0) -/* @brief SDMABP availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMABP_COUNT (0) -/* @brief SDMACORE availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMACORE_COUNT (0) -/* @brief SDMCORE availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMCORE_COUNT (0) -/* @brief SDRAM availability on the SoC. */ -#define FSL_FEATURE_SOC_SDRAM_COUNT (0) -/* @brief SEMA4 availability on the SoC. */ -#define FSL_FEATURE_SOC_SEMA4_COUNT (0) -/* @brief SEMA42 availability on the SoC. */ -#define FSL_FEATURE_SOC_SEMA42_COUNT (0) /* @brief SEMC availability on the SoC. */ #define FSL_FEATURE_SOC_SEMC_COUNT (1) -/* @brief SHA availability on the SoC. */ -#define FSL_FEATURE_SOC_SHA_COUNT (0) -/* @brief SIM availability on the SoC. */ -#define FSL_FEATURE_SOC_SIM_COUNT (0) -/* @brief SJC availability on the SoC. */ -#define FSL_FEATURE_SOC_SJC_COUNT (0) -/* @brief SLCD availability on the SoC. */ -#define FSL_FEATURE_SOC_SLCD_COUNT (0) -/* @brief SMARTCARD availability on the SoC. */ -#define FSL_FEATURE_SOC_SMARTCARD_COUNT (0) -/* @brief SMC availability on the SoC. */ -#define FSL_FEATURE_SOC_SMC_COUNT (0) /* @brief SNVS availability on the SoC. */ #define FSL_FEATURE_SOC_SNVS_COUNT (1) -/* @brief SPBA availability on the SoC. */ -#define FSL_FEATURE_SOC_SPBA_COUNT (0) /* @brief SPDIF availability on the SoC. */ #define FSL_FEATURE_SOC_SPDIF_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (0) -/* @brief SPIFI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPIFI_COUNT (0) -/* @brief SPM availability on the SoC. */ -#define FSL_FEATURE_SOC_SPM_COUNT (0) /* @brief SRC availability on the SoC. */ #define FSL_FEATURE_SOC_SRC_COUNT (1) -/* @brief SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCON_COUNT (0) -/* @brief SYSCTL0 availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCTL0_COUNT (0) -/* @brief SYSCTL1 availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCTL1_COUNT (0) /* @brief TEMPMON availability on the SoC. */ #define FSL_FEATURE_SOC_TEMPMON_COUNT (1) /* @brief TMR availability on the SoC. */ #define FSL_FEATURE_SOC_TMR_COUNT (4) -/* @brief TPM availability on the SoC. */ -#define FSL_FEATURE_SOC_TPM_COUNT (0) -/* @brief TRGMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) -/* @brief TRIAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) /* @brief TRNG availability on the SoC. */ #define FSL_FEATURE_SOC_TRNG_COUNT (1) /* @brief TSC availability on the SoC. */ #define FSL_FEATURE_SOC_TSC_COUNT (1) -/* @brief TSI availability on the SoC. */ -#define FSL_FEATURE_SOC_TSI_COUNT (0) -/* @brief TSTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TSTMR_COUNT (0) -/* @brief UART availability on the SoC. */ -#define FSL_FEATURE_SOC_UART_COUNT (0) -/* @brief USART availability on the SoC. */ -#define FSL_FEATURE_SOC_USART_COUNT (0) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (0) /* @brief USBHS availability on the SoC. */ #define FSL_FEATURE_SOC_USBHS_COUNT (2) -/* @brief USBDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBDCD_COUNT (0) -/* @brief USBFSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBFSH_COUNT (0) -/* @brief USBHSD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSD_COUNT (0) -/* @brief USBHSDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) -/* @brief USBHSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSH_COUNT (0) /* @brief USBNC availability on the SoC. */ #define FSL_FEATURE_SOC_USBNC_COUNT (2) /* @brief USBPHY availability on the SoC. */ #define FSL_FEATURE_SOC_USBPHY_COUNT (2) -/* @brief USB_HSIC availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_HSIC_COUNT (0) -/* @brief USB_OTG availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_OTG_COUNT (0) -/* @brief USBVREG availability on the SoC. */ -#define FSL_FEATURE_SOC_USBVREG_COUNT (0) /* @brief USDHC availability on the SoC. */ #define FSL_FEATURE_SOC_USDHC_COUNT (2) -/* @brief UTICK availability on the SoC. */ -#define FSL_FEATURE_SOC_UTICK_COUNT (0) -/* @brief VIU availability on the SoC. */ -#define FSL_FEATURE_SOC_VIU_COUNT (0) -/* @brief VREF availability on the SoC. */ -#define FSL_FEATURE_SOC_VREF_COUNT (0) -/* @brief VFIFO availability on the SoC. */ -#define FSL_FEATURE_SOC_VFIFO_COUNT (0) /* @brief WDOG availability on the SoC. */ #define FSL_FEATURE_SOC_WDOG_COUNT (2) -/* @brief WKPU availability on the SoC. */ -#define FSL_FEATURE_SOC_WKPU_COUNT (0) -/* @brief WWDT availability on the SoC. */ -#define FSL_FEATURE_SOC_WWDT_COUNT (0) -/* @brief XBAR availability on the SoC. */ -#define FSL_FEATURE_SOC_XBAR_COUNT (0) /* @brief XBARA availability on the SoC. */ #define FSL_FEATURE_SOC_XBARA_COUNT (1) /* @brief XBARB availability on the SoC. */ #define FSL_FEATURE_SOC_XBARB_COUNT (2) -/* @brief XCVR availability on the SoC. */ -#define FSL_FEATURE_SOC_XCVR_COUNT (0) -/* @brief XRDC availability on the SoC. */ -#define FSL_FEATURE_SOC_XRDC_COUNT (0) -/* @brief XTALOSC availability on the SoC. */ -#define FSL_FEATURE_SOC_XTALOSC_COUNT (0) /* @brief XTALOSC24M availability on the SoC. */ #define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1) -/* @brief ZLL availability on the SoC. */ -#define FSL_FEATURE_SOC_ZLL_COUNT (0) /* ADC module features */ @@ -582,6 +167,11 @@ /* @brief Remove ALT Clock selection feature. */ #define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1) +/* ADC_ETC module features */ + +/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */ +#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1) + /* AOI module features */ /* @brief Maximum value of input mux. */ @@ -666,6 +256,29 @@ /* @brief Has Additional 1588 Timer Channel Interrupt. */ #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0) +/* FLEXIO module features */ + +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200404) + /* FLEXRAM module features */ /* @brief Bank size */ @@ -697,6 +310,15 @@ /* @brief Supports IRQ 0-31. */ #define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1) +/* IGPIO module features */ + +/* @brief Has data register set DR_SET. */ +#define FSL_FEATURE_IGPIO_HAS_DR_SET (1) +/* @brief Has data register clear DR_CLEAR. */ +#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1) +/* @brief Has data register toggle DR_TOGGLE. */ +#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1) + /* LCDIF module features */ /* @brief LCDIF does not support alpha support. */ @@ -912,7 +534,7 @@ /* @brief There is CORE0_RST bit in SCR register. */ #define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1) /* @brief There is LOCKUP_RST bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (1) +#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (0) /* @brief There is SWRC bit in SCR register. */ #define FSL_FEATURE_SRC_HAS_SCR_SWRC (0) /* @brief There is EIM_RST bit in SCR register. */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct index f3cbb93fac..4f310217c9 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct @@ -1,50 +1,63 @@ #! armcc -E /* ** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B ** ** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Reference manual: IMXRT1050RM Rev.1, 03/2018 ** Version: rev. 0.1, 2017-01-10 -** Build: b171109 +** Build: b180606 ** ** Abstract: ** Linker file for the Keil ARM C/C++ Compiler ** +** The Clear BSD License ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2018 NXP +** All rights reserved. ** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: ** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. ** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. ** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.nxp.com ** mail: support@nxp.com ** ** ################################################################### */ -#define __ram_vector_table__ 1 + +#define __ram_vector_table__ 1 + +#define __stack_size__ 0x8000 +#define __heap_size__ 0x10000 #if (defined(__ram_vector_table__)) #define __ram_vector_table_size__ 0x00000400 @@ -52,20 +65,32 @@ #define __ram_vector_table_size__ 0x00000000 #endif +#define m_flash_config_start 0x60000000 +#define m_flash_config_size 0x00001000 + +#define m_ivt_start 0x60001000 +#define m_ivt_size 0x00001000 + #define m_interrupts_start 0x60002000 #define m_interrupts_size 0x00000400 #define m_text_start 0x60002400 #define m_text_size 0x03FFDC00 +#define m_data_start 0x80000000 +#define m_data_size 0x01E00000 + +#define m_ncache_start 0x81E00000 +#define m_ncache_size 0x00200000 + #define m_interrupts_ram_start 0x20000000 #define m_interrupts_ram_size __ram_vector_table_size__ -#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size) -#define m_data_size (0x00020000 - m_interrupts_ram_size) +#define m_data2_start (m_interrupts_ram_start + m_interrupts_ram_size) +#define m_data2_size (0x00020000 - m_interrupts_ram_size) -#define m_data2_start 0x20200000 -#define m_data2_size 0x00040000 +#define m_data3_start 0x20200000 +#define m_data3_size 0x00040000 /* Sizes */ #if (defined(__stack_size__)) @@ -80,11 +105,20 @@ #define Heap_Size 0x0400 #endif -LR_IROM1 m_interrupts_start m_text_start+m_text_size-m_interrupts_size { ; load region size_region - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address +LR_IROM1 m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region + RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address + * (.boot_hdr.conf, +FIRST) + } + + RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address + * (.boot_hdr.ivt, +FIRST) + * (.boot_hdr.boot_data) + * (.boot_hdr.dcd_data) + } + VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address * (RESET,+FIRST) } - ER_IROM1 m_text_start m_text_size { ; load address = execution address + ER_IROM1 m_text_start FIXED m_text_size { ; load address = execution address * (InRoot$$Sections) .ANY (+RO) } @@ -98,12 +132,16 @@ LR_IROM1 m_interrupts_start m_text_start+m_text_size-m_interrupts_size { ; loa #endif RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data .ANY (+RW +ZI) - * (NonCacheable.init) - * (NonCacheable) + *(m_usb_dma_init_data) + *(m_usb_dma_noninit_data) } RW_IRAM1 +0 EMPTY Heap_Size { ; Heap region growing up } ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down } + RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data + * (NonCacheable.init) + * (NonCacheable) + } } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/startup_MIMXRT1052.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/startup_MIMXRT1052.S index 22cd46e7ba..a40c03d6ac 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/startup_MIMXRT1052.S +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/startup_MIMXRT1052.S @@ -1,38 +1,45 @@ -; * --------------------------------------------------------------------------------------- +; * ------------------------------------------------------------------------- ; * @file: startup_MIMXRT1052.s ; * @purpose: CMSIS Cortex-M7 Core Device Startup File ; * MIMXRT1052 ; * @version: 0.1 ; * @date: 2017-1-10 -; * @build: b170927 -; * --------------------------------------------------------------------------------------- +; * @build: b180509 +; * ------------------------------------------------------------------------- ; * +; * The Clear BSD License ; * Copyright 1997-2016 Freescale Semiconductor, Inc. -; * Copyright 2016-2017 NXP -; * Redistribution and use in source and binary forms, with or without modification, -; * are permitted provided that the following conditions are met: +; * Copyright 2016-2018 NXP +; * All rights reserved. ; * -; * 1. Redistributions of source code must retain the above copyright notice, this list -; * of conditions and the following disclaimer. +; * Redistribution and use in source and binary forms, with or without +; * modification, are permitted (subject to the limitations in the +; * disclaimer below) provided that the following conditions are met: ; * -; * 2. Redistributions in binary form must reproduce the above copyright notice, this -; * list of conditions and the following disclaimer in the documentation and/or -; * other materials provided with the distribution. +; * * Redistributions of source code must retain the above copyright +; * notice, this list of conditions and the following disclaimer. ; * -; * 3. Neither the name of the copyright holder nor the names of its -; * contributors may be used to endorse or promote products derived from this -; * software without specific prior written permission. +; * * Redistributions in binary form must reproduce the above copyright +; * notice, this list of conditions and the following disclaimer in the +; * documentation and/or other materials provided with the distribution. ; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * * Neither the name of the copyright holder nor the names of its +; * contributors may be used to endorse or promote products derived from +; * this software without specific prior written permission. +; * +; * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +; * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +; * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +; * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +; * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +; * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +; * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +; * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ; * ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ; * diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld index a98dce74a8..d39ceb05e1 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld @@ -1,42 +1,51 @@ /* ** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B ** ** Compiler: GNU C Compiler -** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Reference manual: IMXRT1050RM Rev.1, 03/2018 ** Version: rev. 0.1, 2017-01-10 -** Build: b171108 +** Build: b180509 ** ** Abstract: ** Linker file for the GNU C Compiler ** +** The Clear BSD License ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2018 NXP +** All rights reserved. ** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: ** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. ** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. ** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.nxp.com ** mail: support@nxp.com @@ -49,15 +58,8 @@ ENTRY(Reset_Handler) __ram_vector_table__ = 1; -/* With the RTOS in use, this does not affect the main stack size. The size of - * the stack where main runs is determined via the RTOS. */ -__stack_size__ = 0x400; - -/* This is the guaranteed minimum available heap size for an application. When - * uVisor is enabled, this is also the maximum available heap size. The - * HEAP_SIZE value is set by uVisor porters to balance the size of the legacy - * heap and the page heap in uVisor applications. */ -__heap_size__ = 0x1000; +__stack_size__ = 0x8000; +__heap_size__ = 0x10000; HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; @@ -66,15 +68,38 @@ M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0; /* Specify the memory areas */ MEMORY { + m_flash_config (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00 - m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 - m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 + m_data (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 + m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data3 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 } /* Define output sections */ SECTIONS { + .flash_config : + { + . = ALIGN(4); + __FLASH_BASE = .; + KEEP(* (.boot_hdr.conf)) /* flash config section */ + . = ALIGN(4); + } > m_flash_config + + ivt_begin= ORIGIN(m_flash_config) + LENGTH(m_flash_config); + + .ivt : AT(ivt_begin) + { + . = ALIGN(4); + KEEP(* (.boot_hdr.ivt)) /* ivt section */ + KEEP(* (.boot_hdr.boot_data)) /* boot section */ + KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ + . = ALIGN(4); + } > m_ivt + /* The startup code goes first into internal RAM */ .interrupts : { @@ -182,7 +207,7 @@ SECTIONS . += M_VECTOR_RAM_SIZE; . = ALIGN(4); __interrupts_ram_end__ = .; /* Define a global symbol at data end */ - } > m_data + } > m_data2 __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; @@ -207,14 +232,14 @@ SECTIONS *(NonCacheable.init) . = ALIGN(4); __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ - } > m_data + } > m_ncache . = __noncachedata_init_end__; .ncache : { *(NonCacheable) . = ALIGN(4); __noncachedata_end__ = .; /* define a global symbol at ncache data end */ - } > m_data + } > m_ncache __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); text_end = ORIGIN(m_text) + LENGTH(m_text); diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/startup_MIMXRT1052.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/startup_MIMXRT1052.S index 05c1004bb9..a35793b80b 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/startup_MIMXRT1052.S +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/startup_MIMXRT1052.S @@ -1,38 +1,45 @@ -/* ---------------------------------------------------------------------------------------*/ -/* @file: startup_MIMXRT1052.s */ -/* @purpose: CMSIS Cortex-M7 Core Device Startup File */ -/* MIMXRT1052 */ -/* @version: 0.1 */ -/* @date: 2017-1-10 */ -/* @build: b170927 */ -/* ---------------------------------------------------------------------------------------*/ -/* */ -/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2017 NXP */ -/* Redistribution and use in source and binary forms, with or without modification, */ -/* are permitted provided that the following conditions are met: */ -/* */ -/* 1. Redistributions of source code must retain the above copyright notice, this list */ -/* of conditions and the following disclaimer. */ -/* */ -/* 2. Redistributions in binary form must reproduce the above copyright notice, this */ -/* list of conditions and the following disclaimer in the documentation and/or */ -/* other materials provided with the distribution. */ -/* */ -/* 3. Neither the name of the copyright holder nor the names of its */ -/* contributors may be used to endorse or promote products derived from this */ -/* software without specific prior written permission. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ -/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ -/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ -/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ -/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ -/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ -/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ -/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ -/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ -/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ------------------------------------------------------------------------- */ +/* @file: startup_MIMXRT1052.s */ +/* @purpose: CMSIS Cortex-M7 Core Device Startup File */ +/* MIMXRT1052 */ +/* @version: 0.1 */ +/* @date: 2017-1-10 */ +/* @build: b180509 */ +/* ------------------------------------------------------------------------- */ +/* */ +/* The Clear BSD License */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2018 NXP */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted (subject to the limitations in the */ +/* disclaimer below) provided that the following conditions are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of the copyright holder nor the names of its */ +/* contributors may be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE */ +/* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT */ +/* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED */ +/* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ +/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE */ +/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */ +/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */ +/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */ +/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */ +/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN */ +/* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /*****************************************************************************/ /* Version: GCC for ARM Embedded Processors */ /*****************************************************************************/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf index 49473b2e0d..7bc7fe409c 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf @@ -1,51 +1,60 @@ /* ** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B ** ** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Reference manual: IMXRT1050RM Rev.1, 03/2018 ** Version: rev. 0.1, 2017-01-10 -** Build: b170927 +** Build: b180509 ** ** Abstract: ** Linker file for the IAR ANSI C/C++ Compiler for ARM ** +** The Clear BSD License ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2018 NXP +** All rights reserved. ** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: ** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. ** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. ** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.nxp.com ** mail: support@nxp.com ** ** ################################################################### */ + define symbol __ram_vector_table__ = 1; -/* Heap 1/4 of ram and stack 1/8 */ define symbol __stack_size__=0x8000; define symbol __heap_size__=0x10000; @@ -67,6 +76,17 @@ define symbol m_data_end = 0x2001FFFF; define symbol m_data2_start = 0x20200000; define symbol m_data2_end = 0x2023FFFF; +define symbol m_data3_start = 0x80000000; +define symbol m_data3_end = 0x81DFFFFF; + +define symbol m_ncache_start = 0x81E00000; +define symbol m_ncache_end = 0x81FFFFFF; + +define exported symbol m_boot_hdr_conf_start = 0x60000000; +define symbol m_boot_hdr_ivt_start = 0x60001000; +define symbol m_boot_hdr_boot_data_start = 0x60001020; +define symbol m_boot_hdr_dcd_data_start = 0x60001030; + /* Sizes */ if (isdefinedsymbol(__stack_size__)) { define symbol __size_cstack__ = __stack_size__; @@ -88,26 +108,35 @@ define memory mem with size = 4G; define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region DATA_region = mem:[from m_data_start to m_data_end]; define region DATA2_region = mem:[from m_data2_start to m_data2_end]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end]; define block CSTACK with alignment = 8, size = __size_cstack__ { }; define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; -define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block RW { first readwrite, section m_usb_dma_init_data }; +define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; +define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; initialize by copy { readwrite, section .textrw }; do not initialize { section .noinit }; place at address mem: m_interrupts_start { readonly section .intvec }; +place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; +place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; +place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; +place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; + +keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; + place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in DATA_region { block NCACHE_VAR }; +place in DATA3_region { block RW }; +place in DATA3_region { block ZI }; +place in DATA3_region { last block HEAP }; place in CSTACK_region { block CSTACK }; +place in NCACHE_region { block NCACHE_VAR }; place in m_interrupts_ram_region { section m_interrupts_ram }; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/startup_MIMXRT1052.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/startup_MIMXRT1052.S index 6662e38884..620c96ee70 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/startup_MIMXRT1052.S +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/startup_MIMXRT1052.S @@ -1,38 +1,45 @@ -; --------------------------------------------------------------------------------------- +; ------------------------------------------------------------------------- ; @file: startup_MIMXRT1052.s ; @purpose: CMSIS Cortex-M7 Core Device Startup File ; MIMXRT1052 ; @version: 0.1 ; @date: 2017-1-10 -; @build: b170927 -; --------------------------------------------------------------------------------------- +; @build: b180509 +; ------------------------------------------------------------------------- ; +; The Clear BSD License ; Copyright 1997-2016 Freescale Semiconductor, Inc. -; Copyright 2016-2017 NXP -; Redistribution and use in source and binary forms, with or without modification, -; are permitted provided that the following conditions are met: +; Copyright 2016-2018 NXP +; All rights reserved. ; -; 1. Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted (subject to the limitations in the +; disclaimer below) provided that the following conditions are met: ; -; 2. Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. ; -; 3. Neither the name of the copyright holder nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. ; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * Neither the name of the copyright holder nor the names of its +; contributors may be used to endorse or promote products derived from +; this software without specific prior written permission. +; +; NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +; GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +; HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +; WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +; BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +; OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +; IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ; ; The modules in this file are included in the libraries, and may be replaced ; by any user-defined modules that define the PUBLIC symbol _program_start or diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/fsl_device_registers.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/fsl_device_registers.h index e569bbeba9..f546a9df0e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/fsl_device_registers.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/fsl_device_registers.h @@ -1,30 +1,37 @@ /* + * The Clear BSD License * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Copyright 2016-2018 NXP + * All rights reserved. * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: * - * 2. Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * * Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ @@ -36,7 +43,8 @@ * * The CPU macro should be declared in the project or makefile. */ -#if (defined(CPU_MIMXRT1052CVL5A) || defined(CPU_MIMXRT1052DVL6A)) +#if (defined(CPU_MIMXRT1052CVJ5B) || defined(CPU_MIMXRT1052CVL5B) || defined(CPU_MIMXRT1052DVJ6B) || \ + defined(CPU_MIMXRT1052DVL6B)) #define MIMXRT1052_SERIES diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.c index f505e8ec9d..c9e37381b8 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.c @@ -1,7 +1,9 @@ /* ** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B ** ** Compilers: Keil ARM C/C++ Compiler ** Freescale C/C++ for Embedded ARM @@ -9,41 +11,48 @@ ** IAR ANSI C/C++ Compiler for ARM ** MCUXpresso Compiler ** -** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Reference manual: IMXRT1050RM Rev.1, 03/2018 ** Version: rev. 0.1, 2017-01-10 -** Build: b170927 +** Build: b180509 ** ** Abstract: ** Provides a system configuration function and a global variable that ** contains the system frequency. It configures the device and initializes ** the oscillator (PLL) that is part of the microcontroller device. ** +** The Clear BSD License ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2018 NXP +** All rights reserved. ** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: ** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. ** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. ** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.nxp.com ** mail: support@nxp.com @@ -86,6 +95,15 @@ void SystemInit (void) { SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ +#if defined(__MCUXPRESSO) + extern uint32_t g_pfnVectors[]; // Vector table defined in startup code + SCB->VTOR = (uint32_t)g_pfnVectors; +#endif + +/* Disable Watchdog Power Down Counter */ +WDOG1->WMCR &= ~WDOG_WMCR_PDE_MASK; +WDOG2->WMCR &= ~WDOG_WMCR_PDE_MASK; + /* Watchdog disable */ #if (DISABLE_WDOG) @@ -110,12 +128,17 @@ void SystemInit (void) { /* Enable instruction and data caches */ #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT - SCB_EnableICache(); + if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) { + SCB_EnableICache(); + } #endif #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT - SCB_EnableDCache(); + if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) { + SCB_EnableDCache(); + } #endif + SystemInitHook(); } /* ---------------------------------------------------------------------------- @@ -135,15 +158,26 @@ void SystemCoreClockUpdate (void) { { /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ case CCM_CBCMR_PERIPH_CLK2_SEL(0U): - freq = (24000000UL * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + if(CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) + { + freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + freq = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + } break; /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ case CCM_CBCMR_PERIPH_CLK2_SEL(1U): - freq = 24000000UL; + freq = CPU_XTAL_CLK_HZ; break; case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): default: freq = 0U; @@ -155,11 +189,29 @@ void SystemCoreClockUpdate (void) { /* Pre_Periph_clk ---> Periph_clk */ else { - PLL1MainClock = ((24000000UL * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> - CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U); + /* check if pll is bypassed */ + if(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK) + { + PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U); + } - PLL2MainClock = (24000000UL * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U)); - PLL2MainClock += ((uint64_t)24000000UL * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + /* check if pll is bypassed */ + if(CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) + { + PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + PLL2MainClock = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U)); + } + PLL2MainClock += ((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) @@ -193,3 +245,11 @@ void SystemCoreClockUpdate (void) { SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U)); } + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.h index 2a559acf31..8d9f2073d8 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.h @@ -1,7 +1,9 @@ /* ** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B ** ** Compilers: Keil ARM C/C++ Compiler ** Freescale C/C++ for Embedded ARM @@ -9,41 +11,48 @@ ** IAR ANSI C/C++ Compiler for ARM ** MCUXpresso Compiler ** -** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Reference manual: IMXRT1050RM Rev.1, 03/2018 ** Version: rev. 0.1, 2017-01-10 -** Build: b170927 +** Build: b180509 ** ** Abstract: ** Provides a system configuration function and a global variable that ** contains the system frequency. It configures the device and initializes ** the oscillator (PLL) that is part of the microcontroller device. ** +** The Clear BSD License ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2018 NXP +** All rights reserved. ** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: ** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. ** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. ** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.nxp.com ** mail: support@nxp.com @@ -84,6 +93,9 @@ extern "C" { #define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */ +#define CPU_CLK1_HZ 0UL /* Value of the CLK1 (select the CLK1_N/CLK1_P as source) frequency in Hz */ + /* If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned. */ + #define DEFAULT_SYSTEM_CLOCK 528000000UL /* Default System clock value */ @@ -116,6 +128,18 @@ void SystemInit (void); */ void SystemCoreClockUpdate (void); +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.c index 43a0f1445b..d3cdb6f645 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,6 +34,12 @@ #include "fsl_adc.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.adc_12b1msps_sar" +#endif + + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h index e5b6b8c16f..8b46fb1ba5 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.c index 08f6bdb45a..f17dcc3ba7 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,6 +34,11 @@ #include "fsl_adc_etc.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.adc_etc" +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -90,7 +99,11 @@ void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config) /* Set ADC_ETC_CTRL register. */ tmp32 = ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(config->TSC0triggerPriority) | ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(config->TSC1triggerPriority) | - ADC_ETC_CTRL_PRE_DIVIDER(config->clockPreDivider) | ADC_ETC_CTRL_TRIG_ENABLE(config->XBARtriggerMask); + ADC_ETC_CTRL_PRE_DIVIDER(config->clockPreDivider) | ADC_ETC_CTRL_TRIG_ENABLE(config->XBARtriggerMask) +#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL + | ADC_ETC_CTRL_DMA_MODE_SEL(config->dmaMode) +#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/ + ; if (config->enableTSCBypass) { tmp32 |= ADC_ETC_CTRL_TSC_BYPASS_MASK; @@ -124,6 +137,9 @@ void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config) config->enableTSCBypass = true; config->enableTSC0Trigger = false; config->enableTSC1Trigger = false; +#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL + config->dmaMode = kADC_ETC_TrigDMAWithLatchedSignal; +#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/ config->TSC0triggerPriority = 0U; config->TSC1triggerPriority = 0U; config->clockPreDivider = 0U; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.h index fd14a129ee..06cb5675b0 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -87,6 +91,17 @@ typedef enum _adc_etc_interrupt_enable kADC_ETC_Done2InterruptEnable = 3U, /* Enable the DONE2 interrupt when ADC conversions complete. */ } adc_etc_interrupt_enable_t; +#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL +/*! +* @brief DMA mode selection. +*/ +typedef enum _adc_etc_dma_mode_selection +{ + kADC_ETC_TrigDMAWithLatchedSignal = 0U, /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */ + kADC_ETC_TrigDMAWithPulsedSignal = 1U, /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */ +} adc_etc_dma_mode_selection_t; +#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/ + /*! * @brief ADC_ETC configuration. */ @@ -96,6 +111,9 @@ typedef struct _adc_etc_config Otherwise TSC would trigger ADC through ADC_ETC. */ bool enableTSC0Trigger; /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */ bool enableTSC1Trigger; /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/ +#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL + adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */ +#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/ uint32_t TSC0triggerPriority; /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */ uint32_t TSC1triggerPriority; /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */ uint32_t clockPreDivider; /* Pre-divider for trig delay and interval. Available range is 0-255. diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.c index e389272955..91c091c75e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -34,6 +38,12 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.aipstz" +#endif + + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.h index b98fdafc8d..9d46f2e6a5 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -66,9 +70,9 @@ typedef enum _aipstz_master { /*! @brief List of AIPSTZ peripheral access control configuration.*/ typedef enum _aipstz_peripheral_access_control { kAIPSTZ_PeripheralAllowUntrustedMaster = 1U, - kAIPSTZ_PeripheralWriteProtected = (1U < 1), - kAIPSTZ_PeripheralRequireSupervisor = (1U < 2), - kAIPSTZ_PeripheralAllowBufferedWrite = (1U < 2) + kAIPSTZ_PeripheralWriteProtected = (1U << 1), + kAIPSTZ_PeripheralRequireSupervisor = (1U << 2), + kAIPSTZ_PeripheralAllowBufferedWrite = (1U << 3) } aipstz_peripheral_access_control_t; /*! @brief List of AIPSTZ peripherals. Organized by register offset for higher 32 bits, width for the 8-15 bits and shift for lower 8 bits.*/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.c index 17bfb944da..c20f13c928 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -29,6 +33,12 @@ */ #include "fsl_aoi.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.aoi" +#endif + + /******************************************************************************* * Variables ******************************************************************************/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.h index 9bf4947673..47dbd9b9ca 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.c index dd079e578c..15a804b0c5 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright 2017 NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -34,6 +38,12 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.bee" +#endif + + /******************************************************************************* * Variables ******************************************************************************/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.h index 11d4ef3010..1eb6ae1ed6 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright 2017 NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.c index 02740c45e5..595fefe733 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -33,7 +37,13 @@ /******************************************************************************* * Definitions ******************************************************************************/ -#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cache_armv7_m7" +#endif + +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT #define L2CACHE_OPERATION_TIMEOUT 0xFFFFFU #define L2CACHE_8WAYS_MASK 0xFFU #define L2CACHE_16WAYS_MASK 0xFFFFU @@ -126,7 +136,7 @@ static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t reg /* Set the opeartion for all ways/entries of the cache. */ *(uint32_t *)regAddr = mask; /* Waiting for until the operation is complete. */ - while ((*(uint32_t *)regAddr & mask) && timeout) + while ((*(volatile uint32_t *)regAddr & mask) && timeout) { __ASM("nop"); timeout--; @@ -397,7 +407,7 @@ void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; } } -#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte) { @@ -420,41 +430,41 @@ void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte) void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) { -#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT #if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT L2CACHE_InvalidateByRange(address, size_byte); #endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ -#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ L1CACHE_InvalidateICacheByRange(address, size_byte); } void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) { -#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT #if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT L2CACHE_InvalidateByRange(address, size_byte); #endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ -#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ L1CACHE_InvalidateDCacheByRange(address, size_byte); } void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte) { L1CACHE_CleanDCacheByRange(address, size_byte); -#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT #if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT L2CACHE_CleanByRange(address, size_byte); #endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ -#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ } void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) { L1CACHE_CleanInvalidateDCacheByRange(address, size_byte); -#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT #if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT L2CACHE_CleanInvalidateByRange(address, size_byte); #endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ -#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.h index eed78bee45..a041ea2a34 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -47,15 +51,15 @@ #define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ -#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT #ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT #define FSL_SDK_DISBLE_L2CACHE_PRESENT 0 #endif -#endif /* (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ /******************************************************************************* * Definitions ******************************************************************************/ -#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT /*! @brief Number of level 2 cache controller ways. */ typedef enum _l2cache_way_num @@ -133,7 +137,7 @@ typedef struct _l2cache_config /* ------------------------ other settings -------------------------------------- */ l2cache_writealloc_t writeAlloc;/*!< Write allcoate force option. */ } l2cache_config_t; -#endif /* (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ /******************************************************************************* * API ******************************************************************************/ @@ -286,7 +290,7 @@ static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32 } /*@}*/ -#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT /*! * @name Control for L2 pl310 cache *@{ @@ -414,7 +418,7 @@ void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte); void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable); /*@}*/ -#endif /* (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ /*! * @name Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.c index 342f0aba92..fba76beac2 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.c @@ -1,8 +1,11 @@ /* + * The Clear BSD License * Copyright 2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -15,6 +18,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -27,12 +31,11 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "fsl_common.h" #include "fsl_clock.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif /******************************************************************************* * Variables @@ -47,9 +50,17 @@ uint32_t g_rtcXtalFreq; * Prototypes ******************************************************************************/ +/*! + * @brief Get the periph clock frequency. + * + * @return Periph clock frequency in Hz. + */ +static uint32_t CLOCK_GetPeriphClkFreq(void); + /******************************************************************************* * Code ******************************************************************************/ + static uint32_t CLOCK_GetPeriphClkFreq(void) { uint32_t freq; @@ -70,6 +81,9 @@ static uint32_t CLOCK_GetPeriphClkFreq(void) break; case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): default: freq = 0U; @@ -100,7 +114,8 @@ static uint32_t CLOCK_GetPeriphClkFreq(void) /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */ case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): - freq = CLOCK_GetPllFreq(kCLOCK_PllArm) / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); + freq = CLOCK_GetPllFreq(kCLOCK_PllArm) / + (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); break; default: @@ -158,10 +173,11 @@ uint32_t CLOCK_GetFreq(clock_name_t name) switch (name) { case kCLOCK_CpuClk: - /* Periph_clk ---> AHB Clock */ + /* Periph_clk ---> AHB Clock */ case kCLOCK_AhbClk: /* Periph_clk ---> AHB Clock */ - freq = CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); + freq = + CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); break; case kCLOCK_SemcClk: @@ -190,7 +206,8 @@ uint32_t CLOCK_GetFreq(clock_name_t name) case kCLOCK_IpgClk: /* Periph_clk ---> AHB Clock ---> IPG Clock */ - freq = CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); + freq = + CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); freq /= (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U); break; @@ -237,13 +254,10 @@ uint32_t CLOCK_GetFreq(clock_name_t name) freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3); break; case kCLOCK_EnetPll0Clk: - freq = CLOCK_GetPllFreq(kCLOCK_PllEnet0); + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet); break; case kCLOCK_EnetPll1Clk: - freq = CLOCK_GetPllFreq(kCLOCK_PllEnet1); - break; - case kCLOCK_EnetPll2Clk: - freq = CLOCK_GetPllFreq(kCLOCK_PllEnet2); + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet25M); break; case kCLOCK_AudioPllClk: freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); @@ -259,14 +273,76 @@ uint32_t CLOCK_GetFreq(clock_name_t name) return freq; } +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq) +{ + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK; + USB1->USBCMD |= USBHS_USBCMD_RST_MASK; + for (volatile uint32_t i = 0; i < 400000; + i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + { + __ASM("nop"); + } + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | + (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq) +{ + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK; + USB2->USBCMD |= USBHS_USBCMD_RST_MASK; + for (volatile uint32_t i = 0; i < 400000; + i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + { + __ASM("nop"); + } + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | + (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + if (CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK) + { + CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + } + else + { + CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll); + } + USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; + + USBPHY1->PWD = 0; + USBPHY1->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK; + return true; +} + +void CLOCK_DisableUsbhs0PhyPllClock(void) +{ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} + void CLOCK_InitArmPll(const clock_arm_pll_config_t *config) { - CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_ENABLE_MASK | - CCM_ANALOG_PLL_ARM_DIV_SELECT(config->loopDivider); + /* Bypass PLL first */ + CCM_ANALOG->PLL_ARM = (CCM_ANALOG->PLL_ARM & (~CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_ARM_BYPASS_MASK | CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_ARM = + (CCM_ANALOG->PLL_ARM & (~(CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK | CCM_ANALOG_PLL_ARM_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_ARM_ENABLE_MASK | CCM_ANALOG_PLL_ARM_DIV_SELECT(config->loopDivider); while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0) { } + + /* Disable Bypass */ + CCM_ANALOG->PLL_ARM &= ~CCM_ANALOG_PLL_ARM_BYPASS_MASK; } void CLOCK_DeinitArmPll(void) @@ -276,12 +352,20 @@ void CLOCK_DeinitArmPll(void) void CLOCK_InitSysPll(const clock_sys_pll_config_t *config) { - CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_ENABLE_MASK | - CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider); + /* Bypass PLL first */ + CCM_ANALOG->PLL_SYS = (CCM_ANALOG->PLL_SYS & (~CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_SYS_BYPASS_MASK | CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_SYS = + (CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider); while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0) { } + + /* Disable Bypass */ + CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_BYPASS_MASK; } void CLOCK_DeinitSysPll(void) @@ -291,14 +375,20 @@ void CLOCK_DeinitSysPll(void) void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config) { - CCM_ANALOG->PLL_USB1 = CCM_ANALOG_PLL_USB1_ENABLE_MASK | - CCM_ANALOG_PLL_USB1_POWER_MASK | - CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK | - CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider); + /* Bypass PLL first */ + CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_USB1_BYPASS_MASK | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)) | + CCM_ANALOG_PLL_USB1_ENABLE_MASK | CCM_ANALOG_PLL_USB1_POWER_MASK | + CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider); while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0) { } + + /* Disable Bypass */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; } void CLOCK_DeinitUsb1Pll(void) @@ -308,14 +398,20 @@ void CLOCK_DeinitUsb1Pll(void) void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config) { - CCM_ANALOG->PLL_USB2 = CCM_ANALOG_PLL_USB2_ENABLE_MASK | - CCM_ANALOG_PLL_USB2_POWER_MASK | - CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK | - CCM_ANALOG_PLL_USB2_DIV_SELECT(config->loopDivider); + /* Bypass PLL first */ + CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_USB2_BYPASS_MASK | CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)) | + CCM_ANALOG_PLL_USB2_ENABLE_MASK | CCM_ANALOG_PLL_USB2_POWER_MASK | + CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB2_DIV_SELECT(config->loopDivider); while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0) { } + + /* Disable Bypass */ + CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_BYPASS_MASK; } void CLOCK_DeinitUsb2Pll(void) @@ -328,6 +424,10 @@ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) uint32_t pllAudio; uint32_t misc2 = 0; + /* Bypass PLL first */ + CCM_ANALOG->PLL_AUDIO = (CCM_ANALOG->PLL_AUDIO & (~CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_AUDIO_BYPASS_MASK | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(config->src); + CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator); CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(config->denominator); @@ -348,7 +448,9 @@ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) * | 16 | 0 | 3 | * ------------------------------------------------------------------------ */ - pllAudio = CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider); + pllAudio = + (CCM_ANALOG->PLL_AUDIO & (~(CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK | CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider); switch (config->postDivider) { @@ -376,14 +478,17 @@ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) break; } - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)) - | misc2; + CCM_ANALOG->MISC2 = + (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)) | misc2; CCM_ANALOG->PLL_AUDIO = pllAudio; while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0) { } + + /* Disable Bypass */ + CCM_ANALOG->PLL_AUDIO &= ~CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; } void CLOCK_DeinitAudioPll(void) @@ -396,6 +501,10 @@ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config) uint32_t pllVideo; uint32_t misc2 = 0; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(config->src); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(config->numerator); CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(config->denominator); @@ -416,7 +525,9 @@ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config) * | 16 | 0 | 3 | * ------------------------------------------------------------------------ */ - pllVideo = CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(config->loopDivider); + pllVideo = + (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(config->loopDivider); switch (config->postDivider) { @@ -451,6 +562,9 @@ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config) while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) { } + + /* Disable Bypass */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; } void CLOCK_DeinitVideoPll(void) @@ -460,30 +574,32 @@ void CLOCK_DeinitVideoPll(void) void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config) { - uint32_t enet_pll = CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(config->loopDivider1) | - CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(config->loopDivider0); + uint32_t enet_pll = CCM_ANALOG_PLL_ENET_DIV_SELECT(config->loopDivider); - if (config->enableClkOutput0) + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_ENET_BYPASS_MASK | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(config->src); + + if (config->enableClkOutput) { - enet_pll |= CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK; + enet_pll |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; } - if (config->enableClkOutput1) - { - enet_pll |= CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK; - } - - if (config->enableClkOutput2) + if (config->enableClkOutput25M) { enet_pll |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; } - CCM_ANALOG->PLL_ENET = enet_pll; + CCM_ANALOG->PLL_ENET = + (CCM_ANALOG->PLL_ENET & (~(CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) | + enet_pll; /* Wait for stable */ while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) { } + + /* Disable Bypass */ + CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK; } void CLOCK_DeinitEnetPll(void) @@ -498,24 +614,38 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll) uint64_t freqTmp; const uint32_t enetRefClkFreq[] = { - 25000000U, /* 25M */ - 50000000U, /* 50M */ + 25000000U, /* 25M */ + 50000000U, /* 50M */ 100000000U, /* 100M */ - 125000000U /* 125M */ + 125000000U /* 125M */ }; + /* check if PLL is enabled */ + if (!CLOCK_IsPllEnabled(CCM_ANALOG, pll)) + { + return 0U; + } + + /* get pll reference clock */ + freq = CLOCK_GetPllBypassRefClk(CCM_ANALOG, pll); + + /* check if pll is bypassed */ + if (CLOCK_IsPllBypassed(CCM_ANALOG, pll)) + { + return freq; + } + switch (pll) { case kCLOCK_PllArm: - freq = ((CLOCK_GetOscFreq() * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> - CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U); + freq = ((freq * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> + 1U); break; - case kCLOCK_PllSys: - freq = CLOCK_GetOscFreq(); - /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ - freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + freqTmp = + ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) { @@ -530,16 +660,16 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll) break; case kCLOCK_PllUsb1: - freq = (CLOCK_GetOscFreq() * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + freq = (freq * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); break; case kCLOCK_PllAudio: - freq = CLOCK_GetOscFreq(); - /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ - divSelect = (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT; + divSelect = + (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT; - freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_AUDIO_DENOM)); + freqTmp = + ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_AUDIO_DENOM)); freq = freq * divSelect + (uint32_t)freqTmp; @@ -589,12 +719,12 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll) break; case kCLOCK_PllVideo: - freq = CLOCK_GetOscFreq(); - /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ - divSelect = (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT; + divSelect = + (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT; - freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_VIDEO_DENOM)); + freqTmp = + ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_VIDEO_DENOM)); freq = freq * divSelect + (uint32_t)freqTmp; @@ -642,28 +772,20 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll) break; } break; - - case kCLOCK_PllEnet0: - divSelect = (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK) - >> CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT; + case kCLOCK_PllEnet: + divSelect = + (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT; freq = enetRefClkFreq[divSelect]; break; - case kCLOCK_PllEnet1: - divSelect = (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK) - >> CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT; - freq = enetRefClkFreq[divSelect]; - break; - - case kCLOCK_PllEnet2: - /* ref_enetpll2 if fixed at 25MHz. */ + case kCLOCK_PllEnet25M: + /* ref_enetpll1 if fixed at 25MHz. */ freq = 25000000UL; break; case kCLOCK_PllUsb2: - freq = (CLOCK_GetOscFreq() * ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) ? 22U : 20U)); + freq = (freq * ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) ? 22U : 20U)); break; - default: freq = 0U; break; @@ -677,7 +799,8 @@ void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac) uint32_t pfdIndex = (uint32_t)pfd; uint32_t pfd528; - pfd528 = CCM_ANALOG->PFD_528 & ~((CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) << (8 * pfdIndex)); + pfd528 = CCM_ANALOG->PFD_528 & + ~((CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) << (8 * pfdIndex)); /* Disable the clock output first. */ CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfdIndex)); @@ -696,7 +819,8 @@ void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac) uint32_t pfdIndex = (uint32_t)pfd; uint32_t pfd480; - pfd480 = CCM_ANALOG->PFD_480 & ~((CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) << (8 * pfdIndex)); + pfd480 = CCM_ANALOG->PFD_480 & + ~((CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) << (8 * pfdIndex)); /* Disable the clock output first. */ CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfdIndex)); @@ -765,78 +889,29 @@ uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd) default: freq = 0U; - break; + break; } freq *= 18U; return freq; } -bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq) -{ - CCM->CCGR6 |= CCM_CCGR6_CG0_MASK ; - USB1->USBCMD |= USBHS_USBCMD_RST_MASK; - for (volatile uint32_t i = 0; i < 400000; i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ - { - __ASM("nop"); - } - PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); - return true; -} - - -bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq) -{ - CCM->CCGR6 |= CCM_CCGR6_CG0_MASK ; - USB2->USBCMD |= USBHS_USBCMD_RST_MASK; - for (volatile uint32_t i = 0; i < 400000; i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ - { - __ASM("nop"); - } - PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); - return true; -} - - -bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) -{ - const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; - CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll); - USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ - USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; - - USBPHY1->PWD = 0; - USBPHY1->CTRL |= - USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | - USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | - USBPHY_CTRL_ENUTMILEVEL2_MASK | - USBPHY_CTRL_ENUTMILEVEL3_MASK; - return true; -} bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) { - const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; CLOCK_InitUsb2Pll(&g_ccmConfigUsbPll); - USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ USBPHY2->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; - USBPHY2->PWD = 0; - USBPHY2->CTRL |= - USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | - USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | - USBPHY_CTRL_ENUTMILEVEL2_MASK | - USBPHY_CTRL_ENUTMILEVEL3_MASK; + USBPHY2->PWD = 0; + USBPHY2->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK; return true; } -void CLOCK_DisableUsbhs0PhyPllClock(void) -{ - CLOCK_DeinitUsb1Pll(); - USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ -} void CLOCK_DisableUsbhs1PhyPllClock(void) { - CLOCK_DeinitUsb2Pll(); - USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ + CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK; + USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.h index 57b7df7ed1..52fd227e2e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.h @@ -1,8 +1,11 @@ /* + * The Clear BSD License * Copyright 2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -15,6 +18,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,32 +34,22 @@ #ifndef _FSL_CLOCK_H_ #define _FSL_CLOCK_H_ -#include "fsl_device_registers.h" -#include -#include -#include +#include "fsl_common.h" -/*! - * @addtogroup clock - * @{ - */ +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ /******************************************************************************* - * Definitions + * Configurations ******************************************************************************/ -#define CCM_TUPLE(reg, shift, mask, busyShift) ((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U)) -#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple) & 0xFFU)))) -#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU) -#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU)))) -#define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU) - -#define CCM_NO_BUSY_WAIT (0x20U) /*! @brief Configure whether driver controls clock * * When set to 0, peripheral drivers will enable clock in initialize function * and disable clock in de-initialize function. When set to 1, peripheral - * driver will not control the clock, application could control the clock out of + * driver will not control the clock, application could contol the clock out of * the driver. * * @note All drivers share this feature switcher. If it is set to 1, application @@ -65,12 +59,44 @@ #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 #endif +/******************************************************************************* + * Definitions + ******************************************************************************/ + /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.1.0. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) -/*@}*/ +/*! @brief CLOCK driver version 2.1.2. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/* analog pll definition */ +#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U) + +/*@}*/ +#define CCM_TUPLE(reg, shift, mask, busyShift) \ + ((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | \ + ((busyShift) << 26U)) +#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU)))) +#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU) +#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU)))) +#define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU) + +#define CCM_NO_BUSY_WAIT (0x20U) + +/*! + * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields. + */ +#define CCM_ANALOG_TUPLE(reg, shift) ((((uint32_t)(&((CCM_ANALOG_Type *)0U)->reg) & 0xFFFU) << 16U) | (shift)) +#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU) +#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \ + (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off))) +#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U) + +/*! + * @brief clock1PN frequency. + */ +#define CLKPN_FREQ 0U /*! @brief External XTAL (24M OSC/SYSOSC) clock frequency. * @@ -95,310 +121,304 @@ extern uint32_t g_rtcXtalFreq; #define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq #define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq - /*! @brief Clock ip name array for ADC. */ -#define ADC_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Adc1 \ - } - -/*! @brief Clock ip name array for ADC_5HC. */ -#define ADC_5HC_CLOCKS \ - { \ - kCLOCK_Adc_5hc \ +/*! @brief Clock ip name array for ADC. */ +#define ADC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \ } /*! @brief Clock ip name array for AOI. */ -#define AOI_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \ +#define AOI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \ } /*! @brief Clock ip name array for BEE. */ -#define BEE_CLOCKS \ - { \ - kCLOCK_Bee \ - } +#define BEE_CLOCKS \ + { \ + kCLOCK_Bee \ + } /*! @brief Clock ip name array for CMP. */ -#define CMP_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, \ - kCLOCK_Acmp3, kCLOCK_Acmp4 \ +#define CMP_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \ } /*! @brief Clock ip name array for CSI. */ -#define CSI_CLOCKS \ - { \ - kCLOCK_Csi \ +#define CSI_CLOCKS \ + { \ + kCLOCK_Csi \ } /*! @brief Clock ip name array for DCDC. */ -#define DCDC_CLOCKS \ - { \ - kCLOCK_Dcdc \ +#define DCDC_CLOCKS \ + { \ + kCLOCK_Dcdc \ } /*! @brief Clock ip name array for DCP. */ -#define DCP_CLOCKS \ - { \ - kCLOCK_Dcp \ +#define DCP_CLOCKS \ + { \ + kCLOCK_Dcp \ } /*! @brief Clock ip name array for DMAMUX_CLOCKS. */ -#define DMAMUX_CLOCKS \ - { \ - kCLOCK_Dma \ - } +#define DMAMUX_CLOCKS \ + { \ + kCLOCK_Dma \ + } /*! @brief Clock ip name array for DMA. */ -#define EDMA_CLOCKS \ - { \ - kCLOCK_Dma \ - } +#define EDMA_CLOCKS \ + { \ + kCLOCK_Dma \ + } /*! @brief Clock ip name array for ENC. */ -#define ENC_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, \ - kCLOCK_Enc3, kCLOCK_Enc4 \ +#define ENC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \ } /*! @brief Clock ip name array for ENET. */ -#define ENET_CLOCKS \ - { \ - kCLOCK_Enet \ +#define ENET_CLOCKS \ + { \ + kCLOCK_Enet \ } /*! @brief Clock ip name array for EWM. */ -#define EWM_CLOCKS \ - { \ - kCLOCK_Ewm0 \ - } +#define EWM_CLOCKS \ + { \ + kCLOCK_Ewm0 \ + } /*! @brief Clock ip name array for FLEXCAN. */ -#define FLEXCAN_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \ } - + /*! @brief Clock ip name array for FLEXCAN Peripheral clock. */ -#define FLEXCAN_PERIPH_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \ - } +#define FLEXCAN_PERIPH_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \ + } /*! @brief Clock ip name array for FLEXIO. */ -#define FLEXIO_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \ } /*! @brief Clock ip name array for FLEXRAM. */ -#define FLEXRAM_CLOCKS \ - { \ - kCLOCK_FlexRam \ - } +#define FLEXRAM_CLOCKS \ + { \ + kCLOCK_FlexRam \ + } /*! @brief Clock ip name array for FLEXSPI. */ -#define FLEXSPI_CLOCKS \ - { \ - kCLOCK_FlexSpi \ - } +#define FLEXSPI_CLOCKS \ + { \ + kCLOCK_FlexSpi \ + } + +/*! @brief Clock ip name array for FLEXSPI EXSC. */ +#define FLEXSPI_EXSC_CLOCKS \ + { \ + kCLOCK_FlexSpiExsc \ + } /*! @brief Clock ip name array for GPIO. */ -#define GPIO_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, \ - kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ +#define GPIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ } /*! @brief Clock ip name array for GPT. */ -#define GPT_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \ +#define GPT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \ } /*! @brief Clock ip name array for KPP. */ -#define KPP_CLOCKS \ - { \ - kCLOCK_Kpp \ - } - +#define KPP_CLOCKS \ + { \ + kCLOCK_Kpp \ + } + /*! @brief Clock ip name array for LCDIF. */ -#define LCDIF_CLOCKS \ - { \ - kCLOCK_Lcd \ +#define LCDIF_CLOCKS \ + { \ + kCLOCK_Lcd \ } /*! @brief Clock ip name array for LCDIF PIXEL. */ -#define LCDIF_PERIPH_CLOCKS \ - { \ - kCLOCK_LcdPixel \ +#define LCDIF_PERIPH_CLOCKS \ + { \ + kCLOCK_LcdPixel \ } /*! @brief Clock ip name array for LPI2C. */ -#define LPI2C_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, \ - kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \ - } +#define LPI2C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \ + } /*! @brief Clock ip name array for LPSPI. */ -#define LPSPI_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, \ - kCLOCK_Lpspi3, kCLOCK_Lpspi4 \ - } +#define LPSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \ + } /*! @brief Clock ip name array for LPUART. */ -#define LPUART_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, \ - kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \ - kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \ - } +#define LPUART_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \ + kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \ + } + +/*! @brief Clock ip name array for MQS. */ +#define MQS_CLOCKS \ + { \ + kCLOCK_Mqs \ + } + +/*! @brief Clock ip name array for OCRAM EXSC. */ +#define OCRAM_EXSC_CLOCKS \ + { \ + kCLOCK_OcramExsc \ + } /*! @brief Clock ip name array for PIT. */ -#define PIT_CLOCKS \ - { \ - kCLOCK_Pit \ +#define PIT_CLOCKS \ + { \ + kCLOCK_Pit \ } /*! @brief Clock ip name array for PWM. */ -#define PWM_CLOCKS \ - { \ - { \ - kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ - kCLOCK_IpInvalid \ - } \ - , \ - { \ - kCLOCK_Pwm1, kCLOCK_Pwm1,kCLOCK_Pwm1, kCLOCK_Pwm1 \ - } \ - , \ - { \ - kCLOCK_Pwm2, kCLOCK_Pwm2,kCLOCK_Pwm2, kCLOCK_Pwm2 \ - } \ - , \ - { \ - kCLOCK_Pwm3, kCLOCK_Pwm3,kCLOCK_Pwm3, kCLOCK_Pwm3 \ - } \ - , \ - { \ - kCLOCK_Pwm4, kCLOCK_Pwm4,kCLOCK_Pwm4, kCLOCK_Pwm4 \ - } \ - } +#define PWM_CLOCKS \ + { \ + { \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid \ + } \ + , {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \ + {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \ + { \ + kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \ + } \ + } /*! @brief Clock ip name array for PXP. */ -#define PXP_CLOCKS \ - { \ - kCLOCK_Pxp \ +#define PXP_CLOCKS \ + { \ + kCLOCK_Pxp \ } /*! @brief Clock ip name array for RTWDOG. */ -#define RTWDOG_CLOCKS \ - { \ - kCLOCK_Wdog3 \ - } +#define RTWDOG_CLOCKS \ + { \ + kCLOCK_Wdog3 \ + } /*! @brief Clock ip name array for SAI. */ -#define SAI_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, \ - kCLOCK_Sai3 \ +#define SAI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \ } /*! @brief Clock ip name array for SEMC. */ -#define SEMC_CLOCKS \ - { \ - kCLOCK_Semc \ +#define SEMC_CLOCKS \ + { \ + kCLOCK_Semc \ } +/*! @brief Clock ip name array for SEMC EXSC. */ +#define SEMC_EXSC_CLOCKS \ + { \ + kCLOCK_SemcExsc \ + } /*! @brief Clock ip name array for QTIMER. */ -#define TMR_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, \ - kCLOCK_Timer3, kCLOCK_Timer4 \ +#define TMR_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ } /*! @brief Clock ip name array for TRNG. */ -#define TRNG_CLOCKS \ - { \ - kCLOCK_Trng \ +#define TRNG_CLOCKS \ + { \ + kCLOCK_Trng \ } /*! @brief Clock ip name array for TSC. */ -#define TSC_CLOCKS \ - { \ - kCLOCK_Tsc \ - } - -/*! @brief Clock ip name array for WDOG. */ -#define WDOG_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \ +#define TSC_CLOCKS \ + { \ + kCLOCK_Tsc \ } +/*! @brief Clock ip name array for WDOG. */ +#define WDOG_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \ + } /*! @brief Clock ip name array for USDHC. */ -#define USDHC_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \ +#define USDHC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \ } - + /*! @brief Clock ip name array for SPDIF. */ -#define SPDIF_CLOCKS \ - { \ - kCLOCK_Spdif \ +#define SPDIF_CLOCKS \ + { \ + kCLOCK_Spdif \ } - + /*! @brief Clock ip name array for XBARA. */ -#define XBARA_CLOCKS \ - { \ - kCLOCK_Xbar1 \ - } +#define XBARA_CLOCKS \ + { \ + kCLOCK_Xbar1 \ + } /*! @brief Clock ip name array for XBARB. */ -#define XBARB_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, \ - kCLOCK_Xbar3 \ - } +#define XBARB_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \ + } /*! @brief Clock name used to get clock frequency. */ typedef enum _clock_name { - kCLOCK_CpuClk = 0x0U, /*!< CPU clock */ - kCLOCK_AhbClk = 0x1U, /*!< AHB clock */ - kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */ - kCLOCK_IpgClk = 0x3U, /*!< IPG clock */ + kCLOCK_CpuClk = 0x0U, /*!< CPU clock */ + kCLOCK_AhbClk = 0x1U, /*!< AHB clock */ + kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */ + kCLOCK_IpgClk = 0x3U, /*!< IPG clock */ - kCLOCK_OscClk = 0x4U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */ - kCLOCK_RtcClk = 0x5U, /*!< RTC clock. (RTCCLK) */ + kCLOCK_OscClk = 0x4U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */ + kCLOCK_RtcClk = 0x5U, /*!< RTC clock. (RTCCLK) */ - kCLOCK_ArmPllClk = 0x6U, /*!< ARMPLLCLK. */ + kCLOCK_ArmPllClk = 0x6U, /*!< ARMPLLCLK. */ - kCLOCK_Usb1PllClk = 0x7U, /*!< USB1PLLCLK. */ - kCLOCK_Usb1PllPfd0Clk = 0x8U, /*!< USB1PLLPDF0CLK. */ - kCLOCK_Usb1PllPfd1Clk = 0x9U, /*!< USB1PLLPFD1CLK. */ - kCLOCK_Usb1PllPfd2Clk = 0xAU, /*!< USB1PLLPFD2CLK. */ - kCLOCK_Usb1PllPfd3Clk = 0xBU, /*!< USB1PLLPFD3CLK. */ + kCLOCK_Usb1PllClk = 0x7U, /*!< USB1PLLCLK. */ + kCLOCK_Usb1PllPfd0Clk = 0x8U, /*!< USB1PLLPDF0CLK. */ + kCLOCK_Usb1PllPfd1Clk = 0x9U, /*!< USB1PLLPFD1CLK. */ + kCLOCK_Usb1PllPfd2Clk = 0xAU, /*!< USB1PLLPFD2CLK. */ + kCLOCK_Usb1PllPfd3Clk = 0xBU, /*!< USB1PLLPFD3CLK. */ - kCLOCK_Usb2PllClk = 0xCU, /*!< USB2PLLCLK. */ + kCLOCK_Usb2PllClk = 0xCU, /*!< USB2PLLCLK. */ - kCLOCK_SysPllClk = 0xDU, /*!< SYSPLLCLK. */ - kCLOCK_SysPllPfd0Clk = 0xEU, /*!< SYSPLLPDF0CLK. */ - kCLOCK_SysPllPfd1Clk = 0xFU, /*!< SYSPLLPFD1CLK. */ - kCLOCK_SysPllPfd2Clk = 0x10U, /*!< SYSPLLPFD2CLK. */ - kCLOCK_SysPllPfd3Clk = 0x11U, /*!< SYSPLLPFD3CLK. */ + kCLOCK_SysPllClk = 0xDU, /*!< SYSPLLCLK. */ + kCLOCK_SysPllPfd0Clk = 0xEU, /*!< SYSPLLPDF0CLK. */ + kCLOCK_SysPllPfd1Clk = 0xFU, /*!< SYSPLLPFD1CLK. */ + kCLOCK_SysPllPfd2Clk = 0x10U, /*!< SYSPLLPFD2CLK. */ + kCLOCK_SysPllPfd3Clk = 0x11U, /*!< SYSPLLPFD3CLK. */ - kCLOCK_EnetPll0Clk = 0x12U, /*!< Enet PLLCLK ref_enetpll0. */ - kCLOCK_EnetPll1Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll1. */ - kCLOCK_EnetPll2Clk = 0x14U, /*!< Enet PLLCLK ref_enetpll2. */ + kCLOCK_EnetPll0Clk = 0x12U, /*!< Enet PLLCLK ref_enetpll0. */ + kCLOCK_EnetPll1Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll1. */ - kCLOCK_AudioPllClk = 0x15U, /*!< Audio PLLCLK. */ - kCLOCK_VideoPllClk = 0x16U, /*!< Video PLLCLK. */ + kCLOCK_AudioPllClk = 0x14U, /*!< Audio PLLCLK. */ + kCLOCK_VideoPllClk = 0x15U, /*!< Video PLLCLK. */ } clock_name_t; #define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */ @@ -412,156 +432,155 @@ typedef enum _clock_ip_name kCLOCK_IpInvalid = -1, /* CCM CCGR0 */ - kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */ - kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */ - /*!< CCGR0, CG2, Reserved */ - /*!< CCGR0, CG3, Reserved */ - /*!< CCGR0, CG4, Reserved */ - kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */ - kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */ - kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */ - kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */ - kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */ - kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */ - kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */ - kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */ - kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */ - kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */ - kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */ + kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */ + kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */ + kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2 */ + kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */ + kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */ + kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */ + kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */ + kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */ + kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */ + kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */ + kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */ + kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */ + kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */ + kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */ + kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */ + kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */ /* CCM CCGR1 */ - kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */ - kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */ - kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */ - kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */ - kCLOCK_Adc_5hc = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */ - kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */ - kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */ - kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*!< CCGR1, CG7 */ - kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */ - /*!< CCGR1, CG9, Reserved */ - kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */ - kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */ - kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */ - kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */ - kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */ - kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */ + kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */ + kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */ + kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */ + kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */ + kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */ + kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */ + kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */ + kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*!< CCGR1, CG7 */ + kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */ + kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9 */ + kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */ + kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */ + kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */ + kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */ + kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */ + kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */ /* CCM CCGR2 */ - /*!< CCGR2, CG0, Reserved */ - kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, /*!< CCGR2, CG1 */ - kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */ - kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */ - kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */ - kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */ - kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */ - kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*!< CCGR2, CG7 */ - kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*!< CCGR2, CG8 */ - kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*!< CCGR2, CG9 */ - kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10 */ - kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */ - kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */ - kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */ - kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14 */ - kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15 */ + kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */ + kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, /*!< CCGR2, CG1 */ + kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */ + kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */ + kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */ + kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */ + kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */ + kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*!< CCGR2, CG7 */ + kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*!< CCGR2, CG8 */ + kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*!< CCGR2, CG9 */ + kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10 */ + kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */ + kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */ + kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */ + kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14 */ + kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15 */ /* CCM CCGR3 */ - kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*!< CCGR3, CG0 */ - kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */ - kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */ - kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */ - kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */ - kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*!< CCGR3, CG5 */ - kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*!< CCGR3, CG6 */ - kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */ - kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */ - kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */ - kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */ - kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */ - kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */ - kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */ - kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14 */ - kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */ + kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*!< CCGR3, CG0 */ + kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */ + kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */ + kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */ + kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */ + kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*!< CCGR3, CG5 */ + kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*!< CCGR3, CG6 */ + kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */ + kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */ + kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */ + kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */ + kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */ + kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */ + kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */ + kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14 */ + kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */ /* CCM CCGR4 */ - kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */ - kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */ - kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */ - kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */ - kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5 */ - kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */ - kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */ - kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */ - kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */ - kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10 */ - kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11 */ - kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */ - kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */ - kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14 */ - kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15 */ + kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */ + kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */ + kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */ + kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */ + kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5 */ + kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */ + kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */ + kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */ + kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */ + kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10 */ + kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11 */ + kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */ + kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */ + kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14 */ + kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15 */ /* CCM CCGR5 */ - kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */ - kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */ - kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */ - kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */ - kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */ - kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */ - kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */ - kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */ - kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*!< CCGR5, CG8 */ - kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */ - kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */ - kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */ - kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */ - kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */ - kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */ - kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */ + kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */ + kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */ + kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */ + kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */ + kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */ + kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */ + kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */ + kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */ + kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*!< CCGR5, CG8 */ + kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */ + kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */ + kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */ + kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */ + kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */ + kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */ + kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */ /* CCM CCGR6 */ - kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */ - kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */ - kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */ - kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */ - kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */ - kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */ - kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */ - kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */ - kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */ - kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */ - kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */ - kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */ - kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */ - kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */ - kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */ - kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */ + kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */ + kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */ + kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */ + kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */ + kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */ + kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */ + kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */ + kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */ + kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */ + kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */ + kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */ + kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */ + kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */ + kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */ + kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */ + kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */ } clock_ip_name_t; /*! @brief OSC 24M sorce select */ typedef enum _clock_osc { - kCLOCK_RcOsc = 0U, /*!< On chip OSC. */ - kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */ + kCLOCK_RcOsc = 0U, /*!< On chip OSC. */ + kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */ } clock_osc_t; /*! @brief Clock gate value */ typedef enum _clock_gate_value { - kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */ - kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */ - kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */ + kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */ + kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */ + kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */ } clock_gate_value_t; /*! @brief System clock mode */ typedef enum _clock_mode_t { - kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */ - kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */ - kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */ + kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */ + kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */ + kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */ } clock_mode_t; - /*! * @brief MUX control names for clock mux setting. * @@ -572,41 +591,86 @@ typedef enum _clock_mode_t */ typedef enum _clock_mux { - kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR, CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT, CCM_CCSR_PLL3_SW_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */ + kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR, + CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT, + CCM_CCSR_PLL3_SW_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */ - kCLOCK_PeriphMux = CCM_TUPLE(CBCDR, CCM_CBCDR_PERIPH_CLK_SEL_SHIFT, CCM_CBCDR_PERIPH_CLK_SEL_MASK, CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */ - kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR, CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT, CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< semc mux name */ - kCLOCK_SemcMux = CCM_TUPLE(CBCDR, CCM_CBCDR_SEMC_CLK_SEL_SHIFT, CCM_CBCDR_SEMC_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< semc mux name */ - - kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR, CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT, CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */ - kCLOCK_TraceMux = CCM_TUPLE(CBCMR, CCM_CBCMR_TRACE_CLK_SEL_SHIFT, CCM_CBCMR_TRACE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< trace mux name */ - kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR, CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT, CCM_CBCMR_PERIPH_CLK2_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */ - kCLOCK_LpspiMux = CCM_TUPLE(CBCMR, CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, CCM_CBCMR_LPSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi mux name */ + kCLOCK_PeriphMux = CCM_TUPLE(CBCDR, + CCM_CBCDR_PERIPH_CLK_SEL_SHIFT, + CCM_CBCDR_PERIPH_CLK_SEL_MASK, + CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */ + kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR, + CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT, + CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< semc mux name */ + kCLOCK_SemcMux = CCM_TUPLE( + CBCDR, CCM_CBCDR_SEMC_CLK_SEL_SHIFT, CCM_CBCDR_SEMC_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< semc mux name */ - kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT, CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< flexspi mux name */ - kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT, CCM_CSCMR1_USDHC2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */ - kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT, CCM_CSCMR1_USDHC1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */ - kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, CCM_CSCMR1_SAI3_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 mux name */ - kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, CCM_CSCMR1_SAI2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 mux name */ - kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, CCM_CSCMR1_SAI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 mux name */ - kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT, CCM_CSCMR1_PERCLK_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< perclk mux name */ + kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */ + kCLOCK_TraceMux = CCM_TUPLE( + CBCMR, CCM_CBCMR_TRACE_CLK_SEL_SHIFT, CCM_CBCMR_TRACE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< trace mux name */ + kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR, + CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT, + CCM_CBCMR_PERIPH_CLK2_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */ + kCLOCK_LpspiMux = CCM_TUPLE( + CBCMR, CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, CCM_CBCMR_LPSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi mux name */ - kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT, CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */ - kCLOCK_CanMux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_CAN_CLK_SEL_SHIFT, CCM_CSCMR2_CAN_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< can mux name */ + kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1, + CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT, + CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexspi mux name */ + kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1, + CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT, + CCM_CSCMR1_USDHC2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */ + kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1, + CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT, + CCM_CSCMR1_USDHC1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */ + kCLOCK_Sai3Mux = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, CCM_CSCMR1_SAI3_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 mux name */ + kCLOCK_Sai2Mux = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, CCM_CSCMR1_SAI2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 mux name */ + kCLOCK_Sai1Mux = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, CCM_CSCMR1_SAI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 mux name */ + kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1, + CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT, + CCM_CSCMR1_PERCLK_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< perclk mux name */ - kCLOCK_UartMux = CCM_TUPLE(CSCDR1, CCM_CSCDR1_UART_CLK_SEL_SHIFT, CCM_CSCDR1_UART_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< uart mux name */ - - kCLOCK_SpdifMux = CCM_TUPLE(CDCDR, CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, CCM_CDCDR_SPDIF0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< spdif mux name */ - kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR, CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT, CCM_CDCDR_FLEXIO1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */ + kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2, + CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT, + CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */ + kCLOCK_CanMux = CCM_TUPLE( + CSCMR2, CCM_CSCMR2_CAN_CLK_SEL_SHIFT, CCM_CSCMR2_CAN_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< can mux name */ - kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT, CCM_CSCDR2_LPI2C_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */ - kCLOCK_Lcdif1PreMux = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT, CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif1 pre mux name */ - kCLOCK_Lcdif1Mux = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT, CCM_CSCDR2_LCDIF_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif1 mux name */ + kCLOCK_UartMux = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_UART_CLK_SEL_SHIFT, CCM_CSCDR1_UART_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< uart mux name */ - kCLOCK_CsiMux = CCM_TUPLE(CSCDR3, CCM_CSCDR3_CSI_CLK_SEL_SHIFT, CCM_CSCDR3_CSI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< csi mux name */ + kCLOCK_SpdifMux = CCM_TUPLE( + CDCDR, CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, CCM_CDCDR_SPDIF0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< spdif mux name */ + kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR, + CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */ + + kCLOCK_Lpi2cMux = CCM_TUPLE( + CSCDR2, CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT, CCM_CSCDR2_LPI2C_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */ + kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lcdif pre mux name */ + + kCLOCK_CsiMux = CCM_TUPLE( + CSCDR3, CCM_CSCDR3_CSI_CLK_SEL_SHIFT, CCM_CSCDR3_CSI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< csi mux name */ } clock_mux_t; - /*! * @brief DIV control names for clock div setting. * @@ -617,146 +681,212 @@ typedef enum _clock_mux */ typedef enum _clock_div { - kCLOCK_ArmDiv = CCM_TUPLE(CACRR, CCM_CACRR_ARM_PODF_SHIFT, CCM_CACRR_ARM_PODF_MASK, CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */ + kCLOCK_ArmDiv = CCM_TUPLE( + CACRR, CCM_CACRR_ARM_PODF_SHIFT, CCM_CACRR_ARM_PODF_MASK, CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */ - kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR, CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT, CCM_CBCDR_PERIPH_CLK2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */ - kCLOCK_SemcDiv = CCM_TUPLE(CBCDR, CCM_CBCDR_SEMC_PODF_SHIFT, CCM_CBCDR_SEMC_PODF_MASK, CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */ - kCLOCK_AhbDiv = CCM_TUPLE(CBCDR, CCM_CBCDR_AHB_PODF_SHIFT, CCM_CBCDR_AHB_PODF_MASK, CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */ - kCLOCK_IpgDiv = CCM_TUPLE(CBCDR, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */ + kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR, + CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT, + CCM_CBCDR_PERIPH_CLK2_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */ + kCLOCK_SemcDiv = CCM_TUPLE(CBCDR, + CCM_CBCDR_SEMC_PODF_SHIFT, + CCM_CBCDR_SEMC_PODF_MASK, + CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */ + kCLOCK_AhbDiv = CCM_TUPLE( + CBCDR, CCM_CBCDR_AHB_PODF_SHIFT, CCM_CBCDR_AHB_PODF_MASK, CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */ + kCLOCK_IpgDiv = + CCM_TUPLE(CBCDR, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */ - kCLOCK_LpspiDiv = CCM_TUPLE(CBCMR, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */ - kCLOCK_Lcdif1Div = CCM_TUPLE(CBCMR, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif1 div name */ + kCLOCK_LpspiDiv = CCM_TUPLE( + CBCMR, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */ + kCLOCK_LcdifDiv = CCM_TUPLE( + CBCMR, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif div name */ - kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1, CCM_CSCMR1_FLEXSPI_PODF_SHIFT, CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< flexspi div name */ - kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1, CCM_CSCMR1_PERCLK_PODF_SHIFT, CCM_CSCMR1_PERCLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< perclk div name */ + kCLOCK_FlexspiDiv = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_FLEXSPI_PODF_SHIFT, CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< flexspi div name */ + kCLOCK_PerclkDiv = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_PERCLK_PODF_SHIFT, CCM_CSCMR1_PERCLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< perclk div name */ - kCLOCK_CanDiv = CCM_TUPLE(CSCMR2, CCM_CSCMR2_CAN_CLK_PODF_SHIFT, CCM_CSCMR2_CAN_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< can div name */ + kCLOCK_CanDiv = CCM_TUPLE( + CSCMR2, CCM_CSCMR2_CAN_CLK_PODF_SHIFT, CCM_CSCMR2_CAN_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< can div name */ - kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1, CCM_CSCDR1_TRACE_PODF_SHIFT, CCM_CSCDR1_TRACE_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< trace div name */ - kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1, CCM_CSCDR1_USDHC2_PODF_SHIFT, CCM_CSCDR1_USDHC2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */ - kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1, CCM_CSCDR1_USDHC1_PODF_SHIFT, CCM_CSCDR1_USDHC1_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */ - kCLOCK_UartDiv = CCM_TUPLE(CSCDR1, CCM_CSCDR1_UART_CLK_PODF_SHIFT, CCM_CSCDR1_UART_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< uart div name */ + kCLOCK_TraceDiv = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_TRACE_PODF_SHIFT, CCM_CSCDR1_TRACE_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< trace div name */ + kCLOCK_Usdhc2Div = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_USDHC2_PODF_SHIFT, CCM_CSCDR1_USDHC2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */ + kCLOCK_Usdhc1Div = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_USDHC1_PODF_SHIFT, CCM_CSCDR1_USDHC1_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */ + kCLOCK_UartDiv = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_UART_CLK_PODF_SHIFT, CCM_CSCDR1_UART_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< uart div name */ - kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR, CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT, CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */ - kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR, CCM_CS1CDR_SAI3_CLK_PRED_SHIFT, CCM_CS1CDR_SAI3_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ - kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR, CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, CCM_CS1CDR_SAI3_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 div name */ - kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR, CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT, CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ - kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR, CCM_CS1CDR_SAI1_CLK_PRED_SHIFT, CCM_CS1CDR_SAI1_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */ - kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR, CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, CCM_CS1CDR_SAI1_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 div name */ + kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR, + CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT, + CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */ + kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR, + CCM_CS1CDR_SAI3_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI3_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai3Div = CCM_TUPLE( + CS1CDR, CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, CCM_CS1CDR_SAI3_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 div name */ + kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR, + CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT, + CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR, + CCM_CS1CDR_SAI1_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */ + kCLOCK_Sai1Div = CCM_TUPLE( + CS1CDR, CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, CCM_CS1CDR_SAI1_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 div name */ - kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR, CCM_CS2CDR_SAI2_CLK_PRED_SHIFT, CCM_CS2CDR_SAI2_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */ - kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR, CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, CCM_CS2CDR_SAI2_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 div name */ + kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR, + CCM_CS2CDR_SAI2_CLK_PRED_SHIFT, + CCM_CS2CDR_SAI2_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */ + kCLOCK_Sai2Div = CCM_TUPLE( + CS2CDR, CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, CCM_CS2CDR_SAI2_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 div name */ - kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR, CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT, CCM_CDCDR_SPDIF0_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< spdif pre div name */ - kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR, CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT, CCM_CDCDR_SPDIF0_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< spdif div name */ - kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR, CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT, CCM_CDCDR_FLEXIO1_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */ - kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR, CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT, CCM_CDCDR_FLEXIO1_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< flexio1 div name */ + kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR, + CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif pre div name */ + kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR, + CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif div name */ + kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR, + CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */ + kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR, + CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 div name */ - kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT, CCM_CSCDR2_LPI2C_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpi2c div name */ - kCLOCK_Lcdif1PreDiv = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LCDIF_PRED_SHIFT, CCM_CSCDR2_LCDIF_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif1 pre div name */ + kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2, + CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT, + CCM_CSCDR2_LPI2C_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< lpi2c div name */ + kCLOCK_LcdifPreDiv = CCM_TUPLE( + CSCDR2, CCM_CSCDR2_LCDIF_PRED_SHIFT, CCM_CSCDR2_LCDIF_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */ - kCLOCK_CsiDiv = CCM_TUPLE(CSCDR3, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */ + kCLOCK_CsiDiv = + CCM_TUPLE(CSCDR3, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */ } clock_div_t; - -/*! @brief PLL configuration for ARM */ -typedef struct _clock_arm_pll_config -{ - uint32_t loopDivider; /*!< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */ -} clock_arm_pll_config_t; - -/*! @brief PLL configuration for USB */ -typedef struct _clock_usb_pll_config -{ - uint8_t loopDivider; /*!< PLL loop divider. - 0 - Fout=Fref*20; - 1 - Fout=Fref*22 */ -} clock_usb_pll_config_t; - - -/*! @brief PLL configuration for System */ -typedef struct _clock_sys_pll_config -{ - uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M). - 0 - Fout=Fref*20; - 1 - Fout=Fref*22 */ - uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ - uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ -} clock_sys_pll_config_t; - -/*! @brief PLL configuration for AUDIO and VIDEO */ -typedef struct _clock_audio_pll_config -{ - uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ - uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ - uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ - uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ -} clock_audio_pll_config_t; - -/*! @brief PLL configuration for AUDIO and VIDEO */ -typedef struct _clock_video_pll_config -{ - uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ - uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ - uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ - uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ -} clock_video_pll_config_t; - -/*! @brief PLL configuration for ENET */ -typedef struct _clock_enet_pll_config -{ - bool enableClkOutput0; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */ - bool enableClkOutput1; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */ - bool enableClkOutput2; /*!< Power on and enable PLL clock output for ENET2 (ref_enetpll2). */ - uint8_t loopDivider0; /*!< Controls the frequency of the ENET0 reference clock. - b00 25MHz - b01 50MHz - b10 100MHz (not 50% duty cycle) - b11 125MHz */ - uint8_t loopDivider1; /*!< Controls the frequency of the ENET1 reference clock. - b00 25MHz - b01 50MHz - b10 100MHz (not 50% duty cycle) - b11 125MHz */ -} clock_enet_pll_config_t; - -/*! @brief PLL name */ -typedef enum _clock_pll -{ - kCLOCK_PllArm = 0U, /*!< PLL ARM */ - kCLOCK_PllSys = 1U, /*!< PLL SYS */ - kCLOCK_PllUsb1 = 2U, /*!< PLL USB1 */ - kCLOCK_PllAudio = 3U, /*!< PLL Audio */ - kCLOCK_PllVideo = 4U, /*!< PLL Video */ - kCLOCK_PllEnet0 = 5U, /*!< PLL Enet0 */ - kCLOCK_PllEnet1 = 6U, /*!< PLL Enet1 */ - kCLOCK_PllEnet2 = 7U, /*!< PLL Enet2 */ - kCLOCK_PllUsb2 = 8U, /*!< PLL USB2 */ -} clock_pll_t; - -/*! @brief PLL PFD name */ -typedef enum _clock_pfd -{ - kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */ - kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */ - kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */ - kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */ -} clock_pfd_t; - /*! @brief USB clock source definition. */ typedef enum _clock_usb_src { - kCLOCK_Usb480M = 0, /*!< Use 480M. */ - kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not - care the clock source. */ + kCLOCK_Usb480M = 0, /*!< Use 480M. */ + kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not + care the clock source. */ } clock_usb_src_t; /*! @brief Source of the USB HS PHY. */ typedef enum _clock_usb_phy_src { - kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ + kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ } clock_usb_phy_src_t; +/*!@brief PLL clock source, bypass cloco source also */ +enum _clock_pll_clk_src +{ + kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */ + kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */ +}; + +/*! @brief PLL configuration for ARM */ +typedef struct _clock_arm_pll_config +{ + uint32_t loopDivider; /*!< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ +} clock_arm_pll_config_t; + +/*! @brief PLL configuration for USB */ +typedef struct _clock_usb_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_usb_pll_config_t; + +/*! @brief PLL configuration for System */ +typedef struct _clock_sys_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M). + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_sys_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_audio_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ +} clock_audio_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_video_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_video_pll_config_t; + +/*! @brief PLL configuration for ENET */ +typedef struct _clock_enet_pll_config +{ + bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */ + + bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */ + uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock. + b00 25MHz + b01 50MHz + b10 100MHz (not 50% duty cycle) + b11 125MHz */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_enet_pll_config_t; + +/*! @brief PLL name */ +typedef enum _clock_pll +{ + kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< PLL ARM */ + kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */ + kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */ + kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */ + kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< PLL Video */ + + kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*!< PLL Enet0 */ + + kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< PLL Enet1 */ + + kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*!< PLL USB2 */ + +} clock_pll_t; + +/*! @brief PLL PFD name */ +typedef enum _clock_pfd +{ + kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */ + kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */ + kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */ + kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */ +} clock_pfd_t; + /******************************************************************************* * API ******************************************************************************/ @@ -814,7 +944,7 @@ static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value) busyShift = CCM_TUPLE_BUSY_SHIFT(divider); CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) | - (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); + (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); assert(busyShift <= CCM_NO_BUSY_WAIT); @@ -835,10 +965,7 @@ static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value) */ static inline uint32_t CLOCK_GetDiv(clock_div_t divider) { - uint32_t value; - - value = (CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider); - return value; + return ((CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider)); } /*! @@ -853,7 +980,7 @@ static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t va uint32_t shift = ((uint32_t)name) & 0x1FU; volatile uint32_t *reg; - assert (index <= 6); + assert(index <= 6); reg = ((volatile uint32_t *)&CCM->CCGR0) + index; *reg = ((*reg) & ~(3U << shift)) | (((uint32_t)value) << shift); @@ -888,7 +1015,22 @@ static inline void CLOCK_SetMode(clock_mode_t mode) { CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode); } - + +/*! + * @brief Gets the OSC clock frequency. + * + * This function will return the external XTAL OSC frequency if it is selected as the source of OSC, + * otherwise internal 24MHz RC OSC frequency will be returned. + * + * @param osc OSC type to get frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetOscFreq(void) +{ + return (XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) ? 24000000UL : g_xtalFreq; +} + /*! * @brief Gets the clock frequency for a specific clock name. * @@ -950,21 +1092,6 @@ void CLOCK_DeinitExternalClk(void); */ void CLOCK_SwitchOsc(clock_osc_t osc); -/*! - * @brief Gets the OSC clock frequency. - * - * This function will return the external XTAL OSC frequency if it is selected as the source of OSC, - * otherwise internal 24MHz RC OSC frequency will be returned. - * - * @param osc OSC type to get frequency. - * - * @return Clock frequency; If the clock is invalid, returns 0. - */ -static inline uint32_t CLOCK_GetOscFreq(void) -{ - return (XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) ? 24000000UL : g_xtalFreq; -} - /*! * @brief Gets the RTC clock frequency. * @@ -995,7 +1122,6 @@ static inline void CLOCK_SetRtcXtalFreq(uint32_t freq) g_rtcXtalFreq = freq; } - /*! * @brief Initialize the RC oscillator 24MHz clock. */ @@ -1007,10 +1133,122 @@ void CLOCK_InitRcOsc24M(void); void CLOCK_DeinitRcOsc24M(void); /* @} */ + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void); + +/* @} */ + /*! * @name PLL/PFD operations * @{ */ +/*! + * @brief PLL bypass setting + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param bypass Bypass the PLL. + * - true: Bypass the PLL. + * - false:Not bypass the PLL. + */ +static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass) +{ + if (bypass) + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT; + } + else + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT; + } +} + +/*! + * @brief Check if PLL is bypassed + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is bypassed. + * - false: The PLL is not bypassed. + */ +static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_PLL_BYPASS_SHIFT)); +} + +/*! + * @brief Check if PLL is enabled + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is enabled. + * - false: The PLL is not enabled. + */ +static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_TUPLE_SHIFT(pll))); +} + +/*! + * @brief PLL bypass clock source setting. + * Note: change the bypass clock source also change the pll reference clock source. + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param src Bypass clock source, reference _clock_pll_bypass_clk_src. + */ +static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src) +{ + CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src; +} + +/*! + * @brief Get PLL bypass clock value, it is PLL reference clock actually. + * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 + * will be returned. + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @retval bypass reference clock frequency value. + */ +static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >> + CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == kCLOCK_PllClkSrc24M) ? + CLOCK_GetOscFreq() : + CLKPN_FREQ; +} /*! * @brief Initialize the ARM PLL. @@ -1095,7 +1333,6 @@ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config); * @brief De-initialize the Video PLL. */ void CLOCK_DeinitVideoPll(void); - /*! * @brief Initialize the ENET PLL. * @@ -1184,20 +1421,6 @@ uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd); */ uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd); -/*! @brief Enable USB HS clock. - * - * This function only enables the access to USB HS prepheral, upper layer - * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY - * clock to use USB HS. - * - * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. - * @param freq USB HS does not care about the clock source, so this parameter is ignored. - * @retval true The clock is set successfully. - * @retval false The clock source is invalid to get proper USB HS clock. - */ -bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); - - /*! @brief Enable USB HS PHY PLL clock. * * This function enables the internal 480MHz USB PHY PLL clock. @@ -1215,20 +1438,6 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); */ void CLOCK_DisableUsbhs0PhyPllClock(void); -/*! @brief Enable USB HS clock. - * - * This function only enables the access to USB HS prepheral, upper layer - * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY - * clock to use USB HS. - * - * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. - * @param freq USB HS does not care about the clock source, so this parameter is ignored. - * @retval true The clock is set successfully. - * @retval false The clock source is invalid to get proper USB HS clock. - */ -bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq); - - /*! @brief Enable USB HS PHY PLL clock. * * This function enables the internal 480MHz USB PHY PLL clock. @@ -1248,7 +1457,6 @@ void CLOCK_DisableUsbhs1PhyPllClock(void); /* @} */ - #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.c index 6a5f15a75b..98039cd6f9 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,6 +34,12 @@ #include "fsl_cmp.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cmp" +#endif + + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.h index 5d16bf08de..e228413f0c 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.c index 86f1625343..903faf52b6 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.c @@ -1,10 +1,13 @@ /* +* The Clear BSD License * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016 NXP * All rights reserved. * +* * Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: +* are permitted (subject to the limitations in the disclaimer below) provided +* that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -17,6 +20,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -38,6 +42,12 @@ typedef struct _mem_align_control_block uint16_t offset; /*!< offset from aligned adress to real address */ } mem_align_cb_t; +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + + #ifndef __GIC_PRIO_BITS #if defined(ENABLE_RAM_VECTOR_TABLE) uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) @@ -99,30 +109,50 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) void EnableDeepSleepIRQ(IRQn_Type interrupt) { - uint32_t index = 0; uint32_t intNumber = (uint32_t)interrupt; - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - SYSCON->STARTERSET[index] = 1u << intNumber; +#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1)) + { + SYSCON->STARTERP1 = 1u << intNumber; + } +#else + { + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1u << intNumber; + } +#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */ EnableIRQ(interrupt); /* also enable interrupt at NVIC */ } void DisableDeepSleepIRQ(IRQn_Type interrupt) { - uint32_t index = 0; uint32_t intNumber = (uint32_t)interrupt; - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } DisableIRQ(interrupt); /* also disable interrupt at NVIC */ - SYSCON->STARTERCLR[index] = 1u << intNumber; +#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1)) + { + SYSCON->STARTERP1 &= ~(1u << intNumber); + } +#else + { + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1u << intNumber; + } +#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */ } #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.h index cd563c2e70..a53dbc2713 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -65,14 +69,16 @@ /*@}*/ /* Debug console type definition. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console base on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console base on SWO. */ /*! @brief Status group numbers. */ enum _status_groups @@ -140,6 +146,7 @@ enum _status_groups kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ @@ -175,6 +182,13 @@ typedef int32_t status_t; #include "fsl_reset.h" #endif +/* + * Macro guard for whether to use default weak IRQ implementation in drivers + */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + /*! @name Min/max macros */ /* @{ */ #if !defined(MIN) @@ -273,13 +287,6 @@ _Pragma("diag_suppress=Pm120") ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) /* @} */ -/*! Function to allocate/free L1 cache aligned memory using the malloc/free. */ -void *SDK_Malloc(size_t size, size_t alignbytes); - -void SDK_Free(void *ptr); - -/* @} */ - /*! @name Non-cacheable region definition macros */ /* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, @@ -339,6 +346,37 @@ void SDK_Free(void *ptr); #endif /* @} */ +/*! @name Time sensitive region */ +/* @{ */ +#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" +#elif(defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +#else +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#else +#error Toolchain not supported. +#endif +#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ +/* @} */ + /******************************************************************************* * API ******************************************************************************/ @@ -511,6 +549,24 @@ void SDK_Free(void *ptr); void DisableDeepSleepIRQ(IRQn_Type interrupt); #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + /*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ + void *SDK_Malloc(size_t size, size_t alignbytes); + + /*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ + void SDK_Free(void *ptr); + #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.c index be90aa1058..df993d29dc 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2017, NXP Semiconductors, Inc. * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -34,6 +38,12 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.csi" +#endif + + /* Two frame buffer loaded to CSI register at most. */ #define CSI_MAX_ACTIVE_FRAME_NUM 2 diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.h index 75e17233e9..96230c8318 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2017, NXP Semiconductors, Inc. * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.c index 94893cc9e0..5e0e3a97b4 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2017, NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,6 +34,12 @@ #include "fsl_dcdc.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dcdc_1" +#endif + + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -330,13 +340,12 @@ void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regula void DCDC_BootIntoDCM(DCDC_Type *base) { base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK); - base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U) | + base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x4U) | DCDC_REG2_DCM_SET_CTRL_MASK; } void DCDC_BootIntoCCM(DCDC_Type *base) { base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK; - base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U) | - DCDC_REG2_DCM_SET_CTRL_MASK; + base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U); } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.h index 305d835946..647d3a8589 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2017, NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.c index 8512a301ec..fdc13fa0fc 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright 2017 NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -34,6 +38,12 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dcp" +#endif + + /*! Compile time sizeof() check */ #define BUILD_ASSURE(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused)) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.h index 5b94389581..15694703a6 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright 2017 NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.c index 39ce9cfbea..155531de5a 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -34,6 +38,12 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dmamux" +#endif + + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.h index 071348b2c2..17f32ee2e8 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.c index 65f37619fe..96b0f80022 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -34,6 +38,12 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.edma" +#endif + + #define EDMA_TRANSFER_ENABLED_MASK 0x80U /******************************************************************************* @@ -711,8 +721,10 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t */ if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd]) { + /* Clear the DREQ bits for the dynamic scatter gather */ + tcdRegs->CSR |= DMA_CSR_DREQ_MASK; /* Enable scatter/gather also in the TCD registers. */ - csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + csr = tcdRegs->CSR | DMA_CSR_ESG_MASK; /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ tcdRegs->CSR = csr; /* @@ -727,6 +739,7 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t */ if (tcdRegs->CSR & DMA_CSR_ESG_MASK) { + tcdRegs->CSR &= ~DMA_CSR_DREQ_MASK; return kStatus_Success; } /* diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.h index e356476203..03bc8db16d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -52,7 +56,7 @@ #define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U))) /*! @brief Get the pointer of DCHPRIn */ -#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&(base->DCHPRI3))[DMA_DCHPRI_INDEX(channel)] +#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&((base)->DCHPRI3))[DMA_DCHPRI_INDEX(channel)] /*! @brief eDMA transfer configuration */ typedef enum _edma_transfer_size @@ -60,6 +64,7 @@ typedef enum _edma_transfer_size kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */ kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */ kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */ + kEDMA_TransferSize8Bytes = 0x3U, /*!< Source/Destination data transfer size is 8 bytes every time */ kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */ kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */ } edma_transfer_size_t; @@ -242,7 +247,24 @@ typedef struct _edma_tcd /*! @brief Callback for eDMA */ struct _edma_handle; -/*! @brief Define callback function for eDMA. */ +/*! @brief Define callback function for eDMA. + * + * This callback function is called in the EDMA interrupt handle. + * In normal mode, run into callback function means the transfer users need is done. + * In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not + * all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber. + * + * @param handle EDMA handle pointer, users shall not touch the values inside. + * @param userData The callback user paramter pointer. Users can use this paramter to involve things users need to + * change in EDMA callback function. + * @param transferDone If the current loaded transfer done. In normal mode it means if all transfer done. In scatter + * gather mode, this paramter shows is the current transfer block in EDMA regsiter is done. As the + * load of core is different, it will be different if the new tcd loaded into EDMA registers while + * this callback called. If true, it always means new tcd still not loaded into registers, while + * false means new tcd already loaded into registers. + * @param tcds How many tcds are done from the last callback. This parameter only used in scatter gather mode. It + * tells user how many tcds are finished between the last callback and this. + */ typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds); /*! @brief eDMA transfer handle structure */ @@ -702,7 +724,7 @@ static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel) * @brief Gets the remaining major loop count from the eDMA current channel TCD. * * This function checks the TCD (Task Control Descriptor) status for a specified - * eDMA channel and returns the the number of major loop count that has not finished. + * eDMA channel and returns the number of major loop count that has not finished. * * @param base eDMA peripheral base address. * @param channel eDMA channel number. @@ -774,7 +796,10 @@ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel); /*! * @brief Installs the TCDs memory pool into the eDMA handle. * - * This function is called after the EDMA_CreateHandle to use scatter/gather feature. + * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used + * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block + * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. + * Users need to preapre tcd memory and also configure tcds using interface EDMA_SubmitTransfer. * * @param handle eDMA handle pointer. * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. @@ -786,7 +811,7 @@ void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t * @brief Installs a callback function for the eDMA transfer. * * This callback is called in the eDMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. + * the current major loop transfer completes. This function will be called every time one tcd finished transfer. * * @param handle eDMA handle pointer. * @param callback eDMA callback function pointer. @@ -824,8 +849,8 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config, * @brief Submits the eDMA transfer request. * * This function submits the eDMA transfer request according to the transfer configuration structure. - * If submitting the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. * * @param handle eDMA handle pointer. * @param config Pointer to eDMA transfer configuration structure. diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.c index de6221a943..51aabe3b88 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2017, NXP Semiconductors, Inc. * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,6 +34,12 @@ #include "fsl_elcdif.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.elcdif" +#endif + + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -286,10 +296,6 @@ status_t ELCDIF_UpdateLut( for (i = 0; i < count; i++) { *regLutData = lutData[i]; - - for (volatile uint32_t j = 0; j < 0x80; j++) - { - } } return kStatus_Success; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.h index e420b84d6a..2183c84f7d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2017, NXP Semiconductors, Inc. * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.c index c513d5be5a..76db836d06 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -33,6 +37,12 @@ /******************************************************************************* * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.enc" +#endif + #define ENC_CTRL_W1C_FLAGS (ENC_CTRL_HIRQ_MASK | ENC_CTRL_XIRQ_MASK | ENC_CTRL_DIRQ_MASK | ENC_CTRL_CMPIRQ_MASK) #define ENC_CTRL2_W1C_FLAGS (ENC_CTRL2_SABIRQ_MASK | ENC_CTRL2_ROIRQ_MASK | ENC_CTRL2_RUIRQ_MASK) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.h index 740fc639bc..64c4f402da 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -303,6 +307,22 @@ void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base); */ void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config); +/*! + * @brief Enable watchdog for ENC module. + * + * @param base ENC peripheral base address + * @param enable Enables or disables the watchdog + */ +void ENC_EnableWatchdog(ENC_Type *base, bool enable); + +/*! + * @brief Set initial position value for ENC module. + * + * @param base ENC peripheral base address + * @param value Positive initial value + */ +void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value); + /* @} */ /*! diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.c index 2e7e002425..d44b73eb94 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -36,6 +40,12 @@ /******************************************************************************* * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.enet" +#endif + /*! @brief IPv4 PTP message IP version offset. */ #define ENET_PTP1588_IPVERSION_OFFSET 0x0EU /*! @brief IPv4 PTP message UDP protocol offset. */ @@ -99,7 +109,9 @@ /*! @brief NanoSecond in one second. */ #define ENET_NANOSECOND_ONE_SECOND 1000000000U /*! @brief Define a common clock cycle delays used for time stamp capture. */ -#define ENET_1588TIME_DELAY_COUNT 38U +#ifndef ENET_1588TIME_DELAY_COUNT +#define ENET_1588TIME_DELAY_COUNT 10U +#endif /*! @brief Defines the macro for converting constants from host byte order to network byte order. */ #define ENET_HTONS(n) __REV16(n) @@ -793,6 +805,12 @@ static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, const enet_config #else rxBuffer = buffCfg->rxBufferAlign; #endif + +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Invalidate rx buffers before DMA transfer data into them. */ + DCACHE_InvalidateByRange((uint32_t)rxBuffer, (buffCfg->rxBdNumber * rxBuffSizeAlign)); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + for (count = 0; count < buffCfg->rxBdNumber; count++) { /* Set data buffer and the length. */ @@ -1172,24 +1190,18 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u else { /* A frame on one buffer or several receive buffers are both considered. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL /* Add the cache invalidate maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ -/* A frame on one buffer or several receive buffers are both considered. */ +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE enet_ptp_time_data_t ptpTimestamp; - bool isPtpEventMessage = false; -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + bool isPtpEventMessage = false; /* Parse the PTP message according to the header message. */ isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false); #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ @@ -1205,11 +1217,6 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u { /* Copy the frame to user's buffer without FCS. */ len = curBuffDescrip->length - offset; -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ memcpy(data + offset, (void *)address, len); #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE /* Store the PTP 1588 timestamp for received PTP event frame. */ @@ -1240,11 +1247,7 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u { break; } -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[0]); offset += handle->rxBuffSizeAlign[0]; @@ -1254,13 +1257,13 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u /* Get the current buffer descriptor. */ curBuffDescrip = handle->rxBdCurrent[0]; -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL /* Add the cache invalidate maintain. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]); #endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ } @@ -1346,6 +1349,9 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d address = (uint32_t)curBuffDescrip->buffer; #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ memcpy((void *)address, data, length); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + DCACHE_CleanByRange(address, length); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ /* Set data length. */ curBuffDescrip->length = length; #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE @@ -1371,15 +1377,6 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d { handle->txBdCurrent[0]++; } -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - DCACHE_CleanByRange(address, length); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ /* Active the transmit buffer descriptor. */ ENET_ActiveSend(base, 0); @@ -1413,15 +1410,19 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d } /* update the size left to be transmit. */ sizeleft = length - len; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ if (sizeleft > handle->txBuffSizeAlign[0]) { /* Data copy. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ /* Data length update. */ curBuffDescrip->length = handle->txBuffSizeAlign[0]; len += handle->txBuffSizeAlign[0]; @@ -1433,24 +1434,15 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d } else { -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + memcpy((void *)address, data + len, sizeleft); - curBuffDescrip->length = sizeleft; - /* Set Last buffer wrap flag. */ - curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL /* Add the cache clean maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + DCACHE_CleanByRange(address, sizeleft); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + curBuffDescrip->length = sizeleft; + /* Set Last buffer wrap flag. */ + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; /* Active the transmit buffer descriptor. */ ENET_ActiveSend(base, 0); @@ -1637,25 +1629,19 @@ status_t ENET_ReadFrameMultiRing( else { /* A frame on one buffer or several receive buffers are both considered. */ -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache invalidate maintain. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache invalidate maintain. */ DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[ringId]); #endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE enet_ptp_time_data_t ptpTimestamp; bool isPtpEventMessage = false; - /* Parse the PTP message according to the header message. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false); #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ @@ -1670,11 +1656,6 @@ status_t ENET_ReadFrameMultiRing( { /* Copy the frame to user's buffer without FCS. */ len = curBuffDescrip->length - offset; -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ memcpy(data + offset, (void *)address, len); #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE /* Store the PTP 1588 timestamp for received PTP event frame. */ @@ -1705,11 +1686,6 @@ status_t ENET_ReadFrameMultiRing( { break; } -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[ringId]); offset += handle->rxBuffSizeAlign[ringId]; @@ -1721,13 +1697,13 @@ status_t ENET_ReadFrameMultiRing( /* Get the current buffer descriptor. */ curBuffDescrip = handle->rxBdCurrent[ringId]; -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache invalidate maintain. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache invalidate maintain. */ DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[ringId]); #endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ } @@ -1777,6 +1753,11 @@ status_t ENET_SendFrameMultiRing( #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ memcpy((void *)address, data, length); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, length); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Set data length. */ curBuffDescrip->length = length; #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE @@ -1802,15 +1783,7 @@ status_t ENET_SendFrameMultiRing( { handle->txBdCurrent[ringId]++; } -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - DCACHE_CleanByRange(address, length); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Active the transmit buffer descriptor. */ ENET_ActiveSend(base, ringId); @@ -1844,53 +1817,41 @@ status_t ENET_SendFrameMultiRing( } /* update the size left to be transmit. */ sizeleft = length - len; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ if (sizeleft > handle->txBuffSizeAlign[ringId]) { /* Data copy. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ memcpy((void*)address, data + len, handle->txBuffSizeAlign[ringId]); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, handle->txBuffSizeAlign[ringId]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ /* Data length update. */ curBuffDescrip->length = handle->txBuffSizeAlign[ringId]; len += handle->txBuffSizeAlign[ringId]; /* Sets the control flag. */ curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK; curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - DCACHE_CleanByRange(address, handle->txBuffSizeAlign[ringId]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Active the transmit buffer descriptor*/ ENET_ActiveSend(base, ringId); } else { -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + memcpy((void *)address, data + len, sizeleft); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, sizeleft); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ curBuffDescrip->length = sizeleft; /* Set Last buffer wrap flag. */ curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - DCACHE_CleanByRange(address, sizeleft); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Active the transmit buffer descriptor. */ ENET_ActiveSend(base, ringId); @@ -1899,9 +1860,6 @@ status_t ENET_SendFrameMultiRing( /* Get the current buffer descriptor address. */ curBuffDescrip = handle->txBdCurrent[ringId]; -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL -/* Add the cache invalidate maintain. */ -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)); return kStatus_ENET_TxFrameBusy; @@ -2154,7 +2112,7 @@ static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *pt switch (ENET_HTONS(ptpType)) { /* Ethernet layer 2. */ case ENET_ETHERNETL2: - if (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) <= kENET_PtpEventMsgType) + if ((*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) & 0x0F) <= kENET_PtpEventMsgType) { isPtpMsg = true; if (!isFastEnabled) @@ -2487,6 +2445,7 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimeData, false); if (isPtpEventMessage) { + /* Only store tx timestamp for ptp event message. */ do { /* Increase current buffer descriptor to the next one. */ @@ -2522,6 +2481,9 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui ptpTimeData.timeStamp.second = handle->msTimerSecond - 1; } + /* Save transmit time stamp nanosecond. */ + ptpTimeData.timeStamp.nanosecond = curBuffDescrip->timestamp; + /* Enable the interrupt. */ EnableGlobalIRQ(primask); @@ -2532,7 +2494,6 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui /* Get the current transmit buffer descriptor. */ curBuffDescrip = handle->txBdDirtyTime[ringId]; - /* Get the control status data, If the buffer descriptor has not been processed break out. */ if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) { @@ -2541,6 +2502,18 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui } while (handle->txBdDirtyTime[ringId] != handle->txBdCurrent[ringId]); return kStatus_ENET_TxFrameFail; } + else + { + /* Only increase current buffer descriptor to the next one. */ + if (handle->txBdDirtyTime[ringId]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdDirtyTime[ringId] = handle->txBdBase[ringId]; + } + else + { + handle->txBdDirtyTime[ringId]++; + } + } return kStatus_Success; } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.h index d652e2bafb..3538bca2f2 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -46,7 +50,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief Defines the driver version. */ -#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1. */ +#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) /*!< Version 2.2.3. */ /*@}*/ /*! @name ENET DESCRIPTOR QUEUE */ @@ -194,7 +198,7 @@ typedef enum _enet_mii_mode * * Notice: "kENET_MiiSpeed1000M" only supported when mii mode is "kENET_RgmiiMode". */ -typedef enum _enet_mii_speed +typedef enum _enet_mii_speed { kENET_MiiSpeed10M = 0U, /*!< Speed 10 Mbps. */ kENET_MiiSpeed100M = 1U, /*!< Speed 100 Mbps. */ @@ -204,21 +208,21 @@ typedef enum _enet_mii_speed } enet_mii_speed_t; /*! @brief Defines the half or full duplex for the MII data interface. */ -typedef enum _enet_mii_duplex +typedef enum _enet_mii_duplex { kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */ kENET_MiiFullDuplex /*!< Full duplex mode. */ } enet_mii_duplex_t; /*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */ -typedef enum _enet_mii_write +typedef enum _enet_mii_write { kENET_MiiWriteNoCompliant = 0U, /*!< Write frame operation, but not MII-compliant. */ kENET_MiiWriteValidFrame /*!< Write frame operation for a valid MII management frame. */ } enet_mii_write_t; /*! @brief Defines the read operation for the MII management frame. */ -typedef enum _enet_mii_read +typedef enum _enet_mii_read { kENET_MiiReadValidFrame = 2U, /*!< Read frame operation for a valid MII management frame. */ kENET_MiiReadNoCompliant = 3U /*!< Read frame operation, but not MII-compliant. */ @@ -226,7 +230,8 @@ typedef enum _enet_mii_read #if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO /*! @brief Define the MII opcode for extended MDIO_CLAUSES_45 Frame. */ -typedef enum _enet_mii_extend_opcode { +typedef enum _enet_mii_extend_opcode +{ kENET_MiiAddrWrite_C45 = 0U, /*!< Address Write operation. */ kENET_MiiWriteFrame_C45 = 1U, /*!< Write frame operation for a valid MII management frame. */ kENET_MiiReadFrame_C45 = 3U /*!< Read frame operation for a valid MII management frame. */ @@ -245,7 +250,7 @@ typedef enum _enet_mii_extend_opcode { * configure rxFifoFullThreshold and txFifoWatermark * in the enet_config_t. */ -typedef enum _enet_special_control_flag +typedef enum _enet_special_control_flag { kENET_ControlFlowControlEnable = 0x0001U, /*!< Enable ENET flow control: pause frame. */ kENET_ControlRxPayloadCheckEnable = 0x0002U, /*!< Enable ENET receive payload length check. */ @@ -268,7 +273,7 @@ typedef enum _enet_special_control_flag * members. Members usually map to interrupt enable bits in one or more * peripheral registers. */ -typedef enum _enet_interrupt_enable +typedef enum _enet_interrupt_enable { kENET_BabrInterrupt = ENET_EIR_BABR_MASK, /*!< Babbling receive error interrupt source */ kENET_BabtInterrupt = ENET_EIR_BABT_MASK, /*!< Babbling transmit error interrupt source */ @@ -302,7 +307,7 @@ typedef enum _enet_interrupt_enable } enet_interrupt_enable_t; /*! @brief Defines the common interrupt event for callback use. */ -typedef enum _enet_event +typedef enum _enet_event { kENET_RxEvent, /*!< Receive event. */ kENET_TxEvent, /*!< Transmit event. */ @@ -314,7 +319,7 @@ typedef enum _enet_event #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB /*! @brief Defines certain idle slope for bandwidth fraction. */ -typedef enum _enet_idle_slope +typedef enum _enet_idle_slope { kENET_IdleSlope1 = 1U, /*!< The bandwidth fraction is about 0.002. */ kENET_IdleSlope2 = 2U, /*!< The bandwidth fraction is about 0.003. */ @@ -339,7 +344,7 @@ typedef enum _enet_idle_slope #endif /* FSL_FEATURE_ENET_HAS_AVB */ /*! @brief Defines the transmit accelerator configuration. */ -typedef enum _enet_tx_accelerator +typedef enum _enet_tx_accelerator { kENET_TxAccelIsShift16Enabled = ENET_TACC_SHIFT16_MASK, /*!< Transmit FIFO shift-16. */ kENET_TxAccelIpCheckEnabled = ENET_TACC_IPCHK_MASK, /*!< Insert IP header checksum. */ @@ -347,7 +352,7 @@ typedef enum _enet_tx_accelerator } enet_tx_accelerator_t; /*! @brief Defines the receive accelerator configuration. */ -typedef enum _enet_rx_accelerator +typedef enum _enet_rx_accelerator { kENET_RxAccelPadRemoveEnabled = ENET_RACC_PADREM_MASK, /*!< Padding removal for short IP frames. */ kENET_RxAccelIpCheckEnabled = ENET_RACC_IPDIS_MASK, /*!< Discard with wrong IP header checksum. */ @@ -358,7 +363,7 @@ typedef enum _enet_rx_accelerator #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE /*! @brief Defines the ENET PTP message related constant. */ -typedef enum _enet_ptp_event_type +typedef enum _enet_ptp_event_type { kENET_PtpEventMsgType = 3U, /*!< PTP event message type. */ kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */ @@ -367,7 +372,7 @@ typedef enum _enet_ptp_event_type } enet_ptp_event_type_t; /*! @brief Defines the IEEE 1588 PTP timer channel numbers. */ -typedef enum _enet_ptp_timer_channel +typedef enum _enet_ptp_timer_channel { kENET_PtpTimerChannel1 = 0U, /*!< IEEE 1588 PTP timer Channel 1. */ kENET_PtpTimerChannel2, /*!< IEEE 1588 PTP timer Channel 2. */ @@ -481,14 +486,16 @@ typedef struct _enet_data_error_stats */ typedef struct _enet_buffer_config { - uint16_t rxBdNumber; /*!< Receive buffer descriptor number. */ - uint16_t txBdNumber; /*!< Transmit buffer descriptor number. */ - uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ - uint32_t txBuffSizeAlign; /*!< Aligned transmit data buffer size. */ - volatile enet_rx_bd_struct_t *rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address: should be non-cacheable. */ - volatile enet_tx_bd_struct_t *txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address: should be non-cacheable. */ - uint8_t *rxBufferAlign; /*!< Receive data buffer start address. */ - uint8_t *txBufferAlign; /*!< Transmit data buffer start address. */ + uint16_t rxBdNumber; /*!< Receive buffer descriptor number. */ + uint16_t txBdNumber; /*!< Transmit buffer descriptor number. */ + uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ + uint32_t txBuffSizeAlign; /*!< Aligned transmit data buffer size. */ + volatile enet_rx_bd_struct_t + *rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address: should be non-cacheable. */ + volatile enet_tx_bd_struct_t + *txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address: should be non-cacheable. */ + uint8_t *rxBufferAlign; /*!< Receive data buffer start address. */ + uint8_t *txBufferAlign; /*!< Transmit data buffer start address. */ } enet_buffer_config_t; #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.c index f22eff941e..bbc49d62e7 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,6 +34,12 @@ #include "fsl_ewm.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ewm" +#endif + + /******************************************************************************* * Code ******************************************************************************/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.h index aa32ed3c71..55ab66af95 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.c index caf73d56b5..132dbfb702 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -31,10 +35,14 @@ #include "fsl_flexcan.h" /******************************************************************************* - * Definitons + * Definitions ******************************************************************************/ -#define FLEXCAN_TIME_QUANTA_NUM (10) +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcan" +#endif + /*! @brief FlexCAN Internal State. */ enum _flexcan_state @@ -80,14 +88,6 @@ typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle); * Prototypes ******************************************************************************/ -/*! - * @brief Get the FlexCAN instance from peripheral base address. - * - * @param base FlexCAN peripheral base address. - * @return FlexCAN instance. - */ -uint32_t FLEXCAN_GetInstance(CAN_Type *base); - /*! * @brief Enter FlexCAN Freeze Mode. * @@ -159,8 +159,12 @@ static void FLEXCAN_Reset(CAN_Type *base); * @param base FlexCAN peripheral base address. * @param sourceClock_Hz Source Clock in Hz. * @param baudRate_Bps Baud Rate in Bps. + * @param timingConfig FlexCAN timingConfig. */ -static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps); +static void FLEXCAN_SetBaudRate(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRate_Bps, + flexcan_timing_config_t timingConfig); #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) /*! @@ -171,8 +175,24 @@ static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_ * @param base FlexCAN peripheral base address. * @param sourceClock_Hz Source Clock in Hz. * @param baudRateFD_Bps FD frame Baud Rate in Bps. + * @param timingConfig FlexCAN timingConfig. */ -static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateFD_Bps); +static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateFD_Bps, flexcan_timing_config_t timingConfig); + +/*! + * @brief Get Mailbox offset number by dword. + * + * This function gets the offset number of the specified mailbox. + * Mailbox is not consecutive between memory regions when payload is not 8 bytes + * so need to calculate the specified mailbox address. + * For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes + * payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword + * after the 0x4002_4080, which is actually the address of mailbox MB[1].CS. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx Mailbox index. + */ +static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx); #endif /******************************************************************************* @@ -230,6 +250,7 @@ uint32_t FLEXCAN_GetInstance(CAN_Type *base) static void FLEXCAN_EnterFreezeMode(CAN_Type *base) { /* Set Freeze, Halt bits. */ + base->MCR |= CAN_MCR_FRZ_MASK; base->MCR |= CAN_MCR_HALT_MASK; /* Wait until the FlexCAN Module enter freeze mode. */ @@ -242,6 +263,7 @@ static void FLEXCAN_ExitFreezeMode(CAN_Type *base) { /* Clear Freeze, Halt bits. */ base->MCR &= ~CAN_MCR_HALT_MASK; + base->MCR &= ~CAN_MCR_FRZ_MASK; /* Wait until the FlexCAN Module exit freeze mode. */ while (base->MCR & CAN_MCR_FRZACK_MASK) @@ -405,14 +427,20 @@ static void FLEXCAN_Reset(CAN_Type *base) } } -static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps) +static void FLEXCAN_SetBaudRate(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRate_Bps, + flexcan_timing_config_t timingConfig) { - flexcan_timing_config_t timingConfig; - uint32_t priDiv = baudRate_Bps * FLEXCAN_TIME_QUANTA_NUM; + /* FlexCAN timing setting formula: + * quantum = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1); + */ + uint32_t quantum = 1 + (timingConfig.phaseSeg1 + 1) + (timingConfig.phaseSeg2 + 1) + (timingConfig.propSeg + 1); + uint32_t priDiv = baudRate_Bps * quantum; /* Assertion: Desired baud rate is too high. */ assert(baudRate_Bps <= 1000000U); - /* Assertion: Source clock should greater than baud rate * FLEXCAN_TIME_QUANTA_NUM. */ + /* Assertion: Source clock should greater than baud rate * quantum. */ assert(priDiv <= sourceClock_Hz); if (0 == priDiv) @@ -428,27 +456,26 @@ static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_ priDiv = 0xFF; } - /* FlexCAN timing setting formula: - * FLEXCAN_TIME_QUANTA_NUM = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1); - */ timingConfig.preDivider = priDiv; - timingConfig.phaseSeg1 = 3; - timingConfig.phaseSeg2 = 2; - timingConfig.propSeg = 1; - timingConfig.rJumpwidth = 1; /* Update actual timing characteristic. */ FLEXCAN_SetTimingConfig(base, &timingConfig); } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateFD_Bps) +static void FLEXCAN_SetFDBaudRate(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRateFD_Bps, + flexcan_timing_config_t timingConfig) { - flexcan_timing_config_t timingConfig; - uint32_t priDiv = baudRateFD_Bps * FLEXCAN_TIME_QUANTA_NUM; + /* FlexCAN FD timing setting formula: + * quantum = 1 + (FPSEG1 + 1) + (FPSEG2 + 1) + FPROPSEG; + */ + uint32_t quantum = 1 + (timingConfig.fphaseSeg1 + 1) + (timingConfig.fphaseSeg2 + 1) + timingConfig.fpropSeg; + uint32_t priDiv = baudRateFD_Bps * quantum; /* Assertion: Desired baud rate is too high. */ - assert(baudRateFD_Bps <= 1000000U); + assert(baudRateFD_Bps <= 8000000U); /* Assertion: Source clock should greater than baud rate * FLEXCAN_TIME_QUANTA_NUM. */ assert(priDiv <= sourceClock_Hz); @@ -465,14 +492,7 @@ static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint3 priDiv = 0xFF; } - /* FlexCAN timing setting formula: - * FLEXCAN_TIME_QUANTA_NUM = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1); - */ - timingConfig.preDivider = priDiv; - timingConfig.phaseSeg1 = 3; - timingConfig.phaseSeg2 = 2; - timingConfig.propSeg = 1; - timingConfig.rJumpwidth = 1; + timingConfig.fpreDivider = priDiv; /* Update actual timing characteristic. */ FLEXCAN_SetFDTimingConfig(base, &timingConfig); @@ -541,9 +561,9 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc base->MCR = mcrTemp; /* Baud Rate Configuration.*/ - FLEXCAN_SetBaudRate(base, sourceClock_Hz, config->baudRate); + FLEXCAN_SetBaudRate(base, sourceClock_Hz, config->baudRate, config->timingConfig); #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - FLEXCAN_SetFDBaudRate(base, sourceClock_Hz, config->baudRateFD); + FLEXCAN_SetFDBaudRate(base, sourceClock_Hz, config->baudRateFD, config->timingConfig); #endif } @@ -588,6 +608,17 @@ void FLEXCAN_GetDefaultConfig(flexcan_config_t *config) config->enableIndividMask = false; #if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) config->enableDoze = false; +#endif + /* Default protocol timing configuration, time quantum is 10. */ + config->timingConfig.phaseSeg1 = 3; + config->timingConfig.phaseSeg2 = 2; + config->timingConfig.propSeg = 1; + config->timingConfig.rJumpwidth = 1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + config->timingConfig.fphaseSeg1 = 3; + config->timingConfig.fphaseSeg2 = 3; + config->timingConfig.fpropSeg = 1; + config->timingConfig.frJumpwidth = 1; #endif } @@ -606,6 +637,15 @@ void FLEXCAN_FDEnable(CAN_Type *base, flexcan_mb_size_t dataSize, bool brs) FLEXCAN_EnterFreezeMode(base); base->MCR |= CAN_MCR_FDEN_MASK; base->FDCTRL |= CAN_FDCTRL_MBDSR0(dataSize); +#if defined(CAN_FDCTRL_MBDSR1_MASK) + base->FDCTRL |= CAN_FDCTRL_MBDSR1(dataSize); +#endif +#if defined(CAN_FDCTRL_MBDSR2_MASK) + base->FDCTRL |= CAN_FDCTRL_MBDSR2(dataSize); +#endif +#if defined(CAN_FDCTRL_MBDSR3_MASK) + base->FDCTRL |= CAN_FDCTRL_MBDSR3(dataSize); +#endif /* Exit Freeze Mode. */ FLEXCAN_ExitFreezeMode(base); } @@ -652,14 +692,15 @@ void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *co /* Enter Freeze Mode. */ FLEXCAN_EnterFreezeMode(base); + base->CBT |= CAN_CBT_BTF(1); /* Cleaning previous Timing Setting. */ base->FDCBT &= ~(CAN_FDCBT_FPRESDIV_MASK | CAN_FDCBT_FRJW_MASK | CAN_FDCBT_FPSEG1_MASK | CAN_FDCBT_FPSEG2_MASK | CAN_FDCBT_FPROPSEG_MASK); /* Updating Timing Setting according to configuration structure. */ - base->FDCBT |= (CAN_FDCBT_FPRESDIV(config->preDivider) | CAN_FDCBT_FRJW(config->rJumpwidth) | - CAN_FDCBT_FPSEG1(config->phaseSeg1) | CAN_FDCBT_FPSEG2(config->phaseSeg2) | - CAN_FDCBT_FPROPSEG(config->propSeg)); + base->FDCBT |= (CAN_FDCBT_FPRESDIV(config->fpreDivider) | CAN_FDCBT_FRJW(config->frJumpwidth) | + CAN_FDCBT_FPSEG1(config->fphaseSeg1) | CAN_FDCBT_FPSEG2(config->fphaseSeg2) | + CAN_FDCBT_FPROPSEG(config->fpropSeg)); /* Exit Freeze Mode. */ FLEXCAN_ExitFreezeMode(base); @@ -728,6 +769,35 @@ void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) base->MB[mbIdx].WORD1 = 0x0; } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx) +{ + uint32_t dataSize; + uint32_t offset = 0; + dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + switch (dataSize) + { + case kFLEXCAN_8BperMB: + offset = (mbIdx / 32) * 512 + mbIdx % 32 * 16; + break; + case kFLEXCAN_16BperMB: + offset = (mbIdx / 21) * 512 + mbIdx % 21 * 24; + break; + case kFLEXCAN_32BperMB: + offset = (mbIdx / 12) * 512 + mbIdx % 12 * 40; + break; + case kFLEXCAN_64BperMB: + offset = (mbIdx / 7) * 512 + mbIdx % 7 * 72; + break; + default: + break; + } + /* To get the dword aligned offset, need to divide by 4. */ + offset = offset / 4; + return offset; +} +#endif + #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) { @@ -735,85 +805,44 @@ void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint8_t cnt = 0; + uint8_t payload_dword = 1; uint32_t dataSize; dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); +#endif /* Inactivate Message Buffer. */ if (enable) { - switch (dataSize) - { - case kFLEXCAN_8BperMB: - base->MB_8B[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); - break; - case kFLEXCAN_16BperMB: - base->MB_16B[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); - break; - case kFLEXCAN_32BperMB: - base->MB_32B[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); - break; - case kFLEXCAN_64BperMB: - base->MB_64B[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); - break; - default: - break; - } + /* Inactivate by writing CS. */ + mbAddr[offset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); } else { - switch (dataSize) - { - case kFLEXCAN_8BperMB: - base->MB_8B[mbIdx].CS = 0; - break; - case kFLEXCAN_16BperMB: - base->MB_16B[mbIdx].CS = 0; - break; - case kFLEXCAN_32BperMB: - base->MB_32B[mbIdx].CS = 0; - break; - case kFLEXCAN_64BperMB: - base->MB_64B[mbIdx].CS = 0; - break; - default: - break; - } + mbAddr[offset] = 0x0; } - /* Clean ID and Message Buffer content. */ - switch (dataSize) + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < dataSize + 1; cnt++) { - case kFLEXCAN_8BperMB: - base->MB_8B[mbIdx].ID = 0x0; - for (cnt = 0; cnt < 2; cnt++) - { - base->MB_8B[mbIdx].WORD[cnt] = 0x0; - } - break; - case kFLEXCAN_16BperMB: - base->MB_16B[mbIdx].ID = 0x0; - for (cnt = 0; cnt < 4; cnt++) - { - base->MB_16B[mbIdx].WORD[cnt] = 0x0; - } - break; - case kFLEXCAN_32BperMB: - base->MB_32B[mbIdx].ID = 0x0; - for (cnt = 0; cnt < 8; cnt++) - { - base->MB_32B[mbIdx].WORD[cnt] = 0x0; - } - break; - case kFLEXCAN_64BperMB: - base->MB_64B[mbIdx].ID = 0x0; - for (cnt = 0; cnt < 16; cnt++) - { - base->MB_64B[mbIdx].WORD[cnt] = 0x0; - } - break; - default: - break; + payload_dword *= 2; } + + /* Clean ID. */ + mbAddr[offset + 1] = 0x0; + /* Clean Message Buffer content, DWORD by DWORD. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2 + cnt] = 0x0; + } + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif } #endif @@ -867,68 +896,22 @@ void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_ uint32_t cs_temp = 0; uint8_t cnt = 0; - uint32_t dataSize; - dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); - /* Inactivate Message Buffer and clean ID, Message Buffer content. */ - switch (dataSize) + /* Inactivate all mailboxes first, clean ID and Message Buffer content. */ + for (cnt = 0; cnt < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); cnt++) { - case kFLEXCAN_8BperMB: - base->MB_8B[mbIdx].CS = 0; - base->MB_8B[mbIdx].ID = 0x0; - for (cnt = 0; cnt < 2; cnt++) - { - base->MB_8B[mbIdx].WORD[cnt] = 0x0; - } - break; - case kFLEXCAN_16BperMB: - base->MB_16B[mbIdx].CS = 0; - base->MB_16B[mbIdx].ID = 0x0; - for (cnt = 0; cnt < 4; cnt++) - { - base->MB_16B[mbIdx].WORD[cnt] = 0x0; - } - break; - case kFLEXCAN_32BperMB: - base->MB_32B[mbIdx].CS = 0; - base->MB_32B[mbIdx].ID = 0x0; - for (cnt = 0; cnt < 8; cnt++) - { - base->MB_32B[mbIdx].WORD[cnt] = 0x0; - } - break; - case kFLEXCAN_64BperMB: - base->MB_64B[mbIdx].CS = 0; - base->MB_64B[mbIdx].ID = 0x0; - for (cnt = 0; cnt < 16; cnt++) - { - base->MB_64B[mbIdx].WORD[cnt] = 0x0; - } - break; - default: - break; + base->MB[cnt].CS = 0; + base->MB[cnt].ID = 0; + base->MB[cnt].WORD0 = 0; + base->MB[cnt].WORD1 = 0; } if (enable) { /* Setup Message Buffer ID. */ - switch (dataSize) - { - case kFLEXCAN_8BperMB: - base->MB_8B[mbIdx].ID = config->id; - break; - case kFLEXCAN_16BperMB: - base->MB_16B[mbIdx].ID = config->id; - break; - case kFLEXCAN_32BperMB: - base->MB_32B[mbIdx].ID = config->id; - break; - case kFLEXCAN_64BperMB: - base->MB_64B[mbIdx].ID = config->id; - break; - default: - break; - } + mbAddr[offset + 1] = config->id; /* Setup Message Buffer format. */ if (kFLEXCAN_FrameFormatExtend == config->format) @@ -938,23 +921,7 @@ void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_ /* Activate Rx Message Buffer. */ cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); - switch (dataSize) - { - case kFLEXCAN_8BperMB: - base->MB_8B[mbIdx].CS = cs_temp; - break; - case kFLEXCAN_16BperMB: - base->MB_16B[mbIdx].CS = cs_temp; - break; - case kFLEXCAN_32BperMB: - base->MB_32B[mbIdx].CS = cs_temp; - break; - case kFLEXCAN_64BperMB: - base->MB_64B[mbIdx].CS = cs_temp; - break; - default: - break; - } + mbAddr[offset] = cs_temp; } } #endif @@ -1152,57 +1119,27 @@ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_fra /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(txFrame); - assert(txFrame->length <= 15); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp = 0; uint8_t cnt = 0; uint32_t can_cs = 0; + uint8_t payload_dword = 1; uint32_t dataSize; dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); +#endif + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); - switch (dataSize) - { - case kFLEXCAN_8BperMB: - can_cs = base->MB_8B[mbIdx].CS; - break; - case kFLEXCAN_16BperMB: - can_cs = base->MB_16B[mbIdx].CS; - break; - case kFLEXCAN_32BperMB: - can_cs = base->MB_32B[mbIdx].CS; - break; - case kFLEXCAN_64BperMB: - can_cs = base->MB_64B[mbIdx].CS; - break; - default: - break; - } + can_cs = mbAddr[0]; /* Check if Message Buffer is available. */ if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (can_cs & CAN_CS_CODE_MASK)) { /* Inactive Tx Message Buffer and Fill Message ID field. */ - switch (dataSize) - { - case kFLEXCAN_8BperMB: - base->MB_8B[mbIdx].CS = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); - base->MB_8B[mbIdx].ID = txFrame->id; - break; - case kFLEXCAN_16BperMB: - base->MB_16B[mbIdx].CS = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); - base->MB_16B[mbIdx].ID = txFrame->id; - break; - case kFLEXCAN_32BperMB: - base->MB_32B[mbIdx].CS = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); - base->MB_32B[mbIdx].ID = txFrame->id; - break; - case kFLEXCAN_64BperMB: - base->MB_64B[mbIdx].CS = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); - base->MB_64B[mbIdx].ID = txFrame->id; - break; - default: - break; - } + mbAddr[offset] = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); + mbAddr[offset + 1] = txFrame->id; /* Fill Message Format field. */ if (kFLEXCAN_FrameFormatExtend == txFrame->format) @@ -1212,44 +1149,23 @@ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_fra cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length) | CAN_CS_EDL(1); - /* Load Message Payload and Activate Tx Message Buffer. */ - switch (dataSize) + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < dataSize + 1; cnt++) { - case kFLEXCAN_8BperMB: - for (cnt = 0; cnt < 2; cnt++) - { - base->MB_8B[mbIdx].WORD[cnt] = txFrame->dataWord[cnt]; - } - base->MB_8B[mbIdx].CS = cs_temp; - break; - case kFLEXCAN_16BperMB: - for (cnt = 0; cnt < 4; cnt++) - { - base->MB_16B[mbIdx].WORD[cnt] = txFrame->dataWord[cnt]; - } - base->MB_16B[mbIdx].CS = cs_temp; - break; - case kFLEXCAN_32BperMB: - for (cnt = 0; cnt < 8; cnt++) - { - base->MB_32B[mbIdx].WORD[cnt] = txFrame->dataWord[cnt]; - } - base->MB_32B[mbIdx].CS = cs_temp; - break; - case kFLEXCAN_64BperMB: - for (cnt = 0; cnt < 16; cnt++) - { - base->MB_64B[mbIdx].WORD[cnt] = txFrame->dataWord[cnt]; - } - base->MB_64B[mbIdx].CS = cs_temp; - break; - default: - break; + payload_dword *= 2; } + /* Load Message Payload and Activate Tx Message Buffer. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2 + cnt] = txFrame->dataWord[cnt]; + } + mbAddr[offset] = cs_temp; + #if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) - base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); - base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); #endif return kStatus_Success; @@ -1331,30 +1247,14 @@ status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *r uint32_t can_id = 0; uint32_t dataSize; dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; - cs_temp = base->MB[mbIdx].CS; + uint8_t payload_dword = 1; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); /* Read CS field of Rx Message Buffer to lock Message Buffer. */ - switch (dataSize) - { - case kFLEXCAN_8BperMB: - cs_temp = base->MB_8B[mbIdx].CS; - can_id = base->MB_8B[mbIdx].ID; - break; - case kFLEXCAN_16BperMB: - cs_temp = base->MB_16B[mbIdx].CS; - can_id = base->MB_16B[mbIdx].ID; - break; - case kFLEXCAN_32BperMB: - cs_temp = base->MB_32B[mbIdx].CS; - can_id = base->MB_32B[mbIdx].ID; - break; - case kFLEXCAN_64BperMB: - cs_temp = base->MB_64B[mbIdx].CS; - can_id = base->MB_64B[mbIdx].ID; - break; - default: - break; - } + cs_temp = mbAddr[offset]; + can_id = mbAddr[offset + 1]; + /* Get Rx Message Buffer Code field. */ rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT; @@ -1373,35 +1273,17 @@ status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *r /* Get the message length. */ rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT; - /* Store Message Payload. */ - switch (dataSize) + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < dataSize + 1; cnt++) { - case kFLEXCAN_8BperMB: - for (cnt = 0; cnt < 2; cnt++) - { - rxFrame->dataWord[cnt] = base->MB_8B[mbIdx].WORD[cnt]; - } - break; - case kFLEXCAN_16BperMB: - for (cnt = 0; cnt < 4; cnt++) - { - rxFrame->dataWord[cnt] = base->MB_16B[mbIdx].WORD[cnt]; - } - break; - case kFLEXCAN_32BperMB: - for (cnt = 0; cnt < 8; cnt++) - { - rxFrame->dataWord[cnt] = base->MB_32B[mbIdx].WORD[cnt]; - } - break; - case kFLEXCAN_64BperMB: - for (cnt = 0; cnt < 16; cnt++) - { - rxFrame->dataWord[cnt] = base->MB_64B[mbIdx].WORD[cnt]; - } - break; - default: - break; + payload_dword *= 2; + } + + /* Store Message Payload. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + rxFrame->dataWord[cnt] = mbAddr[offset + 2 + cnt]; } /* Read free-running timer to unlock Rx Message Buffer. */ @@ -2201,3 +2083,45 @@ void DMA_FLEXCAN2_INT_DriverIRQHandler(void) #endif } #endif + +#if defined(ADMA__CAN0) +void ADMA_FLEXCAN0_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); + + s_flexcanIsr(ADMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__CAN1) +void ADMA_FLEXCAN1_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); + + s_flexcanIsr(ADMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__CAN2) +void ADMA_FLEXCAN2_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); + + s_flexcanIsr(ADMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h index 3ae7598f00..78ec2c4293 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -44,7 +48,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief FlexCAN driver version 2.2.0. */ -#define FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /*@}*/ /*! @brief FlexCAN Frame ID helper macro. */ @@ -68,24 +72,26 @@ (FLEXCAN_ID_STD(id) << 1)) /*!< Standard Rx FIFO Mask helper macro Type A helper macro. */ #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide) \ (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ - (((uint32_t)(id) & 0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */ + (((uint32_t)(id)&0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */ #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide) \ (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ - (((uint32_t)(id) & 0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */ + (((uint32_t)(id)&0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */ #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \ - (((uint32_t)(id) & 0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */ + (((uint32_t)(id)&0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */ #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \ - (((uint32_t)(id) & 0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ + (((uint32_t)(id)&0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \ - (((uint32_t)(id) & 0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ + (((uint32_t)(id)&0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \ - (((uint32_t)(id) & 0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */ + (((uint32_t)(id)&0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */ #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) \ (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */ #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \ - (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ - ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ + ( \ + ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \ + << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \ (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \ @@ -119,9 +125,10 @@ #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \ FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW( \ id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ -#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \ - FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. \ - */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. \ \ \ \ \ \ + */ #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \ FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */ #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \ @@ -130,9 +137,10 @@ #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \ FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW( \ id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */ -#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \ - FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. \ - */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. \ \ \ \ \ \ + */ #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \ FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH( \ id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ @@ -363,11 +371,11 @@ typedef struct _flexcan_fd_frame uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ uint32_t srr : 1; /*!< Substitute Remote request. */ uint32_t : 1; - uint32_t code : 4; /*!< Message Buffer Code. */ + uint32_t code : 4; /*!< Message Buffer Code. */ uint32_t : 1; - uint32_t esi : 1; /*!< Error State Indicator. */ - uint32_t brs : 1; /*!< Bit Rate Switch. */ - uint32_t edl : 1; /*!< Extended Data Length. */ + uint32_t esi : 1; /*!< Error State Indicator. */ + uint32_t brs : 1; /*!< Bit Rate Switch. */ + uint32_t edl : 1; /*!< Extended Data Length. */ }; struct { @@ -395,6 +403,23 @@ typedef struct _flexcan_fd_frame } flexcan_fd_frame_t; #endif +/*! @brief FlexCAN protocol timing characteristic configuration structure. */ +typedef struct _flexcan_timing_config +{ + uint16_t preDivider; /*!< Clock Pre-scaler Division Factor. */ + uint8_t rJumpwidth; /*!< Re-sync Jump Width. */ + uint8_t phaseSeg1; /*!< Phase Segment 1. */ + uint8_t phaseSeg2; /*!< Phase Segment 2. */ + uint8_t propSeg; /*!< Propagation Segment. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + uint16_t fpreDivider; /*!< Fast Clock Pre-scaler Division Factor. */ + uint8_t frJumpwidth; /*!< Fast Re-sync Jump Width. */ + uint8_t fphaseSeg1; /*!< Fast Phase Segment 1. */ + uint8_t fphaseSeg2; /*!< Fast Phase Segment 2. */ + uint8_t fpropSeg; /*!< Fast Propagation Segment. */ +#endif +} flexcan_timing_config_t; + /*! @brief FlexCAN module configuration structure. */ typedef struct _flexcan_config { @@ -412,18 +437,9 @@ typedef struct _flexcan_config #if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) bool enableDoze; /*!< Enable or Disable Doze Mode. */ #endif + flexcan_timing_config_t timingConfig; /* Protocol timing . */ } flexcan_config_t; -/*! @brief FlexCAN protocol timing characteristic configuration structure. */ -typedef struct _flexcan_timing_config -{ - uint16_t preDivider; /*!< Clock Pre-scaler Division Factor. */ - uint8_t rJumpwidth; /*!< Re-sync Jump Width. */ - uint8_t phaseSeg1; /*!< Phase Segment 1. */ - uint8_t phaseSeg2; /*!< Phase Segment 2. */ - uint8_t propSeg; /*!< Propagation Segment. */ -} flexcan_timing_config_t; - /*! * @brief FlexCAN Receive Message Buffer configuration structure * @@ -510,6 +526,14 @@ extern "C" { * @{ */ +/*! + * @brief Get the FlexCAN instance from peripheral base address. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN instance. + */ +uint32_t FLEXCAN_GetInstance(CAN_Type *base); + /*! * @brief Initializes a FlexCAN instance. * @@ -525,6 +549,7 @@ extern "C" { * flexcanConfig.enableSelfWakeup = false; * flexcanConfig.enableIndividMask = false; * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; * FLEXCAN_Init(CAN0, &flexcanConfig, 8000000UL); * @endcode * @@ -556,6 +581,7 @@ void FLEXCAN_Deinit(CAN_Type *base); * flexcanConfig->enableSelfWakeup = false; * flexcanConfig->enableIndividMask = false; * flexcanConfig->enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; * * @param config Pointer to the FlexCAN configuration structure. */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.c index 892a3eed3a..e6c256c3ee 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -34,12 +38,25 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio" +#endif + + /*< @brief user configurable flexio handle count. */ #define FLEXIO_HANDLE_COUNT 2 /******************************************************************************* * Variables ******************************************************************************/ +/*! @brief Pointers to flexio bases for each instance. */ +FLEXIO_Type *const s_flexioBases[] = FLEXIO_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to flexio clocks for each instance. */ +const clock_ip_name_t s_flexioClocks[] = FLEXIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /*< @brief pointer to array of FLEXIO handle. */ static void *s_flexioHandle[FLEXIO_HANDLE_COUNT]; @@ -50,14 +67,6 @@ static void *s_flexioType[FLEXIO_HANDLE_COUNT]; /*< @brief pointer to array of FLEXIO Isr. */ static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT]; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to flexio clocks for each instance. */ -const clock_ip_name_t s_flexioClocks[] = FLEXIO_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointers to flexio bases for each instance. */ -FLEXIO_Type *const s_flexioBases[] = FLEXIO_BASE_PTRS; - /******************************************************************************* * Codes ******************************************************************************/ @@ -178,7 +187,7 @@ uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig) { base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource) -#if defined(FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH) && FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH +#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH | FLEXIO_SHIFTCFG_PWIDTH(shifterConfig->parallelWidth) #endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ | FLEXIO_SHIFTCFG_SSTOP(shifterConfig->shifterStop) | diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.h index 80ab21f643..bebca939ec 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -43,8 +47,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief FlexIO driver version 2.0.1. */ -#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*! @brief FlexIO driver version 2.0.2. */ +#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*@}*/ /*! @brief Calculate FlexIO timer trigger.*/ @@ -185,11 +189,11 @@ typedef enum _flexio_shifter_mode kFLEXIO_ShifterModeTransmit = 0x2U, /*!< Transmit mode. */ kFLEXIO_ShifterModeMatchStore = 0x4U, /*!< Match store mode. */ kFLEXIO_ShifterModeMatchContinuous = 0x5U, /*!< Match continuous mode. */ -#if defined(FSL_FEATURE_FLEXIO_HAS_STATE_MODE) && FSL_FEATURE_FLEXIO_HAS_STATE_MODE +#if FSL_FEATURE_FLEXIO_HAS_STATE_MODE kFLEXIO_ShifterModeState = 0x6U, /*!< SHIFTBUF contents are used for storing programmable state attributes. */ #endif /* FSL_FEATURE_FLEXIO_HAS_STATE_MODE */ -#if defined(FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE) && FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE +#if FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE kFLEXIO_ShifterModeLogic = 0x7U, /*!< SHIFTBUF contents are used for implementing programmable logic look up table. */ #endif /* FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE */ @@ -290,7 +294,7 @@ typedef struct _flexio_shifter_config flexio_pin_polarity_t pinPolarity; /*!< Shifter Pin Polarity. */ /* Shifter. */ flexio_shifter_mode_t shifterMode; /*!< Configures the mode of the Shifter. */ -#if defined(FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH) && FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH +#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH uint32_t parallelWidth; /*!< Configures the parallel width when using parallel mode.*/ #endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ flexio_shifter_input_source_t inputSource; /*!< Selects the input source for the shifter. */ @@ -301,6 +305,16 @@ typedef struct _flexio_shifter_config /*! @brief typedef for FlexIO simulated driver interrupt handler.*/ typedef void (*flexio_isr_t)(void *base, void *handle); +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to flexio bases for each instance. */ +extern FLEXIO_Type *const s_flexioBases[]; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to flexio clocks for each instance. */ +extern const clock_ip_name_t s_flexioClocks[]; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /******************************************************************************* * API ******************************************************************************/ @@ -357,6 +371,13 @@ void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig); */ void FLEXIO_Deinit(FLEXIO_Type *base); +/*! + * @brief Get instance number for FLEXIO module. + * + * @param base FLEXIO peripheral base address. + */ +uint32_t FLEXIO_GetInstance(FLEXIO_Type *base); + /* @} */ /*! diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.c index 13790d2a60..3d3ca0d657 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -34,6 +38,12 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_i2c_master" +#endif + + /*! @brief FLEXIO I2C transfer state */ enum _flexio_i2c_master_transfer_states { @@ -45,18 +55,10 @@ enum _flexio_i2c_master_transfer_states kFLEXIO_I2C_ReceiveData = 0x5U, /*!< Receive data transfer phase*/ }; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -extern const clock_ip_name_t s_flexioClocks[]; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -extern FLEXIO_Type *const s_flexioBases[]; - /******************************************************************************* * Prototypes ******************************************************************************/ -extern uint32_t FLEXIO_GetInstance(FLEXIO_Type *base); - /*! * @brief Set up master transfer, send slave address and decide the initial * transfer state. @@ -97,7 +99,7 @@ static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base, * Codes ******************************************************************************/ -uint32_t FLEXIO_I2C_GetInstance(FLEXIO_I2C_Type *base) +static uint32_t FLEXIO_I2C_GetInstance(FLEXIO_I2C_Type *base) { return FLEXIO_GetInstance(base->flexioBase); } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.h index 0a38087bfb..5e6ee2b9bf 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -44,8 +48,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief FlexIO I2C master driver version 2.1.2. */ -#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/*! @brief FlexIO I2C master driver version 2.1.5. */ +#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) /*@}*/ /*! @brief FlexIO I2C transfer status*/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.c index 0f6767e32e..5e7bc43773 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,6 +34,12 @@ #include "fsl_flexio_i2s.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s" +#endif + + /******************************************************************************* * Definitations ******************************************************************************/ @@ -43,8 +53,6 @@ enum _sai_transfer_state * Prototypes ******************************************************************************/ -extern uint32_t FLEXIO_GetInstance(FLEXIO_Type *base); - /*! * @brief Receive a piece of data in non-blocking way. * @@ -68,17 +76,11 @@ static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, * Variables ******************************************************************************/ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -extern const clock_ip_name_t s_flexioClocks[]; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -extern FLEXIO_Type *const s_flexioBases[]; - /******************************************************************************* * Code ******************************************************************************/ -uint32_t FLEXIO_I2S_GetInstance(FLEXIO_I2S_Type *base) +static uint32_t FLEXIO_I2S_GetInstance(FLEXIO_I2S_Type *base) { return FLEXIO_GetInstance(base->flexioBase); } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.h index b111dbc52e..2d7326c37e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -44,8 +48,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief FlexIO I2S driver version 2.1.1. */ -#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/*! @brief FlexIO I2S driver version 2.1.4. */ +#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*@}*/ /*! @brief FlexIO I2S transfer status */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s_edma.c index 74721384ca..223d71d759 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s_edma.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s_edma.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,11 +34,17 @@ #include "fsl_flexio_i2s_edma.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s_edma" +#endif + + /******************************************************************************* * Definitations ******************************************************************************/ /* Used for 32byte aligned */ -#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)address + 32) & ~0x1FU) +#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + 32) & ~0x1FU) /*flexioBase); } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi.h index a6eb84a511..e72f6e09cd 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -45,8 +49,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief FlexIO SPI driver version 2.1.1. */ -#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*! @brief FlexIO SPI driver version 2.1.3. */ +#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) /*@}*/ #ifndef FLEXIO_SPI_DUMMYDATA diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi_edma.c index aafa851935..2c6aeda82b 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi_edma.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi_edma.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -31,8 +35,14 @@ #include "fsl_flexio_spi_edma.h" /******************************************************************************* - * Definitons + * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_spi_edma" +#endif + /*flexioBase); } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart.h index 169a1495eb..356752a14a 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -45,8 +49,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief FlexIO UART driver version 2.1.2. */ -#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/*! @brief FlexIO UART driver version 2.1.4. */ +#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*@}*/ /*! @brief Error codes for the UART driver. */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart_edma.c index 5fa493a899..3b008e620f 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart_edma.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart_edma.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -34,6 +38,12 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_uart_edma" +#endif + + /*GPR14 &= ~IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_MASK; - IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ(FLEXRAM_MapTcmSizeToRegister(dtcmBankNum)); + IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK; + IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(FLEXRAM_MapTcmSizeToRegister(dtcmBankNum)); IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK; } else @@ -167,8 +176,8 @@ static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum) /* itcm configuration */ if (itcmBankNum != 0U) { - IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_MASK; - IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ(FLEXRAM_MapTcmSizeToRegister(itcmBankNum)); + IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK; + IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(FLEXRAM_MapTcmSizeToRegister(itcmBankNum)); IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK; } else diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexram.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexram.h index 65a667475a..b84e8daec9 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexram.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexram.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright 2017 NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -44,8 +48,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief Driver version 2.0.1. */ -#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) +/*! @brief Driver version 2.0.2. */ +#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 2U)) /*@}*/ /*! @brief flexram write read sel */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c index 57780839f6..d74ab47e23 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,6 +34,12 @@ #include "fsl_flexspi.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexspi" +#endif + + /******************************************************************************* * Definitations ******************************************************************************/ @@ -97,8 +107,10 @@ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status); * Variables ******************************************************************************/ +#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ /*! @brief Pointers to flexspi handles for each instance. */ static void *s_flexspiHandle[FSL_FEATURE_SOC_FLEXSPI_COUNT]; +#endif /*! @brief Pointers to flexspi bases for each instance. */ static FLEXSPI_Type *const s_flexspiBases[] = FLEXSPI_BASE_PTRS; @@ -247,7 +259,7 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config) FLEXSPI_MCR0_HSEN(config->enableHalfSpeedAccess) | FLEXSPI_MCR0_COMBINATIONEN(config->enableCombination) | FLEXSPI_MCR0_ATDFEN(config->ahbConfig.enableAHBWriteIpTxFifo) | - FLEXSPI_MCR0_ATDFEN(config->ahbConfig.enableAHBWriteIpRxFifo) | FLEXSPI_MCR0_MDIS_MASK; + FLEXSPI_MCR0_ARDFEN(config->ahbConfig.enableAHBWriteIpRxFifo) | FLEXSPI_MCR0_MDIS_MASK; base->MCR0 = configValue; /* Configure MCR1 configurations. */ @@ -256,28 +268,45 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config) base->MCR1 = configValue; /* Configure MCR2 configurations. */ - configValue = FLEXSPI_MCR2_RESUMEWAIT(config->ahbConfig.resumeWaitCycle) | - FLEXSPI_MCR2_SCKBDIFFOPT(config->enableSckBDiffOpt) | - FLEXSPI_MCR2_SAMEDEVICEEN(config->enableSameConfigForAll) | - FLEXSPI_MCR2_CLRAHBBUFOPT(config->ahbConfig.enableClearAHBBufferOpt); + configValue = base->MCR2; + configValue &= ~(FLEXSPI_MCR2_RESUMEWAIT_MASK | FLEXSPI_MCR2_SCKBDIFFOPT_MASK | FLEXSPI_MCR2_SAMEDEVICEEN_MASK | + FLEXSPI_MCR2_CLRAHBBUFOPT_MASK); + configValue |= FLEXSPI_MCR2_RESUMEWAIT(config->ahbConfig.resumeWaitCycle) | + FLEXSPI_MCR2_SCKBDIFFOPT(config->enableSckBDiffOpt) | + FLEXSPI_MCR2_SAMEDEVICEEN(config->enableSameConfigForAll) | + FLEXSPI_MCR2_CLRAHBBUFOPT(config->ahbConfig.enableClearAHBBufferOpt); + base->MCR2 = configValue; /* Configure AHB control items. */ - base->AHBCR = FLEXSPI_AHBCR_PREFETCHEN(config->ahbConfig.enableAHBPrefetch) | - FLEXSPI_AHBCR_BUFFERABLEEN(config->ahbConfig.enableAHBBufferable) | - FLEXSPI_AHBCR_CACHABLEEN(config->ahbConfig.enableAHBCachable); + configValue = base->AHBCR; + configValue &= ~(FLEXSPI_AHBCR_READADDROPT_MASK | FLEXSPI_AHBCR_PREFETCHEN_MASK | FLEXSPI_AHBCR_BUFFERABLEEN_MASK | + FLEXSPI_AHBCR_CACHABLEEN_MASK); + configValue |= FLEXSPI_AHBCR_READADDROPT(config->ahbConfig.enableReadAddressOpt) | + FLEXSPI_AHBCR_PREFETCHEN(config->ahbConfig.enableAHBPrefetch) | + FLEXSPI_AHBCR_BUFFERABLEEN(config->ahbConfig.enableAHBBufferable) | + FLEXSPI_AHBCR_CACHABLEEN(config->ahbConfig.enableAHBCachable); + base->AHBCR = configValue; /* Configure AHB rx buffers. */ - for (i = 0; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1; i++) + for (i = 0; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++) { - base->AHBRXBUFCR0[i] = FLEXSPI_AHBRXBUFCR0_PRIORITY(config->ahbConfig.buffer[i].priority) | - FLEXSPI_AHBRXBUFCR0_MSTRID(config->ahbConfig.buffer[i].masterIndex) | - FLEXSPI_AHBRXBUFCR0_BUFSZ(config->ahbConfig.buffer[i].bufferSize / 8); + configValue = base->AHBRXBUFCR0[i]; + + configValue &= ~(FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK | + FLEXSPI_AHBRXBUFCR0_MSTRID_MASK | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK); + configValue |= FLEXSPI_AHBRXBUFCR0_PREFETCHEN(config->ahbConfig.buffer[i].enablePrefetch) | + FLEXSPI_AHBRXBUFCR0_PRIORITY(config->ahbConfig.buffer[i].priority) | + FLEXSPI_AHBRXBUFCR0_MSTRID(config->ahbConfig.buffer[i].masterIndex) | + FLEXSPI_AHBRXBUFCR0_BUFSZ(config->ahbConfig.buffer[i].bufferSize * 8); + base->AHBRXBUFCR0[i] = configValue; } /* Configure IP Fifo watermarks. */ + base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXWMRK_MASK; base->IPRXFCR |= FLEXSPI_IPRXFCR_RXWMRK(config->rxWatermark / 8 - 1); - base->IPTXFCR |= FLEXSPI_IPRXFCR_RXWMRK(config->txWatermark / 8 - 1); + base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXWMRK_MASK; + base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK(config->txWatermark / 8 - 1); } void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) @@ -299,7 +328,12 @@ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) config->ahbConfig.ahbBusTimeoutCycle = 0xFFFFU; config->ahbConfig.resumeWaitCycle = 0x20U; memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer)); + for (uint8_t i = 0; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++) + { + config->ahbConfig.buffer[i].bufferSize = 256; /* Default buffer size 256 bytes*/ + } config->ahbConfig.enableClearAHBBufferOpt = false; + config->ahbConfig.enableReadAddressOpt = false; config->ahbConfig.enableAHBPrefetch = false; config->ahbConfig.enableAHBBufferable = false; config->ahbConfig.enableAHBCachable = false; @@ -358,6 +392,15 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, base->DLLCR[index] = FLEXSPI_ConfigureDll(base, config); /* Configure write mask. */ + if (config->enableWriteMask) + { + base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMOPT1_MASK; + } + else + { + base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMOPT1_MASK; + } + if (index == 0) /*PortA*/ { base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENA_MASK; @@ -591,8 +634,10 @@ void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, handle->completionCallback = callback; handle->userData = userData; +#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ /* Save the context in global variables to support the double weak mechanism. */ s_flexspiHandle[instance] = handle; +#endif /* Enable NVIC interrupt. */ EnableIRQ(s_flexspiIrqs[instance]); @@ -785,6 +830,7 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle) } } +#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ #if defined(FLEXSPI) void FLEXSPI_DriverIRQHandler(void) { @@ -819,3 +865,4 @@ void FLEXSPI1_DriverIRQHandler(void) #endif } #endif +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.h index 965c2ad210..e2f00393b3 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -46,8 +50,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief FLEXSPI driver version 2.0.1. */ -#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*! @brief FLEXSPI driver version 2.0.2. */ +#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*@}*/ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0) @@ -231,9 +235,11 @@ typedef enum _flexspi_command_type typedef struct _flexspi_ahbBuffer_config { - uint8_t priority; - uint8_t masterIndex; - uint16_t bufferSize; + uint8_t priority; /*!< This priority for AHB Master Read which this AHB RX Buffer is assigned. */ + uint8_t masterIndex; /*!< AHB Master ID the AHB RX Buffer is assigned. */ + uint16_t bufferSize; /*!< AHB buffer size in byte. */ + bool enablePrefetch; /*!< AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows + prefetch disable/enable seperately for each master. */ } flexspi_ahbBuffer_config_t; /*! @brief FLEXSPI configuration structure. */ @@ -269,6 +275,8 @@ typedef struct _flexspi_config flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */ bool enableClearAHBBufferOpt; /*!< Enable/disable automatically clean AHB RX Buffer and TX Buffer when FLEXSPI returns STOP mode ACK. */ + bool enableReadAddressOpt; /*!< Enable/disable remove AHB read burst start address alignment limitation. + when eanble, there is no AHB read burst start address alignment limitation. */ bool enableAHBPrefetch; /*!< Enable/disable AHB read prefetch feature, when enabled, FLEXSPI will fetch more data than current AHB burst. */ bool enableAHBBufferable; /*!< Enable/disable AHB bufferable write access support, when enabled, diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.c new file mode 100644 index 0000000000..d52cfa3572 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.c @@ -0,0 +1,72 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexspi_nor_boot.h" + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.ivt"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.ivt" +#endif +/************************************* + * IVT Data + *************************************/ +const ivt image_vector_table = { + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.boot_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.boot_data" +#endif +/************************************* + * Boot Data + *************************************/ +const BOOT_DATA_T boot_data = { + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ +}; +#endif + + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.h new file mode 100644 index 0000000000..2656feb101 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.h @@ -0,0 +1,131 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FLEXSPI_NOR_BOOT_H__ +#define __FLEXSPI_NOR_BOOT_H__ + +#include +#include "device.h" + +/************************************* + * IVT Data + *************************************/ +typedef struct _ivt_ { + /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields + * (see @ref data) + */ + uint32_t hdr; + /** Absolute address of the first instruction to execute from the + * image + */ + uint32_t entry; + /** Reserved in this version of HAB: should be NULL. */ + uint32_t reserved1; + /** Absolute address of the image DCD: may be NULL. */ + uint32_t dcd; + /** Absolute address of the Boot Data: may be NULL, but not interpreted + * any further by HAB + */ + uint32_t boot_data; + /** Absolute address of the IVT.*/ + uint32_t self; + /** Absolute address of the image CSF.*/ + uint32_t csf; + /** Reserved in this version of HAB: should be zero. */ + uint32_t reserved2; +} ivt; + +#define IVT_MAJOR_VERSION 0x4 +#define IVT_MAJOR_VERSION_SHIFT 0x4 +#define IVT_MAJOR_VERSION_MASK 0xF +#define IVT_MINOR_VERSION 0x1 +#define IVT_MINOR_VERSION_SHIFT 0x0 +#define IVT_MINOR_VERSION_MASK 0xF + +#define IVT_VERSION(major, minor) \ + ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ + (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) + +/* IVT header */ +#define IVT_TAG_HEADER 0xD1 /**< Image Vector Table */ +#define IVT_SIZE 0x2000 +#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) +#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) + +/* Set resume entry */ +#if defined(__CC_ARM) + extern uint32_t __Vectors[]; + extern uint32_t Image$$RW_m_config_text$$Base[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors) +#define FLASH_BASE ((uint32_t)Image$$RW_m_config_text$$Base) +#elif defined(__MCUXPRESSO) + extern uint32_t __Vectors[]; + extern uint32_t __boot_hdr_start__[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors) +#define FLASH_BASE ((uint32_t)__boot_hdr_start__) +#elif defined(__ICCARM__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t m_boot_hdr_conf_start[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) +#define FLASH_BASE ((uint32_t)m_boot_hdr_conf_start) +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __FLASH_BASE[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) +#define FLASH_BASE ((uint32_t)__FLASH_BASE) +#endif + +#define DCD_ADDRESS dcd_data +#define BOOT_DATA_ADDRESS &boot_data +#define CSF_ADDRESS 0 +#define IVT_RSVD (uint32_t)(0x00000000) + +/************************************* + * Boot Data + *************************************/ +typedef struct _boot_data_ { + uint32_t start; /* boot start location */ + uint32_t size; /* size */ + uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ + uint32_t placeholder; /* placehoder to make even 0x10 size */ +}BOOT_DATA_T; + +#define FLASH_SIZE BOARD_FLASH_SIZE +#define PLUGIN_FLAG (uint32_t)0 + +/* External Variables */ +const BOOT_DATA_T boot_data; +extern const uint8_t dcd_data[]; + +#endif /* __FLEXSPI_NOR_BOOT_H__ */ + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpc.c index 806d28ccf8..90b7eb1542 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpc.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpc.c @@ -1,10 +1,13 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016 NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -17,6 +20,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -31,6 +35,12 @@ #include "fsl_gpc.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gpc_1" +#endif + + void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId) { uint32_t irqRegNum = irqId / 32U; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpc.h index b4a2981eb4..5ba31ecf65 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpc.h @@ -1,10 +1,13 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016 NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -17,6 +20,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpio.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpio.c index a5f7246c67..f4714aa53e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpio.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpio.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,6 +34,12 @@ #include "fsl_gpio.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.igpio" +#endif + + /******************************************************************************* * Variables ******************************************************************************/ @@ -76,7 +86,7 @@ static uint32_t GPIO_GetInstance(GPIO_Type *base) return instance; } -void GPIO_PinInit(GPIO_Type* base, uint32_t pin, const gpio_pin_config_t* Config) +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Enable GPIO clock. */ @@ -93,7 +103,7 @@ void GPIO_PinInit(GPIO_Type* base, uint32_t pin, const gpio_pin_config_t* Config } else { - GPIO_WritePinOutput(base, pin, Config->outputLogic); + GPIO_PinWrite(base, pin, Config->outputLogic); base->GDIR |= (1U << pin); } @@ -101,20 +111,20 @@ void GPIO_PinInit(GPIO_Type* base, uint32_t pin, const gpio_pin_config_t* Config GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode); } -void GPIO_PinWrite(GPIO_Type* base, uint32_t pin, uint8_t output) +void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) { assert(pin < 32); if (output == 0U) { - base->DR &= ~(1U << pin); /* Set pin output to low level.*/ + base->DR &= ~(1U << pin); /* Set pin output to low level.*/ } else { - base->DR |= (1U << pin); /* Set pin output to high level.*/ + base->DR |= (1U << pin); /* Set pin output to high level.*/ } } -void GPIO_PinSetInterruptConfig(GPIO_Type* base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) +void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) { volatile uint32_t *icr; uint32_t icrShift; @@ -124,7 +134,7 @@ void GPIO_PinSetInterruptConfig(GPIO_Type* base, uint32_t pin, gpio_interrupt_mo /* Register reset to default value */ base->EDGE_SEL &= ~(1U << pin); - if(pin < 16) + if (pin < 16) { icr = &(base->ICR1); } @@ -133,21 +143,21 @@ void GPIO_PinSetInterruptConfig(GPIO_Type* base, uint32_t pin, gpio_interrupt_mo icr = &(base->ICR2); icrShift -= 16; } - switch(pinInterruptMode) + switch (pinInterruptMode) { - case(kGPIO_IntLowLevel): + case (kGPIO_IntLowLevel): *icr &= ~(3U << (2 * icrShift)); break; - case(kGPIO_IntHighLevel): + case (kGPIO_IntHighLevel): *icr = (*icr & (~(3U << (2 * icrShift)))) | (1U << (2 * icrShift)); break; - case(kGPIO_IntRisingEdge): + case (kGPIO_IntRisingEdge): *icr = (*icr & (~(3U << (2 * icrShift)))) | (2U << (2 * icrShift)); break; - case(kGPIO_IntFallingEdge): + case (kGPIO_IntFallingEdge): *icr |= (3U << (2 * icrShift)); break; - case(kGPIO_IntRisingOrFallingEdge): + case (kGPIO_IntRisingOrFallingEdge): base->EDGE_SEL |= (1U << pin); break; default: diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpio.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpio.h index cad971080c..834a9c981a 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpio.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpio.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -51,27 +55,28 @@ /*! @brief GPIO direction definition. */ typedef enum _gpio_pin_direction { - kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input.*/ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input.*/ kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output.*/ } gpio_pin_direction_t; /*! @brief GPIO interrupt mode definition. */ typedef enum _gpio_interrupt_mode { - kGPIO_NoIntmode = 0U, /*!< Set current pin general IO functionality.*/ - kGPIO_IntLowLevel = 1U, /*!< Set current pin interrupt is low-level sensitive.*/ - kGPIO_IntHighLevel = 2U, /*!< Set current pin interrupt is high-level sensitive.*/ - kGPIO_IntRisingEdge = 3U, /*!< Set current pin interrupt is rising-edge sensitive.*/ - kGPIO_IntFallingEdge = 4U, /*!< Set current pin interrupt is falling-edge sensitive.*/ + kGPIO_NoIntmode = 0U, /*!< Set current pin general IO functionality.*/ + kGPIO_IntLowLevel = 1U, /*!< Set current pin interrupt is low-level sensitive.*/ + kGPIO_IntHighLevel = 2U, /*!< Set current pin interrupt is high-level sensitive.*/ + kGPIO_IntRisingEdge = 3U, /*!< Set current pin interrupt is rising-edge sensitive.*/ + kGPIO_IntFallingEdge = 4U, /*!< Set current pin interrupt is falling-edge sensitive.*/ kGPIO_IntRisingOrFallingEdge = 5U, /*!< Enable the edge select bit to override the ICR register's configuration.*/ } gpio_interrupt_mode_t; /*! @brief GPIO Init structure definition. */ typedef struct _gpio_pin_config { - gpio_pin_direction_t direction; /*!< Specifies the pin direction. */ - uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ - gpio_interrupt_mode_t interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */ + gpio_pin_direction_t direction; /*!< Specifies the pin direction. */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ + gpio_interrupt_mode_t + interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */ } gpio_pin_config_t; /******************************************************************************* @@ -96,7 +101,7 @@ extern "C" { * @param initConfig pointer to a @ref gpio_pin_config_t structure that * contains the configuration information. */ -void GPIO_PinInit(GPIO_Type* base, uint32_t pin, const gpio_pin_config_t* Config); +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config); /*@}*/ /*! @@ -113,13 +118,13 @@ void GPIO_PinInit(GPIO_Type* base, uint32_t pin, const gpio_pin_config_t* Config * - 0: corresponding pin output low-logic level. * - 1: corresponding pin output high-logic level. */ -void GPIO_PinWrite(GPIO_Type* base, uint32_t pin, uint8_t output); +void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output); /*! * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite. */ -static inline void GPIO_WritePinOutput(GPIO_Type* base, uint32_t pin, uint8_t output) +static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) { GPIO_PinWrite(base, pin, output); } @@ -130,16 +135,20 @@ static inline void GPIO_WritePinOutput(GPIO_Type* base, uint32_t pin, uint8_t ou * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) * @param mask GPIO pin number macro */ -static inline void GPIO_PortSet(GPIO_Type* base, uint32_t mask) +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask) { +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && (FSL_FEATURE_IGPIO_HAS_DR_SET == 1)) + base->DR_SET = mask; +#else base->DR |= mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_SET */ } /*! * @brief Sets the output level of the multiple GPIO pins to the logic 1. * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortSet. */ -static inline void GPIO_SetPinsOutput(GPIO_Type* base, uint32_t mask) +static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) { GPIO_PortSet(base, mask); } @@ -150,20 +159,37 @@ static inline void GPIO_SetPinsOutput(GPIO_Type* base, uint32_t mask) * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) * @param mask GPIO pin number macro */ -static inline void GPIO_PortClear(GPIO_Type* base, uint32_t mask) +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask) { +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && (FSL_FEATURE_IGPIO_HAS_DR_CLEAR == 1)) + base->DR_CLEAR = mask; +#else base->DR &= ~mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_CLEAR */ } /*! * @brief Sets the output level of the multiple GPIO pins to the logic 0. * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortClear. */ -static inline void GPIO_ClearPinsOutput(GPIO_Type* base, uint32_t mask) +static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) { GPIO_PortClear(base, mask); } +/*! + * @brief Reverses the current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_TOGGLE) && (FSL_FEATURE_IGPIO_HAS_DR_TOGGLE == 1)) + base->DR_TOGGLE = mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_TOGGLE */ +} + /*! * @brief Reads the current input value of the GPIO port. * @@ -171,7 +197,7 @@ static inline void GPIO_ClearPinsOutput(GPIO_Type* base, uint32_t mask) * @param pin GPIO port pin number. * @retval GPIO port input value. */ -static inline uint32_t GPIO_PinRead(GPIO_Type* base, uint32_t pin) +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) { assert(pin < 32); @@ -182,7 +208,7 @@ static inline uint32_t GPIO_PinRead(GPIO_Type* base, uint32_t pin) * @brief Reads the current input value of the GPIO port. * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinRead. */ -static inline uint32_t GPIO_ReadPinInput(GPIO_Type* base, uint32_t pin) +static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) { return GPIO_PinRead(base, pin); } @@ -193,28 +219,29 @@ static inline uint32_t GPIO_ReadPinInput(GPIO_Type* base, uint32_t pin) * @{ */ - /*! - * @brief Reads the current GPIO pin pad status. - * - * @param base GPIO base pointer. - * @param pin GPIO port pin number. - * @retval GPIO pin pad status value. - */ -static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type* base, uint32_t pin) +/*! +* @brief Reads the current GPIO pin pad status. +* +* @param base GPIO base pointer. +* @param pin GPIO port pin number. +* @retval GPIO pin pad status value. +*/ +static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin) { assert(pin < 32); return (uint8_t)(((base->PSR) >> pin) & 0x1U); } - /*! - * @brief Reads the current GPIO pin pad status. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinReadPadStatus. - */ -static inline uint8_t GPIO_ReadPadStatus(GPIO_Type* base, uint32_t pin) +/*! +* @brief Reads the current GPIO pin pad status. +* @deprecated Do not use this function. It has been superceded by @ref GPIO_PinReadPadStatus. +*/ +static inline uint8_t GPIO_ReadPadStatus(GPIO_Type *base, uint32_t pin) { return GPIO_PinReadPadStatus(base, pin); } + /*@}*/ /*! @@ -230,13 +257,13 @@ static inline uint8_t GPIO_ReadPadStatus(GPIO_Type* base, uint32_t pin) * @param pininterruptMode pointer to a @ref gpio_interrupt_mode_t structure * that contains the interrupt mode information. */ -void GPIO_PinSetInterruptConfig(GPIO_Type* base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode); +void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode); /*! * @brief Sets the current pin interrupt mode. * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinSetInterruptConfig. */ -static inline void GPIO_SetPinInterruptConfig(GPIO_Type* base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) +static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) { GPIO_PinSetInterruptConfig(base, pin, pinInterruptMode); } @@ -247,7 +274,7 @@ static inline void GPIO_SetPinInterruptConfig(GPIO_Type* base, uint32_t pin, gpi * @param base GPIO base pointer. * @param mask GPIO pin number macro. */ -static inline void GPIO_PortEnableInterrupts(GPIO_Type* base, uint32_t mask) +static inline void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t mask) { base->IMR |= mask; } @@ -258,7 +285,7 @@ static inline void GPIO_PortEnableInterrupts(GPIO_Type* base, uint32_t mask) * @param base GPIO base pointer. * @param mask GPIO pin number macro. */ -static inline void GPIO_EnableInterrupts(GPIO_Type* base, uint32_t mask) +static inline void GPIO_EnableInterrupts(GPIO_Type *base, uint32_t mask) { GPIO_PortEnableInterrupts(base, mask); } @@ -269,7 +296,7 @@ static inline void GPIO_EnableInterrupts(GPIO_Type* base, uint32_t mask) * @param base GPIO base pointer. * @param mask GPIO pin number macro. */ -static inline void GPIO_PortDisableInterrupts(GPIO_Type* base, uint32_t mask) +static inline void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t mask) { base->IMR &= ~mask; } @@ -278,7 +305,7 @@ static inline void GPIO_PortDisableInterrupts(GPIO_Type* base, uint32_t mask) * @brief Disables the specific pin interrupt. * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortDisableInterrupts. */ -static inline void GPIO_DisableInterrupts(GPIO_Type* base, uint32_t mask) +static inline void GPIO_DisableInterrupts(GPIO_Type *base, uint32_t mask) { GPIO_PortDisableInterrupts(base, mask); } @@ -289,7 +316,7 @@ static inline void GPIO_DisableInterrupts(GPIO_Type* base, uint32_t mask) * @param base GPIO base pointer. * @retval current pin interrupt status flag. */ -static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type* base) +static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base) { return base->ISR; } @@ -300,7 +327,7 @@ static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type* base) * @param base GPIO base pointer. * @retval current pin interrupt status flag. */ -static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type* base) +static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) { return GPIO_PortGetInterruptFlags(base); } @@ -312,7 +339,7 @@ static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type* base) * @param base GPIO base pointer. * @param mask GPIO pin number macro. */ -static inline void GPIO_PortClearInterruptFlags(GPIO_Type* base, uint32_t mask) +static inline void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask) { base->ISR = mask; } @@ -324,7 +351,7 @@ static inline void GPIO_PortClearInterruptFlags(GPIO_Type* base, uint32_t mask) * @param base GPIO base pointer. * @param mask GPIO pin number macro. */ -static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type* base, uint32_t mask) +static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) { GPIO_PortClearInterruptFlags(base, mask); } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpt.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpt.c index 2857a80276..39b0e89fb5 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpt.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpt.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,6 +34,12 @@ #include "fsl_gpt.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gpt" +#endif + + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpt.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpt.h index 9ad873ad7a..1cea054557 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpt.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpt.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_iomuxc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_iomuxc.h index ff5f9d9dd7..2a7dabb802 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_iomuxc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_iomuxc.h @@ -1,31 +1,37 @@ /* - * Copyright (c) 2016, Freescale Semiconductor, Inc. + * The Clear BSD License + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _FSL_IOMUXC_H_ @@ -43,6 +49,10 @@ /******************************************************************************* * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif /*! @name Driver version */ /*@{*/ @@ -54,7 +64,7 @@ /*@{*/ /*! @brief The pin function ID is a tuple of */ #define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U -#define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0, 0, 0x400A8018U +#define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U #define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU #define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU @@ -74,7 +84,6 @@ #define IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 0x401F8014U, 0x3U, 0x401F860CU, 0x0U, 0x401F8204U #define IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 0x401F8014U, 0x4U, 0, 0, 0x401F8204U #define IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x401F8014U, 0x5U, 0, 0, 0x401F8204U -#define IOMUXC_GPIO_EMC_00_JTAG_DONE 0x401F8014U, 0x7U, 0, 0, 0x401F8204U #define IOMUXC_GPIO_EMC_01_SEMC_DATA01 0x401F8018U, 0x0U, 0, 0, 0x401F8208U #define IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00 0x401F8018U, 0x1U, 0, 0, 0x401F8208U @@ -82,7 +91,6 @@ #define IOMUXC_GPIO_EMC_01_XBAR1_IN03 0x401F8018U, 0x3U, 0x401F8610U, 0x0U, 0x401F8208U #define IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 0x401F8018U, 0x4U, 0, 0, 0x401F8208U #define IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x401F8018U, 0x5U, 0, 0, 0x401F8208U -#define IOMUXC_GPIO_EMC_01_JTAG_DE_B 0x401F8018U, 0x7U, 0, 0, 0x401F8208U #define IOMUXC_GPIO_EMC_02_SEMC_DATA02 0x401F801CU, 0x0U, 0, 0, 0x401F820CU #define IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01 0x401F801CU, 0x1U, 0x401F8498U, 0x0U, 0x401F820CU @@ -90,7 +98,6 @@ #define IOMUXC_GPIO_EMC_02_XBAR1_INOUT04 0x401F801CU, 0x3U, 0x401F8614U, 0x0U, 0x401F820CU #define IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 0x401F801CU, 0x4U, 0, 0, 0x401F820CU #define IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x401F801CU, 0x5U, 0, 0, 0x401F820CU -#define IOMUXC_GPIO_EMC_02_JTAG_FAIL 0x401F801CU, 0x7U, 0, 0, 0x401F820CU #define IOMUXC_GPIO_EMC_03_SEMC_DATA03 0x401F8020U, 0x0U, 0, 0, 0x401F8210U #define IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01 0x401F8020U, 0x1U, 0, 0, 0x401F8210U @@ -98,7 +105,6 @@ #define IOMUXC_GPIO_EMC_03_XBAR1_INOUT05 0x401F8020U, 0x3U, 0x401F8618U, 0x0U, 0x401F8210U #define IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 0x401F8020U, 0x4U, 0, 0, 0x401F8210U #define IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x401F8020U, 0x5U, 0, 0, 0x401F8210U -#define IOMUXC_GPIO_EMC_03_JTAG_ACTIVE 0x401F8020U, 0x7U, 0, 0, 0x401F8210U #define IOMUXC_GPIO_EMC_04_SEMC_DATA04 0x401F8024U, 0x0U, 0, 0, 0x401F8214U #define IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02 0x401F8024U, 0x1U, 0x401F849CU, 0x0U, 0x401F8214U @@ -490,6 +496,7 @@ #define IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02 0x401F80ECU, 0x4U, 0, 0, 0x401F82DCU #define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F82DCU #define IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x401F80ECU, 0x6U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_NMI_GLUE_NMI 0x401F80ECU, 0x7U, 0x401F8568U, 0x0U, 0x401F82DCU #define IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x401F80F0U, 0x0U, 0x401F84E8U, 0x1U, 0x401F82E0U #define IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x401F80F0U, 0x1U, 0, 0, 0x401F82E0U @@ -696,6 +703,7 @@ #define IOMUXC_GPIO_B0_04_LCD_DATA00 0x401F814CU, 0x0U, 0, 0, 0x401F833CU #define IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 0x401F814CU, 0x1U, 0x401F8570U, 0x1U, 0x401F833CU #define IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x401F814CU, 0x2U, 0x401F84D4U, 0x1U, 0x401F833CU +#define IOMUXC_GPIO_B0_04_ARM_CM7_TRACE00 0x401F814CU, 0x3U, 0, 0, 0x401F833CU #define IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 0x401F814CU, 0x4U, 0, 0, 0x401F833CU #define IOMUXC_GPIO_B0_04_GPIO2_IO04 0x401F814CU, 0x5U, 0, 0, 0x401F833CU #define IOMUXC_GPIO_B0_04_SRC_BOOT_CFG00 0x401F814CU, 0x6U, 0, 0, 0x401F833CU @@ -703,6 +711,7 @@ #define IOMUXC_GPIO_B0_05_LCD_DATA01 0x401F8150U, 0x0U, 0, 0, 0x401F8340U #define IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 0x401F8150U, 0x1U, 0x401F8574U, 0x1U, 0x401F8340U #define IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x401F8150U, 0x2U, 0x401F84D8U, 0x1U, 0x401F8340U +#define IOMUXC_GPIO_B0_05_ARM_CM7_TRACE01 0x401F8150U, 0x3U, 0, 0, 0x401F8340U #define IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 0x401F8150U, 0x4U, 0, 0, 0x401F8340U #define IOMUXC_GPIO_B0_05_GPIO2_IO05 0x401F8150U, 0x5U, 0, 0, 0x401F8340U #define IOMUXC_GPIO_B0_05_SRC_BOOT_CFG01 0x401F8150U, 0x6U, 0, 0, 0x401F8340U @@ -710,6 +719,7 @@ #define IOMUXC_GPIO_B0_06_LCD_DATA02 0x401F8154U, 0x0U, 0, 0, 0x401F8344U #define IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 0x401F8154U, 0x1U, 0x401F857CU, 0x2U, 0x401F8344U #define IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA00 0x401F8154U, 0x2U, 0x401F8478U, 0x1U, 0x401F8344U +#define IOMUXC_GPIO_B0_06_ARM_CM7_TRACE02 0x401F8154U, 0x3U, 0, 0, 0x401F8344U #define IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 0x401F8154U, 0x4U, 0, 0, 0x401F8344U #define IOMUXC_GPIO_B0_06_GPIO2_IO06 0x401F8154U, 0x5U, 0, 0, 0x401F8344U #define IOMUXC_GPIO_B0_06_SRC_BOOT_CFG02 0x401F8154U, 0x6U, 0, 0, 0x401F8344U @@ -717,6 +727,7 @@ #define IOMUXC_GPIO_B0_07_LCD_DATA03 0x401F8158U, 0x0U, 0, 0, 0x401F8348U #define IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 0x401F8158U, 0x1U, 0x401F8580U, 0x2U, 0x401F8348U #define IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB00 0x401F8158U, 0x2U, 0x401F8488U, 0x1U, 0x401F8348U +#define IOMUXC_GPIO_B0_07_ARM_CM7_TRACE03 0x401F8158U, 0x3U, 0, 0, 0x401F8348U #define IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 0x401F8158U, 0x4U, 0, 0, 0x401F8348U #define IOMUXC_GPIO_B0_07_GPIO2_IO07 0x401F8158U, 0x5U, 0, 0, 0x401F8348U #define IOMUXC_GPIO_B0_07_SRC_BOOT_CFG03 0x401F8158U, 0x6U, 0, 0, 0x401F8348U @@ -755,6 +766,7 @@ #define IOMUXC_GPIO_B0_12_LCD_DATA08 0x401F816CU, 0x0U, 0, 0, 0x401F835CU #define IOMUXC_GPIO_B0_12_XBAR1_INOUT10 0x401F816CU, 0x1U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_ARM_CM7_TRACE_CLK 0x401F816CU, 0x2U, 0, 0, 0x401F835CU #define IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x401F816CU, 0x3U, 0x401F85A0U, 0x1U, 0x401F835CU #define IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 0x401F816CU, 0x4U, 0, 0, 0x401F835CU #define IOMUXC_GPIO_B0_12_GPIO2_IO12 0x401F816CU, 0x5U, 0, 0, 0x401F835CU @@ -762,6 +774,7 @@ #define IOMUXC_GPIO_B0_13_LCD_DATA09 0x401F8170U, 0x0U, 0, 0, 0x401F8360U #define IOMUXC_GPIO_B0_13_XBAR1_INOUT11 0x401F8170U, 0x1U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_ARM_CM7_TRACE_SWO 0x401F8170U, 0x2U, 0, 0, 0x401F8360U #define IOMUXC_GPIO_B0_13_SAI1_MCLK 0x401F8170U, 0x3U, 0x401F858CU, 0x2U, 0x401F8360U #define IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 0x401F8170U, 0x4U, 0, 0, 0x401F8360U #define IOMUXC_GPIO_B0_13_GPIO2_IO13 0x401F8170U, 0x5U, 0, 0, 0x401F8360U @@ -821,7 +834,6 @@ #define IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x401F818CU, 0x3U, 0x401F8434U, 0x1U, 0x401F837CU #define IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 0x401F818CU, 0x4U, 0, 0, 0x401F837CU #define IOMUXC_GPIO_B1_04_GPIO2_IO20 0x401F818CU, 0x5U, 0, 0, 0x401F837CU -#define IOMUXC_GPIO_B1_04_CSU_CSU_ALARM_AUT02 0x401F818CU, 0x6U, 0, 0, 0x401F837CU #define IOMUXC_GPIO_B1_05_LCD_DATA17 0x401F8190U, 0x0U, 0, 0, 0x401F8380U #define IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x401F8190U, 0x1U, 0x401F8524U, 0x1U, 0x401F8380U @@ -829,7 +841,6 @@ #define IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x401F8190U, 0x3U, 0x401F8438U, 0x1U, 0x401F8380U #define IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 0x401F8190U, 0x4U, 0, 0, 0x401F8380U #define IOMUXC_GPIO_B1_05_GPIO2_IO21 0x401F8190U, 0x5U, 0, 0, 0x401F8380U -#define IOMUXC_GPIO_B1_05_CSU_CSU_ALARM_AUT01 0x401F8190U, 0x6U, 0, 0, 0x401F8380U #define IOMUXC_GPIO_B1_06_LCD_DATA18 0x401F8194U, 0x0U, 0, 0, 0x401F8384U #define IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x401F8194U, 0x1U, 0x401F8528U, 0x1U, 0x401F8384U @@ -837,7 +848,6 @@ #define IOMUXC_GPIO_B1_06_ENET_RX_EN 0x401F8194U, 0x3U, 0x401F843CU, 0x1U, 0x401F8384U #define IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 0x401F8194U, 0x4U, 0, 0, 0x401F8384U #define IOMUXC_GPIO_B1_06_GPIO2_IO22 0x401F8194U, 0x5U, 0, 0, 0x401F8384U -#define IOMUXC_GPIO_B1_06_CSU_CSU_ALARM_AUT00 0x401F8194U, 0x6U, 0, 0, 0x401F8384U #define IOMUXC_GPIO_B1_07_LCD_DATA19 0x401F8198U, 0x0U, 0, 0, 0x401F8388U #define IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x401F8198U, 0x1U, 0x401F8520U, 0x1U, 0x401F8388U @@ -845,7 +855,6 @@ #define IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x401F8198U, 0x3U, 0, 0, 0x401F8388U #define IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 0x401F8198U, 0x4U, 0, 0, 0x401F8388U #define IOMUXC_GPIO_B1_07_GPIO2_IO23 0x401F8198U, 0x5U, 0, 0, 0x401F8388U -#define IOMUXC_GPIO_B1_07_CSU_CSU_INT_DEB 0x401F8198U, 0x6U, 0, 0, 0x401F8388U #define IOMUXC_GPIO_B1_08_LCD_DATA20 0x401F819CU, 0x0U, 0, 0, 0x401F838CU #define IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 0x401F819CU, 0x1U, 0, 0, 0x401F838CU @@ -969,7 +978,6 @@ #define IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x401F81D8U, 0x3U, 0x401F859CU, 0x0U, 0x401F83C8U #define IOMUXC_GPIO_SD_B1_01_LPUART4_RX 0x401F81D8U, 0x4U, 0x401F8540U, 0x0U, 0x401F83C8U #define IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x401F81D8U, 0x5U, 0, 0, 0x401F83C8U -#define IOMUXC_GPIO_SD_B1_01_CCM_DI0_EXT_CLK 0x401F81D8U, 0x6U, 0, 0, 0x401F83C8U #define IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x401F81DCU, 0x0U, 0x401F85ECU, 0x0U, 0x401F83CCU #define IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01 0x401F81DCU, 0x1U, 0x401F84BCU, 0x0U, 0x401F83CCU @@ -1015,7 +1023,6 @@ #define IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x401F81F0U, 0x3U, 0, 0, 0x401F83E0U #define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F81F0U, 0x4U, 0x401F8500U, 0x0U, 0x401F83E0U #define IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x401F81F0U, 0x5U, 0, 0, 0x401F83E0U -#define IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x401F81F0U, 0x6U, 0, 0, 0x401F83E0U #define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x401F81F4U, 0x0U, 0x401F85F8U, 0x0U, 0x401F83E4U #define IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00 0x401F81F4U, 0x1U, 0x401F84A8U, 0x0U, 0x401F83E4U @@ -1038,7 +1045,6 @@ #define IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x401F81FCU, 0x3U, 0x401F84D8U, 0x0U, 0x401F83ECU #define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F81FCU, 0x4U, 0, 0, 0x401F83ECU #define IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x401F81FCU, 0x5U, 0, 0, 0x401F83ECU -#define IOMUXC_GPIO_SD_B1_10_SRC_SYSTEM_RESET 0x401F81FCU, 0x6U, 0, 0, 0x401F83ECU #define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x401F8200U, 0x0U, 0x401F8604U, 0x0U, 0x401F83F0U #define IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03 0x401F8200U, 0x1U, 0x401F84B4U, 0x0U, 0x401F83F0U @@ -1046,7 +1052,6 @@ #define IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x401F8200U, 0x3U, 0x401F84D4U, 0x0U, 0x401F83F0U #define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8200U, 0x4U, 0, 0, 0x401F83F0U #define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x401F8200U, 0x5U, 0, 0, 0x401F83F0U -#define IOMUXC_GPIO_SD_B1_11_SRC_EARLY_RESET 0x401F8200U, 0x6U, 0, 0, 0x401F83F0U #define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U) #define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U) @@ -1164,11 +1169,15 @@ static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, */ static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable) { - uint32_t gpr = base->GPR1 & 0xFFF; + mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK + | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK + | IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK + | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK + | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK); if (enable) { - base->GPR1 = mode | gpr; + base->GPR1 |= mode; } else { diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_kpp.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_kpp.c index cafd2786ac..f83fd25705 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_kpp.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_kpp.c @@ -1,8 +1,11 @@ /* + * The Clear BSD License * Copyright 2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -15,6 +18,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -32,6 +36,12 @@ /******************************************************************************* * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.kpp" +#endif + #define KPP_KEYPAD_SCAN_TIMES (3U) /******************************************************************************* * Prototypes diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_kpp.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_kpp.h index e7be068903..46eb3aab57 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_kpp.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_kpp.h @@ -1,8 +1,11 @@ /* + * The Clear BSD License * Copyright 2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -15,6 +18,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c.c index 0be94ff9c5..7ce2c37213 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -36,6 +40,11 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpi2c" +#endif + /*! @brief Common sets of flags used by the driver. */ enum _lpi2c_flag_constants { @@ -115,14 +124,8 @@ static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz, uint32_t maxCycles, uint32_t prescaler); -/* Not static so it can be used from fsl_lpi2c_edma.c. */ -status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status); - static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base); -/* Not static so it can be used from fsl_lpi2c_edma.c. */ -status_t LPI2C_CheckForBusyBus(LPI2C_Type *base); - static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone); static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle); @@ -156,13 +159,13 @@ static const clock_ip_name_t kLpi2cPeriphClocks[] = LPI2C_PERIPH_CLOCKS; static lpi2c_master_isr_t s_lpi2cMasterIsr; /*! @brief Pointers to master handles for each instance. */ -static lpi2c_master_handle_t *s_lpi2cMasterHandle[FSL_FEATURE_SOC_LPI2C_COUNT]; +static lpi2c_master_handle_t *s_lpi2cMasterHandle[ARRAY_SIZE(kLpi2cBases)]; /*! @brief Pointer to slave IRQ handler for each instance. */ static lpi2c_slave_isr_t s_lpi2cSlaveIsr; /*! @brief Pointers to slave handles for each instance. */ -static lpi2c_slave_handle_t *s_lpi2cSlaveHandle[FSL_FEATURE_SOC_LPI2C_COUNT]; +static lpi2c_slave_handle_t *s_lpi2cSlaveHandle[ARRAY_SIZE(kLpi2cBases)]; /******************************************************************************* * Code @@ -204,6 +207,9 @@ static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz, uint32_t maxCycles, uint32_t prescaler) { + assert(sourceClock_Hz > 0); + assert(prescaler > 0); + uint32_t busCycle_ns = 1000000 / (sourceClock_Hz / prescaler / 1000); uint32_t cycles = 0; @@ -692,7 +698,7 @@ status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize) status_t LPI2C_MasterSend(LPI2C_Type *base, const void *txBuff, size_t txSize) { - uint8_t *buf = (uint8_t *)((void *)txBuff); + const uint8_t *buf = (const uint8_t *)((const void *)txBuff); assert(txBuff); @@ -834,6 +840,10 @@ void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, /* Clear internal IRQ enables and enable NVIC IRQ. */ LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. + In some cases the LPI2C IRQ is configured through INTMUX, user needs to enable + INTMUX IRQ in application code. */ EnableIRQ(kLpi2cIrqs[instance]); } @@ -1352,7 +1362,7 @@ static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags) status_t LPI2C_SlaveSend(LPI2C_Type *base, const void *txBuff, size_t txSize, size_t *actualTxSize) { - uint8_t *buf = (uint8_t *)((void *)txBuff); + const uint8_t *buf = (const uint8_t *)((const void *)txBuff); size_t remaining = txSize; assert(txBuff); @@ -1804,6 +1814,14 @@ void LPI2C3_DriverIRQHandler(void) } #endif +#if defined(LPI2C4) +/* Implementation of LPI2C4 handler named in startup code. */ +void LPI2C4_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C4, 4); +} +#endif + #if defined(CM4_0__LPI2C) /* Implementation of CM4_0__LPI2C handler named in startup code. */ void M4_0_LPI2C_DriverIRQHandler(void) @@ -1812,6 +1830,14 @@ void M4_0_LPI2C_DriverIRQHandler(void) } #endif +#if defined(CM4__LPI2C) +/* Implementation of CM4__LPI2C handler named in startup code. */ +void M4_LPI2C_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(CM4__LPI2C, LPI2C_GetInstance(CM4__LPI2C)); +} +#endif + #if defined(CM4_1__LPI2C) /* Implementation of CM4_1__LPI2C handler named in startup code. */ void M4_1_LPI2C_DriverIRQHandler(void) @@ -1859,3 +1885,43 @@ void DMA_I2C4_INT_DriverIRQHandler(void) LPI2C_CommonIRQHandler(DMA__LPI2C4, LPI2C_GetInstance(DMA__LPI2C4)); } #endif + +#if defined(ADMA__LPI2C0) +/* Implementation of DMA__LPI2C0 handler named in startup code. */ +void ADMA_I2C0_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C0, LPI2C_GetInstance(ADMA__LPI2C0)); +} +#endif + +#if defined(ADMA__LPI2C1) +/* Implementation of DMA__LPI2C1 handler named in startup code. */ +void ADMA_I2C1_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C1, LPI2C_GetInstance(ADMA__LPI2C1)); +} +#endif + +#if defined(ADMA__LPI2C2) +/* Implementation of DMA__LPI2C2 handler named in startup code. */ +void ADMA_I2C2_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C2, LPI2C_GetInstance(ADMA__LPI2C2)); +} +#endif + +#if defined(ADMA__LPI2C3) +/* Implementation of DMA__LPI2C3 handler named in startup code. */ +void ADMA_I2C3_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C3, LPI2C_GetInstance(ADMA__LPI2C3)); +} +#endif + +#if defined(ADMA__LPI2C4) +/* Implementation of DMA__LPI2C3 handler named in startup code. */ +void ADMA_I2C4_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C4, LPI2C_GetInstance(ADMA__LPI2C4)); +} +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c.h index 6ffdb1b6fb..1706a548ef 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -45,8 +49,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPI2C driver version 2.1.3. */ -#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) +/*! @brief LPI2C driver version 2.1.5. */ +#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) /*@}*/ /*! @brief Timeout times for waiting flag. */ @@ -498,6 +502,12 @@ void LPI2C_MasterDeinit(LPI2C_Type *base); */ void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config); +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status); + +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_CheckForBusyBus(LPI2C_Type *base); + /*! * @brief Performs a software reset. * @@ -708,6 +718,10 @@ static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, * The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud * rate. Do not call this function during a transfer, or the transfer is aborted. * + * @note Please note that the second parameter is the clock frequency of LPI2C module, the third + * parameter means user configured bus baudrate, this implementation is different from other I2C drivers + * which use baudrate configuration as second parameter and source clock frequency as third parameter. + * * @param base The LPI2C peripheral base address. * @param sourceClock_Hz LPI2C functional clock frequency in Hertz. * @param baudRate_Hz Requested bus frequency in Hertz. @@ -844,6 +858,11 @@ status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t * is created, there is not a corresponding destroy handle. If the user wants to * terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called. * + * + * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * * @param base The LPI2C peripheral base address. * @param[out] handle Pointer to the LPI2C master driver handle. * @param callback User provided pointer to the asynchronous callback function. @@ -935,7 +954,7 @@ void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *hand * slaveConfig->sclStall.enableAddress = true; * slaveConfig->ignoreAck = false; * slaveConfig->enableReceivedAddressRead = false; - * slaveConfig->sdaGlitchFilterWidth_ns = 0; // TODO determine default width values + * slaveConfig->sdaGlitchFilterWidth_ns = 0; * slaveConfig->sclGlitchFilterWidth_ns = 0; * slaveConfig->dataValidDelay_ns = 0; * slaveConfig->clockHoldTime_ns = 0; @@ -1188,6 +1207,10 @@ status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_ * is created, there is not a corresponding destroy handle. If the user wants to * terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called. * + * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * @param base The LPI2C peripheral base address. * @param[out] handle Pointer to the LPI2C slave driver handle. * @param callback User provided pointer to the asynchronous callback function. diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c_edma.c index 70776923a0..b79dea63a1 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c_edma.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c_edma.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -36,6 +40,11 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpi2c_edma" +#endif + /* @brief Mask to align an address to 32 bytes. */ #define ALIGN_32_MASK (0x1fU) @@ -96,12 +105,6 @@ typedef void (*lpi2c_isr_t)(LPI2C_Type *base, void *handle); * Prototypes ******************************************************************************/ -/* Defined in fsl_lpi2c.c. */ -extern status_t LPI2C_CheckForBusyBus(LPI2C_Type *base); - -/* Defined in fsl_lpi2c.c. */ -extern status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status); - static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle); static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds); @@ -446,7 +449,15 @@ status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handl static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds) { lpi2c_master_edma_handle_t *handle = (lpi2c_master_edma_handle_t *)userData; - bool hasReceiveData = (handle->transfer.direction == kLPI2C_Read) && (handle->transfer.dataSize); + bool hasReceiveData; + + if (!handle) + { + return; + } + + hasReceiveData = (handle->transfer.direction == kLPI2C_Read) && (handle->transfer.dataSize); + if (hasReceiveData && !FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) { if (EDMA_GetNextTCDAddress(handle->tx) != 0) @@ -455,11 +466,6 @@ static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, b } } - if (!handle) - { - return; - } - /* Check for errors. */ status_t result = LPI2C_MasterCheckAndClearError(handle->base, LPI2C_MasterGetStatusFlags(handle->base)); diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c_edma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c_edma.h index 5283560a38..b66edbfd4b 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c_edma.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c_edma.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -37,6 +41,12 @@ * Definitions ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief LPI2C EDMA driver version 2.1.5. */ +#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) +/*@}*/ + /*! * @addtogroup lpi2c_master_edma_driver * @{ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.c index 8e4dc99f35..3a515e1739 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -33,6 +37,12 @@ /******************************************************************************* * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpspi" +#endif + /*! * @brief Default watermark values. * @@ -53,12 +63,6 @@ typedef void (*lpspi_slave_isr_t)(LPSPI_Type *base, lpspi_slave_handle_t *handle /******************************************************************************* * Prototypes ******************************************************************************/ -/*! -* @brief Get instance number for LPSPI module. -* -* @param base LPSPI peripheral base address. -*/ -uint32_t LPSPI_GetInstance(LPSPI_Type *base); /*! * @brief Configures the LPSPI peripheral chip select polarity. @@ -114,12 +118,6 @@ static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle */ static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle); -/*! -* @brief Check the argument for transfer . -* This is not a public API. Not static because lpspi_edma.c will use this API. -*/ -bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame); - /*! * @brief LPSPI common interrupt handler. * @@ -158,7 +156,7 @@ static lpspi_master_isr_t s_lpspiMasterIsr; /*! @brief Pointer to slave IRQ handler for each instance. */ static lpspi_slave_isr_t s_lpspiSlaveIsr; /* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ -volatile uint8_t s_dummyData[ARRAY_SIZE(s_lpspiBases)] = {0}; +volatile uint8_t g_lpspiDummyData[ARRAY_SIZE(s_lpspiBases)] = {0}; /********************************************************************************************************************** * Code *********************************************************************************************************************/ @@ -183,7 +181,7 @@ uint32_t LPSPI_GetInstance(LPSPI_Type *base) void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData) { uint32_t instance = LPSPI_GetInstance(base); - s_dummyData[instance] = dummyData; + g_lpspiDummyData[instance] = dummyData; } void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz) @@ -634,7 +632,7 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; uint32_t temp = 0U; - uint8_t dummyData = s_dummyData[LPSPI_GetInstance(base)]; + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) { @@ -799,7 +797,7 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; uint32_t temp = 0U; - uint8_t dummyData = s_dummyData[LPSPI_GetInstance(base)]; + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) { @@ -1820,3 +1818,34 @@ void DMA_SPI3_INT_DriverIRQHandler(void) LPSPI_CommonIRQHandler(DMA__LPSPI3, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI3)]); } #endif + +#if defined(ADMA__LPSPI0) +void ADMA_SPI0_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)]); + LPSPI_CommonIRQHandler(ADMA__LPSPI0, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)]); +} +#endif + +#if defined(ADMA__LPSPI1) +void ADMA_SPI1_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)]); + LPSPI_CommonIRQHandler(ADMA__LPSPI1, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)]); +} +#endif +#if defined(ADMA__LPSPI2) +void ADMA_SPI2_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)]); + LPSPI_CommonIRQHandler(ADMA__LPSPI2, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)]); +} +#endif + +#if defined(ADMA__LPSPI3) +void ADMA_SPI3_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)]); + LPSPI_CommonIRQHandler(ADMA__LPSPI3, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)]); +} +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.h index e29f192824..72895a225b 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -52,6 +56,9 @@ #define LPSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for tx if there is not txData. */ #endif +/*! @brief Global variable for dummy data value setting. */ +extern volatile uint8_t g_lpspiDummyData[]; + /*! @brief Status for the LPSPI driver.*/ enum _lpspi_status { @@ -223,17 +230,17 @@ enum _lpspi_transfer_config_flag_for_master kLPSPI_MasterByteSwap = 1U << 22 /*!< Is master swap the byte. - * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set - * lpspi_shift_direction_t to MSB). - * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used - * or not, the waveform is 1 2 3 4 5 6 7 8. - * 2. If you set bitPerFrame = 16 : - * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. - * 3. If you set bitPerFrame = 32 : - * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. - */ + * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set + * lpspi_shift_direction_t to MSB). + * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used + * or not, the waveform is 1 2 3 4 5 6 7 8. + * 2. If you set bitPerFrame = 16 : + * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. + * 3. If you set bitPerFrame = 32 : + * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. + */ }; #define LPSPI_SLAVE_PCS_SHIFT (4U) /*!< LPSPI slave PCS shift macro , internal used. */ @@ -249,17 +256,17 @@ enum _lpspi_transfer_config_flag_for_slave kLPSPI_SlaveByteSwap = 1U << 22 /*!< Is slave swap the byte. - * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set - * lpspi_shift_direction_t to MSB). - * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used - * or not, the waveform is 1 2 3 4 5 6 7 8. - * 2. If you set bitPerFrame = 16 : - * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. - * 3. If you set bitPerFrame = 32 : - * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. - */ + * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set + * lpspi_shift_direction_t to MSB). + * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used + * or not, the waveform is 1 2 3 4 5 6 7 8. + * 2. If you set bitPerFrame = 16 : + * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. + * 3. If you set bitPerFrame = 32 : + * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. + */ }; /*! @brief LPSPI transfer state, which is used for LPSPI transactional API state machine. */ @@ -376,16 +383,16 @@ struct _lpspi_master_handle volatile uint8_t rxWatermark; /*!< Rx watermark. */ - volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR . */ - volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR . */ + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ uint8_t *volatile txData; /*!< Send buffer. */ uint8_t *volatile rxData; /*!< Receive buffer. */ volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ - volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times . */ - volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times . */ + volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ + volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ uint32_t totalByteCount; /*!< Number of transfer bytes*/ @@ -406,8 +413,8 @@ struct _lpspi_slave_handle volatile uint8_t rxWatermark; /*!< Rx watermark. */ - volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR . */ - volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR . */ + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ uint8_t *volatile txData; /*!< Send buffer. */ uint8_t *volatile rxData; /*!< Receive buffer. */ @@ -415,8 +422,8 @@ struct _lpspi_slave_handle volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ - volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times . */ - volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times . */ + volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ + volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ uint32_t totalByteCount; /*!< Number of transfer bytes*/ @@ -718,6 +725,24 @@ static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base) * @{ */ +/*! +* @brief Get instance number for LPSPI module. +* +* @param base LPSPI peripheral base address. +* @return Return the value of LPSPI instance. +*/ +uint32_t LPSPI_GetInstance(LPSPI_Type *base); + +/*! +* @brief Check the argument for transfer . +* +* @param transfer the transfer struct to be used. +* @param bitPerFrame The bit size of one frame. +* @param bytePerFrame The byte size of one frame. +* @return Return true for right and false for wrong. +*/ +bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame); + /*! * @brief Configures the LPSPI for either master or slave. * @@ -797,12 +822,12 @@ static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask) * size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not * divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported. * - * Note 1 : The transmit command register should be initialized before enabling the LPSPI in slave mode, although + * Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although * the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command * register * should only be changed if the LPSPI is idle. * - * Note 2 : The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That + * Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That * means the TCR register should be written to when the Tx FIFO is not full. * * @param base LPSPI peripheral address. diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi_edma.c index 48f01b1851..cbc7af7e76 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi_edma.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi_edma.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -31,8 +35,14 @@ #include "fsl_lpspi_edma.h" /*********************************************************************************************************************** -* Definitons +* Definitions ***********************************************************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpspi_edma" +#endif + /*! * @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private. */ @@ -71,18 +81,6 @@ static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, void *g_lpspiEdmaPrivateHandle, bool transferDone, uint32_t tcds); -/*! -* @brief Get instance number for LPSPI module. -* This is not a public API and it's extern from fsl_lpspi.c. -* @param base LPSPI peripheral base address -*/ -extern uint32_t LPSPI_GetInstance(LPSPI_Type *base); - -/*! -* @brief Check the argument for transfer . -* This is not a public API. It's extern from fsl_lpspi.c. -*/ -extern bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame); static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap); @@ -94,8 +92,6 @@ static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint3 static lpspi_master_edma_private_handle_t s_lpspiMasterEdmaPrivateHandle[FSL_FEATURE_SOC_LPSPI_COUNT]; static lpspi_slave_edma_private_handle_t s_lpspiSlaveEdmaPrivateHandle[FSL_FEATURE_SOC_LPSPI_COUNT]; -/*! @brief Global variable for dummy data value setting. */ -extern volatile uint8_t s_dummyData[]; /*********************************************************************************************************************** * Code ***********************************************************************************************************************/ @@ -225,7 +221,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * bool isThereExtraTxBytes = false; - uint8_t dummyData = s_dummyData[instance]; + uint8_t dummyData = g_lpspiDummyData[instance]; edma_transfer_config_t transferConfigRx; edma_transfer_config_t transferConfigTx; @@ -657,7 +653,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; uint32_t temp = 0U; - uint8_t dummyData = s_dummyData[LPSPI_GetInstance(base)]; + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) { diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi_edma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi_edma.h index cc0ffe8d5b..54b71bed43 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi_edma.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi_edma.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -41,6 +45,11 @@ /*********************************************************************************************************************** * Definitions **********************************************************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief LPSPI EDMA driver version 2.0.2. */ +#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ /*! * @brief Forward declaration of the _lpspi_master_edma_handle typedefs. @@ -88,10 +97,10 @@ struct _lpspi_master_edma_handle volatile uint8_t rxWatermark; /*!< Rx watermark. */ - volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR . */ - volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR . */ + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ - volatile uint8_t bytesLastRead; /*!< Bytes for last read RDR . */ + volatile uint8_t bytesLastRead; /*!< Bytes for last read RDR. */ volatile uint8_t isThereExtraRxBytes; /*!< Is there extra RX byte. */ uint8_t *volatile txData; /*!< Send buffer. */ @@ -119,7 +128,7 @@ struct _lpspi_master_edma_handle edma_handle_t *edmaRxRegToRxDataHandle; /*!CTRL; bool isSevenDataBits = - ((ctrl & LPUART_CTRL_M7_MASK) || - ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); + ((ctrl & LPUART_CTRL_M7_MASK) || ((!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); #endif /* The Non Blocking read data API assume user have ensured there is enough space in @@ -698,8 +699,7 @@ status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT uint32_t ctrl = base->CTRL; bool isSevenDataBits = - ((ctrl & LPUART_CTRL_M7_MASK) || - ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); + ((ctrl & LPUART_CTRL_M7_MASK) || ((!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); #endif while (length--) @@ -764,8 +764,7 @@ void LPUART_TransferCreateHandle(LPUART_Type *base, #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT uint32_t ctrl = base->CTRL; bool isSevenDataBits = - ((ctrl & LPUART_CTRL_M7_MASK) || - ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); + ((ctrl & LPUART_CTRL_M7_MASK) || ((!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); #endif /* Zero the handle. */ @@ -1651,8 +1650,20 @@ void M4_1_LPUART_DriverIRQHandler(void) } #endif +#if defined(CM4__LPUART) +void M4_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr(CM4__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4__LPUART)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + #if defined(DMA__LPUART0) -void DMA_UART0_INT_IRQHandler(void) +void DMA_UART0_INT_DriverIRQHandler(void) { s_lpuartIsr(DMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART0)]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping @@ -1664,7 +1675,7 @@ void DMA_UART0_INT_IRQHandler(void) #endif #if defined(DMA__LPUART1) -void DMA_UART1_INT_IRQHandler(void) +void DMA_UART1_INT_DriverIRQHandler(void) { s_lpuartIsr(DMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART1)]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping @@ -1676,7 +1687,7 @@ void DMA_UART1_INT_IRQHandler(void) #endif #if defined(DMA__LPUART2) -void DMA_UART2_INT_IRQHandler(void) +void DMA_UART2_INT_DriverIRQHandler(void) { s_lpuartIsr(DMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART2)]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping @@ -1688,7 +1699,7 @@ void DMA_UART2_INT_IRQHandler(void) #endif #if defined(DMA__LPUART3) -void DMA_UART3_INT_IRQHandler(void) +void DMA_UART3_INT_DriverIRQHandler(void) { s_lpuartIsr(DMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART3)]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping @@ -1700,7 +1711,7 @@ void DMA_UART3_INT_IRQHandler(void) #endif #if defined(DMA__LPUART4) -void DMA_UART4_INT_IRQHandler(void) +void DMA_UART4_INT_DriverIRQHandler(void) { s_lpuartIsr(DMA__LPUART4, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART4)]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping @@ -1710,3 +1721,51 @@ void DMA_UART4_INT_IRQHandler(void) #endif } #endif + +#if defined(ADMA__LPUART0) +void ADMA_UART0_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(ADMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART0)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__LPUART1) +void ADMA_UART1_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(ADMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART1)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__LPUART2) +void ADMA_UART2_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(ADMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART2)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__LPUART3) +void ADMA_UART3_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(ADMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART3)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart.h index aa4528a753..395c27a68d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -548,6 +552,14 @@ static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable) * @{ */ +/*! + * @brief Get the LPUART instance from peripheral base address. + * + * @param base LPUART peripheral base address. + * @return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base); + /*! * @brief Enables or disables the LPUART transmitter. * diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart_edma.c index 19f33ffa72..add9488179 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart_edma.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart_edma.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -34,6 +38,11 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpuart_edma" +#endif + /*MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ + SAI_TxReset(base); + /* Configure audio protocol */ switch (config->protocol) { @@ -337,6 +348,10 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) default: break; } + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + SAI_TxSetFIFOErrorContinue(base, true); +#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ } void SAI_RxInit(I2S_Type *base, const sai_config_t *config) @@ -358,6 +373,8 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ + SAI_RxReset(base); + /* Configure audio protocol */ switch (config->protocol) { @@ -441,6 +458,10 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) default: break; } + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + SAI_RxSetFIFOErrorContinue(base, true); +#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ } void SAI_Deinit(I2S_Type *base) @@ -457,7 +478,7 @@ void SAI_TxGetDefaultConfig(sai_config_t *config) config->bclkSource = kSAI_BclkSourceMclkDiv; config->masterSlave = kSAI_Master; config->mclkSource = kSAI_MclkSourceSysclk; - config->protocol = kSAI_BusLeftJustified; + config->protocol = kSAI_BusI2S; config->syncMode = kSAI_ModeAsync; #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) config->mclkOutputEnable = true; @@ -469,7 +490,7 @@ void SAI_RxGetDefaultConfig(sai_config_t *config) config->bclkSource = kSAI_BclkSourceMclkDiv; config->masterSlave = kSAI_Master; config->mclkSource = kSAI_MclkSourceSysclk; - config->protocol = kSAI_BusLeftJustified; + config->protocol = kSAI_BusI2S; config->syncMode = kSAI_ModeSync; #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) config->mclkOutputEnable = true; @@ -583,6 +604,74 @@ void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask) base->RCR3 |= I2S_RCR3_RCE(mask); } +void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order) +{ + uint32_t val = (base->TCR4) & (~I2S_TCR4_MF_MASK); + + val |= I2S_TCR4_MF(order); + base->TCR4 = val; +} + +void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order) +{ + uint32_t val = (base->RCR4) & (~I2S_RCR4_MF_MASK); + + val |= I2S_RCR4_MF(order); + base->RCR4 = val; +} + +void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->TCR2) & (~I2S_TCR2_BCP_MASK); + + val |= I2S_TCR2_BCP(polarity); + base->TCR2 = val; +} + +void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->RCR2) & (~I2S_RCR2_BCP_MASK); + + val |= I2S_RCR2_BCP(polarity); + base->RCR2 = val; +} + +void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->TCR4) & (~I2S_TCR4_FSP_MASK); + + val |= I2S_TCR4_FSP(polarity); + base->TCR4 = val; +} + +void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->RCR4) & (~I2S_RCR4_FSP_MASK); + + val |= I2S_RCR4_FSP(polarity); + base->RCR4 = val; +} + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) +{ + uint32_t val = base->TCR4; + + val &= ~I2S_TCR4_FPACK_MASK; + val |= I2S_TCR4_FPACK(pack); + base->TCR4 = val; +} + +void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) +{ + uint32_t val = base->RCR4; + + val &= ~I2S_RCR4_FPACK_MASK; + val |= I2S_RCR4_FPACK(pack); + base->RCR4 = val; +} +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + void SAI_TxSetFormat(I2S_Type *base, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, @@ -633,7 +722,14 @@ void SAI_TxSetFormat(I2S_Type *base, } else { - base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(format->bitWidth - 1); + if (base->TCR4 & I2S_TCR4_MF_MASK) + { + base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(format->bitWidth - 1); + } + else + { + base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(0); + } } /* Set mono or stereo */ @@ -699,7 +795,14 @@ void SAI_RxSetFormat(I2S_Type *base, } else { - base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(format->bitWidth - 1); + if (base->RCR4 & I2S_RCR4_MF_MASK) + { + base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(format->bitWidth - 1); + } + else + { + base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(0); + } } /* Set mono or stereo */ @@ -1575,6 +1678,192 @@ void AUDIO_SAI7_INT_DriverIRQHandler(void) } #endif /* AUDIO__SAI7 */ +#if defined(ADMA__SAI0) +void ADMA_SAI0_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI0->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI0->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI0->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI0->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI0, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI0->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI0->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI0->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI0->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI0, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI0 */ + +#if defined(ADMA__SAI1) +void ADMA_SAI1_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI1->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI1->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI1->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI1->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI1, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI1->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI1->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI1->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI1->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI1, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI1 */ + +#if defined(ADMA__SAI2) +void ADMA_SAI2_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI2->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI2->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI2->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI2->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI2, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI2->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI2->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI2->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI2->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI2, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI2 */ + +#if defined(ADMA__SAI3) +void ADMA_SAI3_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI3->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI3->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI3->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI3->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI3, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI3->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI3->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI3->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI3->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI3, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI3 */ + +#if defined(ADMA__SAI4) +void ADMA_SAI4_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI4->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI4->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI4->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI4->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI4, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI4->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI4->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI4->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI4->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI4, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI4 */ + +#if defined(ADMA__SAI5) +void ADMA_SAI5_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI5->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI5->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI5->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI5->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI5, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI5->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI5->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI5->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI5->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI5, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI5 */ + #if defined(SAI0) void SAI0_DriverIRQHandler(void) { @@ -1697,6 +1986,28 @@ void SAI3_DriverIRQHandler(void) __DSB(); #endif } + +void SAI3_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][0]); + s_saiTxIsr(SAI3, s_saiHandle[3][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void SAI3_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][1]); + s_saiRxIsr(SAI3, s_saiHandle[3][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} #endif /* SAI3 */ #if defined(SAI4) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.h index 857e9c2212..82dd26bfa6 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -44,7 +48,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) /*!< Version 2.1.3 */ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4 */ /*@}*/ /*! @brief SAI return status*/ @@ -84,6 +88,20 @@ typedef enum _sai_mono_stereo kSAI_MonoLeft /*!< Only left channel have sound. */ } sai_mono_stereo_t; +/*! @brief SAI data order, MSB or LSB */ +typedef enum _sai_data_order +{ + kSAI_DataLSB = 0x0U, /*!< LSB bit transferred first */ + kSAI_DataMSB /*!< MSB bit transferred first */ +} sai_data_order_t; + +/*! @brief SAI clock polarity, active high or low */ +typedef enum _sai_clock_polarity +{ + kSAI_PolarityActiveHigh = 0x0U, /*!< Clock active high */ + kSAI_PolarityActiveLow /*!< Clock active low */ +} sai_clock_polarity_t; + /*! @brief Synchronous or asynchronous mode */ typedef enum _sai_sync_mode { @@ -281,7 +299,7 @@ extern "C" { void SAI_TxInit(I2S_Type *base, const sai_config_t *config); /*! - * @brief Initializes the the SAI Rx peripheral. + * @brief Initializes the SAI Rx peripheral. * * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. * The configuration structure can be custom filled or set with default values by @@ -473,6 +491,115 @@ void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask); */ void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask); +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order); + +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * @brief Set Tx FIFO packing feature. + * + * @param base SAI base pointer. + * @param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ +void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack); + +/*! +* @brief Set Rx FIFO packing feature. +* +* @param base SAI base pointer. +* @param pack FIFO pack type. It is element of sai_fifo_packing_t. +*/ +void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack); +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR +/*! +* @brief Set Tx FIFO error continue. +* +* FIFO error continue mode means SAI will keep running while FIFO error occured. If this feature +* not enabled, SAI will hang and users need to clear FEF flag in TCSR register. +* +* @param base SAI base pointer. +* @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. +*/ +static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) +{ + if (isEnabled) + { + base->TCR4 |= I2S_TCR4_FCONT_MASK; + } + else + { + base->TCR4 &= ~I2S_TCR4_FCONT_MASK; + } +} + +/*! +* @brief Set Rx FIFO error continue. +* +* FIFO error continue mode means SAI will keep running while FIFO error occured. If this feature +* not enabled, SAI will hang and users need to clear FEF flag in RCSR register. +* +* @param base SAI base pointer. +* @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. +*/ +static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) +{ + if (isEnabled) + { + base->RCR4 |= I2S_RCR4_FCONT_MASK; + } + else + { + base->RCR4 &= ~I2S_RCR4_FCONT_MASK; + } +} +#endif /*! @} */ /*! @@ -857,7 +984,7 @@ status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_ void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle); /*! - * @brief Aborts the the current IRQ receive. + * @brief Aborts the current IRQ receive. * * @note This API can be called when an interrupt non-blocking transfer initiates * to abort the transfer early. diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai_edma.c index 6f4dda6998..11bdae301b 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai_edma.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai_edma.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,11 +34,18 @@ #include "fsl_sai_edma.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sai_edma" +#endif + /******************************************************************************* * Definitations ******************************************************************************/ /* Used for 32byte aligned */ -#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)address + 32) & ~0x1FU) +#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + 32) & ~0x1FU) + +static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; /*tcd), SAI_XFER_QUEUE_SIZE); + EDMA_InstallTCDMemory(dmaHandle, (edma_tcd_t *)(STCD_ADDR(handle->tcd)), SAI_XFER_QUEUE_SIZE); /* Install callback for Tx dma channel */ EDMA_SetCallback(dmaHandle, SAI_TxEDMACallback, &s_edmaPrivateHandle[instance][0]); diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai_edma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai_edma.h index ef4f5c005a..0b806d246b 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai_edma.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai_edma.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -42,6 +46,11 @@ * Definitions ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4 */ +/*@}*/ + typedef struct _sai_edma_handle sai_edma_handle_t; /*! @brief SAI eDMA transfer callback function for finish and error */ @@ -50,19 +59,19 @@ typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, s /*! @brief SAI DMA transfer handle, users should not touch the content of the handle.*/ struct _sai_edma_handle { - edma_handle_t *dmaHandle; /*!< DMA handler for SAI send */ - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - uint8_t bytesPerFrame; /*!< Bytes in a frame */ - uint8_t channel; /*!< Which data channel */ - uint8_t count; /*!< The transfer data count in a DMA request */ - uint32_t state; /*!< Internal state for SAI eDMA transfer */ - sai_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */ - void *userData; /*!< User callback parameter */ - edma_tcd_t tcd[SAI_XFER_QUEUE_SIZE + 1U]; /*!< TCD pool for eDMA transfer. */ - sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ - size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ - volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ - volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ + edma_handle_t *dmaHandle; /*!< DMA handler for SAI send */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + uint8_t bytesPerFrame; /*!< Bytes in a frame */ + uint8_t channel; /*!< Which data channel */ + uint8_t count; /*!< The transfer data count in a DMA request */ + uint32_t state; /*!< Internal state for SAI eDMA transfer */ + sai_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */ + void *userData; /*!< User callback parameter */ + uint8_t tcd[(SAI_XFER_QUEUE_SIZE + 1U) * sizeof(edma_tcd_t)]; /*!< TCD pool for eDMA transfer. */ + sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ + size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ }; /******************************************************************************* diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_semc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_semc.c index fd58101fc1..31dbe76495 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_semc.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_semc.c @@ -1,8 +1,11 @@ /* + * The Clear BSD License * Copyright 2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -15,6 +18,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -33,6 +37,12 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.semc" +#endif + + /*! @brief Define macros for SEMC driver. */ #define SEMC_IPCOMMANDDATASIZEBYTEMAX (4U) #define SEMC_IPCOMMANDMAGICKEY (0xA55A) @@ -62,7 +72,7 @@ #define SEMC_BR_MEMSIZE_MAX (4 * 1024 * 1024) #define SEMC_SDRAM_MODESETCAL_OFFSET (4) #define SEMC_BR_REG_NUM (9) -#define SEMC_BYTE_NUMBIT (4) +#define SEMC_BYTE_NUMBIT (8) /******************************************************************************* * Prototypes ******************************************************************************/ @@ -116,6 +126,7 @@ static status_t SEMC_IsIPCommandDone(SEMC_Type *base); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /*! @brief Pointers to SEMC clocks for each instance. */ static const clock_ip_name_t s_semcClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_CLOCKS; +static const clock_ip_name_t s_semcExtClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_EXSC_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /*! @brief Pointers to SEMC bases for each instance. */ @@ -193,6 +204,9 @@ static status_t SEMC_ConfigureIPCommand(SEMC_Type *base, uint8_t size_bytes) * then the 4-byte data transfer will be split into two 2-byte transfer, the slave address * will be switched automatically according to connected device type*/ base->IPCR1 = SEMC_IPCR1_DATSZ(size_bytes); + /* Clear data size. */ + base->IPCR2 = 0; + /* Set data size. */ if (size_bytes < 4) { base->IPCR2 |= SEMC_IPCR2_BM3_MASK; @@ -212,7 +226,8 @@ static status_t SEMC_IsIPCommandDone(SEMC_Type *base) { /* Poll status bit till command is done*/ while (!(base->INTR & SEMC_INTR_IPCMDDONE_MASK)) - {}; + { + }; /* Clear status bit */ base->INTR |= SEMC_INTR_IPCMDDONE_MASK; @@ -266,6 +281,7 @@ void SEMC_Init(SEMC_Type *base, semc_config_t *configure) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Un-gate sdram controller clock. */ CLOCK_EnableClock(s_semcClock[SEMC_GetInstance(base)]); + CLOCK_EnableClock(s_semcExtClock[SEMC_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /* Initialize all BR to zero due to the default base address set. */ @@ -310,6 +326,7 @@ void SEMC_Deinit(SEMC_Type *base) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Disable SDRAM clock. */ CLOCK_DisableClock(s_semcClock[SEMC_GetInstance(base)]); + CLOCK_DisableClock(s_semcExtClock[SEMC_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } @@ -367,16 +384,18 @@ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_con base->IOCR &= ~SEMC_IOCR_MUX_A8_MASK; /* Timing setting. */ - base->SDRAMCR1 = SEMC_SDRAMCR1_PRE2ACT(SEMC_ConvertTiming(config->tPrecharge2Act_Ns, clkSrc_Hz)) | - SEMC_SDRAMCR1_ACT2RW(SEMC_ConvertTiming(config->tAct2ReadWrtie_Ns, clkSrc_Hz)) | - SEMC_SDRAMCR1_RFRC(SEMC_ConvertTiming(config->tRefreshRecovery_Ns, clkSrc_Hz)) | - SEMC_SDRAMCR1_WRC(SEMC_ConvertTiming(config->tWriteRecovery_Ns, clkSrc_Hz)) | - SEMC_SDRAMCR1_CKEOFF(SEMC_ConvertTiming(config->tCkeOff_Ns, clkSrc_Hz)) | - SEMC_SDRAMCR1_ACT2PRE(SEMC_ConvertTiming(config->tAct2Prechage_Ns, clkSrc_Hz)); - base->SDRAMCR2 = SEMC_SDRAMCR2_SRRC(SEMC_ConvertTiming(config->tSelfRefRecovery_Ns, clkSrc_Hz)) | - SEMC_SDRAMCR2_REF2REF(SEMC_ConvertTiming(config->tRefresh2Refresh_Ns, clkSrc_Hz)) | - SEMC_SDRAMCR2_ACT2ACT(SEMC_ConvertTiming(config->tAct2Act_Ns, clkSrc_Hz)) | - SEMC_SDRAMCR2_ITO(idle); + base->SDRAMCR1 = SEMC_SDRAMCR1_PRE2ACT(SEMC_ConvertTiming(config->tPrecharge2Act_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_ACT2RW(SEMC_ConvertTiming(config->tAct2ReadWrite_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_RFRC(SEMC_ConvertTiming(config->tRefreshRecovery_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_WRC(SEMC_ConvertTiming(config->tWriteRecovery_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_CKEOFF(SEMC_ConvertTiming(config->tCkeOff_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_ACT2PRE(SEMC_ConvertTiming(config->tAct2Prechage_Ns, clkSrc_Hz) - 1); + base->SDRAMCR2 = + SEMC_SDRAMCR2_SRRC(SEMC_ConvertTiming(config->tSelfRefRecovery_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR2_REF2REF( + SEMC_ConvertTiming(config->tRefresh2Refresh_Ns, clkSrc_Hz)) | /* No Minus one to keep with RM */ + SEMC_SDRAMCR2_ACT2ACT(SEMC_ConvertTiming(config->tAct2Act_Ns, clkSrc_Hz)) | /* No Minus one to keep with RM */ + SEMC_SDRAMCR2_ITO(idle); base->SDRAMCR3 = SEMC_SDRAMCR3_REBL(config->refreshBurstLen - 1) | /* N * 16 * 1s / clkSrc_Hz = config->tPrescalePeriod_Ns */ SEMC_SDRAMCR3_PRESCALE(prescale) | SEMC_SDRAMCR3_RT(refresh) | SEMC_SDRAMCR3_UT(urgentRef); @@ -399,11 +418,6 @@ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_con { return result; } - result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_AutoRefresh, 0, NULL); - if (result != kStatus_Success) - { - return result; - } /* Mode setting value. */ mode = (uint16_t)config->burstLen | (uint16_t)(config->casLatency << SEMC_SDRAM_MODESETCAL_OFFSET); result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_Modeset, mode, NULL); @@ -411,6 +425,8 @@ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_con { return result; } + /* Enables refresh */ + base->SDRAMCR3 |= SEMC_SDRAMCR3_REN_MASK; return kStatus_Success; } @@ -418,6 +434,7 @@ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_con status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz) { assert(config); + assert(config->timingConfig); uint8_t memsize; status_t result; @@ -471,21 +488,21 @@ status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_ SEMC_NANDCR0_EDO(config->edoModeEnabled) | SEMC_NANDCR0_COL(config->columnAddrBitNum); /* Timing setting. */ - base->NANDCR1 = SEMC_NANDCR1_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz)) | - SEMC_NANDCR1_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz)) | - SEMC_NANDCR1_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz)) | - SEMC_NANDCR1_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz)) | - SEMC_NANDCR1_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz)) | - SEMC_NANDCR1_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz)) | - SEMC_NANDCR1_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz)) | - SEMC_NANDCR1_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz)); - base->NANDCR2 = SEMC_NANDCR2_TWHR(SEMC_ConvertTiming(config->tWehigh2Relow_Ns, clkSrc_Hz)) | - SEMC_NANDCR2_TRHW(SEMC_ConvertTiming(config->tRehigh2Welow_Ns, clkSrc_Hz)) | - SEMC_NANDCR2_TADL(SEMC_ConvertTiming(config->tAle2WriteStart_Ns, clkSrc_Hz)) | - SEMC_NANDCR2_TRR(SEMC_ConvertTiming(config->tReady2Relow_Ns, clkSrc_Hz)) | - SEMC_NANDCR2_TWB(SEMC_ConvertTiming(config->tWehigh2Busy_Ns, clkSrc_Hz)); + base->NANDCR1 = SEMC_NANDCR1_CES(SEMC_ConvertTiming(config->timingConfig->tCeSetup_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_CEH(SEMC_ConvertTiming(config->timingConfig->tCeHold_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_WEL(SEMC_ConvertTiming(config->timingConfig->tWeLow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_WEH(SEMC_ConvertTiming(config->timingConfig->tWeHigh_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_REL(SEMC_ConvertTiming(config->timingConfig->tReLow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_REH(SEMC_ConvertTiming(config->timingConfig->tReHigh_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_TA(SEMC_ConvertTiming(config->timingConfig->tTurnAround_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_CEITV(SEMC_ConvertTiming(config->timingConfig->tCeInterval_Ns, clkSrc_Hz) - 1); + base->NANDCR2 = SEMC_NANDCR2_TWHR(SEMC_ConvertTiming(config->timingConfig->tWehigh2Relow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TRHW(SEMC_ConvertTiming(config->timingConfig->tRehigh2Welow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TADL(SEMC_ConvertTiming(config->timingConfig->tAle2WriteStart_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TRR(SEMC_ConvertTiming(config->timingConfig->tReady2Relow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TWB(SEMC_ConvertTiming(config->timingConfig->tWehigh2Busy_Ns, clkSrc_Hz) - 1); base->NANDCR3 = config->arrayAddrOption; - return SEMC_ConfigureIPCommand(base, (config->portSize + 1)); + return kStatus_Success; } status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz) @@ -502,8 +519,8 @@ status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux); uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ? - SEMC_IOCR_NOR_CE - 1 : - ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_NOR_CE_A8 : SEMC_IOCR_NOR_CE); + SEMC_IOCR_NOR_CE - 1 : + ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_NOR_CE_A8 : SEMC_IOCR_NOR_CE); /* IOMUX setting. */ base->IOCR = iocReg | (muxCe << config->cePinMux); @@ -615,8 +632,8 @@ status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_ uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux); uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ? - SEMC_IOCR_PSRAM_CE - 1 : - ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_PSRAM_CE_A8 : SEMC_IOCR_PSRAM_CE); + SEMC_IOCR_PSRAM_CE - 1 : + ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_PSRAM_CE_A8 : SEMC_IOCR_PSRAM_CE); /* IOMUX setting. */ base->IOCR = iocReg | (muxCe << config->cePinMux); @@ -721,8 +738,8 @@ status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->csxPinMux); uint32_t muxCsx = (config->csxPinMux == kSEMC_MUXRDY) ? - SEMC_IOCR_DBI_CSX - 1 : - ((config->csxPinMux == kSEMC_MUXA8) ? SEMC_IOCR_DBI_CSX_A8 : SEMC_IOCR_DBI_CSX); + SEMC_IOCR_DBI_CSX - 1 : + ((config->csxPinMux == kSEMC_MUXA8) ? SEMC_IOCR_DBI_CSX_A8 : SEMC_IOCR_DBI_CSX); /* IOMUX setting. */ base->IOCR = iocReg | (muxCsx << config->csxPinMux); @@ -751,8 +768,8 @@ status_t SEMC_SendIPCommand( SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read) { uint32_t cmdMode; - bool readCmd = false; - bool writeCmd = false; + bool readCmd = 0; + bool writeCmd = 0; status_t result; /* Clear status bit */ @@ -765,9 +782,9 @@ status_t SEMC_SendIPCommand( switch (type) { case kSEMC_MemType_NAND: - readCmd = (cmdMode == kSEMC_NANDCM_AXICmdAddrRead) || (cmdMode == kSEMC_NANDCM_CommandAddressRead) || + readCmd = (cmdMode == kSEMC_NANDCM_CommandAddressRead) || (cmdMode == kSEMC_NANDCM_CommandRead) || (cmdMode == kSEMC_NANDCM_Read); - writeCmd = (cmdMode == kSEMC_NANDCM_AXICmdAddrWrite) || (cmdMode == kSEMC_NANDCM_CommandAddressWrite) || + writeCmd = (cmdMode == kSEMC_NANDCM_CommandAddressWrite) || (cmdMode == kSEMC_NANDCM_CommandWrite) || (cmdMode == kSEMC_NANDCM_Write); break; case kSEMC_MemType_NOR: @@ -817,7 +834,6 @@ status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *dat status_t result = kStatus_Success; uint16_t ipCmd; - uint8_t dataSize = base->NANDCR0 & SEMC_NANDCR0_PS_MASK; uint32_t tempData = 0; /* Write command built */ @@ -842,13 +858,12 @@ status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *dat while (size_bytes) { - tempData |= ((uint32_t)*(data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT)); + tempData |= ((uint32_t) * (data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT)); size_bytes--; } result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, tempData, NULL); } - SEMC_ConfigureIPCommand(base, dataSize); return result; } @@ -858,7 +873,6 @@ status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data assert(data); status_t result = kStatus_Success; - uint8_t dataSize = base->NANDCR0 & SEMC_NANDCR0_PS_MASK; uint16_t ipCmd; uint32_t tempData = 0; @@ -886,12 +900,11 @@ status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data while (size_bytes) { - *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * (size_bytes - 1))) & 0xFFU; size_bytes--; + *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * size_bytes)) & 0xFFU; } } - SEMC_ConfigureIPCommand(base, dataSize); return result; } @@ -924,8 +937,8 @@ status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Read, 0, &tempData); while (size_bytes) { - *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * (size_bytes - 1))) & 0xFFU; size_bytes--; + *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * size_bytes)) & 0xFFU; } } @@ -961,7 +974,7 @@ status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data while (size_bytes) { - tempData |= ((uint32_t)*(data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT)); + tempData |= ((uint32_t) * (data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT)); size_bytes--; } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_semc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_semc.h index 7afbb594a0..a6937e12ee 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_semc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_semc.h @@ -1,8 +1,11 @@ /* + * The Clear BSD License * Copyright 2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -15,6 +18,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -42,8 +46,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief SEMC driver version 2.0.0. */ -#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief SEMC driver version 2.0.1. */ +#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*@}*/ /*! @brief SEMC status. */ @@ -87,10 +91,10 @@ typedef enum _semc_sdram_cs { } semc_sdram_cs_t; /*! @brief SEMC NAND device type. */ -typedef enum _semc_nand_type { - kSEMC_NAND_AXI = 0, - kSEMC_NAND_IP, -} semc_nand_type_t; +typedef enum _semc_nand_access_type { + kSEMC_NAND_ACCESS_BY_AXI = 0, + kSEMC_NAND_ACCESS_BY_IPCMD, +} semc_nand_access_type_t; /*! @brief SEMC interrupts . */ typedef enum _semc_interrupt_enable { @@ -273,9 +277,7 @@ typedef enum _semc_ipcmd_nand_addrmode { /*! @brief SEMC IP command for NAND： command mode. */ typedef enum _semc_ipcmd_nand_cmdmode { - kSEMC_NANDCM_AXICmdAddrRead = 0x0U, /*!< For AXI read. */ - kSEMC_NANDCM_AXICmdAddrWrite, /*!< For AXI write. */ - kSEMC_NANDCM_Command, /*!< command. */ + kSEMC_NANDCM_Command = 0x2U, /*!< command. */ kSEMC_NANDCM_CommandHold, /*!< Command hold. */ kSEMC_NANDCM_CommandAddress, /*!< Command address. */ kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */ @@ -345,7 +347,7 @@ typedef struct _semc_sdram_config semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ semc_caslatency_t casLatency; /*!< CAS latency. */ uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */ - uint8_t tAct2ReadWrtie_Ns; /*!< Act to read/write wait time in unit of nanosecond. */ + uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */ uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */ uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */ uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */ @@ -360,6 +362,26 @@ typedef struct _semc_sdram_config uint8_t refreshBurstLen; /*!< Refresh burst length. */ } semc_sdram_config_t; + +/*! @brief SEMC NAND device timing configuration structure. */ +typedef struct _semc_nand_timing_config +{ + uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */ + uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */ + uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */ + uint8_t tWeLow_Ns; /*!< WE low time: tWP. */ + uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */ + uint8_t tReLow_Ns; /*!< RE low time: tRP. */ + uint8_t tReHigh_Ns; /*!< RE high time: tREH. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */ + uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */ + uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */ + uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */ + uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */ + uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */ +} semc_nand_timing_config_t; + + /*! @brief SEMC NAND configuration structure. */ typedef struct _semc_nand_config { @@ -374,19 +396,7 @@ typedef struct _semc_nand_config semc_nand_address_option_t arrayAddrOption; /*!< Address option. */ sem_nand_burst_len_t burstLen; /*!< Burst length. */ smec_port_size_t portSize; /*!< Port size. */ - uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */ - uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */ - uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */ - uint8_t tWeLow_Ns; /*!< WE low time: tWP. */ - uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */ - uint8_t tReLow_Ns; /*!< RE low time: tRP. */ - uint8_t tReHigh_Ns; /*!< RE high time: tREH. */ - uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */ - uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */ - uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */ - uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */ - uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */ - uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */ + semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */ } semc_nand_config_t; /*! @brief SEMC NOR configuration structure. */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_hp.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_hp.c index 1f98dec45c..0e6efab131 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_hp.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_hp.c @@ -1,9 +1,12 @@ /* - * Copyright (c) 2017, Freescale Semiconductor, Inc. + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2017, NXP * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -12,38 +15,11 @@ * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Copyright (c) 2017, NXP Semiconductors, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * o Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -61,6 +37,12 @@ /******************************************************************************* * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.snvs_hp" +#endif + #define SECONDS_IN_A_DAY (86400U) #define SECONDS_IN_A_HOUR (3600U) #define SECONDS_IN_A_MINUTE (60U) @@ -463,69 +445,18 @@ uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base) return flags; } -void SNVS_HP_RTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask) -{ - uint32_t wrMask = 0U; - - if (mask & kSNVS_RTC_PeriodicInterruptFlag) - { - wrMask |= SNVS_HPSR_PI_MASK; - } - - if (mask & kSNVS_RTC_AlarmInterruptFlag) - { - wrMask |= SNVS_HPSR_HPTA_MASK; - } - - base->HPSR |= wrMask; -} - -void SNVS_HP_RTC_EnableInterrupts(SNVS_Type *base, uint32_t mask) -{ - uint32_t wrMask = 0U; - - if (mask & kSNVS_RTC_PeriodicInterruptEnable) - { - wrMask |= SNVS_HPCR_PI_EN_MASK; - } - - if (mask & kSNVS_RTC_AlarmInterruptEnable) - { - wrMask |= SNVS_HPCR_HPTA_EN_MASK; - } - - base->HPCR |= wrMask; -} - -void SNVS_HP_RTC_DisableInterrupts(SNVS_Type *base, uint32_t mask) -{ - uint32_t wrMask = 0U; - - if (mask & kSNVS_RTC_PeriodicInterruptEnable) - { - wrMask |= SNVS_HPCR_PI_EN_MASK; - } - - if (mask & kSNVS_RTC_AlarmInterruptEnable) - { - wrMask |= SNVS_HPCR_HPTA_EN_MASK; - } - - base->HPCR &= ~wrMask; -} - uint32_t SNVS_HP_RTC_GetEnabledInterrupts(SNVS_Type *base) { uint32_t val = 0U; if (base->HPCR & SNVS_HPCR_PI_EN_MASK) { - val |= kSNVS_RTC_PeriodicInterruptFlag; + val |= kSNVS_RTC_PeriodicInterrupt; } if (base->HPCR & SNVS_HPCR_HPTA_EN_MASK) { - val |= kSNVS_RTC_AlarmInterruptFlag; + val |= kSNVS_RTC_AlarmInterrupt; } return val; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_hp.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_hp.h index d06b0233ec..27bf7e6625 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_hp.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_hp.h @@ -1,9 +1,12 @@ /* - * Copyright (c) 2017, Freescale Semiconductor, Inc. + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2017, NXP * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -12,38 +15,11 @@ * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Copyright (c) 2017, NXP Semiconductors, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * o Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -76,17 +52,17 @@ /*@}*/ /*! @brief List of SNVS interrupts */ -typedef enum _snvs_hp_interrupt_enable +typedef enum _snvs_hp_interrupts { - kSNVS_RTC_PeriodicInterruptEnable = 1U, /*!< RTC periodic interrupt.*/ - kSNVS_RTC_AlarmInterruptEnable = 2U, /*!< RTC time alarm.*/ -} snvs_hp_interrupt_enable_t; + kSNVS_RTC_AlarmInterrupt = SNVS_HPCR_HPTA_EN_MASK, /*!< RTC time alarm */ + kSNVS_RTC_PeriodicInterrupt = SNVS_HPCR_PI_EN_MASK, /*!< RTC periodic interrupt */ +} snvs_hp_interrupts_t; /*! @brief List of SNVS flags */ typedef enum _snvs_hp_status_flags { - kSNVS_RTC_PeriodicInterruptFlag = 1U, /*!< RTC periodic interrupt flag */ - kSNVS_RTC_AlarmInterruptFlag = 2U, /*!< RTC time alarm flag */ + kSNVS_RTC_AlarmInterruptFlag = SNVS_HPSR_HPTA_MASK, /*!< RTC time alarm flag */ + kSNVS_RTC_PeriodicInterruptFlag = SNVS_HPSR_PI_MASK, /*!< RTC periodic interrupt flag */ } snvs_hp_status_flags_t; /*! @brief Structure is used to hold the date and time */ @@ -235,7 +211,10 @@ void SNVS_HP_RTC_TimeSynchronize(SNVS_Type *base); * @param mask The interrupts to enable. This is a logical OR of members of the * enumeration ::snvs_interrupt_enable_t */ -void SNVS_HP_RTC_EnableInterrupts(SNVS_Type *base, uint32_t mask); +static inline void SNVS_HP_RTC_EnableInterrupts(SNVS_Type *base, uint32_t mask) +{ + base->HPCR |= mask; +} /*! * @brief Disables the selected SNVS interrupts. @@ -244,7 +223,10 @@ void SNVS_HP_RTC_EnableInterrupts(SNVS_Type *base, uint32_t mask); * @param mask The interrupts to enable. This is a logical OR of members of the * enumeration ::snvs_interrupt_enable_t */ -void SNVS_HP_RTC_DisableInterrupts(SNVS_Type *base, uint32_t mask); +static inline void SNVS_HP_RTC_DisableInterrupts(SNVS_Type *base, uint32_t mask) +{ + base->HPCR &= ~mask; +} /*! * @brief Gets the enabled SNVS interrupts. @@ -280,7 +262,10 @@ uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base); * @param mask The status flags to clear. This is a logical OR of members of the * enumeration ::snvs_status_flags_t */ -void SNVS_HP_RTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask); +static inline void SNVS_HP_RTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask) +{ + base->HPSR |= mask; +} /*! @}*/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_lp.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_lp.c index d99f91e3d4..c9f539630e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_lp.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_lp.c @@ -1,9 +1,12 @@ /* - * Copyright (c) 2017, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2017, NXP + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -33,6 +37,12 @@ /******************************************************************************* * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.snvs_lp" +#endif + #define SECONDS_IN_A_DAY (86400U) #define SECONDS_IN_A_HOUR (3600U) #define SECONDS_IN_A_MINUTE (60U) @@ -404,37 +414,13 @@ uint32_t SNVS_LP_SRTC_GetStatusFlags(SNVS_Type *base) return flags; } -void SNVS_LP_SRTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask) -{ - if (mask & kSNVS_SRTC_AlarmInterruptFlag) - { - base->LPSR |= SNVS_LPSR_LPTA_MASK; - } -} - -void SNVS_LP_SRTC_EnableInterrupts(SNVS_Type *base, uint32_t mask) -{ - if (mask & kSNVS_SRTC_AlarmInterruptEnable) - { - base->LPCR |= SNVS_LPCR_LPTA_EN_MASK; - } -} - -void SNVS_LP_SRTC_DisableInterrupts(SNVS_Type *base, uint32_t mask) -{ - if (mask & kSNVS_SRTC_AlarmInterruptEnable) - { - base->LPCR &= ~SNVS_LPCR_LPTA_EN_MASK; - } -} - uint32_t SNVS_LP_SRTC_GetEnabledInterrupts(SNVS_Type *base) { uint32_t val = 0U; if (base->LPCR & SNVS_LPCR_LPTA_EN_MASK) { - val |= kSNVS_SRTC_AlarmInterruptFlag; + val |= kSNVS_SRTC_AlarmInterrupt; } return val; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_lp.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_lp.h index 9bda2701ce..bd61d52ddb 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_lp.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_lp.h @@ -1,9 +1,12 @@ /* - * Copyright (c) 2017, Freescale Semiconductor, Inc. + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2017, NXP * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -12,38 +15,11 @@ * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Copyright (c) 2017, NXP Semiconductors, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * o Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -76,15 +52,15 @@ /*@}*/ /*! @brief List of SNVS_LP interrupts */ -typedef enum _snvs_lp_srtc_interrupt_enable +typedef enum _snvs_lp_srtc_interrupts { - kSNVS_SRTC_AlarmInterruptEnable = 4U, /*!< SRTC time alarm.*/ -} snvs_lp_srtc_interrupt_enable_t; + kSNVS_SRTC_AlarmInterrupt = SNVS_LPCR_LPTA_EN_MASK, /*!< SRTC time alarm.*/ +} snvs_lp_srtc_interrupts_t; /*! @brief List of SNVS_LP flags */ typedef enum _snvs_lp_srtc_status_flags { - kSNVS_SRTC_AlarmInterruptFlag = 4U, /*!< SRTC time alarm flag*/ + kSNVS_SRTC_AlarmInterruptFlag = SNVS_LPSR_LPTA_MASK, /*!< SRTC time alarm flag */ } snvs_lp_srtc_status_flags_t; /*! @brief List of SNVS_LP external tampers */ @@ -263,7 +239,10 @@ void SNVS_LP_SRTC_GetAlarm(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime); * @param mask The interrupts to enable. This is a logical OR of members of the * enumeration ::snvs_interrupt_enable_t */ -void SNVS_LP_SRTC_EnableInterrupts(SNVS_Type *base, uint32_t mask); +static inline void SNVS_LP_SRTC_EnableInterrupts(SNVS_Type *base, uint32_t mask) +{ + base->LPCR |= mask; +} /*! * @brief Disables the selected SNVS interrupts. @@ -272,7 +251,10 @@ void SNVS_LP_SRTC_EnableInterrupts(SNVS_Type *base, uint32_t mask); * @param mask The interrupts to enable. This is a logical OR of members of the * enumeration ::snvs_interrupt_enable_t */ -void SNVS_LP_SRTC_DisableInterrupts(SNVS_Type *base, uint32_t mask); +static inline void SNVS_LP_SRTC_DisableInterrupts(SNVS_Type *base, uint32_t mask) +{ + base->LPCR &= ~mask; +} /*! * @brief Gets the enabled SNVS interrupts. @@ -308,7 +290,10 @@ uint32_t SNVS_LP_SRTC_GetStatusFlags(SNVS_Type *base); * @param mask The status flags to clear. This is a logical OR of members of the * enumeration ::snvs_status_flags_t */ -void SNVS_LP_SRTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask); +static inline void SNVS_LP_SRTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask) +{ + base->LPSR |= mask; +} /*! @}*/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.c index b0e70c0358..80b3229e20 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2017, NXP Semiconductor, Inc. * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,6 +34,12 @@ #include "fsl_spdif.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.spdif" +#endif + + /******************************************************************************* * Definitations ******************************************************************************/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.h index 67763b73a4..ce852af544 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -726,7 +730,7 @@ status_t SPDIF_TransferGetReceiveCount(SPDIF_Type *base, spdif_handle_t *handle, void SPDIF_TransferAbortSend(SPDIF_Type *base, spdif_handle_t *handle); /*! - * @brief Aborts the the current IRQ receive. + * @brief Aborts the current IRQ receive. * * @note This API can be called when an interrupt non-blocking transfer initiates * to abort the transfer early. diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif_edma.c index 32909f9234..79cc2ff05d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif_edma.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif_edma.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,6 +34,12 @@ #include "fsl_spdif_edma.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.spdif_edma" +#endif + + /******************************************************************************* * Definitations ******************************************************************************/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif_edma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif_edma.h index c8f6e552b7..2815616f26 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif_edma.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif_edma.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -42,6 +46,11 @@ * Definitions ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +#define FSL_SPDIF_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + typedef struct _spdif_edma_handle spdif_edma_handle_t; /*! @brief SPDIF eDMA transfer callback function for finish and error */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_src.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_src.c index 3bce29533f..7672586d32 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_src.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_src.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,6 +34,12 @@ #include "fsl_src.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.src" +#endif + + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_src.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_src.h index 8d4dfcaeb0..bf25582051 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_src.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_src.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.c index 0aafb78d8e..68864316fe 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -34,6 +38,12 @@ /******************************************************************************* * Definitions *******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.trng" +#endif + /* Default values for user configuration structure.*/ #if (defined(KW40Z4_SERIES) || defined(KW41Z4_SERIES) || defined(KW31Z4_SERIES) || defined(KW21Z4_SERIES) || \ defined(MCIMX7U5_M4_SERIES) || defined(KW36Z4_SERIES)) @@ -1242,7 +1252,7 @@ status_t TRNG_GetDefaultConfig(trng_config_t *userConfig) { status_t result; - if (userConfig != 0) + if (userConfig != NULL) { userConfig->lock = TRNG_USER_CONFIG_DEFAULT_LOCK; userConfig->clockMode = kTRNG_ClockModeRingOscillator; @@ -1519,7 +1529,7 @@ status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig) status_t result; /* Check input parameters.*/ - if ((base != 0) && (userConfig != 0)) + if ((base != NULL) && (userConfig != NULL)) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Enable the clock gate. */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.h index 5d349a3c22..de844e892e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * + * Copyright 2016-2018 NXP + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -46,16 +50,18 @@ /*! @name Driver version */ /*@{*/ -/*! @brief TRNG driver version 2.0.1. +/*! @brief TRNG driver version 2.0.2. * - * Current version: 2.0.1 + * Current version: 2.0.2 * * Change log: + * - Version 2.0.2 + * - fix MISRA issues * - Version 2.0.1 * - add support for KL8x and KL28Z * - update default OSCDIV for K81 to divide by 2 */ -#define FSL_TRNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +#define FSL_TRNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*@}*/ /*! @brief TRNG sample mode. Used by trng_config_t. */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tsc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tsc.c index 1e869e4dad..75f5c62d21 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tsc.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tsc.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,6 +34,12 @@ #include "fsl_tsc.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.tsc" +#endif + + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -90,7 +100,7 @@ void TSC_Init(TSC_Type *base, const tsc_config_t *config) } base->BASIC_SETTING = tmp32; /* Configure TSC_PS_INPUT_BUFFER_ADDR register. */ - base->PS_INPUT_BUFFER_ADDR = TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME(config->prechargeTime); + base->PRE_CHARGE_TIME = TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(config->prechargeTime); } void TSC_Deinit(TSC_Type *base) @@ -111,7 +121,7 @@ void TSC_GetDefaultConfig(tsc_config_t *config) uint32_t TSC_GetMeasureValue(TSC_Type *base, tsc_corrdinate_value_selection_t selection) { - uint32_t tmp32 = 0U; + uint32_t tmp32 = 0; if (selection == kTSC_XCoordinateValueSelection) { diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tsc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tsc.h index e68e1b27bc..84ea320633 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tsc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tsc.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -541,11 +545,4 @@ void TSC_DebugEnableDetection(TSC_Type *base, tsc_detection_mode_t detectionMode * @param mode TSC port mode.(pull down, pull up and 200k-pull up) */ void TSC_DebugSetPortMode(TSC_Type *base, tsc_port_source_t port, tsc_port_mode_t mode); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - #endif /* _FSL_TSC_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_usdhc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_usdhc.c index b54b27c28e..d5145ff5cf 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_usdhc.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_usdhc.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -36,15 +40,23 @@ /******************************************************************************* * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.usdhc" +#endif + /*! @brief Clock setting */ /* Max SD clock divisor from base clock */ #define USDHC_MAX_DVS ((USDHC_SYS_CTRL_DVS_MASK >> USDHC_SYS_CTRL_DVS_SHIFT) + 1U) +#define USDHC_MAX_CLKFS ((USDHC_SYS_CTRL_SDCLKFS_MASK >> USDHC_SYS_CTRL_SDCLKFS_SHIFT) + 1U) #define USDHC_PREV_DVS(x) ((x) -= 1U) #define USDHC_PREV_CLKFS(x, y) ((x) >>= (y)) /* Typedef for interrupt handler. */ typedef void (*usdhc_isr_t)(USDHC_Type *base, usdhc_handle_t *handle); - +/*! @brief Dummy data buffer for mmc boot mode */ +AT_NONCACHEABLE_SECTION_ALIGN(uint32_t s_usdhcBootDummy, USDHC_ADMA2_ADDRESS_ALIGN); /******************************************************************************* * Prototypes ******************************************************************************/ @@ -273,7 +285,7 @@ static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, usdhc_data_t *data return kStatus_USDHC_BusyTransferring; } /* check transfer block count */ - if ((data->blockCount > USDHC_MAX_BLOCK_COUNT)) + if ((data->blockCount > USDHC_MAX_BLOCK_COUNT) || ((data->txData == NULL) && (data->rxData == NULL))) { return kStatus_InvalidArgument; } @@ -331,6 +343,11 @@ static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, usdhc_data_t *data /* clear data flags */ mixCtrl &= ~(USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK | USDHC_MIX_CTRL_DTDSEL_MASK | USDHC_MIX_CTRL_AC12EN_MASK); + + if (base->PRES_STATE & kUSDHC_CommandInhibitFlag) + { + return kStatus_USDHC_BusyTransferring; + } } /* config the mix parameter */ @@ -453,16 +470,16 @@ static status_t USDHC_ReadByDataPortBlocking(USDHC_Type *base, usdhc_data_t *dat while ((error == kStatus_Success) && (transferredWords < totalWords)) { - while (!(USDHC_GetInterruptStatusFlags(base) & - (kUSDHC_BufferReadReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_TuningErrorFlag))) + while (!(interruptStatus & (kUSDHC_BufferReadReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_TuningErrorFlag))) { + interruptStatus = USDHC_GetInterruptStatusFlags(base); } - interruptStatus = USDHC_GetInterruptStatusFlags(base); /* during std tuning process, software do not need to read data, but wait BRR is enough */ if ((data->dataType == kUSDHC_TransferDataTuning) && (interruptStatus & kUSDHC_BufferReadReadyFlag)) { USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferReadReadyFlag | kUSDHC_TuningPassFlag); + return kStatus_Success; } else if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) @@ -489,6 +506,7 @@ static status_t USDHC_ReadByDataPortBlocking(USDHC_Type *base, usdhc_data_t *dat transferredWords = USDHC_ReadDataPort(base, data, transferredWords); /* clear buffer read ready */ USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferReadReadyFlag); + interruptStatus = 0U; } } @@ -572,13 +590,11 @@ static status_t USDHC_WriteByDataPortBlocking(USDHC_Type *base, usdhc_data_t *da while ((error == kStatus_Success) && (transferredWords < totalWords)) { - while (!(USDHC_GetInterruptStatusFlags(base) & - (kUSDHC_BufferWriteReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_TuningErrorFlag))) + while (!(interruptStatus & (kUSDHC_BufferWriteReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_TuningErrorFlag))) { + interruptStatus = USDHC_GetInterruptStatusFlags(base); } - interruptStatus = USDHC_GetInterruptStatusFlags(base); - if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) { USDHC_ClearInterruptStatusFlags(base, kUSDHC_TuningErrorFlag); @@ -603,15 +619,17 @@ static status_t USDHC_WriteByDataPortBlocking(USDHC_Type *base, usdhc_data_t *da transferredWords = USDHC_WriteDataPort(base, data, transferredWords); /* clear buffer write ready */ USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferWriteReadyFlag); + interruptStatus = 0U; } } /* Wait write data complete or data transfer error after the last writing operation. */ - while (!(USDHC_GetInterruptStatusFlags(base) & (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag))) + while (!(interruptStatus & (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag))) { + interruptStatus = USDHC_GetInterruptStatusFlags(base); } - if ((USDHC_GetInterruptStatusFlags(base) & kUSDHC_DataErrorFlag) != 0U) + if ((interruptStatus & kUSDHC_DataErrorFlag) != 0U) { if (!(data->enableIgnoreError)) { @@ -697,12 +715,11 @@ static status_t USDHC_WaitCommandDone(USDHC_Type *base, usdhc_command_t *command if (pollingCmdDone) { /* Wait command complete or USDHC encounters error. */ - while (!(USDHC_GetInterruptStatusFlags(base) & (kUSDHC_CommandCompleteFlag | kUSDHC_CommandErrorFlag))) + while (!(interruptStatus & (kUSDHC_CommandCompleteFlag | kUSDHC_CommandErrorFlag))) { + interruptStatus = USDHC_GetInterruptStatusFlags(base); } - interruptStatus = USDHC_GetInterruptStatusFlags(base); - if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) { error = kStatus_USDHC_TuningError; @@ -735,18 +752,17 @@ static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, if (enDMA) { /* Wait data complete or USDHC encounters error. */ - while (!(USDHC_GetInterruptStatusFlags(base) & - (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag | kUSDHC_TuningErrorFlag))) + while (!((interruptStatus & + (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag | kUSDHC_TuningErrorFlag)))) { + interruptStatus = USDHC_GetInterruptStatusFlags(base); } - interruptStatus = USDHC_GetInterruptStatusFlags(base); - if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) { error = kStatus_USDHC_TuningError; } - else if ((interruptStatus & (kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag)) != 0U) + else if (((interruptStatus & (kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag)) != 0U)) { if ((!(data->enableIgnoreError)) || (interruptStatus & kUSDHC_DataTimeoutFlag)) { @@ -756,6 +772,11 @@ static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, else { } + /* load dummy data */ + if ((data->dataType == kUSDHC_TransferDataBootcontinous) && (error == kStatus_Success)) + { + *(data->rxData) = s_usdhcBootDummy; + } USDHC_ClearInterruptStatusFlags(base, (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag | kUSDHC_TuningPassFlag | kUSDHC_TuningErrorFlag)); @@ -772,15 +793,6 @@ static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, } } -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* invalidate cache for read */ - if ((data != NULL) && (data->rxData != NULL) && (data->dataType != kUSDHC_TransferDataTuning)) - { - /* invalidate the DCACHE */ - DCACHE_InvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); - } -#endif - return error; } @@ -887,16 +899,12 @@ uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busCl uint32_t prescaler = 0U; uint32_t sysctl = 0U; uint32_t nearestFrequency = 0U; - uint32_t maxClKFS = ((USDHC_SYS_CTRL_SDCLKFS_MASK >> USDHC_SYS_CTRL_SDCLKFS_SHIFT) + 1U); - bool enDDR = false; - /* DDR mode max clkfs can reach 512 */ - if ((base->MIX_CTRL & USDHC_MIX_CTRL_DDR_EN_MASK) != 0U) - { - enDDR = true; - maxClKFS *= 2U; - } + /* calucate total divisor first */ - totalDiv = srcClock_Hz / busClock_Hz; + if ((totalDiv = srcClock_Hz / busClock_Hz) > (USDHC_MAX_CLKFS * USDHC_MAX_DVS)) + { + return 0U; + } if (totalDiv != 0U) { @@ -911,7 +919,7 @@ uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busCl { prescaler = totalDiv / USDHC_MAX_DVS; /* prescaler must be a value which equal 2^n and smaller than SDHC_MAX_CLKFS */ - while (((maxClKFS % prescaler) != 0U) || (prescaler == 1U)) + while (((USDHC_MAX_CLKFS % prescaler) != 0U) || (prescaler == 1U)) { prescaler++; } @@ -922,7 +930,8 @@ uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busCl { divisor++; } - nearestFrequency = srcClock_Hz / divisor / prescaler; + + nearestFrequency = srcClock_Hz / (divisor == 0U ? 1U : divisor) / prescaler; } else { @@ -935,8 +944,8 @@ uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busCl } else { - divisor = totalDiv; - prescaler = 0U; + divisor = (totalDiv / 2U) + 1U; /* make sure the output frequency not bigger than target value */ + prescaler = 2U; } nearestFrequency = srcClock_Hz / totalDiv; } @@ -959,7 +968,7 @@ uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busCl /* calucate the value write to register */ if (prescaler != 0U) { - USDHC_PREV_CLKFS(prescaler, (enDDR ? 2U : 1U)); + USDHC_PREV_CLKFS(prescaler, 1U); } /* Set the SD clock frequency divisor, SD clock frequency select, data timeout counter value. */ @@ -992,6 +1001,33 @@ bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout) return ((!timeout) ? false : true); } +void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos) +{ + uint32_t prescaler = (base->SYS_CTRL & USDHC_SYS_CTRL_SDCLKFS_MASK) >> USDHC_SYS_CTRL_SDCLKFS_SHIFT; + + if (enable) + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_NIBBLE_POS_MASK; + base->MIX_CTRL |= (USDHC_MIX_CTRL_DDR_EN_MASK | USDHC_MIX_CTRL_NIBBLE_POS(nibblePos)); + prescaler >>= 1U; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DDR_EN_MASK; + + if (prescaler == 0U) + { + prescaler += 1U; + } + else + { + prescaler <<= 1U; + } + } + + base->SYS_CTRL = (base->SYS_CTRL & (~USDHC_SYS_CTRL_SDCLKFS_MASK)) | USDHC_SYS_CTRL_SDCLKFS(prescaler); +} + void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config) { assert(config); @@ -1040,6 +1076,11 @@ status_t USDHC_SetADMA1Descriptor( { return kStatus_USDHC_DMADataAddrNotAlign; } + + if (flags == kUSDHC_AdmaDescriptorMultipleFlag) + { + return kStatus_USDHC_NotSupport; + } /* * Add non aligned access support ,user need make sure your buffer size is big * enough to hold the data,in other words,user need make sure the buffer size @@ -1060,19 +1101,6 @@ status_t USDHC_SetADMA1Descriptor( { miniEntries = ((dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U); } - /* calucate the start entry for multiple descriptor mode, ADMA engine is not stop, so update the descriptor - data adress and data size is enough */ - if (flags == kUSDHC_AdmaDescriptorMultipleFlag) - { - for (i = 0U; i < maxEntries; i++) - { - if ((adma1EntryAddress[i] & kUSDHC_Adma1DescriptorValidFlag) == 0U) - { - startEntries = i; - break; - } - } - } /* ADMA1 needs two descriptors to finish a transfer */ miniEntries <<= 1U; @@ -1082,8 +1110,7 @@ status_t USDHC_SetADMA1Descriptor( return kStatus_OutOfRange; } - for (i = startEntries; i < (flags == kUSDHC_AdmaDescriptorSingleFlag ? (miniEntries + startEntries) : maxEntries); - i += 2U) + for (i = startEntries; i < (miniEntries + startEntries); i += 2U) { if (dataBytes > USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) { @@ -1091,29 +1118,18 @@ status_t USDHC_SetADMA1Descriptor( } else { - dmaBufferLen = (dataBytes == 0U ? sizeof(uint32_t) : - dataBytes); /* adma don't support 0 data length transfer descriptor */ + dmaBufferLen = dataBytes; } adma1EntryAddress[i] = (dmaBufferLen << USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT); adma1EntryAddress[i] |= kUSDHC_Adma1DescriptorTypeSetLength; - adma1EntryAddress[i + 1U] = ((uint32_t)(data) << USDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT); - adma1EntryAddress[i + 1U] |= (dataBytes == 0U) ? 0U : kUSDHC_Adma1DescriptorTypeTransfer; + adma1EntryAddress[i + 1U] = (uint32_t)(data); + adma1EntryAddress[i + 1U] |= kUSDHC_Adma1DescriptorTypeTransfer; data += dmaBufferLen / sizeof(uint32_t); - if (dataBytes != 0U) - { - dataBytes -= dmaBufferLen; - } + dataBytes -= dmaBufferLen; } /* the end of the descriptor */ adma1EntryAddress[i - 1U] |= kUSDHC_Adma1DescriptorEndFlag; - /* add a dummy valid ADMA descriptor for multiple descriptor mode, this is useful when transfer boot data, the ADMA - engine - will not stop at block gap */ - if (flags == kUSDHC_AdmaDescriptorMultipleFlag) - { - adma1EntryAddress[miniEntries + startEntries] |= kUSDHC_Adma1DescriptorTypeTransfer; - } return kStatus_Success; } @@ -1162,10 +1178,12 @@ status_t USDHC_SetADMA2Descriptor( { if ((adma2EntryAddress[i].attribute & kUSDHC_Adma2DescriptorValidFlag) == 0U) { - startEntries = i; break; } } + startEntries = i; + /* add one entry for dummy entry */ + miniEntries += 1U; } if ((miniEntries + startEntries) > maxEntries) @@ -1173,8 +1191,7 @@ status_t USDHC_SetADMA2Descriptor( return kStatus_OutOfRange; } - for (i = startEntries; i < (flags == kUSDHC_AdmaDescriptorSingleFlag ? (miniEntries + startEntries) : maxEntries); - i++) + for (i = startEntries; i < (miniEntries + startEntries); i++) { if (dataBytes > USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) { @@ -1187,9 +1204,10 @@ status_t USDHC_SetADMA2Descriptor( } /* Each descriptor for ADMA2 is 64-bit in length */ - adma2EntryAddress[i].address = data; + adma2EntryAddress[i].address = (dataBytes == 0U) ? &s_usdhcBootDummy : data; adma2EntryAddress[i].attribute = (dmaBufferLen << USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT); - adma2EntryAddress[i].attribute |= (dataBytes == 0U) ? 0U : kUSDHC_Adma2DescriptorTypeTransfer; + adma2EntryAddress[i].attribute |= + (dataBytes == 0U) ? 0U : (kUSDHC_Adma2DescriptorTypeTransfer | kUSDHC_Adma2DescriptorInterruptFlag); data += (dmaBufferLen / sizeof(uint32_t)); if (dataBytes != 0U) @@ -1197,14 +1215,18 @@ status_t USDHC_SetADMA2Descriptor( dataBytes -= dmaBufferLen; } } - /* set the end bit */ - adma2EntryAddress[i - 1U].attribute |= kUSDHC_Adma2DescriptorEndFlag; + /* add a dummy valid ADMA descriptor for multiple descriptor mode, this is useful when transfer boot data, the ADMA engine will not stop at block gap */ if (flags == kUSDHC_AdmaDescriptorMultipleFlag) { - adma2EntryAddress[miniEntries + startEntries].attribute |= kUSDHC_Adma2DescriptorTypeTransfer; + adma2EntryAddress[startEntries + 1U].attribute |= kUSDHC_Adma2DescriptorTypeTransfer; + } + else + { + /* set the end bit */ + adma2EntryAddress[i - 1U].attribute |= kUSDHC_Adma2DescriptorEndFlag; } return kStatus_Success; @@ -1267,7 +1289,11 @@ status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, assert(NULL != dataConfig); status_t error = kStatus_Fail; - const uint32_t *data = (dataConfig->rxData == NULL) ? dataConfig->txData : dataConfig->rxData; + uint32_t bootDummyOffset = dataConfig->dataType == kUSDHC_TransferDataBootcontinous ? sizeof(uint32_t) : 0U; + const uint32_t *data = + (const uint32_t *)((uint32_t)((dataConfig->rxData == NULL) ? dataConfig->txData : dataConfig->rxData) + + bootDummyOffset); + uint32_t blockSize = dataConfig->blockSize * dataConfig->blockCount - bootDummyOffset; switch (dmaConfig->dmaMode) { @@ -1278,16 +1304,15 @@ status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, break; #endif case kUSDHC_DmaModeSimple: + error = kStatus_Success; break; case kUSDHC_DmaModeAdma1: - error = USDHC_SetADMA1Descriptor(dmaConfig->admaTable, dmaConfig->admaTableWords, data, - dataConfig->blockSize * dataConfig->blockCount, flags); + error = USDHC_SetADMA1Descriptor(dmaConfig->admaTable, dmaConfig->admaTableWords, data, blockSize, flags); break; case kUSDHC_DmaModeAdma2: - error = USDHC_SetADMA2Descriptor(dmaConfig->admaTable, dmaConfig->admaTableWords, data, - dataConfig->blockSize * dataConfig->blockCount, flags); + error = USDHC_SetADMA2Descriptor(dmaConfig->admaTable, dmaConfig->admaTableWords, data, blockSize, flags); break; default: return kStatus_USDHC_PrepareAdmaDescriptorFailed; @@ -1321,22 +1346,6 @@ status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig return kStatus_USDHC_ReTuningRequest; } -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - if ((data != NULL) && (!executeTuning)) - { - if (data->txData != NULL) - { - /* clear the DCACHE */ - DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount)); - } - else - { - /* clear the DCACHE */ - DCACHE_CleanByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); - } - } -#endif - /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/ if ((data != NULL) && (dmaConfig != NULL) && (!executeTuning)) { @@ -1352,11 +1361,27 @@ status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig /* disable DMA, using polling mode in this situation */ USDHC_EnableInternalDMA(base, false); } +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + else + { + if (data->txData != NULL) + { + /* clear the DCACHE */ + DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount)); + } + else + { + /* clear the DCACHE */ + DCACHE_CleanInvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); + } + } +#endif /* config the data transfer parameter */ - if (kStatus_Success != USDHC_SetDataTransferConfig(base, data, &(command->flags))) + error = USDHC_SetDataTransferConfig(base, data, &(command->flags)); + if (kStatus_Success != error) { - return kStatus_InvalidArgument; + return error; } /* send command first */ USDHC_SendCommand(base, command); @@ -1392,22 +1417,6 @@ status_t USDHC_TransferNonBlocking(USDHC_Type *base, return kStatus_USDHC_ReTuningRequest; } -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - if ((data != NULL) && (!executeTuning)) - { - if (data->txData != NULL) - { - /* clear the DCACHE */ - DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount)); - } - else - { - /* clear the DCACHE */ - DCACHE_CleanByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); - } - } -#endif - /* Save command and data into handle before transferring. */ handle->command = command; handle->data = data; @@ -1429,10 +1438,26 @@ status_t USDHC_TransferNonBlocking(USDHC_Type *base, /* disable DMA, using polling mode in this situation */ USDHC_EnableInternalDMA(base, false); } - - if (kStatus_Success != USDHC_SetDataTransferConfig(base, data, &(command->flags))) +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + else { - return kStatus_InvalidArgument; + if (data->txData != NULL) + { + /* clear the DCACHE */ + DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount)); + } + else + { + /* clear the DCACHE */ + DCACHE_CleanInvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); + } + } +#endif + + error = USDHC_SetDataTransferConfig(base, data, &(command->flags)); + if (kStatus_Success != error) + { + return error; } /* send command first */ @@ -1594,8 +1619,7 @@ static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, u { assert(handle->data); - if (((!(handle->data->enableIgnoreError)) || (interruptFlags & kUSDHC_DataTimeoutFlag)) && - (interruptFlags & (kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag))) + if ((!(handle->data->enableIgnoreError)) && ((interruptFlags & (kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag)))) { if (handle->callback.TransferComplete) { @@ -1623,27 +1647,19 @@ static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, u { handle->transferredWords = USDHC_WriteDataPort(base, handle->data, handle->transferredWords); } - else if (interruptFlags & kUSDHC_DataCompleteFlag) + else { - if (handle->callback.TransferComplete) + if ((interruptFlags & kUSDHC_DmaCompleteFlag) && + (handle->data->dataType == kUSDHC_TransferDataBootcontinous)) + { + *(handle->data->rxData) = s_usdhcBootDummy; + } + + if ((handle->callback.TransferComplete) && (interruptFlags & kUSDHC_DataCompleteFlag)) { handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); } } - else - { - /* Do nothing when DMA complete flag is set. Wait until data complete flag is set. */ - } -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* invalidate cache for read */ - if ((handle->data != NULL) && (handle->data->rxData != NULL) && - (handle->data->dataType != kUSDHC_TransferDataTuning)) - { - /* invalidate the DCACHE */ - DCACHE_InvalidateByRange((uint32_t)handle->data->rxData, - (handle->data->blockSize) * (handle->data->blockCount)); - } -#endif } } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_usdhc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_usdhc.h index b7799d221c..4139dfd8bd 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_usdhc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_usdhc.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -43,8 +47,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief Driver version 2.2.1. */ -#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 1U)) +/*! @brief Driver version 2.2.3. */ +#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 3U)) /*@}*/ /*! @brief Maximum block count can be set one time */ @@ -60,7 +64,7 @@ enum _usdhc_status kStatus_USDHC_DMADataAddrNotAlign = MAKE_STATUS(kStatusGroup_USDHC, 4U), /*!< data address not align */ kStatus_USDHC_ReTuningRequest = MAKE_STATUS(kStatusGroup_USDHC, 5U), /*!< re-tuning request */ kStatus_USDHC_TuningError = MAKE_STATUS(kStatusGroup_USDHC, 6U), /*!< tuning error */ - + kStatus_USDHC_NotSupport = MAKE_STATUS(kStatusGroup_USDHC, 7U), /*!< not support */ }; /*! @brief Host controller capabilities flag mask */ @@ -261,13 +265,21 @@ enum _usdhc_adma_error_status_flag * * This state is the detail state when ADMA error has occurred. */ -typedef enum _usdhc_adma_error_state +enum _usdhc_adma_error_state { - kUSDHC_AdmaErrorStateStopDma = 0x00U, /*!< Stop DMA */ - kUSDHC_AdmaErrorStateFetchDescriptor = 0x01U, /*!< Fetch descriptor */ - kUSDHC_AdmaErrorStateChangeAddress = 0x02U, /*!< Change address */ - kUSDHC_AdmaErrorStateTransferData = 0x03U, /*!< Transfer data */ -} usdhc_adma_error_state_t; + kUSDHC_AdmaErrorStateStopDma = + 0x00U, /*!< Stop DMA, previous location set in the ADMA system address is error address */ + kUSDHC_AdmaErrorStateFetchDescriptor = + 0x01U, /*!< Fetch descriptor, current location set in the ADMA system address is error address */ + kUSDHC_AdmaErrorStateChangeAddress = 0x02U, /*!< Change address, no DMA error is occured */ + kUSDHC_AdmaErrorStateTransferData = + 0x03U, /*!< Transfer data, previous location set in the ADMA system address is error address */ + kUSDHC_AdmaErrorStateInvalidLength = 0x04U, /*!< Invalid length in ADMA descriptor */ + kUSDHC_AdmaErrorStateInvalidDescriptor = 0x08U, /*!< Invalid descriptor fetched by ADMA */ + + kUSDHC_AdmaErrorState = kUSDHC_AdmaErrorStateInvalidLength | kUSDHC_AdmaErrorStateInvalidDescriptor | + kUSDHC_AdmaErrorStateFetchDescriptor, /*!< ADMA error state */ +}; /*! @brief Force event mask */ enum _usdhc_force_event @@ -800,6 +812,7 @@ static inline void USDHC_EnableInternalDMA(USDHC_Type *base, bool enable) else { base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; + base->PROT_CTRL &= ~USDHC_PROT_CTRL_DMASEL_MASK; } } @@ -902,7 +915,7 @@ static inline uint32_t USDHC_GetAutoCommand12ErrorStatusFlags(USDHC_Type *base) */ static inline uint32_t USDHC_GetAdmaErrorStatusFlags(USDHC_Type *base) { - return base->ADMA_ERR_STATUS; + return base->ADMA_ERR_STATUS & 0xFU; } /*! @@ -1005,7 +1018,7 @@ static inline void USDHC_SetDataBusWidth(USDHC_Type *base, usdhc_data_bus_width_ } /*! - * @brief Fills the the data port. + * @brief Fills the data port. * * This function is used to implement the data transfer by Data Port instead of DMA. * @@ -1329,18 +1342,7 @@ static inline uint32_t USDHC_CheckTuningError(USDHC_Type *base) * @param enable/disable flag * @param nibble position */ -static inline void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos) -{ - if (enable) - { - base->MIX_CTRL &= ~USDHC_MIX_CTRL_NIBBLE_POS_MASK; - base->MIX_CTRL |= (USDHC_MIX_CTRL_DDR_EN_MASK | USDHC_MIX_CTRL_NIBBLE_POS(nibblePos)); - } - else - { - base->MIX_CTRL &= ~USDHC_MIX_CTRL_DDR_EN_MASK; - } -} +void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos); /*! * @brief the enable/disable HS400 mode diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_wdog.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_wdog.c index c359a5c4af..b1cc4eb1fb 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_wdog.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_wdog.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -30,6 +34,12 @@ #include "fsl_wdog.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.wdog01" +#endif + + /******************************************************************************* * Variables ******************************************************************************/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_wdog.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_wdog.h index d2bb5576d3..508714bbe1 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_wdog.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_wdog.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbara.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbara.c index b21318064d..3a8d903565 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbara.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbara.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -34,6 +38,12 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xbara" +#endif + + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbara.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbara.h index b12b0edb9e..98410a198b 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbara.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbara.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -167,7 +171,7 @@ void XBARA_SetSignalsConnection(XBARA_Type *base, xbar_input_signal_t input, xba uint32_t XBARA_GetStatusFlags(XBARA_Type *base); /*! - * @brief Clears the the edge detection status flags of relative mask. + * @brief Clears the edge detection status flags of relative mask. * * @param base XBARA peripheral address. * @param mask the status flags to clear. diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbarb.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbarb.c index cd30bb4d61..627b0ab91f 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbarb.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbarb.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -34,6 +38,12 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xbarb" +#endif + + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbarb.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbarb.h index b7e8818d1f..38e687fb06 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbarb.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbarb.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/mbed_rtx.h b/targets/TARGET_NXP/mbed_rtx.h index abc4119529..f21e3f1ebc 100644 --- a/targets/TARGET_NXP/mbed_rtx.h +++ b/targets/TARGET_NXP/mbed_rtx.h @@ -17,6 +17,8 @@ #ifndef MBED_MBED_RTX_H #define MBED_MBED_RTX_H +#include + #if defined(TARGET_LPC11U68) #ifndef INITIAL_SP @@ -93,10 +95,30 @@ #define INITIAL_SP (0x20028000UL) #endif -#elif defined(TARGET_MIMXRT1050) +#elif defined(TARGET_MIMXRT1050_EVK) -#ifndef INITIAL_SP -#define INITIAL_SP (0x20020000UL) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + extern uint32_t Image$$RW_IRAM1$$ZI$$Base[]; + extern uint32_t Image$$RW_IRAM1$$ZI$$Length[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Length[]; + #define HEAP_START ((unsigned char*) Image$$RW_IRAM1$$ZI$$Base) + #define HEAP_SIZE ((uint32_t) Image$$RW_IRAM1$$ZI$$Length) + #define ISR_STACK_START ((unsigned char*)Image$$ARM_LIB_STACK$$ZI$$Base) + #define ISR_STACK_SIZE ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Length) +#elif defined(__GNUC__) + extern uint32_t __StackTop[]; + extern uint32_t __StackLimit[]; + extern uint32_t __end__; + extern uint32_t __HeapLimit[]; + #define HEAP_START ((unsigned char*)&__end__) + #define HEAP_SIZE ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START)) + #define ISR_STACK_START ((unsigned char*)__StackLimit) + #define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit)) +#elif defined(__ICCARM__) + /* No region declarations needed */ +#else + #error "no toolchain defined" #endif #endif diff --git a/targets/targets.json b/targets/targets.json index 816431e733..8bed7c342e 100755 --- a/targets/targets.json +++ b/targets/targets.json @@ -750,7 +750,7 @@ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], "extra_labels": ["NXP", "MCUXpresso_MCUS", "EVK", "MIMXRT1050", "IMX"], "is_disk_virtual": true, - "macros": ["CPU_MIMXRT1052DVL6A", "FSL_RTOS_MBED"], + "macros": ["CPU_MIMXRT1052DVL6B", "FSL_RTOS_MBED", "XIP_BOOT_HEADER_ENABLE=1", "XIP_EXTERNAL_FLASH=1", "XIP_BOOT_HEADER_DCD_ENABLE=1"], "inherits": ["Target"], "detect_code": ["0227"], "device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2CSLAVE", "ERROR_RED", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"], diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json index 9600b6890a..7c1bc3d5d3 100644 --- a/tools/export/iar/iar_definitions.json +++ b/tools/export/iar/iar_definitions.json @@ -4,7 +4,7 @@ }, "STM32L433RC": { "OGChipSelectEditMenu": "STM32L433RC\tST STM32L433RC" - }, + }, "STM32L496AG": { "OGChipSelectEditMenu": "STM32L496AG\tST STM32L496AG" }, @@ -86,9 +86,6 @@ "MKW41Z512xxx4": { "OGChipSelectEditMenu": "MKW41Z512xxx4\tNXP MKW41Z512xxx4" }, - "MIMXRT1052xxx6A": { - "OGChipSelectEditMenu": "MIMXRT1052xxx6A\tNXP MIMXRT1052xxx6A" - }, "LPC54114J256BD64": { "OGChipSelectEditMenu": "LPC54114J256_M4\tNXP LPC54114J256_M4" },