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Merge pull request #10534 from OpenNuvoton/nuvoton_nano130_fix-vectab-virtual 

NANO130: Fix optimization error with NVIC_SetVector/NVIC_GetVector on ARMC6
pull/10573/head
Martin Kojtal 2019-05-13 14:14:48 +01:00 committed by GitHub
parent 571caad59e fcab482357
commit 22d78b40de
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2 changed files with 18 additions and 9 deletions
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3
targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_IAR/NANO130.icf
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@ -19,6 +19,7 @@ define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__]; define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
define block ROMVEC with alignment = 8 { readonly section .intvec };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
@ -26,7 +27,7 @@ define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite }; initialize by copy { readwrite };
do not initialize { section .noinit }; do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place at address mem:__ICFEDIT_intvec_start__ { block ROMVEC };
place in ROM_region { readonly }; place in ROM_region { readonly };
place at start of IRAM_region { block CSTACK }; place at start of IRAM_region { block CSTACK };

24
targets/TARGET_NUVOTON/TARGET_NANO100/device/cmsis_nvic.h
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@ -23,18 +23,26 @@
#define NVIC_USER_IRQ_NUMBER 32 #define NVIC_USER_IRQ_NUMBER 32
#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER) #define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) /* Avoid optimization error on e.g. ARMC6
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base) *
* If NVIC_FLASH_VECTOR_ADDRESS is directly defined as 0, the compiler would see it
* as NULL, and deliberately optimize NVIC_GetVector to an undefined instruction -
* trapping because we're accessing an array at NULL.
*
* A suggested solution by Arm is to define NVIC_FLASH_VECTOR_ADDRESS as a symbol
* instead to avoid such unwanted optimization.
*/
#if defined(__ARMCC_VERSION)
extern uint32_t Image$$ER_IROM1$$Base;
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IROM1$$Base)
#elif defined(__ICCARM__) #elif defined(__ICCARM__)
# pragma section = "IRAMVEC" #pragma section = "ROMVEC"
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) __section_begin("IRAMVEC")) #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t) __section_begin("ROMVEC"))
#elif defined(__GNUC__) #elif defined(__GNUC__)
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__) extern uint32_t __vector_table;
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t) &__vector_table)
#endif #endif
#define NVIC_FLASH_VECTOR_ADDRESS 0
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif