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mbed-os
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Merge pull request #3 from mbedmicro/master 

Update my fork with original
pull/1172/head
David H 2015-06-09 17:37:41 +10:00
parent 060195772c 8902229372
commit 2234248149
253 changed files with 40542 additions and 2096 deletions
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1
README.md
View File

@ -30,6 +30,7 @@ NXP:
* [mbed LPC11U24](http://developer.mbed.org/platforms/mbed-LPC11U24/) (Cortex-M0)
* [EA LPC11U35](http://developer.mbed.org/platforms/EA-LPC11U35/) (Cortex-M0)
* mbed LPC2368 (ARM7TDMI-S)
* LPC2460 (ARM7TDMI-S)
* LPC810 (Cortex-M0+)
* [LPC812](http://developer.mbed.org/platforms/NXP-LPC800-MAX/) (Cortex-M0+)
* [EA LPC4088](http://developer.mbed.org/platforms/EA-LPC4088/) (Cortex-M4F)

2
libraries/USBDevice/USBDevice/USBEndpoints.h
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@ -37,7 +37,7 @@ typedef enum {
} EP_STATUS;
/* Include configuration for specific target */
#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC2460) || defined(TARGET_LPC4088_DM)
#include "USBEndpoints_LPC17_LPC23.h"
#elif defined(TARGET_LPC11UXX) || defined(TARGET_LPC1347) || defined (TARGET_LPC11U6X) || defined (TARGET_LPC1549)
#include "USBEndpoints_LPC11U.h"

4
libraries/USBDevice/USBDevice/USBEndpoints_Maxim.h
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@ -85,6 +85,10 @@
#define EPINT_IN (EP4IN)
#define EPINT_OUT_callback EP3_OUT_callback
#define EPINT_IN_callback EP4_IN_callback
/* Isochronous endpoints */
/* NOT SUPPORTED - use invalid endpoint number to prevent built errors */
#define EPISO_OUT (EP0OUT)
#define EPISO_IN (EP0IN)
#define MAX_PACKET_SIZE_EPBULK (64)
#define MAX_PACKET_SIZE_EPINT (64)

2
libraries/USBDevice/USBDevice/USBHAL_LPC17.cpp
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@ -16,7 +16,7 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC2460)
#include "USBHAL.h"

2
libraries/USBDevice/USBSerial/CircBuffer.h
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@ -57,7 +57,7 @@ private:
volatile uint16_t write;
volatile uint16_t read;
static const int size = Size+1; //a modern optimizer should be able to remove this so it uses no ram.
T buf[Size];
T buf[Size+1];
};
#endif

2
libraries/USBHost/USBHost/USBHALHost_LPC17.cpp
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@ -14,7 +14,7 @@
* limitations under the License.
*/
#if defined(TARGET_LPC1768)
#if defined(TARGET_LPC1768) || defined(TARGET_LPC2460)
#include "mbed.h"
#include "USBHALHost.h"

6
libraries/mbed/api/CircularBuffer.h
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@ -88,9 +88,9 @@ public:
private:
T _pool[BufferSize];
CounterType _head;
CounterType _tail;
bool _full;
volatile CounterType _head;
volatile CounterType _tail;
volatile bool _full;
};
}

17
libraries/mbed/api/SPI.h
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@ -45,10 +45,21 @@ namespace mbed {
*
* #include "mbed.h"
*
* // hardware ssel (where applicable)
* //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
*
* // software ssel
* SPI device(p5, p6, p7); // mosi, miso, sclk
* DigitalOut cs(p8); // ssel
*
* int main() {
* // hardware ssel (where applicable)
* //int response = device.write(0xFF);
*
* // software ssel
* cs = 0;
* int response = device.write(0xFF);
* cs = 1;
* }
* @endcode
*/
@ -57,17 +68,15 @@ class SPI {
public:
/** Create a SPI master connected to the specified pins
*
* Pin Options:
* (5, 6, 7) or (11, 12, 13)
*
* mosi or miso can be specfied as NC if not used
*
* @param mosi SPI Master Out, Slave In pin
* @param miso SPI Master In, Slave Out pin
* @param sclk SPI Clock pin
* @param ssel SPI chip select pin
*/
SPI(PinName mosi, PinName miso, PinName sclk, PinName _unused=NC);
SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel=NC);
/** Configure the data transmission format
*

4
libraries/mbed/api/SPISlave.h
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@ -53,9 +53,6 @@ class SPISlave {
public:
/** Create a SPI slave connected to the specified pins
*
* Pin Options:
* (5, 6, 7i, 8) or (11, 12, 13, 14)
*
* mosi or miso can be specfied as NC if not used
*
@ -63,7 +60,6 @@ public:
* @param miso SPI Master In, Slave Out pin
* @param sclk SPI Clock pin
* @param ssel SPI chip select pin
* @param name (optional) A string to identify the object
*/
SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);

2
libraries/mbed/api/Ticker.h
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@ -60,7 +60,7 @@ public:
Ticker() : TimerEvent() {
}
Ticker(const ticker_data_t *const data) : TimerEvent(data) {
Ticker(const ticker_data_t *data) : TimerEvent(data) {
}
/** Attach a function to be called by the Ticker, specifiying the interval in seconds

4
libraries/mbed/api/Timer.h
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@ -46,7 +46,7 @@ class Timer {
public:
Timer();
Timer(const ticker_data_t *const data);
Timer(const ticker_data_t *data);
/** Start the timer
*/
@ -83,7 +83,7 @@ protected:
int _running; // whether the timer is running
unsigned int _start; // the start time of the latest slice
int _time; // any accumulated time from previous slices
const ticker_data_t *const _ticker_data;
const ticker_data_t *_ticker_data;
};
} // namespace mbed

2
libraries/mbed/api/TimerEvent.h
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@ -47,7 +47,7 @@ protected:
ticker_event_t event;
const ticker_data_t *const _ticker_data;
const ticker_data_t *_ticker_data;
};
} // namespace mbed

2
libraries/mbed/api/mbed.h
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@ -16,7 +16,7 @@
#ifndef MBED_H
#define MBED_H
#define MBED_LIBRARY_VERSION 99
#define MBED_LIBRARY_VERSION 100
#include "platform.h"

4
libraries/mbed/common/SPI.cpp
View File

@ -23,7 +23,7 @@ namespace mbed {
CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
#endif
SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName _unused) :
SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
_spi(),
#if DEVICE_SPI_ASYNCH
_irq(this),
@ -32,7 +32,7 @@ SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName _unused) :
_bits(8),
_mode(0),
_hz(1000000) {
spi_init(&_spi, mosi, miso, sclk, NC);
spi_init(&_spi, mosi, miso, sclk, ssel);
spi_format(&_spi, _bits, _mode, 0);
spi_frequency(&_spi, _hz);
}

2
libraries/mbed/common/Timer.cpp
View File

@ -23,7 +23,7 @@ Timer::Timer() : _running(), _start(), _time(), _ticker_data(get_us_ticker_data(
reset();
}
Timer::Timer(const ticker_data_t *const data) : _running(), _start(), _time(), _ticker_data(data) {
Timer::Timer(const ticker_data_t *data) : _running(), _start(), _time(), _ticker_data(data) {
reset();
}

972
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/LPC24xx.h Normal file
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@ -0,0 +1,972 @@
/* mbed Microcontroller Library - LPC24xx CMSIS-like structs
* Copyright (C) 2009-2015 ARM Limited. All rights reserved.
*
* An LPC24xx header file, based on LPC23xx.h
*/
#ifndef __LPC24xx_H
#define __LPC24xx_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** LPC23xx Specific Interrupt Numbers *******************************************************/
WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
TIMER0_IRQn = 4, /*!< Timer0 Interrupt */
TIMER1_IRQn = 5, /*!< Timer1 Interrupt */
UART0_IRQn = 6, /*!< UART0 Interrupt */
UART1_IRQn = 7, /*!< UART1 Interrupt */
PWM0_IRQn = 8, /*!< PWM0 Interrupt */
PWM1_IRQn = 8, /*!< PWM1 Interrupt */
I2C0_IRQn = 9, /*!< I2C0 Interrupt */
SPI_IRQn = 10, /*!< SPI Interrupt */
SSP0_IRQn = 10, /*!< SSP0 Interrupt */
SSP1_IRQn = 11, /*!< SSP1 Interrupt */
PLL0_IRQn = 12, /*!< PLL0 Lock (Main PLL) Interrupt */
RTC_IRQn = 13, /*!< Real Time Clock Interrupt */
EINT0_IRQn = 14, /*!< External Interrupt 0 Interrupt */
EINT1_IRQn = 15, /*!< External Interrupt 1 Interrupt */
EINT2_IRQn = 16, /*!< External Interrupt 2 Interrupt */
EINT3_IRQn = 17, /*!< External Interrupt 3 Interrupt */
ADC_IRQn = 18, /*!< A/D Converter Interrupt */
I2C1_IRQn = 19, /*!< I2C1 Interrupt */
BOD_IRQn = 20, /*!< Brown-Out Detect Interrupt */
ENET_IRQn = 21, /*!< Ethernet Interrupt */
USB_IRQn = 22, /*!< USB Interrupt */
CAN_IRQn = 23, /*!< CAN Interrupt */
SDMMC_IRQn = 24, /*!< SD/MMC Interrupt */
DMA_IRQn = 25, /*!< General Purpose DMA Interrupt */
TIMER2_IRQn = 26, /*!< Timer2 Interrupt */
TIMER3_IRQn = 27, /*!< Timer3 Interrupt */
UART2_IRQn = 28, /*!< UART2 Interrupt */
UART3_IRQn = 29, /*!< UART3 Interrupt */
I2C2_IRQn = 30, /*!< I2C2 Interrupt */
I2S_IRQn = 31, /*!< I2S Interrupt */
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the ARM7 Processor and Core Peripherals */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#include <core_arm7.h>
#include "system_LPC24xx.h" /* System Header */
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/*------------- Vector Interupt Controler (VIC) ------------------------------*/
typedef struct
{
__I uint32_t IRQStatus;
__I uint32_t FIQStatus;
__I uint32_t RawIntr;
__IO uint32_t IntSelect;
__IO uint32_t IntEnable;
__O uint32_t IntEnClr;
__IO uint32_t SoftInt;
__O uint32_t SoftIntClr;
__IO uint32_t Protection;
__IO uint32_t SWPriorityMask;
__IO uint32_t RESERVED0[54];
__IO uint32_t VectAddr[32];
__IO uint32_t RESERVED1[32];
__IO uint32_t VectPriority[32];
__IO uint32_t RESERVED2[800];
__IO uint32_t Address;
} LPC_VIC_TypeDef;
/*------------- System Control (SC) ------------------------------------------*/
typedef struct
{
__IO uint32_t MAMCR;
__IO uint32_t MAMTIM;
uint32_t RESERVED0[14];
__IO uint32_t MEMMAP;
uint32_t RESERVED1[15];
__IO uint32_t PLL0CON; /* Clocking and Power Control */
__IO uint32_t PLL0CFG;
__I uint32_t PLL0STAT;
__O uint32_t PLL0FEED;
uint32_t RESERVED2[12];
__IO uint32_t PCON;
__IO uint32_t PCONP;
uint32_t RESERVED3[15];
__IO uint32_t CCLKCFG;
__IO uint32_t USBCLKCFG;
__IO uint32_t CLKSRCSEL;
uint32_t RESERVED4[12];
__IO uint32_t EXTINT; /* External Interrupts */
__IO uint32_t INTWAKE;
__IO uint32_t EXTMODE;
__IO uint32_t EXTPOLAR;
uint32_t RESERVED6[12];
__IO uint32_t RSID; /* Reset */
__IO uint32_t CSPR;
__IO uint32_t AHBCFG1;
__IO uint32_t AHBCFG2;
uint32_t RESERVED7[4];
__IO uint32_t SCS; /* Syscon Miscellaneous Registers */
__IO uint32_t IRCTRIM; /* Clock Dividers */
__IO uint32_t PCLKSEL0;
__IO uint32_t PCLKSEL1;
uint32_t RESERVED8[4];
__IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
uint32_t RESERVED9;
// __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
} LPC_SC_TypeDef;
/*------------- Pin Connect Block (PINCON) -----------------------------------*/
typedef struct
{
__IO uint32_t PINSEL0;
__IO uint32_t PINSEL1;
__IO uint32_t PINSEL2;
__IO uint32_t PINSEL3;
__IO uint32_t PINSEL4;
__IO uint32_t PINSEL5;
__IO uint32_t PINSEL6;
__IO uint32_t PINSEL7;
__IO uint32_t PINSEL8;
__IO uint32_t PINSEL9;
__IO uint32_t PINSEL10;
uint32_t RESERVED0[5];
__IO uint32_t PINMODE0;
__IO uint32_t PINMODE1;
__IO uint32_t PINMODE2;
__IO uint32_t PINMODE3;
__IO uint32_t PINMODE4;
__IO uint32_t PINMODE5;
__IO uint32_t PINMODE6;
__IO uint32_t PINMODE7;
__IO uint32_t PINMODE8;
__IO uint32_t PINMODE9;
__IO uint32_t PINMODE_OD0;
__IO uint32_t PINMODE_OD1;
__IO uint32_t PINMODE_OD2;
__IO uint32_t PINMODE_OD3;
__IO uint32_t PINMODE_OD4;
} LPC_PINCON_TypeDef;
#define PCTIM0 1
#define PCTIM1 2
#define PCUART0 3
#define PCUART1 4
#define PCPWM1 6
#define PCI2C0 7
#define PCSPI 8
#define PCRTC 9
#define PCSSP1 10
#define PCEMC 11
#define PCADC 12
#define PCAN1 13
#define PCAN2 14
#define PCI2C1 19
#define PCSSP0 21
#define PCTIM2 22
#define PCTIM3 23
#define PCUART2 24
#define PCUART3 25
#define PCI2C2 26
#define PCI2S 27
#define PCSDC 28
#define PCGPDMA 29
#define PCENET 30
#define PCUSB 31
/*------------- General Purpose Input/Output (GPIO) --------------------------*/
typedef struct
{
__IO uint32_t FIODIR;
uint32_t RESERVED0[3];
__IO uint32_t FIOMASK;
__IO uint32_t FIOPIN;
__IO uint32_t FIOSET;
__O uint32_t FIOCLR;
} LPC_GPIO_TypeDef;
typedef struct
{
__I uint32_t IntStatus;
__I uint32_t IO0IntStatR;
__I uint32_t IO0IntStatF;
__O uint32_t IO0IntClr;
__IO uint32_t IO0IntEnR;
__IO uint32_t IO0IntEnF;
uint32_t RESERVED0[3];
__I uint32_t IO2IntStatR;
__I uint32_t IO2IntStatF;
__O uint32_t IO2IntClr;
__IO uint32_t IO2IntEnR;
__IO uint32_t IO2IntEnF;
} LPC_GPIOINT_TypeDef;
/*------------- Timer (TIM) --------------------------------------------------*/
typedef struct
{
__IO uint32_t IR;
__IO uint32_t TCR;
__IO uint32_t TC;
__IO uint32_t PR;
__IO uint32_t PC;
__IO uint32_t MCR;
__IO uint32_t MR0;
__IO uint32_t MR1;
__IO uint32_t MR2;
__IO uint32_t MR3;
__IO uint32_t CCR;
__I uint32_t CR0;
__I uint32_t CR1;
uint32_t RESERVED0[2];
__IO uint32_t EMR;
uint32_t RESERVED1[12];
__IO uint32_t CTCR;
} LPC_TIM_TypeDef;
/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
typedef struct
{
__IO uint32_t IR;
__IO uint32_t TCR;
__IO uint32_t TC;
__IO uint32_t PR;
__IO uint32_t PC;
__IO uint32_t MCR;
__IO uint32_t MR0;
__IO uint32_t MR1;
__IO uint32_t MR2;
__IO uint32_t MR3;
__IO uint32_t CCR;
__I uint32_t CR0;
__I uint32_t CR1;
__I uint32_t CR2;
__I uint32_t CR3;
uint32_t RESERVED0;
__IO uint32_t MR4;
__IO uint32_t MR5;
__IO uint32_t MR6;
__IO uint32_t PCR;
__IO uint32_t LER;
uint32_t RESERVED1[7];
__IO uint32_t CTCR;
} LPC_PWM_TypeDef;
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct
{
union {
__I uint8_t RBR;
__O uint8_t THR;
__IO uint8_t DLL;
uint32_t RESERVED0;
};
union {
__IO uint8_t DLM;
__IO uint32_t IER;
};
union {
__I uint32_t IIR;
__O uint8_t FCR;
};
__IO uint8_t LCR;
uint8_t RESERVED1[7];
__IO uint8_t LSR;
uint8_t RESERVED2[7];
__IO uint8_t SCR;
uint8_t RESERVED3[3];
__IO uint32_t ACR;
__IO uint8_t ICR;
uint8_t RESERVED4[3];
__IO uint8_t FDR;
uint8_t RESERVED5[7];
__IO uint8_t TER;
uint8_t RESERVED6[27];
__IO uint8_t RS485CTRL;
uint8_t RESERVED7[3];
__IO uint8_t ADRMATCH;
} LPC_UART_TypeDef;
typedef struct
{
union {
__I uint8_t RBR;
__O uint8_t THR;
__IO uint8_t DLL;
uint32_t RESERVED0;
};
union {
__IO uint8_t DLM;
__IO uint32_t IER;
};
union {
__I uint32_t IIR;
__O uint8_t FCR;
};
__IO uint8_t LCR;
uint8_t RESERVED1[3];
__IO uint8_t MCR;
uint8_t RESERVED2[3];
__IO uint8_t LSR;
uint8_t RESERVED3[3];
__IO uint8_t MSR;
uint8_t RESERVED4[3];
__IO uint8_t SCR;
uint8_t RESERVED5[3];
__IO uint32_t ACR;
uint32_t RESERVED6;
__IO uint32_t FDR;
uint32_t RESERVED7;
__IO uint8_t TER;
uint8_t RESERVED8[27];
__IO uint8_t RS485CTRL;
uint8_t RESERVED9[3];
__IO uint8_t ADRMATCH;
uint8_t RESERVED10[3];
__IO uint8_t RS485DLY;
} LPC_UART1_TypeDef;
/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
typedef struct
{
__IO uint32_t SPCR;
__I uint32_t SPSR;
__IO uint32_t SPDR;
__IO uint32_t SPCCR;
uint32_t RESERVED0[3];
__IO uint32_t SPINT;
} LPC_SPI_TypeDef;
/*------------- Synchronous Serial Communication (SSP) -----------------------*/
typedef struct
{
__IO uint32_t CR0;
__IO uint32_t CR1;
__IO uint32_t DR;
__I uint32_t SR;
__IO uint32_t CPSR;
__IO uint32_t IMSC;
__IO uint32_t RIS;
__IO uint32_t MIS;
__IO uint32_t ICR;
__IO uint32_t DMACR;
} LPC_SSP_TypeDef;
/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
typedef struct
{
__IO uint32_t I2CONSET;
__I uint32_t I2STAT;
__IO uint32_t I2DAT;
__IO uint32_t I2ADR0;
__IO uint32_t I2SCLH;
__IO uint32_t I2SCLL;
__O uint32_t I2CONCLR;
__IO uint32_t MMCTRL;
__IO uint32_t I2ADR1;
__IO uint32_t I2ADR2;
__IO uint32_t I2ADR3;
__I uint32_t I2DATA_BUFFER;
__IO uint32_t I2MASK0;
__IO uint32_t I2MASK1;
__IO uint32_t I2MASK2;
__IO uint32_t I2MASK3;
} LPC_I2C_TypeDef;
/*------------- Inter IC Sound (I2S) -----------------------------------------*/
typedef struct
{
__IO uint32_t I2SDAO;
__I uint32_t I2SDAI;
__O uint32_t I2STXFIFO;
__I uint32_t I2SRXFIFO;
__I uint32_t I2SSTATE;
__IO uint32_t I2SDMA1;
__IO uint32_t I2SDMA2;
__IO uint32_t I2SIRQ;
__IO uint32_t I2STXRATE;
__IO uint32_t I2SRXRATE;
__IO uint32_t I2STXBITRATE;
__IO uint32_t I2SRXBITRATE;
__IO uint32_t I2STXMODE;
__IO uint32_t I2SRXMODE;
} LPC_I2S_TypeDef;
/*------------- Real-Time Clock (RTC) ----------------------------------------*/
typedef struct
{
__IO uint8_t ILR;
uint8_t RESERVED0[3];
__IO uint8_t CTC;
uint8_t RESERVED1[3];
__IO uint8_t CCR;
uint8_t RESERVED2[3];
__IO uint8_t CIIR;
uint8_t RESERVED3[3];
__IO uint8_t AMR;
uint8_t RESERVED4[3];
__I uint32_t CTIME0;
__I uint32_t CTIME1;
__I uint32_t CTIME2;
__IO uint8_t SEC;
uint8_t RESERVED5[3];
__IO uint8_t MIN;
uint8_t RESERVED6[3];
__IO uint8_t HOUR;
uint8_t RESERVED7[3];
__IO uint8_t DOM;
uint8_t RESERVED8[3];
__IO uint8_t DOW;
uint8_t RESERVED9[3];
__IO uint16_t DOY;
uint16_t RESERVED10;
__IO uint8_t MONTH;
uint8_t RESERVED11[3];
__IO uint16_t YEAR;
uint16_t RESERVED12;
__IO uint32_t CALIBRATION;
__IO uint32_t GPREG0;
__IO uint32_t GPREG1;
__IO uint32_t GPREG2;
__IO uint32_t GPREG3;
__IO uint32_t GPREG4;
__IO uint8_t WAKEUPDIS;
uint8_t RESERVED13[3];
__IO uint8_t PWRCTRL;
uint8_t RESERVED14[3];
__IO uint8_t ALSEC;
uint8_t RESERVED15[3];
__IO uint8_t ALMIN;
uint8_t RESERVED16[3];
__IO uint8_t ALHOUR;
uint8_t RESERVED17[3];
__IO uint8_t ALDOM;
uint8_t RESERVED18[3];
__IO uint8_t ALDOW;
uint8_t RESERVED19[3];
__IO uint16_t ALDOY;
uint16_t RESERVED20;
__IO uint8_t ALMON;
uint8_t RESERVED21[3];
__IO uint16_t ALYEAR;
uint16_t RESERVED22;
} LPC_RTC_TypeDef;
/*------------- Watchdog Timer (WDT) -----------------------------------------*/
typedef struct
{
__IO uint8_t WDMOD;
uint8_t RESERVED0[3];
__IO uint32_t WDTC;
__O uint8_t WDFEED;
uint8_t RESERVED1[3];
__I uint32_t WDTV;
__IO uint32_t WDCLKSEL;
} LPC_WDT_TypeDef;
/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
typedef struct
{
__IO uint32_t ADCR;
__IO uint32_t ADGDR;
uint32_t RESERVED0;
__IO uint32_t ADINTEN;
__I uint32_t ADDR0;
__I uint32_t ADDR1;
__I uint32_t ADDR2;
__I uint32_t ADDR3;
__I uint32_t ADDR4;
__I uint32_t ADDR5;
__I uint32_t ADDR6;
__I uint32_t ADDR7;
__I uint32_t ADSTAT;
__IO uint32_t ADTRM;
} LPC_ADC_TypeDef;
/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
typedef struct
{
__IO uint32_t DACR;
__IO uint32_t DACCTRL;
__IO uint16_t DACCNTVAL;
} LPC_DAC_TypeDef;
/*------------- Multimedia Card Interface (MCI) ------------------------------*/
typedef struct
{
__IO uint32_t MCIPower; /* Power control */
__IO uint32_t MCIClock; /* Clock control */
__IO uint32_t MCIArgument;
__IO uint32_t MMCCommand;
__I uint32_t MCIRespCmd;
__I uint32_t MCIResponse0;
__I uint32_t MCIResponse1;
__I uint32_t MCIResponse2;
__I uint32_t MCIResponse3;
__IO uint32_t MCIDataTimer;
__IO uint32_t MCIDataLength;
__IO uint32_t MCIDataCtrl;
__I uint32_t MCIDataCnt;
__I uint32_t MCIStatus;
__O uint32_t MCIClear;
__IO uint32_t MCIMask0;
uint32_t RESERVED1[2];
__I uint32_t MCIFifoCnt;
uint32_t RESERVED2[13];
__IO uint32_t MCIFIFO[16];
} LPC_MCI_TypeDef;
/*------------- Controller Area Network (CAN) --------------------------------*/
typedef struct
{
__IO uint32_t mask[512]; /* ID Masks */
} LPC_CANAF_RAM_TypeDef;
typedef struct /* Acceptance Filter Registers */
{
__IO uint32_t AFMR;
__IO uint32_t SFF_sa;
__IO uint32_t SFF_GRP_sa;
__IO uint32_t EFF_sa;
__IO uint32_t EFF_GRP_sa;
__IO uint32_t ENDofTable;
__I uint32_t LUTerrAd;
__I uint32_t LUTerr;
__IO uint32_t FCANIE;
__IO uint32_t FCANIC0;
__IO uint32_t FCANIC1;
} LPC_CANAF_TypeDef;
typedef struct /* Central Registers */
{
__I uint32_t CANTxSR;
__I uint32_t CANRxSR;
__I uint32_t CANMSR;
} LPC_CANCR_TypeDef;
typedef struct /* Controller Registers */
{
__IO uint32_t MOD;
__O uint32_t CMR;
__IO uint32_t GSR;
__I uint32_t ICR;
__IO uint32_t IER;
__IO uint32_t BTR;
__IO uint32_t EWL;
__I uint32_t SR;
__IO uint32_t RFS;
__IO uint32_t RID;
__IO uint32_t RDA;
__IO uint32_t RDB;
__IO uint32_t TFI1;
__IO uint32_t TID1;
__IO uint32_t TDA1;
__IO uint32_t TDB1;
__IO uint32_t TFI2;
__IO uint32_t TID2;
__IO uint32_t TDA2;
__IO uint32_t TDB2;
__IO uint32_t TFI3;
__IO uint32_t TID3;
__IO uint32_t TDA3;
__IO uint32_t TDB3;
} LPC_CAN_TypeDef;
/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
typedef struct /* Common Registers */
{
__I uint32_t DMACIntStat;
__I uint32_t DMACIntTCStat;
__O uint32_t DMACIntTCClear;
__I uint32_t DMACIntErrStat;
__O uint32_t DMACIntErrClr;
__I uint32_t DMACRawIntTCStat;
__I uint32_t DMACRawIntErrStat;
__I uint32_t DMACEnbldChns;
__IO uint32_t DMACSoftBReq;
__IO uint32_t DMACSoftSReq;
__IO uint32_t DMACSoftLBReq;
__IO uint32_t DMACSoftLSReq;
__IO uint32_t DMACConfig;
__IO uint32_t DMACSync;
} LPC_GPDMA_TypeDef;
typedef struct /* Channel Registers */
{
__IO uint32_t DMACCSrcAddr;
__IO uint32_t DMACCDestAddr;
__IO uint32_t DMACCLLI;
__IO uint32_t DMACCControl;
__IO uint32_t DMACCConfig;
} LPC_GPDMACH_TypeDef;
/*------------- Universal Serial Bus (USB) -----------------------------------*/
typedef struct
{
__I uint32_t HcRevision; /* USB Host Registers */
__IO uint32_t HcControl;
__IO uint32_t HcCommandStatus;
__IO uint32_t HcInterruptStatus;
__IO uint32_t HcInterruptEnable;
__IO uint32_t HcInterruptDisable;
__IO uint32_t HcHCCA;
__I uint32_t HcPeriodCurrentED;
__IO uint32_t HcControlHeadED;
__IO uint32_t HcControlCurrentED;
__IO uint32_t HcBulkHeadED;
__IO uint32_t HcBulkCurrentED;
__I uint32_t HcDoneHead;
__IO uint32_t HcFmInterval;
__I uint32_t HcFmRemaining;
__I uint32_t HcFmNumber;
__IO uint32_t HcPeriodicStart;
__IO uint32_t HcLSTreshold;
__IO uint32_t HcRhDescriptorA;
__IO uint32_t HcRhDescriptorB;
__IO uint32_t HcRhStatus;
__IO uint32_t HcRhPortStatus1;
__IO uint32_t HcRhPortStatus2;
uint32_t RESERVED0[40];
__I uint32_t Module_ID;
__I uint32_t OTGIntSt; /* USB On-The-Go Registers */
__IO uint32_t OTGIntEn;
__O uint32_t OTGIntSet;
__O uint32_t OTGIntClr;
__IO uint32_t OTGStCtrl;
__IO uint32_t OTGTmr;
uint32_t RESERVED1[58];
__I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
__IO uint32_t USBDevIntEn;
__O uint32_t USBDevIntClr;
__O uint32_t USBDevIntSet;
__O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
__I uint32_t USBCmdData;
__I uint32_t USBRxData; /* USB Device Transfer Registers */
__O uint32_t USBTxData;
__I uint32_t USBRxPLen;
__O uint32_t USBTxPLen;
__IO uint32_t USBCtrl;
__O uint32_t USBDevIntPri;
__I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
__IO uint32_t USBEpIntEn;
__O uint32_t USBEpIntClr;
__O uint32_t USBEpIntSet;
__O uint32_t USBEpIntPri;
__IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
__O uint32_t USBEpInd;
__IO uint32_t USBMaxPSize;
__I uint32_t USBDMARSt; /* USB Device DMA Registers */
__O uint32_t USBDMARClr;
__O uint32_t USBDMARSet;
uint32_t RESERVED2[9];
__IO uint32_t USBUDCAH;
__I uint32_t USBEpDMASt;
__O uint32_t USBEpDMAEn;
__O uint32_t USBEpDMADis;
__I uint32_t USBDMAIntSt;
__IO uint32_t USBDMAIntEn;
uint32_t RESERVED3[2];
__I uint32_t USBEoTIntSt;
__O uint32_t USBEoTIntClr;
__O uint32_t USBEoTIntSet;
__I uint32_t USBNDDRIntSt;
__O uint32_t USBNDDRIntClr;
__O uint32_t USBNDDRIntSet;
__I uint32_t USBSysErrIntSt;
__O uint32_t USBSysErrIntClr;
__O uint32_t USBSysErrIntSet;
uint32_t RESERVED4[15];
__I uint32_t I2C_RX; /* USB OTG I2C Registers */
__O uint32_t I2C_WO;
__I uint32_t I2C_STS;
__IO uint32_t I2C_CTL;
__IO uint32_t I2C_CLKHI;
__O uint32_t I2C_CLKLO;
uint32_t RESERVED5[823];
union {
__IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
__IO uint32_t OTGClkCtrl;
};
union {
__I uint32_t USBClkSt;
__I uint32_t OTGClkSt;
};
} LPC_USB_TypeDef;
/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
typedef struct
{
__IO uint32_t MAC1; /* MAC Registers */
__IO uint32_t MAC2;
__IO uint32_t IPGT;
__IO uint32_t IPGR;
__IO uint32_t CLRT;
__IO uint32_t MAXF;
__IO uint32_t SUPP;
__IO uint32_t TEST;
__IO uint32_t MCFG;
__IO uint32_t MCMD;
__IO uint32_t MADR;
__O uint32_t MWTD;
__I uint32_t MRDD;
__I uint32_t MIND;
uint32_t RESERVED0[2];
__IO uint32_t SA0;
__IO uint32_t SA1;
__IO uint32_t SA2;
uint32_t RESERVED1[45];
__IO uint32_t Command; /* Control Registers */
__I uint32_t Status;
__IO uint32_t RxDescriptor;
__IO uint32_t RxStatus;
__IO uint32_t RxDescriptorNumber;
__I uint32_t RxProduceIndex;
__IO uint32_t RxConsumeIndex;
__IO uint32_t TxDescriptor;
__IO uint32_t TxStatus;
__IO uint32_t TxDescriptorNumber;
__IO uint32_t TxProduceIndex;
__I uint32_t TxConsumeIndex;
uint32_t RESERVED2[10];
__I uint32_t TSV0;
__I uint32_t TSV1;
__I uint32_t RSV;
uint32_t RESERVED3[3];
__IO uint32_t FlowControlCounter;
__I uint32_t FlowControlStatus;
uint32_t RESERVED4[34];
__IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
__IO uint32_t RxFilterWoLStatus;
__IO uint32_t RxFilterWoLClear;
uint32_t RESERVED5;
__IO uint32_t HashFilterL;
__IO uint32_t HashFilterH;
uint32_t RESERVED6[882];
__I uint32_t IntStatus; /* Module Control Registers */
__IO uint32_t IntEnable;
__O uint32_t IntClear;
__O uint32_t IntSet;
uint32_t RESERVED7;
__IO uint32_t PowerDown;
uint32_t RESERVED8;
__IO uint32_t Module_ID;
} LPC_EMAC_TypeDef;
/*-------------------- External Memory Controller (EMC) ----------------------*/
typedef struct
{
__IO uint32_t EMCControl;
__I uint32_t EMCStatus;
__IO uint32_t EMCConfig;
uint32_t RESERVED1[5];
__IO uint32_t EMCDynamicControl;
__IO uint32_t EMCDynamicRefresh;
__IO uint32_t EMCDynamicReadConfig;
uint32_t RESERVED2;
__IO uint32_t EMCDynamicRP;
__IO uint32_t EMCDynamicRAS;
__IO uint32_t EMCDynamicSREX;
__IO uint32_t EMCDynamicAPR;
__IO uint32_t EMCDynamicDAL;
__IO uint32_t EMCDynamicWR;
__IO uint32_t EMCDynamicRC;
__IO uint32_t EMCDynamicRFC;
__IO uint32_t EMCDynamicXSR;
__IO uint32_t EMCDynamicRRD;
__IO uint32_t EMCDynamicMRD;
uint32_t RESERVED3[9];
__IO uint32_t EMCStaticExtendedWait;
uint32_t RESERVED4[31];
__IO uint32_t EMCDynamicConfig0;
__IO uint32_t EMCDynamicRasCas0;
uint32_t RESERVED5[6];
__IO uint32_t EMCDynamicConfig1;
__IO uint32_t EMCDynamicRasCas1;
uint32_t RESERVED6[6];
__IO uint32_t EMCDynamicConfic2;
__IO uint32_t EMCDynamicRasCas2;
uint32_t RESERVED7[6];
__IO uint32_t EMCDynamicConfig3;
__IO uint32_t EMCDynamicRasCas3;
uint32_t RESERVED8[38];
__IO uint32_t EMCStaticConfig0;
__IO uint32_t EMCStaticWaitWen0;
__IO uint32_t EMCStaticWaitOen0;
__IO uint32_t EMCStaticWaitRd0;
__IO uint32_t EMCStaticWaitPage0;
__IO uint32_t EMCStaticWaitWr0;
__IO uint32_t EMCStaticWaitTurn0;
uint32_t RESERVED9;
__IO uint32_t EMCStaticConfig1;
__IO uint32_t EMCStaticWaitWen1;
__IO uint32_t EMCStaticWaitOen1;
__IO uint32_t EMCStaticWaitRd1;
__IO uint32_t EMCStaticWaitPage1;
__IO uint32_t EMCStaticWaitWr1;
__IO uint32_t EMCStaticWaitTurn1;
uint32_t RESERVED10;
__IO uint32_t EMCStaticConfig2;
__IO uint32_t EMCStaticWaitWen2;
__IO uint32_t EMCStaticWaitOen2;
__IO uint32_t EMCStaticWaitRd2;
__IO uint32_t EMCStaticWaitPage2;
__IO uint32_t EMCStaticWaitWr2;
__IO uint32_t EMCStaticWaitTurn2;
uint32_t RESERVED11;
__IO uint32_t EMCStaticConfig3;
__IO uint32_t EMCStaticWaitWen3;
__IO uint32_t EMCStaticWaitOen3;
__IO uint32_t EMCStaticWaitRd3;
__IO uint32_t EMCStaticWaitPage3;
__IO uint32_t EMCStaticWaitWr3;
__IO uint32_t EMCStaticWaitTurn3;
} LPC_EMC_TypeDef;
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/* Base addresses */
/* AHB Peripheral # 0 */
/*
#define FLASH_BASE (0x00000000UL)
#define RAM_BASE (0x10000000UL)
#define GPIO_BASE (0x2009C000UL)
#define APB0_BASE (0x40000000UL)
#define APB1_BASE (0x40080000UL)
#define AHB_BASE (0x50000000UL)
#define CM3_BASE (0xE0000000UL)
*/
// TODO - #define VIC_BASE_ADDR 0xFFFFF000
#define LPC_WDT_BASE (0xE0000000)
#define LPC_TIM0_BASE (0xE0004000)
#define LPC_TIM1_BASE (0xE0008000)
#define LPC_UART0_BASE (0xE000C000)
#define LPC_UART1_BASE (0xE0010000)
#define LPC_PWM1_BASE (0xE0018000)
#define LPC_I2C0_BASE (0xE001C000)
#define LPC_SPI_BASE (0xE0020000)
#define LPC_RTC_BASE (0xE0024000)
#define LPC_GPIOINT_BASE (0xE0028080)
#define LPC_PINCON_BASE (0xE002C000)
#define LPC_SSP1_BASE (0xE0030000)
#define LPC_ADC_BASE (0xE0034000)
#define LPC_CANAF_RAM_BASE (0xE0038000)
#define LPC_CANAF_BASE (0xE003C000)
#define LPC_CANCR_BASE (0xE0040000)
#define LPC_CAN1_BASE (0xE0044000)
#define LPC_CAN2_BASE (0xE0048000)
#define LPC_I2C1_BASE (0xE005C000)
#define LPC_SSP0_BASE (0xE0068000)
#define LPC_DAC_BASE (0xE006C000)
#define LPC_TIM2_BASE (0xE0070000)
#define LPC_TIM3_BASE (0xE0074000)
#define LPC_UART2_BASE (0xE0078000)
#define LPC_UART3_BASE (0xE007C000)
#define LPC_I2C2_BASE (0xE0080000)
#define LPC_I2S_BASE (0xE0088000)
#define LPC_MCI_BASE (0xE008C000)
#define LPC_SC_BASE (0xE01FC000)
#define LPC_EMAC_BASE (0xFFE00000)
#define LPC_GPDMA_BASE (0xFFE04000)
#define LPC_GPDMACH0_BASE (0xFFE04100)
#define LPC_GPDMACH1_BASE (0xFFE04120)
#define LPC_EMC_BASE (0xFFE08000)
#define LPC_USB_BASE (0xFFE0C000)
#define LPC_VIC_BASE (0xFFFFF000)
/* GPIOs */
#define LPC_GPIO0_BASE (0x3FFFC000)
#define LPC_GPIO1_BASE (0x3FFFC020)
#define LPC_GPIO2_BASE (0x3FFFC040)
#define LPC_GPIO3_BASE (0x3FFFC060)
#define LPC_GPIO4_BASE (0x3FFFC080)
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
#define LPC_SC (( LPC_SC_TypeDef *) LPC_SC_BASE)
#define LPC_GPIO0 (( LPC_GPIO_TypeDef *) LPC_GPIO0_BASE)
#define LPC_GPIO1 (( LPC_GPIO_TypeDef *) LPC_GPIO1_BASE)
#define LPC_GPIO2 (( LPC_GPIO_TypeDef *) LPC_GPIO2_BASE)
#define LPC_GPIO3 (( LPC_GPIO_TypeDef *) LPC_GPIO3_BASE)
#define LPC_GPIO4 (( LPC_GPIO_TypeDef *) LPC_GPIO4_BASE)
#define LPC_WDT (( LPC_WDT_TypeDef *) LPC_WDT_BASE)
#define LPC_TIM0 (( LPC_TIM_TypeDef *) LPC_TIM0_BASE)
#define LPC_TIM1 (( LPC_TIM_TypeDef *) LPC_TIM1_BASE)
#define LPC_TIM2 (( LPC_TIM_TypeDef *) LPC_TIM2_BASE)
#define LPC_TIM3 (( LPC_TIM_TypeDef *) LPC_TIM3_BASE)
#define LPC_UART0 (( LPC_UART_TypeDef *) LPC_UART0_BASE)
#define LPC_UART1 (( LPC_UART1_TypeDef *) LPC_UART1_BASE)
#define LPC_UART2 (( LPC_UART_TypeDef *) LPC_UART2_BASE)
#define LPC_UART3 (( LPC_UART_TypeDef *) LPC_UART3_BASE)
#define LPC_PWM1 (( LPC_PWM_TypeDef *) LPC_PWM1_BASE)
#define LPC_I2C0 (( LPC_I2C_TypeDef *) LPC_I2C0_BASE)
#define LPC_I2C1 (( LPC_I2C_TypeDef *) LPC_I2C1_BASE)
#define LPC_I2C2 (( LPC_I2C_TypeDef *) LPC_I2C2_BASE)
#define LPC_I2S (( LPC_I2S_TypeDef *) LPC_I2S_BASE)
#define LPC_SPI (( LPC_SPI_TypeDef *) LPC_SPI_BASE)
#define LPC_RTC (( LPC_RTC_TypeDef *) LPC_RTC_BASE)
#define LPC_GPIOINT (( LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE)
#define LPC_PINCON (( LPC_PINCON_TypeDef *) LPC_PINCON_BASE)
#define LPC_SSP0 (( LPC_SSP_TypeDef *) LPC_SSP0_BASE)
#define LPC_SSP1 (( LPC_SSP_TypeDef *) LPC_SSP1_BASE)
#define LPC_ADC (( LPC_ADC_TypeDef *) LPC_ADC_BASE)
#define LPC_DAC (( LPC_DAC_TypeDef *) LPC_DAC_BASE)
#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
#define LPC_CANAF (( LPC_CANAF_TypeDef *) LPC_CANAF_BASE)
#define LPC_CANCR (( LPC_CANCR_TypeDef *) LPC_CANCR_BASE)
#define LPC_CAN1 (( LPC_CAN_TypeDef *) LPC_CAN1_BASE)
#define LPC_CAN2 (( LPC_CAN_TypeDef *) LPC_CAN2_BASE)
#define LPC_MCI (( LPC_MCI_TypeDef *) LPC_MCI_BASE)
#define LPC_EMAC (( LPC_EMAC_TypeDef *) LPC_EMAC_BASE)
#define LPC_GPDMA (( LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE)
#define LPC_GPDMACH0 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE)
#define LPC_GPDMACH1 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE)
#define LPC_USB (( LPC_USB_TypeDef *) LPC_USB_BASE)
#define LPC_VIC (( LPC_VIC_TypeDef *) LPC_VIC_BASE)
#define LPC_EMC (( LPC_EMC_TypeDef *) LPC_EMC_BASE)
#ifdef __cplusplus
}
#endif
#endif // __LPC24xx_H

210
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/LPC2460.ld Normal file
View File

@ -0,0 +1,210 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(vectors)
/* Memory Definitions: */
MEMORY
{
Flash (rx) : ORIGIN = 0xA0001000, LENGTH = 512k
Ram (rwx) : ORIGIN = 0x40000040, LENGTH = 64k - 0x40
UsbRam (rw) : ORIGIN = 0x7FD00000, LENGTH = 8k
EthRam (rw) : ORIGIN = 0x7FE00000, LENGTH = 16k
CanRam (rw) : ORIGIN = 0xE0038000, LENGTH = 2k
BatRam (rw) : ORIGIN = 0xE0084000, LENGTH = 2k
}
/* Stack sizes: */
UND_Stack_Size = 64;
SVC_Stack_Size = 64;
ABT_Stack_Size = 64;
FIQ_Stack_Size = 64;
IRQ_Stack_Size = 64;
User_Stack_Size = 4096;
Stack_Size_Total = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size + User_Stack_Size;
/* Stack tops for each mode: */
__und_stack_top__ = __stacks_top__;
__abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ;
__fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ;
__irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ;
__svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ;
__usr_stack_top__ = __svc_stack_top__ - User_Stack_Size ;
/* C-accessible symbols for memory address ranges: */
__FLASH_segment_start__ = ORIGIN( Flash );
__FLASH_segment_end__ = ORIGIN( Flash ) + LENGTH( Flash );
__SRAM_segment_start__ = ORIGIN( Ram );
__SRAM_segment_end__ = ORIGIN( Ram ) + LENGTH( Ram );
/* Stacks (full descending) at top of RAM, grows downward:
*
* __stack_min__ is used by the malloc implementation to ensure heap never collides
* with stack (assuming stack never grows beyond Stack_Size_Total in length) */
__stacks_top__ = __SRAM_segment_end__;
__stacks_min__ = __SRAM_segment_end__ - Stack_Size_Total;
SECTIONS
{
/* first section is .text which is used for code */
__text_start__ = . ;
.text : {
__privileged_code_start__ = . ;
KEEP( *( .vectors ) )
*( .privileged_code )
__privileged_code_end__ = .;
*( .text .text.* .gnu.linkonce.t.* )
*( .plt )
*( .gnu.warning )
*( .glue_7t ) *( .glue_7 ) *( .vfp11_veneer )
*( .rodata .rodata.* .gnu.linkonce.r.* )
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.gcc_except_table)
*(.eh_frame_hdr)
*(.eh_frame)
. = ALIGN( 4 ) ;
KEEP( *( .init ) )
. = ALIGN( 4 ) ;
__preinit_array_start = . ;
KEEP( *( .preinit_array ) )
__preinit_array_end = . ;
. = ALIGN( 4 ) ;
__init_array_start = . ;
KEEP( *( SORT( .init_array.* ) ) )
KEEP( *( .init_array ) )
__init_array_end = . ;
. = ALIGN( 4 ) ;
KEEP( *crtbegin.o( .ctors ) )
KEEP( *( EXCLUDE_FILE( *crtend.o ) .ctors ) )
KEEP( *( SORT( .ctors.* ) ) )
KEEP( *crtend.o( .ctors ) )
. = ALIGN( 4 ) ;
KEEP( *( .fini ) )
. = ALIGN( 4 ) ;
__fini_array_start = . ;
KEEP( *( .fini_array ) )
KEEP( *( SORT( .fini_array.* ) ) )
__fini_array_end = . ;
KEEP( *crtbegin.o( .dtors ) )
KEEP( *( EXCLUDE_FILE( *crtend.o ) .dtors ) )
KEEP( *( SORT( .dtors.* ) ) )
KEEP( *crtend.o( .dtors ) )
} >Flash
__exidx_start = . ;
.ARM.exidx : {
*( .ARM.exidx* .gnu.linkonce.armexidx.* )
} >Flash
__exidx_end = . ;
.text.align : { . = ALIGN( 8 ) ; } >Flash /* Alignment schenanigans */
__text_end__ = . ;
/* .bss section -- used for uninitialized data */
/* Located at the start of RAM */
.bss (NOLOAD) : {
__bss_start__ = . ;
*crt0.o( .ram_vectors )
__user_bss_start__ = . ;
*( .user_bss )
__user_bss_end__ = . ;
*( .shbss )
*( .bss .bss.* .gnu.linkonce.b.* )
*( COMMON )
*( .ram.b )
. = ALIGN( 8 ) ;
__bss_end__ = . ;
} >Ram AT>Flash
/* .data section -- used for initialized data */
.data : {
__data_start__ = . ;
KEEP( *( .jcr ) )
*( .got.plt ) *( .got )
*( .shdata )
*( .data .data.* .gnu.linkonce.d.* )
*( .ram )
. = ALIGN( 8 ) ;
__data_end__ = . ;
} >Ram AT>Flash
__data_init_start__ = LOADADDR( .data ) ;
/* Heap starts here and grows up in memory */
. = ALIGN( 8 ) ;
__heap_start__ = . ;
end = . ;
__end__ = . ;
.stab 0 (NOLOAD) : { *(.stab) }
.stabstr 0 (NOLOAD) : { *(.stabstr) }
/* DWARF debug sections. */
/* Symbols in the DWARF debugging sections are relative to the */
/* beginning of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* DWARF 3 */
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
.note.gnu.arm.ident 0 : { KEEP( *( .note.gnu.arm.ident ) ) }
.ARM.attributes 0 : {
KEEP( *( .ARM.attributes ) )
KEEP( *( .gnu.attributes ) )
}
/DISCARD/ : { *( .note.GNU-stack ) }
/* C data can be defined as being in special purpose RAMs using
* __attribute__ ((section ("ethram"))) for example. */
.usbram (NOLOAD):
{
*( .usbram )
*( .usbram.* )
} > UsbRam
.ethram (NOLOAD):
{
*( .ethram )
*( .ethram.* )
} > EthRam
.canram (NOLOAD):
{
*( .canram )
*( .canram.* )
} > CanRam
.batram (NOLOAD):
{
*( .batram )
*( .batram.* )
} > BatRam
}

195
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_functions.s Normal file
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/* .include "vector_defns.h" */
.section .privileged_code, "ax"
.arm
.weak __mbed_fiq
.weak __mbed_undef
.weak __mbed_prefetch_abort
.weak __mbed_data_abort
.weak __mbed_irq
.weak __mbed_swi
.weak __mbed_dcc_irq
.weak __mbed_reset
.global __mbed_init_realmonitor
.weak SVC_Handler
.weak IRQ_Handler
/* .global __mbed_init */
__mbed_fiq:
B __mbed_fiq
__mbed_undef:
LDR PC, =0x7fffffa0
__mbed_prefetch_abort:
LDR PC, =0x7fffffb0
__mbed_data_abort:
LDR PC, =0x7fffffc0
__mbed_irq:
/*
If RTOS is enabled then goto RTOS IRQ handler
*/
PUSH {R0}
LDR R0, =IRQ_Handler
CMP R0, #0
POP {R0}
BNE IRQ_Handler
/*
else use CMSIS IRQ handler
*/
MSR CPSR_c, #0x1F|0x80|0x40
STMDB sp!, {r0-r3,r12,lr}
MOV r0, #0xFFFFFF00
LDR r0, [r0]
MOV lr, pc
BX r0
MOV r0, #0xFFFFFF00
STR r0, [r0]
LDMFD sp!,{r0-r3,r12,lr}
MSR CPSR_c, #0x12|0x80|0x40
SUBS pc, lr, #4
__mbed_swi:
/*
If RTOS is enabled then goto RTOS SVC handler
*/
PUSH {R0}
LDR R0, =SVC_Handler
CMP R0, #0
POP {R0}
BNE SVC_Handler
/*
else use CMSIS SVC handler
*/
STMFD sp!, {a4, r4, ip, lr}
LDR r4, =0x40000040
LDR a4, =0x00940000
LDR PC, =0x7ffff820
__mbed_dcc_irq:
LDMFD sp!,{r0-r3,r12,lr}
MSR CPSR_c, #0x12|0x80|0x40
SUB lr, lr, #4
STMFD sp!, {ip,lr}
LDR LR, =0xfffff000
STR LR, [LR, #0xf00]
LDR PC, =0x7fffffe0
/*
__mbed_reset is called after reset
we setup the stacks and realmonitor, then call Reset_Handler like on M3
*/
.section .text, "ax"
.arm
.global Reset_handler
Reset_Handler:
.extern __libc_init_array
.extern SystemInit
.weak software_init_hook
LDR R0, =SystemInit
MOV LR, PC
BX R0
/* if (software_init_hook) // give control to the RTOS
software_init_hook(); // this will also call __libc_init_array
*/
LDR R0, =software_init_hook
CMP R0, #0
BEQ nortos
ORR R0,R0,#1 /* set thumb address */
BX R0
/* else */
nortos:
LDR R0, =__libc_init_array
MOV LR, PC
BX R0
MSR CPSR_c, #0x1F /* enable irq */
LDR R0, =main
BX R0
__mbed_reset:
LDR R0, =( __SRAM_segment_end__ )
MSR CPSR_c, #0x1B|0x80|0x40
MOV SP, R0
SUB R0, R0, #0x00000040
MSR CPSR_c, #0x17|0x80|0x40
MOV SP, R0
SUB R0, R0, #0x00000040
MSR CPSR_c, #0x11|0x80|0x40
MOV SP, R0
SUB R0, R0, #0x00000040
MSR CPSR_c, #0x12|0x80|0x40
MOV SP, R0
SUB R0, R0, #0x00000040
MSR CPSR_c, #0x13|0x80|0x40
MOV SP, R0
SUB R0, R0, #0x00000040
/*
MSR CPSR_c, #0x10|0x80|0x40
MOV SP, R0
*/
MSR CPSR_c, #0x1F|0x80|0x40
MOV SP, R0
MSR CPSR_c, #0x13|0x80|0x40 /* execute in Supervisor mode */
/* Relocate .data section (Copy from ROM to RAM) */
LDR R1, =__text_end__ /* _etext */
LDR R2, =__data_start__ /* _data */
LDR R3, =__data_end__ /* _edata */
CMP R2, R3
BEQ DataIsEmpty
LoopRel: CMP R2, R3
LDRLO R0, [R1], #4
STRLO R0, [R2], #4
BLO LoopRel
DataIsEmpty:
/* Clear .bss section (Zero init) */
MOV R0, #0
LDR R1, =__bss_start__
LDR R2, =__bss_end__
CMP R1,R2
BEQ BSSIsEmpty
LoopZI: CMP R1, R2
STRLO R0, [R1], #4
BLO LoopZI
BSSIsEmpty:
/* Init realmonitor */
/*
LDR R0, =__mbed_init_realmonitor
MOV LR, PC
BX R0
*/
/* Go to Reset_Handler */
LDR R0, =Reset_Handler
BX R0

45
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_table.s Normal file
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# 1 "vector_table.s"
# 1 "<built-in>"
# 1 "<command line>"
# 1 "vector_table.s"
;
# 1 "vector_defns.h" 1
# 7 "vector_table.s" 2
;
.section .vectors, "ax"
.arm
.global __main
.global __mbed_reset
.global __mbed_undef
.global __mbed_swi
.global __mbed_prefetch_abort
.global __mbed_data_abort
.global __mbed_irq
.global __mbed_fiq
;
_start:
LDR PC, =__mbed_reset
LDR PC, =__mbed_undef
LDR PC, =__mbed_swi
LDR PC, =__mbed_prefetch_abort
LDR PC, =__mbed_data_abort
NOP ;
LDR PC, =__mbed_irq
LDR PC, =__mbed_fiq

13
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis.h Normal file
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/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2015 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in LPC2368 specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "LPC24xx.h"
#include "cmsis_nvic.h"
#endif

40
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis_nvic.c Normal file
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/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2011-2015 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "cmsis_nvic.h"
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
LPC_VIC->VectAddr[(int)IRQn] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
return LPC_VIC->VectAddr[(int)IRQn];
}

51
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis_nvic.h Normal file
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/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2011-2015 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS 32
#define NVIC_USER_IRQ_OFFSET 0
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

44
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/core_arm7.c Normal file
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/* mbed Microcontroller Library
* Copyright (C) 2008-2015 ARM Limited. All rights reserved.
*
* ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
* based on core_cm3.h, V1.20
*/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for armcc */
#define __INLINE __inline /*!< inline keyword for armcc */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for iarcc */
#define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for gcc */
#define __INLINE inline /*!< inline keyword for gcc */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
#if defined ( __CC_ARM )
/**
* @brief Return the Main Stack Pointer (return current ARM7 stack)
*
* @param none
* @return uint32_t Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void)
{
return __current_sp();
}
#endif

343
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/core_arm7.h Normal file
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/* mbed Microcontroller Library
* Copyright (C) 2008-2015 ARM Limited. All rights reserved.
*
* ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
* based on core_cm3.h, V1.20
*/
#ifndef __ARM7_CORE_H__
#define __ARM7_CORE_H__
#include "vector_defns.h"
#ifdef __cplusplus
extern "C" {
#endif
//#include "cmsis_nvic.h"
#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex core */
/**
* Lint configuration \n
* ----------------------- \n
*
* The following Lint messages will be suppressed and not shown: \n
* \n
* --- Error 10: --- \n
* register uint32_t __regBasePri __asm("basepri"); \n
* Error 10: Expecting ';' \n
* \n
* --- Error 530: --- \n
* return(__regBasePri); \n
* Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
* \n
* --- Error 550: --- \n
* __regBasePri = (basePri & 0x1ff); \n
* } \n
* Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
* \n
* --- Error 754: --- \n
* uint32_t RESERVED0[24]; \n
* Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
* \n
* --- Error 750: --- \n
* #define __CM3_CORE_H__ \n
* Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
* \n
* --- Error 528: --- \n
* static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
* Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
* \n
* --- Error 751: --- \n
* } InterruptType_Type; \n
* Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
* \n
* \n
* Note: To re-enable a Message, insert a space before 'lint' * \n
*
*/
/*lint -save */
/*lint -e10 */
/*lint -e530 */
/*lint -e550 */
/*lint -e754 */
/*lint -e750 */
/*lint -e528 */
/*lint -e751 */
#include <stdint.h> /* Include standard types */
#if defined ( __CC_ARM )
/**
* @brief Return the Main Stack Pointer (current ARM7 stack)
*
* @param none
* @return uint32_t Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
extern uint32_t __get_MSP(void);
#endif
#if defined (__ICCARM__)
#include <intrinsics.h> /* IAR Intrinsics */
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
#endif
typedef struct
{
uint32_t IRQStatus;
uint32_t FIQStatus;
uint32_t RawIntr;
uint32_t IntSelect;
uint32_t IntEnable;
uint32_t IntEnClr;
uint32_t SoftInt;
uint32_t SoftIntClr;
uint32_t Protection;
uint32_t SWPriorityMask;
uint32_t RESERVED0[54];
uint32_t VectAddr[32];
uint32_t RESERVED1[32];
uint32_t VectPriority[32];
uint32_t RESERVED2[800];
uint32_t Address;
} NVIC_TypeDef;
#define NVIC_BASE (0xFFFFF000)
#define NVIC (( NVIC_TypeDef *) NVIC_BASE)
/**
* IO definitions
*
* define access restrictions to peripheral registers
*/
#ifdef __cplusplus
#define __I volatile /*!< defines 'read only' permissions */
#else
#define __I volatile const /*!< defines 'read only' permissions */
#endif
#define __O volatile /*!< defines 'write only' permissions */
#define __IO volatile /*!< defines 'read / write' permissions */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#define __NOP __nop
//#define __WFI __wfi
//#define __WFE __wfe
//#define __SEV __sev
//#define __ISB() __isb(0)
//#define __DSB() __dsb(0)
//#define __DMB() __dmb(0)
//#define __REV __rev
//#define __RBIT __rbit
#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
#define __STREXB(value, ptr) __strex(value, ptr)
#define __STREXH(value, ptr) __strex(value, ptr)
#define __STREXW(value, ptr) __strex(value, ptr)
#define __disable_irq() unsigned tmp_IntEnable = LPC_VIC->IntEnable; \
LPC_VIC->IntEnClr = 0xffffffff
#define __enable_irq() LPC_VIC->IntEnable = tmp_IntEnable
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
static __INLINE void __enable_irq() {
unsigned long temp;
__asm__ __volatile__("mrs %0, cpsr\n"
"bic %0, %0, #0x80\n"
"msr cpsr_c, %0"
: "=r" (temp)
:
: "memory");
}
static __INLINE uint32_t __disable_irq() {
unsigned long old,temp;
__asm__ __volatile__("mrs %0, cpsr\n"
"orr %1, %0, #0xc0\n"
"msr cpsr_c, %1"
: "=r" (old), "=r" (temp)
:
: "memory");
return (old & 0x80) == 0;
}
static __INLINE void __NOP() { __ASM volatile ("nop"); }
/** \brief Get Control Bits of Status Register
This function returns the content of the Control Bits from the Program Status Register.
\return Control Bits value
*/
__attribute__( ( always_inline ) ) static inline uint32_t __get_CONTROL(void)
{
uint32_t result;
__asm__ __volatile__ ("MRS %0, CPSR \n"
"AND %0,%0,#31" : "=r" (result) );
return(result);
}
#define MODE_USER 0x10
#define MODE_FIQ 0x11
#define MODE_IRQ 0x12
#define MODE_SUPERVISOR 0x13
#define MODE_ABORT 0x17
#define MODE_UNDEFINED 0x1B
#define MODE_SYSTEM 0x1F
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/**
* @brief Enable Interrupt in NVIC Interrupt Controller
*
* @param IRQn_Type IRQn specifies the interrupt number
* @return none
*
* Enable a device specific interupt in the NVIC interrupt controller.
* The interrupt number cannot be a negative value.
*/
static __INLINE void NVIC_EnableIRQ(uint32_t IRQn)
{
NVIC->IntEnable = 1 << (uint32_t)IRQn;
}
/**
* @brief Disable the interrupt line for external interrupt specified
*
* @param IRQn_Type IRQn is the positive number of the external interrupt
* @return none
*
* Disable a device specific interupt in the NVIC interrupt controller.
* The interrupt number cannot be a negative value.
*/
static __INLINE void NVIC_DisableIRQ(uint32_t IRQn)
{
NVIC->IntEnClr = 1 << (uint32_t)IRQn;
}
/**
* @brief Pend Interrupt in NVIC Interrupt Controller
*
* @param IRQn_Type IRQn specifies the interrupt number
* @return none
*
* Force software a device specific interupt in the NVIC interrupt controller.
* The interrupt number cannot be a negative value.
*/
static __INLINE void NVIC_PendIRQ(uint32_t IRQn)
{
NVIC->SoftInt = 1 << (uint32_t)IRQn;
}
/**
* @brief Unpend the interrupt in NVIC Interrupt Controller
*
* @param IRQn_Type IRQn is the positive number of the external interrupt
* @return none
*
* Clear software device specific interupt in the NVIC interrupt controller.
* The interrupt number cannot be a negative value.
*/
static __INLINE void NVIC_UnpendIRQ(uint32_t IRQn)
{
NVIC->SoftIntClr = 1 << (uint32_t)IRQn;
}
/**
* @brief Is IRQ pending
*
* @param IRQn_Type IRQn is the positive number of the external interrupt
* @return 0 if IRQ is not pending
* 1 if IRQ is pending
*
* Returns software device specific interupt in the NVIC interrupt controller.
* The interrupt number cannot be a negative value.
*/
static __INLINE uint32_t NVIC_Pending(uint32_t IRQn)
{
return (NVIC->SoftInt & (1 << (uint32_t)IRQn)) != 0;
}
static __INLINE uint32_t __get_IPSR(void)
{
unsigned i;
for(i = 0; i < 32; i ++)
if(NVIC->Address == NVIC->VectAddr[i])
return i;
return 1; // 1 is an invalid entry in the interrupt table on LPC2460
}
#ifdef __cplusplus
}
#endif
#endif /* __ARM7_CORE_H__ */
/*lint -restore */

164
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/system_LPC24xx.c Normal file
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/* mbed Microcontroller Library
* Copyright (C) 2008-2015 ARM Limited. All rights reserved.
*
* ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
*/
#include <stdint.h>
#include "LPC24xx.h"
#define CLOCK_SETUP 1
#define SCS_Val ((1<<4) | (1 << 5))
#define CLKSRCSEL_Val 0x00000001
#define PLL0_SETUP 1
#define PLL0CFG_Val 0x0000000B
#define CCLKCFG_Val 0x00000003
#define USBCLKCFG_Val 0x00000005
#define PCLKSEL0_Val 0x00000000
#define PCLKSEL1_Val 0x00000000
#define PCONP_Val (1 << PCEMC)
#define CLKOUTCFG_Val 0x00000000
#define MAMCR_Val 0x00000002
#define MAMTIM_Val 0x00000004
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
#define XTAL (12000000UL) /* Oscillator frequency */
#define OSC_CLK ( XTAL) /* Main oscillator frequency */
#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
/* F_cco0 = (2 * M * F_in) / N */
#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
#define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
/* Determine core clock frequency according to settings */
#if (PLL0_SETUP)
#if ((CLKSRCSEL_Val & 0x03) == 1)
#define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
#elif ((CLKSRCSEL_Val & 0x03) == 2)
#define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
#else
#define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
#endif
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
/* Determine clock frequency according to clock register values */
if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
switch (LPC_SC->CLKSRCSEL & 0x03) {
case 0: /* Int. RC oscillator => PLL0 */
case 3: /* Reserved, default to Int. RC */
SystemCoreClock = (IRC_OSC *
(((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
((LPC_SC->CCLKCFG & 0xFF)+ 1));
break;
case 1: /* Main oscillator => PLL0 */
SystemCoreClock = (OSC_CLK *
(((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
((LPC_SC->CCLKCFG & 0xFF)+ 1));
break;
case 2: /* RTC oscillator => PLL0 */
SystemCoreClock = (RTC_CLK *
(((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
((LPC_SC->CCLKCFG & 0xFF)+ 1));
break;
}
} else {
switch (LPC_SC->CLKSRCSEL & 0x03) {
case 0: /* Int. RC oscillator => PLL0 */
case 3: /* Reserved, default to Int. RC */
SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
break;
case 1: /* Main oscillator => PLL0 */
SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
break;
case 2: /* RTC oscillator => PLL0 */
SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
break;
}
}
}
void vectorRemap()
{
#define ARM_VECTOR_REBASE (0x40000000)
extern unsigned long __privileged_code_start__; /* Startup code address from linker */
int i;
/* Copy ARM vector table into internal RAM */
for (i = 0; i <= 56; i+=2)
{
*(unsigned short *)(ARM_VECTOR_REBASE + i) = *(unsigned short *)((unsigned long)(&__privileged_code_start__) + i);
}
// *(unsigned long *)(ARM_VECTOR_REBASE) = (unsigned long)armUnexpReset;
/* Remap the interrupt vectors to RAM */
LPC_SC->MEMMAP = 2;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemFrequency variable.
*/
void SystemInit (void)
{
LPC_WDT->WDMOD = 0; /* Disable internal watchdog */
#if (CLOCK_SETUP) /* Clock Setup */
LPC_SC->SCS = SCS_Val;
if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
while ((LPC_SC->SCS & (1 << 6)) == 0); /* Wait for Oscillator to be ready */
}
LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
#if (PLL0_SETUP)
LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
LPC_SC->PLL0CFG = PLL0CFG_Val;
LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
LPC_SC->PLL0FEED = 0xAA;
LPC_SC->PLL0FEED = 0x55;
while (!(LPC_SC->PLL0STAT & (1 << 26))); /* Wait for PLOCK0 */
LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
LPC_SC->PLL0FEED = 0xAA;
LPC_SC->PLL0FEED = 0x55;
#endif
LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
#endif
LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
// Setup MAM
LPC_SC->MAMTIM = MAMTIM_Val;
LPC_SC->MAMCR = MAMCR_Val;
vectorRemap();
}

44
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/system_LPC24xx.h Normal file
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@ -0,0 +1,44 @@
/* mbed Microcontroller Library
* Copyright (C) 2008-2015 ARM Limited. All rights reserved.
*
* ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
* based on cmsis system_LPC17xx.h
*/
#ifndef __SYSTEM_LPC24xx_H
#define __SYSTEM_LPC24xx_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif

77
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/vector_defns.h Normal file
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@ -0,0 +1,77 @@
/* mbed Microcontroller Library - Vectors
* Copyright (c) 2006-2015 ARM Limited. All rights reserved.
*/
#ifndef MBED_VECTOR_DEFNS_H
#define MBED_VECTOR_DEFNS_H
// Assember Macros
#ifdef __ARMCC_VERSION
#define EXPORT(x) EXPORT x
#define WEAK_EXPORT(x) EXPORT x [WEAK]
#define IMPORT(x) IMPORT x
#define LABEL(x) x
#else
#define EXPORT(x) .global x
#define WEAK_EXPORT(x) .weak x
#define IMPORT(x) .global x
#define LABEL(x) x:
#endif
// RealMonitor
// Requires RAM (0x40000040-0x4000011F) to be allocated by the linker
// RealMonitor entry points
#define rm_init_entry 0x7fffff91
#define rm_undef_handler 0x7fffffa0
#define rm_prefetchabort_handler 0x7fffffb0
#define rm_dataabort_handler 0x7fffffc0
#define rm_irqhandler2 0x7fffffe0
//#define rm_RunningToStopped 0x7ffff808 // ARM - MBED64
#define rm_RunningToStopped 0x7ffff820 // ARM - PHAT40
// Unofficial RealMonitor entry points and variables
#define RM_MSG_SWI 0x00940000
#define StateP 0x40000040
// VIC register addresses
#define VIC_Base 0xfffff000
#define VICAddress_Offset 0xf00
#define VICVectAddr0_Offset 0x100
#define VICVectAddr2_Offset 0x108
#define VICVectAddr3_Offset 0x10c
#define VICVectAddr31_Offset 0x17c
#define VICIntEnClr_Offset 0x014
#define VICIntEnClr (*(volatile unsigned long *)(VIC_Base + 0x014))
#define VICVectAddr2 (*(volatile unsigned long *)(VIC_Base + 0x108))
#define VICVectAddr3 (*(volatile unsigned long *)(VIC_Base + 0x10C))
// ARM Mode bits and Interrupt flags in PSRs
#define Mode_USR 0x10
#define Mode_FIQ 0x11
#define Mode_IRQ 0x12
#define Mode_SVC 0x13
#define Mode_ABT 0x17
#define Mode_UND 0x1B
#define Mode_SYS 0x1F
#define I_Bit 0x80 // when I bit is set, IRQ is disabled
#define F_Bit 0x40 // when F bit is set, FIQ is disabled
// MCU RAM
#define LPC2460_RAM_ADDRESS 0x40000000 // RAM Base
#define LPC2460_RAM_SIZE 0x10000 // 64KB
// ISR Stack Allocation
#define UND_stack_size 0x00000040
#define SVC_stack_size 0x00000040
#define ABT_stack_size 0x00000040
#define FIQ_stack_size 0x00000000
#define IRQ_stack_size 0x00000040
#define ISR_stack_size (UND_stack_size + SVC_stack_size + ABT_stack_size + FIQ_stack_size + IRQ_stack_size)
// Full Descending Stack, so top-most stack points to just above the top of RAM
#define LPC2460_STACK_TOP (LPC2460_RAM_ADDRESS + LPC2460_RAM_SIZE)
#define USR_STACK_TOP (LPC2460_STACK_TOP - ISR_stack_size)
#endif

22
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/vector_realmonitor.c Normal file
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@ -0,0 +1,22 @@
/* mbed Microcontroller Library - RealMonitor
* Copyright (c) 2006-2015 ARM Limited. All rights reserved.
*/
#include "vector_defns.h"
extern void __mbed_dcc_irq(void);
/* Function: __mbed_init_realmonitor
* Setup the RealMonitor DCC Interrupt Handlers
*/
void __mbed_init_realmonitor(void) __attribute__((weak));
void __mbed_init_realmonitor() {
// Disable all interrupts
VICIntEnClr = 0xffffffff;
// Set DCC interrupt vector addresses
VICVectAddr2 = (unsigned)&__mbed_dcc_irq;
VICVectAddr3 = (unsigned)&__mbed_dcc_irq;
// Initialise RealMonitor
((void (*)(void))rm_init_entry)();
}

13
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/startup_stm32f103xb.s
View File

@ -77,6 +77,8 @@ defined in linker script */
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
@ -109,10 +111,15 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
//bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
//bl main
bl _start
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**

153
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/TOOLCHAIN_GCC_ARM/STM32F446XE.ld Normal file
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@ -0,0 +1,153 @@
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
RAM (rwx) : ORIGIN = 0x200001C4, LENGTH = 128k - 0x1C4
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* _estack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
_sidata = .;
.data : AT (__etext)
{
__data_start__ = .;
_sdata = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
_edata = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
_ebss = .;
} > RAM
.heap (COPY):
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
_estack = __StackTop;
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

559
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/TOOLCHAIN_GCC_ARM/startup_stm32f446xx.s Normal file
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@ -0,0 +1,559 @@
/**
******************************************************************************
* @file startup_stm32f446xx.s
* @author MCD Application Team
* @version V2.3.0
* @date 02-March-2015
* @brief STM32F446xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
//bl __libc_init_array
/* Call the application's entry point.*/
//bl main
// Calling the crt0 'cold-start' entry point. There __libc_init_array is called
// and when existing hardware_init_hook() and software_init_hook() before
// starting main(). software_init_hook() is available and has to be called due
// to initializsation when using rtos.
bl _start
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDIO_IRQHandler /* SDIO */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word FPU_IRQHandler /* FPU */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SPI4_IRQHandler /* SPI4 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SAI1_IRQHandler /* SAI1 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SAI2_IRQHandler /* SAI2 */
.word QuadSPI_IRQHandler /* QuadSPI */
.word CEC_IRQHandler /* CEC */
.word SPDIF_RX_IRQHandler /* SPDIF RX */
.word FMPI2C1_Event_IRQHandler /* FMPI2C 1 Event */
.word FMPI2C1_Error_IRQHandler /* FMPI2C 1 Error */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QuadSPI_IRQHandler
.thumb_set QuadSPI_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak FMPI2C1_Event_IRQHandler
.thumb_set FMPI2C1_Event_IRQHandler,Default_Handler
.weak FMPI2C1_Error_IRQHandler
.thumb_set FMPI2C1_Error_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

38
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/* mbed Microcontroller Library
* A generic CMSIS include header
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "stm32f4xx.h"
#include "cmsis_nvic.h"
#endif

55
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/cmsis_nvic.c Normal file
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/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t *)SCB->VTOR;
uint32_t i;
// Copy and switch to dynamic vectors if the first time called
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
uint32_t *old_vectors = vectors;
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
for (i=0; i<NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
}
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
}

55
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/cmsis_nvic.h Normal file
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/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
// STM32F411RE
// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
// MCU Peripherals: 86 vectors = 344 bytes from 0x40 to 0x197
// Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
#define NVIC_NUM_VECTORS 102
#define NVIC_USER_IRQ_OFFSET 16
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

122
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/hal_tick.c Normal file
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/**
******************************************************************************
* @file hal_tick.c
* @author MCD Application Team
* @brief Initialization of HAL tick
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#include "hal_tick.h"
TIM_HandleTypeDef TimMasterHandle;
uint32_t PreviousVal = 0;
void us_ticker_irq_handler(void);
void timer_irq_handler(void) {
// Channel 1 for mbed timeout
if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
us_ticker_irq_handler();
}
// Channel 2 for HAL tick
if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
__HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
if ((val - PreviousVal) >= HAL_TICK_DELAY) {
// Increment HAL variable
HAL_IncTick();
// Prepare next interrupt
__HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
PreviousVal = val;
#if 0 // For DEBUG only
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
#endif
}
}
}
// Reconfigure the HAL tick using a standard timer instead of systick.
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
// Enable timer clock
TIM_MST_RCC;
// Reset timer
TIM_MST_RESET_ON;
TIM_MST_RESET_OFF;
// Update the SystemCoreClock variable
SystemCoreClockUpdate();
// Configure time base
TimMasterHandle.Instance = TIM_MST;
TimMasterHandle.Init.Period = 0xFFFFFFFF;
TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 2 / 1000000) - 1; // 1 µs tick
TimMasterHandle.Init.ClockDivision = 0;
TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
TimMasterHandle.Init.RepetitionCounter = 0;
HAL_TIM_OC_Init(&TimMasterHandle);
NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
NVIC_EnableIRQ(TIM_MST_IRQ);
// Channel 1 for mbed timeout
HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
// Channel 2 for HAL tick
HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
__HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
#if 0 // For DEBUG only
__GPIOB_CLK_ENABLE();
GPIO_InitTypeDef GPIO_InitStruct;
GPIO_InitStruct.Pin = GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
#endif
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

60
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/hal_tick.h Normal file
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/**
******************************************************************************
* @file hal_tick.h
* @author MCD Application Team
* @brief Initialization of HAL tick
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HAL_TICK_H
#define __HAL_TICK_H
#ifdef __cplusplus
extern "C" {
#endif
#include "stm32f4xx.h"
#include "cmsis_nvic.h"
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define HAL_TICK_DELAY (1000) // 1 ms
#ifdef __cplusplus
}
#endif
#endif // __HAL_TICK_H
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f446xx.h Normal file
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232
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f4xx.h Normal file
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/**
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F4xx device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx
* @{
*/
#ifndef __STM32F4xx_H
#define __STM32F4xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32F4)
#define STM32F4
#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
/* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
/* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
/* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
/* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
STM32F439NI, STM32F429IG and STM32F429II Devices */
/* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
/* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
#define STM32F446xx /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
and STM32F446ZE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
#define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.0
*/
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
|(__STM32F4xx_CMSIS_DEVICE_VERSION))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32F405xx)
#include "stm32f405xx.h"
#elif defined(STM32F415xx)
#include "stm32f415xx.h"
#elif defined(STM32F407xx)
#include "stm32f407xx.h"
#elif defined(STM32F417xx)
#include "stm32f417xx.h"
#elif defined(STM32F427xx)
#include "stm32f427xx.h"
#elif defined(STM32F437xx)
#include "stm32f437xx.h"
#elif defined(STM32F429xx)
#include "stm32f429xx.h"
#elif defined(STM32F439xx)
#include "stm32f439xx.h"
#elif defined(STM32F401xC)
#include "stm32f401xc.h"
#elif defined(STM32F401xE)
#include "stm32f401xe.h"
#elif defined(STM32F411xE)
#include "stm32f411xe.h"
#elif defined(STM32F446xx)
#include "stm32f446xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
ERROR = 0,
SUCCESS = !ERROR
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macro
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32f4xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32F4xx_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f4xx_hal_conf.h
* @author MCD Application Team
* @version V1.1.0
* @date 26-December-2014
* @brief HAL configuration file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CONF_H
#define __STM32F4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DCMI_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_DMA2D_MODULE_ENABLED
#define HAL_ETH_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
#define HAL_PCCARD_MODULE_ENABLED
#define HAL_SRAM_MODULE_ENABLED
#define HAL_SDRAM_MODULE_ENABLED
#define HAL_HASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_LTDC_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_SAI_MODULE_ENABLED
#define HAL_SD_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 1
#define DATA_CACHE_ENABLE 1
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1 */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2
#define MAC_ADDR1 0
#define MAC_ADDR2 0
#define MAC_ADDR3 0
#define MAC_ADDR4 0
#define MAC_ADDR5 0
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848 PHY Address*/
#define DP83848_PHY_ADDRESS 0x01
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f4xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32f4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32f4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32f4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f4xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f4xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32f4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f4xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32f4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32f4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32f4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.3.0
* @date 02-March-2015
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* This file configures the system clock as follows:
*-----------------------------------------------------------------------------
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
* | (external 8 MHz clock) | (internal 16 MHz)
* | 2- PLL_HSE_XTAL |
* | (external 8 MHz xtal) |
*-----------------------------------------------------------------------------
* SYSCLK(MHz) | 180 | 16
*-----------------------------------------------------------------------------
* AHBCLK (MHz) | 180 | 16
*-----------------------------------------------------------------------------
* APB1CLK (MHz) | 45 | 4
*-----------------------------------------------------------------------------
* APB2CLK (MHz) | 90 | 8
*-----------------------------------------------------------------------------
* USB capable (48 MHz precise clock) | YES | NO
*-----------------------------------------------------------------------------
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx_system
* @{
*/
/** @addtogroup STM32F4xx_System_Private_Includes
* @{
*/
#include "stm32f4xx.h"
#include "hal_tick.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx)
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F446xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx)
/* #define DATA_IN_ExtSDRAM */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
#error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Macros
* @{
*/
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
#define USE_PLL_HSE_EXTC (1) /* Use external clock */
#define USE_PLL_HSE_XTAL (0) /* Use external xtal */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 18000000;
__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
* @{
*/
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
#endif
uint8_t SetSysClock_PLL_HSI(void);
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
/* Configure the Cube driver */
SystemCoreClock = 18000000; // At this stage the HSI is used as system clock
HAL_Init();
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings */
SetSysClock();
/* Reset the timer to avoid issues after the RAM initialization */
TIM_MST_RESET_ON;
TIM_MST_RESET_OFF;
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
* depends on the application requirements), user has to ensure that HSE_VALUE
* is same as the real frequency of the crystal used. Otherwise, this function
* may have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
* This function configures the external memories (SRAM/SDRAM)
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
#if defined (DATA_IN_ExtSDRAM)
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register uint32_t index;
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
clock */
RCC->AHB1ENR |= 0x000001F8;
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x000000CC;
GPIOD->AFR[1] = 0xCC000CCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xA02A000A;
/* Configure PDx pins speed to 50 MHz */
GPIOD->OSPEEDR = 0xA02A000A;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00000CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA800A;
/* Configure PEx pins speed to 50 MHz */
GPIOE->OSPEEDR = 0xAAAA800A;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xAA800AAA;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0xAAAAAAAA;
/* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0xAAAAAAAA;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x00000000;
/* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000;
/*-- FMC Configuration ------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001;
/* Configure and enable SDRAM bank1 */
FMC_Bank5_6->SDCR[0] = 0x000019E4;
FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Delay */
for (index = 0; index<1000; index++);
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Auto refresh command */
FMC_Bank5_6->SDCMR = 0x00000073;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* MRD register program */
FMC_Bank5_6->SDCMR = 0x00046014;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR;
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
/* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#endif /* DATA_IN_ExtSDRAM */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx)
#if defined(DATA_IN_ExtSRAM)
/*-- GPIOs Configuration -----------------------------------------------------*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR |= 0x00000078;
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCC0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA000AAA;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xFF000FFF;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0x00CCCCCC;
GPIOG->AFR[1] = 0x000000C0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00085AAA;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000CAFFF;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FMC/FSMC Configuration --------------------------------------------------*/
/* Enable the FMC/FSMC interface clock */
RCC->AHB3ENR |= 0x00000001;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F446xx)
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001011;
FSMC_Bank1->BTCR[3] = 0x00000201;
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
#endif /* DATA_IN_ExtSRAM */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
}
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
* @note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
void SetSysClock(void)
{
/* 1- Try to start with HSE and external clock */
#if USE_PLL_HSE_EXTC != 0
if (SetSysClock_PLL_HSE(1) == 0)
#endif
{
/* 2- If fail try to start with HSE and external xtal */
#if USE_PLL_HSE_XTAL != 0
if (SetSysClock_PLL_HSE(0) == 0)
#endif
{
/* 3- If fail start with HSI clock */
if (SetSysClock_PLL_HSI() == 0)
{
while(1)
{
// [TODO] Put something here to tell the user that a problem occured...
}
}
}
}
/* Output clock on MCO2 pin(PC9) for debugging purpose */
//HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
}
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/* Enable HSE oscillator and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
if (bypass == 0)
{
RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
}
else
{
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
}
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 8;
RCC_OscInitStruct.PLL.PLLN = 360;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 7;
RCC_OscInitStruct.PLL.PLLR = 4;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
return 0; // FAIL
}
HAL_PWREx_ActivateOverDrive();
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
{
return 0; // FAIL
}
/* Output clock on MCO1 pin(PA8) for debugging purpose */
//if (bypass == 0)
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
//else
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
return 1; // OK
}
#endif
/******************************************************************************/
/* PLL (clocked by HSI) used as System clock source */
/******************************************************************************/
uint8_t SetSysClock_PLL_HSI(void)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSI oscillator and activate PLL with HSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
RCC_OscInitStruct.HSICalibrationValue = 16;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
//RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
//RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384)
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
return 0; // FAIL
}
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
{
return 0; // FAIL
}
/* Output clock on MCO1 pin(PA8) for debugging purpose */
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
return 1; // OK
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

123
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.h Normal file
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@ -0,0 +1,123 @@
/**
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 02-March-2015
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32F4XX_H
#define __SYSTEM_STM32F4XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32F4xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Exported_types
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
extern void SetSysClock(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32F4XX_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

13
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_GCC_ARM/startup_stm32l152xe.s
View File

@ -78,6 +78,8 @@ defined in linker script */
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
@ -110,10 +112,15 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
//bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
//bl main
bl _start
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**

15
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/W7500.sct Normal file
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@ -0,0 +1,15 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00020000 { ; load region size_region
ER_IROM1 0x00000000 0x00020000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00004000 { ; RW data
.ANY (+RW +ZI)
}
}

213
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s Normal file
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@ -0,0 +1,213 @@
;/**************************************************************************//**
; * @file startup_CMSDK_CM0.s
; * @brief CMSIS Cortex-M0 Core Device Startup File for
; * Device CMSDK_CM0
; * @version V3.01
; * @date 06. March 2012
; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER
; * @note
; * Copyright (C) 2012 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp EQU 0x20004000 ; Top of RAM (16 KB for WIZwiki_W7500)
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
DCD SSP0_Handler ; 16+ 0: SSP 0 Handler
DCD SSP1_Handler ; 16+ 1: SSP 1 Handler
DCD UART0_Handler ; 16+ 2: UART 0 Handler
DCD UART1_Handler ; 16+ 3: UART 1 Handler
DCD UART2_Handler ; 16+ 4: UART 2 Handler
DCD I2C0_Handler ; 16+ 5: I2C 0 Handler
DCD I2C1_Handler ; 16+ 6: I2C 1 Handler
DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler
DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler
DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler
DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler
DCD DMA_Handler ; 16+11: DMA Combined Handler
DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler
DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler
DCD PWM0_Handler ; 16+14: PWM0 Handler
DCD PWM1_Handler ; 16+15: PWM1 Handler
DCD PWM2_Handler ; 16+16: PWM2 Handler
DCD PWM3_Handler ; 16+17: PWM3 Handler
DCD PWM4_Handler ; 16+18: PWM4 Handler
DCD PWM5_Handler ; 16+19: PWM5 Handler
DCD PWM6_Handler ; 16+20: PWM6 Handler
DCD PWM7_Handler ; 16+21: PWM7 Handler
DCD RTC_Handler ; 16+22: RTC Handler
DCD ADC_Handler ; 16+23: ADC Handler
DCD WZTOE_Handler ; 16+24: WZTOE_Handler
DCD EXTI_Handler ; 16+25: EXTI_Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT SSP0_Handler [WEAK]
EXPORT SSP1_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT UART2_Handler [WEAK]
EXPORT I2C0_Handler [WEAK]
EXPORT I2C1_Handler [WEAK]
EXPORT PORT0_Handler [WEAK]
EXPORT PORT1_Handler [WEAK]
EXPORT PORT2_Handler [WEAK]
EXPORT PORT3_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT DUALTIMER0_Handler [WEAK]
EXPORT DUALTIMER1_Handler [WEAK]
EXPORT PWM0_Handler [WEAK]
EXPORT PWM1_Handler [WEAK]
EXPORT PWM2_Handler [WEAK]
EXPORT PWM3_Handler [WEAK]
EXPORT PWM4_Handler [WEAK]
EXPORT PWM5_Handler [WEAK]
EXPORT PWM6_Handler [WEAK]
EXPORT PWM7_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT WZTOE_Handler [WEAK]
EXPORT EXTI_Handler [WEAK]
SSP0_Handler
SSP1_Handler
UART0_Handler
UART1_Handler
UART2_Handler
I2C0_Handler
I2C1_Handler
PORT0_Handler
PORT1_Handler
PORT2_Handler
PORT3_Handler
DMA_Handler
DUALTIMER0_Handler
DUALTIMER1_Handler
PWM0_Handler
PWM1_Handler
PWM2_Handler
PWM3_Handler
PWM4_Handler
PWM5_Handler
PWM6_Handler
PWM7_Handler
RTC_Handler
ADC_Handler
WZTOE_Handler
EXTI_Handler
B .
ENDP
ALIGN
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
END

31
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/sys.cpp Normal file
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@ -0,0 +1,31 @@
/* mbed Microcontroller Library - stackheap
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* Setup a fixed single stack/heap memory model,
* between the top of the RW/ZI region and the stackpointer
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

15
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/W7500.sct Normal file
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@ -0,0 +1,15 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00020000 { ; load region size_region
ER_IROM1 0x00000000 0x00020000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00004000 { ; RW data
.ANY (+RW +ZI)
}
}

186
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/startup_W7500x.s Normal file
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@ -0,0 +1,186 @@
;/**************************************************************************//**
; * @file startup_CMSDK_CM0.s
; * @brief CMSIS Cortex-M0 Core Device Startup File for
; * Device CMSDK_CM0
; * @version V3.01
; * @date 06. March 2012
; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER
; * @note
; * Copyright (C) 2012 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
__initial_sp EQU 0x20004000 ; Top of RAM (16 KB for WIZwiki_W7500)
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
DCD SSP0_Handler ; 16+ 0: SSP 0 Handler
DCD SSP1_Handler ; 16+ 1: SSP 1 Handler
DCD UART0_Handler ; 16+ 2: UART 0 Handler
DCD UART1_Handler ; 16+ 3: UART 1 Handler
DCD UART2_Handler ; 16+ 4: UART 2 Handler
DCD I2C0_Handler ; 16+ 5: I2C 0 Handler
DCD I2C1_Handler ; 16+ 6: I2C 1 Handler
DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler
DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler
DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler
DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler
DCD DMA_Handler ; 16+11: DMA Combined Handler
DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler
DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler
DCD PWM0_Handler ; 16+14: PWM0 Handler
DCD PWM1_Handler ; 16+15: PWM1 Handler
DCD PWM2_Handler ; 16+16: PWM2 Handler
DCD PWM3_Handler ; 16+17: PWM3 Handler
DCD PWM4_Handler ; 16+18: PWM4 Handler
DCD PWM5_Handler ; 16+19: PWM5 Handler
DCD PWM6_Handler ; 16+20: PWM6 Handler
DCD PWM7_Handler ; 16+21: PWM7 Handler
DCD RTC_Handler ; 16+22: RTC Handler
DCD ADC_Handler ; 16+23: ADC Handler
DCD WZTOE_Handler ; 16+24: WZTOE_Handler
DCD EXTI_Handler ; 16+25: EXTI_Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT SSP0_Handler [WEAK]
EXPORT SSP1_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT UART2_Handler [WEAK]
EXPORT I2C0_Handler [WEAK]
EXPORT I2C1_Handler [WEAK]
EXPORT PORT0_Handler [WEAK]
EXPORT PORT1_Handler [WEAK]
EXPORT PORT2_Handler [WEAK]
EXPORT PORT3_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT DUALTIMER0_Handler [WEAK]
EXPORT DUALTIMER1_Handler [WEAK]
EXPORT PWM0_Handler [WEAK]
EXPORT PWM1_Handler [WEAK]
EXPORT PWM2_Handler [WEAK]
EXPORT PWM3_Handler [WEAK]
EXPORT PWM4_Handler [WEAK]
EXPORT PWM5_Handler [WEAK]
EXPORT PWM6_Handler [WEAK]
EXPORT PWM7_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT WZTOE_Handler [WEAK]
EXPORT EXTI_Handler [WEAK]
SSP0_Handler
SSP1_Handler
UART0_Handler
UART1_Handler
UART2_Handler
I2C0_Handler
I2C1_Handler
PORT0_Handler
PORT1_Handler
PORT2_Handler
PORT3_Handler
DMA_Handler
DUALTIMER0_Handler
DUALTIMER1_Handler
PWM0_Handler
PWM1_Handler
PWM2_Handler
PWM3_Handler
PWM4_Handler
PWM5_Handler
PWM6_Handler
PWM7_Handler
RTC_Handler
ADC_Handler
WZTOE_Handler
EXTI_Handler
B .
ENDP
ALIGN
END

31
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/sys.cpp Normal file
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@ -0,0 +1,31 @@
/* mbed Microcontroller Library - stackheap
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* Setup a fixed single stack/heap memory model,
* between the top of the RW/ZI region and the stackpointer
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

152
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/W7500.ld Normal file
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@ -0,0 +1,152 @@
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 /* 16K */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

259
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/startup_W7500.s Normal file
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@ -0,0 +1,259 @@
/* File: startup_W7500.s
* Purpose: startup file for Cortex-M0 devices. Should use with
* GCC for ARM Embedded Processors
* Version: V1.4
* Date: 20 Dezember 2012
*
*/
/* Copyright (c) 2011 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.syntax unified
.arch armv6-m
.section .stack
.align 3
/*
// <h> Stack Configuration
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x200
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
/*
// <h> Heap Configuration
// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
/* Vector Table */
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long SSP0_Handler /* 16+ 0: SSP 0 Handler */
.long SSP1_Handler /* 16+ 1: SSP 1 Handler */
.long UART0_Handler /* 16+ 2: UART 0 Handler */
.long UART1_Handler /* 16+ 3: UART 1 Handler */
.long UART2_Handler /* 16+ 4: UART 2 Handler */
.long I2C0_Handler /* 16+ 5: I2C 0 Handler */
.long I2C1_Handler /* 16+ 6: I2C 1 Handler */
.long PORT0_Handler /* 16+ 7: GPIO Port 0 Combined Handler */
.long PORT1_Handler /* 16+ 8: GPIO Port 1 Combined Handler */
.long PORT2_Handler /* 16+ 9: GPIO Port 2 Combined Handler */
.long PORT3_Handler /* 16+10: GPIO Port 3 Combined Handler */
.long DMA_Handler /* 16+11: DMA Combined Handler */
.long DUALTIMER0_Handler /* 16+12: Dual timer 0 handler */
.long DUALTIMER1_Handler /* 16+ 13: Dual timer 1 Handler */
.long PWM0_Handler /* 16+ 14: PWM0 Handler */
.long PWM1_Handler /* 16+ 15: PWM1 Handler */
.long PWM2_Handler /* 16+ 16: PWM2 Handler */
.long PWM3_Handler /* 16+ 17: PWM3 Handler */
.long PWM4_Handler /* 16+ 18: PWM4 Handler */
.long PWM5_Handler /* 16+ 19: PWM5 Handler */
.long PWM6_Handler /* 16+ 20: PWM6 Handler */
.long PWM7_Handler /* 16+ 21: PWM7 Handler */
.long RTC_Handler /* 16+ 22: RTC Handler */
.long ADC_Handler /* 16+ 23: ADC Handler */
.long WZTOE_Handler /* 16+ 24: WZTOE Handler */
.long EXTI_Handler /* 16+ 25: EXTI Handler */
.size __isr_vector, . - __isr_vector
/* Reset Handler */
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
subs r2, r1
ble .LC3
movs r0, 0
.LC2:
str r0, [r1, r2]
subs r2, 4
bge .LC2
.LC3:
#endif /* __STARTUP_CLEAR_BSS */
/*bl _start*/
bl main
.pool
.size Reset_Handler, . - Reset_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
/* System Exception Handlers */
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
def_default_handler BusFault_Handler
def_default_handler UsageFault_Handler
def_default_handler SVC_Handler
def_default_handler DebugMon_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
/* IRQ Handlers */
def_default_handler SSP0_Handler
def_default_handler SSP1_Handler
def_default_handler UART0_Handler
def_default_handler UART1_Handler
def_default_handler UART2_Handler
def_default_handler I2C0_Handler
def_default_handler I2C1_Handler
def_default_handler PORT0_Handler
def_default_handler PORT1_Handler
def_default_handler PORT2_Handler
def_default_handler PORT3_Handler
def_default_handler DMA_Handler
def_default_handler DUALTIMER0_Handler
def_default_handler DUALTIMER1_Handler
def_default_handler PWM0_Handler
def_default_handler PWM1_Handler
def_default_handler PWM2_Handler
def_default_handler PWM3_Handler
def_default_handler PWM4_Handler
def_default_handler PWM5_Handler
def_default_handler PWM6_Handler
def_default_handler PWM7_Handler
def_default_handler RTC_Handler
def_default_handler ADC_Handler
def_default_handler WZTOE_Handler
def_default_handler EXTI_Handler
/*
def_default_handler Default_Handler
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
*/
.end

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/* mbed Microcontroller Library
* A generic CMSIS include header
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "W7500x.h"
#include "cmsis_nvic.h"
#endif

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/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
vectors[IRQn + 16] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
// Return the vector
return vectors[IRQn + 16];
}

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/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS 41
#define NVIC_USER_IRQ_OFFSET 16
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

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/**************************************************************************//**
* @file system_CMSDK_CM0.c
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for
* Device CMSDK
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include "system_W7500x.h"
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
//#define SYSCLK_EXTERN_OSC
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemFrequency = 0; /*!< System Clock Frequency (Core Clock) */
uint32_t SystemCoreClock = 0; /*!< Processor Clock Frequency */
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
uint8_t M,N,OD;
#ifdef SYSCLK_EXTERN_OSC
CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK;
#else
CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK;
#endif
OD = (1 << (CRG->PLL_FCR & 0x01)) * (1 << ((CRG->PLL_FCR & 0x02) >> 1));
N = (CRG->PLL_FCR >> 8 ) & 0x3F;
M = (CRG->PLL_FCR >> 16) & 0x3F;
#ifdef SYSCLK_EXTERN_OSC
SystemCoreClock = EXTERN_XTAL * M / N * 1 / OD;
#else
SystemCoreClock = INTERN_XTAL * M / N * 1 / OD;
#endif
}
uint32_t GetSystemClock()
{
return SystemCoreClock;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
uint8_t M,N,OD;
(*((volatile uint32_t *)(W7500x_TRIM_BGT))) = (*((volatile uint32_t *)(W7500x_INFO_BGT)));
(*((volatile uint32_t *)(W7500x_TRIM_OSC))) = (*((volatile uint32_t *)(W7500x_INFO_OSC)));
// Set PLL input frequency
#ifdef SYSCLK_EXTERN_OSC
CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK;
#else
CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK;
#endif
OD = (1 << (CRG->PLL_FCR & 0x01)) * (1 << ((CRG->PLL_FCR & 0x02) >> 1));
N = (CRG->PLL_FCR >> 8 ) & 0x3F;
M = (CRG->PLL_FCR >> 16) & 0x3F;
#ifdef SYSCLK_EXTERN_OSC
SystemCoreClock = EXTERN_XTAL * M / N * 1 / OD;
#else
SystemCoreClock = INTERN_XTAL * M / N * 1 / OD;
#endif
}

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/**************************************************************************//**
* @file system_W7500x.h
* @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File for
* Device W7500x
* @version V3.10
* @date 23. November 2012
*
* @note
*
******************************************************************************/
/* Copyright (c) 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef SYSTEM_W7500x_H /* ToDo: replace '<Device>' with your device name */
#define SYSTEM_W7500x_H
#ifdef __cplusplus
extern "C" {
#endif
#include "W7500x.h"
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t GetSystemClock(void); /*!< Get System Clock Frequency */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define EXTERN_XTAL (8000000UL) /* External Oscillator Frequency */
#define INTERN_XTAL (8000000UL) /* Internal Oscillator Frequency */
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_W7500x_H */

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#include "W7500x.h"
void ADC_PowerDownEnable (FunctionalState NewState)
{
if (NewState != DISABLE) ADC->ADC_CTR = ADC_CTR_PWD_PD;
else ADC->ADC_CTR = ADC_CTR_PWD_NRMOP;
}
void ADC_ChannelSelect (ADC_CH num)
{
assert_param(IS_ADC_CH_NUM(num));
ADC->ADC_CHSEL = num;
}
void ADC_Start (void)
{
ADC->ADC_START = ADC_START_START;
}
uint16_t ADC_ReadData (void)
{
return ((uint16_t)ADC->ADC_DATA);
}
void ADC_InterruptMask (FunctionalState NewState)
{
if (NewState != DISABLE) ADC->ADC_INT = ADC_INT_MASK_ENA;
else ADC->ADC_INT = ADC_INT_MASK_DIS;
}
uint8_t ADC_IsInterrupt (void)
{
return (((uint8_t)ADC->ADC_INT && 0x01ul));
}
void ADC_InterruptClear (void)
{
ADC->ADC_INT = ADC_INTCLEAR;
}
void ADC_Init (void)
{
// ADC_CLK on
ADC_PowerDownEnable(DISABLE);
//ADC_ChannelSelect(num);
}
void ADC_DeInit (void)
{
// ADC_CLK off
ADC_PowerDownEnable(ENABLE);
ADC_InterruptMask(DISABLE);
}

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/**
******************************************************************************
* @file
* @author
* @version
* @date
* @brief This file contains all the functions prototypes for the ADC
* firmware library.
******************************************************************************
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __W7500X_ADC_H
#define __W7500X_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "W7500x.h"
typedef enum { ADC_CH0 = 0,
ADC_CH1 = 1,
ADC_CH2 = 2,
ADC_CH3 = 3,
ADC_CH4 = 4,
ADC_CH5 = 5,
ADC_CH6 = 6,
ADC_CH7 = 7,
ADC_CH15 = 15} ADC_CH;
#define IS_ADC_CH_NUM(NUM) (((NUM) == ADC_CH0) || \
((NUM) == ADC_CH1) || \
((NUM) == ADC_CH2) || \
((NUM) == ADC_CH3) || \
((NUM) == ADC_CH4) || \
((NUM) == ADC_CH5) || \
((NUM) == ADC_CH6) || \
((NUM) == ADC_CH7) || \
((NUM) == ADC_CH15))
void ADC_Init(void);
void ADC_DeInit(void);
void ADC_PowerDownEnable (FunctionalState NewState);
void ADC_ChannelSelect (ADC_CH num);
void ADC_Start (void);
uint16_t ADC_ReadData (void);
void ADC_InterruptMask (FunctionalState NewState);
uint8_t ADC_IsInterrupt (void);
void ADC_InterruptClear (void);
#ifdef __cplusplus
}
#endif
#endif //__W7500X_ADC_H

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#include "W7500x_gpio.h"
#include "W7500x_exti.h"
#include "W7500x_pwm.h"
#include "W7500x_uart.h"
#include "W7500x_i2c.h"
#include "W7500x_adc.h"
#include "system_W7500x.h"
#ifdef USE_FULL_ASSERT
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__,__LINE__))
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */

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#include "W7500x_crg.h"
void CRG_DeInit(void)
{
//To Do
}
void CRG_OSC_PowerDownEnable(FunctionalState NewState)
{
if(NewState != DISABLE) CRG->OSC_PDR = CRG_OSC_PDR_PD;
else CRG->OSC_PDR = CRG_OSC_PDR_NRMLOP;
}
void CRG_PLL_PowerDownEnable(FunctionalState NewState)
{
if(NewState != DISABLE) CRG->PLL_PDR = CRG_PLL_PDR_PD;
else CRG->PLL_PDR = CRG_PLL_PDR_NRMLOP;
}
void CRG_PLL_OutputEnable(FunctionalState NewState)
{
if(NewState != DISABLE) CRG->PLL_OER = CRG_PLL_OER_EN;
else CRG->PLL_OER = CRG_PLL_OER_DIS;
}
void CRG_PLL_BypassEnable(FunctionalState NewState)
{
if(NewState != DISABLE) CRG->PLL_BPR = CRG_PLL_BPR_EN;
else CRG->PLL_BPR = CRG_PLL_BPR_DIS;
}
void CRG_PLL_InputFrequencySelect(CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_PLL_SRC(src));
if( src == CRG_RCLK ) CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK;
else CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK;
}
void CRG_FCLK_SourceSelect(CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_FCLK_SRC(src));
if ( src == CRG_RCLK ) CRG->FCLK_SSR = CRG_FCLK_SSR_RCLK;
else if ( src == CRG_OCLK ) CRG->FCLK_SSR = CRG_FCLK_SSR_OCLK;
else CRG->FCLK_SSR = CRG_FCLK_SSR_MCLK;
}
void CRG_FCLK_SetPrescale(CRG_PREDIV prediv)
{
assert_param(IS_CRG_FCLK_PREDIV(prediv));
if ( prediv == CRG_PREDIV1 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV1;
else if ( prediv == CRG_PREDIV2 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV2;
else if ( prediv == CRG_PREDIV4 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV4;
else CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV8;
}
void CRG_SSPCLK_SourceSelect(CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_SSPCLK_SRC(src));
if ( src == CRG_CLK_DIS ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_DIS;
else if ( src == CRG_MCLK ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK;
else if ( src == CRG_RCLK ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_RCLK;
else CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_OCLK;
}
void CRG_SSPCLK_SetPrescale(CRG_PREDIV prediv)
{
assert_param(IS_CRG_SSPCLK_PREDIV(prediv));
if ( prediv == CRG_PREDIV1 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1;
else if ( prediv == CRG_PREDIV2 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV2;
else if ( prediv == CRG_PREDIV4 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV4;
else CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV8;
}
void CRG_ADCCLK_SourceSelect(CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_ADCCLK_SRC(src));
if ( src == CRG_CLK_DIS ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_DIS;
else if ( src == CRG_MCLK ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_MCLK;
else if ( src == CRG_RCLK ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_RCLK;
else CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_OCLK;
}
void CRG_ADCCLK_SetPrescale(CRG_PREDIV prediv)
{
assert_param(IS_CRG_ADCCLK_PREDIV(prediv));
if ( prediv == CRG_PREDIV1 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV1;
else if ( prediv == CRG_PREDIV2 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV2;
else if ( prediv == CRG_PREDIV4 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV4;
else CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV8;
}
void CRG_TIMERCLK_SourceSelect(CRG_TIMER num, CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_TIMERCLK_NUM(num));
assert_param(IS_CRG_TIMERCLK_SRC(src));
if ( src == CRG_CLK_DIS ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_DIS);
else if ( src == CRG_MCLK ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_MCLK);
else if ( src == CRG_RCLK ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_RCLK);
else CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_OCLK);
}
void CRG_TIMERCLK_SetPrescale(CRG_TIMER num, CRG_PREDIV prediv)
{
assert_param(IS_CRG_TIMERCLK_NUM(num));
assert_param(IS_CRG_TIMERCLK_PREDIV(prediv));
if ( prediv == CRG_PREDIV1 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV1);
else if ( prediv == CRG_PREDIV2 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV2);
else if ( prediv == CRG_PREDIV4 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV4);
else if ( prediv == CRG_PREDIV8 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV8);
else if ( prediv == CRG_PREDIV16 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV16);
else if ( prediv == CRG_PREDIV32 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV32);
else if ( prediv == CRG_PREDIV64 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV64);
else CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV128);
}
void CRG_PWMCLK_SourceSelect(CRG_PWM num, CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_PWMCLK_NUM(num));
assert_param(IS_CRG_PWMCLK_SRC(src));
if ( src == CRG_CLK_DIS ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_DIS);
else if ( src == CRG_MCLK ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_MCLK);
else if ( src == CRG_RCLK ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_RCLK);
else CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_OCLK);
}
void CRG_PWMCLK_SetPrescale(CRG_PWM num, CRG_PREDIV prediv)
{
assert_param(IS_CRG_PWMCLK_NUM(num));
assert_param(IS_CRG_PWMCLK_PREDIV(prediv));
if ( prediv == CRG_PREDIV1 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV1);
else if ( prediv == CRG_PREDIV2 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV2);
else if ( prediv == CRG_PREDIV4 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV4);
else if ( prediv == CRG_PREDIV8 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV8);
else if ( prediv == CRG_PREDIV16 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV16);
else if ( prediv == CRG_PREDIV32 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV32);
else if ( prediv == CRG_PREDIV64 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV64);
else CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV128);
}
void CRG_RTC_HS_SourceSelect(CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_RTC_HS_SRC(src));
if ( src == CRG_CLK_DIS ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_DIS;
else if ( src == CRG_MCLK ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_MCLK;
else if ( src == CRG_RCLK ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_RCLK;
else CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_OCLK;
if ( src != CRG_CLK_DIS ) CRG_RTC_SourceSelect(CRG_CLK_HIGH);
}
void CRG_RTC_HS_SetPrescale(CRG_PREDIV prediv)
{
assert_param(IS_CRG_RTC_HS_PREDIV(prediv));
if ( prediv == CRG_PREDIV1 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV1;
else if ( prediv == CRG_PREDIV2 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV2;
else if ( prediv == CRG_PREDIV4 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV4;
else if ( prediv == CRG_PREDIV8 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV8;
else if ( prediv == CRG_PREDIV16 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV16;
else if ( prediv == CRG_PREDIV32 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV32;
else if ( prediv == CRG_PREDIV64 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV64;
else CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV128;
}
void CRG_RTC_SourceSelect(CRG_CLK_LOW_SOURCE src)
{
assert_param(IS_CRG_RTC_LOW_SRC(src));
if (src == CRG_CLK_LOW)
{
CRG_RTC_HS_SourceSelect(CRG_CLK_DIS);
CRG->RTC_SSR = CRG_RTC_SSR_LW;
}
else
{
CRG->RTC_SSR = CRG_RTC_SSR_HS;
}
}
void CRG_WDOGCLK_HS_SourceSelect(CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_WDOGCLK_HS_SRC(src));
if ( src == CRG_CLK_DIS ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_DIS;
else if ( src == CRG_MCLK ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_MCLK;
else if ( src == CRG_RCLK ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_RCLK;
else CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_OCLK;
if ( src != CRG_CLK_DIS ) CRG_WDOGCLK_SourceSelect(CRG_CLK_HIGH);
}
void CRG_WDOGCLK_HS_SetPrescale(CRG_PREDIV prediv)
{
assert_param(IS_CRG_WDOGCLK_HS_PREDIV(prediv));
if ( prediv == CRG_PREDIV1 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV1;
else if ( prediv == CRG_PREDIV2 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV2;
else if ( prediv == CRG_PREDIV4 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV4;
else if ( prediv == CRG_PREDIV8 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV8;
else if ( prediv == CRG_PREDIV16 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV16;
else if ( prediv == CRG_PREDIV32 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV32;
else if ( prediv == CRG_PREDIV64 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV64;
else CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV128;
}
void CRG_WDOGCLK_SourceSelect(CRG_CLK_LOW_SOURCE src)
{
assert_param(IS_CRG_WDOGCLK_LOW_SRC(src));
if (src == CRG_CLK_LOW)
{
CRG_WDOGCLK_HS_SourceSelect(CRG_CLK_DIS);
CRG->WDOGCLK_SSR = CRG_WDOGCLK_SSR_LW;
}
else
{
CRG->WDOGCLK_SSR = CRG_WDOGCLK_SSR_HS;
}
}
void CRG_UARTCLK_SourceSelect(CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_UARTCLK_SRC(src));
if ( src == CRG_CLK_DIS ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_DIS;
else if ( src == CRG_MCLK ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_MCLK;
else if ( src == CRG_RCLK ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK;
else CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_OCLK;
}
void CRG_UARTCLK_SetPrescale(CRG_PREDIV prediv)
{
assert_param(IS_CRG_UARTCLK_PREDIV(prediv));
if ( prediv == CRG_PREDIV1 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV1;
else if ( prediv == CRG_PREDIV2 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV2;
else if ( prediv == CRG_PREDIV4 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV4;
else CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV8;
}
void CRG_MII_Enable(FunctionalState rx_clk, FunctionalState tx_clk)
{
assert_param(IS_FUNCTIONAL_STATE(rx_clk));
assert_param(IS_FUNCTIONAL_STATE(tx_clk));
if ( rx_clk != DISABLE ) CRG->MIICLK_ECR |= CRG_MIICLK_ECR_EN_RXCLK;
else CRG->MIICLK_ECR &= ~(CRG_MIICLK_ECR_EN_RXCLK);
if ( tx_clk != DISABLE ) CRG->MIICLK_ECR |= CRG_MIICLK_ECR_EN_TXCLK;
else CRG->MIICLK_ECR &= ~(CRG_MIICLK_ECR_EN_TXCLK);
}
void CRG_SetMonitoringClock(uint32_t value)
{
assert_param(IS_CRG_MONCLK_SSR(value));
CRG->MONCLK_SSR = value;
}
uint32_t CRG_GetMonitoringClock(void)
{
return (uint8_t)CRG->MONCLK_SSR;
}

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/**
******************************************************************************
* @file
* @author
* @version
* @date
* @brief This file contains all the functions prototypes for the Clock Reset Generator
* firmware library.
******************************************************************************
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __W7500X_CRG_H
#define __W7500X_CRG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "W7500x.h"
// It will be in W7500x_crg.h
typedef enum { CRG_CLK_DIS = 0, CRG_MCLK, CRG_RCLK, CRG_OCLK } CRG_CLK_SOURCE;
typedef enum { CRG_CLK_HIGH = 0, CRG_CLK_LOW } CRG_CLK_LOW_SOURCE;
typedef enum { CRG_PREDIV1 = 0, CRG_PREDIV2, CRG_PREDIV4, CRG_PREDIV8, CRG_PREDIV16, \
CRG_PREDIV32, CRG_PREDIV64, CRG_PREDIV128 } CRG_PREDIV;
typedef enum { CRG_TIMER0 = 0, CRG_TIMER1 } CRG_TIMER;
typedef enum { CRG_PWM0 = 0, CRG_PWM1, CRG_PWM2, CRG_PWM3, CRG_PWM4, CRG_PWM5, CRG_PWM6, CRG_PWM7 } CRG_PWM;
#define IS_CRG_PLL_SRC(SRC) (((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK))
#define IS_CRG_FCLK_SRC(SRC) (((SRC) == CRG_MCLK) || ((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK))
#define CRG_CLK_SRC_DEFAULT(SRC) (((SRC) == CRG_CLK_DIS) || ((SRC) == CRG_MCLK) || \
((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK))
#define CRG_CLK_SRC_LOW(SRC) (((SRC) == CRG_CLK_HIGH) || ((SRC) == CRG_CLK_LOW))
#define CRG_CLK_PREDIV_DEFAULT(DIV) (((DIV) == CRG_PREDIV1) || ((DIV) == CRG_PREDIV2) || \
((DIV) == CRG_PREDIV4) || ((DIV) == CRG_PREDIV8))
#define CRG_CLK_PREDIV_ADVANCE(DIV) (((DIV) == CRG_PREDIV1) || ((DIV) == CRG_PREDIV2) || \
((DIV) == CRG_PREDIV4) || ((DIV) == CRG_PREDIV8) || \
((DIV) == CRG_PREDIV16) || ((DIV) == CRG_PREDIV32) || \
((DIV) == CRG_PREDIV64) || ((DIV) == CRG_PREDIV128))
#define IS_CRG_FCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
#define IS_CRG_SSPCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
#define IS_CRG_SSPCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
#define IS_CRG_ADCCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
#define IS_CRG_ADCCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
#define IS_CRG_TIMERCLK_NUM(NUM) (((NUM) == CRG_TIMER0) || ((NUM) == CRG_TIMER1))
#define IS_CRG_TIMERCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
#define IS_CRG_TIMERCLK_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
#define CRG_SET_TIMERCLK_SSR(NUM,VALUE) \
(*((volatile uint32_t *)(CRG->TIMER0CLK_SSR) + (0x10ul * NUM)) = VALUE)
#define CRG_SET_TIMERCLK_PREDIV(NUM,VALUE) \
(*((volatile uint32_t *)(CRG->TIMER0CLK_PVSR) + (0x10ul * NUM)) = VALUE)
//#define CRG_SET_TIMERCLK_SSR(num,value) CRG->TIMER##num##CLK_SSR = value
//#define CRG_SET_TIMERCLK_PREDIV(num,value) CRG->TIMER##num##CLK_PVSR = value
#define IS_CRG_PWMCLK_NUM(NUM) (((NUM) == CRG_PWM0) || ((NUM) == CRG_PWM1) || \
((NUM) == CRG_PWM2) || ((NUM) == CRG_PWM3) || \
((NUM) == CRG_PWM4) || ((NUM) == CRG_PWM5) || \
((NUM) == CRG_PWM6) || ((NUM) == CRG_PWM7) )
#define IS_CRG_PWMCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
#define IS_CRG_PWMCLK_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
#define CRG_SET_PWMCLK_SSR(NUM,VALUE) \
(*((volatile uint32_t *)(CRG->PWM0CLK_SSR) + (0x10ul * NUM)) = VALUE)
#define CRG_SET_PWMCLK_PREDIV(NUM,VALUE) \
(*((volatile uint32_t *)(CRG->PWM0CLK_PVSR) + (0x10ul * NUM)) = VALUE)
//#define CRG_SET_PWMCLK_SSR(num,value) CRG->PWM##num##CLK_SSR = value
//#define CRG_SET_PWMCLK_PREDIV(num,value) CRG->PWM##num##CLK_PVSR = value
#define IS_CRG_RTC_HS_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
#define IS_CRG_RTC_HS_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
#define IS_CRG_RTC_LOW_SRC(SRC) CRG_CLK_SRC_LOW(SRC)
#define IS_CRG_WDOGCLK_HS_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
#define IS_CRG_WDOGCLK_HS_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
#define IS_CRG_WDOGCLK_LOW_SRC(SRC) CRG_CLK_SRC_LOW(SRC)
#define IS_CRG_UARTCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
#define IS_CRG_UARTCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
#define IS_CRG_MONCLK_SSR(value) (((value) >= 0x00ul) || ((value) <= 0x13ul))
void CRG_DeInit(void);
void CRG_OSC_PowerDownEnable (FunctionalState NewState);
void CRG_PLL_PowerDownEnable (FunctionalState NewState);
void CRG_PLL_OutputEnable (FunctionalState NewState);
void CRG_PLL_BypassEnable (FunctionalState NewState);
void CRG_PLL_InputFrequencySelect (CRG_CLK_SOURCE src);
void CRG_FCLK_SourceSelect (CRG_CLK_SOURCE src);
void CRG_FCLK_SetPrescale (CRG_PREDIV prediv);
void CRG_SSPCLK_SourceSelect (CRG_CLK_SOURCE src);
void CRG_SSPCLK_SetPrescale (CRG_PREDIV prediv);
void CRG_ADCCLK_SourceSelect (CRG_CLK_SOURCE src);
void CRG_ADCCLK_SetPrescale (CRG_PREDIV prediv);
void CRG_TIMERCLK_SourceSelect (CRG_TIMER num, CRG_CLK_SOURCE src);
void CRG_TIMERCLK_SetPrescale (CRG_TIMER num, CRG_PREDIV prediv);
void CRG_PWMCLK_SourceSelect (CRG_PWM num, CRG_CLK_SOURCE src);
void CRG_PWMCLK_SetPrescale (CRG_PWM num, CRG_PREDIV prediv);
void CRG_RTC_HS_SourceSelect (CRG_CLK_SOURCE src);
void CRG_RTC_HS_SetPrescale (CRG_PREDIV prediv);
void CRG_RTC_SourceSelect (CRG_CLK_LOW_SOURCE src);
void CRG_WDOGCLK_HS_SourceSelect (CRG_CLK_SOURCE src);
void CRG_WDOGCLK_HS_SetPrescale (CRG_PREDIV prediv);
void CRG_WDOGCLK_SourceSelect (CRG_CLK_LOW_SOURCE src);
void CRG_UARTCLK_SourceSelect (CRG_CLK_SOURCE src);
void CRG_UARTCLK_SetPrescale (CRG_PREDIV prediv);
void CRG_MII_Enable (FunctionalState rx_clk, FunctionalState tx_clk);
void CRG_SetMonitoringClock (uint32_t value);
uint32_t CRG_GetMonitoringClock (void);
#ifdef __cplusplus
}
#endif
#endif

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#include "W7500x.h"
/**
* @brief Deinitializes the EXTI peripheral registers to their default reset values.
* @param None
* @retval None
*/
void EXTI_DeInit(void)
{
uint32_t i, loop =16;
for(i=0; i<loop; i++)
{
EXTI_PA->Port[i] = 0x00;
EXTI_PB->Port[i] = 0x00;
EXTI_PC->Port[i] = 0x00;
}
for(i=0; i<5; i++)
{
EXTI_PD->Port[i] = 0x00;
}
}
/**
* @brief Initializes the EXTI peripheral according to the specified
* parameters in the EXTI_InitStruct.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
* that contains the configuration information for the EXTI peripheral.
* @retval None
*/
void EXTI_Init(PAD_Type Px, EXTI_InitTypeDef* EXTI_InitStruct)
{
uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16;
P_Port_Def *px_exti;
assert_param(IS_PAD_TYPE(Px));
if (Px == PAD_PA) px_exti = EXTI_PA;
else if (Px == PAD_PB) px_exti = EXTI_PB;
else if (Px == PAD_PC) px_exti = EXTI_PC;
else
{
px_exti = (P_Port_Def*)EXTI_PD;
loop = 5;
}
for(pinpos = 0x00; pinpos < loop; pinpos++)
{
pos = ((uint32_t)0x01) << pinpos;
currentpin = (EXTI_InitStruct->EXTI_Line) & pos;
if(currentpin == pos)
{
px_exti->Port[pinpos] |= EXTI_Px_INTEN_ENABLE;
if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising)
px_exti->Port[pinpos] |= EXTI_Px_INTPOR_RISING_EDGE;
else
px_exti->Port[pinpos] |= EXTI_Px_INTPOR_FALLING_EDGE;
}
}
}
void EXTI_Polarity_Set(PAD_Type Px, uint16_t GPIO_Pin, uint16_t Polarity )
{
uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16;
P_Port_Def *px_exti;
assert_param(IS_PAD_TYPE(Px));
if (Px == PAD_PA) px_exti = EXTI_PA;
else if (Px == PAD_PB) px_exti = EXTI_PB;
else if (Px == PAD_PC) px_exti = EXTI_PC;
else
{
px_exti = (P_Port_Def*)EXTI_PD;
loop = 5;
}
for(pinpos = 0x00; pinpos < loop; pinpos++)
{
pos = ((uint32_t)0x01) << pinpos;
currentpin = GPIO_Pin & pos;
if(currentpin == pos)
{
if(Polarity == EXTI_Trigger_Rising)
px_exti->Port[pinpos] |= EXTI_Px_INTPOR_RISING_EDGE;
else
px_exti->Port[pinpos] |= EXTI_Px_INTPOR_FALLING_EDGE;
}
}
}
/**
* @brief Fills each EXTI_InitStruct member with its reset value.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
{
EXTI_InitStruct->EXTI_Line = 0xFF;
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
}
uint16_t EXTI_Px_GetEXTEN(PAD_Type Px)
{
uint32_t i, loop = 16;
uint16_t ret=0;
P_Port_Def *px_exti;
assert_param(IS_PAD_TYPE(Px));
if (Px == PAD_PA) px_exti = EXTI_PA;
else if (Px == PAD_PB) px_exti = EXTI_PB;
else if (Px == PAD_PC) px_exti = EXTI_PC;
else
{
px_exti = (P_Port_Def*)EXTI_PD;
loop = 5;
}
for(i = 0x00; i < loop; i++)
{
ret |= (((px_exti->Port[i]&0x2)>>1)<<i);
}
return ret;
}
uint16_t EXTI_Px_GetEXTINTPOL(PAD_Type Px)
{
uint32_t i, loop = 16;
uint16_t ret=0;
P_Port_Def *px_exti;
assert_param(IS_PAD_TYPE(Px));
if (Px == PAD_PA) px_exti = EXTI_PA;
else if (Px == PAD_PB) px_exti = EXTI_PB;
else if (Px == PAD_PC) px_exti = EXTI_PC;
else
{
px_exti = (P_Port_Def*)EXTI_PD;
loop = 5;
}
for(i = 0x00; i < loop; i++)
{
ret |= ((px_exti->Port[i]&0x1)<<i);
}
return ret;
}

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/**
******************************************************************************
* @file
* @author
* @version
* @date
* @brief This file contains all the functions prototypes for the GPIO
* firmware library.
******************************************************************************
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __W7500X_EXTI_H
#define __W7500X_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "W7500x.h"
/**
* @brief EXTI mode enumeration
*/
typedef enum
{
EXTI_Mode_Disable = 0x00,
EXTI_Mode_Interrupt = 0x02
}EXTIMode_TypeDef;
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Rising) || \
((MODE) == EXTI_Mode_Interrupt))
/**
* @brief EXTI Trigger enumeration
*/
typedef enum
{
EXTI_Trigger_Rising = 0x00,
EXTI_Trigger_Falling = 0x01
}EXTITrigger_TypeDef;
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
((TRIGGER) == EXTI_Trigger_Falling))
/**
* @brief EXTI Init Structure definition
*/
typedef struct
{
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
This parameter can be any combination of @ref EXTI_Lines */
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.This parameter can be a value of @ref EXTIMode_TypeDef */
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */
}EXTI_InitTypeDef;
/**
* @}
*/
void EXTI_DeInit(void);
void EXTI_Init(PAD_Type Px, EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_Polarity_Set(PAD_Type Px, uint16_t GPIO_Pin, uint16_t Polarity );
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
uint32_t EXTI_GetEXTIConfig(PAD_Type Px, uint16_t GPIO_Pin);
uint16_t EXTI_Px_GetEXTEN(PAD_Type Px);
uint16_t EXTI_Px_GetEXTINTPOL(PAD_Type Px);
#ifdef __cplusplus
}
#endif
#endif //__W7500X_EXTI_H

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#include "W7500x.h"
void HAL_GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
uint32_t i, loop =16;
P_Port_Def *px_pcr;
P_Port_Def *px_afsr;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
/* DeInit GPIOx Registers */
GPIOx->DATA = 0x0000;
GPIOx->DATAOUT = 0x0000;
//GPIOx->OUTENSET = 0x0000;
GPIOx->OUTENCLR = 0xFFFF;
//GPIOx->INTENSET = 0x0000;
GPIOx->INTENCLR = 0xFFFF;
//GPIOx->INTTYPESET = 0x0000;
GPIOx->INTTYPECLR = 0xFFFF;
//GPIOx->INTPOLSET = 0x0000;
GPIOx->INTPOLCLR = 0xFFFF;
/* DeInit GPIOx
* Pad Control Register
* Pad Extern interrupt Enable Register
* Pad Alternate Function Select Register
*/
if (GPIOx == GPIOA)
{
px_pcr = PA_PCR;
px_afsr = PA_AFSR;
}
else if (GPIOx == GPIOB)
{
px_pcr = PB_PCR;
px_afsr = PB_AFSR;
}
else if (GPIOx == GPIOC)
{
px_pcr = PC_PCR;
px_afsr = PC_AFSR;
}
else // if (GPIOx == GPIOD)
{
px_pcr = (P_Port_Def*)PD_PCR;
px_afsr = (P_Port_Def*)PD_AFSR;
loop = 5;
}
for(i=0; i<loop; i++)
{
px_pcr->Port[i] = 0x60;
px_afsr->Port[i] = PAD_AF0;
}
}
void HAL_GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16;
P_Port_Def *px_pcr;
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
// assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
if (GPIOx == GPIOA) px_pcr = PA_PCR;
else if (GPIOx == GPIOB) px_pcr = PB_PCR;
else if (GPIOx == GPIOC) px_pcr = PC_PCR;
else
{
px_pcr = (P_Port_Def*)PD_PCR;
loop = 5;
}
for(pinpos = 0x00; pinpos < loop; pinpos++)
{
pos = ((uint32_t)0x01) << pinpos;
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
if(currentpin == pos)
{
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT)
{
GPIOx->OUTENSET |= pos;
}
else // GPIO_Mode_In
{
GPIOx->OUTENCLR = pos;
}
// Configure pull-up pull-down bits
if(GPIO_InitStruct->GPIO_Pad & Px_PCR_PUPD_UP)
{
px_pcr->Port[pinpos] &= ~(Px_PCR_PUPD_UP | Px_PCR_PUPD_DOWN);
px_pcr->Port[pinpos] |= Px_PCR_PUPD_UP;
}
else
{
px_pcr->Port[pinpos] &= ~(Px_PCR_PUPD_UP | Px_PCR_PUPD_DOWN);
px_pcr->Port[pinpos] |= Px_PCR_PUPD_DOWN;
}
// Configure Driving stregnth selections bit
if(GPIO_InitStruct->GPIO_Pad & Px_PCR_DS_HIGH)
{
px_pcr->Port[pinpos] |= Px_PCR_DS_HIGH;
}
else
{
px_pcr->Port[pinpos] &= ~(Px_PCR_DS_HIGH);
}
// Configure Open Drain selections bit
if(GPIO_InitStruct->GPIO_Pad & Px_PCR_OD)
{
px_pcr->Port[pinpos] |= Px_PCR_OD;
}
else
{
px_pcr->Port[pinpos] &= ~(Px_PCR_OD);
}
// Configure Input buffer enable selection bit
if(GPIO_InitStruct->GPIO_Pad & Px_PCR_IE)
{
px_pcr->Port[pinpos] |= Px_PCR_IE;
}
else
{
px_pcr->Port[pinpos] &= ~(Px_PCR_IE);
}
// Configure input type (CMOS input or Summit trigger input) select bit
if(GPIO_InitStruct->GPIO_Pad & Px_PCR_CS_SUMMIT)
{
px_pcr->Port[pinpos] |= Px_PCR_CS_SUMMIT;
}
else
{
px_pcr->Port[pinpos] &= ~(Px_PCR_CS_SUMMIT);
}
}
}
}
void HAL_GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
{
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
GPIO_InitStruct->GPIO_Pad = (GPIOPad_TypeDef)(GPIO_PuPd_UP);
}
uint8_t HAL_GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if((GPIOx->DATA & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
uint8_t HAL_GPIO_ReadInputData(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
return ((uint16_t)GPIOx->DATA);
}
uint8_t HAL_GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if((GPIOx->DATAOUT & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
uint16_t HAL_GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALLPERIPH(GPIOx));
return ((uint16_t)GPIOx->DATAOUT);
}
void HAL_GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
(GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = GPIO_Pin;
(GPIOx->UB_MASKED[(uint8_t)((GPIO_Pin)>>8)]) = GPIO_Pin;
}
void HAL_GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
(GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = ~(GPIO_Pin);
(GPIOx->UB_MASKED[(uint8_t)(GPIO_Pin>>8)]) = ~(GPIO_Pin);
}
void HAL_GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_BIT_ACTION(BitVal));
(GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = BitVal;
(GPIOx->UB_MASKED[(uint8_t)((GPIO_Pin)>>8)]) = BitVal;
}
void HAL_GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
GPIOx->DATAOUT = PortVal;
}
void HAL_PAD_AFConfig(PAD_Type Px, uint16_t GPIO_Pin, PAD_AF_TypeDef P_AF)
{
int i;
uint16_t idx =0x1;
assert_param(IS_PAD_Type(Px));
for(i=0;i<16;i++)
{
if(GPIO_Pin & (idx<<i))
{
if(Px == PAD_PA)
{
assert_param(IS_PA_NUM(i));
PA_AFSR->Port[i] &= ~(0x03ul);
PA_AFSR->Port[i] |= P_AF;
}
else if(Px == PAD_PB)
{
assert_param(IS_PB_NUM(i));
PB_AFSR->Port[i] &= ~(0x03ul);
PB_AFSR->Port[i] |= P_AF;
}
else if(Px == PAD_PC)
{
assert_param(IS_PC_NUM(i));
PC_AFSR->Port[i] &= ~(0x03ul);
PC_AFSR->Port[i] |= P_AF;
}
else
{
assert_param(IS_PD_NUM(i));
PD_AFSR->Port[i] &= ~(0x03ul);
PD_AFSR->Port[i] |= P_AF;
}
}
}
}

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/**
******************************************************************************
* @file
* @author
* @version
* @date
* @brief This file contains all the functions prototypes for the GPIO
* firmware library.
******************************************************************************
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __W7500X_HAL_GPIO_H
#define __W7500X_HAL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "W7500x.h"
#define GPIO_Pin_0 (uint16_t)(0x01 << 0) // Pin 0 Selected
#define GPIO_Pin_1 (uint16_t)(0x01 << 1) // Pin 1 Selected
#define GPIO_Pin_2 (uint16_t)(0x01 << 2) // Pin 2 Selected
#define GPIO_Pin_3 (uint16_t)(0x01 << 3) // Pin 3 Selected
#define GPIO_Pin_4 (uint16_t)(0x01 << 4) // Pin 4 Selected
#define GPIO_Pin_5 (uint16_t)(0x01 << 5) // Pin 5 Selected
#define GPIO_Pin_6 (uint16_t)(0x01 << 6) // Pin 6 Selected
#define GPIO_Pin_7 (uint16_t)(0x01 << 7) // Pin 7 Selected
#define GPIO_Pin_8 (uint16_t)(0x01 << 8) // Pin 8 Selected
#define GPIO_Pin_9 (uint16_t)(0x01 << 9) // Pin 9 Selected
#define GPIO_Pin_10 (uint16_t)(0x01 << 10) // Pin 10 Selected
#define GPIO_Pin_11 (uint16_t)(0x01 << 11) // Pin 11 Selected
#define GPIO_Pin_12 (uint16_t)(0x01 << 12) // Pin 12 Selected
#define GPIO_Pin_13 (uint16_t)(0x01 << 13) // Pin 13 Selected
#define GPIO_Pin_14 (uint16_t)(0x01 << 14) // Pin 14 Selected
#define GPIO_Pin_15 (uint16_t)(0x01 << 15) // Pin 15 Selected
#define GPIO_Pin_All (uint16_t)(0xFFFF) // All pins Selected
#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || \
(((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3) || \
(((PIN) == GPIO_Pin_4) || ((PIN) == GPIO_Pin_5) || \
(((PIN) == GPIO_Pin_6) || ((PIN) == GPIO_Pin_7) || \
(((PIN) == GPIO_Pin_8) || ((PIN) == GPIO_Pin_9) || \
(((PIN) == GPIO_Pin_10) || ((PIN) == GPIO_Pin_11) || \
(((PIN) == GPIO_Pin_12) || ((PIN) == GPIO_Pin_13) || \
(((PIN) == GPIO_Pin_14) || ((PIN) == GPIO_Pin_15) )
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || \
((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) )
typedef enum
{
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
GPIO_Mode_AF = 0x02 /*!< GPIO Alternate function Mode */
}GPIOMode_TypeDef;
typedef enum
{
GPIO_NO_PUPD = 0x0ul,
GPIO_PuPd_UP = Px_PCR_PUPD_UP,
GPIO_PuPd_DOWN = Px_PCR_PUPD_DOWN,
GPIO_OD = Px_PCR_OD,
}GPIOPad_TypeDef;
typedef struct
{
uint32_t GPIO_Pin;
GPIOMode_TypeDef GPIO_Mode;
GPIOPad_TypeDef GPIO_Pad;
}GPIO_InitTypeDef;
typedef enum
{
Bit_RESET = 0,
Bit_SET
}BitAction;
typedef enum
{
PAD_PA = 0,
PAD_PB,
PAD_PC,
PAD_PD
}PAD_Type;
typedef enum
{
PAD_AF0 = Px_AFSR_AF0,
PAD_AF1 = Px_AFSR_AF1,
PAD_AF2 = Px_AFSR_AF2,
PAD_AF3 = Px_AFSR_AF3
}PAD_AF_TypeDef;
#define IS_PAD_TYPE(Px) (((Px) == PAD_PA) || ((Px) == PAD_PB) \
((Px) == PAD_PC) || ((Px) == PAD_PD))
#define IS_PA_NUM(NUM) (((NUM)>=0) && ((NUM)<16))
#define IS_PB_NUM(NUM) (((NUM)>=0) && ((NUM)<16))
#define IS_PC_NUM(NUM) (((NUM)>=0) && ((NUM)<16))
#define IS_PD_NUM(NUM) (((NUM)>=0) && ((NUM)< 5))
#define IS_PAD_AF(AF) (((AF) == PAD_AF0) || ((AF) == PAD_AF1) || \
((AF) == PAD_AF2) || ((AF) == PAD_AF3))
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION_ == Bit_RESET) || (ACTION) ==Bit_SET))
void HAL_GPIO_DeInit(GPIO_TypeDef* GPIOx);
void HAL_GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void HAL_GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
uint8_t HAL_GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint8_t HAL_GPIO_ReadInputData(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint8_t HAL_GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t HAL_GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
void HAL_GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
void HAL_GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
void HAL_PAD_AFConfig(PAD_Type Px, uint16_t Pnum, PAD_AF_TypeDef P_AF);
#ifdef __cplusplus
}
#endif
#endif // __W7500X_HAL_GPIO_H

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#include "W7500x.h"
/** @defgroup I2C_Private_Functions
* @{
*/
/**
* @brief Initializes the I2Cx peripheral according to the specified
* parameters in the I2C_InitStruct.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
* contains the configuration information for the specified I2C peripheral.
* @retval None
*/
void I2C_Delay(uint32_t nCount)
{
for(; nCount != 0; nCount--);
}
uint32_t I2C_Init(I2C_TypeDef* I2Cx, I2C_ConfigStruct conf)
{
uint32_t mode;
uint8_t prescale;
uint16_t timeout;
uint16_t slave_address;
mode = conf.mode;
slave_address = conf.slave_address;
if(mode == I2C_Master)
{
prescale = conf.master.prescale;
timeout = conf.master.timeout;
I2C_CoreEn(I2Cx,ENABLE);
I2C_MasterSlave(I2Cx,ENABLE);
I2C_Prescale(I2Cx,prescale); // 0x61 //When PLL clk is 20MHz and Prescale value set 0x61, SCL is 100KHz
I2C_TimeoutSet(I2Cx,timeout); // 0xFFFF
I2C_CoreEn(I2Cx,DISABLE);
}
else if(conf.mode == I2C_Slave)
{
I2C_AcknowledgeConfig(I2Cx,ENABLE);
I2C_SetSlavAddress(I2Cx,slave_address);
}
else
return ERROR;
I2C_AcknowledgeConfig(I2Cx,ENABLE);
return SUCCESS;
}
void I2C_DeInit(I2C_TypeDef* I2Cx)
{
I2C_InterRst(I2Cx,ENABLE);
I2C_CoreEn(I2Cx, ENABLE);
I2C_InterRst(I2Cx,DISABLE);
I2C_CoreEn(I2Cx, DISABLE);
}
ErrorStatus I2C_Start(I2C_TypeDef* I2Cx, uint16_t slave_address, I2C_CTR ctr)
{
ErrorStatus ret;
I2C_GenerateSTART(I2Cx,ENABLE);
I2C_SendSlaveAddress(I2Cx,slave_address,(I2C_CTR)ctr);
I2C_GenerateSTART(I2Cx,DISABLE);
ret=I2C_CheckEvent(I2Cx,I2C_ACKR);
return ret;
}
void I2C_Stop(I2C_TypeDef* I2Cx)
{
I2C_GenerateSTOP(I2Cx,ENABLE);
I2C_GenerateSTOP(I2Cx,DISABLE);
}
void I2C_Reset(I2C_TypeDef* I2Cx)
{
I2C_CoreEn(I2Cx,ENABLE);
// Maybe, it needs a little delay
I2C_CoreEn(I2Cx,DISABLE);
}
void I2C_SendData(I2C_TypeDef* I2Cx,uint16_t Data)
{
I2Cx -> TXR = (uint16_t)Data;
}
int8_t I2C_SendDataAck(I2C_TypeDef* I2Cx,uint16_t Data)
{
I2Cx -> TXR = (uint16_t)Data;
if(I2C_CheckEvent(I2Cx,I2C_ACKR) == ERROR)
{
return ERROR;
}
return SUCCESS;
}
int I2C_ReceiveData(I2C_TypeDef* I2Cx, int last)
{
if( I2C_CheckEvent(I2Cx,I2C_ACKT) == ERROR )
return -1;
if(last)
{
I2C_AcknowledgeConfig(I2Cx,DISABLE);
if( I2C_CheckEvent(I2Cx,I2C_ACKT) == ERROR )
return -1;
I2C_Stop(I2Cx);
}
return (uint8_t)I2Cx -> RXR;
}
int I2C_Burst_Read(I2C_TypeDef* I2Cx, uint16_t address, uint8_t *data, int length, int stop)
{
int recv_cnt;
if( I2C_Start(I2Cx,address,I2C_READ_SA7) == ERROR){
return -1;
}
for(recv_cnt=0;recv_cnt<length;recv_cnt++)
{
}
return recv_cnt;
}
int I2C_Burst_Write(I2C_TypeDef* I2Cx, uint16_t address, uint8_t *data, int length, int stop)
{
int cnt;
if( I2C_Start(I2Cx,address,I2C_WRITE_SA7) == ERROR)
{
return -1;
}
for(cnt=0;cnt<length;cnt++)
{
if( I2C_SendDataAck(I2Cx,data[cnt]) == ERROR )
{
I2C_Stop(I2Cx);
return -1;
}
}
// If not repeated start, send stop
if(stop)
{
I2C_Stop(I2Cx);
}
return length;
}
/**
* @brief Generates I2Cx communication START condition.
* @param I2Cx: where x can be 0 or 1 to select the I2C peripheral.
* @param NewState: NewState of the I2C START condition generation.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE) I2Cx->CMDR = I2C_CMDR_STA;
else I2Cx->CMDR = I2C_CMDR_STA;
}
/**
* @brief Generates I2Cx communication STOP condition.
* @param I2Cx: where x can be 0 or 1 to select the I2C peripheral.
* @param NewState: NewState of the I2C STOP condition generation.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE) I2Cx->CMDR = I2C_CMDR_STO;
else I2Cx->CMDR = I2C_CMDR_STO;
}
/**
* @brief Enables or disables the specified I2C acknowledge feature.
* @param I2Cx: where x can be 0 or 1 to select the I2C peripheral.
* @param NewState: NewState of the I2C Acknowledgement.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE) I2Cx -> CMDR = I2C_CMDR_ACK;
else I2Cx -> CMDR = I2C_CMDR_ACK;
}
/**
* @brief Generates I2Cx communication REGenerateSTART condition
* @param I2Cx: where x can be 0 or 1 to select the I2C peripheral.
* @param NewState: NewState of the I2C Acknowledgement.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void I2C_RESTART(I2C_TypeDef * I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE) I2Cx->CMDR = I2C_CMDR_RESTA;
else I2Cx->CMDR = I2C_CMDR_RESTA;
}
/**
* @brief Enable or disable the specified I2C Core_en feature
* @param I2Cx: where x can be 0 or 1 to select the I2C peripheral.
* @param NewState: NewState of the I2C Acknowledgement.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void I2C_CoreEn(I2C_TypeDef* I2Cx,FunctionalState NewState)
{
/*Control*/
if(NewState != DISABLE) I2Cx -> CTR = I2C_CTR_COREEN;
else I2Cx -> CTR = I2C_CTR_COREEN;
}
void I2C_InterEn(I2C_TypeDef* I2Cx,FunctionalState NewState)
{
/*Control Interrupt Enable*/
if(NewState != DISABLE) I2Cx -> CTR = I2C_CTR_INTEREN;
else I2Cx -> CTR = I2C_CTR_INTEREN;
}
void I2C_MasterSlave(I2C_TypeDef* I2Cx,FunctionalState NewState)
{
/*Control MasterSlave select*/
if(NewState == ENABLE)
{
if( (I2Cx->CTR & I2C_CTR_MODE) != I2C_CTR_MODE )
{
I2Cx->CTR = I2C_CTR_MODE;
}
}
else // DISABLE
{
if( (I2Cx->CTR & I2C_CTR_MODE) == I2C_CTR_MODE )
{
I2Cx->CTR = I2C_CTR_MODE;
}
}
}
void I2C_ControlRW(I2C_TypeDef* I2Cx,FunctionalState NewState)
{
/*Control Read(receive)*/
if(NewState == ENABLE)
{
if( (I2Cx->CTR & I2C_CTR_CTRRWN) != I2C_CTR_CTRRWN )
{
I2Cx->CTR = I2C_CTR_CTRRWN;
}
}
else // DISABLE
{
if( (I2Cx->CTR & I2C_CTR_CTRRWN) == I2C_CTR_CTRRWN )
{
I2Cx->CTR = I2C_CTR_CTRRWN;
}
}
}
void I2C_ControlEn(I2C_TypeDef* I2Cx,FunctionalState NewState)
{
/*Control*/
if(NewState == ENABLE)
{
if( (I2Cx->CTR & I2C_CTR_CTEN) != I2C_CTR_CTEN )
{
I2Cx->CTR = I2C_CTR_CTEN;
}
}
else // DISABLE
{
if( (I2Cx->CTR & I2C_CTR_CTEN) == I2C_CTR_CTEN )
{
I2Cx->CTR = I2C_CTR_CTEN;
}
}
}
void I2C_InterRst(I2C_TypeDef* I2Cx,FunctionalState NewState)
{
/*Control*/
if(NewState == ENABLE)
{
if( (I2Cx->ISCR & I2C_ISCR_RST) != I2C_ISCR_RST )
{
I2Cx->ISCR = I2C_ISCR_RST;
}
}
else // DISABLE
{
if( (I2Cx->ISCR & I2C_ISCR_RST) == I2C_ISCR_RST )
{
I2Cx->ISCR = I2C_ISCR_RST;
}
}
}
void I2C_Prescale(I2C_TypeDef* I2Cx,uint16_t Data)
{
I2Cx -> PRER = (uint16_t)Data;
}
void I2C_TimeoutSet(I2C_TypeDef* I2Cx,uint16_t Data)
{
I2Cx -> TSR = (uint16_t)Data;
}
void I2C_SetSlavAddress(I2C_TypeDef* I2Cx,uint16_t Data)
{
I2Cx -> SADDR = (uint16_t)Data;
}
uint8_t I2C_StatusRead(I2C_TypeDef* I2Cx)
{
return (uint8_t)I2Cx -> SR;
}
ErrorStatus WaitEvent(I2C_TypeDef* I2Cx, uint32_t flag, FlagStatus status)
{
int Timeout=0,loopcnt=0;
Timeout = I2Cx->TSR;
if(status == SET)
{
for(loopcnt=Timeout; loopcnt>0; loopcnt--)
{
if( ((I2Cx->SR) & flag) == flag )
return SUCCESS;
}
}
else
{
for(loopcnt=Timeout; loopcnt>0; loopcnt--)
{
if( ((I2Cx->SR) & flag) != flag )
return SUCCESS;
}
}
return ERROR;
}
/**
* @brief Checks whether the specified I2C flag is set or not.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param I2C_EVENT: specifies the event to be checked.
*/
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx,I2C_SR sr)
{
switch(sr)
{
case(I2C_ACKR):
if( WaitEvent(I2Cx, I2C_SR_ACKR, SET) == ERROR) return ERROR;
if( WaitEvent(I2Cx, I2C_SR_ACKR, RESET) == ERROR) return ERROR;
break;
case(I2C_ACKT ):
if( WaitEvent(I2Cx, I2C_SR_ACKT, SET) == ERROR) return ERROR;
if( WaitEvent(I2Cx, I2C_SR_ACKT, RESET) == ERROR) return ERROR;
break;
case(I2C_OACKR):
if( WaitEvent(I2Cx, I2C_SR_ACKR, SET) == ERROR) return ERROR;
break;
case(I2C_SACKR ):
if( WaitEvent(I2Cx, I2C_SR_ACKR, RESET) == ERROR) return ERROR;
break;
case(I2C_BT ):
if( WaitEvent(I2Cx, I2C_SR_BT, RESET) == ERROR) return ERROR;
break;
default:
return ERROR;
}
return SUCCESS;
}
/*
void I2C_MasterInit(I2C_TypeDef * I2Cx,uint8_t Prescale,uint16_t Timeout,I2C_CTR Ctr)
{
switch(Ctr)
{
case(I2C_WRITE_SA7): //000
case(I2C_READ_SA7): //001
I2C_CoreEn(I2Cx,ENABLE);
break;
case(I2C_WRITE_SA10): //010
case(I2C_READ_SA10): //011
I2C_CoreEn(I2Cx,ENABLE);
I2C_SlaveAddressLength(I2Cx,ENABLE);
break;
case(I2C_CTRWRITE_SA7): //100
I2C_CoreEn(I2Cx,ENABLE);
I2C_ControlEn(I2Cx,ENABLE);
break;
case(I2C_CTRREAD_SA7): //101
I2C_CoreEn(I2Cx,ENABLE);
I2C_ControlRW(I2Cx,ENABLE);
I2C_ControlEn(I2Cx,ENABLE);
break;
case(I2C_CTRWRITE_SA10): //110
I2C_CoreEn(I2Cx,ENABLE);
I2C_ControlRW(I2Cx,DISABLE);
I2C_ControlEn(I2Cx,ENABLE);
I2C_SlaveAddressLength(I2Cx,ENABLE);
break;
case(I2C_CTRREAD_SA10): //111
I2C_CoreEn(I2Cx,ENABLE);
I2C_ControlRW(I2Cx,ENABLE);
I2C_ControlEn(I2Cx,ENABLE);
I2C_SlaveAddressLength(I2Cx,ENABLE);
break;
default:
return;
}
I2C_MasterSlave(I2Cx,ENABLE);
I2C_MasterSlave(I2Cx,DISABLE);
I2C_MasterSlave(I2Cx,ENABLE);
I2C_Prescale(I2Cx,Prescale); // 0x61 //When PLL clk is 20MHz and Prescale value set 0x61, SCL is 100KHz
I2C_TimeoutSet(I2Cx,Timeout); // 0xFFFF
#if defined(I2C_INT)
I2C_CoreEn(I2Cx,DISABLE);
I2C_InterEn(I2Cx,ENABLE);
#else
I2C_CoreEn(I2Cx,DISABLE);
#endif
}
void I2C_SlaveInit(I2C_TypeDef * I2Cx, FunctionalState NewState,uint16_t data)
{
if(NewState != DISABLE)
{
I2C_SlaveAddressLength(I2Cx,ENABLE);
}
else
I2C_AcknowledgeConfig(I2Cx,ENABLE);
I2C_SetSlavAddress(I2Cx,data);
}
*/
void I2C_SendSlaveAddress(I2C_TypeDef* I2Cx, uint8_t SlaveAddress,I2C_CTR Ctr)
{
switch(Ctr)
{
case(I2C_READ_SA7):
I2C_SendData(I2Cx,SlaveAddress|I2C_READ);
break;
case(I2C_WRITE_SA7):
I2C_SendData(I2Cx,SlaveAddress|I2C_WRITE);
break;
// case(I2C_READ_SA10):
// I2C_SendData(I2Cx,SlaveAddress|I2C_READ);
// break;
//
// case(I2C_WRITE_SA10):
// I2C_SendData(I2Cx,SlaveAddress|I2C_WRITE);
// break;
case(I2C_CTRWRITE_SA7):
case(I2C_CTRREAD_SA7):
// case(I2C_CTRWRITE_SA10):
// case(I2C_CTRREAD_SA10):
I2C_SendData(I2Cx,SlaveAddress);
break;
default:
return;
}
}
int8_t I2C_Restart_Structure(I2C_TypeDef * I2Cx,uint32_t SlaveAddress,I2C_CTR Ctr)
{
I2C_RESTART(I2Cx,ENABLE);
I2C_SendSlaveAddress(I2Cx,SlaveAddress,Ctr);
if((I2C_CheckEvent(I2Cx,I2C_OACKR)) == ERROR )
{
return 0;
}
I2C_RESTART(I2Cx,DISABLE);
if((I2C_CheckEvent(I2Cx,I2C_SACKR)) == ERROR)
{
return 0;
}
return 1;
}
/**
* @brief Reads the specified I2C register and returns its value.
* @param I2C_Register: specifies the register to read.
* This parameter can be one of the following values:
* @arg I2C_Register_CR1: CR1 register.
* @arg I2C_Register_CR2: CR2 register.
* @arg I2C_Register_OAR1: OAR1 register.
* @arg I2C_Register_OAR2: OAR2 register.
* @arg I2C_Register_DR: DR register.
* @arg I2C_Register_SR1: SR1 register.
* @arg I2C_Register_SR2: SR2 register.
* @arg I2C_Register_CCR: CCR register.
* @arg I2C_Register_TRISE: TRISE register.
* @retval The value of the read register.
*/
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t) I2Cx;
tmp += I2C_Register;
/* Return the selected register value */
return (*(__IO uint16_t *) tmp);
}

231
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.h Normal file
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#include "W7500x.h"
/**
* @defgroup I2C_Public_Types I2X Public Types
*/
typedef enum
{
I2C_WRITE_SA7=0,
I2C_READ_SA7,
//I2C_WRITE_SA10,
//I2C_READ_SA10,
I2C_CTRWRITE_SA7,
I2C_CTRREAD_SA7,
//I2C_CTRWRITE_SA10,
//I2C_CTRREAD_SA10,
} I2C_CTR;
typedef enum
{
I2C_ACKR=0,
I2C_ACKT,
I2C_OACKR,
I2C_SACKR,
I2C_BT,
} I2C_SR;
typedef enum
{
INT_ACKR=-1,
INT_ACKT=-2,
INT_NACKR=-3,
INT_NACKT=-4,
INT_BT=-5,
} I2C_ERROR;
/**
*@
*/
/** @defgroup I2C_registers
* @{
*/
#define I2C_Register_PRER ((uint8_t)0x00)
#define I2C_Register_CTR ((uint8_t)0x04)
#define I2C_Register_CMDR ((uint8_t)0x08)
#define I2C_Register_SR ((uint8_t)0x0C)
#define I2C_Register_TSR ((uint8_t)0x10)
#define I2C_Register_SADDR ((uint8_t)0x14)
#define I2C_Register_TXR ((uint8_t)0x18)
#define I2C_Register_RXR ((uint8_t)0x1C)
#define I2C_Register_ISR ((uint8_t)0x20)
#define I2C_Register_ISCR ((uint8_t)0x24)
#define I2C_Register_ISMR ((uint8_t)0x28)
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_PRER) || \
((REGISTER) == I2C_Register_CTR) || \
((REGISTER) == I2C_Register_CMDR) || \
((REGISTER) == I2C_Register_SR) || \
((REGISTER) == I2C_Register_TSR) || \
((REGISTER) == I2C_Register_SADDR) || \
((REGISTER) == I2C_Register_TXR) || \
((REGISTER) == I2C_Register_RXR) || \
((REGISTER) == I2C_Register_ISR)|| \
((REGISTER) == I2C_Register_ISCR)| \
((REGISTER) == I2C_Register_ISMR))
/**
* @}
*/
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @}
*/
/**
* @brief I2C Interrput Status Register Mask flags
*/
//------------------------------------------------
// I2C_ISMR_BIT
//------------------------------------------------
/**
* @}
*/
/** @defgroup I2C_Private_Defines
* @{
*/
/* I2C COREEN mask */
#define I2C_CTR_COREEN_DIS ((uint16_t)0xFF7F)
/* I2C INTEREN mask */
#define I2C_CTR_INTEREN_DIS ((uint16_t)0xFFBF)
/* I2C MODE(M/SN) mask */
#define I2C_CTR_MODE_SLAVE ((uint16_t)0xFFDF)
/* I2C ADDR10(10/7N) mask */
#define I2C_CTR_ADDR10_7BIT ((uint16_t)0xFFEF)
/* I2C CTRRWN(R/WN) mask */
#define I2C_CTR_CTRRWN_DIS ((uint16_t)0xFFF7)
/* I2C CTREN mask */
#define I2C_CTR_CTEN_DIS ((uint16_t)0xFFFB)
/* I2C START mask */
#define I2C_CMDR_START_DIS ((uint16_t)0xFF7F)
/* I2C STOP mask */
#define I2C_CMDR_STOP_DIS ((uint16_t)0xFFBF)
/* I2C ACK mask */
#define I2C_CMDR_ACK_NAK ((uint16_t)0xFFDF)
/* I2C RESTART mask */
#define I2C_CMDR_RESTA_DIS ((uint16_t)0xFFEF)
/* I2C INTERRUPT RESET mask */
#define I2C_ISCR_RST_DIS ((uint16_t)0xFFFE)
/**
* @}
*/
#define I2C_WRITE 0
#define I2C_READ 1
#define I2C_RWSEL(NewState) (((NewState) == I2C_WRITE)|| \
((NewState) == I2C_READ))
#define I2C_Ack_Enable (0x01ul << 5)
#define I2C_Ack_Disable (0x00ul << 5)
#define IS_I2C_ACK_NewState(NewState) (((NewState) == I2C_Ack_Enable) || \
((NewState) == I2C_Ack_Disable))
#define I2C_MASTER_MODE (0x01ul << 5 ) // 0x20
#define I2C_SLAVE_MODE (0x00ul << 5 ) // 0x20
#define IS_I2C_MODE(MODE) ((MODE) == I2C_MASTER_MODE)|| \
(MODE) == I2C_SLAVE_MODE))
#define I2C_CTR_MODE (0x01ul << 5 ) // 0x20
#define SLAVE_ADDR10 0x208
typedef enum
{
I2C_Master = I2C_MASTER_MODE,
I2C_Slave = I2C_SLAVE_MODE
}I2C_MODE;
typedef struct
{
uint8_t prescale;
uint16_t timeout;
I2C_CTR control;
}I2C_MasterConfStruct;
typedef struct
{
uint32_t mode;
uint16_t slave_address; // only on slave mode
I2C_MasterConfStruct master;
}I2C_ConfigStruct;
/** @defgroup I2C_Exported_Functions
* @{
*/
uint32_t I2C_Init (I2C_TypeDef* I2Cx, I2C_ConfigStruct conf);
void setFrequency (I2C_TypeDef* I2Cx, uint8_t prescale);
void I2C_DeInit (I2C_TypeDef* I2Cx);
ErrorStatus I2C_Start (I2C_TypeDef* I2Cx, uint16_t slave_address, I2C_CTR ctr);
void I2C_Stop (I2C_TypeDef* I2Cx);
void I2C_Reset (I2C_TypeDef* I2Cx);
void I2C_SendData (I2C_TypeDef* I2Cx,uint16_t Data);
int8_t I2C_SendDataAck (I2C_TypeDef* I2Cx,uint16_t Data);
int I2C_ReceiveData (I2C_TypeDef* I2Cx, int last);
int I2C_Burst_Read (I2C_TypeDef* I2Cx, uint16_t address, uint8_t *data, int length, int stop);
int I2C_Burst_Write (I2C_TypeDef* I2Cx, uint16_t address, uint8_t *data, int length, int stop);
void I2C_Delay (uint32_t nCount);
void I2C_GenerateSTART (I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP (I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig (I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_RESTART (I2C_TypeDef * I2Cx, FunctionalState NewState);
void I2C_CoreEn (I2C_TypeDef* I2Cx,FunctionalState NewState);
void I2C_InterEn (I2C_TypeDef* I2Cx,FunctionalState NewState);
void I2C_MasterSlave(I2C_TypeDef* I2Cx,FunctionalState NewState);
void I2C_ControlRW (I2C_TypeDef* I2Cx,FunctionalState NewState);
void I2C_ControlEn (I2C_TypeDef* I2Cx,FunctionalState NewState);
void I2C_InterRst (I2C_TypeDef* I2Cx,FunctionalState NewState);
void I2C_Prescale (I2C_TypeDef* I2Cx,uint16_t Data);
void I2C_TimeoutSet (I2C_TypeDef* I2Cx,uint16_t Data);
void I2C_SetSlavAddress (I2C_TypeDef* I2Cx,uint16_t Data);
uint8_t I2C_StatusRead (I2C_TypeDef* I2Cx);
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx,I2C_SR sr);
void I2C_MasterInit (I2C_TypeDef * I2Cx,uint8_t Prescale,uint16_t Timeout,I2C_CTR Ctr);
void I2C_SlaveInit (I2C_TypeDef * I2Cx,FunctionalState NewState, uint16_t data);
void I2C_SendSlaveAddress (I2C_TypeDef* I2Cx, uint8_t SlaveAddress,I2C_CTR Ctr);
int8_t I2C_Restart_Structure(I2C_TypeDef * I2Cx,uint32_t SlaveAddress,I2C_CTR Ctr);
uint16_t I2C_ReadRegister (I2C_TypeDef* I2Cx, uint8_t I2C_Register);
/**
* @}
*/

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/**
******************************************************************************
* @file
* @author
* @version
* @date
* @brief This file contains all the functions prototypes for the UART
* firmware library.
******************************************************************************
*
******************************************************************************
*/
/* Includes -------------------------------------------*/
#include "W7500x.h"
void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn)
{
if( PWM_CHn == PWM_CH0 )
{
PWM->IER &= PWM_IER_IE0_Disable; ///< Interrupt enable register
PWM->SSR &= PWM_SSR_SS0_Stop; ///< Start Stop register
PWM->PSR &= PWM_PSR_PS0_Restart; ///< Pause register
PWM_CH0->IER = 0; ///< Interrupt enable register
PWM_CH0->ICR = PWM_CHn_ICR_MatchInterruptClear |
PWM_CHn_ICR_OverflowInterruptClear |
PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
PWM_CH0->PR = 0; ///< Prescale register
PWM_CH0->MR = 0; ///< Match register
PWM_CH0->LR = 0xFFFFFFFF; ///< Limit register
PWM_CH0->UDMR = 0; ///< Up Dowm mode register
PWM_CH0->TCMR = 0; ///< Timer Counter mode register
PWM_CH0->PEEER = 0; ///< PWM output Enable and External input Enable register
PWM_CH0->CMR = 0; ///< Capture mode register
PWM_CH0->PDMR = 0; ///< Periodic Mode register
PWM_CH0->DZER = 0; ///< Dead Zone Enable register
PWM_CH0->DZCR = 0; ///< Dead Zone Counter register
}
else if( PWM_CHn == PWM_CH1 )
{
PWM->IER &= PWM_IER_IE1_Disable; ///< Reset Interrupt enable register
PWM->SSR &= PWM_SSR_SS1_Stop; ///< Reset Start Stop register
PWM->PSR &= PWM_PSR_PS1_Restart; ///< Reset Pause register
PWM_CH1->IER = 0; ///< Interrupt enable register
PWM_CH1->ICR = PWM_CHn_ICR_MatchInterruptClear |
PWM_CHn_ICR_OverflowInterruptClear |
PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
PWM_CH1->PR = 0; ///< Prescale register
PWM_CH1->MR = 0; ///< Match register
PWM_CH1->LR = 0xFFFFFFFF; ///< Limit register
PWM_CH1->UDMR = 0; ///< Up Dowm mode register
PWM_CH1->TCMR = 0; ///< Timer Counter mode register
PWM_CH1->PEEER = 0; ///< PWM output Enable and External input Enable register
PWM_CH1->CMR = 0; ///< Capture mode register
PWM_CH1->PDMR = 0; ///< Periodic Mode register
PWM_CH1->DZER = 0; ///< Dead Zone Enable register
PWM_CH1->DZCR = 0; ///< Dead Zone Counter register
}
else if( PWM_CHn == PWM_CH2)
{
PWM->IER &= PWM_IER_IE2_Disable; ///< Interrupt enable register
PWM->SSR &= PWM_SSR_SS2_Stop; ///< Start Stop register
PWM->PSR &= PWM_PSR_PS2_Restart; ///< Pause register
PWM_CH2->IER = 0; ///< Interrupt enable register
PWM_CH2->ICR = PWM_CHn_ICR_MatchInterruptClear |
PWM_CHn_ICR_OverflowInterruptClear |
PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
PWM_CH2->PR = 0; ///< Prescale register
PWM_CH2->MR = 0; ///< Match register
PWM_CH2->LR = 0xFFFFFFFF; ///< Limit register
PWM_CH2->UDMR = 0; ///< Up Dowm mode register
PWM_CH2->TCMR = 0; ///< Timer Counter mode register
PWM_CH2->PEEER = 0; ///< PWM output Enable and External input Enable register
PWM_CH2->CMR = 0; ///< Capture mode register
PWM_CH2->PDMR = 0; ///< Periodic Mode register
PWM_CH2->DZER = 0; ///< Dead Zone Enable register
PWM_CH2->DZCR = 0; ///< Dead Zone Counter register
}
else if( PWM_CHn == PWM_CH3 )
{
PWM->IER &= PWM_IER_IE3_Disable; ///< Interrupt enable register
PWM->SSR &= PWM_SSR_SS3_Stop; ///< Start Stop register
PWM->PSR &= PWM_PSR_PS3_Restart; ///< Pause register
PWM_CH3->IER = 0; ///< Interrupt enable register
PWM_CH3->ICR = PWM_CHn_ICR_MatchInterruptClear |
PWM_CHn_ICR_OverflowInterruptClear |
PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
PWM_CH3->MR = 0; ///< Match register
PWM_CH3->LR = 0xFFFFFFFF; ///< Limit register
PWM_CH3->UDMR = 0; ///< Up Dowm mode register
PWM_CH3->TCMR = 0; ///< Timer Counter mode register
PWM_CH3->PEEER = 0; ///< PWM output Enable and External input Enable register
PWM_CH3->CMR = 0; ///< Capture mode register
PWM_CH3->PDMR = 0; ///< Periodic Mode register
PWM_CH3->DZER = 0; ///< Dead Zone Enable register
PWM_CH3->DZCR = 0; ///< Dead Zone Counter register
}
else if( PWM_CHn == PWM_CH4 )
{
PWM->SSR &= PWM_IER_IE4_Disable; ///< Start Stop register
PWM->PSR &= PWM_SSR_SS4_Stop; ///< Pause register
PWM->IER &= PWM_PSR_PS4_Restart; ///< Interrupt enable register
PWM_CH4->IER = 0; ///< Interrupt enable register
PWM_CH4->ICR = PWM_CHn_ICR_MatchInterruptClear |
PWM_CHn_ICR_OverflowInterruptClear |
PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
PWM_CH4->PR = 0; ///< Prescale register
PWM_CH4->MR = 0; ///< Match register
PWM_CH4->LR = 0xFFFF; ///< Limit register
PWM_CH4->UDMR = 0; ///< Up Dowm mode register
PWM_CH4->TCMR = 0; ///< Timer Counter mode register
PWM_CH4->PEEER = 0; ///< PWM output Enable and External input Enable register
PWM_CH4->CMR = 0; ///< Capture mode register
PWM_CH4->PDMR = 0; ///< Periodic Mode register
PWM_CH4->DZER = 0; ///< Dead Zone Enable register
PWM_CH4->DZCR = 0; ///< Dead Zone Counter register
}
else if( PWM_CHn == PWM_CH5 )
{
PWM->SSR &= PWM_IER_IE5_Disable; ///< Start Stop register
PWM->PSR &= PWM_SSR_SS5_Stop; ///< Pause register
PWM->IER &= PWM_PSR_PS5_Restart; ///< Interrupt enable register
PWM_CH5->IER = 0; ///< Interrupt enable register
PWM_CH5->ICR = PWM_CHn_ICR_MatchInterruptClear |
PWM_CHn_ICR_OverflowInterruptClear |
PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
PWM_CH5->PR = 0; ///< Prescale register
PWM_CH5->MR = 0; ///< Match register
PWM_CH5->LR = 0xFFFFFFFF; ///< Limit register
PWM_CH5->UDMR = 0; ///< Up Dowm mode register
PWM_CH5->TCMR = 0; ///< Timer Counter mode register
PWM_CH5->PEEER = 0; ///< PWM output Enable and External input Enable register
PWM_CH5->CMR = 0; ///< Capture mode register
PWM_CH5->PDMR = 0; ///< Periodic Mode register
PWM_CH5->DZER = 0; ///< Dead Zone Enable register
PWM_CH5->DZCR = 0; ///< Dead Zone Counter register
}
else if( PWM_CHn == PWM_CH6 )
{
PWM->SSR &= PWM_IER_IE6_Disable; ///< Start Stop register
PWM->PSR &= PWM_SSR_SS6_Stop; ///< Pause register
PWM->IER &= PWM_PSR_PS6_Restart; ///< Interrupt enable register
PWM_CH6->IER = 0; ///< Interrupt enable register
PWM_CH6->ICR = PWM_CHn_ICR_MatchInterruptClear |
PWM_CHn_ICR_OverflowInterruptClear |
PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
PWM_CH6->PR = 0; ///< Prescale register
PWM_CH6->MR = 0; ///< Match register
PWM_CH6->LR = 0xFFFFFFFF; ///< Limit register
PWM_CH6->UDMR = 0; ///< Up Dowm mode register
PWM_CH6->TCMR = 0; ///< Timer Counter mode register
PWM_CH6->PEEER = 0; ///< PWM output Enable and External input Enable register
PWM_CH6->CMR = 0; ///< Capture mode register
PWM_CH6->PDMR = 0; ///< Periodic Mode register
PWM_CH6->DZER = 0; ///< Dead Zone Enable register
PWM_CH6->DZCR = 0; ///< Dead Zone Counter register
}
else if( PWM_CHn == PWM_CH7 )
{
PWM->SSR &= PWM_IER_IE7_Disable; ///< Start Stop register
PWM->PSR &= PWM_SSR_SS7_Stop; ///< Pause register
PWM->IER &= PWM_PSR_PS7_Restart; ///< Interrupt enable register
PWM_CH7->IER = 0; ///< Interrupt enable register
PWM_CH7->ICR = PWM_CHn_ICR_MatchInterruptClear |
PWM_CHn_ICR_OverflowInterruptClear |
PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
PWM_CH7->PR = 0; ///< Prescale register
PWM_CH7->MR = 0; ///< Match register
PWM_CH7->LR = 0xFFFFFFFF; ///< Limit register
PWM_CH7->UDMR = 0; ///< Up Dowm mode register
PWM_CH7->TCMR = 0; ///< Timer Counter mode register
PWM_CH7->PEEER = 0; ///< PWM output Enable and External input Enable register
PWM_CH7->CMR = 0; ///< Capture mode register
PWM_CH7->PDMR = 0; ///< Periodic Mode register
PWM_CH7->DZER = 0; ///< Dead Zone Enable register
PWM_CH7->DZCR = 0; ///< Dead Zone Counter register
}
}
void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct) //complet
{
/* Stop PWM_CHn */
PWM_CHn_Stop(PWM_CHn);
/* Select Timer/Counter mode as Timer mode */
PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
/* Set Prescale register value */
PWM_CHn->PR = PWM_TimerModeInitStruct->PWM_CHn_PR;
/* Set Match register value */
PWM_CHn->MR = PWM_TimerModeInitStruct->PWM_CHn_MR;
/* Set Limit register value */
PWM_CHn->LR = PWM_TimerModeInitStruct->PWM_CHn_LR;
/* Select Up-down mode */
PWM_CHn->UDMR = PWM_TimerModeInitStruct->PWM_CHn_UDMR;
/* Select Periodic mode */
PWM_CHn->PDMR = PWM_TimerModeInitStruct->PWM_CHn_PDMR;
}
void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_PR_FILTER(PWM_CaptureModeInitStruct->PWM_CHn_PR));
assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_MR));
assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_LR));
assert_param(IS_PWM_CHn_UDMR(PWM_CaptureModeInitStruct->PWM_CHn_UDMR));
assert_param(IS_PWM_CHn_PDMR(PWM_CaptureModeInitStruct->PWM_CHn_PDMR));
assert_param(IS_PWM_CHn_CMR(PWM_CaptureModeInitStruct->PWM_CHn_CMR));
/* Stop PWM_CHn */
PWM_CHn_Stop(PWM_CHn);
/* Select Timer/Counter mode as Timer mode */
PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
/* Set Prescale register value */
PWM_CHn->PR = PWM_CaptureModeInitStruct->PWM_CHn_PR;
/* Set Match register value */
PWM_CHn->MR = PWM_CaptureModeInitStruct->PWM_CHn_MR;
/* Set Limit register value */
PWM_CHn->LR = PWM_CaptureModeInitStruct->PWM_CHn_LR;
/* Select Up-down mode */
PWM_CHn->UDMR = PWM_CaptureModeInitStruct->PWM_CHn_UDMR;
/* Select Periodic mode */
PWM_CHn->PDMR = PWM_CaptureModeInitStruct->PWM_CHn_PDMR;
/* Select Capture mode */
PWM_CHn->CMR = PWM_CaptureModeInitStruct->PWM_CHn_CMR;
/* External input enable */
PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable;
}
void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
/* Stop PWM_CHn */
PWM_CHn_Stop(PWM_CHn);
/* Select Timer/Counter mode as Timer mode */
PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
/* Set Match register value */
PWM_CHn->MR = PWM_CounterModeInitStruct->PWM_CHn_MR;
/* Set Limit register value */
PWM_CHn->LR = PWM_CounterModeInitStruct->PWM_CHn_LR;
/* Select Up-down mode */
PWM_CHn->UDMR = PWM_CounterModeInitStruct->PWM_CHn_UDMR;
/* Select Periodic mode */
PWM_CHn->PDMR = PWM_CounterModeInitStruct->PWM_CHn_PDMR;
/* Select Counter mode */
PWM_CHn->TCMR = PWM_CounterModeInitStruct->PWM_CHn_TCMR;
/* Enable external input */
PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable;
}
void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_PR_FILTER(PWM_DeadzoneModeInitStruct->PWM_CHn_PR));
assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_MR));
assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_LR));
assert_param(IS_PWM_CHn_UDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR));
assert_param(IS_PWM_CHn_PDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR));
assert_param(IS_PWM_Deadznoe(PWM_CHn));
/* Stop PWM_CHn */
PWM_CHn_Stop(PWM_CHn);
/* Select Timer/Counter mode as Timer mode */
PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
/* Set Prescale register value */
PWM_CHn->PR = PWM_DeadzoneModeInitStruct->PWM_CHn_PR;
/* Set Match register value */
PWM_CHn->MR = PWM_DeadzoneModeInitStruct->PWM_CHn_MR;
/* Set Limit register value */
PWM_CHn->LR = PWM_DeadzoneModeInitStruct->PWM_CHn_LR;
/* Select Up-down mode */
PWM_CHn->UDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR;
/* Select Periodic mode */
PWM_CHn->PDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR;
/* Enable Dead Zone generation */
PWM_CHn->DZER = PWM_CHn_DZER_Enable;
/* Set Dead Zone Counter */
PWM_CHn->DZCR = PWM_DeadzoneModeInitStruct->PWM_CHn_DZCR;
}
void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable ) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_Output(outputEnDisable));
if( PWM_CHn->DZER )
assert_param(IS_PWM_Deadznoe(PWM_CHn));
/* Stop PWM_CHn */
PWM_CHn_Stop(PWM_CHn);
/*Config PWM output and External input */
PWM_CHn->PEEER = outputEnDisable;
}
void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn)
{
PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_PWMEnable);
}
void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn)
{
PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_Disable);
}
void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
/* Stop PWM_CHn */
PWM_CHn_Stop(PWM_CHn);
if(state == ENABLE)
{
if(PWM_CHn == PWM_CH0) {
PWM->IER |= PWM_IER_IE0_Enable;
}
else if(PWM_CHn == PWM_CH1) {
PWM->IER |= PWM_IER_IE1_Enable;
}
else if(PWM_CHn == PWM_CH2) {
PWM->IER |= PWM_IER_IE2_Enable;
}
else if(PWM_CHn == PWM_CH3) {
PWM->IER |= PWM_IER_IE3_Enable;
}
else if(PWM_CHn == PWM_CH4) {
PWM->IER |= PWM_IER_IE4_Enable;
}
else if(PWM_CHn == PWM_CH5) {
PWM->IER |= PWM_IER_IE5_Enable;
}
else if(PWM_CHn == PWM_CH6) {
PWM->IER |= PWM_IER_IE6_Enable;
}
else if(PWM_CHn == PWM_CH7) {
PWM->IER |= PWM_IER_IE7_Enable;
}
}
else
{
if(PWM_CHn == PWM_CH0) {
PWM->IER &= PWM_IER_IE0_Disable;
}
else if(PWM_CHn == PWM_CH1) {
PWM->IER &= PWM_IER_IE1_Disable;
}
else if(PWM_CHn == PWM_CH2) {
PWM->IER &= PWM_IER_IE2_Disable;
}
else if(PWM_CHn == PWM_CH3) {
PWM->IER &= PWM_IER_IE3_Disable;
}
else if(PWM_CHn == PWM_CH4) {
PWM->IER &= PWM_IER_IE4_Disable;
}
else if(PWM_CHn == PWM_CH5) {
PWM->IER &= PWM_IER_IE5_Disable;
}
else if(PWM_CHn == PWM_CH6) {
PWM->IER &= PWM_IER_IE6_Disable;
}
else if(PWM_CHn == PWM_CH7) {
PWM->IER &= PWM_IER_IE7_Disable;
}
}
}
FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn)
{
FlagStatus ret_val = RESET;
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
if(PWM_CHn == PWM_CH0) {
ret_val = (FlagStatus)((PWM->IER & 0x01) >> 0);
}
else if(PWM_CHn == PWM_CH1) {
ret_val = (FlagStatus)((PWM->IER & 0x02) >> 1);
}
else if(PWM_CHn == PWM_CH2) {
ret_val = (FlagStatus)((PWM->IER & 0x04) >> 2);
}
else if(PWM_CHn == PWM_CH3) {
ret_val = (FlagStatus)((PWM->IER & 0x08) >> 3);
}
else if(PWM_CHn == PWM_CH4) {
ret_val = (FlagStatus)((PWM->IER & 0x10) >> 4);
}
else if(PWM_CHn == PWM_CH5) {
ret_val = (FlagStatus)((PWM->IER & 0x20) >> 5);
}
else if(PWM_CHn == PWM_CH6) {
ret_val = (FlagStatus)((PWM->IER & 0x40) >> 6);
}
else if(PWM_CHn == PWM_CH7) {
ret_val = (FlagStatus)((PWM->IER & 0x80) >> 7);
}
return ret_val;
}
void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_CHn_IER(PWM_CHn_IER));
/* Stop PWM_CHn */
PWM_CHn_Stop(PWM_CHn);
if(state == ENABLE)
PWM_CHn->IER |= PWM_CHn_IER;
else
PWM_CHn->IER &= ~PWM_CHn_IER;
}
uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->IER;
}
uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->IR;
}
void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR)
{
/* Check the parameters */
PWM_CHn->ICR = PWM_CHn_ICR;
}
void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
/* Set Start Stop register */
if(PWM_CHn == PWM_CH0) {
PWM->SSR |= PWM_SSR_SS0_Start;
}
else if(PWM_CHn == PWM_CH1) {
PWM->SSR |= PWM_SSR_SS1_Start;
}
else if(PWM_CHn == PWM_CH2) {
PWM->SSR |= PWM_SSR_SS2_Start;
}
else if(PWM_CHn == PWM_CH3) {
PWM->SSR |= PWM_SSR_SS3_Start;
}
else if(PWM_CHn == PWM_CH4) {
PWM->SSR |= PWM_SSR_SS4_Start;
}
else if(PWM_CHn == PWM_CH5) {
PWM->SSR |= PWM_SSR_SS5_Start;
}
else if(PWM_CHn == PWM_CH6) {
PWM->SSR |= PWM_SSR_SS6_Start;
}
else if(PWM_CHn == PWM_CH7) {
PWM->SSR |= PWM_SSR_SS7_Start;
}
}
void PWM_Multi_Start(uint32_t ssr_bit_flag) //complete
{
/* Set Start Stop register */
PWM->SSR |= ssr_bit_flag;
}
void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Reset Start Stop register */
if(PWM_CHn == PWM_CH0) {
PWM->SSR &= PWM_SSR_SS0_Stop;
}
else if(PWM_CHn == PWM_CH1) {
PWM->SSR &= PWM_SSR_SS1_Stop;
}
else if(PWM_CHn == PWM_CH2) {
PWM->SSR &= PWM_SSR_SS2_Stop;
}
else if(PWM_CHn == PWM_CH3) {
PWM->SSR &= PWM_SSR_SS3_Stop;
}
else if(PWM_CHn == PWM_CH4) {
PWM->SSR &= PWM_SSR_SS4_Stop;
}
else if(PWM_CHn == PWM_CH5) {
PWM->SSR &= PWM_SSR_SS5_Stop;
}
else if(PWM_CHn == PWM_CH6) {
PWM->SSR &= PWM_SSR_SS6_Stop;
}
else if(PWM_CHn == PWM_CH7) {
PWM->SSR &= PWM_SSR_SS7_Stop;
}
}
void PWM_Multi_Stop(uint32_t ssr_bit_flag) //complete
{
/* Reset Start Stop register */
PWM->SSR &= ~ssr_bit_flag;
}
void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn)
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
/* Set Pause register */
if(PWM_CHn == PWM_CH0) {
PWM->PSR |= PWM_PSR_PS0_Pause;
}
else if(PWM_CHn == PWM_CH1) {
PWM->PSR |= PWM_PSR_PS1_Pause;
}
else if(PWM_CHn == PWM_CH2) {
PWM->PSR |= PWM_PSR_PS2_Pause;
}
else if(PWM_CHn == PWM_CH3) {
PWM->PSR |= PWM_PSR_PS3_Pause;
}
else if(PWM_CHn == PWM_CH4) {
PWM->PSR |= PWM_PSR_PS4_Pause;
}
else if(PWM_CHn == PWM_CH5) {
PWM->PSR |= PWM_PSR_PS5_Pause;
}
else if(PWM_CHn == PWM_CH6) {
PWM->PSR |= PWM_PSR_PS6_Pause;
}
else if(PWM_CHn == PWM_CH7) {
PWM->PSR |= PWM_PSR_PS7_Pause;
}
}
void PWM_Multi_Pause(uint32_t psr_bit_flag)
{
PWM->PSR |= psr_bit_flag;
}
void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn)
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
/* Reset Pause register */
if(PWM_CHn == PWM_CH0) {
PWM->PSR &= PWM_PSR_PS0_Restart;
}
else if(PWM_CHn == PWM_CH1) {
PWM->PSR &= PWM_PSR_PS1_Restart;
}
else if(PWM_CHn == PWM_CH2) {
PWM->PSR &= PWM_PSR_PS2_Restart;
}
else if(PWM_CHn == PWM_CH3) {
PWM->PSR &= PWM_PSR_PS3_Restart;
}
else if(PWM_CHn == PWM_CH4) {
PWM->PSR &= PWM_PSR_PS4_Restart;
}
else if(PWM_CHn == PWM_CH5) {
PWM->PSR &= PWM_PSR_PS5_Restart;
}
else if(PWM_CHn == PWM_CH6) {
PWM->PSR &= PWM_PSR_PS6_Restart;
}
else if(PWM_CHn == PWM_CH7) {
PWM->PSR &= PWM_PSR_PS7_Restart;
}
}
void PWM_Multi_Restart(uint32_t psr_bit_flag)
{
PWM->PSR &= ~psr_bit_flag;
}
uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->TCR;
}
uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->PCR;
}
uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->PR;
}
void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_PR_FILTER(PR));
PWM_CHn->PR = PR;
}
uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->MR;
}
void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
PWM_CHn->MR = MR;
}
uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->LR;
}
void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
PWM_CHn->LR = LR;
}
uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->UDMR;
}
void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_CHn_UDMR(UDMR));
PWM_CHn->UDMR = UDMR;
}
uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->TCMR;
}
void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_CHn_TCMR(TCMR));
PWM_CHn->TCMR = TCMR;
}
uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->PEEER;
}
void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_CHn_PEEER(PEEER));
PWM_CHn->PEEER = PEEER;
}
uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->CMR;
}
void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_CHn_CMR(CMR));
PWM_CHn->CMR = CMR;
}
uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn)
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->CR;
}
uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->PDMR;
}
void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_CHn_PDMR(PDMR));
PWM_CHn->PDMR = PDMR;
}
uint32_t PWM_CHn_GetDZER(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->DZER;
}
void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_CHn_DZER(DZER));
PWM_CHn->DZER = DZER;
}
uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->DZCR;
}
void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_CHn_DZCR_FILTER(DZCR));
PWM_CHn->DZCR = DZCR;
}
void PWM_CH0_ClearMatchInt(void)
{
PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_MatchInterruptClear);
}
void PWM_CH0_ClearOverflowInt(void)
{
PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_OverflowInterruptClear);
}
void PWM_CH0_ClearCaptureInt(void)
{
PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_CaptureInterruptClear);
}
void PWM_CH1_ClearMatchInt(void)
{
PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_MatchInterruptClear);
}
void PWM_CH1_ClearOverflowInt(void)
{
PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_OverflowInterruptClear);
}
void PWM_CH1_ClearCaptureInt(void)
{
PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_CaptureInterruptClear);
}
void PWM_CH2_ClearMatchInt(void)
{
PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_MatchInterruptClear);
}
void PWM_CH2_ClearOverflowInt(void)
{
PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_OverflowInterruptClear);
}
void PWM_CH2_ClearCaptureInt(void)
{
PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_CaptureInterruptClear);
}
void PWM_CH3_ClearMatchInt(void)
{
PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_MatchInterruptClear);
}
void PWM_CH3_ClearOverflowInt(void)
{
PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_OverflowInterruptClear);
}
void PWM_CH3_ClearCaptureInt(void)
{
PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_CaptureInterruptClear);
}
void PWM_CH4_ClearMatchInt(void)
{
PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_MatchInterruptClear);
}
void PWM_CH4_ClearOverflowInt(void)
{
PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_OverflowInterruptClear);
}
void PWM_CH4_ClearCaptureInt(void)
{
PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_CaptureInterruptClear);
}
void PWM_CH5_ClearMatchInt(void)
{
PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_MatchInterruptClear);
}
void PWM_CH5_ClearOverflowInt(void)
{
PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_OverflowInterruptClear);
}
void PWM_CH5_ClearCaptureInt(void)
{
PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_CaptureInterruptClear);
}
void PWM_CH6_ClearMatchInt(void)
{
PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_MatchInterruptClear);
}
void PWM_CH6_ClearOverflowInt(void)
{
PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_OverflowInterruptClear);
}
void PWM_CH6_ClearCaptureInt(void)
{
PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_CaptureInterruptClear);
}
void PWM_CH7_ClearMatchInt(void)
{
PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_MatchInterruptClear);
}
void PWM_CH7_ClearOverflowInt(void)
{
PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_OverflowInterruptClear);
}
void PWM_CH7_ClearCaptureInt(void)
{
PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_CaptureInterruptClear);
}

289
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.h Normal file
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@ -0,0 +1,289 @@
/**
******************************************************************************
* @file
* @author
* @version
* @date
* @brief This file contains all the functions prototypes for the UART
* firmware library.
******************************************************************************
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __W7500X_PWM_H
#define __W7500X_PWM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "W7500x.h"
/**********************************************************************************************/
/**********************************************************************************************/
// This structure and define must be in W7500x.h
/**********************************************************************************************/
/**********************************************************************************************/
typedef struct
{
uint32_t PWM_CHn_PEEER;
}PWM_CtrlPWMOutputTypeDef;
typedef struct
{
uint32_t PWM_CHn_PR;
uint32_t PWM_CHn_MR;
uint32_t PWM_CHn_LR;
uint32_t PWM_CHn_UDMR;
uint32_t PWM_CHn_PDMR;
uint32_t PWM_CHn_DZCR;
}PWM_DeadzoneModeInitTypDef;
#define IS_PWM_ALL_CH(CHn) ((CHn == PWM_CH0) || \
(CHn == PWM_CH1) || \
(CHn == PWM_CH2) || \
(CHn == PWM_CH3) || \
(CHn == PWM_CH4) || \
(CHn == PWM_CH5) || \
(CHn == PWM_CH6) || \
(CHn == PWM_CH7))
#define PWM_IER_IE0_Enable (0x1ul << 0)
#define PWM_IER_IE1_Enable (0x1ul << 1)
#define PWM_IER_IE2_Enable (0x1ul << 2)
#define PWM_IER_IE3_Enable (0x1ul << 3)
#define PWM_IER_IE4_Enable (0x1ul << 4)
#define PWM_IER_IE5_Enable (0x1ul << 5)
#define PWM_IER_IE6_Enable (0x1ul << 6)
#define PWM_IER_IE7_Enable (0x1ul << 7)
#define PWM_IER_IE0_Disable ~PWM_IER_IE0_Enable
#define PWM_IER_IE1_Disable ~PWM_IER_IE1_Enable
#define PWM_IER_IE2_Disable ~PWM_IER_IE2_Enable
#define PWM_IER_IE3_Disable ~PWM_IER_IE3_Enable
#define PWM_IER_IE4_Disable ~PWM_IER_IE4_Enable
#define PWM_IER_IE5_Disable ~PWM_IER_IE5_Enable
#define PWM_IER_IE6_Disable ~PWM_IER_IE6_Enable
#define PWM_IER_IE7_Disable ~PWM_IER_IE7_Enable
#define PWM_SSR_SS0_Start (0x1ul << 0)
#define PWM_SSR_SS1_Start (0x1ul << 1)
#define PWM_SSR_SS2_Start (0x1ul << 2)
#define PWM_SSR_SS3_Start (0x1ul << 3)
#define PWM_SSR_SS4_Start (0x1ul << 4)
#define PWM_SSR_SS5_Start (0x1ul << 5)
#define PWM_SSR_SS6_Start (0x1ul << 6)
#define PWM_SSR_SS7_Start (0x1ul << 7)
#define PWM_SSR_SS0_Stop ~PWM_SSR_SS0_Start
#define PWM_SSR_SS1_Stop ~PWM_SSR_SS1_Start
#define PWM_SSR_SS2_Stop ~PWM_SSR_SS2_Start
#define PWM_SSR_SS3_Stop ~PWM_SSR_SS3_Start
#define PWM_SSR_SS4_Stop ~PWM_SSR_SS4_Start
#define PWM_SSR_SS5_Stop ~PWM_SSR_SS5_Start
#define PWM_SSR_SS6_Stop ~PWM_SSR_SS6_Start
#define PWM_SSR_SS7_Stop ~PWM_SSR_SS7_Start
#define IS_SSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
#define PWM_PSR_PS0_Pause (0x1ul << 0)
#define PWM_PSR_PS1_Pause (0x1ul << 1)
#define PWM_PSR_PS2_Pause (0x1ul << 2)
#define PWM_PSR_PS3_Pause (0x1ul << 3)
#define PWM_PSR_PS4_Pause (0x1ul << 4)
#define PWM_PSR_PS5_Pause (0x1ul << 5)
#define PWM_PSR_PS6_Pause (0x1ul << 6)
#define PWM_PSR_PS7_Pause (0x1ul << 7)
#define PWM_PSR_PS0_Restart ~PWM_PSR_PS0_Pause
#define PWM_PSR_PS1_Restart ~PWM_PSR_PS1_Pause
#define PWM_PSR_PS2_Restart ~PWM_PSR_PS2_Pause
#define PWM_PSR_PS3_Restart ~PWM_PSR_PS3_Pause
#define PWM_PSR_PS4_Restart ~PWM_PSR_PS4_Pause
#define PWM_PSR_PS5_Restart ~PWM_PSR_PS5_Pause
#define PWM_PSR_PS6_Restart ~PWM_PSR_PS6_Pause
#define PWM_PSR_PS7_Restart ~PWM_PSR_PS7_Pause
#define IS_PWM_PSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
#define PWM_CHn_IER_MIE (0x1ul << 0) ///< Match Interrupt Enable
#define PWM_CHn_IER_OIE (0x1ul << 1) ///< Overflow Interrupt Enable
#define PWM_CHn_IER_CIE (0x1ul << 2) ///< Capture Interrupt Enable
#define IS_PWM_CHn_IER(FLAG) (FLAG <= 0x7)
#define PWM_CHn_IER_MI_Msk (0x1ul << 0) ///< Match Interrupt Enable Mask
#define PWM_CHn_IER_OI_Msk (0x1ul << 1) ///< Overflow Interrupt Enable Mask
#define PWM_CHn_IER_CI_Msk (0x1ul << 2) ///< Capture Interrupt Enable Mask
#define PWM_CHn_ICR_MatchInterruptClear (0x1ul << 0)
#define PWM_CHn_ICR_OverflowInterruptClear (0x1ul << 1)
#define PWM_CHn_ICR_CaptureInterruptClear (0x1ul << 2)
#define IS_PWM_CHn_IntClearFlag(FLAG) FLAG <= 0x7
/*
#define IS_PWM_STOP(CHn) (((CHn == PWM_CH0) && (PWM->SSR & PWM_SSR_SS0)) || \
((CHn == PWM_CH1) && (PWM->SSR & PWM_SSR_SS1)) || \
((CHn == PWM_CH2) && (PWM->SSR & PWM_SSR_SS2)) || \
((CHn == PWM_CH3) && (PWM->SSR & PWM_SSR_SS3)) || \
((CHn == PWM_CH4) && (PWM->SSR & PWM_SSR_SS4)) || \
((CHn == PWM_CH5) && (PWM->SSR & PWM_SSR_SS5)) || \
((CHn == PWM_CH6) && (PWM->SSR & PWM_SSR_SS6)) || \
((CHn == PWM_CH7) && (PWM->SSR & PWM_SSR_SS7)))
*/
#define IS_PWM_PR_FILTER(MAXVAL) (MAXVAL <= 0x1F)
#define PWM_CHn_UDMR_UpCount (0x0ul)
#define PWM_CHn_UDMR_DownCount (0x1ul)
#define IS_PWM_CHn_UDMR(MODE) ((MODE == PWM_CHn_UDMR_UpCount) || \
(MODE == PWM_CHn_UDMR_DownCount))
#define PWM_CHn_TCMR_TimerMode (0x0ul)
#define PWM_CHn_TCMR_RisingCounterMode (0x1ul)
#define PWM_CHn_TCMR_FallingCounterMode (0x2ul)
#define PWM_CHn_TCMR_BothCounterMode (0x3ul)
#define IS_PWM_CHn_TCMR(MODE) ((MODE == PWM_CHn_TCMR_RisingCounterMode) || \
(MODE == PWM_CHn_TCMR_FallingCounterMode) || \
(MODE == PWM_CHn_TCMR_BothCounterMode))
#define PWM_CHn_PEEER_Disable (0x0ul)
#define PWM_CHn_PEEER_ExtEnable (0x1ul)
#define PWM_CHn_PEEER_PWMEnable (0x2ul)
#define IS_PWM_CHn_PEEER(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
(ENABLE == PWM_CHn_PEEER_ExtEnable) || \
(ENABLE == PWM_CHn_PEEER_PWMEnable))
#define IS_PWM_Output(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
(ENABLE == PWM_CHn_PEEER_PWMEnable))
#define PWM_CHn_CMR_RisingEdge 0x0ul
#define PWM_CHn_CMR_FallingEdge 0x1ul
#define IS_PWM_CHn_CMR(MODE) ((MODE == PWM_CHn_CMR_RisingEdge) || \
(MODE == PWM_CHn_CMR_FallingEdge))
#define PWM_CHn_PDMR_Oneshot (0x0ul)
#define PWM_CHn_PDMR_Periodic (0x1ul)
#define IS_PWM_CHn_PDMR(MODE) ((MODE == PWM_CHn_PDMR_Periodic) || \
(MODE == PWM_CHn_PDMR_Oneshot))
#define PWM_CHn_DZER_Enable (0x1ul)
#define PWM_CHn_DZER_Disable (0x0ul)
#define PWM_CHn_DZER(ENABLE) ((ENABLE == PWM_CHn_DZER_Enable) || \
(ENABLE == PWM_CHn_DZER_Disable))
#define IS_PWM_Deadznoe(CHn) (((CHn == PWM_CH0) && (PWM_CH1->DZER == PWM_CHn_DZER_Disable)) || \
((CHn == PWM_CH1) && (PWM_CH0->DZER == PWM_CHn_DZER_Disable)) || \
((CHn == PWM_CH2) && (PWM_CH3->DZER == PWM_CHn_DZER_Disable)) || \
((CHn == PWM_CH3) && (PWM_CH2->DZER == PWM_CHn_DZER_Disable)) || \
((CHn == PWM_CH4) && (PWM_CH5->DZER == PWM_CHn_DZER_Disable)) || \
((CHn == PWM_CH5) && (PWM_CH4->DZER == PWM_CHn_DZER_Disable)) || \
((CHn == PWM_CH6) && (PWM_CH7->DZER == PWM_CHn_DZER_Disable)) || \
((CHn == PWM_CH7) && (PWM_CH6->DZER == PWM_CHn_DZER_Disable)))
#define IS_PWM_CHn_DZCR_FILTER(MAXVAL) (MAXVAL <= 0x3FF)
void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn);
void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct);
void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct);
void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct);
void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct);
void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable );
void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn) ;
void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn) ;
void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state);
FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state);
void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn);
void PWM_Multi_Start(uint32_t ssr_bit_flag);
void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn);
void PWM_Multi_Stop(uint32_t ssr_bit_flag);
void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn);
void PWM_Multi_Pause(uint32_t psr_bit_flag);
void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn);
void PWM_Multi_Restart(uint32_t psr_bit_flag);
uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR);
uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn);
uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn);
uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR);
uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR);
uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR);
uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR);
uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR);
uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER);
uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR);
uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn);
uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR);
void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER);
uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR);
void PWM_CH0_ClearMatchInt(void);
void PWM_CH0_ClearOverflowInt(void);
void PWM_CH0_ClearCaptureInt(void);
void PWM_CH1_ClearMatchInt(void);
void PWM_CH1_ClearOverflowInt(void);
void PWM_CH1_ClearCaptureInt(void);
void PWM_CH2_ClearMatchInt(void);
void PWM_CH2_ClearOverflowInt(void);
void PWM_CH2_ClearCaptureInt(void);
void PWM_CH3_ClearMatchInt(void);
void PWM_CH3_ClearOverflowInt(void);
void PWM_CH3_ClearCaptureInt(void);
void PWM_CH4_ClearMatchInt(void);
void PWM_CH4_ClearOverflowInt(void);
void PWM_CH4_ClearCaptureInt(void);
void PWM_CH5_ClearMatchInt(void);
void PWM_CH5_ClearOverflowInt(void);
void PWM_CH5_ClearCaptureInt(void);
void PWM_CH6_ClearMatchInt(void);
void PWM_CH6_ClearOverflowInt(void);
void PWM_CH6_ClearCaptureInt(void);
void PWM_CH7_ClearMatchInt(void);
void PWM_CH7_ClearOverflowInt(void);
void PWM_CH7_ClearCaptureInt(void);
void PWM0_Handler(void);
void PWM1_Handler(void);
void PWM2_Handler(void);
void PWM3_Handler(void);
void PWM4_Handler(void);
void PWM5_Handler(void);
void PWM6_Handler(void);
void PWM7_Handler(void);
//Temporary macro=======
#define PWM_CH(N) ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + (N * 0x100UL)))
//======================
#ifdef __cplusplus
}
#endif
#endif //__W7500X_PWM_H

370
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.c Normal file
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@ -0,0 +1,370 @@
/**
******************************************************************************
* @file W7500x_uart.c
* @author
* @version
* @date
* @brief
******************************************************************************
* @attention
*
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "W7500x.h"
void UART_StructInit(UART_InitTypeDef* UART_InitStruct)
{
/* UART_InitStruct members default value */
UART_InitStruct->UART_BaudRate = 115200;
UART_InitStruct->UART_WordLength = UART_WordLength_8b ;
UART_InitStruct->UART_StopBits = UART_StopBits_1;
UART_InitStruct->UART_Parity = UART_Parity_No ;
UART_InitStruct->UART_Mode = UART_Mode_Rx | UART_Mode_Tx;
UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None ;
}
void UART_DeInit(UART_TypeDef *UARTx)
{
}
uint32_t UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct)
{
float baud_divisor;
uint32_t tmpreg=0x00, uartclock=0x00;
uint32_t integer_baud = 0x00, fractional_baud = 0x00;
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLength));
assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity));
assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits));
assert_param(IS_UART_HARDWARE_FLOW_CONTROL(UART_InitStruct->UART_HardwareFlowControl));
assert_param(IS_UART_MODE(UART_InitStruct->UART_Mode));
UARTx->CR &= ~(UART_CR_UARTEN);
// Set baudrate
CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK; // Set UART Clock using internal Oscilator ( 8MHz )
uartclock = (8000000UL) / (1 << CRG->UARTCLK_PVSR);
baud_divisor = ((float)uartclock / (16 * UART_InitStruct->UART_BaudRate));
integer_baud = (uint32_t)baud_divisor;
fractional_baud = (uint32_t)((baud_divisor - integer_baud) * 64 + 0.5);
UARTx->IBRD = integer_baud;
UARTx->FBRD = fractional_baud;
tmpreg = UARTx->LCR_H;
tmpreg &= ~(0x00EE);
tmpreg |= (UART_InitStruct->UART_WordLength | UART_InitStruct->UART_StopBits | UART_InitStruct->UART_Parity);
UARTx->LCR_H |= tmpreg;
tmpreg = UARTx->CR;
tmpreg &= ~(UART_CR_CTSEn | UART_CR_RTSEn | UART_CR_RXE | UART_CR_TXE | UART_CR_UARTEN);
tmpreg |= (UART_InitStruct->UART_Mode | UART_InitStruct->UART_HardwareFlowControl);
UARTx->CR |= tmpreg;
UARTx->CR |= UART_CR_UARTEN;
return 0;
}
void UART_SendData(UART_TypeDef* UARTx, uint16_t Data)
{
assert_param(IS_UART_01_PERIPH(UARTx));
UARTx->DR = Data;
}
uint16_t UART_ReceiveData(UART_TypeDef* UARTx)
{
assert_param(IS_UART_01_PERIPH(UARTx));
return (uint16_t)(UARTx->DR);
}
void UART_SendBreak(UART_TypeDef* UARTx)
{
assert_param(IS_UART_01_PERIPH(UARTx));
UARTx->LCR_H |= UART_LCR_H_BRK;
}
FlagStatus UART_GetRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS)
{
FlagStatus bitstatus = RESET;
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS));
if( (UARTx->STATUS.RSR & UART_RECV_STATUS) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
void UART_ClearRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS)
{
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS));
UARTx->STATUS.ECR = (uint16_t)UART_RECV_STATUS;
}
FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG)
{
FlagStatus bitstatus = RESET;
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_FLAG(UART_FLAG));
if ((UARTx->FR & UART_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*
void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG)
{
}
*/
void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState)
{
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_IT_FLAG(UART_IT));
if ( NewState != DISABLE )
{
UARTx->IMSC |= UART_IT;
}
else
{
UARTx->ICR |= UART_IT;
}
}
ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT)
{
ITStatus bitstatus = RESET;
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_IT_FLAG(UART_IT));
if ((UARTx->MIS & UART_IT) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT)
{
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_IT_FLAG(UART_IT));
UARTx->ICR |= UART_IT;
}
void S_UART_DeInit()
{
}
uint32_t S_UART_Init(uint32_t baud)
{
uint32_t tmpreg=0x00;
uint32_t uartclock = 0x00, integer_baud = 0x00;
assert_param(IS_UART_MODE(S_UART_InitStruct->UART_Mode));
if(CRG->FCLK_SSR == CRG_FCLK_SSR_RCLK)
{
uartclock = INTERN_XTAL;
}
else if(CRG->FCLK_SSR == CRG_FCLK_SSR_OCLK)
{
uartclock = EXTERN_XTAL;
}
else
{
uartclock = GetSystemClock();
}
integer_baud = (uint32_t)(uartclock / baud);
UART2->BAUDDIV = integer_baud;
tmpreg = UART2->CTRL;
tmpreg &= ~(S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN);
tmpreg |= (S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN);
UART2->CTRL = tmpreg;
return 0;
}
void S_UART_SendData(uint16_t Data)
{
while(UART2->STATE & S_UART_STATE_TX_BUF_FULL);
UART2->DATA = Data;
}
uint16_t S_UART_ReceiveData()
{
return (uint16_t)(UART2->DATA);
}
FlagStatus S_UART_GetFlagStatus(uint16_t S_UART_FLAG)
{
FlagStatus bitstatus = RESET;
assert_param(IS_S_UART_FLAG(S_UART_FLAG));
if ((UART2->STATE & S_UART_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
void S_UART_ITConfig(uint16_t S_UART_IT, FunctionalState NewState)
{
assert_param(IS_S_UART_IT_FLAG(S_UART_IT));
if ( NewState != DISABLE )
{
UART2->CTRL |= S_UART_IT;
}
else
{
UART2->CTRL &= ~(S_UART_IT);
}
}
ITStatus S_UART_GetITStatus(uint16_t S_UART_IT)
{
ITStatus bitstatus = RESET;
assert_param(IS_S_UART_IT_FLAG(S_UART_IT));
if ((UART2->INT.STATUS & (S_UART_IT >> 2)) != (uint16_t) RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
void S_UART_ClearITPendingBit(uint16_t S_UART_IT)
{
assert_param(IS_S_UART_IT_FLAG(S_UART_IT));
UART2->INT.CLEAR |= (S_UART_IT >> 2);
}
/**************************************************/
// It will be moved to application board's driver */
/**************************************************/
uint8_t UartPutc(UART_TypeDef* UARTx, uint8_t ch)
{
UART_SendData(UARTx,ch);
while(UARTx->FR & UART_FR_BUSY);
return (ch);
}
void UartPuts(UART_TypeDef* UARTx, uint8_t *str)
{
uint8_t ch;
do{
ch = *str;
if(ch != (uint8_t)0x0)
{
UartPutc(UARTx, ch);
}
*str++;
}while(ch != 0);
}
uint8_t UartGetc(UART_TypeDef* UARTx)
{
while(UARTx->FR & UART_FR_RXFE);
return (UARTx->DR & 0xFF);
}
uint8_t S_UartPutc(uint8_t ch)
{
S_UART_SendData(ch);
return (ch);
}
void S_UartPuts(uint8_t *str)
{
uint8_t ch;
do{
ch = *str;
if(ch != (uint8_t)0x0)
{
S_UART_SendData(ch);
}
*str++;
}while(ch != 0);
}
uint8_t S_UartGetc()
{
while( (UART2->STATE & S_UART_STATE_RX_BUF_FULL) == 0 );
return (uint8_t)S_UART_ReceiveData();
}

289
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.h Normal file
View File

@ -0,0 +1,289 @@
/**
******************************************************************************
* @file
* @author
* @version
* @date
* @brief This file contains all the functions prototypes for the UART
* firmware library.
******************************************************************************
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __W7500X_UART_H
#define __W7500X_UART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "W7500x.h"
/**
* @brief UART Init Structure definition
*/
typedef struct
{
uint32_t UART_BaudRate;
uint16_t UART_WordLength;
uint16_t UART_StopBits;
uint16_t UART_Parity;
uint16_t UART_Mode;
uint16_t UART_HardwareFlowControl;
} UART_InitTypeDef;
/**
* @}
*/
/** @defgroup UART_Exported_Constants
* @{
*/
#define IS_UART_01_PERIPH(PERIPH) (((PERIPH) == UART0) || ((PERIPH) == UART1))
#define IS_UART_2_PERIPH(PERIPH) ((PERIPH) == UART2)
/**
* @}
*/
/** @addtogroup UART_Word_Length
* @{
*/
#define UART_WordLength_8b ((uint16_t)UART_LCR_H_WLEN(3))
#define UART_WordLength_7b ((uint16_t)UART_LCR_H_WLEN(2))
#define UART_WordLength_6b ((uint16_t)UART_LCR_H_WLEN(1))
#define UART_WordLength_5b ((uint16_t)UART_LCR_H_WLEN(0))
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WordLength_8b) || \
((LENGTH) == UART_WordLength_7b) || \
((LENGTH) == UART_WordLength_6b) || \
((LENGTH) == UART_WordLength_5b) )
/**
* @}
*/
/** @addtogroup UART_Parity
* @{
*/
#define UART_Parity_No ((uint16_t)0x0000)
#define UART_Parity_Even ((uint16_t)(UART_LCR_H_PEN | UART_LCR_H_EPS))
#define UART_Parity_Odd ((uint16_t)(UART_LCR_H_PEN))
#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_No) || \
((PARITY) == UART_Parity_Even) || \
((PARITY) == UART_Parity_Odd))
/**
* @}
*/
/** @addtogroup UART_Stop_Bits
* @{
*/
#define UART_StopBits_1 ((uint16_t)0x0000)
#define UART_StopBits_2 ((uint16_t)(UART_LCR_H_STP2))
#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \
((STOPBITS) == UART_StopBits_2))
/**
* @}
*/
/** @addtogroup UART_Mode
* @{
*/
#define UART_Mode_Rx ((uint16_t)(UART_CR_RXE))
#define UART_Mode_Tx ((uint16_t)(UART_CR_TXE))
#define IS_UART_MODE(MODE) (((MODE) == UART_Mode_Rx) || \
((MODE) == UART_Mode_Tx))
/**
* @}
*/
/** @addtogroup UART_Hardware_Flow_Control
* @{
*/
#define UART_HardwareFlowControl_None ((uint16_t)0x0000)
#define UART_HardwareFlowControl_RTS ((uint16_t)UART_CR_RTSEn)
#define UART_HardwareFlowControl_CTS ((uint16_t)UART_CR_CTSEn)
#define UART_HardwareFlowControl_RTS_CTS ((uint16_t)(UART_CR_RTSEn | UART_CR_CTSEn))
#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL) \
(((CONTROL) == UART_HardwareFlowControl_None) || \
((CONTROL) == UART_HardwareFlowControl_RTS) || \
((CONTROL) == UART_HardwareFlowControl_CTS) || \
((CONTROL) == UART_HardwareFlowControl_RTS_CTS))
/**
* @}
*/
/** @addtogroup UART_Receive Status
* @{
*/
#define UART_RECV_STATUS_OE ((uint16_t)0x01UL << 3) /*!< Overrun error */
#define UART_RECV_STATUS_BE ((uint16_t)0x01UL << 2) /*!< Break error */
#define UART_RECV_STATUS_PE ((uint16_t)0x01UL << 1) /*!< Parity error */
#define UART_RECV_STATUS_FE ((uint16_t)0x01UL << 0) /*!< Framing error */
#define IS_UART_RECV_STATUS(FLAG) (((FLAG) == UART_RECV_STATUS_OE) || ((FLAG) == UART_RECV_STATUS_BE) || \
((FLAG) == UART_RECV_STATUS_PE) || ((FLAG) == UART_RECV_STATUS_FE))
/**
* @}
*/
/** @addtogroup UART_Flags
* @{
*/
#define UART_FLAG_RI ((uint16_t)0x01UL << 8) /*!< Ring indicator */
#define UART_FLAG_TXFE ((uint16_t)0x01UL << 7) /*!< Transmit FIFO empty */
#define UART_FLAG_RXFF ((uint16_t)0x01UL << 6) /*!< Receive FIFO full */
#define UART_FLAG_TXFF ((uint16_t)0x01UL << 5) /*!< Transmit FIFO full */
#define UART_FLAG_RXFE ((uint16_t)0x01UL << 4) /*!< Receive FIFO empty */
#define UART_FLAG_BUSY ((uint16_t)0x01UL << 3) /*!< UART busy */
#define UART_FLAG_DCD ((uint16_t)0x01UL << 2) /*!< Data carrier detect */
#define UART_FLAG_DSR ((uint16_t)0x01UL << 1) /*!< Data set ready */
#define UART_FLAG_CTS ((uint16_t)0x01UL << 0) /*!< Clear to send */
#define IS_UART_FLAG(FLAG) (((FLAG) == UART_FLAG_RI) || ((FLAG) == UART_FLAG_TXFE) || \
((FLAG) == UART_FLAG_RXFF) || ((FLAG) == UART_FLAG_TXFF) || \
((FLAG) == UART_FLAG_RXFE) || ((FLAG) == UART_FLAG_BUSY) || \
((FLAG) == UART_FLAG_DCD) || ((FLAG) == UART_FLAG_DSR) || \
((FLAG) == UART_FLAG_CTS))
/**
* @}
*/
/** @addtogroup UART_IT_Flags
* @{
*/
#define UART_IT_FLAG_OEI ((uint16_t)0x01UL << 10) /*!< Overrun error interrupt */
#define UART_IT_FLAG_BEI ((uint16_t)0x01UL << 9) /*!< Break error interrupt */
#define UART_IT_FLAG_PEI ((uint16_t)0x01UL << 8) /*!< Parity error interrupt */
#define UART_IT_FLAG_FEI ((uint16_t)0x01UL << 7) /*!< Framing error interrupt */
#define UART_IT_FLAG_RTI ((uint16_t)0x01UL << 6) /*!< Receive timeout interrupt */
#define UART_IT_FLAG_TXI ((uint16_t)0x01UL << 5) /*!< Transmit interrupt */
#define UART_IT_FLAG_RXI ((uint16_t)0x01UL << 4) /*!< Receive interrupt */
#define UART_IT_FLAG_DSRMI ((uint16_t)0x01UL << 3) /*!< UARTDSR modem interrupt */
#define UART_IT_FLAG_DCDMI ((uint16_t)0x01UL << 2) /*!< UARTDCD modem interrupt */
#define UART_IT_FLAG_CTSMI ((uint16_t)0x01UL << 1) /*!< UARTCTS modem interrupt */
#define UART_IT_FLAG_RIMI ((uint16_t)0x01UL << 0) /*!< UARTRI modem interrupt */
#define IS_UART_IT_FLAG(FLAG) (((FLAG) == UART_IT_FLAG_OEI) || ((FLAG) == UART_IT_FLAG_BEI) || \
((FLAG) == UART_IT_FLAG_PEI) || ((FLAG) == UART_IT_FLAG_FEI) || \
((FLAG) == UART_IT_FLAG_RTI) || ((FLAG) == UART_IT_FLAG_TXI) || \
((FLAG) == UART_IT_FLAG_RXI) || ((FLAG) == UART_IT_FLAG_DSRMI) || \
((FLAG) == UART_IT_FLAG_DCDMI)|| ((FLAG) == UART_IT_FLAG_CTSMI) || \
((FLAG) == UART_IT_FLAG_RIMI))
/**
* @}
*/
/** @addtogroup UART_FIFO_Level Select
* @{
*/
#define UART_IFLS_RXIFLSEL7_8 ((uint16_t)(UART_IFLS_RXIFLSEL(4)))
#define UART_IFLS_RXIFLSEL3_4 ((uint16_t)(UART_IFLS_RXIFLSEL(3)))
#define UART_IFLS_RXIFLSEL1_2 ((uint16_t)(UART_IFLS_RXIFLSEL(2)))
#define UART_IFLS_RXIFLSEL1_4 ((uint16_t)(UART_IFLS_RXIFLSEL(1)))
#define UART_IFLS_RXIFLSEL1_8 ((uint16_t)(UART_IFLS_RXIFLSEL(0)))
#define UART_IFLS_TXIFLSEL7_8 ((uint16_t)(UART_IFLS_TXIFLSEL(4)))
#define UART_IFLS_TXIFLSEL3_4 ((uint16_t)(UART_IFLS_TXIFLSEL(3)))
#define UART_IFLS_TXIFLSEL1_2 ((uint16_t)(UART_IFLS_TXIFLSEL(2)))
#define UART_IFLS_TXIFLSEL1_4 ((uint16_t)(UART_IFLS_TXIFLSEL(1)))
#define UART_IFLS_TXIFLSEL1_8 ((uint16_t)(UART_IFLS_TXIFLSEL(0)))
#define IS_UART_FIFO_Level(FLAG) (((FLAG) == UART_IFLS_RXIFLSEL7_8) || ((FLAG) == UART_IFLS_RXIFLSEL3_4)|| \
((FLAG) == UART_IFLS_RXIFLSEL1_2)|| ((FLAG) == UART_IFLS_RXIFLSEL1_4)|| ((FLAG) == UART_IFLS_RXIFLSEL1_8)||\
((FLAG) == UART_IFLS_TXIFLSEL7_8)|| ((FLAG) == UART_IFLS_TXIFLSEL3_4)|| \
((FLAG) == UART_IFLS_TXIFLSEL1_2)|| ((FLAG) == UART_IFLS_TXIFLSEL1_4)||((FLAG) == UART_IFLS_TXIFLSEL1_8))
/**
* @}
*/
/** @addtogroup S_UART_Flags
* @{
*/
#define S_UART_FLAG_RXO ((uint16_t)0x01UL << 3) /*!< RX buffer Overrun */
#define S_UART_FLAG_TXO ((uint16_t)0x01UL << 2) /*!< TX buffer Overrun */
#define S_UART_FLAG_RXF ((uint16_t)0x01UL << 1) /*!< RX buffer Full */
#define S_UART_FLAG_TXF ((uint16_t)0x01UL << 0) /*!< TX buffer Full */
#define IS_S_UART_FLAG(FLAG) (((FLAG) == S_UART_FLAG_RXO) || ((FLAG) == S_UART_FLAG_TXO) || \
((FLAG) == S_UART_FLAG_RXF) || ((FLAG) == S_UART_FLAG_TXF))
/**
* @}
*/
/** @addtogroup S_UART_IT_Flags
* @{
*/
#define S_UART_IT_FLAG_RXOI ((uint16_t)0x01UL << 5) /*!< RX overrun interrupt */
#define S_UART_IT_FLAG_TXOI ((uint16_t)0x01UL << 4) /*!< TX overrun interrupt */
#define S_UART_IT_FLAG_RXI ((uint16_t)0x01UL << 3) /*!< RX interrupt */
#define S_UART_IT_FLAG_TXI ((uint16_t)0x01UL << 2) /*!< TX interrupt */
#define IS_S_UART_IT_FLAG(FLAG) (((FLAG) == S_UART_IT_FLAG_RXOI) || ((FLAG) == S_UART_IT_FLAG_TXOI) || \
((FLAG) == S_UART_IT_FLAG_RXI) || ((FLAG) == S_UART_IT_FLAG_TXI))
/**
* @}
*/
void UART_StructInit (UART_InitTypeDef* UART_InitStruct);
uint32_t UART_Init (UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct);
void UART_SendData (UART_TypeDef* UARTx, uint16_t Data);
uint16_t UART_ReceiveData (UART_TypeDef* UARTx);
void UART_SendBreak (UART_TypeDef* UARTx);
void UART_ClearRecvStatus (UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS);
FlagStatus UART_GetFlagStatus (UART_TypeDef* UARTx, uint16_t UART_FLAG);
void UART_ITConfig (UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState);
ITStatus UART_GetITStatus (UART_TypeDef* UARTx, uint16_t UART_IT);
void UART_ClearITPendingBit (UART_TypeDef* UARTx, uint16_t UART_IT);
void S_UART_DeInit(void);
uint32_t S_UART_Init(uint32_t baud);
void S_UART_SendData(uint16_t Data);
uint16_t S_UART_ReceiveData(void);
uint8_t UartPutc (UART_TypeDef* UARTx, uint8_t ch);
void UartPuts (UART_TypeDef* UARTx, uint8_t *str);
uint8_t UartGetc (UART_TypeDef* UARTx);
uint8_t S_UartPutc(uint8_t ch);
void S_UartPuts(uint8_t *str);
uint8_t S_UartGetc(void);
#ifdef __cplusplus
}
#endif
#endif // __W7500X_UART_H

8
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/spi_api.c
View File

@ -41,14 +41,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
obj->spi->MCR &= ~(SPI_MCR_MDIS_MASK | SPI_MCR_HALT_MASK);
//obj->spi->MCR |= SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK;
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// not halt in the debug mode
obj->spi->SR |= SPI_SR_EOQF_MASK;

8
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/spi_api.c
View File

@ -60,14 +60,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable SPI
obj->spi->C1 |= SPI_C1_SPE_MASK;

8
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/spi_api.c
View File

@ -40,14 +40,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable SPI
obj->spi->C1 |= SPI_C1_SPE_MASK;

8
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/spi_api.c
View File

@ -81,14 +81,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable SPI
obj->spi->C1 |= SPI_C1_SPE_MASK;
obj->spi->C2 &= ~SPI_C2_SPIMODE_MASK; //8bit

8
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/spi_api.c
View File

@ -98,14 +98,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable SPI
obj->spi->C1 |= SPI_C1_SPE_MASK;
obj->spi->C2 &= ~SPI_C2_SPIMODE_MASK; //8bit

7
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/spi_api.c
View File

@ -43,14 +43,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
uint32_t spi_address[] = SPI_BASE_ADDRS;
DSPI_HAL_Init(spi_address[obj->instance]);
DSPI_HAL_Disable(spi_address[obj->instance]);
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
DSPI_HAL_SetDelay(spi_address[obj->instance], kDspiCtar0, 0, 0, kDspiPcsToSck);
spi_frequency(obj, 1000000);
DSPI_HAL_Enable(spi_address[obj->instance]);
DSPI_HAL_StartTransfer(spi_address[obj->instance]);

8
libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/PinNames.h
View File

@ -170,10 +170,10 @@ typedef enum {
AOUT_CO = (0xF << PORT_SHIFT) | 2,
AOUT_DO = (0xF << PORT_SHIFT) | 3,
LED_GREEN = P7_4,
LED_RED = P7_0,
LED_YELLOW = P6_6,
LED_BLUE = P7_6,
LED_GREEN = P6_6,
LED_RED = P7_1,
LED_YELLOW = P7_0,
LED_BLUE = P6_7,
// mbed original LED naming
LED1 = LED_RED,

2
libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/spi_api.c
View File

@ -115,7 +115,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
void spi_frequency(spi_t *obj, int hz)
{
// Maximum frequency is half the system frequency
MBED_ASSERT((unsigned int)hz < (SystemCoreClock / 2));
MBED_ASSERT((unsigned int)hz <= (SystemCoreClock / 2));
unsigned clocks = ((SystemCoreClock/2)/(hz));
// Figure out the divider ratio

6
libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/spi_api.c
View File

@ -88,10 +88,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
obj->spi->gen_ctrl = (MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN |
MXC_F_SPI_GEN_CTRL_TX_FIFO_EN |
MXC_F_SPI_GEN_CTRL_RX_FIFO_EN );
// Give instance the default settings
spi_format(obj, DEFAULT_CHAR, DEFAULT_MODE, 0);
spi_frequency(obj, DEFAULT_FREQ);
}
//******************************************************************************
@ -115,7 +111,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
void spi_frequency(spi_t *obj, int hz)
{
// Maximum frequency is half the system frequency
MBED_ASSERT((unsigned int)hz < (SystemCoreClock / 2));
MBED_ASSERT((unsigned int)hz <= (SystemCoreClock / 2));
unsigned clocks = ((SystemCoreClock/2)/(hz));
// Figure out the divider ratio

12
libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h
View File

@ -90,12 +90,12 @@ typedef enum {
I2C_SDA0 = p22,
I2C_SCL0 = p20,
A0 = p0,
A1 = p1,
A2 = p2,
A3 = p3,
A4 = p4,
A5 = p5,
A0 = p1,
A1 = p2,
A2 = p3,
A3 = p4,
A4 = p5,
A5 = p6,
SWIO = p19,
VERF0 = p0,

8
libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c
View File

@ -25,7 +25,7 @@
#define CMD_POWER_UP (0xAB)
#define CMD_POWER_DOWN (0xB9)
void spi_flash_init(void)
void flash_init(void)
{
NRF_GPIO->PIN_CNF[SPIM1_MOSI_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
@ -79,7 +79,7 @@ void spi_flash_init(void)
}
void spi_flash_powerDown(void)
void flash_powerDown(void)
{
NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos);
//spi.write(CMD_POWER_DOWN);
@ -115,9 +115,9 @@ void mbed_sdk_init()
{// Do nothing.
}
spi_flash_init();
flash_init();
//nrf_delay_ms(10);
spi_flash_powerDown();
flash_powerDown();
}

11
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/spi_api.c
View File

@ -85,17 +85,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable the ssp channel
ssp_enable(obj);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);

11
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/spi_api.c
View File

@ -50,17 +50,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable the ssp channel
ssp_enable(obj);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);

11
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/spi_api.c
View File

@ -87,17 +87,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable the ssp channel
ssp_enable(obj);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);

11
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC13XX/spi_api.c
View File

@ -79,17 +79,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable the ssp channel
ssp_enable(obj);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);

11
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/spi_api.c
View File

@ -158,17 +158,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
LPC_SYSCON->SYSAHBCLKCTRL1 |= (0x1 << (obj->spi_n + 9));
LPC_SYSCON->PRESETCTRL1 |= (0x1 << (obj->spi_n + 9));
LPC_SYSCON->PRESETCTRL1 &= ~(0x1 << (obj->spi_n + 9));
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable the spi channel
spi_enable(obj);
}
void spi_free(spi_t *obj)

11
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/spi_api.c
View File

@ -72,17 +72,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
case SPI_0: LPC_SC->PCONP |= 1 << 21; break;
case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable the ssp channel
ssp_enable(obj);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);

11
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC23XX/spi_api.c
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@ -73,17 +73,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable the ssp channel
ssp_enable(obj);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);

120
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PeripheralNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)LPC_UART0_BASE,
UART_1 = (int)LPC_UART1_BASE,
UART_2 = (int)LPC_UART2_BASE,
UART_3 = (int)LPC_UART3_BASE
} UARTName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3,
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7
} ADCName;
typedef enum {
DAC_0 = 0
} DACName;
typedef enum {
SPI_0 = (int)LPC_SSP0_BASE,
SPI_1 = (int)LPC_SSP1_BASE
} SPIName;
typedef enum {
I2C_0 = (int)LPC_I2C0_BASE,
I2C_1 = (int)LPC_I2C1_BASE,
I2C_2 = (int)LPC_I2C2_BASE
} I2CName;
typedef enum {
PWM_1 = 1,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6
} PWMName;
typedef enum {
CAN_1 = (int)LPC_CAN1_BASE,
CAN_2 = (int)LPC_CAN2_BASE
} CANName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_2
// Default peripherals
#define MBED_SPI0 p5, p6, p7, p8
//#define MBED_SPI1 p11, p12, p13, p14
#define MBED_UART0 p9, p10
#define MBED_UART1 p13, p14
#define MBED_UART2 p15, p16
#define MBED_UARTUSB USBTX, USBRX
#define MBED_I2C0 p17, p18
//#define MBED_I2C1 p9, p10
#define MBED_CAN0 p19, p20
#define MBED_ANALOGOUT0 p21
#define MBED_ANALOGIN0 p22
#define MBED_ANALOGIN1 p23
//#define MBED_ANALOGIN2 p17
//#define MBED_ANALOGIN3 p18
//#define MBED_ANALOGIN4 p19
//#define MBED_ANALOGIN5 p20
#define MBED_PWMOUT0 p24
#define MBED_PWMOUT1 p25
#define MBED_PWMOUT2 p26
#define MBED_PWMOUT3 p27
//#define MBED_PWMOUT4 p22
//#define MBED_PWMOUT5 p21
#define MBED_USB_D_PLUS p28
#define MBED_USB_D_MINUS p29
#define MBED_MCICLK p30
#define MBED_MCICMD p31
#define MBED_MCIDAT0 p32
#define MBED_MCIDAT1 p33
#define MBED_MCIDAT2 p34
#define MBED_MCIDAT3 p35
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PinNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// LPC Pin Names
P0_0 = LPC_GPIO0_BASE,
P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,
P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,
P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,
// mbed DIP Pin Names
p5 = P0_18,
p6 = P0_17,
p7 = P0_15,
p8 = P0_16,
p9 = P0_2,
p10 = P0_3,
p11 = P0_18,
p12 = P0_17,
p13 = P2_0,
p14 = P2_1,
p15 = P4_28,
p16 = P4_29,
p17 = P2_30,
p18 = P2_31,
p19 = P0_0,
p20 = P0_1,
p21 = P0_26,
p22 = P0_12,
p23 = P0_13,
p24 = P1_20,
p25 = P1_21,
p26 = P1_23,
p27 = P1_24,
p28 = P0_29,
p29 = P0_30,
p30 = P1_2,
p31 = P1_3,
p32 = P1_6,
p33 = P1_7,
p34 = P1_11,
p35 = P1_12,
// Other mbed Pin Names
LED1 = P1_19,
LED2 = P2_26,
LED3 = P2_27,
LED4 = P2_27,
USBTX = P2_8,
USBRX = P2_9,
EXT_WDT = P0_10,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullUp = 0,
PullDown = 3,
PullNone = 2,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
// version of PINCON_TypeDef using register arrays
typedef struct {
__IO uint32_t PINSEL[11];
uint32_t RESERVED0[5];
__IO uint32_t PINMODE[10];
} PINCONARRAY_TypeDef;
#define PINCONARRAY ((PINCONARRAY_TypeDef *)LPC_PINCON_BASE)
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PortNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
Port0 = 0,
Port1 = 1,
Port2 = 2,
Port3 = 3,
Port4 = 4
} PortName;
#define PORT_0 Port0
#define PORT_1 Port1
#define PORT_2 Port2
#define PORT_3 Port3
#ifdef __cplusplus
}
#endif
#endif

125
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/analogin_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogin_api.h"
#include "cmsis.h"
#include "pinmap.h"
#define ANALOGIN_MEDIAN_FILTER 1
#define ADC_10BIT_RANGE 0x3FF
#define ADC_12BIT_RANGE 0xFFF
static inline int div_round_up(int x, int y) {
return (x + (y - 1)) / y;
}
static const PinMap PinMap_ADC[] = {
{P0_23, ADC0_0, 1},
{P0_24, ADC0_1, 1},
{P0_25, ADC0_2, 1},
{P0_26, ADC0_3, 1},
{P1_30, ADC0_4, 3},
{P1_31, ADC0_5, 3},
{P0_12, ADC0_6, 3},
{P0_13, ADC0_7, 3},
{NC, NC, 0}
};
#define ADC_RANGE ADC_10BIT_RANGE
void analogin_init(analogin_t *obj, PinName pin) {
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
// ensure power is turned on
LPC_SC->PCONP |= (1 << PCADC);
// set PCLK of ADC to /1
LPC_SC->PCLKSEL0 &= ~(0x3 << 24);
LPC_SC->PCLKSEL0 |= (0x1 << 24);
uint32_t PCLK = SystemCoreClock;
// calculate minimum clock divider
// clkdiv = divider - 1
uint32_t MAX_ADC_CLK = 4500000;
uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1;
// Set the generic software-controlled ADC settings
LPC_ADC->ADCR = (0 << 0) // SEL: 0 = no channels selected
| (clkdiv << 8) // CLKDIV: PCLK max ~= 25MHz, /25 to give safe 1MHz at fastest
| (0 << 16) // BURST: 0 = software control
| (0 << 17) // CLKS: not applicable
| (1 << 21) // PDN: 1 = operational
| (0 << 24) // START: 0 = no start
| (0 << 27); // EDGE: not applicable
pinmap_pinout(pin, PinMap_ADC);
}
static inline uint32_t adc_read(analogin_t *obj) {
// Select the appropriate channel and start conversion
LPC_ADC->ADCR &= ~0xFF;
LPC_ADC->ADCR |= 1 << (int)obj->adc;
LPC_ADC->ADCR |= 1 << 24;
// Repeatedly get the sample data until DONE bit
unsigned int data;
do {
data = LPC_ADC->ADGDR;
} while ((data & ((unsigned int)1 << 31)) == 0);
// Stop conversion
LPC_ADC->ADCR &= ~(1 << 24);
return (data >> 6) & ADC_RANGE; // 10 bit
}
static inline void order(uint32_t *a, uint32_t *b) {
if (*a > *b) {
uint32_t t = *a;
*a = *b;
*b = t;
}
}
static inline uint32_t adc_read_u32(analogin_t *obj) {
uint32_t value;
#if ANALOGIN_MEDIAN_FILTER
uint32_t v1 = adc_read(obj);
uint32_t v2 = adc_read(obj);
uint32_t v3 = adc_read(obj);
order(&v1, &v2);
order(&v2, &v3);
order(&v1, &v2);
value = v2;
#else
value = adc_read(obj);
#endif
return value;
}
uint16_t analogin_read_u16(analogin_t *obj) {
uint32_t value = adc_read_u32(obj);
return (value << 6) | ((value >> 4) & 0x003F); // 10 bit
}
float analogin_read(analogin_t *obj) {
uint32_t value = adc_read_u32(obj);
return (float)value * (1.0f / (float)ADC_RANGE);
}

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/analogout_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogout_api.h"
#include "cmsis.h"
#include "pinmap.h"
static const PinMap PinMap_DAC[] = {
{P0_26, DAC_0, 2},
{NC , NC , 0}
};
void analogout_init(dac_t *obj, PinName pin) {
obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
MBED_ASSERT(obj->dac != (DACName)NC);
// power is on by default, set DAC clk divider is /4
LPC_SC->PCLKSEL0 &= ~(0x3 << 22);
// map out (must be done before accessing registers)
pinmap_pinout(pin, PinMap_DAC);
analogout_write_u16(obj, 0);
}
void analogout_free(dac_t *obj) {}
static inline void dac_write(int value) {
value &= 0x3FF; // 10-bit
// Set the DAC output
LPC_DAC->DACR = (0 << 16) // bias = 0
| (value << 6);
}
static inline int dac_read() {
return (LPC_DAC->DACR >> 6) & 0x3FF;
}
void analogout_write(dac_t *obj, float value) {
if (value < 0.0f) {
dac_write(0);
} else if (value > 1.0f) {
dac_write(0x3FF);
} else {
dac_write(value * (float)0x3FF);
}
}
void analogout_write_u16(dac_t *obj, uint16_t value) {
dac_write(value >> 6); // 10-bit
}
float analogout_read(dac_t *obj) {
uint32_t value = dac_read();
return (float)value * (1.0f / (float)0x3FF);
}
uint16_t analogout_read_u16(dac_t *obj) {
uint32_t value = dac_read(); // 10-bit
return (value << 6) | ((value >> 4) & 0x003F);
}

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/can_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "can_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include <math.h>
#include <string.h>
/* Acceptance filter mode in AFMR register */
#define ACCF_OFF 0x01
#define ACCF_BYPASS 0x02
#define ACCF_ON 0x00
#define ACCF_FULLCAN 0x04
/* There are several bit timing calculators on the internet.
http://www.port.de/engl/canprod/sv_req_form.html
http://www.kvaser.com/can/index.htm
*/
static const PinMap PinMap_CAN_RD[] = {
{P0_0 , CAN_1, 1},
{P0_4 , CAN_2, 2},
{P0_21, CAN_1, 3},
{P2_7 , CAN_2, 1},
{NC , NC , 0}
};
static const PinMap PinMap_CAN_TD[] = {
{P0_1 , CAN_1, 1},
{P0_5 , CAN_2, 2},
{P0_22, CAN_1, 3},
{P2_8 , CAN_2, 1},
{NC , NC , 0}
};
// Type definition to hold a CAN message
struct CANMsg {
unsigned int reserved1 : 16;
unsigned int dlc : 4; // Bits 16..19: DLC - Data Length Counter
unsigned int reserved0 : 10;
unsigned int rtr : 1; // Bit 30: Set if this is a RTR message
unsigned int type : 1; // Bit 31: Set if this is a 29-bit ID message
unsigned int id; // CAN Message ID (11-bit or 29-bit)
unsigned char data[8]; // CAN Message Data Bytes 0-7
};
typedef struct CANMsg CANMsg;
static uint32_t can_disable(can_t *obj) {
uint32_t sm = obj->dev->MOD;
obj->dev->MOD |= 1;
return sm;
}
static inline void can_enable(can_t *obj) {
if (obj->dev->MOD & 1) {
obj->dev->MOD &= ~(1);
}
}
int can_mode(can_t *obj, CanMode mode) {
return 0; // not implemented
}
int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
return 0; // not implemented
}
static int can_pclk(can_t *obj) {
int value = 0;
switch ((int)obj->dev) {
case CAN_1: value = (LPC_SC->PCLKSEL0 & (0x3 << 26)) >> 26; break;
case CAN_2: value = (LPC_SC->PCLKSEL0 & (0x3 << 28)) >> 28; break;
}
switch (value) {
case 1: return 1;
case 2: return 2;
case 3: return 6;
default: return 4;
}
}
// This table has the sampling points as close to 75% as possible. The first
// value is TSEG1, the second TSEG2.
static const int timing_pts[23][2] = {
{0x0, 0x0}, // 2, 50%
{0x1, 0x0}, // 3, 67%
{0x2, 0x0}, // 4, 75%
{0x3, 0x0}, // 5, 80%
{0x3, 0x1}, // 6, 67%
{0x4, 0x1}, // 7, 71%
{0x5, 0x1}, // 8, 75%
{0x6, 0x1}, // 9, 78%
{0x6, 0x2}, // 10, 70%
{0x7, 0x2}, // 11, 73%
{0x8, 0x2}, // 12, 75%
{0x9, 0x2}, // 13, 77%
{0x9, 0x3}, // 14, 71%
{0xA, 0x3}, // 15, 73%
{0xB, 0x3}, // 16, 75%
{0xC, 0x3}, // 17, 76%
{0xD, 0x3}, // 18, 78%
{0xD, 0x4}, // 19, 74%
{0xE, 0x4}, // 20, 75%
{0xF, 0x4}, // 21, 76%
{0xF, 0x5}, // 22, 73%
{0xF, 0x6}, // 23, 70%
{0xF, 0x7}, // 24, 67%
};
static unsigned int can_speed(unsigned int sclk, unsigned int pclk, unsigned int cclk, unsigned char psjw) {
uint32_t btr;
uint16_t brp = 0;
uint32_t calcbit;
uint32_t bitwidth;
int hit = 0;
int bits;
bitwidth = sclk / (pclk * cclk);
brp = bitwidth / 0x18;
while ((!hit) && (brp < bitwidth / 4)) {
brp++;
for (bits = 22; bits > 0; bits--) {
calcbit = (bits + 3) * (brp + 1);
if (calcbit == bitwidth) {
hit = 1;
break;
}
}
}
if (hit) {
btr = ((timing_pts[bits][1] << 20) & 0x00700000)
| ((timing_pts[bits][0] << 16) & 0x000F0000)
| ((psjw << 14) & 0x0000C000)
| ((brp << 0) & 0x000003FF);
} else {
btr = 0xFFFFFFFF;
}
return btr;
}
void can_init(can_t *obj, PinName rd, PinName td) {
CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td);
MBED_ASSERT((int)obj->dev != NC);
switch ((int)obj->dev) {
case CAN_1: LPC_SC->PCONP |= 1 << PCAN1; break;
case CAN_2: LPC_SC->PCONP |= 1 << PCAN2; break;
}
pinmap_pinout(rd, PinMap_CAN_RD);
pinmap_pinout(td, PinMap_CAN_TD);
can_reset(obj);
obj->dev->IER = 0; // Disable Interrupts
can_frequency(obj, 100000);
LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter
}
void can_free(can_t *obj) {
switch ((int)obj->dev) {
case CAN_1: LPC_SC->PCONP &= ~(1 << PCAN1); break;
case CAN_2: LPC_SC->PCONP &= ~(1 << PCAN2); break;
}
}
int can_frequency(can_t *obj, int f) {
int pclk = can_pclk(obj);
int btr = can_speed(SystemCoreClock, pclk, (unsigned int)f, 1);
if (btr > 0) {
uint32_t modmask = can_disable(obj);
obj->dev->BTR = btr;
obj->dev->MOD = modmask;
return 1;
} else {
return 0;
}
}
int can_write(can_t *obj, CAN_Message msg, int cc) {
unsigned int CANStatus;
CANMsg m;
can_enable(obj);
m.id = msg.id ;
m.dlc = msg.len & 0xF;
m.rtr = msg.type;
m.type = msg.format;
memcpy(m.data, msg.data, msg.len);
const unsigned int *buf = (const unsigned int *)&m;
CANStatus = obj->dev->SR;
if (CANStatus & 0x00000004) {
obj->dev->TFI1 = buf[0] & 0xC00F0000;
obj->dev->TID1 = buf[1];
obj->dev->TDA1 = buf[2];
obj->dev->TDB1 = buf[3];
if (cc) {
obj->dev->CMR = 0x30;
} else {
obj->dev->CMR = 0x21;
}
return 1;
} else if (CANStatus & 0x00000400) {
obj->dev->TFI2 = buf[0] & 0xC00F0000;
obj->dev->TID2 = buf[1];
obj->dev->TDA2 = buf[2];
obj->dev->TDB2 = buf[3];
if (cc) {
obj->dev->CMR = 0x50;
} else {
obj->dev->CMR = 0x41;
}
return 1;
} else if (CANStatus & 0x00040000) {
obj->dev->TFI3 = buf[0] & 0xC00F0000;
obj->dev->TID3 = buf[1];
obj->dev->TDA3 = buf[2];
obj->dev->TDB3 = buf[3];
if (cc) {
obj->dev->CMR = 0x90;
} else {
obj->dev->CMR = 0x81;
}
return 1;
}
return 0;
}
int can_read(can_t *obj, CAN_Message *msg, int handle) {
CANMsg x;
unsigned int *i = (unsigned int *)&x;
can_enable(obj);
if (obj->dev->GSR & 0x1) {
*i++ = obj->dev->RFS; // Frame
*i++ = obj->dev->RID; // ID
*i++ = obj->dev->RDA; // Data A
*i++ = obj->dev->RDB; // Data B
obj->dev->CMR = 0x04; // release receive buffer
msg->id = x.id;
msg->len = x.dlc;
msg->format = (x.type)? CANExtended : CANStandard;
msg->type = (x.rtr)? CANRemote: CANData;
memcpy(msg->data,x.data,x.dlc);
return 1;
}
return 0;
}
void can_reset(can_t *obj) {
can_disable(obj);
obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset
}
unsigned char can_rderror(can_t *obj) {
return (obj->dev->GSR >> 16) & 0xFF;
}
unsigned char can_tderror(can_t *obj) {
return (obj->dev->GSR >> 24) & 0xFF;
}
void can_monitor(can_t *obj, int silent) {
uint32_t mod_mask = can_disable(obj);
if (silent) {
obj->dev->MOD |= (1 << 1);
} else {
obj->dev->MOD &= ~(1 << 1);
}
if (!(mod_mask & 1)) {
can_enable(obj);
}
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_PORTIN 1
#define DEVICE_PORTOUT 1
#define DEVICE_PORTINOUT 1
#define DEVICE_INTERRUPTIN 1
#define DEVICE_ANALOGIN 1
#define DEVICE_ANALOGOUT 1
#define DEVICE_SERIAL 1
#define DEVICE_I2C 1
#define DEVICE_I2CSLAVE 1
#define DEVICE_SPI 1
#define DEVICE_SPISLAVE 1
#define DEVICE_CAN 1
#define DEVICE_RTC 1
#define DEVICE_ETHERNET 1
#define DEVICE_PWMOUT 1
#define DEVICE_SEMIHOST 0
#define DEVICE_LOCALFILESYSTEM 0
#define DEVICE_ID_LENGTH 32
#define DEVICE_MAC_OFFSET 20
#define DEVICE_SLEEP 0
#define DEVICE_DEBUG_AWARENESS 0
#define DEVICE_STDIO_MESSAGES 1
#define DEVICE_ERROR_PATTERN 1
#include "objects.h"
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <string.h>
#include "ethernet_api.h"
#include "cmsis.h"
#include "mbed_interface.h"
#include "toolchain.h"
#include "mbed_error.h"
#define NEW_LOGIC 0
#define NEW_ETH_BUFFER 0
#if NEW_ETH_BUFFER
#define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets)
#define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets)
#define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size
#define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length)
#else
// Memfree calculation:
// (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
// (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
#define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
//#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
//#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
#define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */
#define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */
const int ethernet_MTU_SIZE = 0x300;
#endif
#define ETHERNET_ADDR_SIZE 6
PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */
unsigned int Packet;
unsigned int Ctrl;
};
typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
PACKED struct RX_STAT_TypeDef { /* RX Status struct */
unsigned int Info;
unsigned int HashCRC;
};
typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */
unsigned int Packet;
unsigned int Ctrl;
};
typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
PACKED struct TX_STAT_TypeDef { /* TX Status struct */
unsigned int Info;
};
typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
/* MAC Configuration Register 1 */
#define MAC1_REC_EN 0x00000001 /* Receive Enable */
#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
/* MAC Configuration Register 2 */
#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
/* Back-to-Back Inter-Packet-Gap Register */
#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
/* Non Back-to-Back Inter-Packet-Gap Register */
#define IPGR_DEF 0x00000012 /* Recommended value */
/* Collision Window/Retry Register */
#define CLRT_DEF 0x0000370F /* Default value */
/* PHY Support Register */
#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
//#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
#define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */
/* Test Register */
#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
#define TEST_TST_PAUSE 0x00000002 /* Test Pause */
#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
/* MII Management Configuration Register */
#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
#define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */
#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
/* MII Management Command Register */
#define MCMD_READ 0x00000001 /* MII Read */
#define MCMD_SCAN 0x00000002 /* MII Scan continuously */
#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
/* MII Management Address Register */
#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
/* MII Management Indicators Register */
#define MIND_BUSY 0x00000001 /* MII is Busy */
#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
/* Command Register */
#define CR_RX_EN 0x00000001 /* Enable Receive */
#define CR_TX_EN 0x00000002 /* Enable Transmit */
#define CR_REG_RES 0x00000008 /* Reset Host Registers */
#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
#define CR_RMII 0x00000200 /* Reduced MII Interface */
#define CR_FULL_DUP 0x00000400 /* Full Duplex */
/* Status Register */
#define SR_RX_EN 0x00000001 /* Enable Receive */
#define SR_TX_EN 0x00000002 /* Enable Transmit */
/* Transmit Status Vector 0 Register */
#define TSV0_CRC_ERR 0x00000001 /* CRC error */
#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
#define TSV0_DONE 0x00000008 /* Tramsmission Completed */
#define TSV0_MCAST 0x00000010 /* Multicast Destination */
#define TSV0_BCAST 0x00000020 /* Broadcast Destination */
#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
#define TSV0_GIANT 0x00000400 /* Giant Frame */
#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
#define TSV0_PAUSE 0x20000000 /* Pause Frame */
#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
#define TSV0_VLAN 0x80000000 /* VLAN Frame */
/* Transmit Status Vector 1 Register */
#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
/* Receive Status Vector Register */
#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
#define RSV_CRC_ERR 0x00100000 /* CRC Error */
#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
#define RSV_REC_OK 0x00800000 /* Frame Received OK */
#define RSV_MCAST 0x01000000 /* Multicast Frame */
#define RSV_BCAST 0x02000000 /* Broadcast Frame */
#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
#define RSV_PAUSE 0x10000000 /* Pause Frame */
#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
#define RSV_VLAN 0x40000000 /* VLAN Frame */
/* Flow Control Counter Register */
#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
/* Flow Control Status Register */
#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
/* Receive Filter Control Register */
#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
/* Receive Filter WoL Status/Clear Registers */
#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
/* Interrupt Status/Enable/Clear/Set Registers */
#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
#define INT_RX_ERR 0x00000002 /* Receive Error */
#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
#define INT_RX_DONE 0x00000008 /* Receive Done */
#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
#define INT_TX_ERR 0x00000020 /* Transmit Error */
#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
#define INT_TX_DONE 0x00000080 /* Transmit Done */
#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
/* Power Down Register */
#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
/* RX Descriptor Control Word */
#define RCTRL_SIZE 0x000007FF /* Buffer size mask */
#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
/* RX Status Hash CRC Word */
#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
/* RX Status Information Word */
#define RINFO_SIZE 0x000007FF /* Data size in bytes */
#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
#define RINFO_VLAN 0x00080000 /* VLAN Frame */
#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
#define RINFO_MCAST 0x00200000 /* Multicast Frame */
#define RINFO_BCAST 0x00400000 /* Broadcast Frame */
#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
#define RINFO_LEN_ERR 0x02000000 /* Length Error */
#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
#define RINFO_OVERRUN 0x10000000 /* Receive overrun */
#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
//#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
/* TX Descriptor Control Word */
#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
/* TX Status Information Word */
#define TINFO_COL_CNT 0x01E00000 /* Collision Count */
#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
/* ENET Device Revision ID */
#define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
/* DP83848C PHY Registers */
#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
/* PHY Extended Registers */
#define PHY_REG_STS 0x10 /* Status Register */
#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
#define PHY_REG_RECR 0x15 /* Receive Error Counter */
#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
#define PHY_REG_PHYCR 0x19 /* PHY Control Register */
#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
#define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */
#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
#define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */
#define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */
#define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */
#define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */
#define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */
#define PHY_BMCR_RESET 0x8000 /* PHY Reset */
#define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */
#define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */
#define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */
static int phy_read(unsigned int PhyReg);
static int phy_write(unsigned int PhyReg, unsigned short Data);
static void txdscr_init(void);
static void rxdscr_init(void);
#if defined (__ICCARM__)
# define AHBSRAM1
#elif defined(TOOLCHAIN_GCC_CR)
# define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
#else
# define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned))
#endif
AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG];
AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG];
#if NEW_LOGIC
static int rx_consume_offset = -1;
static int tx_produce_offset = -1;
#else
static int send_doff = 0;
static int send_idx = -1;
static int send_size = 0;
static int receive_soff = 0;
static int receive_idx = -1;
#endif
static uint32_t phy_id = 0;
static inline int rinc(int idx, int mod) {
++idx;
idx %= mod;
return idx;
}
//extern unsigned int SystemFrequency;
static inline unsigned int clockselect() {
if(SystemCoreClock < 10000000) {
return 1;
} else if(SystemCoreClock < 15000000) {
return 2;
} else if(SystemCoreClock < 20000000) {
return 3;
} else if(SystemCoreClock < 25000000) {
return 4;
} else if(SystemCoreClock < 35000000) {
return 5;
} else if(SystemCoreClock < 50000000) {
return 6;
} else if(SystemCoreClock < 70000000) {
return 7;
} else if(SystemCoreClock < 80000000) {
return 8;
} else if(SystemCoreClock < 90000000) {
return 9;
} else if(SystemCoreClock < 100000000) {
return 10;
} else if(SystemCoreClock < 120000000) {
return 11;
} else if(SystemCoreClock < 130000000) {
return 12;
} else if(SystemCoreClock < 140000000) {
return 13;
} else if(SystemCoreClock < 150000000) {
return 15;
} else if(SystemCoreClock < 160000000) {
return 16;
} else {
return 0;
}
}
#ifndef min
#define min(x, y) (((x)<(y))?(x):(y))
#endif
/*----------------------------------------------------------------------------
Ethernet Device initialize
*----------------------------------------------------------------------------*/
int ethernet_init() {
int regv, tout;
char mac[ETHERNET_ADDR_SIZE];
unsigned int clock = clockselect();
LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */
LPC_PINCON->PINSEL2 = 0x50150105; /* Enable P1 Ethernet Pins. */
LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
/* Reset all EMAC internal modules. */
LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
for(tout = 100; tout; tout--) __NOP(); /* A short delay after reset. */
LPC_EMAC->MAC1 = MAC1_PASS_ALL; /* Initialize MAC control registers. */
LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
LPC_EMAC->MAXF = ETH_MAX_FLEN;
LPC_EMAC->CLRT = CLRT_DEF;
LPC_EMAC->IPGR = IPGR_DEF;
LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Enable Reduced MII interface. */
LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */
LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */
for(tout = 100; tout; tout--) __NOP(); /* A short delay */
LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
LPC_EMAC->MCMD = 0;
LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */
for (tout = 100; tout; tout--) __NOP(); /* A short delay */
LPC_EMAC->SUPP = 0;
phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */
for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */
regv = phy_read(PHY_REG_BMCR);
if(regv < 0 || tout == 0) {
return -1; /* Error */
}
if(!(regv & PHY_BMCR_RESET)) {
break; /* Reset complete. */
}
}
phy_id = (phy_read(PHY_REG_IDR1) << 16);
phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
}
ethernet_set_link(-1, 0);
/* Set the Ethernet MAC Address registers */
ethernet_address(mac);
LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
txdscr_init(); /* initialize DMA TX Descriptor */
rxdscr_init(); /* initialize DMA RX Descriptor */
LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
/* Receive Broadcast, Perfect Match Packets */
LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */
LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */
LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */
LPC_EMAC->MAC1 |= MAC1_REC_EN;
#if NEW_LOGIC
rx_consume_offset = -1;
tx_produce_offset = -1;
#else
send_doff = 0;
send_idx = -1;
send_size = 0;
receive_soff = 0;
receive_idx = -1;
#endif
return 0;
}
/*----------------------------------------------------------------------------
Ethernet Device Uninitialize
*----------------------------------------------------------------------------*/
void ethernet_free() {
LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE);
LPC_EMAC->IntClear = 0xFFFF;
LPC_SC->PCONP &= ~0x40000000; /* Power down the EMAC controller. */
LPC_PINCON->PINSEL2 &= ~0x50150105; /* Disable P1 ethernet pins. */
LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000000;
}
// if(TxProduceIndex == TxConsumeIndex) buffer array is empty
// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
// TxConsumeIndex - The buffer that will/is beign sent by hardware
int ethernet_write(const char *data, int slen) {
#if NEW_LOGIC
if(tx_produce_offset < 0) { // mark as active if not already
tx_produce_offset = 0;
}
int index = LPC_EMAC->TxProduceIndex;
int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum
int requested = slen;
int ncopy = min(remaining, requested);
void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset);
void *psrc = (void *)(data);
if(ncopy > 0 ){
if(data != NULL) {
memcpy(pdst, psrc, ncopy);
} else {
memset(pdst, 0, ncopy);
}
}
tx_produce_offset += ncopy;
return ncopy;
#else
void *pdst, *psrc;
const int dlen = ETH_FRAG_SIZE;
int copy = 0;
int soff = 0;
if(send_idx == -1) {
send_idx = LPC_EMAC->TxProduceIndex;
}
if(slen + send_doff > ethernet_MTU_SIZE) {
return -1;
}
do {
copy = min(slen - soff, dlen - send_doff);
pdst = (void *)(txdesc[send_idx].Packet + send_doff);
psrc = (void *)(data + soff);
if(send_doff + copy > ETH_FRAG_SIZE) {
txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT);
send_idx = rinc(send_idx, NUM_TX_FRAG);
send_doff = 0;
}
if(data != NULL) {
memcpy(pdst, psrc, copy);
} else {
memset(pdst, 0, copy);
}
soff += copy;
send_doff += copy;
send_size += copy;
} while(soff != slen);
return soff;
#endif
}
int ethernet_send() {
#if NEW_LOGIC
if(tx_produce_offset < 0) { // no buffer active
return -1;
}
// ensure there is a link
if(!ethernet_link()) {
return -2;
}
// we have been writing in to a buffer, so finalise it
int size = tx_produce_offset;
int index = LPC_EMAC->TxProduceIndex;
txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST);
// Increment ProduceIndex to allow it to be sent
// We can only do this if the next slot is free
int next = rinc(index, NUM_TX_FRAG);
while(next == LPC_EMAC->TxConsumeIndex) {
for(int i=0; i<1000; i++) { __NOP(); }
}
LPC_EMAC->TxProduceIndex = next;
tx_produce_offset = -1;
return size;
#else
int s = send_size;
txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST);
send_idx = rinc(send_idx, NUM_TX_FRAG);
LPC_EMAC->TxProduceIndex = send_idx;
send_doff = 0;
send_idx = -1;
send_size = 0;
return s;
#endif
}
// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
//
// if(RxConsumeIndex == RxProduceIndex) buffer array is empty
// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
// Recevies an arrived ethernet packet.
// Receiving an ethernet packet will drop the last received ethernet packet
// and make a new ethernet packet ready to read.
// Returns size of packet, else 0 if nothing to receive
// We read from RxConsumeIndex from position rx_consume_offset
// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
// rx_consume_offset = -1 // no frame
// rx_consume_offset = 0 // start of frame
// Assumption: A fragment should alway be a whole frame
int ethernet_receive() {
#if NEW_LOGIC
// if we are currently reading a valid RxConsume buffer, increment to the next one
if(rx_consume_offset >= 0) {
LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG);
}
// if the buffer is empty, mark it as no valid buffer
if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) {
rx_consume_offset = -1;
return 0;
}
uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
rx_consume_offset = 0;
// check if it is not marked as last or for errors
if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) {
return -1;
}
int size = (info & RINFO_SIZE) + 1;
return size - 4; // don't include checksum bytes
#else
if(receive_idx == -1) {
receive_idx = LPC_EMAC->RxConsumeIndex;
} else {
while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && ((uint32_t)receive_idx != LPC_EMAC->RxProduceIndex)) {
receive_idx = rinc(receive_idx, NUM_RX_FRAG);
}
unsigned int info = rxstat[receive_idx].Info;
int slen = (info & RINFO_SIZE) + 1;
if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
/* Invalid frame, ignore it and free buffer. */
receive_idx = rinc(receive_idx, NUM_RX_FRAG);
}
receive_idx = rinc(receive_idx, NUM_RX_FRAG);
receive_soff = 0;
LPC_EMAC->RxConsumeIndex = receive_idx;
}
if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex) {
receive_idx = -1;
return 0;
}
return (rxstat[receive_idx].Info & RINFO_SIZE) - 3;
#endif
}
// Read from an recevied ethernet packet.
// After receive returnd a number bigger than 0 it is
// possible to read bytes from this packet.
// Read will write up to size bytes into data.
// It is possible to use read multible times.
// Each time read will start reading after the last read byte before.
int ethernet_read(char *data, int dlen) {
#if NEW_LOGIC
// Check we have a valid buffer to read
if(rx_consume_offset < 0) {
return 0;
}
// Assume 1 fragment block
uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum
int remaining = size - rx_consume_offset;
int requested = dlen;
int ncopy = min(remaining, requested);
void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset);
void *pdst = (void *)(data);
if(data != NULL && ncopy > 0) {
memcpy(pdst, psrc, ncopy);
}
rx_consume_offset += ncopy;
return ncopy;
#else
int slen;
int copy = 0;
unsigned int more;
unsigned int info;
void *pdst, *psrc;
int doff = 0;
if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) {
return 0;
}
do {
info = rxstat[receive_idx].Info;
more = !(info & RINFO_LAST_FLAG);
slen = (info & RINFO_SIZE) + 1;
if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
/* Invalid frame, ignore it and free buffer. */
receive_idx = rinc(receive_idx, NUM_RX_FRAG);
} else {
copy = min(slen - receive_soff, dlen - doff);
psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff);
pdst = (void *)(data + doff);
if(data != NULL) {
/* check if Buffer available */
memcpy(pdst, psrc, copy);
}
receive_soff += copy;
doff += copy;
if((more && (receive_soff == slen))) {
receive_idx = rinc(receive_idx, NUM_RX_FRAG);
receive_soff = 0;
}
}
} while(more && !(doff == dlen) && !receive_soff);
return doff;
#endif
}
int ethernet_link(void) {
if (phy_id == DP83848C_ID) {
return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
}
else { // LAN8720_ID
return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
}
}
static int phy_write(unsigned int PhyReg, unsigned short Data) {
unsigned int timeOut;
LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
LPC_EMAC->MWTD = Data;
for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) { /* Wait until operation completed */
if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
return 0;
}
}
return -1;
}
static int phy_read(unsigned int PhyReg) {
unsigned int timeOut;
LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
LPC_EMAC->MCMD = MCMD_READ;
for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */
if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
LPC_EMAC->MCMD = 0;
return LPC_EMAC->MRDD; /* Return a 16-bit value. */
}
}
return -1;
}
static void txdscr_init() {
int i;
for(i = 0; i < NUM_TX_FRAG; i++) {
txdesc[i].Packet = (uint32_t)&txbuf[i];
txdesc[i].Ctrl = 0;
txstat[i].Info = 0;
}
LPC_EMAC->TxDescriptor = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */
LPC_EMAC->TxStatus = (uint32_t)txstat;
LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
LPC_EMAC->TxProduceIndex = 0; /* Tx Descriptors Point to 0 */
}
static void rxdscr_init() {
int i;
for(i = 0; i < NUM_RX_FRAG; i++) {
rxdesc[i].Packet = (uint32_t)&rxbuf[i];
rxdesc[i].Ctrl = RCTRL_INT | (ETH_FRAG_SIZE-1);
rxstat[i].Info = 0;
rxstat[i].HashCRC = 0;
}
LPC_EMAC->RxDescriptor = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */
LPC_EMAC->RxStatus = (uint32_t)rxstat;
LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
LPC_EMAC->RxConsumeIndex = 0; /* Rx Descriptors Point to 0 */
}
void ethernet_address(char *mac) {
mbed_mac_address(mac);
}
void ethernet_set_link(int speed, int duplex) {
unsigned short phy_data;
int tout;
if((speed < 0) || (speed > 1)) {
phy_data = PHY_AUTO_NEG;
} else {
phy_data = (((unsigned short) speed << 13) |
((unsigned short) duplex << 8));
}
phy_write(PHY_REG_BMCR, phy_data);
for(tout = 100; tout; tout--) { __NOP(); } /* A short delay */
switch(phy_id) {
case DP83848C_ID:
phy_data = phy_read(PHY_REG_STS);
if(phy_data & PHY_STS_DUPLEX) {
LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
LPC_EMAC->Command |= CR_FULL_DUP;
LPC_EMAC->IPGT = IPGT_FULL_DUP;
} else {
LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP;
LPC_EMAC->Command &= ~CR_FULL_DUP;
LPC_EMAC->IPGT = IPGT_HALF_DUP;
}
if(phy_data & PHY_STS_SPEED) {
LPC_EMAC->SUPP &= ~SUPP_SPEED;
} else {
LPC_EMAC->SUPP |= SUPP_SPEED;
}
break;
case LAN8720_ID:
phy_data = phy_read(PHY_REG_SCSR);
if (phy_data & PHY_SCSR_DUPLEX) {
LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
LPC_EMAC->Command |= CR_FULL_DUP;
LPC_EMAC->IPGT = IPGT_FULL_DUP;
} else {
LPC_EMAC->Command &= ~CR_FULL_DUP;
LPC_EMAC->IPGT = IPGT_HALF_DUP;
}
if(phy_data & PHY_SCSR_100MBIT) {
LPC_EMAC->SUPP |= SUPP_SPEED;
} else {
LPC_EMAC->SUPP &= ~SUPP_SPEED;
}
break;
}
}

57
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "gpio_api.h"
#include "pinmap.h"
uint32_t gpio_set(PinName pin) {
LPC_SC->SCS |= 1; // High speed GPIO is enabled on ports 0 and 1
pin_function(pin, 0);
return (1 << ((int)pin & 0x1F));
}
void gpio_init(gpio_t *obj, PinName pin) {
if (pin == (PinName)NC)
return;
obj->pin = pin;
if (pin == (PinName)NC)
return;
obj->mask = gpio_set(pin);
LPC_GPIO_TypeDef *port_reg = (LPC_GPIO_TypeDef *) ((int)pin & ~0x1F);
obj->reg_set = &port_reg->FIOSET;
obj->reg_mask = &port_reg->FIOMASK;
obj->reg_clr = &port_reg->FIOCLR;
obj->reg_in = &port_reg->FIOPIN;
obj->reg_dir = &port_reg->FIODIR;
}
void gpio_mode(gpio_t *obj, PinMode mode) {
pin_mode(obj->pin, mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction) {
if (obj->pin == (PinName)NC)
return;
switch (direction) {
case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
}
}

154
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_irq_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_irq_api.h"
#include "mbed_error.h"
#include <stddef.h>
#include "cmsis.h"
#define CHANNEL_NUM 48
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler irq_handler;
static void handle_interrupt_in(void) {
// Read in all current interrupt registers. We do this once as the
// GPIO interrupt registers are on the APB bus, and this is slow.
uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
uint32_t mask0 = 0;
uint32_t mask2 = 0;
int i;
// P0.0-0.31
for (i = 0; i < 32; i++) {
uint32_t pmask = (1 << i);
if (rise0 & pmask) {
mask0 |= pmask;
if (channel_ids[i] != 0)
irq_handler(channel_ids[i], IRQ_RISE);
}
if (fall0 & pmask) {
mask0 |= pmask;
if (channel_ids[i] != 0)
irq_handler(channel_ids[i], IRQ_FALL);
}
}
// P2.0-2.15
for (i = 0; i < 16; i++) {
uint32_t pmask = (1 << i);
int channel_index = i + 32;
if (rise2 & pmask) {
mask2 |= pmask;
if (channel_ids[channel_index] != 0)
irq_handler(channel_ids[channel_index], IRQ_RISE);
}
if (fall2 & pmask) {
mask2 |= pmask;
if (channel_ids[channel_index] != 0)
irq_handler(channel_ids[channel_index], IRQ_FALL);
}
}
// Clear the interrupts we just handled
LPC_GPIOINT->IO0IntClr = mask0;
LPC_GPIOINT->IO2IntClr = mask2;
}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
if (pin == NC) return -1;
irq_handler = handler;
obj->port = (int)pin & ~0x1F;
obj->pin = (int)pin & 0x1F;
// Interrupts available only on GPIO0 and GPIO2
if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
error("pins on this port cannot generate interrupts");
}
// put us in the interrupt table
int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
channel_ids[index] = id;
obj->ch = index;
NVIC_SetVector(EINT3_IRQn, (uint32_t)handle_interrupt_in);
NVIC_EnableIRQ(EINT3_IRQn);
return 0;
}
void gpio_irq_free(gpio_irq_t *obj) {
channel_ids[obj->ch] = 0;
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
// ensure nothing is pending
switch (obj->port) {
case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
}
// enable the pin interrupt
if (event == IRQ_RISE) {
switch (obj->port) {
case LPC_GPIO0_BASE:
if (enable) {
LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
} else {
LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
}
break;
case LPC_GPIO2_BASE:
if (enable) {
LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
} else {
LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
}
break;
}
} else {
switch (obj->port) {
case LPC_GPIO0_BASE:
if (enable) {
LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
} else {
LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
}
break;
case LPC_GPIO2_BASE:
if (enable) {
LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
} else {
LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
}
break;
}
}
}
void gpio_irq_enable(gpio_irq_t *obj) {
NVIC_EnableIRQ(EINT3_IRQn);
}
void gpio_irq_disable(gpio_irq_t *obj) {
NVIC_DisableIRQ(EINT3_IRQn);
}

59
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_object.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#include "mbed_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pin;
uint32_t mask;
__IO uint32_t *reg_dir;
__IO uint32_t *reg_mask;
__IO uint32_t *reg_set;
__IO uint32_t *reg_clr;
__I uint32_t *reg_in;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value) {
MBED_ASSERT(obj->pin != (PinName)NC);
*obj->reg_mask &= ~obj->mask;
if (value)
*obj->reg_set = obj->mask;
else
*obj->reg_clr = obj->mask;
}
static inline int gpio_read(gpio_t *obj) {
MBED_ASSERT(obj->pin != (PinName)NC);
*obj->reg_mask &= ~obj->mask;
return ((*obj->reg_in & obj->mask) ? 1 : 0);
}
static inline int gpio_is_connected(const gpio_t *obj) {
return obj->pin != (PinName)NC;
}
#ifdef __cplusplus
}
#endif
#endif

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