mirror of https://github.com/ARMmbed/mbed-os.git
STM32H7 STM32Cube FW V1.5.0 => V1.7.0: CMSIS part
jeromecoutant
parent
7d181c1bf7
commit
21f262b5c3
File diff suppressed because it is too large
Load Diff
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@ -3075,6 +3075,7 @@ typedef struct
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#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */
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#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
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/******************** Bit definition for ADC_SQR1 register ********************/
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#define ADC_SQR1_L_Pos (0U)
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#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
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@ -3337,6 +3338,7 @@ typedef struct
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#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
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#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
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/******************** Bit definition for ADC_OFR2 register ********************/
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#define ADC_OFR2_OFFSET2_Pos (0U)
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#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
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@ -3381,6 +3383,7 @@ typedef struct
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#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
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#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
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/******************** Bit definition for ADC_OFR3 register ********************/
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#define ADC_OFR3_OFFSET3_Pos (0U)
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#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
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@ -3425,6 +3428,7 @@ typedef struct
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#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
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#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
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/******************** Bit definition for ADC_OFR4 register ********************/
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#define ADC_OFR4_OFFSET4_Pos (0U)
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#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
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@ -3469,6 +3473,7 @@ typedef struct
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#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
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#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
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/******************** Bit definition for ADC_JDR1 register ********************/
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#define ADC_JDR1_JDATA_Pos (0U)
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#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
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@ -8493,6 +8498,9 @@ typedef struct
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#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
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#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
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#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
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#define DMA_SxCR_TRBUFF_Pos (20U)
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#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
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#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
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#define DMA_SxCR_CT_Pos (19U)
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#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
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#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
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@ -9099,6 +9107,9 @@ typedef struct
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#define DMA2D_CR_ABORT_Pos (2U)
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#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
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#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
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#define DMA2D_CR_LOM_Pos (6U)
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#define DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos) /*!< 0x00000040 */
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#define DMA2D_CR_LOM DMA2D_CR_LOM_Msk /*!< Line Offset Mode */
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#define DMA2D_CR_TEIE_Pos (8U)
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#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
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#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
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@ -9118,10 +9129,11 @@ typedef struct
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#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
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#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
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#define DMA2D_CR_MODE_Pos (16U)
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#define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
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#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
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#define DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos) /*!< 0x00070000 */
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#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[2:0] */
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#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
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#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
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#define DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos) /*!< 0x00040000 */
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/******************** Bit definition for DMA2D_ISR register *****************/
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@ -9174,7 +9186,7 @@ typedef struct
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/******************** Bit definition for DMA2D_FGOR register ****************/
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#define DMA2D_FGOR_LO_Pos (0U)
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#define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
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#define DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x0000FFFF */
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#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
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/******************** Bit definition for DMA2D_BGMAR register ***************/
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@ -9186,7 +9198,7 @@ typedef struct
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/******************** Bit definition for DMA2D_BGOR register ****************/
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#define DMA2D_BGOR_LO_Pos (0U)
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#define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
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#define DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x0000FFFF */
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#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
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/******************** Bit definition for DMA2D_FGPFCCR register *************/
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@ -9304,6 +9316,9 @@ typedef struct
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#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
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#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
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#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
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#define DMA2D_OPFCCR_SB_Pos (8U)
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#define DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos) /*!< 0x00000100 */
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#define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk /*!< Swap Bytes */
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#define DMA2D_OPFCCR_AI_Pos (20U)
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#define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
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#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */
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@ -9315,27 +9330,57 @@ typedef struct
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/*!<Mode_ARGB8888/RGB888 */
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#define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FFU) /*!< Output BLUE Value */
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#define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00U) /*!< Output GREEN Value */
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#define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000U) /*!< Output Red Value */
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#define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000U) /*!< Output Alpha Channel Value */
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#define DMA2D_OCOLR_BLUE_1_Pos (0U)
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#define DMA2D_OCOLR_BLUE_1_Msk (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos) /*0x000000FFU*/
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#define DMA2D_OCOLR_BLUE_1 DMA2D_OCOLR_BLUE_1_Msk /*!< Output BLUE Value */
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#define DMA2D_OCOLR_GREEN_1_Pos (8U)
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#define DMA2D_OCOLR_GREEN_1_Msk (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos) /*0x0000FF00U)*/
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#define DMA2D_OCOLR_GREEN_1 DMA2D_OCOLR_GREEN_1_Msk /*!< Output GREEN Value */
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#define DMA2D_OCOLR_RED_1_Pos (16U)
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#define DMA2D_OCOLR_RED_1_Msk (0xFFUL << DMA2D_OCOLR_RED_1_Pos) /*0x00FF0000U */
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#define DMA2D_OCOLR_RED_1 DMA2D_OCOLR_RED_1_Msk /*!< Output Red Value */
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#define DMA2D_OCOLR_ALPHA_1_Pos (24U)
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#define DMA2D_OCOLR_ALPHA_1_Msk (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) /*0xFF000000U*/
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#define DMA2D_OCOLR_ALPHA_1 DMA2D_OCOLR_ALPHA_1_Msk /*!< Output Alpha Channel Value */
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/*!<Mode_RGB565 */
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#define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001FU) /*!< Output BLUE Value */
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#define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0U) /*!< Output GREEN Value */
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#define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800U) /*!< Output Red Value */
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#define DMA2D_OCOLR_BLUE_2_Pos (0U)
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#define DMA2D_OCOLR_BLUE_2_Msk (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos) /*0x0000001FU*/
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#define DMA2D_OCOLR_BLUE_2 DMA2D_OCOLR_BLUE_2_Msk /*!< Output BLUE Value */
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#define DMA2D_OCOLR_GREEN_2_Pos (5U)
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#define DMA2D_OCOLR_GREEN_2_Msk (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) /* 0x000007E0U */
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#define DMA2D_OCOLR_GREEN_2 DMA2D_OCOLR_GREEN_2_Msk /*!< Output GREEN Value */
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#define DMA2D_OCOLR_RED_2_Pos (11U)
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#define DMA2D_OCOLR_RED_2_Msk (0xF8UL<<DMA2D_OCOLR_RED_2_Pos) /*0x0000F800U*/
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#define DMA2D_OCOLR_RED_2 DMA2D_OCOLR_RED_2_Msk /*!< Output Red Value */
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/*!<Mode_ARGB1555 */
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#define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001FU) /*!< Output BLUE Value */
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#define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0U) /*!< Output GREEN Value */
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#define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00U) /*!< Output Red Value */
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#define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000U) /*!< Output Alpha Channel Value */
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#define DMA2D_OCOLR_BLUE_3_Pos (0U)
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#define DMA2D_OCOLR_BLUE_3_Msk (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) /*0x0000001FU*/
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#define DMA2D_OCOLR_BLUE_3 DMA2D_OCOLR_BLUE_3_Msk /*!< Output BLUE Value */
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#define DMA2D_OCOLR_GREEN_3_Pos (5U)
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#define DMA2D_OCOLR_GREEN_3_Msk (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) /*0x000003E0U*/
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#define DMA2D_OCOLR_GREEN_3 DMA2D_OCOLR_GREEN_3_Msk /*!< Output GREEN Value */
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#define DMA2D_OCOLR_RED_3_Pos (10U)
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#define DMA2D_OCOLR_RED_3_Msk (0x7CUL << DMA2D_OCOLR_RED_3_Pos) /* 0x00007C00U*/
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#define DMA2D_OCOLR_RED_3 DMA2D_OCOLR_RED_3_Msk /*!< Output Red Value */
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#define DMA2D_OCOLR_ALPHA_3_Pos (15U)
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#define DMA2D_OCOLR_ALPHA_3_Msk (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos) /*0x00008000U*/
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#define DMA2D_OCOLR_ALPHA_3 DMA2D_OCOLR_ALPHA_3_Msk /*!< Output Alpha Channel Value */
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/*!<Mode_ARGB4444 */
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#define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000FU) /*!< Output BLUE Value */
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#define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0U) /*!< Output GREEN Value */
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#define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00U) /*!< Output Red Value */
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#define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000U) /*!< Output Alpha Channel Value */
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#define DMA2D_OCOLR_BLUE_4_Pos (0U)
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#define DMA2D_OCOLR_BLUE_4_Msk (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) /*0x0000000FU*/
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#define DMA2D_OCOLR_BLUE_4 DMA2D_OCOLR_BLUE_4_Msk /*!< Output BLUE Value */
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#define DMA2D_OCOLR_GREEN_4_Pos (4U)
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#define DMA2D_OCOLR_GREEN_4_Msk (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) /*0x000000F0U*/
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#define DMA2D_OCOLR_GREEN_4 DMA2D_OCOLR_GREEN_4_Msk /*!< Output GREEN Value */
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#define DMA2D_OCOLR_RED_4_Pos (8U)
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#define DMA2D_OCOLR_RED_4_Msk (0xFUL << DMA2D_OCOLR_RED_4_Pos) /*0x00000F00U*/
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#define DMA2D_OCOLR_RED_4 DMA2D_OCOLR_RED_4_Msk /*!< Output Red Value */
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#define DMA2D_OCOLR_ALPHA_4_Pos (12U)
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#define DMA2D_OCOLR_ALPHA_4_Msk (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos) /*0x0000F000U*/
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#define DMA2D_OCOLR_ALPHA_4 DMA2D_OCOLR_ALPHA_4_Msk /*!< Output Alpha Channel Value */
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/******************** Bit definition for DMA2D_OMAR register ****************/
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@ -9346,7 +9391,7 @@ typedef struct
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/******************** Bit definition for DMA2D_OOR register *****************/
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#define DMA2D_OOR_LO_Pos (0U)
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#define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
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#define DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos) /*!< 0x0000FFFF */
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#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Output Line Offset */
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/******************** Bit definition for DMA2D_NLR register *****************/
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@ -10505,10 +10550,15 @@ typedef struct
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/* */
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/******************************************************************************/
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/*
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* @brief FLASH Total Sectors Number
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* @brief FLASH Global Defines
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*/
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#define FLASH_SECTOR_TOTAL 8U
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#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U
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#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
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#define FLASH_SIZE 0x200000UL /* 2 MB */
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#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
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#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
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#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
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#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
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#define DUAL_BANK /* Dual-bank Flash */
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/******************* Bits definition for FLASH_ACR register **********************/
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#define FLASH_ACR_LATENCY_Pos (0U)
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@ -13852,8 +13902,10 @@ typedef struct
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/* Power Control */
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/* */
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/******************************************************************************/
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/************************* NUMBER OF POWER DOMAINS **************************/
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#define POWER_DOMAINS_NUMBER 3U /*!< 3 Domains */
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/******************** Bit definition for PWR_CR1 register ********************/
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/******************** Bit definition for PWR_CR1 register *******************/
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#define PWR_CR1_ALS_Pos (17U)
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#define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) /*!< 0x00060000 */
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#define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */
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@ -13864,7 +13916,7 @@ typedef struct
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#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Analog Voltage Detector Enable */
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#define PWR_CR1_SVOS_Pos (14U)
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#define PWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos) /*!< 0x0000C000 */
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#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection. */
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#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection */
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#define PWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos) /*!< 0x00004000 */
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#define PWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos) /*!< 0x00008000 */
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#define PWR_CR1_FLPS_Pos (9U)
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@ -13881,7 +13933,7 @@ typedef struct
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#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */
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#define PWR_CR1_PVDEN_Pos (4U)
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#define PWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos) /*!< 0x00000010 */
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#define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk /*!< Programmable Voltage detector enable. */
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#define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk /*!< Programmable Voltage detector enable */
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#define PWR_CR1_LPDS_Pos (0U)
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#define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */
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#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low Power Deepsleep with SVOS3 */
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@ -13922,7 +13974,7 @@ typedef struct
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#define PWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos) /*!< 0x00060000 */
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#define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk /*!< AVD level 3 */
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/******************** Bit definition for PWR_CSR1 register ********************/
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/******************** Bit definition for PWR_CSR1 register ******************/
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#define PWR_CSR1_AVDO_Pos (16U)
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#define PWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos) /*!< 0x00010000 */
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#define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk /*!< Analog Voltage Detect Output */
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@ -13938,7 +13990,7 @@ typedef struct
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#define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos) /*!< 0x00000010 */
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#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< Programmable Voltage Detect Output */
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/******************** Bit definition for PWR_CR2 register ********************/
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/******************** Bit definition for PWR_CR2 register *******************/
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#define PWR_CR2_TEMPH_Pos (23U)
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#define PWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos) /*!< 0x00800000 */
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#define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk /*!< Monitored temperature level above high threshold */
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@ -13961,7 +14013,7 @@ typedef struct
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#define PWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos) /*!< 0x00000001 */
|
||||
#define PWR_CR2_BREN PWR_CR2_BREN_Msk /*!< Backup regulator enable */
|
||||
|
||||
/******************** Bit definition for PWR_CR3 register ********************/
|
||||
/******************** Bit definition for PWR_CR3 register *******************/
|
||||
#define PWR_CR3_USB33RDY_Pos (26U)
|
||||
#define PWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos) /*!< 0x04000000 */
|
||||
#define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk /*!< USB supply ready */
|
||||
|
|
@ -13987,7 +14039,7 @@ typedef struct
|
|||
#define PWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos) /*!< 0x00000001 */
|
||||
#define PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk /*!< Power Management Unit bypass */
|
||||
|
||||
/******************** Bit definition for PWR_CPUCR register ********************/
|
||||
/******************** Bit definition for PWR_CPUCR register *****************/
|
||||
#define PWR_CPUCR_RUN_D3_Pos (11U)
|
||||
#define PWR_CPUCR_RUN_D3_Msk (0x1UL << PWR_CPUCR_RUN_D3_Pos) /*!< 0x00000800 */
|
||||
#define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
|
||||
|
|
@ -14016,7 +14068,8 @@ typedef struct
|
|||
#define PWR_CPUCR_PDDS_D1_Msk (0x1UL << PWR_CPUCR_PDDS_D1_Pos) /*!< 0x00000001 */
|
||||
#define PWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk /*!< D1 domain Power Down Deepsleep selection */
|
||||
|
||||
/******************** Bit definition for PWR_D3CR register ********************/
|
||||
|
||||
/******************** Bit definition for PWR_D3CR register ******************/
|
||||
#define PWR_D3CR_VOS_Pos (14U)
|
||||
#define PWR_D3CR_VOS_Msk (0x3UL << PWR_D3CR_VOS_Pos) /*!< 0x0000C000 */
|
||||
#define PWR_D3CR_VOS PWR_D3CR_VOS_Msk /*!< Voltage Scaling selection according performance */
|
||||
|
|
@ -14026,7 +14079,7 @@ typedef struct
|
|||
#define PWR_D3CR_VOSRDY_Msk (0x1UL << PWR_D3CR_VOSRDY_Pos) /*!< 0x00002000 */
|
||||
#define PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY_Msk /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */
|
||||
|
||||
/******************** Bit definition for PWR_WKUPCR register ********************/
|
||||
/****************** Bit definition for PWR_WKUPCR register ******************/
|
||||
#define PWR_WKUPCR_WKUPC6_Pos (5U)
|
||||
#define PWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos) /*!< 0x00000020 */
|
||||
#define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk /*!< Clear Wakeup Pin Flag 6 */
|
||||
|
|
@ -14046,7 +14099,7 @@ typedef struct
|
|||
#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */
|
||||
#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */
|
||||
|
||||
/******************** Bit definition for PWR_WKUPFR register ********************/
|
||||
/******************** Bit definition for PWR_WKUPFR register ****************/
|
||||
#define PWR_WKUPFR_WKUPF6_Pos (5U)
|
||||
#define PWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos) /*!< 0x00000020 */
|
||||
#define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk /*!< Wakeup Pin Flag 6 */
|
||||
|
|
@ -14066,7 +14119,7 @@ typedef struct
|
|||
#define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */
|
||||
#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */
|
||||
|
||||
/******************** Bit definition for PWR_WKUPEPR register ********************/
|
||||
/****************** Bit definition for PWR_WKUPEPR register *****************/
|
||||
#define PWR_WKUPEPR_WKUPPUPD6_Pos (26U)
|
||||
#define PWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x0C000000 */
|
||||
#define PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk /*!< Wakeup Pin pull configuration for WKUP6 */
|
||||
|
|
@ -14142,6 +14195,9 @@ typedef struct
|
|||
/* Reset and Clock Control */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/******************************* RCC VERSION ********************************/
|
||||
#define RCC_VER_X
|
||||
|
||||
/******************** Bit definition for RCC_CR register ********************/
|
||||
#define RCC_CR_HSION_Pos (0U)
|
||||
#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -15109,28 +15165,32 @@ typedef struct
|
|||
#define RCC_AHB2ENR_DCMIEN_Pos (0U)
|
||||
#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
|
||||
#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
|
||||
#define RCC_AHB2ENR_CRYPEN_Pos (4U)
|
||||
#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
|
||||
#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
|
||||
#define RCC_AHB2ENR_HASHEN_Pos (5U)
|
||||
#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
|
||||
#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
|
||||
#define RCC_AHB2ENR_RNGEN_Pos (6U)
|
||||
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
|
||||
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
|
||||
#define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
|
||||
#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */
|
||||
#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
|
||||
#define RCC_AHB2ENR_D2SRAM1EN_Pos (29U)
|
||||
#define RCC_AHB2ENR_D2SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_D2SRAM1EN_Pos) /*!< 0x20000000 */
|
||||
#define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_D2SRAM1EN_Msk
|
||||
#define RCC_AHB2ENR_D2SRAM2EN_Pos (30U)
|
||||
#define RCC_AHB2ENR_D2SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_D2SRAM2EN_Pos) /*!< 0x40000000 */
|
||||
#define RCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_D2SRAM2EN_Msk
|
||||
#define RCC_AHB2ENR_D2SRAM3EN_Pos (31U)
|
||||
#define RCC_AHB2ENR_D2SRAM3EN_Msk (0x1UL << RCC_AHB2ENR_D2SRAM3EN_Pos) /*!< 0x80000000 */
|
||||
#define RCC_AHB2ENR_D2SRAM3EN RCC_AHB2ENR_D2SRAM3EN_Msk
|
||||
#define RCC_AHB2ENR_SRAM1EN_Pos (29U)
|
||||
#define RCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos) /*!< 0x20000000 */
|
||||
#define RCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk
|
||||
#define RCC_AHB2ENR_SRAM2EN_Pos (30U)
|
||||
#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */
|
||||
#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk
|
||||
#define RCC_AHB2ENR_SRAM3EN_Pos (31U)
|
||||
#define RCC_AHB2ENR_SRAM3EN_Msk (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos) /*!< 0x80000000 */
|
||||
#define RCC_AHB2ENR_SRAM3EN RCC_AHB2ENR_SRAM3EN_Msk
|
||||
|
||||
/* Legacy define */
|
||||
#define RCC_AHB2ENR_D2SRAM1EN_Pos RCC_AHB2ENR_SRAM1EN_Pos
|
||||
#define RCC_AHB2ENR_D2SRAM1EN_Msk RCC_AHB2ENR_SRAM1EN_Msk
|
||||
#define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_SRAM1EN
|
||||
#define RCC_AHB2ENR_D2SRAM2EN_Pos RCC_AHB2ENR_SRAM2EN_Pos
|
||||
#define RCC_AHB2ENR_D2SRAM2EN_Msk RCC_AHB2ENR_SRAM2EN_Msk
|
||||
#define RCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_SRAM2EN
|
||||
#define RCC_AHB2ENR_D2SRAM3EN_Pos RCC_AHB2ENR_SRAM3EN_Pos
|
||||
#define RCC_AHB2ENR_D2SRAM3EN_Msk RCC_AHB2ENR_SRAM3EN_Msk
|
||||
#define RCC_AHB2ENR_D2SRAM3EN RCC_AHB2ENR_SRAM3EN
|
||||
|
||||
/******************** Bit definition for RCC_AHB4ENR register ******************/
|
||||
#define RCC_AHB4ENR_GPIOAEN_Pos (0U)
|
||||
|
|
@ -15181,9 +15241,6 @@ typedef struct
|
|||
#define RCC_AHB4ENR_BKPRAMEN_Pos (28U)
|
||||
#define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) /*!< 0x10000000 */
|
||||
#define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk
|
||||
#define RCC_AHB4ENR_D3SRAM1EN_Pos (29U)
|
||||
#define RCC_AHB4ENR_D3SRAM1EN_Msk (0x1UL << RCC_AHB4ENR_D3SRAM1EN_Pos) /*!< 0x20000000 */
|
||||
#define RCC_AHB4ENR_D3SRAM1EN RCC_AHB4ENR_D3SRAM1EN_Msk
|
||||
|
||||
/******************** Bit definition for RCC_APB3ENR register ******************/
|
||||
#define RCC_APB3ENR_LTDCEN_Pos (3U)
|
||||
|
|
@ -15270,6 +15327,10 @@ typedef struct
|
|||
#define RCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */
|
||||
#define RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk
|
||||
|
||||
/* Legacy define */
|
||||
#define RCC_APB1LENR_HDMICECEN_Pos RCC_APB1LENR_CECEN_Pos
|
||||
#define RCC_APB1LENR_HDMICECEN_Msk RCC_APB1LENR_CECEN_Msk
|
||||
#define RCC_APB1LENR_HDMICECEN RCC_APB1LENR_CECEN
|
||||
/******************** Bit definition for RCC_APB1HENR register ******************/
|
||||
#define RCC_APB1HENR_CRSEN_Pos (1U)
|
||||
#define RCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */
|
||||
|
|
@ -15423,12 +15484,6 @@ typedef struct
|
|||
#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
|
||||
#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
|
||||
#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
|
||||
#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
|
||||
#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
|
||||
#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
|
||||
#define RCC_AHB2RSTR_HASHRST_Pos (5U)
|
||||
#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
|
||||
#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
|
||||
#define RCC_AHB2RSTR_RNGRST_Pos (6U)
|
||||
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
|
||||
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
|
||||
|
|
@ -15564,6 +15619,10 @@ typedef struct
|
|||
#define RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */
|
||||
#define RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk
|
||||
|
||||
/* Legacy define */
|
||||
#define RCC_APB1LRSTR_HDMICECRST_Pos RCC_APB1LRSTR_CECRST_Pos
|
||||
#define RCC_APB1LRSTR_HDMICECRST_Msk RCC_APB1LRSTR_CECRST_Msk
|
||||
#define RCC_APB1LRSTR_HDMICECRST RCC_APB1LRSTR_CECRST
|
||||
/******************** Bit definition for RCC_APB1HRSTR register ******************/
|
||||
#define RCC_APB1HRSTR_CRSRST_Pos (1U)
|
||||
#define RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */
|
||||
|
|
@ -15800,28 +15859,32 @@ typedef struct
|
|||
#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
|
||||
#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
|
||||
#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
|
||||
#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
|
||||
#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
|
||||
#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
|
||||
#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
|
||||
#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
|
||||
#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
|
||||
#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
|
||||
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
|
||||
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
|
||||
#define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U)
|
||||
#define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
|
||||
#define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk
|
||||
#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos (30U)
|
||||
#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_D2SRAM1LPEN_Pos) /*!< 0x40000000 */
|
||||
#define RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_D2SRAM1LPEN_Msk
|
||||
#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos (30U)
|
||||
#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_D2SRAM2LPEN_Pos) /*!< 0x40000000 */
|
||||
#define RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_D2SRAM2LPEN_Msk
|
||||
#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos (31U)
|
||||
#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk (0x1UL << RCC_AHB2LPENR_D2SRAM3LPEN_Pos) /*!< 0x80000000 */
|
||||
#define RCC_AHB2LPENR_D2SRAM3LPEN RCC_AHB2LPENR_D2SRAM3LPEN_Msk
|
||||
#define RCC_AHB2LPENR_SRAM1LPEN_Pos (29U)
|
||||
#define RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */
|
||||
#define RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk
|
||||
#define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U)
|
||||
#define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */
|
||||
#define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk
|
||||
#define RCC_AHB2LPENR_SRAM3LPEN_Pos (31U)
|
||||
#define RCC_AHB2LPENR_SRAM3LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */
|
||||
#define RCC_AHB2LPENR_SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN_Msk
|
||||
|
||||
/* Legacy define */
|
||||
#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos RCC_AHB2LPENR_SRAM1LPEN_Pos
|
||||
#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk RCC_AHB2LPENR_SRAM1LPEN_Msk
|
||||
#define RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN
|
||||
#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos RCC_AHB2LPENR_SRAM2LPEN_Pos
|
||||
#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk RCC_AHB2LPENR_SRAM2LPEN_Msk
|
||||
#define RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN
|
||||
#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos RCC_AHB2LPENR_SRAM3LPEN_Pos
|
||||
#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk RCC_AHB2LPENR_SRAM3LPEN_Msk
|
||||
#define RCC_AHB2LPENR_D2SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN
|
||||
|
||||
/******************** Bit definition for RCC_AHB4LPENR register ******************/
|
||||
#define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)
|
||||
|
|
@ -15869,10 +15932,14 @@ typedef struct
|
|||
#define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U)
|
||||
#define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
|
||||
#define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk
|
||||
#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos (29U)
|
||||
#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk (0x1UL << RCC_AHB4LPENR_D3SRAM1LPEN_Pos) /*!< 0x20000000 */
|
||||
#define RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_D3SRAM1LPEN_Msk
|
||||
#define RCC_AHB4LPENR_SRAM4LPEN_Pos (29U)
|
||||
#define RCC_AHB4LPENR_SRAM4LPEN_Msk (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */
|
||||
#define RCC_AHB4LPENR_SRAM4LPEN RCC_AHB4LPENR_SRAM4LPEN_Msk
|
||||
|
||||
/* Legacy define */
|
||||
#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos RCC_AHB4LPENR_SRAM4LPEN_Pos
|
||||
#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk RCC_AHB4LPENR_SRAM4LPEN_Msk
|
||||
#define RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_SRAM4LPEN
|
||||
/******************** Bit definition for RCC_APB3LPENR register ******************/
|
||||
#define RCC_APB3LPENR_LTDCLPEN_Pos (3U)
|
||||
#define RCC_APB3LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */
|
||||
|
|
@ -15958,6 +16025,10 @@ typedef struct
|
|||
#define RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */
|
||||
#define RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk
|
||||
|
||||
/* Legacy define */
|
||||
#define RCC_APB1LLPENR_HDMICECEN_Pos RCC_APB1LLPENR_CECLPEN_Pos
|
||||
#define RCC_APB1LLPENR_HDMICECEN_Msk RCC_APB1LLPENR_CECLPEN_Msk
|
||||
#define RCC_APB1LLPENR_HDMICECEN RCC_APB1LLPENR_CECLPEN
|
||||
/******************** Bit definition for RCC_APB1HLPENR register ******************/
|
||||
#define RCC_APB1HLPENR_CRSLPEN_Pos (1U)
|
||||
#define RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */
|
||||
|
|
@ -19091,7 +19162,6 @@ typedef struct
|
|||
/* */
|
||||
/******************************************************************************/
|
||||
#define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature */
|
||||
#define TIM17_TI1_SPDIF_FS_SUPPORT /*!< TIM17 Trigger input 1 to SPDIF FS connection feature */
|
||||
|
||||
/******************* Bit definition for TIM_CR1 register ********************/
|
||||
#define TIM_CR1_CEN_Pos (0U)
|
||||
|
|
@ -20932,6 +21002,8 @@ typedef struct
|
|||
/* DBG */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/********************************* DEVICE ID ********************************/
|
||||
#define STM32H7_DEV_ID 0x450UL
|
||||
|
||||
/******************** Bit definition for DBGMCU_IDCODE register *************/
|
||||
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
|
||||
|
|
@ -24097,10 +24169,11 @@ typedef struct
|
|||
#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
|
||||
#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
|
||||
#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
|
||||
|
|
@ -24275,6 +24348,9 @@ typedef struct
|
|||
#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
|
||||
#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
|
||||
#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
|
||||
#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */
|
||||
#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
|
||||
#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
|
||||
#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
|
||||
|
|
@ -24293,6 +24369,15 @@ typedef struct
|
|||
#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
|
||||
#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
|
||||
#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
|
||||
#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
|
||||
#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
|
||||
#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */
|
||||
#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
|
||||
#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
|
||||
#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */
|
||||
#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
|
||||
#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
|
||||
#define USB_OTG_GINTSTS_CMOD_Pos (0U)
|
||||
|
|
@ -25056,12 +25141,18 @@ typedef struct
|
|||
#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
|
||||
#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
|
||||
#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
|
||||
#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */
|
||||
#define USB_OTG_DIEPINT_TOC_Pos (3U)
|
||||
#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
|
||||
#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
|
||||
#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
|
||||
#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
|
||||
#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
|
||||
#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */
|
||||
#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
|
||||
#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
|
||||
#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
|
||||
|
|
@ -25217,6 +25308,9 @@ typedef struct
|
|||
#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
|
||||
#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
|
||||
#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
|
||||
#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */
|
||||
#define USB_OTG_DOEPINT_STUP_Pos (3U)
|
||||
#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
|
||||
#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
|
||||
|
|
@ -25229,9 +25323,21 @@ typedef struct
|
|||
#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
|
||||
#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
|
||||
#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
|
||||
#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
|
||||
#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
|
||||
#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */
|
||||
#define USB_OTG_DOEPINT_BERR_Pos (12U)
|
||||
#define USB_OTG_DOEPINT_BERR_Msk (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
|
||||
#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */
|
||||
#define USB_OTG_DOEPINT_NAK_Pos (13U)
|
||||
#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
|
||||
#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */
|
||||
#define USB_OTG_DOEPINT_NYET_Pos (14U)
|
||||
#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
|
||||
#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
|
||||
#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
|
||||
|
||||
|
|
@ -25509,6 +25615,7 @@ typedef struct
|
|||
/******************************** HSEM Instances *******************************/
|
||||
#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
|
||||
#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */
|
||||
#define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
|
||||
#define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
|
||||
|
||||
#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/
|
||||
|
|
@ -25595,6 +25702,7 @@ typedef struct
|
|||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/************* TIM Instances : at least 1 capture/compare channel *************/
|
||||
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
|
|
@ -25608,6 +25716,7 @@ typedef struct
|
|||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/************ TIM Instances : at least 2 capture/compare channels *************/
|
||||
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
|
|
@ -25617,6 +25726,7 @@ typedef struct
|
|||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/************ TIM Instances : at least 3 capture/compare channels *************/
|
||||
#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
|
|
@ -25632,6 +25742,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
||||
/************ TIM Instances : at least 5 capture/compare channels *************/
|
||||
#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
|
@ -25702,13 +25813,15 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
||||
/****************** TIM Instances : remapping capability **********************/
|
||||
#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
||||
((__INSTANCE__) == TIM2) || \
|
||||
((__INSTANCE__) == TIM3) || \
|
||||
((__INSTANCE__) == TIM5) || \
|
||||
((__INSTANCE__) == TIM16) || \
|
||||
((__INSTANCE__) == TIM17))
|
||||
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/*************** TIM Instances : external trigger reamp input available *******/
|
||||
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -25727,6 +25840,7 @@ typedef struct
|
|||
((INSTANCE) == TIM7) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
|
||||
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
|
|
@ -25888,6 +26002,7 @@ typedef struct
|
|||
((__INSTANCE__) == TIM3) || \
|
||||
((__INSTANCE__) == TIM4) || \
|
||||
((__INSTANCE__) == TIM5) || \
|
||||
((__INSTANCE__) == TIM6) || \
|
||||
((__INSTANCE__) == TIM8) || \
|
||||
((__INSTANCE__) == TIM12) || \
|
||||
((__INSTANCE__) == TIM15))
|
||||
|
|
@ -25903,6 +26018,7 @@ typedef struct
|
|||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
|
||||
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
|
|
@ -25920,6 +26036,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
||||
/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
|
||||
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
|
|
@ -25945,6 +26062,7 @@ typedef struct
|
|||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
|
||||
/****************** TIM Instances : TIM_32B_COUNTER ***************************/
|
||||
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM2) || \
|
||||
|
|
@ -26138,6 +26256,7 @@ typedef struct
|
|||
#define PVD_IRQn PVD_AVD_IRQn
|
||||
|
||||
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define HASH_RNG_IRQHandler RNG_IRQHandler
|
||||
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
|
|
@ -26145,16 +26264,12 @@ typedef struct
|
|||
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define PVD_IRQHandler PVD_AVD_IRQHandler
|
||||
|
||||
/* Aliases for COMP __IRQHandler */
|
||||
#define COMP_IRQHandler COMP1_IRQHandler
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/****************************** Product define *********************************/
|
||||
#define FLASH_SIZE 0x200000UL /* 2 MB */
|
||||
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
|
||||
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
|
||||
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -3248,6 +3248,7 @@ typedef struct
|
|||
#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */
|
||||
#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
|
||||
|
||||
|
||||
/******************** Bit definition for ADC_SQR1 register ********************/
|
||||
#define ADC_SQR1_L_Pos (0U)
|
||||
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
|
||||
|
|
@ -3510,6 +3511,7 @@ typedef struct
|
|||
#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
|
||||
#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
|
||||
|
||||
|
||||
/******************** Bit definition for ADC_OFR2 register ********************/
|
||||
#define ADC_OFR2_OFFSET2_Pos (0U)
|
||||
#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
|
||||
|
|
@ -3554,6 +3556,7 @@ typedef struct
|
|||
#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
|
||||
#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
|
||||
|
||||
|
||||
/******************** Bit definition for ADC_OFR3 register ********************/
|
||||
#define ADC_OFR3_OFFSET3_Pos (0U)
|
||||
#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
|
||||
|
|
@ -3598,6 +3601,7 @@ typedef struct
|
|||
#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
|
||||
#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
|
||||
|
||||
|
||||
/******************** Bit definition for ADC_OFR4 register ********************/
|
||||
#define ADC_OFR4_OFFSET4_Pos (0U)
|
||||
#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
|
||||
|
|
@ -3642,6 +3646,7 @@ typedef struct
|
|||
#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
|
||||
#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
|
||||
|
||||
|
||||
/******************** Bit definition for ADC_JDR1 register ********************/
|
||||
#define ADC_JDR1_JDATA_Pos (0U)
|
||||
#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
|
||||
|
|
@ -8679,6 +8684,9 @@ typedef struct
|
|||
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
|
||||
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
|
||||
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
|
||||
#define DMA_SxCR_TRBUFF_Pos (20U)
|
||||
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
|
||||
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
|
||||
#define DMA_SxCR_CT_Pos (19U)
|
||||
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
|
||||
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
|
||||
|
|
@ -9285,6 +9293,9 @@ typedef struct
|
|||
#define DMA2D_CR_ABORT_Pos (2U)
|
||||
#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
|
||||
#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
|
||||
#define DMA2D_CR_LOM_Pos (6U)
|
||||
#define DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos) /*!< 0x00000040 */
|
||||
#define DMA2D_CR_LOM DMA2D_CR_LOM_Msk /*!< Line Offset Mode */
|
||||
#define DMA2D_CR_TEIE_Pos (8U)
|
||||
#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
|
||||
#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
|
||||
|
|
@ -9304,10 +9315,11 @@ typedef struct
|
|||
#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
|
||||
#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
|
||||
#define DMA2D_CR_MODE_Pos (16U)
|
||||
#define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
|
||||
#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
|
||||
#define DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos) /*!< 0x00070000 */
|
||||
#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[2:0] */
|
||||
#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
|
||||
#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
|
||||
#define DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos) /*!< 0x00040000 */
|
||||
|
||||
/******************** Bit definition for DMA2D_ISR register *****************/
|
||||
|
||||
|
|
@ -9360,7 +9372,7 @@ typedef struct
|
|||
/******************** Bit definition for DMA2D_FGOR register ****************/
|
||||
|
||||
#define DMA2D_FGOR_LO_Pos (0U)
|
||||
#define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
|
||||
#define DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x0000FFFF */
|
||||
#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
|
||||
|
||||
/******************** Bit definition for DMA2D_BGMAR register ***************/
|
||||
|
|
@ -9372,7 +9384,7 @@ typedef struct
|
|||
/******************** Bit definition for DMA2D_BGOR register ****************/
|
||||
|
||||
#define DMA2D_BGOR_LO_Pos (0U)
|
||||
#define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
|
||||
#define DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x0000FFFF */
|
||||
#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
|
||||
|
||||
/******************** Bit definition for DMA2D_FGPFCCR register *************/
|
||||
|
|
@ -9490,6 +9502,9 @@ typedef struct
|
|||
#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
|
||||
#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
|
||||
#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
|
||||
#define DMA2D_OPFCCR_SB_Pos (8U)
|
||||
#define DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos) /*!< 0x00000100 */
|
||||
#define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk /*!< Swap Bytes */
|
||||
#define DMA2D_OPFCCR_AI_Pos (20U)
|
||||
#define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
|
||||
#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */
|
||||
|
|
@ -9501,27 +9516,57 @@ typedef struct
|
|||
|
||||
/*!<Mode_ARGB8888/RGB888 */
|
||||
|
||||
#define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FFU) /*!< Output BLUE Value */
|
||||
#define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00U) /*!< Output GREEN Value */
|
||||
#define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000U) /*!< Output Red Value */
|
||||
#define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000U) /*!< Output Alpha Channel Value */
|
||||
#define DMA2D_OCOLR_BLUE_1_Pos (0U)
|
||||
#define DMA2D_OCOLR_BLUE_1_Msk (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos) /*0x000000FFU*/
|
||||
#define DMA2D_OCOLR_BLUE_1 DMA2D_OCOLR_BLUE_1_Msk /*!< Output BLUE Value */
|
||||
#define DMA2D_OCOLR_GREEN_1_Pos (8U)
|
||||
#define DMA2D_OCOLR_GREEN_1_Msk (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos) /*0x0000FF00U)*/
|
||||
#define DMA2D_OCOLR_GREEN_1 DMA2D_OCOLR_GREEN_1_Msk /*!< Output GREEN Value */
|
||||
#define DMA2D_OCOLR_RED_1_Pos (16U)
|
||||
#define DMA2D_OCOLR_RED_1_Msk (0xFFUL << DMA2D_OCOLR_RED_1_Pos) /*0x00FF0000U */
|
||||
#define DMA2D_OCOLR_RED_1 DMA2D_OCOLR_RED_1_Msk /*!< Output Red Value */
|
||||
#define DMA2D_OCOLR_ALPHA_1_Pos (24U)
|
||||
#define DMA2D_OCOLR_ALPHA_1_Msk (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) /*0xFF000000U*/
|
||||
#define DMA2D_OCOLR_ALPHA_1 DMA2D_OCOLR_ALPHA_1_Msk /*!< Output Alpha Channel Value */
|
||||
|
||||
/*!<Mode_RGB565 */
|
||||
#define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001FU) /*!< Output BLUE Value */
|
||||
#define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0U) /*!< Output GREEN Value */
|
||||
#define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800U) /*!< Output Red Value */
|
||||
#define DMA2D_OCOLR_BLUE_2_Pos (0U)
|
||||
#define DMA2D_OCOLR_BLUE_2_Msk (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos) /*0x0000001FU*/
|
||||
#define DMA2D_OCOLR_BLUE_2 DMA2D_OCOLR_BLUE_2_Msk /*!< Output BLUE Value */
|
||||
#define DMA2D_OCOLR_GREEN_2_Pos (5U)
|
||||
#define DMA2D_OCOLR_GREEN_2_Msk (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) /* 0x000007E0U */
|
||||
#define DMA2D_OCOLR_GREEN_2 DMA2D_OCOLR_GREEN_2_Msk /*!< Output GREEN Value */
|
||||
#define DMA2D_OCOLR_RED_2_Pos (11U)
|
||||
#define DMA2D_OCOLR_RED_2_Msk (0xF8UL<<DMA2D_OCOLR_RED_2_Pos) /*0x0000F800U*/
|
||||
#define DMA2D_OCOLR_RED_2 DMA2D_OCOLR_RED_2_Msk /*!< Output Red Value */
|
||||
|
||||
/*!<Mode_ARGB1555 */
|
||||
#define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001FU) /*!< Output BLUE Value */
|
||||
#define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0U) /*!< Output GREEN Value */
|
||||
#define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00U) /*!< Output Red Value */
|
||||
#define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000U) /*!< Output Alpha Channel Value */
|
||||
#define DMA2D_OCOLR_BLUE_3_Pos (0U)
|
||||
#define DMA2D_OCOLR_BLUE_3_Msk (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) /*0x0000001FU*/
|
||||
#define DMA2D_OCOLR_BLUE_3 DMA2D_OCOLR_BLUE_3_Msk /*!< Output BLUE Value */
|
||||
#define DMA2D_OCOLR_GREEN_3_Pos (5U)
|
||||
#define DMA2D_OCOLR_GREEN_3_Msk (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) /*0x000003E0U*/
|
||||
#define DMA2D_OCOLR_GREEN_3 DMA2D_OCOLR_GREEN_3_Msk /*!< Output GREEN Value */
|
||||
#define DMA2D_OCOLR_RED_3_Pos (10U)
|
||||
#define DMA2D_OCOLR_RED_3_Msk (0x7CUL << DMA2D_OCOLR_RED_3_Pos) /* 0x00007C00U*/
|
||||
#define DMA2D_OCOLR_RED_3 DMA2D_OCOLR_RED_3_Msk /*!< Output Red Value */
|
||||
#define DMA2D_OCOLR_ALPHA_3_Pos (15U)
|
||||
#define DMA2D_OCOLR_ALPHA_3_Msk (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos) /*0x00008000U*/
|
||||
#define DMA2D_OCOLR_ALPHA_3 DMA2D_OCOLR_ALPHA_3_Msk /*!< Output Alpha Channel Value */
|
||||
|
||||
/*!<Mode_ARGB4444 */
|
||||
#define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000FU) /*!< Output BLUE Value */
|
||||
#define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0U) /*!< Output GREEN Value */
|
||||
#define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00U) /*!< Output Red Value */
|
||||
#define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000U) /*!< Output Alpha Channel Value */
|
||||
#define DMA2D_OCOLR_BLUE_4_Pos (0U)
|
||||
#define DMA2D_OCOLR_BLUE_4_Msk (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) /*0x0000000FU*/
|
||||
#define DMA2D_OCOLR_BLUE_4 DMA2D_OCOLR_BLUE_4_Msk /*!< Output BLUE Value */
|
||||
#define DMA2D_OCOLR_GREEN_4_Pos (4U)
|
||||
#define DMA2D_OCOLR_GREEN_4_Msk (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) /*0x000000F0U*/
|
||||
#define DMA2D_OCOLR_GREEN_4 DMA2D_OCOLR_GREEN_4_Msk /*!< Output GREEN Value */
|
||||
#define DMA2D_OCOLR_RED_4_Pos (8U)
|
||||
#define DMA2D_OCOLR_RED_4_Msk (0xFUL << DMA2D_OCOLR_RED_4_Pos) /*0x00000F00U*/
|
||||
#define DMA2D_OCOLR_RED_4 DMA2D_OCOLR_RED_4_Msk /*!< Output Red Value */
|
||||
#define DMA2D_OCOLR_ALPHA_4_Pos (12U)
|
||||
#define DMA2D_OCOLR_ALPHA_4_Msk (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos) /*0x0000F000U*/
|
||||
#define DMA2D_OCOLR_ALPHA_4 DMA2D_OCOLR_ALPHA_4_Msk /*!< Output Alpha Channel Value */
|
||||
|
||||
/******************** Bit definition for DMA2D_OMAR register ****************/
|
||||
|
||||
|
|
@ -9532,7 +9577,7 @@ typedef struct
|
|||
/******************** Bit definition for DMA2D_OOR register *****************/
|
||||
|
||||
#define DMA2D_OOR_LO_Pos (0U)
|
||||
#define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
|
||||
#define DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos) /*!< 0x0000FFFF */
|
||||
#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Output Line Offset */
|
||||
|
||||
/******************** Bit definition for DMA2D_NLR register *****************/
|
||||
|
|
@ -13765,10 +13810,15 @@ typedef struct
|
|||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief FLASH Total Sectors Number
|
||||
* @brief FLASH Global Defines
|
||||
*/
|
||||
#define FLASH_SECTOR_TOTAL 8U
|
||||
#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U
|
||||
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
|
||||
#define FLASH_SIZE 0x200000UL /* 2 MB */
|
||||
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
|
||||
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
|
||||
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
|
||||
#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
|
||||
#define DUAL_BANK /* Dual-bank Flash */
|
||||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
|
|
@ -17525,8 +17575,10 @@ typedef struct
|
|||
/* Power Control */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/************************* NUMBER OF POWER DOMAINS **************************/
|
||||
#define POWER_DOMAINS_NUMBER 3U /*!< 3 Domains */
|
||||
|
||||
/******************** Bit definition for PWR_CR1 register ********************/
|
||||
/******************** Bit definition for PWR_CR1 register *******************/
|
||||
#define PWR_CR1_ALS_Pos (17U)
|
||||
#define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) /*!< 0x00060000 */
|
||||
#define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */
|
||||
|
|
@ -17537,7 +17589,7 @@ typedef struct
|
|||
#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Analog Voltage Detector Enable */
|
||||
#define PWR_CR1_SVOS_Pos (14U)
|
||||
#define PWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos) /*!< 0x0000C000 */
|
||||
#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection. */
|
||||
#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection */
|
||||
#define PWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos) /*!< 0x00004000 */
|
||||
#define PWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR1_FLPS_Pos (9U)
|
||||
|
|
@ -17554,7 +17606,7 @@ typedef struct
|
|||
#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */
|
||||
#define PWR_CR1_PVDEN_Pos (4U)
|
||||
#define PWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos) /*!< 0x00000010 */
|
||||
#define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk /*!< Programmable Voltage detector enable. */
|
||||
#define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk /*!< Programmable Voltage detector enable */
|
||||
#define PWR_CR1_LPDS_Pos (0U)
|
||||
#define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */
|
||||
#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low Power Deepsleep with SVOS3 */
|
||||
|
|
@ -17595,7 +17647,7 @@ typedef struct
|
|||
#define PWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos) /*!< 0x00060000 */
|
||||
#define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk /*!< AVD level 3 */
|
||||
|
||||
/******************** Bit definition for PWR_CSR1 register ********************/
|
||||
/******************** Bit definition for PWR_CSR1 register ******************/
|
||||
#define PWR_CSR1_AVDO_Pos (16U)
|
||||
#define PWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos) /*!< 0x00010000 */
|
||||
#define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk /*!< Analog Voltage Detect Output */
|
||||
|
|
@ -17611,7 +17663,7 @@ typedef struct
|
|||
#define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos) /*!< 0x00000010 */
|
||||
#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< Programmable Voltage Detect Output */
|
||||
|
||||
/******************** Bit definition for PWR_CR2 register ********************/
|
||||
/******************** Bit definition for PWR_CR2 register *******************/
|
||||
#define PWR_CR2_TEMPH_Pos (23U)
|
||||
#define PWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos) /*!< 0x00800000 */
|
||||
#define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk /*!< Monitored temperature level above high threshold */
|
||||
|
|
@ -17634,7 +17686,7 @@ typedef struct
|
|||
#define PWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos) /*!< 0x00000001 */
|
||||
#define PWR_CR2_BREN PWR_CR2_BREN_Msk /*!< Backup regulator enable */
|
||||
|
||||
/******************** Bit definition for PWR_CR3 register ********************/
|
||||
/******************** Bit definition for PWR_CR3 register *******************/
|
||||
#define PWR_CR3_USB33RDY_Pos (26U)
|
||||
#define PWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos) /*!< 0x04000000 */
|
||||
#define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk /*!< USB supply ready */
|
||||
|
|
@ -17671,7 +17723,7 @@ typedef struct
|
|||
#define PWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos) /*!< 0x00000001 */
|
||||
#define PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk /*!< Power Management Unit bypass */
|
||||
|
||||
/******************** Bit definition for PWR_CPUCR register ********************/
|
||||
/******************** Bit definition for PWR_CPUCR register *****************/
|
||||
#define PWR_CPUCR_RUN_D3_Pos (11U)
|
||||
#define PWR_CPUCR_RUN_D3_Msk (0x1UL << PWR_CPUCR_RUN_D3_Pos) /*!< 0x00000800 */
|
||||
#define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
|
||||
|
|
@ -17706,7 +17758,7 @@ typedef struct
|
|||
#define PWR_CPUCR_PDDS_D1_Msk (0x1UL << PWR_CPUCR_PDDS_D1_Pos) /*!< 0x00000001 */
|
||||
#define PWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk /*!< D1 domain Power Down Deepsleep selection */
|
||||
|
||||
/******************** Bit definition for PWR_CPU2CR register ********************/
|
||||
/******************** Bit definition for PWR_CPU2CR register ****************/
|
||||
#define PWR_CPU2CR_RUN_D3_Pos (11U)
|
||||
#define PWR_CPU2CR_RUN_D3_Msk (0x1UL << PWR_CPU2CR_RUN_D3_Pos) /*!< 0x00000800 */
|
||||
#define PWR_CPU2CR_RUN_D3 PWR_CPU2CR_RUN_D3_Msk /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
|
||||
|
|
@ -17741,7 +17793,8 @@ typedef struct
|
|||
#define PWR_CPU2CR_PDDS_D1_Msk (0x1UL << PWR_CPU2CR_PDDS_D1_Pos) /*!< 0x00000001 */
|
||||
#define PWR_CPU2CR_PDDS_D1 PWR_CPU2CR_PDDS_D1_Msk /*!< D1 domain Power Down Deepsleep selection */
|
||||
|
||||
/******************** Bit definition for PWR_D3CR register ********************/
|
||||
|
||||
/******************** Bit definition for PWR_D3CR register ******************/
|
||||
#define PWR_D3CR_VOS_Pos (14U)
|
||||
#define PWR_D3CR_VOS_Msk (0x3UL << PWR_D3CR_VOS_Pos) /*!< 0x0000C000 */
|
||||
#define PWR_D3CR_VOS PWR_D3CR_VOS_Msk /*!< Voltage Scaling selection according performance */
|
||||
|
|
@ -17751,7 +17804,7 @@ typedef struct
|
|||
#define PWR_D3CR_VOSRDY_Msk (0x1UL << PWR_D3CR_VOSRDY_Pos) /*!< 0x00002000 */
|
||||
#define PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY_Msk /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */
|
||||
|
||||
/******************** Bit definition for PWR_WKUPCR register ********************/
|
||||
/****************** Bit definition for PWR_WKUPCR register ******************/
|
||||
#define PWR_WKUPCR_WKUPC6_Pos (5U)
|
||||
#define PWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos) /*!< 0x00000020 */
|
||||
#define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk /*!< Clear Wakeup Pin Flag 6 */
|
||||
|
|
@ -17771,7 +17824,7 @@ typedef struct
|
|||
#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */
|
||||
#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */
|
||||
|
||||
/******************** Bit definition for PWR_WKUPFR register ********************/
|
||||
/******************** Bit definition for PWR_WKUPFR register ****************/
|
||||
#define PWR_WKUPFR_WKUPF6_Pos (5U)
|
||||
#define PWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos) /*!< 0x00000020 */
|
||||
#define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk /*!< Wakeup Pin Flag 6 */
|
||||
|
|
@ -17791,7 +17844,7 @@ typedef struct
|
|||
#define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */
|
||||
#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */
|
||||
|
||||
/******************** Bit definition for PWR_WKUPEPR register ********************/
|
||||
/****************** Bit definition for PWR_WKUPEPR register *****************/
|
||||
#define PWR_WKUPEPR_WKUPPUPD6_Pos (26U)
|
||||
#define PWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x0C000000 */
|
||||
#define PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk /*!< Wakeup Pin pull configuration for WKUP6 */
|
||||
|
|
@ -17867,6 +17920,9 @@ typedef struct
|
|||
/* Reset and Clock Control */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/******************************* RCC VERSION ********************************/
|
||||
#define RCC_VER_X
|
||||
|
||||
/******************** Bit definition for RCC_CR register ********************/
|
||||
#define RCC_CR_HSION_Pos (0U)
|
||||
#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -18860,28 +18916,32 @@ typedef struct
|
|||
#define RCC_AHB2ENR_DCMIEN_Pos (0U)
|
||||
#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
|
||||
#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
|
||||
#define RCC_AHB2ENR_CRYPEN_Pos (4U)
|
||||
#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
|
||||
#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
|
||||
#define RCC_AHB2ENR_HASHEN_Pos (5U)
|
||||
#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
|
||||
#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
|
||||
#define RCC_AHB2ENR_RNGEN_Pos (6U)
|
||||
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
|
||||
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
|
||||
#define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
|
||||
#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */
|
||||
#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
|
||||
#define RCC_AHB2ENR_D2SRAM1EN_Pos (29U)
|
||||
#define RCC_AHB2ENR_D2SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_D2SRAM1EN_Pos) /*!< 0x20000000 */
|
||||
#define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_D2SRAM1EN_Msk
|
||||
#define RCC_AHB2ENR_D2SRAM2EN_Pos (30U)
|
||||
#define RCC_AHB2ENR_D2SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_D2SRAM2EN_Pos) /*!< 0x40000000 */
|
||||
#define RCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_D2SRAM2EN_Msk
|
||||
#define RCC_AHB2ENR_D2SRAM3EN_Pos (31U)
|
||||
#define RCC_AHB2ENR_D2SRAM3EN_Msk (0x1UL << RCC_AHB2ENR_D2SRAM3EN_Pos) /*!< 0x80000000 */
|
||||
#define RCC_AHB2ENR_D2SRAM3EN RCC_AHB2ENR_D2SRAM3EN_Msk
|
||||
#define RCC_AHB2ENR_SRAM1EN_Pos (29U)
|
||||
#define RCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos) /*!< 0x20000000 */
|
||||
#define RCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk
|
||||
#define RCC_AHB2ENR_SRAM2EN_Pos (30U)
|
||||
#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */
|
||||
#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk
|
||||
#define RCC_AHB2ENR_SRAM3EN_Pos (31U)
|
||||
#define RCC_AHB2ENR_SRAM3EN_Msk (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos) /*!< 0x80000000 */
|
||||
#define RCC_AHB2ENR_SRAM3EN RCC_AHB2ENR_SRAM3EN_Msk
|
||||
|
||||
/* Legacy define */
|
||||
#define RCC_AHB2ENR_D2SRAM1EN_Pos RCC_AHB2ENR_SRAM1EN_Pos
|
||||
#define RCC_AHB2ENR_D2SRAM1EN_Msk RCC_AHB2ENR_SRAM1EN_Msk
|
||||
#define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_SRAM1EN
|
||||
#define RCC_AHB2ENR_D2SRAM2EN_Pos RCC_AHB2ENR_SRAM2EN_Pos
|
||||
#define RCC_AHB2ENR_D2SRAM2EN_Msk RCC_AHB2ENR_SRAM2EN_Msk
|
||||
#define RCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_SRAM2EN
|
||||
#define RCC_AHB2ENR_D2SRAM3EN_Pos RCC_AHB2ENR_SRAM3EN_Pos
|
||||
#define RCC_AHB2ENR_D2SRAM3EN_Msk RCC_AHB2ENR_SRAM3EN_Msk
|
||||
#define RCC_AHB2ENR_D2SRAM3EN RCC_AHB2ENR_SRAM3EN
|
||||
|
||||
/******************** Bit definition for RCC_AHB4ENR register ******************/
|
||||
#define RCC_AHB4ENR_GPIOAEN_Pos (0U)
|
||||
|
|
@ -18932,9 +18992,6 @@ typedef struct
|
|||
#define RCC_AHB4ENR_BKPRAMEN_Pos (28U)
|
||||
#define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) /*!< 0x10000000 */
|
||||
#define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk
|
||||
#define RCC_AHB4ENR_D3SRAM1EN_Pos (29U)
|
||||
#define RCC_AHB4ENR_D3SRAM1EN_Msk (0x1UL << RCC_AHB4ENR_D3SRAM1EN_Pos) /*!< 0x20000000 */
|
||||
#define RCC_AHB4ENR_D3SRAM1EN RCC_AHB4ENR_D3SRAM1EN_Msk
|
||||
|
||||
/******************** Bit definition for RCC_APB3ENR register ******************/
|
||||
#define RCC_APB3ENR_LTDCEN_Pos (3U)
|
||||
|
|
@ -19027,6 +19084,10 @@ typedef struct
|
|||
#define RCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */
|
||||
#define RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk
|
||||
|
||||
/* Legacy define */
|
||||
#define RCC_APB1LENR_HDMICECEN_Pos RCC_APB1LENR_CECEN_Pos
|
||||
#define RCC_APB1LENR_HDMICECEN_Msk RCC_APB1LENR_CECEN_Msk
|
||||
#define RCC_APB1LENR_HDMICECEN RCC_APB1LENR_CECEN
|
||||
/******************** Bit definition for RCC_APB1HENR register ******************/
|
||||
#define RCC_APB1HENR_CRSEN_Pos (1U)
|
||||
#define RCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */
|
||||
|
|
@ -19183,12 +19244,6 @@ typedef struct
|
|||
#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
|
||||
#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
|
||||
#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
|
||||
#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
|
||||
#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
|
||||
#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
|
||||
#define RCC_AHB2RSTR_HASHRST_Pos (5U)
|
||||
#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
|
||||
#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
|
||||
#define RCC_AHB2RSTR_RNGRST_Pos (6U)
|
||||
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
|
||||
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
|
||||
|
|
@ -19327,6 +19382,10 @@ typedef struct
|
|||
#define RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */
|
||||
#define RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk
|
||||
|
||||
/* Legacy define */
|
||||
#define RCC_APB1LRSTR_HDMICECRST_Pos RCC_APB1LRSTR_CECRST_Pos
|
||||
#define RCC_APB1LRSTR_HDMICECRST_Msk RCC_APB1LRSTR_CECRST_Msk
|
||||
#define RCC_APB1LRSTR_HDMICECRST RCC_APB1LRSTR_CECRST
|
||||
/******************** Bit definition for RCC_APB1HRSTR register ******************/
|
||||
#define RCC_APB1HRSTR_CRSRST_Pos (1U)
|
||||
#define RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */
|
||||
|
|
@ -19575,28 +19634,32 @@ typedef struct
|
|||
#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
|
||||
#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
|
||||
#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
|
||||
#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
|
||||
#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
|
||||
#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
|
||||
#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
|
||||
#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
|
||||
#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
|
||||
#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
|
||||
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
|
||||
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
|
||||
#define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U)
|
||||
#define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
|
||||
#define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk
|
||||
#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos (30U)
|
||||
#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_D2SRAM1LPEN_Pos) /*!< 0x40000000 */
|
||||
#define RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_D2SRAM1LPEN_Msk
|
||||
#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos (30U)
|
||||
#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_D2SRAM2LPEN_Pos) /*!< 0x40000000 */
|
||||
#define RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_D2SRAM2LPEN_Msk
|
||||
#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos (31U)
|
||||
#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk (0x1UL << RCC_AHB2LPENR_D2SRAM3LPEN_Pos) /*!< 0x80000000 */
|
||||
#define RCC_AHB2LPENR_D2SRAM3LPEN RCC_AHB2LPENR_D2SRAM3LPEN_Msk
|
||||
#define RCC_AHB2LPENR_SRAM1LPEN_Pos (29U)
|
||||
#define RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */
|
||||
#define RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk
|
||||
#define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U)
|
||||
#define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */
|
||||
#define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk
|
||||
#define RCC_AHB2LPENR_SRAM3LPEN_Pos (31U)
|
||||
#define RCC_AHB2LPENR_SRAM3LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */
|
||||
#define RCC_AHB2LPENR_SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN_Msk
|
||||
|
||||
/* Legacy define */
|
||||
#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos RCC_AHB2LPENR_SRAM1LPEN_Pos
|
||||
#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk RCC_AHB2LPENR_SRAM1LPEN_Msk
|
||||
#define RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN
|
||||
#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos RCC_AHB2LPENR_SRAM2LPEN_Pos
|
||||
#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk RCC_AHB2LPENR_SRAM2LPEN_Msk
|
||||
#define RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN
|
||||
#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos RCC_AHB2LPENR_SRAM3LPEN_Pos
|
||||
#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk RCC_AHB2LPENR_SRAM3LPEN_Msk
|
||||
#define RCC_AHB2LPENR_D2SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN
|
||||
|
||||
/******************** Bit definition for RCC_AHB4LPENR register ******************/
|
||||
#define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)
|
||||
|
|
@ -19644,10 +19707,14 @@ typedef struct
|
|||
#define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U)
|
||||
#define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
|
||||
#define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk
|
||||
#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos (29U)
|
||||
#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk (0x1UL << RCC_AHB4LPENR_D3SRAM1LPEN_Pos) /*!< 0x20000000 */
|
||||
#define RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_D3SRAM1LPEN_Msk
|
||||
#define RCC_AHB4LPENR_SRAM4LPEN_Pos (29U)
|
||||
#define RCC_AHB4LPENR_SRAM4LPEN_Msk (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */
|
||||
#define RCC_AHB4LPENR_SRAM4LPEN RCC_AHB4LPENR_SRAM4LPEN_Msk
|
||||
|
||||
/* Legacy define */
|
||||
#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos RCC_AHB4LPENR_SRAM4LPEN_Pos
|
||||
#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk RCC_AHB4LPENR_SRAM4LPEN_Msk
|
||||
#define RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_SRAM4LPEN
|
||||
/******************** Bit definition for RCC_APB3LPENR register ******************/
|
||||
#define RCC_APB3LPENR_LTDCLPEN_Pos (3U)
|
||||
#define RCC_APB3LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */
|
||||
|
|
@ -19739,6 +19806,10 @@ typedef struct
|
|||
#define RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */
|
||||
#define RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk
|
||||
|
||||
/* Legacy define */
|
||||
#define RCC_APB1LLPENR_HDMICECEN_Pos RCC_APB1LLPENR_CECLPEN_Pos
|
||||
#define RCC_APB1LLPENR_HDMICECEN_Msk RCC_APB1LLPENR_CECLPEN_Msk
|
||||
#define RCC_APB1LLPENR_HDMICECEN RCC_APB1LLPENR_CECLPEN
|
||||
/******************** Bit definition for RCC_APB1HLPENR register ******************/
|
||||
#define RCC_APB1HLPENR_CRSLPEN_Pos (1U)
|
||||
#define RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */
|
||||
|
|
@ -22918,7 +22989,6 @@ typedef struct
|
|||
/* */
|
||||
/******************************************************************************/
|
||||
#define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature */
|
||||
#define TIM17_TI1_SPDIF_FS_SUPPORT /*!< TIM17 Trigger input 1 to SPDIF FS connection feature */
|
||||
|
||||
/******************* Bit definition for TIM_CR1 register ********************/
|
||||
#define TIM_CR1_CEN_Pos (0U)
|
||||
|
|
@ -24759,6 +24829,8 @@ typedef struct
|
|||
/* DBG */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/********************************* DEVICE ID ********************************/
|
||||
#define STM32H7_DEV_ID 0x450UL
|
||||
|
||||
/******************** Bit definition for DBGMCU_IDCODE register *************/
|
||||
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
|
||||
|
|
@ -28035,10 +28107,11 @@ typedef struct
|
|||
#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
|
||||
#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
|
||||
#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
|
||||
#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
|
||||
|
|
@ -28213,6 +28286,9 @@ typedef struct
|
|||
#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
|
||||
#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
|
||||
#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
|
||||
#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */
|
||||
#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
|
||||
#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
|
||||
#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
|
||||
|
|
@ -28231,6 +28307,15 @@ typedef struct
|
|||
#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
|
||||
#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
|
||||
#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
|
||||
#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
|
||||
#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
|
||||
#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */
|
||||
#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
|
||||
#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
|
||||
#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */
|
||||
#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
|
||||
#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
|
||||
#define USB_OTG_GINTSTS_CMOD_Pos (0U)
|
||||
|
|
@ -28994,12 +29079,18 @@ typedef struct
|
|||
#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
|
||||
#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
|
||||
#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
|
||||
#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */
|
||||
#define USB_OTG_DIEPINT_TOC_Pos (3U)
|
||||
#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
|
||||
#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
|
||||
#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
|
||||
#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
|
||||
#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
|
||||
#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */
|
||||
#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
|
||||
#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
|
||||
#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
|
||||
|
|
@ -29155,6 +29246,9 @@ typedef struct
|
|||
#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
|
||||
#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
|
||||
#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
|
||||
#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */
|
||||
#define USB_OTG_DOEPINT_STUP_Pos (3U)
|
||||
#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
|
||||
#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
|
||||
|
|
@ -29167,9 +29261,21 @@ typedef struct
|
|||
#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
|
||||
#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
|
||||
#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
|
||||
#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
|
||||
#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
|
||||
#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */
|
||||
#define USB_OTG_DOEPINT_BERR_Pos (12U)
|
||||
#define USB_OTG_DOEPINT_BERR_Msk (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
|
||||
#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */
|
||||
#define USB_OTG_DOEPINT_NAK_Pos (13U)
|
||||
#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
|
||||
#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */
|
||||
#define USB_OTG_DOEPINT_NYET_Pos (14U)
|
||||
#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
|
||||
#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
|
||||
#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
|
||||
|
||||
|
|
@ -29449,6 +29555,8 @@ typedef struct
|
|||
/******************** Bit definition for HSEM_CR register *****************/
|
||||
#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */
|
||||
#define HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */
|
||||
#define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
|
||||
#define HSEM_CR_COREID_CPU2 (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)
|
||||
#if defined(CORE_CM4)
|
||||
#define HSEM_CR_COREID_CURRENT (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)
|
||||
#else /* CORE_CM7 */
|
||||
|
|
@ -29539,6 +29647,7 @@ typedef struct
|
|||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/************* TIM Instances : at least 1 capture/compare channel *************/
|
||||
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
|
|
@ -29552,6 +29661,7 @@ typedef struct
|
|||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/************ TIM Instances : at least 2 capture/compare channels *************/
|
||||
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
|
|
@ -29561,6 +29671,7 @@ typedef struct
|
|||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/************ TIM Instances : at least 3 capture/compare channels *************/
|
||||
#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
|
|
@ -29576,6 +29687,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
||||
/************ TIM Instances : at least 5 capture/compare channels *************/
|
||||
#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
|
@ -29646,13 +29758,15 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
||||
/****************** TIM Instances : remapping capability **********************/
|
||||
#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
||||
((__INSTANCE__) == TIM2) || \
|
||||
((__INSTANCE__) == TIM3) || \
|
||||
((__INSTANCE__) == TIM5) || \
|
||||
((__INSTANCE__) == TIM16) || \
|
||||
((__INSTANCE__) == TIM17))
|
||||
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/*************** TIM Instances : external trigger reamp input available *******/
|
||||
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -29671,6 +29785,7 @@ typedef struct
|
|||
((INSTANCE) == TIM7) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
|
||||
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
|
|
@ -29832,6 +29947,7 @@ typedef struct
|
|||
((__INSTANCE__) == TIM3) || \
|
||||
((__INSTANCE__) == TIM4) || \
|
||||
((__INSTANCE__) == TIM5) || \
|
||||
((__INSTANCE__) == TIM6) || \
|
||||
((__INSTANCE__) == TIM8) || \
|
||||
((__INSTANCE__) == TIM12) || \
|
||||
((__INSTANCE__) == TIM15))
|
||||
|
|
@ -29847,6 +29963,7 @@ typedef struct
|
|||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
|
||||
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
|
|
@ -29864,6 +29981,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
||||
/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
|
||||
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
|
|
@ -29889,6 +30007,7 @@ typedef struct
|
|||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
|
||||
/****************** TIM Instances : TIM_32B_COUNTER ***************************/
|
||||
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM2) || \
|
||||
|
|
@ -30083,6 +30202,7 @@ typedef struct
|
|||
#define PVD_IRQn PVD_AVD_IRQn
|
||||
|
||||
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define HASH_RNG_IRQHandler RNG_IRQHandler
|
||||
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
|
|
@ -30090,16 +30210,12 @@ typedef struct
|
|||
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define PVD_IRQHandler PVD_AVD_IRQHandler
|
||||
|
||||
/* Aliases for COMP __IRQHandler */
|
||||
#define COMP_IRQHandler COMP1_IRQHandler
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/****************************** Product define *********************************/
|
||||
#define FLASH_SIZE 0x200000UL /* 2 MB */
|
||||
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
|
||||
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
|
||||
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -59,7 +59,8 @@
|
|||
*/
|
||||
|
||||
#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
|
||||
!defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx)
|
||||
!defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx) && \
|
||||
!defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ)
|
||||
/* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
|
||||
/* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
|
||||
/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
|
||||
|
|
@ -68,6 +69,11 @@
|
|||
/* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
|
||||
/* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */
|
||||
/* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */
|
||||
/* #define STM32H7B0xx */ /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */
|
||||
/* #define STM32H7A3xx */ /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */
|
||||
/* #define STM32H7A3xxQ */ /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */
|
||||
/* #define STM32H7B3xx */ /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */
|
||||
/* #define STM32H7B3xxQ */ /*!< STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q */
|
||||
#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
|
|
@ -88,10 +94,10 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V1.6.0
|
||||
* @brief CMSIS Device version number V1.8.0
|
||||
*/
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|
|
@ -123,6 +129,18 @@
|
|||
#include "stm32h747xx.h"
|
||||
#elif defined(STM32H757xx)
|
||||
#include "stm32h757xx.h"
|
||||
#elif defined(STM32H7B0xx)
|
||||
#include "stm32h7b0xx.h"
|
||||
#elif defined(STM32H7B0xxQ)
|
||||
#include "stm32h7b0xxq.h"
|
||||
#elif defined(STM32H7A3xx)
|
||||
#include "stm32h7a3xx.h"
|
||||
#elif defined(STM32H7B3xx)
|
||||
#include "stm32h7b3xx.h"
|
||||
#elif defined(STM32H7A3xxQ)
|
||||
#include "stm32h7a3xxq.h"
|
||||
#elif defined(STM32H7B3xxQ)
|
||||
#include "stm32h7b3xxq.h"
|
||||
#else
|
||||
#error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
|
||||
#endif
|
||||
|
|
@ -149,8 +167,8 @@ typedef enum
|
|||
|
||||
typedef enum
|
||||
{
|
||||
ERROR = 0,
|
||||
SUCCESS = !ERROR
|
||||
SUCCESS = 0,
|
||||
ERROR = !SUCCESS
|
||||
} ErrorStatus;
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -55,12 +55,7 @@
|
|||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
#if defined(DUAL_CORE) && defined(CORE_CM4)
|
||||
#define SystemCoreClock SystemD2Clock /*!< System Domain1 Clock Frequency */
|
||||
#else
|
||||
#define SystemCoreClock SystemD1Clock
|
||||
#endif
|
||||
extern uint32_t SystemD1Clock; /*!< System Domain1 Clock Frequency */
|
||||
extern uint32_t SystemCoreClock; /*!< System Domain1 Clock Frequency */
|
||||
extern uint32_t SystemD2Clock; /*!< System Domain2 Clock Frequency */
|
||||
extern const uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue