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Aligned with the astyle rule: rz_a1h emac driver

pull/13375/head
RyoheiHagimoto 2020-08-03 09:00:51 +09:00
parent e818c489d5
commit 21773f245d
2 changed files with 101 additions and 65 deletions
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17
features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_emac.cpp
View File

@ -24,17 +24,19 @@
#define RZ_A1_ETH_IF_NAME "en" #define RZ_A1_ETH_IF_NAME "en"
// Weak so a module can override // Weak so a module can override
MBED_WEAK EMAC &EMAC::get_default_instance() { MBED_WEAK EMAC &EMAC::get_default_instance()
{
return RZ_A1_EMAC::get_instance(); return RZ_A1_EMAC::get_instance();
} }
RZ_A1_EMAC &RZ_A1_EMAC::get_instance() { RZ_A1_EMAC &RZ_A1_EMAC::get_instance()
{
static RZ_A1_EMAC emac; static RZ_A1_EMAC emac;
return emac; return emac;
} }
RZ_A1_EMAC::RZ_A1_EMAC() : hwaddr(), hwaddr_set(false), power_on(false), connect_sts(false), RZ_A1_EMAC::RZ_A1_EMAC() : hwaddr(), hwaddr_set(false), power_on(false), connect_sts(false),
link_mode_last(NEGO_FAIL), recvThread(osPriorityNormal, 896) link_mode_last(NEGO_FAIL), recvThread(osPriorityNormal, 896)
{ {
} }
@ -168,15 +170,18 @@ void RZ_A1_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr)
} }
void RZ_A1_EMAC::_recv_callback(void) { void RZ_A1_EMAC::_recv_callback(void)
{
get_instance().recv_callback(); get_instance().recv_callback();
} }
void RZ_A1_EMAC::recv_callback(void) { void RZ_A1_EMAC::recv_callback(void)
{
recvThread.flags_set(1); recvThread.flags_set(1);
} }
void RZ_A1_EMAC::recv_task(void) { void RZ_A1_EMAC::recv_task(void)
{
uint16_t recv_size; uint16_t recv_size;
emac_mem_buf_t *buf; emac_mem_buf_t *buf;
int cnt; int cnt;

149
features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_eth.c
View File

@ -80,13 +80,13 @@
#define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */ #define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */
#define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */ #define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */
/* 0x00040000 : Detect frame reception */ /* 0x00040000 : Detect frame reception */
/* 0x00010000 : Receive FIFO overflow */ /* 0x00010000 : Receive FIFO overflow */
/* 0x00000010 : Residual bit frame reception */ /* 0x00000010 : Residual bit frame reception */
/* 0x00000008 : Long frame reception */ /* 0x00000008 : Long frame reception */
/* 0x00000004 : Short frame reception */ /* 0x00000004 : Short frame reception */
/* 0x00000002 : PHY-LSI reception error */ /* 0x00000002 : PHY-LSI reception error */
/* 0x00000001 : Receive frame CRC error */ /* 0x00000001 : Receive frame CRC error */
#define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */ #define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */
void rza1_ethernet_address(char *); void rza1_ethernet_address(char *);
@ -115,16 +115,16 @@ typedef struct tag_edmac_recv_desc {
#if defined(__ICCARM__) #if defined(__ICCARM__)
#pragma data_alignment=16 #pragma data_alignment=16
static uint8_t rza1_ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) + static uint8_t rza1_ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
(sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) + (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
(NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) + (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
(NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] //16 bytes aligned! (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] //16 bytes aligned!
@ ".mirrorram"; @ ".mirrorram";
#else #else
static uint8_t rza1_ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) + static uint8_t rza1_ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
(sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) + (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
(NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) + (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
(NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]
__attribute((section("NC_BSS"),aligned(16))); //16 bytes aligned! __attribute((section("NC_BSS"), aligned(16))); //16 bytes aligned!
#endif #endif
static int32_t rx_read_offset; /* read offset */ static int32_t rx_read_offset; /* read offset */
static int32_t tx_wite_offset; /* write offset */ static int32_t tx_wite_offset; /* write offset */
@ -140,10 +140,10 @@ static uint32_t phy_id = 0;
static uint32_t start_stop = 1; /* 0:stop 1:start */ static uint32_t start_stop = 1; /* 0:stop 1:start */
static uint32_t tsu_ten_tmp = 0; static uint32_t tsu_ten_tmp = 0;
volatile struct st_ether_from_tsu_adrh0* ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] = volatile struct st_ether_from_tsu_adrh0 *ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST; ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
/* function */ /* function */
static void lan_reg_reset(void); static void lan_reg_reset(void);
@ -162,7 +162,8 @@ static void set_ether_pir(uint32_t set_data);
static void wait_100us(int32_t wait_cnt); static void wait_100us(int32_t wait_cnt);
int ethernetext_init(rza1_ethernet_cfg_t *p_ethcfg) { int ethernetext_init(rza1_ethernet_cfg_t *p_ethcfg)
{
int32_t i; int32_t i;
uint16_t val; uint16_t val;
@ -224,7 +225,7 @@ int ethernetext_init(rza1_ethernet_cfg_t *p_ethcfg) {
} }
phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16) phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16)
| (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG); | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG);
Interrupt_priority = p_ethcfg->int_priority; Interrupt_priority = p_ethcfg->int_priority;
p_recv_cb_fnc = p_ethcfg->recv_cb; p_recv_cb_fnc = p_ethcfg->recv_cb;
@ -239,7 +240,8 @@ int ethernetext_init(rza1_ethernet_cfg_t *p_ethcfg) {
return 0; return 0;
} }
void ethernetext_start_stop(int32_t mode) { void ethernetext_start_stop(int32_t mode)
{
if (mode == 1) { if (mode == 1) {
/* start */ /* start */
ETHEREDTRR0 |= EDTRR0_TR; ETHEREDTRR0 |= EDTRR0_TR;
@ -253,7 +255,8 @@ void ethernetext_start_stop(int32_t mode) {
} }
} }
int ethernetext_chk_link_mode(void) { int ethernetext_chk_link_mode(void)
{
int32_t link; int32_t link;
uint16_t data; uint16_t data;
@ -283,13 +286,15 @@ int ethernetext_chk_link_mode(void) {
return link; return link;
} }
void ethernetext_set_link_mode(int32_t link) { void ethernetext_set_link_mode(int32_t link)
{
lan_reg_reset(); /* Resets the E-MAC,E-DMAC */ lan_reg_reset(); /* Resets the E-MAC,E-DMAC */
lan_desc_create(); /* Initialize of buffer memory */ lan_desc_create(); /* Initialize of buffer memory */
lan_reg_set(link); /* E-DMAC, E-MAC initialization */ lan_reg_set(link); /* E-DMAC, E-MAC initialization */
} }
void ethernetext_add_multicast_group(const uint8_t *addr) { void ethernetext_add_multicast_group(const uint8_t *addr)
{
uint32_t cnt; uint32_t cnt;
uint32_t tmp_data_h; uint32_t tmp_data_h;
uint32_t tmp_data_l; uint32_t tmp_data_l;
@ -320,7 +325,8 @@ void ethernetext_add_multicast_group(const uint8_t *addr) {
} }
} }
void ethernetext_remove_multicast_group(const uint8_t *addr) { void ethernetext_remove_multicast_group(const uint8_t *addr)
{
uint32_t cnt; uint32_t cnt;
uint32_t tmp_data_h; uint32_t tmp_data_h;
uint32_t tmp_data_l; uint32_t tmp_data_l;
@ -328,9 +334,9 @@ void ethernetext_remove_multicast_group(const uint8_t *addr) {
tmp_data_h = ((uint32_t)addr[0] << 24) | ((uint32_t)addr[1] << 16) | ((uint32_t)addr[2] << 8) | ((uint32_t)addr[3]); tmp_data_h = ((uint32_t)addr[0] << 24) | ((uint32_t)addr[1] << 16) | ((uint32_t)addr[2] << 8) | ((uint32_t)addr[3]);
tmp_data_l = ((uint32_t)addr[4] << 8) | ((uint32_t)addr[5]); tmp_data_l = ((uint32_t)addr[4] << 8) | ((uint32_t)addr[5]);
for (cnt = 0; cnt< 32; cnt++) { for (cnt = 0; cnt < 32; cnt++) {
if ((ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0 == tmp_data_h) && if ((ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0 == tmp_data_h) &&
(ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0 == tmp_data_l)) { (ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0 == tmp_data_l)) {
while ((ETHERTSU_ADSBSY & 0x00000001) != 0) { while ((ETHERTSU_ADSBSY & 0x00000001) != 0) {
; ;
} }
@ -347,7 +353,8 @@ void ethernetext_remove_multicast_group(const uint8_t *addr) {
} }
} }
void ethernetext_set_all_multicast(int all) { void ethernetext_set_all_multicast(int all)
{
if (all != 0) { if (all != 0) {
ETHERECMR0 &= ~(0x00002000); ETHERECMR0 &= ~(0x00002000);
ETHERTSU_TEN = 0x00000000; ETHERTSU_TEN = 0x00000000;
@ -358,7 +365,8 @@ void ethernetext_set_all_multicast(int all) {
} }
int rza1_ethernet_init() { int rza1_ethernet_init()
{
rza1_ethernet_cfg_t ethcfg; rza1_ethernet_cfg_t ethcfg;
ethcfg.int_priority = 5; ethcfg.int_priority = 5;
@ -370,17 +378,19 @@ int rza1_ethernet_init() {
return 0; return 0;
} }
void rza1_ethernet_free() { void rza1_ethernet_free()
{
ETHERARSTR |= 0x00000001; /* ETHER software reset */ ETHERARSTR |= 0x00000001; /* ETHER software reset */
CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */ CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */
} }
int rza1_ethernet_write(const char *data, int slen) { int rza1_ethernet_write(const char *data, int slen)
{
edmac_send_desc_t *p_send_desc; edmac_send_desc_t *p_send_desc;
int32_t copy_size; int32_t copy_size;
if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0) if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0)
|| (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) { || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) {
copy_size = 0; copy_size = 0;
} else { } else {
p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */ p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
@ -399,7 +409,8 @@ int rza1_ethernet_write(const char *data, int slen) {
return copy_size; return copy_size;
} }
int rza1_ethernet_send() { int rza1_ethernet_send()
{
edmac_send_desc_t *p_send_desc; edmac_send_desc_t *p_send_desc;
int32_t ret; int32_t ret;
@ -431,7 +442,8 @@ int rza1_ethernet_send() {
return ret; return ret;
} }
int rza1_ethernet_receive() { int rza1_ethernet_receive()
{
edmac_recv_desc_t *p_recv_desc; edmac_recv_desc_t *p_recv_desc;
int32_t receive_size = 0; int32_t receive_size = 0;
@ -475,7 +487,8 @@ int rza1_ethernet_receive() {
return receive_size; return receive_size;
} }
int rza1_ethernet_read(char *data, int dlen) { int rza1_ethernet_read(char *data, int dlen)
{
edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */ edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */
int32_t copy_size; int32_t copy_size;
@ -493,13 +506,15 @@ int rza1_ethernet_read(char *data, int dlen) {
return copy_size; return copy_size;
} }
void rza1_ethernet_address(char *mac) { void rza1_ethernet_address(char *mac)
{
if (mac != NULL) { if (mac != NULL) {
mbed_mac_address(mac); /* Get MAC Address */ mbed_mac_address(mac); /* Get MAC Address */
} }
} }
int rza1_ethernet_link(void) { int rza1_ethernet_link(void)
{
int32_t ret; int32_t ret;
uint16_t data; uint16_t data;
@ -513,7 +528,8 @@ int rza1_ethernet_link(void) {
return ret; return ret;
} }
void rza1_ethernet_set_link(int speed, int duplex) { void rza1_ethernet_set_link(int speed, int duplex)
{
uint16_t data; uint16_t data;
int32_t i; int32_t i;
int32_t link; int32_t link;
@ -538,7 +554,8 @@ void rza1_ethernet_set_link(int speed, int duplex) {
ethernetext_set_link_mode(link); ethernetext_set_link_mode(link);
} }
void INT_Ether(void) { void INT_Ether(void)
{
uint32_t stat_edmac; uint32_t stat_edmac;
uint32_t stat_etherc; uint32_t stat_etherc;
@ -559,7 +576,8 @@ void INT_Ether(void) {
} }
} }
static void lan_reg_reset(void) { static void lan_reg_reset(void)
{
volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */ volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */
ETHERARSTR |= 0x00000001; /* ETHER software reset */ ETHERARSTR |= 0x00000001; /* ETHER software reset */
@ -576,7 +594,8 @@ static void lan_reg_reset(void) {
} }
} }
static void lan_desc_create(void) { static void lan_desc_create(void)
{
int32_t i; int32_t i;
uint8_t *p_memory_top; uint8_t *p_memory_top;
@ -615,14 +634,15 @@ static void lan_desc_create(void) {
p_recv_end_desc = NULL; p_recv_end_desc = NULL;
} }
static void lan_reg_set(int32_t link) { static void lan_reg_set(int32_t link)
{
/* MAC address setting */ /* MAC address setting */
ETHERMAHR0 = ((uint8_t)mac_addr[0] << 24) ETHERMAHR0 = ((uint8_t)mac_addr[0] << 24)
| ((uint8_t)mac_addr[1] << 16) | ((uint8_t)mac_addr[1] << 16)
| ((uint8_t)mac_addr[2] << 8) | ((uint8_t)mac_addr[2] << 8)
| (uint8_t)mac_addr[3]; | (uint8_t)mac_addr[3];
ETHERMALR0 = ((uint8_t)mac_addr[4] << 8) ETHERMALR0 = ((uint8_t)mac_addr[4] << 8)
| (uint8_t)mac_addr[5]; | (uint8_t)mac_addr[5];
/* E-DMAC */ /* E-DMAC */
ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0]; ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0];
@ -676,7 +696,8 @@ static void lan_reg_set(int32_t link) {
} }
} }
static uint16_t phy_reg_read(uint16_t reg_addr) { static uint16_t phy_reg_read(uint16_t reg_addr)
{
uint16_t data; uint16_t data;
mii_preamble(); mii_preamble();
@ -688,7 +709,8 @@ static uint16_t phy_reg_read(uint16_t reg_addr) {
return data; return data;
} }
static void phy_reg_write(uint16_t reg_addr, uint16_t data) { static void phy_reg_write(uint16_t reg_addr, uint16_t data)
{
mii_preamble(); mii_preamble();
mii_cmd(reg_addr, PHY_WRITE); mii_cmd(reg_addr, PHY_WRITE);
mii_write_1(); mii_write_1();
@ -697,7 +719,8 @@ static void phy_reg_write(uint16_t reg_addr, uint16_t data) {
mii_z(); mii_z();
} }
static void mii_preamble(void) { static void mii_preamble(void)
{
int32_t i = 32; int32_t i = 32;
for (i = 32; i > 0; i--) { for (i = 32; i > 0; i--) {
@ -706,7 +729,8 @@ static void mii_preamble(void) {
} }
} }
static void mii_cmd(uint16_t reg_addr, uint32_t option) { static void mii_cmd(uint16_t reg_addr, uint32_t option)
{
int32_t i; int32_t i;
uint16_t data = 0; uint16_t data = 0;
@ -724,7 +748,8 @@ static void mii_cmd(uint16_t reg_addr, uint32_t option) {
} }
} }
static void mii_reg_read(uint16_t *data) { static void mii_reg_read(uint16_t *data)
{
int32_t i; int32_t i;
uint16_t reg_data = 0; uint16_t reg_data = 0;
@ -740,7 +765,8 @@ static void mii_reg_read(uint16_t *data) {
*data = reg_data; *data = reg_data;
} }
static void mii_reg_write(uint16_t data) { static void mii_reg_write(uint16_t data)
{
int32_t i; int32_t i;
/* Data are written one bit at a time */ /* Data are written one bit at a time */
@ -754,28 +780,32 @@ static void mii_reg_write(uint16_t data) {
} }
} }
static void mii_z(void) { static void mii_z(void)
{
set_ether_pir(PIR0_MDC_LOW); set_ether_pir(PIR0_MDC_LOW);
set_ether_pir(PIR0_MDC_HIGH); set_ether_pir(PIR0_MDC_HIGH);
set_ether_pir(PIR0_MDC_HIGH); set_ether_pir(PIR0_MDC_HIGH);
set_ether_pir(PIR0_MDC_LOW); set_ether_pir(PIR0_MDC_LOW);
} }
static void mii_write_1(void) { static void mii_write_1(void)
{
set_ether_pir(PIR0_MDO | PIR0_MMD); set_ether_pir(PIR0_MDO | PIR0_MMD);
set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC); set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC); set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
set_ether_pir(PIR0_MDO | PIR0_MMD); set_ether_pir(PIR0_MDO | PIR0_MMD);
} }
static void mii_write_0(void) { static void mii_write_0(void)
{
set_ether_pir(PIR0_MMD); set_ether_pir(PIR0_MMD);
set_ether_pir(PIR0_MMD | PIR0_MDC); set_ether_pir(PIR0_MMD | PIR0_MDC);
set_ether_pir(PIR0_MMD | PIR0_MDC); set_ether_pir(PIR0_MMD | PIR0_MDC);
set_ether_pir(PIR0_MMD); set_ether_pir(PIR0_MMD);
} }
static void set_ether_pir(uint32_t set_data) { static void set_ether_pir(uint32_t set_data)
{
int32_t i; int32_t i;
for (i = MDC_WAIT; i > 0; i--) { for (i = MDC_WAIT; i > 0; i--) {
@ -783,7 +813,8 @@ static void set_ether_pir(uint32_t set_data) {
} }
} }
static void wait_100us(int32_t wait_cnt) { static void wait_100us(int32_t wait_cnt)
{
volatile int32_t j = LOOP_100us * wait_cnt; volatile int32_t j = LOOP_100us * wait_cnt;
while (--j) { while (--j) {