Merge pull request #3893 from jeromecoutant/PULL_REQUEST_CUBE_UPDATE_F7_V1.6.0

[STM32F7] Update STM32 Cube version v1.6.0

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_stm32f7xx.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f7xx.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f7xx.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f7xx.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   CMSIS STM32F7xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -111,11 +111,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V1.1.2
+  * @brief CMSIS Device version number V1.2.0
   */
 #define __STM32F7_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32F7_CMSIS_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
+#define __STM32F7_CMSIS_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
-#define __STM32F7_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
+#define __STM32F7_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
 #define __STM32F7_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32F7_CMSIS_VERSION        ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
                                        |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/system_stm32f7xx.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f7xx.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.       
   ******************************************************************************  
   * @attention

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_stm32f7xx.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f7xx.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/stm32f7xx.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   CMSIS STM32F7xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -111,11 +111,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V1.1.2
+  * @brief CMSIS Device version number V1.2.0
   */
 #define __STM32F7_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32F7_CMSIS_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
+#define __STM32F7_CMSIS_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
-#define __STM32F7_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
+#define __STM32F7_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
 #define __STM32F7_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32F7_CMSIS_VERSION        ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
                                        |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/system_stm32f7xx.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f7xx.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.       
   ******************************************************************************  
   * @attention

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_stm32f7xx.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f7xx.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/stm32f7xx.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   CMSIS STM32F7xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -111,11 +111,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V1.1.2
+  * @brief CMSIS Device version number V1.2.0
   */
 #define __STM32F7_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32F7_CMSIS_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
+#define __STM32F7_CMSIS_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
-#define __STM32F7_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
+#define __STM32F7_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
 #define __STM32F7_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32F7_CMSIS_VERSION        ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
                                        |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/system_stm32f7xx.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f7xx.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.       
   ******************************************************************************  
   * @attention

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_stm32f7xx.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f7xx.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/stm32f7xx.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   CMSIS STM32F7xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -111,11 +111,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V1.1.2
+  * @brief CMSIS Device version number V1.2.0
   */
 #define __STM32F7_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32F7_CMSIS_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
+#define __STM32F7_CMSIS_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
-#define __STM32F7_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
+#define __STM32F7_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
 #define __STM32F7_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32F7_CMSIS_VERSION        ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
                                        |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/system_stm32f7xx.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f7xx.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.       
   ******************************************************************************  
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32_hal_legacy.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32_hal_legacy.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   This file contains aliases definition for the STM32Cube HAL constants 
   *          macros and functions maintained for legacy purpose.
   ******************************************************************************
@@ -241,9 +241,9 @@
 #define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
 #define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
 #define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC_WAVE_NONE                                   ((uint32_t)0x00000000U)
+#define DAC_WAVE_NONE                                   0x00000000U
-#define DAC_WAVE_NOISE                                  ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
-#define DAC_WAVE_TRIANGLE                               ((uint32_t)DAC_CR_WAVE1_1)                           
+#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
 #define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
 #define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
 #define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
@@ -917,48 +917,45 @@
 #define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
 #define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
 
-#define ETH_MMCCR              ((uint32_t)0x00000100U)  
+#define ETH_MMCCR              0x00000100U
-#define ETH_MMCRIR             ((uint32_t)0x00000104U)  
+#define ETH_MMCRIR             0x00000104U
-#define ETH_MMCTIR             ((uint32_t)0x00000108U)  
+#define ETH_MMCTIR             0x00000108U
-#define ETH_MMCRIMR            ((uint32_t)0x0000010CU)  
+#define ETH_MMCRIMR            0x0000010CU
-#define ETH_MMCTIMR            ((uint32_t)0x00000110U)  
+#define ETH_MMCTIMR            0x00000110U
-#define ETH_MMCTGFSCCR         ((uint32_t)0x0000014CU)  
+#define ETH_MMCTGFSCCR         0x0000014CU
-#define ETH_MMCTGFMSCCR        ((uint32_t)0x00000150U)  
+#define ETH_MMCTGFMSCCR        0x00000150U
-#define ETH_MMCTGFCR           ((uint32_t)0x00000168U)  
+#define ETH_MMCTGFCR           0x00000168U
-#define ETH_MMCRFCECR          ((uint32_t)0x00000194U)  
+#define ETH_MMCRFCECR          0x00000194U
-#define ETH_MMCRFAECR          ((uint32_t)0x00000198U)  
+#define ETH_MMCRFAECR          0x00000198U
-#define ETH_MMCRGUFCR          ((uint32_t)0x000001C4U)
+#define ETH_MMCRGUFCR          0x000001C4U
  
-#define ETH_MAC_TXFIFO_FULL          ((uint32_t)0x02000000)  /* Tx FIFO full */
+#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY      ((uint32_t)0x01000000)  /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE  ((uint32_t)0x00400000)  /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE     ((uint32_t)0x00000000)  /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ     ((uint32_t)0x00100000)  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING  ((uint32_t)0x00200000)  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING  ((uint32_t)0x00300000)  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE     ((uint32_t)0x00080000)  /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            ((uint32_t)0x00000000)  /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         ((uint32_t)0x00020000)  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   ((uint32_t)0x00040000)  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    ((uint32_t)0x00060000)  /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE      ((uint32_t)0x00010000)  /* MAC MII transmit engine active */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY             ((uint32_t)0x00000000)  /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD   ((uint32_t)0x00000100)  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD   ((uint32_t)0x00000200)  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL              ((uint32_t)0x00000300)  /* Rx FIFO fill level: full */
+#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
-#if defined(STM32F1)
+#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
-#else
+#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_IDLE               ((uint32_t)0x00000000)  /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#define ETH_MAC_READCONTROLLER_READING_DATA       ((uint32_t)0x00000020)  /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_READCONTROLLER_READING_STATUS     ((uint32_t)0x00000040)  /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
-#endif
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_READCONTROLLER_FLUSHING           ((uint32_t)0x00000060)  /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE     ((uint32_t)0x00000010)  /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE    ((uint32_t)0x00000000)  /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE  ((uint32_t)0x00000002)  /* MAC small FIFO read controller active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004)  /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE    ((uint32_t)0x00000006)  /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   ((uint32_t)0x00000001)  /* MAC MII receive protocol engine active */
 
 /**
   * @}
@@ -2231,26 +2228,26 @@
 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE        __HAL_RCC_USART4_CLK_DISABLE
+#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE         __HAL_RCC_USART4_CLK_ENABLE
+#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_USART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_USART4_CLK_SLEEP_DISABLE 
+#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE 
-#define __USART4_FORCE_RESET        __HAL_RCC_USART4_FORCE_RESET
+#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
-#define __USART4_RELEASE_RESET      __HAL_RCC_USART4_RELEASE_RESET
+#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE        __HAL_RCC_USART5_CLK_DISABLE
+#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE         __HAL_RCC_USART5_CLK_ENABLE
+#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_USART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_USART5_CLK_SLEEP_DISABLE 
+#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE 
-#define __USART5_FORCE_RESET        __HAL_RCC_USART5_FORCE_RESET
+#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
-#define __USART5_RELEASE_RESET      __HAL_RCC_USART5_RELEASE_RESET
+#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE        __HAL_RCC_USART7_CLK_DISABLE
+#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE         __HAL_RCC_USART7_CLK_ENABLE
+#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
-#define __USART7_FORCE_RESET        __HAL_RCC_USART7_FORCE_RESET
+#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
-#define __USART7_RELEASE_RESET      __HAL_RCC_USART7_RELEASE_RESET
+#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE        __HAL_RCC_USART8_CLK_DISABLE
+#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE         __HAL_RCC_USART8_CLK_ENABLE
+#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
-#define __USART8_FORCE_RESET        __HAL_RCC_USART8_FORCE_RESET
+#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
-#define __USART8_RELEASE_RESET      __HAL_RCC_USART8_RELEASE_RESET
+#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
 #define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
 #define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
 #define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
@@ -2784,11 +2781,14 @@
 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
 #define DfsdmClockSelection         Dfsdm1ClockSelection
 #define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
-#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK
+#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
 #define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
 #define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
 #define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
-
+#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
 /**
   * @}
   */
@@ -2918,6 +2918,14 @@
 #define  SDIO_IRQn                  SDMMC1_IRQn
 #define  SDIO_IRQHandler            SDMMC1_IRQHandler
 #endif
+
+#if defined(STM32F7) || defined(STM32F4)
+#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
+#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
+#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
+#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
+#endif
+
 /**
   * @}
   */

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   HAL module driver.
   *          This is the common part of the HAL initialization
   *
@@ -68,11 +68,11 @@
   * @{
   */
 /**
- * @brief STM32F7xx HAL Driver version number V1.1.2
+ * @brief STM32F7xx HAL Driver version number V1.2.0
    */
 #define __STM32F7xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32F7xx_HAL_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
+#define __STM32F7xx_HAL_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
-#define __STM32F7xx_HAL_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
+#define __STM32F7xx_HAL_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
 #define __STM32F7xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32F7xx_HAL_VERSION         ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
                                         |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   This file contains all the functions prototypes for the HAL 
   *          module driver.
   ******************************************************************************

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_adc.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the Analog to Digital Convertor (ADC) peripheral:
   *           + Initialization and de-initialization functions
@@ -270,7 +270,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
   assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
   assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
+  assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
   assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
   assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_adc.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of ADC HAL extension module.
   ******************************************************************************
   * @attention
@@ -88,6 +88,7 @@ typedef struct
                                                     Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
                                        If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
                                                     Scan direction is upward: from rank1 to rank 'n'.
+                                       This parameter can be a value of @ref ADC_Scan_mode.
                                        This parameter can be set to ENABLE or DISABLE */
   uint32_t EOCSelection;          /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
                                        This parameter can be a value of @ref ADC_EOCSelection.
@@ -135,7 +136,8 @@ typedef struct
   uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
                                         This parameter can be a value of @ref ADC_channels */
   uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer.
-                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16 
+                                        This parameter can be a value of @ref ADC_regular_rank */
   uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
                                         Unit: ADC clock cycles
                                         Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
@@ -337,6 +339,38 @@ typedef struct
   * @}
   */ 
 
+/** @defgroup ADC_Scan_mode ADC sequencer scan mode
+  * @{
+  */
+#define ADC_SCAN_DISABLE         ((uint32_t)0x00000000)        /*!< Scan mode disabled */
+#define ADC_SCAN_ENABLE          ((uint32_t)0x00000001)        /*!< Scan mode enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_rank ADC group regular sequencer rank
+  * @{
+  */
+#define ADC_REGULAR_RANK_1    ((uint32_t)0x00000001)       /*!< ADC regular conversion rank 1  */
+#define ADC_REGULAR_RANK_2    ((uint32_t)0x00000002)       /*!< ADC regular conversion rank 2  */
+#define ADC_REGULAR_RANK_3    ((uint32_t)0x00000003)       /*!< ADC regular conversion rank 3  */
+#define ADC_REGULAR_RANK_4    ((uint32_t)0x00000004)       /*!< ADC regular conversion rank 4  */
+#define ADC_REGULAR_RANK_5    ((uint32_t)0x00000005)       /*!< ADC regular conversion rank 5  */
+#define ADC_REGULAR_RANK_6    ((uint32_t)0x00000006)       /*!< ADC regular conversion rank 6  */
+#define ADC_REGULAR_RANK_7    ((uint32_t)0x00000007)       /*!< ADC regular conversion rank 7  */
+#define ADC_REGULAR_RANK_8    ((uint32_t)0x00000008)       /*!< ADC regular conversion rank 8  */
+#define ADC_REGULAR_RANK_9    ((uint32_t)0x00000009)       /*!< ADC regular conversion rank 9  */
+#define ADC_REGULAR_RANK_10   ((uint32_t)0x0000000A)       /*!< ADC regular conversion rank 10 */
+#define ADC_REGULAR_RANK_11   ((uint32_t)0x0000000B)       /*!< ADC regular conversion rank 11 */
+#define ADC_REGULAR_RANK_12   ((uint32_t)0x0000000C)       /*!< ADC regular conversion rank 12 */
+#define ADC_REGULAR_RANK_13   ((uint32_t)0x0000000D)       /*!< ADC regular conversion rank 13 */
+#define ADC_REGULAR_RANK_14   ((uint32_t)0x0000000E)       /*!< ADC regular conversion rank 14 */
+#define ADC_REGULAR_RANK_15   ((uint32_t)0x0000000F)       /*!< ADC regular conversion rank 15 */
+#define ADC_REGULAR_RANK_16   ((uint32_t)0x00000010)       /*!< ADC regular conversion rank 16 */
+/**
+  * @}
+  */
+
 /** @defgroup ADC_channels ADC Common Channels
   * @{
   */ 
@@ -705,7 +739,8 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
 																			((__REGTRIG__) == ADC_SOFTWARE_START))
 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
-                                      ((__ALIGN__) == ADC_DATAALIGN_LEFT))		
+                                      ((__ALIGN__) == ADC_DATAALIGN_LEFT))
+		
                                       									
 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES)   || \
                                       ((__TIME__) == ADC_SAMPLETIME_15CYCLES)  || \
@@ -730,9 +765,29 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
                                             ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
                                             ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
+
+#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) == ADC_REGULAR_RANK_1 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_2 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_3 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_4 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_5 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_6 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_7 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_8 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_9 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_10) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_11) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_12) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_13) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_14) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_15) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_16))
+
+#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
+                                         ((__SCAN_MODE__) == ADC_SCAN_ENABLE))
+
 #define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))
 #define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
-#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)16)))
 #define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))
 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__)                                     \
    ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_adc_ex.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the ADC extension peripheral:
   *           + Extended features functions

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_adc.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of ADC HAL module.
   ******************************************************************************
   * @attention
@@ -217,7 +217,7 @@ typedef struct
   * @}
   */ 
 
-/** @defgroup ADCEx_injected_rank ADC Injected Rank
+/** @defgroup ADCEx_injected_rank ADC Injected Channel Rank
   * @{
   */ 
 #define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001U)
@@ -333,9 +333,12 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO)  || \
                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1)   || \
                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)  || \
-											((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
+					    ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
+#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) == ADC_INJECTED_RANK_1) || \
+                                       ((__RANK__) == ADC_INJECTED_RANK_2) || \
+                                       ((__RANK__) == ADC_INJECTED_RANK_3) || \
+                                       ((__RANK__) == ADC_INJECTED_RANK_4))
 #define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
-#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)4)))
 
 /**
   * @brief  Set the selected injected Channel rank.

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_can.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   CAN HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Controller Area Network (CAN) peripheral:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_can.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of CAN HAL module.
   ******************************************************************************
   * @attention
@@ -232,8 +232,8 @@ typedef struct
 
   HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
 
-  __IO uint32_t               ErrorCode;  /*!< CAN Error code                 */
+  __IO uint32_t               ErrorCode;  /*!< CAN Error code
-
+                                               This parameter can be a value of @ref CAN_Error_Code */
 }CAN_HandleTypeDef;
 
 /**
@@ -245,7 +245,7 @@ typedef struct
   * @{
   */
 
-/** @defgroup HAL_CAN_Error_Code HAL CAN Error Code
+/** @defgroup CAN_Error_Code CAN Error Code
   * @{
   */
 #define   HAL_CAN_ERROR_NONE      0x00U    /*!< No error             */

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cec.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   CEC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the High Definition Multimedia Interface 

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cec.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of CEC HAL module.
   ******************************************************************************
   * @attention
@@ -43,11 +43,11 @@
  extern "C" {
 #endif
 
-#if defined (CEC) 
-
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f7xx_hal_def.h"
 
+#if defined (CEC)
+
 /** @addtogroup STM32F7xx_HAL_Driver
   * @{
   */

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_conf.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_conf.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   HAL configuration file.
   ******************************************************************************
   * @attention
@@ -95,6 +95,8 @@
 #define HAL_DSI_MODULE_ENABLED
 #define HAL_JPEG_MODULE_ENABLED
 #define HAL_MDIOS_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_MMC_MODULE_ENABLED
 
 
 /* ########################## HSE/HSI Values adaptation ##################### */
@@ -103,7 +105,6 @@
   *        This value is used by the RCC HAL module to compute the system frequency
   *        (when HSE is used as system clock source, directly or through the PLL).
   */
-//#if !defined  (HSE_VALUE)
 #if defined(TARGET_DISCO_F746NG) || defined(TARGET_DISCO_F769NI)
   #define HSE_VALUE    25000000U /*!< Value of the External oscillator in Hz */
 #else
@@ -427,6 +428,14 @@
  #include "stm32f7xx_hal_mdios.h"
 #endif /* HAL_MDIOS_MODULE_ENABLED */
 
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f7xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f7xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
 /* Exported macro ------------------------------------------------------------*/
 #ifdef  USE_FULL_ASSERT
 /**

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cortex.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   CORTEX HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the CORTEX:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cortex.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of CORTEX HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_crc.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   CRC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_crc.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of CRC HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_crc_ex.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Extended CRC HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_crc_ex.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of CRC HAL extension module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cryp.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of CRYP HAL module.
   ******************************************************************************
   * @attention
@@ -527,6 +527,638 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
   * @}
   */ 
   
+#if defined (AES)
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRYP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Types CRYP Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  CRYP Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t DataType;       /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+                             This parameter can be a value of @ref CRYP_Data_Type */
+
+  uint32_t KeySize;        /*!< 128 or 256-bit key length. 
+                             This parameter can be a value of @ref CRYP_Key_Size */
+                             
+  uint32_t OperatingMode;  /*!< AES operating mode. 
+                             This parameter can be a value of @ref CRYP_AES_OperatingMode */
+                             
+  uint32_t ChainingMode;   /*!< AES chaining mode. 
+                             This parameter can be a value of @ref CRYP_AES_ChainingMode */
+                             
+  uint32_t KeyWriteFlag;   /*!< Allows to bypass or not key write-up before decryption. 
+                             This parameter can be a value of @ref CRYP_Key_Write */                             
+                             
+  uint32_t GCMCMACPhase;   /*!< Indicates the processing phase of the Galois Counter Mode (GCM), 
+                             Galois Message Authentication Code (GMAC) or Cipher Message 
+                             Authentication Code (CMAC) or Counter with Cipher Mode (CCM) when
+                             the latter is applicable.
+                             This parameter can be a value of @ref CRYP_GCM_CMAC_Phase */                                                                                          
+
+  uint8_t* pKey;           /*!< Encryption/Decryption Key */
+
+  uint8_t* pInitVect;      /*!< Initialization Vector used for CTR, CBC, GCM/GMAC, CMAC, 
+                                (and CCM when applicable) modes */
+
+  uint8_t* Header;         /*!< Header used in GCM/GMAC, CMAC (and CCM when applicable) modes */
+
+  uint64_t HeaderSize;     /*!< Header size in bytes */
+                                                     
+}CRYP_InitTypeDef;
+
+/** 
+  * @brief HAL CRYP State structures definition
+  */
+typedef enum
+{
+  HAL_CRYP_STATE_RESET             = 0x00,  /*!< CRYP not yet initialized or disabled  */
+  HAL_CRYP_STATE_READY             = 0x01,  /*!< CRYP initialized and ready for use    */
+  HAL_CRYP_STATE_BUSY              = 0x02,  /*!< CRYP internal processing is ongoing   */
+  HAL_CRYP_STATE_TIMEOUT           = 0x03,  /*!< CRYP timeout state                    */
+  HAL_CRYP_STATE_ERROR             = 0x04,  /*!< CRYP error state                      */
+  HAL_CRYP_STATE_SUSPENDED         = 0x05   /*!< CRYP suspended                        */
+}HAL_CRYP_STATETypeDef;
+
+/** 
+  * @brief HAL CRYP phase structures definition
+  */
+typedef enum
+{
+  HAL_CRYP_PHASE_READY             = 0x01,    /*!< CRYP peripheral is ready for initialization.           */
+  HAL_CRYP_PHASE_PROCESS           = 0x02,    /*!< CRYP peripheral is in processing phase                 */
+  HAL_CRYP_PHASE_START             = 0x03,    /*!< CRYP peripheral has been initialized but 
+                                                 GCM/GMAC/CMAC(/CCM) initialization phase has not started */
+  HAL_CRYP_PHASE_INIT_OVER         = 0x04,    /*!< GCM/GMAC/CMAC(/CCM) init phase has been carried out    */ 
+  HAL_CRYP_PHASE_HEADER_OVER       = 0x05,    /*!< GCM/GMAC/CMAC(/CCM) header phase has been carried out  */ 
+  HAL_CRYP_PHASE_PAYLOAD_OVER      = 0x06,    /*!< GCM(/CCM) payload phase has been carried out           */ 
+  HAL_CRYP_PHASE_FINAL_OVER        = 0x07,    /*!< GCM/GMAC/CMAC(/CCM) final phase has been carried out   */
+  HAL_CRYP_PHASE_HEADER_SUSPENDED  = 0x08,    /*!< GCM/GMAC/CMAC(/CCM) header phase has been suspended    */
+  HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09,    /*!< GCM(/CCM) payload phase has been suspended             */  
+  HAL_CRYP_PHASE_NOT_USED          = 0x0a     /*!< Phase is irrelevant to the current chaining mode       */                                                                                                                                                                                                                                                                   
+}HAL_PhaseTypeDef;
+
+/** 
+  * @brief HAL CRYP mode suspend definitions
+  */
+typedef enum
+{
+  HAL_CRYP_SUSPEND_NONE            = 0x00,    /*!< CRYP peripheral suspension not requested */
+  HAL_CRYP_SUSPEND                 = 0x01     /*!< CRYP peripheral suspension requested     */                                                                                                                                                                                                                                                                  
+}HAL_SuspendTypeDef;
+
+
+/** 
+  * @brief  HAL CRYP Error Codes definition  
+  */ 
+#define HAL_CRYP_ERROR_NONE      ((uint32_t)0x00000000)  /*!< No error        */
+#define HAL_CRYP_WRITE_ERROR     ((uint32_t)0x00000001)  /*!< Write error     */
+#define HAL_CRYP_READ_ERROR      ((uint32_t)0x00000002)  /*!< Read error      */
+#define HAL_CRYP_DMA_ERROR       ((uint32_t)0x00000004)  /*!< DMA error       */  
+#define HAL_CRYP_BUSY_ERROR      ((uint32_t)0x00000008)  /*!< Busy flag error */  
+
+/** 
+  * @brief  CRYP handle Structure definition
+  */ 
+typedef struct
+{
+      AES_TypeDef              *Instance;        /*!< Register base address        */
+
+      CRYP_InitTypeDef         Init;             /*!< CRYP initialization parameters */
+
+      uint8_t                  *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) input buffer */
+
+      uint8_t                  *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) output buffer */
+
+      uint32_t                 CrypInCount;      /*!< Input data size in bytes or, after suspension, the remaining 
+                                                       number of bytes to process */
+
+      uint32_t                 CrypOutCount;     /*!< Output data size in bytes */
+
+      HAL_PhaseTypeDef         Phase;            /*!< CRYP peripheral processing phase for GCM, GMAC, CMAC 
+                                                    (or CCM when applicable) modes.
+                                                     Indicates the last phase carried out to ease
+                                                     phase transitions  */
+
+      DMA_HandleTypeDef        *hdmain;          /*!< CRYP peripheral Input DMA handle parameters */
+
+      DMA_HandleTypeDef        *hdmaout;         /*!< CRYP peripheral Output DMA handle parameters */
+
+      HAL_LockTypeDef          Lock;             /*!< CRYP locking object */
+
+   __IO  HAL_CRYP_STATETypeDef State;            /*!< CRYP peripheral state */
+   
+    __IO uint32_t              ErrorCode;        /*!< CRYP peripheral error code */
+     
+     HAL_SuspendTypeDef        SuspendRequest;   /*!< CRYP peripheral suspension request flag */     
+}CRYP_HandleTypeDef;
+
+/** 
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
+  * @{
+  */
+
+/** @defgroup CRYP_Key_Size  Key size selection
+  * @{
+  */
+#define CRYP_KEYSIZE_128B         ((uint32_t)0x00000000)  /*!< 128-bit long key */ 
+#define CRYP_KEYSIZE_256B         AES_CR_KEYSIZE          /*!< 256-bit long key */ 
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Data_Type  AES Data Type selection
+  * @{
+  */
+#define CRYP_DATATYPE_32B         ((uint32_t)0x00000000)  /*!< 32-bit data type (no swapping)        */
+#define CRYP_DATATYPE_16B         AES_CR_DATATYPE_0       /*!< 16-bit data type (half-word swapping) */
+#define CRYP_DATATYPE_8B          AES_CR_DATATYPE_1       /*!< 8-bit data type (byte swapping)       */
+#define CRYP_DATATYPE_1B          AES_CR_DATATYPE         /*!< 1-bit data type (bit swapping)        */
+/**
+  * @}
+  */
+  
+ /** @defgroup CRYP_AES_State  AES Enable state
+  * @{
+  */ 
+#define CRYP_AES_DISABLE                 ((uint32_t)0x00000000)   /*!< Disable AES */
+#define CRYP_AES_ENABLE                   AES_CR_EN               /*!< Enable AES  */
+/**
+  * @}
+  */            
+  
+/** @defgroup CRYP_AES_OperatingMode AES operating mode
+  * @{
+  */ 
+#define CRYP_ALGOMODE_ENCRYPT                   ((uint32_t)0x00000000)  /*!< Encryption mode                            */
+#define CRYP_ALGOMODE_KEYDERIVATION             AES_CR_MODE_0           /*!< Key derivation mode                        */
+#define CRYP_ALGOMODE_DECRYPT                   AES_CR_MODE_1           /*!< Decryption                                 */
+#define CRYP_ALGOMODE_KEYDERIVATION_DECRYPT     AES_CR_MODE             /*!< Key derivation and decryption              */
+#define CRYP_ALGOMODE_TAG_GENERATION            ((uint32_t)0x00000000)  /*!< GMAC or CMAC authentication tag generation */
+/**
+  * @}
+  */                   
+
+/** @defgroup CRYP_AES_ChainingMode AES chaining mode
+  * @{
+  */                                                                
+#define CRYP_CHAINMODE_AES_ECB            ((uint32_t)0x00000000)            /*!< Electronic codebook chaining algorithm                   */
+#define CRYP_CHAINMODE_AES_CBC            AES_CR_CHMOD_0                    /*!< Cipher block chaining algorithm                          */
+#define CRYP_CHAINMODE_AES_CTR            AES_CR_CHMOD_1                    /*!< Counter mode chaining algorithm                          */
+#define CRYP_CHAINMODE_AES_GCM_GMAC       (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
+#define CRYP_CHAINMODE_AES_CMAC           AES_CR_CHMOD_2                    /*!< Cipher message authentication code                       */
+#if defined(AES_CR_NPBLB)
+#define CRYP_CHAINMODE_AES_CCM_CMAC       AES_CR_CHMOD_2                    /*!< Counter with Cipher Mode - Cipher message authentication code */  
+#endif
+/**         
+  * @}
+  */
+  
+/** @defgroup CRYP_Key_Write AES decryption key write-up flag
+  * @{
+  */ 
+#define CRYP_KEY_WRITE_ENABLE            ((uint32_t)0x00000000)  /*!< Enable decryption key writing  */ 
+#define CRYP_KEY_WRITE_DISABLE           ((uint32_t)0x00000001)  /*!< Disable decryption key writing */ 
+/**
+  * @}
+  */  
+  
+/** @defgroup CRYP_DMAIN DMA Input phase management enable state
+  * @{
+  */
+#define CRYP_DMAIN_DISABLE             ((uint32_t)0x00000000)    /*!< Disable DMA Input phase management */
+#define CRYP_DMAIN_ENABLE              AES_CR_DMAINEN            /*!< Enable DMA Input phase management  */
+/**
+  * @}
+  */
+  
+/** @defgroup CRYP_DMAOUT DMA Output phase management enable state
+  * @{
+  */
+#define CRYP_DMAOUT_DISABLE             ((uint32_t)0x00000000)   /*!< Disable DMA Output phase management */
+#define CRYP_DMAOUT_ENABLE              AES_CR_DMAOUTEN          /*!< Enable DMA Output phase management  */
+/**
+  * @}
+  */  
+  
+  
+/** @defgroup CRYP_GCM_CMAC_Phase GCM/GMAC and CMAC processing phase selection
+  * @{
+  */
+#define CRYP_GCM_INIT_PHASE             ((uint32_t)0x00000000)  /*!< GCM/GMAC (or CCM) init phase        */ 
+#define CRYP_GCMCMAC_HEADER_PHASE       AES_CR_GCMPH_0          /*!< GCM/GMAC or (CCM/)CMAC header phase */ 
+#define CRYP_GCM_PAYLOAD_PHASE          AES_CR_GCMPH_1          /*!< GCM(/CCM) payload phase             */ 
+#define CRYP_GCMCMAC_FINAL_PHASE        AES_CR_GCMPH            /*!< GCM/GMAC or (CCM/)CMAC final phase  */ 
+/* Definitions duplication for code readibility's sake: 
+   supported or not supported chain modes are not specified for each phase */
+#define CRYP_INIT_PHASE                 ((uint32_t)0x00000000)  /*!< Init phase    */ 
+#define CRYP_HEADER_PHASE               AES_CR_GCMPH_0          /*!< Header phase  */ 
+#define CRYP_PAYLOAD_PHASE              AES_CR_GCMPH_1          /*!< Payload phase */ 
+#define CRYP_FINAL_PHASE                AES_CR_GCMPH            /*!< Final phase   */ 
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Flags   AES status flags
+  * @{
+  */
+
+#define CRYP_FLAG_BUSY    AES_SR_BUSY   /*!< GCM process suspension forbidden */
+#define CRYP_FLAG_WRERR   AES_SR_WRERR  /*!< Write Error                      */
+#define CRYP_FLAG_RDERR   AES_SR_RDERR  /*!< Read error                       */
+#define CRYP_FLAG_CCF     AES_SR_CCF    /*!< Computation completed            */
+/**
+  * @}
+  */
+  
+/** @defgroup CRYP_Clear_Flags   AES clearing flags
+  * @{
+  */
+
+#define CRYP_CCF_CLEAR    AES_CR_CCFC   /*!< Computation Complete Flag Clear */
+#define CRYP_ERR_CLEAR    AES_CR_ERRC   /*!< Error Flag Clear                */
+/**
+  * @}
+  */
+
+/** @defgroup AES_Interrupts_Enable AES Interrupts Enable bits
+  * @{
+  */ 
+#define CRYP_IT_CCFIE                         AES_CR_CCFIE /*!< Computation Complete interrupt enable */
+#define CRYP_IT_ERRIE                         AES_CR_ERRIE /*!< Error interrupt enable                */
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Interrupts_Flags   AES Interrupts flags
+  * @{
+  */
+#define CRYP_IT_WRERR   AES_SR_WRERR  /*!< Write Error           */
+#define CRYP_IT_RDERR   AES_SR_RDERR  /*!< Read Error            */
+#define CRYP_IT_CCF     AES_SR_CCF    /*!< Computation completed */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
+  * @{
+  */
+
+/** @brief Reset CRYP handle state.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @retval None
+  */
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+
+/**
+  * @brief  Enable the CRYP AES peripheral.
+  * @retval None
+  */
+#define __HAL_CRYP_ENABLE()  (AES->CR |=  AES_CR_EN)
+
+/**
+  * @brief  Disable the CRYP AES peripheral.
+  * @retval None
+  */
+#define __HAL_CRYP_DISABLE() (AES->CR &=  ~AES_CR_EN)
+
+/**
+  * @brief  Set the algorithm operating mode.
+  * @param  __OPERATING_MODE__: specifies the operating mode
+  *          This parameter can be one of the following values:
+  *            @arg @ref CRYP_ALGOMODE_ENCRYPT encryption     
+  *            @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation        
+  *            @arg @ref CRYP_ALGOMODE_DECRYPT decryption 
+  *            @arg @ref CRYP_ALGOMODE_KEYDERIVATION_DECRYPT key derivation and decryption  
+  * @retval None
+  */
+#define __HAL_CRYP_SET_OPERATINGMODE(__OPERATING_MODE__) MODIFY_REG(AES->CR, AES_CR_MODE, (__OPERATING_MODE__))  
+
+
+/**
+  * @brief  Set the algorithm chaining mode.
+  * @param  __CHAINING_MODE__: specifies the chaining mode
+  *          This parameter can be one of the following values:
+  *            @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook     
+  *            @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining        
+  *            @arg @ref CRYP_CHAINMODE_AES_CTR CounTeR mode
+  *            @arg @ref CRYP_CHAINMODE_AES_GCM_GMAC Galois Counter Mode or Galois Message Authentication Code     
+  *            @arg @ref CRYP_CHAINMODE_AES_CMAC Cipher Message Authentication Code (or Counter with Cipher Mode when applicable)
+  * @retval None
+  */
+#define __HAL_CRYP_SET_CHAININGMODE(__CHAINING_MODE__) MODIFY_REG(AES->CR, AES_CR_CHMOD, (__CHAINING_MODE__))  
+
+
+
+/** @brief  Check whether the specified CRYP status flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden  
+  *            @arg @ref CRYP_IT_WRERR Write Error 
+  *            @arg @ref CRYP_IT_RDERR Read Error 
+  *            @arg @ref CRYP_IT_CCF Computation Complete                 
+  * @retval The state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_CRYP_GET_FLAG(__FLAG__) ((AES->SR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief  Clear the CRYP pending status flag.
+  * @param  __FLAG__: specifies the flag to clear.
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
+  *            @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear  
+  * @retval None
+  */
+#define __HAL_CRYP_CLEAR_FLAG(__FLAG__) SET_BIT(AES->CR, (__FLAG__))
+
+
+
+/** @brief  Check whether the specified CRYP interrupt source is enabled or not.
+  * @param __INTERRUPT__: CRYP interrupt source to check
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
+  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt  
+  * @retval State of interruption (TRUE or FALSE).
+  */
+#define __HAL_CRYP_GET_IT_SOURCE(__INTERRUPT__) ((AES->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+
+/** @brief  Check whether the specified CRYP interrupt is set or not.
+  * @param  __INTERRUPT__: specifies the interrupt to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_IT_WRERR Write Error 
+  *            @arg @ref CRYP_IT_RDERR Read Error 
+  *            @arg @ref CRYP_IT_CCF  Computation Complete                 
+  * @retval The state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_CRYP_GET_IT(__INTERRUPT__) ((AES->SR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+
+
+/** @brief  Clear the CRYP pending interrupt.
+  * @param  __INTERRUPT__: specifies the IT to clear.
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
+  *            @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear    
+  * @retval None
+  */
+#define __HAL_CRYP_CLEAR_IT(__INTERRUPT__) SET_BIT(AES->CR, (__INTERRUPT__))
+
+
+/**
+  * @brief  Enable the CRYP interrupt.  
+  * @param  __INTERRUPT__: CRYP Interrupt.
+  *         This parameter can be one of the following values:  
+  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
+  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt    
+  * @retval None
+  */
+#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((AES->CR) |= (__INTERRUPT__))
+
+
+/**
+  * @brief  Disable the CRYP interrupt.
+  * @param  __INTERRUPT__: CRYP Interrupt.
+  *         This parameter can be one of the following values:  
+  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
+  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt    
+  * @retval None
+  */
+#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((AES->CR) &= ~(__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup  CRYP_Private_Macros   CRYP Private Macros
+  * @{
+  */
+
+/**
+  * @brief Verify the key size length.
+  * @param __KEYSIZE__: Ciphering/deciphering algorithm key size. 
+  * @retval SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid)
+  */  
+#define IS_CRYP_KEYSIZE(__KEYSIZE__)  (((__KEYSIZE__) == CRYP_KEYSIZE_128B)  || \
+                                       ((__KEYSIZE__) == CRYP_KEYSIZE_256B))
+
+/**
+  * @brief Verify the input data type.
+  * @param __DATATYPE__: Ciphering/deciphering algorithm input data type.
+  * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
+  */  
+#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
+                                        ((__DATATYPE__) == CRYP_DATATYPE_16B) || \
+                                        ((__DATATYPE__) == CRYP_DATATYPE_8B)  || \
+                                        ((__DATATYPE__) == CRYP_DATATYPE_1B))
+
+/**
+  * @brief Verify the CRYP AES IP running mode.
+  * @param __MODE__: CRYP AES IP running mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */                                     
+#define IS_CRYP_AES(__MODE__) (((__MODE__) == CRYP_AES_DISABLE) || \
+                               ((__MODE__) == CRYP_AES_ENABLE)) 
+
+/**
+  * @brief Verify the selected CRYP algorithm.
+  * @param __ALGOMODE__: Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter).
+  * @retval SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid)
+  */                            
+#define IS_CRYP_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT)        || \
+                                        ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION)  || \
+                                        ((__ALGOMODE__) == CRYP_ALGOMODE_DECRYPT)        || \
+                                        ((__ALGOMODE__) == CRYP_ALGOMODE_TAG_GENERATION) || \
+                                        ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT))  
+
+/**
+  * @brief Verify the selected CRYP chaining algorithm.
+  * @param __CHAINMODE__: Selected CRYP chaining algorithm.
+  * @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid)
+  */   
+#if defined(AES_CR_NPBLB)
+#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB)     || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC)      || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR)      || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CCM_CMAC))   
+#else
+#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB)     || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC)      || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR)      || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC))    
+#endif                                
+
+/**
+  * @brief Verify the deciphering key write option.
+  * @param __WRITE__: deciphering key write option.
+  * @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid)
+  */                                   
+#define IS_CRYP_WRITE(__WRITE__)   (((__WRITE__) == CRYP_KEY_WRITE_ENABLE)      || \
+                                    ((__WRITE__) == CRYP_KEY_WRITE_DISABLE))
+
+/**
+  * @brief Verify the CRYP input data DMA mode.
+  * @param __MODE__: CRYP input data DMA mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */  
+#define IS_CRYP_DMAIN(__MODE__) (((__MODE__) == CRYP_DMAIN_DISABLE) || \
+                                 ((__MODE__) == CRYP_DMAIN_ENABLE)) 
+
+/**
+  * @brief Verify the CRYP output data DMA mode.
+  * @param __MODE__: CRYP output data DMA mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */                             
+#define IS_CRYP_DMAOUT(__MODE__) (((__MODE__) == CRYP_DMAOUT_DISABLE) || \
+                                  ((__MODE__) == CRYP_DMAOUT_ENABLE)) 
+
+/**
+  * @brief Verify the CRYP AES ciphering/deciphering/authentication algorithm phase.
+  * @param __PHASE__: CRYP AES ciphering/deciphering/authentication algorithm phase.
+  * @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid)
+  */                               
+#define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_GCM_INIT_PHASE)       || \
+                                          ((__PHASE__) == CRYP_GCMCMAC_HEADER_PHASE) || \
+                                          ((__PHASE__) == CRYP_GCM_PAYLOAD_PHASE)    || \
+                                          ((__PHASE__) == CRYP_GCMCMAC_FINAL_PHASE))
+                                      
+/**
+  * @}
+  */
+
+/* Include CRYP HAL Extended module */
+#include "stm32f7xx_hal_cryp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRYP_Exported_Functions CRYP Exported Functions
+  * @{
+  */
+  
+/** @addtogroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions
+  * @{
+  */
+    
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
+
+/* MSP initialization/de-initialization functions  ****************************/
+void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+  
+/** @addtogroup CRYP_Exported_Functions_Group2 AES processing functions 
+  * @{
+  */  
+
+/* AES encryption/decryption processing functions  ****************************/
+
+/* AES encryption/decryption using polling  ***********************************/
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+
+/* AES encryption/decryption using interrupt  *********************************/
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* AES encryption/decryption using DMA  ***************************************/
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/**
+  * @}
+  */
+  
+/** @addtogroup CRYP_Exported_Functions_Group3 Callback functions
+  * @{
+  */ 
+/* CallBack functions  ********************************************************/
+void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);  
+  
+/**
+  * @}
+  */
+  
+/** @addtogroup CRYP_Exported_Functions_Group4 CRYP IRQ handler 
+  * @{
+  */    
+
+/* AES interrupt handling function  *******************************************/
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+  
+/** @addtogroup CRYP_Exported_Functions_Group5 Peripheral State functions 
+  * @{
+  */
+
+/* Peripheral State functions  ************************************************/
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+uint32_t              HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#endif /* AES */  
+
+  
 #ifdef __cplusplus
 }
 #endif

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cryp_ex.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of CRYP HAL Extension module.
   ******************************************************************************
   * @attention
@@ -209,6 +209,76 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);
 
 #endif /* CRYP */
 
+#if defined (AES)
+
+/** @addtogroup CRYPEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* CallBack functions  ********************************************************/
+void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */ 
+
+/** @addtogroup CRYPEx_Exported_Functions_Group2
+  * @{
+  */
+
+/* AES encryption/decryption processing functions  ****************************/
+HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp,  uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
+HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp,  uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
+
+/* AES encryption/decryption/authentication processing functions  *************/
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
+
+/**
+  * @}
+  */ 
+
+/** @addtogroup CRYPEx_Exported_Functions_Group3
+  * @{
+  */
+
+/* AES suspension/resumption functions  ***************************************/
+void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
+void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
+void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
+void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
+void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize);
+void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize);
+void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
+void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
+void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */  
+  
+
+/**
+  * @}
+  */ 
+  
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup CRYPEx_Private_Functions CRYPEx Private Functions
+  * @{
+  */
+HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+ 
+#endif /* AES */
 
 /**
   * @}

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dac.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   DAC HAL module driver.
   *         This file provides firmware functions to manage the following 
   *         functionalities of the Digital to Analog Converter (DAC) peripheral:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dac.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of DAC HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dac_ex.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Extended DAC HAL module driver.
   *         This file provides firmware functions to manage the following 
   *         functionalities of DAC extension peripheral:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dac.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of DAC HAL Extension module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dcmi.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   DCMI HAL module driver
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Digital Camera Interface (DCMI) peripheral:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dcmi.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of DCMI HAL module.
   ******************************************************************************
   * @attention
@@ -43,10 +43,10 @@
  extern "C" {
 #endif
 
-#if defined (DCMI)
-
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f7xx_hal_def.h"
+
+#if defined (DCMI)
  
 /** @addtogroup STM32F7xx_HAL_Driver
   * @{

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dcmi_ex.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Empty file; This file is no longer used to handle the Black&White
   *          feature. Its content is now moved to common files
   *          (stm32f7xx_hal_dcmi.c/.h) as there's no device's dependency within F7

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dcmi_ex.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of DCMI Extension HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_def.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_def.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   This file contains HAL common defines, enumeration, macros and 
   *          structures definitions. 
   ******************************************************************************

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dfsdm.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the Digital Filter for Sigma-Delta Modulators
   *          (DFSDM) peripherals:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dfsdm.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of DFSDM HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   DMA HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of DMA HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma2d.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   DMA2D HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the DMA2D peripheral:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma2d.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of DMA2D HAL module.
   ******************************************************************************
   * @attention
@@ -43,11 +43,11 @@
  extern "C" {
 #endif
 
-#if defined (DMA2D)
-
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f7xx_hal_def.h"
 
+#if defined (DMA2D)
+
 /** @addtogroup STM32F7xx_HAL_Driver
   * @{
   */

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma_ex.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   DMA Extension HAL module driver
   *         This file provides firmware functions to manage the following 
   *         functionalities of the DMA Extension peripheral:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma_ex.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of DMA HAL extension module.
   ******************************************************************************
   * @attention
@@ -93,7 +93,9 @@ typedef enum
 #define DMA_CHANNEL_5        ((uint32_t)0x0A000000U)  /*!< DMA Channel 5 */
 #define DMA_CHANNEL_6        ((uint32_t)0x0C000000U)  /*!< DMA Channel 6 */
 #define DMA_CHANNEL_7        ((uint32_t)0x0E000000U)  /*!< DMA Channel 7 */
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
+    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
+    defined (STM32F779xx)
 #define DMA_CHANNEL_8        ((uint32_t)0x10000000U)  /*!< DMA Channel 8 */
 #define DMA_CHANNEL_9        ((uint32_t)0x12000000U)  /*!< DMA Channel 9 */
 #define DMA_CHANNEL_10       ((uint32_t)0x14000000U)  /*!< DMA Channel 10*/
@@ -102,7 +104,8 @@ typedef enum
 #define DMA_CHANNEL_13       ((uint32_t)0x1A000000U)  /*!< DMA Channel 13*/
 #define DMA_CHANNEL_14       ((uint32_t)0x1C000000U)  /*!< DMA Channel 14*/
 #define DMA_CHANNEL_15       ((uint32_t)0x1E000000U)  /*!< DMA Channel 15*/
-#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
+          STM32F769xx || STM32F777xx || STM32F779xx */
 
 /**
   * @}
@@ -140,7 +143,9 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre
   * @brief    DMAEx private macros 
   * @{
   */
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
+    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
+    defined (STM32F779xx)
 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0)  || \
                                  ((CHANNEL) == DMA_CHANNEL_1)  || \
                                  ((CHANNEL) == DMA_CHANNEL_2)  || \
@@ -166,7 +171,8 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre
                                  ((CHANNEL) == DMA_CHANNEL_5) || \
                                  ((CHANNEL) == DMA_CHANNEL_6) || \
                                  ((CHANNEL) == DMA_CHANNEL_7))
-#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
+          STM32F769xx || STM32F777xx || STM32F779xx */
 /**
   * @}
   */  

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dsi.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   DSI HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the DSI peripheral:
@@ -605,11 +605,7 @@ __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
 @verbatim
  ===============================================================================
                     ##### Peripheral Control functions #####
- ===============================================================================  
+ ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) 
-      (+) 
-      (+) 
 
 @endverbatim
   * @{

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dsi.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of DSI HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_eth.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   ETH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Ethernet (ETH) peripheral:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_eth.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of ETH HAL module.
   ******************************************************************************
   * @attention
@@ -43,11 +43,11 @@
  extern "C" {
 #endif
 
-#if defined (ETH)   
-
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f7xx_hal_def.h"
 
+#if defined (ETH)
+
 /** @addtogroup STM32F7xx_HAL_Driver
   * @{
   */

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_flash.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   FLASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the internal FLASH memory:
@@ -801,6 +801,13 @@ static void FLASH_SetErrorCode(void)
     pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS;
   }
   
+#if defined (FLASH_OPTCR2_PCROP)
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
+  { 
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
+  }  
+#endif /* FLASH_OPTCR2_PCROP */
+  
   /* Clear error programming flags */
   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);
 }

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_flash.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of FLASH HAL module.
   ******************************************************************************
   * @attention
@@ -111,6 +111,7 @@ typedef struct
 #define HAL_FLASH_ERROR_PGA          ((uint32_t)0x00000008U)    /*!< Programming Alignment error   */
 #define HAL_FLASH_ERROR_WRP          ((uint32_t)0x00000010U)    /*!< Write protection error        */
 #define HAL_FLASH_ERROR_OPERATION    ((uint32_t)0x00000020U)    /*!< Operation Error               */
+#define HAL_FLASH_ERROR_RD           ((uint32_t)0x00000040U)    /*!< Read Protection Error         */
 /**
   * @}
   */
@@ -138,9 +139,14 @@ typedef struct
 #define FLASH_FLAG_ERSERR              FLASH_SR_ERSERR         /*!< FLASH Erasing Sequence error flag         */
 #define FLASH_FLAG_BSY                 FLASH_SR_BSY            /*!< FLASH Busy flag                           */
 
-
+#if defined (FLASH_OPTCR2_PCROP)
+#define FLASH_FLAG_RDERR               FLASH_SR_RDERR          /*!< FLASH Read protection error flag          */
+#define FLASH_FLAG_ALL_ERRORS     (FLASH_FLAG_OPERR   | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+                                   FLASH_FLAG_PGPERR  | FLASH_FLAG_ERSERR | FLASH_FLAG_RDERR)
+#else
 #define FLASH_FLAG_ALL_ERRORS     (FLASH_FLAG_OPERR   | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
                                    FLASH_FLAG_PGPERR  | FLASH_FLAG_ERSERR)
+#endif /* FLASH_OPTCR2_PCROP */
 /**
   * @}
   */

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_flash_ex.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Extended FLASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the FLASH extension peripheral:
@@ -131,6 +131,13 @@ static void               FLASH_MassErase(uint8_t VoltageRange);
 static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);
 #endif /* FLASH_OPTCR_nDBANK */
 
+#if defined (FLASH_OPTCR2_PCROP)
+static HAL_StatusTypeDef  FLASH_OB_PCROP_Config(uint32_t PCROPSector);
+static HAL_StatusTypeDef  FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp);
+static uint32_t           FLASH_OB_GetPCROP(void);
+static uint32_t           FLASH_OB_GetPCROPRDP(void);
+#endif /* FLASH_OPTCR2_PCROP */
+
 extern HAL_StatusTypeDef  FLASH_WaitForLastOperation(uint32_t Timeout);
 /**
   * @}
@@ -366,6 +373,20 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
   {
     status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1);
   }
+  
+#if defined (FLASH_OPTCR2_PCROP)
+  /* PCROP configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)
+  {
+    status = FLASH_OB_PCROP_Config(pOBInit->PCROPSector);
+  }
+  
+  /* PCROP_RDP configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_PCROP_RDP) == OPTIONBYTE_PCROP_RDP)
+  {
+    status = FLASH_OB_PCROP_RDP_Config(pOBInit->PCROPRdp);
+  }
+#endif /* FLASH_OPTCR2_PCROP */
 
   /* Process Unlocked */
   __HAL_UNLOCK(&pFlash);
@@ -402,6 +423,14 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
   
   /*Get Boot Address when Boot pin = 1 */
   pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);
+
+#if defined (FLASH_OPTCR2_PCROP)
+  /*Get PCROP Sectors */
+  pOBInit->PCROPSector = FLASH_OB_GetPCROP();
+  
+  /*Get PCROP_RDP Value */
+  pOBInit->PCROPRdp = FLASH_OB_GetPCROPRDP();
+#endif /* FLASH_OPTCR2_PCROP */
 }
 /**
   * @}
@@ -1021,6 +1050,79 @@ static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption)
   return Address;
 }
 
+#if defined (FLASH_OPTCR2_PCROP)
+/**
+  * @brief  Set the PCROP protection for sectors.
+  * @param  PCROPSector: specifies the sector(s) to be PCROP protected.
+  *         This parameter can be one of the following values:
+  *            @arg OB_PCROP_SECTOR_x: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_7
+  *            @arg OB_PCROP_SECTOR_ALL
+  *    
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_PCROP_SECTOR(PCROPSector));
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  { 
+    MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP, PCROPSector);
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Set the PCROP_RDP value
+  * @param  Pcrop_Rdp: specifies the PCROP_RDP bit value.
+  *    
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_PCROP_RDP_VALUE(Pcrop_Rdp));
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  { 
+    MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP_RDP, Pcrop_Rdp);
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Return the FLASH PCROP Protection Option Bytes value.
+  * @retval uint32_t FLASH PCROP Protection Option Bytes value
+  */
+static uint32_t FLASH_OB_GetPCROP(void)
+{
+  /* Return the FLASH write protection Register value */
+  return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP));
+}
+
+/**
+  * @brief  Return the FLASH PCROP_RDP option byte value.
+  * @retval uint32_t FLASH PCROP_RDP option byte value
+  */
+static uint32_t FLASH_OB_GetPCROPRDP(void)
+{
+  /* Return the FLASH write protection Register value */
+  return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP_RDP));
+}
+#endif /* FLASH_OPTCR2_PCROP */
+
 /**
   * @}
   */

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_flash_ex.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of FLASH HAL Extension module.
   ******************************************************************************
   * @attention
@@ -113,6 +113,14 @@ typedef struct
   uint32_t BootAddr1;    /*!< Boot base address when Boot pin = 1.
                               This parameter can be a value of @ref FLASHEx_Boot_Address */
 
+#if defined (FLASH_OPTCR2_PCROP)
+  uint32_t PCROPSector;  /*!< Set the PCROP sector.
+                              This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_Sectors */
+
+  uint32_t PCROPRdp;    /*!< Set the PCROP_RDP option.
+                              This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_RDP */                                
+#endif /* FLASH_OPTCR2_PCROP */
+
 } FLASH_OBProgramInitTypeDef;
 
 /**
@@ -162,6 +170,10 @@ typedef struct
 #define OPTIONBYTE_BOR         ((uint32_t)0x08U)  /*!< BOR option byte configuration  */
 #define OPTIONBYTE_BOOTADDR_0  ((uint32_t)0x10U)  /*!< Boot 0 Address configuration   */
 #define OPTIONBYTE_BOOTADDR_1  ((uint32_t)0x20U)  /*!< Boot 1 Address configuration   */
+#if defined (FLASH_OPTCR2_PCROP)
+#define OPTIONBYTE_PCROP       ((uint32_t)0x40U)  /*!< PCROP configuration            */
+#define OPTIONBYTE_PCROP_RDP   ((uint32_t)0x80U)  /*!< PCROP_RDP configuration        */
+#endif /* FLASH_OPTCR2_PCROP */
 /**
   * @}
   */
@@ -275,7 +287,11 @@ typedef struct
 #define OB_BOOTADDR_AXIM_FLASH       ((uint32_t)0x2000U)  /*!< Boot from Flash on AXIM interface (0x08000000)  */
 #define OB_BOOTADDR_DTCM_RAM         ((uint32_t)0x8000U)  /*!< Boot from DTCM RAM (0x20000000)                 */
 #define OB_BOOTADDR_SRAM1            ((uint32_t)0x8004U)  /*!< Boot from SRAM1 (0x20010000)                    */
+#if (SRAM2_BASE == 0x2003C000U)
+#define OB_BOOTADDR_SRAM2            ((uint32_t)0x800FU)  /*!< Boot from SRAM2 (0x2003C000)                    */
+#else
 #define OB_BOOTADDR_SRAM2            ((uint32_t)0x8013U)  /*!< Boot from SRAM2 (0x2004C000)                    */
+#endif /* SRAM2_BASE == 0x2003C000U */
 /**
   * @}
   */
@@ -426,6 +442,33 @@ typedef struct
   */
 #endif /* FLASH_SECTOR_TOTAL == 8 */
 
+#if defined (FLASH_OPTCR2_PCROP)
+/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors
+  * @{
+  */
+#define OB_PCROP_SECTOR_0     ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0      */
+#define OB_PCROP_SECTOR_1     ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1      */
+#define OB_PCROP_SECTOR_2     ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2      */
+#define OB_PCROP_SECTOR_3     ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3      */
+#define OB_PCROP_SECTOR_4     ((uint32_t)0x00000010U) /*!< PC Readout protection of Sector4      */
+#define OB_PCROP_SECTOR_5     ((uint32_t)0x00000020U) /*!< PC Readout protection of Sector5      */
+#define OB_PCROP_SECTOR_6     ((uint32_t)0x00000040U) /*!< PC Readout protection of Sector6      */
+#define OB_PCROP_SECTOR_7     ((uint32_t)0x00000080U) /*!< PC Readout protection of Sector7      */
+#define OB_PCROP_SECTOR_All   ((uint32_t)0x000000FFU) /*!< PC Readout protection of all Sectors  */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_PCROP_RDP FLASH Option Bytes PCROP_RDP Bit
+  * @{
+  */
+#define OB_PCROP_RDP_ENABLE   ((uint32_t)0x80000000U) /*!< PCROP_RDP Enable      */
+#define OB_PCROP_RDP_DISABLE  ((uint32_t)0x00000000U) /*!< PCROP_RDP Disable     */
+/**
+  * @}
+  */
+#endif /* FLASH_OPTCR2_PCROP */
+
 /**
   * @}
   */ 
@@ -489,8 +532,14 @@ void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
 #define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
                            ((VALUE) == OB_WRPSTATE_ENABLE))  
 
+#if defined (FLASH_OPTCR2_PCROP)
+#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP        | OPTIONBYTE_USER |\
+                                          OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1 |\
+                                          OPTIONBYTE_PCROP | OPTIONBYTE_PCROP_RDP)))
+#else
 #define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP        | OPTIONBYTE_USER |\
                                           OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1)))
+#endif /* FLASH_OPTCR2_PCROP */
 
 #define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013)
 
@@ -530,8 +579,8 @@ void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
                                    ((LATENCY) == FLASH_LATENCY_14) || \
                                    ((LATENCY) == FLASH_LATENCY_15))
 
-#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
-
+                                   (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))
 #define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
 
 #if (FLASH_SECTOR_TOTAL == 8)
@@ -574,6 +623,12 @@ void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
                                     ((VALUE) == OB_DUAL_BOOT_ENABLE))
 #endif /* FLASH_OPTCR_nDBOOT */
 
+#if defined (FLASH_OPTCR2_PCROP)
+#define IS_OB_PCROP_SECTOR(SECTOR)   (((SECTOR) & (uint32_t)0xFFFFFF00U) == 0x00000000U)
+#define IS_OB_PCROP_RDP_VALUE(VALUE) (((VALUE) == OB_PCROP_RDP_DISABLE) || \
+                                      ((VALUE) == OB_PCROP_RDP_ENABLE))
+#endif /* FLASH_OPTCR2_PCROP */
+
 /**
   * @}
   */

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_gpio.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   GPIO HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_gpio.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of GPIO HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio_ex.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_gpio_ex.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of GPIO HAL Extension module.
   ******************************************************************************
   * @attention
@@ -237,6 +237,122 @@
 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
 /*----------------------------------------------------------------------------*/
 
+/*---------------------------- STM32F72xxx/STM32F73xxx -----------------------*/      
+#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx)
+ /** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
+#define GPIO_AF3_LPTIM1        ((uint8_t)0x03U)  /* LPTIM1 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */ 
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */
+#define GPIO_AF5_SPI5          ((uint8_t)0x05U)  /* SPI5 Alternate Function mapping        */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_UART5         ((uint8_t)0x07U)  /* UART5 Alternate Function mapping      */
+#define GPIO_AF7_SPI2          ((uint8_t)0x07U)  /* SPI2 Alternate Function mapping       */
+#define GPIO_AF7_SPI3          ((uint8_t)0x07U)  /* SPI3 Alternate Function mapping       */ 
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7         ((uint8_t)0x08U)  /* UART7 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */
+#define GPIO_AF8_SAI2          ((uint8_t)0x08U)  /* SAI2 Alternate Function mapping   */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping   */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping   */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping   */
+#define GPIO_AF9_QUADSPI       ((uint8_t)0x09U)  /* QUADSPI Alternate Function mapping */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0xAU)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0xAU)  /* OTG_HS Alternate Function mapping */
+#define GPIO_AF10_QUADSPI       ((uint8_t)0xAU)  /* QUADSPI Alternate Function mapping */
+#define GPIO_AF10_SAI2          ((uint8_t)0xAU)  /* SAI2 Alternate Function mapping */
+#define GPIO_AF10_SDMMC2        ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */   
+
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF11_SDMMC2        ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping   */
+   
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_FMC           ((uint8_t)0xCU)  /* FMC Alternate Function mapping                      */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0xCU)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDMMC1        ((uint8_t)0xCU)  /* SDMMC1 Alternate Function mapping                   */
+   
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF13_RNG           ((uint8_t)0x0DU)  /* RNG Alternate Function mapping */   
+   
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */     
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */
+/*----------------------------------------------------------------------------*/
+
 /**
   * @}
   */ 
@@ -309,6 +425,16 @@
                                               ((__GPIOx__) == (GPIOJ))? 9U : 10U)
 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
 
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx)
+#define GPIO_GET_INDEX(__GPIOx__)   (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                              ((__GPIOx__) == (GPIOB))? 1U :\
+                                              ((__GPIOx__) == (GPIOC))? 2U :\
+                                              ((__GPIOx__) == (GPIOD))? 3U :\
+                                              ((__GPIOx__) == (GPIOE))? 4U :\
+                                              ((__GPIOx__) == (GPIOF))? 5U :\
+                                              ((__GPIOx__) == (GPIOG))? 6U :\
+                                              ((__GPIOx__) == (GPIOH))? 7U : 8U)
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */
 /**
   * @}
   */
@@ -487,6 +613,33 @@
                           ((AF) == GPIO_AF12_SDMMC1)    || ((AF) == GPIO_AF12_FMC)       || \
                           ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF13_DCMI)      || \
                           ((AF) == GPIO_AF10_OTG_FS))
+#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \
+                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF5_SPI3)       || \
+                          ((AF) == GPIO_AF5_SPI4)       || ((AF) == GPIO_AF5_SPI5)       || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \
+                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)       || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)      || \
+                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)      || \
+                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF9_QUADSPI)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF10_SAI2)      || ((AF) == GPIO_AF10_QUADSPI)   || \
+                          ((AF) == GPIO_AF10_SDMMC2)    || ((AF) == GPIO_AF11_SDMMC2)    || \
+                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1)    || \
+                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF15_EVENTOUT)  || \
+                          ((AF) == GPIO_AF10_OTG_FS))
 #endif /* STM32F756xx || STM32F746xx */
 /**
   * @}

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hash.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   HASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the HASH peripheral:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hash.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of HASH HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hash_ex.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   HASH HAL Extension module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of HASH peripheral:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hash_ex.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of HASH HAL Extension module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hcd.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   HCD HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the USB Peripheral Controller:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hcd.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of HCD HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_i2c.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of I2C HAL module.
   ******************************************************************************
   * @attention
@@ -98,47 +98,46 @@ typedef struct
 
 /** @defgroup HAL_state_structure_definition HAL state structure definition
   * @brief  HAL State structure definition
-  * @note  HAL I2C State value coding follow below described bitmap :
+  * @note  HAL I2C State value coding follow below described bitmap :\n
-  *          b7-b6  Error information 
+  *          b7-b6  Error information\n
-  *             00 : No Error
+  *             00 : No Error\n
-  *             01 : Abort (Abort user request on going)
+  *             01 : Abort (Abort user request on going)\n
-  *             10 : Timeout
+  *             10 : Timeout\n
-  *             11 : Error
+  *             11 : Error\n
-  *          b5     IP initilisation status
+  *          b5     IP initilisation status\n
-  *             0  : Reset (IP not initialized)
+  *             0  : Reset (IP not initialized)\n
-  *             1  : Init done (IP initialized and ready to use. HAL I2C Init function called)
+  *             1  : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
-  *          b4     (not used)
+  *          b4     (not used)\n
-  *             x  : Should be set to 0
+  *             x  : Should be set to 0\n
-  *          b3
+  *          b3\n
-  *             0  : Ready or Busy (No Listen mode ongoing)
+  *             0  : Ready or Busy (No Listen mode ongoing)\n
-  *             1  : Listen (IP in Address Listen Mode)
+  *             1  : Listen (IP in Address Listen Mode)\n
-  *          b2     Intrinsic process state
+  *          b2     Intrinsic process state\n
-  *             0  : Ready
+  *             0  : Ready\n
-  *             1  : Busy (IP busy with some configuration or internal operations)
+  *             1  : Busy (IP busy with some configuration or internal operations)\n
-  *          b1     Rx state
+  *          b1     Rx state\n
-  *             0  : Ready (no Rx operation ongoing)
+  *             0  : Ready (no Rx operation ongoing)\n
-  *             1  : Busy (Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)\n
-  *          b0     Tx state
+  *          b0     Tx state\n
-  *             0  : Ready (no Tx operation ongoing)
+  *             0  : Ready (no Tx operation ongoing)\n
   *             1  : Busy (Tx operation ongoing)
   * @{
   */ 
-
 typedef enum
 {
   HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
   HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
   HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
-  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */ 
+  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
   HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
   HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
   HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
-                                                 process is ongoing                        */
+                                                 process is ongoing                         */
   HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
-                                                 process is ongoing                        */
+                                                 process is ongoing                         */
-  HAL_I2C_STATE_ABORT             = 0x60,    /*!< Abort user request ongoing                */
+  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
   HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
-  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */ 
+  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
 
 }HAL_I2C_StateTypeDef;
 
@@ -148,19 +147,19 @@ typedef enum
 
 /** @defgroup HAL_mode_structure_definition HAL mode structure definition
   * @brief  HAL Mode structure definition
-  * @note  HAL I2C Mode value coding follow below described bitmap :
+  * @note  HAL I2C Mode value coding follow below described bitmap :\n
-  *          b7     (not used)
+  *          b7     (not used)\n
-  *             x  : Should be set to 0
+  *             x  : Should be set to 0\n
-  *          b6
+  *          b6\n
-  *             0  : None
+  *             0  : None\n
-  *             1  : Memory (HAL I2C communication is in Memory Mode)
+  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
-  *          b5
+  *          b5\n
-  *             0  : None
+  *             0  : None\n
-  *             1  : Slave (HAL I2C communication is in Slave Mode)
+  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
-  *          b4
+  *          b4\n
-  *             0  : None
+  *             0  : None\n
-  *             1  : Master (HAL I2C communication is in Master Mode)
+  *             1  : Master (HAL I2C communication is in Master Mode)\n
-  *          b3-b2-b1-b0  (not used)
+  *          b3-b2-b1-b0  (not used)\n
   *             xxxx : Should be set to 0000
   * @{
   */
@@ -178,24 +177,23 @@ typedef enum
   */
 
 /** @defgroup I2C_Error_Code_definition I2C Error Code definition
-  * @brief  I2C Error Code definition  
+  * @brief  I2C Error Code definition
   * @{
   */
-#define HAL_I2C_ERROR_NONE      ((uint32_t)0x00000000U)    /*!< No error              */
+#define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
-#define HAL_I2C_ERROR_BERR      ((uint32_t)0x00000001U)    /*!< BERR error            */
+#define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
-#define HAL_I2C_ERROR_ARLO      ((uint32_t)0x00000002U)    /*!< ARLO error            */
+#define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
-#define HAL_I2C_ERROR_AF        ((uint32_t)0x00000004U)    /*!< ACKF error            */
+#define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
-#define HAL_I2C_ERROR_OVR       ((uint32_t)0x00000008U)    /*!< OVR error             */
+#define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
-#define HAL_I2C_ERROR_DMA       ((uint32_t)0x00000010U)    /*!< DMA transfer error    */
+#define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
-#define HAL_I2C_ERROR_TIMEOUT   ((uint32_t)0x00000020U)    /*!< Timeout error         */
+#define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
-#define HAL_I2C_ERROR_SIZE      ((uint32_t)0x00000040U)    /*!< Size Management error */
+#define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
-#define HAL_I2C_ERROR_ABORT     ((uint32_t)0x00000080U)    /*!< Abort user request    */
 /**
   * @}
   */
 
 /** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
-  * @brief  I2C handle Structure definition  
+  * @brief  I2C handle Structure definition
   * @{
   */
 typedef struct __I2C_HandleTypeDef
@@ -237,7 +235,7 @@ typedef struct __I2C_HandleTypeDef
 
 /**
   * @}
-  */  
+  */
 /* Exported constants --------------------------------------------------------*/
 
 /** @defgroup I2C_Exported_Constants I2C Exported Constants
@@ -259,8 +257,8 @@ typedef struct __I2C_HandleTypeDef
 /** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
   * @{
   */
-#define I2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00000001U)
+#define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
-#define I2C_ADDRESSINGMODE_10BIT        ((uint32_t)0x00000002U)
+#define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
 /**
   * @}
   */
@@ -268,7 +266,7 @@ typedef struct __I2C_HandleTypeDef
 /** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
   * @{
   */
-#define I2C_DUALADDRESS_DISABLE         ((uint32_t)0x00000000U)
+#define I2C_DUALADDRESS_DISABLE         (0x00000000U)
 #define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
 /**
   * @}
@@ -292,7 +290,7 @@ typedef struct __I2C_HandleTypeDef
 /** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
   * @{
   */
-#define I2C_GENERALCALL_DISABLE         ((uint32_t)0x00000000U)
+#define I2C_GENERALCALL_DISABLE         (0x00000000U)
 #define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
 /**
   * @}
@@ -301,7 +299,7 @@ typedef struct __I2C_HandleTypeDef
 /** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
   * @{
   */
-#define I2C_NOSTRETCH_DISABLE           ((uint32_t)0x00000000U)
+#define I2C_NOSTRETCH_DISABLE           (0x00000000U)
 #define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
 /**
   * @}
@@ -310,17 +308,17 @@ typedef struct __I2C_HandleTypeDef
 /** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
   * @{
   */
-#define I2C_MEMADD_SIZE_8BIT            ((uint32_t)0x00000001U)
+#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
-#define I2C_MEMADD_SIZE_16BIT           ((uint32_t)0x00000002U)
+#define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
 /**
   * @}
   */
   
-/** @defgroup I2C_XferDirection I2C Transfer Direction
+/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
   * @{
   */
-#define I2C_DIRECTION_TRANSMIT          ((uint32_t)0x00000000U)
+#define I2C_DIRECTION_TRANSMIT          (0x00000000U)
-#define I2C_DIRECTION_RECEIVE           ((uint32_t)0x00000001U)
+#define I2C_DIRECTION_RECEIVE           (0x00000001U)
 /**
   * @}
   */
@@ -330,7 +328,7 @@ typedef struct __I2C_HandleTypeDef
   */
 #define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
 #define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
-#define  I2C_SOFTEND_MODE               ((uint32_t)0x00000000U)
+#define  I2C_SOFTEND_MODE               (0x00000000U)
 /**
   * @}
   */
@@ -338,7 +336,7 @@ typedef struct __I2C_HandleTypeDef
 /** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
   * @{
   */
-#define  I2C_NO_STARTSTOP               ((uint32_t)0x00000000U)
+#define  I2C_NO_STARTSTOP               (0x00000000U)
 #define  I2C_GENERATE_STOP              I2C_CR2_STOP
 #define  I2C_GENERATE_START_READ        (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
 #define  I2C_GENERATE_START_WRITE       I2C_CR2_START
@@ -365,7 +363,7 @@ typedef struct __I2C_HandleTypeDef
 
 /** @defgroup I2C_Flag_definition I2C Flag definition
   * @{
-  */ 
+  */
 #define I2C_FLAG_TXE                    I2C_ISR_TXE
 #define I2C_FLAG_TXIS                   I2C_ISR_TXIS
 #define I2C_FLAG_RXNE                   I2C_ISR_RXNE
@@ -391,7 +389,7 @@ typedef struct __I2C_HandleTypeDef
   */
 
 /* Exported macros -----------------------------------------------------------*/
-  
+
 /** @defgroup I2C_Exported_Macros I2C Exported Macros
   * @{
   */
@@ -429,7 +427,7 @@ typedef struct __I2C_HandleTypeDef
   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
   *            @arg @ref I2C_IT_RXI   RX interrupt enable
   *            @arg @ref I2C_IT_TXI   TX interrupt enable
-  *   
+  *
   * @retval None
   */
 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
@@ -485,16 +483,16 @@ typedef struct __I2C_HandleTypeDef
   *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
   *            @arg @ref I2C_FLAG_BERR    Bus error
   *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
-  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun            
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
   *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
-  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag 
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
   *            @arg @ref I2C_FLAG_ALERT   SMBus alert
   *
   * @retval None
   */
 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
                                                                                  : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
- 
+
 /** @brief  Enable the specified I2C peripheral.
   * @param  __HANDLE__ specifies the I2C Handle.
   * @retval None
@@ -594,7 +592,7 @@ void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
 /**
   * @}
-  */ 
+  */
 
 /** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
   * @{
@@ -667,17 +665,17 @@ uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
 
 #define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
 
-#define I2C_GET_ADDR_MATCH(__HANDLE__)            (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16)
+#define I2C_GET_ADDR_MATCH(__HANDLE__)            (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
-#define I2C_GET_DIR(__HANDLE__)                   (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
+#define I2C_GET_DIR(__HANDLE__)                   (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
 #define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
 #define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
 #define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
 
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= (uint32_t)0x000003FF)
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FF)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
 
-#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
+#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
 
 #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_i2c_ex.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   I2C Extended HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of I2C Extended peripheral:
@@ -14,13 +14,12 @@
                ##### I2C peripheral Extended features  #####
   ==============================================================================
 
-  [..] Comparing to other previous devices, the I2C interface for STM32F7XX
+  [..] Comparing to other previous devices, the I2C interface for STM32F7xx
        devices contains the following additional features
 
        (+) Possibility to disable or enable Analog Noise Filter
        (+) Use of a configured Digital Noise Filter
-       (+) Disable or enable Fast Mode Plus (available only for STM32F76xxx/STM32F77xxx 
+       (+) Disable or enable Fast Mode Plus
-           devices)
 
                      ##### How to use this driver #####
   ==============================================================================
@@ -29,7 +28,7 @@
     (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
     (#) Configure the enable or disable of fast mode plus driving capability using the functions :
           (++) HAL_I2CEx_EnableFastModePlus()
-          (++) HAL_I2CEx_DisbleFastModePlus()
+          (++) HAL_I2CEx_DisableFastModePlus()
   @endverbatim
   ******************************************************************************
   * @attention
@@ -68,7 +67,7 @@
   * @{
   */
 
-/** @defgroup I2CEx I2C Extended HAL module driver
+/** @defgroup I2CEx I2CEx
   * @brief I2C Extended HAL module driver
   * @{
   */
@@ -94,7 +93,7 @@
                       ##### Extended features functions #####
  ===============================================================================
     [..] This section provides functions allowing to:
-      (+) Configure Noise Filters
+      (+) Configure Noise Filters 
       (+) Configure Fast Mode Plus
 
 @endverbatim
@@ -103,9 +102,9 @@
 
 /**
   * @brief  Configure I2C Analog noise filter.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2Cx peripheral.
+  *                the configuration information for the specified I2Cx peripheral.
-  * @param  AnalogFilter: New state of the Analog filter.
+  * @param  AnalogFilter New state of the Analog filter.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
@@ -113,30 +112,30 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t
   /* Check the parameters */
   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
   assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
-  
+
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
     hi2c->State = HAL_I2C_STATE_BUSY;
-    
+
     /* Disable the selected I2C peripheral */
     __HAL_I2C_DISABLE(hi2c);
-    
+
     /* Reset I2Cx ANOFF bit */
     hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
-    
+
     /* Set analog filter bit*/
     hi2c->Instance->CR1 |= AnalogFilter;
-    
+
     __HAL_I2C_ENABLE(hi2c);
-    
+
     hi2c->State = HAL_I2C_STATE_READY;
-    
+
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
-    
+
     return HAL_OK;
   }
   else
@@ -147,48 +146,48 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t
 
 /**
   * @brief  Configure I2C Digital noise filter.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2Cx peripheral.
+  *                the configuration information for the specified I2Cx peripheral.
-  * @param  DigitalFilter: Coefficient of digital noise filter between 0x00 and 0x0F.
+  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
 {
-  uint32_t tmpreg = 0;
+  uint32_t tmpreg = 0U;
-  
+
   /* Check the parameters */
   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
   assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
-  
+
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
     hi2c->State = HAL_I2C_STATE_BUSY;
-    
+
     /* Disable the selected I2C peripheral */
     __HAL_I2C_DISABLE(hi2c);
-    
+
     /* Get the old register value */
     tmpreg = hi2c->Instance->CR1;
-    
+
     /* Reset I2Cx DNF bits [11:8] */
     tmpreg &= ~(I2C_CR1_DNF);
-    
+
     /* Set I2Cx DNF coefficient */
-    tmpreg |= DigitalFilter << 8;
+    tmpreg |= DigitalFilter << 8U;
-    
+
     /* Store the new register value */
     hi2c->Instance->CR1 = tmpreg;
-    
+
     __HAL_I2C_ENABLE(hi2c);
-    
+
     hi2c->State = HAL_I2C_STATE_READY;
-    
+
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
-    
+
     return HAL_OK;
   }
   else
@@ -197,44 +196,65 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
   }
 }
 
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#if defined(SYSCFG_PMC_I2C1_FMP)
 /**
   * @brief Enable the I2C fast mode plus driving capability.
-  * @param ConfigFastModePlus: Selects the pin.
+  * @param ConfigFastModePlus Selects the pin.
   *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
   * @retval None
   */
 void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
 {
   /* Check the parameter */
   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
-  
+
   /* Enable SYSCFG clock */
   __HAL_RCC_SYSCFG_CLK_ENABLE();
-  
+
   /* Enable fast mode plus driving capability for selected pin */
   SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);
 }
 
 /**
   * @brief Disable the I2C fast mode plus driving capability.
-  * @param ConfigFastModePlus: Selects the pin.
+  * @param ConfigFastModePlus Selects the pin.
   *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
   * @retval None
   */
 void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
 {
   /* Check the parameter */
   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
-  
+
   /* Enable SYSCFG clock */
   __HAL_RCC_SYSCFG_CLK_ENABLE();
-  
+
   /* Disable fast mode plus driving capability for selected pin */
   CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);
 }
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#endif /* SYSCFG_PMC_I2C1_FMP */
-
 /**
   * @}
   */

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.h

@@ -2,9 +2,9 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_i2c_ex.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
-  * @brief   Header file of I2C HAL Extension module.
+  * @brief   Header file of I2C HAL Extended module.
   ******************************************************************************
   * @attention
   *
@@ -57,15 +57,15 @@
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
 
-/** @defgroup I2CEx_Exported_Constants I2CEx Exported Constants
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
   * @{
   */
 
-/** @defgroup I2CEx_Analog_Filter I2CEx Analog Filter
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
   * @{
   */
-#define I2C_ANALOGFILTER_ENABLE        ((uint32_t)0x00000000U)
+#define I2C_ANALOGFILTER_ENABLE         0x00000000U
-#define I2C_ANALOGFILTER_DISABLE       I2C_CR1_ANFOFF
+#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
 /**
   * @}
   */
@@ -73,40 +73,71 @@
 /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
   * @{
   */
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define I2C_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */
-
+#if defined(SYSCFG_PMC_I2C_PB6_FMP)
-#define I2C_FASTMODEPLUS_PB6          SYSCFG_PMC_I2C_PB6_FMP
+#define I2C_FASTMODEPLUS_PB6            SYSCFG_PMC_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
-#define I2C_FASTMODEPLUS_PB7          SYSCFG_PMC_I2C_PB7_FMP
+#define I2C_FASTMODEPLUS_PB7            SYSCFG_PMC_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
-#define I2C_FASTMODEPLUS_PB8          SYSCFG_PMC_I2C_PB8_FMP
+#else
-#define I2C_FASTMODEPLUS_PB9          SYSCFG_PMC_I2C_PB9_FMP
+#define I2C_FASTMODEPLUS_PB6            (uint32_t)(0x00000004U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB6 not supported   */
-
+#define I2C_FASTMODEPLUS_PB7            (uint32_t)(0x00000008U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB7 not supported   */
-#define I2C_FASTMODEPLUS_I2C1         SYSCFG_PMC_I2C1_FMP
+#endif
-#define I2C_FASTMODEPLUS_I2C2         SYSCFG_PMC_I2C2_FMP
+#if defined(SYSCFG_PMC_I2C_PB8_FMP)
-#define I2C_FASTMODEPLUS_I2C3         SYSCFG_PMC_I2C3_FMP
+#define I2C_FASTMODEPLUS_PB8            SYSCFG_PMC_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
-#define I2C_FASTMODEPLUS_I2C4         SYSCFG_PMC_I2C4_FMP
+#define I2C_FASTMODEPLUS_PB9            SYSCFG_PMC_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
-
+#else
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx  */
+#define I2C_FASTMODEPLUS_PB8            (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported   */
+#define I2C_FASTMODEPLUS_PB9            (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported   */
+#endif
+#if defined(SYSCFG_PMC_I2C1_FMP)
+#define I2C_FASTMODEPLUS_I2C1           SYSCFG_PMC_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C1           (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported  */
+#endif
+#if defined(SYSCFG_PMC_I2C2_FMP)
+#define I2C_FASTMODEPLUS_I2C2           SYSCFG_PMC_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C2           (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported  */
+#endif
+#if defined(SYSCFG_PMC_I2C3_FMP)
+#define I2C_FASTMODEPLUS_I2C3           SYSCFG_PMC_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C3           (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported  */
+#endif
+#if defined(SYSCFG_PMC_I2C4_FMP)
+#define I2C_FASTMODEPLUS_I2C4           SYSCFG_PMC_I2C4_FMP                           /*!< Enable Fast Mode Plus on I2C4 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C4           (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported  */
+#endif
 /**
   * @}
   */
-  
+
 /**
   * @}
   */ 
-  
+
 /* Exported macro ------------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
 
-/* Peripheral Control methods  ************************************************/
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#if defined(SYSCFG_PMC_I2C1_FMP)
 void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
 void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#endif /* SYSCFG_PMC_I2C1_FMP */
 
 /* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
   * @{
   */
 
@@ -115,7 +146,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
   */
 
 /* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macro I2C Private Macros
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
   * @{
   */
 #define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
@@ -130,7 +161,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
-										 (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))
 #elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP)
 #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
@@ -138,7 +169,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
-										 (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
 #elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP)
 #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
@@ -156,16 +187,21 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
 #endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */
 /**
   * @}
+  */ 
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
+  * @{
   */
+/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */
 /**
   * @}
   */
 
-/* Private Functions ---------------------------------------------------------*/
+/**
-/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @}
-  * @{
   */
-/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */
+
 /**
   * @}
   */
@@ -184,5 +220,4 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
 
 #endif /* __STM32F7xx_HAL_I2C_EX_H */
 
-
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_i2s.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   I2S HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_i2s.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of I2S HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_irda.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   IRDA HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the IrDA (Infrared Data Association) Peripheral
@@ -99,6 +99,7 @@
      (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt
      (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt
 
+    [..]
      (@) You can refer to the IRDA HAL driver header file for more useful macros
 
   @endverbatim
@@ -193,7 +194,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
   * @{
   */
 
-/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
   *  @brief    Initialization and Configuration functions
   *
 @verbatim
@@ -405,28 +406,28 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
         (++) HAL_IRDA_ErrorCallback()
 
     (#) Non-Blocking mode transfers could be aborted using Abort API's :
-        (+) HAL_IRDA_Abort()
+        (++) HAL_IRDA_Abort()
-        (+) HAL_IRDA_AbortTransmit()
+        (++) HAL_IRDA_AbortTransmit()
-        (+) HAL_IRDA_AbortReceive()
+        (++) HAL_IRDA_AbortReceive()
-        (+) HAL_IRDA_Abort_IT()
+        (++) HAL_IRDA_Abort_IT()
-        (+) HAL_IRDA_AbortTransmit_IT()
+        (++) HAL_IRDA_AbortTransmit_IT()
-        (+) HAL_IRDA_AbortReceive_IT()
+        (++) HAL_IRDA_AbortReceive_IT()
 
     (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
-        (+) HAL_IRDA_AbortCpltCallback()
+        (++) HAL_IRDA_AbortCpltCallback()
-        (+) HAL_IRDA_AbortTransmitCpltCallback()
+        (++) HAL_IRDA_AbortTransmitCpltCallback()
-        (+) HAL_IRDA_AbortReceiveCpltCallback()
+        (++) HAL_IRDA_AbortReceiveCpltCallback()
 
     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
         Errors are handled as follows :
-       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is 
+       (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is 
-           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
-           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
-           and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
+            and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
-           If user wants to abort it, Abort services should be called by user.
+            If user wants to abort it, Abort services should be called by user.
-       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+       (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
-           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
-           Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+            Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
 
 @endverbatim
   * @{
@@ -1758,16 +1759,6 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
       return HAL_TIMEOUT;
     }
   }
-  /* Check if the Receiver is enabled */
-  if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
-  {
-    /* Wait until REACK flag is set */
-    if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
-    {
-      /* Timeout occurred */
-      return HAL_TIMEOUT;
-    }
-  }
 
   /* Initialize the IRDA state*/
   hirda->gState  = HAL_IRDA_STATE_READY;

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_irda.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of IRDA HAL module.
   ******************************************************************************
   * @attention
@@ -599,7 +599,7 @@ typedef struct
 #include "stm32f7xx_hal_irda_ex.h"  
 
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup IRDA_Exported_Functions IrDA Exported Functions
+/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
   * @{
   */
 

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda_ex.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_irda_ex.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of IRDA HAL Extension module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_iwdg.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   IWDG HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Independent Watchdog (IWDG) peripheral:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_iwdg.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of IWDG HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_jpeg.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   JPEG HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the JPEG encoder/decoder peripheral:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_jpeg.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of JPEG HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_lptim.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   LPTIM HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Low Power Timer (LPTIM) peripheral:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_lptim.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of LPTIM HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_ltdc.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   LTDC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the LTDC peripheral:

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_ltdc.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of LTDC HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_ltdc_ex.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   LTDC Extension HAL module driver.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_ltdc_ex.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of LTDC HAL Extension module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_mdios.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   MDIOS HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the MDIOS Peripheral.

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_mdios.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of MDIOS HAL module.
   ******************************************************************************
   * @attention
@@ -43,11 +43,11 @@
  extern "C" {
 #endif
 
-#if defined (MDIOS)
-   
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f7xx_hal_def.h"
 
+#if defined (MDIOS)
+
 /** @addtogroup STM32F7xx_HAL_Driver
   * @{
   */

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mmc.h

@@ -0,0 +1,695 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_mmc.h
+  * @author  MCD Application Team
+  * @version V1.2.0
+  * @date    30-December-2016
+  * @brief   Header file of MMC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_MMC_H
+#define __STM32F7xx_HAL_MMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_ll_sdmmc.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup MMC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup MMC_Exported_Types MMC Exported Types
+  * @{
+  */
+
+/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
+  * @{
+  */   
+typedef enum
+{
+  HAL_MMC_STATE_RESET                  = ((uint32_t)0x00000000U),  /*!< MMC not yet initialized or disabled  */
+  HAL_MMC_STATE_READY                  = ((uint32_t)0x00000001U),  /*!< MMC initialized and ready for use    */
+  HAL_MMC_STATE_TIMEOUT                = ((uint32_t)0x00000002U),  /*!< MMC Timeout state                    */
+  HAL_MMC_STATE_BUSY                   = ((uint32_t)0x00000003U),  /*!< MMC process ongoing                  */
+  HAL_MMC_STATE_PROGRAMMING            = ((uint32_t)0x00000004U),  /*!< MMC Programming State                */
+  HAL_MMC_STATE_RECEIVING              = ((uint32_t)0x00000005U),  /*!< MMC Receinving State                 */
+  HAL_MMC_STATE_TRANSFER               = ((uint32_t)0x00000006U),  /*!< MMC Transfert State                  */
+  HAL_MMC_STATE_ERROR                  = ((uint32_t)0x0000000FU)   /*!< MMC is in error state                */
+}HAL_MMC_StateTypeDef;
+/** 
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
+  * @{
+  */   
+typedef enum
+{
+  HAL_MMC_CARD_READY                  = ((uint32_t)0x00000001U),  /*!< Card state is ready                     */
+  HAL_MMC_CARD_IDENTIFICATION         = ((uint32_t)0x00000002U),  /*!< Card is in identification state         */
+  HAL_MMC_CARD_STANDBY                = ((uint32_t)0x00000003U),  /*!< Card is in standby state                */
+  HAL_MMC_CARD_TRANSFER               = ((uint32_t)0x00000004U),  /*!< Card is in transfer state               */  
+  HAL_MMC_CARD_SENDING                = ((uint32_t)0x00000005U),  /*!< Card is sending an operation            */
+  HAL_MMC_CARD_RECEIVING              = ((uint32_t)0x00000006U),  /*!< Card is receiving operation information */
+  HAL_MMC_CARD_PROGRAMMING            = ((uint32_t)0x00000007U),  /*!< Card is in programming state            */
+  HAL_MMC_CARD_DISCONNECTED           = ((uint32_t)0x00000008U),  /*!< Card is disconnected                    */
+  HAL_MMC_CARD_ERROR                  = ((uint32_t)0x000000FFU)   /*!< Card response Error                     */
+}HAL_MMC_CardStateTypeDef;
+/** 
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition   
+  * @{
+  */
+#define MMC_InitTypeDef      SDMMC_InitTypeDef 
+#define MMC_TypeDef          SDMMC_TypeDef
+
+/** 
+  * @brief  MMC Card Information Structure definition
+  */ 
+typedef struct
+{
+  uint32_t CardType;                     /*!< Specifies the card Type                         */
+
+  uint32_t Class;                        /*!< Specifies the class of the card class           */
+
+  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */
+  
+  uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */
+
+  uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */
+  
+  uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */
+
+  uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */
+
+}HAL_MMC_CardInfoTypeDef;
+
+/** 
+  * @brief  MMC handle Structure definition
+  */ 
+typedef struct
+{
+  MMC_TypeDef                   *Instance;        /*!< MMC registers base address           */
+  
+  MMC_InitTypeDef               Init;             /*!< MMC required parameters              */
+  
+  HAL_LockTypeDef              Lock;             /*!< MMC locking object                   */
+  
+  uint32_t                     *pTxBuffPtr;      /*!< Pointer to MMC Tx transfer Buffer    */
+
+  uint32_t                     TxXferSize;       /*!< MMC Tx Transfer size                 */
+
+  uint32_t                     *pRxBuffPtr;      /*!< Pointer to MMC Rx transfer Buffer    */
+
+  uint32_t                     RxXferSize;       /*!< MMC Rx Transfer size                 */
+  
+  __IO uint32_t                Context;          /*!< MMC transfer context                 */
+ 
+  __IO HAL_MMC_StateTypeDef     State;            /*!< MMC card State                       */
+  
+  __IO uint32_t                ErrorCode;        /*!< MMC Card Error codes                 */  
+ 
+  DMA_HandleTypeDef            *hdmarx;          /*!< MMC Rx DMA handle parameters         */
+  
+  DMA_HandleTypeDef            *hdmatx;          /*!< MMC Tx DMA handle parameters         */
+  
+  HAL_MMC_CardInfoTypeDef       MmcCard;           /*!< MMC Card information                 */
+
+  uint32_t                     CSD[4];           /*!< MMC card specific data table         */
+  
+  uint32_t                     CID[4];           /*!< MMC card identification number table */
+  
+}MMC_HandleTypeDef;
+
+/** 
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register 
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
+  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
+  __IO uint8_t  Reserved1;            /*!< Reserved                              */
+  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
+  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
+  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
+  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
+  __IO uint8_t  Reserved2;            /*!< Reserved                              */
+  __IO uint32_t DeviceSize;           /*!< Device Size                           */
+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
+  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
+  __IO uint8_t  Reserved3;            /*!< Reserved                              */
+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
+  __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */
+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
+  __IO uint8_t  FileFormat;           /*!< File format                           */
+  __IO uint8_t  ECC;                  /*!< ECC code                              */
+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
+  __IO uint8_t  Reserved4;            /*!< Always 1                              */
+  
+}HAL_MMC_CardCSDTypeDef;
+/** 
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
+  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
+  __IO uint32_t ProdName1;       /*!< Product Name part1    */
+  __IO uint8_t  ProdName2;       /*!< Product Name part2    */
+  __IO uint8_t  ProdRev;         /*!< Product Revision      */
+  __IO uint32_t ProdSN;          /*!< Product Serial Number */
+  __IO uint8_t  Reserved1;       /*!< Reserved1             */
+  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
+  __IO uint8_t  CID_CRC;         /*!< CID CRC               */
+  __IO uint8_t  Reserved2;       /*!< Always 1              */
+
+}HAL_MMC_CardCIDTypeDef;
+/** 
+  * @}
+  */
+
+/** 
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup MMC_Exported_Constants Exported Constants
+  * @{
+  */
+
+#define BLOCKSIZE   ((uint32_t)512U)         /*!< Block size is 512 bytes */
+#define CAPACITY    ((uint32_t)0x80000000U)  /*!< 2 G bytes constant      */
+
+/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition 
+  * @{
+  */  
+#define HAL_MMC_ERROR_NONE                     SDMMC_ERROR_NONE                    /*!< No error                                                      */
+#define HAL_MMC_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL            /*!< Command response received (but CRC check failed)              */
+#define HAL_MMC_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL           /*!< Data block sent/received (CRC check failed)                   */
+#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT         /*!< Command response timeout                                      */
+#define HAL_MMC_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT            /*!< Data timeout                                                  */
+#define HAL_MMC_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN             /*!< Transmit FIFO underrun                                        */
+#define HAL_MMC_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN              /*!< Receive FIFO overrun                                          */
+#define HAL_MMC_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED         /*!< Misaligned address                                            */
+#define HAL_MMC_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR           /*!< Transferred block length is not allowed for the card or the 
+                                                                                       number of transferred bytes does not match the block length   */
+#define HAL_MMC_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR           /*!< An error in the sequence of erase command occurs              */
+#define HAL_MMC_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM         /*!< An invalid selection for erase groups                         */
+#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION    /*!< Attempt to program a write protect block                      */
+#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED      /*!< Sequence or password error has been detected in unlock 
+                                                                                       command or if there was an attempt to access a locked card    */
+#define HAL_MMC_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED          /*!< CRC check of the previous command failed                      */
+#define HAL_MMC_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD             /*!< Command is not legal for the card state                       */
+#define HAL_MMC_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED         /*!< Card internal ECC was applied but failed to correct the data  */
+#define HAL_MMC_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                  /*!< Internal card controller error                                */
+#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR     /*!< General or unknown error                                      */
+#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN    /*!< The card could not sustain data reading in stream rmode       */
+#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN    /*!< The card could not sustain data programming in stream mode    */
+#define HAL_MMC_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE       /*!< CID/CSD overwrite error                                       */
+#define HAL_MMC_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP           /*!< Only partial address space was erased                         */
+#define HAL_MMC_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED       /*!< Command has been executed without using internal ECC          */
+#define HAL_MMC_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET             /*!< Erase sequence was cleared before executing because an out 
+                                                                                       of erase sequence command was received                        */
+#define HAL_MMC_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR             /*!< Error in sequence of authentication                           */
+#define HAL_MMC_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE       /*!< Error in case of invalid voltage range                        */        
+#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE       /*!< Error when addressed block is out of range                    */        
+#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE  /*!< Error when command request is not applicable                  */  
+#define HAL_MMC_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER       /*!< the used parameter is not valid                               */  
+#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE     /*!< Error when feature is not insupported                         */
+#define HAL_MMC_ERROR_BUSY                     SDMMC_ERROR_BUSY                    /*!< Error when transfer process is busy                           */ 
+#define HAL_MMC_ERROR_DMA                      SDMMC_ERROR_DMA                     /*!< Error while DMA transfer                                      */
+#define HAL_MMC_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                 /*!< Timeout error                                                 */
+                                                
+/** 
+  * @}
+  */
+ 
+/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
+  * @{
+  */ 
+#define   MMC_CONTEXT_NONE                 ((uint32_t)0x00000000U)  /*!< None                             */
+#define   MMC_CONTEXT_READ_SINGLE_BLOCK    ((uint32_t)0x00000001U)  /*!< Read single block operation      */
+#define   MMC_CONTEXT_READ_MULTIPLE_BLOCK  ((uint32_t)0x00000002U)  /*!< Read multiple blocks operation   */
+#define   MMC_CONTEXT_WRITE_SINGLE_BLOCK   ((uint32_t)0x00000010U)  /*!< Write single block operation     */
+#define   MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)  /*!< Write multiple blocks operation  */
+#define   MMC_CONTEXT_IT                   ((uint32_t)0x00000008U)  /*!< Process in Interrupt mode        */
+#define   MMC_CONTEXT_DMA                  ((uint32_t)0x00000080U)  /*!< Process in DMA mode              */  
+
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
+  * @{
+  */
+/** 
+  * @brief 
+  */
+#define MMC_HIGH_VOLTAGE_RANGE         0x80FF8000U  /*!< VALUE OF ARGUMENT            */
+#define MMC_DUAL_VOLTAGE_RANGE         0x80FF8080U  /*!< VALUE OF ARGUMENT            */
+#define eMMC_HIGH_VOLTAGE_RANGE        0xC0FF8000U  /*!< for eMMC > 2Gb sector mode   */
+#define eMMC_DUAL_VOLTAGE_RANGE        0xC0FF8080U  /*!< for eMMC > 2Gb sector mode   */
+#define MMC_INVALID_VOLTAGE_RANGE      0x0001FF01U 
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
+  * @{
+  */
+#define  MMC_HIGH_VOLTAGE_CARD     ((uint32_t)0x00000000U)
+#define  MMC_DUAL_VOLTAGE_CARD     ((uint32_t)0x00000001U)
+/**
+  * @}
+  */
+      
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup MMC_Exported_macros MMC Exported Macros
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+ 
+/**
+  * @brief  Enable the MMC device.
+  * @retval None
+  */ 
+#define __HAL_MMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
+
+/**
+  * @brief  Disable the MMC device.
+  * @retval None
+  */
+#define __HAL_MMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)
+
+/**
+  * @brief  Enable the SDMMC DMA transfer.
+  * @retval None
+  */ 
+#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
+
+/**
+  * @brief  Disable the SDMMC DMA transfer.
+  * @retval None
+  */
+#define __HAL_MMC_DMA_DISABLE(__HANDLE__)  __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
+ 
+/**
+  * @brief  Enable the MMC device interrupt.
+  * @param  __HANDLE__: MMC Handle  
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
+  * @retval None
+  */
+#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the MMC device interrupt.
+  * @param  __HANDLE__: MMC Handle   
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt   
+  * @retval None
+  */
+#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified MMC flag is set or not. 
+  * @param  __HANDLE__: MMC Handle   
+  * @param  __FLAG__: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress
+  *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress
+  *            @arg SDMMC_FLAG_RXACT:    Data receive in progress
+  *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+  *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
+  *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full
+  *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full
+  *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty
+  *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty
+  *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO
+  *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO
+  *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received
+  * @retval The new state of MMC FLAG (SET or RESET).
+  */
+#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Clear the MMC's pending flags.
+  * @param  __HANDLE__: MMC Handle  
+  * @param  __FLAG__: specifies the flag to clear.  
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received
+  * @retval None
+  */
+#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Check whether the specified MMC interrupt has occurred or not.
+  * @param  __HANDLE__: MMC Handle   
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
+  * @retval The new state of SD IT (SET or RESET).
+  */
+#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Clear the MMC's interrupt pending bits.
+  * @param  __HANDLE__: MMC Handle
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
+  * @retval None
+  */
+#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @}
+  */
+  
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup MMC_Exported_Functions MMC Exported Functions
+  * @{
+  */
+  
+/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
+void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
+/**
+  * @}
+  */
+  
+/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+/* Non-Blocking mode: IT */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+
+void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
+
+/* Callback in non blocking modes (DMA) */
+void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
+/**
+  * @}
+  */
+  
+/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
+  * @{
+  */
+HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef        HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef        HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef        HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
+  * @{
+  */
+HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
+uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management
+  * @{
+  */
+HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
+/**
+  * @}
+  */
+    
+/* Private types -------------------------------------------------------------*/
+/** @defgroup MMC_Private_Types MMC Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup MMC_Private_Defines MMC Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+          
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Variables MMC Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Constants MMC Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup MMC_Private_Macros MMC Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Functions MMC Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F7xx_HAL_MMC_H */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_nand.h
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   Header file of NAND HAL module.
   ******************************************************************************
   * @attention
@@ -94,7 +94,7 @@ typedef struct
 {
   uint16_t Page;   /*!< NAND memory Page address  */
 
-  uint16_t Zone;   /*!< NAND memory Zone address  */
+  uint16_t Plane;   /*!< NAND memory Zone address  */
 
   uint16_t Block;  /*!< NAND memory Block address */
 
@@ -105,31 +105,43 @@ typedef struct
   */ 
 typedef struct
 {
-  uint32_t PageSize;       /*!< NAND memory page (without spare area) size measured in K. bytes */
+  uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes 
+                                              for 8 bits adressing or words for 16 bits addressing             */
 
-  uint32_t SpareAreaSize;  /*!< NAND memory spare area size measured in K. bytes                */
+  uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes 
+                                              for 8 bits adressing or words for 16 bits addressing             */
+  
+  uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
 
-  uint32_t BlockSize;      /*!< NAND memory block size number of pages                          */
+  uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
+     
+  uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
 
-  uint32_t BlockNbr;       /*!< NAND memory number of blocks                                    */
+  uint32_t        PlaneSize;             /*!< NAND memory zone size measured in number of blocks               */
 
-  uint32_t ZoneSize;       /*!< NAND memory zone size measured in number of blocks              */
+  FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This 
-}NAND_InfoTypeDef;
+                                              parameter is mandatory for some NAND parts after the read 
+                                              command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. 
+                                              Example: Toshiba THTH58BYG3S0HBAI6.
+                                              This parameter could be ENABLE or DISABLE
+                                              Please check the Read Mode sequnece in the NAND device datasheet */
+}NAND_DeviceConfigTypeDef; 
 
 /** 
   * @brief  NAND handle Structure definition
   */   
 typedef struct
 {
-  FMC_NAND_TypeDef             *Instance;  /*!< Register base address                        */
+  FMC_NAND_TypeDef               *Instance;  /*!< Register base address                                 */
   
-  FMC_NAND_InitTypeDef         Init;       /*!< NAND device control configuration parameters */
+  FMC_NAND_InitTypeDef           Init;       /*!< NAND device control configuration parameters          */
 
-  HAL_LockTypeDef              Lock;       /*!< NAND locking object                          */
+  HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */
 
-  __IO HAL_NAND_StateTypeDef   State;      /*!< NAND device access state                     */
+  __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
+
+  NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */
 
-  NAND_InfoTypeDef             Info;       /*!< NAND characteristic information structure    */
 }NAND_HandleTypeDef;
 /**
   * @}
@@ -163,6 +175,11 @@ typedef struct
 /* Initialization/de-initialization functions  ********************************/
 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
+
+HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
+
+HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+
 void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
 void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
@@ -177,19 +194,21 @@ void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
   */
 
 /* IO operation functions  ****************************************************/
-HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+
 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
 
 HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
 HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
-uint32_t           HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+
 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 
 /**
@@ -271,7 +290,9 @@ uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
   * @retval NAND Raw address value
   */
 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
-                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
+                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
+
+#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
 
 /**
   * @brief  NAND memory address cycling.
@@ -282,6 +303,15 @@ uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
+
+/**
+  * @brief  NAND memory Columns cycling.
+  * @param  __ADDRESS__: NAND memory address.
+  * @retval NAND Column address cycling value.
+  */
+#define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st Column addressing cycle */
+#define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */
+
 /**
   * @}
   */

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nor.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_nor.c
   * @author  MCD Application Team
-  * @version V1.1.2
+  * @version V1.2.0
-  * @date    23-September-2016 
+  * @date    30-December-2016
   * @brief   NOR HAL module driver.
   *          This file provides a generic firmware to drive NOR memories mounted 
   *          as external device.