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[NUCLEO_F103RB] Update rtc + serial

pull/329/head
bcostm 2014-05-27 09:05:26 +02:00
parent 57db78211c
commit 20fee9fbff
2 changed files with 9 additions and 6 deletions
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7
libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/rtc_api.c
View File

@ -87,7 +87,12 @@ void rtc_init(void) {
} }
void rtc_free(void) { void rtc_free(void) {
RCC_DeInit(); // Resets the RCC clock configuration to the default reset state // Disable RTC, LSE and LSI clocks
PWR_BackupAccessCmd(ENABLE); // Allow access to Backup Domain
RCC_RTCCLKCmd(DISABLE);
RCC_LSEConfig(RCC_LSE_OFF);
RCC_LSICmd(DISABLE);
rtc_inited = 0; rtc_inited = 0;
} }

8
libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/serial_api.c
View File

@ -95,12 +95,15 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
// Enable USART clock // Enable USART clock
if (obj->uart == UART_1) { if (obj->uart == UART_1) {
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
obj->index = 0;
} }
if (obj->uart == UART_2) { if (obj->uart == UART_2) {
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
obj->index = 1;
} }
if (obj->uart == UART_3) { if (obj->uart == UART_3) {
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
obj->index = 2;
} }
// Configure the UART pins // Configure the UART pins
@ -118,11 +121,6 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
init_usart(obj); init_usart(obj);
// The index is used by irq
if (obj->uart == UART_1) obj->index = 0;
if (obj->uart == UART_2) obj->index = 1;
if (obj->uart == UART_3) obj->index = 2;
// For stdio management // For stdio management
if (obj->uart == STDIO_UART) { if (obj->uart == STDIO_UART) {
stdio_uart_inited = 1; stdio_uart_inited = 1;