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Merge pull request #182 from sg-/nxp_master_merge 

NXP master merge
pull/183/head
Emilio Monti 2014-02-20 22:57:10 +00:00
parent 65f5457fff 1edb07ae94
commit 1f2da5f604
29 changed files with 5049 additions and 4 deletions
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1721
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/LPC15xx.h Normal file
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libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/LPC15xx.sct Normal file
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LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(16+47 vect * 4 bytes) = 0x100
; 36kB(0x9000) - 0x100 = 0x8F00
RW_IRAM1 (0x02000000+0x100) (0x9000-0x100) {
.ANY (+RW +ZI)
}
}

316
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/startup_LPC15xx.s Normal file
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;/**************************************************************************//**
; * @file startup_LPC15xx.s
; * @brief CMSIS Cortex-M3 Core Device Startup File for
; * NXP LPC15xx Device Series
; * @version V1.00
; * @date 17. July 2013
; *
; * @note
; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 16+ 0 Windowed watchdog timer interrupt
DCD BOD_IRQHandler ; 16+ 1 BOD interrupt
DCD FLASH_IRQHandler ; 16+ 2 Flash controller interrupt
DCD EE_IRQHandler ; 16+ 3 EEPROM controller interrupt
DCD DMA_IRQHandler ; 16+ 4 DMA interrupt
DCD GINT0_IRQHandler ; 16+ 5 GPIO group0 interrupt
DCD GINT1_IRQHandler ; 16+ 6 GPIO group1 interrupt
DCD PIN_INT0_IRQHandler ; 16+ 7 Pin interrupt 0 or pattern match engine slice 0 interrupt
DCD PIN_INT1_IRQHandler ; 16+ 8 Pin interrupt 1 or pattern match engine slice 1 interrupt
DCD PIN_INT2_IRQHandler ; 16+ 9 Pin interrupt 2 or pattern match engine slice 2 interrupt
DCD PIN_INT3_IRQHandler ; 16+10 Pin interrupt 3 or pattern match engine slice 3 interrupt
DCD PIN_INT4_IRQHandler ; 16+11 Pin interrupt 4 or pattern match engine slice 4 interrupt
DCD PIN_INT5_IRQHandler ; 16+12 Pin interrupt 5 or pattern match engine slice 5 interrupt
DCD PIN_INT6_IRQHandler ; 16+13 Pin interrupt 6 or pattern match engine slice 6 interrupt
DCD PIN_INT7_IRQHandler ; 16+14 Pin interrupt 7 or pattern match engine slice 7 interrupt
DCD RIT_IRQHandler ; 16+15 RIT interrupt
DCD SCT0_IRQHandler ; 16+16 State configurable timer interrupt
DCD SCT1_IRQHandler ; 16+17 State configurable timer interrupt
DCD SCT2_IRQHandler ; 16+18 State configurable timer interrupt
DCD SCT3_IRQHandler ; 16+19 State configurable timer interrupt
DCD MRT_IRQHandler ; 16+20 Multi-rate timer interrupt
DCD UART0_IRQHandler ; 16+21 USART0 interrupt
DCD UART1_IRQHandler ; 16+22 USART1 interrupt
DCD UART2_IRQHandler ; 16+23 USART2 interrupt
DCD I2C0_IRQHandler ; 16+24 I2C0 interrupt
DCD SPI0_IRQHandler ; 16+25 SPI0 interrupt
DCD SPI1_IRQHandler ; 16+26 SPI1 interrupt
DCD C_CAN0_IRQHandler ; 16+27 C_CAN0 interrupt
DCD USB_IRQ_IRQHandler ; 16+28 USB interrupt
DCD USB_FIQ_IRQHandler ; 16+29 USB interrupt
DCD USBWAKEUP_IRQHandler ; 16+30 USB wake-up interrupt
DCD ADC0_SEQA_IRQHandler ; 16+31 ADC0 sequence A completion.
DCD ADC0_SEQB_IRQHandler ; 16+32 ADC0 sequence B completion.
DCD ADC0_THCMP_IRQHandler ; 16+33 ADC0 threshold compare
DCD ADC0_OVR_IRQHandler ; 16+34 ADC0 overrun
DCD ADC1_SEQA_IRQHandler ; 16+35 ADC1 sequence A completion.
DCD ADC1_SEQB_IRQHandler ; 16+36 ADC1 sequence B completion.
DCD ADC1_THCMP_IRQHandler ; 16+37 ADC1 threshold compare
DCD ADC1_OVR_IRQHandler ; 16+38 ADC1 overrun
DCD DAC_IRQHandler ; 16+39 DAC interrupt
DCD CMP0_IRQHandler ; 16+40 Analog comparator 0 interrupt (ACMP0)
DCD CMP1_IRQHandler ; 16+41 Analog comparator 1 interrupt (ACMP1)
DCD CMP2_IRQHandler ; 16+42 Analog comparator 2 interrupt (ACMP2)
DCD CMP3_IRQHandler ; 16+43 Analog comparator 3 interrupt (ACMP3)
DCD QEI_IRQHandler ; 16+44 QEI interrupt
DCD RTC_ALARM_IRQHandler ; 16+45 RTC alarm interrupt
DCD RTC_WAKE_IRQHandler ; 16+46 RTC wake-up interrut
; <h> Code Read Protection
; <o> Code Read Protection <0xFFFFFFFF=>CRP Disabled
; <0x12345678=>CRP Level 1
; <0x87654321=>CRP Level 2
; <0x43218765=>CRP Level 3 (ARE YOU SURE?)
; <0x4E697370=>NO ISP (ARE YOU SURE?)
; </h>
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
;--- enable SRAM1 and SRAM2 memory
LDR R0, =0x400740C4 ; SYSAHBCLKCTRL0 register addr
LDR R2, [R0] ; read SYSAHBCLKCTRL0
ORR R2, R2, #0x18 ; enable SRAM1, SRAM2
STR R2, [R0] ; store SYSAHBCLKCTRL0
;---
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT EE_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT PIN_INT0_IRQHandler [WEAK]
EXPORT PIN_INT1_IRQHandler [WEAK]
EXPORT PIN_INT2_IRQHandler [WEAK]
EXPORT PIN_INT3_IRQHandler [WEAK]
EXPORT PIN_INT4_IRQHandler [WEAK]
EXPORT PIN_INT5_IRQHandler [WEAK]
EXPORT PIN_INT6_IRQHandler [WEAK]
EXPORT PIN_INT7_IRQHandler [WEAK]
EXPORT RIT_IRQHandler [WEAK]
EXPORT SCT0_IRQHandler [WEAK]
EXPORT SCT1_IRQHandler [WEAK]
EXPORT SCT2_IRQHandler [WEAK]
EXPORT SCT3_IRQHandler [WEAK]
EXPORT MRT_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT C_CAN0_IRQHandler [WEAK]
EXPORT USB_IRQ_IRQHandler [WEAK]
EXPORT USB_FIQ_IRQHandler [WEAK]
EXPORT USBWAKEUP_IRQHandler [WEAK]
EXPORT ADC0_SEQA_IRQHandler [WEAK]
EXPORT ADC0_SEQB_IRQHandler [WEAK]
EXPORT ADC0_THCMP_IRQHandler [WEAK]
EXPORT ADC0_OVR_IRQHandler [WEAK]
EXPORT ADC1_SEQA_IRQHandler [WEAK]
EXPORT ADC1_SEQB_IRQHandler [WEAK]
EXPORT ADC1_THCMP_IRQHandler [WEAK]
EXPORT ADC1_OVR_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT CMP1_IRQHandler [WEAK]
EXPORT CMP2_IRQHandler [WEAK]
EXPORT CMP3_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
EXPORT RTC_ALARM_IRQHandler [WEAK]
EXPORT RTC_WAKE_IRQHandler [WEAK]
WDT_IRQHandler
BOD_IRQHandler
FLASH_IRQHandler
EE_IRQHandler
DMA_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
PIN_INT0_IRQHandler
PIN_INT1_IRQHandler
PIN_INT2_IRQHandler
PIN_INT3_IRQHandler
PIN_INT4_IRQHandler
PIN_INT5_IRQHandler
PIN_INT6_IRQHandler
PIN_INT7_IRQHandler
RIT_IRQHandler
SCT0_IRQHandler
SCT1_IRQHandler
SCT2_IRQHandler
SCT3_IRQHandler
MRT_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
I2C0_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
C_CAN0_IRQHandler
USB_IRQ_IRQHandler
USB_FIQ_IRQHandler
USBWAKEUP_IRQHandler
ADC0_SEQA_IRQHandler
ADC0_SEQB_IRQHandler
ADC0_THCMP_IRQHandler
ADC0_OVR_IRQHandler
ADC1_SEQA_IRQHandler
ADC1_SEQB_IRQHandler
ADC1_THCMP_IRQHandler
ADC1_OVR_IRQHandler
DAC_IRQHandler
CMP0_IRQHandler
CMP1_IRQHandler
CMP2_IRQHandler
CMP3_IRQHandler
QEI_IRQHandler
RTC_ALARM_IRQHandler
RTC_WAKE_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
END

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libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/sys.cpp Normal file
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/* mbed Microcontroller Library - stackheap
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* Setup a fixed single stack/heap memory model,
* between the top of the RW/ZI region and the stackpointer
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

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libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis.h Normal file
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/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in LPC8xx specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "LPC15xx.h"
#include "cmsis_nvic.h"
#endif

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libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis_nvic.c Normal file
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/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
* Copyright (c) 2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x02000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
uint32_t i;
// Copy and switch to dynamic vectors if the first time called
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
uint32_t *old_vectors = vectors;
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
for (i=0; i<NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
}
vectors[IRQn + 16] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}

26
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis_nvic.h Normal file
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/* mbed Microcontroller Library - cmsis_nvic
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 47) // CORE + MCU Peripherals
#define NVIC_USER_IRQ_OFFSET 16
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c Normal file
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/**************************************************************************//**
* @file system_LPC15xx.c
* @brief CMSIS Cortex-M3 Device System Source File for
* NXP LPC15xx Device Series
* @version V1.00
* @date 19. July 2013
*
* @note
* Copyright (C) 2013 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include "LPC15xx.h"
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*- SystemCoreClock Configuration -------------------------------------------*/
// <e0> SystemCoreClock Configuration
#define CLOCK_SETUP 1
//
// <h> System Oscillator Control (SYSOSCCTRL)
// <o.0> BYPASS: System Oscillator Bypass Enable
// <i> If enabled then PLL input (sys_osc_clk) is fed
// <i> directly from XTALIN and XTALOUT pins.
// <o.1> FREQRANGE: System Oscillator Frequency Range
// <i> Determines frequency range for Low-power oscillator.
// <0=> 1 - 20 MHz
// <1=> 15 - 25 MHz
// </h>
#define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000
//
// <o.0..1> System PLL Clock Source Select (SYSPLLCLKSEL)
// <0=> IRC Oscillator
// <1=> Crystal Oscillator (SYSOSC)
#define SYSPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
//
// <e> Clock Configuration (Manual)
#define CLOCK_SETUP_REG 1
//
// <o.0..1> Main Clock Source Select A (MAINCLKSELA)
// <0=> IRC Oscillator
// <1=> System Oscillator
// <2=> WD Oscillator
#define MAINCLKSELA_Val 0x00000001 // Reset value: 0x000
//
// <o.0..1> Main Clock Source Select B (MAINCLKSELB)
// <0=> MAINCLKSELA
// <1=> System PLL Input
// <2=> System PLL Output
// <3=> RTC Oscillator
#define MAINCLKSELB_Val 0x00000002 // Reset value: 0x000
//
// <h> System PLL Setting (SYSPLLCTRL)
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
// <o.0..5> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o.5..7> PSEL: Post Divider Selection
// <i> Post divider ratio P. Division ratio is 2 * P
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
#define SYSPLLCTRL_Val 0x00000005 // Reset value: 0x000
//
// <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV)
// <i> Divides main clock to provide system clock to core, memories, and peripherals.
// <i> 0 = is disabled
// <0-255>
#define SYSAHBCLKDIV_Val 0x00000001 // Reset value: 0x001
// </e>
//
// <e> Clock Configuration (via ROM PLL API)
#define CLOCK_SETUP_API 0
//
// <o> PLL API Mode Select
// <0=> Exact
// <1=> Less than or equal
// <2=> Greater than or equal
// <3=> As close as possible
#define PLL_API_MODE_Val 0
//
// <o> CPU Frequency [Hz] <1000000-72000000:1000>
#define PLL_API_FREQ_Val 72000000
// </e>
//
// <e> USB Clock Configuration
#define USB_CLOCK_SETUP 0
// <h> USB PLL Control (USBPLLCTRL)
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
// <o.0..5> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o.7..6> PSEL: Post Divider Selection
// <i> Post divider ratio P. Division ratio is 2 * P
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
#define USBPLLCTRL_Val 0x00000023 // Reset value: 0x000
//
// <o.0..1> USB PLL Clock Source Select (USBPLLCLKSEL.SEL)
// <0=> IRC Oscillator
// <1=> System Oscillator
#define USBPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
//
// <o.0..1> USB Clock Source Select (USBCLKSEL.SEL)
// <0=> IRC Oscillator
// <1=> System Oscillator
// <2=> USB PLL out
// <3=> Main clock
#define USBCLKSEL_Val 0x00000002 // Reset value: 0x000
//
// <o.0..7> USB Clock Divider (USBCLKDIV.DIV)
// <i> Divides USB clock to 48 MHz.
// <i> 0 = is disabled
// <0-255>
#define USBCLKDIV_Val 0x00000001 // Reset Value: 0x001
// </e>
//
// <e> SCT Clock Configuration
#define SCT_CLOCK_SETUP 1
// <h> SCT PLL Control (SCTPLLCTRL)
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
// <o.0..5> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o.7..6> PSEL: Post Divider Selection
// <i> Post divider ratio P. Division ratio is 2 * P
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
#define SCTPLLCTRL_Val 0x00000005 // Reset value: 0x000
//
// <o.0..1> SCT PLL Clock Source Select (SCTPLLCLKSEL.SEL)
// <0=> IRC Oscillator
// <1=> System Oscillator
#define SCTPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
// </e>
//
// </e>
//
// <o0>System Oscillator (XTAL) Frequency [Hz] <1000000-25000000>
// <i> XTAL frequency must be in the range of 1 MHz to 25 MHz
//
#define XTAL_CLK_Val 12000000
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */
#define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */
#define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */
#define __RTC_OSC_CLK ( 32768UL) /* RTC oscillator freq */
#define __WDT_OSC_CLK ( 503000UL) /* WDT oscillator freq */
/*----------------------------------------------------------------------------
Check the register settings
*----------------------------------------------------------------------------*/
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
#define CHECK_RSVD(val, mask) (val & mask)
#if (CHECK_RANGE((SYSOSCCTRL_Val), 0, 1))
#error "SYSOSCCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
#error "SYSPLLCLKSEL: Value out of range!"
#endif
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000000FF))
#error "SYSPLLCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((MAINCLKSELA_Val), 0, 2))
#error "MAINCLKSELA: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((MAINCLKSELB_Val), ~0x00000003))
#error "MAINCLKSELB: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
#error "SYSAHBCLKDIV: Value out of range!"
#endif
#if ( CLOCK_SETUP_REG == CLOCK_SETUP_API )
#error "You must select either manual or API based Clock Configuration!"
#endif
#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
#error "USBPLLCLKSEL: Value out of range!"
#endif
#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x00000FF))
#error "USBPLLCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((USBCLKSEL_Val), 0, 3))
#error "USBCLKSEL: Value out of range!"
#endif
#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
#error "USBCLKDIV: Value out of range!"
#endif
#if (CHECK_RANGE((SCTPLLCLKSEL_Val), 0, 1))
#error "SCTPLLCLKSEL: Value out of range!"
#endif
#if (CHECK_RSVD((SCTPLLCTRL_Val), ~0x00000FF))
#error "SCTPLLCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000))
#error "XTAL frequency is out of bounds"
#endif
#if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3))
#error "PLL API Mode Select not valid"
#endif
#if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 72000000))
#error "CPU Frequency (API mode) not valid"
#endif
/*----------------------------------------------------------------------------
Calculate system core clock
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP) /* Clock Setup */
/* sys_pllclkin calculation */
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
#else
#error "Oops"
#endif
#if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
#if ((MAINCLKSELA_Val & 0x03) == 0)
#define __MAINA_CLOCK (__IRC_OSC_CLK)
#elif ((MAINCLKSELA_Val & 0x03) == 1)
#define __MAINA_CLOCK (__SYS_OSC_CLK)
#elif ((MAINCLKSELA_Val & 0x03) == 2)
#define __MAINA_CLOCK (__WDT_OSC_CLK)
#else
#error "Oops"
#endif
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
/* main clock calculation */
#if ((MAINCLKSELB_Val & 0x03) == 0)
#define __MAINB_CLOCK (__MAINA_CLOCK)
#elif ((MAINCLKSELB_Val & 0x03) == 1)
#define __MAINB_CLOCK (__SYS_PLLCLKIN)
#elif ((MAINCLKSELB_Val & 0x03) == 2)
#define __MAINB_CLOCK (__SYS_PLLCLKOUT)
#elif ((MAINCLKSELB_Val & 0x03) == 3)
#define __MAINB_CLOCK (__RTC_OSC_CLK)
#else
#error "Oops"
#endif
#define __SYSTEM_CLOCK (__MAINB_CLOCK / SYSAHBCLKDIV_Val)
#endif /* Clock Setup via Register */
#if (CLOCK_SETUP_API == 1) /* Clock Setup via ROM API */
#define __SYSTEM_CLOCK (PLL_API_FREQ_Val)
#endif /* Clock Setup via PLL API */
#else
#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
#endif /* CLOCK_SETUP */
#if ((CLOCK_SETUP == 1) && (CLOCK_SETUP_API == 1)) /* PLL Setup via PLL API */
#include "power_api.h"
typedef struct _ROM {
const unsigned p_dev0;
const unsigned p_dev1;
const unsigned p_dev2;
const PWRD * pPWRD; /* ROM Power Management API */
const unsigned p_dev4;
const unsigned p_dev5;
const unsigned p_dev6;
const unsigned p_dev7;
} ROM;
/*----------------------------------------------------------------------------
PLL API Function
*----------------------------------------------------------------------------*/
static void setPLL(const uint32_t pllMode, const uint32_t pllInFreq, const uint32_t reqCpuFreq)
{
uint32_t cmd[5], res[5];
ROM ** rom = (ROM **) 0x03000200; /* pointer to power API calls */
cmd[0] = pllInFreq; /* PLL's input freq in KHz */
cmd[1] = reqCpuFreq; /* requested CPU freq in KHz */
cmd[2] = pllMode;
cmd[3] = 0; /* no timeout for PLL to lock */
/* Execute API call */
(*rom)->pPWRD->set_pll(cmd, res); /* call API function */
if ((res[0] != PLL_CMD_SUCCESS)){ /* in case of an error ... */
while(1); /* ... stay here */
}
}
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /* System Clock Frequency */
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
/* Determine clock frequency according to clock register values */
switch (LPC_SYSCON->MAINCLKSELB & 0x03) {
case 0: /* MAINCLKSELA clock sel */
switch (LPC_SYSCON->MAINCLKSELA & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK;
break;
case 1: /* System oscillator */
SystemCoreClock = __SYS_OSC_CLK;
break;
case 2: /* Watchdog oscillator */
SystemCoreClock = __WDT_OSC_CLK;
break;
case 3: /* Reserved */
SystemCoreClock = 0;
break;
}
break;
case 1: /* Input Clock to System PLL */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK;
break;
case 1: /* System oscillator */
SystemCoreClock = __SYS_OSC_CLK;
break;
case 2: /* Reserved */
case 3: /* Reserved */
SystemCoreClock = 0;
break;
}
break;
case 2: /* System PLL Clock Out */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
break;
case 1: /* System oscillator */
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
break;
case 2: /* Reserved */
case 3: /* Reserved */
SystemCoreClock = 0;
break;
}
break;
case 3: /* WDT Oscillator */
SystemCoreClock = __WDT_OSC_CLK;
break;
}
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
*/
void SystemInit (void) {
#if (CLOCK_SETUP)
volatile uint32_t i;
#endif
#if (CLOCK_SETUP) /* Clock Setup */
#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 21); /* Power-up sysosc */
for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
#endif
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
#if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
#if (((MAINCLKSELA_Val & 0x03) == 1) )
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 21); /* Power-up sysosc */
for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
#endif
#if (((MAINCLKSELA_Val & 0x03) == 2) )
LPC_SYSCON->PDRUNCFG &= ~(1 << 20); /* Power-up WDT Clock */
for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
#endif
#if ((MAINCLKSELB_Val & 0x03) == 3)
LPC_SYSCON->RTCOSCCTRL = (1 << 0); /* Enable 32 kHz output */
for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
#endif
LPC_SYSCON->MAINCLKSELA = MAINCLKSELA_Val; /* select MAINCLKA clock */
#if ((MAINCLKSELB_Val & 0x03) == 2) /* Main Clock is PLL Out */
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 22); /* Power-up SYSPLL */
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
#endif
LPC_SYSCON->MAINCLKSELB = MAINCLKSELB_Val; /* select Main clock */
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
#endif /* Clock Setup via Register */
#if (CLOCK_SETUP_API == 1) /* Clock Setup via PLL API */
// LPC_SYSCON->SYSPLLCLKSEL = 0x00; /* Use IRC */
LPC_SYSCON->MAINCLKSELB = (1 << 2); /* Select System PLL output */
LPC_SYSCON->SYSAHBCLKDIV = 1;
setPLL(PLL_API_MODE_Val, __SYS_PLLCLKIN / 1000, PLL_API_FREQ_Val / 1000);
#endif /* Clock Setup via PLL API */
#if (USB_CLOCK_SETUP == 1) /* USB clock is used */
LPC_SYSCON->PDRUNCFG &= ~(1 << 9); /* Power-up USB PHY */
#if ((USBCLKSEL_Val & 0x003) == 2) /* USB clock is USB PLL out */
LPC_SYSCON->PDRUNCFG &= ~(1 << 23); /* Power-up USB PLL */
LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
LPC_SYSCON->USBCLKSEL = 0x02; /* Select USB PLL */
#endif
LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
#else /* USB clock is not used */
LPC_SYSCON->PDRUNCFG |= (1 << 9); /* Power-down USB PHY */
LPC_SYSCON->PDRUNCFG |= (1 << 23); /* Power-down USB PLL */
#endif
#if (SCT_CLOCK_SETUP == 1) /* SCT clock is used */
LPC_SYSCON->PDRUNCFG &= ~(1 << 24); /* Power-up SCT PLL */
LPC_SYSCON->SCTPLLCLKSEL = SCTPLLCLKSEL_Val; /* Select PLL Input */
LPC_SYSCON->SCTPLLCTRL = SCTPLLCTRL_Val;
while (!(LPC_SYSCON->SCTPLLSTAT & 0x01)); /* Wait Until PLL Locked */
#else /* SCT clock is not used */
LPC_SYSCON->PDRUNCFG |= (1 << 24); /* Power-down SCT PLL */
#endif
#endif /* Clock Setup */
LPC_SYSCON->SYSAHBCLKCTRL0 |= (1UL << 12); /* enable clock for SWM */
}

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/**************************************************************************//**
* @file system_LPC15xx.h
* @brief CMSIS Cortex-M3 Device System Header File for
* NXP LPC15xx Device Series
* @version V1.00
* @date 19. July 2013
*
* @note
* Copyright (C) 2013 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __SYSTEM_LPC15xx_H
#define __SYSTEM_LPC15xx_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/** @addtogroup LPC15xx_System
* @{
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
#endif /* __SYSTEM_LPC15xx_H */

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3,
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7,
ADC0_8,
ADC0_9,
ADC0_10,
ADC0_11,
ADC1_0,
ADC1_1,
ADC1_2,
ADC1_3,
ADC1_4,
ADC1_5,
ADC1_6,
ADC1_7,
ADC1_8,
ADC1_9,
ADC1_10,
ADC1_11,
} ADCName;
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/PinNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
// LPC Pin Names
P0_0 = 0,
P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12,
LED_RED = P0_25,
LED_GREEN = P0_3,
LED_BLUE = P1_1,
// mbed original LED naming
LED1 = LED_BLUE,
LED2 = LED_GREEN,
LED3 = LED_RED,
LED4 = LED_RED,
// Serial to USB pins
USBTX = P0_18,
USBRX = P0_13,
// Arduino Shield Receptacles Names
D0 = P0_13,
D1 = P0_18,
D2 = P0_29,
D3 = P0_9,
D4 = P0_10,
D5 = P0_16, // same port as D13
D6 = P1_3,
D7 = P0_0,
D8 = P0_24,
D9 = P1_0,
D10= P0_27,
D11= P0_28,
D12= P0_12,
D13= P0_16, // same port as D5
A0 = P0_8,
A1 = P0_7,
A2 = P0_6,
A3 = P0_5,
A4 = P0_23, // same port as SDA
A5 = P0_22, // same port as SCL
SDA= P0_23, // same port as A4
SCL= P0_22, // same port as A5
// Not connected
NC = (int)0xFFFFFFFF,
} PinName;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4
} PinMode;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
typedef struct {
unsigned char n;
unsigned char offset;
} SWM_Map;
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/PortNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
Port0 = 0,
Port1 = 1,
Port2 = 2
} PortName;
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "analogin_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
#define ANALOGIN_MEDIAN_FILTER 1
#define ADC_10BIT_RANGE 0x3FF
#define ADC_12BIT_RANGE 0xFFF
#define ADC_RANGE ADC_12BIT_RANGE
static const PinMap PinMap_ADC[] = {
{P0_8 , ADC0_0, 0},
{P0_7 , ADC0_1, 0},
{P0_6 , ADC0_2, 0},
{P0_5 , ADC0_3, 0},
{P0_4 , ADC0_4, 0},
{P0_3 , ADC0_5, 0},
{P0_2 , ADC0_6, 0},
{P0_1 , ADC0_7, 0},
{P1_0 , ADC0_8, 0},
{P0_31, ADC0_9, 0},
{P0_0 , ADC0_10,0},
{P0_30, ADC0_11,0},
{P1_1 , ADC1_0, 0},
{P0_9 , ADC1_1, 0},
{P0_10, ADC1_2, 0},
{P0_11, ADC1_3, 0},
{P1_2 , ADC1_4, 0},
{P1_3 , ADC1_5, 0},
{P0_13, ADC1_6, 0},
{P0_14, ADC1_7, 0},
{P0_15, ADC1_8, 0},
{P0_16, ADC1_9, 0},
{P1_4 , ADC1_10,0},
{P1_5 , ADC1_11,0},
};
void analogin_init(analogin_t *obj, PinName pin) {
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
if (obj->adc == (uint32_t)NC) {
error("ADC pin mapping failed");
}
uint32_t port = (pin >> 5);
// enable clock for GPIOx
LPC_SYSCON->SYSAHBCLKCTRL0 |= (1UL << (14 + port));
// pin enable
LPC_SWM->PINENABLE0 &= ~(1UL << obj->adc);
// configure GPIO as input
LPC_GPIO_PORT->DIR[port] &= ~(1UL << (pin & 0x1F));
// power up ADC
if (obj->adc < ADC1_0)
{
// ADC0
LPC_SYSCON->PDRUNCFG &= ~(1 << 10);
LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 27);
}
else {
// ADC1
LPC_SYSCON->PDRUNCFG &= ~(1 << 11);
LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 28);
}
// select IRC as async. clock, divided by 1
LPC_SYSCON->ADCASYNCCLKSEL = 0;
LPC_SYSCON->ADCASYNCCLKDIV = 1;
__IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1);
// start calibration
adc_reg->CTRL |= (1UL << 30);
__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
// asynchronous mode
adc_reg->CTRL = (1UL << 8);
}
static inline uint32_t adc_read(analogin_t *obj) {
__IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1);
// select channel
adc_reg->SEQA_CTRL &= ~(0xFFF);
adc_reg->SEQA_CTRL |= (1UL << (obj->adc & 0x1F));
// start conversion and sequence enable
adc_reg->SEQA_CTRL |= ((1UL << 26) | (1UL << 31));
// Repeatedly get the sample data until DONE bit
volatile uint32_t data;
do {
data = adc_reg->SEQA_GDAT;
} while ((data & (1UL << 31)) == 0);
// Stop conversion
adc_reg->SEQA_CTRL &= ~(1UL << 31);
return ((data >> 4) & ADC_RANGE);
}
static inline void order(uint32_t *a, uint32_t *b) {
if (*a > *b) {
uint32_t t = *a;
*a = *b;
*b = t;
}
}
static inline uint32_t adc_read_u32(analogin_t *obj) {
uint32_t value;
#if ANALOGIN_MEDIAN_FILTER
uint32_t v1 = adc_read(obj);
uint32_t v2 = adc_read(obj);
uint32_t v3 = adc_read(obj);
order(&v1, &v2);
order(&v2, &v3);
order(&v1, &v2);
value = v2;
#else
value = adc_read(obj);
#endif
return value;
}
uint16_t analogin_read_u16(analogin_t *obj) {
uint32_t value = adc_read_u32(obj);
return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
}
float analogin_read(analogin_t *obj) {
uint32_t value = adc_read_u32(obj);
return (float)value * (1.0f / (float)ADC_RANGE);
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_PORTIN 0
#define DEVICE_PORTOUT 0
#define DEVICE_PORTINOUT 0
#define DEVICE_INTERRUPTIN 1
#define DEVICE_ANALOGIN 1
#define DEVICE_ANALOGOUT 0
#define DEVICE_SERIAL 1
#define DEVICE_SERIAL_FC 1
#define DEVICE_I2C 1
#define DEVICE_I2CSLAVE 0
#define DEVICE_SPI 1
#define DEVICE_SPISLAVE 1
#define DEVICE_CAN 0
#define DEVICE_RTC 0
#define DEVICE_ETHERNET 0
#define DEVICE_PWMOUT 0
#define DEVICE_SEMIHOST 0
#define DEVICE_LOCALFILESYSTEM 0
#define DEVICE_SLEEP 0
#define DEVICE_DEBUG_AWARENESS 0
#define DEVICE_STDIO_MESSAGES 0
#define DEVICE_ERROR_RED 0
#include "objects.h"
#endif

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
#include "pinmap.h"
static int gpio_enabled = 0;
static void gpio_enable(void) {
gpio_enabled = 1;
/* Enable AHB clock to the GPIO0/1/2 and IOCON domain. */
LPC_SYSCON->SYSAHBCLKCTRL0 |= (0xFUL << 13);
}
uint32_t gpio_set(PinName pin) {
if (!gpio_enabled)
gpio_enable();
return (1UL << ((int)pin & 0x1f));
}
void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
if(pin == NC) return;
obj->pin = pin;
obj->mask = gpio_set(pin);
unsigned int port = (unsigned int)(pin >> 5);
obj->reg_set = &LPC_GPIO_PORT->SET[port];
obj->reg_clr = &LPC_GPIO_PORT->CLR[port];
obj->reg_in = &LPC_GPIO_PORT->PIN[port];
obj->reg_dir = &LPC_GPIO_PORT->DIR[port];
gpio_dir(obj, direction);
switch (direction) {
case PIN_OUTPUT: pin_mode(pin, PullNone); break;
case PIN_INPUT : pin_mode(pin, PullDown); break;
}
}
void gpio_mode(gpio_t *obj, PinMode mode) {
pin_mode(obj->pin, mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction) {
switch (direction) {
case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
}
}

139
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "cmsis.h"
#include "gpio_irq_api.h"
#include "error.h"
#define CHANNEL_NUM 8
#define LPC_GPIO_X LPC_PINT
#define PININT_IRQ PIN_INT0_IRQn
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler irq_handler;
static inline void handle_interrupt_in(uint32_t channel) {
uint32_t ch_bit = (1 << channel);
// Return immediately if:
// * The interrupt was already served
// * There is no user handler
// * It is a level interrupt, not an edge interrupt
if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
(channel_ids[channel] == 0 ) ||
(LPC_GPIO_X->ISEL & ch_bit ) ) return;
if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE);
LPC_GPIO_X->RISE = ch_bit;
}
if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_FALL);
LPC_GPIO_X->FALL = ch_bit;
}
LPC_GPIO_X->IST = ch_bit;
}
void gpio_irq0(void) {handle_interrupt_in(0);}
void gpio_irq1(void) {handle_interrupt_in(1);}
void gpio_irq2(void) {handle_interrupt_in(2);}
void gpio_irq3(void) {handle_interrupt_in(3);}
void gpio_irq4(void) {handle_interrupt_in(4);}
void gpio_irq5(void) {handle_interrupt_in(5);}
void gpio_irq6(void) {handle_interrupt_in(6);}
void gpio_irq7(void) {handle_interrupt_in(7);}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
// PINT only supprt GPIO port 0 and 1 interrupt
if (pin >= P2_0) return -1;
irq_handler = handler;
int found_free_channel = 0;
int i = 0;
for (i=0; i<CHANNEL_NUM; i++) {
if (channel_ids[i] == 0) {
channel_ids[i] = id;
obj->ch = i;
found_free_channel = 1;
break;
}
}
if (!found_free_channel) return -1;
/* Enable AHB clock to the PIN, GPIO0/1, IOCON and MUX domain. */
LPC_SYSCON->SYSAHBCLKCTRL0 |= ((1 << 18) | (0x1D << 11));
LPC_INMUX->PINTSEL[obj->ch] = pin;
// Interrupt Wake-Up Enable
LPC_SYSCON->STARTERP0 |= (1 << (obj->ch + 5));
LPC_GPIO_PORT->DIR[pin >> 5] &= ~(1 << (pin & 0x1F));
void (*channels_irq)(void) = NULL;
switch (obj->ch) {
case 0: channels_irq = &gpio_irq0; break;
case 1: channels_irq = &gpio_irq1; break;
case 2: channels_irq = &gpio_irq2; break;
case 3: channels_irq = &gpio_irq3; break;
case 4: channels_irq = &gpio_irq4; break;
case 5: channels_irq = &gpio_irq5; break;
case 6: channels_irq = &gpio_irq6; break;
case 7: channels_irq = &gpio_irq7; break;
}
NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
return 0;
}
void gpio_irq_free(gpio_irq_t *obj) {
channel_ids[obj->ch] = 0;
LPC_SYSCON->STARTERP0 &= ~(1 << (obj->ch + 5));
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
unsigned int ch_bit = (1 << obj->ch);
// Clear interrupt
if (!(LPC_GPIO_X->ISEL & ch_bit))
LPC_GPIO_X->IST = ch_bit;
// Edge trigger
LPC_GPIO_X->ISEL &= ~ch_bit;
if (event == IRQ_RISE) {
if (enable) {
LPC_GPIO_X->IENR |= ch_bit;
} else {
LPC_GPIO_X->IENR &= ~ch_bit;
}
} else {
if (enable) {
LPC_GPIO_X->IENF |= ch_bit;
} else {
LPC_GPIO_X->IENF &= ~ch_bit;
}
}
}
void gpio_irq_enable(gpio_irq_t *obj) {
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
}
void gpio_irq_disable(gpio_irq_t *obj) {
NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
}

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_object.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pin;
uint32_t mask;
__IO uint32_t *reg_dir;
__IO uint32_t *reg_set;
__IO uint32_t *reg_clr;
__I uint32_t *reg_in;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value) {
if (value)
*obj->reg_set = obj->mask;
else
*obj->reg_clr = obj->mask;
}
static inline int gpio_read(gpio_t *obj) {
return ((*obj->reg_in & obj->mask) ? 1 : 0);
}
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/i2c_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "i2c_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
static uint8_t repeated_start = 0;
#define I2C_STAT(x) ((LPC_I2C0->STAT >> 1) & (0x07))
static inline int i2c_status(i2c_t *obj) {
return I2C_STAT(obj);
}
// Wait until the Serial Interrupt (SI) is set
static int i2c_wait_SI(i2c_t *obj) {
int timeout = 0;
while (!(LPC_I2C0->STAT & (1 << 0))) {
timeout++;
if (timeout > 100000) return -1;
}
return 0;
}
static inline void i2c_interface_enable(i2c_t *obj) {
LPC_I2C0->CFG |= (1 << 0);
}
static inline void i2c_power_enable(i2c_t *obj) {
// Enables clock for I2C0
LPC_SYSCON->SYSAHBCLKCTRL1 |= (1<<13);
// LPC_SYSCON->PRESETCTRL1 &= ~(0x1<<13);
LPC_SYSCON->PRESETCTRL1 |= (0x1<<13);
LPC_SYSCON->PRESETCTRL1 &= ~(0x1 << 13);
}
void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
// ピン定義の確認どうしよう…
// enable power
i2c_power_enable(obj);
// pin enable
LPC_SWM->PINENABLE1 &= ~(0x3 << 3);
// set default frequency at 100k
i2c_frequency(obj, 100000);
i2c_interface_enable(obj);
}
inline int i2c_start(i2c_t *obj) {
int status = 0;
if (repeated_start) {
LPC_I2C0->MSTCTL = (1 << 1) | (1 << 0);
repeated_start = 0;
} else {
LPC_I2C0->MSTCTL = (1 << 1);
}
return status;
}
inline int i2c_stop(i2c_t *obj) {
int timeout = 0;
LPC_I2C0->MSTCTL = (1 << 2) | (1 << 0);
while ((LPC_I2C0->STAT & ((1 << 0) | (7 << 1))) != ((1 << 0) | (0 << 1))) {
timeout ++;
if (timeout > 100000) return 1;
}
return 0;
}
static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
// write the data
LPC_I2C0->MSTDAT = value;
if (!addr)
LPC_I2C0->MSTCTL = (1 << 0);
// wait and return status
i2c_wait_SI(obj);
return i2c_status(obj);
}
static inline int i2c_do_read(i2c_t *obj, int last) {
// wait for it to arrive
i2c_wait_SI(obj);
if (!last)
LPC_I2C0->MSTCTL = (1 << 0);
// return the data
//return (I2C_DAT(obj) & 0xFF);
return (LPC_I2C0->MSTDAT & 0xFF);
}
void i2c_frequency(i2c_t *obj, int hz) {
// No peripheral clock divider on the M0
uint32_t PCLK = SystemCoreClock;
uint32_t clkdiv = PCLK / (hz * 4) - 1;
LPC_I2C0->DIV = clkdiv;
LPC_I2C0->MSTTIME = 0;
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
int count, status;
int timeout = 0;
i2c_start(obj);
//status = i2c_do_write(obj, (address | 0x01), 1);
LPC_I2C0->MSTDAT = (address | 0x01);
LPC_I2C0->MSTCTL |= 0x20;
while (!(LPC_I2C0->STAT & (1 << 0))) {
timeout++;
if (timeout > 100000) return -1;
}
status = ((LPC_I2C0->STAT >> 1) & (0x07));
if (status != 0x01) {
i2c_stop(obj);
return I2C_ERROR_NO_SLAVE;
}
// Read in all except last byte
for (count = 0; count < (length - 1); count++) {
//int value = i2c_do_read(obj, 0);
while (!(LPC_I2C0->STAT & (1 << 0))) {
timeout++;
if (timeout > 100000) return -1;
}
if (!0)
LPC_I2C0->MSTCTL = (1 << 0);
data[count] = (LPC_I2C0->MSTDAT & 0xFF);
//
status = ((LPC_I2C0->STAT >> 1) & (0x07));
if (status != 0x00) {
i2c_stop(obj);
return count;
}
//data[count] = (char) value;
}
// read in last byte
//int value = i2c_do_read(obj, 1);
while (!(LPC_I2C0->STAT & (1 << 0))) {
timeout++;
if (timeout > 100000) return -1;
}
data[count] = (LPC_I2C0->MSTDAT & 0xFF);
//
status = i2c_status(obj);
if (status != 0x01) {
i2c_stop(obj);
return length - 1;
}
//data[count] = (char) value;
// If not repeated start, send stop.
if (stop) {
i2c_stop(obj);
} else {
repeated_start = 1;
}
return length;
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
int i, status;
int timeout = 0;
i2c_start(obj);
//status = i2c_do_write(obj, (address & 0xFE), 1);
LPC_I2C0->MSTDAT = (address & 0xFE);
LPC_I2C0->MSTCTL |= 0x20;
// wait and return status
while (!(LPC_I2C0->STAT & (1 << 0))) {
timeout++;
if (timeout > 100000) return -1;
}
status = ((LPC_I2C0->STAT >> 1) & (0x07));
if (status != 0x02) {
i2c_stop(obj);
return I2C_ERROR_NO_SLAVE;
}
for (i=0; i<length; i++) {
//status = i2c_do_write(obj, data[i], 0);
LPC_I2C0->MSTDAT = data[i];
LPC_I2C0->MSTCTL = (1 << 0);
// wait and return status
while (!(LPC_I2C0->STAT & (1 << 0))) {
timeout++;
if (timeout > 100000) return -1;
}
status = ((LPC_I2C0->STAT >> 1) & (0x07));
if (status != 0x02) {
i2c_stop(obj);
return i;
}
}
// If not repeated start, send stop.
if (stop) {
i2c_stop(obj);
} else {
repeated_start = 1;
}
return length;
}
void i2c_reset(i2c_t *obj) {
i2c_stop(obj);
}
int i2c_byte_read(i2c_t *obj, int last) {
return (i2c_do_read(obj, last) & 0xFF);
}
int i2c_byte_write(i2c_t *obj, int data) {
int ack;
int status = i2c_do_write(obj, (data & 0xFF), 0);
switch(status) {
case 2:
ack = 1;
break;
default:
ack = 0;
break;
}
return ack;
}

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/objects.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
struct gpio_irq_s {
uint32_t ch;
};
struct serial_s {
LPC_USART0_Type *uart;
unsigned char index;
};
struct analogin_s {
ADCName adc;
};
struct i2c_s {
LPC_I2C0_Type *i2c;
};
struct spi_s {
LPC_SPI0_Type *spi;
unsigned char spi_n;
};
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/pinmap.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "pinmap.h"
#include "error.h"
void pin_function(PinName pin, int function) {
}
void pin_mode(PinName pin, PinMode mode) {
if (pin == (uint32_t)NC) { return; }
if ((pin == P0_22) || (pin == P0_23)) {
// The true open-drain pins PIO0_22 and PIO0_23 can be configured for different I2C-bus speeds.
return;
}
__IO uint32_t *reg = (__IO uint32_t*)(LPC_IOCON_BASE + (pin * 4));
if (mode == OpenDrain) {
*reg |= (1 << 10);
} else {
uint32_t tmp = *reg;
tmp &= ~(0x3 << 3);
tmp |= (mode & 0x3) << 3;
*reg = tmp;
}
}

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// math.h required for floating point operations for baud rate calculation
#include <math.h>
#include <string.h>
#include "serial_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
/******************************************************************************
* INITIALIZATION
******************************************************************************/
#define UART_NUM 3
static const SWM_Map SWM_UART_TX[] = {
{0, 0}, // Pin assign register0, 7:0bit
{1, 8}, // Pin assign register1, 15:8bit
{2, 16}, // Pin assign register2, 23:16bit
};
static const SWM_Map SWM_UART_RX[] = {
{0, 8},
{1, 16},
{2, 24},
};
static const SWM_Map SWM_UART_RTS[] = {
{0, 16},
{1, 24},
{3, 0},
};
static const SWM_Map SWM_UART_CTS[] = {
{0, 24},
{2, 0},
{3, 8}
};
// bit flags for used UARTs
static unsigned char uart_used = 0;
static int get_available_uart(void) {
int i;
for (i=0; i<3; i++) {
if ((uart_used & (1 << i)) == 0)
return i;
}
return -1;
}
#define UART_EN (0x01<<0)
#define CTS_DELTA (0x01<<5)
#define RXBRK (0x01<<10)
#define DELTA_RXBRK (0x01<<11)
#define RXRDY (0x01<<0)
#define TXRDY (0x01<<2)
#define TXBRKEN (0x01<<1)
#define CTSEN (0x01<<9)
static uint32_t UARTSysClk;
static uint32_t serial_irq_ids[UART_NUM] = {0};
static uart_irq_handler irq_handler;
int stdio_uart_inited = 0;
serial_t stdio_uart;
void serial_init(serial_t *obj, PinName tx, PinName rx) {
int is_stdio_uart = 0;
int uart_n = get_available_uart();
if (uart_n == -1) {
error("No available UART");
}
obj->index = uart_n;
obj->uart = (LPC_USART0_Type *)(LPC_USART0_BASE + (0x4000 * uart_n));
uart_used |= (1 << uart_n);
const SWM_Map *swm;
uint32_t regVal;
swm = &SWM_UART_TX[uart_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
LPC_SWM->PINASSIGN[swm->n] = regVal | (tx << swm->offset);
swm = &SWM_UART_RX[uart_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
LPC_SWM->PINASSIGN[swm->n] = regVal | (rx << swm->offset);
/* uart clock divided by 6 */
LPC_SYSCON->UARTCLKDIV =6;
/* disable uart interrupts */
NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
/* Enable UART clock */
LPC_SYSCON->SYSAHBCLKCTRL1 |= (1 << (17 + uart_n));
/* Peripheral reset control to UART, a "1" bring it out of reset. */
// LPC_SYSCON->PRESETCTRL1 &= ~(0x1 << (17 + uart_n));
LPC_SYSCON->PRESETCTRL1 |= (0x1 << (17 + uart_n));
LPC_SYSCON->PRESETCTRL1 ^= (0x1 << (17 + uart_n));
UARTSysClk = SystemCoreClock / LPC_SYSCON->UARTCLKDIV;
// set default baud rate and format
serial_baud (obj, 9600);
serial_format(obj, 8, ParityNone, 1);
/* Clear all status bits. */
obj->uart->STAT = CTS_DELTA | DELTA_RXBRK;
/* enable uart interrupts */
NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
/* Enable UART interrupt */
// obj->uart->INTENSET = RXRDY | TXRDY | DELTA_RXBRK;
/* Enable UART */
obj->uart->CFG |= UART_EN;
is_stdio_uart = ((tx == USBTX) && (rx == USBRX));
if (is_stdio_uart) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj) {
uart_used &= ~(1 << obj->index);
serial_irq_ids[obj->index] = 0;
}
// serial_baud
// set the baud rate, taking in to account the current SystemFrequency
void serial_baud(serial_t *obj, int baudrate) {
/* Integer divider:
BRG = UARTSysClk/(Baudrate * 16) - 1
Frational divider:
FRG = ((UARTSysClk / (Baudrate * 16 * (BRG + 1))) - 1)
where
FRG = (LPC_SYSCON->UARTFRDADD + 1) / (LPC_SYSCON->UARTFRDSUB + 1)
(1) The easiest way is set SUB value to 256, -1 encoded, thus SUB
register is 0xFF.
(2) In ADD register value, depending on the value of UartSysClk,
baudrate, BRG register value, and SUB register value, be careful
about the order of multiplier and divider and make sure any
multiplier doesn't exceed 32-bit boundary and any divider doesn't get
down below one(integer 0).
(3) ADD should be always less than SUB.
*/
obj->uart->BRG = UARTSysClk / 16 / baudrate - 1;
// To use of the fractional baud rate generator, you must write 0xFF to the DIV
// value to yield a denominator value of 256. All other values are not supported.
LPC_SYSCON->FRGCTRL = 0xFF;
LPC_SYSCON->FRGCTRL |= ( ( ((UARTSysClk / 16) * (0xFF + 1)) /
(baudrate * (obj->uart->BRG + 1))
) - (0xFF + 1) ) << 8;
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
// 0: 1 stop bits, 1: 2 stop bits
if (stop_bits != 1 && stop_bits != 2) {
error("Invalid stop bits specified");
}
stop_bits -= 1;
// 0: 7 data bits ... 2: 9 data bits
if (data_bits < 7 || data_bits > 9) {
error("Invalid number of bits (%d) in serial format, should be 7..9", data_bits);
}
data_bits -= 7;
int paritysel;
switch (parity) {
case ParityNone: paritysel = 0; break;
case ParityEven: paritysel = 2; break;
case ParityOdd : paritysel = 3; break;
default:
error("Invalid serial parity setting");
return;
}
obj->uart->CFG = (data_bits << 2)
| (paritysel << 4)
| (stop_bits << 6);
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
static inline void uart_irq(uint32_t iir, uint32_t index) {
// [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
SerialIrq irq_type;
switch (iir) {
case 1: irq_type = TxIrq; break;
case 2: irq_type = RxIrq; break;
default: return;
}
if (serial_irq_ids[index] != 0)
irq_handler(serial_irq_ids[index], irq_type);
}
void uart0_irq() {uart_irq((LPC_USART0->STAT & (1 << 2)) ? 2 : 1, 0);}
void uart1_irq() {uart_irq((LPC_USART1->STAT & (1 << 2)) ? 2 : 1, 1);}
void uart2_irq() {uart_irq((LPC_USART2->STAT & (1 << 2)) ? 2 : 1, 2);}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
switch ((int)obj->uart) {
case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
}
if (enable) {
obj->uart->INTENSET = (1 << ((irq == RxIrq) ? 0 : 2));
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
} else { // disable
int all_disabled = 0;
SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
obj->uart->INTENSET &= ~(1 << ((irq == RxIrq) ? 0 : 2));
all_disabled = (obj->uart->INTENSET & (1 << ((other_irq == RxIrq) ? 0 : 2))) == 0;
if (all_disabled)
NVIC_DisableIRQ(irq_n);
}
}
/******************************************************************************
* READ/WRITE
******************************************************************************/
int serial_getc(serial_t *obj) {
while (!serial_readable(obj));
return obj->uart->RXDATA;
}
void serial_putc(serial_t *obj, int c) {
while (!serial_writable(obj));
obj->uart->TXDATA = c;
}
int serial_readable(serial_t *obj) {
return obj->uart->STAT & RXRDY;
}
int serial_writable(serial_t *obj) {
return obj->uart->STAT & TXRDY;
}
void serial_clear(serial_t *obj) {
// [TODO]
}
void serial_pinout_tx(PinName tx) {
}
void serial_break_set(serial_t *obj) {
obj->uart->CTRL |= TXBRKEN;
}
void serial_break_clear(serial_t *obj) {
obj->uart->CTRL &= ~TXBRKEN;
}
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
const SWM_Map *swm_rts, *swm_cts;
uint32_t regVal_rts, regVal_cts;
swm_rts = &SWM_UART_RTS[obj->index];
swm_cts = &SWM_UART_CTS[obj->index];
regVal_rts = LPC_SWM->PINASSIGN[swm_rts->n] & ~(0xFF << swm_rts->offset);
regVal_cts = LPC_SWM->PINASSIGN[swm_cts->n] & ~(0xFF << swm_cts->offset);
if (FlowControlNone == type) {
LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
obj->uart->CFG &= ~CTSEN;
return;
}
if ((FlowControlRTS == type || FlowControlRTSCTS == type) && (rxflow != NC)) {
LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (rxflow << swm_rts->offset);
if (FlowControlRTS == type) {
LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
obj->uart->CFG &= ~CTSEN;
}
}
if ((FlowControlCTS == type || FlowControlRTSCTS == type) && (txflow != NC)) {
LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (txflow << swm_cts->offset);
obj->uart->CFG |= CTSEN;
if (FlowControlCTS == type) {
LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
}
}
}

215
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/spi_api.c Normal file
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@ -0,0 +1,215 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <math.h>
#include "spi_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
static const SWM_Map SWM_SPI_SSEL[] = {
{4, 0},
{5, 24},
};
static const SWM_Map SWM_SPI_SCLK[] = {
{3, 8},
{5, 0},
};
static const SWM_Map SWM_SPI_MOSI[] = {
{3, 16},
{5, 8},
};
static const SWM_Map SWM_SPI_MISO[] = {
{3, 24},
{5, 16},
};
// bit flags for used SPIs
static unsigned char spi_used = 0;
static int get_available_spi(void) {
int i;
for (i=0; i<2; i++) {
if ((spi_used & (1 << i)) == 0)
return i;
}
return -1;
}
static inline void spi_disable(spi_t *obj);
static inline void spi_enable(spi_t *obj);
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
int spi_n = get_available_spi();
if (spi_n == -1) {
error("No available SPI");
}
obj->spi_n = spi_n;
spi_used |= (1 << spi_n);
obj->spi = (spi_n) ? (LPC_SPI0_Type *)(LPC_SPI1_BASE) : (LPC_SPI0_Type *)(LPC_SPI0_BASE);
const SWM_Map *swm;
uint32_t regVal;
if (sclk != NC) {
swm = &SWM_SPI_SCLK[obj->spi_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
LPC_SWM->PINASSIGN[swm->n] = regVal | (sclk << swm->offset);
}
if (mosi != NC) {
swm = &SWM_SPI_MOSI[obj->spi_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
LPC_SWM->PINASSIGN[swm->n] = regVal | (mosi << swm->offset);
}
if (miso != NC) {
swm = &SWM_SPI_MISO[obj->spi_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
LPC_SWM->PINASSIGN[swm->n] = regVal | (miso << swm->offset);
}
if (ssel != NC) {
swm = &SWM_SPI_SSEL[obj->spi_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
LPC_SWM->PINASSIGN[swm->n] = regVal | (ssel << swm->offset);
}
// clear interrupts
obj->spi->INTENCLR = 0x3f;
// enable power and clocking
switch (obj->spi_n) {
case 0:
LPC_SYSCON->SYSAHBCLKCTRL1 |= (0x1<<9);
LPC_SYSCON->PRESETCTRL1 |= (0x1<<9);
LPC_SYSCON->PRESETCTRL1 &= ~(0x1<<9);
break;
case 1:
LPC_SYSCON->SYSAHBCLKCTRL1 |= (0x1<<10);
LPC_SYSCON->PRESETCTRL1 |= (0x1<<10);
LPC_SYSCON->PRESETCTRL1 &= ~(0x1<<10);
break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable the spi channel
spi_enable(obj);
}
void spi_free(spi_t *obj) {}
void spi_format(spi_t *obj, int bits, int mode, int slave) {
spi_disable(obj);
if (!(bits >= 1 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
error("SPI format error");
}
int polarity = (mode & 0x2) ? 1 : 0;
int phase = (mode & 0x1) ? 1 : 0;
// set it up
int LEN = bits - 1; // LEN - Data Length
int CPOL = (polarity) ? 1 : 0; // CPOL - Clock Polarity select
int CPHA = (phase) ? 1 : 0; // CPHA - Clock Phase select
uint32_t tmp = obj->spi->CFG;
tmp &= ~((1 << 5) | (1 << 4) | (1 << 2));
tmp |= (CPOL << 5) | (CPHA << 4) | ((slave ? 0 : 1) << 2);
obj->spi->CFG = tmp;
// select frame length
tmp = obj->spi->TXDATCTL;
tmp &= ~(0xf << 24);
tmp |= (LEN << 24);
obj->spi->TXDATCTL = tmp;
spi_enable(obj);
}
void spi_frequency(spi_t *obj, int hz) {
spi_disable(obj);
uint32_t PCLK = SystemCoreClock;
obj->spi->DIV = PCLK/hz - 1;
obj->spi->DLY = 0;
spi_enable(obj);
}
static inline void spi_disable(spi_t *obj) {
obj->spi->CFG &= ~(1 << 0);
}
static inline void spi_enable(spi_t *obj) {
obj->spi->CFG |= (1 << 0);
}
static inline int spi_readable(spi_t *obj) {
return obj->spi->STAT & (1 << 0);
}
static inline int spi_writeable(spi_t *obj) {
return obj->spi->STAT & (1 << 1);
}
static inline void spi_write(spi_t *obj, int value) {
while (!spi_writeable(obj));
// end of transfer
obj->spi->TXDATCTL |= (1 << 20);
obj->spi->TXDAT = value;
}
static inline int spi_read(spi_t *obj) {
while (!spi_readable(obj));
return obj->spi->RXDAT;
}
static inline int spi_busy(spi_t *obj) {
// checking RXOV(Receiver Overrun interrupt flag)
return obj->spi->STAT & (1 << 2);
}
int spi_master_write(spi_t *obj, int value) {
spi_write(obj, value);
return spi_read(obj);
}
int spi_slave_receive(spi_t *obj) {
return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
}
int spi_slave_read(spi_t *obj) {
return obj->spi->RXDAT;
}
void spi_slave_write(spi_t *obj, int value) {
while (spi_writeable(obj) == 0) ;
obj->spi->TXDAT = value;
}

94
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/us_ticker.c Normal file
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@ -0,0 +1,94 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "us_ticker_api.h"
#include "PeripheralNames.h"
#define US_TICKER_TIMER_IRQn SCT0_IRQn
int us_ticker_inited = 0;
void us_ticker_init(void) {
if (us_ticker_inited) return;
us_ticker_inited = 1;
// Enable the SCT0 clock
LPC_SYSCON->SYSAHBCLKCTRL1 |= (1 << 2);
// Clear peripheral reset the SCT0:
LPC_SYSCON->PRESETCTRL1 |= (1 << 2);
LPC_SYSCON->PRESETCTRL1 &= ~(1 << 2);
// Unified counter (32 bits)
LPC_SCT0->CONFIG |= 1;
// halt and clear the counter
LPC_SCT0->CTRL |= (1 << 2) | (1 << 3);
// System Clock (12)MHz -> us_ticker (1)MHz
LPC_SCT0->CTRL |= ((SystemCoreClock/1000000 - 1) << 5);
// unhalt the counter:
// - clearing bit 2 of the CTRL register
LPC_SCT0->CTRL &= ~(1 << 2);
NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
}
uint32_t us_ticker_read() {
if (!us_ticker_inited)
us_ticker_init();
return LPC_SCT0->COUNT;
}
void us_ticker_set_interrupt(unsigned int timestamp) {
// halt the counter:
// - setting bit 2 of the CTRL register
LPC_SCT0->CTRL |= (1 << 2);
// set timestamp in compare register
LPC_SCT0->MATCH0 = timestamp;
// unhalt the counter:
// - clearing bit 2 of the CTRL register
LPC_SCT0->CTRL &= ~(1 << 2);
// if events are not enabled, enable them
if (!(LPC_SCT0->EVEN & 0x01)) {
// comb mode = match only
LPC_SCT0->EV0_CTRL = (1 << 12);
// ref manual:
// In simple applications that do not
// use states, write 0x01 to this
// register to enable an event
LPC_SCT0->EV0_STATE |= 0x1;
// enable events
LPC_SCT0->EVEN |= 0x1;
}
}
void us_ticker_disable_interrupt(void) {
LPC_SCT0->EVEN &= ~1;
}
void us_ticker_clear_interrupt(void) {
LPC_SCT0->EVFLAG = 1;
}

1
workspace_tools/build_release.py
View File

@ -35,6 +35,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = (
('LPC4088', ('ARM', 'GCC_ARM', 'GCC_CR')),
('LPC1114', ('uARM',)),
('LPC11U35_401', ('ARM', 'uARM')),
('LPC1549', ('uARM',)),
('KL05Z', ('ARM', 'uARM', 'GCC_ARM')),
('KL25Z', ('ARM', 'GCC_ARM')),

4
workspace_tools/export/uvision4.py
View File

@ -21,9 +21,9 @@ from os.path import basename
class Uvision4(Exporter):
NAME = 'uVision4'
TARGETS = ['LPC1768', 'LPC11U24', 'KL05Z', 'KL25Z', 'KL46Z', 'K20D5M', 'LPC1347', 'LPC1114', 'LPC11C24', 'LPC4088', 'LPC812', 'NUCLEO_F103RB', 'NUCLEO_L152RE', 'NUCLEO_F030R8', 'NUCLEO_F401RE', 'UBLOX_C027']
TARGETS = ['LPC1768', 'LPC11U24', 'KL05Z', 'KL25Z', 'KL46Z', 'K20D5M', 'LPC1347', 'LPC1114', 'LPC11C24', 'LPC4088', 'LPC812', 'NUCLEO_F103RB', 'NUCLEO_L152RE', 'NUCLEO_F030R8', 'NUCLEO_F401RE', 'UBLOX_C027', 'LPC1549']
USING_MICROLIB = ['LPC11U24', 'LPC1114', 'LPC11C24', 'LPC812', 'NUCLEO_F103RB', 'NUCLEO_L152RE', 'NUCLEO_F030R8', 'NUCLEO_F401RE']
USING_MICROLIB = ['LPC11U24', 'LPC1114', 'LPC11C24', 'LPC812', 'NUCLEO_F103RB', 'NUCLEO_L152RE', 'NUCLEO_F030R8', 'NUCLEO_F401RE', 'LPC1549']
FILE_TYPES = {
'c_sources':'1',

2
workspace_tools/export/uvision4_lpc1114.uvproj.tmpl
View File

@ -73,7 +73,7 @@
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --bin -o build\{{name}}_LPC1114.bin build\{{name}}.axf</UserProg1Name>
<UserProg2Name></UserProg2Name>

223
workspace_tools/export/uvision4_lpc1549.uvopt.tmpl Normal file
View File

@ -0,0 +1,223 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>mbed NXP LPC1549</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>1</RunSim>
<RunTarget>0</RunTarget>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\build\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>8</CpuCode>
<Books>
<Book>
<Number>0</Number>
<Title>Data Sheet</Title>
<Path>DATASHTS\NXP\LPC15xx\NotYetAvailable.pdf</Path>
</Book>
<Book>
<Number>1</Number>
<Title>User Manual</Title>
<Path>DATASHTS\NXP\LPC15xx\NotYetAvailable.pdf</Path>
</Book>
<Book>
<Number>2</Number>
<Title>Generic User Guide</Title>
<Path>datashts\arm\cortex_m0p\r0p0\DUI0662A_CORTEX_M0P_R0P0_DGUG.PDF</Path>
</Book>
</Books>
<DllOpt>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments></SimDllArguments>
<SimDlgDllName>DCM.DLL</SimDlgDllName>
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDllName>TCM.DLL</TargetDlgDllName>
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
</DllOpt>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>0</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<nTsel>14</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\CMSIS_AGDI.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>CMSIS_AGDI</Key>
<Name>-X"MBED CMSIS-DAP" -U154902001A4E0E21E7B1E490 -O4303 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -FO15 -FD2000000 -FC800 -FN1 -FF0LPC15xx_256 -FS00 -FL040000</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=90,120,456,345,0)(1009=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>-UM0869MEE -O4303 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD2000000 -FC800 -FN1 -FF0LPC15xx_256 -FS00 -FL040000</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
</TargetOption>
</Target>
<Group>
<GroupName>src</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>8</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>1</TopLine>
<CurrentLine>7</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>main.cpp</PathWithFileName>
<FilenameWithoutPath>main.cpp</FilenameWithoutPath>
</File>
</Group>
</ProjectOpt>

431
workspace_tools/export/uvision4_lpc1549.uvproj.tmpl Normal file
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@ -0,0 +1,431 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
<SchemaVersion>1.1</SchemaVersion>
<Header>###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision </Header>
<Targets>
<Target>
<TargetName>mbed NXP LPC1549</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<TargetCommonOption>
<Device>LPC1549</Device>
<Vendor>NXP (founded by Philips)</Vendor>
<Cpu>IRAM(0x02000000-0x02008FFF) IROM(0x0-0x3FFFF) CLOCK(12000000) CPUTYPE("Cortex-M3")</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile>"STARTUP\NXP\LPC15xx\startup_LPC15xx.s" ("NXP LPC15xx Startup Code")</StartupFile>
<FlashDriverDll>UL2CM3(-O4303 -S0 -C0 -FO7 -FD2000000 -FC800 -FN1 -FF0LPC15xx_256 -FS00 -FL040000)</FlashDriverDll>
<DeviceId>7281</DeviceId>
<RegisterFile>LPC15xx.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>SFD\NXP\LPC15xx\LPC15xx.SFR</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath>NXP\LPC15xx\</RegisterFilePath>
<DBRegisterFilePath>NXP\LPC15xx\</DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\</OutputDirectory>
<OutputName>{{name}}</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\build\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --bin -o build\{{name}}_LPC1549.bin build\{{name}}.axf</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments></SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>0</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<RestoreTracepoints>1</RestoreTracepoints>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>14</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
<Driver>BIN\CMSIS_AGDI.dll</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M3"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x2000000</StartAddress>
<Size>0x9000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x2000000</StartAddress>
<Size>0x9000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>3</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>0</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<VariousControls>
<MiscControls></MiscControls>
<Define>{% for s in symbols %} {{s}}, {% endfor %}</Define>
<Undefine></Undefine>
<IncludePath> {% for path in include_paths %} {{path}}; {% endfor %} </IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<ScatterFile>{{scatter_file}}</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc>
{% for file in object_files %}
{{file}}
{% endfor %}
</Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
{% for group,files in source_files %}
<Group>
<GroupName>{{group}}</GroupName>
<Files>
{% for file in files %}
<File>
<FileName>{{file.name}}</FileName>
<FileType>{{file.type}}</FileType>
<FilePath>{{file.path}}</FilePath>
{%if file.type == "1" %}
<FileOption>
<FileArmAds>
<Cads>
<VariousControls>
<MiscControls>--c99</MiscControls>
</VariousControls>
</Cads>
</FileArmAds>
</FileOption>
{% endif %}
</File>
{% endfor %}
</Files>
</Group>
{% endfor %}
</Groups>
</Target>
</Targets>
</Project>

12
workspace_tools/targets.py
View File

@ -434,6 +434,15 @@ class NRF51822(Target):
with open(binf, "wb") as f:
sdh.tofile(f, format = 'bin')
class LPC1549(Target):
def __init__(self):
Target.__init__(self)
self.core = "Cortex-M3"
self.extra_labels = ['NXP', 'LPC15XX']
self.supported_toolchains = ["uARM"]
# Get a single instance for each target
TARGETS = [
@ -459,7 +468,8 @@ TARGETS = [
LPC11C24(),
LPC11U35_401(),
NRF51822(),
UBLOX_C027()
UBLOX_C027(),
LPC1549()
]
# Map each target name to its unique instance