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Merge pull request #3767 from OpenNuvoton/nuvoton 

[NUC472] Support no-XRAM configuration
pull/3732/merge
Sam Grove 2017-02-21 10:49:13 -06:00 committed by GitHub
parent 094fab43e7 0bd8fb22c4
commit 1ee18b4ecb
10 changed files with 366 additions and 4 deletions
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0
targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/NUC472.sct → targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_SUPPORTED/NUC472.sct
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29
targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct Normal file
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@ -0,0 +1,29 @@
LR_IROM1 0x00000000 {
ER_IROM1 0x00000000 { ; load address = execution address
*(RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
; uvisor-lib.a (+RW +ZI)
;}
ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
}
ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 142)) { ; Reserve for vectors
}
RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
.ANY (+RW +ZI)
}
; Extern SRAM for HEAP
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x10000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
}
ScatterAssert(LoadLimit(LR_IROM1) <= 0x00080000) ; 512 KB APROM
ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000) ; 64 KB SRAM (internal)

0
targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/NUC472.sct → targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_SUPPORTED/NUC472.sct
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29
targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct Normal file
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@ -0,0 +1,29 @@
LR_IROM1 0x00000000 {
ER_IROM1 0x00000000 { ; load address = execution address
*(RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
; uvisor-lib.a (+RW +ZI)
;}
ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
}
ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 142)) { ; Reserve for vectors
}
RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
.ANY (+RW +ZI)
}
; Extern SRAM for HEAP
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x10000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
}
ScatterAssert(LoadLimit(LR_IROM1) <= 0x00080000) ; 512 KB APROM
ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000) ; 64 KB SRAM (internal)

0
targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/NUC472.ld → targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_SUPPORTED/NUC472.ld
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268
targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_UNSUPPORTED/NUC472.ld Normal file
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@ -0,0 +1,268 @@
/*
* Nuvoton NUC472 GCC linker script file
*/
StackSize = 0x800;
MEMORY
{
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00080000 - 0x00000400
RAM_INTERN (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 - 0x00000000
}
/**
* Must match cmsis_nvic.h
*/
__vector_size = 4 * (16 + 142);
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(4);
} > VECTORS
/* ensure that uvisor bss is at the beginning of memory */
.uvisor.bss (NOLOAD):
{
. = ALIGN(32);
__uvisor_bss_start = .;
/* protected uvisor main bss */
. = ALIGN(32);
__uvisor_bss_main_start = .;
KEEP(*(.keep.uvisor.bss.main))
. = ALIGN(32);
__uvisor_bss_main_end = .;
/* protected uvisor secure boxes bss */
. = ALIGN(32);
__uvisor_bss_boxes_start = .;
KEEP(*(.keep.uvisor.bss.boxes))
. = ALIGN(32);
__uvisor_bss_boxes_end = .;
/* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. */
. = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));
__uvisor_bss_end = .;
} > RAM_INTERN
.text :
{
/* uVisor code and data */
. = ALIGN(4);
__uvisor_main_start = .;
*(.uvisor.main)
__uvisor_main_end = .;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > FLASH
/* .stack section doesn't contains any symbols. It is only
* used for linker to reserve space for the main stack section
* WARNING: .stack should come immediately after the last secure memory
* section. This provides stack overflow detection. */
.stack (NOLOAD):
{
__StackLimit = .;
*(.stack*);
. += StackSize - (. - __StackLimit);
} > RAM_INTERN
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ADDR(.stack) + SIZEOF(.stack);
__StackLimit = ADDR(.stack);
PROVIDE(__stack = __StackTop);
/* Relocate vector table in SRAM */
.isr_vector.reloc (NOLOAD) :
{
. = ALIGN(1 << LOG2CEIL(__vector_size));
PROVIDE(__start_vector_table__ = .);
. += __vector_size;
PROVIDE(__end_vector_table__ = .);
} > RAM_INTERN
.data :
{
PROVIDE( __etext = LOADADDR(.data) );
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
/* All data end */
. = ALIGN(32);
__data_end__ = .;
} >RAM_INTERN AT>FLASH
/* uvisor configuration data */
.uvisor.secure :
{
. = ALIGN(32);
__uvisor_secure_start = .;
/* uvisor secure boxes configuration tables */
. = ALIGN(32);
__uvisor_cfgtbl_start = .;
KEEP(*(.keep.uvisor.cfgtbl))
. = ALIGN(32);
__uvisor_cfgtbl_end = .;
/* pointers to uvisor secure boxes configuration tables */
/* note: no further alignment here, we need to have the exact list of pointers */
__uvisor_cfgtbl_ptr_start = .;
KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
KEEP(*(.keep.uvisor.cfgtbl_ptr))
__uvisor_cfgtbl_ptr_end = .;
/* the following symbols are kept for backward compatibility and will be soon
* deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)
* will need to use uVisor 0.8.x or above, or the security assertions will halt the
* system */
/************************/
__uvisor_data_src = .;
__uvisor_data_start = .;
__uvisor_data_end = .;
/************************/
. = ALIGN(32);
__uvisor_secure_end = .;
} >FLASH
.uninitialized (NOLOAD):
{
. = ALIGN(32);
__uninitialized_start = .;
*(.uninitialized)
KEEP(*(.keep.uninitialized))
. = ALIGN(32);
__uninitialized_end = .;
} > RAM_INTERN
.bss.extern (NOLOAD):
{
__bss_extern_start__ = .;
/**
* Place large .bss* sections into external SRAM if internal SRAM is insufficient.
* Such memory arrangement requires initializing .bss.extern section to zero in startup file. Check startup fiile in cmsis-core-* for support or not.
*/
*lwip_*.o(.bss*)
*lwip_*.o(COMMON)
*mesh_system.o(.bss*)
__bss_extern_end__ = .;
} > RAM_INTERN
.bss (NOLOAD):
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM_INTERN
.heap (NOLOAD):
{
__end__ = .;
end = __end__;
*(.heap*);
. += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
__HeapLimit = .;
} > RAM_INTERN
PROVIDE(__heap_size = SIZEOF(.heap));
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
/* Provide physical memory boundaries for uVisor. */
__uvisor_flash_start = ORIGIN(VECTORS);
__uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
__uvisor_sram_start = ORIGIN(RAM_INTERN);
__uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);
}

0
targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/NUC472_442.icf → targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_SUPPORTED/NUC472_442.icf
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targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_UNSUPPORTED/NUC472_442.icf Normal file
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@ -0,0 +1,36 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x00080000;
define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_IRAM_end__ = 0x20010000;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x8000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
define block IRAMVEC with alignment = 1024, size = 4 * (16 + 142) { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place at start of IRAM_region { block CSTACK };
place in IRAM_region { block IRAMVEC };
place in IRAM_region { readwrite };
place in IRAM_region { block HEAP };

6
targets/TARGET_NUVOTON/TARGET_NUC472/device/system_NUC472_442.c
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@ -19,7 +19,7 @@ uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Cor
uint32_t CyclesPerUs = (__HSI / 1000000); /*!< Cycles per micro second */
uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0, __LIRC, 0, 0, 0, __HIRC}; /*!< System clock source table */
#if defined TARGET_NUMAKER_PFM_NUC472
#if defined TARGET_NU_XRAM_SUPPORTED
static void nu_ebi_init(void);
#endif
@ -113,13 +113,13 @@ void SystemInit (void)
/*------------------------------------------------------------------------*/
#endif
#if defined TARGET_NUMAKER_PFM_NUC472
#if defined TARGET_NU_XRAM_SUPPORTED
// NOTE: C-runtime not initialized yet. Ensure no static memory (global variable) are accessed in this function.
nu_ebi_init();
#endif
}
#if defined TARGET_NUMAKER_PFM_NUC472
#if defined TARGET_NU_XRAM_SUPPORTED
void nu_ebi_init(void)
{
/* Enable IP clock */

2
targets/targets.json
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@ -2553,7 +2553,7 @@
"NUMAKER_PFM_NUC472": {
"core": "Cortex-M4F",
"default_toolchain": "ARM",
"extra_labels": ["NUVOTON", "NUC472", "NUMAKER_PFM_NUC472"],
"extra_labels": ["NUVOTON", "NUC472", "NU_XRAM_SUPPORTED"],
"is_disk_virtual": true,
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"inherits": ["Target"],