From 1d0aee9065d4c11e18f7abd1357e8a91ee0bb52d Mon Sep 17 00:00:00 2001 From: dbestm Date: Thu, 31 Mar 2016 17:34:42 +0200 Subject: [PATCH] [XXX_F3XX] enhance rtc api add define to select LSI or LSE, update rtc api accordingly --- .../TARGET_STM32F3/stm32f3xx_hal_rcc.h | 2 +- .../TARGET_DISCO_F303VC/device.h | 1 + .../TARGET_DISCO_F334C8/device.h | 1 + .../TARGET_NUCLEO_F302R8/device.h | 1 + .../TARGET_NUCLEO_F303K8/device.h | 1 + .../TARGET_NUCLEO_F303RE/device.h | 1 + .../TARGET_NUCLEO_F334R8/device.h | 1 + .../hal/TARGET_STM/TARGET_STM32F3/rtc_api.c | 67 ++++++++++++------- 8 files changed, 48 insertions(+), 27 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.h index a872f54825..2b0ac72d33 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.h @@ -164,7 +164,7 @@ typedef struct * @{ */ /* LSE state change timeout */ -#define LSE_TIMEOUT_VALUE ((uint32_t)100) /* 5 s */ +#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ /* Disable Backup domain write protection state change timeout */ #define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device.h index f842633cf8..0ec2fdffa6 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device.h @@ -48,6 +48,7 @@ #define DEVICE_SPISLAVE 1 #define DEVICE_RTC 1 +#define DEVICE_RTC_LSI 1 #define DEVICE_PWMOUT 1 diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device.h index f842633cf8..0ec2fdffa6 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device.h @@ -48,6 +48,7 @@ #define DEVICE_SPISLAVE 1 #define DEVICE_RTC 1 +#define DEVICE_RTC_LSI 1 #define DEVICE_PWMOUT 1 diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device.h index f842633cf8..8b1f3d7ca2 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device.h @@ -48,6 +48,7 @@ #define DEVICE_SPISLAVE 1 #define DEVICE_RTC 1 +#define DEVICE_RTC_LSI 0 #define DEVICE_PWMOUT 1 diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device.h index f842633cf8..8b1f3d7ca2 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device.h @@ -48,6 +48,7 @@ #define DEVICE_SPISLAVE 1 #define DEVICE_RTC 1 +#define DEVICE_RTC_LSI 0 #define DEVICE_PWMOUT 1 diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device.h index f842633cf8..8b1f3d7ca2 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device.h @@ -48,6 +48,7 @@ #define DEVICE_SPISLAVE 1 #define DEVICE_RTC 1 +#define DEVICE_RTC_LSI 0 #define DEVICE_PWMOUT 1 diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device.h index f842633cf8..8b1f3d7ca2 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device.h @@ -48,6 +48,7 @@ #define DEVICE_SPISLAVE 1 #define DEVICE_RTC 1 +#define DEVICE_RTC_LSI 0 #define DEVICE_PWMOUT 1 diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/rtc_api.c index a848fd517c..838eb4083c 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/rtc_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/rtc_api.c @@ -33,7 +33,9 @@ #include "mbed_error.h" +#if DEVICE_RTC_LSI static int rtc_inited = 0; +#endif static RTC_HandleTypeDef RtcHandle; @@ -42,21 +44,13 @@ void rtc_init(void) RCC_OscInitTypeDef RCC_OscInitStruct; uint32_t rtc_freq = 0; - if (rtc_inited) return; +#if DEVICE_RTC_LSI rtc_inited = 1; +#endif RtcHandle.Instance = RTC; - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - +#if !DEVICE_RTC_LSI // Enable LSE Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; /* Mandatory, otherwise the PLL is reconfigured! */ @@ -65,23 +59,35 @@ void rtc_init(void) // Connect LSE to RTC __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); rtc_freq = LSE_VALUE; - } else { - // Enable LSI clock - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - error("RTC error: LSI clock initialization failed."); - } - // Connect LSI to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); - // Note: The LSI clock can be measured precisely using a timer input capture. - rtc_freq = LSI_VALUE; } + else { + error("RTC error: LSE clock initialization failed."); + } +#else + // Enable Power clock + __PWR_CLK_ENABLE(); + + // Enable access to Backup domain + HAL_PWR_EnableBkUpAccess(); + + // Reset Backup domain + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + + // Enable LSI clock + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! + RCC_OscInitStruct.LSEState = RCC_LSE_OFF; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + error("RTC error: LSI clock initialization failed."); + } + // Connect LSI to RTC + __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); + // Note: The LSI clock can be measured precisely using a timer input capture. + rtc_freq = LSI_VALUE; +#endif - // Check if RTC is already initialized - if ((RTC->ISR & RTC_ISR_INITS) == RTC_ISR_INITS) return; // Enable RTC __HAL_RCC_RTC_ENABLE(); @@ -100,6 +106,7 @@ void rtc_init(void) void rtc_free(void) { +#if DEVICE_RTC_LSI // Enable Power clock __PWR_CLK_ENABLE(); @@ -112,6 +119,7 @@ void rtc_free(void) // Disable access to Backup domain HAL_PWR_DisableBkUpAccess(); +#endif // Disable LSI and LSE clocks RCC_OscInitTypeDef RCC_OscInitStruct; @@ -121,12 +129,19 @@ void rtc_free(void) RCC_OscInitStruct.LSEState = RCC_LSE_OFF; HAL_RCC_OscConfig(&RCC_OscInitStruct); +#if DEVICE_RTC_LSI rtc_inited = 0; +#endif } int rtc_isenabled(void) { +#if DEVICE_RTC_LSI return rtc_inited; +#else + if ((RTC->ISR & RTC_ISR_INITS) == RTC_ISR_INITS) return 1; + else return 0; +#endif } /*