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nRF52 - switch irq priorities of driver handlers to level (APP_IRQ_PRIORITY_LOWEST) 7. 

This is fix for bad settings inherited from nRF5 SDK. It might caused eroneus behavior when nrf_drv API were called form irq context etc.
pull/2969/head
Andrzej Puzdrowski 2016-10-10 14:00:29 +02:00
parent 8f492a20a7
commit 1ca0918996
10 changed files with 69 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/analogin_api.c
View File

@ -35,7 +35,7 @@ static const nrf_drv_saadc_config_t saadc_config =
{ {
.resolution = NRF_SAADC_RESOLUTION_12BIT, .resolution = NRF_SAADC_RESOLUTION_12BIT,
.oversample = NRF_SAADC_OVERSAMPLE_DISABLED, .oversample = NRF_SAADC_OVERSAMPLE_DISABLED,
.interrupt_priority = APP_IRQ_PRIORITY_LOW .interrupt_priority = SAADC_CONFIG_IRQ_PRIORITY
}; };
void analogin_init(analogin_t *obj, PinName pin) void analogin_init(analogin_t *obj, PinName pin)

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/pwmout_api.c
View File

@ -346,7 +346,7 @@ static void internal_pwmout_exe(pwmout_t *obj, bool new_period, bool initializat
NRF_DRV_PWM_PIN_NOT_USED, // channel 2 NRF_DRV_PWM_PIN_NOT_USED, // channel 2
NRF_DRV_PWM_PIN_NOT_USED, // channel 3 NRF_DRV_PWM_PIN_NOT_USED, // channel 3
}, },
.irq_priority = APP_IRQ_PRIORITY_LOW, .irq_priority = PWM0_CONFIG_IRQ_PRIORITY,
.base_clock = pulsewidth_set.pwm_clk, .base_clock = pulsewidth_set.pwm_clk,
.count_mode = NRF_PWM_MODE_UP, .count_mode = NRF_PWM_MODE_UP,
.top_value = pulsewidth_set.period_hwu, .top_value = pulsewidth_set.period_hwu,

60
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/nrf_drv_config.h
View File

@ -59,7 +59,7 @@
#if (CLOCK_ENABLED == 1) #if (CLOCK_ENABLED == 1)
#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default #define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default
#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal #define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal
#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#endif #endif
/* GPIOTE */ /* GPIOTE */
@ -67,7 +67,7 @@
#if (GPIOTE_ENABLED == 1) #if (GPIOTE_ENABLED == 1)
#define GPIOTE_CONFIG_USE_SWI_EGU false #define GPIOTE_CONFIG_USE_SWI_EGU false
#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 8 #define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 8
#endif #endif
@ -82,7 +82,7 @@
#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz #define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer #define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer
#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit #define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define TIMER0_INSTANCE_INDEX 0 #define TIMER0_INSTANCE_INDEX 0
#endif #endif
@ -93,7 +93,7 @@
#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz #define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer #define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer
#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit #define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED) #define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED)
#endif #endif
@ -104,7 +104,7 @@
#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz #define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer #define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer
#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit #define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED) #define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED)
#endif #endif
@ -115,7 +115,7 @@
#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz #define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer #define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer
#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit #define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) #define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
#endif #endif
@ -126,7 +126,7 @@
#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz #define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer #define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer
#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit #define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) #define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
#endif #endif
@ -139,7 +139,7 @@
#if (RTC0_ENABLED == 1) #if (RTC0_ENABLED == 1)
#define RTC0_CONFIG_FREQUENCY 32678 #define RTC0_CONFIG_FREQUENCY 32678
#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define RTC0_CONFIG_RELIABLE false #define RTC0_CONFIG_RELIABLE false
#define RTC0_INSTANCE_INDEX 0 #define RTC0_INSTANCE_INDEX 0
@ -149,7 +149,7 @@
#if (RTC1_ENABLED == 1) #if (RTC1_ENABLED == 1)
#define RTC1_CONFIG_FREQUENCY 32768 #define RTC1_CONFIG_FREQUENCY 32768
#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define RTC1_CONFIG_RELIABLE false #define RTC1_CONFIG_RELIABLE false
#define RTC1_INSTANCE_INDEX (RTC0_ENABLED) #define RTC1_INSTANCE_INDEX (RTC0_ENABLED)
@ -159,7 +159,7 @@
#if (RTC2_ENABLED == 1) #if (RTC2_ENABLED == 1)
#define RTC2_CONFIG_FREQUENCY 32768 #define RTC2_CONFIG_FREQUENCY 32768
#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define RTC2_CONFIG_RELIABLE false #define RTC2_CONFIG_RELIABLE false
#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED) #define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED)
@ -176,7 +176,7 @@
#if (RNG_ENABLED == 1) #if (RNG_ENABLED == 1)
#define RNG_CONFIG_ERROR_CORRECTION true #define RNG_CONFIG_ERROR_CORRECTION true
#define RNG_CONFIG_POOL_SIZE 8 #define RNG_CONFIG_POOL_SIZE 8
#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#endif #endif
/* PWM */ /* PWM */
@ -188,7 +188,7 @@
#define PWM0_CONFIG_OUT1_PIN 3 #define PWM0_CONFIG_OUT1_PIN 3
#define PWM0_CONFIG_OUT2_PIN 4 #define PWM0_CONFIG_OUT2_PIN 4
#define PWM0_CONFIG_OUT3_PIN 5 #define PWM0_CONFIG_OUT3_PIN 5
#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz #define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP #define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
#define PWM0_CONFIG_TOP_VALUE 1000 #define PWM0_CONFIG_TOP_VALUE 1000
@ -205,7 +205,7 @@
#define PWM1_CONFIG_OUT1_PIN 3 #define PWM1_CONFIG_OUT1_PIN 3
#define PWM1_CONFIG_OUT2_PIN 4 #define PWM1_CONFIG_OUT2_PIN 4
#define PWM1_CONFIG_OUT3_PIN 5 #define PWM1_CONFIG_OUT3_PIN 5
#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz #define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP #define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
#define PWM1_CONFIG_TOP_VALUE 1000 #define PWM1_CONFIG_TOP_VALUE 1000
@ -222,7 +222,7 @@
#define PWM2_CONFIG_OUT1_PIN 3 #define PWM2_CONFIG_OUT1_PIN 3
#define PWM2_CONFIG_OUT2_PIN 4 #define PWM2_CONFIG_OUT2_PIN 4
#define PWM2_CONFIG_OUT3_PIN 5 #define PWM2_CONFIG_OUT3_PIN 5
#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz #define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP #define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
#define PWM2_CONFIG_TOP_VALUE 1000 #define PWM2_CONFIG_TOP_VALUE 1000
@ -243,7 +243,7 @@
#define SPI0_CONFIG_SCK_PIN 2 #define SPI0_CONFIG_SCK_PIN 2
#define SPI0_CONFIG_MOSI_PIN 3 #define SPI0_CONFIG_MOSI_PIN 3
#define SPI0_CONFIG_MISO_PIN 4 #define SPI0_CONFIG_MISO_PIN 4
#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define SPI0_INSTANCE_INDEX 0 #define SPI0_INSTANCE_INDEX 0
#endif #endif
@ -256,7 +256,7 @@
#define SPI1_CONFIG_SCK_PIN 2 #define SPI1_CONFIG_SCK_PIN 2
#define SPI1_CONFIG_MOSI_PIN 3 #define SPI1_CONFIG_MOSI_PIN 3
#define SPI1_CONFIG_MISO_PIN 4 #define SPI1_CONFIG_MISO_PIN 4
#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define SPI1_INSTANCE_INDEX (SPI0_ENABLED) #define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
#endif #endif
@ -269,7 +269,7 @@
#define SPI2_CONFIG_SCK_PIN 2 #define SPI2_CONFIG_SCK_PIN 2
#define SPI2_CONFIG_MOSI_PIN 3 #define SPI2_CONFIG_MOSI_PIN 3
#define SPI2_CONFIG_MISO_PIN 4 #define SPI2_CONFIG_MISO_PIN 4
#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED) #define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
#endif #endif
@ -283,7 +283,7 @@
#define SPIS0_CONFIG_SCK_PIN 2 #define SPIS0_CONFIG_SCK_PIN 2
#define SPIS0_CONFIG_MOSI_PIN 3 #define SPIS0_CONFIG_MOSI_PIN 3
#define SPIS0_CONFIG_MISO_PIN 4 #define SPIS0_CONFIG_MISO_PIN 4
#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define SPIS0_INSTANCE_INDEX 0 #define SPIS0_INSTANCE_INDEX 0
#endif #endif
@ -294,7 +294,7 @@
#define SPIS1_CONFIG_SCK_PIN 2 #define SPIS1_CONFIG_SCK_PIN 2
#define SPIS1_CONFIG_MOSI_PIN 3 #define SPIS1_CONFIG_MOSI_PIN 3
#define SPIS1_CONFIG_MISO_PIN 4 #define SPIS1_CONFIG_MISO_PIN 4
#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED #define SPIS1_INSTANCE_INDEX SPIS0_ENABLED
#endif #endif
@ -305,7 +305,7 @@
#define SPIS2_CONFIG_SCK_PIN 2 #define SPIS2_CONFIG_SCK_PIN 2
#define SPIS2_CONFIG_MOSI_PIN 3 #define SPIS2_CONFIG_MOSI_PIN 3
#define SPIS2_CONFIG_MISO_PIN 4 #define SPIS2_CONFIG_MISO_PIN 4
#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED) #define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED)
#endif #endif
@ -340,7 +340,7 @@
#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K #define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
#define TWI0_CONFIG_SCL 0 #define TWI0_CONFIG_SCL 0
#define TWI0_CONFIG_SDA 1 #define TWI0_CONFIG_SDA 1
#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define TWI0_INSTANCE_INDEX 0 #define TWI0_INSTANCE_INDEX 0
#endif #endif
@ -353,7 +353,7 @@
#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K #define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
#define TWI1_CONFIG_SCL 0 #define TWI1_CONFIG_SCL 0
#define TWI1_CONFIG_SDA 1 #define TWI1_CONFIG_SDA 1
#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define TWI1_INSTANCE_INDEX (TWI0_ENABLED) #define TWI1_INSTANCE_INDEX (TWI0_ENABLED)
#endif #endif
@ -368,7 +368,7 @@
#define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */ #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */
#define TWIS0_CONFIG_SCL 0 #define TWIS0_CONFIG_SCL 0
#define TWIS0_CONFIG_SDA 1 #define TWIS0_CONFIG_SDA 1
#define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define TWIS0_INSTANCE_INDEX 0 #define TWIS0_INSTANCE_INDEX 0
#endif #endif
@ -380,7 +380,7 @@
#define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */ #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */
#define TWIS1_CONFIG_SCL 0 #define TWIS1_CONFIG_SCL 0
#define TWIS1_CONFIG_SDA 1 #define TWIS1_CONFIG_SDA 1
#define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED) #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED)
#endif #endif
@ -402,7 +402,7 @@
#define QDEC_CONFIG_PIO_LED 3 #define QDEC_CONFIG_PIO_LED 3
#define QDEC_CONFIG_LEDPRE 511 #define QDEC_CONFIG_LEDPRE 511
#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH #define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH
#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define QDEC_CONFIG_DBFEN false #define QDEC_CONFIG_DBFEN false
#define QDEC_CONFIG_SAMPLE_INTEN false #define QDEC_CONFIG_SAMPLE_INTEN false
#endif #endif
@ -411,7 +411,7 @@
#define ADC_ENABLED 0 #define ADC_ENABLED 0
#if (ADC_ENABLED == 1) #if (ADC_ENABLED == 1)
#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#endif #endif
@ -421,7 +421,7 @@
#if (SAADC_ENABLED == 1) #if (SAADC_ENABLED == 1)
#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT #define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT
#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED #define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED
#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#endif #endif
/* PDM */ /* PDM */
@ -431,7 +431,7 @@
#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO #define PDM_CONFIG_MODE NRF_PDM_MODE_MONO
#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING #define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING
#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K #define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K
#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#endif #endif
/* COMP */ /* COMP */
@ -443,7 +443,7 @@
#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High #define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High
#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst #define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst
#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off #define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off
#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0 #define COMP_CONFIG_INPUT NRF_COMP_INPUT_0
#endif #endif
@ -453,7 +453,7 @@
#if (LPCOMP_ENABLED == 1) #if (LPCOMP_ENABLED == 1)
#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8 #define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8
#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN #define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN
#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW #define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0 #define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0
#endif #endif

7
targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c
View File

@ -125,7 +125,12 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
.scl = scl, .scl = scl,
.sda = sda, .sda = sda,
.frequency = NRF_TWI_FREQ_100K, .frequency = NRF_TWI_FREQ_100K,
.interrupt_priority = APP_IRQ_PRIORITY_LOW, #ifdef NRF51
.interrupt_priority = APP_IRQ_PRIORITY_LOW
#elif defined(NRF52)
.interrupt_priority = APP_IRQ_PRIORITY_LOWEST
#endif
}; };
for (i = 0; i < TWI_COUNT; ++i) { for (i = 0; i < TWI_COUNT; ++i) {

4
targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/common/nrf_drv_common.c
View File

@ -226,7 +226,11 @@ void nrf_drv_common_irq_enable(IRQn_Type IRQn, uint8_t priority)
{ {
#ifdef SOFTDEVICE_PRESENT #ifdef SOFTDEVICE_PRESENT
#ifdef NRF51
ASSERT((priority == APP_IRQ_PRIORITY_LOW) || (priority == APP_IRQ_PRIORITY_HIGH)); ASSERT((priority == APP_IRQ_PRIORITY_LOW) || (priority == APP_IRQ_PRIORITY_HIGH));
#elif defined(NRF52)
ASSERT((priority == APP_IRQ_PRIORITY_LOWEST) || (priority == APP_IRQ_PRIORITY_HIGH));
#endif
#endif #endif
NVIC_SetPriority(IRQn, priority); NVIC_SetPriority(IRQn, priority);

4
targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/pwm/app_pwm.c
View File

@ -789,7 +789,11 @@ ret_code_t app_pwm_init(app_pwm_t const * const p_instance, app_pwm_config_t con
.frequency = timer_freq, .frequency = timer_freq,
.mode = NRF_TIMER_MODE_TIMER, .mode = NRF_TIMER_MODE_TIMER,
.bit_width = NRF_TIMER_BIT_WIDTH_16, .bit_width = NRF_TIMER_BIT_WIDTH_16,
#ifdef NRF51
.interrupt_priority = APP_IRQ_PRIORITY_LOW, .interrupt_priority = APP_IRQ_PRIORITY_LOW,
#elif defined(NRF52)
.interrupt_priority = APP_IRQ_PRIORITY_LOWEST,
#endif
.p_context = (void *) (uint32_t) p_instance->p_timer->instance_id .p_context = (void *) (uint32_t) p_instance->p_timer->instance_id
}; };
err_code = nrf_drv_timer_init(p_instance->p_timer, &timer_cfg, err_code = nrf_drv_timer_init(p_instance->p_timer, &timer_cfg,

6
targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_log.c
View File

@ -181,7 +181,11 @@ uint32_t log_uart_init()
UART_RX_BUF_SIZE, UART_RX_BUF_SIZE,
UART_TX_BUF_SIZE, UART_TX_BUF_SIZE,
uart_error_cb, uart_error_cb,
APP_IRQ_PRIORITY_LOW, #ifdef NRF51
APP_IRQ_PRIORITY_LOW
#elif defined(NRF52)
APP_IRQ_PRIORITY_LOWEST
#endif
err_code); err_code);
initialized = true; initialized = true;

8
targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c
View File

@ -74,6 +74,12 @@
#define UART_DEFAULT_CTS UART0_CONFIG_PSEL_CTS #define UART_DEFAULT_CTS UART0_CONFIG_PSEL_CTS
#define UART_DEFAULT_RTS UART0_CONFIG_PSEL_RTS #define UART_DEFAULT_RTS UART0_CONFIG_PSEL_RTS
#ifdef NRF51
#define NRFx_MBED_UART_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
#elif defined(NRF52)
#define NRFx_MBED_UART_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
#endif
// Required by "retarget.cpp". // Required by "retarget.cpp".
int stdio_uart_inited = 0; int stdio_uart_inited = 0;
serial_t stdio_uart; serial_t stdio_uart;
@ -287,7 +293,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
#if DEVICE_SERIAL_ASYNCH #if DEVICE_SERIAL_ASYNCH
nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_ERROR); nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_ERROR);
#endif #endif
nrf_drv_common_irq_enable(UART_IRQn, APP_IRQ_PRIORITY_LOW); nrf_drv_common_irq_enable(UART_IRQn, NRFx_MBED_UART_IRQ_PRIORITY);
// TX interrupt needs to be signaled when transmitter buffer is empty, // TX interrupt needs to be signaled when transmitter buffer is empty,
// so a dummy transmission is needed to get the TXDRDY event initially // so a dummy transmission is needed to get the TXDRDY event initially

4
targets/TARGET_NORDIC/TARGET_NRF5/spi_api.c
View File

@ -201,7 +201,7 @@ static void prepare_master_config(nrf_drv_spi_config_t *p_config,
p_config->frequency = p_spi_info->frequency; p_config->frequency = p_spi_info->frequency;
p_config->mode = (nrf_drv_spi_mode_t)p_spi_info->spi_mode; p_config->mode = (nrf_drv_spi_mode_t)p_spi_info->spi_mode;
p_config->irq_priority = APP_IRQ_PRIORITY_LOW; p_config->irq_priority = SPI1_CONFIG_IRQ_PRIORITY;
p_config->orc = 0xFF; p_config->orc = 0xFF;
p_config->bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST; p_config->bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST;
} }
@ -215,7 +215,7 @@ static void prepare_slave_config(nrf_drv_spis_config_t *p_config,
p_config->csn_pin = p_spi_info->ss_pin; p_config->csn_pin = p_spi_info->ss_pin;
p_config->mode = (nrf_drv_spis_mode_t)p_spi_info->spi_mode; p_config->mode = (nrf_drv_spis_mode_t)p_spi_info->spi_mode;
p_config->irq_priority = APP_IRQ_PRIORITY_LOW; p_config->irq_priority = SPIS1_CONFIG_IRQ_PRIORITY;
p_config->orc = NRF_DRV_SPIS_DEFAULT_ORC; p_config->orc = NRF_DRV_SPIS_DEFAULT_ORC;
p_config->def = NRF_DRV_SPIS_DEFAULT_DEF; p_config->def = NRF_DRV_SPIS_DEFAULT_DEF;
p_config->bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST; p_config->bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST;

8
targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c
View File

@ -40,6 +40,7 @@
#include "common_rtc.h" #include "common_rtc.h"
#include "app_util.h" #include "app_util.h"
#include "nrf_drv_common.h" #include "nrf_drv_common.h"
#include "nrf_drv_config.h"
#include "lp_ticker_api.h" #include "lp_ticker_api.h"
@ -125,7 +126,12 @@ void common_rtc_init(void)
US_TICKER_INT_MASK); US_TICKER_INT_MASK);
nrf_drv_common_irq_enable(nrf_drv_get_IRQn(COMMON_RTC_INSTANCE), nrf_drv_common_irq_enable(nrf_drv_get_IRQn(COMMON_RTC_INSTANCE),
APP_IRQ_PRIORITY_LOW); #ifdef NRF51
APP_IRQ_PRIORITY_LOW
#elif defined(NRF52)
APP_IRQ_PRIORITY_LOWEST
#endif
);
nrf_rtc_task_trigger(COMMON_RTC_INSTANCE, NRF_RTC_TASK_START); nrf_rtc_task_trigger(COMMON_RTC_INSTANCE, NRF_RTC_TASK_START);