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Merge pull request #905 from Willem23/master 

LPC81x - Update us_ticker.c, using MRT
pull/931/head
Martin Kojtal 2015-02-24 13:36:38 +00:00
parent 7ae7dafa66 9241e5eaba
commit 1b2a62100a
2 changed files with 118 additions and 67 deletions
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51
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h
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@ -368,23 +368,46 @@ typedef struct { /*!< (@ 0x40028000) WKT Structure
} LPC_WKT_TypeDef; } LPC_WKT_TypeDef;
/*@}*/ /* end of group LPC8xx_WKT */ /*@}*/ /* end of group LPC8xx_WKT */
/*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/ /*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/
typedef struct { //New, Copied from lpc824
__IO uint32_t INTVAL; /**
__IO uint32_t TIMER; * @brief Multi-Rate Timer (MRT) (MRT)
__IO uint32_t CTRL; */
__IO uint32_t STAT; typedef struct { /*!< (@ 0x40004000) MRT Structure */
} MRT_Channel_cfg_Type; __IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value
is loaded into the TIMER0 register. */
typedef struct { __I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the
MRT_Channel_cfg_Type Channel[4]; value of the down-counter. */
uint32_t Reserved0[1]; __IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls
__IO uint32_t IDLE_CH; the MRT0 modes. */
__IO uint32_t IRQ_FLAG; __IO uint32_t STAT0; /*!< (@ 0x4000400C) MRT0 Status register. */
__IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value
is loaded into the TIMER0 register. */
__I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the
value of the down-counter. */
__IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls
the MRT0 modes. */
__IO uint32_t STAT1; /*!< (@ 0x4000401C) MRT0 Status register. */
__IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value
is loaded into the TIMER0 register. */
__I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the
value of the down-counter. */
__IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls
the MRT0 modes. */
__IO uint32_t STAT2; /*!< (@ 0x4000402C) MRT0 Status register. */
__IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value
is loaded into the TIMER0 register. */
__I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the
value of the down-counter. */
__IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls
the MRT0 modes. */
__IO uint32_t STAT3; /*!< (@ 0x4000403C) MRT0 Status register. */
__I uint32_t RESERVED0[45];
__I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns
the number of the first idle channel. */
__IO uint32_t IRQ_FLAG; /*!< (@ 0x400040F8) Global interrupt flag register */
} LPC_MRT_TypeDef; } LPC_MRT_TypeDef;
/*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/ /*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/
/** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter /** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter
@{ @{

118
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c
View File

@ -17,77 +17,105 @@
#include "us_ticker_api.h" #include "us_ticker_api.h"
#include "PeripheralNames.h" #include "PeripheralNames.h"
#define US_TICKER_TIMER_IRQn SCT_IRQn //New, using MRT instead of SCT, needed to free up SCT for PWM
//Ported from LPC824 libs
static int us_ticker_inited = 0;
unsigned int ticker_fullcount_us;
unsigned long int ticker_expired_count_us = 0;
int MRT_Clock_MHz;
int us_ticker_inited = 0; #define US_TICKER_TIMER_IRQn MRT_IRQn
void us_ticker_init(void) { void us_ticker_init(void) {
if (us_ticker_inited) return;
if (us_ticker_inited)
return;
us_ticker_inited = 1; us_ticker_inited = 1;
// Enable the SCT clock // Calculate MRT clock value (MRT has no prescaler)
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); MRT_Clock_MHz = (SystemCoreClock / 1000000);
// Calculate fullcounter value in us (MRT has 31 bits and clock is 30 MHz)
ticker_fullcount_us = 0x80000000UL/MRT_Clock_MHz;
// Clear peripheral reset the SCT: // Enable the MRT clock
LPC_SYSCON->PRESETCTRL |= (1 << 8); LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10);
// Unified counter (32 bits) // Clear peripheral reset the MRT
LPC_SCT->CONFIG |= 1; LPC_SYSCON->PRESETCTRL |= (1 << 7);
// halt and clear the counter // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
LPC_SCT->CTRL_L |= (1 << 2) | (1 << 3); LPC_MRT->INTVAL0 = 0xFFFFFFFFUL;
// Enable Ch0 interrupt, Mode 0 is Repeat Interrupt
LPC_MRT->CTRL0 = (0x0 << 1) | (0x1 << 0);
// System Clock (12)MHz -> us_ticker (1)MHz // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
LPC_SCT->CTRL_L |= ((SystemCoreClock/1000000 - 1) << 5); LPC_MRT->INTVAL1 = 0x80000000UL;
// Disable ch1 interrupt, Mode 0 is Repeat Interrupt
// unhalt the counter: LPC_MRT->CTRL1 = (0x0 << 1) | (0x0 << 0);
// - clearing bit 2 of the CTRL register
LPC_SCT->CTRL_L &= ~(1 << 2);
// Set MRT interrupt vector
NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
} }
//TIMER0 is used for us ticker and timers (Timer, wait(), wait_us() etc)
uint32_t us_ticker_read() { uint32_t us_ticker_read() {
if (!us_ticker_inited) if (!us_ticker_inited)
us_ticker_init(); us_ticker_init();
return LPC_SCT->COUNT_U; // Generate ticker value
// MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer
// Calculate expected value using current count and number of expired times to mimic a 32bit timer @ 1 MHz
//
// ticker_expired_count_us
// The variable ticker_expired_count_us keeps track of the number of 31bits overflows (counted by TIMER0) and
// corrects that back to us counts.
//
// (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_Clock_MHz
// The counter is a 31bit downcounter from 7FFFFFFF so correct to actual count-up value and correct
// for 30 counts per us.
//
// Added up these 2 parts result in current us time returned as 32 bits.
return (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_Clock_MHz + ticker_expired_count_us;
} }
//TIMER1 is used for Timestamped interrupts (Ticker(), Timeout())
void us_ticker_set_interrupt(timestamp_t timestamp) { void us_ticker_set_interrupt(timestamp_t timestamp) {
// halt the counter:
// - setting bit 2 of the CTRL register
LPC_SCT->CTRL_L |= (1 << 2);
// set timestamp in compare register // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer
LPC_SCT->MATCH[0].U = (uint32_t)timestamp; // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
// Note: The MRT has less counter headroom available than the typical mbed 32bit timer @ 1 MHz.
// The calculated counter interval until the next timestamp will be truncated and an
// 'early' interrupt will be generated in case the max required count interval exceeds
// the available 31 bits space. However, the mbed us_ticker interrupt handler will
// check current time against the next scheduled timestamp and simply re-issue the
// same interrupt again when needed. The calculated counter interval will now be smaller.
LPC_MRT->INTVAL1 = (((timestamp - us_ticker_read()) * MRT_Clock_MHz) | 0x80000000UL);
// unhalt the counter: // Enable interrupt
// - clearing bit 2 of the CTRL register LPC_MRT->CTRL1 |= 1;
LPC_SCT->CTRL_L &= ~(1 << 2); }
// if events are not enabled, enable them //Disable Timestamped interrupts triggered by TIMER1
if (!(LPC_SCT->EVEN & 0x01)) { void us_ticker_disable_interrupt() {
//Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock)
LPC_MRT->CTRL1 &= ~1;
}
// comb mode = match only void us_ticker_clear_interrupt() {
LPC_SCT->EVENT[0].CTRL = (1 << 12);
// ref manual: //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock)
// In simple applications that do not if (LPC_MRT->STAT1 & 1)
// use states, write 0x01 to this LPC_MRT->STAT1 = 1;
// register to enable an event
LPC_SCT->EVENT[0].STATE |= 0x1;
// enable events //Timer0 for us counter (31 bits downcounter @ SystemCoreClock)
LPC_SCT->EVEN |= 0x1; if (LPC_MRT->STAT0 & 1) {
LPC_MRT->STAT0 = 1;
// ticker_expired_count_us = (ticker_expired * 0x80000000UL) / MRT_Clock_MHz
// The variable ticker_expired_count_us keeps track of the number of 31bits overflows (counted by TIMER0) and
// the multiplication/division corrects that back to us counts.
ticker_expired_count_us += ticker_fullcount_us;
} }
} }
void us_ticker_disable_interrupt(void) {
LPC_SCT->EVEN &= ~1;
}
void us_ticker_clear_interrupt(void) {
LPC_SCT->EVFLAG = 1;
}