mirror of https://github.com/ARMmbed/mbed-os.git
[NUCLEO_L053R8] Update registers and system files
bcostm
parent
54844496e7
commit
1a95683a30
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@ -2,21 +2,21 @@
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******************************************************************************
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* @file stm32l053xx.h
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* @author MCD Application Team
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* @version V1.1.0
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* @date 18-June-2014
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* @version V1.2.0
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* @date 06-February-2015
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* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for STM32L0xx devices.
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* definitions and memory mapping for stm32l053xx devices.
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*
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* This file contains:
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* - Data structures and the address mapping for all peripherals
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* - Peripheral's registers declarations and bits definition
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* - Macros to access peripheral’s registers hardware
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* - Macros to access peripheral's registers hardware
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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@ -71,7 +71,6 @@
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#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/**
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* @}
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*/
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@ -81,7 +80,7 @@
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*/
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/**
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* @brief STM32L0xx Interrupt Number Definition, according to the selected device
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* @brief stm32l053xx Interrupt Number Definition, according to the selected device
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* in @ref Library_configuration_section
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*/
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@ -121,8 +120,8 @@ typedef enum
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USART1_IRQn = 27, /*!< USART1 Interrupt */
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USART2_IRQn = 28, /*!< USART2 Interrupt */
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RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */
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LCD_IRQn = 30, /*!< LCD Interrupts */
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USB_IRQn = 31 /*!< USB global Interrupt */
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LCD_IRQn = 30, /*!< LCD Interrupt */
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USB_IRQn = 31, /*!< USB global Interrupt */
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} IRQn_Type;
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/**
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@ -193,6 +192,7 @@ typedef struct
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/**
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* @brief Clock Recovery System
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*/
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typedef struct
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{
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__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
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@ -279,7 +279,7 @@ typedef struct
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__IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
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__IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
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__IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
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__IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */
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__IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
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__IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
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} FLASH_TypeDef;
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@ -291,7 +291,7 @@ typedef struct
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{
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__IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
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__IO uint32_t USER; /*!< user register, Address offset: 0x04 */
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__IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */
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__IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
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} OB_TypeDef;
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@ -445,7 +445,6 @@ typedef struct
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__IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
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} RCC_TypeDef;
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/**
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* @brief Random numbers generator
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*/
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@ -456,7 +455,6 @@ typedef struct
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__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
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} RNG_TypeDef;
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/**
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* @brief Real-Time Clock
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*/
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@ -623,7 +621,6 @@ typedef struct
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__IO uint16_t RESERVEDE; /*!< Reserved */
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} USB_TypeDef;
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/**
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* @}
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*/
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@ -634,8 +631,8 @@ typedef struct
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#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
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#define FLASH_END ((uint32_t)0x0800FFFF) /*!< FLASH end address in the alias region */
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#define DATA_EEPROM_BASE ((uint32_t)0x08080000) /*!<DATA_EEPROM base address in the alias region */
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#define DATA_EEPROM_END ((uint32_t)0x080807FF) /*!<DATA_EEPROM end address in the alias region */
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#define DATA_EEPROM_BASE ((uint32_t)0x08080000) /*!< DATA_EEPROM base address in the alias region */
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#define DATA_EEPROM_END ((uint32_t)0x080807FF) /*!< DATA EEPROM end address in the alias region */
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#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
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#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
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@ -1055,22 +1052,22 @@ typedef struct
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#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
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#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
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#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Interrupt enable */
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#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun interrupt enable */
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/***************** Bit definition for DAC_SWTRIGR register ******************/
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#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */
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#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
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/***************** Bit definition for DAC_DHR12R1 register ******************/
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#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */
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#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
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/***************** Bit definition for DAC_DHR12L1 register ******************/
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#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */
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#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
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/****************** Bit definition for DAC_DHR8R1 register ******************/
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#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */
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#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
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/******************* Bit definition for DAC_DOR1 register *******************/
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#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */
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#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFF) /*!< DAC channel1 data output */
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/******************** Bit definition for DAC_SR register ********************/
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#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
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@ -1103,6 +1100,7 @@ typedef struct
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#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
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/****************** Bit definition for DBGMCU_CR register *******************/
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#define DBGMCU_CR_DBG ((uint32_t)0x00000007) /*!< Debug mode mask */
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#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
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#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
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#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
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@ -1367,6 +1365,7 @@ typedef struct
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#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
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#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
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#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
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/****************** Bit definition for EXTI_PR register *********************/
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#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
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#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
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@ -1411,7 +1410,7 @@ typedef struct
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#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
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#define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
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#define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
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#define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
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#define FLASH_PECR_FIX ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
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#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
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#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
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#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
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@ -1434,7 +1433,7 @@ typedef struct
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/****************** Bit definition for FLASH_SR register *******************/
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#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
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#define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
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#define FLASH_SR_ENDHV ((uint32_t)0x00000004) /*!< End of high voltage */
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#define FLASH_SR_HVOFF ((uint32_t)0x00000004) /*!< End of high voltage */
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#define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
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#define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protection error */
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@ -1447,12 +1446,18 @@ typedef struct
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/* alias maintained for legacy */
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#define FLASH_SR_FWWER FLASH_SR_FWWERR
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#define FLASH_SR_ENHV FLASH_SR_ENDHV
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#define FLASH_SR_ENHV FLASH_SR_HVOFF
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#define FLASH_SR_ENDHV FLASH_SR_HVOFF
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/****************** Bit definition for FLASH_OBR register *******************/
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#define FLASH_OBR_RDPRT ((uint32_t)0x000000AA) /*!< Read Protection */
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#define FLASH_OBR_SPRMOD ((uint32_t)0x00000100) /*!< Selection of protection mode of WPR bits */
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#define FLASH_OBR_BOR_LEV ((uint32_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
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/****************** Bit definition for FLASH_OPTR register *******************/
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#define FLASH_OPTR_RDPROT ((uint32_t)0x000000FF) /*!< Read Protection */
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#define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100) /*!< Selection of protection mode of WPR bits */
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#define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
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#define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */
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#define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */
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#define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */
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#define FLASH_OPTR_USER ((uint32_t)0x00700000) /*!< User Option Bytes */
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#define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000) /*!< BOOT1 */
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/****************** Bit definition for FLASH_WRPR register ******************/
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#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protection bits */
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@ -1885,8 +1890,6 @@ typedef struct
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#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */
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#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */
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#define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /*!< Mux Segment Enable Bit */
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/******************* Bit definition for LCD_FCR register ********************/
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#define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */
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#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */
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#define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x0000400) /*!< Bit 0 */
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#define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /*!< Bit 1 */
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/*!< I2C2 Clock source selection */
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/*!< I2C1 Clock source selection */
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#define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000) /*!< I2C1SEL [1:0] bits */
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#define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
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#define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
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/*!< LPTIM1 Clock source selection */
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#define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000) /*!< LPTIM1SEL [1:0] bits */
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#define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
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@ -2805,9 +2809,12 @@ typedef struct
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#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
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/******************** Bits definition for RTC_OR register ****************/
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#define RTC_OR_RTC_OUT_RMP ((uint32_t)0x00000002) /*!< */
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#define RTC_OR_OUT_RMP ((uint32_t)0x00000002) /*!< */
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#define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001) /*!< */
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/* Bit names aliases maintained for legacy */
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#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
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/******************** Bits definition for RTC_BKP0R register ****************/
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#define RTC_BKP0R ((uint32_t)0xFFFFFFFF) /*!< */
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#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
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#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
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#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
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/****************** Bit definition for SPI_I2SPR register *******************/
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#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
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#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
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#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
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#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
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/**
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* @brief EXTI5 configuration
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*/
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#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
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#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
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#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
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#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
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#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
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#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
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#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
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#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
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#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
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#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
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#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
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#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
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#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
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/******************** Bit definition for TIM_SR register ********************/
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/******************* Bit definition for TIM_DMAR register *******************/
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#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
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/******************* Bit definition for TIM_OR register *********************/
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/******************* Bit definition for TIM_OR register *********************/
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#define TIM2_OR_ETR_RMP ((uint32_t)0x00000007) /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
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#define TIM2_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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#define TIM22_OR_TI1_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
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#define TIM22_OR_TI1_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
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/******************************************************************************/
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/* */
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/* Touch Sensing Controller (TSC) */
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/******************************* ADC Instances ********************************/
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#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
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/******************************** COMP Instances ******************************/
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/******************************* COMP Instances *******************************/
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#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
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((INSTANCE) == COMP2))
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/******************************* CRC Instances ********************************/
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#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
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/******************************* DAC Instances ********************************/
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/******************************* DAC Instances *********************************/
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#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
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/******************************** DMA Instances *******************************/
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/******************************* DMA Instances *********************************/
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#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
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((INSTANCE) == DMA1_Stream1) || \
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((INSTANCE) == DMA1_Stream2) || \
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((INSTANCE) == GPIOD) || \
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((INSTANCE) == GPIOH))
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/******************************** I2C Instances *******************************/
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#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
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((INSTANCE) == I2C2))
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/******************************** I2S Instances *******************************/
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#define IS_I2S_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
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#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
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/******************************* RNG Instances ********************************/
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#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
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/******************************** SPI Instances *******************************/
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#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
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((INSTANCE) == SPI2))
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/****************** LPTIM Instances : All supported instances *****************/
|
||||
#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
|
||||
|
||||
|
|
@ -4035,10 +4037,10 @@ typedef struct
|
|||
/******************* TIM Instances : Timer input XOR function *****************/
|
||||
#define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
|
||||
|
||||
|
||||
/****************** TIM Instances : DMA requests generation (UDE) *************/
|
||||
#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM6))
|
||||
|
||||
/************ TIM Instances : DMA requests generation (CCxDE) *****************/
|
||||
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
|
||||
|
||||
|
|
@ -4096,12 +4098,31 @@ typedef struct
|
|||
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2))
|
||||
|
||||
/****************** USART Instances : Auto Baud Rate detection ****************/
|
||||
|
||||
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2))
|
||||
|
||||
/******************** UART Instances : Half-Duplex mode **********************/
|
||||
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == LPUART1))
|
||||
|
||||
/******************** UART Instances : LIN mode **********************/
|
||||
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2))
|
||||
|
||||
/******************** UART Instances : Wake-up from Stop mode **********************/
|
||||
|
||||
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == LPUART1))
|
||||
|
||||
/****************** UART Instances : Hardware Flow control ********************/
|
||||
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == LPUART1))
|
||||
|
||||
|
||||
/********************* UART Instances : Smard card mode ***********************/
|
||||
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2))
|
||||
|
|
@ -4119,6 +4140,9 @@ typedef struct
|
|||
/****************************** WWDG Instances ********************************/
|
||||
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
|
||||
|
||||
/****************************** LCD Instances ********************************/
|
||||
#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -4136,18 +4160,14 @@ typedef struct
|
|||
#define LPUART1_IRQn RNG_LPUART1_IRQn
|
||||
#define AES_LPUART1_IRQn RNG_LPUART1_IRQn
|
||||
#define AES_RNG_LPUART1_IRQn RNG_LPUART1_IRQn
|
||||
|
||||
#define TIM6_IRQn TIM6_DAC_IRQn
|
||||
|
||||
#define RCC_IRQn RCC_CRS_IRQn
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define LPUART1_IRQHandler RNG_LPUART1_IRQHandler
|
||||
#define AES_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
|
||||
#define AES_RNG_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
|
||||
|
||||
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
|
||||
|
||||
#define RCC_IRQHandler RCC_CRS_IRQHandler
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32l0xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 18-June-2014
|
||||
* @version V1.2.0
|
||||
* @date 06-February-2015
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for STM32L0xx devices.
|
||||
|
|
@ -20,7 +20,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -66,18 +66,31 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32 Family
|
||||
*/
|
||||
#if !defined (STM32L0)
|
||||
#define STM32L0
|
||||
#endif /* STM32L0 */
|
||||
|
||||
/* Uncomment the line below according to the target STM32 device used in your
|
||||
application
|
||||
*/
|
||||
|
||||
#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && !defined (STM32L062xx) && \
|
||||
!defined (STM32L063xx) && !defined (STM32L061xx)
|
||||
/* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6,STM32L051C8,STM32L051R6 and STM32L051R8 Devices */
|
||||
/* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8,STM32L052C6,STM32L052C8,STM32L052R6 and STM32L052R8 Devices */
|
||||
#define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, and STM32L053R8 Devices */
|
||||
#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) \
|
||||
&& !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx)
|
||||
/* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */
|
||||
/* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */
|
||||
#define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
|
||||
/* #define STM32L061xx */ /*!< */
|
||||
/* #define STM32L062xx */ /*!< STM32L062K8 */
|
||||
/* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */
|
||||
/* #define STM32L061xx */
|
||||
/* #define STM32L071xx */ /*!< */
|
||||
/* #define STM32L072xx */ /*!< */
|
||||
/* #define STM32L073xx */ /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */
|
||||
/* #define STM32L081xx */ /*!< */
|
||||
/* #define STM32L082xx */ /*!< */
|
||||
/* #define STM32L083xx */ /*!< */
|
||||
#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
|
|
@ -93,10 +106,10 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V1.1.0
|
||||
* @brief CMSIS Device version number V1.2.0
|
||||
*/
|
||||
#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
|
||||
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32L0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|
|
@ -112,7 +125,11 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32L051xx)
|
||||
#if defined(STM32L031xx)
|
||||
#include "stm32l031xx.h"
|
||||
#elif defined(STM32L041xx)
|
||||
#include "stm32l041xx.h"
|
||||
#elif defined(STM32L051xx)
|
||||
#include "stm32l051xx.h"
|
||||
#elif defined(STM32L052xx)
|
||||
#include "stm32l052xx.h"
|
||||
|
|
@ -124,6 +141,18 @@
|
|||
#include "stm32l063xx.h"
|
||||
#elif defined(STM32L061xx)
|
||||
#include "stm32l061xx.h"
|
||||
#elif defined(STM32L071xx)
|
||||
#include "stm32l071xx.h"
|
||||
#elif defined(STM32L072xx)
|
||||
#include "stm32l072xx.h"
|
||||
#elif defined(STM32L073xx)
|
||||
#include "stm32l073xx.h"
|
||||
#elif defined(STM32L082xx)
|
||||
#include "stm32l082xx.h"
|
||||
#elif defined(STM32L083xx)
|
||||
#include "stm32l083xx.h"
|
||||
#elif defined(STM32L081xx)
|
||||
#include "stm32l081xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)"
|
||||
#endif
|
||||
|
|
@ -177,7 +206,6 @@ typedef enum
|
|||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -186,7 +214,6 @@ typedef enum
|
|||
#include "stm32l0xx_hal.h"
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32l0xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 18-June-2014
|
||||
* @version V1.2.0
|
||||
* @date 06-February-2015
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
|
|
@ -40,7 +40,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -145,12 +145,9 @@
|
|||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 32000000;
|
||||
|
||||
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
|
||||
const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
//const uint32_t MSIRangeTable[7] = {64000, 128000, 256000, 512000, 1000000, 2000000, 4000000};
|
||||
uint32_t SystemCoreClock = 32000000;
|
||||
__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
__IO const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -270,7 +267,8 @@ void SystemCoreClockUpdate (void)
|
|||
switch (tmp)
|
||||
{
|
||||
case 0x00: /* MSI used as system clock */
|
||||
SystemCoreClock = ((1 <<((RCC->ICSCR & RCC_ICSCR_MSIRANGE)>>13 ))* 64000);
|
||||
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
|
||||
SystemCoreClock = (32768 * (1 << (msirange + 1)));
|
||||
break;
|
||||
case 0x04: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32l0xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 18-June-2014
|
||||
* @version V1.2.0
|
||||
* @date 06-February-2015
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
Loading…
Reference in New Issue