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[NUCLEO_L053R8] Update registers and system files

pull/961/head
bcostm 2015-03-10 11:44:55 +01:00
parent 54844496e7
commit 1a95683a30
4 changed files with 2010 additions and 1965 deletions
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118
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/stm32l053xx.h
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@ -2,21 +2,21 @@
****************************************************************************** ******************************************************************************
* @file stm32l053xx.h * @file stm32l053xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.1.0 * @version V1.2.0
* @date 18-June-2014 * @date 06-February-2015
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices. * definitions and memory mapping for stm32l053xx devices.
* *
* This file contains: * This file contains:
* - Data structures and the address mapping for all peripherals * - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition * - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware * - Macros to access peripheral's registers hardware
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -71,7 +71,6 @@
#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ #define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/** /**
* @} * @}
*/ */
@ -81,7 +80,7 @@
*/ */
/** /**
* @brief STM32L0xx Interrupt Number Definition, according to the selected device * @brief stm32l053xx Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section * in @ref Library_configuration_section
*/ */
@ -121,8 +120,8 @@ typedef enum
USART1_IRQn = 27, /*!< USART1 Interrupt */ USART1_IRQn = 27, /*!< USART1 Interrupt */
USART2_IRQn = 28, /*!< USART2 Interrupt */ USART2_IRQn = 28, /*!< USART2 Interrupt */
RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */ RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */
LCD_IRQn = 30, /*!< LCD Interrupts */ LCD_IRQn = 30, /*!< LCD Interrupt */
USB_IRQn = 31 /*!< USB global Interrupt */ USB_IRQn = 31, /*!< USB global Interrupt */
} IRQn_Type; } IRQn_Type;
/** /**
@ -193,6 +192,7 @@ typedef struct
/** /**
* @brief Clock Recovery System * @brief Clock Recovery System
*/ */
typedef struct typedef struct
{ {
__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
@ -279,7 +279,7 @@ typedef struct
__IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
__IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
__IO uint32_t SR; /*!< Status register, Address offset: 0x18 */ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
__IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
__IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
} FLASH_TypeDef; } FLASH_TypeDef;
@ -291,7 +291,7 @@ typedef struct
{ {
__IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
__IO uint32_t USER; /*!< user register, Address offset: 0x04 */ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
__IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
} OB_TypeDef; } OB_TypeDef;
@ -445,7 +445,6 @@ typedef struct
__IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
} RCC_TypeDef; } RCC_TypeDef;
/** /**
* @brief Random numbers generator * @brief Random numbers generator
*/ */
@ -456,7 +455,6 @@ typedef struct
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
} RNG_TypeDef; } RNG_TypeDef;
/** /**
* @brief Real-Time Clock * @brief Real-Time Clock
*/ */
@ -623,7 +621,6 @@ typedef struct
__IO uint16_t RESERVEDE; /*!< Reserved */ __IO uint16_t RESERVEDE; /*!< Reserved */
} USB_TypeDef; } USB_TypeDef;
/** /**
* @} * @}
*/ */
@ -635,7 +632,7 @@ typedef struct
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define FLASH_END ((uint32_t)0x0800FFFF) /*!< FLASH end address in the alias region */ #define FLASH_END ((uint32_t)0x0800FFFF) /*!< FLASH end address in the alias region */
#define DATA_EEPROM_BASE ((uint32_t)0x08080000) /*!< DATA_EEPROM base address in the alias region */ #define DATA_EEPROM_BASE ((uint32_t)0x08080000) /*!< DATA_EEPROM base address in the alias region */
#define DATA_EEPROM_END ((uint32_t)0x080807FF) /*!<DATA_EEPROM end address in the alias region */ #define DATA_EEPROM_END ((uint32_t)0x080807FF) /*!< DATA EEPROM end address in the alias region */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
@ -1055,22 +1052,22 @@ typedef struct
#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Interrupt enable */ #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun interrupt enable */
/***************** Bit definition for DAC_SWTRIGR register ******************/ /***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
/***************** Bit definition for DAC_DHR12R1 register ******************/ /***************** Bit definition for DAC_DHR12R1 register ******************/
#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L1 register ******************/ /***************** Bit definition for DAC_DHR12L1 register ******************/
#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R1 register ******************/ /****************** Bit definition for DAC_DHR8R1 register ******************/
#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/ /******************* Bit definition for DAC_DOR1 register *******************/
#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ #define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFF) /*!< DAC channel1 data output */
/******************** Bit definition for DAC_SR register ********************/ /******************** Bit definition for DAC_SR register ********************/
#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
@ -1103,6 +1100,7 @@ typedef struct
#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
/****************** Bit definition for DBGMCU_CR register *******************/ /****************** Bit definition for DBGMCU_CR register *******************/
#define DBGMCU_CR_DBG ((uint32_t)0x00000007) /*!< Debug mode mask */
#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
@ -1367,6 +1365,7 @@ typedef struct
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */ #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */ #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */ #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/****************** Bit definition for EXTI_PR register *********************/ /****************** Bit definition for EXTI_PR register *********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */ #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */ #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
@ -1411,7 +1410,7 @@ typedef struct
#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */ #define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
#define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */ #define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
#define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */ #define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
#define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */ #define FLASH_PECR_FIX ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */ #define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */ #define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */ #define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
@ -1434,7 +1433,7 @@ typedef struct
/****************** Bit definition for FLASH_SR register *******************/ /****************** Bit definition for FLASH_SR register *******************/
#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */ #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
#define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/ #define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
#define FLASH_SR_ENDHV ((uint32_t)0x00000004) /*!< End of high voltage */ #define FLASH_SR_HVOFF ((uint32_t)0x00000004) /*!< End of high voltage */
#define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */ #define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
#define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protection error */ #define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protection error */
@ -1447,12 +1446,18 @@ typedef struct
/* alias maintained for legacy */ /* alias maintained for legacy */
#define FLASH_SR_FWWER FLASH_SR_FWWERR #define FLASH_SR_FWWER FLASH_SR_FWWERR
#define FLASH_SR_ENHV FLASH_SR_ENDHV #define FLASH_SR_ENHV FLASH_SR_HVOFF
#define FLASH_SR_ENDHV FLASH_SR_HVOFF
/****************** Bit definition for FLASH_OBR register *******************/ /****************** Bit definition for FLASH_OPTR register *******************/
#define FLASH_OBR_RDPRT ((uint32_t)0x000000AA) /*!< Read Protection */ #define FLASH_OPTR_RDPROT ((uint32_t)0x000000FF) /*!< Read Protection */
#define FLASH_OBR_SPRMOD ((uint32_t)0x00000100) /*!< Selection of protection mode of WPR bits */ #define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100) /*!< Selection of protection mode of WPR bits */
#define FLASH_OBR_BOR_LEV ((uint32_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ #define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
#define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */
#define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */
#define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */
#define FLASH_OPTR_USER ((uint32_t)0x00700000) /*!< User Option Bytes */
#define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000) /*!< BOOT1 */
/****************** Bit definition for FLASH_WRPR register ******************/ /****************** Bit definition for FLASH_WRPR register ******************/
#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protection bits */ #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protection bits */
@ -1885,8 +1890,6 @@ typedef struct
#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */ #define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */
#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */ #define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */
#define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /*!< Mux Segment Enable Bit */
/******************* Bit definition for LCD_FCR register ********************/ /******************* Bit definition for LCD_FCR register ********************/
#define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */ #define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */
#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */ #define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */
@ -2416,11 +2419,12 @@ typedef struct
#define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x0000400) /*!< Bit 0 */ #define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x0000400) /*!< Bit 0 */
#define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /*!< Bit 1 */ #define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /*!< Bit 1 */
/*!< I2C2 Clock source selection */ /*!< I2C1 Clock source selection */
#define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000) /*!< I2C1SEL [1:0] bits */ #define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000) /*!< I2C1SEL [1:0] bits */
#define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ #define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
#define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ #define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
/*!< LPTIM1 Clock source selection */ /*!< LPTIM1 Clock source selection */
#define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000) /*!< LPTIM1SEL [1:0] bits */ #define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000) /*!< LPTIM1SEL [1:0] bits */
#define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ #define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
@ -2805,9 +2809,12 @@ typedef struct
#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_OR register ****************/ /******************** Bits definition for RTC_OR register ****************/
#define RTC_OR_RTC_OUT_RMP ((uint32_t)0x00000002) /*!< */ #define RTC_OR_OUT_RMP ((uint32_t)0x00000002) /*!< */
#define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001) /*!< */ #define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001) /*!< */
/* Bit names aliases maintained for legacy */
#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
/******************** Bits definition for RTC_BKP0R register ****************/ /******************** Bits definition for RTC_BKP0R register ****************/
#define RTC_BKP0R ((uint32_t)0xFFFFFFFF) /*!< */ #define RTC_BKP0R ((uint32_t)0xFFFFFFFF) /*!< */
@ -2894,7 +2901,6 @@ typedef struct
#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */ #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */ #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */ #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
/****************** Bit definition for SPI_I2SPR register *******************/ /****************** Bit definition for SPI_I2SPR register *******************/
#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */ #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */ #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
@ -2976,7 +2982,6 @@ typedef struct
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */ #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */ #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
/** /**
* @brief EXTI5 configuration * @brief EXTI5 configuration
*/ */
@ -3167,15 +3172,12 @@ typedef struct
#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */ #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */ #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */ #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */ #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */ #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */ #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */ #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */ #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */ #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */ #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
/******************** Bit definition for TIM_SR register ********************/ /******************** Bit definition for TIM_SR register ********************/
@ -3385,7 +3387,6 @@ typedef struct
/******************* Bit definition for TIM_DMAR register *******************/ /******************* Bit definition for TIM_DMAR register *******************/
#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */ #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
/******************* Bit definition for TIM_OR register *********************/
/******************* Bit definition for TIM_OR register *********************/ /******************* Bit definition for TIM_OR register *********************/
#define TIM2_OR_ETR_RMP ((uint32_t)0x00000007) /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */ #define TIM2_OR_ETR_RMP ((uint32_t)0x00000007) /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
#define TIM2_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */ #define TIM2_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
@ -3411,6 +3412,7 @@ typedef struct
#define TIM22_OR_TI1_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ #define TIM22_OR_TI1_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
#define TIM22_OR_TI1_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ #define TIM22_OR_TI1_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
/* Touch Sensing Controller (TSC) */ /* Touch Sensing Controller (TSC) */
@ -3958,17 +3960,17 @@ typedef struct
/******************************* ADC Instances ********************************/ /******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
/******************************** COMP Instances ******************************/ /******************************* COMP Instances *******************************/
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2)) ((INSTANCE) == COMP2))
/******************************* CRC Instances ********************************/ /******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/******************************* DAC Instances ********************************/ /******************************* DAC Instances *********************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC) #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
/******************************** DMA Instances *******************************/ /******************************* DMA Instances *********************************/
#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \ #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
((INSTANCE) == DMA1_Stream1) || \ ((INSTANCE) == DMA1_Stream1) || \
((INSTANCE) == DMA1_Stream2) || \ ((INSTANCE) == DMA1_Stream2) || \
@ -3985,13 +3987,12 @@ typedef struct
((INSTANCE) == GPIOD) || \ ((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOH)) ((INSTANCE) == GPIOH))
/******************************** I2C Instances *******************************/ /******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2)) ((INSTANCE) == I2C2))
/******************************** I2S Instances *******************************/ /******************************** I2S Instances *******************************/
#define IS_I2S_INSTANCE(INSTANCE) ((INSTANCE) == SPI2) #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
/******************************* RNG Instances ********************************/ /******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
@ -4005,6 +4006,7 @@ typedef struct
/******************************** SPI Instances *******************************/ /******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2)) ((INSTANCE) == SPI2))
/****************** LPTIM Instances : All supported instances *****************/ /****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1) #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
@ -4035,10 +4037,10 @@ typedef struct
/******************* TIM Instances : Timer input XOR function *****************/ /******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2) #define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
/****************** TIM Instances : DMA requests generation (UDE) *************/ /****************** TIM Instances : DMA requests generation (UDE) *************/
#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
((INSTANCE) == TIM6)) ((INSTANCE) == TIM6))
/************ TIM Instances : DMA requests generation (CCxDE) *****************/ /************ TIM Instances : DMA requests generation (CCxDE) *****************/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2) #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
@ -4096,12 +4098,31 @@ typedef struct
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2)) ((INSTANCE) == USART2))
/****************** USART Instances : Auto Baud Rate detection ****************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == LPUART1))
/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == LPUART1))
/****************** UART Instances : Hardware Flow control ********************/ /****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \ ((INSTANCE) == USART2) || \
((INSTANCE) == LPUART1)) ((INSTANCE) == LPUART1))
/********************* UART Instances : Smard card mode ***********************/ /********************* UART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2)) ((INSTANCE) == USART2))
@ -4119,6 +4140,9 @@ typedef struct
/****************************** WWDG Instances ********************************/ /****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** LCD Instances ********************************/
#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
/** /**
* @} * @}
*/ */
@ -4136,18 +4160,14 @@ typedef struct
#define LPUART1_IRQn RNG_LPUART1_IRQn #define LPUART1_IRQn RNG_LPUART1_IRQn
#define AES_LPUART1_IRQn RNG_LPUART1_IRQn #define AES_LPUART1_IRQn RNG_LPUART1_IRQn
#define AES_RNG_LPUART1_IRQn RNG_LPUART1_IRQn #define AES_RNG_LPUART1_IRQn RNG_LPUART1_IRQn
#define TIM6_IRQn TIM6_DAC_IRQn #define TIM6_IRQn TIM6_DAC_IRQn
#define RCC_IRQn RCC_CRS_IRQn #define RCC_IRQn RCC_CRS_IRQn
/* Aliases for __IRQHandler */ /* Aliases for __IRQHandler */
#define LPUART1_IRQHandler RNG_LPUART1_IRQHandler #define LPUART1_IRQHandler RNG_LPUART1_IRQHandler
#define AES_LPUART1_IRQHandler RNG_LPUART1_IRQHandler #define AES_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
#define AES_RNG_LPUART1_IRQHandler RNG_LPUART1_IRQHandler #define AES_RNG_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
#define TIM6_IRQHandler TIM6_DAC_IRQHandler #define TIM6_IRQHandler TIM6_DAC_IRQHandler
#define RCC_IRQHandler RCC_CRS_IRQHandler #define RCC_IRQHandler RCC_CRS_IRQHandler
/** /**

55
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/stm32l0xx.h
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32l0xx.h * @file stm32l0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.1.0 * @version V1.2.0
* @date 18-June-2014 * @date 06-February-2015
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices. * definitions and memory mapping for STM32L0xx devices.
@ -20,7 +20,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -66,18 +66,31 @@
* @{ * @{
*/ */
/**
* @brief STM32 Family
*/
#if !defined (STM32L0)
#define STM32L0
#endif /* STM32L0 */
/* Uncomment the line below according to the target STM32 device used in your /* Uncomment the line below according to the target STM32 device used in your
application application
*/ */
#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && !defined (STM32L062xx) && \ #if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) \
!defined (STM32L063xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx)
/* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6,STM32L051C8,STM32L051R6 and STM32L051R8 Devices */ /* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */
/* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8,STM32L052C6,STM32L052C8,STM32L052R6 and STM32L052R8 Devices */ /* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */
#define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, and STM32L053R8 Devices */ #define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
/* #define STM32L061xx */ /*!< */
/* #define STM32L062xx */ /*!< STM32L062K8 */ /* #define STM32L062xx */ /*!< STM32L062K8 */
/* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */ /* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */
/* #define STM32L061xx */ /* #define STM32L071xx */ /*!< */
/* #define STM32L072xx */ /*!< */
/* #define STM32L073xx */ /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */
/* #define STM32L081xx */ /*!< */
/* #define STM32L082xx */ /*!< */
/* #define STM32L083xx */ /*!< */
#endif #endif
/* Tip: To avoid modifying this file each time you need to switch between these /* Tip: To avoid modifying this file each time you need to switch between these
@ -93,10 +106,10 @@
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V1.1.0 * @brief CMSIS Device version number V1.2.0
*/ */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ #define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ #define __STM32L0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
@ -112,7 +125,11 @@
* @{ * @{
*/ */
#if defined(STM32L051xx) #if defined(STM32L031xx)
#include "stm32l031xx.h"
#elif defined(STM32L041xx)
#include "stm32l041xx.h"
#elif defined(STM32L051xx)
#include "stm32l051xx.h" #include "stm32l051xx.h"
#elif defined(STM32L052xx) #elif defined(STM32L052xx)
#include "stm32l052xx.h" #include "stm32l052xx.h"
@ -124,6 +141,18 @@
#include "stm32l063xx.h" #include "stm32l063xx.h"
#elif defined(STM32L061xx) #elif defined(STM32L061xx)
#include "stm32l061xx.h" #include "stm32l061xx.h"
#elif defined(STM32L071xx)
#include "stm32l071xx.h"
#elif defined(STM32L072xx)
#include "stm32l072xx.h"
#elif defined(STM32L073xx)
#include "stm32l073xx.h"
#elif defined(STM32L082xx)
#include "stm32l082xx.h"
#elif defined(STM32L083xx)
#include "stm32l083xx.h"
#elif defined(STM32L081xx)
#include "stm32l081xx.h"
#else #else
#error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)" #error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)"
#endif #endif
@ -177,7 +206,6 @@ typedef enum
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
/** /**
* @} * @}
*/ */
@ -186,7 +214,6 @@ typedef enum
#include "stm32l0xx_hal.h" #include "stm32l0xx_hal.h"
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif /* __cplusplus */ #endif /* __cplusplus */

16
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file system_stm32l0xx.c * @file system_stm32l0xx.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.1.0 * @version V1.2.0
* @date 18-June-2014 * @date 06-February-2015
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
* *
* This file provides two functions and one global variable to be called from * This file provides two functions and one global variable to be called from
@ -40,7 +40,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -146,11 +146,8 @@
variable is updated automatically. variable is updated automatically.
*/ */
uint32_t SystemCoreClock = 32000000; uint32_t SystemCoreClock = 32000000;
__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; __IO const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
//const uint32_t MSIRangeTable[7] = {64000, 128000, 256000, 512000, 1000000, 2000000, 4000000};
/** /**
* @} * @}
@ -270,7 +267,8 @@ void SystemCoreClockUpdate (void)
switch (tmp) switch (tmp)
{ {
case 0x00: /* MSI used as system clock */ case 0x00: /* MSI used as system clock */
SystemCoreClock = ((1 <<((RCC->ICSCR & RCC_ICSCR_MSIRANGE)>>13 ))* 64000); msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
SystemCoreClock = (32768 * (1 << (msirange + 1)));
break; break;
case 0x04: /* HSI used as system clock */ case 0x04: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE; SystemCoreClock = HSI_VALUE;

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.h
View File

@ -2,13 +2,13 @@
****************************************************************************** ******************************************************************************
* @file system_stm32l0xx.h * @file system_stm32l0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.1.0 * @version V1.2.0
* @date 18-June-2014 * @date 06-February-2015
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met: