diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt index 2e8ebff97b..c7eda3458e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt @@ -1,4 +1,45 @@ ================ Revision history ============================================ +5.1.2: + Misc. bugfixes and improvements. + +5.1.1: + - Enabled errata CMU_E113 workaround for EFM32GG revE. + +5.1.0: + - em_timer: Added support for WTIMER0 and WTIMER1. Added EFM_ASSERT in + em_timer to check that operations on a 16 bit timer is always <= 0xFFFF. + - em_usart: Updated the baudrate sync calculation in USART_BaudrateSyncSet(). + The calculated baudrate is not using any fractional bits and it is always + lower than or equal to the specified frequency. + - em_emu: added function EMU_DCDCConductionModeSet() to allow switching + between DCDC Low-Noise Continuous Conduction Mode (CCM) and + Discontinuous Conduction Mode (DCM). + - SYSTEM_GetSRAMSize() updated to return size of SRAM excluding RAMH for EFR32xG1. + - em_csen: Added support for CSEN (Capacitive Sense Module). + - em_adc: updated ADC_PosSel_TypeDef enum names. + - em_vdac: Added support for VDAC (voltage DAC). + - em_smu: Added support for SMU (Security Management Unit) module. + SMU is used to restrict access to device peripherals. + - Updated emlib to use the _SILICON_LABS_32B_SERIES_x, + _SILICON_LABS_32B_SERIES_x_CONFIG and _SILICON_LABS_GECKO_INTERNAL_SDID_x + macros instead of the _SILICON_LABS_32B_PLATFORM_x and + _SILICON_LABS_32B_PLATFORM_x_GEN_x macros. + - em_rtcc: added workarounds for errata RTCC_E203 and RTCC_E204 for + EFR32xG12, EFM32xG12, EFR32xG13 and EFM32xG13 devices. + - em_lesense: added LESENSE_DecoderPrsOut() for configuring PRS output + from the LESENSE decoder on EFM32xG12 and EFR32xG12. + - em_lesense: added support for the new evaluation modes for EFM32xG12 and + EFR32xG12. + - em_emu: added EMU_RamPowerDown() function for powering down a memory range + and deprecating EMU_MemPwrDown(). + - em_emu: added support for voltage scaling. + - em_emu: added support for EM2 and 3 peripheral retention control. + - em_chip: added current consumption fixes for EFM32xG12 and EFR32xG12. + - em_emu: added support for DCDC EM01-LP mode. + - em_lesense: Support for Series 1 devices + - em_acmp: Added ACMP_ExternalInputSelect() which is used when the ACMP is + controlled by an external module like LESENSE. + 5.0.0: - em_core: New module, contains API for enabling/disabling interrupts and implementing critical regions. diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h index 19345e9a97..ed9de1b4dd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_acmp.h * @brief Analog Comparator (ACMP) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -283,7 +283,7 @@ typedef enum } ACMP_VLPInput_Typedef; #endif -#if defined(_SILICON_LABS_32B_PLATFORM_2) +#if defined(_ACMP_INPUTSEL_POSSEL_APORT0XCH0) /** ACMP Input Selection */ typedef enum { @@ -447,8 +447,12 @@ typedef enum acmpInputAPORT4YCH14 = _ACMP_INPUTSEL_POSSEL_APORT4YCH14, acmpInputAPORT4XCH15 = _ACMP_INPUTSEL_POSSEL_APORT4XCH15, acmpInputAPORT4XCH31 = _ACMP_INPUTSEL_POSSEL_APORT4XCH31, +#if defined(_ACMP_INPUTSEL_POSSEL_DACOUT0) acmpInputDACOUT0 = _ACMP_INPUTSEL_POSSEL_DACOUT0, +#endif +#if defined(_ACMP_INPUTSEL_POSSEL_DACOUT1) acmpInputDACOUT1 = _ACMP_INPUTSEL_POSSEL_DACOUT1, +#endif acmpInputVLP = _ACMP_INPUTSEL_POSSEL_VLP, acmpInputVBDIV = _ACMP_INPUTSEL_POSSEL_VBDIV, acmpInputVADIV = _ACMP_INPUTSEL_POSSEL_VADIV, @@ -500,6 +504,31 @@ typedef enum } ACMP_Channel_TypeDef; #endif +#if defined(_ACMP_EXTIFCTRL_MASK) +/** + * ACMP External input select. This type is used to select which APORT that is + * used by an external module like LESENSE when it's taking control over + * the ACMP input. + */ +typedef enum +{ + acmpExternalInputAPORT0X = _ACMP_EXTIFCTRL_APORTSEL_APORT0X, + acmpExternalInputAPORT0Y = _ACMP_EXTIFCTRL_APORTSEL_APORT0Y, + acmpExternalInputAPORT1X = _ACMP_EXTIFCTRL_APORTSEL_APORT1X, + acmpExternalInputAPORT1Y = _ACMP_EXTIFCTRL_APORTSEL_APORT1Y, + acmpExternalInputAPORT1XY = _ACMP_EXTIFCTRL_APORTSEL_APORT1XY, + acmpExternalInputAPORT2X = _ACMP_EXTIFCTRL_APORTSEL_APORT2X, + acmpExternalInputAPORT2Y = _ACMP_EXTIFCTRL_APORTSEL_APORT2Y, + acmpExternalInputAPORT2YX = _ACMP_EXTIFCTRL_APORTSEL_APORT2YX, + acmpExternalInputAPORT3X = _ACMP_EXTIFCTRL_APORTSEL_APORT3X, + acmpExternalInputAPORT3Y = _ACMP_EXTIFCTRL_APORTSEL_APORT3Y, + acmpExternalInputAPORT3XY = _ACMP_EXTIFCTRL_APORTSEL_APORT3XY, + acmpExternalInputAPORT4X = _ACMP_EXTIFCTRL_APORTSEL_APORT4X, + acmpExternalInputAPORT4Y = _ACMP_EXTIFCTRL_APORTSEL_APORT4Y, + acmpExternalInputAPORT4YX = _ACMP_EXTIFCTRL_APORTSEL_APORT4YX, +} ACMP_ExternalInput_Typedef; +#endif + /******************************************************************************* ****************************** STRUCTS ************************************ ******************************************************************************/ @@ -824,6 +853,9 @@ void ACMP_CapsenseChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef channel); void ACMP_ChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef negSel, ACMP_Channel_TypeDef posSel); void ACMP_Disable(ACMP_TypeDef *acmp); void ACMP_Enable(ACMP_TypeDef *acmp); +#if defined(_ACMP_EXTIFCTRL_MASK) +void ACMP_ExternalInputSelect(ACMP_TypeDef *acmp, ACMP_ExternalInput_Typedef aport); +#endif void ACMP_GPIOSetup(ACMP_TypeDef *acmp, uint32_t location, bool enable, bool invert); void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init); void ACMP_Reset(ACMP_TypeDef *acmp); diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h index 0cd23c792a..08bb52614d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_adc.h * @brief Analog to Digital Converter (ADC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -494,25 +494,26 @@ typedef enum adcPosSelAPORT4YCH30 = _ADC_SINGLECTRL_POSSEL_APORT4YCH30, adcPosSelAPORT4XCH31 = _ADC_SINGLECTRL_POSSEL_APORT4XCH31, adcPosSelAVDD = _ADC_SINGLECTRL_POSSEL_AVDD, - adcPosSelBU = _ADC_SINGLECTRL_POSSEL_BU, - adcPosSelAREG = _ADC_SINGLECTRL_POSSEL_AREG, - adcPosSelVREGOUTPA = _ADC_SINGLECTRL_POSSEL_VREGOUTPA, - adcPosSelPDBU = _ADC_SINGLECTRL_POSSEL_PDBU, - adcPosSelIO0 = _ADC_SINGLECTRL_POSSEL_IO0, - adcPosSelIO1 = _ADC_SINGLECTRL_POSSEL_IO1, - adcPosSelVSP = _ADC_SINGLECTRL_POSSEL_VSP, + adcPosSelDVDD = _ADC_SINGLECTRL_POSSEL_AREG, + adcPosSelPAVDD = _ADC_SINGLECTRL_POSSEL_VREGOUTPA, + adcPosSelDECOUPLE = _ADC_SINGLECTRL_POSSEL_PDBU, + adcPosSelIOVDD = _ADC_SINGLECTRL_POSSEL_IO0, adcPosSelOPA2 = _ADC_SINGLECTRL_POSSEL_OPA2, adcPosSelOPA3 = _ADC_SINGLECTRL_POSSEL_OPA3, adcPosSelTEMP = _ADC_SINGLECTRL_POSSEL_TEMP, adcPosSelDAC0OUT0 = _ADC_SINGLECTRL_POSSEL_DAC0OUT0, - adcPosSelTESTP = _ADC_SINGLECTRL_POSSEL_TESTP, - adcPosSelSP1 = _ADC_SINGLECTRL_POSSEL_SP1, - adcPosSelSP2 = _ADC_SINGLECTRL_POSSEL_SP2, adcPosSelDAC0OUT1 = _ADC_SINGLECTRL_POSSEL_DAC0OUT1, adcPosSelSUBLSB = _ADC_SINGLECTRL_POSSEL_SUBLSB, adcPosSelDEFAULT = _ADC_SINGLECTRL_POSSEL_DEFAULT, adcPosSelVSS = _ADC_SINGLECTRL_POSSEL_VSS } ADC_PosSel_TypeDef; + +/* Map legacy or incorrectly named select enums to correct enums. */ +#define adcPosSelIO0 adcPosSelIOVDD +#define adcPosSelVREGOUTPA adcPosSelPAVDD +#define adcPosSelAREG adcPosSelDVDD +#define adcPosSelPDBU adcPosSelDECOUPLE + #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h index b7aee281d9..63c76353f4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_aes.h * @brief Advanced encryption standard (AES) accelerator peripheral API. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h index fb4d2f0d93..d0a2a92259 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_assert.h * @brief Emlib peripheral API "assert" implementation. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h index 1303111ef9..5787aa377c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_burtc.h * @brief Backup Real Time Counter (BURTC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bus.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bus.h index c775e3437a..fc13eaf9f3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bus.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bus.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_bus.h * @brief RAM and peripheral bit-field set and clear API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -30,8 +30,8 @@ * ******************************************************************************/ -#ifndef EM_BUS__ -#define EM_BUS__ +#ifndef EM_BUS_H +#define EM_BUS_H #include "em_device.h" @@ -46,9 +46,9 @@ extern "C" { /***************************************************************************//** * @addtogroup BUS - * @brief BUS RAM and register bit/field read/write API + * @brief BUS register and RAM bit/field read/write API * @details - * API to perform bitbanded and masked accesses to SRAM and peripheral memory. + * API to perform bit-band and field set/clear access to RAM and peripherals. * @{ ******************************************************************************/ @@ -280,7 +280,10 @@ __STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr, * @param[in] mask Peripheral register mask * * @param[in] val Peripheral register value. The value must be shifted to the - correct bit position in the register. + correct bit position in the register corresponding to the field + defined by the mask parameter. The register value must be + contained in the field defined by the mask parameter. This + function is not performing masking of val internally. ******************************************************************************/ __STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, uint32_t mask, @@ -326,4 +329,4 @@ __STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr, } #endif -#endif /* EM_BUS__ */ +#endif /* EM_BUS_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h index 41979c626b..75989934b1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_chip.h * @brief Chip Initialization API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -49,7 +49,7 @@ extern "C" { /***************************************************************************//** * @addtogroup CHIP - * @brief Chip Initialization API + * @brief Chip errata workarounds initialization API * @details * API to initialize chip for errata workarounds. * @{ @@ -69,7 +69,7 @@ extern "C" { *****************************************************************************/ __STATIC_INLINE void CHIP_Init(void) { -#if defined(_EFM32_GECKO_FAMILY) +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) uint32_t rev; SYSTEM_ChipRevision_TypeDef chipRev; volatile uint32_t *reg; @@ -161,26 +161,31 @@ __STATIC_INLINE void CHIP_Init(void) } #endif -#if defined(_EFM32_GIANT_FAMILY) - uint32_t rev; +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) + + /****************************/ + /* Fix for errata CMU_E113. */ + + uint8_t prodRev; SYSTEM_ChipRevision_TypeDef chipRev; - rev = *(volatile uint32_t *)(0x0FE081FC); + prodRev = SYSTEM_GetProdRev(); SYSTEM_ChipRevisionGet(&chipRev); - if (((rev >> 24) > 15) && (chipRev.minor == 3)) + if ((prodRev >= 16) && (chipRev.minor >= 3)) { /* This fixes an issue with the LFXO on high temperatures. */ *(volatile uint32_t*)0x400C80C0 = - ( *(volatile uint32_t*)0x400C80C0 & ~(1<<6) ) | (1<<4); + ( *(volatile uint32_t*)0x400C80C0 & ~(1 << 6) ) | (1 << 4); } #endif -#if defined(_EFM32_HAPPY_FAMILY) - uint32_t rev; - rev = *(volatile uint32_t *)(0x0FE081FC); +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) - if ((rev >> 24) <= 129) + uint8_t prodRev; + prodRev = SYSTEM_GetProdRev(); + + if (prodRev <= 129) { /* This fixes a mistaken internal connection between PC0 and PC4 */ /* This disables an internal pulldown on PC4 */ @@ -190,7 +195,7 @@ __STATIC_INLINE void CHIP_Init(void) } #endif -#if defined(_SILICON_LABS_32B_PLATFORM_2_GEN_1) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) /**************************** * Fixes for errata GPIO_E201 (slewrate) and @@ -244,11 +249,33 @@ __STATIC_INLINE void CHIP_Init(void) } #endif -#if defined(_SILICON_LABS_32B_PLATFORM_2_GEN_2) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) - /* No fixes required. */ + uint8_t prodRev = SYSTEM_GetProdRev(); + /* EM2 current fixes for early samples */ + if (prodRev == 0) + { + *(volatile uint32_t *)(EMU_BASE + 0x190) = 0x0000ADE8UL; + *(volatile uint32_t *)(EMU_BASE + 0x198) |= (0x1 << 2); + *(volatile uint32_t *)(EMU_BASE + 0x190) = 0x0; + } + if (prodRev < 2) + { + *(volatile uint32_t *)(EMU_BASE + 0x164) |= (0x1 << 13); + } + + /* Set optimal LFRCOCTRL VREFUPDATE and enable duty cycling of vref */ + CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~_CMU_LFRCOCTRL_VREFUPDATE_MASK) + | CMU_LFRCOCTRL_VREFUPDATE_64CYCLES + | CMU_LFRCOCTRL_ENVREF; #endif + +#if defined(_EFR_DEVICE) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 84) + MSC->CTRL |= 0x1 << 8; +#endif + + } /** @} (end addtogroup CHIP) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h index 733ae8c022..b049ff9881 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_cmu.h * @brief Clock management unit (CMU) API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -130,10 +130,15 @@ extern "C" { #define CMU_LCDPRE_CLK_BRANCH 19 #define CMU_LCD_CLK_BRANCH 20 #define CMU_LESENSE_CLK_BRANCH 21 +#define CMU_CSEN_LF_CLK_BRANCH 22 #define CMU_CLK_BRANCH_POS 17 #define CMU_CLK_BRANCH_MASK 0x1f +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/* Max clock frequency for VSCALE voltages */ +#define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000 +#endif /** @endcond */ /******************************************************************************* @@ -161,7 +166,7 @@ extern "C" { /** Clock divider configuration */ typedef uint32_t CMU_ClkDiv_TypeDef; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /** Clockprescaler configuration */ typedef uint32_t CMU_ClkPresc_TypeDef; #endif @@ -853,7 +858,7 @@ typedef enum | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFBCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS), + | (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined( CMU_LFBCLKEN0_LEUART1 ) @@ -938,7 +943,10 @@ typedef enum cmuOsc_USHFRCO, /**< USB high frequency RC oscillator */ #endif #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO ) - cmuOsc_ULFRCO /**< Ultra low frequency RC oscillator. */ + cmuOsc_ULFRCO, /**< Ultra low frequency RC oscillator. */ +#endif +#if defined( _CMU_STATUS_PLFRCOENS_MASK ) + cmuOsc_PLFRCO, /**< Precision Low Frequency Oscillator. */ #endif } CMU_Osc_TypeDef; @@ -953,24 +961,27 @@ typedef enum /** Selectable clock sources. */ typedef enum { - cmuSelect_Error, /**< Usage error. */ - cmuSelect_Disabled, /**< Clock selector disabled. */ - cmuSelect_LFXO, /**< Low frequency crystal oscillator. */ - cmuSelect_LFRCO, /**< Low frequency RC oscillator. */ - cmuSelect_HFXO, /**< High frequency crystal oscillator. */ - cmuSelect_HFRCO, /**< High frequency RC oscillator. */ - cmuSelect_HFCLKLE, /**< High frequency LE clock divided by 2 or 4. */ - cmuSelect_AUXHFRCO, /**< Auxilliary clock source can be used for debug clock */ - cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on - Tiny Gecko and for USBC (not used on Gecko) */ + cmuSelect_Error, /**< Usage error. */ + cmuSelect_Disabled, /**< Clock selector disabled. */ + cmuSelect_LFXO, /**< Low frequency crystal oscillator. */ + cmuSelect_LFRCO, /**< Low frequency RC oscillator. */ + cmuSelect_HFXO, /**< High frequency crystal oscillator. */ + cmuSelect_HFRCO, /**< High frequency RC oscillator. */ + cmuSelect_HFCLKLE, /**< High frequency LE clock divided by 2 or 4. */ + cmuSelect_AUXHFRCO, /**< Auxilliary clock source can be used for debug clock */ + cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on + Tiny Gecko and for USBC (not used on Gecko) */ #if defined( CMU_STATUS_USHFRCOENS ) - cmuSelect_USHFRCO, /**< USB high frequency RC oscillator */ + cmuSelect_USHFRCO, /**< USB high frequency RC oscillator */ #endif #if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 ) - cmuSelect_USHFRCODIV2,/**< USB high frequency RC oscillator */ + cmuSelect_USHFRCODIV2, /**< USB high frequency RC oscillator */ #endif #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO ) - cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */ + cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */ +#endif +#if defined( _CMU_STATUS_PLFRCOENS_MASK ) + cmuSelect_PLFRCO, /**< Precision Low Frequency Oscillator. */ #endif } CMU_Select_TypeDef; @@ -1192,7 +1203,7 @@ CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock); void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div); uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock); -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, uint32_t presc); uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock); #endif @@ -1441,7 +1452,7 @@ __STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2) } -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /***************************************************************************//** * @brief * Convert prescaler dividend to logarithmic value. Only works for even diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h index 03d00b53eb..e22df15fa5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_common.h * @brief General purpose utilities. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -107,6 +107,9 @@ extern "C" { /** MDK-ARM compiler: Macro for handling weak symbols. */ #define SL_WEAK __attribute__ ((weak)) +/** MDK-ARM compiler: Macro for handling non-returning functions. */ +#define SL_NORETURN __attribute__ ((noreturn)) + /** MDK-ARM compiler: Macro for handling section placement */ #define SL_ATTRIBUTE_SECTION(X) __attribute__ ((section(X))) #endif @@ -118,6 +121,9 @@ extern "C" { /** @brief IAR Embedded Workbench: Macros for handling weak symbols. */ #define SL_WEAK __weak +/** @brief IAR Embedded Workbench: Macro for handling non-returning functions. */ +#define SL_NORETURN __noreturn + /** IAR Embedded Workbench: Macro for handling section placement */ #define SL_ATTRIBUTE_SECTION(X) @ X #endif @@ -164,6 +170,9 @@ extern "C" { /** @brief Macro for defining a weak symbol. */ #define SL_WEAK __attribute__ ((weak)) +/** @brief Macro for handling non-returning functions. */ +#define SL_NORETURN __attribute__ ((noreturn)) + /** Macro for placing a variable in a section. * @n Use this macro after the variable definition, before the = or ;. * @n X denotes the section to place the variable in. @@ -174,13 +183,13 @@ extern "C" { /***************************************************************************//** * @brief - * Count trailing number of zero's. Use CLZ instruction if available. + * Count trailing number of zeros. Use CLZ instruction if available. * * @param[in] value * Data value to check for number of trailing zero bits. * * @return - * Number of trailing zero's in value. + * Number of trailing zeros in value. ******************************************************************************/ __STATIC_INLINE uint32_t SL_CTZ(uint32_t value) { @@ -194,31 +203,14 @@ __STATIC_INLINE uint32_t SL_CTZ(uint32_t value) #endif } -/***************************************************************************//** - * @brief - * Count trailing number of zero's. Use CLZ instruction if available. - * - * @deprecated - * Deprecated function. New code should use @ref SL_CTZ(). - * @param[in] value - * Data value to check for number of trailing zero bits. - * - * @return - * Number of trailing zero's in value. - ******************************************************************************/ +/* Deprecated function. New code should use @ref SL_CTZ. */ __STATIC_INLINE uint32_t EFM32_CTZ(uint32_t value) { -#if (__CORTEX_M >= 3) - return __CLZ(__RBIT(value)); - -#else - uint32_t zeros; - for(zeros=0; (zeros<32) && ((value&0x1) == 0); zeros++, value>>=1); - return zeros; -#endif + return SL_CTZ(value); } + /** @} (end addtogroup COMMON) */ /** @} (end addtogroup emlib) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_core.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_core.h index c30af03047..45131f3fba 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_core.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_core.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_core.h * @brief Core interrupt handling API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cryotimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cryotimer.h index 4ae47098bd..43403b81e8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cryotimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cryotimer.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_cryotimer.h * @brief Ultra Low Energy Timer/Counter (CRYOTIMER) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crypto.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crypto.h index 3b44aa1585..977f9da95a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crypto.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crypto.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_crypto.h * @brief Cryptography accelerator peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_csen.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_csen.h new file mode 100644 index 0000000000..aacf4cbc25 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_csen.h @@ -0,0 +1,778 @@ +/***************************************************************************//** + * @file em_csen.h + * @brief Capacitive Sense Module (CSEN) peripheral API + * @version 5.1.2 + ******************************************************************************* + * @section License + * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************* + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + +#ifndef EM_CSEN_H +#define EM_CSEN_H + +#include "em_device.h" +#if defined( CSEN_COUNT ) && ( CSEN_COUNT > 0 ) + +#include +#include "em_bus.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup CSEN + * @brief Capacitive Sense (CSEN) Peripheral API + * + * @details + * This module provides functions for controlling the capacitive sense + * peripheral of Silicon Labs 32-bit MCUs and SoCs. The CSEN includes a + * capacitance-to-digital circuit that measures capacitance on selected + * inputs. Measurements are performed using either a successive approximation + * register (SAR) or a delta modulator (DM) analog to digital converter. + * + * The CSEN can be configured to measure capacitance on a single port pin + * or to automatically measure multiple port pins in succession using scan + * mode. Also several port pins can be shorted together to measure the + * combined capacitance. + * + * The CSEN includes an accumulator which can be configured to average + * multiple conversions on the selected input. Additionally, an exponential + * moving average (EMA) calculator is included to provide data smoothing. + * A comparator is also included and can be used to terminate a continuous + * conversion when the configured threshold condition is met. + * + * The following example shows how to intialize and start a single + * conversion on one input: + * + * @include em_csen_single.c + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Comparator Mode. Selects the operation of the digital comparator. */ +typedef enum +{ + /** Comparator is disabled. */ + csenCmpModeDisabled = 0, + + /** Comparator trips when the result is greater than the threshold. */ + csenCmpModeGreater = CSEN_CTRL_CMPEN | CSEN_CTRL_CMPPOL_GT, + + /** Comparator trips when the result is less or equal to the threshold. */ + csenCmpModeLessOrEqual = CSEN_CTRL_CMPEN | CSEN_CTRL_CMPPOL_LTE, + + /** Comparator trips when the EMA is within the threshold window. */ + csenCmpModeEMAWindow = CSEN_CTRL_EMACMPEN, +} CSEN_CmpMode_TypeDef; + + +/** Converter Select. Determines the converter operational mode. */ +typedef enum +{ + /** Successive Approximation (SAR) converter. */ + csenConvSelSAR = CSEN_CTRL_CONVSEL_SAR, + + /** Successive Approximation (SAR) converter with low freq attenuation. */ + csenConvSelSARChop = CSEN_CTRL_CONVSEL_SAR | CSEN_CTRL_CHOPEN_ENABLE, + + /** Delta Modulation (DM) converter. */ + csenConvSelDM = CSEN_CTRL_CONVSEL_DM, + + /** Delta Modulation (DM) converter with low frequency attenuation. */ + csenConvSelDMChop = CSEN_CTRL_CONVSEL_DM | CSEN_CTRL_CHOPEN_ENABLE, +} CSEN_ConvSel_TypeDef; + + +/** Sample Mode. Determines how inputs are sampled for a conversion. */ +typedef enum +{ + /** Convert multiple inputs shorted together and stop. */ + csenSampleModeBonded = CSEN_CTRL_CM_SGL | CSEN_CTRL_MCEN_ENABLE, + + /** Convert one input and stop. */ + csenSampleModeSingle = CSEN_CTRL_CM_SGL, + + /** Convert multiple inputs one at a time and stop. */ + csenSampleModeScan = CSEN_CTRL_CM_SCAN, + + /** Continuously convert multiple inputs shorted together. */ + csenSampleModeContBonded = CSEN_CTRL_CM_CONTSGL | CSEN_CTRL_MCEN_ENABLE, + + /** Continuously convert one input. */ + csenSampleModeContSingle = CSEN_CTRL_CM_CONTSGL, + + /** Continuously convert multiple inputs one at a time. */ + csenSampleModeContScan = CSEN_CTRL_CM_CONTSCAN, +} CSEN_SampleMode_TypeDef; + + +/** Start Trigger Select. */ +typedef enum +{ + csenTrigSelPRS = _CSEN_CTRL_STM_PRS, /**< PRS system. */ + csenTrigSelTimer = _CSEN_CTRL_STM_TIMER, /**< CSEN PC timer. */ + csenTrigSelStart = _CSEN_CTRL_STM_START, /**< Start bit. */ +} CSEN_TrigSel_TypeDef; + + +/** Accumulator Mode Select. */ +typedef enum +{ + csenAccMode1 = _CSEN_CTRL_ACU_ACC1, /**< Accumulate 1 sample. */ + csenAccMode2 = _CSEN_CTRL_ACU_ACC2, /**< Accumulate 2 samples. */ + csenAccMode4 = _CSEN_CTRL_ACU_ACC4, /**< Accumulate 4 samples. */ + csenAccMode8 = _CSEN_CTRL_ACU_ACC8, /**< Accumulate 8 samples. */ + csenAccMode16 = _CSEN_CTRL_ACU_ACC16, /**< Accumulate 16 samples. */ + csenAccMode32 = _CSEN_CTRL_ACU_ACC32, /**< Accumulate 32 samples. */ + csenAccMode64 = _CSEN_CTRL_ACU_ACC64, /**< Accumulate 64 samples. */ +} CSEN_AccMode_TypeDef; + + +/** Successive Approximation (SAR) Conversion Resolution. */ +typedef enum +{ + csenSARRes10 = _CSEN_CTRL_SARCR_CLK10, /**< 10-bit resolution. */ + csenSARRes12 = _CSEN_CTRL_SARCR_CLK12, /**< 12-bit resolution. */ + csenSARRes14 = _CSEN_CTRL_SARCR_CLK14, /**< 14-bit resolution. */ + csenSARRes16 = _CSEN_CTRL_SARCR_CLK16, /**< 16-bit resolution. */ +} CSEN_SARRes_TypeDef; + + +/** Delta Modulator (DM) Conversion Resolution. */ +typedef enum +{ + csenDMRes10 = _CSEN_DMCFG_CRMODE_DM10, /**< 10-bit resolution. */ + csenDMRes12 = _CSEN_DMCFG_CRMODE_DM12, /**< 12-bit resolution. */ + csenDMRes14 = _CSEN_DMCFG_CRMODE_DM14, /**< 14-bit resolution. */ + csenDMRes16 = _CSEN_DMCFG_CRMODE_DM16, /**< 16-bit resolution. */ +} CSEN_DMRes_TypeDef; + + +/** Period counter clock pre-scaler. See the reference manual for source clock + * information. */ +typedef enum +{ + csenPCPrescaleDiv1 = _CSEN_TIMCTRL_PCPRESC_DIV1, /**< Divide by 1. */ + csenPCPrescaleDiv2 = _CSEN_TIMCTRL_PCPRESC_DIV2, /**< Divide by 2. */ + csenPCPrescaleDiv4 = _CSEN_TIMCTRL_PCPRESC_DIV4, /**< Divide by 4. */ + csenPCPrescaleDiv8 = _CSEN_TIMCTRL_PCPRESC_DIV8, /**< Divide by 8. */ + csenPCPrescaleDiv16 = _CSEN_TIMCTRL_PCPRESC_DIV16, /**< Divide by 16. */ + csenPCPrescaleDiv32 = _CSEN_TIMCTRL_PCPRESC_DIV32, /**< Divide by 32. */ + csenPCPrescaleDiv64 = _CSEN_TIMCTRL_PCPRESC_DIV64, /**< Divide by 64. */ + csenPCPrescaleDiv128 = _CSEN_TIMCTRL_PCPRESC_DIV128, /**< Divide by 128. */ +} CSEN_PCPrescale_TypeDef; + + +/** Exponential Moving Average sample weight. */ +typedef enum +{ + csenEMASampleW1 = _CSEN_EMACTRL_EMASAMPLE_W1, /**< Weight 1. */ + csenEMASampleW2 = _CSEN_EMACTRL_EMASAMPLE_W2, /**< Weight 2. */ + csenEMASampleW4 = _CSEN_EMACTRL_EMASAMPLE_W4, /**< Weight 4. */ + csenEMASampleW8 = _CSEN_EMACTRL_EMASAMPLE_W8, /**< Weight 8. */ + csenEMASampleW16 = _CSEN_EMACTRL_EMASAMPLE_W16, /**< Weight 16. */ + csenEMASampleW32 = _CSEN_EMACTRL_EMASAMPLE_W32, /**< Weight 32. */ + csenEMASampleW64 = _CSEN_EMACTRL_EMASAMPLE_W64, /**< Weight 64. */ +} CSEN_EMASample_TypeDef; + + +/** Reset Phase Timing Select (units are microseconds). */ +typedef enum +{ + csenResetPhaseSel0 = 0, /**< Reset phase time = 0.75 usec. */ + csenResetPhaseSel1 = 1, /**< Reset phase time = 1.00 usec. */ + csenResetPhaseSel2 = 2, /**< Reset phase time = 1.20 usec. */ + csenResetPhaseSel3 = 3, /**< Reset phase time = 1.50 usec. */ + csenResetPhaseSel4 = 4, /**< Reset phase time = 2.00 usec. */ + csenResetPhaseSel5 = 5, /**< Reset phase time = 3.00 usec. */ + csenResetPhaseSel6 = 6, /**< Reset phase time = 6.00 usec. */ + csenResetPhaseSel7 = 7, /**< Reset phase time = 12.0 usec. */ +} CSEN_ResetPhaseSel_TypeDef; + + +/** Drive Strength Select. Scales the output current. */ +typedef enum +{ + csenDriveSelFull = 0, /**< Drive strength = fully on. */ + csenDriveSel1 = 1, /**< Drive strength = 1/8 full scale. */ + csenDriveSel2 = 2, /**< Drive strength = 1/4 full scale. */ + csenDriveSel3 = 3, /**< Drive strength = 3/8 full scale. */ + csenDriveSel4 = 4, /**< Drive strength = 1/2 full scale. */ + csenDriveSel5 = 5, /**< Drive strength = 5/8 full scale. */ + csenDriveSel6 = 6, /**< Drive strength = 3/4 full scale. */ + csenDriveSel7 = 7, /**< Drive strength = 7/8 full scale. */ +} CSEN_DriveSel_TypeDef; + + +/** Gain Select. See reference manual for information on each setting. */ +typedef enum +{ + csenGainSel1X = 0, /**< Gain = 1x. */ + csenGainSel2X = 1, /**< Gain = 2x. */ + csenGainSel3X = 2, /**< Gain = 3x. */ + csenGainSel4X = 3, /**< Gain = 4x. */ + csenGainSel5X = 4, /**< Gain = 5x. */ + csenGainSel6X = 5, /**< Gain = 6x. */ + csenGainSel7X = 6, /**< Gain = 7x. */ + csenGainSel8X = 7, /**< Gain = 8x. */ +} CSEN_GainSel_TypeDef; + + +/** Peripheral Reflex System signal used to trigger conversion. */ +typedef enum +{ + csenPRSSELCh0 = _CSEN_PRSSEL_PRSSEL_PRSCH0, /**< PRS channel 0. */ + csenPRSSELCh1 = _CSEN_PRSSEL_PRSSEL_PRSCH1, /**< PRS channel 1. */ + csenPRSSELCh2 = _CSEN_PRSSEL_PRSSEL_PRSCH2, /**< PRS channel 2. */ + csenPRSSELCh3 = _CSEN_PRSSEL_PRSSEL_PRSCH3, /**< PRS channel 3. */ + csenPRSSELCh4 = _CSEN_PRSSEL_PRSSEL_PRSCH4, /**< PRS channel 4. */ + csenPRSSELCh5 = _CSEN_PRSSEL_PRSSEL_PRSCH5, /**< PRS channel 5. */ + csenPRSSELCh6 = _CSEN_PRSSEL_PRSSEL_PRSCH6, /**< PRS channel 6. */ + csenPRSSELCh7 = _CSEN_PRSSEL_PRSSEL_PRSCH7, /**< PRS channel 7. */ + csenPRSSELCh8 = _CSEN_PRSSEL_PRSSEL_PRSCH8, /**< PRS channel 8. */ + csenPRSSELCh9 = _CSEN_PRSSEL_PRSSEL_PRSCH9, /**< PRS channel 9. */ + csenPRSSELCh10 = _CSEN_PRSSEL_PRSSEL_PRSCH10, /**< PRS channel 10. */ + csenPRSSELCh11 = _CSEN_PRSSEL_PRSSEL_PRSCH11, /**< PRS channel 11. */ +} CSEN_PRSSel_TypeDef; + + +/** APORT channel to CSEN input selection. */ +typedef enum +{ + csenInputSelDefault = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT, + csenInputSelAPORT1CH0TO7 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7, + csenInputSelAPORT1CH8TO15 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15, + csenInputSelAPORT1CH16TO23 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23, + csenInputSelAPORT1CH24TO31 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31, + csenInputSelAPORT3CH0TO7 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7, + csenInputSelAPORT3CH8TO15 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15, + csenInputSelAPORT3CH16TO23 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23, + csenInputSelAPORT3CH24TO31 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31, +} CSEN_InputSel_TypeDef; + + +/** APORT channel to CSEN single input selection. */ +typedef enum +{ + csenSingleSelDefault = _CSEN_SINGLECTRL_SINGLESEL_DEFAULT, + csenSingleSelAPORT1XCH0 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0, + csenSingleSelAPORT1YCH1 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1, + csenSingleSelAPORT1XCH2 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2, + csenSingleSelAPORT1YCH3 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3, + csenSingleSelAPORT1XCH4 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4, + csenSingleSelAPORT1YCH5 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5, + csenSingleSelAPORT1XCH6 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6, + csenSingleSelAPORT1YCH7 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7, + csenSingleSelAPORT1XCH8 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8, + csenSingleSelAPORT1YCH9 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9, + csenSingleSelAPORT1XCH10 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10, + csenSingleSelAPORT1YCH11 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11, + csenSingleSelAPORT1XCH12 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12, + csenSingleSelAPORT1YCH13 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13, + csenSingleSelAPORT1XCH14 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14, + csenSingleSelAPORT1YCH15 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15, + csenSingleSelAPORT1XCH16 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16, + csenSingleSelAPORT1YCH17 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17, + csenSingleSelAPORT1XCH18 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18, + csenSingleSelAPORT1YCH19 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19, + csenSingleSelAPORT1XCH20 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20, + csenSingleSelAPORT1YCH21 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21, + csenSingleSelAPORT1XCH22 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22, + csenSingleSelAPORT1YCH23 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23, + csenSingleSelAPORT1XCH24 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24, + csenSingleSelAPORT1YCH25 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25, + csenSingleSelAPORT1XCH26 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26, + csenSingleSelAPORT1YCH27 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27, + csenSingleSelAPORT1XCH28 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28, + csenSingleSelAPORT1YCH29 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29, + csenSingleSelAPORT1XCH30 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30, + csenSingleSelAPORT1YCH31 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31, + csenSingleSelAPORT3XCH0 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0, + csenSingleSelAPORT3YCH1 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1, + csenSingleSelAPORT3XCH2 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2, + csenSingleSelAPORT3YCH3 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3, + csenSingleSelAPORT3XCH4 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4, + csenSingleSelAPORT3YCH5 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5, + csenSingleSelAPORT3XCH6 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6, + csenSingleSelAPORT3YCH7 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7, + csenSingleSelAPORT3XCH8 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8, + csenSingleSelAPORT3YCH9 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9, + csenSingleSelAPORT3XCH10 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10, + csenSingleSelAPORT3YCH11 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11, + csenSingleSelAPORT3XCH12 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12, + csenSingleSelAPORT3YCH13 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13, + csenSingleSelAPORT3XCH14 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14, + csenSingleSelAPORT3YCH15 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15, + csenSingleSelAPORT3XCH16 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16, + csenSingleSelAPORT3YCH17 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17, + csenSingleSelAPORT3XCH18 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18, + csenSingleSelAPORT3YCH19 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19, + csenSingleSelAPORT3XCH20 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20, + csenSingleSelAPORT3YCH21 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21, + csenSingleSelAPORT3XCH22 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22, + csenSingleSelAPORT3YCH23 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23, + csenSingleSelAPORT3XCH24 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24, + csenSingleSelAPORT3YCH25 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25, + csenSingleSelAPORT3XCH26 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26, + csenSingleSelAPORT3YCH27 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27, + csenSingleSelAPORT3XCH28 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28, + csenSingleSelAPORT3YCH29 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29, + csenSingleSelAPORT3XCH30 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30, + csenSingleSelAPORT3YCH31 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31, +} CSEN_SingleSel_TypeDef; + + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** CSEN init structure, common for all measurement modes. */ +typedef struct +{ + /** Requests system charge pump high accuracy mode. */ + bool cpAccuracyHi; + + /** Disables external kelvin connection and senses capacitor locally. */ + bool localSense; + + /** Keeps the converter warm allowing continuous conversions. */ + bool keepWarm; + + /** Converter warmup time is warmUpCount + 3 converter clock cycles. */ + uint8_t warmUpCount; + + /** Period counter reload value. */ + uint8_t pcReload; + + /** Period counter pre-scaler. */ + CSEN_PCPrescale_TypeDef pcPrescale; + + /** Peripheral reflex system trigger selection. */ + CSEN_PRSSel_TypeDef prsSel; + + /** CSEN input to APORT channel mapping. */ + CSEN_InputSel_TypeDef input0To7; + CSEN_InputSel_TypeDef input8To15; + CSEN_InputSel_TypeDef input16To23; + CSEN_InputSel_TypeDef input24To31; + CSEN_InputSel_TypeDef input32To39; + CSEN_InputSel_TypeDef input40To47; + CSEN_InputSel_TypeDef input48To55; + CSEN_InputSel_TypeDef input56To63; +} CSEN_Init_TypeDef; + +#define CSEN_INIT_DEFAULT \ +{ \ + false, /* Charge pump low accuracy mode. */ \ + false, /* Use external kelvin connection. */ \ + false, /* Disable keep warm. */ \ + 0, /* 0+3 cycle warmup time. */ \ + 0, /* Period counter reload. */ \ + csenPCPrescaleDiv1, /* Period counter prescale. */ \ + csenPRSSELCh0, /* PRS channel 0. */ \ + csenInputSelAPORT1CH0TO7, /* input0To7 -> aport1ch0to7 */ \ + csenInputSelAPORT1CH8TO15, /* input8To15 -> aport1ch8to15 */ \ + csenInputSelAPORT1CH16TO23, /* input16To23 -> aport1ch16to23 */ \ + csenInputSelAPORT1CH24TO31, /* input24To31 -> aport1ch24to31 */ \ + csenInputSelAPORT3CH0TO7, /* input32To39 -> aport3ch0to7 */ \ + csenInputSelAPORT3CH8TO15, /* input40To47 -> aport3ch8to15 */ \ + csenInputSelAPORT3CH16TO23, /* input48To55 -> aport3ch16to23 */ \ + csenInputSelAPORT3CH24TO31, /* input56To63 -> aport3ch24to31 */ \ +} + + +/** Measurement mode init structure. */ +typedef struct +{ + /** Selects the conversion sample mode. */ + CSEN_SampleMode_TypeDef sampleMode; + + /** Selects the conversion trigger source. */ + CSEN_TrigSel_TypeDef trigSel; + + /** Enables DMA operation. */ + bool enableDma; + + /** Disables dividing the accumulated result. */ + bool sumOnly; + + /** Selects the number of samples to accumulate per conversion. */ + CSEN_AccMode_TypeDef accMode; + + /** Selects the Exponential Moving Average sample weighting. */ + CSEN_EMASample_TypeDef emaSample; + + /** Enables the comparator and selects the comparison type. */ + CSEN_CmpMode_TypeDef cmpMode; + + /** Comparator threshold value. Meaning depends on @p cmpMode. */ + uint16_t cmpThr; + + /** Selects an APORT channel for a single conversion. */ + CSEN_SingleSel_TypeDef singleSel; + + /** + * Mask selects inputs 0 to 31. Effect depends on @p sampleMode. If sample + * mode is bonded, then mask selects inputs to short together. If sample + * mode is scan, then mask selects which inputs will be scanned. If sample + * mode is single and auto-ground is on (@p autoGnd is true), mask selects + * which pins are grounded. + */ + uint32_t inputMask0; + + /** Mask selects inputs 32 to 63. See @p inputMask0 for more information. */ + uint32_t inputMask1; + + /** Ground inactive inputs during a conversion. */ + bool autoGnd; + + /** Selects the converter type. */ + CSEN_ConvSel_TypeDef convSel; + + /** Selects the Successive Approximation (SAR) converter resolution. */ + CSEN_SARRes_TypeDef sarRes; + + /** Selects the Delta Modulation (DM) converter resolution. */ + CSEN_DMRes_TypeDef dmRes; + + /** Sets the number of DM iterations (comparisons) per cycle. Only applies + * to the Delta Modulation converter. */ + uint8_t dmIterPerCycle; + + /** Sets number of DM converter cycles. Only applies to the + * Delta Modulation converter. */ + uint8_t dmCycles; + + /** Sets the DM converter initial delta value. Only applies to the + * Delta Modulation converter. */ + uint8_t dmDelta; + + /** Disable DM automatic delta size reduction per cycle. Only applies to the + * Delta Modulation converter. */ + bool dmFixedDelta; + + /** Selects the reset phase timing. Most measurements should use the default + * value. See reference manual for details on when to adjust. */ + CSEN_ResetPhaseSel_TypeDef resetPhase; + + /** Selects the output drive strength. Most measurements should use the + * default value. See reference manual for details on when to adjust. */ + CSEN_DriveSel_TypeDef driveSel; + + /** Selects the converter gain. */ + CSEN_GainSel_TypeDef gainSel; +} CSEN_InitMode_TypeDef; + +#define CSEN_INITMODE_DEFAULT \ +{ \ + csenSampleModeSingle, /* Sample one input and stop. */ \ + csenTrigSelStart, /* Use start bit to trigger. */ \ + false, /* Disable DMA. */ \ + false, /* Average the accumulated result. */ \ + csenAccMode1, /* Accumulate 1 sample. */ \ + csenEMASampleW1, /* Disable the EMA. */ \ + csenCmpModeDisabled, /* Disable the comparator. */ \ + 0, /* Comparator threshold not used. */ \ + csenSingleSelDefault, /* Disconnect the single input. */ \ + 0, /* Disable inputs 0 to 31. */ \ + 0, /* Disable inputs 32 to 63. */ \ + false, /* Do not ground inactive inputs. */ \ + csenConvSelSAR, /* Use the SAR converter. */ \ + csenSARRes10, /* Set SAR resolution to 10 bits. */ \ + csenDMRes10, /* Set DM resolution to 10 bits. */ \ + 0, /* Set DM conv/cycle to default. */ \ + 0, /* Set DM cycles to default. */ \ + 0, /* Set DM initial delta to default. */ \ + false, /* Use DM auto delta reduction. */ \ + csenResetPhaseSel0, /* Use shortest reset phase time. */ \ + csenDriveSelFull, /* Use full output current. */ \ + csenGainSel8X, /* Use highest converter gain. */ \ +} + + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get last conversion result. + * + * @note + * Check conversion busy flag before calling this function. In addition, + * the result width and format depend on the parameters passed to the + * @ref CSEN_InitMode() function. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @return + * Result data from last conversion. + ******************************************************************************/ +__STATIC_INLINE uint32_t CSEN_DataGet(CSEN_TypeDef *csen) +{ + return csen->DATA; +} + +/***************************************************************************//** + * @brief + * Get last exponential moving average. + * + * @note + * Confirm CSEN is idle before calling this function. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @return + * Exponential moving average from last conversion. + ******************************************************************************/ +__STATIC_INLINE uint32_t CSEN_EMAGet(CSEN_TypeDef *csen) +{ + return (csen->EMA & _CSEN_EMA_EMA_MASK); +} + +/***************************************************************************//** + * @brief + * Set exponential moving average initial value. + * + * @note + * Call this function before starting a conversion. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] ema + * Initial value for the exponential moving average. + ******************************************************************************/ +__STATIC_INLINE void CSEN_EMASet(CSEN_TypeDef *csen, uint32_t ema) +{ + csen->EMA = ema & _CSEN_EMA_EMA_MASK; +} + +/***************************************************************************//** + * @brief + * Disables the CSEN. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void CSEN_Disable(CSEN_TypeDef *csen) +{ + BUS_RegBitWrite(&csen->CTRL, _CSEN_CTRL_EN_SHIFT, 0); +} + +/***************************************************************************//** + * @brief + * Enables the CSEN. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void CSEN_Enable(CSEN_TypeDef *csen) +{ + BUS_RegBitWrite(&csen->CTRL, _CSEN_CTRL_EN_SHIFT, 1); +} + +void CSEN_DMBaselineSet(CSEN_TypeDef *csen, uint32_t up, uint32_t down); +void CSEN_Init(CSEN_TypeDef *csen, const CSEN_Init_TypeDef *init); +void CSEN_InitMode(CSEN_TypeDef *csen, const CSEN_InitMode_TypeDef *init); +void CSEN_Reset(CSEN_TypeDef *csen); + + +/***************************************************************************//** + * @brief + * Clear one or more pending CSEN interrupts. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] flags + * Pending CSEN interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the CSEN module (CSEN_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void CSEN_IntClear(CSEN_TypeDef *csen, uint32_t flags) +{ + csen->IFC = flags; +} + + +/***************************************************************************//** + * @brief + * Disable one or more CSEN interrupts. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] flags + * CSEN interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the CSEN module (CSEN_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void CSEN_IntDisable(CSEN_TypeDef *csen, uint32_t flags) +{ + csen->IEN &= ~flags; +} + + +/***************************************************************************//** + * @brief + * Enable one or more CSEN interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using CSEN_IntClear() prior to enabling + * if such a pending interrupt should be ignored. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] flags + * CSEN interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the CSEN module (CSEN_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void CSEN_IntEnable(CSEN_TypeDef *csen, uint32_t flags) +{ + csen->IEN |= flags; +} + + +/***************************************************************************//** + * @brief + * Get pending CSEN interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @return + * CSEN interrupt sources pending. A bitwise logic OR combination of valid + * interrupt flags for the CSEN module (CSEN_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t CSEN_IntGet(CSEN_TypeDef *csen) +{ + return csen->IF; +} + + +/***************************************************************************//** + * @brief + * Get enabled and pending CSEN interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled CSEN interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in CSENx_IEN_nnn + * register (CSENx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the CSEN module + * (CSENx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t CSEN_IntGetEnabled(CSEN_TypeDef *csen) +{ + uint32_t ien; + + /* Store CSENx->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + ien = csen->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return csen->IF & ien; +} + + +/***************************************************************************//** + * @brief + * Set one or more pending CSEN interrupts from SW. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] flags + * CSEN interrupt sources to set to pending. Use a bitwise logic OR combination + * of valid interrupt flags for the CSEN module (CSEN_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void CSEN_IntSet(CSEN_TypeDef *csen, uint32_t flags) +{ + csen->IFS = flags; +} + + +/***************************************************************************//** + * @brief + * Return CSEN conversion busy status. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @return + * True if CSEN conversion is in progress. + ******************************************************************************/ +__STATIC_INLINE bool CSEN_IsBusy(CSEN_TypeDef *csen) +{ + return (bool)(csen->STATUS & _CSEN_STATUS_CSENBUSY_MASK); +} + + +/***************************************************************************//** + * @brief + * Start scan sequence and/or single conversion. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void CSEN_Start(CSEN_TypeDef *csen) +{ + csen->CMD = CSEN_CMD_START; +} + + +/** @} (end addtogroup CSEN) */ +/** @} (end addtogroup emlib) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(CSEN_COUNT) && (CSEN_COUNT > 0) */ +#endif /* EM_CSEN_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h index 4218d61138..e9df3b6051 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dac.h * @brief Digital to Analog Converter (DAC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h index 0baca2a731..bc96fc93ca 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dbg.h * @brief Debug (DBG) API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h index 5d557684f8..c79f23fbfc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dma.h * @brief Direct memory access (DMA) API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -360,21 +360,21 @@ typedef struct void DMA_ActivateAuto(unsigned int channel, bool primary, void *dst, - void *src, + const void *src, unsigned int nMinus1); void DMA_ActivateBasic(unsigned int channel, bool primary, bool useBurst, void *dst, - void *src, + const void *src, unsigned int nMinus1); void DMA_ActivatePingPong(unsigned int channel, bool useBurst, void *primDst, - void *primSrc, + const void *primSrc, unsigned int primNMinus1, void *altDst, - void *altSrc, + const void *altSrc, unsigned int altNMinus1); void DMA_ActivateScatterGather(unsigned int channel, bool useBurst, @@ -446,7 +446,7 @@ void DMA_RefreshPingPong(unsigned int channel, bool primary, bool useBurst, void *dst, - void *src, + const void *src, unsigned int nMinus1, bool last); void DMA_Reset(void); diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h index 8515bac98c..86c772a09e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_ebi.h * @brief External Bus Iterface (EBI) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h index 0594f3cfd0..49ace57649 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_emu.h * @brief Energy management unit (EMU) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -151,15 +151,13 @@ typedef enum } EMU_EM4PinRetention_TypeDef; #endif - -#if defined( _EMU_PWRCFG_MASK ) -/** Power configurations */ +/** Power configurations. DCDC-to-DVDD is currently the only supported mode. */ typedef enum { /** DCDC is connected to DVDD */ - emuPowerConfig_DcdcToDvdd = EMU_PWRCFG_PWRCFG_DCDCTODVDD, + emuPowerConfig_DcdcToDvdd, } EMU_PowerConfig_TypeDef; -#endif + #if defined( _EMU_DCDCCTRL_MASK ) /** DCDC operating modes */ @@ -176,6 +174,19 @@ typedef enum } EMU_DcdcMode_TypeDef; #endif +#if defined( _EMU_DCDCCTRL_MASK ) +/** DCDC conduction modes */ +typedef enum +{ + /** DCDC Low-Noise Continuous Conduction Mode (CCM). EFR32 interference minimization + features are available in this mode. */ + emuDcdcConductionMode_ContinuousLN, + /** DCDC Low-Noise Discontinuous Conduction Mode (DCM). This mode should be used for EFM32 or + when the EFR32 radio is not enabled. */ + emuDcdcConductionMode_DiscontinuousLN, +} EMU_DcdcConductionMode_TypeDef; +#endif + #if defined( _EMU_PWRCTRL_MASK ) /** DCDC to DVDD mode analog peripheral power supply select */ typedef enum @@ -194,7 +205,7 @@ typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef; /** High efficiency mode. EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */ #define emuDcdcLnHighEfficiency -1 -/** Deprecated. Fast transient response mode. Specify a reverse current limit instead. */ +/** Default reverse current for fast transient response mode (low noise). */ #define emuDcdcLnFastTransient 160 #endif @@ -258,7 +269,7 @@ typedef enum } EMU_VmonChannel_TypeDef; #endif /* EMU_STATUS_VMONRDY */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) /** Bias mode configurations */ typedef enum { @@ -268,56 +279,184 @@ typedef enum } EMU_BiasMode_TypeDef; #endif +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/** Supported EM0/1 Voltage Scaling Levels */ +typedef enum +{ + /** High-performance voltage level. HF clock can be set to any frequency. */ + emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2, + /** Low-power optimized voltage level. The HF clock must be limited + to @ref CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX Hz at this voltage. + EM0/1 voltage scaling is applied when the core clock frequency is + changed from @ref CMU or when calling @ref EMU_EM01Init() when the HF + clock is already below the limit. */ + emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE0, +} EMU_VScaleEM01_TypeDef; +#endif + +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) +/** Supported EM2/3 Voltage Scaling Levels */ +typedef enum +{ + /** Fast-wakeup voltage level. */ + emuVScaleEM23_FastWakeup = _EMU_CTRL_EM23VSCALE_VSCALE2, + /** Low-power optimized voltage level. Using this voltage level in EM2 and 3 + adds 20-25us to wakeup time if the EM0 and 1 voltage must be scaled + up to @ref emuVScaleEM01_HighPerformance on EM2 or 3 exit. */ + emuVScaleEM23_LowPower = _EMU_CTRL_EM23VSCALE_VSCALE0, +} EMU_VScaleEM23_TypeDef; +#endif + +#if defined( _EMU_CTRL_EM4HVSCALE_MASK ) +/** Supported EM4H Voltage Scaling Levels */ +typedef enum +{ + /** Fast-wakeup voltage level. */ + emuVScaleEM4H_FastWakeup = _EMU_CTRL_EM4HVSCALE_VSCALE2, + /** Low-power optimized voltage level. Using this voltage level in EM4H + adds 20-25us to wakeup time if the EM0 and 1 voltage must be scaled + up to @ref emuVScaleEM01_HighPerformance on EM4H exit. */ + emuVScaleEM4H_LowPower = _EMU_CTRL_EM4HVSCALE_VSCALE0, +} EMU_VScaleEM4H_TypeDef; +#endif + +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +/** Peripheral EM2 and 3 retention control */ +typedef enum +{ + emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK, /* Select LEUART0 retention control */ + emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK, /* Select CSEN retention control */ + emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK, /* Select LESENSE0 retention control */ + emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK, /* Select LETIMER0 retention control */ + emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK, /* Select ADC0 retention control */ + emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK, /* Select IDAC0 retention control */ + emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK, /* Select DAC0 retention control */ + emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /* Select I2C1 retention control */ + emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, /* Select I2C0 retention control */ + emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK, /* Select ACMP1 retention control */ + emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK, /* Select ACMP0 retention control */ +#if defined( _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK ) + emuPeripheralRetention_PCNT2 = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK, /* Select PCNT2 retention control */ + emuPeripheralRetention_PCNT1 = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK, /* Select PCNT1 retention control */ +#endif + emuPeripheralRetention_PCNT0 = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK, /* Select PCNT0 retention control */ + + emuPeripheralRetention_D1 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/* Select all peripherals in domain 1 */ + emuPeripheralRetention_D2 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK + | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK + | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK +#if defined( _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK ) + | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK + | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK +#endif + | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /* Select all peripherals in domain 2 */ + emuPeripheralRetention_ALL = emuPeripheralRetention_D1 + | emuPeripheralRetention_D2, /* Select all peripherals with retention control */ +} EMU_PeripheralRetention_TypeDef; +#endif + /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ -/** Energy Mode 2 and 3 initialization structure */ +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/** EM0 and 1 initialization structure. Voltage scaling is applied when + the core clock frequency is changed from @ref CMU. EM0 an 1 emuVScaleEM01_HighPerformance + is always enabled. */ typedef struct { - bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3 */ + bool vScaleEM01LowPowerVoltageEnable; /**< EM0/1 low power voltage status */ +} EMU_EM01Init_TypeDef; +#endif + +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/** Default initialization of EM0 and 1 configuration */ +#define EMU_EM01INIT_DEFAULT \ +{ \ + false /** Do not scale down in EM0/1 */ \ +} +#endif + +/** EM2 and 3 initialization structure */ +typedef struct +{ + bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3 */ +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) + EMU_VScaleEM23_TypeDef vScaleEM23Voltage; /**< EM2/3 voltage scaling level */ +#endif } EMU_EM23Init_TypeDef; /** Default initialization of EM2 and 3 configuration */ -#define EMU_EM23INIT_DEFAULT \ -{ false } /* Reduced voltage regulator drive strength in EM2 and EM3 */ - +#if defined( _EMU_CTRL_EM4HVSCALE_MASK ) +#define EMU_EM23INIT_DEFAULT \ +{ \ + false, /* Reduced voltage regulator drive strength in EM2/3 */ \ + emuVScaleEM23_FastWakeup, /* Do not scale down in EM2/3 */ \ +} +#else +#define EMU_EM23INIT_DEFAULT \ +{ \ + false, /* Reduced voltage regulator drive strength in EM2/3 */ \ +} +#endif #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK ) -/** Energy Mode 4 initialization structure */ +/** EM4 initialization structure */ typedef struct { #if defined( _EMU_EM4CONF_MASK ) - /* Init parameters for platforms with EMU->EM4CONF register */ - bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator */ - bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4 */ - EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator */ - bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt */ - bool vreg; /**< Enable EM4 voltage regulator */ - + /* Init parameters for platforms with EMU->EM4CONF register (Series 0) */ + bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator */ + bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4 */ + EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator */ + bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt */ + bool vreg; /**< Enable EM4 voltage regulator */ #elif defined( _EMU_EM4CTRL_MASK ) - /* Init parameters for platforms with EMU->EM4CTRL register */ + /* Init parameters for platforms with EMU->EM4CTRL register (Series 1) */ bool retainLfxo; /**< Disable the LFXO upon EM4 entry */ bool retainLfrco; /**< Disable the LFRCO upon EM4 entry */ bool retainUlfrco; /**< Disable the ULFRCO upon EM4 entry */ EMU_EM4State_TypeDef em4State; /**< Hibernate or shutoff EM4 state */ EMU_EM4PinRetention_TypeDef pinRetentionMode; /**< EM4 pin retention mode */ #endif +#if defined( _EMU_CTRL_EM4HVSCALE_MASK ) + EMU_VScaleEM4H_TypeDef vScaleEM4HVoltage;/**< EM4H voltage scaling level */ +#endif } EMU_EM4Init_TypeDef; #endif -/** Default initialization of EM4 configuration */ #if defined( _EMU_EM4CONF_MASK ) +/** Default initialization of EM4 configuration (Series 0) */ #define EMU_EM4INIT_DEFAULT \ { \ false, /* Dont't lock configuration after it's been set */ \ - false, /* No reset will be asserted due to Brownout when in EM4 */ \ + false, /* No reset will be asserted due to BOD in EM4 */ \ emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator */ \ true, /* Wake up on EM4 BURTC interrupt */ \ true, /* Enable VREG */ \ } -#endif -#if defined( _EMU_EM4CTRL_MASK ) + +#elif defined( _EMU_CTRL_EM4HVSCALE_MASK ) +/** Default initialization of EM4 configuration (Series 1 with VSCALE) */ +#define EMU_EM4INIT_DEFAULT \ +{ \ + false, /* Retain LFXO configuration upon EM4 entry */ \ + false, /* Retain LFRCO configuration upon EM4 entry */ \ + false, /* Retain ULFRCO configuration upon EM4 entry */ \ + emuEM4Shutoff, /* Use EM4 shutoff state */ \ + emuPinRetentionDisable, /* Do not retain pins in EM4 */ \ + emuVScaleEM4H_FastWakeup, /* Do not scale down in EM4H */ \ +} + +#elif defined( _EMU_EM4CTRL_MASK ) +/** Default initialization of EM4 configuration (Series 1 without VSCALE) */ #define EMU_EM4INIT_DEFAULT \ { \ false, /* Retain LFXO configuration upon EM4 entry */ \ @@ -380,7 +519,8 @@ typedef struct /** DCDC initialization structure */ typedef struct { - EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration */ + EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration. + @ref emuPowerConfig_DcdcToDvdd is currently the only supported mode. */ EMU_DcdcMode_TypeDef dcdcMode; /**< DCDC regulator operating mode in EM0/1 */ uint16_t mVout; /**< Target output voltage (mV) */ uint16_t em01LoadCurrent_mA; /**< Estimated average load current in EM0/1 (mA). @@ -407,26 +547,11 @@ typedef struct /** Default DCDC initialization */ #if defined( _EFM_DEVICE ) -#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG) && (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) #define EMU_DCDCINIT_DEFAULT \ { \ emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ - emuDcdcMode_LowNoise, /* Low-niose mode in EM0 (can be set to LowPower on EFM32PG revB0) */ \ - 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \ - 5, /* Nominal EM0/1 load current of less than 5mA */ \ - 10, /* Nominal EM2/3/4 load current less than 10uA */ \ - 200, /* Maximum average current of 200mA - (assume strong battery or other power source) */ \ - emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \ - emuDcdcLnHighEfficiency, /* Use high-efficiency mode */ \ - emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \ -} - -#else -#define EMU_DCDCINIT_DEFAULT \ -{ \ - emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ - emuDcdcMode_LowNoise, /* Low-niose mode in EM0 (can be set to LowPower on EFM32PG revB0) */ \ + emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \ 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \ 5, /* Nominal EM0/1 load current of less than 5mA */ \ 10, /* Nominal EM2/3/4 load current less than 10uA */ \ @@ -436,25 +561,24 @@ typedef struct emuDcdcLnHighEfficiency, /* Use high-efficiency mode */ \ emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor */ \ } +#else +#define EMU_DCDCINIT_DEFAULT \ +{ \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ + emuDcdcMode_LowPower, /* Low-power mode in EM0 */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \ + 5, /* Nominal EM0/1 load current of less than 5mA */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source) */ \ + emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \ + emuDcdcLnHighEfficiency, /* Use high-efficiency mode */ \ + emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \ +} #endif #else /* EFR32 device */ -#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG) && (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) -#define EMU_DCDCINIT_DEFAULT \ -{ \ - emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ - emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \ - 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \ - 15, /* Nominal EM0/1 load current of less than 15mA */ \ - 10, /* Nominal EM2/3/4 load current less than 10uA */ \ - 200, /* Maximum average current of 200mA - (assume strong battery or other power source) */ \ - emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \ - 160, /* Maximum reverse current of 160mA */ \ - emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \ -} - -#else +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) #define EMU_DCDCINIT_DEFAULT \ { \ emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ @@ -468,6 +592,20 @@ typedef struct 160, /* Maximum reverse current of 160mA */ \ emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor */ \ } +#else +#define EMU_DCDCINIT_DEFAULT \ +{ \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ + emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \ + 15, /* Nominal EM0/1 load current of less than 15mA */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source) */ \ + emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \ + 160, /* Maximum reverse current of 160mA */ \ + emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \ +} #endif #endif #endif @@ -522,6 +660,52 @@ typedef struct ***************************** PROTOTYPES ********************************** ******************************************************************************/ +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init); +#endif +void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init); +#if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK ) +void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init); +#endif +void EMU_EnterEM2(bool restore); +void EMU_EnterEM3(bool restore); +void EMU_Restore(void); +void EMU_EnterEM4(void); +#if defined( _EMU_EM4CTRL_MASK ) +void EMU_EnterEM4H(void); +void EMU_EnterEM4S(void); +#endif +void EMU_MemPwrDown(uint32_t blocks); +void EMU_RamPowerDown(uint32_t start, uint32_t end); +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable); +#endif +void EMU_UpdateOscConfig(void); +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait); +void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait); +#endif +#if defined( BU_PRESENT ) +void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit); +void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value); +void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value); +#endif +#if defined( _EMU_DCDCCTRL_MASK ) +bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit); +void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode); +void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet); +bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage); +void EMU_DCDCOptimizeSlice(uint32_t mALoadCurrent); +void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band); +bool EMU_DCDCPowerOff(void); +#endif +#if defined( EMU_STATUS_VMONRDY ) +void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit); +void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit); +void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable); +bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel); +#endif + /***************************************************************************//** * @brief * Enter energy mode 1 (EM1). @@ -533,38 +717,35 @@ __STATIC_INLINE void EMU_EnterEM1(void) __WFI(); } -void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init); -#if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK ) -void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init); -#endif -void EMU_EnterEM2(bool restore); -void EMU_EnterEM3(bool restore); -void EMU_EnterEM4(void); -#if defined( _EMU_EM4CTRL_MASK ) -void EMU_EnterEM4H(void); -void EMU_EnterEM4S(void); -#endif -void EMU_MemPwrDown(uint32_t blocks); -void EMU_UpdateOscConfig(void); -#if defined( BU_PRESENT ) -void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit); -void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value); -void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value); -#endif -#if defined( _EMU_DCDCCTRL_MASK ) -bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit); -void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode); -bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage); -void EMU_DCDCOptimizeSlice(uint32_t mALoadCurrent); -void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band); -bool EMU_DCDCPowerOff(void); -#endif -#if defined( EMU_STATUS_VMONRDY ) -void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit); -void EMU_VmonHystInit(EMU_VmonHystInit_TypeDef *vmonInit); -void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable); -bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel); +#if defined( _EMU_STATUS_VSCALE_MASK ) +/***************************************************************************//** + * @brief + * Wait for voltage scaling to complete + ******************************************************************************/ +__STATIC_INLINE void EMU_VScaleWait(void) +{ + while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT)); +} +#endif + +#if defined( _EMU_STATUS_VSCALE_MASK ) +/***************************************************************************//** + * @brief + * Get current voltage scaling level + * + * @return + * Current voltage scaling level + ******************************************************************************/ +__STATIC_INLINE EMU_VScaleEM01_TypeDef EMU_VScaleGet(void) +{ + EMU_VScaleWait(); + return (EMU_VScaleEM01_TypeDef)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) + >> _EMU_STATUS_VSCALE_SHIFT); +} +#endif + +#if defined( _EMU_STATUS_VMONRDY_MASK ) /***************************************************************************//** * @brief * Get the status of the voltage monitor (VMON). @@ -577,7 +758,7 @@ __STATIC_INLINE bool EMU_VmonStatusGet(void) { return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT); } -#endif /* EMU_STATUS_VMONRDY */ +#endif /* _EMU_STATUS_VMONRDY_MASK */ #if defined( _EMU_IF_MASK ) /***************************************************************************//** @@ -805,7 +986,7 @@ __STATIC_INLINE void EMU_UnlatchPinRetention(void) } #endif -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode); #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpcrc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpcrc.h index f66b4efe9d..5ce0660d4c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpcrc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpcrc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h index ec09bdf8af..049d811497 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_gpio.h * @brief General Purpose IO (GPIO) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -68,6 +68,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 9 #define _GPIO_PORT_E_PIN_COUNT 12 #define _GPIO_PORT_F_PIN_COUNT 6 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0xF77F #define _GPIO_PORT_B_PIN_MASK 0x79F8 @@ -75,6 +80,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0x01FF #define _GPIO_PORT_E_PIN_MASK 0xFFF0 #define _GPIO_PORT_F_PIN_MASK 0x003F +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined( _EFM32_HAPPY_FAMILY ) @@ -84,6 +94,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 4 #define _GPIO_PORT_E_PIN_COUNT 4 #define _GPIO_PORT_F_PIN_COUNT 6 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0x0707 #define _GPIO_PORT_B_PIN_MASK 0x6980 @@ -91,6 +106,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0x00F0 #define _GPIO_PORT_E_PIN_MASK 0x3C00 #define _GPIO_PORT_F_PIN_MASK 0x003F +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined( _EFM32_GIANT_FAMILY ) \ || defined( _EFM32_WONDER_FAMILY ) @@ -101,6 +121,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 16 #define _GPIO_PORT_E_PIN_COUNT 16 #define _GPIO_PORT_F_PIN_COUNT 13 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0xFFFF #define _GPIO_PORT_B_PIN_MASK 0xFFFF @@ -108,6 +133,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0xFFFF #define _GPIO_PORT_E_PIN_MASK 0xFFFF #define _GPIO_PORT_F_PIN_MASK 0x1FFF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined( _EFM32_GECKO_FAMILY ) @@ -117,6 +147,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 16 #define _GPIO_PORT_E_PIN_COUNT 16 #define _GPIO_PORT_F_PIN_COUNT 10 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0xFFFF #define _GPIO_PORT_B_PIN_MASK 0xFFFF @@ -124,11 +159,13 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0xFFFF #define _GPIO_PORT_E_PIN_MASK 0xFFFF #define _GPIO_PORT_F_PIN_MASK 0x03FF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 -#elif defined( _EFR32_MIGHTY_FAMILY ) \ - || defined( _EFR32_BLUE_FAMILY ) \ - || defined( _EFR32_FLEX_FAMILY ) \ - || defined( _EFR32_ZAPPY_FAMILY ) +#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) && defined( _EFR_DEVICE ) #define _GPIO_PORT_A_PIN_COUNT 6 #define _GPIO_PORT_B_PIN_COUNT 5 @@ -136,6 +173,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 6 #define _GPIO_PORT_E_PIN_COUNT 0 #define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0x003F #define _GPIO_PORT_B_PIN_MASK 0xF800 @@ -143,9 +185,13 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0xFC00 #define _GPIO_PORT_E_PIN_MASK 0x0000 #define _GPIO_PORT_F_PIN_MASK 0x00FF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 -#elif defined( _EFM32_PEARL_FAMILY ) \ - || defined( _EFM32_JADE_FAMILY ) +#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) && defined( _EFM_DEVICE ) #define _GPIO_PORT_A_PIN_COUNT 6 #define _GPIO_PORT_B_PIN_COUNT 5 @@ -153,6 +199,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 7 #define _GPIO_PORT_E_PIN_COUNT 0 #define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0x003F #define _GPIO_PORT_B_PIN_MASK 0xF800 @@ -160,54 +211,95 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0xFE00 #define _GPIO_PORT_E_PIN_MASK 0x0000 #define _GPIO_PORT_F_PIN_MASK 0x00FF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 + +#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_84 ) + +#define _GPIO_PORT_A_PIN_COUNT 10 +#define _GPIO_PORT_B_PIN_COUNT 10 +#define _GPIO_PORT_C_PIN_COUNT 12 +#define _GPIO_PORT_D_PIN_COUNT 8 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 16 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 4 +#define _GPIO_PORT_J_PIN_COUNT 2 +#define _GPIO_PORT_K_PIN_COUNT 3 + +#define _GPIO_PORT_A_PIN_MASK 0x03FF +#define _GPIO_PORT_B_PIN_MASK 0xFFC0 +#define _GPIO_PORT_C_PIN_MASK 0x0FFF +#define _GPIO_PORT_D_PIN_MASK 0xFF00 +#define _GPIO_PORT_E_PIN_MASK 0x0000 +#define _GPIO_PORT_F_PIN_MASK 0xFFFF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x000F +#define _GPIO_PORT_J_PIN_MASK 0xC000 +#define _GPIO_PORT_K_PIN_MASK 0x0007 + +#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_89 ) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 6 +#define _GPIO_PORT_D_PIN_COUNT 6 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x003F +#define _GPIO_PORT_B_PIN_MASK 0xF800 +#define _GPIO_PORT_C_PIN_MASK 0x0FC0 +#define _GPIO_PORT_D_PIN_MASK 0xFC00 +#define _GPIO_PORT_E_PIN_MASK 0x0000 +#define _GPIO_PORT_F_PIN_MASK 0x00FF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 #else #warning "Port and pin masks are not defined for this family." #endif -#if defined( _GPIO_PORT_G_PIN_COUNT ) && defined( _GPIO_PORT_H_PIN_COUNT ) -#define _GPIO_PORT_SIZE(port) ( \ - (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \ - (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \ - (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \ - (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \ - (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \ - (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \ - (port) == 6 ? _GPIO_PORT_G_PIN_COUNT : \ - (port) == 7 ? _GPIO_PORT_H_PIN_COUNT : \ +#define _GPIO_PORT_SIZE(port) ( \ + (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \ + (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \ + (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \ + (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \ + (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \ + (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \ + (port) == 6 ? _GPIO_PORT_G_PIN_COUNT : \ + (port) == 7 ? _GPIO_PORT_H_PIN_COUNT : \ + (port) == 8 ? _GPIO_PORT_I_PIN_COUNT : \ + (port) == 9 ? _GPIO_PORT_J_PIN_COUNT : \ + (port) == 10 ? _GPIO_PORT_K_PIN_COUNT : \ 0) -#else -#define _GPIO_PORT_SIZE(port) ( \ - (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \ - (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \ - (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \ - (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \ - (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \ - (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \ - 0) -#endif -#if defined( _GPIO_PORT_G_PIN_MASK ) && defined( _GPIO_PORT_H_PIN_MASK ) -#define _GPIO_PORT_MASK(port) ( \ - (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \ - (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \ - (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \ - (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \ - (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \ - (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \ - (port) == 6 ? _GPIO_PORT_G_PIN_MASK : \ - (port) == 7 ? _GPIO_PORT_H_PIN_MASK : \ +#define _GPIO_PORT_MASK(port) ( \ + (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \ + (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \ + (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \ + (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \ + (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \ + (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \ + (port) == 6 ? _GPIO_PORT_G_PIN_MASK : \ + (port) == 7 ? _GPIO_PORT_H_PIN_MASK : \ + (port) == 8 ? _GPIO_PORT_I_PIN_MASK : \ + (port) == 9 ? _GPIO_PORT_J_PIN_MASK : \ + (port) == 10 ? _GPIO_PORT_K_PIN_MASK : \ 0) -#else -#define _GPIO_PORT_MASK(port) ( \ - (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \ - (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \ - (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \ - (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \ - (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \ - (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \ - 0) -#endif /** Validation of port and pin */ #define GPIO_PORT_VALID(port) ( _GPIO_PORT_MASK(port) ) @@ -224,15 +316,17 @@ extern "C" { #define GPIO_PIN_MAX 15 /** Highest GPIO port number */ -#if defined( _GPIO_PORT_J_PIN_COUNT ) +#if ( _GPIO_PORT_K_PIN_COUNT > 0 ) +#define GPIO_PORT_MAX 10 +#elif ( _GPIO_PORT_J_PIN_COUNT > 0 ) #define GPIO_PORT_MAX 9 -#elif defined( _GPIO_PORT_I_PIN_COUNT ) +#elif ( _GPIO_PORT_I_PIN_COUNT > 0 ) #define GPIO_PORT_MAX 8 -#elif defined( _GPIO_PORT_H_PIN_COUNT ) +#elif ( _GPIO_PORT_H_PIN_COUNT > 0 ) #define GPIO_PORT_MAX 7 -#elif defined( _GPIO_PORT_G_PIN_COUNT ) +#elif ( _GPIO_PORT_G_PIN_COUNT > 0 ) #define GPIO_PORT_MAX 6 -#elif defined( _GPIO_PORT_F_PIN_COUNT ) +#elif ( _GPIO_PORT_F_PIN_COUNT > 0 ) #define GPIO_PORT_MAX 5 #else #error "Max GPIO port number is undefined for this part." @@ -266,13 +360,22 @@ typedef enum gpioPortE = 4, #endif #if ( _GPIO_PORT_F_PIN_COUNT > 0 ) - gpioPortF = 5 + gpioPortF = 5, #endif -#if defined( _GPIO_PORT_G_PIN_COUNT ) && ( _GPIO_PORT_G_PIN_COUNT > 0 ) - gpioPortG = 6 +#if ( _GPIO_PORT_G_PIN_COUNT > 0 ) + gpioPortG = 6, #endif -#if defined( _GPIO_PORT_H_PIN_COUNT ) && ( _GPIO_PORT_H_PIN_COUNT > 0 ) - gpioPortH = 7 +#if ( _GPIO_PORT_H_PIN_COUNT > 0 ) + gpioPortH = 7, +#endif +#if ( _GPIO_PORT_I_PIN_COUNT > 0 ) + gpioPortI = 8, +#endif +#if ( _GPIO_PORT_J_PIN_COUNT > 0 ) + gpioPortJ = 9, +#endif +#if ( _GPIO_PORT_K_PIN_COUNT > 0 ) + gpioPortK = 10, #endif } GPIO_Port_TypeDef; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h index 659a218612..356cfb86fe 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_i2c.h * @brief Inter-intergrated circuit (I2C) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -68,12 +68,17 @@ extern "C" { * @note * Due to chip characteristics, the max value is somewhat reduced. */ -#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_TINY_FAMILY) \ - || defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY) +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GECKO_FAMILY) \ + || defined(_EFM32_TINY_FAMILY) \ + || defined(_EFM32_ZERO_FAMILY) \ + || defined(_EFM32_HAPPY_FAMILY)) #define I2C_FREQ_STANDARD_MAX 93000 -#elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) +#elif defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GIANT_FAMILY) \ + || defined(_EFM32_WONDER_FAMILY)) #define I2C_FREQ_STANDARD_MAX 92000 -#elif defined(_SILICON_LABS_32B_PLATFORM_2) +#elif defined(_SILICON_LABS_32B_SERIES_1) // None of the chips on this platform has been characterized on this parameter. // Use same value as on Wonder until further notice. #define I2C_FREQ_STANDARD_MAX 92000 diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h index 7d253e5550..47c4d18415 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_idac.h * @brief Current Digital to Analog Converter (IDAC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h index adbc7c1b1f..c7325001d6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_int.h * @brief Interrupt enable/disable unit API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h index 583a26cfc4..62a54059d3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_lcd.h * @brief Liquid Crystal Display (LCD) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ldma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ldma.h index a40d6f873f..9dfb127e58 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ldma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ldma.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_ldma.h * @brief Direct memory access (LDMA) API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -239,15 +239,12 @@ typedef enum typedef enum { ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. - #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SCAN ) + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN) ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SCAN. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE ) + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE) ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SINGLE. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_AGCRSSI ) - ldmaPeripheralSignal_AGC_RSSI = LDMA_CH_REQSEL_SIGSEL_AGCRSSI | LDMA_CH_REQSEL_SOURCESEL_AGC, ///< Trig on AGC_RSSI. - #endif #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD ) ldmaPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0RD. #endif @@ -263,107 +260,182 @@ typedef enum #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR ) ldmaPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1WR. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV ) + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD) + ldmaPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR) + ldmaPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR) + ldmaPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD) + ldmaPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR) + ldmaPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD) + ldmaPeripheralSignal_CRYPTO1_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR) + ldmaPeripheralSignal_CRYPTO1_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR) + ldmaPeripheralSignal_CRYPTO1_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD) + ldmaPeripheralSignal_CRYPTO1_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR) + ldmaPeripheralSignal_CRYPTO1_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CSENBSLN) + ldmaPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_BSLN. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA) + ldmaPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_DATA. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV) ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_RXDATAV. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0TXBL ) + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0TXBL) ldmaPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_TXBL. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV ) + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV) + ldmaPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL) + ldmaPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV) + ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trig on LESENSE_BUFDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV) ldmaPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_RXDATAV. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL ) + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL) ldmaPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXBL. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY ) + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY) ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXEMPTY. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG ) - ldmaPeripheralSignal_MODEM_DEBUG = LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMA_CH_REQSEL_SOURCESEL_MODEM, ///< Trig on MODEM_DEBUG. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_MSCWDATA ) + #if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA) ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trig on MSC_WDATA. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF ) - ldmaPeripheralSignal_PROTIMER_BOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_BOF. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 ) - ldmaPeripheralSignal_PROTIMER_CC0 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC0. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 ) - ldmaPeripheralSignal_PROTIMER_CC1 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC1. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 ) - ldmaPeripheralSignal_PROTIMER_CC2 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC2. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 ) - ldmaPeripheralSignal_PROTIMER_CC3 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC3. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 ) - ldmaPeripheralSignal_PROTIMER_CC4 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC4. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF ) - ldmaPeripheralSignal_PROTIMER_POF = LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_POF. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF ) - ldmaPeripheralSignal_PROTIMER_WOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_WOF. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ0 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ0) ldmaPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ0. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ1 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ1) ldmaPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ1. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC0) ldmaPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC0. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC1) ldmaPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC1. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC2) ldmaPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC2. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF) ldmaPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_UFOF. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC0) ldmaPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC0. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC1) ldmaPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC1. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC2) ldmaPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC2. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC3) ldmaPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC3. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF) ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_UFOF. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV) ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_RXDATAV. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXBL ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXBL) ldmaPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXBL. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY) ldmaPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXEMPTY. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV) ldmaPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAV. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT) ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAVRIGHT. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBL ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBL) ldmaPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBL. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT) ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBLRIGHT. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY ) - ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1 ///< Trig on USART1_TXEMPTY. + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY) + ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV) + ldmaPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBL) + ldmaPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY) + ldmaPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV) + ldmaPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT) + ldmaPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBL) + ldmaPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT) + ldmaPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY) + ldmaPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0) + ldmaPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH1) + ldmaPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0) + ldmaPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1) + ldmaPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2) + ldmaPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF) + ldmaPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0) + ldmaPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1) + ldmaPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2) + ldmaPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3) + ldmaPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF) + ldmaPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1 ///< Trig on WTIMER1_UFOF. #endif } LDMA_PeripheralSignal_t; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h index 95bde6dcf1..3f74bf0706 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_lesense.h * @brief Low Energy Sensor (LESENSE) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -35,9 +35,7 @@ #include "em_device.h" -/* LESENSE is currently only supported on Platform 1. Full support for Platform 2 LESENSE - will be included in the next release. */ -#if defined(LESENSE_COUNT) && (LESENSE_COUNT > 0) && defined(_SILICON_LABS_32B_PLATFORM_1) +#if defined(LESENSE_COUNT) && (LESENSE_COUNT > 0) #include #include @@ -56,11 +54,11 @@ extern "C" { * @{ ******************************************************************************/ -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** Number of decoder states supported by current device. */ +#define LESENSE_NUM_DECODER_STATES (_LESENSE_DECSTATE_DECSTATE_MASK + 1) - - -/** @endcond */ +/** Number of LESENSE channels. */ +#define LESENSE_NUM_CHANNELS 16 /******************************************************************************* ******************************** ENUMS ************************************ @@ -139,8 +137,16 @@ typedef enum /** Alternate excitation is mapped to the LES_ALTEX pins. */ lesenseAltExMapALTEX = _LESENSE_CTRL_ALTEXMAP_ALTEX, +#if defined(_LESENSE_CTRL_ALTEXMAP_ACMP) /** Alternate excitation is mapped to the pins of the other ACMP. */ - lesenseAltExMapACMP = _LESENSE_CTRL_ALTEXMAP_ACMP + lesenseAltExMapACMP = _LESENSE_CTRL_ALTEXMAP_ACMP, +#endif + +#if defined(_LESENSE_CTRL_ALTEXMAP_CH) + /** Alternative excitation is mapped to the pin of LESENSE channel + * (X+8 mod 16), X being the active channel. */ + lesenseAltExMapCH = _LESENSE_CTRL_ALTEXMAP_CH, +#endif } LESENSE_AltExMap_TypeDef; @@ -213,12 +219,20 @@ typedef enum * Note: this value could be used for both DAC Ch0 and Ch1. */ lesenseDACIfData = _LESENSE_PERCTRL_DACCH0DATA_DACDATA, +#if defined(_LESENSE_PERCTRL_DACCH0DATA_ACMPTHRES) /** DAC channel x data is defined by ACMPTHRES in LESENSE_CHx_INTERACT. * Note: this value could be used for both DAC Ch0 and Ch1. */ - lesenseACMPThres = _LESENSE_PERCTRL_DACCH0DATA_ACMPTHRES + lesenseACMPThres = _LESENSE_PERCTRL_DACCH0DATA_ACMPTHRES, +#endif + +#if defined(_LESENSE_PERCTRL_DACCH0DATA_THRES) + /** DAC channel x data is defined by THRES in LESENSE_CHx_INTERACT. + * Note: this value could be used for both DAC Ch0 and Ch1. */ + lesenseThres = _LESENSE_PERCTRL_DACCH0DATA_THRES, +#endif } LESENSE_ControlDACData_TypeDef; - +#if defined(_LESENSE_PERCTRL_DACCH0CONV_MASK) /** DAC channel x conversion mode configuration. */ typedef enum { @@ -238,8 +252,9 @@ typedef enum * Note: this value could be used for both DAC Ch0 and Ch1. */ lesenseDACConvModeSampleOff = _LESENSE_PERCTRL_DACCH0CONV_SAMPLEOFF } LESENSE_ControlDACConv_TypeDef; +#endif - +#if defined(_LESENSE_PERCTRL_DACCH0OUT_MASK) /** DAC channel x output mode configuration. */ typedef enum { @@ -259,8 +274,10 @@ typedef enum * Note: this value could be used for both DAC Ch0 and Ch1. */ lesenseDACOutModePinADCACMP = _LESENSE_PERCTRL_DACCH0OUT_PINADCACMP } LESENSE_ControlDACOut_TypeDef; +#endif +#if defined(_LESENSE_PERCTRL_DACREF_MASK) /** DAC reference configuration. */ typedef enum { @@ -270,6 +287,7 @@ typedef enum /** DAC uses bandgap reference. */ lesenseDACRefBandGap = LESENSE_PERCTRL_DACREF_BANDGAP } LESENSE_DACRef_TypeDef; +#endif /** ACMPx control configuration. */ @@ -321,10 +339,18 @@ typedef enum typedef enum { /** Counter output will be used in comparison. */ - lesenseSampleModeCounter = LESENSE_CH_INTERACT_SAMPLE_COUNTER, + lesenseSampleModeCounter = 0x0 << _LESENSE_CH_INTERACT_SAMPLE_SHIFT, /** ACMP output will be used in comparison. */ - lesenseSampleModeACMP = LESENSE_CH_INTERACT_SAMPLE_ACMP + lesenseSampleModeACMP = LESENSE_CH_INTERACT_SAMPLE_ACMP, + +#if defined(LESENSE_CH_INTERACT_SAMPLE_ADC) + /** ADC output will be used in comparison. */ + lesenseSampleModeADC = LESENSE_CH_INTERACT_SAMPLE_ADC, + + /** Differential ADC output will be used in comparison. */ + lesenseSampleModeADCDiff = LESENSE_CH_INTERACT_SAMPLE_ADCDIFF, +#endif } LESENSE_ChSampleMode_TypeDef; @@ -377,13 +403,19 @@ typedef enum * Note: this value could be used for all channels. */ lesenseChPinIdleLow = _LESENSE_IDLECONF_CH0_LOW, +#if defined(_LESENSE_IDLECONF_CH0_DAC) + /** Channel pin is connected to DAC output in idle phase. + * Note: this value could be used for all channels. */ + lesenseChPinIdleDACC = _LESENSE_IDLECONF_CH0_DAC +#else /** Channel pin is connected to DAC CH0 output in idle phase. * Note: only applies to channel 0, 1, 2, 3. */ lesenseChPinIdleDACCh0 = _LESENSE_IDLECONF_CH0_DACCH0, /** Channel pin is connected to DAC CH1 output in idle phase. * Note: only applies to channel 12, 13, 14, 15. */ - lesenseChPinIdleDACCh1 = _LESENSE_IDLECONF_CH12_DACCH1 + lesenseChPinIdleDACCh1 = _LESENSE_IDLECONF_CH12_DACCH1, +#endif } LESENSE_ChPinIdleMode_TypeDef; @@ -401,16 +433,43 @@ typedef enum /** Compare modes for counter comparison. */ typedef enum { - /** Set interrupt flag if counter value is less than CTRTHRESHOLD, or if the - * ACMP output is 0. */ + /** Comparison evaluates to 1 if the sensor data is less than the counter + * threshold, or if the ACMP output is 0. */ lesenseCompModeLess = LESENSE_CH_EVAL_COMP_LESS, - /** Set interrupt flag if counter value is greater than, or equal to - * CTRTHRESHOLD, or if the ACMP output is 1. */ + /** Comparison evaluates to 1 if the sensor data is greater than, or equal to + * the counter threshold, or if the ACMP output is 1. */ lesenseCompModeGreaterOrEq = LESENSE_CH_EVAL_COMP_GE } LESENSE_ChCompMode_TypeDef; +#if defined(_LESENSE_CH_EVAL_MODE_MASK) +/** Sensor evaluation modes. */ +typedef enum +{ + /** Threshold comparison evaluation mode. In this mode the sensor data + * is compared to the configured threshold value. Two possible comparison + * operators can be used on the sensor data, either >= (GE) or < (LT). + * Which operator to use is given using the + * @ref LESENSE_ChDesc_TypeDef::compMode member. */ + lesenseEvalModeThreshold = _LESENSE_CH_EVAL_MODE_THRES, + + /** Sliding window evaluation mode. In this mode the sensor data is + * evaluated against the upper and lower limits of a window range. The + * windows range is defined by a base value and a window size. */ + lesenseEvalModeSlidingWindow = _LESENSE_CH_EVAL_MODE_SLIDINGWIN, + + /** Step detection evaluation mode. In this mode the sensor data is compared + * to the sensor data from the previous measurement. The sensor evaluation + * will result in a "1" if the difference between the current measurement + * and the previous one is greater than a configurable "step size". If the + * difference is less than the configured step size then the sensor + * evaluation will result in a "0". */ + lesenseEvalModeStepDetection = _LESENSE_CH_EVAL_MODE_STEPDET, +} LESENSE_ChEvalMode_TypeDef; +#endif + + /** Idle phase configuration of alternate excitation channels. */ typedef enum { @@ -533,19 +592,25 @@ typedef struct true /* Keep LESENSE running in debug mode. */ \ } - /** LESENSE timing control descriptor structure. */ typedef struct { /** Set the number of LFACLK cycles to delay sensor interaction on * each channel. Valid range: 0-3 (2 bit). */ uint8_t startDelay; + + /** + * Set to true do delay the startup of AUXHFRCO until the system enters + * the excite phase. This will reduce the time AUXHFRCO is enabled and + * reduce power usage. */ + bool delayAuxStartup; } LESENSE_TimeCtrlDesc_TypeDef; /** Default configuration for LESENSE_TimeCtrlDesc_TypeDef structure. */ -#define LESENSE_TIMECTRL_DESC_DEFAULT \ -{ \ - 0U /* No sensor interaction delay. */ \ +#define LESENSE_TIMECTRL_DESC_DEFAULT \ +{ \ + 0U, /* No sensor interaction delay. */ \ + false /* Don't delay the AUXHFRCO startup. */ \ } @@ -555,28 +620,36 @@ typedef struct /** Configure DAC channel 0 data control. */ LESENSE_ControlDACData_TypeDef dacCh0Data; +#if defined(_LESENSE_PERCTRL_DACCH0CONV_MASK) /** Configure how LESENSE controls conversion on DAC channel 0. */ LESENSE_ControlDACConv_TypeDef dacCh0ConvMode; /** Configure how LESENSE controls output on DAC channel 0. */ LESENSE_ControlDACOut_TypeDef dacCh0OutMode; +#endif /** Configure DAC channel 1 data control. */ LESENSE_ControlDACData_TypeDef dacCh1Data; +#if defined(_LESENSE_PERCTRL_DACCH1CONV_MASK) /** Configure how LESENSE controls conversion on DAC channel 1. */ LESENSE_ControlDACConv_TypeDef dacCh1ConvMode; /** Configure how LESENSE controls output on DAC channel 1. */ LESENSE_ControlDACOut_TypeDef dacCh1OutMode; +#endif +#if defined(_LESENSE_PERCTRL_DACPRESC_MASK) /** Configure the prescaling factor for the LESENSE - DAC interface. * Valid range: 0-31 (5bit). */ uint8_t dacPresc; +#endif +#if defined(_LESENSE_PERCTRL_DACREF_MASK) /** Configure the DAC reference to be used. Set to #lesenseDACRefVdd to use * VDD and set to #lesenseDACRefBandGap to use bandgap as reference. */ LESENSE_DACRef_TypeDef dacRef; +#endif /** Configure how LESENSE controls ACMP 0. */ LESENSE_ControlACMP_TypeDef acmp0Mode; @@ -586,24 +659,41 @@ typedef struct /** Configure how LESENSE controls ACMPs and the DAC in idle mode. */ LESENSE_WarmupMode_TypeDef warmupMode; + +#if defined(_LESENSE_PERCTRL_DACCONVTRIG_MASK) + /** When set to true the DAC is only enabled once for each scan. When + * set to false the DAC is enabled before every channel measurement. */ + bool dacScan; +#endif } LESENSE_PerCtrlDesc_TypeDef; /** Default configuration for LESENSE_PerCtrl_TypeDef structure. */ +#if defined(_SILICON_LABS_32B_SERIES_0) #define LESENSE_PERCTRL_DESC_DEFAULT \ { \ - lesenseDACIfData, /**/ \ - lesenseDACConvModeDisable, /**/ \ - lesenseDACOutModeDisable, /**/ \ - lesenseDACIfData, /**/ \ - lesenseDACConvModeDisable, /**/ \ - lesenseDACOutModeDisable, /**/ \ - 0U, /**/ \ - lesenseDACRefVdd, /**/ \ - lesenseACMPModeMuxThres, /**/ \ - lesenseACMPModeMuxThres, /**/ \ - lesenseWarmupModeKeepWarm, /**/ \ + lesenseDACIfData, /* DAC channel 0 data is defined by DAC_CH0DATA register */ \ + lesenseDACConvModeDisable, /* LESENSE does not control DAC CH0. */ \ + lesenseDACOutModeDisable, /* DAC channel 0 output to pin disabled. */ \ + lesenseDACIfData, /* DAC channel 1 data is defined by DAC_CH1DATA register */ \ + lesenseDACConvModeDisable, /* LESENSE does not control DAC CH1. */ \ + lesenseDACOutModeDisable, /* DAC channel 1 output to pin disabled. */ \ + 0U, /* DAC prescaling factor of 1 (0+1). */ \ + lesenseDACRefVdd, /* DAC uses VDD reference. */ \ + lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP0. */ \ + lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP1. */ \ + lesenseWarmupModeKeepWarm, /* Keep both ACMPs and the DAC powered up when LESENSE is idle. */ \ } - +#else +#define LESENSE_PERCTRL_DESC_DEFAULT \ +{ \ + lesenseDACIfData, /* DAC channel 0 data is defined by DAC_CH0DATA register. */ \ + lesenseDACIfData, /* DAC channel 1 data is defined by DAC_CH1DATA register. */ \ + lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP0. */ \ + lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP1. */ \ + lesenseWarmupModeKeepWarm, /* Keep both ACMPs and the DAC powered up when LESENSE is idle. */ \ + false, /* DAC is enable for before every channel measurement. */ \ +} +#endif /** LESENSE decoder control descriptor structure. */ typedef struct @@ -615,7 +705,7 @@ typedef struct uint32_t initState; /** Set to enable the decoder to check the present state in addition - * to the states defined in DECCONF. */ + * to the states defined in TCONF. */ bool chkState; /** When set, a transition from state x in the decoder will set interrupt flag @@ -658,19 +748,19 @@ typedef struct /** Default configuration for LESENSE_PerCtrl_TypeDef structure. */ #define LESENSE_DECCTRL_DESC_DEFAULT \ { \ - lesenseDecInputSensorSt, /**/ \ - 0U, /**/ \ - false, /**/ \ - true, /**/ \ - true, /**/ \ - true, /**/ \ - true, /**/ \ - true, /**/ \ - false, /**/ \ - lesensePRSCh0, /**/ \ - lesensePRSCh1, /**/ \ - lesensePRSCh2, /**/ \ - lesensePRSCh3, /**/ \ + lesenseDecInputSensorSt, /* The SENSORSTATE register is used as input to the decoder. */ \ + 0U, /* State 0 is the initial state of the decoder. */ \ + false, /* Disable check of current state. */ \ + true, /* Enable channel x % 16 interrupt on state x change. */ \ + true, /* Enable decoder hysteresis on PRS0 output. */ \ + true, /* Enable decoder hysteresis on PRS1 output. */ \ + true, /* Enable decoder hysteresis on PRS2 output. */ \ + true, /* Enable decoder hysteresis on PRS3 output. */ \ + false, /* Disable count mode on decoder PRS channels 0 and 1*/ \ + lesensePRSCh0, /* PRS Channel 0 as input for bit 0 of the LESENSE decoder. */ \ + lesensePRSCh1, /* PRS Channel 1 as input for bit 1 of the LESENSE decoder. */ \ + lesensePRSCh2, /* PRS Channel 2 as input for bit 2 of the LESENSE decoder. */ \ + lesensePRSCh3, /* PRS Channel 3 as input for bit 3 of the LESENSE decoder. */ \ } @@ -745,14 +835,16 @@ typedef struct uint8_t exTime; /** Configure sample delay. Sampling will occur after sampleDelay+1 sample - * clock cycles. Valid range: 0-127 (7 bits). */ + * clock cycles. Valid range: 0-127 (7 bits) or 0-255 (8 bits) depending on + * device. */ uint8_t sampleDelay; /** Configure measure delay. Sensor measuring is delayed for measDelay - * excitation clock cycles. Valid range: 0-127 (7 bits). */ - uint8_t measDelay; + * excitation clock cycles. Valid range: 0-127 (7 bits) or 0-1023 (10 bits) + * depending on device. */ + uint16_t measDelay; - /** Configure ACMP threshold. + /** Configure ACMP threshold or DAC data. * If perCtrl.dacCh0Data or perCtrl.dacCh1Data is set to #lesenseDACIfData, * acmpThres defines the 12-bit DAC data in the corresponding data register * of the DAC interface (DACn_CH0DATA and DACn_CH1DATA). @@ -763,29 +855,61 @@ typedef struct * In this case, the valid range is: 0-63 (6 bits). */ uint16_t acmpThres; - /** Select if ACMP output or counter output should be used in comparison. */ + /** Select if ACMP output, ADC output or counter output should be used in + * comparison. */ LESENSE_ChSampleMode_TypeDef sampleMode; /** Configure interrupt generation mode for CHx interrupt flag. */ LESENSE_ChIntMode_TypeDef intMode; - /** Configure decision threshold for counter comparison. + /** Configure decision threshold for sensor data comparison. * Valid range: 0-65535 (16 bits). */ uint16_t cntThres; /** Select mode for counter comparison. */ LESENSE_ChCompMode_TypeDef compMode; + +#if defined(_LESENSE_CH_EVAL_MODE_MASK) + /** Select sensor evaluation mode. */ + LESENSE_ChEvalMode_TypeDef evalMode; +#endif + } LESENSE_ChDesc_TypeDef; /** Configuration structure for all scan channels. */ typedef struct { - /** Channel descriptor for all 16 channels. */ - LESENSE_ChDesc_TypeDef Ch[16]; + /** Channel descriptor for all LESENSE channels. */ + LESENSE_ChDesc_TypeDef Ch[LESENSE_NUM_CHANNELS]; } LESENSE_ChAll_TypeDef; /** Default configuration for scan channel. */ +#if defined(_LESENSE_CH_EVAL_MODE_MASK) +#define LESENSE_CH_CONF_DEFAULT \ +{ \ + true, /* Enable scan channel. */ \ + true, /* Enable the assigned pin on scan channel. */ \ + true, /* Enable interrupts on channel. */ \ + lesenseChPinExHigh, /* Channel pin is high during the excitation period. */ \ + lesenseChPinIdleLow, /* Channel pin is low during the idle period. */ \ + false, /* Don't use alternate excitation pins for excitation. */ \ + false, /* Disabled to shift results from this channel to the decoder register. */ \ + false, /* Disabled to invert the scan result bit. */ \ + false, /* Disabled to store counter value in the result buffer. */ \ + lesenseClkLF, /* Use the LF clock for excitation timing. */ \ + lesenseClkLF, /* Use the LF clock for sample timing. */ \ + 0x03U, /* Excitation time is set to 3(+1) excitation clock cycles. */ \ + 0x09U, /* Sample delay is set to 9(+1) sample clock cycles. */ \ + 0x06U, /* Measure delay is set to 6 excitation clock cycles.*/ \ + 0x00U, /* ACMP threshold has been set to 0. */ \ + lesenseSampleModeACMP, /* ACMP output will be used in comparison. */ \ + lesenseSetIntNone, /* No interrupt is generated by the channel. */ \ + 0xFFU, /* Counter threshold has bee set to 0xFF. */ \ + lesenseCompModeLess, /* Compare mode has been set to trigger interrupt on "less". */ \ + lesenseEvalModeThreshold /* Compare mode has been set to trigger interrupt on "less". */ \ +} +#else #define LESENSE_CH_CONF_DEFAULT \ { \ true, /* Enable scan channel. */ \ @@ -808,6 +932,8 @@ typedef struct 0xFFU, /* Counter threshold has bee set to 0xFF. */ \ lesenseCompModeLess /* Compare mode has been set to trigger interrupt on "less". */ \ } +#endif + /** Default configuration for all sensor channels. */ #define LESENSE_SCAN_CONF_DEFAULT \ @@ -887,6 +1013,7 @@ typedef struct } /** Default configuration for all alternate excitation channels. */ +#if defined(_LESENSE_CTRL_ALTEXMAP_ACMP) #define LESENSE_ALTEX_CONF_DEFAULT \ { \ lesenseAltExMapACMP, \ @@ -909,7 +1036,30 @@ typedef struct LESENSE_ALTEX_CH_CONF_DEFAULT /* Alternate excitation channel 15. */ \ } \ } - +#else +#define LESENSE_ALTEX_CONF_DEFAULT \ +{ \ + lesenseAltExMapCH, \ + { \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 0. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 1. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 2. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 3. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 4. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 5. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 6. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 7. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 8. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 9. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 10. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 11. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 12. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 13. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 14. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT /* Alternate excitation channel 15. */ \ + } \ +} +#endif /** Decoder state condition descriptor structure. */ typedef struct @@ -966,11 +1116,12 @@ typedef struct /** Configuration structure for the decoder. */ typedef struct { - /** Descriptor of the 16 decoder states. */ - LESENSE_DecStDesc_TypeDef St[16]; + /** Descriptor of the 16 or 32 decoder states depending on the device. */ + LESENSE_DecStDesc_TypeDef St[LESENSE_NUM_DECODER_STATES]; } LESENSE_DecStAll_TypeDef; /** Default configuration for all decoder states. */ +#if defined(_SILICON_LABS_32B_SERIES_0) #define LESENSE_DECODER_CONF_DEFAULT \ { /* chain | Descriptor A | Descriptor B */ \ { \ @@ -992,44 +1143,93 @@ typedef struct { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT } /* Decoder state 15. */ \ } \ } +#else +#define LESENSE_DECODER_CONF_DEFAULT \ +{ /* chain | Descriptor A | Descriptor B */ \ + { \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 0. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 1. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 2. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 3. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 4. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 5. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 6. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 7. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 8. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 9. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 10. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 11. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 12. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 13. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 14. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 15. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 16. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 17. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 18. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 19. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 20. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 21. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 22. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 23. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 24. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 25. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 26. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 27. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 28. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 29. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 30. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT } /* Decoder state 31. */ \ + } \ +} +#endif /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ -void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset); +void LESENSE_Init(const LESENSE_Init_TypeDef * init, bool reqReset); void LESENSE_Reset(void); -uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t const scanFreq); -void LESENSE_ScanModeSet(LESENSE_ScanMode_TypeDef const scanMode, - bool const start); +uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t scanFreq); +void LESENSE_ScanModeSet(LESENSE_ScanMode_TypeDef scanMode, bool start); +void LESENSE_StartDelaySet(uint8_t startDelay); +void LESENSE_ClkDivSet(LESENSE_ChClk_TypeDef clk, + LESENSE_ClkPresc_TypeDef clkDiv); -void LESENSE_StartDelaySet(uint8_t const startDelay); - -void LESENSE_ClkDivSet(LESENSE_ChClk_TypeDef const clk, - LESENSE_ClkPresc_TypeDef const clkDiv); - -void LESENSE_ChannelAllConfig(LESENSE_ChAll_TypeDef const *confChAll); -void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, - uint32_t const chIdx); -void LESENSE_ChannelEnable(uint8_t const chIdx, - bool const enaScanCh, - bool const enaPin); +void LESENSE_ChannelAllConfig(const LESENSE_ChAll_TypeDef * confChAll); +void LESENSE_ChannelConfig(const LESENSE_ChDesc_TypeDef * confCh, + uint32_t chIdx); +void LESENSE_ChannelEnable(uint8_t chIdx, + bool enaScanCh, + bool enaPin); void LESENSE_ChannelEnableMask(uint16_t chMask, uint16_t pinMask); -void LESENSE_ChannelTimingSet(uint8_t const chIdx, - uint8_t const exTime, - uint8_t const sampleDelay, - uint8_t const measDelay); -void LESENSE_ChannelThresSet(uint8_t const chIdx, - uint16_t const acmpThres, - uint16_t const cntThres); +void LESENSE_ChannelTimingSet(uint8_t chIdx, + uint8_t exTime, + uint8_t sampleDelay, + uint16_t measDelay); +void LESENSE_ChannelThresSet(uint8_t chIdx, + uint16_t acmpThres, + uint16_t cntThres); +#if defined(_LESENSE_CH_EVAL_MODE_MASK) +void LESENSE_ChannelSlidingWindow(uint8_t chIdx, + uint32_t windowSize, + uint32_t initValue); +void LESENSE_ChannelStepDetection(uint8_t chIdx, + uint32_t stepSize, + uint32_t initValue); +void LESENSE_WindowSizeSet(uint32_t windowSize); +void LESENSE_StepSizeSet(uint32_t stepSize); +#endif -void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx); +void LESENSE_AltExConfig(const LESENSE_ConfAltEx_TypeDef * confAltEx); -void LESENSE_DecoderStateAllConfig(LESENSE_DecStAll_TypeDef const *confDecStAll); -void LESENSE_DecoderStateConfig(LESENSE_DecStDesc_TypeDef const *confDecSt, - uint32_t const decSt); +void LESENSE_DecoderStateAllConfig(const LESENSE_DecStAll_TypeDef * confDecStAll); +void LESENSE_DecoderStateConfig(const LESENSE_DecStDesc_TypeDef * confDecSt, + uint32_t decSt); void LESENSE_DecoderStateSet(uint32_t decSt); uint32_t LESENSE_DecoderStateGet(void); +#if defined(_LESENSE_PRSCTRL_MASK) +void LESENSE_DecoderPrsOut(bool enable, uint32_t decMask, uint32_t decCmp); +#endif void LESENSE_ScanStart(void); void LESENSE_ScanStop(void); @@ -1126,7 +1326,7 @@ __STATIC_INLINE uint32_t LESENSE_ChannelActiveGet(void) ******************************************************************************/ __STATIC_INLINE uint32_t LESENSE_ScanResultGet(void) { - return LESENSE->SCANRES; + return LESENSE->SCANRES & _LESENSE_SCANRES_SCANRES_MASK; } @@ -1184,6 +1384,7 @@ __STATIC_INLINE uint32_t LESENSE_SensorStateGet(void) } +#if defined(LESENSE_POWERDOWN_RAM) /***************************************************************************//** * @brief * Shut off power to the LESENSE RAM, disables LESENSE. @@ -1201,6 +1402,7 @@ __STATIC_INLINE void LESENSE_RAMPowerDown(void) /* Power down LESENSE RAM */ LESENSE->POWERDOWN = LESENSE_POWERDOWN_RAM; } +#endif /***************************************************************************//** diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h index 782a9b8740..9a3eeb8340 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_letimer.h * @brief Low Energy Timer (LETIMER) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h index ac6f842ced..656c0e4b97 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h @@ -2,7 +2,7 @@ * @file em_leuart.h * @brief Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) * peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h index 3b5c528381..b562694d39 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_mpu.h * @brief Memory protection unit (MPU) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h index 895ef37ccc..9a71be990f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_msc.h * @brief Flash controller (MSC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -132,7 +132,7 @@ extern "C" { /** Return codes for writing/erasing the flash */ typedef enum { - mscReturnOk = 0, /**< Flash write/erase successful. */ + mscReturnOk = 0, /**< Flash write/erase successful. */ mscReturnInvalidAddr = -1, /**< Invalid address. Write to an address that is not flash. */ mscReturnLocked = -2, /**< Flash address is locked. */ mscReturnTimeOut = -3, /**< Timeout while writing to flash. */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h index cdb2201986..204bfd1669 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file em_opamp.h * @brief Operational Amplifier (OPAMP) peripheral API - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -34,7 +34,8 @@ #define EM_OPAMP_H #include "em_device.h" -#if defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1) +#if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \ + || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0))) #ifdef __cplusplus extern "C" { @@ -42,7 +43,12 @@ extern "C" { #include #include + +#if defined(_SILICON_LABS_32B_SERIES_0) #include "em_dac.h" +#elif defined (_SILICON_LABS_32B_SERIES_1) +#include "em_vdac.h" +#endif /***************************************************************************//** * @addtogroup emlib @@ -57,7 +63,11 @@ extern "C" { /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** Validation of DAC OPA number for assert statements. */ +#if defined(_SILICON_LABS_32B_SERIES_0) #define DAC_OPA_VALID(opa) ((opa) <= OPA2) +#elif defined(_SILICON_LABS_32B_SERIES_1) +#define VDAC_OPA_VALID(opa) ((opa) <= OPA2) +#endif /** @endcond */ @@ -76,34 +86,249 @@ typedef enum /** OPAMP negative terminal input selection values. */ typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) opaNegSelDisable = DAC_OPA0MUX_NEGSEL_DISABLE, /**< Input disabled. */ opaNegSelUnityGain = DAC_OPA0MUX_NEGSEL_UG, /**< Unity gain feedback path. */ opaNegSelResTap = DAC_OPA0MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */ opaNegSelNegPad = DAC_OPA0MUX_NEGSEL_NEGPAD /**< Negative pad as input. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaNegSelAPORT1YCH1 = VDAC_OPA_MUX_NEGSEL_APORT1YCH1, /**< APORT1YCH1 */ + opaNegSelAPORT1YCH3 = VDAC_OPA_MUX_NEGSEL_APORT1YCH3, /**< APORT1YCH3 */ + opaNegSelAPORT1YCH5 = VDAC_OPA_MUX_NEGSEL_APORT1YCH5, /**< APORT1YCH5 */ + opaNegSelAPORT1YCH7 = VDAC_OPA_MUX_NEGSEL_APORT1YCH7, /**< APORT1YCH7 */ + opaNegSelAPORT1YCH9 = VDAC_OPA_MUX_NEGSEL_APORT1YCH9, /**< APORT1YCH9 */ + opaNegSelAPORT1YCH11 = VDAC_OPA_MUX_NEGSEL_APORT1YCH11, /**< APORT1YCH11 */ + opaNegSelAPORT1YCH13 = VDAC_OPA_MUX_NEGSEL_APORT1YCH13, /**< APORT1YCH13 */ + opaNegSelAPORT1YCH15 = VDAC_OPA_MUX_NEGSEL_APORT1YCH15, /**< APORT1YCH15 */ + opaNegSelAPORT1YCH17 = VDAC_OPA_MUX_NEGSEL_APORT1YCH17, /**< APORT1YCH17 */ + opaNegSelAPORT1YCH19 = VDAC_OPA_MUX_NEGSEL_APORT1YCH19, /**< APORT1YCH19 */ + opaNegSelAPORT1YCH21 = VDAC_OPA_MUX_NEGSEL_APORT1YCH21, /**< APORT1YCH21 */ + opaNegSelAPORT1YCH23 = VDAC_OPA_MUX_NEGSEL_APORT1YCH23, /**< APORT1YCH23 */ + opaNegSelAPORT1YCH25 = VDAC_OPA_MUX_NEGSEL_APORT1YCH25, /**< APORT1YCH25 */ + opaNegSelAPORT1YCH27 = VDAC_OPA_MUX_NEGSEL_APORT1YCH27, /**< APORT1YCH27 */ + opaNegSelAPORT1YCH29 = VDAC_OPA_MUX_NEGSEL_APORT1YCH29, /**< APORT1YCH29 */ + opaNegSelAPORT1YCH31 = VDAC_OPA_MUX_NEGSEL_APORT1YCH31, /**< APORT1YCH31 */ + opaNegSelAPORT2YCH0 = VDAC_OPA_MUX_NEGSEL_APORT2YCH0, /**< APORT2YCH0 */ + opaNegSelAPORT2YCH2 = VDAC_OPA_MUX_NEGSEL_APORT2YCH2, /**< APORT2YCH2 */ + opaNegSelAPORT2YCH4 = VDAC_OPA_MUX_NEGSEL_APORT2YCH4, /**< APORT2YCH4 */ + opaNegSelAPORT2YCH6 = VDAC_OPA_MUX_NEGSEL_APORT2YCH6, /**< APORT2YCH6 */ + opaNegSelAPORT2YCH8 = VDAC_OPA_MUX_NEGSEL_APORT2YCH8, /**< APORT2YCH8 */ + opaNegSelAPORT2YCH10 = VDAC_OPA_MUX_NEGSEL_APORT2YCH10, /**< APORT2YCH10 */ + opaNegSelAPORT2YCH12 = VDAC_OPA_MUX_NEGSEL_APORT2YCH12, /**< APORT2YCH12 */ + opaNegSelAPORT2YCH14 = VDAC_OPA_MUX_NEGSEL_APORT2YCH14, /**< APORT2YCH14 */ + opaNegSelAPORT2YCH16 = VDAC_OPA_MUX_NEGSEL_APORT2YCH16, /**< APORT2YCH16 */ + opaNegSelAPORT2YCH18 = VDAC_OPA_MUX_NEGSEL_APORT2YCH18, /**< APORT2YCH18 */ + opaNegSelAPORT2YCH20 = VDAC_OPA_MUX_NEGSEL_APORT2YCH20, /**< APORT2YCH20 */ + opaNegSelAPORT2YCH22 = VDAC_OPA_MUX_NEGSEL_APORT2YCH22, /**< APORT2YCH22 */ + opaNegSelAPORT2YCH24 = VDAC_OPA_MUX_NEGSEL_APORT2YCH24, /**< APORT2YCH24 */ + opaNegSelAPORT2YCH26 = VDAC_OPA_MUX_NEGSEL_APORT2YCH26, /**< APORT2YCH26 */ + opaNegSelAPORT2YCH28 = VDAC_OPA_MUX_NEGSEL_APORT2YCH28, /**< APORT2YCH28 */ + opaNegSelAPORT2YCH30 = VDAC_OPA_MUX_NEGSEL_APORT2YCH30, /**< APORT2YCH30 */ + opaNegSelAPORT3YCH1 = VDAC_OPA_MUX_NEGSEL_APORT3YCH1, /**< APORT3YCH1 */ + opaNegSelAPORT3YCH3 = VDAC_OPA_MUX_NEGSEL_APORT3YCH3, /**< APORT3YCH3 */ + opaNegSelAPORT3YCH5 = VDAC_OPA_MUX_NEGSEL_APORT3YCH5, /**< APORT3YCH5 */ + opaNegSelAPORT3YCH7 = VDAC_OPA_MUX_NEGSEL_APORT3YCH7, /**< APORT3YCH7 */ + opaNegSelAPORT3YCH9 = VDAC_OPA_MUX_NEGSEL_APORT3YCH9, /**< APORT3YCH9 */ + opaNegSelAPORT3YCH11 = VDAC_OPA_MUX_NEGSEL_APORT3YCH11, /**< APORT3YCH11 */ + opaNegSelAPORT3YCH13 = VDAC_OPA_MUX_NEGSEL_APORT3YCH13, /**< APORT3YCH13 */ + opaNegSelAPORT3YCH15 = VDAC_OPA_MUX_NEGSEL_APORT3YCH15, /**< APORT3YCH15 */ + opaNegSelAPORT3YCH17 = VDAC_OPA_MUX_NEGSEL_APORT3YCH17, /**< APORT3YCH17 */ + opaNegSelAPORT3YCH19 = VDAC_OPA_MUX_NEGSEL_APORT3YCH19, /**< APORT3YCH19 */ + opaNegSelAPORT3YCH21 = VDAC_OPA_MUX_NEGSEL_APORT3YCH21, /**< APORT3YCH21 */ + opaNegSelAPORT3YCH23 = VDAC_OPA_MUX_NEGSEL_APORT3YCH23, /**< APORT3YCH23 */ + opaNegSelAPORT3YCH25 = VDAC_OPA_MUX_NEGSEL_APORT3YCH25, /**< APORT3YCH25 */ + opaNegSelAPORT3YCH27 = VDAC_OPA_MUX_NEGSEL_APORT3YCH27, /**< APORT3YCH27 */ + opaNegSelAPORT3YCH29 = VDAC_OPA_MUX_NEGSEL_APORT3YCH29, /**< APORT3YCH29 */ + opaNegSelAPORT3YCH31 = VDAC_OPA_MUX_NEGSEL_APORT3YCH31, /**< APORT3YCH31 */ + opaNegSelAPORT4YCH0 = VDAC_OPA_MUX_NEGSEL_APORT4YCH0, /**< APORT4YCH0 */ + opaNegSelAPORT4YCH2 = VDAC_OPA_MUX_NEGSEL_APORT4YCH2, /**< APORT4YCH2 */ + opaNegSelAPORT4YCH4 = VDAC_OPA_MUX_NEGSEL_APORT4YCH4, /**< APORT4YCH4 */ + opaNegSelAPORT4YCH6 = VDAC_OPA_MUX_NEGSEL_APORT4YCH6, /**< APORT4YCH6 */ + opaNegSelAPORT4YCH8 = VDAC_OPA_MUX_NEGSEL_APORT4YCH8, /**< APORT4YCH8 */ + opaNegSelAPORT4YCH10 = VDAC_OPA_MUX_NEGSEL_APORT4YCH10, /**< APORT4YCH10 */ + opaNegSelAPORT4YCH12 = VDAC_OPA_MUX_NEGSEL_APORT4YCH12, /**< APORT4YCH12 */ + opaNegSelAPORT4YCH14 = VDAC_OPA_MUX_NEGSEL_APORT4YCH14, /**< APORT4YCH14 */ + opaNegSelAPORT4YCH16 = VDAC_OPA_MUX_NEGSEL_APORT4YCH16, /**< APORT4YCH16 */ + opaNegSelAPORT4YCH18 = VDAC_OPA_MUX_NEGSEL_APORT4YCH18, /**< APORT4YCH18 */ + opaNegSelAPORT4YCH20 = VDAC_OPA_MUX_NEGSEL_APORT4YCH20, /**< APORT4YCH20 */ + opaNegSelAPORT4YCH22 = VDAC_OPA_MUX_NEGSEL_APORT4YCH22, /**< APORT4YCH22 */ + opaNegSelAPORT4YCH24 = VDAC_OPA_MUX_NEGSEL_APORT4YCH24, /**< APORT4YCH24 */ + opaNegSelAPORT4YCH26 = VDAC_OPA_MUX_NEGSEL_APORT4YCH26, /**< APORT4YCH26 */ + opaNegSelAPORT4YCH28 = VDAC_OPA_MUX_NEGSEL_APORT4YCH28, /**< APORT4YCH28 */ + opaNegSelAPORT4YCH30 = VDAC_OPA_MUX_NEGSEL_APORT4YCH30, /**< APORT4YCH30 */ + opaNegSelDisable = VDAC_OPA_MUX_NEGSEL_DISABLE, /**< Input disabled. */ + opaNegSelUnityGain = VDAC_OPA_MUX_NEGSEL_UG, /**< Unity gain feedback path. */ + opaNegSelResTap = VDAC_OPA_MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */ + opaNegSelNegPad = VDAC_OPA_MUX_NEGSEL_NEGPAD /**< Negative pad as input. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ } OPAMP_NegSel_TypeDef; /** OPAMP positive terminal input selection values. */ typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) opaPosSelDisable = DAC_OPA0MUX_POSSEL_DISABLE, /**< Input disabled. */ opaPosSelDac = DAC_OPA0MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */ opaPosSelPosPad = DAC_OPA0MUX_POSSEL_POSPAD, /**< Positive pad as input. */ opaPosSelOpaIn = DAC_OPA0MUX_POSSEL_OPA0INP, /**< Input from OPAx. */ opaPosSelResTapOpa0 = DAC_OPA0MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap from OPA0. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaPosSelAPORT1XCH0 = VDAC_OPA_MUX_POSSEL_APORT1XCH0, /**< APORT1XCH0 */ + opaPosSelAPORT1XCH2 = VDAC_OPA_MUX_POSSEL_APORT1XCH2, /**< APORT1XCH2 */ + opaPosSelAPORT1XCH4 = VDAC_OPA_MUX_POSSEL_APORT1XCH4, /**< APORT1XCH4 */ + opaPosSelAPORT1XCH6 = VDAC_OPA_MUX_POSSEL_APORT1XCH6, /**< APORT1XCH6 */ + opaPosSelAPORT1XCH8 = VDAC_OPA_MUX_POSSEL_APORT1XCH8, /**< APORT1XCH8 */ + opaPosSelAPORT1XCH10 = VDAC_OPA_MUX_POSSEL_APORT1XCH10, /**< APORT1XCH10 */ + opaPosSelAPORT1XCH12 = VDAC_OPA_MUX_POSSEL_APORT1XCH12, /**< APORT1XCH12 */ + opaPosSelAPORT1XCH14 = VDAC_OPA_MUX_POSSEL_APORT1XCH14, /**< APORT1XCH14 */ + opaPosSelAPORT1XCH16 = VDAC_OPA_MUX_POSSEL_APORT1XCH16, /**< APORT1XCH16 */ + opaPosSelAPORT1XCH18 = VDAC_OPA_MUX_POSSEL_APORT1XCH18, /**< APORT1XCH18 */ + opaPosSelAPORT1XCH20 = VDAC_OPA_MUX_POSSEL_APORT1XCH20, /**< APORT1XCH20 */ + opaPosSelAPORT1XCH22 = VDAC_OPA_MUX_POSSEL_APORT1XCH22, /**< APORT1XCH22 */ + opaPosSelAPORT1XCH24 = VDAC_OPA_MUX_POSSEL_APORT1XCH24, /**< APORT1XCH24 */ + opaPosSelAPORT1XCH26 = VDAC_OPA_MUX_POSSEL_APORT1XCH26, /**< APORT1XCH26 */ + opaPosSelAPORT1XCH28 = VDAC_OPA_MUX_POSSEL_APORT1XCH28, /**< APORT1XCH28 */ + opaPosSelAPORT1XCH30 = VDAC_OPA_MUX_POSSEL_APORT1XCH30, /**< APORT1XCH30 */ + opaPosSelAPORT2XCH1 = VDAC_OPA_MUX_POSSEL_APORT2XCH1, /**< APORT2XCH1 */ + opaPosSelAPORT2XCH3 = VDAC_OPA_MUX_POSSEL_APORT2XCH3, /**< APORT2XCH3 */ + opaPosSelAPORT2XCH5 = VDAC_OPA_MUX_POSSEL_APORT2XCH5, /**< APORT2XCH5 */ + opaPosSelAPORT2XCH7 = VDAC_OPA_MUX_POSSEL_APORT2XCH7, /**< APORT2XCH7 */ + opaPosSelAPORT2XCH9 = VDAC_OPA_MUX_POSSEL_APORT2XCH9, /**< APORT2XCH9 */ + opaPosSelAPORT2XCH11 = VDAC_OPA_MUX_POSSEL_APORT2XCH11, /**< APORT2XCH11 */ + opaPosSelAPORT2XCH13 = VDAC_OPA_MUX_POSSEL_APORT2XCH13, /**< APORT2XCH13 */ + opaPosSelAPORT2XCH15 = VDAC_OPA_MUX_POSSEL_APORT2XCH15, /**< APORT2XCH15 */ + opaPosSelAPORT2XCH17 = VDAC_OPA_MUX_POSSEL_APORT2XCH17, /**< APORT2XCH17 */ + opaPosSelAPORT2XCH19 = VDAC_OPA_MUX_POSSEL_APORT2XCH19, /**< APORT2XCH19 */ + opaPosSelAPORT2XCH21 = VDAC_OPA_MUX_POSSEL_APORT2XCH21, /**< APORT2XCH21 */ + opaPosSelAPORT2XCH23 = VDAC_OPA_MUX_POSSEL_APORT2XCH23, /**< APORT2XCH23 */ + opaPosSelAPORT2XCH25 = VDAC_OPA_MUX_POSSEL_APORT2XCH25, /**< APORT2XCH25 */ + opaPosSelAPORT2XCH27 = VDAC_OPA_MUX_POSSEL_APORT2XCH27, /**< APORT2XCH27 */ + opaPosSelAPORT2XCH29 = VDAC_OPA_MUX_POSSEL_APORT2XCH29, /**< APORT2XCH29 */ + opaPosSelAPORT2XCH31 = VDAC_OPA_MUX_POSSEL_APORT2XCH31, /**< APORT2XCH31 */ + opaPosSelAPORT3XCH0 = VDAC_OPA_MUX_POSSEL_APORT3XCH0, /**< APORT3XCH0 */ + opaPosSelAPORT3XCH2 = VDAC_OPA_MUX_POSSEL_APORT3XCH2, /**< APORT3XCH2 */ + opaPosSelAPORT3XCH4 = VDAC_OPA_MUX_POSSEL_APORT3XCH4, /**< APORT3XCH4 */ + opaPosSelAPORT3XCH6 = VDAC_OPA_MUX_POSSEL_APORT3XCH6, /**< APORT3XCH6 */ + opaPosSelAPORT3XCH8 = VDAC_OPA_MUX_POSSEL_APORT3XCH8, /**< APORT3XCH8 */ + opaPosSelAPORT3XCH10 = VDAC_OPA_MUX_POSSEL_APORT3XCH10, /**< APORT3XCH10 */ + opaPosSelAPORT3XCH12 = VDAC_OPA_MUX_POSSEL_APORT3XCH12, /**< APORT3XCH12 */ + opaPosSelAPORT3XCH14 = VDAC_OPA_MUX_POSSEL_APORT3XCH14, /**< APORT3XCH14 */ + opaPosSelAPORT3XCH16 = VDAC_OPA_MUX_POSSEL_APORT3XCH16, /**< APORT3XCH16 */ + opaPosSelAPORT3XCH18 = VDAC_OPA_MUX_POSSEL_APORT3XCH18, /**< APORT3XCH18 */ + opaPosSelAPORT3XCH20 = VDAC_OPA_MUX_POSSEL_APORT3XCH20, /**< APORT3XCH20 */ + opaPosSelAPORT3XCH22 = VDAC_OPA_MUX_POSSEL_APORT3XCH22, /**< APORT3XCH22 */ + opaPosSelAPORT3XCH24 = VDAC_OPA_MUX_POSSEL_APORT3XCH24, /**< APORT3XCH24 */ + opaPosSelAPORT3XCH26 = VDAC_OPA_MUX_POSSEL_APORT3XCH26, /**< APORT3XCH26 */ + opaPosSelAPORT3XCH28 = VDAC_OPA_MUX_POSSEL_APORT3XCH28, /**< APORT3XCH28 */ + opaPosSelAPORT3XCH30 = VDAC_OPA_MUX_POSSEL_APORT3XCH30, /**< APORT3XCH30 */ + opaPosSelAPORT4XCH1 = VDAC_OPA_MUX_POSSEL_APORT4XCH1, /**< APORT4XCH1 */ + opaPosSelAPORT4XCH3 = VDAC_OPA_MUX_POSSEL_APORT4XCH3, /**< APORT4XCH3 */ + opaPosSelAPORT4XCH5 = VDAC_OPA_MUX_POSSEL_APORT4XCH5, /**< APORT4XCH5 */ + opaPosSelAPORT4XCH7 = VDAC_OPA_MUX_POSSEL_APORT4XCH7, /**< APORT4XCH7 */ + opaPosSelAPORT4XCH9 = VDAC_OPA_MUX_POSSEL_APORT4XCH9, /**< APORT4XCH9 */ + opaPosSelAPORT4XCH11 = VDAC_OPA_MUX_POSSEL_APORT4XCH11, /**< APORT4XCH11 */ + opaPosSelAPORT4XCH13 = VDAC_OPA_MUX_POSSEL_APORT4XCH13, /**< APORT4XCH13 */ + opaPosSelAPORT4XCH15 = VDAC_OPA_MUX_POSSEL_APORT4XCH15, /**< APORT4XCH15 */ + opaPosSelAPORT4XCH17 = VDAC_OPA_MUX_POSSEL_APORT4XCH17, /**< APORT4XCH17 */ + opaPosSelAPORT4XCH19 = VDAC_OPA_MUX_POSSEL_APORT4XCH19, /**< APORT4XCH19 */ + opaPosSelAPORT4XCH21 = VDAC_OPA_MUX_POSSEL_APORT4XCH21, /**< APORT4XCH21 */ + opaPosSelAPORT4XCH23 = VDAC_OPA_MUX_POSSEL_APORT4XCH23, /**< APORT4XCH23 */ + opaPosSelAPORT4XCH25 = VDAC_OPA_MUX_POSSEL_APORT4XCH25, /**< APORT4XCH25 */ + opaPosSelAPORT4XCH27 = VDAC_OPA_MUX_POSSEL_APORT4XCH27, /**< APORT4XCH27 */ + opaPosSelAPORT4XCH29 = VDAC_OPA_MUX_POSSEL_APORT4XCH29, /**< APORT4XCH29 */ + opaPosSelAPORT4XCH31 = VDAC_OPA_MUX_POSSEL_APORT4XCH31, /**< APORT4XCH31 */ + opaPosSelDisable = VDAC_OPA_MUX_POSSEL_DISABLE, /**< Input disabled. */ + opaPosSelDac = VDAC_OPA_MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */ + opaPosSelPosPad = VDAC_OPA_MUX_POSSEL_POSPAD, /**< Positive pad as input. */ + opaPosSelOpaIn = VDAC_OPA_MUX_POSSEL_OPANEXT, /**< Input from OPAx. */ + opaPosSelResTap = VDAC_OPA_MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ } OPAMP_PosSel_TypeDef; /** OPAMP output terminal selection values. */ typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) opaOutModeDisable = DAC_OPA0MUX_OUTMODE_DISABLE, /**< OPA output disabled. */ opaOutModeMain = DAC_OPA0MUX_OUTMODE_MAIN, /**< Main output to pin enabled. */ opaOutModeAlt = DAC_OPA0MUX_OUTMODE_ALT, /**< Alternate output(s) enabled (not OPA2). */ opaOutModeAll = DAC_OPA0MUX_OUTMODE_ALL /**< Both main and alternate enabled (not OPA2). */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaOutModeDisable = 0, /**< OPA output disabled. */ + opaOutModeMain = VDAC_OPA_OUT_MAINOUTEN, /**< Main output to pin enabled. */ + opaOutModeAlt = VDAC_OPA_OUT_ALTOUTEN, /**< Alternate output(s) enabled (not OPA2). */ + opaOutModeAll = VDAC_OPA_OUT_SHORT, /**< Both main and alternate enabled (not OPA2). */ + opaOutModeAPORT1YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1), /**< APORT output to APORT1YCH1 pin enabled. */ + opaOutModeAPORT1YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3), /**< APORT output to APORT1YCH3 pin enabled. */ + opaOutModeAPORT1YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5), /**< APORT output to APORT1YCH5 pin enabled. */ + opaOutModeAPORT1YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7), /**< APORT output to APORT1YCH7 pin enabled. */ + opaOutModeAPORT1YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9), /**< APORT output to APORT1YCH9 pin enabled. */ + opaOutModeAPORT1YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11), /**< APORT output to APORT1YCH11 pin enabled. */ + opaOutModeAPORT1YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13), /**< APORT output to APORT1YCH13 pin enabled. */ + opaOutModeAPORT1YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15), /**< APORT output to APORT1YCH15 pin enabled. */ + opaOutModeAPORT1YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17), /**< APORT output to APORT1YCH17 pin enabled. */ + opaOutModeAPORT1YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19), /**< APORT output to APORT1YCH19 pin enabled. */ + opaOutModeAPORT1YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21), /**< APORT output to APORT1YCH21 pin enabled. */ + opaOutModeAPORT1YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23), /**< APORT output to APORT1YCH23 pin enabled. */ + opaOutModeAPORT1YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25), /**< APORT output to APORT1YCH25 pin enabled. */ + opaOutModeAPORT1YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27), /**< APORT output to APORT1YCH27 pin enabled. */ + opaOutModeAPORT1YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29), /**< APORT output to APORT1YCH29 pin enabled. */ + opaOutModeAPORT1YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31), /**< APORT output to APORT1YCH31 pin enabled. */ + opaOutModeAPORT2YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0), /**< APORT output to APORT2YCH0 pin enabled. */ + opaOutModeAPORT2YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2), /**< APORT output to APORT2YCH2 pin enabled. */ + opaOutModeAPORT2YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4), /**< APORT output to APORT2YCH4 pin enabled. */ + opaOutModeAPORT2YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6), /**< APORT output to APORT2YCH6 pin enabled. */ + opaOutModeAPORT2YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8), /**< APORT output to APORT2YCH8 pin enabled. */ + opaOutModeAPORT2YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10), /**< APORT output to APORT2YCH10 pin enabled. */ + opaOutModeAPORT2YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12), /**< APORT output to APORT2YCH12 pin enabled. */ + opaOutModeAPORT2YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14), /**< APORT output to APORT2YCH14 pin enabled. */ + opaOutModeAPORT2YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16), /**< APORT output to APORT2YCH16 pin enabled. */ + opaOutModeAPORT2YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18), /**< APORT output to APORT2YCH18 pin enabled. */ + opaOutModeAPORT2YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20), /**< APORT output to APORT2YCH20 pin enabled. */ + opaOutModeAPORT2YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22), /**< APORT output to APORT2YCH22 pin enabled. */ + opaOutModeAPORT2YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24), /**< APORT output to APORT2YCH24 pin enabled. */ + opaOutModeAPORT2YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26), /**< APORT output to APORT2YCH26 pin enabled. */ + opaOutModeAPORT2YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28), /**< APORT output to APORT2YCH28 pin enabled. */ + opaOutModeAPORT2YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30), /**< APORT output to APORT2YCH30 pin enabled. */ + opaOutModeAPORT3YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1), /**< APORT output to APORT3YCH1 pin enabled. */ + opaOutModeAPORT3YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3), /**< APORT output to APORT3YCH3 pin enabled. */ + opaOutModeAPORT3YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5), /**< APORT output to APORT3YCH5 pin enabled. */ + opaOutModeAPORT3YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7), /**< APORT output to APORT3YCH7 pin enabled. */ + opaOutModeAPORT3YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9), /**< APORT output to APORT3YCH9 pin enabled. */ + opaOutModeAPORT3YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11), /**< APORT output to APORT3YCH11 pin enabled. */ + opaOutModeAPORT3YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13), /**< APORT output to APORT3YCH13 pin enabled. */ + opaOutModeAPORT3YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15), /**< APORT output to APORT3YCH15 pin enabled. */ + opaOutModeAPORT3YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17), /**< APORT output to APORT3YCH17 pin enabled. */ + opaOutModeAPORT3YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19), /**< APORT output to APORT3YCH19 pin enabled. */ + opaOutModeAPORT3YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21), /**< APORT output to APORT3YCH21 pin enabled. */ + opaOutModeAPORT3YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23), /**< APORT output to APORT3YCH23 pin enabled. */ + opaOutModeAPORT3YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25), /**< APORT output to APORT3YCH25 pin enabled. */ + opaOutModeAPORT3YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27), /**< APORT output to APORT3YCH27 pin enabled. */ + opaOutModeAPORT3YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29), /**< APORT output to APORT3YCH29 pin enabled. */ + opaOutModeAPORT3YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31), /**< APORT output to APORT3YCH31 pin enabled. */ + opaOutModeAPORT4YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0), /**< APORT output to APORT4YCH0 pin enabled. */ + opaOutModeAPORT4YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2), /**< APORT output to APORT4YCH2 pin enabled. */ + opaOutModeAPORT4YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4), /**< APORT output to APORT4YCH4 pin enabled. */ + opaOutModeAPORT4YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6), /**< APORT output to APORT4YCH6 pin enabled. */ + opaOutModeAPORT4YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8), /**< APORT output to APORT4YCH8 pin enabled. */ + opaOutModeAPORT4YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10), /**< APORT output to APORT4YCH10 pin enabled. */ + opaOutModeAPORT4YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12), /**< APORT output to APORT4YCH12 pin enabled. */ + opaOutModeAPORT4YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14), /**< APORT output to APORT4YCH14 pin enabled. */ + opaOutModeAPORT4YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16), /**< APORT output to APORT4YCH16 pin enabled. */ + opaOutModeAPORT4YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18), /**< APORT output to APORT4YCH18 pin enabled. */ + opaOutModeAPORT4YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20), /**< APORT output to APORT4YCH20 pin enabled. */ + opaOutModeAPORT4YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22), /**< APORT output to APORT4YCH22 pin enabled. */ + opaOutModeAPORT4YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24), /**< APORT output to APORT4YCH24 pin enabled. */ + opaOutModeAPORT4YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26), /**< APORT output to APORT4YCH26 pin enabled. */ + opaOutModeAPORT4YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28), /**< APORT output to APORT4YCH28 pin enabled. */ + opaOutModeAPORT4YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30), /**< APORT output to APORT4YCH30 pin enabled. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ } OPAMP_OutMode_TypeDef; /** OPAMP gain values. */ typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) opaResSelDefault = DAC_OPA0MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */ opaResSelR2eq0_33R1 = DAC_OPA0MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */ opaResSelR2eqR1 = DAC_OPA0MUX_RESSEL_RES1, /**< R2 = R1 */ @@ -113,18 +338,94 @@ typedef enum opaResSelR2eq4_33R1 = DAC_OPA0MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */ opaResSelR2eq7R1 = DAC_OPA0MUX_RESSEL_RES6, /**< R2 = 7 * R1 */ opaResSelR2eq15R1 = DAC_OPA0MUX_RESSEL_RES7 /**< R2 = 15 * R1 */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaResSelDefault = VDAC_OPA_MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */ + opaResSelR2eq0_33R1 = VDAC_OPA_MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */ + opaResSelR2eqR1 = VDAC_OPA_MUX_RESSEL_RES1, /**< R2 = R1 */ + opaResSelR1eq1_67R1 = VDAC_OPA_MUX_RESSEL_RES2, /**< R2 = 1.67 R1 */ + opaResSelR2eq2_2R1 = VDAC_OPA_MUX_RESSEL_RES3, /**< R2 = 2.2 * R1 */ + opaResSelR2eq3R1 = VDAC_OPA_MUX_RESSEL_RES4, /**< R2 = 3 * R1 */ + opaResSelR2eq4_33R1 = VDAC_OPA_MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */ + opaResSelR2eq7R1 = VDAC_OPA_MUX_RESSEL_RES6, /**< R2 = 7 * R1 */ + opaResSelR2eq15R1 = VDAC_OPA_MUX_RESSEL_RES7 /**< R2 = 15 * R1 */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ } OPAMP_ResSel_TypeDef; /** OPAMP resistor ladder input selector values. */ typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) opaResInMuxDisable = DAC_OPA0MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */ opaResInMuxOpaIn = DAC_OPA0MUX_RESINMUX_OPA0INP, /**< Input from OPAx. */ opaResInMuxNegPad = DAC_OPA0MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */ opaResInMuxPosPad = DAC_OPA0MUX_RESINMUX_POSPAD, /**< Input from positive pad. */ opaResInMuxVss = DAC_OPA0MUX_RESINMUX_VSS /**< Input connected to Vss. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaResInMuxDisable = VDAC_OPA_MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */ + opaResInMuxOpaIn = VDAC_OPA_MUX_RESINMUX_OPANEXT, /**< Input from OPAx. */ + opaResInMuxNegPad = VDAC_OPA_MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */ + opaResInMuxPosPad = VDAC_OPA_MUX_RESINMUX_POSPAD, /**< Input from positive pad. */ + opaResInMuxComPad = VDAC_OPA_MUX_RESINMUX_COMPAD, /**< Input from negative pad of OPA0. + Direct input to support common reference. */ + opaResInMuxCenter = VDAC_OPA_MUX_RESINMUX_CENTER, /**< OPA0 and OPA1 Resmux connected to form fully + differential instrumentation amplifier. */ + opaResInMuxVss = VDAC_OPA_MUX_RESINMUX_VSS, /**< Input connected to Vss. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ } OPAMP_ResInMux_TypeDef; +#if defined(_SILICON_LABS_32B_SERIES_1) +typedef enum +{ + opaPrsModeDefault = VDAC_OPA_CTRL_PRSMODE_DEFAULT, /**< Default value when PRS is not the trigger. */ + opaPrsModePulsed = VDAC_OPA_CTRL_PRSMODE_PULSED, /**< PRS trigger is a pulse that starts the OPAMP + warmup sequence. The end of the warmup sequence + is controlled by timeout settings in OPAxTIMER. */ + opaPrsModeTimed = VDAC_OPA_CTRL_PRSMODE_TIMED, /**< PRS trigger is a pulse long enough to provide the + OPAMP warmup sequence. The end of the warmup + sequence is controlled by the edge of the pulse. */ +} OPAMP_PrsMode_TypeDef; + +typedef enum +{ + opaPrsSelDefault = VDAC_OPA_CTRL_PRSSEL_DEFAULT, /**< Default value when PRS is not the trigger. */ + opaPrsSelCh0 = VDAC_OPA_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0 triggers OPAMP. */ + opaPrsSelCh1 = VDAC_OPA_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1 triggers OPAMP. */ + opaPrsSelCh2 = VDAC_OPA_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2 triggers OPAMP. */ + opaPrsSelCh3 = VDAC_OPA_CTRL_PRSSEL_PRSCH3, /**< PRS channel 3 triggers OPAMP. */ + opaPrsSelCh4 = VDAC_OPA_CTRL_PRSSEL_PRSCH4, /**< PRS channel 4 triggers OPAMP. */ + opaPrsSelCh5 = VDAC_OPA_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5 triggers OPAMP. */ + opaPrsSelCh6 = VDAC_OPA_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6 triggers OPAMP. */ + opaPrsSelCh7 = VDAC_OPA_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7 triggers OPAMP. */ + opaPrsSelCh8 = VDAC_OPA_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8 triggers OPAMP. */ + opaPrsSelCh9 = VDAC_OPA_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9 triggers OPAMP. */ + opaPrsSelCh10 = VDAC_OPA_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10 triggers OPAMP. */ + opaPrsSelCh11 = VDAC_OPA_CTRL_PRSSEL_PRSCH11, /**< PRS channel 11 triggers OPAMP. */ +} OPAMP_PrsSel_TypeDef; + +typedef enum +{ + opaPrsOutDefault = VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT, /**< Default value. */ + opaPrsOutWarm = VDAC_OPA_CTRL_PRSOUTMODE_WARM, /**< Warm status available on PRS. */ + opaPrsOutOutValid = VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID, /**< Outvalid status available on PRS. */ +} OPAMP_PrsOut_TypeDef; + +typedef enum +{ + opaOutScaleDefault = VDAC_OPA_CTRL_OUTSCALE_DEFAULT, /**< Default OPAM output drive strength. */ + opaOutScaleFull = VDAC_OPA_CTRL_OUTSCALE_FULL, /**< OPAMP uses full output drive strength. */ + opaOutSacleHalf = VDAC_OPA_CTRL_OUTSCALE_HALF, /**< OPAMP uses half output drive strength. */ +} OPAMP_OutScale_Typedef; + +typedef enum +{ + opaDrvStrDefault = VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT, /**< Default value. */ + opaDrvStrLowerAccLowStr = (0 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Lower accuracy with low drive stregth. */ + opaDrvStrLowAccLowStr = (1 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Low accuracy with low drive stregth. */ + opaDrvStrHighAccHighStr = (2 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< High accuracy with high drive stregth. */ + opaDrvStrHigherAccHighStr = (3 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Higher accuracy with high drive stregth. */ +} OPAMP_DrvStr_Typedef; +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ + /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ @@ -139,6 +440,7 @@ typedef struct OPAMP_ResInMux_TypeDef resInMux; /**< Select input source for resistor ladder. */ uint32_t outPen; /**< Alternate output enable bit mask. This value should consist of one or more of the + @if DOXYDOC_P1_DEVICE DAC_OPA[opa#]MUX_OUTPEN_OUT[output#] flags (defined in \_dac.h) OR'ed together. @n @n @@ -163,7 +465,24 @@ typedef struct E.g: @n init.outPen = DAC_OPA0MUX_OUTPEN_OUT0 | DAC_OPA0MUX_OUTPEN_OUT2 | - DAC_OPA0MUX_OUTPEN_OUT4; */ + DAC_OPA0MUX_OUTPEN_OUT4; + + @elseif DOXYDOC_P2_DEVICE + VDAC_OPA_OUT_ALTOUTPADEN_OUT[output#] flags + (defined in \_vdac.h) OR'ed together. + @n @n + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT0 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT1 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT2 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT3 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT4 + + E.g: @n + init.outPen = VDAC_OPA_OUT_ALTOUTPADEN_OUT0 | + VDAC_OPA_OUT_ALTOUTPADEN_OUT2 | + VDAC_OPA_OUT_ALTOUTPADEN_OUT4; + @endif */ +#if defined(_SILICON_LABS_32B_SERIES_0) uint32_t bias; /**< Set OPAMP bias current. */ bool halfBias; /**< Divide OPAMP bias current by 2. */ bool lpfPosPadDisable; /**< Disable low pass filter on positive pad. */ @@ -174,9 +493,34 @@ typedef struct bool shortInputs; /**< Short OPAMP input terminals. */ bool hcmDisable; /**< Disable input rail-to-rail capability. */ bool defaultOffset; /**< Use factory calibrated opamp offset value. */ - uint32_t offset; /**< Opamp offset value when @ref defaultOffset is false.*/ + uint32_t offset; /**< Opamp offset value when @ref defaultOffset is + false. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + OPAMP_DrvStr_Typedef drvStr; /**< OPAx operation mode. */ + bool gain3xEn; /**< Enable 3x gain resistor ladder. */ + bool halfDrvStr; /**< Half or full output drive strength. */ + bool ugBwScale; /**< Unity gain bandwidth scaled by factor of 2.5. */ + bool prsEn; /**< Enable PRS as OPAMP trigger. */ + OPAMP_PrsMode_TypeDef prsMode; /**< Selects PRS trigger mode. */ + OPAMP_PrsSel_TypeDef prsSel; /**< PRS channel trigger select. */ + OPAMP_PrsOut_TypeDef prsOutSel; /**< PRS output select. */ + bool aportYMasterDisable; /**< Disable bus master request on APORT Y. */ + bool aportXMasterDisable; /**< Disable bus master request on APORT X. */ + uint32_t settleTime; /**< Number of clock cycles to drive the output. */ + uint32_t startupDly; /**< OPAx startup delay in us. */ + bool hcmDisable; /**< Disable input rail-to-rail capability. */ + bool defaultOffsetN; /**< Use factory calibrated opamp inverting input + offset value. */ + uint32_t offsetN; /**< Opamp inverting input offset value when + @ref defaultOffsetInv is false. */ + bool defaultOffsetP; /**< Use factory calibrated opamp non-inverting + input offset value. */ + uint32_t offsetP; /**< Opamp non-inverting input offset value when + @ref defaultOffsetNon is false. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_1) */ } OPAMP_Init_TypeDef; +#if defined(_SILICON_LABS_32B_SERIES_0) /** Configuration of OPA0/1 in unity gain voltage follower mode. */ #define OPA_INIT_UNITY_GAIN \ { \ @@ -551,12 +895,468 @@ typedef struct 0 /* Opamp offset value (not used). */ \ } +#elif defined(_SILICON_LABS_32B_SERIES_1) +/** Configuration of OPA in unity gain voltage follower mode. */ +#define OPA_INIT_UNITY_GAIN \ +{ \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Resistor ladder disabled. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA in non-inverting amplifier mode. */ +#define OPA_INIT_NON_INVERTING \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA in inverting amplifier mode. */ +#define OPA_INIT_INVERTING \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA0 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA1 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelOpaIn, /* Pos input from OPA0 output. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA2 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelOpaIn, /* Pos input from OPA1 output. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA0 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA0 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA1 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA1 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA2 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA2 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA0 in two-opamp differential driver mode. */ +#define OPA_INIT_DIFF_DRIVER_OPA0 \ +{ \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Resistor ladder disabled. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA1 in two-opamp differential driver mode. */ +#define OPA_INIT_DIFF_DRIVER_OPA1 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA0 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA0 \ +{ \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA1 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA1 \ +{ \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Disable resistor ladder. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA2 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA2 \ +{ \ + opaNegSelResTap, /* Input from resistor ladder tap. */ \ + opaPosSelResTap, /* Input from OPA0 resistor ladder tap. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA0 in two-opamp instrumentation amplifier mode. */ +#define OPA_INIT_INSTR_AMP_OPA0 \ +{ \ + opaNegSelResTap, /* Input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA1 in two-opamp instrumentation amplifier mode. */ +#define OPA_INIT_INSTR_AMP_OPA1 \ +{ \ + opaNegSelNegPad, /* Neg input from pad. */ \ + opaPosSelResTap, /* Input from resistor ladder tap. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ + /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ +#if defined(_SILICON_LABS_32B_SERIES_0) void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa); void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init); +#elif defined(_SILICON_LABS_32B_SERIES_1) +void OPAMP_Disable(VDAC_TypeDef *dac, OPAMP_TypeDef opa); +void OPAMP_Enable(VDAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init); +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ /** @} (end addtogroup OPAMP) */ /** @} (end addtogroup emlib) */ @@ -565,5 +1365,6 @@ void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_Typ } #endif -#endif /* defined( OPAMP_PRESENT ) && ( OPAMP_COUNT == 1 ) */ +#endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) + || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */ #endif /* EM_OPAMP_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h index c2a7b95c50..7dabb41427 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_pcnt.h * @brief Pulse Counter (PCNT) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h index 26306b70c4..1d995a7df6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_prs.h * @brief Peripheral Reflex System (PRS) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ramfunc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ramfunc.h index 51dee93b30..5476c265bb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ramfunc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ramfunc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_ramfunc.h * @brief RAM code support. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h index 81404cdcda..f8ea76bbe7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_rmu.h * @brief Reset Management Unit (RMU) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h index c3cb033095..14b28ed06c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_rtc.h * @brief Real Time Counter (RTC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtcc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtcc.h index 3f6789a1cd..388a69ff48 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtcc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtcc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file * @brief Real Time Counter (RTCC) peripheral API. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -53,6 +53,21 @@ extern "C" { * @{ ******************************************************************************/ +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) +/* Enable fix for errata "RTCC_E203 - Potential Stability Issue with RTCC + * Registers". */ +#define ERRATA_FIX_RTCC_E203 +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) +/* Enable fix for errata "RTCC_E204 - Disabling the RTCC Backup RAM may consume extra + * current". */ +#define ERRATA_FIX_RTCC_E204 +#endif +/** @endcond */ + /******************************************************************************* ********************************* ENUM ************************************ ******************************************************************************/ @@ -588,7 +603,26 @@ __STATIC_INLINE void RTCC_IntSet( uint32_t flags ) ******************************************************************************/ __STATIC_INLINE void RTCC_Lock( void ) { +#if defined(ERRATA_FIX_RTCC_E203) + /* RTCC_E203 - Potential Stability Issue with RTCC Registers + * RTCC_LOCK register must be modified while RTCC clock is disabled. */ + uint32_t lfeReg = CMU->LFECLKEN0; + bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED); + if (cmuLocked) + { + CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; + } + CMU->LFECLKEN0 = 0x0; +#endif RTCC->LOCK = RTCC_LOCK_LOCKKEY_LOCK; +#if defined(ERRATA_FIX_RTCC_E203) + /* Restore clock state after RTCC_E203 fix. */ + CMU->LFECLKEN0 = lfeReg; + if (cmuLocked) + { + CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; + } +#endif } /***************************************************************************//** @@ -626,7 +660,11 @@ void RTCC_Reset( void ); ******************************************************************************/ __STATIC_INLINE void RTCC_RetentionRamPowerDown( void ) { +#if !defined(ERRATA_FIX_RTCC_E204) + /* Devices that are affected by RTCC_E204 should always keep the RTCC + * backup RAM retained. */ RTCC->POWERDOWN = RTCC_POWERDOWN_RAM; +#endif } void RTCC_StatusClear( void ); @@ -682,7 +720,26 @@ __STATIC_INLINE void RTCC_TimeSet( uint32_t time ) ******************************************************************************/ __STATIC_INLINE void RTCC_Unlock( void ) { +#if defined(ERRATA_FIX_RTCC_E203) + /* RTCC_E203 - Potential Stability Issue with RTCC Registers + * RTCC_LOCK register must be modified while RTCC clock is disabled. */ + uint32_t lfeReg = CMU->LFECLKEN0; + bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED); + if (cmuLocked) + { + CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; + } + CMU->LFECLKEN0 = 0x0; +#endif RTCC->LOCK = RTCC_LOCK_LOCKKEY_UNLOCK; +#if defined(ERRATA_FIX_RTCC_E203) + /* Restore clock state after RTCC_E203 fix. */ + CMU->LFECLKEN0 = lfeReg; + if (cmuLocked) + { + CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; + } +#endif } /** @} (end addtogroup RTCC) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h new file mode 100644 index 0000000000..140bc825fd --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h @@ -0,0 +1,466 @@ +/***************************************************************************//** + * @file em_smu.h + * @brief Security Management Unit (SMU) peripheral API + * @version 5.1.2 + ******************************************************************************* + * @section License + * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************* + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + +#ifndef EM_SMU_H +#define EM_SMU_H + +#include "em_device.h" +#if defined(SMU_COUNT) && (SMU_COUNT > 0) + +#include "em_assert.h" +#include "em_bus.h" + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup SMU + * @brief Security Management Unit (SMU) Peripheral API + * + * @details + * The Security Management Unit (SMU) forms the control and status/reporting + * component of bus-level security in EFM32/EFR32 devices. + * + * Peripheral-level protection is provided via the peripheral protection unit + * (PPU). The PPU provides a hardware access barrier to any peripheral that is + * configured to be protected. When an attempt is made to access a peripheral + * without the required privilege/security level, the PPU detects the fault + * and intercepts the access. No write or read of the peripheral register + * space occurs, and an all-zero value is returned if the access is a read. + * + * @subsection Usage example + * @include em_smu_init.c + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** SMU peripheral identifiers. */ +typedef enum { + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */ + smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1 */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */ + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */ + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */ + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */ + smuPeripheralPCNT1 = _SMU_PPUPATD0_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1 */ + smuPeripheralPCNT2 = _SMU_PPUPATD0_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2 */ + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */ + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */ + smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3 */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */ + smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1 */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */ + smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1 */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */ + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */ + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */ + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */ + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */ + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */ + +#else +#error "No peripherals defined for SMU for this device configuration." +#endif + smuPeripheralEnd +} SMU_Peripheral_TypeDef; + +/** SMU peripheral privileged access enablers. */ +typedef struct { + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */ + bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1 */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH */ + bool privilegedReserved3 : 1; /**< Reserved privileged access enabler */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0 */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */ + bool privilegedReserved4 : 1; /**< Reserved privileged access enabler */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */ + bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1 */ + bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2 */ + bool privilegedReserved5 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved6 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved7 : 1; /**< Reserved privileged access enabler */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedReserved8 : 1; /**< Reserved privileged access enabler */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */ + bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */ + bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1 */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */ + bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1 */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH */ + bool privilegedReserved3 : 1; /**< Reserved privileged access enabler */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0 */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */ + bool privilegedReserved4 : 1; /**< Reserved privileged access enabler */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */ + bool privilegedReserved5 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved6 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved7 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved8 : 1; /**< Reserved privileged access enabler */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedReserved9 : 1; /**< Reserved privileged access enabler */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */ + +#else +#error "No peripherals defined for SMU for this device configuration" +#endif +} SMU_PrivilegedAccess_TypeDef; + +/******************************************************************************* + ****************************** STRUCTS ************************************ + ******************************************************************************/ + +/** SMU initialization structure. */ +typedef struct { + union { + uint32_t reg[2]; /**< Periperal access control array.*/ + SMU_PrivilegedAccess_TypeDef access; /**< Periperal access control array.*/ + } ppu; + bool enable; /**< SMU enable flag, when set SMU_Init() will enable SMU.*/ +} SMU_Init_TypeDef; + +#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID > 80) +/** Default SMU initialization struct settings. */ +#define SMU_INIT_DEFAULT { \ + {{0}}, /* No peripherals acsess protected. */ \ + true /* Enable SMU.*/ \ +} +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Enable or disable the Peripheral Protection Unit of the SMU. + * + * @param[in] enable + * True if the PPU should be enabled, false if it should be disabled. + ******************************************************************************/ +__STATIC_INLINE void SMU_EnablePPU(bool enable) +{ + BUS_RegBitWrite(&SMU->PPUCTRL, _SMU_PPUCTRL_ENABLE_SHIFT, enable); +} + +/***************************************************************************//** + * @brief + * Initialize the Peripheral Protection Unit of the SMU. + * + * @param[in] init + * Pointer to initialization struct defining which peripherals should only + * be accessed from privileged mode, and whether the PPU should be enabled. + ******************************************************************************/ +__STATIC_INLINE void SMU_Init(const SMU_Init_TypeDef *init) +{ + SMU->PPUPATD0 = init->ppu.reg[0]; + SMU->PPUPATD1 = init->ppu.reg[1]; + + SMU_EnablePPU(init->enable); +} + +/***************************************************************************//** + * @brief + * Change the access settings for a peripheral + * + * @details + * Set whether the peripheral can only be accessed from privileged mode + * + * @param[in] peripheral + * ID of the peripheral to change access settings for + * + * @param[in] privileged + * True if the peripheral should only be allowed to be accessed from + * privileged mode, false if the peripheral can be accessed from unprivileged + * mode. + ******************************************************************************/ +__STATIC_INLINE void SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral, + bool privileged) +{ + EFM_ASSERT(peripheral < smuPeripheralEnd); + + if (peripheral < 32) { + BUS_RegBitWrite(&SMU->PPUPATD0, peripheral, privileged); + } else { + BUS_RegBitWrite(&SMU->PPUPATD1, peripheral - 32, privileged); + } +} + +/***************************************************************************//** + * @brief + * Get the ID of the peripheral that caused an access fault. + * + * @note + * The return value is only valid if the @ref SMU_IF_PPUPRIV interrupt flag + * is set. + * + * @return + * ID of the faulting peripheral. + ******************************************************************************/ +__STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral(void) +{ + return (SMU_Peripheral_TypeDef)SMU->PPUFS; +} + +/***************************************************************************//** + * @brief + * Clear one or more pending SMU interrupts. + * + * @param[in] flags + * Bitwise logic OR of SMU interrupt sources to clear. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntClear(uint32_t flags) +{ + SMU->IFC = flags; +} + +/***************************************************************************//** + * @brief + * Disable one or more SMU interrupts. + * + * @param[in] flags + * SMU interrupt sources to disable. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntDisable(uint32_t flags) +{ + SMU->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more SMU interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using SMU_IntClear() prior to enabling + * if such a pending interrupt should be ignored. + * + * @param[in] flags + * SMU interrupt sources to enable. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntEnable(uint32_t flags) +{ + SMU->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending SMU interrupts. + * + * @return + * SMU interrupt sources pending. + ******************************************************************************/ +__STATIC_INLINE uint32_t SMU_IntGet(void) +{ + return SMU->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending SMU interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled SMU interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in SMU_IEN register + * and + * - the OR combination of valid interrupt flags in SMU_IF register. + ******************************************************************************/ +__STATIC_INLINE uint32_t SMU_IntGetEnabled(void) +{ + uint32_t tmp; + + // Store SMU->IEN in temporary variable in order to define explicit order + // of volatile accesses. + tmp = SMU->IEN; + + // Bitwise AND of pending and enabled interrupts + return SMU->IF & tmp; +} + +/************************************************************************Æ**//** + * @brief + * Set one or more pending SMU interrupts from SW. + * + * @param[in] flags + * SMU interrupt sources to set to pending. + *************************************************************************Æ****/ +__STATIC_INLINE void SMU_IntSet(uint32_t flags) +{ + SMU->IFS = flags; +} + +/** @} (end addtogroup SMU) */ +/** @} (end addtogroup emlib) */ + +#ifdef __cplusplus +} +#endif + +#endif // defined(SMU_COUNT) && (SMU_COUNT > 0) +#endif // EM_SMU_H diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h index 34810a81c0..84d2049edd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_system.h * @brief System API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -86,10 +86,22 @@ typedef enum systemPartFamilyEfm32Happy = _DEVINFO_PART_DEVICE_FAMILY_EFM32HG, /**< EFM32 Happy Gecko Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B) - systemPartFamilyEfm32Pearl1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B, /**< EFM32 Pearl Gecko Gen1 Basic Device Family */ + systemPartFamilyEfm32Pearl1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B, /**< EFM32 Pearl Gecko Series 1 Config 1 Basic Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B) - systemPartFamilyEfm32Jade1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B, /**< EFM32 Jade Gecko Gen1 Basic Device Family */ + systemPartFamilyEfm32Jade1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B, /**< EFM32 Jade Gecko Series 1 Config 1 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B) + systemPartFamilyEfm32Pearl12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B, /**< EFM32 Pearl Gecko Series 1 Config 2 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B) + systemPartFamilyEfm32Jade12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B, /**< EFM32 Jade Gecko Series 1 Config 2 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B) + systemPartFamilyEfm32Pearl13B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B, /**< EFM32 Pearl Gecko Series 1 Config 3 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B) + systemPartFamilyEfm32Jade13B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B, /**< EFM32 Jade Gecko Series 1 Config 3 Basic Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32WG) systemPartFamilyEzr32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EZR32WG, /**< EZR32 Wonder Device Family */ @@ -101,78 +113,89 @@ typedef enum systemPartFamilyEzr32Happy = _DEVINFO_PART_DEVICE_FAMILY_EZR32HG, /**< EZR32 Happy Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P) - systemPartFamilyMighty1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P, /**< EFR32 Mighty Gecko Gen1 Premium Device Family */ + systemPartFamilyMighty1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P, /**< EFR32 Mighty Gecko Series 1 Config 1 Premium Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B) - systemPartFamilyMighty1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B, /**< EFR32 Mighty Gecko Gen1 Basic Device Family */ + systemPartFamilyMighty1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B, /**< EFR32 Mighty Gecko Series 1 Config 1 Basic Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V) - systemPartFamilyMighty1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V, /**< EFR32 Mighty Gecko Gen1 Value Device Family */ + systemPartFamilyMighty1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V, /**< EFR32 Mighty Gecko Series 1 Config 1 Value Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P) - systemPartFamilyBlue1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P, /**< EFR32 Blue Gecko Gen1 Premium Device Family */ + systemPartFamilyBlue1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P, /**< EFR32 Blue Gecko Series 1 Config 1 Premium Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B) - systemPartFamilyBlue1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B, /**< EFR32 Blue Gecko Gen1 Basic Device Family */ + systemPartFamilyBlue1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B, /**< EFR32 Blue Gecko Series 1 Config 1 Basic Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V) - systemPartFamilyBlue1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V, /**< EFR32 Blue Gecko Gen1 Value Device Family */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P) - systemPartFamilyZappy1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P, /**< EFR32 Zappy Gecko Gen1 Premium Device Family */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B) - systemPartFamilyZappy1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B, /**< EFR32 Zappy Gecko Gen1 Basic Device Family */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V) - systemPartFamilyZappy1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V, /**< EFR32 Zappy Gecko Gen1 Value Device Family */ + systemPartFamilyBlue1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V, /**< EFR32 Blue Gecko Series 1 Config 1 Value Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P) - systemPartFamilyFlex1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P, /**< EFR32 Flex Gecko Gen1 Premium Device Family */ + systemPartFamilyFlex1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P, /**< EFR32 Flex Gecko Series 1 Config 1 Premium Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B) - systemPartFamilyFlex1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B, /**< EFR32 Flex Gecko Gen1 Basic Device Family */ + systemPartFamilyFlex1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B, /**< EFR32 Flex Gecko Series 1 Config 1 Basic Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V) - systemPartFamilyFlex1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V, /**< EFR32 Flex Gecko Gen1 Value Device Family */ + systemPartFamilyFlex1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V, /**< EFR32 Flex Gecko Series 1 Config 1 Value Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P) - systemPartFamilyMighty2P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P, /**< EFR32 Mighty Gecko Gen2 Premium Device Family */ + systemPartFamilyMighty2P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P, /**< EFR32 Mighty Gecko Series 1 Config 2 Premium Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2B) - systemPartFamilyMighty2B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2B, /**< EFR32 Mighty Gecko Gen2 Basic Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P) + systemPartFamilyMighty12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P, /**< EFR32 Mighty Gecko Series 1 Config 2 Premium Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2V) - systemPartFamilyMighty2V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2V, /**< EFR32 Mighty Gecko Gen2 Value Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B) + systemPartFamilyMighty12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B, /**< EFR32 Mighty Gecko Series 1 Config 2 Basic Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG2P) - systemPartFamilyBlue2P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG2P, /**< EFR32 Blue Gecko Gen2 Premium Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V) + systemPartFamilyMighty12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V, /**< EFR32 Mighty Gecko Series 1 Config 2 Value Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG2B) - systemPartFamilyBlue2B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG2B, /**< EFR32 Blue Gecko Gen2 Basic Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P) + systemPartFamilyBlue12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P, /**< EFR32 Blue Gecko Series 1 Config 2 Premium Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG2V) - systemPartFamilyBlue2V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG2V, /**< EFR32 Blue Gecko Gen2 Value Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B) + systemPartFamilyBlue12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B, /**< EFR32 Blue Gecko Series 1 Config 2 Basic Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2P) - systemPartFamilyZappy2P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2P, /**< EFR32 Zappy Gecko Gen2 Premium Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V) + systemPartFamilyBlue12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V, /**< EFR32 Blue Gecko Series 1 Config 2 Value Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2B) - systemPartFamilyZappy2B = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2B, /**< EFR32 Zappy Gecko Gen2 Basic Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P) + systemPartFamilyFlex12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P, /**< EFR32 Flex Gecko Series 1 Config 2 Premium Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2V) - systemPartFamilyZappy2V = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2V, /**< EFR32 Zappy Gecko Gen2 Value Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B) + systemPartFamilyFlex12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B, /**< EFR32 Flex Gecko Series 1 Config 2 Basic Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG2P) - systemPartFamilyFlex2P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG2P, /**< EFR32 Flex Gecko Gen2 Premium Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V) + systemPartFamilyFlex12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V, /**< EFR32 Flex Gecko Series 1 Config 2 Value Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG2B) - systemPartFamilyFlex2B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG2B, /**< EFR32 Flex Gecko Gen2 Basic Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P) + systemPartFamilyMighty13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P, /**< EFR32 Mighty Gecko Series 1 Config 3 Premium Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG2V) - systemPartFamilyFlex2V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG2V, /**< EFR32 Flex Gecko Gen2 Value Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B) + systemPartFamilyMighty13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B, /**< EFR32 Mighty Gecko Series 1 Config 3 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V) + systemPartFamilyMighty13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V, /**< EFR32 Mighty Gecko Series 1 Config 3 Value Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P) + systemPartFamilyBlue13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P, /**< EFR32 Blue Gecko Series 1 Config 3 Premium Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B) + systemPartFamilyBlue13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B, /**< EFR32 Blue Gecko Series 1 Config 3 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V) + systemPartFamilyBlue13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V, /**< EFR32 Blue Gecko Series 1 Config 3 Value Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P) + systemPartFamilyFlex13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P, /**< EFR32 Flex Gecko Series 1 Config 3 Premium Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B) + systemPartFamilyFlex13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B, /**< EFR32 Flex Gecko Series 1 Config 3 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V) + systemPartFamilyFlex13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V, /**< EFR32 Flex Gecko Series 1 Config 3 Value Device Family */ #endif - @@ -290,23 +313,32 @@ __STATIC_INLINE uint8_t SYSTEM_GetProdRev(void) * @note * This function retrievs the correct value by reading the chip device * info structure. If your binary is made for one specific device only, - * the \#define SRAM_SIZE can be used instead. + * @ref SRAM_SIZE can be used instead. * * @return * The size of the internal SRAM (in KB). ******************************************************************************/ __STATIC_INLINE uint16_t SYSTEM_GetSRAMSize(void) { + uint16_t sizekb; + #if defined(_EFM32_GECKO_FAMILY) /* Early Gecko devices had a bug where SRAM and Flash size were swapped. */ if (SYSTEM_GetProdRev() < 5) { - return (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) - >> _DEVINFO_MSIZE_FLASH_SHIFT; + sizekb = (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) + >> _DEVINFO_MSIZE_FLASH_SHIFT; } #endif - return (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) - >> _DEVINFO_MSIZE_SRAM_SHIFT; + sizekb = (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) + >> _DEVINFO_MSIZE_SRAM_SHIFT; + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE) + /* Do not include EFR32xG1 RAMH */ + sizekb--; +#endif + + return sizekb; } /***************************************************************************//** @@ -316,7 +348,7 @@ __STATIC_INLINE uint16_t SYSTEM_GetSRAMSize(void) * @note * This function retrievs the correct value by reading the chip device * info structure. If your binary is made for one specific device only, - * the \#define FLASH_SIZE can be used instead. + * @ref FLASH_SIZE can be used instead. * * @return * The size of the internal flash (in KB). @@ -343,7 +375,7 @@ __STATIC_INLINE uint16_t SYSTEM_GetFlashSize(void) * @note * This function retrievs the correct value by reading the chip device * info structure. If your binary is made for one specific device only, - * the \#define FLASH_PAGE_SIZE can be used instead. + * @ref FLASH_PAGE_SIZE can be used instead. * * @return * The page size of the internal flash in bytes. diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h index dce5bbc174..cc5d48bb63 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_timer.h * @brief Timer/counter (TIMER) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -59,32 +59,16 @@ extern "C" { /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - /** Validation of TIMER register block pointer reference for assert statements. */ -#if (TIMER_COUNT == 1) -#define TIMER_REF_VALID(ref) ((ref) == TIMER0) -#elif (TIMER_COUNT == 2) -#define TIMER_REF_VALID(ref) (((ref) == TIMER0) || ((ref) == TIMER1)) -#elif (TIMER_COUNT == 3) -#define TIMER_REF_VALID(ref) (((ref) == TIMER0) \ - || ((ref) == TIMER1) \ - || ((ref) == TIMER2)) -#elif (TIMER_COUNT == 4) -#define TIMER_REF_VALID(ref) (((ref) == TIMER0) \ - || ((ref) == TIMER1) \ - || ((ref) == TIMER2) \ - || ((ref) == TIMER3)) -#else -#error "Undefined number of timers." -#endif +#define TIMER_REF_VALID(ref) TIMER_Valid(ref) /** Validation of TIMER compare/capture channel number */ -#if defined(_SILICON_LABS_32B_PLATFORM_1) +#if defined(_SILICON_LABS_32B_SERIES_0) #define TIMER_CH_VALID(ch) ((ch) < 3) -#elif defined(_SILICON_LABS_32B_PLATFORM_2) +#elif defined(_SILICON_LABS_32B_SERIES_1) #define TIMER_CH_VALID(ch) ((ch) < 4) #else -#error "Unknown platform. Undefined number of channels." +#error "Unknown device. Undefined number of channels." #endif /** @endcond */ @@ -499,6 +483,66 @@ typedef struct ***************************** PROTOTYPES ********************************** ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Validate the TIMER register block pointer + * + * @param[in] ref + * Pointer to TIMER peripheral register block. + * + * @return + * true if ref points to a valid timer, false otherwise. + ******************************************************************************/ +__STATIC_INLINE bool TIMER_Valid(const TIMER_TypeDef *ref) +{ + return (ref == TIMER0) +#if defined(TIMER1) + || (ref == TIMER1) +#endif +#if defined(TIMER2) + || (ref == TIMER2) +#endif +#if defined(TIMER3) + || (ref == TIMER3) +#endif +#if defined(WTIMER0) + || (ref == WTIMER0) +#endif +#if defined(WTIMER1) + || (ref == WTIMER1) +#endif + ; +} + +/***************************************************************************//** + * @brief + * Get the Max count of the timer + * + * @param[in] timer + * Pointer to TIMER peripheral register block. + * + * @return + * The max count value of the timer. This is 0xFFFF for 16 bit timers + * and 0xFFFFFFFF for 32 bit timers. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_MaxCount(const TIMER_TypeDef *ref) +{ +#if defined(WTIMER_PRESENT) + if ((ref == WTIMER0) +#if defined(WTIMER1) + || (ref == WTIMER1) +#endif + ) + { + return 0xFFFFFFFFUL; + } +#else + (void) ref; +#endif + return 0xFFFFUL; +} + /***************************************************************************//** * @brief * Get capture value for compare/capture channel when operating in capture @@ -542,6 +586,7 @@ __STATIC_INLINE void TIMER_CompareBufSet(TIMER_TypeDef *timer, unsigned int ch, uint32_t val) { + EFM_ASSERT(val <= TIMER_MaxCount(timer)); timer->CC[ch].CCVB = val; } @@ -564,6 +609,7 @@ __STATIC_INLINE void TIMER_CompareSet(TIMER_TypeDef *timer, unsigned int ch, uint32_t val) { + EFM_ASSERT(val <= TIMER_MaxCount(timer)); timer->CC[ch].CCV = val; } @@ -596,6 +642,7 @@ __STATIC_INLINE uint32_t TIMER_CounterGet(TIMER_TypeDef *timer) ******************************************************************************/ __STATIC_INLINE void TIMER_CounterSet(TIMER_TypeDef *timer, uint32_t val) { + EFM_ASSERT(val <= TIMER_MaxCount(timer)); timer->CNT = val; } @@ -867,6 +914,7 @@ void TIMER_Reset(TIMER_TypeDef *timer); ******************************************************************************/ __STATIC_INLINE void TIMER_TopBufSet(TIMER_TypeDef *timer, uint32_t val) { + EFM_ASSERT(val <= TIMER_MaxCount(timer)); timer->TOPB = val; } @@ -899,6 +947,7 @@ __STATIC_INLINE uint32_t TIMER_TopGet(TIMER_TypeDef *timer) ******************************************************************************/ __STATIC_INLINE void TIMER_TopSet(TIMER_TypeDef *timer, uint32_t val) { + EFM_ASSERT(val <= TIMER_MaxCount(timer)); timer->TOP = val; } @@ -919,7 +968,6 @@ __STATIC_INLINE void TIMER_Unlock(TIMER_TypeDef *timer) } #endif - /** @} (end addtogroup TIMER) */ /** @} (end addtogroup emlib) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h index b80642c9e4..ac79f8d18c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h @@ -2,7 +2,7 @@ * @file em_usart.h * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) * peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -86,7 +86,7 @@ extern "C" { * @if DOXYDOC_P1_DEVICE * @include em_usart_route_p1.c * @note UART hardware flow control is not directly supported in hardware on - * @ref _SILICON_LABS_32B_PLATFORM_1 parts. + * @ref _SILICON_LABS_32B_SERIES_0 parts. * @endif * @if DOXYDOC_P2_DEVICE * @include em_usart_route_p2.c diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h index 66b55c3c85..fdb3e36a2c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_vcmp.h * @brief Voltage Comparator (VCMP) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vdac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vdac.h new file mode 100644 index 0000000000..6997dd2ee3 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vdac.h @@ -0,0 +1,420 @@ +/***************************************************************************//** + * @file em_vdac.h + * @brief Digital to Analog Converter (VDAC) peripheral API + * @version 5.1.2 + ******************************************************************************* + * @section License + * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************* + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + +#ifndef EM_VDAC_H +#define EM_VDAC_H + +#include "em_device.h" + +#if defined(VDAC_COUNT) && (VDAC_COUNT > 0) + +#include "em_assert.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup VDAC + * @brief Digital to Analog Voltage Converter (VDAC) Peripheral API + * + * @details + * This module contains functions to control the VDAC peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The VDAC converts digital values to analog + * signals at up to 500 ksps with 12-bit accuracy. The VDAC is designed for + * low energy consumption, but can also provide very good performance. + * + * The following steps are necessary for basic operation: + * + * Clock enable: + * @code + CMU_ClockEnable(cmuClock_VDAC0, true);@endcode + * + * Initialize the VDAC with default settings and modify selected fields: + * @code + VDAC_Init_TypeDef vdacInit = VDAC_INIT_DEFAULT; + VDAC_InitChannel_TypeDef vdacChInit = VDAC_INITCHANNEL_DEFAULT; + + // Set prescaler to get 1 MHz VDAC clock frequency. + vdacInit.prescaler = VDAC_PrescaleCalc(1000000, true, 0); + VDAC_Init(VDAC0, &vdacInit); + + vdacChInit.enable = true; + VDAC_InitChannel(VDAC0, &vdacChInit, 0);@endcode + * + * Perform a conversion: + * @code + VDAC_ChannelOutputSet(VDAC0, 0, 250);@endcode + * + * @note The output stage of a VDAC channel consist of an onchip operational + * amplifier in the OPAMP module. This opamp is highly configurable and to + * exploit the VDAC functionality fully, you might need to configure the opamp + * using the OPAMP API. By using the OPAMP API you will also load opamp + * calibration values. The default (reset) settings of the opamp will be + * sufficient for many applications. + * @{ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of VDAC register block pointer reference for assert statements.*/ +#define VDAC_REF_VALID(ref) ((ref) == VDAC0) + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Channel refresh period. */ +typedef enum +{ + vdacRefresh8 = _VDAC_CTRL_REFRESHPERIOD_8CYCLES, /**< Refresh every 8 clock cycles. */ + vdacRefresh16 = _VDAC_CTRL_REFRESHPERIOD_16CYCLES, /**< Refresh every 16 clock cycles. */ + vdacRefresh32 = _VDAC_CTRL_REFRESHPERIOD_32CYCLES, /**< Refresh every 32 clock cycles. */ + vdacRefresh64 = _VDAC_CTRL_REFRESHPERIOD_64CYCLES, /**< Refresh every 64 clock cycles. */ +} VDAC_Refresh_TypeDef; + +/** Reference voltage for VDAC. */ +typedef enum +{ + vdacRef1V25Ln = _VDAC_CTRL_REFSEL_1V25LN, /**< Internal low noise 1.25 V bandgap reference. */ + vdacRef2V5Ln = _VDAC_CTRL_REFSEL_2V5LN, /**< Internal low noise 2.5 V bandgap reference. */ + vdacRef1V25 = _VDAC_CTRL_REFSEL_1V25, /**< Internal 1.25 V bandgap reference. */ + vdacRef2V5 = _VDAC_CTRL_REFSEL_2V5, /**< Internal 2.5 V bandgap reference. */ + vdacRefAvdd = _VDAC_CTRL_REFSEL_VDD, /**< AVDD reference. */ + vdacRefExtPin = _VDAC_CTRL_REFSEL_EXT, /**< External pin reference. */ +} VDAC_Ref_TypeDef; + +/** Peripheral Reflex System signal used to trig VDAC channel conversion. */ +typedef enum +{ + vdacPrsSelCh0 = _VDAC_CH0CTRL_PRSSEL_PRSCH0 , /**< PRS ch 0 triggers conversion. */ + vdacPrsSelCh1 = _VDAC_CH0CTRL_PRSSEL_PRSCH1 , /**< PRS ch 1 triggers conversion. */ + vdacPrsSelCh2 = _VDAC_CH0CTRL_PRSSEL_PRSCH2 , /**< PRS ch 2 triggers conversion. */ + vdacPrsSelCh3 = _VDAC_CH0CTRL_PRSSEL_PRSCH3 , /**< PRS ch 3 triggers conversion. */ + vdacPrsSelCh4 = _VDAC_CH0CTRL_PRSSEL_PRSCH4 , /**< PRS ch 4 triggers conversion. */ + vdacPrsSelCh5 = _VDAC_CH0CTRL_PRSSEL_PRSCH5 , /**< PRS ch 5 triggers conversion. */ + vdacPrsSelCh6 = _VDAC_CH0CTRL_PRSSEL_PRSCH6 , /**< PRS ch 6 triggers conversion. */ + vdacPrsSelCh7 = _VDAC_CH0CTRL_PRSSEL_PRSCH7 , /**< PRS ch 7 triggers conversion. */ + vdacPrsSelCh8 = _VDAC_CH0CTRL_PRSSEL_PRSCH8 , /**< PRS ch 8 triggers conversion. */ + vdacPrsSelCh9 = _VDAC_CH0CTRL_PRSSEL_PRSCH9 , /**< PRS ch 9 triggers conversion. */ + vdacPrsSelCh10 = _VDAC_CH0CTRL_PRSSEL_PRSCH10, /**< PRS ch 10 triggers conversion. */ + vdacPrsSelCh11 = _VDAC_CH0CTRL_PRSSEL_PRSCH11, /**< PRS ch 11 triggers conversion. */ +} VDAC_PrsSel_TypeDef; + +/** Channel conversion trigger mode. */ +typedef enum +{ + vdacTrigModeSw = _VDAC_CH0CTRL_TRIGMODE_SW, /**< Channel is triggered by CHnDATA or COMBDATA write. */ + vdacTrigModePrs = _VDAC_CH0CTRL_TRIGMODE_PRS, /**< Channel is triggered by PRS input. */ + vdacTrigModeRefresh = _VDAC_CH0CTRL_TRIGMODE_REFRESH, /**< Channel is triggered by Refresh timer. */ + vdacTrigModeSwPrs = _VDAC_CH0CTRL_TRIGMODE_SWPRS, /**< Channel is triggered by CHnDATA/COMBDATA write or PRS input. */ + vdacTrigModeSwRefresh = _VDAC_CH0CTRL_TRIGMODE_SWREFRESH, /**< Channel is triggered by CHnDATA/COMBDATA write or Refresh timer. */ + vdacTrigModeLesense = _VDAC_CH0CTRL_TRIGMODE_LESENSE, /**< Channel is triggered by LESENSE. */ +} VDAC_TrigMode_TypeDef; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** VDAC init structure, common for both channels. */ +typedef struct +{ + /** Select between main and alternate output path calibration values. */ + bool mainCalibration; + + /** Selects clock from asynchronous or synchronous (with respect to + peripheral clock) source */ + bool asyncClockMode; + + /** Warmup mode, keep VDAC on (in idle) - or shutdown between conversions.*/ + bool warmupKeepOn; + + /** Channel refresh period. */ + VDAC_Refresh_TypeDef refresh; + + /** Prescaler for VDAC clock. Clock is source clock divided by prescaler+1. */ + uint32_t prescaler; + + /** Reference voltage to use. */ + VDAC_Ref_TypeDef reference; + + /** Enable/disable reset of prescaler on CH 0 start. */ + bool ch0ResetPre; + + /** Enable/disable output enable control by CH1 PRS signal. */ + bool outEnablePRS; + + /** Enable/disable sine mode. */ + bool sineEnable; + + /** Select if single ended or differential output mode. */ + bool diff; +} VDAC_Init_TypeDef; + +/** Default config for VDAC init structure. */ +#define VDAC_INIT_DEFAULT \ +{ \ + true, /* Use main output path calibration values. */ \ + false, /* Use synchronous clock mode. */ \ + false, /* Turn off between sample off conversions.*/ \ + vdacRefresh8, /* Refresh every 8th cycle. */ \ + 0, /* No prescaling. */ \ + vdacRef1V25Ln, /* 1.25V internal low noise reference. */ \ + false, /* Do not reset prescaler on CH 0 start. */ \ + false, /* VDAC output enable always on. */ \ + false, /* Disable sine mode. */ \ + false /* Single ended mode. */ \ +} + +/** VDAC channel init structure. */ +typedef struct +{ + /** Enable channel. */ + bool enable; + + /** + * Peripheral reflex system trigger selection. Only applicable if @p trigMode + * is set to @p vdacTrigModePrs or @p vdacTrigModeSwPrs. */ + VDAC_PrsSel_TypeDef prsSel; + + /** Treat the PRS signal asynchronously. */ + bool prsAsync; + + /** Channel conversion trigger mode. */ + VDAC_TrigMode_TypeDef trigMode; + + /** Set channel conversion mode to sample/shut-off mode. Default is + * continous.*/ + bool sampleOffMode; +} VDAC_InitChannel_TypeDef; + +/** Default config for VDAC channel init structure. */ +#define VDAC_INITCHANNEL_DEFAULT \ +{ \ + false, /* Leave channel disabled when init done. */ \ + vdacPrsSelCh0, /* PRS CH 0 triggers conversion. */ \ + false, /* Treat PRS channel as a synchronous signal. */ \ + vdacTrigModeSw, /* Conversion trigged by CH0DATA or COMBDATA write. */ \ + false, /* Channel conversion set to continous. */ \ +} + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void VDAC_ChannelOutputSet(VDAC_TypeDef *vdac, + unsigned int channel, + uint32_t value); +void VDAC_Enable(VDAC_TypeDef *vdac, unsigned int ch, bool enable); +void VDAC_Init(VDAC_TypeDef *vdac, const VDAC_Init_TypeDef *init); +void VDAC_InitChannel(VDAC_TypeDef *vdac, + const VDAC_InitChannel_TypeDef *init, + unsigned int ch); + +/***************************************************************************//** + * @brief + * Set the output signal of VDAC channel 0 to a given value. + * + * @details + * This function sets the output signal of VDAC channel 0 by writing @p value + * to the CH0DATA register. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] value + * Value to write to channel 0 output register CH0DATA. + ******************************************************************************/ +__STATIC_INLINE void VDAC_Channel0OutputSet(VDAC_TypeDef *vdac, + uint32_t value) +{ + EFM_ASSERT(value<=_VDAC_CH0DATA_MASK); + vdac->CH0DATA = value; +} + +/***************************************************************************//** + * @brief + * Set the output signal of VDAC channel 1 to a given value. + * + * @details + * This function sets the output signal of VDAC channel 1 by writing @p value + * to the CH1DATA register. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] value + * Value to write to channel 1 output register CH1DATA. + ******************************************************************************/ +__STATIC_INLINE void VDAC_Channel1OutputSet(VDAC_TypeDef *vdac, + uint32_t value) +{ + EFM_ASSERT(value<=_VDAC_CH1DATA_MASK); + vdac->CH1DATA = value; +} + +/***************************************************************************//** + * @brief + * Clear one or more pending VDAC interrupts. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * Pending VDAC interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntClear(VDAC_TypeDef *vdac, uint32_t flags) +{ + vdac->IFC = flags; +} + +/***************************************************************************//** + * @brief + * Disable one or more VDAC interrupts. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * VDAC interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntDisable(VDAC_TypeDef *vdac, uint32_t flags) +{ + vdac->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more VDAC interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using VDAC_IntClear() prior to enabling + * if such a pending interrupt should be ignored. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * VDAC interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntEnable(VDAC_TypeDef *vdac, uint32_t flags) +{ + vdac->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending VDAC interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @return + * VDAC interrupt sources pending. A bitwise logic OR combination of valid + * interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t VDAC_IntGet(VDAC_TypeDef *vdac) +{ + return vdac->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending VDAC interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled VDAC interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in VDACx_IEN_nnn + * register (VDACx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the VDAC module + * (VDACx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t VDAC_IntGetEnabled(VDAC_TypeDef *vdac) +{ + uint32_t ien = vdac->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return vdac->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending VDAC interrupts from SW. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * VDAC interrupt sources to set to pending. Use a bitwise logic OR + * combination of valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntSet(VDAC_TypeDef *vdac, uint32_t flags) +{ + vdac->IFS = flags; +} + +uint32_t VDAC_PrescaleCalc(uint32_t vdacFreq, bool syncMode, uint32_t hfperFreq); +void VDAC_Reset(VDAC_TypeDef *vdac); + +/** @} (end addtogroup VDAC) */ +/** @} (end addtogroup emlib) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(VDAC_COUNT) && (VDAC_COUNT > 0) */ +#endif /* EM_VDAC_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h index 2ec5de4443..a4e1ca8599 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_version.h * @brief Assign correct part number for include file - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -53,18 +53,18 @@ extern "C" { ******************************************************************************/ /** Version number of emlib peripheral API. */ -#define _EMLIB_VERSION 5.0.0 +#define _EMLIB_VERSION 5.1.2 /** Major version of emlib. Bumped when incompatible API changes introduced. */ #define _EMLIB_VERSION_MAJOR 5 /** Minor version of emlib. Bumped when functionality is added in a backwards- compatible manner. */ -#define _EMLIB_VERSION_MINOR 0 +#define _EMLIB_VERSION_MINOR 1 /** Patch revision of emlib. Bumped when adding backwards-compatible bug fixes.*/ -#define _EMLIB_VERSION_PATCH 0 +#define _EMLIB_VERSION_PATCH 2 /** Version number of targeted CMSIS package. */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h index a554109410..0e4c4a40f0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_wdog.h * @brief Watchdog (WDOG) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c index 9a2bb69f36..ac0c944044 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_acmp.c * @brief Analog Comparator (ACMP) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -230,6 +230,32 @@ void ACMP_Enable(ACMP_TypeDef *acmp) acmp->CTRL |= ACMP_CTRL_EN; } +#if defined(_ACMP_EXTIFCTRL_MASK) +/***************************************************************************//** + * @brief + * Select and enable an external input. + * + * @details + * This is used when an external module needs to take control of the ACMP + * POSSEL field in order to configure the APORT input for the ACMP. Modules + * like LESENSE use this to change the ACMP input during a scan sequence. + * + * @param[in] acmp + * Pointer to ACMP peripheral register block. + * + * @param[in] aport + * This parameter decides which APORT(s) the ACMP will use when it's being + * controlled by an external module. + ******************************************************************************/ +void ACMP_ExternalInputSelect(ACMP_TypeDef *acmp, ACMP_ExternalInput_Typedef aport) +{ + acmp->EXTIFCTRL = (aport << _ACMP_EXTIFCTRL_APORTSEL_SHIFT) + | ACMP_EXTIFCTRL_EN; + while (!(acmp->STATUS & ACMP_STATUS_EXTIFACT)) + ; +} +#endif + /***************************************************************************//** * @brief * Reset ACMP to same state as after a HW reset. @@ -351,7 +377,8 @@ void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init) EFM_ASSERT(ACMP_REF_VALID(acmp)); /* Make sure biasprog is within bounds */ - EFM_ASSERT(init->biasProg < 16); + EFM_ASSERT(init->biasProg <= + (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT)); /* Make sure the ACMP is disable since we might be changing the * ACMP power source */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c index a14f6b821e..612c5fe494 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_adc.c * @brief Analog to Digital Converter (ADC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -62,7 +62,7 @@ #define ADC_REF_VALID(ref) ((ref) == ADC0) /** Max ADC clock */ -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) #define ADC_MAX_CLOCK 13000000 #else #define ADC_MAX_CLOCK 16000000 @@ -180,7 +180,7 @@ #define DEVINFO_ADC0_OFFSET2XVDD_SHIFT _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT #endif -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) #define FIX_ADC_TEMP_BIAS_EN #endif /** @endcond */ @@ -418,8 +418,8 @@ void ADC_Init(ADC_TypeDef *adc, const ADC_Init_TypeDef *init) init->em2ClockConfig); #endif -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) - /* Fix for errata ADC_EXXX */ +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) + /* A debugger can trigger the SCANUF interrupt on EFM32xG1 or EFR32xG1 */ ADC_IntClear(adc, ADC_IFC_SCANUF); #endif } @@ -750,9 +750,10 @@ void ADC_InitScan(ADC_TypeDef *adc, const ADC_InitScan_TypeDef *init) if (init->rep) { -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) - /* Scan repeat mode does not work on platform 2 as described in errata ADC_EXXX. */ - EFM_ASSERT(false); +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) + /* Scan repeat mode does not work on EFM32JG1, EFM32PG1 or EFR32xG1x devices. + * The errata is called ADC_E211 in the errata document. */ + EFM_ASSERT(false); #endif tmp |= ADC_SCANCTRL_REP; } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c index 10c302527d..715535ceee 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_aes.c * @brief Advanced Encryption Standard (AES) accelerator peripheral API. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c index 9050c63a81..b9bd09a899 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_assert.c * @brief Assert API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c index 018761e4bf..a81a4446b2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_burtc.c * @brief Backup Real Time Counter (BURTC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c index 5b878b892d..dba72ff21f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_cmu.c * @brief Clock management unit (CMU) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -37,6 +37,7 @@ #include "em_assert.h" #include "em_bus.h" #include "em_emu.h" +#include "em_cmu.h" #include "em_system.h" #include "em_common.h" @@ -60,12 +61,12 @@ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /** Maximum allowed core frequency when using 0 wait-states on flash access. */ #define CMU_MAX_FREQ_0WS 26000000 /** Maximum allowed core frequency when using 1 wait-states on flash access */ #define CMU_MAX_FREQ_1WS 40000000 -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) /** Maximum allowed core frequency when using 0 wait-states on flash access. */ #define CMU_MAX_FREQ_0WS 16000000 /** Maximum allowed core frequency when using 1 wait-states on flash access */ @@ -76,19 +77,21 @@ /** Maximum frequency for HFLE interface */ #if defined( CMU_CTRL_HFLE ) -/** Maximum HFLE frequency for EFM32 and EZR32 Wonder Gecko. */ -#if defined( _EFM32_WONDER_FAMILY ) \ - || defined( _EZR32_WONDER_FAMILY ) +/** Maximum HFLE frequency for series 0 EFM32 and EZR32 Wonder Gecko. */ +#if defined( _SILICON_LABS_32B_SERIES_0 ) \ + && (defined( _EFM32_WONDER_FAMILY ) \ + || defined( _EZR32_WONDER_FAMILY )) #define CMU_MAX_FREQ_HFLE 24000000 -/** Maximum HFLE frequency for other platform 1 parts with maximum core clock +/** Maximum HFLE frequency for other series 0 parts with maximum core clock higher than 32MHz. */ -#elif defined( _EFM32_GIANT_FAMILY ) \ - || defined( _EFM32_LEOPARD_FAMILY ) \ - || defined( _EZR32_LEOPARD_FAMILY ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) \ + && (defined( _EFM32_GIANT_FAMILY ) \ + || defined( _EFM32_LEOPARD_FAMILY ) \ + || defined( _EZR32_LEOPARD_FAMILY )) #define CMU_MAX_FREQ_HFLE maxFreqHfle() #endif #elif defined( CMU_CTRL_WSHFLE ) -/** Maximum HFLE frequency for platform 2 parts */ +/** Maximum HFLE frequency for series 1 parts */ #define CMU_MAX_FREQ_HFLE 32000000 #endif @@ -112,9 +115,10 @@ static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz; /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -#if defined( _EFM32_GIANT_FAMILY ) \ - || defined( _EFM32_LEOPARD_FAMILY ) \ - || defined( _EZR32_LEOPARD_FAMILY ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) \ + && (defined( _EFM32_GIANT_FAMILY ) \ + || defined( _EFM32_LEOPARD_FAMILY ) \ + || defined( _EZR32_LEOPARD_FAMILY )) /***************************************************************************//** * @brief * Return max allowed frequency for low energy peripherals. @@ -235,7 +239,7 @@ static uint32_t auxClkGet(void) ret = auxHfrcoFreq; #elif defined( _CMU_AUXHFRCOCTRL_BAND_MASK ) - /* All platform 1 families except EFM32G */ + /* All series 0 families except EFM32G */ switch(CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK) { case CMU_AUXHFRCOCTRL_BAND_1MHZ: @@ -585,6 +589,12 @@ static uint32_t lfClkGet(CMU_Clock_TypeDef lfClkBranch) ret = SystemULFRCOClockGet(); break; +#if defined( CMU_LFACLKSEL_LFA_PLFRCO ) + case _CMU_LFACLKSEL_LFA_PLFRCO: + ret = SystemLFRCOClockGet(); + break; +#endif + #if defined( _CMU_LFACLKSEL_LFA_HFCLKLE ) case _CMU_LFACLKSEL_LFA_HFCLKLE: ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) @@ -1101,10 +1111,10 @@ uint32_t CMU_CalibrateCountGet(void) ******************************************************************************/ CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) { -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) return 1 + (uint32_t)CMU_ClockPrescGet(clock); -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) uint32_t divReg; CMU_ClkDiv_TypeDef ret; @@ -1233,10 +1243,10 @@ CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) ******************************************************************************/ void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div) { -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1)); -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) uint32_t freq; uint32_t divReg; @@ -1560,7 +1570,7 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) #endif break; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) #if defined( CRYPTO_PRESENT ) \ || defined( LDMA_PRESENT ) \ || defined( GPCRC_PRESENT ) \ @@ -1584,7 +1594,7 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) break; #endif -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) #if defined( AES_PRESENT ) \ || defined( DMA_PRESENT ) \ || defined( EBI_PRESENT ) \ @@ -1617,10 +1627,10 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) #if defined( _CMU_LFACLKEN0_LETIMER0_MASK ) case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFA); -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) >> _CMU_LFAPRESC0_LETIMER0_SHIFT; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) ret /= CMU_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) >> _CMU_LFAPRESC0_LETIMER0_SHIFT); #endif @@ -1659,10 +1669,10 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) #if defined( _CMU_LFBCLKEN0_LEUART0_MASK ) case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFB); -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) >> _CMU_LFBPRESC0_LEUART0_SHIFT; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) >> _CMU_LFBPRESC0_LEUART0_SHIFT); #endif @@ -1672,17 +1682,25 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) #if defined( _CMU_LFBCLKEN0_LEUART1_MASK ) case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFB); -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) >> _CMU_LFBPRESC0_LEUART1_SHIFT; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) >> _CMU_LFBPRESC0_LEUART1_SHIFT); #endif break; #endif -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _CMU_LFBCLKEN0_CSEN_MASK ) + case (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFB); + ret /= CMU_Log2ToDiv(((CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) + >> _CMU_LFBPRESC0_CSEN_SHIFT) + 4); + break; +#endif + +#if defined( _SILICON_LABS_32B_SERIES_1 ) case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFE); break; @@ -1712,7 +1730,7 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) } -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /***************************************************************************//** * @brief * Get clock prescaler. @@ -1809,6 +1827,15 @@ uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock) break; #endif +#if defined( _CMU_LFBPRESC0_CSEN_MASK ) + case cmuClock_CSEN_LF: + ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) + >> _CMU_LFBPRESC0_CSEN_SHIFT)); + /* Convert the exponent to prescaler value. */ + ret = CMU_Log2ToDiv(ret + 4) - 1U; + break; +#endif + default: EFM_ASSERT(0); ret = 0U; @@ -1845,7 +1872,7 @@ uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock) #endif -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /***************************************************************************//** * @brief * Set clock prescaler. @@ -2044,6 +2071,22 @@ void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc) break; #endif +#if defined( _CMU_LFBPRESC0_CSEN_MASK ) + case cmuClock_CSEN_LF: + EFM_ASSERT((presc <= 127U) && (presc >= 15U)); + + /* Convert prescaler value to DIV exponent scale. + * DIV16 is the lowest supported prescaler. */ + presc = CMU_PrescToLog2(presc) - 4; + + /* LF register about to be modified require sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_CSEN_MASK) + | (presc << _CMU_LFBPRESC0_CSEN_SHIFT); + break; +#endif + default: EFM_ASSERT(0); break; @@ -2089,7 +2132,7 @@ void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc) * @li #cmuClock_LFA * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO * @li #cmuClock_LFC - * @endif @if _SILICON_LABS_32B_PLATFORM_2 + * @endif @if _SILICON_LABS_32B_SERIES_1 * @li #cmuClock_LFE * @endif * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT @@ -2217,6 +2260,12 @@ CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) break; #endif +#if defined( CMU_LFACLKSEL_LFA_PLFRCO ) + case CMU_LFACLKSEL_LFA_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + default: ret = cmuSelect_Disabled; break; @@ -2282,6 +2331,12 @@ CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) ret = cmuSelect_HFCLKLE; break; +#if defined( CMU_LFBCLKSEL_LFB_PLFRCO ) + case CMU_LFBCLKSEL_LFB_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + default: ret = cmuSelect_Disabled; break; @@ -2331,6 +2386,12 @@ CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) break; #endif +#if defined( CMU_LFECLKSEL_LFE_PLFRCO ) + case CMU_LFECLKSEL_LFE_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + default: ret = cmuSelect_Disabled; break; @@ -2436,7 +2497,7 @@ CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) * @li #cmuClock_LFA * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO * @li #cmuClock_LFC - * @endif @if _SILICON_LABS_32B_PLATFORM_2 + * @endif @if _SILICON_LABS_32B_SERIES_1 * @li #cmuClock_LFE * @endif * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT @@ -2454,20 +2515,43 @@ CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) * @li #cmuSelect_AUXHFRCO * @li #cmuSelect_HFCLK @ifnot DOXYDOC_EFM32_GECKO_FAMILY * @li #cmuSelect_ULFRCO + * @li #cmuSelect_PLFRCO * @endif ******************************************************************************/ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) { - uint32_t select = cmuOsc_HFRCO; - CMU_Osc_TypeDef osc = cmuOsc_HFRCO; - uint32_t freq; - uint32_t tmp; - uint32_t selRegId; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) - volatile uint32_t *selReg = NULL; + uint32_t select = cmuOsc_HFRCO; + CMU_Osc_TypeDef osc = cmuOsc_HFRCO; + uint32_t freq; + uint32_t tmp; + uint32_t selRegId; +#if defined( _SILICON_LABS_32B_SERIES_1 ) + volatile uint32_t *selReg = NULL; #endif #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) - uint32_t lfExtended = 0; + uint32_t lfExtended = 0; +#endif + +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + uint32_t vScaleFrequency = 0; /* Use default */ + + /* Start voltage upscaling before clock is set. */ + if (clock == cmuClock_HF) + { + if (ref == cmuSelect_HFXO) + { + vScaleFrequency = SystemHFXOClockGet(); + } + else if ((ref == cmuSelect_HFRCO) + && (CMU_HFRCOBandGet() > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) + { + vScaleFrequency = CMU_HFRCOBandGet(); + } + if (vScaleFrequency != 0) + { + EMU_VScaleEM01ByClock(vScaleFrequency, false); + } + } #endif selRegId = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK; @@ -2478,18 +2562,18 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) switch (ref) { case cmuSelect_LFXO: -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) select = CMU_HFCLKSEL_HF_LFXO; -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) select = CMU_CMD_HFCLKSEL_LFXO; #endif osc = cmuOsc_LFXO; break; case cmuSelect_LFRCO: -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) select = CMU_HFCLKSEL_HF_LFRCO; -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) select = CMU_CMD_HFCLKSEL_LFRCO; #endif osc = cmuOsc_LFRCO; @@ -2523,9 +2607,9 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) break; case cmuSelect_HFRCO: -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) select = CMU_HFCLKSEL_HF_HFRCO; -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) select = CMU_CMD_HFCLKSEL_HFRCO; #endif osc = cmuOsc_HFRCO; @@ -2561,6 +2645,14 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) /* Configure worst case wait states for flash access before selecting */ flashWaitStateMax(); +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + /* Wait for voltage upscaling to complete before clock is set. */ + if (vScaleFrequency != 0) + { + EMU_VScaleWait(); + } +#endif + /* Switch to selected oscillator */ #if defined( _CMU_HFCLKSEL_MASK ) CMU->HFCLKSEL = select; @@ -2573,18 +2665,24 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE); #endif - /* Keep EMU module informed */ - EMU_UpdateOscConfig(); - /* Update CMSIS core clock variable */ /* (The function will update the global variable) */ freq = SystemCoreClockGet(); /* Optimize flash access wait state setting for currently selected core clk */ flashWaitStateControl(freq); + +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + /* Keep EMU module informed on source HF clock frequency. This will apply voltage + downscaling after clock is set if downscaling is configured. */ + if (vScaleFrequency == 0) + { + EMU_VScaleEM01ByClock(0, true); + } +#endif break; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) case CMU_LFACLKSEL_REG: selReg = (selReg == NULL) ? &CMU->LFACLKSEL : selReg; #if !defined( _CMU_LFACLKSEL_LFA_HFCLKLE ) @@ -2633,6 +2731,14 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) tmp = _CMU_LFACLKSEL_LFA_ULFRCO; break; +#if defined( _CMU_STATUS_PLFRCOENS_MASK ) + case cmuSelect_PLFRCO: + /* Ensure selected oscillator is enabled, waiting for it to stabilize */ + CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); + tmp = _CMU_LFACLKSEL_LFA_PLFRCO; + break; +#endif + default: EFM_ASSERT(0); return; @@ -2640,7 +2746,7 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) *selReg = tmp; break; -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) case CMU_LFACLKSEL_REG: case CMU_LFBCLKSEL_REG: switch (ref) @@ -3154,6 +3260,11 @@ void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq) /* Reduce HFLE frequency if possible. */ setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE); + + /* Update voltage scaling */ +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + EMU_VScaleEM01ByClock(0, true); +#endif } #endif /* _CMU_HFRCOCTRL_FREQRANGE_MASK */ @@ -3238,15 +3349,17 @@ void CMU_HFXOAutostartEnable(uint32_t userSel, | (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0) | (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0); - CMU->HFXOCTRL = hfxoCtrl; - /* Set wait-states for HFXO if automatic start and select is configured. */ if (userSel || enEM0EM1StartSel) { hfxoFreq = SystemHFXOClockGet(); flashWaitStateControl(hfxoFreq); - setHfLeConfig(hfxoFreq, CMU_MAX_FREQ_HFLE); + setHfLeConfig(hfxoFreq, CMU_MAX_FREQ_HFLE); } + + /* Update HFXOCTRL after wait-states are updated as HF may automatically switch + to HFXO when automatic select is enabled . */ + CMU->HFXOCTRL = hfxoCtrl; } #endif @@ -3268,6 +3381,11 @@ void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit) /* Do not disable HFXO if it is currently selected as HF/Core clock */ EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO); + /* REGPWRSEL must be set to DVDD before the HFXO can be enabled. */ +#if defined( _EMU_PWRCTRL_REGPWRSEL_MASK ) + EFM_ASSERT(EMU->PWRCTRL & EMU_PWRCTRL_REGPWRSEL_DVDD); +#endif + /* HFXO must be disabled before reconfiguration */ CMU_OscillatorEnable(cmuOsc_HFXO, false, true); @@ -3476,7 +3594,7 @@ void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit) void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) { uint32_t rdyBitPos; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) uint32_t ensBitPos; #endif #if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK ) @@ -3492,7 +3610,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_HFRCOEN; disBit = CMU_OSCENCMD_HFRCODIS; rdyBitPos = _CMU_STATUS_HFRCORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_HFRCOENS_SHIFT; #endif break; @@ -3501,7 +3619,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_HFXOEN; disBit = CMU_OSCENCMD_HFXODIS; rdyBitPos = _CMU_STATUS_HFXORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_HFXOENS_SHIFT; #endif break; @@ -3510,7 +3628,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_AUXHFRCOEN; disBit = CMU_OSCENCMD_AUXHFRCODIS; rdyBitPos = _CMU_STATUS_AUXHFRCORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_AUXHFRCOENS_SHIFT; #endif break; @@ -3519,7 +3637,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_LFRCOEN; disBit = CMU_OSCENCMD_LFRCODIS; rdyBitPos = _CMU_STATUS_LFRCORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_LFRCOENS_SHIFT; #endif break; @@ -3528,7 +3646,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_LFXOEN; disBit = CMU_OSCENCMD_LFXODIS; rdyBitPos = _CMU_STATUS_LFXORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_LFXOENS_SHIFT; #endif break; @@ -3538,12 +3656,21 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_USHFRCOEN; disBit = CMU_OSCENCMD_USHFRCODIS; rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT; #endif break; #endif +#if defined( _CMU_STATUS_PLFRCOENS_MASK ) + case cmuOsc_PLFRCO: + enBit = CMU_OSCENCMD_PLFRCOEN; + disBit = CMU_OSCENCMD_PLFRCODIS; + rdyBitPos = _CMU_STATUS_PLFRCORDY_SHIFT; + ensBitPos = _CMU_STATUS_PLFRCOENS_SHIFT; + break; +#endif + default: /* Undefined clock source or cmuOsc_ULFRCO. ULFRCO is always enabled, and cannot be disabled. Ie. the definition of cmuOsc_ULFRCO is primarely @@ -3576,7 +3703,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) #endif CMU->OSCENCMD = enBit; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /* Always wait for ENS to go high */ while (!BUS_RegBitRead(&CMU->STATUS, ensBitPos)) { @@ -3618,16 +3745,13 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) { CMU->OSCENCMD = disBit; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /* Always wait for ENS to go low */ while (BUS_RegBitRead(&CMU->STATUS, ensBitPos)) { } #endif } - - /* Keep EMU module informed */ - EMU_UpdateOscConfig(); } @@ -3715,7 +3839,7 @@ void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT)); val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT); -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_LFRCOBSY_SHIFT)); #endif CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK)) @@ -3726,7 +3850,7 @@ void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT)); val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT); -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT)) { } @@ -3739,7 +3863,7 @@ void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT)); val &= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT); -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT)) { } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_core.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_core.c index 90283edf82..8f1895e844 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_core.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_core.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_core.c * @brief Core interrupt handling API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -63,11 +63,13 @@ blocking capabilities. @li CRITICAL section: Inside a critical sections all interrupts are - disabled (except for fault handlers). The PRIMASK register is used for + disabled (except for fault handlers). The PRIMASK register is always used for interrupt disable/enable. - @li ATOMIC section: Interrupts with priority equal to or lower than a - given level are disabled. The interrupt disable priority level is defined - at compile time. The BASEPRI register is used for interrupt disable/enable. + @li ATOMIC section: This type of section is configurable and the default + method is to use PRIMASK. With BASEPRI configuration, interrupts with priority + equal to or lower than a given configurable level are disabled. The interrupt + disable priority level is defined at compile time. The BASEPRI register is not + available for all architectures. @li NVIC mask section: Disable NVIC (external interrupts) on an individual manner. @@ -535,7 +537,7 @@ void CORE_NvicDisableMask(const CORE_nvicMask_t *disable) /***************************************************************************//** * @brief - * Get current NVIC interrupt enable mask. + * Set current NVIC interrupt enable mask. * * @param[out] enable * Mask specifying which NVIC interrupts are currently enabled. @@ -556,7 +558,7 @@ void CORE_NvicEnableMask(const CORE_nvicMask_t *enable) * Mask specifying which NVIC interrupts to briefly enable. * * @note - * Usully used within a NVIC mask section. + * Usually used within a NVIC mask section. ******************************************************************************/ void CORE_YieldNvicMask(const CORE_nvicMask_t *enable) { diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cryotimer.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cryotimer.c index 7a4b67acdb..871a0b8641 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cryotimer.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cryotimer.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_cryotimer.c * @brief Ultra Low Energy Timer/Counter (CRYOTIMER) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_crypto.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_crypto.c index fd6b29a44c..d3c526abc6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_crypto.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_crypto.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_crypto.c * @brief Cryptography accelerator peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -1139,12 +1139,13 @@ void CRYPTO_AES_DecryptKey128(CRYPTO_TypeDef * crypto, uint32_t * _out = (uint32_t *) out; const uint32_t * _in = (const uint32_t *) in; + /* Setup CRYPTO in AES-128 mode. */ + crypto->CTRL = CRYPTO_CTRL_AES_AES128; + /* Load key */ CRYPTO_BurstToCrypto(&crypto->KEYBUF, &_in[0]); /* Do dummy encryption to generate decrypt key */ - crypto->CTRL = CRYPTO_CTRL_AES_AES128; - CRYPTO_IntClear(crypto, CRYPTO_IF_INSTRDONE); crypto->CMD = CRYPTO_CMD_INSTR_AESENC; /* Save decryption key */ @@ -1176,12 +1177,14 @@ void CRYPTO_AES_DecryptKey256(CRYPTO_TypeDef * crypto, uint32_t * _out = (uint32_t *) out; const uint32_t * _in = (const uint32_t *) in; + /* Setup CRYPTO in AES-256 mode. */ + crypto->CTRL = CRYPTO_CTRL_AES_AES256; + /* Load key */ CRYPTO_BurstToCrypto(&crypto->KEYBUF, &_in[0]); CRYPTO_BurstToCrypto(&crypto->KEYBUF, &_in[4]); /* Do dummy encryption to generate decrypt key */ - crypto->CTRL = CRYPTO_CTRL_AES_AES256; crypto->CMD = CRYPTO_CMD_INSTR_AESENC; /* Save decryption key */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_csen.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_csen.c new file mode 100644 index 0000000000..331fa724e5 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_csen.c @@ -0,0 +1,294 @@ +/***************************************************************************//** + * @file em_csen.c + * @brief Capacitive Sense Module (CSEN) peripheral API + * @version 5.1.2 + ******************************************************************************* + * @section License + * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************* + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + +#include "em_csen.h" +#if defined( CSEN_COUNT ) && ( CSEN_COUNT > 0 ) + +#include "em_assert.h" +#include "em_cmu.h" +#include + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup CSEN + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of CSEN register block pointer reference for assert statements. */ +#define CSEN_REF_VALID(ref) ((ref) == CSEN) + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Set the DM integrator initial value. + * + * @details + * Sets the initial value of the integrator(s) for the Delta Modulation (DM) + * converter. The initial value for the ramp-down integrator has no effect + * if low frequency attenuation was not selected by the mode initialization + * function @ref CSEN_InitMode(). + * + * @note + * Confirm CSEN is idle before calling this function. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] up + * Initial value for the ramp-up integrator. + * + * @param[in] down + * Initial value for the ramp-down integrator. Has no effect if low frequency + * attenuation is not configured. + ******************************************************************************/ +void CSEN_DMBaselineSet(CSEN_TypeDef *csen, uint32_t up, uint32_t down) +{ + EFM_ASSERT(up < 0x10000); + EFM_ASSERT(down < 0x10000); + + csen->DMBASELINE = (up << _CSEN_DMBASELINE_BASELINEUP_SHIFT) + | (down << _CSEN_DMBASELINE_BASELINEDN_SHIFT); +} + + +/***************************************************************************//** + * @brief + * Initialize CSEN. + * + * @details + * Initializes common functionality for all measurement types. In addition, + * measurement mode must be configured, please refer to @ref CSEN_InitMode(). + * + * @note + * This function will stop any ongoing conversion and disable CSEN. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] init + * Pointer to CSEN initialization structure. + ******************************************************************************/ +void CSEN_Init(CSEN_TypeDef *csen, const CSEN_Init_TypeDef *init) +{ + uint32_t tmp; + + EFM_ASSERT(CSEN_REF_VALID(csen)); + EFM_ASSERT(init->warmUpCount < 4); + + /* Initialize CTRL. This will stop any conversion in progress. */ + tmp = CSEN_CTRL_STM_DEFAULT; + + if (init->cpAccuracyHi) + { + tmp |= CSEN_CTRL_CPACCURACY_HI; + } + + if (init->localSense) + { + tmp |= _CSEN_CTRL_LOCALSENS_MASK; + } + + if (init->keepWarm) + { + tmp |= CSEN_CTRL_WARMUPMODE_KEEPCSENWARM; + } + + csen->CTRL = tmp; + + /* Initialize TIMCTRL. */ + csen->TIMCTRL = (init->warmUpCount << _CSEN_TIMCTRL_WARMUPCNT_SHIFT) + | (init->pcReload << _CSEN_TIMCTRL_PCTOP_SHIFT) + | (init->pcPrescale << _CSEN_TIMCTRL_PCPRESC_SHIFT); + + /* PRSSEL only has one field */ + csen->PRSSEL = init->prsSel << _CSEN_PRSSEL_PRSSEL_SHIFT; + + /* Set input selections for inputs 0 to 31 */ + csen->SCANINPUTSEL0 = (init->input0To7 << _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_SHIFT) + | (init->input8To15 << _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_SHIFT) + | (init->input16To23 << _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_SHIFT) + | (init->input24To31 << _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_SHIFT); + + /* Set input selections for inputs 32 to 63 */ + csen->SCANINPUTSEL1 = (init->input32To39 << _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_SHIFT) + | (init->input40To47 << _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_SHIFT) + | (init->input48To55 << _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_SHIFT) + | (init->input56To63 << _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_SHIFT); +} + + +/***************************************************************************//** + * @brief + * Initialize a CSEN measurement mode. + * + * @details + * Used to configure any type of measurement mode. After the measurement + * has been configured, calling @ref CSEN_Enable() will enable CSEN and + * allow it to start a conversion from the selected trigger source. To + * manually start a conversion use @ref CSEN_Start(). To check if a + * conversion is in progress use @ref CSEN_IsBusy(), or alternatively + * use the interrupt flags returned by @ref CSEN_IntGet() to detect when + * a conversion is completed. + * + * @note + * This function will stop any ongoing conversion and disable CSEN. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] init + * Pointer to CSEN measurement mode initialization structure. + ******************************************************************************/ +void CSEN_InitMode(CSEN_TypeDef *csen, const CSEN_InitMode_TypeDef *init) +{ + uint32_t tmp; + + EFM_ASSERT(CSEN_REF_VALID(csen)); + EFM_ASSERT(init->dmIterPerCycle < 0x10); + EFM_ASSERT(init->dmCycles < 0x10); + + /* Initialize CTRL. This will stop any conversion in progress. + * These composite inputs set multiple fields. They do not need + * to be shifted. */ + tmp = ((uint32_t)init->sampleMode + | (uint32_t)init->convSel + | (uint32_t)init->cmpMode); + + tmp |= (init->trigSel << _CSEN_CTRL_STM_SHIFT) + | (init->accMode << _CSEN_CTRL_ACU_SHIFT) + | (init->sarRes << _CSEN_CTRL_SARCR_SHIFT); + + if (init->enableDma) + { + tmp |= CSEN_CTRL_DMAEN_ENABLE; + } + + if (init->sumOnly) + { + tmp |= CSEN_CTRL_DRSF_ENABLE; + } + + if (init->autoGnd) + { + tmp |= CSEN_CTRL_AUTOGND_ENABLE; + } + + /* Preserve the fields that were initialized by CSEN_Init(). */ + tmp |= csen->CTRL & (_CSEN_CTRL_CPACCURACY_MASK + | _CSEN_CTRL_LOCALSENS_MASK + | _CSEN_CTRL_WARMUPMODE_MASK); + + csen->CTRL = tmp; + + /* EMACTRL only has one field */ + csen->EMACTRL = init->emaSample << _CSEN_EMACTRL_EMASAMPLE_SHIFT; + + /* CMPTHR only has one field */ + csen->CMPTHR = init->cmpThr << _CSEN_CMPTHR_CMPTHR_SHIFT; + + /* SINGLECTRL only has one field */ + csen->SINGLECTRL = init->singleSel << _CSEN_SINGLECTRL_SINGLESEL_SHIFT; + + /* Set all input enables */ + csen->SCANMASK0 = init->inputMask0; + csen->SCANMASK1 = init->inputMask1; + + /* Initialize DMCFG. */ + tmp = (init->dmRes << _CSEN_DMCFG_CRMODE_SHIFT) + | (init->dmCycles << _CSEN_DMCFG_DMCR_SHIFT) + | (init->dmIterPerCycle << _CSEN_DMCFG_DMR_SHIFT) + | (init->dmDelta << _CSEN_DMCFG_DMG_SHIFT); + + if (init->dmFixedDelta) + { + tmp |= CSEN_DMCFG_DMGRDIS; + } + + csen->DMCFG = tmp; + + /* Initialize ANACTRL. */ + csen->ANACTRL = (init->resetPhase << _CSEN_ANACTRL_TRSTPROG_SHIFT) + | (init->driveSel << _CSEN_ANACTRL_IDACIREFS_SHIFT) + | (init->gainSel << _CSEN_ANACTRL_IREFPROG_SHIFT); +} + + +/***************************************************************************//** + * @brief + * Reset CSEN to same state as after a HW reset. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + ******************************************************************************/ +void CSEN_Reset(CSEN_TypeDef *csen) +{ + EFM_ASSERT(CSEN_REF_VALID(csen)); + + /* Resetting CTRL stops any conversion in progress. */ + csen->CTRL = _CSEN_CTRL_RESETVALUE; + csen->TIMCTRL = _CSEN_TIMCTRL_RESETVALUE; + csen->PRSSEL = _CSEN_PRSSEL_RESETVALUE; + csen->DATA = _CSEN_DATA_RESETVALUE; + csen->SCANMASK0 = _CSEN_SCANMASK0_RESETVALUE; + csen->SCANINPUTSEL0 = _CSEN_SCANINPUTSEL0_RESETVALUE; + csen->SCANMASK1 = _CSEN_SCANMASK1_RESETVALUE; + csen->SCANINPUTSEL1 = _CSEN_SCANINPUTSEL1_RESETVALUE; + csen->CMPTHR = _CSEN_CMPTHR_RESETVALUE; + csen->EMA = _CSEN_EMA_RESETVALUE; + csen->EMACTRL = _CSEN_EMACTRL_RESETVALUE; + csen->SINGLECTRL = _CSEN_SINGLECTRL_RESETVALUE; + csen->DMBASELINE = _CSEN_DMBASELINE_RESETVALUE; + csen->DMCFG = _CSEN_DMCFG_RESETVALUE; + csen->ANACTRL = _CSEN_ANACTRL_RESETVALUE; + csen->IEN = _CSEN_IEN_RESETVALUE; + csen->IFC = _CSEN_IF_MASK; +} + + +/** @} (end addtogroup CSEN) */ +/** @} (end addtogroup emlib) */ +#endif /* defined(CSEN_COUNT) && (CSEN_COUNT > 0) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c index de6694d365..074dc94530 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dac.c * @brief Digital to Analog Converter (DAC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c index 0888225897..c259a967bd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dbg.c * @brief Debug (DBG) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c index 7dae4a395e..4ad4cdb8fa 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dma.c * @brief Direct memory access (DMA) module peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -173,7 +173,7 @@ static void DMA_Prepare(unsigned int channel, bool primary, bool useBurst, void *dst, - void *src, + const void *src, unsigned int nMinus1) { DMA_DESCRIPTOR_TypeDef *descr; @@ -209,7 +209,7 @@ static void DMA_Prepare(unsigned int channel, inc = (descr->CTRL & _DMA_CTRL_SRC_INC_MASK) >> _DMA_CTRL_SRC_INC_SHIFT; if (inc == _DMA_CTRL_SRC_INC_NONE) { - descr->SRCEND = src; + descr->SRCEND = (volatile void*)src; } else { @@ -386,7 +386,7 @@ void DMA_IRQHandler(void) void DMA_ActivateAuto(unsigned int channel, bool primary, void *dst, - void *src, + const void *src, unsigned int nMinus1) { uint32_t chBit; @@ -450,7 +450,7 @@ void DMA_ActivateBasic(unsigned int channel, bool primary, bool useBurst, void *dst, - void *src, + const void *src, unsigned int nMinus1) { EFM_ASSERT(channel < DMA_CHAN_COUNT); @@ -521,10 +521,10 @@ void DMA_ActivateBasic(unsigned int channel, void DMA_ActivatePingPong(unsigned int channel, bool useBurst, void *primDst, - void *primSrc, + const void *primSrc, unsigned int primNMinus1, void *altDst, - void *altSrc, + const void *altSrc, unsigned int altNMinus1) { EFM_ASSERT(channel < DMA_CHAN_COUNT); @@ -1136,7 +1136,7 @@ void DMA_RefreshPingPong(unsigned int channel, bool primary, bool useBurst, void *dst, - void *src, + const void *src, unsigned int nMinus1, bool stop) { @@ -1174,7 +1174,7 @@ void DMA_RefreshPingPong(unsigned int channel, inc = (descr->CTRL & _DMA_CTRL_SRC_INC_MASK) >> _DMA_CTRL_SRC_INC_SHIFT; if (inc == _DMA_CTRL_SRC_INC_NONE) { - descr->SRCEND = src; + descr->SRCEND = (volatile void*)src; } else { diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c index 6c1c5178c0..fd114788f7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_ebi.c * @brief External Bus Interface (EBI) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c index c5d329e6c6..154bae1252 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_emu.c * @brief Energy Management Unit (EMU) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -70,9 +70,10 @@ #error Conflict in LFXOENS and LFXOEN bitpositions #endif - /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Fix for errata EMU_E107 - non-WIC interrupt masks. */ +#if defined( _SILICON_LABS_32B_SERIES_0 ) +/* Fix for errata EMU_E107 - non-WIC interrupt masks. + * Zero Gecko and future families are not affected by errata EMU_E107 */ #if defined( _EFM32_GECKO_FAMILY ) #define ERRATA_FIX_EMU_E107_EN #define NON_WIC_INT_MASK_0 (~(0x0dfc0323U)) @@ -93,41 +94,65 @@ #define NON_WIC_INT_MASK_0 (~(0xff020e63U)) #define NON_WIC_INT_MASK_1 (~(0x00000046U)) -#else -/* Zero Gecko and future families are not affected by errata EMU_E107 */ +#endif #endif /* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */ -#if defined( _EFM32_HAPPY_FAMILY ) +#if defined(_SILICON_LABS_32B_SERIES_0) && defined( _EFM32_HAPPY_FAMILY ) #define ERRATA_FIX_EMU_E108_EN #endif /* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) #define ERRATA_FIX_EMU_E208_EN #endif /* Enable FETCNT tuning errata fix */ -#if defined( _EMU_DCDCCTRL_MASK ) && defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) #define ERRATA_FIX_DCDC_FETCNT_SET_EN #endif /* Enable LN handshake errata fix */ -#if defined( _EMU_DCDCCTRL_MASK ) && ( _SILICON_LABS_32B_PLATFORM_2_GEN < 3 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) #define ERRATA_FIX_DCDC_LNHS_BLOCK_EN +typedef enum +{ + errataFixDcdcHsInit, + errataFixDcdcHsTrimSet, + errataFixDcdcHsBypassLn, + errataFixDcdcHsLnWaitDone +} errataFixDcdcHs_TypeDef; +static errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit; #endif -/* Enable bypass current limiter enable timing fix */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_2 ) -#define ERRATA_FIX_BYPLIMEN_TIMING_EN +/* Used to figure out if a memory address is inside or outside of a RAM block. + * A memory address is inside a RAM block if the address is greater than the + * RAM block address. */ +#define ADDRESS_NOT_IN_BLOCK(addr, block) ((addr) <= (block)) + +/* RAM Block layout for various device families. Note that some devices + * have special layout in RAM0. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) +#define RAM1_BLOCKS 2 +#define RAM1_BLOCK_SIZE 0x10000 // 64 kB blocks +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) +#define RAM0_BLOCKS 2 +#define RAM0_BLOCK_SIZE 0x4000 +#define RAM1_BLOCKS 2 +#define RAM1_BLOCK_SIZE 0x4000 // 16 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) +#define RAM0_BLOCKS 4 +#define RAM0_BLOCK_SIZE 0x8000 // 32 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) +#define RAM0_BLOCKS 4 +#define RAM0_BLOCK_SIZE 0x1000 // 4 kB blocks #endif -#define EMU_DCDCCLIMCTRL (uint32_t *)(EMU_BASE + 0x054) -#if !defined(_EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT) -#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 -#endif -#if !defined(_EMU_PWRCTRL_DVDDBODDIS_SHIFT) -#define EMU_PWRCTRL_DVDDBODDIS (1 << 12) +#if defined(_SILICON_LABS_32B_SERIES_0) +/* RAM_MEM_END on Gecko devices have a value larger than the SRAM_SIZE */ +#define RAM0_END (SRAM_BASE + SRAM_SIZE - 1) +#else +#define RAM0_END RAM_MEM_END #endif /** @endcond */ @@ -141,41 +166,23 @@ #if !defined(PWRCFG_DCDCTODVDD_VMAX) #define PWRCFG_DCDCTODVDD_VMAX 3000 #endif - -typedef enum -{ - errataFixDcdcHsInit, - errataFixDcdcHsTrimSet, - errataFixDcdcHsBypassLn, - errataFixDcdcHsLnWaitDone -} errataFixDcdcHs_TypeDef; -errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit; #endif /******************************************************************************* - ************************** LOCAL VARIABLES ******************************** + *************************** LOCAL VARIABLES ******************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/** - * CMU configured oscillator selection and oscillator enable status. When a - * user configures oscillators, this varaiable shall shadow the configuration. - * It is used by the EMU module in order to be able to restore the oscillator - * config after having been in certain energy modes (since HW may automatically - * alter config when going into an energy mode). It is the responsibility of - * the CMU module to keep it up-to-date (or a user if not using the CMU API - * for oscillator control). - */ -static uint32_t cmuStatus; -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) -static uint16_t cmuHfclkStatus; -#endif + +/* Static user configuration */ #if defined( _EMU_DCDCCTRL_MASK ) static uint16_t dcdcMaxCurrent_mA; static uint16_t dcdcEm01LoadCurrent_mA; static EMU_DcdcLnReverseCurrentControl_TypeDef dcdcReverseCurrentControl; #endif - +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +static EMU_EM01Init_TypeDef vScaleEM01Config = {false}; +#endif /** @endcond */ @@ -185,147 +192,105 @@ static EMU_DcdcLnReverseCurrentControl_TypeDef dcdcReverseCurrentControl; /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/* Convert from level to EM0 and 1 command bit */ +__STATIC_INLINE uint32_t vScaleEM01Cmd(EMU_VScaleEM01_TypeDef level) +{ + return EMU_CMD_EM01VSCALE0 << (_EMU_STATUS_VSCALE_VSCALE0 - (uint32_t)level); +} +#endif + /***************************************************************************//** * @brief - * Restore oscillators and core clock after having been in EM2 or EM3. + * Save/restore/update oscillator, core clock and voltage scaling configuration on + * EM2 or EM3 entry/exit. + * + * @details + * Hardware may automatically change oscillator and voltage scaling configuration + * when going into or out of an energy mode. Static data in this function keeps track of + * such configuration bits and is used to restore state if needed. + * ******************************************************************************/ -static void emuRestore(void) +typedef enum +{ + emState_Save, /* Save EMU and CMU state */ + emState_Restore, /* Restore and unlock */ +} emState_TypeDef; + +static void emState(emState_TypeDef action) { uint32_t oscEnCmd; uint32_t cmuLocked; + static uint32_t cmuStatus; + static CMU_Select_TypeDef hfClock; +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + static uint8_t vScaleStatus; +#endif - /* Although we could use the CMU API for most of the below handling, we */ - /* would like this function to be as efficient as possible. */ - /* CMU registers may be locked */ - cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; - CMU_Unlock(); + /* Save or update state */ + if (action == emState_Save) + { + /* Save configuration. */ + cmuStatus = CMU->STATUS; + hfClock = CMU_ClockSelectGet(cmuClock_HF); +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + /* Save vscale */ + EMU_VScaleWait(); + vScaleStatus = (uint8_t)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) + >> _EMU_STATUS_VSCALE_SHIFT); +#endif + } + else if (action == emState_Restore) /* Restore state */ + { + /* Apply saved configuration. */ +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + /* Restore EM0 and 1 voltage scaling level. EMU_VScaleWait() is called later, + just before HF clock select is set. */ + EMU->CMD = vScaleEM01Cmd((EMU_VScaleEM01_TypeDef)vScaleStatus); +#endif - /* AUXHFRCO are automatically disabled (except if using debugger). */ - /* HFRCO, USHFRCO and HFXO are automatically disabled. */ - /* LFRCO/LFXO may be disabled by SW in EM3. */ - /* Restore according to status prior to entering energy mode. */ - oscEnCmd = 0; - oscEnCmd |= ((cmuStatus & CMU_STATUS_HFRCOENS) ? CMU_OSCENCMD_HFRCOEN : 0); - oscEnCmd |= ((cmuStatus & CMU_STATUS_AUXHFRCOENS) ? CMU_OSCENCMD_AUXHFRCOEN : 0); - oscEnCmd |= ((cmuStatus & CMU_STATUS_LFRCOENS) ? CMU_OSCENCMD_LFRCOEN : 0); - oscEnCmd |= ((cmuStatus & CMU_STATUS_HFXOENS) ? CMU_OSCENCMD_HFXOEN : 0); - oscEnCmd |= ((cmuStatus & CMU_STATUS_LFXOENS) ? CMU_OSCENCMD_LFXOEN : 0); + /* CMU registers may be locked */ + cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; + CMU_Unlock(); + + /* AUXHFRCO are automatically disabled (except if using debugger). */ + /* HFRCO, USHFRCO and HFXO are automatically disabled. */ + /* LFRCO/LFXO may be disabled by SW in EM3. */ + /* Restore according to status prior to entering energy mode. */ + oscEnCmd = 0; + oscEnCmd |= ((cmuStatus & CMU_STATUS_HFRCOENS) ? CMU_OSCENCMD_HFRCOEN : 0); + oscEnCmd |= ((cmuStatus & CMU_STATUS_AUXHFRCOENS) ? CMU_OSCENCMD_AUXHFRCOEN : 0); + oscEnCmd |= ((cmuStatus & CMU_STATUS_LFRCOENS) ? CMU_OSCENCMD_LFRCOEN : 0); + oscEnCmd |= ((cmuStatus & CMU_STATUS_HFXOENS) ? CMU_OSCENCMD_HFXOEN : 0); + oscEnCmd |= ((cmuStatus & CMU_STATUS_LFXOENS) ? CMU_OSCENCMD_LFXOEN : 0); #if defined( _CMU_STATUS_USHFRCOENS_MASK ) - oscEnCmd |= ((cmuStatus & CMU_STATUS_USHFRCOENS) ? CMU_OSCENCMD_USHFRCOEN : 0); + oscEnCmd |= ((cmuStatus & CMU_STATUS_USHFRCOENS) ? CMU_OSCENCMD_USHFRCOEN : 0); #endif - CMU->OSCENCMD = oscEnCmd; + CMU->OSCENCMD = oscEnCmd; - -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - /* Restore oscillator used for clocking core */ - switch (cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK) - { - case CMU_HFCLKSTATUS_SELECTED_LFRCO: - /* HFRCO could only be selected if the autostart HFXO feature is not - * enabled, otherwise the HFXO would be started and selected automatically. - * Note: this error hook helps catching erroneous oscillator configurations, - * when the AUTOSTARTSELEM0EM1 is set in CMU_HFXOCTRL. */ - if (!(CMU->HFXOCTRL & CMU_HFXOCTRL_AUTOSTARTSELEM0EM1)) - { - /* Wait for LFRCO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_LFRCORDY)) - ; - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFRCO; - } - else - { - EFM_ASSERT(0); - } - break; - - case CMU_HFCLKSTATUS_SELECTED_LFXO: - /* Wait for LFXO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_LFXORDY)) - ; - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFXO; - break; - - case CMU_HFCLKSTATUS_SELECTED_HFXO: - /* Wait for HFXO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_HFXORDY)) - ; -#if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK ) - if (BUS_RegMaskedRead(&CMU->HFXOCTRL, - _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) - == CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD) - { - while (BUS_RegMaskedRead(&CMU->STATUS, - _CMU_STATUS_HFXOSHUNTOPTRDY_MASK - | _CMU_STATUS_HFXOPEAKDETRDY_MASK) - != (CMU_STATUS_HFXOSHUNTOPTRDY | CMU_STATUS_HFXOPEAKDETRDY)) - ; - } -#endif - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO; - break; - - default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */ - /* If core clock was HFRCO core clock, it is automatically restored to */ - /* state prior to entering energy mode. No need for further action. */ - break; - } -#else - switch (cmuStatus & (CMU_STATUS_HFRCOSEL - | CMU_STATUS_HFXOSEL - | CMU_STATUS_LFRCOSEL -#if defined( CMU_STATUS_USHFRCODIV2SEL ) - | CMU_STATUS_USHFRCODIV2SEL -#endif - | CMU_STATUS_LFXOSEL)) - { - case CMU_STATUS_LFRCOSEL: - /* Wait for LFRCO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_LFRCORDY)) - ; - CMU->CMD = CMU_CMD_HFCLKSEL_LFRCO; - break; - - case CMU_STATUS_LFXOSEL: - /* Wait for LFXO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_LFXORDY)) - ; - CMU->CMD = CMU_CMD_HFCLKSEL_LFXO; - break; - - case CMU_STATUS_HFXOSEL: - /* Wait for HFXO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_HFXORDY)) - ; - CMU->CMD = CMU_CMD_HFCLKSEL_HFXO; - break; - -#if defined( CMU_STATUS_USHFRCODIV2SEL ) - case CMU_STATUS_USHFRCODIV2SEL: - /* Wait for USHFRCO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_USHFRCORDY)) - ; - CMU->CMD = _CMU_CMD_HFCLKSEL_USHFRCODIV2; - break; +#if defined( _EMU_STATUS_VSCALE_MASK ) + /* Wait for upscale to complete and then restore selected clock */ + EMU_VScaleWait(); #endif - default: /* CMU_STATUS_HFRCOSEL */ - /* If core clock was HFRCO core clock, it is automatically restored to */ - /* state prior to entering energy mode. No need for further action. */ - break; - } + if (hfClock != cmuSelect_HFRCO) + { + CMU_ClockSelectSet(cmuClock_HF, hfClock); + } - /* If HFRCO was disabled before entering Energy Mode, turn it off again */ - /* as it is automatically enabled by wake up */ - if ( ! (cmuStatus & CMU_STATUS_HFRCOENS) ) - { - CMU->OSCENCMD = CMU_OSCENCMD_HFRCODIS; - } -#endif - /* Restore CMU register locking */ - if (cmuLocked) - { - CMU_Lock(); + /* If HFRCO was disabled before entering Energy Mode, turn it off again */ + /* as it is automatically enabled by wake up */ + if ( ! (cmuStatus & CMU_STATUS_HFRCOENS) ) + { + CMU->OSCENCMD = CMU_OSCENCMD_HFRCODIS; + } + + /* Restore CMU register locking */ + if (cmuLocked) + { + CMU_Lock(); + } } } @@ -412,7 +377,49 @@ static void dcdcHsFixLnBlock(void) #endif +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) +/* Configure EMU and CMU for EM2 and 3 voltage downscale */ +static void vScaleDownEM23Setup(void) +{ + uint32_t hfSrcClockFrequency; + EMU_VScaleEM23_TypeDef scaleEM23Voltage = + (EMU_VScaleEM23_TypeDef)((EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) + >> _EMU_CTRL_EM23VSCALE_SHIFT); + + EMU_VScaleEM01_TypeDef currentEM01Voltage = + (EMU_VScaleEM01_TypeDef)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) + >> _EMU_STATUS_VSCALE_SHIFT); + + /* Wait until previous scaling is done. */ + EMU_VScaleWait(); + + /* Inverse coding. */ + if ((uint32_t)scaleEM23Voltage > (uint32_t)currentEM01Voltage) + { + /* Set safe clock and wait-states. */ + if (scaleEM23Voltage == emuVScaleEM23_LowPower) + { + hfSrcClockFrequency = CMU_ClockDivGet(cmuClock_HF) * CMU_ClockFreqGet(cmuClock_HF); + /* Set default low power voltage HFRCO band as HF clock. */ + if (hfSrcClockFrequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX) + { + CMU_HFRCOBandSet(cmuHFRCOFreq_19M0Hz); + } + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); + } + else + { + /* Other voltage scaling levels are not currently supported. */ + EFM_ASSERT(false); + } + } + else + { + /* Same voltage or hardware will scale to min(EMU_CTRL_EM23VSCALE, EMU_STATUS_VSCALE) */ + } +} +#endif /** @endcond */ @@ -458,9 +465,13 @@ static void dcdcHsFixLnBlock(void) * the starting and selecting of the core clocks will be identical to the user * independently of the value of the @p restore parameter when waking up on * the wakeup sources corresponding to the autostart and select setting. + * @par + * If voltage scaling is supported, the restore parameter is true and the EM0 + * voltage scaling level is set higher than the EM2 level, then the EM0 level is + * also restored. * * @param[in] restore - * @li true - restore oscillators and clocks, see function details. + * @li true - restore oscillators, clocks and voltage scaling, see function details. * @li false - do not restore oscillators and clocks, see function details. * @par * The @p restore option should only be used if all clock control is done @@ -473,11 +484,11 @@ void EMU_EnterEM2(bool restore) uint32_t nonWicIntEn[2]; #endif - /* Auto-update CMU status just in case before entering energy mode. */ - /* This variable is normally kept up-to-date by the CMU API. */ - cmuStatus = CMU->STATUS; -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS); + /* Save EMU and CMU state requiring restore on EM2 exit. */ + emState(emState_Save); + +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) + vScaleDownEM23Setup(); #endif /* Enter Cortex deep sleep mode */ @@ -504,9 +515,6 @@ void EMU_EnterEM2(bool restore) #if defined( ERRATA_FIX_DCDC_LNHS_BLOCK_EN ) dcdcHsFixLnBlock(); #endif -#if defined( ERRATA_FIX_BYPLIMEN_TIMING_EN ) - BUS_RegBitWrite(EMU_DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); -#endif __WFI(); @@ -525,21 +533,16 @@ void EMU_EnterEM2(bool restore) } #endif - /* Restore oscillators/clocks if specified */ + /* Restore oscillators/clocks and voltage scaling if supported. */ if (restore) { - emuRestore(); + emState(emState_Restore); } - /* If not restoring, and original clock was not HFRCO, we have to */ - /* update CMSIS core clock variable since core clock has changed */ - /* to using HFRCO. */ -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - else if ((cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK) - != CMU_HFCLKSTATUS_SELECTED_HFRCO) -#else - else if (!(cmuStatus & CMU_STATUS_HFRCOSEL)) -#endif + else { + /* If not restoring, and original clock was not HFRCO, we have to */ + /* update CMSIS core clock variable since HF clock has changed */ + /* to HFRCO. */ SystemCoreClockUpdate(); } } @@ -579,9 +582,13 @@ void EMU_EnterEM2(bool restore) * If a debugger is attached, the AUXHFRCO will not be disabled if enabled * upon entering EM3. It will thus remain enabled when returning to EM0 * regardless of the @p restore parameter. + * @par + * If voltage scaling is supported, the restore parameter is true and the EM0 + * voltage scaling level is set higher than the EM3 level, then the EM0 level is + * also restored. * * @param[in] restore - * @li true - restore oscillators and clocks, see function details. + * @li true - restore oscillators, clocks and voltage scaling, see function details. * @li false - do not restore oscillators and clocks, see function details. * @par * The @p restore option should only be used if all clock control is done @@ -596,11 +603,11 @@ void EMU_EnterEM3(bool restore) uint32_t nonWicIntEn[2]; #endif - /* Auto-update CMU status just in case before entering energy mode. */ - /* This variable is normally kept up-to-date by the CMU API. */ - cmuStatus = CMU->STATUS; -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS); + /* Save EMU and CMU state requiring restore on EM2 exit. */ + emState(emState_Save); + +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) + vScaleDownEM23Setup(); #endif /* CMU registers may be locked */ @@ -640,9 +647,6 @@ void EMU_EnterEM3(bool restore) #if defined( ERRATA_FIX_DCDC_LNHS_BLOCK_EN ) dcdcHsFixLnBlock(); #endif -#if defined( ERRATA_FIX_BYPLIMEN_TIMING_EN ) - BUS_RegBitWrite(EMU_DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); -#endif __WFI(); @@ -661,26 +665,36 @@ void EMU_EnterEM3(bool restore) } #endif - /* Restore oscillators/clocks if specified */ + /* Restore oscillators/clocks and voltage scaling if supported. */ if (restore) { - emuRestore(); + emState(emState_Restore); } - /* If not restoring, and original clock was not HFRCO, we have to */ - /* update CMSIS core clock variable since core clock has changed */ - /* to using HFRCO. */ -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - else if ((cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK) - != CMU_HFCLKSTATUS_SELECTED_HFRCO) -#else - else if (!(cmuStatus & CMU_STATUS_HFRCOSEL)) -#endif + else { + /* If not restoring, and original clock was not HFRCO, we have to */ + /* update CMSIS core clock variable since HF clock has changed */ + /* to HFRCO. */ SystemCoreClockUpdate(); } } +/***************************************************************************//** + * @brief + * Restore CMU HF clock select state, oscillator enable and voltage scaling + * (if available) after @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called + * with the restore parameter set to false. Calling this function is + * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the + * restore parameter set to true, but it allows the application to evaluate the + * wakeup reason before restoring state. + ******************************************************************************/ +void EMU_Restore(void) +{ + emState(emState_Restore); +} + + /***************************************************************************//** * @brief * Enter energy mode 4 (EM4). @@ -745,9 +759,6 @@ void EMU_EnterEM4(void) #if defined( ERRATA_FIX_DCDC_LNHS_BLOCK_EN ) dcdcHsFixLnBlock(); #endif -#if defined( ERRATA_FIX_BYPLIMEN_TIMING_EN ) - BUS_RegBitWrite(EMU_DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); -#endif for (i = 0; i < 4; i++) { @@ -805,69 +816,258 @@ void EMU_EnterEM4S(void) * memory blocks for a device. * * @note - * Only a reset can make the specified memory block(s) available for use - * after having been powered down. Function will be void for devices not - * supporting this feature. + * Only a POR reset can power up the specified memory block(s) after powerdown. + * + * @deprecated + * This function is deprecated, use @ref EMU_RamPowerDown() instead which + * maps a user provided memory range into RAM blocks to power down. ******************************************************************************/ void EMU_MemPwrDown(uint32_t blocks) { -#if defined( _EMU_MEMCTRL_POWERDOWN_MASK ) - EFM_ASSERT(blocks <= (_EMU_MEMCTRL_POWERDOWN_MASK - >> _EMU_MEMCTRL_POWERDOWN_SHIFT)); - EMU->MEMCTRL = blocks; - -#elif defined( _EMU_MEMCTRL_RAMPOWERDOWN_MASK ) \ - && defined( _EMU_MEMCTRL_RAMHPOWERDOWN_MASK ) \ - && defined( _EMU_MEMCTRL_SEQRAMPOWERDOWN_MASK ) - EFM_ASSERT((blocks & (_EMU_MEMCTRL_RAMPOWERDOWN_MASK - | _EMU_MEMCTRL_RAMHPOWERDOWN_MASK - | _EMU_MEMCTRL_SEQRAMPOWERDOWN_MASK)) - == blocks); - EMU->MEMCTRL = blocks; - -#elif defined( _EMU_MEMCTRL_RAMPOWERDOWN_MASK ) - EFM_ASSERT((blocks & _EMU_MEMCTRL_RAMPOWERDOWN_MASK) == blocks); - EMU->MEMCTRL = blocks; - -#elif defined( _EMU_RAM0CTRL_RAMPOWERDOWN_MASK ) - EFM_ASSERT((blocks & _EMU_RAM0CTRL_RAMPOWERDOWN_MASK) == blocks); - EMU->RAM0CTRL = blocks; - +#if defined( _EMU_MEMCTRL_MASK ) + EMU->MEMCTRL = blocks & _EMU_MEMCTRL_MASK; +#elif defined( _EMU_RAM0CTRL_MASK ) + EMU->RAM0CTRL = blocks & _EMU_RAM0CTRL_MASK; #else (void)blocks; #endif } +/***************************************************************************//** + * @brief + * Power down RAM memory blocks. + * + * @details + * This function will power down all the RAM blocks that are within a given + * range. The RAM block layout is different between device families, so this + * function can be used in a generic way to power down a RAM memory region + * which is known to be unused. + * + * This function will only power down blocks which are completely enclosed + * by the memory range given by [start, end). + * + * Here is an example of how to power down all RAM blocks except the first + * one. The first RAM block is special in that it cannot be powered down + * by the hardware. The size of this first RAM block is device specific + * see the reference manual to find the RAM block sizes. + * + * @code + * EMU_RamPowerDown(SRAM_BASE, SRAM_BASE + SRAM_SIZE); + * @endcode + * + * @note + * Only a POR reset can power up the specified memory block(s) after powerdown. + * + * @param[in] start + * The start address of the RAM region to power down. This address is + * inclusive. + * + * @param[in] end + * The end address of the RAM region to power down. This address is + * exclusive. If this parameter is 0, then all RAM blocks contained in the + * region from start to the upper RAM address will be powered down. + ******************************************************************************/ +void EMU_RamPowerDown(uint32_t start, uint32_t end) +{ + uint32_t mask = 0; + + if (end == 0) + { + end = SRAM_BASE + SRAM_SIZE; + } + + // Check to see if something in RAM0 can be powered down + if (end > RAM0_END) + { +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) // EFM32xG12 and EFR32xG12 + // Block 0 is 16 kB and cannot be powered off + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000) << 0; // Block 1, 16 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20008000) << 1; // Block 2, 16 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x2000C000) << 2; // Block 3, 16 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20010000) << 3; // Block 4, 64 kB +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) // EFM32xG1 and EFR32xG1 + // Block 0 is 4 kB and cannot be powered off + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20001000) << 0; // Block 1, 4 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20002000) << 1; // Block 2, 8 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000) << 2; // Block 3, 8 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000) << 3; // Block 4, 7 kB +#elif defined(RAM0_BLOCKS) + // These platforms have equally sized RAM blocks + for (int i = 1; i < RAM0_BLOCKS; i++) + { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM_MEM_BASE + (i * RAM0_BLOCK_SIZE)) << (i - 1); + } +#endif + } + + // Power down the selected blocks +#if defined( _EMU_MEMCTRL_MASK ) + EMU->MEMCTRL = EMU->MEMCTRL | mask; +#elif defined( _EMU_RAM0CTRL_MASK ) + EMU->RAM0CTRL = EMU->RAM0CTRL | mask; +#else + // These devices are unable to power down RAM blocks + (void) mask; + (void) start; +#endif + +#if defined(RAM1_MEM_END) + mask = 0; + if (end > RAM1_MEM_END) + { + for (int i = 0; i < RAM1_BLOCKS; i++) + { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM1_MEM_BASE + (i * RAM1_BLOCK_SIZE)) << i; + } + } + EMU->RAM1CTRL |= mask; +#endif +} + +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +/***************************************************************************//** + * @brief + * Set EM2 3 peripheral retention control. + * + * @param[in] periMask + * Peripheral select mask. Use | operator to select multiple peripheral, for example + * @ref emuPeripheralRetention_LEUART0 | @ref emuPeripheralRetention_VDAC0. + * @param[in] enable + * Peripheral retention enable (true) or disable (false). + * + * + * @note + * Only peripheral retention disable is currently supported. Peripherals are + * enabled by default, and can only be disabled. + ******************************************************************************/ +void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable) +{ + EFM_ASSERT(!enable); + EMU->EM23PERNORETAINCTRL = periMask & emuPeripheralRetention_ALL; +} +#endif + /***************************************************************************//** * @brief * Update EMU module with CMU oscillator selection/enable status. * - * @details - * When entering EM2 and EM3, the HW may change the core clock oscillator - * used, as well as disabling some oscillators. The user may optionally select - * to restore the oscillators after waking up from EM2 and EM3 through the - * SW API. - * - * However, in order to support this in a safe way, the EMU module must - * be kept up-to-date on the actual selected configuration. The CMU - * module must keep the EMU module up-to-date. - * - * This function is mainly intended for internal use by the CMU module, - * but if the applications changes oscillator configurations without - * using the CMU API, this function can be used to keep the EMU module - * up-to-date. + * @deprecated + * Oscillator status is saved in @ref EMU_EnterEM2() and @ref EMU_EnterEM3(). ******************************************************************************/ void EMU_UpdateOscConfig(void) { - /* Fetch current configuration */ - cmuStatus = CMU->STATUS; -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS); -#endif + emState(emState_Save); } +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/***************************************************************************//** + * @brief + * Voltage scale in EM0 and 1 by clock frequency. + * + * @param[in] clockFrequency + * Use CMSIS HF clock if 0, or override to custom clock. Providing a + * custom clock frequency is required if using a non-standard HFXO + * frequency. + * @param[in] wait + * Wait for scaling to complate. + * + * @note + * This function is primarely needed by the @ref CMU module. + ******************************************************************************/ +void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait) +{ + uint32_t hfSrcClockFrequency; + uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT); + + /* VSCALE frequency is HFSRCCLK */ + if (clockFrequency == 0) + { + hfSrcClockFrequency = SystemHFClockGet() * hfPresc; + } + else + { + hfSrcClockFrequency = clockFrequency; + } + + /* Apply EM0 and 1 voltage scaling command. */ + if (vScaleEM01Config.vScaleEM01LowPowerVoltageEnable + && (hfSrcClockFrequency < CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) + { + EMU->CMD = vScaleEM01Cmd(emuVScaleEM01_LowPower); + } + else + { + EMU->CMD = vScaleEM01Cmd(emuVScaleEM01_HighPerformance); + } + + if (wait) + { + EMU_VScaleWait(); + } +} +#endif + + +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/***************************************************************************//** + * @brief + * Force voltage scaling in EM0 and 1 to a specific voltage level. + * + * @param[in] voltage + * Target VSCALE voltage level. + * @param[in] wait + * Wait for scaling to complate. + * + * @note + * This function is useful for upscaling before programming Flash from @ref MSC, + * and downscaling after programming is done. Flash programming is only supported + * at @ref emuVScaleEM01_HighPerformance. + * + * @note + * This function ignores @ref vScaleEM01LowPowerVoltageEnable set from @ref + * EMU_EM01Init(). + ******************************************************************************/ +void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait) +{ + uint32_t hfSrcClockFrequency; + uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT); + hfSrcClockFrequency = SystemHFClockGet() * hfPresc; + + if (voltage == emuVScaleEM01_LowPower) + { + EFM_ASSERT(hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX); + } + + EMU->CMD = vScaleEM01Cmd(voltage); + if (wait) + { + EMU_VScaleWait(); + } +} +#endif + + +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/***************************************************************************//** + * @brief + * Update EMU module with Energy Mode 0 and 1 configuration + * + * @param[in] em01Init + * Energy Mode 0 and 1 configuration structure + ******************************************************************************/ +void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init) +{ + vScaleEM01Config.vScaleEM01LowPowerVoltageEnable = + em01Init->vScaleEM01LowPowerVoltageEnable; + EMU_VScaleEM01ByClock(0, true); +} +#endif + + /***************************************************************************//** * @brief * Update EMU module with Energy Mode 2 and 3 configuration @@ -875,7 +1075,7 @@ void EMU_UpdateOscConfig(void) * @param[in] em23Init * Energy Mode 2 and 3 configuration structure ******************************************************************************/ -void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init) +void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init) { #if defined( _EMU_CTRL_EMVREG_MASK ) EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EMVREG) @@ -886,6 +1086,11 @@ void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init) #else (void)em23Init; #endif + +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) + EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM23VSCALE_MASK) + | (em23Init->vScaleEM23Voltage << _EMU_CTRL_EM23VSCALE_SHIFT); +#endif } @@ -897,7 +1102,7 @@ void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init) * @param[in] em4Init * Energy Mode 4 configuration structure ******************************************************************************/ -void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init) +void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init) { #if defined( _EMU_EM4CONF_MASK ) /* Init for platforms with EMU->EM4CONF register */ @@ -937,6 +1142,11 @@ void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init) EMU->EM4CTRL = em4ctrl; #endif + +#if defined( _EMU_CTRL_EM4HVSCALE_MASK ) + EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM4HVSCALE_MASK) + | (em4Init->vScaleEM4HVoltage << _EMU_CTRL_EM4HVSCALE_SHIFT); +#endif } #endif @@ -949,7 +1159,7 @@ void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init) * @param[in] bupdInit * Backup power domain initialization structure ******************************************************************************/ -void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit) +void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit) { uint32_t reg; @@ -1055,8 +1265,8 @@ void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value) #endif +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ #if defined( _EMU_DCDCCTRL_MASK ) - /* Translate fields with different names across platform generations to common names. */ #if defined( _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK ) #define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK @@ -1073,7 +1283,15 @@ void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value) #define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT #endif -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Internal DCDC trim modes. */ +typedef enum +{ + dcdcTrimMode_EM234H_LP = 0, +#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK ) + dcdcTrimMode_EM01_LP, +#endif + dcdcTrimMode_LN, +} dcdcTrimMode_TypeDef; /***************************************************************************//** * @brief @@ -1083,9 +1301,9 @@ void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value) * @return * False if calibration registers are locked ******************************************************************************/ -static bool ConstCalibrationLoad(void) +static bool dcdcConstCalibrationLoad(void) { -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) uint32_t val; volatile uint32_t *reg; @@ -1129,10 +1347,7 @@ static bool ConstCalibrationLoad(void) /* Return when assertions are disabled */ return false; -#elif defined( _SILICON_LABS_32B_PLATFORM_2_GEN_2 ) - return true; #else -#error "Undefined platform 2 generation." return true; #endif } @@ -1143,7 +1358,7 @@ static bool ConstCalibrationLoad(void) * Set recommended and validated current optimization and timing settings * ******************************************************************************/ -static void ValidatedConfigSet(void) +static void dcdcValidatedConfigSet(void) { /* Disable LP mode hysterysis in the state machine control */ #define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) @@ -1151,14 +1366,13 @@ static void ValidatedConfigSet(void) #define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) #define EMU_DCDCSMCTRL (* (volatile uint32_t *)(EMU_BASE + 0x44)) -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) + uint32_t lnForceCcm; + +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) uint32_t dcdcTiming; - SYSTEM_PartFamily_TypeDef family; SYSTEM_ChipRevision_TypeDef rev; #endif - uint32_t lnForceCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); - /* Enable duty cycling of the bias */ EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN; @@ -1166,6 +1380,7 @@ static void ValidatedConfigSet(void) * LNFORCECCM is default 1 for EFR32 * LNFORCECCM is default 0 for EFM32 */ + lnForceCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); if (lnForceCcm) { /* 7MHz is recommended for LNFORCECCM = 1 */ @@ -1177,18 +1392,14 @@ static void ValidatedConfigSet(void) EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); } -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK; EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LPCMPHYSDIS | EMU_DCDCMISCCTRL_LPCMPHYSHI; - family = SYSTEM_GetFamily(); SYSTEM_ChipRevisionGet(&rev); - if ((((family >= systemPartFamilyMighty1P) - && (family <= systemPartFamilyFlex1V)) - || (family == systemPartFamilyEfm32Pearl1B) - || (family == systemPartFamilyEfm32Jade1B)) - && ((rev.major == 1) && (rev.minor < 3)) + if ((rev.major == 1) + && (rev.minor < 3) && (errataFixDcdcHsState == errataFixDcdcHsInit)) { /* LPCMPWAITDIS = 1 */ @@ -1315,16 +1526,14 @@ static void userCurrentLimitsSet(uint32_t maxCurrent_mA, ******************************************************************************/ static void compCtrlSet(EMU_DcdcLnCompCtrl_TypeDef comp) { -#define EMU_DCDCLNCOMPCTRL (*(volatile uint32_t *) (EMU_BASE + 0x58UL)) - switch (comp) { case emuDcdcLnCompCtrl_1u0F: - EMU_DCDCLNCOMPCTRL = 0x57204077UL; + EMU->DCDCLNCOMPCTRL = 0x57204077UL; break; case emuDcdcLnCompCtrl_4u7F: - EMU_DCDCLNCOMPCTRL = 0xB7102137UL; + EMU->DCDCLNCOMPCTRL = 0xB7102137UL; break; default: @@ -1338,21 +1547,29 @@ static void compCtrlSet(EMU_DcdcLnCompCtrl_TypeDef comp) * Load EMU_DCDCLPCTRL_LPCMPHYSSEL depending on LP bias, LP feedback * attenuation and DEVINFOREV. * - * @param[in] attSet + * @param[in] lpAttenuation * LP feedback attenuation. * @param[in] lpCmpBias - * lpCmpBias selection (unshifted) + * lpCmpBias selection. + * @param[in] trimMode + * DCDC trim mode. ******************************************************************************/ -static bool LpCmpHystCalibrationLoad(bool lpAttenuation, uint32_t lpCmpBias) +static bool lpCmpHystCalibrationLoad(bool lpAttenuation, + uint8_t lpCmpBias, + dcdcTrimMode_TypeDef trimMode) { - uint8_t devinfoRev; uint32_t lpcmpHystSel; /* Get calib data revision */ - devinfoRev = SYSTEM_GetDevinfoRev(); +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + uint8_t devinfoRev = SYSTEM_GetDevinfoRev(); /* Load LPATT indexed calibration data */ if (devinfoRev < 4) +#else + /* Format change not present of newer families. */ + if (false) +#endif { lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL0; @@ -1378,17 +1595,17 @@ static bool LpCmpHystCalibrationLoad(bool lpAttenuation, uint32_t lpCmpBias) >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT; break; - case 1 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: + case 1: lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK) >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT; break; - case 2 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: + case 2: lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK) >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT; break; - case 3 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: + case 3: lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK) >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT; break; @@ -1399,19 +1616,138 @@ static bool LpCmpHystCalibrationLoad(bool lpAttenuation, uint32_t lpCmpBias) return false; } } - /* Make sure the sel value is within the field range. */ - lpcmpHystSel <<= _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT; - if (lpcmpHystSel & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) + + /* Set trims */ + if (trimMode == dcdcTrimMode_EM234H_LP) { - EFM_ASSERT(false); - /* Return when assertions are disabled */ - return false; + /* Make sure the sel value is within the field range. */ + lpcmpHystSel <<= _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT; + if (lpcmpHystSel & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) + { + EFM_ASSERT(false); + /* Return when assertions are disabled */ + return false; + } + EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) | lpcmpHystSel; } - EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) | lpcmpHystSel; + +#if defined( _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK ) + if (trimMode == dcdcTrimMode_EM01_LP) + { + /* Make sure the sel value is within the field range. */ + lpcmpHystSel <<= _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT; + if (lpcmpHystSel & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) + { + EFM_ASSERT(false); + /* Return when assertions are disabled */ + return false; + } + EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) | lpcmpHystSel; + } +#endif return true; } + +/***************************************************************************//** + * @brief + * Load LPVREF low and high from DEVINFO. + * + * @param[out] vrefL + * LPVREF low from DEVINFO. + * @param[out] vrefH + * LPVREF high from DEVINFO. + * @param[in] lpAttenuation + * LP feedback attenuation. + * @param[in] lpcmpBias + * lpcmpBias to lookup in DEVINFO. + ******************************************************************************/ +static void lpGetDevinfoVrefLowHigh(uint32_t *vrefL, + uint32_t *vrefH, + bool lpAttenuation, + uint8_t lpcmpBias) +{ + uint32_t vrefLow = 0; + uint32_t vrefHigh = 0; + + /* Find VREF high and low in DEVINFO indexed by LPCMPBIAS (lpcmpBias) + and LPATT (lpAttenuation) */ + uint32_t switchVal = (lpcmpBias << 8) | (lpAttenuation ? 1 : 0); + switch (switchVal) + { + case ((0 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL2; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT; + break; + + case ((1 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL2; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT; + break; + + case ((2 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL3; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT; + break; + + case ((3 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL3; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT; + break; + + case ((0 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL0; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT; + break; + + case ((1 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL0; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT; + break; + + case ((2 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL1; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT; + break; + + case ((3 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL1; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT; + break; + + default: + EFM_ASSERT(false); + break; + } + *vrefL = vrefLow; + *vrefH = vrefHigh; +} + /** @endcond */ /***************************************************************************//** @@ -1431,11 +1767,11 @@ void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) return; } -#if defined(_SILICON_LABS_32B_PLATFORM_2_GEN_1) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY); /* Configure bypass current limiter */ - BUS_RegBitWrite(EMU_DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, dcdcMode == emuDcdcMode_Bypass ? 0 : 1); + BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, dcdcMode == emuDcdcMode_Bypass ? 0 : 1); /* Fix for errata DCDC_E203 */ if (((EMU_DcdcMode_TypeDef)currentDcdcMode == emuDcdcMode_Bypass) @@ -1444,8 +1780,9 @@ void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) errataFixDcdcHsState = errataFixDcdcHsBypassLn; } -#elif defined(_SILICON_LABS_32B_PLATFORM_2_GEN_2) +#else + /* Fix for errata DCDC_E204 */ if (((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_OFF) || (currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS)) && ((dcdcMode == emuDcdcMode_LowPower) || (dcdcMode == emuDcdcMode_LowNoise))) { @@ -1455,21 +1792,65 @@ void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | EMU_DCDCCTRL_DCDCMODE_LOWNOISE; while(!(EMU_IntGet() & EMU_IF_DCDCLNRUNNING)); } - else if (dcdcMode == emuDcdcMode_Bypass) - { - /* Enable limiter to remove current peak. Disable again in EMU_EnterEM2/3/4 */ - while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY); - BUS_RegBitWrite(EMU_DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 1); - } -#else -#error "DCDC mode handling is undefined for this family." #endif /* Set user requested mode. */ + while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY); EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | dcdcMode; } +/***************************************************************************//** + * @brief + * Set DCDC LN regulator conduction mode + * + * @param[in] conductionMode + * DCDC LN conduction mode. + * @param[in] rcoDefaultSet + * The default DCDC RCO band for the conductionMode will be used if true. + * Otherwise the current RCO configuration is used. + ******************************************************************************/ +void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet) +{ + EMU_DcdcMode_TypeDef currentDcdcMode + = (EMU_DcdcMode_TypeDef)(EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK); + EMU_DcdcLnRcoBand_TypeDef rcoBand + = (EMU_DcdcLnRcoBand_TypeDef)((EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK) + >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT); + + /* Set bypass mode and wait for bypass mode to settle before + EMU_DCDCMISCCTRL_LNFORCECCM is set. Restore current DCDC mode. */ + EMU_IntClear(EMU_IFC_DCDCINBYPASS); + EMU_DCDCModeSet(emuDcdcMode_Bypass); + while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY); + while(!(EMU_IntGet() & EMU_IF_DCDCINBYPASS)); + if (conductionMode == emuDcdcConductionMode_DiscontinuousLN) + { + EMU->DCDCMISCCTRL &= ~ EMU_DCDCMISCCTRL_LNFORCECCM; + if (rcoDefaultSet) + { + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); + } + else + { + /* emuDcdcConductionMode_DiscontinuousLN supports up to 4MHz LN RCO. */ + EFM_ASSERT(rcoBand <= emuDcdcLnRcoBand_4MHz); + } + } + else + { + EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LNFORCECCM; + if (rcoDefaultSet) + { + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz); + } + } + EMU_DCDCModeSet(currentDcdcMode); + /* Update slice configuration as it depends on conduction mode and RCO band. */ + EMU_DCDCOptimizeSlice(dcdcEm01LoadCurrent_mA); +} + + /***************************************************************************//** * @brief * Configure DCDC regulator @@ -1485,20 +1866,18 @@ void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) * @return * True if initialization parameters are valid ******************************************************************************/ -bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) +bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit) { -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - uint32_t lpCmpBiasSelEM01; -#endif uint32_t lpCmpBiasSelEM234H; +#if defined(_EMU_PWRCFG_MASK) /* Set external power configuration. This enables writing to the other DCDC registers. */ - EMU->PWRCFG = dcdcInit->powerConfig; + EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; /* EMU->PWRCFG is write-once and POR reset only. Check that we could set the desired power configuration. */ - if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != dcdcInit->powerConfig) + if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != EMU_PWRCFG_PWRCFG_DCDCTODVDD) { /* If this assert triggers unexpectedly, please power cycle the kit to reset the power configuration. */ @@ -1506,23 +1885,25 @@ bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) /* Return when assertions are disabled */ return false; } +#endif /* Load DCDC calibration data from the DI page */ - ConstCalibrationLoad(); + dcdcConstCalibrationLoad(); /* Check current parameters */ EFM_ASSERT(dcdcInit->maxCurrent_mA <= 200); EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= dcdcInit->maxCurrent_mA); EFM_ASSERT(dcdcInit->reverseCurrentControl <= 200); - /* DCDC low-noise supports max 200mA */ if (dcdcInit->dcdcMode == emuDcdcMode_LowNoise) { + /* DCDC low-noise supports max 200mA */ EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 200); } -#if (_SILICON_LABS_32B_PLATFORM_2_GEN > 1) +#if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80) else if (dcdcInit->dcdcMode == emuDcdcMode_LowPower) { + /* Up to 10mA is supported for EM01-LP mode. */ EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 10); } #endif @@ -1530,22 +1911,6 @@ bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) /* EM2/3/4 current above 10mA is not supported */ EFM_ASSERT(dcdcInit->em234LoadCurrent_uA <= 10000); - /* Decode LP comparator bias for EM0/1 and EM2/3 */ -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - lpCmpBiasSelEM01 = EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3; - if (dcdcInit->dcdcMode == emuDcdcMode_LowPower) - { - if (dcdcInit->em01LoadCurrent_mA <= 1) - { - lpCmpBiasSelEM01 = EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1; - } - else if (dcdcInit->em01LoadCurrent_mA <= 3) - { - lpCmpBiasSelEM01 = EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2; - } - } -#endif - if (dcdcInit->em234LoadCurrent_uA < 75) { lpCmpBiasSelEM234H = 0; @@ -1575,14 +1940,15 @@ bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) | (dcdcInit->reverseCurrentControl >= 0 ? EMU_DCDCMISCCTRL_LNFORCECCM : 0)); #if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + /* Only 10mA EM01-LP current is supported */ EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - | lpCmpBiasSelEM01; + | EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3; #endif /* 2. Set recommended and validated current optimization settings <= Depends on LNFORCECCM => Updates DCDCLNFREQCTRL_RCOBAND */ - ValidatedConfigSet(); + dcdcValidatedConfigSet(); /* 3. Updated static currents and limits user data. Limiters are updated in EMU_DCDCOptimizeSlice() */ @@ -1611,27 +1977,28 @@ bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) return false; } -#if ( _SILICON_LABS_32B_PLATFORM_2_GEN == 1 ) +#if ( _SILICON_LABS_GECKO_INTERNAL_SDID == 80 ) /* Select analog peripheral power supply. This must be done before - DCDC mode is set for GEN_1. */ + DCDC mode is set for all EFM32xG1 and EFR32xG1 devices. */ BUS_RegBitWrite(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_SHIFT, dcdcInit->anaPeripheralPower ? 1 : 0); #endif +#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) + /* Select DVDD as input to the digital regulator. The switch to DVDD will take + effect once the DCDC output is stable. */ + EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; +#endif + /* Set EM0 DCDC operating mode. Output voltage set in EMU_DCDCOutputVoltageSet() above takes effect if mode is changed from bypass/off mode. */ EMU_DCDCModeSet(dcdcInit->dcdcMode); - /* Select DVDD as input to the digital regulator */ -#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) - EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; -#endif - -#if ( _SILICON_LABS_32B_PLATFORM_2_GEN > 1 ) +#if ( _SILICON_LABS_GECKO_INTERNAL_SDID != 80 ) /* Select analog peripheral power supply. This must be done after - DCDC mode is set for GEN > 1. */ + DCDC mode is set for all devices other than EFM32xG1 and EFR32xG1. */ BUS_RegBitWrite(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_SHIFT, dcdcInit->anaPeripheralPower ? 1 : 0); @@ -1640,7 +2007,6 @@ bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) return true; } - /***************************************************************************//** * @brief * Set DCDC output voltage @@ -1657,27 +2023,21 @@ bool EMU_DCDCOutputVoltageSet(uint32_t mV, { #if defined( _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK ) +#define DCDC_TRIM_MODES ((uint8_t)dcdcTrimMode_LN + 1) bool validOutVoltage; - uint8_t lnMode; - bool attSet; - uint32_t attMask; - uint32_t vrefLow = 0; - uint32_t vrefHigh = 0; - uint32_t vrefVal = 0; + bool attenuationSet; uint32_t mVlow = 0; uint32_t mVhigh = 0; - uint32_t vrefShift; - uint32_t lpcmpBias; - volatile uint32_t* ctrlReg; + uint32_t mVdiff; + uint32_t vrefVal[DCDC_TRIM_MODES] = {0}; + uint32_t vrefLow[DCDC_TRIM_MODES] = {0}; + uint32_t vrefHigh[DCDC_TRIM_MODES] = {0}; + uint8_t lpcmpBias[DCDC_TRIM_MODES] = {0}; /* Check that the set voltage is within valid range. Voltages are obtained from the datasheet. */ - validOutVoltage = false; - if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) == EMU_PWRCFG_PWRCFG_DCDCTODVDD) - { - validOutVoltage = ((mV >= PWRCFG_DCDCTODVDD_VMIN) - && (mV <= PWRCFG_DCDCTODVDD_VMAX)); - } + validOutVoltage = ((mV >= PWRCFG_DCDCTODVDD_VMIN) + && (mV <= PWRCFG_DCDCTODVDD_VMAX)); if (!validOutVoltage) { @@ -1686,167 +2046,127 @@ bool EMU_DCDCOutputVoltageSet(uint32_t mV, return false; } - /* Populate both LP and LN registers, set control reg pointer and VREF shift. */ - for (lnMode = 0; lnMode <= 1; lnMode++) + /* Set attenuation to use and low/high range. */ + attenuationSet = (mV > 1800); + if (attenuationSet) { - if (((lnMode == 0) && !setLpVoltage) - || ((lnMode == 1) && !setLnVoltage)) - { - continue; - } + mVlow = 1800; + mVhigh = 3000; + mVdiff = mVhigh - mVlow; + } + else + { + mVlow = 1200; + mVhigh = 1800; + mVdiff = mVhigh - mVlow; + } - ctrlReg = (lnMode ? &EMU->DCDCLNVCTRL : &EMU->DCDCLPVCTRL); - vrefShift = (lnMode ? _EMU_DCDCLNVCTRL_LNVREF_SHIFT - : _EMU_DCDCLPVCTRL_LPVREF_SHIFT); + /* Get 2-point calib data from DEVINFO */ - /* Set attenuation to use */ - attSet = (mV > 1800); - /* Always set mVlow different from mVhigh to avoid division by zero */ - /* further down. */ - if (attSet) + /* LN mode */ + if (attenuationSet) { - mVlow = 1800; - mVhigh = 3000; - attMask = (lnMode ? EMU_DCDCLNVCTRL_LNATT : EMU_DCDCLPVCTRL_LPATT); + vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; + vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) + >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT; + vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT; } else { - mVlow = 1200; - mVhigh = 1800; - attMask = 0; + vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; + vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT; + vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT; } - /* Get 2-point calib data from DEVINFO, calculate trimming and set voltege */ - if (lnMode) - { - /* Set low-noise DCDC output voltage tuning */ - if (attSet) - { - vrefLow = DEVINFO->DCDCLNVCTRL0; - vrefHigh = (vrefLow & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) - >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK) - >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT; - } - else - { - vrefLow = DEVINFO->DCDCLNVCTRL0; - vrefHigh = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK) - >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK) - >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT; - } - } - else - { - /* Set low-power DCDC output voltage tuning */ - /* Get LPCMPBIAS and make sure masks are not overlayed */ - lpcmpBias = EMU->DCDCMISCCTRL & _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK; - EFM_ASSERT(!(_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK & attMask)); - switch (attMask | lpcmpBias) - { - case EMU_DCDCLPVCTRL_LPATT: - vrefLow = DEVINFO->DCDCLPVCTRL2; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT; - break; + /* LP EM234H mode */ + lpcmpBias[dcdcTrimMode_EM234H_LP] = (EMU->DCDCMISCCTRL & _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) + >> _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; + lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM234H_LP], + &vrefHigh[dcdcTrimMode_EM234H_LP], + attenuationSet, + lpcmpBias[dcdcTrimMode_EM234H_LP]); - case EMU_DCDCLPVCTRL_LPATT | 1 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL2; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT; - break; - - case EMU_DCDCLPVCTRL_LPATT | 2 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL3; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT; - break; - - case EMU_DCDCLPVCTRL_LPATT | 3 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL3; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT; - break; - - case 0: - vrefLow = DEVINFO->DCDCLPVCTRL0; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT; - break; - - case 1 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL0; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT; - break; - - case 2 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL1; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT; - break; - - case 3 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL1; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT; - break; - - default: - EFM_ASSERT(false); - break; - } - - /* Load LP comparator hysteresis calibration */ - if(!(LpCmpHystCalibrationLoad(attSet, lpcmpBias))) - { - EFM_ASSERT(false); - /* Return when assertions are disabled */ - return false; - } - } /* Low-nise / low-power mode */ +#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK ) + /* LP EM01 mode */ + lpcmpBias[dcdcTrimMode_EM01_LP] = (EMU->DCDCLPEM01CFG & _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + >> _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT; + lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM01_LP], + &vrefHigh[dcdcTrimMode_EM01_LP], + attenuationSet, + lpcmpBias[dcdcTrimMode_EM01_LP]); +#endif - /* Check for valid 2-point trim values */ - if (mVlow >= mVhigh) + /* Calculate output voltage trims */ + vrefVal[dcdcTrimMode_LN] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_LN] - vrefLow[dcdcTrimMode_LN])) + / mVdiff; + vrefVal[dcdcTrimMode_LN] += vrefLow[dcdcTrimMode_LN]; + + vrefVal[dcdcTrimMode_EM234H_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM234H_LP] - vrefLow[dcdcTrimMode_EM234H_LP])) + / mVdiff; + vrefVal[dcdcTrimMode_EM234H_LP] += vrefLow[dcdcTrimMode_EM234H_LP]; + +#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK ) + vrefVal[dcdcTrimMode_EM01_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM01_LP] - vrefLow[dcdcTrimMode_EM01_LP])) + / mVdiff; + vrefVal[dcdcTrimMode_EM01_LP] += vrefLow[dcdcTrimMode_EM01_LP]; +#endif + + /* Range checks */ + if ((vrefVal[dcdcTrimMode_LN] > vrefHigh[dcdcTrimMode_LN]) + || (vrefVal[dcdcTrimMode_LN] < vrefLow[dcdcTrimMode_LN]) +#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK ) + || (vrefVal[dcdcTrimMode_EM01_LP] > vrefHigh[dcdcTrimMode_EM01_LP]) + || (vrefVal[dcdcTrimMode_EM01_LP] < vrefLow[dcdcTrimMode_EM01_LP]) +#endif + || (vrefVal[dcdcTrimMode_EM234H_LP] > vrefHigh[dcdcTrimMode_EM234H_LP]) + || (vrefVal[dcdcTrimMode_EM234H_LP] < vrefLow[dcdcTrimMode_EM234H_LP])) + { + EFM_ASSERT(false); + /* Return when assertions are disabled */ + return false; + } + + /* Update output voltage tuning for LN and LP modes. */ + if (setLnVoltage) + { + EMU->DCDCLNVCTRL = (EMU->DCDCLNVCTRL & ~(_EMU_DCDCLNVCTRL_LNVREF_MASK | _EMU_DCDCLNVCTRL_LNATT_MASK)) + | (vrefVal[dcdcTrimMode_LN] << _EMU_DCDCLNVCTRL_LNVREF_SHIFT) + | (attenuationSet ? EMU_DCDCLNVCTRL_LNATT : 0); + } + + if (setLpVoltage) + { + /* Load LP EM234H comparator hysteresis calibration */ + if(!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM234H_LP], dcdcTrimMode_EM234H_LP))) { EFM_ASSERT(false); /* Return when assertions are disabled */ return false; } - /* Calculate and set voltage trim */ - vrefVal = ((mV - mVlow) * (vrefHigh - vrefLow)) / (mVhigh - mVlow); - vrefVal += vrefLow; - - /* Range check */ - if ((vrefVal > vrefHigh) || (vrefVal < vrefLow)) +#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK ) + /* Load LP EM234H comparator hysteresis calibration */ + if(!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM01_LP], dcdcTrimMode_EM01_LP))) { EFM_ASSERT(false); /* Return when assertions are disabled */ return false; } - /* Update DCDCLNVCTRL/DCDCLPVCTRL */ - *ctrlReg = (vrefVal << vrefShift) | attMask; + /* LP VREF is that max of trims for EM01 and EM234H. */ + vrefVal[dcdcTrimMode_EM234H_LP] = SL_MAX(vrefVal[dcdcTrimMode_EM234H_LP], vrefVal[dcdcTrimMode_EM01_LP]); +#endif + + /* Don't exceed max available code as specified in the reference manual for EMU_DCDCLPVCTRL. */ + vrefVal[dcdcTrimMode_EM234H_LP] = SL_MIN(vrefVal[dcdcTrimMode_EM234H_LP], 0xE7U); + EMU->DCDCLPVCTRL = (EMU->DCDCLPVCTRL & ~(_EMU_DCDCLPVCTRL_LPVREF_MASK | _EMU_DCDCLPVCTRL_LPATT_MASK)) + | (vrefVal[dcdcTrimMode_EM234H_LP] << _EMU_DCDCLPVCTRL_LPVREF_SHIFT) + | (attenuationSet ? EMU_DCDCLPVCTRL_LPATT : 0); } #endif return true; @@ -1969,11 +2289,15 @@ bool EMU_DCDCPowerOff(void) { bool dcdcModeSet; +#if defined(_EMU_PWRCFG_MASK) /* Set DCDCTODVDD only to enable write access to EMU->DCDCCTRL */ EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; +#endif /* Select DVDD as input to the digital regulator */ -#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) +#if defined(EMU_PWRCTRL_IMMEDIATEPWRSWITCH) + EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD | EMU_PWRCTRL_IMMEDIATEPWRSWITCH; +#elif defined(EMU_PWRCTRL_REGPWRSEL_DVDD) EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; #endif @@ -2015,7 +2339,7 @@ __STATIC_INLINE uint32_t vmonMilliVoltToFineThreshold(int mV, uint32_t coarseThr * @param[in] vmonInit * VMON initialization struct ******************************************************************************/ -void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit) +void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit) { uint32_t thresholdCoarse, thresholdFine; EFM_ASSERT((vmonInit->threshold >= 1200) && (vmonInit->threshold <= 3980)); @@ -2073,7 +2397,7 @@ void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit) * @param[in] vmonInit * VMON Hysteresis initialization struct ******************************************************************************/ -void EMU_VmonHystInit(EMU_VmonHystInit_TypeDef *vmonInit) +void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit) { uint32_t riseThresholdCoarse, riseThresholdFine, fallThresholdCoarse, fallThresholdFine; /* VMON supports voltages between 1200 mV and 3980 mV (inclusive) in 20 mV increments */ @@ -2181,20 +2505,20 @@ bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel) } #endif /* EMU_STATUS_VMONRDY */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) -/** +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) +/***************************************************************************//** * @brief * Adjust the bias refresh rate * * @details * This function is only meant to be used under high-temperature operation on - * the first generation EFR32, Pearl and Jade. Adjusting the bias mode will + * EFR32xG1 and EFM32xG1 devices. Adjusting the bias mode will * increase the typical current consumption. See application note 1027 * and errata documents for further details. * * @param [in] mode * The new bias refresh rate - */ + ******************************************************************************/ void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode) { #define EMU_TESTLOCK (*(volatile uint32_t *) (EMU_BASE + 0x190)) @@ -2202,37 +2526,37 @@ void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode) #define EMU_BIASTESTCTRL (*(volatile uint32_t *) (EMU_BASE + 0x19C)) #define CMU_ULFRCOCTRL (*(volatile uint32_t *) (CMU_BASE + 0x03C)) - uint32_t freq = 0x2; + uint32_t freq = 0x2u; bool emuTestLocked = false; if (mode == emuBiasMode_1KHz) { - freq = 0x0; + freq = 0x0u; } - if (EMU_TESTLOCK == 0x1) + if (EMU_TESTLOCK == 0x1u) { emuTestLocked = true; - EMU_TESTLOCK = 0xADE8; + EMU_TESTLOCK = 0xADE8u; } if (mode == emuBiasMode_Continuous) { - EMU_BIASCONF &= ~0x74; + EMU_BIASCONF &= ~0x74u; } else { - EMU_BIASCONF |= 0x74; + EMU_BIASCONF |= 0x74u; } - EMU_BIASTESTCTRL |= 0x8; - CMU_ULFRCOCTRL = (CMU_ULFRCOCTRL & ~0xC00) - | ((freq & 0x3) << 10); - EMU_BIASTESTCTRL &= ~0x8; + EMU_BIASTESTCTRL |= 0x8u; + CMU_ULFRCOCTRL = (CMU_ULFRCOCTRL & ~0xC00u) + | ((freq & 0x3u) << 10u); + EMU_BIASTESTCTRL &= ~0x8u; if (emuTestLocked) { - EMU_TESTLOCK = 0; + EMU_TESTLOCK = 0u; } } #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpcrc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpcrc.c index 3914e87adf..bee3af2ea8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpcrc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpcrc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c index 599cfe414e..15011e06f8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c @@ -2,7 +2,7 @@ * @file em_gpio.c * @brief General Purpose IO (GPIO) peripheral API * devices. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -148,10 +148,10 @@ void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, * by this function. * * @note - * On platform 1 devices the pin number parameter is not used. The + * On series 0 devices the pin number parameter is not used. The * pin number used on these devices is hardwired to the interrupt with the * same number. @n - * On platform 2 devices, pin number can be selected freely within a group. + * On series 1 devices, pin number can be selected freely within a group. * Interrupt numbers are divided into 4 groups (intNo / 4) and valid pin * number within the interrupt groups are: * 0: pins 0-3 @@ -185,7 +185,7 @@ void GPIO_ExtIntConfig(GPIO_Port_TypeDef port, bool fallingEdge, bool enable) { - uint32_t tmp; + uint32_t tmp = 0; #if !defined(_GPIO_EXTIPINSELL_MASK) (void)pin; #endif @@ -291,12 +291,12 @@ void GPIO_PinModeSet(GPIO_Port_TypeDef port, * register controls pins 0-7 and MODEH controls pins 8-15. */ if (pin < 8) { - GPIO->P[port].MODEL = (GPIO->P[port].MODEL & ~(0xF << (pin * 4))) + GPIO->P[port].MODEL = (GPIO->P[port].MODEL & ~(0xFu << (pin * 4))) | (mode << (pin * 4)); } else { - GPIO->P[port].MODEH = (GPIO->P[port].MODEH & ~(0xF << ((pin - 8) * 4))) + GPIO->P[port].MODEH = (GPIO->P[port].MODEH & ~(0xFu << ((pin - 8) * 4))) | (mode << ((pin - 8) * 4)); } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c index d28873105a..287e031511 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_i2c.c * @brief Inter-integrated Circuit (I2C) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -77,9 +77,9 @@ #define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST) /* Max I2C transmission rate constant */ -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) #define I2C_CR_MAX 4 -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) #define I2C_CR_MAX 8 #else #warning "Max I2C transmission rate constant is not defined" @@ -257,21 +257,21 @@ void I2C_BusFreqSet(I2C_TypeDef *i2c, switch(i2cMode) { case i2cClockHLRStandard: -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) minFreq = 4200000; break; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) minFreq = 2000000; break; #endif case i2cClockHLRAsymetric: -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) minFreq = 11000000; break; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) minFreq = 5000000; break; #endif case i2cClockHLRFast: -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) minFreq = 24400000; break; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) minFreq = 14000000; break; #endif } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c index 1dfc2b6d5b..7d6428eac9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_idac.c * @brief Current Digital to Analog Converter (IDAC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -48,7 +48,8 @@ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /* Fix for errata IDAC_E101 - IDAC output current degradation */ -#if defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY) +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY)) #define ERRATA_FIX_IDAC_E101_EN #endif /** @endcond */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_int.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_int.c index ed84185d64..32ef970104 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_int.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_int.c @@ -1,7 +1,7 @@ /**************************************************************************//** * @file em_int.c * @brief Interrupt enable/disable unit API - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c index 99833a8d36..5a8b05893b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_lcd.c * @brief Liquid Crystal Display (LCD) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ldma.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ldma.c index 9a1718016e..1a2f8a1f15 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ldma.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ldma.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_ldma.c * @brief Direct memory access (LDMA) module peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c index 88e7d65c21..aee2ec7597 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_lesense.c * @brief Low Energy Sensor (LESENSE) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -31,9 +31,8 @@ ******************************************************************************/ #include "em_lesense.h" -/* LESENSE is currently only supported on Platform 1. Full support for Platform 2 LESENSE - will be included in the next release. */ -#if defined(LESENSE_COUNT) && (LESENSE_COUNT > 0) && defined(_SILICON_LABS_32B_PLATFORM_1) + +#if defined(LESENSE_COUNT) && (LESENSE_COUNT > 0) #include "em_assert.h" #include "em_bus.h" #include "em_cmu.h" @@ -60,6 +59,22 @@ * @{ ******************************************************************************/ +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined(_LESENSE_ROUTE_MASK) +#define GENERIC_LESENSE_ROUTE LESENSE->ROUTE +#else +#define GENERIC_LESENSE_ROUTE LESENSE->ROUTEPEN +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) +/* DACOUT mode only available on channel 0,1,2,3,12,13,14,15 */ +#define DACOUT_SUPPORT 0xF00F +#else +/* DACOUT mode only available on channel 4,5,7,10,12,13 */ +#define DACOUT_SUPPORT 0x34B0 +#endif +/** @endcond */ + /******************************************************************************* ************************** LOCAL FUNCTIONS ******************************** ******************************************************************************/ @@ -100,11 +115,13 @@ * Request to call @ref LESENSE_Reset() first in order to initialize all * LESENSE registers with the default value. ******************************************************************************/ -void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset) +void LESENSE_Init(const LESENSE_Init_TypeDef * init, bool reqReset) { /* Sanity check of initialization values */ EFM_ASSERT((uint32_t)init->timeCtrl.startDelay < 4U); +#if defined(_LESENSE_PERCTRL_DACPRESC_MASK) EFM_ASSERT((uint32_t)init->perCtrl.dacPresc < 32U); +#endif /* Reset LESENSE registers if requested. */ if (reqReset) @@ -114,6 +131,11 @@ void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset) /* Set sensor start delay for each channel. */ LESENSE_StartDelaySet((uint32_t)init->timeCtrl.startDelay); +#if defined(_LESENSE_TIMCTRL_AUXSTARTUP_MASK) + /* Configure the AUXHRFCO startup delay. */ + LESENSE->TIMCTRL = (LESENSE->TIMCTRL & (~_LESENSE_TIMCTRL_AUXSTARTUP_MASK)) + | (init->timeCtrl.delayAuxStartup << _LESENSE_TIMCTRL_AUXSTARTUP_SHIFT); +#endif /* LESENSE core control configuration. * Set PRS source, SCANCONF register usage strategy, interrupt and @@ -127,8 +149,10 @@ void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset) | (uint32_t)init->coreCtrl.scanConfSel | (uint32_t)init->coreCtrl.bufTrigLevel | (uint32_t)init->coreCtrl.wakeupOnDMA +#if defined(_LESENSE_CTRL_ACMP0INV_MASK) | ((uint32_t)init->coreCtrl.invACMP0 << _LESENSE_CTRL_ACMP0INV_SHIFT) | ((uint32_t)init->coreCtrl.invACMP1 << _LESENSE_CTRL_ACMP1INV_SHIFT) +#endif | ((uint32_t)init->coreCtrl.dualSample << _LESENSE_CTRL_DUALSAMPLE_SHIFT) | ((uint32_t)init->coreCtrl.storeScanRes << _LESENSE_CTRL_STRSCANRES_SHIFT) | ((uint32_t)init->coreCtrl.bufOverWr << _LESENSE_CTRL_BUFOW_SHIFT) @@ -144,15 +168,24 @@ void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset) * duty cycle (warm up) mode. */ LESENSE->PERCTRL = ((uint32_t)init->perCtrl.dacCh0Data << _LESENSE_PERCTRL_DACCH0DATA_SHIFT) + | ((uint32_t)init->perCtrl.dacCh1Data << _LESENSE_PERCTRL_DACCH1DATA_SHIFT) +#if defined(_LESENSE_PERCTRL_DACCH0CONV_MASK) | ((uint32_t)init->perCtrl.dacCh0ConvMode << _LESENSE_PERCTRL_DACCH0CONV_SHIFT) | ((uint32_t)init->perCtrl.dacCh0OutMode << _LESENSE_PERCTRL_DACCH0OUT_SHIFT) - | ((uint32_t)init->perCtrl.dacCh1Data << _LESENSE_PERCTRL_DACCH1DATA_SHIFT) | ((uint32_t)init->perCtrl.dacCh1ConvMode << _LESENSE_PERCTRL_DACCH1CONV_SHIFT) | ((uint32_t)init->perCtrl.dacCh1OutMode << _LESENSE_PERCTRL_DACCH1OUT_SHIFT) | ((uint32_t)init->perCtrl.dacPresc << _LESENSE_PERCTRL_DACPRESC_SHIFT) | (uint32_t)init->perCtrl.dacRef +#endif | ((uint32_t)init->perCtrl.acmp0Mode << _LESENSE_PERCTRL_ACMP0MODE_SHIFT) | ((uint32_t)init->perCtrl.acmp1Mode << _LESENSE_PERCTRL_ACMP1MODE_SHIFT) +#if defined(_LESENSE_PERCTRL_ACMP0INV_MASK) + | ((uint32_t)init->coreCtrl.invACMP0 << _LESENSE_PERCTRL_ACMP0INV_SHIFT) + | ((uint32_t)init->coreCtrl.invACMP1 << _LESENSE_PERCTRL_ACMP1INV_SHIFT) +#endif +#if defined(_LESENSE_PERCTRL_DACCONVTRIG_MASK) + | ((uint32_t)init->perCtrl.dacScan << _LESENSE_PERCTRL_DACCONVTRIG_SHIFT) +#endif | (uint32_t)init->perCtrl.warmupMode; /* LESENSE decoder general control configuration. @@ -211,7 +244,7 @@ void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset) * Frequency in Hz calculated and set by this function. Users can use this to * compare the requested and set values. ******************************************************************************/ -uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t const scanFreq) +uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t scanFreq) { uint32_t tmp; uint32_t pcPresc = 0UL; /* Period counter prescaler. */ @@ -293,8 +326,8 @@ uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t const scanFreq) * @param[in] start * If true, LESENSE_ScanStart() is immediately issued after configuration. ******************************************************************************/ -void LESENSE_ScanModeSet(LESENSE_ScanMode_TypeDef const scanMode, - bool const start) +void LESENSE_ScanModeSet(LESENSE_ScanMode_TypeDef scanMode, + bool start) { uint32_t tmp; /* temporary storage of the CTRL register value */ @@ -335,7 +368,7 @@ void LESENSE_ScanModeSet(LESENSE_ScanMode_TypeDef const scanMode, * @param[in] startDelay * Number of LFACLK cycles to delay. Valid range: 0-3 (2 bit). ******************************************************************************/ -void LESENSE_StartDelaySet(uint8_t const startDelay) +void LESENSE_StartDelaySet(uint8_t startDelay) { uint32_t tmp; /* temporary storage of the TIMCTRL register value */ @@ -378,8 +411,8 @@ void LESENSE_StartDelaySet(uint8_t const startDelay) * @param[in] clkDiv * Clock divisor value. Valid range depends on the @p clk value. ******************************************************************************/ -void LESENSE_ClkDivSet(LESENSE_ChClk_TypeDef const clk, - LESENSE_ClkPresc_TypeDef const clkDiv) +void LESENSE_ClkDivSet(LESENSE_ChClk_TypeDef clk, + LESENSE_ClkPresc_TypeDef clkDiv) { uint32_t tmp; @@ -440,12 +473,12 @@ void LESENSE_ClkDivSet(LESENSE_ChClk_TypeDef const clk, * @param[in] confChAll * Configuration structure for all (16) LESENSE sensor channels. ******************************************************************************/ -void LESENSE_ChannelAllConfig(LESENSE_ChAll_TypeDef const *confChAll) +void LESENSE_ChannelAllConfig(const LESENSE_ChAll_TypeDef * confChAll) { uint32_t i; /* Iterate through all the 16 channels */ - for (i = 0U; i < 16U; ++i) + for (i = 0U; i < LESENSE_NUM_CHANNELS; ++i) { /* Configure scan channels. */ LESENSE_ChannelConfig(&confChAll->Ch[i], i); @@ -475,26 +508,31 @@ void LESENSE_ChannelAllConfig(LESENSE_ChAll_TypeDef const *confChAll) * @param[in] chIdx * Channel index to configure (0-15). ******************************************************************************/ -void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, - uint32_t const chIdx) +void LESENSE_ChannelConfig(const LESENSE_ChDesc_TypeDef * confCh, + uint32_t chIdx) { uint32_t tmp; /* Service variable. */ /* Sanity check of configuration parameters */ - EFM_ASSERT(chIdx < 16U); - EFM_ASSERT(confCh->exTime < 64U); - EFM_ASSERT(confCh->sampleDelay < 128U); - EFM_ASSERT(confCh->measDelay < 128U); + EFM_ASSERT(chIdx < LESENSE_NUM_CHANNELS); + EFM_ASSERT(confCh->exTime <= (_LESENSE_CH_TIMING_EXTIME_MASK >> _LESENSE_CH_TIMING_EXTIME_SHIFT)); + EFM_ASSERT(confCh->measDelay <= (_LESENSE_CH_TIMING_MEASUREDLY_MASK >> _LESENSE_CH_TIMING_MEASUREDLY_SHIFT)); +#if defined(_SILICON_LABS_32B_SERIES_0) + // Sample delay on other devices are 8 bits which fits perfectly in uint8_t + EFM_ASSERT(confCh->sampleDelay <= (_LESENSE_CH_TIMING_SAMPLEDLY_MASK >> _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT)); +#endif + /* Not a complete assert, as the max. value of acmpThres depends on other * configuration parameters, check the parameter description of acmpThres for * for more details! */ EFM_ASSERT(confCh->acmpThres < 4096U); - EFM_ASSERT(!(confCh->chPinExMode == lesenseChPinExDACOut - && (chIdx != 2U) - && (chIdx != 3U) - && (chIdx != 4U) - && (chIdx != 5U))); + if (confCh->chPinExMode == lesenseChPinExDACOut) + { + EFM_ASSERT((0x1 << chIdx) & DACOUT_SUPPORT); + } + +#if defined(_LESENSE_IDLECONF_CH0_DACCH0) EFM_ASSERT(!(confCh->chPinIdleMode == lesenseChPinIdleDACCh1 && ((chIdx != 12U) && (chIdx != 13U) @@ -505,6 +543,7 @@ void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, && (chIdx != 1U) && (chIdx != 2U) && (chIdx != 3U)))); +#endif /* Configure chIdx setup in LESENSE idle phase. * Read-modify-write in order to support reconfiguration during LESENSE @@ -516,9 +555,9 @@ void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, /* Channel specific timing configuration on scan channel chIdx. * Set excitation time, sampling delay, measurement delay. */ LESENSE_ChannelTimingSet(chIdx, - (uint32_t)confCh->exTime, - (uint32_t)confCh->sampleDelay, - (uint32_t)confCh->measDelay); + confCh->exTime, + confCh->sampleDelay, + confCh->measDelay); /* Channel specific configuration of clocks, sample mode, excitation pin mode * alternate excitation usage and interrupt mode on scan channel chIdx in @@ -538,22 +577,26 @@ void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, (uint32_t)confCh->compMode | ((uint32_t)confCh->shiftRes << _LESENSE_CH_EVAL_DECODE_SHIFT) | ((uint32_t)confCh->storeCntRes << _LESENSE_CH_EVAL_STRSAMPLE_SHIFT) - | ((uint32_t)confCh->invRes << _LESENSE_CH_EVAL_SCANRESINV_SHIFT); + | ((uint32_t)confCh->invRes << _LESENSE_CH_EVAL_SCANRESINV_SHIFT) +#if defined(_LESENSE_CH_EVAL_MODE_MASK) + | ((uint32_t)confCh->evalMode << _LESENSE_CH_EVAL_MODE_SHIFT) +#endif + ; /* Configure analog comparator (ACMP) threshold and decision threshold for * counter separately with the function provided for that. */ LESENSE_ChannelThresSet(chIdx, - (uint32_t)confCh->acmpThres, - (uint32_t)confCh->cntThres); + confCh->acmpThres, + confCh->cntThres); /* Enable/disable interrupts on channel */ - BUS_RegBitWrite(&(LESENSE->IEN), chIdx, confCh->enaInt); + BUS_RegBitWrite(&LESENSE->IEN, chIdx, confCh->enaInt); /* Enable/disable CHchIdx pin. */ - BUS_RegBitWrite(&(LESENSE->ROUTE), chIdx, confCh->enaPin); + BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, chIdx, confCh->enaPin); /* Enable/disable scan channel chIdx. */ - BUS_RegBitWrite(&(LESENSE->CHEN), chIdx, confCh->enaScanCh); + BUS_RegBitWrite(&LESENSE->CHEN, chIdx, confCh->enaScanCh); } @@ -574,7 +617,7 @@ void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, * @param[in] confAltEx * Configuration structure for LESENSE alternate excitation pins. ******************************************************************************/ -void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx) +void LESENSE_AltExConfig(const LESENSE_ConfAltEx_TypeDef * confAltEx) { uint32_t i; uint32_t tmp; @@ -583,7 +626,7 @@ void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx) /* Configure alternate excitation mapping. * Atomic read-modify-write using BUS_RegBitWrite function in order to * support reconfiguration during LESENSE operation. */ - BUS_RegBitWrite(&(LESENSE->CTRL), + BUS_RegBitWrite(&LESENSE->CTRL, _LESENSE_CTRL_ALTEXMAP_SHIFT, confAltEx->altExMap); @@ -596,7 +639,7 @@ void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx) /* Enable/disable alternate excitation pin i. * Atomic read-modify-write using BUS_RegBitWrite function in order to * support reconfiguration during LESENSE operation. */ - BUS_RegBitWrite(&(LESENSE->ROUTE), + BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, (16UL + i), confAltEx->AltEx[i].enablePin); @@ -608,20 +651,24 @@ void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx) LESENSE->ALTEXCONF = tmp; /* Enable/disable always excite on channel i */ - BUS_RegBitWrite(&(LESENSE->ALTEXCONF), + BUS_RegBitWrite(&LESENSE->ALTEXCONF, (16UL + i), confAltEx->AltEx[i].alwaysEx); } break; +#if defined(_LESENSE_CTRL_ALTEXMAP_ACMP) case lesenseAltExMapACMP: +#else + case lesenseAltExMapCH: +#endif /* Iterate through all the 16 alternate excitation channels */ for (i = 0U; i < 16U; ++i) { /* Enable/disable alternate ACMP excitation channel pin i. */ /* Atomic read-modify-write using BUS_RegBitWrite function in order to * support reconfiguration during LESENSE operation. */ - BUS_RegBitWrite(&(LESENSE->ROUTE), + BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, i, confAltEx->AltEx[i].enablePin); } @@ -658,18 +705,18 @@ void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx) * @param[in] enaPin * Enable/disable the pin assigned to the channel selected by @p chIdx. ******************************************************************************/ -void LESENSE_ChannelEnable(uint8_t const chIdx, - bool const enaScanCh, - bool const enaPin) +void LESENSE_ChannelEnable(uint8_t chIdx, + bool enaScanCh, + bool enaPin) { /* Enable/disable the assigned pin of scan channel chIdx. * Note: BUS_RegBitWrite() function is used for setting/clearing single * bit peripheral register bitfields. Read the function description in * em_bus.h for more details. */ - BUS_RegBitWrite(&(LESENSE->ROUTE), chIdx, enaPin); + BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, chIdx, enaPin); /* Enable/disable scan channel chIdx. */ - BUS_RegBitWrite(&(LESENSE->CHEN), chIdx, enaScanCh); + BUS_RegBitWrite(&LESENSE->CHEN, chIdx, enaScanCh); } @@ -700,7 +747,7 @@ void LESENSE_ChannelEnableMask(uint16_t chMask, uint16_t pinMask) /* Enable/disable all channels at once according to the mask. */ LESENSE->CHEN = chMask; /* Enable/disable all channel pins at once according to the mask. */ - LESENSE->ROUTE = pinMask; + GENERIC_LESENSE_ROUTE = pinMask; } @@ -732,15 +779,18 @@ void LESENSE_ChannelEnableMask(uint16_t chMask, uint16_t pinMask) * Measure delay on chIdx. Sensor measuring is delayed for measDelay+1 * excitation clock cycles. Valid range: 0-127 (7 bits). ******************************************************************************/ -void LESENSE_ChannelTimingSet(uint8_t const chIdx, - uint8_t const exTime, - uint8_t const sampleDelay, - uint8_t const measDelay) +void LESENSE_ChannelTimingSet(uint8_t chIdx, + uint8_t exTime, + uint8_t sampleDelay, + uint16_t measDelay) { /* Sanity check of parameters. */ - EFM_ASSERT(exTime < 64U); - EFM_ASSERT(sampleDelay < 128U); - EFM_ASSERT(measDelay < 128U); + EFM_ASSERT(exTime <= (_LESENSE_CH_TIMING_EXTIME_MASK >> _LESENSE_CH_TIMING_EXTIME_SHIFT)); + EFM_ASSERT(measDelay <= (_LESENSE_CH_TIMING_MEASUREDLY_MASK >> _LESENSE_CH_TIMING_MEASUREDLY_SHIFT)); +#if defined(_SILICON_LABS_32B_SERIES_0) + // Sample delay on other devices are 8 bits which fits perfectly in uint8_t + EFM_ASSERT(sampleDelay <= (_LESENSE_CH_TIMING_SAMPLEDLY_MASK >> _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT)); +#endif /* Channel specific timing configuration on scan channel chIdx. * Setting excitation time, sampling delay, measurement delay. */ @@ -784,9 +834,9 @@ void LESENSE_ChannelTimingSet(uint8_t const chIdx, * Decision threshold for counter comparison. * Valid range: 0-65535 (16 bits). ******************************************************************************/ -void LESENSE_ChannelThresSet(uint8_t const chIdx, - uint16_t const acmpThres, - uint16_t const cntThres) +void LESENSE_ChannelThresSet(uint8_t chIdx, + uint16_t acmpThres, + uint16_t cntThres) { uint32_t tmp; /* temporary storage */ @@ -794,13 +844,13 @@ void LESENSE_ChannelThresSet(uint8_t const chIdx, /* Sanity check for acmpThres only, cntThres is 16bit value. */ EFM_ASSERT(acmpThres < 4096U); /* Sanity check for LESENSE channel id. */ - EFM_ASSERT(chIdx < 16); + EFM_ASSERT(chIdx < LESENSE_NUM_CHANNELS); /* Save the INTERACT register value of channel chIdx to tmp. * Please be aware the effects of the non-atomic Read-Modify-Write cycle! */ - tmp = LESENSE->CH[chIdx].INTERACT & ~(_LESENSE_CH_INTERACT_ACMPTHRES_MASK); + tmp = LESENSE->CH[chIdx].INTERACT & ~(0xFFF); /* Set the ACMP threshold value to the INTERACT register of channel chIdx. */ - tmp |= (uint32_t)acmpThres << _LESENSE_CH_INTERACT_ACMPTHRES_SHIFT; + tmp |= (uint32_t)acmpThres; /* Write the new value to the INTERACT register. */ LESENSE->CH[chIdx].INTERACT = tmp; @@ -813,6 +863,122 @@ void LESENSE_ChannelThresSet(uint8_t const chIdx, LESENSE->CH[chIdx].EVAL = tmp; } +#if defined(_LESENSE_CH_EVAL_MODE_MASK) +/***************************************************************************//** + * @brief + * Configure Sliding Window evaluation mode for a specific channel + * + * @details + * This function will configure the evaluation mode, the initial + * sensor measurement (COMPTHRES) and the window size. For other channel + * related configuration see the @ref LESENSE_ChannelConfig() function. + * + * @warning + * Beware that the step size and window size configuration are global to all + * LESENSE channels and use the same register field in the hardware. This + * means that any windowSize configuration passed to this function will + * apply for all channels and override all other stepSize/windowSize + * configurations. + * + * @param[in] chIdx + * Identifier of the scan channel. Valid range: 0-15. + * + * @param[in] windowSize + * Window size to be used on all channels. + * + * @param[in] initValue + * The initial sensor value for the channel. + ******************************************************************************/ +void LESENSE_ChannelSlidingWindow(uint8_t chIdx, + uint32_t windowSize, + uint32_t initValue) +{ + LESENSE_CH_TypeDef * ch = &LESENSE->CH[chIdx]; + + LESENSE_WindowSizeSet(windowSize); + ch->EVAL = (ch->EVAL & ~(_LESENSE_CH_EVAL_COMPTHRES_MASK | _LESENSE_CH_EVAL_MODE_MASK)) + | (initValue << _LESENSE_CH_EVAL_COMPTHRES_SHIFT) + | LESENSE_CH_EVAL_MODE_SLIDINGWIN; +} + +/***************************************************************************//** + * @brief + * Configure step detection evaluation mode for a specific channel + * + * @details + * This function will configure the evaluation mode, the initial + * sensor measurement (COMPTHRES) and the window size. For other channel + * related configuration see the @ref LESENSE_ChannelConfig() function. + * + * @warning + * Beware that the step size and window size configuration are global to all + * LESENSE channels and use the same register field in the hardware. This + * means that any stepSize configuration passed to this function will + * apply for all channels and override all other stepSize/windowSize + * configurations. + * + * @param[in] chIdx + * Identifier of the scan channel. Valid range: 0-15. + * + * @param[in] stepSize + * Step size to be used on all channels. + * + * @param[in] initValue + * The initial sensor value for the channel. + ******************************************************************************/ +void LESENSE_ChannelStepDetection(uint8_t chIdx, + uint32_t stepSize, + uint32_t initValue) +{ + LESENSE_CH_TypeDef * ch = &LESENSE->CH[chIdx]; + + LESENSE_StepSizeSet(stepSize); + ch->EVAL = (ch->EVAL & ~(_LESENSE_CH_EVAL_COMPTHRES_MASK | _LESENSE_CH_EVAL_MODE_MASK)) + | (initValue << _LESENSE_CH_EVAL_COMPTHRES_SHIFT) + | LESENSE_CH_EVAL_MODE_STEPDET; +} + +/***************************************************************************//** + * @brief + * Set the window size for all LESENSE channels. + * + * @details + * The window size is used by all channels that are configured as + * @ref lesenseEvalModeSlidingWindow. + * + * @warning + * The window size configuration is using the same register field as the + * step detection size. So the window size configuration will have an + * effect on channels configured with the @ref lesenseEvalModeStepDetection + * evaluation mode as well. + * + * @param[in] windowSize + * The window size to use for all channels. + ******************************************************************************/ +void LESENSE_WindowSizeSet(uint32_t windowSize) +{ + LESENSE->EVALCTRL = (LESENSE->EVALCTRL & ~_LESENSE_EVALCTRL_WINSIZE_MASK) + | windowSize; +} + +/***************************************************************************//** + * @brief + * Set the step size for all LESENSE channels. + * + * @details + * The step size is configured using the same register field as use to + * configure window size. So calling this function will overwrite any + * previously configured window size as done by the + * @ref LESENSE_WindowSizeSet() function. + * + * @param[in] stepSize + * The step size to use for all channels. + ******************************************************************************/ +void LESENSE_StepSizeSet(uint32_t stepSize) +{ + LESENSE_WindowSizeSet(stepSize); +} +#endif /***************************************************************************//** * @brief @@ -828,14 +994,14 @@ void LESENSE_ChannelThresSet(uint8_t const chIdx, * LESENSE_DecoderStateConfig() function. * * @param[in] confDecStAll - * Configuration structure for all (16) LESENSE decoder states. + * Configuration structure for all (16 or 32) LESENSE decoder states. ******************************************************************************/ -void LESENSE_DecoderStateAllConfig(LESENSE_DecStAll_TypeDef const *confDecStAll) +void LESENSE_DecoderStateAllConfig(const LESENSE_DecStAll_TypeDef * confDecStAll) { uint32_t i; - /* Iterate through all the 16 decoder states. */ - for (i = 0U; i < 16U; ++i) + /* Iterate through all the 16 or 32 decoder states. */ + for (i = 0U; i < LESENSE_NUM_DECODER_STATES; ++i) { /* Configure decoder state i. */ LESENSE_DecoderStateConfig(&confDecStAll->St[i], i); @@ -856,19 +1022,19 @@ void LESENSE_DecoderStateAllConfig(LESENSE_DecStAll_TypeDef const *confDecStAll) * Configuration structure for a single LESENSE decoder state. * * @param[in] decSt - * Decoder state index to configure (0-15). + * Decoder state index to configure (0-15) or (0-31) depending on device. ******************************************************************************/ -void LESENSE_DecoderStateConfig(LESENSE_DecStDesc_TypeDef const *confDecSt, - uint32_t const decSt) +void LESENSE_DecoderStateConfig(const LESENSE_DecStDesc_TypeDef * confDecSt, + uint32_t decSt) { /* Sanity check of configuration parameters */ - EFM_ASSERT(decSt < 16U); + EFM_ASSERT(decSt < LESENSE_NUM_DECODER_STATES); EFM_ASSERT((uint32_t)confDecSt->confA.compMask < 16U); EFM_ASSERT((uint32_t)confDecSt->confA.compVal < 16U); - EFM_ASSERT((uint32_t)confDecSt->confA.nextState < 16U); + EFM_ASSERT((uint32_t)confDecSt->confA.nextState < LESENSE_NUM_DECODER_STATES); EFM_ASSERT((uint32_t)confDecSt->confB.compMask < 16U); EFM_ASSERT((uint32_t)confDecSt->confB.compVal < 16U); - EFM_ASSERT((uint32_t)confDecSt->confB.nextState < 16U); + EFM_ASSERT((uint32_t)confDecSt->confB.nextState < LESENSE_NUM_DECODER_STATES); /* Configure state descriptor A (LESENSE_STi_TCONFA) for decoder state i. * Setting sensor compare value, sensor mask, next state index, @@ -907,11 +1073,12 @@ void LESENSE_DecoderStateConfig(LESENSE_DecStDesc_TypeDef const *confDecSt, * enabling the decoder! * * @param[in] decSt - * Decoder state to set as current state. Valid range: 0-15 + * Decoder state to set as current state. Valid range: 0-15 or 0-31 + * depending on device. ******************************************************************************/ void LESENSE_DecoderStateSet(uint32_t decSt) { - EFM_ASSERT(decSt < 16U); + EFM_ASSERT(decSt <= _LESENSE_DECSTATE_DECSTATE_MASK); LESENSE->DECSTATE = decSt & _LESENSE_DECSTATE_DECSTATE_MASK; } @@ -930,6 +1097,28 @@ uint32_t LESENSE_DecoderStateGet(void) return LESENSE->DECSTATE & _LESENSE_DECSTATE_DECSTATE_MASK; } +#if defined(_LESENSE_PRSCTRL_MASK) +/***************************************************************************//** + * @brief + * Enable or disable PRS output from the LESENSE decoder. + * + * @param[in] enable + * enable/disable the PRS output from the LESENSE decoder. true to enable and + * false to disable. + * + * @param[in] decMask + * Decoder state compare value mask + * + * @param[in] decVal + * Decoder state compare value. + ******************************************************************************/ +void LESENSE_DecoderPrsOut(bool enable, uint32_t decMask, uint32_t decVal) +{ + LESENSE->PRSCTRL = (enable << _LESENSE_PRSCTRL_DECCMPEN_SHIFT) + | (decMask << _LESENSE_PRSCTRL_DECCMPMASK_SHIFT) + | (decVal << _LESENSE_PRSCTRL_DECCMPVAL_SHIFT); +} +#endif /***************************************************************************//** * @brief @@ -1092,15 +1281,23 @@ void LESENSE_Reset(void) LESENSE->PERCTRL = _LESENSE_PERCTRL_RESETVALUE; LESENSE->DECCTRL = _LESENSE_DECCTRL_RESETVALUE; LESENSE->BIASCTRL = _LESENSE_BIASCTRL_RESETVALUE; +#if defined(_LESENSE_EVALCTRL_MASK) + LESENSE->EVALCTRL = _LESENSE_EVALCTRL_RESETVALUE; + LESENSE->PRSCTRL = _LESENSE_PRSCTRL_RESETVALUE; +#endif LESENSE->CHEN = _LESENSE_CHEN_RESETVALUE; LESENSE->IDLECONF = _LESENSE_IDLECONF_RESETVALUE; LESENSE->ALTEXCONF = _LESENSE_ALTEXCONF_RESETVALUE; /* Disable LESENSE to control GPIO pins */ - LESENSE->ROUTE = _LESENSE_ROUTE_RESETVALUE; +#if defined(_LESENSE_ROUTE_MASK) + LESENSE->ROUTE = _LESENSE_ROUTE_RESETVALUE; +#else + LESENSE->ROUTEPEN = _LESENSE_ROUTEPEN_RESETVALUE; +#endif /* Reset all channel configuration registers */ - for (i = 0U; i < 16U; ++i) + for (i = 0U; i < LESENSE_NUM_CHANNELS; ++i) { LESENSE->CH[i].TIMING = _LESENSE_CH_TIMING_RESETVALUE; LESENSE->CH[i].INTERACT = _LESENSE_CH_INTERACT_RESETVALUE; @@ -1108,7 +1305,7 @@ void LESENSE_Reset(void) } /* Reset all decoder state configuration registers */ - for (i = 0U; i < 16U; ++i) + for (i = 0U; i < LESENSE_NUM_DECODER_STATES; ++i) { LESENSE->ST[i].TCONFA = _LESENSE_ST_TCONFA_RESETVALUE; LESENSE->ST[i].TCONFB = _LESENSE_ST_TCONFB_RESETVALUE; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c index 666aa4a19b..7281084139 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_letimer.c * @brief Low Energy Timer (LETIMER) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c index 30e6e68565..b96dee3060 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c @@ -2,7 +2,7 @@ * @file em_leuart.c * @brief Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) * Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c index acaad77aae..066de51082 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_mpu.c * @brief Memory Protection Unit (MPU) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c index 30c14dc971..6bc3975f04 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_msc.c * @brief Flash controller (MSC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -57,8 +57,8 @@ #define WORDS_PER_DATA_PHASE (1) #endif +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) /* Fix for errata FLASH_E201 - Potential program failure after Power On */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) #define ERRATA_FIX_FLASH_E201_EN #endif @@ -159,6 +159,13 @@ void MSC_Init(void) #if defined( _MSC_TIMEBASE_MASK ) uint32_t freq, cycles; #endif + +#if defined( _EMU_STATUS_VSCALE_MASK ) + /* VSCALE must be done and flash erase and write requires VSCALE2 */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif + /* Unlock the MSC */ MSC->LOCK = MSC_UNLOCK_CODE; /* Disable writing to the flash */ @@ -382,7 +389,7 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, { uint32_t timeOut; uint32_t wordIndex; - uint32_t wordsPerDataPhase; + bool useWDouble = false; MSC_Status_TypeDef retval = mscReturnOk; #if !defined( _EFM32_GECKO_FAMILY ) uint32_t irqState; @@ -392,6 +399,7 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, /* If LPWRITE (Low Power Write) is NOT enabled, set WDOUBLE (Write Double word) */ if (!(MSC->WRITECTRL & MSC_WRITECTRL_LPWRITE)) { +#if defined(_SILICON_LABS_32B_SERIES_0) /* If the number of words to be written are odd, we need to align by writing a single word first, before setting the WDOUBLE bit. */ if (numWords & 0x1) @@ -431,14 +439,11 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, } /* Now we can set the double word option in order to write two words per data phase. */ +#endif MSC->WRITECTRL |= MSC_WRITECTRL_WDOUBLE; - wordsPerDataPhase = 2; + useWDouble = true; } - else #endif /* defined( _MSC_WRITECTRL_LPWRITE_MASK ) && defined( _MSC_WRITECTRL_WDOUBLE_MASK ) */ - { - wordsPerDataPhase = 1; - } /* Write the rest as double word write if wordsPerDataPhase == 2 */ if (numWords > 0) @@ -451,34 +456,34 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, wordIndex = 0; while(wordIndex < numWords) { - MSC->WDATA = *data++; - wordIndex++; - if (wordsPerDataPhase == 1) + if (!useWDouble) { - MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; - } - else if (wordsPerDataPhase == 2) - { - while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)); MSC->WDATA = *data++; wordIndex++; - - /* Trigger double write. Platform 1 and 2 - have different trigger behavior for - double word write as described in the - reference manual for MSC_WRITECMD_WRITEONCE - and WRITETRIG. */ -#if defined(_SILICON_LABS_32B_PLATFORM_1) MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; -#else + } + + else // useWDouble == true + { + /* Trigger double write according to flash properties. */ +#if defined(_SILICON_LABS_32B_SERIES_0) + MSC->WDATA = *data++; + while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)); + MSC->WDATA = *data++; + wordIndex += 2; + MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; + +#elif (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) + while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)); + do + { + MSC->WDATA = *data++; + wordIndex++; + } while ((MSC->STATUS & MSC_STATUS_WDATAREADY) + && (wordIndex < numWords)); MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; #endif } - else - { - /* Not supported. */ - EFM_ASSERT(false); - } /* Wait for the transaction to finish. */ timeOut = MSC_PROGRAM_TIMEOUT; @@ -539,14 +544,37 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; } } - MSC->WDATA = *data; - if ((wordsPerDataPhase == 1) - || ((wordsPerDataPhase == 2) && (wordIndex & 0x1))) + + if (!useWDouble) { + MSC->WDATA = *data; MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; + data++; + wordIndex++; + } + + else // useWDouble == true + { + /* Trigger double write according to flash properties. */ +#if defined(_SILICON_LABS_32B_SERIES_0) + MSC->WDATA = *data; + if (wordIndex & 0x1) + { + MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; + } + data++; + wordIndex++; + +#elif (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) + do + { + MSC->WDATA = *data++; + wordIndex++; + } while ((MSC->STATUS & MSC_STATUS_WDATAREADY) + && (wordIndex < numWords)); + MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; +#endif } - data++; - wordIndex++; } if (irqState == 0) @@ -587,8 +615,8 @@ MSC_RAMFUNC_DEFINITION_END * Write address * @param[in] data * Pointer to the first data word to load. - * @param[in] numWords - * Number of data words (32-bit) to load. + * @param[in] numBytes + * Number of data bytes to load, must be a multiple of 4 bytes. * @param[in] writeStrategy * Write strategy to apply. * @return @@ -612,6 +640,12 @@ MSC_Status_TypeDef MSC_WriteWordI(uint32_t *address, /* Check number of bytes. Must be divisable by four */ EFM_ASSERT((numBytes & 0x3) == 0); +#if defined( _EMU_STATUS_VSCALE_MASK ) + /* VSCALE must be done and flash write requires VSCALE2 */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif + /* Enable writing to the MSC */ MSC->WRITECTRL |= MSC_WRITECTRL_WREN; @@ -717,6 +751,11 @@ MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) /* Address must be aligned to pages */ EFM_ASSERT((((uint32_t) startAddress) & (FLASH_PAGE_SIZE - 1)) == 0); +#if defined( _EMU_STATUS_VSCALE_MASK ) + /* VSCALE must be done and flash erase requires VSCALE2 */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif /* Enable writing to the MSC */ MSC->WRITECTRL |= MSC_WRITECTRL_WREN; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c index 6963ab69f1..a342cd7bbd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c @@ -1,7 +1,7 @@ /**************************************************************************//** * @file em_opamp.c * @brief Operational Amplifier (OPAMP) peripheral API - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -31,7 +31,8 @@ ******************************************************************************/ #include "em_opamp.h" -#if defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1) +#if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \ + || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0))) #include "em_system.h" #include "em_assert.h" @@ -50,8 +51,13 @@ * @li OPAMP_Enable() Configure and enable an opamp. * @li OPAMP_Disable() Disable an opamp. * + * @if DOXYDOC_P1_DEVICE * All OPAMP functions assume that the DAC clock is running. If the DAC is not * used, the clock can be turned off when the opamp's are configured. + * @elseif DOXYDOC_P2_DEVICE + * All OPAMP functions assume that the VDAC clock is running. If the VDAC is not + * used, the clock can be turned off when the opamp's are configured. + * @endif * * If the available gain values dont suit the application at hand, the resistor * ladders can be disabled and external gain programming resistors used. @@ -64,8 +70,12 @@ * pads should be connected to a suitable signal ground. * * \nUnity gain voltage follower.\n + * @if DOXYDOC_P1_DEVICE * Use predefined macros @ref OPA_INIT_UNITY_GAIN and * @ref OPA_INIT_UNITY_GAIN_OPA2. + * @elseif DOXYDOC_P2_DEVICE + * Use predefined macro @ref OPA_INIT_UNITY_GAIN. + * @endif * @verbatim |\ @@ -78,8 +88,12 @@ @endverbatim * * \nNon-inverting amplifier.\n + * @if DOXYDOC_P1_DEVICE * Use predefined macros @ref OPA_INIT_NON_INVERTING and * @ref OPA_INIT_NON_INVERTING_OPA2. + * @elseif DOXYDOC_P2_DEVICE + * Use predefined macro @ref OPA_INIT_NON_INVERTING. + * @endif * @verbatim |\ @@ -95,8 +109,12 @@ NEGPAD @endverbatim * * \nInverting amplifier.\n + * @if DOXYDOC_P1_DEVICE * Use predefined macros @ref OPA_INIT_INVERTING and * @ref OPA_INIT_INVERTING_OPA2. + * @elseif DOXYDOC_P2_DEVICE + * Use predefined macro @ref OPA_INIT_INVERTING. + * @endif * @verbatim _____R2____ @@ -185,6 +203,36 @@ |___________| @endverbatim * + * @if DOXYDOC_P2_DEVICE + * \nInstrumentation amplifier.\n + * Use predefined macros @ref OPA_INIT_INSTR_AMP_OPA0 and + * @ref OPA_INIT_INSTR_AMP_OPA0. + * @verbatim + + |\ + __________|+\ OPA1 + | \______________ + ___|_ / | + | | / | + | |/ R2 + |____________| + | + R1 + | + R1 + ____________| + | | + | R2 + | |\ | + |___|+\ OPA0 | + | \_____|________ + __________|_ / + | / + |/ + + @endverbatim + * @endif + * * @{ ******************************************************************************/ @@ -196,14 +244,27 @@ * @brief * Disable an Operational Amplifier. * + * @if DOXYDOC_P1_DEVICE * @param[in] dac * Pointer to DAC peripheral register block. + * @elseif DOXYDOC_P2_DEVICE + * @param[in] dac + * Pointer to VDAC peripheral register block. + * @endif + * * * @param[in] opa * Selects an OPA, valid vaules are @ref OPA0, @ref OPA1 and @ref OPA2. ******************************************************************************/ -void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa) +void OPAMP_Disable( +#if defined(_SILICON_LABS_32B_SERIES_0) + DAC_TypeDef *dac, +#elif defined(_SILICON_LABS_32B_SERIES_1) + VDAC_TypeDef *dac, +#endif + OPAMP_TypeDef opa) { +#if defined(_SILICON_LABS_32B_SERIES_0) EFM_ASSERT(DAC_REF_VALID(dac)); EFM_ASSERT(DAC_OPA_VALID(opa)); @@ -221,6 +282,33 @@ void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa) { dac->OPACTRL &= ~DAC_OPACTRL_OPA2EN; } + +#elif defined(_SILICON_LABS_32B_SERIES_1) + EFM_ASSERT(VDAC_REF_VALID(dac)); + EFM_ASSERT(VDAC_OPA_VALID(opa)); + + if (opa == OPA0) + { + dac->CMD |= VDAC_CMD_OPA0DIS; + while (dac->STATUS & VDAC_STATUS_OPA0ENS) + { + } + } + else if (opa == OPA1) + { + dac->CMD |= VDAC_CMD_OPA1DIS; + while (dac->STATUS & VDAC_STATUS_OPA1ENS) + { + } + } + else /* OPA2 */ + { + dac->CMD |= VDAC_CMD_OPA2DIS; + while (dac->STATUS & VDAC_STATUS_OPA2ENS) + { + } + } +#endif } @@ -228,6 +316,7 @@ void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa) * @brief * Configure and enable an Operational Amplifier. * + * @if DOXYDOC_P1_DEVICE * @note * The value of the alternate output enable bit mask in the OPAMP_Init_TypeDef * structure should consist of one or more of the @@ -256,6 +345,23 @@ void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa) * * @param[in] dac * Pointer to DAC peripheral register block. + * @elseif DOXYDOC_P2_DEVICE + * @note + * The value of the alternate output enable bit mask in the OPAMP_Init_TypeDef + * structure should consist of one or more of the + * VDAC_OPA_OUT_ALTOUTPADEN_OUT[output#] flags + * (defined in \_vdac.h) OR'ed together. @n @n + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT0 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT1 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT2 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT3 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT4 + * + * E.g: @n + * init.outPen = VDAC_OPA_OUT_ALTOUTPADEN_OUT0 | VDAC_OPA_OUT_ALTOUTPADEN_OUT4; + * @param[in] dac + * Pointer to VDAC peripheral register block. + * @endif * * @param[in] opa * Selects an OPA, valid vaules are @ref OPA0, @ref OPA1 and @ref OPA2. @@ -263,8 +369,16 @@ void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa) * @param[in] init * Pointer to a structure containing OPAMP init information. ******************************************************************************/ -void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init) +void OPAMP_Enable( +#if defined(_SILICON_LABS_32B_SERIES_0) + DAC_TypeDef *dac, +#elif defined(_SILICON_LABS_32B_SERIES_1) + VDAC_TypeDef *dac, +#endif + OPAMP_TypeDef opa, + const OPAMP_Init_TypeDef *init) { +#if defined(_SILICON_LABS_32B_SERIES_0) uint32_t offset; EFM_ASSERT(DAC_REF_VALID(dac)); @@ -421,9 +535,172 @@ void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef | (init->hcmDisable ? DAC_OPACTRL_OPA2HCMDIS : 0) | DAC_OPACTRL_OPA2EN; } + +#elif defined(_SILICON_LABS_32B_SERIES_1) + uint32_t calData = 0; + uint32_t warmupTime; + + EFM_ASSERT(VDAC_REF_VALID(dac)); + EFM_ASSERT(VDAC_OPA_VALID(opa)); + EFM_ASSERT(init->settleTime <= (_VDAC_OPA_TIMER_SETTLETIME_MASK + >> _VDAC_OPA_TIMER_SETTLETIME_SHIFT)); + EFM_ASSERT(init->startupDly <= (_VDAC_OPA_TIMER_STARTUPDLY_MASK + >> _VDAC_OPA_TIMER_STARTUPDLY_SHIFT)); + EFM_ASSERT((init->outPen & ~_VDAC_OPA_OUT_ALTOUTPADEN_MASK) == 0); + EFM_ASSERT(!((init->gain3xEn == true) + && ((init->negSel == opaNegSelResTap) + || (init->posSel == opaPosSelResTap)))); + EFM_ASSERT((init->drvStr == opaDrvStrLowerAccLowStr) + || (init->drvStr == opaDrvStrLowAccLowStr) + || (init->drvStr == opaDrvStrHighAccHighStr) + || (init->drvStr == opaDrvStrHigherAccHighStr)); + + /* Disable OPAMP before writing to registers. */ + OPAMP_Disable(dac, opa); + + /* Get the calibration value based on OPAMP, Drive Strength, and INCBW. */ + switch (opa) + { + case OPA0: + switch (init->drvStr) + { + case opaDrvStrLowerAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL0 : DEVINFO->OPA0CAL4); + break; + case opaDrvStrLowAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL1 : DEVINFO->OPA0CAL5); + break; + case opaDrvStrHighAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL2 : DEVINFO->OPA0CAL6); + break; + case opaDrvStrHigherAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL3 : DEVINFO->OPA0CAL7); + break; + } + break; + + case OPA1: + switch (init->drvStr) + { + case opaDrvStrLowerAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL0 : DEVINFO->OPA1CAL4); + break; + case opaDrvStrLowAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL1 : DEVINFO->OPA1CAL5); + break; + case opaDrvStrHighAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL2 : DEVINFO->OPA1CAL6); + break; + case opaDrvStrHigherAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL3 : DEVINFO->OPA1CAL7); + break; + } + break; + + case OPA2: + switch (init->drvStr) + { + case opaDrvStrLowerAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL0 : DEVINFO->OPA2CAL4); + break; + case opaDrvStrLowAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL1 : DEVINFO->OPA2CAL5); + break; + case opaDrvStrHighAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL2 : DEVINFO->OPA2CAL6); + break; + case opaDrvStrHigherAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL3 : DEVINFO->OPA2CAL7); + break; + } + break; + } + if (!init->defaultOffsetN) + { + EFM_ASSERT(init->offsetN <= (_VDAC_OPA_CAL_OFFSETN_MASK + >> _VDAC_OPA_CAL_OFFSETN_SHIFT)); + calData = (calData & ~_VDAC_OPA_CAL_OFFSETN_MASK) + | (init->offsetN << _VDAC_OPA_CAL_OFFSETN_SHIFT); + } + if (!init->defaultOffsetP) + { + EFM_ASSERT(init->offsetP <= (_VDAC_OPA_CAL_OFFSETP_MASK + >> _VDAC_OPA_CAL_OFFSETP_SHIFT)); + calData = (calData & ~_VDAC_OPA_CAL_OFFSETP_MASK) + | (init->offsetP << _VDAC_OPA_CAL_OFFSETP_SHIFT); + } + + dac->OPA[opa].CAL = (calData & _VDAC_OPA_CAL_MASK); + + dac->OPA[opa].MUX = (uint32_t)init->resSel + | (init->gain3xEn ? VDAC_OPA_MUX_GAIN3X : 0) + | (uint32_t)init->resInMux + | (uint32_t)init->negSel + | (uint32_t)init->posSel; + + dac->OPA[opa].OUT = (uint32_t)init->outMode + | (uint32_t)init->outPen; + + switch (init->drvStr) + { + case opaDrvStrHigherAccHighStr: + warmupTime = 6; + break; + + case opaDrvStrHighAccHighStr: + warmupTime = 8; + break; + + case opaDrvStrLowAccLowStr: + warmupTime = 85; + break; + + case opaDrvStrLowerAccLowStr: + default: + warmupTime = 100; + break; + } + + dac->OPA[opa].TIMER = (uint32_t)(init->settleTime + << _VDAC_OPA_TIMER_SETTLETIME_SHIFT) + | (uint32_t)(warmupTime + << _VDAC_OPA_TIMER_WARMUPTIME_SHIFT) + | (uint32_t)(init->startupDly + << _VDAC_OPA_TIMER_STARTUPDLY_SHIFT); + + dac->OPA[opa].CTRL = (init->aportYMasterDisable + ? VDAC_OPA_CTRL_APORTYMASTERDIS : 0) + | (init->aportXMasterDisable + ? VDAC_OPA_CTRL_APORTXMASTERDIS : 0) + | (uint32_t)init->prsOutSel + | (uint32_t)init->prsSel + | (uint32_t)init->prsMode + | (init->prsEn ? VDAC_OPA_CTRL_PRSEN : 0) + | (init->halfDrvStr + ? VDAC_OPA_CTRL_OUTSCALE_HALF + : VDAC_OPA_CTRL_OUTSCALE_FULL) + | (init->hcmDisable ? VDAC_OPA_CTRL_HCMDIS : 0) + | (init->ugBwScale ? VDAC_OPA_CTRL_INCBW : 0) + | (uint32_t)init->drvStr; + + if (opa == OPA0) + { + dac->CMD |= VDAC_CMD_OPA0EN; + } + else if (opa == OPA1) + { + dac->CMD |= VDAC_CMD_OPA1EN; + } + else /* OPA2 */ + { + dac->CMD |= VDAC_CMD_OPA2EN; + } + +#endif } /** @} (end addtogroup OPAMP) */ /** @} (end addtogroup emlib) */ -#endif /* defined( OPAMP_PRESENT ) && ( OPAMP_COUNT == 1 ) */ +#endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1) + || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c index 44035ebf14..a71999b7d1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_pcnt.c * @brief Pulse Counter (PCNT) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c index 3b1813423a..244d07c1d6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_prs.c * @brief Peripheral Reflex System (PRS) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c index 9f467e7214..a8cd720863 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c @@ -2,7 +2,7 @@ * @file em_rmu.c * @brief Reset Management Unit (RMU) peripheral module peripheral API * - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -111,7 +111,7 @@ #define RMU_RSTCAUSE_BUMODERST_XMASK 0x00000001UL /** 0000000000000001 < Backup mode reset */ #define NUM_RSTCAUSES 16 -/* EFM32XG1X */ +/* EFM32xG1, EFM32xG12, EFM32xG13 */ #elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00010F1DUL) #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ #define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */ @@ -128,8 +128,8 @@ #error "RMU_RSTCAUSE XMASKs are not defined for this family." #endif +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) /* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) #define ERRATA_FIX_EMU_E208_EN #endif @@ -303,7 +303,7 @@ uint32_t RMU_ResetCauseGet(void) for (i = 0; i < NUM_RSTCAUSES; i++) { zeroXMask = resetCauseMasks[i].resetCauseZeroXMask; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /* Handle soft/hard pin reset */ if (!(LB_CLW0 & LB_CLW0_PINRESETSOFT)) { diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c index c5ee6e79b7..0356bf2964 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_rtc.c * @brief Real Time Counter (RTC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtcc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtcc.c index 76e91979b2..3b5d3a1012 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtcc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtcc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file * @brief Real Time Counter with Calendar (RTCC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c index dcedb24629..cac903b062 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_system.c * @brief System Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -33,7 +33,6 @@ #include "em_system.h" #include "em_assert.h" #include -#include "core_cmSecureAccess.h" /***************************************************************************//** * @addtogroup emlib @@ -62,24 +61,19 @@ void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev) EFM_ASSERT(rev); - uint32_t pid0 = SECURE_READ(&(ROMTABLE->PID0)); - uint32_t pid1 = SECURE_READ(&(ROMTABLE->PID1)); - uint32_t pid2 = SECURE_READ(&(ROMTABLE->PID2)); - uint32_t pid3 = SECURE_READ(&(ROMTABLE->PID3)); - /* CHIP FAMILY bit [5:2] */ - tmp = (((pid1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2); + tmp = (((ROMTABLE->PID1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2); /* CHIP FAMILY bit [1:0] */ - tmp |= ((pid0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT); + tmp |= ((ROMTABLE->PID0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT); rev->family = tmp; /* CHIP MAJOR bit [3:0] */ - rev->major = (pid0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT; + rev->major = (ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT; /* CHIP MINOR bit [7:4] */ - tmp = (((pid2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); + tmp = (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); /* CHIP MINOR bit [3:0] */ - tmp |= ((pid3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); + tmp |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); rev->minor = tmp; } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c index 1182d7310b..5c21e8d4e9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_timer.c * @brief Timer/counter (TIMER) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c index 1e9bb63262..134519ca9c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c @@ -2,7 +2,7 @@ * @file em_usart.c * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) * Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -110,14 +110,18 @@ #define USART_IRDA_VALID(ref) (0) #endif -#if defined(_EZR32_HAPPY_FAMILY) -#define USART_I2S_VALID(ref) ((ref) == USART0) -#elif defined(_EFM32_HAPPY_FAMILY) -#define USART_I2S_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) -#elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) || defined(_SILICON_LABS_32B_PLATFORM_2) -#define USART_I2S_VALID(ref) ((ref) == USART1) -#elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) -#define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) +#if defined(_SILICON_LABS_32B_SERIES_1) + #define USART_I2S_VALID(ref) ((ref) == USART1) +#elif defined(_SILICON_LABS_32B_SERIES_0) + #if defined(_EZR32_HAPPY_FAMILY) + #define USART_I2S_VALID(ref) ((ref) == USART0) + #elif defined(_EFM32_HAPPY_FAMILY) + #define USART_I2S_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) + #elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) + #define USART_I2S_VALID(ref) ((ref) == USART1) + #elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) + #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) +#endif #endif #if (UART_COUNT == 1) @@ -475,11 +479,7 @@ uint32_t USART_BaudrateGet(USART_TypeDef *usart) ******************************************************************************/ void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baudrate) { -#if defined(_USART_CLKDIV_DIV_MASK) && (_USART_CLKDIV_DIV_MASK >= 0x7FFFF8UL) - uint64_t clkdiv; -#else uint32_t clkdiv; -#endif /* Inhibit divide by 0 */ EFM_ASSERT(baudrate); @@ -496,28 +496,8 @@ void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baud refFreq = CMU_ClockFreqGet(cmuClock_HFPER); } -#if defined(_USART_CLKDIV_DIV_MASK) && (_USART_CLKDIV_DIV_MASK >= 0x7FFFF8UL) - /* Calculate CLKDIV with fractional bits */ - clkdiv = (128ULL*refFreq)/baudrate - 256; - - /* - * Make sure we dont use fractional bits, do normal integer rounding when - * discarding fractional bits. - */ - clkdiv = ((clkdiv + 128)/256) << 8; -#else - /* Calculate and set CLKDIV with fractional bits */ - clkdiv = 2 * refFreq; - clkdiv += baudrate - 1; - clkdiv /= baudrate; - clkdiv -= 4; - clkdiv *= 64; - /* Make sure we don't use fractional bits by rounding CLKDIV */ - /* up (and thus reducing baudrate, not increasing baudrate above */ - /* specified value). */ - clkdiv += 0xc0; - clkdiv &= 0xffffff00; -#endif + clkdiv = (refFreq - 1) / (2 * baudrate); + clkdiv = clkdiv << 8; /* Verify that resulting clock divider is within limits */ EFM_ASSERT(!(clkdiv & ~_USART_CLKDIV_DIV_MASK)); diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c index 6198550c36..03cf953c66 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_vcmp.c * @brief Voltage Comparator (VCMP) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vdac.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vdac.c new file mode 100644 index 0000000000..634a6513d2 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vdac.c @@ -0,0 +1,437 @@ +/***************************************************************************//** + * @file em_vdac.c + * @brief Digital to Analog Converter (VDAC) Peripheral API + * @version 5.1.2 + ******************************************************************************* + * @section License + * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************* + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + +#include "em_vdac.h" +#if defined(VDAC_COUNT) && (VDAC_COUNT > 0) +#include "em_cmu.h" + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup VDAC + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of VDAC channel for assert statements. */ +#define VDAC_CH_VALID(ch) ((ch) <= 1) + +/** Max VDAC clock */ +#define VDAC_MAX_CLOCK 1000000 + +/** Max clock frequency of internal clock oscillator, 10 MHz + 20%. */ +#define VDAC_INTERNAL_CLOCK_FREQ 12000000 + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Enable/disable VDAC channel. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] ch + * Channel to enable/disable. + * + * @param[in] enable + * true to enable VDAC channel, false to disable. + ******************************************************************************/ +void VDAC_Enable(VDAC_TypeDef *vdac, unsigned int ch, bool enable) +{ + EFM_ASSERT(VDAC_REF_VALID(vdac)); + EFM_ASSERT(VDAC_CH_VALID(ch)); + + if (ch == 0) + { + if (enable) + { + vdac->CMD = VDAC_CMD_CH0EN; + } + else + { + vdac->CMD = VDAC_CMD_CH0DIS; + while (vdac->STATUS & VDAC_STATUS_CH0ENS); + } + } + else + { + if (enable) + { + vdac->CMD = VDAC_CMD_CH1EN; + } + else + { + vdac->CMD = VDAC_CMD_CH1DIS; + while (vdac->STATUS & VDAC_STATUS_CH1ENS); + } + } +} + +/***************************************************************************//** + * @brief + * Initialize VDAC. + * + * @details + * Initializes common parts for both channels. This function will also load + * calibration values from the Device Information (DI) page into the VDAC + * calibration register. + * To complete a VDAC setup, channel control configuration must also be done, + * please refer to VDAC_InitChannel(). + * + * @note + * This function will disable both channels prior to configuration. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] init + * Pointer to VDAC initialization structure. + ******************************************************************************/ +void VDAC_Init(VDAC_TypeDef *vdac, const VDAC_Init_TypeDef *init) +{ + uint32_t cal, tmp = 0; + uint32_t const volatile *calData; + + EFM_ASSERT(VDAC_REF_VALID(vdac)); + + /* Make sure both channels are disabled. */ + vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; + while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)); + + /* Get OFFSETTRIM calibration value. */ + cal = ((DEVINFO->VDAC0CH1CAL & _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK) + >> _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT) + << _VDAC_CAL_OFFSETTRIM_SHIFT; + + if (init->mainCalibration) + { + calData = &DEVINFO->VDAC0MAINCAL; + } + else + { + calData = &DEVINFO->VDAC0ALTCAL; + } + + /* Get correct GAINERRTRIM calibration value. */ + switch (init->reference) + { + case vdacRef1V25Ln: + tmp = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT; + break; + + case vdacRef2V5Ln: + tmp = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT; + break; + + case vdacRef1V25: + tmp = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT; + break; + + case vdacRef2V5: + tmp = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT; + break; + + case vdacRefAvdd: + case vdacRefExtPin: + tmp = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT; + break; + } + + /* Set GAINERRTRIM calibration value. */ + cal |= tmp << _VDAC_CAL_GAINERRTRIM_SHIFT; + + /* Get GAINERRTRIMCH1 calibration value. */ + switch (init->reference) + { + case vdacRef1V25Ln: + case vdacRef1V25: + case vdacRefAvdd: + case vdacRefExtPin: + tmp = (DEVINFO->VDAC0CH1CAL && _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK) + >> _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT; + break; + + case vdacRef2V5Ln: + case vdacRef2V5: + tmp = (DEVINFO->VDAC0CH1CAL && _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK) + >> _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT; + break; + } + + /* Set GAINERRTRIM calibration value. */ + cal |= tmp << _VDAC_CAL_GAINERRTRIMCH1_SHIFT; + + tmp = ((uint32_t)init->asyncClockMode << _VDAC_CTRL_DACCLKMODE_SHIFT) + | ((uint32_t)init->warmupKeepOn << _VDAC_CTRL_WARMUPMODE_SHIFT) + | ((uint32_t)init->refresh << _VDAC_CTRL_REFRESHPERIOD_SHIFT) + | (((uint32_t)init->prescaler << _VDAC_CTRL_PRESC_SHIFT) + & _VDAC_CTRL_PRESC_MASK) + | ((uint32_t)init->reference << _VDAC_CTRL_REFSEL_SHIFT) + | ((uint32_t)init->ch0ResetPre << _VDAC_CTRL_CH0PRESCRST_SHIFT) + | ((uint32_t)init->outEnablePRS << _VDAC_CTRL_OUTENPRS_SHIFT) + | ((uint32_t)init->sineEnable << _VDAC_CTRL_SINEMODE_SHIFT) + | ((uint32_t)init->diff << _VDAC_CTRL_DIFF_SHIFT); + + /* Write to VDAC registers. */ + vdac->CAL = cal; + vdac->CTRL = tmp; +} + +/***************************************************************************//** + * @brief + * Initialize a VDAC channel. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] init + * Pointer to VDAC channel initialization structure. + * + * @param[in] ch + * Channel number to initialize. + ******************************************************************************/ +void VDAC_InitChannel(VDAC_TypeDef *vdac, + const VDAC_InitChannel_TypeDef *init, + unsigned int ch) +{ + uint32_t vdacChCtrl, vdacStatus; + + EFM_ASSERT(VDAC_REF_VALID(vdac)); + EFM_ASSERT(VDAC_CH_VALID(ch)); + + /* Make sure both channels are disabled. */ + vdacStatus = vdac->STATUS; + vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; + while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)); + + vdacChCtrl = ((uint32_t)init->prsSel << _VDAC_CH0CTRL_PRSSEL_SHIFT) + | ((uint32_t)init->prsAsync << _VDAC_CH0CTRL_PRSASYNC_SHIFT) + | ((uint32_t)init->trigMode << _VDAC_CH0CTRL_TRIGMODE_SHIFT) + | ((uint32_t)init->sampleOffMode << _VDAC_CH0CTRL_CONVMODE_SHIFT); + + if (ch == 0) + { + vdac->CH0CTRL = vdacChCtrl; + } + else + { + vdac->CH1CTRL = vdacChCtrl; + } + + /* Check if the channel must be enabled. */ + if (init->enable) + { + if (ch == 0) + { + vdac->CMD = VDAC_CMD_CH0EN; + } + else + { + vdac->CMD = VDAC_CMD_CH1EN; + } + } + + /* Check if the other channel had to be turned off above + * and needs to be turned on again. */ + if (ch == 0) + { + if (vdacStatus & VDAC_STATUS_CH1ENS) + { + vdac->CMD = VDAC_CMD_CH1EN; + } + } + else + { + if (vdacStatus & VDAC_STATUS_CH0ENS) + { + vdac->CMD = VDAC_CMD_CH0EN; + } + } +} + +/***************************************************************************//** + * @brief + * Set the output signal of a VDAC channel to a given value. + * + * @details + * This function sets the output signal of a VDAC channel by writing @p value + * to the corresponding CHnDATA register. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] channel + * Channel number to set output of. + * + * @param[in] value + * Value to write to the channel output register CHnDATA. + ******************************************************************************/ +void VDAC_ChannelOutputSet(VDAC_TypeDef *vdac, + unsigned int channel, + uint32_t value) +{ + switch(channel) + { + case 0: + VDAC_Channel0OutputSet(vdac, value); + break; + case 1: + VDAC_Channel1OutputSet(vdac, value); + break; + default: + EFM_ASSERT(0); + break; + } +} + +/***************************************************************************//** + * @brief + * Calculate prescaler value used to determine VDAC clock. + * + * @details + * The VDAC clock is given by input clock divided by prescaler+1. + * + * VDAC_CLK = IN_CLK / (prescale + 1) + * + * Maximum VDAC clock is 1 MHz. Input clock is HFPERCLK when VDAC synchronous + * mode is selected, or an internal oscillator of 10 MHz +/- 20% when + * asynchronous mode is selected. + * + * @note + * If the requested VDAC frequency is low and the max prescaler value can not + * adjust the actual VDAC frequency lower than requested, the max prescaler + * value is returned, resulting in a higher VDAC frequency than requested. + * + * @param[in] vdacFreq VDAC frequency target. The frequency will automatically + * be adjusted to be below max allowed VDAC clock. + * + * @param[in] syncMode Set to true if you intend to use VDAC in synchronous + * mode. + * + * @param[in] hfperFreq Frequency in Hz of HFPERCLK oscillator. Set to 0 to + * use currently defined HFPERCLK clock setting. This parameter is only used + * when syncMode is set to true. + * + * @return + * Prescaler value to use for VDAC in order to achieve a clock value less than + * or equal to @p vdacFreq. + ******************************************************************************/ +uint32_t VDAC_PrescaleCalc(uint32_t vdacFreq, bool syncMode, uint32_t hfperFreq) +{ + uint32_t ret, refFreq; + + /* Make sure selected VDAC clock is below max value */ + if (vdacFreq > VDAC_MAX_CLOCK) + { + vdacFreq = VDAC_MAX_CLOCK; + } + + if (!syncMode) + { + refFreq = VDAC_INTERNAL_CLOCK_FREQ; + } + else + { + if (hfperFreq) + { + refFreq = hfperFreq; + } + else + { + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); + } + } + + /* Iterate in order to determine best prescale value. Start with lowest */ + /* prescaler value in order to get the first equal or less VDAC */ + /* frequency value. */ + for (ret = 0; ret <= _VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT; ret++) + { + if ((refFreq / (ret + 1)) <= vdacFreq) + { + break; + } + } + + /* If ret is higher than the max prescaler value, make sure to return + the max value. */ + if (ret > (_VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT)) + { + ret = _VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT; + } + + return ret; +} + +/***************************************************************************//** + * @brief + * Reset VDAC to same state as after a HW reset. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + ******************************************************************************/ +void VDAC_Reset(VDAC_TypeDef *vdac) +{ + /* Disable channels, before resetting other registers. */ + vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; + while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)); + vdac->CH0CTRL = _VDAC_CH0CTRL_RESETVALUE; + vdac->CH1CTRL = _VDAC_CH1CTRL_RESETVALUE; + vdac->CH0DATA = _VDAC_CH0DATA_RESETVALUE; + vdac->CH1DATA = _VDAC_CH1DATA_RESETVALUE; + vdac->CTRL = _VDAC_CTRL_RESETVALUE; + vdac->IEN = _VDAC_IEN_RESETVALUE; + vdac->IFC = _VDAC_IFC_MASK; + vdac->CAL = _VDAC_CAL_RESETVALUE; +} + +/** @} (end addtogroup VDAC) */ +/** @} (end addtogroup emlib) */ +#endif /* defined(VDAC_COUNT) && (VDAC_COUNT > 0) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c index 3e1024d35e..55a66e44d2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c @@ -2,7 +2,7 @@ * @file em_wdog.c * @brief Watchdog (WDOG) peripheral API * devices. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com