From 1a4c11e3b5e4a66e6fed9eecc7fbdd463857c7dd Mon Sep 17 00:00:00 2001 From: offirko Date: Wed, 20 Mar 2019 14:41:45 +0200 Subject: [PATCH] Fixed Bus Mode bit mask to select best mode. When setting Quad Enable, either SR1, SR2 or CR setup is required. Either way register size is up to 2 bytes. --- .../storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp b/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp index af29ad3c64..bf39ff2dda 100644 --- a/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp +++ b/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp @@ -854,7 +854,7 @@ int QSPIFBlockDevice::_sfdp_set_quad_enabled(uint8_t *basic_param_table_ptr) case 1: case 4: status_reg_setup[1] = 0x02; //Bit 1 of Status Reg 2 - sr_write_size = 2; + sr_write_size = 2; tr_debug("Setting QE Bit, Bit 1 of Status Reg 2"); break; @@ -875,7 +875,7 @@ int QSPIFBlockDevice::_sfdp_set_quad_enabled(uint8_t *basic_param_table_ptr) status_reg_setup[1] = 0x2; // Bit 1 of status Reg 2 _read_register_inst = 0x35; sr_read_size = 1; - sr_write_size = 2; + sr_write_size = 2; tr_debug("Setting QE Bit, Bit 1 of Status Reg 2 -special read command"); break; default: