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[RZ/A1H] commit for CMSIS changes 

- adds CA9 related headers
- adds start up routine (only ARMCC is supported)
- adds scatter file for RZ/A1H
- adds GIC driver
- adds peripheral definitions(iodefine) for RZ/A1H
- adds serial flash boot loader for RZ/A1H
pull/594/head
Takayuki Kurosawa 2014-10-24 11:01:05 +09:00
parent b1cb82c520
commit 193bdaa8c9
64 changed files with 27198 additions and 0 deletions
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1035
libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h Normal file
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261
libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.c Normal file
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/**************************************************************************//**
* @file RZ_A1_Init.c
* $Rev: 624 $
* $Date:: 2013-04-24 13:37:48 +0900#$
* @brief RZ_A1 Initialize
******************************************************************************/
/* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved */
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "MBRZA1H.h"
#include "RZ_A1_Init.h"
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
/******************************************************************************
Imported global variables and functions (from other files)
******************************************************************************/
/******************************************************************************
Exported global variables and functions (to be accessed by other files)
******************************************************************************/
/******************************************************************************
Private global variables and functions
******************************************************************************/
/**************************************************************************//**
* Function Name: RZ_A1_SetSramWriteEnable
* @brief Initialize Board settings
*
* Description:<br>
* Set SRAM write enable
* @param none
* @retval none
******************************************************************************/
void RZ_A1_SetSramWriteEnable(void)
{
/* Enable SRAM write access */
CPG.SYSCR3 = 0x0F;
return;
}
/**************************************************************************//**
* Function Name: RZ_A1_InitClock
* @brief Initialize Board settings
*
* Description:<br>
* Initialize Clock
* @param none
* @retval none
******************************************************************************/
void RZ_A1_InitClock(void)
{
/* Cancel L2C standby status before clock change */
L2CREG15_POWER_CTRL = 0x00000001;
/* Clock settings */
/* ClockMode0 */
CPG.FRQCR = 0x1035; /* CPU Clock =399.99MHz */
CPG.FRQCR2 = 0x0001; /* G Clock =266.66MHz */
return;
}
/**************************************************************************//**
* Function Name: RZ_A1_IsClockMode0
* @brief Query Clock Mode
*
* Description:<br>
* Answer ClockMode0 or not
* @param none
* @retval true : clock mode 0
* @retval false : clock mode 1
******************************************************************************/
int RZ_A1_IsClockMode0(void)
{
/* ClockMode0 */
return true;
}
/**************************************************************************//**
* Function Name: RZ_A1_InitBus
* @brief Initialize Bus
*
* Description:<br>
* Initialize CS0-CS3 pin and access timing
* @param none
* @retval none
******************************************************************************/
void RZ_A1_InitBus(void)
{
/***********************************************************************/
/* Set pin alternative mode of NOR_FLASH(CS0, CS1) and SDRAM(CS2, CS3) */
/***********************************************************************/
/* PORT9 partly set to Alternative Mode 1
P9_1(A25), P9_0(A24)
*/
GPIO.PIBC9 &= ~(uint16_t)0x0003u;
GPIO.PBDC9 &= ~(uint16_t)0x0003u;
GPIO.PM9 |= (uint16_t)0x0003u;
GPIO.PMC9 &= ~(uint16_t)0x0003u;
GPIO.PIPC9 &= ~(uint16_t)0x0003u;
GPIO.PBDC9 &= ~(uint16_t)0x0003u;
GPIO.PFC9 &= ~(uint16_t)0x0003u;
GPIO.PFCE9 &= ~(uint16_t)0x0003u;
GPIO.PFCAE9 &= ~(uint16_t)0x0003u;
GPIO.PIPC9 |= (uint16_t)0x0003u;
GPIO.PMC9 |= (uint16_t)0x0003u;
/* PORT8 fully set to Alternative Mode 1
P8_15(A23), P8_14(A22), P8_13(A21), P8_12(A20),
P8_11(A19), P8_10(A18), P8_9(A17), P8_8(A16),
P8_7(A15), P8_6(A14), P8_5(A13), P8_4(A12),
P8_3(A11), P8_2(A10), P8_1(A9), P8_0(A8),
*/
GPIO.PIBC8 = 0x0000u;
GPIO.PBDC8 = 0x0000u;
GPIO.PM8 = 0xffffu;
GPIO.PMC8 = 0x0000u;
GPIO.PIPC8 = 0x0000u;
GPIO.PBDC8 = 0x0000u;
GPIO.PFC8 = 0x0000u;
GPIO.PFCE8 = 0x0000u;
GPIO.PFCAE8 = 0x0000u;
GPIO.PIPC8 = 0xffffu;
GPIO.PMC8 = 0xffffu;
/* PORT7 fully set to Alternative Mode 1
P7_15(A7), P7_14(A6), P7_13(A5), P7_12(A4),
P7_11(A3), P7_10(A2), P7_9(A1), P7_8(RD#),
P7_7(DQMLU#), P7_6(WE#0/DQMLL#), P7_5(RD/WR#), P7_4(CKE),
P7_3(CAS#), P7_2(RAS#), P7_1(CS3#), P7_0(CS0#)
*/
GPIO.PIBC7 = 0x0000u;
GPIO.PBDC7 = 0x0000u;
GPIO.PM7 = 0xffffu;
GPIO.PMC7 = 0x0000u;
GPIO.PIPC7 = 0x0000u;
GPIO.PBDC7 = 0x0000u;
GPIO.PFC7 = 0x0000u;
GPIO.PFCE7 = 0x0000u;
GPIO.PFCAE7 = 0x0000u;
GPIO.PIPC7 = 0xffffu;
GPIO.PMC7 = 0xffffu;
/* PORT6 fully set to Alternative Mode 1
P6_15(D15), P6_14(D14), P6_13(D13), P6_12(D12),
P6_11(D11), P6_10(D10), P6_9(D9), P6_8(D8),
P6_7(D7), P6_6(D6), P6_5(D5), P6_4(D4),
P6_3(D3), P6_2(D2), P6_1(D1), P6_0(D0)
Alternative Mode 1
*/
GPIO.PIBC6 = 0x0000u;
GPIO.PBDC6 = 0x0000u;
GPIO.PM6 = 0xffffu;
GPIO.PMC6 = 0x0000u;
GPIO.PIPC6 = 0x0000u;
GPIO.PBDC6 = 0xffffu;
GPIO.PFC6 = 0x0000u;
GPIO.PFCE6 = 0x0000u;
GPIO.PFCAE6 = 0x0000u;
GPIO.PIPC6 = 0xffffu;
GPIO.PMC6 = 0xffffu;
/* PORT5 partly set to Alternative Mode 6
P5_8(CS2#),
*/
GPIO.PIBC5 &= ~(uint16_t)0x0100u;
GPIO.PBDC5 &= ~(uint16_t)0x0100u;
GPIO.PM5 |= (uint16_t)0x0100u;
GPIO.PMC5 &= ~(uint16_t)0x0100u;
GPIO.PIPC5 &= ~(uint16_t)0x0100u;
GPIO.PBDC5 &= ~(uint16_t)0x0100u;
GPIO.PFC5 |= (uint16_t)0x0100u;
GPIO.PFCE5 &= ~(uint16_t)0x0100u;
GPIO.PFCAE5 |= (uint16_t)0x0100u;
GPIO.PIPC5 |= (uint16_t)0x0100u;
GPIO.PMC5 |= (uint16_t)0x0100u;
/* PORT3 partly set to Alternative Mode 7
P3_7(CS1#),
*/
GPIO.PIBC3 &= ~(uint16_t)0x0080u;
GPIO.PBDC3 &= ~(uint16_t)0x0080u;
GPIO.PM3 |= (uint16_t)0x0080u;
GPIO.PMC3 &= ~(uint16_t)0x0080u;
GPIO.PIPC3 &= ~(uint16_t)0x0080u;
GPIO.PBDC3 &= ~(uint16_t)0x0080u;
GPIO.PFC3 &= ~(uint16_t)0x0080u;
GPIO.PFCE3 |= (uint16_t)0x0080u;
GPIO.PFCAE3 |= (uint16_t)0x0080u;
GPIO.PIPC3 |= (uint16_t)0x0080u;
GPIO.PMC3 |= (uint16_t)0x0080u;
/***********************************************************************/
/* Set bus access timing of NOR_FLASH(CS0, CS1) and SDRAM(CS2, CS3) */
/***********************************************************************/
/* CSn Bus Control Register */
BSC.CS0BCR = 0x10000c00;/* IWW=001b(1cyc),TYPE=000b(Normal),BSZ=10b(16bit)*/
BSC.CS1BCR = 0x10000c00;/* IWW=001b(1cyc),TYPE=000b(Normal),BSZ=10b(16bit)*/
BSC.CS2BCR = 0x00004c00;/* TYPE=100b(SDRAM), BSZ=10b(16bit) */
BSC.CS3BCR = 0x00004c00;/* TYPE=100b(SDRAM), BSZ=10b(16bit) */
/* CS0 Wait Control Register(Normal type) */
/* BAS=0b SW=01b(1.5cyc) WR=0110b(6cyc) WM=1b(ignore) HW=00b(0.5cyc) */
BSC.CS0WCR = 0x00000b40;
/* CS1 Wait Control Register(Normal type) */
/* BAS=0b SW=01b(1.5cyc) WR=0110b(6cyc) WM=1b(ignore) HW=00b(0.5cyc) */
BSC.CS1WCR = 0x00000b40;
/* CS2,3 Wait Control Register(SDRAM type) */
BSC.CS2WCR = 0x00000480;/* A2CL=01b 2cycle */
BSC.CS3WCR = 0x00002492;/* WTRP=01b 1cycle, WTRCD=01b 1cycle, A3CL=01b 2cycle, TRWL=10b 2cycle, WTRC=10b 5cycle */
/* SDRAM Control Register */
BSC.SDCR = 0x00120812;
/* Refresh Timer Constant Register */
BSC.RTCOR = 0xa55a0020;
/* Refresh Timer Control Status Register */
BSC.RTCSR = 0xa55a0010;
/* Write SDRAM Mode Register */
CS2_SDRAM_MODE_16BIT_CAS2_BR_BW = 0x0000;
CS3_SDRAM_MODE_16BIT_CAS2_BR_BW = 0x0000;
return;
}
/******************************************************************************
End of file
******************************************************************************/

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libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.h Normal file
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/**************************************************************************//**
* @file RZ_A1_Init.h
* $Rev: 531 $
* $Date:: 2013-04-16 13:07:35 +0900#$
* @brief RZ_A1 Initialize
******************************************************************************/
/* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved */
#ifndef RZ_A1_INIT_H
#define RZ_A1_INIT_H
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include <stdio.h>
#include <stdbool.h>
#include "iodefine.h"
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/******************************************************************************
Variable Externs
******************************************************************************/
/******************************************************************************
Functions Prototypes
******************************************************************************/
void RZ_A1_SetSramWriteEnable(void);
void RZ_A1_InitClock(void);
int RZ_A1_IsClockMode0(void);
void RZ_A1_InitBus(void);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* RZ_A1_INIT_H */

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libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/MBRZA1H.sct Normal file
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LOAD_TTB 0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM
{
TTB +0 EMPTY 0x4000
{ } ; Level-1 Translation Table for MMU
}
SFLASH_BOOT 0x18000000 (0x8000)
{
BOOT_LOADER_BEGIN 0x18000000 FIXED
{
* ( BOOT_LOADER )
}
}
SFLASH 0x18008000 (0x08000000-0x8000)
{
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; S-Flash ROM : Executable cached region
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
VECTORS 0x18008000 FIXED
{
* (RESET, +FIRST) ; Vector table and other (assembler) startup code
* (InRoot$$Sections) ; All (library) code that must be in a root region
* (+RO-CODE) ; Application RO code (.text)
}
RO_DATA +0 ALIGN 0x00100000 FIXED
{ * (+RO-DATA) } ; Application RO data (.constdata)
RW_DATA 0x20600000 0x00100000 ; Page 1 of On-Chip Large-Capacity RAM (0x20060000 to 0x206FFFFF)
{ * (+RW) } ; Application RW data (.data)
ZI_DATA 0x20100000 0x00100000 ; Page 1 of On-Chip Large-Capacity RAM (0x20010000 to 0x201FFFFF)
{ * (+ZI) } ; Application ZI data (.bss)
RW_DATA_NC 0x60900000 0x00100000
{ * (NC_DATA) } ; Application RW data Non cached area
ZI_DATA_NC +0
{ * (NC_BSS) } ; Application ZI data Non cached area
;HEAP 0x90000000
;{ * (HEAP) }
}

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libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/startup_MBRZA1H.s Normal file
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;/*****************************************************************************
; * @file: startup_MBRZA1H.s
; * @purpose: CMSIS Cortex-A9 Core Device Startup File
; * for the NXP MBRZA1H Device Series
; * @version: V1.02, modified for mbed
; * @date: 27. July 2009, modified 3rd Aug 2009
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2009 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/
GICI_BASE EQU 0xe8202000
ICCIAR_OFFSET EQU 0x0000000C
ICCEOIR_OFFSET EQU 0x00000010
ICCHPIR_OFFSET EQU 0x00000018
GICD_BASE EQU 0xe8201000
ICDISER0_OFFSET EQU 0x00000100
ICDICER0_OFFSET EQU 0x00000180
ICDISPR0_OFFSET EQU 0x00000200
ICDABR0_OFFSET EQU 0x00000300
ICDIPR0_OFFSET EQU 0x00000400
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
T_Bit EQU 0x20 ; when T bit is set, core is in Thumb state
GIC_ERRATA_CHECK_1 EQU 0x000003FE
GIC_ERRATA_CHECK_2 EQU 0x000003FF
Sect_Normal EQU 0x00005c06 ;outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
Sect_Normal_Cod EQU 0x0000dc06 ;outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
Sect_Normal_RO EQU 0x0000dc16 ;as Sect_Normal_Cod, but not executable
Sect_Normal_RW EQU 0x00005c16 ;as Sect_Normal_Cod, but writeable and not executable
Sect_SO EQU 0x00000c12 ;strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
Sect_Device_RO EQU 0x00008c12 ;device, non-shareable, non-executable, ro, domain 0, base addr 0
Sect_Device_RW EQU 0x00000c12 ;as Sect_Device_RO, but writeable
Sect_Fault EQU 0x00000000 ;this translation will fault (the bottom 2 bits are important, the rest are ignored)
RAM_BASE EQU 0x80000000
VRAM_BASE EQU 0x18000000
SRAM_BASE EQU 0x2e000000
ETHERNET EQU 0x1a000000
CS3_PERIPHERAL_BASE EQU 0x1c000000
; <h> Stack Configuration
; <o> Stack Size (in Bytes, per mode) <0x0-0xFFFFFFFF:8>
; </h>
UND_Stack_Size EQU 0x00000100
SVC_Stack_Size EQU 0x00000100
ABT_Stack_Size EQU 0x00000100
FIQ_Stack_Size EQU 0x00000000
IRQ_Stack_Size EQU 0x00000100
USR_Stack_Size EQU 0x00000100
ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
FIQ_Stack_Size + IRQ_Stack_Size)
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE USR_Stack_Size
__initial_sp SPACE ISR_Stack_Size
Stack_Top
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00080000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
ARM
; Vector Table Mapped to Address 0 at Reset
AREA RESET, CODE, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors LDR PC, Reset_Addr ; Address of Reset Handler
LDR PC, Undef_Addr ; Address of Undef Handler
LDR PC, SVC_Addr ; Address of SVC Handler
LDR PC, PAbt_Addr ; Address of Prefetch Abort Handler
LDR PC, DAbt_Addr ; Address of Data Abort Handler
NOP ; Reserved Vector
LDR PC, IRQ_Addr ; Address of IRQ Handler
LDR PC, FIQ_Addr ; Address of FIQ Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
Reset_Addr DCD Reset_Handler
Undef_Addr DCD Undef_Handler
SVC_Addr DCD SVC_Handler
PAbt_Addr DCD PAbt_Handler
DAbt_Addr DCD DAbt_Handler
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
AREA |.text|, CODE, READONLY
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT InitMemorySubsystem
IMPORT __main
IMPORT RZ_A1_SetSramWriteEnable
; Put any cores other than 0 to sleep
MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR
ANDS R0, R0, #3
goToSleep
WFINE
BNE goToSleep
; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
; Enables Full Access i.e. in both privileged and non privileged modes
MRC p15, 0, r0, c1, c0, 2 ; Read Coprocessor Access Control Register (CPACR)
ORR r0, r0, #(0xF << 20) ; Enable access to CP 10 & 11
MCR p15, 0, r0, c1, c0, 2 ; Write Coprocessor Access Control Register (CPACR)
ISB
; Switch on the VFP and NEON hardware
MOV r0, #0x40000000
VMSR FPEXC, r0 ; Write FPEXC register, EN bit set
MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register
BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache
BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache
BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU
BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction
BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs
MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register
ISB
; Set Vector Base Address Register (VBAR) to point to this application's vector table
LDR R0, =__Vectors
MCR p15, 0, R0, c12, c0, 0
; Setup Stack for each exceptional mode
LDR R0, =Stack_Top
; Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_C, #Mode_UND:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
; Enter Abort Mode and set its Stack Pointer
MSR CPSR_C, #Mode_ABT:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
; Enter FIQ Mode and set its Stack Pointer
MSR CPSR_C, #Mode_FIQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
; Enter IRQ Mode and set its Stack Pointer
MSR CPSR_C, #Mode_IRQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
; Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_C, #Mode_SVC:OR:I_Bit:OR:F_Bit
MOV SP, R0
; Enter System Mode to complete initialization and enter kernel
MSR CPSR_C, #Mode_SYS:OR:I_Bit:OR:F_Bit
MOV SP, R0
ISB
LDR R0, =RZ_A1_SetSramWriteEnable
BLX R0
IMPORT create_translation_table
BL create_translation_table
; USR/SYS stack pointer will be set during kernel init
LDR R0, =SystemInit
BLX R0
LDR R0, =InitMemorySubsystem
BLX R0
LDR R0, =__main
BLX R0
ENDP
Undef_Handler\
PROC
EXPORT Undef_Handler [WEAK]
IMPORT CUndefHandler
SRSFD SP!, #Mode_UND
PUSH {R0-R4, R12} ; Save APCS corruptible registers to UND mode stack
MRS R0, SPSR
TST R0, #T_Bit ; Check mode
MOVEQ R1, #4 ; R1 = 4 ARM mode
MOVNE R1, #2 ; R1 = 2 Thumb mode
SUB R0, LR, R1
LDREQ R0, [R0] ; ARM mode - R0 points to offending instruction
BEQ undef_cont
;Thumb instruction
;Determine if it is a 32-bit Thumb instruction
LDRH R0, [R0]
MOV R2, #0x1c
CMP R2, R0, LSR #11
BHS undef_cont ;16-bit Thumb instruction
;32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction.
LDRH R2, [LR]
ORR R0, R2, R0, LSL #16
undef_cont
MOV R2, LR ; Set LR to third argument
; AND R12, SP, #4 ; Ensure stack is 8-byte aligned
MOV R3, SP ; Ensure stack is 8-byte aligned
AND R12, R3, #4
SUB SP, SP, R12 ; Adjust stack
PUSH {R12, LR} ; Store stack adjustment and dummy LR
;R0 Offending instruction
;R1 =2 (Thumb) or =4 (ARM)
BL CUndefHandler
POP {R12, LR} ; Get stack adjustment & discard dummy LR
ADD SP, SP, R12 ; Unadjust stack
LDR LR, [SP, #24] ; Restore stacked LR and possibly adjust for retry
SUB LR, LR, R0
LDR R0, [SP, #28] ; Restore stacked SPSR
MSR SPSR_CXSF, R0
POP {R0-R4, R12} ; Restore stacked APCS registers
ADD SP, SP, #8 ; Adjust SP for already-restored banked registers
MOVS PC, LR
ENDP
PAbt_Handler\
PROC
EXPORT PAbt_Handler [WEAK]
IMPORT CPAbtHandler
SUB LR, LR, #4 ; Pre-adjust LR
SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack
PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack
MRC p15, 0, R0, c5, c0, 1 ; IFSR
MRC p15, 0, R1, c6, c0, 2 ; IFAR
MOV R2, LR ; Set LR to third argument
; AND R12, SP, #4 ; Ensure stack is 8-byte aligned
MOV R3, SP ; Ensure stack is 8-byte aligned
AND R12, R3, #4
SUB SP, SP, R12 ; Adjust stack
PUSH {R12, LR} ; Store stack adjustment and dummy LR
BL CPAbtHandler
POP {R12, LR} ; Get stack adjustment & discard dummy LR
ADD SP, SP, R12 ; Unadjust stack
POP {R0-R4, R12} ; Restore stack APCS registers
RFEFD SP! ; Return from exception
ENDP
DAbt_Handler\
PROC
EXPORT DAbt_Handler [WEAK]
IMPORT CDAbtHandler
SUB LR, LR, #8 ; Pre-adjust LR
SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack
PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack
CLREX ; State of exclusive monitors unknown after taken data abort
MRC p15, 0, R0, c5, c0, 0 ; DFSR
MRC p15, 0, R1, c6, c0, 0 ; DFAR
MOV R2, LR ; Set LR to third argument
; AND R12, SP, #4 ; Ensure stack is 8-byte aligned
MOV R3, SP ; Ensure stack is 8-byte aligned
AND R12, R3, #4
SUB SP, SP, R12 ; Adjust stack
PUSH {R12, LR} ; Store stack adjustment and dummy LR
BL CDAbtHandler
POP {R12, LR} ; Get stack adjustment & discard dummy LR
ADD SP, SP, R12 ; Unadjust stack
POP {R0-R4, R12} ; Restore stacked APCS registers
RFEFD SP! ; Return from exception
ENDP
FIQ_Handler\
PROC
EXPORT FIQ_Handler [WEAK]
;; An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
;; so if a real FIQ Handler is implemented, this will be needed before returning:
;; LDR R1, =GICI_BASE
;; LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
B .
ENDP
SVC_Handler\
PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
IRQ_Handler\
PROC
EXPORT IRQ_Handler [WEAK]
IMPORT IRQCount
IMPORT IRQTable
IMPORT IRQNestLevel
;prologue
SUB LR, LR, #4 ; Pre-adjust LR
SRSFD SP!, #Mode_SVC ; Save LR_IRQ and SPRS_IRQ to SVC mode stack
CPS #Mode_SVC ; Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL
PUSH {R0-R3, R12} ; Save remaining APCS corruptible registers to SVC stack
; AND R1, SP, #4 ; Ensure stack is 8-byte aligned
MOV R3, SP ; Ensure stack is 8-byte aligned
AND R1, R3, #4
SUB SP, SP, R1 ; Adjust stack
PUSH {R1, LR} ; Store stack adjustment and LR_SVC to SVC stack
LDR R0, =IRQNestLevel ; Get address of nesting counter
LDR R1, [R0]
ADD R1, R1, #1 ; Increment nesting counter
STR R1, [R0]
;identify and acknowledge interrupt
LDR R1, =GICI_BASE
LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
LDR R0, [R1, #ICCIAR_OFFSET] ; Read ICCIAR (GIC CPU Interface register)
DSB ; Ensure that interrupt acknowledge completes before re-enabling interrupts
; Workaround GIC 390 errata 733075
; If the ID is not 0, then service the interrupt as normal.
; If the ID is 0 and active, then service interrupt ID 0 as normal.
; If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
; with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced.
;
LDR R2, =GICD_BASE
LDR R3, =GIC_ERRATA_CHECK_1
CMP R0, R3
BEQ unlock_cpu
LDR R3, =GIC_ERRATA_CHECK_2
CMP R0, R3
BEQ unlock_cpu
CMP R0, #0
BNE int_active ; If the ID is not 0, then service the interrupt
LDR R3, [R2, #ICDABR0_OFFSET] ; Get the interrupt state
TST R3, #1
BNE int_active ; If active, then service the interrupt
unlock_cpu
LDR R3, [R2, #ICDIPR0_OFFSET] ; Not active, so unlock the CPU interface
STR R3, [R2, #ICDIPR0_OFFSET] ; with a dummy write
DSB ; Ensure the write completes before continuing
B ret_irq ; Do not service the spurious interrupt
; End workaround
int_active
LDR R2, =IRQCount ; Read number of IRQs
LDR R2, [R2]
CMP R0, R2 ; Clean up and return if no handler
BHS ret_irq ; In a single-processor system, spurious interrupt ID 1023 does not need any special handling
LDR R2, =IRQTable ; Get address of handler
LDR R2, [R2, R0, LSL #2]
CMP R2, #0 ; Clean up and return if handler address is 0
BEQ ret_irq
PUSH {R0,R1}
CPSIE i ; Now safe to re-enable interrupts
BLX R2 ; Call handler. R0 will be IRQ number
CPSID i ; Disable interrupts again
;write EOIR (GIC CPU Interface register)
POP {R0,R1}
DSB ; Ensure that interrupt source is cleared before we write the EOIR
ret_irq
;epilogue
STR R0, [R1, #ICCEOIR_OFFSET]
LDR R0, =IRQNestLevel ; Get address of nesting counter
LDR R1, [R0]
SUB R1, R1, #1 ; Decrement nesting counter
STR R1, [R0]
POP {R1, LR} ; Get stack adjustment and restore LR_SVC
ADD SP, SP, R1 ; Unadjust stack
POP {R0-R3,R12} ; Restore stacked APCS registers
RFEFD SP! ; Return from exception
ENDP
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + USR_Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDIF
END

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/* Linker script for mbed LPC1768 */
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x20000000, LENGTH = 512K
RAM (rwx) : ORIGIN = 0x20080000, LENGTH = (1M)
USB_RAM(rwx) : ORIGIN = 0x20180000, LENGTH = 16K
ETH_RAM(rwx) : ORIGIN = 0x20280000, LENGTH = 16K
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
Image$$RW_RAM1$$Base = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
Image$$RW_RAM1$$ZI$$Limit = . ;
} > RAM
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

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@/*******************************************************************************
@* DISCLAIMER
@* This software is supplied by Renesas Electronics Corporation and is only
@* intended for use with Renesas products. No other uses are authorized. This
@* software is owned by Renesas Electronics Corporation and is protected under
@* all applicable laws, including copyright laws.
@* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
@* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
@* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
@* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
@* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
@* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
@* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
@* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
@* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
@* Renesas reserves the right, without notice, to make changes to this software
@* and to discontinue the availability of this software. By using this software,
@* you agree to the additional terms and conditions found by accessing the
@* following link:
@* http://www.renesas.com/disclaimer
@* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
@*******************************************************************************/
@/*******************************************************************************
@* File Name : irqfiq_handler.s
@* $Rev: 823 $
@* $Date:: 2014-04-21 16:45:10 +0900#$
@* Description : IRQ, FIQ handler
@*******************************************************************************/
@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
.EQU SYS_MODE, 0x1f
@ INTC ICCIAR register address
.EQU INTC_ICCIAR_ADDR, 0xE820200C
@ INTC ICCEOIR register address
.EQU INTC_ICCEOIR_ADDR, 0xE8202010
@ INTC ICDABR0 register address
.EQU INTC_ICDABR0_ADDR, 0xE8201300
@ INTC ICDIPR0 register address
.EQU INTC_ICDIPR0_ADDR, 0xE8201400
@ INTC ICCHPIR register address
.EQU INTC_ICCHPIR_ADDR, 0xE8202018
@==================================================================
@ Entry point for the FIQ handler
@==================================================================
@ PRESERVE8
@ .section IRQ_FIQ_HANDLER, #execinstr
.text
.arm
@ IMPORT FiqHandler_Interrupt
@ IMPORT INTC_Handler_Interrupt
.global irq_handler
.global fiq_handler
@******************************************************************************
@ Function Name : fiq_handler
@ Description : This function is the assembler function executed when the FIQ
@ : interrupt is generated.
@******************************************************************************
fiq_handler:
B FiqHandler_Interrupt
@******************************************************************************
@ Function Name : irq_handler
@ Description : This function is the assembler function executed when the IRQ
@ : interrupt is generated. After saving the stack pointer and
@ : the stack for general registers and obtaining the INTC interrupt
@ : source ID, calls the IntcIrqHandler_interrupt function written
@ : in C language to execute the processing for the INTC interrupt
@ : handler corresponding to the interrupt source ID.
@ : After the INTC interrupt handler processing, restores
@ : the stack pointer and the general registers from the stack and
@ : returns from the IRQ interrupt processing.
@******************************************************************************
irq_handler:
SUB lr, lr, #4
SRSDB sp!, #SYS_MODE @;; Store LR_irq and SPSR_irq in system mode stack
CPS #SYS_MODE @;; Switch to system mode
PUSH {r0-r3, r12} @;; Store other AAPCS registers
LDR r1, =INTC_ICCHPIR_ADDR
LDR r3, [r1]
LDR r2, =INTC_ICCIAR_ADDR
LDR r0, [r2] @;; Read ICCIAR
LDR r2, =0x000003FF
AND r3, r0, r2
CMP r3, r2
BEQ end_of_handler
CMP r3, #0
BNE int_active
LDR r2, =INTC_ICDABR0_ADDR
LDR r3, [r2]
AND r3, r3, #0x00000001
CMP r3, #0
BNE int_active
LDR r2, =INTC_ICDIPR0_ADDR
LDR r3, [r2]
STR r3, [r2]
B end_of_handler
int_active:
PUSH {r0}
MOV r1, sp @;;
AND r1, r1, #4 @;; Make alignment for stack
SUB sp, sp, r1 @;;
PUSH {r1, lr}
BL INTC_Handler_Interrupt @;; First argument(r0) = ICCIAR read value
POP {r1, lr}
ADD sp, sp, r1
POP {r0}
LDR r2, =INTC_ICCEOIR_ADDR
STR r0, [r2] @;; Write ICCEOIR
end_of_handler:
POP {r0-r3, r12} @;; Restore registers
RFEIA sp! @;; Return from system mode stack using RFE
Literals3:
.LTORG
.END

247
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/* File: startup_ARMCM3.s
* Purpose: startup file for Cortex-M3/M4 devices. Should use with
* GNU Tools for ARM Embedded Processors
* Version: V1.1
* Date: 17 June 2011
*
* Copyright (C) 2011 ARM Limited. All rights reserved.
* ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*/
.syntax unified
@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
.equ USR_MODE, 0x10
.equ FIQ_MODE, 0x11
.equ IRQ_MODE, 0x12
.equ SVC_MODE, 0x13
.equ ABT_MODE, 0x17
.equ UND_MODE, 0x1b
.equ SYS_MODE, 0x1f
.equ Thum_bit, 0x20 @ CPSR/SPSR Thumb bit
/* Memory Model
The HEAP starts at the end of the DATA section and grows upward.
The STACK starts at the end of the RAM and grows downward.
The HEAP and stack STACK are only checked at compile time:
(DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
This is just a check for the bare minimum for the Heap+Stack area before
aborting compilation, it is not the run time limit:
Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
*/
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0xc00
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
__AStackLimit:
.space Stack_Size
.size __AStackLimit, . - __AStackLimit
__AStackTop:
.size __AStackTop, . - __AStackTop
__BStackLimit:
.space Stack_Size
.size __BStackLimit, . - __StackLimit
__BStackTop:
.size __BStackTop, . - __BStackTop
__CStackLimit:
.space Stack_Size
.size __CStackLimit, . - __CStackLimit
__CStackTop:
.size __CStackTop, . - __CStackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x800
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.space Heap_Size
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long 0xe59ff018 // 0x00
.long 0xe59ff018 // 0x04
.long 0xe59ff018 // 0x08
.long 0xe59ff018 // 0x0c
.long 0xe59ff018 // 0x10
.long 0xe59ff018 // 0x14
.long 0xe59ff018 // 0x18
.long 0xe59ff018 // 0x1c
.long Reset_Handler /* 0x20 */
.long undefinedInstruction /* 0x24 */
.long softwareInterrupt /* 0x28 */
.long prefetchAboart /* 0x2c */
.long dataAbort /* 0x30 */
.long 0 /* Reserved */
.long irq_handler /* IRQ */
.long fiq_handler /* FIQ */
.size __isr_vector, . - __isr_vector
.text
// .thumb
// .thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* _etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
mrc p15, 0, r0, c1, c0, 0 @;; Read CP15 System Control register (SCTLR)
bic r0, r0, #(0x1 << 12) @;; Clear I bit 12 to disable I Cache
bic r0, r0, #(0x1 << 2) @;; Clear C bit 2 to disable D Cache
bic r0, r0, #0x1 @;; Clear M bit 0 to disable MMU
mcr p15, 0, r0, c1, c0, 0 @;; Write value back to CP15 System Control register
@;; SVC Mode(Default)
LDR sp, =__AStackTop
CPS #IRQ_MODE @;; IRQ Mode
LDR sp, =__BStackTop
CPS #FIQ_MODE @;; FIQ Mode
LDR sp, =__CStackTop
@CPS #ABT_MODE @;; ABT Mode
@LDR sp, =__StackTop
CPS #SYS_MODE @;; SYS Mode
@; System mode Stack pointer is set up ARM_LIB_STACK in the __main()->__entry()
LDR sp, =__StackTop
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.Lflash_to_ram_loop:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .Lflash_to_ram_loop
ldr r0, =set_low_vector
blx r0
ldr r0, =enable_VFP
blx r0
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
set_low_vector:
mrc p15, 0, r0, c1, c0, 0
mov r1, #0xffffdfff
and r0, r1
mcr p15, 0, r0, c1, c0, 0
mrc p15, 0, r0, c12, c0, 0 // vector set
mov r0, #0x20000000
mcr p15, 0, r0, c12, c0, 0 // vector set
bx lr
.equ VFPEnable, 0x40000000
enable_VFP:
;;
mrc p15, 0, r0, c1, c0, 2 ;
orr r0, r0, #(3 << 20) ;
orr r0, r0, #(3 << 22) ;
bic r0, r0, #(3 << 30) ;
mcr p15, 0, r0, c1, c0, 2 ;
isb ;
;;
mov r0, #VFPEnable
vmsr fpexc, r0
bx lr
;;
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler undefinedInstruction /* 0x24 */
def_default_handler softwareInterrupt /* 0x28 */
def_default_handler prefetchAboart /* 0x2c */
def_default_handler dataAbort /* 0x30 */
def_default_handler Default_Handler /* --- */
.global __disable_irq
.global __enable_irq
.global __disable_fiq
.global __enable_fiq
__disable_irq:
mrs r0,apsr @ formerly cpsr
and r0,r0,#0x80
cpsid i
bx lr
__enable_irq:
cpsie i
bx lr
__disable_fiq:
cpsid f
bx lr
__enable_fiq:
cpsie f
bx lr
.end

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/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in LPC1768 specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "MBRZA1H.h"
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/******************************************************************************
* File Name : dev_drv.h
* $Rev: 809 $
* $Date:: 2014-04-09 15:06:36 +0900#$
* Description : Device driver header
******************************************************************************/
#ifndef DEV_DRV_H
#define DEV_DRV_H
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/* ==== Arguments, Return values ==== */
#define DEVDRV_SUCCESS (0) /* Success */
#define DEVDRV_ERROR (-1) /* Failure */
/* ==== Flags ==== */
#define DEVDRV_FLAG_OFF (0) /* Flag OFF */
#define DEVDRV_FLAG_ON (1) /* Flag ON */
/* ==== Channels ==== */
typedef enum devdrv_ch
{
DEVDRV_CH_0, /* Channel 0 */
DEVDRV_CH_1, /* Channel 1 */
DEVDRV_CH_2, /* Channel 2 */
DEVDRV_CH_3, /* Channel 3 */
DEVDRV_CH_4, /* Channel 4 */
DEVDRV_CH_5, /* Channel 5 */
DEVDRV_CH_6, /* Channel 6 */
DEVDRV_CH_7, /* Channel 7 */
DEVDRV_CH_8, /* Channel 8 */
DEVDRV_CH_9, /* Channel 9 */
DEVDRV_CH_10, /* Channel 10 */
DEVDRV_CH_11, /* Channel 11 */
DEVDRV_CH_12, /* Channel 12 */
DEVDRV_CH_13, /* Channel 13 */
DEVDRV_CH_14, /* Channel 14 */
DEVDRV_CH_15 /* Channel 15 */
} devdrv_ch_t;
/******************************************************************************
Variable Externs
******************************************************************************/
/******************************************************************************
Functions Prototypes
******************************************************************************/
#endif /* DEV_DRV_H */
/* End of File */

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/**************************************************************************//**
* @file gic.c
* @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
* @version
* @date 19 Sept 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#include "MBRZA1H.h"
#define GICDistributor ((GICDistributor_Type *) Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */
#define GICInterface ((GICInterface_Type *) Renesas_RZ_A1_GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */
/* Globals for use of post-scatterloading code that must access GIC */
const uint32_t GICDistributor_BASE = Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE;
const uint32_t GICInterface_BASE = Renesas_RZ_A1_GIC_INTERFACE_BASE;
void GIC_EnableDistributor(void)
{
GICDistributor->ICDDCR |= 1; //enable distributor
}
void GIC_DisableDistributor(void)
{
GICDistributor->ICDDCR &=~1; //disable distributor
}
uint32_t GIC_DistributorInfo(void)
{
return (uint32_t)(GICDistributor->ICDICTR);
}
uint32_t GIC_DistributorImplementer(void)
{
return (uint32_t)(GICDistributor->ICDIIDR);
}
void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
{
volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
field += IRQn % 4;
*field = (uint8_t)cpu_target & 0xf;
}
void GIC_SetICDICFR (const uint32_t *ICDICFRn)
{
uint32_t i, num_irq;
//Get the maximum number of interrupts that the GIC supports
num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
for (i = 0; i < (num_irq/16); i++)
{
GICDistributor->ICDISPR[i] = *ICDICFRn++;
}
}
uint32_t GIC_GetTarget(IRQn_Type IRQn)
{
volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
field += IRQn % 4;
return ((uint32_t)*field & 0xf);
}
void GIC_EnableInterface(void)
{
GICInterface->ICCICR |= 1; //enable interface
}
void GIC_DisableInterface(void)
{
GICInterface->ICCICR &=~1; //disable distributor
}
IRQn_Type GIC_AcknowledgePending(void)
{
return (IRQn_Type)(GICInterface->ICCIAR);
}
void GIC_EndInterrupt(IRQn_Type IRQn)
{
GICInterface->ICCEOIR = IRQn;
}
void GIC_EnableIRQ(IRQn_Type IRQn)
{
GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
}
void GIC_DisableIRQ(IRQn_Type IRQn)
{
GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
}
void GIC_SetPendingIRQ(IRQn_Type IRQn)
{
GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
}
void GIC_ClearPendingIRQ(IRQn_Type IRQn)
{
GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
}
void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
{
volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDICFR[IRQn / 16]);
int bit_shift = (IRQn % 16)<<1;
uint8_t save_byte;
field += (bit_shift / 8);
bit_shift %= 8;
save_byte = *field;
save_byte &= ((uint8_t)~(3u << bit_shift));
*field = save_byte | ((uint8_t)((edge_level<<1) | model)<< bit_shift);
}
void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
field += (IRQn % 4);
*field = (uint8_t)priority;
}
uint32_t GIC_GetPriority(IRQn_Type IRQn)
{
volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
field += (IRQn % 4);
return (uint32_t)*field;
}
void GIC_InterfacePriorityMask(uint32_t priority)
{
GICInterface->ICCPMR = priority & 0xff; //set priority mask
}
void GIC_SetBinaryPoint(uint32_t binary_point)
{
GICInterface->ICCBPR = binary_point & 0x07; //set binary point
}
uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
{
return (uint32_t)GICInterface->ICCBPR;
}
uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
{
uint32_t pending, active;
active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
return ((active<<1) | pending);
}
void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
{
GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
}
void GIC_DistInit(void)
{
//IRQn_Type i;
uint32_t i;
uint32_t num_irq = 0;
uint32_t priority_field;
//A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
//configuring all of the interrupts as Secure.
//Disable interrupt forwarding
GIC_DisableDistributor();
//Get the maximum number of interrupts that the GIC supports
num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
/* Priority level is implementation defined.
To determine the number of priority bits implemented write 0xFF to an ICDIPR
priority field and read back the value stored.*/
GIC_SetPriority((IRQn_Type)0, 0xff);
priority_field = GIC_GetPriority((IRQn_Type)0);
for (i = 32; i < num_irq; i++)
{
//Disable all SPI the interrupts
GIC_DisableIRQ((IRQn_Type)i);
//Set level-sensitive and N-N model
//GIC_SetLevelModel(i, 0, 0);
//Set priority
GIC_SetPriority((IRQn_Type)i, priority_field/2);
//Set target list to "all cpus"
GIC_SetTarget((IRQn_Type)i, 0xff);
}
/* Set level-edge and 1-N model */
/* GICDistributor->ICDICFR[ 0] is read only */
GICDistributor->ICDICFR[ 1] = 0x00000055;
GICDistributor->ICDICFR[ 2] = 0xFFFD5555;
GICDistributor->ICDICFR[ 3] = 0x555FFFFF;
GICDistributor->ICDICFR[ 4] = 0x55555555;
GICDistributor->ICDICFR[ 5] = 0x55555555;
GICDistributor->ICDICFR[ 6] = 0x55555555;
GICDistributor->ICDICFR[ 7] = 0x55555555;
GICDistributor->ICDICFR[ 8] = 0x5555F555;
GICDistributor->ICDICFR[ 9] = 0x55555555;
GICDistributor->ICDICFR[10] = 0x55555555;
GICDistributor->ICDICFR[11] = 0xF5555555;
GICDistributor->ICDICFR[12] = 0xF555F555;
GICDistributor->ICDICFR[13] = 0x5555F555;
GICDistributor->ICDICFR[14] = 0x55555555;
GICDistributor->ICDICFR[15] = 0x55555555;
GICDistributor->ICDICFR[16] = 0x55555555;
GICDistributor->ICDICFR[17] = 0xFD555555;
GICDistributor->ICDICFR[18] = 0x55555557;
GICDistributor->ICDICFR[19] = 0x55555555;
GICDistributor->ICDICFR[20] = 0xFFD55555;
GICDistributor->ICDICFR[21] = 0x5F55557F;
GICDistributor->ICDICFR[22] = 0xFD55555F;
GICDistributor->ICDICFR[23] = 0x55555557;
GICDistributor->ICDICFR[24] = 0x55555555;
GICDistributor->ICDICFR[25] = 0x55555555;
GICDistributor->ICDICFR[26] = 0x55555555;
GICDistributor->ICDICFR[27] = 0x55555555;
GICDistributor->ICDICFR[28] = 0x55555555;
GICDistributor->ICDICFR[29] = 0x55555555;
GICDistributor->ICDICFR[30] = 0x55555555;
GICDistributor->ICDICFR[31] = 0x55555555;
GICDistributor->ICDICFR[32] = 0x55555555;
GICDistributor->ICDICFR[33] = 0x55555555;
//Enable distributor
GIC_EnableDistributor();
}
void GIC_CPUInterfaceInit(void)
{
IRQn_Type i;
uint32_t priority_field;
//A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
//configuring all of the interrupts as Secure.
//Disable interrupt forwarding
GIC_DisableInterface();
/* Priority level is implementation defined.
To determine the number of priority bits implemented write 0xFF to an ICDIPR
priority field and read back the value stored.*/
GIC_SetPriority((IRQn_Type)0, 0xff);
priority_field = GIC_GetPriority((IRQn_Type)0);
//SGI and PPI
for (i = (IRQn_Type)0; i < 32; i++)
{
//Set level-sensitive and N-N model for PPI
//if(i > 15)
//GIC_SetLevelModel(i, 0, 0);
//Disable SGI and PPI interrupts
GIC_DisableIRQ(i);
//Set priority
GIC_SetPriority(i, priority_field/2);
}
//Enable interface
GIC_EnableInterface();
//Set binary point to 0
GIC_SetBinaryPoint(0);
//Set priority mask
GIC_InterfacePriorityMask(0xff);
}
void GIC_Enable(void)
{
GIC_DistInit();
GIC_CPUInterfaceInit(); //per CPU
}

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/**************************************************************************//**
* @file gic.h
* @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
* @version
* @date 29 August 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef GIC_H_
#define GIC_H_
/* IO definitions (access restrictions to peripheral registers) */
/**
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
*/
typedef struct
{
__IO uint32_t ICDDCR;
__I uint32_t ICDICTR;
__I uint32_t ICDIIDR;
uint32_t RESERVED0[29];
__IO uint32_t ICDISR[32];
__IO uint32_t ICDISER[32];
__IO uint32_t ICDICER[32];
__IO uint32_t ICDISPR[32];
__IO uint32_t ICDICPR[32];
__I uint32_t ICDABR[32];
uint32_t RESERVED1[32];
__IO uint32_t ICDIPR[256];
__IO uint32_t ICDIPTR[256];
__IO uint32_t ICDICFR[64];
uint32_t RESERVED2[128];
__IO uint32_t ICDSGIR;
} GICDistributor_Type;
/** \brief Structure type to access the Controller Interface (GICC)
*/
typedef struct
{
__IO uint32_t ICCICR; // +0x000 - RW - CPU Interface Control Register
__IO uint32_t ICCPMR; // +0x004 - RW - Interrupt Priority Mask Register
__IO uint32_t ICCBPR; // +0x008 - RW - Binary Point Register
__I uint32_t ICCIAR; // +0x00C - RO - Interrupt Acknowledge Register
__IO uint32_t ICCEOIR; // +0x010 - WO - End of Interrupt Register
__I uint32_t ICCRPR; // +0x014 - RO - Running Priority Register
__I uint32_t ICCHPIR; // +0x018 - RO - Highest Pending Interrupt Register
__IO uint32_t ICCABPR; // +0x01C - RW - Aliased Binary Point Register
uint32_t RESERVED[55];
__I uint32_t ICCIIDR; // +0x0FC - RO - CPU Interface Identification Register
} GICInterface_Type;
/*@} end of GICD */
/* ########################## GIC functions #################################### */
/** \brief Functions that manage interrupts via the GIC.
@{
*/
/** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface
Enables the forwarding of pending interrupts to the CPU interfaces.
*/
void GIC_EnableDistributor(void);
/** \brief Disable Distributor
Disables the forwarding of pending interrupts to the CPU interfaces.
*/
void GIC_DisableDistributor(void);
/** \brief Provides information about the configuration of the GIC.
Provides information about the configuration of the GIC.
- whether the GIC implements the Security Extensions
- the maximum number of interrupt IDs that the GIC supports
- the number of CPU interfaces implemented
- if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).
\return Distributor Information.
*/
uint32_t GIC_DistributorInfo(void);
/** \brief Distributor Implementer Identification Register.
Distributor Implementer Identification Register
\return Implementer Information.
*/
uint32_t GIC_DistributorImplementer(void);
/** \brief Set list of processors that the interrupt is sent to if it is asserted.
The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
This field stores the list of processors that the interrupt is sent to if it is asserted.
\param [in] IRQn Interrupt number.
\param [in] target CPU target
*/
void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target);
/** \brief Get list of processors that the interrupt is sent to if it is asserted.
The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
This field stores the list of processors that the interrupt is sent to if it is asserted.
\param [in] IRQn Interrupt number.
\param [in] target CPU target
*/
uint32_t GIC_GetTarget(IRQn_Type IRQn);
/** \brief Enable Interface
Enables the signalling of interrupts to the target processors.
*/
void GIC_EnableInterface(void);
/** \brief Disable Interface
Disables the signalling of interrupts to the target processors.
*/
void GIC_DisableInterface(void);
/** \brief Acknowledge Interrupt
The function acknowledges the highest priority pending interrupt and returns its IRQ number.
\return Interrupt number
*/
IRQn_Type GIC_AcknowledgePending(void);
/** \brief End Interrupt
The function writes the end of interrupt register, indicating that handling of the interrupt is complete.
\param [in] IRQn Interrupt number.
*/
void GIC_EndInterrupt(IRQn_Type IRQn);
/** \brief Enable Interrupt
Set-enable bit for each interrupt supported by the GIC.
\param [in] IRQn External interrupt number.
*/
void GIC_EnableIRQ(IRQn_Type IRQn);
/** \brief Disable Interrupt
Clear-enable bit for each interrupt supported by the GIC.
\param [in] IRQn Number of the external interrupt to disable
*/
void GIC_DisableIRQ(IRQn_Type IRQn);
/** \brief Set Pending Interrupt
Set-pending bit for each interrupt supported by the GIC.
\param [in] IRQn Interrupt number.
*/
void GIC_SetPendingIRQ(IRQn_Type IRQn);
/** \brief Clear Pending Interrupt
Clear-pending bit for each interrupt supported by the GIC
\param [in] IRQn Number of the interrupt for clear pending
*/
void GIC_ClearPendingIRQ(IRQn_Type IRQn);
/** \brief Int_config field for each interrupt supported by the GIC.
This field identifies whether the corresponding interrupt is:
(1) edge-triggered or (0) level-sensitive
(1) 1-N model or (0) N-N model
\param [in] IRQn Interrupt number.
\param [in] edge_level (1) edge-triggered or (0) level-sensitive
\param [in] model (1) 1-N model or (0) N-N model
*/
void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model);
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
*/
uint32_t GIC_GetPriority(IRQn_Type IRQn);
/** \brief CPU Interface Priority Mask Register
The priority mask level for the CPU interface. If the priority of an interrupt is higher than the
value indicated by this field, the interface signals the interrupt to the processor.
\param [in] Mask.
*/
void GIC_InterfacePriorityMask(uint32_t priority);
/** \brief Set the binary point.
Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
\param [in] Mask.
*/
void GIC_SetBinaryPoint(uint32_t binary_point);
/** \brief Get the binary point.
Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
\return Binary point.
*/
uint32_t GIC_GetBinaryPoint(uint32_t binary_point);
/** \brief Get Interrupt state.
Get the interrupt state, whether pending and/or active
\return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active
*/
uint32_t GIC_GetIRQStatus(IRQn_Type IRQn);
/** \brief Send Software Generated interrupt
Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor.
GIC_InterfacePriorityMask
\param [in] IRQn The Interrupt ID of the SGI.
\param [in] target_list CPUTargetList
\param [in] filter_list TargetListFilter
*/
void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list);
/** \brief API call to initialise the interrupt distributor
API call to initialise the interrupt distributor
*/
void GIC_DistInit(void);
/** \brief API call to initialise the CPU interface
API call to initialise the CPU interface
*/
void GIC_CPUInterfaceInit(void);
/** \brief API call to set the Interrupt Configuration Registers
API call to initialise the Interrupt Configuration Registers
*/
void GIC_SetICDICFR (const uint32_t *ICDICFRn);
/** \brief API call to Enable the GIC
API call to Enable the GIC
*/
void GIC_Enable(void);
#endif /* GIC_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef R7S72100_IODEFINE_H
#define R7S72100_IODEFINE_H
#define IODEFINE_H_VERSION 100
enum iodefine_byte_select_t
{
L = 0, H = 1,
LL= 0, LH = 1, HL = 2, HH = 3
};
/***********************************************************************
<<< [iodefine_reg32_t] >>>
- Padding : sizeof(iodefine_reg32_t) == 4
- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
- &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3
- Endian : Independent (Same as CPU endian as register endian)
- Bit-Order : Independent
************************************************************************/
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
union iodefine_reg32_t
{
volatile uint32_t UINT32; /* 32-bit Access */
volatile uint16_t UINT16[2]; /* 16-bit Access */
volatile uint8_t UINT8[4]; /* 8-bit Access */
};
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/***********************************************************************
<<< [iodefine_reg32_16_t] >>>
- Padding : sizeof(iodefine_reg32_16_t) == 4
- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
- Endian : Independent (Same as CPU endian as register endian)
- Bit-Order : Independent
************************************************************************/
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
union iodefine_reg32_16_t
{
volatile uint32_t UINT32; /* 32-bit Access */
volatile uint16_t UINT16[2]; /* 16-bit Access */
};
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/***********************************************************************
<<< [iodefine_reg16_8_t] >>>
- Padding : sizeof(iodefine_reg16_8_t) == 2
- Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1
- Endian : Independent (Same as CPU endian as register endian)
- Bit-Order : Independent
************************************************************************/
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
union iodefine_reg16_8_t
{
volatile uint16_t UINT16; /* 16-bit Access */
volatile uint8_t UINT8[2]; /* 8-bit Access */
};
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
#include "iodefines/adc_iodefine.h" /* (V1.00a) */
#include "iodefines/bsc_iodefine.h" /* (V1.00a) */
#include "iodefines/ceu_iodefine.h" /* (V1.00a) */
#include "iodefines/cpg_iodefine.h" /* (V1.00a) */
#include "iodefines/disc_iodefine.h" /* (V1.00a) */
#include "iodefines/dmac_iodefine.h" /* (V1.00a) */
#include "iodefines/dvdec_iodefine.h" /* (V1.00a) */
#include "iodefines/ether_iodefine.h" /* (V1.00a) */
#include "iodefines/flctl_iodefine.h" /* (V1.00a) */
#include "iodefines/gpio_iodefine.h" /* (V1.00a) */
#include "iodefines/ieb_iodefine.h" /* (V1.00a) */
#include "iodefines/inb_iodefine.h" /* (V1.00a) */
#include "iodefines/intc_iodefine.h" /* (V1.00a) */
#include "iodefines/irda_iodefine.h" /* (V1.00a) */
#include "iodefines/jcu_iodefine.h" /* (V1.00a) */
#include "iodefines/l2c_iodefine.h" /* (V1.00a) */
#include "iodefines/lin_iodefine.h" /* (V1.00a) */
#include "iodefines/lvds_iodefine.h" /* (V1.00a) */
#include "iodefines/mlb_iodefine.h" /* (V1.00a) */
#include "iodefines/mmc_iodefine.h" /* (V1.00a) */
#include "iodefines/mtu2_iodefine.h" /* (V1.00a) */
#include "iodefines/ostm_iodefine.h" /* (V1.00a) */
#include "iodefines/pfv_iodefine.h" /* (V1.00a) */
#include "iodefines/pwm_iodefine.h" /* (V1.00a) */
#include "iodefines/riic_iodefine.h" /* (V1.00a) */
#include "iodefines/romdec_iodefine.h" /* (V1.00a) */
#include "iodefines/rscan0_iodefine.h" /* (V1.00a) */
#include "iodefines/rspi_iodefine.h" /* (V1.00a) */
#include "iodefines/rtc_iodefine.h" /* (V1.00a) */
#include "iodefines/scif_iodefine.h" /* (V1.00a) */
#include "iodefines/scim_iodefine.h" /* (V1.00a) */
#include "iodefines/scux_iodefine.h" /* (V1.00a) */
#include "iodefines/sdg_iodefine.h" /* (V1.00a) */
#include "iodefines/spdif_iodefine.h" /* (V1.00a) */
#include "iodefines/spibsc_iodefine.h" /* (V1.00a) */
#include "iodefines/ssif_iodefine.h" /* (V1.00a) */
#include "iodefines/usb20_iodefine.h" /* (V1.00a) */
#include "iodefines/vdc5_iodefine.h" /* (V1.00a) */
#include "iodefines/wdt_iodefine.h" /* (V1.00a) */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : adc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef ADC_IODEFINE_H
#define ADC_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_adc
{ /* ADC */
volatile uint16_t ADDRA; /* ADDRA */
volatile uint16_t ADDRB; /* ADDRB */
volatile uint16_t ADDRC; /* ADDRC */
volatile uint16_t ADDRD; /* ADDRD */
volatile uint16_t ADDRE; /* ADDRE */
volatile uint16_t ADDRF; /* ADDRF */
volatile uint16_t ADDRG; /* ADDRG */
volatile uint16_t ADDRH; /* ADDRH */
volatile uint8_t dummy32[16]; /* */
volatile uint16_t ADCMPHA; /* ADCMPHA */
volatile uint16_t ADCMPLA; /* ADCMPLA */
volatile uint16_t ADCMPHB; /* ADCMPHB */
volatile uint16_t ADCMPLB; /* ADCMPLB */
volatile uint16_t ADCMPHC; /* ADCMPHC */
volatile uint16_t ADCMPLC; /* ADCMPLC */
volatile uint16_t ADCMPHD; /* ADCMPHD */
volatile uint16_t ADCMPLD; /* ADCMPLD */
volatile uint16_t ADCMPHE; /* ADCMPHE */
volatile uint16_t ADCMPLE; /* ADCMPLE */
volatile uint16_t ADCMPHF; /* ADCMPHF */
volatile uint16_t ADCMPLF; /* ADCMPLF */
volatile uint16_t ADCMPHG; /* ADCMPHG */
volatile uint16_t ADCMPLG; /* ADCMPLG */
volatile uint16_t ADCMPHH; /* ADCMPHH */
volatile uint16_t ADCMPLH; /* ADCMPLH */
volatile uint8_t dummy33[32]; /* */
volatile uint16_t ADCSR; /* ADCSR */
volatile uint16_t ADCMPER; /* ADCMPER */
volatile uint16_t ADCMPSR; /* ADCMPSR */
};
#define ADC (*(struct st_adc *)0xE8005800uL) /* ADC */
#define ADCADDRA ADC.ADDRA
#define ADCADDRB ADC.ADDRB
#define ADCADDRC ADC.ADDRC
#define ADCADDRD ADC.ADDRD
#define ADCADDRE ADC.ADDRE
#define ADCADDRF ADC.ADDRF
#define ADCADDRG ADC.ADDRG
#define ADCADDRH ADC.ADDRH
#define ADCADCMPHA ADC.ADCMPHA
#define ADCADCMPLA ADC.ADCMPLA
#define ADCADCMPHB ADC.ADCMPHB
#define ADCADCMPLB ADC.ADCMPLB
#define ADCADCMPHC ADC.ADCMPHC
#define ADCADCMPLC ADC.ADCMPLC
#define ADCADCMPHD ADC.ADCMPHD
#define ADCADCMPLD ADC.ADCMPLD
#define ADCADCMPHE ADC.ADCMPHE
#define ADCADCMPLE ADC.ADCMPLE
#define ADCADCMPHF ADC.ADCMPHF
#define ADCADCMPLF ADC.ADCMPLF
#define ADCADCMPHG ADC.ADCMPHG
#define ADCADCMPLG ADC.ADCMPLG
#define ADCADCMPHH ADC.ADCMPHH
#define ADCADCMPLH ADC.ADCMPLH
#define ADCADCSR ADC.ADCSR
#define ADCADCMPER ADC.ADCMPER
#define ADCADCMPSR ADC.ADCMPSR
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : bsc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef BSC_IODEFINE_H
#define BSC_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_bsc
{ /* BSC */
volatile uint32_t CMNCR; /* CMNCR */
#define BSC_CSnBCR_COUNT 6
volatile uint32_t CS0BCR; /* CS0BCR */
volatile uint32_t CS1BCR; /* CS1BCR */
volatile uint32_t CS2BCR; /* CS2BCR */
volatile uint32_t CS3BCR; /* CS3BCR */
volatile uint32_t CS4BCR; /* CS4BCR */
volatile uint32_t CS5BCR; /* CS5BCR */
volatile uint8_t dummy4[12]; /* */
#define BSC_CSnWCR_COUNT 6
volatile uint32_t CS0WCR; /* CS0WCR */
volatile uint32_t CS1WCR; /* CS1WCR */
volatile uint32_t CS2WCR; /* CS2WCR */
volatile uint32_t CS3WCR; /* CS3WCR */
volatile uint32_t CS4WCR; /* CS4WCR */
volatile uint32_t CS5WCR; /* CS5WCR */
volatile uint8_t dummy5[12]; /* */
volatile uint32_t SDCR; /* SDCR */
volatile uint32_t RTCSR; /* RTCSR */
volatile uint32_t RTCNT; /* RTCNT */
volatile uint32_t RTCOR; /* RTCOR */
volatile uint8_t dummy6[4]; /* */
#define BSC_TOSCORn_COUNT 6
volatile uint32_t TOSCOR0; /* TOSCOR0 */
volatile uint32_t TOSCOR1; /* TOSCOR1 */
volatile uint32_t TOSCOR2; /* TOSCOR2 */
volatile uint32_t TOSCOR3; /* TOSCOR3 */
volatile uint32_t TOSCOR4; /* TOSCOR4 */
volatile uint32_t TOSCOR5; /* TOSCOR5 */
volatile uint8_t dummy7[8]; /* */
volatile uint32_t TOSTR; /* TOSTR */
volatile uint32_t TOENR; /* TOENR */
};
#define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */
#define BSCCMNCR BSC.CMNCR
#define BSCCS0BCR BSC.CS0BCR
#define BSCCS1BCR BSC.CS1BCR
#define BSCCS2BCR BSC.CS2BCR
#define BSCCS3BCR BSC.CS3BCR
#define BSCCS4BCR BSC.CS4BCR
#define BSCCS5BCR BSC.CS5BCR
#define BSCCS0WCR BSC.CS0WCR
#define BSCCS1WCR BSC.CS1WCR
#define BSCCS2WCR BSC.CS2WCR
#define BSCCS3WCR BSC.CS3WCR
#define BSCCS4WCR BSC.CS4WCR
#define BSCCS5WCR BSC.CS5WCR
#define BSCSDCR BSC.SDCR
#define BSCRTCSR BSC.RTCSR
#define BSCRTCNT BSC.RTCNT
#define BSCRTCOR BSC.RTCOR
#define BSCTOSCOR0 BSC.TOSCOR0
#define BSCTOSCOR1 BSC.TOSCOR1
#define BSCTOSCOR2 BSC.TOSCOR2
#define BSCTOSCOR3 BSC.TOSCOR3
#define BSCTOSCOR4 BSC.TOSCOR4
#define BSCTOSCOR5 BSC.TOSCOR5
#define BSCTOSTR BSC.TOSTR
#define BSCTOENR BSC.TOENR
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ceu_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef CEU_IODEFINE_H
#define CEU_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_ceu
{ /* CEU */
/* start of struct st_ceu_n */
volatile uint32_t CAPSR; /* CAPSR */
volatile uint32_t CAPCR; /* CAPCR */
volatile uint32_t CAMCR; /* CAMCR */
volatile uint32_t CMCYR; /* CMCYR */
volatile uint32_t CAMOR_A; /* CAMOR_A */
volatile uint32_t CAPWR_A; /* CAPWR_A */
volatile uint32_t CAIFR; /* CAIFR */
volatile uint8_t dummy305[12]; /* */
volatile uint32_t CRCNTR; /* CRCNTR */
volatile uint32_t CRCMPR; /* CRCMPR */
volatile uint32_t CFLCR_A; /* CFLCR_A */
volatile uint32_t CFSZR_A; /* CFSZR_A */
volatile uint32_t CDWDR_A; /* CDWDR_A */
volatile uint32_t CDAYR_A; /* CDAYR_A */
volatile uint32_t CDACR_A; /* CDACR_A */
volatile uint32_t CDBYR_A; /* CDBYR_A */
volatile uint32_t CDBCR_A; /* CDBCR_A */
volatile uint32_t CBDSR_A; /* CBDSR_A */
volatile uint8_t dummy306[12]; /* */
volatile uint32_t CFWCR; /* CFWCR */
volatile uint32_t CLFCR_A; /* CLFCR_A */
volatile uint32_t CDOCR_A; /* CDOCR_A */
volatile uint8_t dummy307[8]; /* */
volatile uint32_t CEIER; /* CEIER */
volatile uint32_t CETCR; /* CETCR */
volatile uint8_t dummy308[4]; /* */
volatile uint32_t CSTSR; /* CSTSR */
volatile uint8_t dummy309[4]; /* */
volatile uint32_t CDSSR; /* CDSSR */
volatile uint8_t dummy310[8]; /* */
volatile uint32_t CDAYR2_A; /* CDAYR2_A */
volatile uint32_t CDACR2_A; /* CDACR2_A */
volatile uint32_t CDBYR2_A; /* CDBYR2_A */
volatile uint32_t CDBCR2_A; /* CDBCR2_A */
/* end of struct st_ceu_n */
volatile uint8_t dummy3110[3936]; /* */
/* start of struct st_ceu_n */
volatile uint8_t dummy3111[4]; /* */
volatile uint8_t dummy3112[4]; /* */
volatile uint8_t dummy3113[4]; /* */
volatile uint8_t dummy3114[4]; /* */
volatile uint32_t CAMOR_B; /* CAMOR_B */
volatile uint32_t CAPWR_B; /* CAPWR_B */
volatile uint8_t dummy3120[4]; /* */
volatile uint8_t dummy3121[12]; /* */
volatile uint8_t dummy3122[4]; /* */
volatile uint8_t dummy3123[4]; /* */
volatile uint32_t CFLCR_B; /* CFLCR_B */
volatile uint32_t CFSZR_B; /* CFSZR_B */
volatile uint32_t CDWDR_B; /* CDWDR_B */
volatile uint32_t CDAYR_B; /* CDAYR_B */
volatile uint32_t CDACR_B; /* CDACR_B */
volatile uint32_t CDBYR_B; /* CDBYR_B */
volatile uint32_t CDBCR_B; /* CDBCR_B */
volatile uint32_t CBDSR_B; /* CBDSR_B */
volatile uint8_t dummy3130[12]; /* */
volatile uint8_t dummy3131[4]; /* */
volatile uint32_t CLFCR_B; /* CLFCR_B */
volatile uint32_t CDOCR_B; /* CDOCR_B */
volatile uint8_t dummy3140[8]; /* */
volatile uint8_t dummy3141[4]; /* */
volatile uint8_t dummy3142[4]; /* */
volatile uint8_t dummy3143[4]; /* */
volatile uint8_t dummy3144[4]; /* */
volatile uint8_t dummy3145[4]; /* */
volatile uint8_t dummy3146[4]; /* */
volatile uint8_t dummy3147[8]; /* */
volatile uint32_t CDAYR2_B; /* CDAYR2_B */
volatile uint32_t CDACR2_B; /* CDACR2_B */
volatile uint32_t CDBYR2_B; /* CDBYR2_B */
volatile uint32_t CDBCR2_B; /* CDBCR2_B */
/* end of struct st_ceu_n */
volatile uint8_t dummy3150[3936]; /* */
/* start of struct st_ceu_n */
volatile uint8_t dummy3151[4]; /* */
volatile uint8_t dummy3152[4]; /* */
volatile uint8_t dummy3153[4]; /* */
volatile uint8_t dummy3154[4]; /* */
volatile uint32_t CAMOR_M; /* CAMOR_M */
volatile uint32_t CAPWR_M; /* CAPWR_M */
volatile uint8_t dummy3160[4]; /* */
volatile uint8_t dummy3161[12]; /* */
volatile uint8_t dummy3162[4]; /* */
volatile uint8_t dummy3163[4]; /* */
volatile uint32_t CFLCR_M; /* CFLCR_M */
volatile uint32_t CFSZR_M; /* CFSZR_M */
volatile uint32_t CDWDR_M; /* CDWDR_M */
volatile uint32_t CDAYR_M; /* CDAYR_M */
volatile uint32_t CDACR_M; /* CDACR_M */
volatile uint32_t CDBYR_M; /* CDBYR_M */
volatile uint32_t CDBCR_M; /* CDBCR_M */
volatile uint32_t CBDSR_M; /* CBDSR_M */
volatile uint8_t dummy3170[12]; /* */
volatile uint8_t dummy3171[4]; /* */
volatile uint32_t CLFCR_M; /* CLFCR_M */
volatile uint32_t CDOCR_M; /* CDOCR_M */
volatile uint8_t dummy3180[8]; /* */
volatile uint8_t dummy3181[4]; /* */
volatile uint8_t dummy3182[4]; /* */
volatile uint8_t dummy3183[4]; /* */
volatile uint8_t dummy3184[4]; /* */
volatile uint8_t dummy3185[4]; /* */
volatile uint8_t dummy3186[4]; /* */
volatile uint8_t dummy3187[8]; /* */
volatile uint32_t CDAYR2_M; /* CDAYR2_M */
volatile uint32_t CDACR2_M; /* CDACR2_M */
volatile uint32_t CDBYR2_M; /* CDBYR2_M */
volatile uint32_t CDBCR2_M; /* CDBCR2_M */
/* end of struct st_ceu_n */
};
struct st_ceu_n
{
volatile uint32_t not_common1; /* */
volatile uint32_t not_common2; /* */
volatile uint32_t not_common3; /* */
volatile uint32_t not_common4; /* */
volatile uint32_t CAMOR; /* CAMOR */
volatile uint32_t CAPWR; /* CAPWR */
volatile uint32_t not_common5; /* */
volatile uint8_t dummy322[12]; /* */
volatile uint32_t not_common6; /* */
volatile uint32_t not_common7; /* */
volatile uint32_t CFLCR; /* CFLCR */
volatile uint32_t CFSZR; /* CFSZR */
volatile uint32_t CDWDR; /* CDWDR */
volatile uint32_t CDAYR; /* CDAYR */
volatile uint32_t CDACR; /* CDACR */
volatile uint32_t CDBYR; /* CDBYR */
volatile uint32_t CDBCR; /* CDBCR */
volatile uint32_t CBDSR; /* CBDSR */
volatile uint8_t dummy323[12]; /* */
volatile uint32_t not_common8; /* */
volatile uint32_t CLFCR; /* CLFCR */
volatile uint32_t CDOCR; /* CDOCR */
volatile uint8_t dummy324[8]; /* */
volatile uint32_t not_common9; /* */
volatile uint32_t not_common10; /* */
volatile uint8_t dummy325[4]; /* */
volatile uint32_t not_common11; /* */
volatile uint8_t dummy326[4]; /* */
volatile uint32_t not_common12; /* */
volatile uint8_t dummy327[8]; /* */
volatile uint32_t CDAYR2; /* CDAYR2 */
volatile uint32_t CDACR2; /* CDACR2 */
volatile uint32_t CDBYR2; /* CDBYR2 */
volatile uint32_t CDBCR2; /* CDBCR2 */
};
#define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */
/* Start of channnel array defines of CEU */
/* Channnel array defines of CEUn */
/*(Sample) value = CEUn[ channel ]->CAMOR; */
#define CEUn_COUNT 3
#define CEUn_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
(volatile struct st_ceu_n*)&CEU_A, \
(volatile struct st_ceu_n*)&CEU_B, \
(volatile struct st_ceu_n*)&CEU_M \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */
#define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */
#define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */
/* End of channnel array defines of CEU */
#define CEUCAPSR CEU.CAPSR
#define CEUCAPCR CEU.CAPCR
#define CEUCAMCR CEU.CAMCR
#define CEUCMCYR CEU.CMCYR
#define CEUCAMOR_A CEU.CAMOR_A
#define CEUCAPWR_A CEU.CAPWR_A
#define CEUCAIFR CEU.CAIFR
#define CEUCRCNTR CEU.CRCNTR
#define CEUCRCMPR CEU.CRCMPR
#define CEUCFLCR_A CEU.CFLCR_A
#define CEUCFSZR_A CEU.CFSZR_A
#define CEUCDWDR_A CEU.CDWDR_A
#define CEUCDAYR_A CEU.CDAYR_A
#define CEUCDACR_A CEU.CDACR_A
#define CEUCDBYR_A CEU.CDBYR_A
#define CEUCDBCR_A CEU.CDBCR_A
#define CEUCBDSR_A CEU.CBDSR_A
#define CEUCFWCR CEU.CFWCR
#define CEUCLFCR_A CEU.CLFCR_A
#define CEUCDOCR_A CEU.CDOCR_A
#define CEUCEIER CEU.CEIER
#define CEUCETCR CEU.CETCR
#define CEUCSTSR CEU.CSTSR
#define CEUCDSSR CEU.CDSSR
#define CEUCDAYR2_A CEU.CDAYR2_A
#define CEUCDACR2_A CEU.CDACR2_A
#define CEUCDBYR2_A CEU.CDBYR2_A
#define CEUCDBCR2_A CEU.CDBCR2_A
#define CEUCAMOR_B CEU.CAMOR_B
#define CEUCAPWR_B CEU.CAPWR_B
#define CEUCFLCR_B CEU.CFLCR_B
#define CEUCFSZR_B CEU.CFSZR_B
#define CEUCDWDR_B CEU.CDWDR_B
#define CEUCDAYR_B CEU.CDAYR_B
#define CEUCDACR_B CEU.CDACR_B
#define CEUCDBYR_B CEU.CDBYR_B
#define CEUCDBCR_B CEU.CDBCR_B
#define CEUCBDSR_B CEU.CBDSR_B
#define CEUCLFCR_B CEU.CLFCR_B
#define CEUCDOCR_B CEU.CDOCR_B
#define CEUCDAYR2_B CEU.CDAYR2_B
#define CEUCDACR2_B CEU.CDACR2_B
#define CEUCDBYR2_B CEU.CDBYR2_B
#define CEUCDBCR2_B CEU.CDBCR2_B
#define CEUCAMOR_M CEU.CAMOR_M
#define CEUCAPWR_M CEU.CAPWR_M
#define CEUCFLCR_M CEU.CFLCR_M
#define CEUCFSZR_M CEU.CFSZR_M
#define CEUCDWDR_M CEU.CDWDR_M
#define CEUCDAYR_M CEU.CDAYR_M
#define CEUCDACR_M CEU.CDACR_M
#define CEUCDBYR_M CEU.CDBYR_M
#define CEUCDBCR_M CEU.CDBCR_M
#define CEUCBDSR_M CEU.CBDSR_M
#define CEUCLFCR_M CEU.CLFCR_M
#define CEUCDOCR_M CEU.CDOCR_M
#define CEUCDAYR2_M CEU.CDAYR2_M
#define CEUCDACR2_M CEU.CDACR2_M
#define CEUCDBYR2_M CEU.CDBYR2_M
#define CEUCDBCR2_M CEU.CDBCR2_M
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : cpg_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef CPG_IODEFINE_H
#define CPG_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_cpg
{ /* CPG */
volatile uint16_t FRQCR; /* FRQCR */
volatile uint8_t dummy319[2]; /* */
volatile uint16_t FRQCR2; /* FRQCR2 */
volatile uint8_t dummy320[2]; /* */
volatile uint8_t CPUSTS; /* CPUSTS */
volatile uint8_t dummy321[7]; /* */
volatile uint8_t STBCR1; /* STBCR1 */
volatile uint8_t dummy322[3]; /* */
volatile uint8_t STBCR2; /* STBCR2 */
volatile uint8_t dummy323[11]; /* */
volatile uint8_t STBREQ1; /* STBREQ1 */
volatile uint8_t dummy324[3]; /* */
volatile uint8_t STBREQ2; /* STBREQ2 */
volatile uint8_t dummy325[11]; /* */
volatile uint8_t STBACK1; /* STBACK1 */
volatile uint8_t dummy326[3]; /* */
volatile uint8_t STBACK2; /* STBACK2 */
volatile uint8_t dummy327[955]; /* */
/* start of struct st_cpg_from_syscr1 */
volatile uint8_t SYSCR1; /* SYSCR1 */
volatile uint8_t dummy328[3]; /* */
/* end of struct st_cpg_from_syscr1 */
/* start of struct st_cpg_from_syscr1 */
volatile uint8_t SYSCR2; /* SYSCR2 */
volatile uint8_t dummy329[3]; /* */
/* end of struct st_cpg_from_syscr1 */
/* start of struct st_cpg_from_syscr1 */
volatile uint8_t SYSCR3; /* SYSCR3 */
volatile uint8_t dummy3300[3]; /* */
/* end of struct st_cpg_from_syscr1 */
volatile uint8_t dummy3301[20]; /* */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR3; /* STBCR3 */
volatile uint8_t dummy331[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR4; /* STBCR4 */
volatile uint8_t dummy332[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR5; /* STBCR5 */
volatile uint8_t dummy333[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR6; /* STBCR6 */
volatile uint8_t dummy334[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR7; /* STBCR7 */
volatile uint8_t dummy335[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR8; /* STBCR8 */
volatile uint8_t dummy336[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR9; /* STBCR9 */
volatile uint8_t dummy337[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR10; /* STBCR10 */
volatile uint8_t dummy338[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR11; /* STBCR11 */
volatile uint8_t dummy339[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR12; /* STBCR12 */
volatile uint8_t dummy3400[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
volatile uint8_t dummy3401[24]; /* */
/* start of struct st_cpg_from_swrstcr1 */
volatile uint8_t SWRSTCR1; /* SWRSTCR1 */
volatile uint8_t dummy341[3]; /* */
/* end of struct st_cpg_from_swrstcr1 */
/* start of struct st_cpg_from_swrstcr1 */
volatile uint8_t SWRSTCR2; /* SWRSTCR2 */
volatile uint8_t dummy342[3]; /* */
/* end of struct st_cpg_from_swrstcr1 */
/* start of struct st_cpg_from_swrstcr1 */
volatile uint8_t SWRSTCR3; /* SWRSTCR3 */
volatile uint8_t dummy3430[3]; /* */
/* end of struct st_cpg_from_swrstcr1 */
volatile uint8_t dummy3431[4]; /* */
volatile uint8_t STBCR13; /* STBCR13 */
volatile uint8_t dummy344[70543]; /* */
volatile uint8_t RRAMKP; /* RRAMKP */
volatile uint8_t dummy345[1]; /* */
volatile uint8_t DSCTR; /* DSCTR */
volatile uint8_t dummy346[1]; /* */
volatile uint16_t DSSSR; /* DSSSR */
volatile uint16_t DSESR; /* DSESR */
volatile uint16_t DSFR; /* DSFR */
volatile uint8_t dummy347[6]; /* */
volatile uint8_t XTALCTR; /* XTALCTR */
};
struct st_cpg_from_syscr1
{
volatile uint8_t SYSCR1; /* SYSCR1 */
volatile uint8_t dummy1[3]; /* */
};
struct st_cpg_from_stbcr3
{
volatile uint8_t STBCR3; /* STBCR3 */
volatile uint8_t dummy1[3]; /* */
};
struct st_cpg_from_swrstcr1
{
volatile uint8_t SWRSTCR1; /* SWRSTCR1 */
volatile uint8_t dummy1[3]; /* */
};
#define CPG (*(struct st_cpg *)0xFCFE0010uL) /* CPG */
/* Start of channnel array defines of CPG */
/* Channnel array defines of CPG_FROM_SWRSTCR1_ARRAY */
/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */
#define CPG_FROM_SWRSTCR1_ARRAY_COUNT 3
#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */
#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */
#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */
/* Channnel array defines of CPG_FROM_STBCR3_ARRAY */
/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */
#define CPG_FROM_STBCR3_ARRAY_COUNT 10
#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \
&CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */
#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */
#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */
#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */
#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */
#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */
#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */
#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */
#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */
#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */
/* Channnel array defines of CPG_FROM_SYSCR1_ARRAY */
/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */
#define CPG_FROM_SYSCR1_ARRAY_COUNT 3
#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */
#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */
#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */
/* End of channnel array defines of CPG */
#define CPGFRQCR CPG.FRQCR
#define CPGFRQCR2 CPG.FRQCR2
#define CPGCPUSTS CPG.CPUSTS
#define CPGSTBCR1 CPG.STBCR1
#define CPGSTBCR2 CPG.STBCR2
#define CPGSTBREQ1 CPG.STBREQ1
#define CPGSTBREQ2 CPG.STBREQ2
#define CPGSTBACK1 CPG.STBACK1
#define CPGSTBACK2 CPG.STBACK2
#define CPGSYSCR1 CPG.SYSCR1
#define CPGSYSCR2 CPG.SYSCR2
#define CPGSYSCR3 CPG.SYSCR3
#define CPGSTBCR3 CPG.STBCR3
#define CPGSTBCR4 CPG.STBCR4
#define CPGSTBCR5 CPG.STBCR5
#define CPGSTBCR6 CPG.STBCR6
#define CPGSTBCR7 CPG.STBCR7
#define CPGSTBCR8 CPG.STBCR8
#define CPGSTBCR9 CPG.STBCR9
#define CPGSTBCR10 CPG.STBCR10
#define CPGSTBCR11 CPG.STBCR11
#define CPGSTBCR12 CPG.STBCR12
#define CPGSWRSTCR1 CPG.SWRSTCR1
#define CPGSWRSTCR2 CPG.SWRSTCR2
#define CPGSWRSTCR3 CPG.SWRSTCR3
#define CPGSTBCR13 CPG.STBCR13
#define CPGRRAMKP CPG.RRAMKP
#define CPGDSCTR CPG.DSCTR
#define CPGDSSSR CPG.DSSSR
#define CPGDSESR CPG.DSESR
#define CPGDSFR CPG.DSFR
#define CPGXTALCTR CPG.XTALCTR
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : disc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef DISC_IODEFINE_H
#define DISC_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_disc
{ /* DISC */
volatile uint32_t DOCMCR; /* DOCMCR */
volatile uint32_t DOCMSTR; /* DOCMSTR */
volatile uint32_t DOCMCLSTR; /* DOCMCLSTR */
volatile uint32_t DOCMIENR; /* DOCMIENR */
volatile uint8_t dummy1[4]; /* */
volatile uint32_t DOCMPMR; /* DOCMPMR */
volatile uint32_t DOCMECRCR; /* DOCMECRCR */
volatile uint32_t DOCMCCRCR; /* DOCMCCRCR */
volatile uint32_t DOCMSPXR; /* DOCMSPXR */
volatile uint32_t DOCMSPYR; /* DOCMSPYR */
volatile uint32_t DOCMSZXR; /* DOCMSZXR */
volatile uint32_t DOCMSZYR; /* DOCMSZYR */
volatile uint32_t DOCMCRCIR; /* DOCMCRCIR */
};
#define DISC0 (*(struct st_disc *)0xFCFFA800uL) /* DISC0 */
#define DISC1 (*(struct st_disc *)0xFCFFB000uL) /* DISC1 */
/* Start of channnel array defines of DISC */
/* Channnel array defines of DISC */
/*(Sample) value = DISC[ channel ]->DOCMCR; */
#define DISC_COUNT 2
#define DISC_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&DISC0, &DISC1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of DISC */
#define DISC0DOCMCR DISC0.DOCMCR
#define DISC0DOCMSTR DISC0.DOCMSTR
#define DISC0DOCMCLSTR DISC0.DOCMCLSTR
#define DISC0DOCMIENR DISC0.DOCMIENR
#define DISC0DOCMPMR DISC0.DOCMPMR
#define DISC0DOCMECRCR DISC0.DOCMECRCR
#define DISC0DOCMCCRCR DISC0.DOCMCCRCR
#define DISC0DOCMSPXR DISC0.DOCMSPXR
#define DISC0DOCMSPYR DISC0.DOCMSPYR
#define DISC0DOCMSZXR DISC0.DOCMSZXR
#define DISC0DOCMSZYR DISC0.DOCMSZYR
#define DISC0DOCMCRCIR DISC0.DOCMCRCIR
#define DISC1DOCMCR DISC1.DOCMCR
#define DISC1DOCMSTR DISC1.DOCMSTR
#define DISC1DOCMCLSTR DISC1.DOCMCLSTR
#define DISC1DOCMIENR DISC1.DOCMIENR
#define DISC1DOCMPMR DISC1.DOCMPMR
#define DISC1DOCMECRCR DISC1.DOCMECRCR
#define DISC1DOCMCCRCR DISC1.DOCMCCRCR
#define DISC1DOCMSPXR DISC1.DOCMSPXR
#define DISC1DOCMSPYR DISC1.DOCMSPYR
#define DISC1DOCMSZXR DISC1.DOCMSZXR
#define DISC1DOCMSZYR DISC1.DOCMSZYR
#define DISC1DOCMCRCIR DISC1.DOCMCRCIR
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : dmac_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef DMAC_IODEFINE_H
#define DMAC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->SEC M1.10.1 : Not magic number */
struct st_dmac
{ /* DMAC */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_0; /* N0SA_0 */
volatile uint32_t N0DA_0; /* N0DA_0 */
volatile uint32_t N0TB_0; /* N0TB_0 */
volatile uint32_t N1SA_0; /* N1SA_0 */
volatile uint32_t N1DA_0; /* N1DA_0 */
volatile uint32_t N1TB_0; /* N1TB_0 */
volatile uint32_t CRSA_0; /* CRSA_0 */
volatile uint32_t CRDA_0; /* CRDA_0 */
volatile uint32_t CRTB_0; /* CRTB_0 */
volatile uint32_t CHSTAT_0; /* CHSTAT_0 */
volatile uint32_t CHCTRL_0; /* CHCTRL_0 */
volatile uint32_t CHCFG_0; /* CHCFG_0 */
volatile uint32_t CHITVL_0; /* CHITVL_0 */
volatile uint32_t CHEXT_0; /* CHEXT_0 */
volatile uint32_t NXLA_0; /* NXLA_0 */
volatile uint32_t CRLA_0; /* CRLA_0 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_1; /* N0SA_1 */
volatile uint32_t N0DA_1; /* N0DA_1 */
volatile uint32_t N0TB_1; /* N0TB_1 */
volatile uint32_t N1SA_1; /* N1SA_1 */
volatile uint32_t N1DA_1; /* N1DA_1 */
volatile uint32_t N1TB_1; /* N1TB_1 */
volatile uint32_t CRSA_1; /* CRSA_1 */
volatile uint32_t CRDA_1; /* CRDA_1 */
volatile uint32_t CRTB_1; /* CRTB_1 */
volatile uint32_t CHSTAT_1; /* CHSTAT_1 */
volatile uint32_t CHCTRL_1; /* CHCTRL_1 */
volatile uint32_t CHCFG_1; /* CHCFG_1 */
volatile uint32_t CHITVL_1; /* CHITVL_1 */
volatile uint32_t CHEXT_1; /* CHEXT_1 */
volatile uint32_t NXLA_1; /* NXLA_1 */
volatile uint32_t CRLA_1; /* CRLA_1 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_2; /* N0SA_2 */
volatile uint32_t N0DA_2; /* N0DA_2 */
volatile uint32_t N0TB_2; /* N0TB_2 */
volatile uint32_t N1SA_2; /* N1SA_2 */
volatile uint32_t N1DA_2; /* N1DA_2 */
volatile uint32_t N1TB_2; /* N1TB_2 */
volatile uint32_t CRSA_2; /* CRSA_2 */
volatile uint32_t CRDA_2; /* CRDA_2 */
volatile uint32_t CRTB_2; /* CRTB_2 */
volatile uint32_t CHSTAT_2; /* CHSTAT_2 */
volatile uint32_t CHCTRL_2; /* CHCTRL_2 */
volatile uint32_t CHCFG_2; /* CHCFG_2 */
volatile uint32_t CHITVL_2; /* CHITVL_2 */
volatile uint32_t CHEXT_2; /* CHEXT_2 */
volatile uint32_t NXLA_2; /* NXLA_2 */
volatile uint32_t CRLA_2; /* CRLA_2 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_3; /* N0SA_3 */
volatile uint32_t N0DA_3; /* N0DA_3 */
volatile uint32_t N0TB_3; /* N0TB_3 */
volatile uint32_t N1SA_3; /* N1SA_3 */
volatile uint32_t N1DA_3; /* N1DA_3 */
volatile uint32_t N1TB_3; /* N1TB_3 */
volatile uint32_t CRSA_3; /* CRSA_3 */
volatile uint32_t CRDA_3; /* CRDA_3 */
volatile uint32_t CRTB_3; /* CRTB_3 */
volatile uint32_t CHSTAT_3; /* CHSTAT_3 */
volatile uint32_t CHCTRL_3; /* CHCTRL_3 */
volatile uint32_t CHCFG_3; /* CHCFG_3 */
volatile uint32_t CHITVL_3; /* CHITVL_3 */
volatile uint32_t CHEXT_3; /* CHEXT_3 */
volatile uint32_t NXLA_3; /* NXLA_3 */
volatile uint32_t CRLA_3; /* CRLA_3 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_4; /* N0SA_4 */
volatile uint32_t N0DA_4; /* N0DA_4 */
volatile uint32_t N0TB_4; /* N0TB_4 */
volatile uint32_t N1SA_4; /* N1SA_4 */
volatile uint32_t N1DA_4; /* N1DA_4 */
volatile uint32_t N1TB_4; /* N1TB_4 */
volatile uint32_t CRSA_4; /* CRSA_4 */
volatile uint32_t CRDA_4; /* CRDA_4 */
volatile uint32_t CRTB_4; /* CRTB_4 */
volatile uint32_t CHSTAT_4; /* CHSTAT_4 */
volatile uint32_t CHCTRL_4; /* CHCTRL_4 */
volatile uint32_t CHCFG_4; /* CHCFG_4 */
volatile uint32_t CHITVL_4; /* CHITVL_4 */
volatile uint32_t CHEXT_4; /* CHEXT_4 */
volatile uint32_t NXLA_4; /* NXLA_4 */
volatile uint32_t CRLA_4; /* CRLA_4 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_5; /* N0SA_5 */
volatile uint32_t N0DA_5; /* N0DA_5 */
volatile uint32_t N0TB_5; /* N0TB_5 */
volatile uint32_t N1SA_5; /* N1SA_5 */
volatile uint32_t N1DA_5; /* N1DA_5 */
volatile uint32_t N1TB_5; /* N1TB_5 */
volatile uint32_t CRSA_5; /* CRSA_5 */
volatile uint32_t CRDA_5; /* CRDA_5 */
volatile uint32_t CRTB_5; /* CRTB_5 */
volatile uint32_t CHSTAT_5; /* CHSTAT_5 */
volatile uint32_t CHCTRL_5; /* CHCTRL_5 */
volatile uint32_t CHCFG_5; /* CHCFG_5 */
volatile uint32_t CHITVL_5; /* CHITVL_5 */
volatile uint32_t CHEXT_5; /* CHEXT_5 */
volatile uint32_t NXLA_5; /* NXLA_5 */
volatile uint32_t CRLA_5; /* CRLA_5 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_6; /* N0SA_6 */
volatile uint32_t N0DA_6; /* N0DA_6 */
volatile uint32_t N0TB_6; /* N0TB_6 */
volatile uint32_t N1SA_6; /* N1SA_6 */
volatile uint32_t N1DA_6; /* N1DA_6 */
volatile uint32_t N1TB_6; /* N1TB_6 */
volatile uint32_t CRSA_6; /* CRSA_6 */
volatile uint32_t CRDA_6; /* CRDA_6 */
volatile uint32_t CRTB_6; /* CRTB_6 */
volatile uint32_t CHSTAT_6; /* CHSTAT_6 */
volatile uint32_t CHCTRL_6; /* CHCTRL_6 */
volatile uint32_t CHCFG_6; /* CHCFG_6 */
volatile uint32_t CHITVL_6; /* CHITVL_6 */
volatile uint32_t CHEXT_6; /* CHEXT_6 */
volatile uint32_t NXLA_6; /* NXLA_6 */
volatile uint32_t CRLA_6; /* CRLA_6 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_7; /* N0SA_7 */
volatile uint32_t N0DA_7; /* N0DA_7 */
volatile uint32_t N0TB_7; /* N0TB_7 */
volatile uint32_t N1SA_7; /* N1SA_7 */
volatile uint32_t N1DA_7; /* N1DA_7 */
volatile uint32_t N1TB_7; /* N1TB_7 */
volatile uint32_t CRSA_7; /* CRSA_7 */
volatile uint32_t CRDA_7; /* CRDA_7 */
volatile uint32_t CRTB_7; /* CRTB_7 */
volatile uint32_t CHSTAT_7; /* CHSTAT_7 */
volatile uint32_t CHCTRL_7; /* CHCTRL_7 */
volatile uint32_t CHCFG_7; /* CHCFG_7 */
volatile uint32_t CHITVL_7; /* CHITVL_7 */
volatile uint32_t CHEXT_7; /* CHEXT_7 */
volatile uint32_t NXLA_7; /* NXLA_7 */
volatile uint32_t CRLA_7; /* CRLA_7 */
/* end of struct st_dmac_n */
volatile uint8_t dummy187[256]; /* */
/* start of struct st_dmaccommon_n */
volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */
volatile uint8_t dummy188[12]; /* */
volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */
volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */
volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */
volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */
volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */
/* end of struct st_dmaccommon_n */
volatile uint8_t dummy189[220]; /* */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_8; /* N0SA_8 */
volatile uint32_t N0DA_8; /* N0DA_8 */
volatile uint32_t N0TB_8; /* N0TB_8 */
volatile uint32_t N1SA_8; /* N1SA_8 */
volatile uint32_t N1DA_8; /* N1DA_8 */
volatile uint32_t N1TB_8; /* N1TB_8 */
volatile uint32_t CRSA_8; /* CRSA_8 */
volatile uint32_t CRDA_8; /* CRDA_8 */
volatile uint32_t CRTB_8; /* CRTB_8 */
volatile uint32_t CHSTAT_8; /* CHSTAT_8 */
volatile uint32_t CHCTRL_8; /* CHCTRL_8 */
volatile uint32_t CHCFG_8; /* CHCFG_8 */
volatile uint32_t CHITVL_8; /* CHITVL_8 */
volatile uint32_t CHEXT_8; /* CHEXT_8 */
volatile uint32_t NXLA_8; /* NXLA_8 */
volatile uint32_t CRLA_8; /* CRLA_8 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_9; /* N0SA_9 */
volatile uint32_t N0DA_9; /* N0DA_9 */
volatile uint32_t N0TB_9; /* N0TB_9 */
volatile uint32_t N1SA_9; /* N1SA_9 */
volatile uint32_t N1DA_9; /* N1DA_9 */
volatile uint32_t N1TB_9; /* N1TB_9 */
volatile uint32_t CRSA_9; /* CRSA_9 */
volatile uint32_t CRDA_9; /* CRDA_9 */
volatile uint32_t CRTB_9; /* CRTB_9 */
volatile uint32_t CHSTAT_9; /* CHSTAT_9 */
volatile uint32_t CHCTRL_9; /* CHCTRL_9 */
volatile uint32_t CHCFG_9; /* CHCFG_9 */
volatile uint32_t CHITVL_9; /* CHITVL_9 */
volatile uint32_t CHEXT_9; /* CHEXT_9 */
volatile uint32_t NXLA_9; /* NXLA_9 */
volatile uint32_t CRLA_9; /* CRLA_9 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_10; /* N0SA_10 */
volatile uint32_t N0DA_10; /* N0DA_10 */
volatile uint32_t N0TB_10; /* N0TB_10 */
volatile uint32_t N1SA_10; /* N1SA_10 */
volatile uint32_t N1DA_10; /* N1DA_10 */
volatile uint32_t N1TB_10; /* N1TB_10 */
volatile uint32_t CRSA_10; /* CRSA_10 */
volatile uint32_t CRDA_10; /* CRDA_10 */
volatile uint32_t CRTB_10; /* CRTB_10 */
volatile uint32_t CHSTAT_10; /* CHSTAT_10 */
volatile uint32_t CHCTRL_10; /* CHCTRL_10 */
volatile uint32_t CHCFG_10; /* CHCFG_10 */
volatile uint32_t CHITVL_10; /* CHITVL_10 */
volatile uint32_t CHEXT_10; /* CHEXT_10 */
volatile uint32_t NXLA_10; /* NXLA_10 */
volatile uint32_t CRLA_10; /* CRLA_10 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_11; /* N0SA_11 */
volatile uint32_t N0DA_11; /* N0DA_11 */
volatile uint32_t N0TB_11; /* N0TB_11 */
volatile uint32_t N1SA_11; /* N1SA_11 */
volatile uint32_t N1DA_11; /* N1DA_11 */
volatile uint32_t N1TB_11; /* N1TB_11 */
volatile uint32_t CRSA_11; /* CRSA_11 */
volatile uint32_t CRDA_11; /* CRDA_11 */
volatile uint32_t CRTB_11; /* CRTB_11 */
volatile uint32_t CHSTAT_11; /* CHSTAT_11 */
volatile uint32_t CHCTRL_11; /* CHCTRL_11 */
volatile uint32_t CHCFG_11; /* CHCFG_11 */
volatile uint32_t CHITVL_11; /* CHITVL_11 */
volatile uint32_t CHEXT_11; /* CHEXT_11 */
volatile uint32_t NXLA_11; /* NXLA_11 */
volatile uint32_t CRLA_11; /* CRLA_11 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_12; /* N0SA_12 */
volatile uint32_t N0DA_12; /* N0DA_12 */
volatile uint32_t N0TB_12; /* N0TB_12 */
volatile uint32_t N1SA_12; /* N1SA_12 */
volatile uint32_t N1DA_12; /* N1DA_12 */
volatile uint32_t N1TB_12; /* N1TB_12 */
volatile uint32_t CRSA_12; /* CRSA_12 */
volatile uint32_t CRDA_12; /* CRDA_12 */
volatile uint32_t CRTB_12; /* CRTB_12 */
volatile uint32_t CHSTAT_12; /* CHSTAT_12 */
volatile uint32_t CHCTRL_12; /* CHCTRL_12 */
volatile uint32_t CHCFG_12; /* CHCFG_12 */
volatile uint32_t CHITVL_12; /* CHITVL_12 */
volatile uint32_t CHEXT_12; /* CHEXT_12 */
volatile uint32_t NXLA_12; /* NXLA_12 */
volatile uint32_t CRLA_12; /* CRLA_12 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_13; /* N0SA_13 */
volatile uint32_t N0DA_13; /* N0DA_13 */
volatile uint32_t N0TB_13; /* N0TB_13 */
volatile uint32_t N1SA_13; /* N1SA_13 */
volatile uint32_t N1DA_13; /* N1DA_13 */
volatile uint32_t N1TB_13; /* N1TB_13 */
volatile uint32_t CRSA_13; /* CRSA_13 */
volatile uint32_t CRDA_13; /* CRDA_13 */
volatile uint32_t CRTB_13; /* CRTB_13 */
volatile uint32_t CHSTAT_13; /* CHSTAT_13 */
volatile uint32_t CHCTRL_13; /* CHCTRL_13 */
volatile uint32_t CHCFG_13; /* CHCFG_13 */
volatile uint32_t CHITVL_13; /* CHITVL_13 */
volatile uint32_t CHEXT_13; /* CHEXT_13 */
volatile uint32_t NXLA_13; /* NXLA_13 */
volatile uint32_t CRLA_13; /* CRLA_13 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_14; /* N0SA_14 */
volatile uint32_t N0DA_14; /* N0DA_14 */
volatile uint32_t N0TB_14; /* N0TB_14 */
volatile uint32_t N1SA_14; /* N1SA_14 */
volatile uint32_t N1DA_14; /* N1DA_14 */
volatile uint32_t N1TB_14; /* N1TB_14 */
volatile uint32_t CRSA_14; /* CRSA_14 */
volatile uint32_t CRDA_14; /* CRDA_14 */
volatile uint32_t CRTB_14; /* CRTB_14 */
volatile uint32_t CHSTAT_14; /* CHSTAT_14 */
volatile uint32_t CHCTRL_14; /* CHCTRL_14 */
volatile uint32_t CHCFG_14; /* CHCFG_14 */
volatile uint32_t CHITVL_14; /* CHITVL_14 */
volatile uint32_t CHEXT_14; /* CHEXT_14 */
volatile uint32_t NXLA_14; /* NXLA_14 */
volatile uint32_t CRLA_14; /* CRLA_14 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_15; /* N0SA_15 */
volatile uint32_t N0DA_15; /* N0DA_15 */
volatile uint32_t N0TB_15; /* N0TB_15 */
volatile uint32_t N1SA_15; /* N1SA_15 */
volatile uint32_t N1DA_15; /* N1DA_15 */
volatile uint32_t N1TB_15; /* N1TB_15 */
volatile uint32_t CRSA_15; /* CRSA_15 */
volatile uint32_t CRDA_15; /* CRDA_15 */
volatile uint32_t CRTB_15; /* CRTB_15 */
volatile uint32_t CHSTAT_15; /* CHSTAT_15 */
volatile uint32_t CHCTRL_15; /* CHCTRL_15 */
volatile uint32_t CHCFG_15; /* CHCFG_15 */
volatile uint32_t CHITVL_15; /* CHITVL_15 */
volatile uint32_t CHEXT_15; /* CHEXT_15 */
volatile uint32_t NXLA_15; /* NXLA_15 */
volatile uint32_t CRLA_15; /* CRLA_15 */
/* end of struct st_dmac_n */
volatile uint8_t dummy190[256]; /* */
/* start of struct st_dmaccommon_n */
volatile uint32_t DCTRL_8_15; /* DCTRL_8_15 */
volatile uint8_t dummy191[12]; /* */
volatile uint32_t DSTAT_EN_8_15; /* DSTAT_EN_8_15 */
volatile uint32_t DSTAT_ER_8_15; /* DSTAT_ER_8_15 */
volatile uint32_t DSTAT_END_8_15; /* DSTAT_END_8_15 */
volatile uint32_t DSTAT_TC_8_15; /* DSTAT_TC_8_15 */
volatile uint32_t DSTAT_SUS_8_15; /* DSTAT_SUS_8_15 */
/* end of struct st_dmaccommon_n */
volatile uint8_t dummy192[350095580]; /* */
volatile uint32_t DMARS0; /* DMARS0 */
volatile uint32_t DMARS1; /* DMARS1 */
volatile uint32_t DMARS2; /* DMARS2 */
volatile uint32_t DMARS3; /* DMARS3 */
volatile uint32_t DMARS4; /* DMARS4 */
volatile uint32_t DMARS5; /* DMARS5 */
volatile uint32_t DMARS6; /* DMARS6 */
volatile uint32_t DMARS7; /* DMARS7 */
};
struct st_dmaccommon_n
{
volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */
volatile uint8_t dummy1[12]; /* */
volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */
volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */
volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */
volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */
volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */
};
struct st_dmac_n
{
volatile uint32_t N0SA_n; /* N0SA_n */
volatile uint32_t N0DA_n; /* N0DA_n */
volatile uint32_t N0TB_n; /* N0TB_n */
volatile uint32_t N1SA_n; /* N1SA_n */
volatile uint32_t N1DA_n; /* N1DA_n */
volatile uint32_t N1TB_n; /* N1TB_n */
volatile uint32_t CRSA_n; /* CRSA_n */
volatile uint32_t CRDA_n; /* CRDA_n */
volatile uint32_t CRTB_n; /* CRTB_n */
volatile uint32_t CHSTAT_n; /* CHSTAT_n */
volatile uint32_t CHCTRL_n; /* CHCTRL_n */
volatile uint32_t CHCFG_n; /* CHCFG_n */
volatile uint32_t CHITVL_n; /* CHITVL_n */
volatile uint32_t CHEXT_n; /* CHEXT_n */
volatile uint32_t NXLA_n; /* NXLA_n */
volatile uint32_t CRLA_n; /* CRLA_n */
};
#define DMAC (*(struct st_dmac *)0xE8200000uL) /* DMAC */
/* Start of channnel array defines of DMAC */
/* Channnel array defines of DMACn */
/*(Sample) value = DMACn[ channel ]->N0SA_n; */
#define DMACn_COUNT 16
#define DMACn_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \
&DMAC8, &DMAC9, &DMAC10, &DMAC11, &DMAC12, &DMAC13, &DMAC14, &DMAC15 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define DMAC0 (*(struct st_dmac_n *)&DMAC.N0SA_0) /* DMAC0 */
#define DMAC1 (*(struct st_dmac_n *)&DMAC.N0SA_1) /* DMAC1 */
#define DMAC2 (*(struct st_dmac_n *)&DMAC.N0SA_2) /* DMAC2 */
#define DMAC3 (*(struct st_dmac_n *)&DMAC.N0SA_3) /* DMAC3 */
#define DMAC4 (*(struct st_dmac_n *)&DMAC.N0SA_4) /* DMAC4 */
#define DMAC5 (*(struct st_dmac_n *)&DMAC.N0SA_5) /* DMAC5 */
#define DMAC6 (*(struct st_dmac_n *)&DMAC.N0SA_6) /* DMAC6 */
#define DMAC7 (*(struct st_dmac_n *)&DMAC.N0SA_7) /* DMAC7 */
#define DMAC8 (*(struct st_dmac_n *)&DMAC.N0SA_8) /* DMAC8 */
#define DMAC9 (*(struct st_dmac_n *)&DMAC.N0SA_9) /* DMAC9 */
#define DMAC10 (*(struct st_dmac_n *)&DMAC.N0SA_10) /* DMAC10 */
#define DMAC11 (*(struct st_dmac_n *)&DMAC.N0SA_11) /* DMAC11 */
#define DMAC12 (*(struct st_dmac_n *)&DMAC.N0SA_12) /* DMAC12 */
#define DMAC13 (*(struct st_dmac_n *)&DMAC.N0SA_13) /* DMAC13 */
#define DMAC14 (*(struct st_dmac_n *)&DMAC.N0SA_14) /* DMAC14 */
#define DMAC15 (*(struct st_dmac_n *)&DMAC.N0SA_15) /* DMAC15 */
/* Channnel array defines of DMACnn */
/*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */
#define DMACnn_COUNT 2
#define DMACnn_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&DMAC07, &DMAC815 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define DMAC07 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7) /* DMAC07 */
#define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15) /* DMAC815 */
/* Channnel array defines of DMACmm */
/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */
struct st_dmars_mm
{
uint32_t DMARS; /* DMARS */
};
#define DMACmm_COUNT 8
#define DMACmm_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define DMAC01 (*(struct st_dmars_mm *)&DMAC.DMARS0) /* DMAC0-1 */
#define DMAC23 (*(struct st_dmars_mm *)&DMAC.DMARS1) /* DMAC2-3 */
#define DMAC45 (*(struct st_dmars_mm *)&DMAC.DMARS2) /* DMAC4-5 */
#define DMAC67 (*(struct st_dmars_mm *)&DMAC.DMARS3) /* DMAC6-7 */
#define DMAC89 (*(struct st_dmars_mm *)&DMAC.DMARS4) /* DMAC8-9 */
#define DMAC1011 (*(struct st_dmars_mm *)&DMAC.DMARS5) /* DMAC10-11 */
#define DMAC1213 (*(struct st_dmars_mm *)&DMAC.DMARS6) /* DMAC12-13 */
#define DMAC1415 (*(struct st_dmars_mm *)&DMAC.DMARS7) /* DMAC14-15 */
/* End of channnel array defines of DMAC */
#define DMACN0SA_0 DMAC.N0SA_0
#define DMACN0DA_0 DMAC.N0DA_0
#define DMACN0TB_0 DMAC.N0TB_0
#define DMACN1SA_0 DMAC.N1SA_0
#define DMACN1DA_0 DMAC.N1DA_0
#define DMACN1TB_0 DMAC.N1TB_0
#define DMACCRSA_0 DMAC.CRSA_0
#define DMACCRDA_0 DMAC.CRDA_0
#define DMACCRTB_0 DMAC.CRTB_0
#define DMACCHSTAT_0 DMAC.CHSTAT_0
#define DMACCHCTRL_0 DMAC.CHCTRL_0
#define DMACCHCFG_0 DMAC.CHCFG_0
#define DMACCHITVL_0 DMAC.CHITVL_0
#define DMACCHEXT_0 DMAC.CHEXT_0
#define DMACNXLA_0 DMAC.NXLA_0
#define DMACCRLA_0 DMAC.CRLA_0
#define DMACN0SA_1 DMAC.N0SA_1
#define DMACN0DA_1 DMAC.N0DA_1
#define DMACN0TB_1 DMAC.N0TB_1
#define DMACN1SA_1 DMAC.N1SA_1
#define DMACN1DA_1 DMAC.N1DA_1
#define DMACN1TB_1 DMAC.N1TB_1
#define DMACCRSA_1 DMAC.CRSA_1
#define DMACCRDA_1 DMAC.CRDA_1
#define DMACCRTB_1 DMAC.CRTB_1
#define DMACCHSTAT_1 DMAC.CHSTAT_1
#define DMACCHCTRL_1 DMAC.CHCTRL_1
#define DMACCHCFG_1 DMAC.CHCFG_1
#define DMACCHITVL_1 DMAC.CHITVL_1
#define DMACCHEXT_1 DMAC.CHEXT_1
#define DMACNXLA_1 DMAC.NXLA_1
#define DMACCRLA_1 DMAC.CRLA_1
#define DMACN0SA_2 DMAC.N0SA_2
#define DMACN0DA_2 DMAC.N0DA_2
#define DMACN0TB_2 DMAC.N0TB_2
#define DMACN1SA_2 DMAC.N1SA_2
#define DMACN1DA_2 DMAC.N1DA_2
#define DMACN1TB_2 DMAC.N1TB_2
#define DMACCRSA_2 DMAC.CRSA_2
#define DMACCRDA_2 DMAC.CRDA_2
#define DMACCRTB_2 DMAC.CRTB_2
#define DMACCHSTAT_2 DMAC.CHSTAT_2
#define DMACCHCTRL_2 DMAC.CHCTRL_2
#define DMACCHCFG_2 DMAC.CHCFG_2
#define DMACCHITVL_2 DMAC.CHITVL_2
#define DMACCHEXT_2 DMAC.CHEXT_2
#define DMACNXLA_2 DMAC.NXLA_2
#define DMACCRLA_2 DMAC.CRLA_2
#define DMACN0SA_3 DMAC.N0SA_3
#define DMACN0DA_3 DMAC.N0DA_3
#define DMACN0TB_3 DMAC.N0TB_3
#define DMACN1SA_3 DMAC.N1SA_3
#define DMACN1DA_3 DMAC.N1DA_3
#define DMACN1TB_3 DMAC.N1TB_3
#define DMACCRSA_3 DMAC.CRSA_3
#define DMACCRDA_3 DMAC.CRDA_3
#define DMACCRTB_3 DMAC.CRTB_3
#define DMACCHSTAT_3 DMAC.CHSTAT_3
#define DMACCHCTRL_3 DMAC.CHCTRL_3
#define DMACCHCFG_3 DMAC.CHCFG_3
#define DMACCHITVL_3 DMAC.CHITVL_3
#define DMACCHEXT_3 DMAC.CHEXT_3
#define DMACNXLA_3 DMAC.NXLA_3
#define DMACCRLA_3 DMAC.CRLA_3
#define DMACN0SA_4 DMAC.N0SA_4
#define DMACN0DA_4 DMAC.N0DA_4
#define DMACN0TB_4 DMAC.N0TB_4
#define DMACN1SA_4 DMAC.N1SA_4
#define DMACN1DA_4 DMAC.N1DA_4
#define DMACN1TB_4 DMAC.N1TB_4
#define DMACCRSA_4 DMAC.CRSA_4
#define DMACCRDA_4 DMAC.CRDA_4
#define DMACCRTB_4 DMAC.CRTB_4
#define DMACCHSTAT_4 DMAC.CHSTAT_4
#define DMACCHCTRL_4 DMAC.CHCTRL_4
#define DMACCHCFG_4 DMAC.CHCFG_4
#define DMACCHITVL_4 DMAC.CHITVL_4
#define DMACCHEXT_4 DMAC.CHEXT_4
#define DMACNXLA_4 DMAC.NXLA_4
#define DMACCRLA_4 DMAC.CRLA_4
#define DMACN0SA_5 DMAC.N0SA_5
#define DMACN0DA_5 DMAC.N0DA_5
#define DMACN0TB_5 DMAC.N0TB_5
#define DMACN1SA_5 DMAC.N1SA_5
#define DMACN1DA_5 DMAC.N1DA_5
#define DMACN1TB_5 DMAC.N1TB_5
#define DMACCRSA_5 DMAC.CRSA_5
#define DMACCRDA_5 DMAC.CRDA_5
#define DMACCRTB_5 DMAC.CRTB_5
#define DMACCHSTAT_5 DMAC.CHSTAT_5
#define DMACCHCTRL_5 DMAC.CHCTRL_5
#define DMACCHCFG_5 DMAC.CHCFG_5
#define DMACCHITVL_5 DMAC.CHITVL_5
#define DMACCHEXT_5 DMAC.CHEXT_5
#define DMACNXLA_5 DMAC.NXLA_5
#define DMACCRLA_5 DMAC.CRLA_5
#define DMACN0SA_6 DMAC.N0SA_6
#define DMACN0DA_6 DMAC.N0DA_6
#define DMACN0TB_6 DMAC.N0TB_6
#define DMACN1SA_6 DMAC.N1SA_6
#define DMACN1DA_6 DMAC.N1DA_6
#define DMACN1TB_6 DMAC.N1TB_6
#define DMACCRSA_6 DMAC.CRSA_6
#define DMACCRDA_6 DMAC.CRDA_6
#define DMACCRTB_6 DMAC.CRTB_6
#define DMACCHSTAT_6 DMAC.CHSTAT_6
#define DMACCHCTRL_6 DMAC.CHCTRL_6
#define DMACCHCFG_6 DMAC.CHCFG_6
#define DMACCHITVL_6 DMAC.CHITVL_6
#define DMACCHEXT_6 DMAC.CHEXT_6
#define DMACNXLA_6 DMAC.NXLA_6
#define DMACCRLA_6 DMAC.CRLA_6
#define DMACN0SA_7 DMAC.N0SA_7
#define DMACN0DA_7 DMAC.N0DA_7
#define DMACN0TB_7 DMAC.N0TB_7
#define DMACN1SA_7 DMAC.N1SA_7
#define DMACN1DA_7 DMAC.N1DA_7
#define DMACN1TB_7 DMAC.N1TB_7
#define DMACCRSA_7 DMAC.CRSA_7
#define DMACCRDA_7 DMAC.CRDA_7
#define DMACCRTB_7 DMAC.CRTB_7
#define DMACCHSTAT_7 DMAC.CHSTAT_7
#define DMACCHCTRL_7 DMAC.CHCTRL_7
#define DMACCHCFG_7 DMAC.CHCFG_7
#define DMACCHITVL_7 DMAC.CHITVL_7
#define DMACCHEXT_7 DMAC.CHEXT_7
#define DMACNXLA_7 DMAC.NXLA_7
#define DMACCRLA_7 DMAC.CRLA_7
#define DMACDCTRL_0_7 DMAC.DCTRL_0_7
#define DMACDSTAT_EN_0_7 DMAC.DSTAT_EN_0_7
#define DMACDSTAT_ER_0_7 DMAC.DSTAT_ER_0_7
#define DMACDSTAT_END_0_7 DMAC.DSTAT_END_0_7
#define DMACDSTAT_TC_0_7 DMAC.DSTAT_TC_0_7
#define DMACDSTAT_SUS_0_7 DMAC.DSTAT_SUS_0_7
#define DMACN0SA_8 DMAC.N0SA_8
#define DMACN0DA_8 DMAC.N0DA_8
#define DMACN0TB_8 DMAC.N0TB_8
#define DMACN1SA_8 DMAC.N1SA_8
#define DMACN1DA_8 DMAC.N1DA_8
#define DMACN1TB_8 DMAC.N1TB_8
#define DMACCRSA_8 DMAC.CRSA_8
#define DMACCRDA_8 DMAC.CRDA_8
#define DMACCRTB_8 DMAC.CRTB_8
#define DMACCHSTAT_8 DMAC.CHSTAT_8
#define DMACCHCTRL_8 DMAC.CHCTRL_8
#define DMACCHCFG_8 DMAC.CHCFG_8
#define DMACCHITVL_8 DMAC.CHITVL_8
#define DMACCHEXT_8 DMAC.CHEXT_8
#define DMACNXLA_8 DMAC.NXLA_8
#define DMACCRLA_8 DMAC.CRLA_8
#define DMACN0SA_9 DMAC.N0SA_9
#define DMACN0DA_9 DMAC.N0DA_9
#define DMACN0TB_9 DMAC.N0TB_9
#define DMACN1SA_9 DMAC.N1SA_9
#define DMACN1DA_9 DMAC.N1DA_9
#define DMACN1TB_9 DMAC.N1TB_9
#define DMACCRSA_9 DMAC.CRSA_9
#define DMACCRDA_9 DMAC.CRDA_9
#define DMACCRTB_9 DMAC.CRTB_9
#define DMACCHSTAT_9 DMAC.CHSTAT_9
#define DMACCHCTRL_9 DMAC.CHCTRL_9
#define DMACCHCFG_9 DMAC.CHCFG_9
#define DMACCHITVL_9 DMAC.CHITVL_9
#define DMACCHEXT_9 DMAC.CHEXT_9
#define DMACNXLA_9 DMAC.NXLA_9
#define DMACCRLA_9 DMAC.CRLA_9
#define DMACN0SA_10 DMAC.N0SA_10
#define DMACN0DA_10 DMAC.N0DA_10
#define DMACN0TB_10 DMAC.N0TB_10
#define DMACN1SA_10 DMAC.N1SA_10
#define DMACN1DA_10 DMAC.N1DA_10
#define DMACN1TB_10 DMAC.N1TB_10
#define DMACCRSA_10 DMAC.CRSA_10
#define DMACCRDA_10 DMAC.CRDA_10
#define DMACCRTB_10 DMAC.CRTB_10
#define DMACCHSTAT_10 DMAC.CHSTAT_10
#define DMACCHCTRL_10 DMAC.CHCTRL_10
#define DMACCHCFG_10 DMAC.CHCFG_10
#define DMACCHITVL_10 DMAC.CHITVL_10
#define DMACCHEXT_10 DMAC.CHEXT_10
#define DMACNXLA_10 DMAC.NXLA_10
#define DMACCRLA_10 DMAC.CRLA_10
#define DMACN0SA_11 DMAC.N0SA_11
#define DMACN0DA_11 DMAC.N0DA_11
#define DMACN0TB_11 DMAC.N0TB_11
#define DMACN1SA_11 DMAC.N1SA_11
#define DMACN1DA_11 DMAC.N1DA_11
#define DMACN1TB_11 DMAC.N1TB_11
#define DMACCRSA_11 DMAC.CRSA_11
#define DMACCRDA_11 DMAC.CRDA_11
#define DMACCRTB_11 DMAC.CRTB_11
#define DMACCHSTAT_11 DMAC.CHSTAT_11
#define DMACCHCTRL_11 DMAC.CHCTRL_11
#define DMACCHCFG_11 DMAC.CHCFG_11
#define DMACCHITVL_11 DMAC.CHITVL_11
#define DMACCHEXT_11 DMAC.CHEXT_11
#define DMACNXLA_11 DMAC.NXLA_11
#define DMACCRLA_11 DMAC.CRLA_11
#define DMACN0SA_12 DMAC.N0SA_12
#define DMACN0DA_12 DMAC.N0DA_12
#define DMACN0TB_12 DMAC.N0TB_12
#define DMACN1SA_12 DMAC.N1SA_12
#define DMACN1DA_12 DMAC.N1DA_12
#define DMACN1TB_12 DMAC.N1TB_12
#define DMACCRSA_12 DMAC.CRSA_12
#define DMACCRDA_12 DMAC.CRDA_12
#define DMACCRTB_12 DMAC.CRTB_12
#define DMACCHSTAT_12 DMAC.CHSTAT_12
#define DMACCHCTRL_12 DMAC.CHCTRL_12
#define DMACCHCFG_12 DMAC.CHCFG_12
#define DMACCHITVL_12 DMAC.CHITVL_12
#define DMACCHEXT_12 DMAC.CHEXT_12
#define DMACNXLA_12 DMAC.NXLA_12
#define DMACCRLA_12 DMAC.CRLA_12
#define DMACN0SA_13 DMAC.N0SA_13
#define DMACN0DA_13 DMAC.N0DA_13
#define DMACN0TB_13 DMAC.N0TB_13
#define DMACN1SA_13 DMAC.N1SA_13
#define DMACN1DA_13 DMAC.N1DA_13
#define DMACN1TB_13 DMAC.N1TB_13
#define DMACCRSA_13 DMAC.CRSA_13
#define DMACCRDA_13 DMAC.CRDA_13
#define DMACCRTB_13 DMAC.CRTB_13
#define DMACCHSTAT_13 DMAC.CHSTAT_13
#define DMACCHCTRL_13 DMAC.CHCTRL_13
#define DMACCHCFG_13 DMAC.CHCFG_13
#define DMACCHITVL_13 DMAC.CHITVL_13
#define DMACCHEXT_13 DMAC.CHEXT_13
#define DMACNXLA_13 DMAC.NXLA_13
#define DMACCRLA_13 DMAC.CRLA_13
#define DMACN0SA_14 DMAC.N0SA_14
#define DMACN0DA_14 DMAC.N0DA_14
#define DMACN0TB_14 DMAC.N0TB_14
#define DMACN1SA_14 DMAC.N1SA_14
#define DMACN1DA_14 DMAC.N1DA_14
#define DMACN1TB_14 DMAC.N1TB_14
#define DMACCRSA_14 DMAC.CRSA_14
#define DMACCRDA_14 DMAC.CRDA_14
#define DMACCRTB_14 DMAC.CRTB_14
#define DMACCHSTAT_14 DMAC.CHSTAT_14
#define DMACCHCTRL_14 DMAC.CHCTRL_14
#define DMACCHCFG_14 DMAC.CHCFG_14
#define DMACCHITVL_14 DMAC.CHITVL_14
#define DMACCHEXT_14 DMAC.CHEXT_14
#define DMACNXLA_14 DMAC.NXLA_14
#define DMACCRLA_14 DMAC.CRLA_14
#define DMACN0SA_15 DMAC.N0SA_15
#define DMACN0DA_15 DMAC.N0DA_15
#define DMACN0TB_15 DMAC.N0TB_15
#define DMACN1SA_15 DMAC.N1SA_15
#define DMACN1DA_15 DMAC.N1DA_15
#define DMACN1TB_15 DMAC.N1TB_15
#define DMACCRSA_15 DMAC.CRSA_15
#define DMACCRDA_15 DMAC.CRDA_15
#define DMACCRTB_15 DMAC.CRTB_15
#define DMACCHSTAT_15 DMAC.CHSTAT_15
#define DMACCHCTRL_15 DMAC.CHCTRL_15
#define DMACCHCFG_15 DMAC.CHCFG_15
#define DMACCHITVL_15 DMAC.CHITVL_15
#define DMACCHEXT_15 DMAC.CHEXT_15
#define DMACNXLA_15 DMAC.NXLA_15
#define DMACCRLA_15 DMAC.CRLA_15
#define DMACDCTRL_8_15 DMAC.DCTRL_8_15
#define DMACDSTAT_EN_8_15 DMAC.DSTAT_EN_8_15
#define DMACDSTAT_ER_8_15 DMAC.DSTAT_ER_8_15
#define DMACDSTAT_END_8_15 DMAC.DSTAT_END_8_15
#define DMACDSTAT_TC_8_15 DMAC.DSTAT_TC_8_15
#define DMACDSTAT_SUS_8_15 DMAC.DSTAT_SUS_8_15
#define DMACDMARS0 DMAC.DMARS0
#define DMACDMARS1 DMAC.DMARS1
#define DMACDMARS2 DMAC.DMARS2
#define DMACDMARS3 DMAC.DMARS3
#define DMACDMARS4 DMAC.DMARS4
#define DMACDMARS5 DMAC.DMARS5
#define DMACDMARS6 DMAC.DMARS6
#define DMACDMARS7 DMAC.DMARS7
/* <-SEC M1.10.1 */
/* <-QAC 0639 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : dvdec_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef DVDEC_IODEFINE_H
#define DVDEC_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_dvdec
{ /* DVDEC */
volatile uint16_t ADCCR1; /* ADCCR1 */
volatile uint8_t dummy1[4]; /* */
#define DVDEC_TGCRn_COUNT 3
volatile uint16_t TGCR1; /* TGCR1 */
volatile uint16_t TGCR2; /* TGCR2 */
volatile uint16_t TGCR3; /* TGCR3 */
volatile uint8_t dummy2[6]; /* */
#define DVDEC_SYNSCRn_COUNT 5
volatile uint16_t SYNSCR1; /* SYNSCR1 */
volatile uint16_t SYNSCR2; /* SYNSCR2 */
volatile uint16_t SYNSCR3; /* SYNSCR3 */
volatile uint16_t SYNSCR4; /* SYNSCR4 */
volatile uint16_t SYNSCR5; /* SYNSCR5 */
#define DVDEC_HAFCCRn_COUNT 3
volatile uint16_t HAFCCR1; /* HAFCCR1 */
volatile uint16_t HAFCCR2; /* HAFCCR2 */
volatile uint16_t HAFCCR3; /* HAFCCR3 */
volatile uint16_t VCDWCR1; /* VCDWCR1 */
volatile uint8_t dummy3[4]; /* */
#define DVDEC_DCPCRn_COUNT 8
volatile uint16_t DCPCR1; /* DCPCR1 */
volatile uint16_t DCPCR2; /* DCPCR2 */
volatile uint16_t DCPCR3; /* DCPCR3 */
volatile uint16_t DCPCR4; /* DCPCR4 */
volatile uint16_t DCPCR5; /* DCPCR5 */
volatile uint16_t DCPCR6; /* DCPCR6 */
volatile uint16_t DCPCR7; /* DCPCR7 */
volatile uint16_t DCPCR8; /* DCPCR8 */
volatile uint16_t NSDCR; /* NSDCR */
volatile uint16_t BTLCR; /* BTLCR */
volatile uint16_t BTGPCR; /* BTGPCR */
#define DVDEC_ACCCRn_COUNT 3
volatile uint16_t ACCCR1; /* ACCCR1 */
volatile uint16_t ACCCR2; /* ACCCR2 */
volatile uint16_t ACCCR3; /* ACCCR3 */
volatile uint16_t TINTCR; /* TINTCR */
volatile uint16_t YCDCR; /* YCDCR */
#define DVDEC_AGCCRn_COUNT 2
volatile uint16_t AGCCR1; /* AGCCR1 */
volatile uint16_t AGCCR2; /* AGCCR2 */
volatile uint16_t PKLIMITCR; /* PKLIMITCR */
#define DVDEC_RGORCRn_COUNT 7
volatile uint16_t RGORCR1; /* RGORCR1 */
volatile uint16_t RGORCR2; /* RGORCR2 */
volatile uint16_t RGORCR3; /* RGORCR3 */
volatile uint16_t RGORCR4; /* RGORCR4 */
volatile uint16_t RGORCR5; /* RGORCR5 */
volatile uint16_t RGORCR6; /* RGORCR6 */
volatile uint16_t RGORCR7; /* RGORCR7 */
volatile uint8_t dummy4[24]; /* */
volatile uint16_t AFCPFCR; /* AFCPFCR */
volatile uint16_t RUPDCR; /* RUPDCR */
volatile uint16_t VSYNCSR; /* VSYNCSR */
volatile uint16_t HSYNCSR; /* HSYNCSR */
#define DVDEC_DCPSRn_COUNT 2
volatile uint16_t DCPSR1; /* DCPSR1 */
volatile uint16_t DCPSR2; /* DCPSR2 */
volatile uint8_t dummy5[4]; /* */
volatile uint16_t NSDSR; /* NSDSR */
#define DVDEC_CROMASRn_COUNT 2
volatile uint16_t CROMASR1; /* CROMASR1 */
volatile uint16_t CROMASR2; /* CROMASR2 */
volatile uint16_t SYNCSSR; /* SYNCSSR */
#define DVDEC_AGCCSRn_COUNT 2
volatile uint16_t AGCCSR1; /* AGCCSR1 */
volatile uint16_t AGCCSR2; /* AGCCSR2 */
volatile uint8_t dummy6[108]; /* */
#define DVDEC_YCSCRn_COUNT 7
volatile uint16_t YCSCR3; /* YCSCR3 */
volatile uint16_t YCSCR4; /* YCSCR4 */
volatile uint16_t YCSCR5; /* YCSCR5 */
volatile uint16_t YCSCR6; /* YCSCR6 */
volatile uint16_t YCSCR7; /* YCSCR7 */
volatile uint16_t YCSCR8; /* YCSCR8 */
volatile uint16_t YCSCR9; /* YCSCR9 */
volatile uint8_t dummy7[2]; /* */
volatile uint16_t YCSCR11; /* YCSCR11 */
volatile uint16_t YCSCR12; /* YCSCR12 */
volatile uint8_t dummy8[104]; /* */
volatile uint16_t DCPCR9; /* DCPCR9 */
volatile uint8_t dummy9[16]; /* */
#define DVDEC_YCTWA_Fn_COUNT 9
volatile uint16_t YCTWA_F0; /* YCTWA_F0 */
volatile uint16_t YCTWA_F1; /* YCTWA_F1 */
volatile uint16_t YCTWA_F2; /* YCTWA_F2 */
volatile uint16_t YCTWA_F3; /* YCTWA_F3 */
volatile uint16_t YCTWA_F4; /* YCTWA_F4 */
volatile uint16_t YCTWA_F5; /* YCTWA_F5 */
volatile uint16_t YCTWA_F6; /* YCTWA_F6 */
volatile uint16_t YCTWA_F7; /* YCTWA_F7 */
volatile uint16_t YCTWA_F8; /* YCTWA_F8 */
#define DVDEC_YCTWB_Fn_COUNT 9
volatile uint16_t YCTWB_F0; /* YCTWB_F0 */
volatile uint16_t YCTWB_F1; /* YCTWB_F1 */
volatile uint16_t YCTWB_F2; /* YCTWB_F2 */
volatile uint16_t YCTWB_F3; /* YCTWB_F3 */
volatile uint16_t YCTWB_F4; /* YCTWB_F4 */
volatile uint16_t YCTWB_F5; /* YCTWB_F5 */
volatile uint16_t YCTWB_F6; /* YCTWB_F6 */
volatile uint16_t YCTWB_F7; /* YCTWB_F7 */
volatile uint16_t YCTWB_F8; /* YCTWB_F8 */
#define DVDEC_YCTNA_Fn_COUNT 9
volatile uint16_t YCTNA_F0; /* YCTNA_F0 */
volatile uint16_t YCTNA_F1; /* YCTNA_F1 */
volatile uint16_t YCTNA_F2; /* YCTNA_F2 */
volatile uint16_t YCTNA_F3; /* YCTNA_F3 */
volatile uint16_t YCTNA_F4; /* YCTNA_F4 */
volatile uint16_t YCTNA_F5; /* YCTNA_F5 */
volatile uint16_t YCTNA_F6; /* YCTNA_F6 */
volatile uint16_t YCTNA_F7; /* YCTNA_F7 */
volatile uint16_t YCTNA_F8; /* YCTNA_F8 */
#define DVDEC_YCTNB_Fn_COUNT 9
volatile uint16_t YCTNB_F0; /* YCTNB_F0 */
volatile uint16_t YCTNB_F1; /* YCTNB_F1 */
volatile uint16_t YCTNB_F2; /* YCTNB_F2 */
volatile uint16_t YCTNB_F3; /* YCTNB_F3 */
volatile uint16_t YCTNB_F4; /* YCTNB_F4 */
volatile uint16_t YCTNB_F5; /* YCTNB_F5 */
volatile uint16_t YCTNB_F6; /* YCTNB_F6 */
volatile uint16_t YCTNB_F7; /* YCTNB_F7 */
volatile uint16_t YCTNB_F8; /* YCTNB_F8 */
volatile uint8_t dummy10[38]; /* */
volatile uint16_t YGAINCR; /* YGAINCR */
volatile uint16_t CBGAINCR; /* CBGAINCR */
volatile uint16_t CRGAINCR; /* CRGAINCR */
volatile uint8_t dummy11[122]; /* */
volatile uint16_t PGA_UPDATE; /* PGA_UPDATE */
volatile uint16_t PGACR; /* PGACR */
volatile uint16_t ADCCR2; /* ADCCR2 */
};
#define DVDEC1 (*(struct st_dvdec *)0xFCFFA008uL) /* DVDEC1 */
#define DVDEC0 (*(struct st_dvdec *)0xFCFFB808uL) /* DVDEC0 */
/* Start of channnel array defines of DVDEC */
/* Channnel array defines of DVDEC */
/*(Sample) value = DVDEC[ channel ]->ADCCR1; */
#define DVDEC_COUNT 2
#define DVDEC_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&DVDEC0, &DVDEC1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of DVDEC */
#define ADCCR1_1 DVDEC1.ADCCR1
#define TGCR1_1 DVDEC1.TGCR1
#define TGCR2_1 DVDEC1.TGCR2
#define TGCR3_1 DVDEC1.TGCR3
#define SYNSCR1_1 DVDEC1.SYNSCR1
#define SYNSCR2_1 DVDEC1.SYNSCR2
#define SYNSCR3_1 DVDEC1.SYNSCR3
#define SYNSCR4_1 DVDEC1.SYNSCR4
#define SYNSCR5_1 DVDEC1.SYNSCR5
#define HAFCCR1_1 DVDEC1.HAFCCR1
#define HAFCCR2_1 DVDEC1.HAFCCR2
#define HAFCCR3_1 DVDEC1.HAFCCR3
#define VCDWCR1_1 DVDEC1.VCDWCR1
#define DCPCR1_1 DVDEC1.DCPCR1
#define DCPCR2_1 DVDEC1.DCPCR2
#define DCPCR3_1 DVDEC1.DCPCR3
#define DCPCR4_1 DVDEC1.DCPCR4
#define DCPCR5_1 DVDEC1.DCPCR5
#define DCPCR6_1 DVDEC1.DCPCR6
#define DCPCR7_1 DVDEC1.DCPCR7
#define DCPCR8_1 DVDEC1.DCPCR8
#define NSDCR_1 DVDEC1.NSDCR
#define BTLCR_1 DVDEC1.BTLCR
#define BTGPCR_1 DVDEC1.BTGPCR
#define ACCCR1_1 DVDEC1.ACCCR1
#define ACCCR2_1 DVDEC1.ACCCR2
#define ACCCR3_1 DVDEC1.ACCCR3
#define TINTCR_1 DVDEC1.TINTCR
#define YCDCR_1 DVDEC1.YCDCR
#define AGCCR1_1 DVDEC1.AGCCR1
#define AGCCR2_1 DVDEC1.AGCCR2
#define PKLIMITCR_1 DVDEC1.PKLIMITCR
#define RGORCR1_1 DVDEC1.RGORCR1
#define RGORCR2_1 DVDEC1.RGORCR2
#define RGORCR3_1 DVDEC1.RGORCR3
#define RGORCR4_1 DVDEC1.RGORCR4
#define RGORCR5_1 DVDEC1.RGORCR5
#define RGORCR6_1 DVDEC1.RGORCR6
#define RGORCR7_1 DVDEC1.RGORCR7
#define AFCPFCR_1 DVDEC1.AFCPFCR
#define RUPDCR_1 DVDEC1.RUPDCR
#define VSYNCSR_1 DVDEC1.VSYNCSR
#define HSYNCSR_1 DVDEC1.HSYNCSR
#define DCPSR1_1 DVDEC1.DCPSR1
#define DCPSR2_1 DVDEC1.DCPSR2
#define NSDSR_1 DVDEC1.NSDSR
#define CROMASR1_1 DVDEC1.CROMASR1
#define CROMASR2_1 DVDEC1.CROMASR2
#define SYNCSSR_1 DVDEC1.SYNCSSR
#define AGCCSR1_1 DVDEC1.AGCCSR1
#define AGCCSR2_1 DVDEC1.AGCCSR2
#define YCSCR3_1 DVDEC1.YCSCR3
#define YCSCR4_1 DVDEC1.YCSCR4
#define YCSCR5_1 DVDEC1.YCSCR5
#define YCSCR6_1 DVDEC1.YCSCR6
#define YCSCR7_1 DVDEC1.YCSCR7
#define YCSCR8_1 DVDEC1.YCSCR8
#define YCSCR9_1 DVDEC1.YCSCR9
#define YCSCR11_1 DVDEC1.YCSCR11
#define YCSCR12_1 DVDEC1.YCSCR12
#define DCPCR9_1 DVDEC1.DCPCR9
#define YCTWA_F0_1 DVDEC1.YCTWA_F0
#define YCTWA_F1_1 DVDEC1.YCTWA_F1
#define YCTWA_F2_1 DVDEC1.YCTWA_F2
#define YCTWA_F3_1 DVDEC1.YCTWA_F3
#define YCTWA_F4_1 DVDEC1.YCTWA_F4
#define YCTWA_F5_1 DVDEC1.YCTWA_F5
#define YCTWA_F6_1 DVDEC1.YCTWA_F6
#define YCTWA_F7_1 DVDEC1.YCTWA_F7
#define YCTWA_F8_1 DVDEC1.YCTWA_F8
#define YCTWB_F0_1 DVDEC1.YCTWB_F0
#define YCTWB_F1_1 DVDEC1.YCTWB_F1
#define YCTWB_F2_1 DVDEC1.YCTWB_F2
#define YCTWB_F3_1 DVDEC1.YCTWB_F3
#define YCTWB_F4_1 DVDEC1.YCTWB_F4
#define YCTWB_F5_1 DVDEC1.YCTWB_F5
#define YCTWB_F6_1 DVDEC1.YCTWB_F6
#define YCTWB_F7_1 DVDEC1.YCTWB_F7
#define YCTWB_F8_1 DVDEC1.YCTWB_F8
#define YCTNA_F0_1 DVDEC1.YCTNA_F0
#define YCTNA_F1_1 DVDEC1.YCTNA_F1
#define YCTNA_F2_1 DVDEC1.YCTNA_F2
#define YCTNA_F3_1 DVDEC1.YCTNA_F3
#define YCTNA_F4_1 DVDEC1.YCTNA_F4
#define YCTNA_F5_1 DVDEC1.YCTNA_F5
#define YCTNA_F6_1 DVDEC1.YCTNA_F6
#define YCTNA_F7_1 DVDEC1.YCTNA_F7
#define YCTNA_F8_1 DVDEC1.YCTNA_F8
#define YCTNB_F0_1 DVDEC1.YCTNB_F0
#define YCTNB_F1_1 DVDEC1.YCTNB_F1
#define YCTNB_F2_1 DVDEC1.YCTNB_F2
#define YCTNB_F3_1 DVDEC1.YCTNB_F3
#define YCTNB_F4_1 DVDEC1.YCTNB_F4
#define YCTNB_F5_1 DVDEC1.YCTNB_F5
#define YCTNB_F6_1 DVDEC1.YCTNB_F6
#define YCTNB_F7_1 DVDEC1.YCTNB_F7
#define YCTNB_F8_1 DVDEC1.YCTNB_F8
#define YGAINCR_1 DVDEC1.YGAINCR
#define CBGAINCR_1 DVDEC1.CBGAINCR
#define CRGAINCR_1 DVDEC1.CRGAINCR
#define PGA_UPDATE_1 DVDEC1.PGA_UPDATE
#define PGACR_1 DVDEC1.PGACR
#define ADCCR2_1 DVDEC1.ADCCR2
#define ADCCR1_0 DVDEC0.ADCCR1
#define TGCR1_0 DVDEC0.TGCR1
#define TGCR2_0 DVDEC0.TGCR2
#define TGCR3_0 DVDEC0.TGCR3
#define SYNSCR1_0 DVDEC0.SYNSCR1
#define SYNSCR2_0 DVDEC0.SYNSCR2
#define SYNSCR3_0 DVDEC0.SYNSCR3
#define SYNSCR4_0 DVDEC0.SYNSCR4
#define SYNSCR5_0 DVDEC0.SYNSCR5
#define HAFCCR1_0 DVDEC0.HAFCCR1
#define HAFCCR2_0 DVDEC0.HAFCCR2
#define HAFCCR3_0 DVDEC0.HAFCCR3
#define VCDWCR1_0 DVDEC0.VCDWCR1
#define DCPCR1_0 DVDEC0.DCPCR1
#define DCPCR2_0 DVDEC0.DCPCR2
#define DCPCR3_0 DVDEC0.DCPCR3
#define DCPCR4_0 DVDEC0.DCPCR4
#define DCPCR5_0 DVDEC0.DCPCR5
#define DCPCR6_0 DVDEC0.DCPCR6
#define DCPCR7_0 DVDEC0.DCPCR7
#define DCPCR8_0 DVDEC0.DCPCR8
#define NSDCR_0 DVDEC0.NSDCR
#define BTLCR_0 DVDEC0.BTLCR
#define BTGPCR_0 DVDEC0.BTGPCR
#define ACCCR1_0 DVDEC0.ACCCR1
#define ACCCR2_0 DVDEC0.ACCCR2
#define ACCCR3_0 DVDEC0.ACCCR3
#define TINTCR_0 DVDEC0.TINTCR
#define YCDCR_0 DVDEC0.YCDCR
#define AGCCR1_0 DVDEC0.AGCCR1
#define AGCCR2_0 DVDEC0.AGCCR2
#define PKLIMITCR_0 DVDEC0.PKLIMITCR
#define RGORCR1_0 DVDEC0.RGORCR1
#define RGORCR2_0 DVDEC0.RGORCR2
#define RGORCR3_0 DVDEC0.RGORCR3
#define RGORCR4_0 DVDEC0.RGORCR4
#define RGORCR5_0 DVDEC0.RGORCR5
#define RGORCR6_0 DVDEC0.RGORCR6
#define RGORCR7_0 DVDEC0.RGORCR7
#define AFCPFCR_0 DVDEC0.AFCPFCR
#define RUPDCR_0 DVDEC0.RUPDCR
#define VSYNCSR_0 DVDEC0.VSYNCSR
#define HSYNCSR_0 DVDEC0.HSYNCSR
#define DCPSR1_0 DVDEC0.DCPSR1
#define DCPSR2_0 DVDEC0.DCPSR2
#define NSDSR_0 DVDEC0.NSDSR
#define CROMASR1_0 DVDEC0.CROMASR1
#define CROMASR2_0 DVDEC0.CROMASR2
#define SYNCSSR_0 DVDEC0.SYNCSSR
#define AGCCSR1_0 DVDEC0.AGCCSR1
#define AGCCSR2_0 DVDEC0.AGCCSR2
#define YCSCR3_0 DVDEC0.YCSCR3
#define YCSCR4_0 DVDEC0.YCSCR4
#define YCSCR5_0 DVDEC0.YCSCR5
#define YCSCR6_0 DVDEC0.YCSCR6
#define YCSCR7_0 DVDEC0.YCSCR7
#define YCSCR8_0 DVDEC0.YCSCR8
#define YCSCR9_0 DVDEC0.YCSCR9
#define YCSCR11_0 DVDEC0.YCSCR11
#define YCSCR12_0 DVDEC0.YCSCR12
#define DCPCR9_0 DVDEC0.DCPCR9
#define YCTWA_F0_0 DVDEC0.YCTWA_F0
#define YCTWA_F1_0 DVDEC0.YCTWA_F1
#define YCTWA_F2_0 DVDEC0.YCTWA_F2
#define YCTWA_F3_0 DVDEC0.YCTWA_F3
#define YCTWA_F4_0 DVDEC0.YCTWA_F4
#define YCTWA_F5_0 DVDEC0.YCTWA_F5
#define YCTWA_F6_0 DVDEC0.YCTWA_F6
#define YCTWA_F7_0 DVDEC0.YCTWA_F7
#define YCTWA_F8_0 DVDEC0.YCTWA_F8
#define YCTWB_F0_0 DVDEC0.YCTWB_F0
#define YCTWB_F1_0 DVDEC0.YCTWB_F1
#define YCTWB_F2_0 DVDEC0.YCTWB_F2
#define YCTWB_F3_0 DVDEC0.YCTWB_F3
#define YCTWB_F4_0 DVDEC0.YCTWB_F4
#define YCTWB_F5_0 DVDEC0.YCTWB_F5
#define YCTWB_F6_0 DVDEC0.YCTWB_F6
#define YCTWB_F7_0 DVDEC0.YCTWB_F7
#define YCTWB_F8_0 DVDEC0.YCTWB_F8
#define YCTNA_F0_0 DVDEC0.YCTNA_F0
#define YCTNA_F1_0 DVDEC0.YCTNA_F1
#define YCTNA_F2_0 DVDEC0.YCTNA_F2
#define YCTNA_F3_0 DVDEC0.YCTNA_F3
#define YCTNA_F4_0 DVDEC0.YCTNA_F4
#define YCTNA_F5_0 DVDEC0.YCTNA_F5
#define YCTNA_F6_0 DVDEC0.YCTNA_F6
#define YCTNA_F7_0 DVDEC0.YCTNA_F7
#define YCTNA_F8_0 DVDEC0.YCTNA_F8
#define YCTNB_F0_0 DVDEC0.YCTNB_F0
#define YCTNB_F1_0 DVDEC0.YCTNB_F1
#define YCTNB_F2_0 DVDEC0.YCTNB_F2
#define YCTNB_F3_0 DVDEC0.YCTNB_F3
#define YCTNB_F4_0 DVDEC0.YCTNB_F4
#define YCTNB_F5_0 DVDEC0.YCTNB_F5
#define YCTNB_F6_0 DVDEC0.YCTNB_F6
#define YCTNB_F7_0 DVDEC0.YCTNB_F7
#define YCTNB_F8_0 DVDEC0.YCTNB_F8
#define YGAINCR_0 DVDEC0.YGAINCR
#define CBGAINCR_0 DVDEC0.CBGAINCR
#define CRGAINCR_0 DVDEC0.CRGAINCR
#define PGA_UPDATE_0 DVDEC0.PGA_UPDATE
#define PGACR_0 DVDEC0.PGACR
#define ADCCR2_0 DVDEC0.ADCCR2
/* <-SEC M1.10.1 */
#endif

427
libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ether_iodefine.h Normal file
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@ -0,0 +1,427 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ether_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef ETHER_IODEFINE_H
#define ETHER_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->SEC M1.10.1 : Not magic number */
struct st_ether
{ /* ETHER */
volatile uint32_t EDSR0; /* EDSR0 */
volatile uint8_t dummy207[12]; /* */
volatile uint32_t TDLAR0; /* TDLAR0 */
volatile uint32_t TDFAR0; /* TDFAR0 */
volatile uint32_t TDFXR0; /* TDFXR0 */
volatile uint32_t TDFFR0; /* TDFFR0 */
volatile uint8_t dummy208[16]; /* */
volatile uint32_t RDLAR0; /* RDLAR0 */
volatile uint32_t RDFAR0; /* RDFAR0 */
volatile uint32_t RDFXR0; /* RDFXR0 */
volatile uint32_t RDFFR0; /* RDFFR0 */
volatile uint8_t dummy209[960]; /* */
volatile uint32_t EDMR0; /* EDMR0 */
volatile uint8_t dummy210[4]; /* */
volatile uint32_t EDTRR0; /* EDTRR0 */
volatile uint8_t dummy211[4]; /* */
volatile uint32_t EDRRR0; /* EDRRR0 */
volatile uint8_t dummy212[20]; /* */
volatile uint32_t EESR0; /* EESR0 */
volatile uint8_t dummy213[4]; /* */
volatile uint32_t EESIPR0; /* EESIPR0 */
volatile uint8_t dummy214[4]; /* */
volatile uint32_t TRSCER0; /* TRSCER0 */
volatile uint8_t dummy215[4]; /* */
volatile uint32_t RMFCR0; /* RMFCR0 */
volatile uint8_t dummy216[4]; /* */
volatile uint32_t TFTR0; /* TFTR0 */
volatile uint8_t dummy217[4]; /* */
volatile uint32_t FDR0; /* FDR0 */
volatile uint8_t dummy218[4]; /* */
volatile uint32_t RMCR0; /* RMCR0 */
volatile uint8_t dummy219[4]; /* */
volatile uint32_t RPADIR0; /* RPADIR0 */
volatile uint8_t dummy220[4]; /* */
volatile uint32_t FCFTR0; /* FCFTR0 */
volatile uint8_t dummy221[120]; /* */
volatile uint32_t CSMR; /* CSMR */
volatile uint32_t CSSBM; /* CSSBM */
volatile uint32_t CSSMR; /* CSSMR */
volatile uint8_t dummy222[16]; /* */
volatile uint32_t ECMR0; /* ECMR0 */
volatile uint8_t dummy223[4]; /* */
volatile uint32_t RFLR0; /* RFLR0 */
volatile uint8_t dummy224[4]; /* */
volatile uint32_t ECSR0; /* ECSR0 */
volatile uint8_t dummy225[4]; /* */
volatile uint32_t ECSIPR0; /* ECSIPR0 */
volatile uint8_t dummy226[4]; /* */
volatile uint32_t PIR0; /* PIR0 */
volatile uint8_t dummy227[48]; /* */
volatile uint32_t APR0; /* APR0 */
volatile uint32_t MPR0; /* MPR0 */
volatile uint32_t PFTCR0; /* PFTCR0 */
volatile uint32_t PFRCR0; /* PFRCR0 */
volatile uint32_t TPAUSER0; /* TPAUSER0 */
volatile uint8_t dummy228[88]; /* */
volatile uint32_t MAHR0; /* MAHR0 */
volatile uint8_t dummy229[4]; /* */
volatile uint32_t MALR0; /* MALR0 */
volatile uint8_t dummy230[372]; /* */
volatile uint32_t CEFCR0; /* CEFCR0 */
volatile uint8_t dummy231[4]; /* */
volatile uint32_t FRECR0; /* FRECR0 */
volatile uint8_t dummy232[4]; /* */
volatile uint32_t TSFRCR0; /* TSFRCR0 */
volatile uint8_t dummy233[4]; /* */
volatile uint32_t TLFRCR0; /* TLFRCR0 */
volatile uint8_t dummy234[4]; /* */
volatile uint32_t RFCR0; /* RFCR0 */
volatile uint8_t dummy235[20]; /* */
volatile uint32_t MAFCR0; /* MAFCR0 */
volatile uint8_t dummy236[4228]; /* */
volatile uint32_t ARSTR; /* ARSTR */
volatile uint32_t TSU_CTRST; /* TSU_CTRST */
volatile uint8_t dummy237[80]; /* */
volatile uint32_t TSU_VTAG0; /* TSU_VTAG0 */
volatile uint8_t dummy238[4]; /* */
volatile uint32_t TSU_ADSBSY; /* TSU_ADSBSY */
volatile uint32_t TSU_TEN; /* TSU_TEN */
volatile uint8_t dummy239[24]; /* */
volatile uint32_t TXNLCR0; /* TXNLCR0 */
volatile uint32_t TXALCR0; /* TXALCR0 */
volatile uint32_t RXNLCR0; /* RXNLCR0 */
volatile uint32_t RXALCR0; /* RXALCR0 */
volatile uint8_t dummy240[112]; /* */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */
volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH1; /* TSU_ADRH1 */
volatile uint32_t TSU_ADRL1; /* TSU_ADRL1 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH2; /* TSU_ADRH2 */
volatile uint32_t TSU_ADRL2; /* TSU_ADRL2 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH3; /* TSU_ADRH3 */
volatile uint32_t TSU_ADRL3; /* TSU_ADRL3 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH4; /* TSU_ADRH4 */
volatile uint32_t TSU_ADRL4; /* TSU_ADRL4 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH5; /* TSU_ADRH5 */
volatile uint32_t TSU_ADRL5; /* TSU_ADRL5 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH6; /* TSU_ADRH6 */
volatile uint32_t TSU_ADRL6; /* TSU_ADRL6 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH7; /* TSU_ADRH7 */
volatile uint32_t TSU_ADRL7; /* TSU_ADRL7 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH8; /* TSU_ADRH8 */
volatile uint32_t TSU_ADRL8; /* TSU_ADRL8 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH9; /* TSU_ADRH9 */
volatile uint32_t TSU_ADRL9; /* TSU_ADRL9 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH10; /* TSU_ADRH10 */
volatile uint32_t TSU_ADRL10; /* TSU_ADRL10 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH11; /* TSU_ADRH11 */
volatile uint32_t TSU_ADRL11; /* TSU_ADRL11 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH12; /* TSU_ADRH12 */
volatile uint32_t TSU_ADRL12; /* TSU_ADRL12 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH13; /* TSU_ADRH13 */
volatile uint32_t TSU_ADRL13; /* TSU_ADRL13 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH14; /* TSU_ADRH14 */
volatile uint32_t TSU_ADRL14; /* TSU_ADRL14 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH15; /* TSU_ADRH15 */
volatile uint32_t TSU_ADRL15; /* TSU_ADRL15 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH16; /* TSU_ADRH16 */
volatile uint32_t TSU_ADRL16; /* TSU_ADRL16 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH17; /* TSU_ADRH17 */
volatile uint32_t TSU_ADRL17; /* TSU_ADRL17 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH18; /* TSU_ADRH18 */
volatile uint32_t TSU_ADRL18; /* TSU_ADRL18 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH19; /* TSU_ADRH19 */
volatile uint32_t TSU_ADRL19; /* TSU_ADRL19 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH20; /* TSU_ADRH20 */
volatile uint32_t TSU_ADRL20; /* TSU_ADRL20 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH21; /* TSU_ADRH21 */
volatile uint32_t TSU_ADRL21; /* TSU_ADRL21 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH22; /* TSU_ADRH22 */
volatile uint32_t TSU_ADRL22; /* TSU_ADRL22 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH23; /* TSU_ADRH23 */
volatile uint32_t TSU_ADRL23; /* TSU_ADRL23 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH24; /* TSU_ADRH24 */
volatile uint32_t TSU_ADRL24; /* TSU_ADRL24 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH25; /* TSU_ADRH25 */
volatile uint32_t TSU_ADRL25; /* TSU_ADRL25 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH26; /* TSU_ADRH26 */
volatile uint32_t TSU_ADRL26; /* TSU_ADRL26 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH27; /* TSU_ADRH27 */
volatile uint32_t TSU_ADRL27; /* TSU_ADRL27 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH28; /* TSU_ADRH28 */
volatile uint32_t TSU_ADRL28; /* TSU_ADRL28 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH29; /* TSU_ADRH29 */
volatile uint32_t TSU_ADRL29; /* TSU_ADRL29 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH30; /* TSU_ADRH30 */
volatile uint32_t TSU_ADRL30; /* TSU_ADRL30 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH31; /* TSU_ADRH31 */
volatile uint32_t TSU_ADRL31; /* TSU_ADRL31 */
/* end of struct st_ether_from_tsu_adrh0 */
};
struct st_ether_from_tsu_adrh0
{
volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */
volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */
};
#define ETHER (*(struct st_ether *)0xE8203000uL) /* ETHER */
/* Start of channnel array defines of ETHER */
/* Channnel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */
/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */
#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT 32
#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&ETHER_FROM_TSU_ADRH0, &ETHER_FROM_TSU_ADRH1, &ETHER_FROM_TSU_ADRH2, &ETHER_FROM_TSU_ADRH3, &ETHER_FROM_TSU_ADRH4, &ETHER_FROM_TSU_ADRH5, &ETHER_FROM_TSU_ADRH6, &ETHER_FROM_TSU_ADRH7, \
&ETHER_FROM_TSU_ADRH8, &ETHER_FROM_TSU_ADRH9, &ETHER_FROM_TSU_ADRH10, &ETHER_FROM_TSU_ADRH11, &ETHER_FROM_TSU_ADRH12, &ETHER_FROM_TSU_ADRH13, &ETHER_FROM_TSU_ADRH14, &ETHER_FROM_TSU_ADRH15, \
&ETHER_FROM_TSU_ADRH16, &ETHER_FROM_TSU_ADRH17, &ETHER_FROM_TSU_ADRH18, &ETHER_FROM_TSU_ADRH19, &ETHER_FROM_TSU_ADRH20, &ETHER_FROM_TSU_ADRH21, &ETHER_FROM_TSU_ADRH22, &ETHER_FROM_TSU_ADRH23, \
&ETHER_FROM_TSU_ADRH24, &ETHER_FROM_TSU_ADRH25, &ETHER_FROM_TSU_ADRH26, &ETHER_FROM_TSU_ADRH27, &ETHER_FROM_TSU_ADRH28, &ETHER_FROM_TSU_ADRH29, &ETHER_FROM_TSU_ADRH30, &ETHER_FROM_TSU_ADRH31 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */
#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */
#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */
#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */
#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */
#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */
#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */
#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */
#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */
#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */
#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */
#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */
#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */
#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */
#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */
#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */
#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */
#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */
#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */
#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */
#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */
#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */
#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */
#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */
#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */
#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */
#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */
#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */
#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */
#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */
#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */
#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */
/* End of channnel array defines of ETHER */
#define ETHEREDSR0 ETHER.EDSR0
#define ETHERTDLAR0 ETHER.TDLAR0
#define ETHERTDFAR0 ETHER.TDFAR0
#define ETHERTDFXR0 ETHER.TDFXR0
#define ETHERTDFFR0 ETHER.TDFFR0
#define ETHERRDLAR0 ETHER.RDLAR0
#define ETHERRDFAR0 ETHER.RDFAR0
#define ETHERRDFXR0 ETHER.RDFXR0
#define ETHERRDFFR0 ETHER.RDFFR0
#define ETHEREDMR0 ETHER.EDMR0
#define ETHEREDTRR0 ETHER.EDTRR0
#define ETHEREDRRR0 ETHER.EDRRR0
#define ETHEREESR0 ETHER.EESR0
#define ETHEREESIPR0 ETHER.EESIPR0
#define ETHERTRSCER0 ETHER.TRSCER0
#define ETHERRMFCR0 ETHER.RMFCR0
#define ETHERTFTR0 ETHER.TFTR0
#define ETHERFDR0 ETHER.FDR0
#define ETHERRMCR0 ETHER.RMCR0
#define ETHERRPADIR0 ETHER.RPADIR0
#define ETHERFCFTR0 ETHER.FCFTR0
#define ETHERCSMR ETHER.CSMR
#define ETHERCSSBM ETHER.CSSBM
#define ETHERCSSMR ETHER.CSSMR
#define ETHERECMR0 ETHER.ECMR0
#define ETHERRFLR0 ETHER.RFLR0
#define ETHERECSR0 ETHER.ECSR0
#define ETHERECSIPR0 ETHER.ECSIPR0
#define ETHERPIR0 ETHER.PIR0
#define ETHERAPR0 ETHER.APR0
#define ETHERMPR0 ETHER.MPR0
#define ETHERPFTCR0 ETHER.PFTCR0
#define ETHERPFRCR0 ETHER.PFRCR0
#define ETHERTPAUSER0 ETHER.TPAUSER0
#define ETHERMAHR0 ETHER.MAHR0
#define ETHERMALR0 ETHER.MALR0
#define ETHERCEFCR0 ETHER.CEFCR0
#define ETHERFRECR0 ETHER.FRECR0
#define ETHERTSFRCR0 ETHER.TSFRCR0
#define ETHERTLFRCR0 ETHER.TLFRCR0
#define ETHERRFCR0 ETHER.RFCR0
#define ETHERMAFCR0 ETHER.MAFCR0
#define ETHERARSTR ETHER.ARSTR
#define ETHERTSU_CTRST ETHER.TSU_CTRST
#define ETHERTSU_VTAG0 ETHER.TSU_VTAG0
#define ETHERTSU_ADSBSY ETHER.TSU_ADSBSY
#define ETHERTSU_TEN ETHER.TSU_TEN
#define ETHERTXNLCR0 ETHER.TXNLCR0
#define ETHERTXALCR0 ETHER.TXALCR0
#define ETHERRXNLCR0 ETHER.RXNLCR0
#define ETHERRXALCR0 ETHER.RXALCR0
#define ETHERTSU_ADRH0 ETHER.TSU_ADRH0
#define ETHERTSU_ADRL0 ETHER.TSU_ADRL0
#define ETHERTSU_ADRH1 ETHER.TSU_ADRH1
#define ETHERTSU_ADRL1 ETHER.TSU_ADRL1
#define ETHERTSU_ADRH2 ETHER.TSU_ADRH2
#define ETHERTSU_ADRL2 ETHER.TSU_ADRL2
#define ETHERTSU_ADRH3 ETHER.TSU_ADRH3
#define ETHERTSU_ADRL3 ETHER.TSU_ADRL3
#define ETHERTSU_ADRH4 ETHER.TSU_ADRH4
#define ETHERTSU_ADRL4 ETHER.TSU_ADRL4
#define ETHERTSU_ADRH5 ETHER.TSU_ADRH5
#define ETHERTSU_ADRL5 ETHER.TSU_ADRL5
#define ETHERTSU_ADRH6 ETHER.TSU_ADRH6
#define ETHERTSU_ADRL6 ETHER.TSU_ADRL6
#define ETHERTSU_ADRH7 ETHER.TSU_ADRH7
#define ETHERTSU_ADRL7 ETHER.TSU_ADRL7
#define ETHERTSU_ADRH8 ETHER.TSU_ADRH8
#define ETHERTSU_ADRL8 ETHER.TSU_ADRL8
#define ETHERTSU_ADRH9 ETHER.TSU_ADRH9
#define ETHERTSU_ADRL9 ETHER.TSU_ADRL9
#define ETHERTSU_ADRH10 ETHER.TSU_ADRH10
#define ETHERTSU_ADRL10 ETHER.TSU_ADRL10
#define ETHERTSU_ADRH11 ETHER.TSU_ADRH11
#define ETHERTSU_ADRL11 ETHER.TSU_ADRL11
#define ETHERTSU_ADRH12 ETHER.TSU_ADRH12
#define ETHERTSU_ADRL12 ETHER.TSU_ADRL12
#define ETHERTSU_ADRH13 ETHER.TSU_ADRH13
#define ETHERTSU_ADRL13 ETHER.TSU_ADRL13
#define ETHERTSU_ADRH14 ETHER.TSU_ADRH14
#define ETHERTSU_ADRL14 ETHER.TSU_ADRL14
#define ETHERTSU_ADRH15 ETHER.TSU_ADRH15
#define ETHERTSU_ADRL15 ETHER.TSU_ADRL15
#define ETHERTSU_ADRH16 ETHER.TSU_ADRH16
#define ETHERTSU_ADRL16 ETHER.TSU_ADRL16
#define ETHERTSU_ADRH17 ETHER.TSU_ADRH17
#define ETHERTSU_ADRL17 ETHER.TSU_ADRL17
#define ETHERTSU_ADRH18 ETHER.TSU_ADRH18
#define ETHERTSU_ADRL18 ETHER.TSU_ADRL18
#define ETHERTSU_ADRH19 ETHER.TSU_ADRH19
#define ETHERTSU_ADRL19 ETHER.TSU_ADRL19
#define ETHERTSU_ADRH20 ETHER.TSU_ADRH20
#define ETHERTSU_ADRL20 ETHER.TSU_ADRL20
#define ETHERTSU_ADRH21 ETHER.TSU_ADRH21
#define ETHERTSU_ADRL21 ETHER.TSU_ADRL21
#define ETHERTSU_ADRH22 ETHER.TSU_ADRH22
#define ETHERTSU_ADRL22 ETHER.TSU_ADRL22
#define ETHERTSU_ADRH23 ETHER.TSU_ADRH23
#define ETHERTSU_ADRL23 ETHER.TSU_ADRL23
#define ETHERTSU_ADRH24 ETHER.TSU_ADRH24
#define ETHERTSU_ADRL24 ETHER.TSU_ADRL24
#define ETHERTSU_ADRH25 ETHER.TSU_ADRH25
#define ETHERTSU_ADRL25 ETHER.TSU_ADRL25
#define ETHERTSU_ADRH26 ETHER.TSU_ADRH26
#define ETHERTSU_ADRL26 ETHER.TSU_ADRL26
#define ETHERTSU_ADRH27 ETHER.TSU_ADRH27
#define ETHERTSU_ADRL27 ETHER.TSU_ADRL27
#define ETHERTSU_ADRH28 ETHER.TSU_ADRH28
#define ETHERTSU_ADRL28 ETHER.TSU_ADRL28
#define ETHERTSU_ADRH29 ETHER.TSU_ADRH29
#define ETHERTSU_ADRL29 ETHER.TSU_ADRL29
#define ETHERTSU_ADRH30 ETHER.TSU_ADRH30
#define ETHERTSU_ADRL30 ETHER.TSU_ADRL30
#define ETHERTSU_ADRH31 ETHER.TSU_ADRH31
#define ETHERTSU_ADRL31 ETHER.TSU_ADRL31
/* <-SEC M1.10.1 */
/* <-QAC 0639 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : flctl_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef FLCTL_IODEFINE_H
#define FLCTL_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_flctl
{ /* FLCTL */
volatile uint32_t FLCMNCR; /* FLCMNCR */
volatile uint32_t FLCMDCR; /* FLCMDCR */
volatile uint32_t FLCMCDR; /* FLCMCDR */
volatile uint32_t FLADR; /* FLADR */
volatile uint32_t FLDATAR; /* FLDATAR */
volatile uint32_t FLDTCNTR; /* FLDTCNTR */
volatile uint32_t FLINTDMACR; /* FLINTDMACR */
volatile uint32_t FLBSYTMR; /* FLBSYTMR */
volatile uint32_t FLBSYCNT; /* FLBSYCNT */
volatile uint8_t dummy555[8]; /* */
volatile uint8_t FLTRCR; /* FLTRCR */
volatile uint8_t dummy556[15]; /* */
volatile uint32_t FLADR2; /* FLADR2 */
volatile uint8_t dummy557[16]; /* */
volatile uint32_t FLDTFIFO; /* FLDTFIFO */
volatile uint8_t dummy558[12]; /* */
volatile uint32_t FLECFIFO; /* FLECFIFO */
};
#define FLCTL (*(struct st_flctl *)0xFCFF4000uL) /* FLCTL */
#define FLCTLFLCMNCR FLCTL.FLCMNCR
#define FLCTLFLCMDCR FLCTL.FLCMDCR
#define FLCTLFLCMCDR FLCTL.FLCMCDR
#define FLCTLFLADR FLCTL.FLADR
#define FLCTLFLDATAR FLCTL.FLDATAR
#define FLCTLFLDTCNTR FLCTL.FLDTCNTR
#define FLCTLFLINTDMACR FLCTL.FLINTDMACR
#define FLCTLFLBSYTMR FLCTL.FLBSYTMR
#define FLCTLFLBSYCNT FLCTL.FLBSYCNT
#define FLCTLFLTRCR FLCTL.FLTRCR
#define FLCTLFLADR2 FLCTL.FLADR2
#define FLCTLFLDTFIFO FLCTL.FLDTFIFO
#define FLCTLFLECFIFO FLCTL.FLECFIFO
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ieb_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef IEB_IODEFINE_H
#define IEB_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_ieb
{ /* IEB */
volatile uint8_t B0BCR; /* B0BCR */
volatile uint8_t dummy495[3]; /* */
volatile uint8_t B0PSR; /* B0PSR */
volatile uint8_t dummy496[3]; /* */
volatile uint16_t B0UAR; /* B0UAR */
volatile uint8_t dummy497[2]; /* */
volatile uint16_t B0SAR; /* B0SAR */
volatile uint8_t dummy498[2]; /* */
volatile uint16_t B0PAR; /* B0PAR */
volatile uint8_t dummy499[2]; /* */
volatile uint16_t B0RSA; /* B0RSA */
volatile uint8_t dummy500[2]; /* */
volatile uint8_t B0CDR; /* B0CDR */
volatile uint8_t dummy501[3]; /* */
volatile uint8_t B0TCD; /* B0TCD */
volatile uint8_t dummy502[3]; /* */
volatile uint8_t B0RCD; /* B0RCD */
volatile uint8_t dummy503[3]; /* */
volatile uint8_t B0DLR; /* B0DLR */
volatile uint8_t dummy504[3]; /* */
volatile uint8_t B0TDL; /* B0TDL */
volatile uint8_t dummy505[3]; /* */
volatile uint8_t B0RDL; /* B0RDL */
volatile uint8_t dummy506[3]; /* */
volatile uint8_t B0CKS; /* B0CKS */
volatile uint8_t dummy507[3]; /* */
volatile uint8_t B0TMS; /* B0TMS */
volatile uint8_t dummy508[3]; /* */
volatile uint8_t B0PCR; /* B0PCR */
volatile uint8_t dummy509[3]; /* */
volatile uint16_t B0BSR; /* B0BSR */
volatile uint8_t dummy510[2]; /* */
volatile uint8_t B0SSR; /* B0SSR */
volatile uint8_t dummy511[3]; /* */
volatile uint8_t B0USR; /* B0USR */
volatile uint8_t dummy512[3]; /* */
volatile uint8_t B0ISR; /* B0ISR */
volatile uint8_t dummy513[3]; /* */
volatile uint8_t B0ESR; /* B0ESR */
volatile uint8_t dummy514[3]; /* */
volatile uint8_t B0FSR; /* B0FSR */
volatile uint8_t dummy515[3]; /* */
volatile uint8_t B0SCR; /* B0SCR */
volatile uint8_t dummy516[3]; /* */
volatile uint8_t B0CCR; /* B0CCR */
volatile uint8_t dummy517[3]; /* */
volatile uint8_t B0STC0; /* B0STC0 */
volatile uint8_t dummy518[3]; /* */
volatile uint8_t B0STC1; /* B0STC1 */
volatile uint8_t dummy519[3]; /* */
volatile uint8_t B0DR; /* B0DR */
};
#define IEB (*(struct st_ieb *)0xFCFEF000uL) /* IEB */
#define IEBB0BCR IEB.B0BCR
#define IEBB0PSR IEB.B0PSR
#define IEBB0UAR IEB.B0UAR
#define IEBB0SAR IEB.B0SAR
#define IEBB0PAR IEB.B0PAR
#define IEBB0RSA IEB.B0RSA
#define IEBB0CDR IEB.B0CDR
#define IEBB0TCD IEB.B0TCD
#define IEBB0RCD IEB.B0RCD
#define IEBB0DLR IEB.B0DLR
#define IEBB0TDL IEB.B0TDL
#define IEBB0RDL IEB.B0RDL
#define IEBB0CKS IEB.B0CKS
#define IEBB0TMS IEB.B0TMS
#define IEBB0PCR IEB.B0PCR
#define IEBB0BSR IEB.B0BSR
#define IEBB0SSR IEB.B0SSR
#define IEBB0USR IEB.B0USR
#define IEBB0ISR IEB.B0ISR
#define IEBB0ESR IEB.B0ESR
#define IEBB0FSR IEB.B0FSR
#define IEBB0SCR IEB.B0SCR
#define IEBB0CCR IEB.B0CCR
#define IEBB0STC0 IEB.B0STC0
#define IEBB0STC1 IEB.B0STC1
#define IEBB0DR IEB.B0DR
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : inb_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef INB_IODEFINE_H
#define INB_IODEFINE_H
struct st_inb
{ /* INB */
volatile uint32_t RMPR; /* RMPR */
#define INB_AXIBUSCTLn_COUNT 11
volatile uint32_t AXIBUSCTL0; /* AXIBUSCTL0 */
volatile uint32_t AXIBUSCTL1; /* AXIBUSCTL1 */
volatile uint32_t AXIBUSCTL2; /* AXIBUSCTL2 */
volatile uint32_t AXIBUSCTL3; /* AXIBUSCTL3 */
volatile uint32_t AXIBUSCTL4; /* AXIBUSCTL4 */
volatile uint32_t AXIBUSCTL5; /* AXIBUSCTL5 */
volatile uint32_t AXIBUSCTL6; /* AXIBUSCTL6 */
volatile uint32_t AXIBUSCTL7; /* AXIBUSCTL7 */
volatile uint32_t AXIBUSCTL8; /* AXIBUSCTL8 */
volatile uint32_t AXIBUSCTL9; /* AXIBUSCTL9 */
volatile uint32_t AXIBUSCTL10; /* AXIBUSCTL10 */
#define INB_AXIRERRCTLn_COUNT 4
volatile uint32_t AXIRERRCTL0; /* AXIRERRCTL0 */
volatile uint32_t AXIRERRCTL1; /* AXIRERRCTL1 */
volatile uint32_t AXIRERRCTL2; /* AXIRERRCTL2 */
volatile uint32_t AXIRERRCTL3; /* AXIRERRCTL3 */
#define INB_AXIRERRSTn_COUNT 4
volatile uint32_t AXIRERRST0; /* AXIRERRST0 */
volatile uint32_t AXIRERRST1; /* AXIRERRST1 */
volatile uint32_t AXIRERRST2; /* AXIRERRST2 */
volatile uint32_t AXIRERRST3; /* AXIRERRST3 */
#define INB_AXIRERRCLRn_COUNT 4
volatile uint32_t AXIRERRCLR0; /* AXIRERRCLR0 */
volatile uint32_t AXIRERRCLR1; /* AXIRERRCLR1 */
volatile uint32_t AXIRERRCLR2; /* AXIRERRCLR2 */
volatile uint32_t AXIRERRCLR3; /* AXIRERRCLR3 */
};
#define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */
#define INBRMPR INB.RMPR
#define INBAXIBUSCTL0 INB.AXIBUSCTL0
#define INBAXIBUSCTL1 INB.AXIBUSCTL1
#define INBAXIBUSCTL2 INB.AXIBUSCTL2
#define INBAXIBUSCTL3 INB.AXIBUSCTL3
#define INBAXIBUSCTL4 INB.AXIBUSCTL4
#define INBAXIBUSCTL5 INB.AXIBUSCTL5
#define INBAXIBUSCTL6 INB.AXIBUSCTL6
#define INBAXIBUSCTL7 INB.AXIBUSCTL7
#define INBAXIBUSCTL8 INB.AXIBUSCTL8
#define INBAXIBUSCTL9 INB.AXIBUSCTL9
#define INBAXIBUSCTL10 INB.AXIBUSCTL10
#define INBAXIRERRCTL0 INB.AXIRERRCTL0
#define INBAXIRERRCTL1 INB.AXIRERRCTL1
#define INBAXIRERRCTL2 INB.AXIRERRCTL2
#define INBAXIRERRCTL3 INB.AXIRERRCTL3
#define INBAXIRERRST0 INB.AXIRERRST0
#define INBAXIRERRST1 INB.AXIRERRST1
#define INBAXIRERRST2 INB.AXIRERRST2
#define INBAXIRERRST3 INB.AXIRERRST3
#define INBAXIRERRCLR0 INB.AXIRERRCLR0
#define INBAXIRERRCLR1 INB.AXIRERRCLR1
#define INBAXIRERRCLR2 INB.AXIRERRCLR2
#define INBAXIRERRCLR3 INB.AXIRERRCLR3
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : irda_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef IRDA_IODEFINE_H
#define IRDA_IODEFINE_H
struct st_irda
{ /* IRDA */
volatile uint8_t IRCR; /* IRCR */
};
#define IRDA (*(struct st_irda *)0xE8014000uL) /* IRDA */
#define IRDAIRCR IRDA.IRCR
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : jcu_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef JCU_IODEFINE_H
#define JCU_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_jcu
{ /* JCU */
volatile uint8_t JCMOD; /* JCMOD */
volatile uint8_t JCCMD; /* JCCMD */
volatile uint8_t dummy145[1]; /* */
volatile uint8_t JCQTN; /* JCQTN */
volatile uint8_t JCHTN; /* JCHTN */
volatile uint8_t JCDRIU; /* JCDRIU */
volatile uint8_t JCDRID; /* JCDRID */
volatile uint8_t JCVSZU; /* JCVSZU */
volatile uint8_t JCVSZD; /* JCVSZD */
volatile uint8_t JCHSZU; /* JCHSZU */
volatile uint8_t JCHSZD; /* JCHSZD */
volatile uint8_t JCDTCU; /* JCDTCU */
volatile uint8_t JCDTCM; /* JCDTCM */
volatile uint8_t JCDTCD; /* JCDTCD */
volatile uint8_t JINTE0; /* JINTE0 */
volatile uint8_t JINTS0; /* JINTS0 */
volatile uint8_t JCDERR; /* JCDERR */
volatile uint8_t JCRST; /* JCRST */
volatile uint8_t dummy146[46]; /* */
volatile uint32_t JIFECNT; /* JIFECNT */
volatile uint32_t JIFESA; /* JIFESA */
volatile uint32_t JIFESOFST; /* JIFESOFST */
volatile uint32_t JIFEDA; /* JIFEDA */
volatile uint32_t JIFESLC; /* JIFESLC */
volatile uint32_t JIFEDDC; /* JIFEDDC */
volatile uint32_t JIFDCNT; /* JIFDCNT */
volatile uint32_t JIFDSA; /* JIFDSA */
volatile uint32_t JIFDDOFST; /* JIFDDOFST */
volatile uint32_t JIFDDA; /* JIFDDA */
volatile uint32_t JIFDSDC; /* JIFDSDC */
volatile uint32_t JIFDDLC; /* JIFDDLC */
volatile uint32_t JIFDADT; /* JIFDADT */
volatile uint8_t dummy147[24]; /* */
volatile uint32_t JINTE1; /* JINTE1 */
volatile uint32_t JINTS1; /* JINTS1 */
volatile uint32_t JIFESVSZ; /* JIFESVSZ */
volatile uint32_t JIFESHSZ; /* JIFESHSZ */
volatile uint8_t dummy148[100]; /* */
/* start of struct st_jcu_from_jcqtbl0 */
volatile uint8_t JCQTBL0; /* JCQTBL0 */
volatile uint8_t dummy149[63]; /* */
/* end of struct st_jcu_from_jcqtbl0 */
/* start of struct st_jcu_from_jcqtbl0 */
volatile uint8_t JCQTBL1; /* JCQTBL1 */
volatile uint8_t dummy150[63]; /* */
/* end of struct st_jcu_from_jcqtbl0 */
/* start of struct st_jcu_from_jcqtbl0 */
volatile uint8_t JCQTBL2; /* JCQTBL2 */
volatile uint8_t dummy151[63]; /* */
/* end of struct st_jcu_from_jcqtbl0 */
/* start of struct st_jcu_from_jcqtbl0 */
volatile uint8_t JCQTBL3; /* JCQTBL3 */
volatile uint8_t dummy152[63]; /* */
/* end of struct st_jcu_from_jcqtbl0 */
volatile uint8_t JCHTBD0; /* JCHTBD0 */
volatile uint8_t dummy153[31]; /* */
volatile uint8_t JCHTBA0; /* JCHTBA0 */
volatile uint8_t dummy154[223]; /* */
volatile uint8_t JCHTBD1; /* JCHTBD1 */
volatile uint8_t dummy155[31]; /* */
volatile uint8_t JCHTBA1; /* JCHTBA1 */
};
struct st_jcu_from_jcqtbl0
{
volatile uint8_t JCQTBL0; /* JCQTBL0 */
volatile uint8_t dummy1[63]; /* */
};
#define JCU (*(struct st_jcu *)0xE8017000uL) /* JCU */
/* Start of channnel array defines of JCU */
/* Channnel array defines of JCU_JCQTBL0 */
/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */
#define JCU_JCQTBL0_COUNT 4
#define JCU_JCQTBL0_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */
#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */
#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */
#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */
/* End of channnel array defines of JCU */
#define JCUJCMOD JCU.JCMOD
#define JCUJCCMD JCU.JCCMD
#define JCUJCQTN JCU.JCQTN
#define JCUJCHTN JCU.JCHTN
#define JCUJCDRIU JCU.JCDRIU
#define JCUJCDRID JCU.JCDRID
#define JCUJCVSZU JCU.JCVSZU
#define JCUJCVSZD JCU.JCVSZD
#define JCUJCHSZU JCU.JCHSZU
#define JCUJCHSZD JCU.JCHSZD
#define JCUJCDTCU JCU.JCDTCU
#define JCUJCDTCM JCU.JCDTCM
#define JCUJCDTCD JCU.JCDTCD
#define JCUJINTE0 JCU.JINTE0
#define JCUJINTS0 JCU.JINTS0
#define JCUJCDERR JCU.JCDERR
#define JCUJCRST JCU.JCRST
#define JCUJIFECNT JCU.JIFECNT
#define JCUJIFESA JCU.JIFESA
#define JCUJIFESOFST JCU.JIFESOFST
#define JCUJIFEDA JCU.JIFEDA
#define JCUJIFESLC JCU.JIFESLC
#define JCUJIFEDDC JCU.JIFEDDC
#define JCUJIFDCNT JCU.JIFDCNT
#define JCUJIFDSA JCU.JIFDSA
#define JCUJIFDDOFST JCU.JIFDDOFST
#define JCUJIFDDA JCU.JIFDDA
#define JCUJIFDSDC JCU.JIFDSDC
#define JCUJIFDDLC JCU.JIFDDLC
#define JCUJIFDADT JCU.JIFDADT
#define JCUJINTE1 JCU.JINTE1
#define JCUJINTS1 JCU.JINTS1
#define JCUJIFESVSZ JCU.JIFESVSZ
#define JCUJIFESHSZ JCU.JIFESHSZ
#define JCUJCQTBL0 JCU.JCQTBL0
#define JCUJCQTBL1 JCU.JCQTBL1
#define JCUJCQTBL2 JCU.JCQTBL2
#define JCUJCQTBL3 JCU.JCQTBL3
#define JCUJCHTBD0 JCU.JCHTBD0
#define JCUJCHTBA0 JCU.JCHTBA0
#define JCUJCHTBD1 JCU.JCHTBD1
#define JCUJCHTBA1 JCU.JCHTBA1
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : l2c_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef L2C_IODEFINE_H
#define L2C_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_l2c
{ /* L2C */
volatile uint32_t REG0_CACHE_ID; /* REG0_CACHE_ID */
volatile uint32_t REG0_CACHE_TYPE; /* REG0_CACHE_TYPE */
volatile uint8_t dummy8[248]; /* */
volatile uint32_t REG1_CONTROL; /* REG1_CONTROL */
volatile uint32_t REG1_AUX_CONTROL; /* REG1_AUX_CONTROL */
volatile uint32_t REG1_TAG_RAM_CONTROL; /* REG1_TAG_RAM_CONTROL */
volatile uint32_t REG1_DATA_RAM_CONTROL; /* REG1_DATA_RAM_CONTROL */
volatile uint8_t dummy9[240]; /* */
volatile uint32_t REG2_EV_COUNTER_CTRL; /* REG2_EV_COUNTER_CTRL */
volatile uint32_t REG2_EV_COUNTER1_CFG; /* REG2_EV_COUNTER1_CFG */
volatile uint32_t REG2_EV_COUNTER0_CFG; /* REG2_EV_COUNTER0_CFG */
volatile uint32_t REG2_EV_COUNTER1; /* REG2_EV_COUNTER1 */
volatile uint32_t REG2_EV_COUNTER0; /* REG2_EV_COUNTER0 */
volatile uint32_t REG2_INT_MASK; /* REG2_INT_MASK */
volatile uint32_t REG2_INT_MASK_STATUS; /* REG2_INT_MASK_STATUS */
volatile uint32_t REG2_INT_RAW_STATUS; /* REG2_INT_RAW_STATUS */
volatile uint32_t REG2_INT_CLEAR; /* REG2_INT_CLEAR */
volatile uint8_t dummy10[1292]; /* */
volatile uint32_t REG7_CACHE_SYNC; /* REG7_CACHE_SYNC */
volatile uint8_t dummy11[60]; /* */
volatile uint32_t REG7_INV_PA; /* REG7_INV_PA */
volatile uint8_t dummy12[8]; /* */
volatile uint32_t REG7_INV_WAY; /* REG7_INV_WAY */
volatile uint8_t dummy13[48]; /* */
volatile uint32_t REG7_CLEAN_PA; /* REG7_CLEAN_PA */
volatile uint8_t dummy14[4]; /* */
volatile uint32_t REG7_CLEAN_INDEX; /* REG7_CLEAN_INDEX */
volatile uint32_t REG7_CLEAN_WAY; /* REG7_CLEAN_WAY */
volatile uint8_t dummy15[48]; /* */
volatile uint32_t REG7_CLEAN_INV_PA; /* REG7_CLEAN_INV_PA */
volatile uint8_t dummy16[4]; /* */
volatile uint32_t REG7_CLEAN_INV_INDEX; /* REG7_CLEAN_INV_INDEX */
volatile uint32_t REG7_CLEAN_INV_WAY; /* REG7_CLEAN_INV_WAY */
volatile uint8_t dummy17[256]; /* */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */
volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN1; /* REG9_D_LOCKDOWN1 */
volatile uint32_t REG9_I_LOCKDOWN1; /* REG9_I_LOCKDOWN1 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN2; /* REG9_D_LOCKDOWN2 */
volatile uint32_t REG9_I_LOCKDOWN2; /* REG9_I_LOCKDOWN2 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN3; /* REG9_D_LOCKDOWN3 */
volatile uint32_t REG9_I_LOCKDOWN3; /* REG9_I_LOCKDOWN3 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN4; /* REG9_D_LOCKDOWN4 */
volatile uint32_t REG9_I_LOCKDOWN4; /* REG9_I_LOCKDOWN4 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN5; /* REG9_D_LOCKDOWN5 */
volatile uint32_t REG9_I_LOCKDOWN5; /* REG9_I_LOCKDOWN5 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN6; /* REG9_D_LOCKDOWN6 */
volatile uint32_t REG9_I_LOCKDOWN6; /* REG9_I_LOCKDOWN6 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN7; /* REG9_D_LOCKDOWN7 */
volatile uint32_t REG9_I_LOCKDOWN7; /* REG9_I_LOCKDOWN7 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint8_t dummy18[16]; /* */
volatile uint32_t REG9_LOCK_LINE_EN; /* REG9_LOCK_LINE_EN */
volatile uint32_t REG9_UNLOCK_WAY; /* REG9_UNLOCK_WAY */
volatile uint8_t dummy19[680]; /* */
volatile uint32_t REG12_ADDR_FILTERING_START; /* REG12_ADDR_FILTERING_START */
volatile uint32_t REG12_ADDR_FILTERING_END; /* REG12_ADDR_FILTERING_END */
volatile uint8_t dummy20[824]; /* */
volatile uint32_t REG15_DEBUG_CTRL; /* REG15_DEBUG_CTRL */
volatile uint8_t dummy21[28]; /* */
volatile uint32_t REG15_PREFETCH_CTRL; /* REG15_PREFETCH_CTRL */
volatile uint8_t dummy22[28]; /* */
volatile uint32_t REG15_POWER_CTRL; /* REG15_POWER_CTRL */
};
struct st_l2c_from_reg9_d_lockdown0
{
volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */
volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */
};
#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */
/* Start of channnel array defines of L2C */
/* Channnel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */
/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */
#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT 8
#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */
#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */
#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */
#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */
#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */
#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */
#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */
#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */
/* End of channnel array defines of L2C */
#define L2CREG0_CACHE_ID L2C.REG0_CACHE_ID
#define L2CREG0_CACHE_TYPE L2C.REG0_CACHE_TYPE
#define L2CREG1_CONTROL L2C.REG1_CONTROL
#define L2CREG1_AUX_CONTROL L2C.REG1_AUX_CONTROL
#define L2CREG1_TAG_RAM_CONTROL L2C.REG1_TAG_RAM_CONTROL
#define L2CREG1_DATA_RAM_CONTROL L2C.REG1_DATA_RAM_CONTROL
#define L2CREG2_EV_COUNTER_CTRL L2C.REG2_EV_COUNTER_CTRL
#define L2CREG2_EV_COUNTER1_CFG L2C.REG2_EV_COUNTER1_CFG
#define L2CREG2_EV_COUNTER0_CFG L2C.REG2_EV_COUNTER0_CFG
#define L2CREG2_EV_COUNTER1 L2C.REG2_EV_COUNTER1
#define L2CREG2_EV_COUNTER0 L2C.REG2_EV_COUNTER0
#define L2CREG2_INT_MASK L2C.REG2_INT_MASK
#define L2CREG2_INT_MASK_STATUS L2C.REG2_INT_MASK_STATUS
#define L2CREG2_INT_RAW_STATUS L2C.REG2_INT_RAW_STATUS
#define L2CREG2_INT_CLEAR L2C.REG2_INT_CLEAR
#define L2CREG7_CACHE_SYNC L2C.REG7_CACHE_SYNC
#define L2CREG7_INV_PA L2C.REG7_INV_PA
#define L2CREG7_INV_WAY L2C.REG7_INV_WAY
#define L2CREG7_CLEAN_PA L2C.REG7_CLEAN_PA
#define L2CREG7_CLEAN_INDEX L2C.REG7_CLEAN_INDEX
#define L2CREG7_CLEAN_WAY L2C.REG7_CLEAN_WAY
#define L2CREG7_CLEAN_INV_PA L2C.REG7_CLEAN_INV_PA
#define L2CREG7_CLEAN_INV_INDEX L2C.REG7_CLEAN_INV_INDEX
#define L2CREG7_CLEAN_INV_WAY L2C.REG7_CLEAN_INV_WAY
#define L2CREG9_D_LOCKDOWN0 L2C.REG9_D_LOCKDOWN0
#define L2CREG9_I_LOCKDOWN0 L2C.REG9_I_LOCKDOWN0
#define L2CREG9_D_LOCKDOWN1 L2C.REG9_D_LOCKDOWN1
#define L2CREG9_I_LOCKDOWN1 L2C.REG9_I_LOCKDOWN1
#define L2CREG9_D_LOCKDOWN2 L2C.REG9_D_LOCKDOWN2
#define L2CREG9_I_LOCKDOWN2 L2C.REG9_I_LOCKDOWN2
#define L2CREG9_D_LOCKDOWN3 L2C.REG9_D_LOCKDOWN3
#define L2CREG9_I_LOCKDOWN3 L2C.REG9_I_LOCKDOWN3
#define L2CREG9_D_LOCKDOWN4 L2C.REG9_D_LOCKDOWN4
#define L2CREG9_I_LOCKDOWN4 L2C.REG9_I_LOCKDOWN4
#define L2CREG9_D_LOCKDOWN5 L2C.REG9_D_LOCKDOWN5
#define L2CREG9_I_LOCKDOWN5 L2C.REG9_I_LOCKDOWN5
#define L2CREG9_D_LOCKDOWN6 L2C.REG9_D_LOCKDOWN6
#define L2CREG9_I_LOCKDOWN6 L2C.REG9_I_LOCKDOWN6
#define L2CREG9_D_LOCKDOWN7 L2C.REG9_D_LOCKDOWN7
#define L2CREG9_I_LOCKDOWN7 L2C.REG9_I_LOCKDOWN7
#define L2CREG9_LOCK_LINE_EN L2C.REG9_LOCK_LINE_EN
#define L2CREG9_UNLOCK_WAY L2C.REG9_UNLOCK_WAY
#define L2CREG12_ADDR_FILTERING_START L2C.REG12_ADDR_FILTERING_START
#define L2CREG12_ADDR_FILTERING_END L2C.REG12_ADDR_FILTERING_END
#define L2CREG15_DEBUG_CTRL L2C.REG15_DEBUG_CTRL
#define L2CREG15_PREFETCH_CTRL L2C.REG15_PREFETCH_CTRL
#define L2CREG15_POWER_CTRL L2C.REG15_POWER_CTRL
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : lin_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef LIN_IODEFINE_H
#define LIN_IODEFINE_H
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_lin
{ /* LIN */
volatile uint8_t dummy1[1]; /* */
volatile uint8_t RLN3nLWBR; /* RLN3nLWBR */
union iodefine_reg16_8_t RLN3nLBRP01; /* RLN3nLBRP01 */
volatile uint8_t RLN3nLSTC; /* RLN3nLSTC */
volatile uint8_t dummy2[3]; /* */
volatile uint8_t RLN3nLMD; /* RLN3nLMD */
volatile uint8_t RLN3nLBFC; /* RLN3nLBFC */
volatile uint8_t RLN3nLSC; /* RLN3nLSC */
volatile uint8_t RLN3nLWUP; /* RLN3nLWUP */
volatile uint8_t RLN3nLIE; /* RLN3nLIE */
volatile uint8_t RLN3nLEDE; /* RLN3nLEDE */
volatile uint8_t RLN3nLCUC; /* RLN3nLCUC */
volatile uint8_t dummy3[1]; /* */
volatile uint8_t RLN3nLTRC; /* RLN3nLTRC */
volatile uint8_t RLN3nLMST; /* RLN3nLMST */
volatile uint8_t RLN3nLST; /* RLN3nLST */
volatile uint8_t RLN3nLEST; /* RLN3nLEST */
volatile uint8_t RLN3nLDFC; /* RLN3nLDFC */
volatile uint8_t RLN3nLIDB; /* RLN3nLIDB */
volatile uint8_t RLN3nLCBR; /* RLN3nLCBR */
volatile uint8_t RLN3nLUDB0; /* RLN3nLUDB0 */
#define LIN_LDBn_COUNT 8
volatile uint8_t RLN3nLDBR1; /* RLN3nLDBR1 */
volatile uint8_t RLN3nLDBR2; /* RLN3nLDBR2 */
volatile uint8_t RLN3nLDBR3; /* RLN3nLDBR3 */
volatile uint8_t RLN3nLDBR4; /* RLN3nLDBR4 */
volatile uint8_t RLN3nLDBR5; /* RLN3nLDBR5 */
volatile uint8_t RLN3nLDBR6; /* RLN3nLDBR6 */
volatile uint8_t RLN3nLDBR7; /* RLN3nLDBR7 */
volatile uint8_t RLN3nLDBR8; /* RLN3nLDBR8 */
volatile uint8_t RLN3nLUOER; /* RLN3nLUOER */
volatile uint8_t RLN3nLUOR1; /* RLN3nLUOR1 */
volatile uint8_t dummy4[2]; /* */
union iodefine_reg16_8_t RLN3nLUTDR; /* RLN3nLUTDR */
union iodefine_reg16_8_t RLN3nLURDR; /* RLN3nLURDR */
union iodefine_reg16_8_t RLN3nLUWTDR; /* RLN3nLUWTDR */
};
#define LIN0 (*(struct st_lin *)0xFCFE9000uL) /* LIN0 */
#define LIN1 (*(struct st_lin *)0xFCFE9800uL) /* LIN1 */
/* Start of channnel array defines of LIN */
/* Channnel array defines of LIN */
/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */
#define LIN_COUNT 2
#define LIN_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&LIN0, &LIN1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of LIN */
#define LIN0RLN30LWBR LIN0.RLN3nLWBR
#define LIN0RLN30LBRP01 LIN0.RLN3nLBRP01.UINT16
#define LIN0RLN30LBRP0 LIN0.RLN3nLBRP01.UINT8[L]
#define LIN0RLN30LBRP1 LIN0.RLN3nLBRP01.UINT8[H]
#define LIN0RLN30LSTC LIN0.RLN3nLSTC
#define LIN0RLN30LMD LIN0.RLN3nLMD
#define LIN0RLN30LBFC LIN0.RLN3nLBFC
#define LIN0RLN30LSC LIN0.RLN3nLSC
#define LIN0RLN30LWUP LIN0.RLN3nLWUP
#define LIN0RLN30LIE LIN0.RLN3nLIE
#define LIN0RLN30LEDE LIN0.RLN3nLEDE
#define LIN0RLN30LCUC LIN0.RLN3nLCUC
#define LIN0RLN30LTRC LIN0.RLN3nLTRC
#define LIN0RLN30LMST LIN0.RLN3nLMST
#define LIN0RLN30LST LIN0.RLN3nLST
#define LIN0RLN30LEST LIN0.RLN3nLEST
#define LIN0RLN30LDFC LIN0.RLN3nLDFC
#define LIN0RLN30LIDB LIN0.RLN3nLIDB
#define LIN0RLN30LCBR LIN0.RLN3nLCBR
#define LIN0RLN30LUDB0 LIN0.RLN3nLUDB0
#define LIN0RLN30LDBR1 LIN0.RLN3nLDBR1
#define LIN0RLN30LDBR2 LIN0.RLN3nLDBR2
#define LIN0RLN30LDBR3 LIN0.RLN3nLDBR3
#define LIN0RLN30LDBR4 LIN0.RLN3nLDBR4
#define LIN0RLN30LDBR5 LIN0.RLN3nLDBR5
#define LIN0RLN30LDBR6 LIN0.RLN3nLDBR6
#define LIN0RLN30LDBR7 LIN0.RLN3nLDBR7
#define LIN0RLN30LDBR8 LIN0.RLN3nLDBR8
#define LIN0RLN30LUOER LIN0.RLN3nLUOER
#define LIN0RLN30LUOR1 LIN0.RLN3nLUOR1
#define LIN0RLN30LUTDR LIN0.RLN3nLUTDR.UINT16
#define LIN0RLN30LUTDRL LIN0.RLN3nLUTDR.UINT8[L]
#define LIN0RLN30LUTDRH LIN0.RLN3nLUTDR.UINT8[H]
#define LIN0RLN30LURDR LIN0.RLN3nLURDR.UINT16
#define LIN0RLN30LURDRL LIN0.RLN3nLURDR.UINT8[L]
#define LIN0RLN30LURDRH LIN0.RLN3nLURDR.UINT8[H]
#define LIN0RLN30LUWTDR LIN0.RLN3nLUWTDR.UINT16
#define LIN0RLN30LUWTDRL LIN0.RLN3nLUWTDR.UINT8[L]
#define LIN0RLN30LUWTDRH LIN0.RLN3nLUWTDR.UINT8[H]
#define LIN1RLN31LWBR LIN1.RLN3nLWBR
#define LIN1RLN31LBRP01 LIN1.RLN3nLBRP01.UINT16
#define LIN1RLN31LBRP0 LIN1.RLN3nLBRP01.UINT8[L]
#define LIN1RLN31LBRP1 LIN1.RLN3nLBRP01.UINT8[H]
#define LIN1RLN31LSTC LIN1.RLN3nLSTC
#define LIN1RLN31LMD LIN1.RLN3nLMD
#define LIN1RLN31LBFC LIN1.RLN3nLBFC
#define LIN1RLN31LSC LIN1.RLN3nLSC
#define LIN1RLN31LWUP LIN1.RLN3nLWUP
#define LIN1RLN31LIE LIN1.RLN3nLIE
#define LIN1RLN31LEDE LIN1.RLN3nLEDE
#define LIN1RLN31LCUC LIN1.RLN3nLCUC
#define LIN1RLN31LTRC LIN1.RLN3nLTRC
#define LIN1RLN31LMST LIN1.RLN3nLMST
#define LIN1RLN31LST LIN1.RLN3nLST
#define LIN1RLN31LEST LIN1.RLN3nLEST
#define LIN1RLN31LDFC LIN1.RLN3nLDFC
#define LIN1RLN31LIDB LIN1.RLN3nLIDB
#define LIN1RLN31LCBR LIN1.RLN3nLCBR
#define LIN1RLN31LUDB0 LIN1.RLN3nLUDB0
#define LIN1RLN31LDBR1 LIN1.RLN3nLDBR1
#define LIN1RLN31LDBR2 LIN1.RLN3nLDBR2
#define LIN1RLN31LDBR3 LIN1.RLN3nLDBR3
#define LIN1RLN31LDBR4 LIN1.RLN3nLDBR4
#define LIN1RLN31LDBR5 LIN1.RLN3nLDBR5
#define LIN1RLN31LDBR6 LIN1.RLN3nLDBR6
#define LIN1RLN31LDBR7 LIN1.RLN3nLDBR7
#define LIN1RLN31LDBR8 LIN1.RLN3nLDBR8
#define LIN1RLN31LUOER LIN1.RLN3nLUOER
#define LIN1RLN31LUOR1 LIN1.RLN3nLUOR1
#define LIN1RLN31LUTDR LIN1.RLN3nLUTDR.UINT16
#define LIN1RLN31LUTDRL LIN1.RLN3nLUTDR.UINT8[L]
#define LIN1RLN31LUTDRH LIN1.RLN3nLUTDR.UINT8[H]
#define LIN1RLN31LURDR LIN1.RLN3nLURDR.UINT16
#define LIN1RLN31LURDRL LIN1.RLN3nLURDR.UINT8[L]
#define LIN1RLN31LURDRH LIN1.RLN3nLURDR.UINT8[H]
#define LIN1RLN31LUWTDR LIN1.RLN3nLUWTDR.UINT16
#define LIN1RLN31LUWTDRL LIN1.RLN3nLUWTDR.UINT8[L]
#define LIN1RLN31LUWTDRH LIN1.RLN3nLUWTDR.UINT8[H]
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
#endif

53
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : lvds_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef LVDS_IODEFINE_H
#define LVDS_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_lvds
{ /* LVDS */
volatile uint32_t LVDS_UPDATE; /* LVDS_UPDATE */
volatile uint32_t LVDSFCL; /* LVDSFCL */
volatile uint8_t dummy608[24]; /* */
volatile uint32_t LCLKSELR; /* LCLKSELR */
volatile uint32_t LPLLSETR; /* LPLLSETR */
volatile uint32_t LPLLMONR; /* LPLLMONR */
};
#define LVDS (*(struct st_lvds *)0xFCFF7A30uL) /* LVDS */
#define LVDSLVDS_UPDATE LVDS.LVDS_UPDATE
#define LVDSLVDSFCL LVDS.LVDSFCL
#define LVDSLCLKSELR LVDS.LCLKSELR
#define LVDSLPLLSETR LVDS.LPLLSETR
#define LVDSLPLLMONR LVDS.LPLLMONR
/* <-SEC M1.10.1 */
#endif

498
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : mlb_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef MLB_IODEFINE_H
#define MLB_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->SEC M1.10.1 : Not magic number */
struct st_mlb
{ /* MLB */
volatile uint32_t DCCR; /* DCCR */
volatile uint32_t SSCR; /* SSCR */
volatile uint32_t SDCR; /* SDCR */
volatile uint32_t SMCR; /* SMCR */
volatile uint8_t dummy156[12]; /* */
volatile uint32_t VCCR; /* VCCR */
volatile uint32_t SBCR; /* SBCR */
volatile uint32_t ABCR; /* ABCR */
volatile uint32_t CBCR; /* CBCR */
volatile uint32_t IBCR; /* IBCR */
volatile uint32_t CICR; /* CICR */
volatile uint8_t dummy157[12]; /* */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR0; /* CECR0 */
volatile uint32_t CSCR0; /* CSCR0 */
volatile uint32_t CCBCR0; /* CCBCR0 */
volatile uint32_t CNBCR0; /* CNBCR0 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR1; /* CECR1 */
volatile uint32_t CSCR1; /* CSCR1 */
volatile uint32_t CCBCR1; /* CCBCR1 */
volatile uint32_t CNBCR1; /* CNBCR1 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR2; /* CECR2 */
volatile uint32_t CSCR2; /* CSCR2 */
volatile uint32_t CCBCR2; /* CCBCR2 */
volatile uint32_t CNBCR2; /* CNBCR2 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR3; /* CECR3 */
volatile uint32_t CSCR3; /* CSCR3 */
volatile uint32_t CCBCR3; /* CCBCR3 */
volatile uint32_t CNBCR3; /* CNBCR3 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR4; /* CECR4 */
volatile uint32_t CSCR4; /* CSCR4 */
volatile uint32_t CCBCR4; /* CCBCR4 */
volatile uint32_t CNBCR4; /* CNBCR4 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR5; /* CECR5 */
volatile uint32_t CSCR5; /* CSCR5 */
volatile uint32_t CCBCR5; /* CCBCR5 */
volatile uint32_t CNBCR5; /* CNBCR5 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR6; /* CECR6 */
volatile uint32_t CSCR6; /* CSCR6 */
volatile uint32_t CCBCR6; /* CCBCR6 */
volatile uint32_t CNBCR6; /* CNBCR6 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR7; /* CECR7 */
volatile uint32_t CSCR7; /* CSCR7 */
volatile uint32_t CCBCR7; /* CCBCR7 */
volatile uint32_t CNBCR7; /* CNBCR7 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR8; /* CECR8 */
volatile uint32_t CSCR8; /* CSCR8 */
volatile uint32_t CCBCR8; /* CCBCR8 */
volatile uint32_t CNBCR8; /* CNBCR8 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR9; /* CECR9 */
volatile uint32_t CSCR9; /* CSCR9 */
volatile uint32_t CCBCR9; /* CCBCR9 */
volatile uint32_t CNBCR9; /* CNBCR9 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR10; /* CECR10 */
volatile uint32_t CSCR10; /* CSCR10 */
volatile uint32_t CCBCR10; /* CCBCR10 */
volatile uint32_t CNBCR10; /* CNBCR10 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR11; /* CECR11 */
volatile uint32_t CSCR11; /* CSCR11 */
volatile uint32_t CCBCR11; /* CCBCR11 */
volatile uint32_t CNBCR11; /* CNBCR11 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR12; /* CECR12 */
volatile uint32_t CSCR12; /* CSCR12 */
volatile uint32_t CCBCR12; /* CCBCR12 */
volatile uint32_t CNBCR12; /* CNBCR12 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR13; /* CECR13 */
volatile uint32_t CSCR13; /* CSCR13 */
volatile uint32_t CCBCR13; /* CCBCR13 */
volatile uint32_t CNBCR13; /* CNBCR13 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR14; /* CECR14 */
volatile uint32_t CSCR14; /* CSCR14 */
volatile uint32_t CCBCR14; /* CCBCR14 */
volatile uint32_t CNBCR14; /* CNBCR14 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR15; /* CECR15 */
volatile uint32_t CSCR15; /* CSCR15 */
volatile uint32_t CCBCR15; /* CCBCR15 */
volatile uint32_t CNBCR15; /* CNBCR15 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR16; /* CECR16 */
volatile uint32_t CSCR16; /* CSCR16 */
volatile uint32_t CCBCR16; /* CCBCR16 */
volatile uint32_t CNBCR16; /* CNBCR16 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR17; /* CECR17 */
volatile uint32_t CSCR17; /* CSCR17 */
volatile uint32_t CCBCR17; /* CCBCR17 */
volatile uint32_t CNBCR17; /* CNBCR17 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR18; /* CECR18 */
volatile uint32_t CSCR18; /* CSCR18 */
volatile uint32_t CCBCR18; /* CCBCR18 */
volatile uint32_t CNBCR18; /* CNBCR18 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR19; /* CECR19 */
volatile uint32_t CSCR19; /* CSCR19 */
volatile uint32_t CCBCR19; /* CCBCR19 */
volatile uint32_t CNBCR19; /* CNBCR19 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR20; /* CECR20 */
volatile uint32_t CSCR20; /* CSCR20 */
volatile uint32_t CCBCR20; /* CCBCR20 */
volatile uint32_t CNBCR20; /* CNBCR20 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR21; /* CECR21 */
volatile uint32_t CSCR21; /* CSCR21 */
volatile uint32_t CCBCR21; /* CCBCR21 */
volatile uint32_t CNBCR21; /* CNBCR21 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR22; /* CECR22 */
volatile uint32_t CSCR22; /* CSCR22 */
volatile uint32_t CCBCR22; /* CCBCR22 */
volatile uint32_t CNBCR22; /* CNBCR22 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR23; /* CECR23 */
volatile uint32_t CSCR23; /* CSCR23 */
volatile uint32_t CCBCR23; /* CCBCR23 */
volatile uint32_t CNBCR23; /* CNBCR23 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR24; /* CECR24 */
volatile uint32_t CSCR24; /* CSCR24 */
volatile uint32_t CCBCR24; /* CCBCR24 */
volatile uint32_t CNBCR24; /* CNBCR24 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR25; /* CECR25 */
volatile uint32_t CSCR25; /* CSCR25 */
volatile uint32_t CCBCR25; /* CCBCR25 */
volatile uint32_t CNBCR25; /* CNBCR25 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR26; /* CECR26 */
volatile uint32_t CSCR26; /* CSCR26 */
volatile uint32_t CCBCR26; /* CCBCR26 */
volatile uint32_t CNBCR26; /* CNBCR26 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR27; /* CECR27 */
volatile uint32_t CSCR27; /* CSCR27 */
volatile uint32_t CCBCR27; /* CCBCR27 */
volatile uint32_t CNBCR27; /* CNBCR27 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR28; /* CECR28 */
volatile uint32_t CSCR28; /* CSCR28 */
volatile uint32_t CCBCR28; /* CCBCR28 */
volatile uint32_t CNBCR28; /* CNBCR28 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR29; /* CECR29 */
volatile uint32_t CSCR29; /* CSCR29 */
volatile uint32_t CCBCR29; /* CCBCR29 */
volatile uint32_t CNBCR29; /* CNBCR29 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR30; /* CECR30 */
volatile uint32_t CSCR30; /* CSCR30 */
volatile uint32_t CCBCR30; /* CCBCR30 */
volatile uint32_t CNBCR30; /* CNBCR30 */
/* end of struct st_mlb_from_cecr0 */
volatile uint8_t dummy158[80]; /* */
#define MLB_LCBCR0_COUNT 31
volatile uint32_t LCBCR0; /* LCBCR0 */
volatile uint32_t LCBCR1; /* LCBCR1 */
volatile uint32_t LCBCR2; /* LCBCR2 */
volatile uint32_t LCBCR3; /* LCBCR3 */
volatile uint32_t LCBCR4; /* LCBCR4 */
volatile uint32_t LCBCR5; /* LCBCR5 */
volatile uint32_t LCBCR6; /* LCBCR6 */
volatile uint32_t LCBCR7; /* LCBCR7 */
volatile uint32_t LCBCR8; /* LCBCR8 */
volatile uint32_t LCBCR9; /* LCBCR9 */
volatile uint32_t LCBCR10; /* LCBCR10 */
volatile uint32_t LCBCR11; /* LCBCR11 */
volatile uint32_t LCBCR12; /* LCBCR12 */
volatile uint32_t LCBCR13; /* LCBCR13 */
volatile uint32_t LCBCR14; /* LCBCR14 */
volatile uint32_t LCBCR15; /* LCBCR15 */
volatile uint32_t LCBCR16; /* LCBCR16 */
volatile uint32_t LCBCR17; /* LCBCR17 */
volatile uint32_t LCBCR18; /* LCBCR18 */
volatile uint32_t LCBCR19; /* LCBCR19 */
volatile uint32_t LCBCR20; /* LCBCR20 */
volatile uint32_t LCBCR21; /* LCBCR21 */
volatile uint32_t LCBCR22; /* LCBCR22 */
volatile uint32_t LCBCR23; /* LCBCR23 */
volatile uint32_t LCBCR24; /* LCBCR24 */
volatile uint32_t LCBCR25; /* LCBCR25 */
volatile uint32_t LCBCR26; /* LCBCR26 */
volatile uint32_t LCBCR27; /* LCBCR27 */
volatile uint32_t LCBCR28; /* LCBCR28 */
volatile uint32_t LCBCR29; /* LCBCR29 */
volatile uint32_t LCBCR30; /* LCBCR30 */
};
struct st_mlb_from_cecr0
{
volatile uint32_t CECR0; /* CECR0 */
volatile uint32_t CSCR0; /* CSCR0 */
volatile uint32_t CCBCR0; /* CCBCR0 */
volatile uint32_t CNBCR0; /* CNBCR0 */
};
#define MLB (*(struct st_mlb *)0xE8034000uL) /* MLB */
/* Start of channnel array defines of MLB */
/* Channnel array defines of MLB_FROM_CECR0_ARRAY */
/*(Sample) value = MLB_FROM_CECR0_ARRAY[ channel ]->CECR0; */
#define MLB_FROM_CECR0_ARRAY_COUNT 31
#define MLB_FROM_CECR0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&MLB_FROM_CECR0, &MLB_FROM_CECR1, &MLB_FROM_CECR2, &MLB_FROM_CECR3, &MLB_FROM_CECR4, &MLB_FROM_CECR5, &MLB_FROM_CECR6, &MLB_FROM_CECR7, \
&MLB_FROM_CECR8, &MLB_FROM_CECR9, &MLB_FROM_CECR10, &MLB_FROM_CECR11, &MLB_FROM_CECR12, &MLB_FROM_CECR13, &MLB_FROM_CECR14, &MLB_FROM_CECR15, \
&MLB_FROM_CECR16, &MLB_FROM_CECR17, &MLB_FROM_CECR18, &MLB_FROM_CECR19, &MLB_FROM_CECR20, &MLB_FROM_CECR21, &MLB_FROM_CECR22, &MLB_FROM_CECR23, \
&MLB_FROM_CECR24, &MLB_FROM_CECR25, &MLB_FROM_CECR26, &MLB_FROM_CECR27, &MLB_FROM_CECR28, &MLB_FROM_CECR29, &MLB_FROM_CECR30 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define MLB_FROM_CECR0 (*(struct st_mlb_from_cecr0 *)&MLB.CECR0) /* MLB_FROM_CECR0 */
#define MLB_FROM_CECR1 (*(struct st_mlb_from_cecr0 *)&MLB.CECR1) /* MLB_FROM_CECR1 */
#define MLB_FROM_CECR2 (*(struct st_mlb_from_cecr0 *)&MLB.CECR2) /* MLB_FROM_CECR2 */
#define MLB_FROM_CECR3 (*(struct st_mlb_from_cecr0 *)&MLB.CECR3) /* MLB_FROM_CECR3 */
#define MLB_FROM_CECR4 (*(struct st_mlb_from_cecr0 *)&MLB.CECR4) /* MLB_FROM_CECR4 */
#define MLB_FROM_CECR5 (*(struct st_mlb_from_cecr0 *)&MLB.CECR5) /* MLB_FROM_CECR5 */
#define MLB_FROM_CECR6 (*(struct st_mlb_from_cecr0 *)&MLB.CECR6) /* MLB_FROM_CECR6 */
#define MLB_FROM_CECR7 (*(struct st_mlb_from_cecr0 *)&MLB.CECR7) /* MLB_FROM_CECR7 */
#define MLB_FROM_CECR8 (*(struct st_mlb_from_cecr0 *)&MLB.CECR8) /* MLB_FROM_CECR8 */
#define MLB_FROM_CECR9 (*(struct st_mlb_from_cecr0 *)&MLB.CECR9) /* MLB_FROM_CECR9 */
#define MLB_FROM_CECR10 (*(struct st_mlb_from_cecr0 *)&MLB.CECR10) /* MLB_FROM_CECR10 */
#define MLB_FROM_CECR11 (*(struct st_mlb_from_cecr0 *)&MLB.CECR11) /* MLB_FROM_CECR11 */
#define MLB_FROM_CECR12 (*(struct st_mlb_from_cecr0 *)&MLB.CECR12) /* MLB_FROM_CECR12 */
#define MLB_FROM_CECR13 (*(struct st_mlb_from_cecr0 *)&MLB.CECR13) /* MLB_FROM_CECR13 */
#define MLB_FROM_CECR14 (*(struct st_mlb_from_cecr0 *)&MLB.CECR14) /* MLB_FROM_CECR14 */
#define MLB_FROM_CECR15 (*(struct st_mlb_from_cecr0 *)&MLB.CECR15) /* MLB_FROM_CECR15 */
#define MLB_FROM_CECR16 (*(struct st_mlb_from_cecr0 *)&MLB.CECR16) /* MLB_FROM_CECR16 */
#define MLB_FROM_CECR17 (*(struct st_mlb_from_cecr0 *)&MLB.CECR17) /* MLB_FROM_CECR17 */
#define MLB_FROM_CECR18 (*(struct st_mlb_from_cecr0 *)&MLB.CECR18) /* MLB_FROM_CECR18 */
#define MLB_FROM_CECR19 (*(struct st_mlb_from_cecr0 *)&MLB.CECR19) /* MLB_FROM_CECR19 */
#define MLB_FROM_CECR20 (*(struct st_mlb_from_cecr0 *)&MLB.CECR20) /* MLB_FROM_CECR20 */
#define MLB_FROM_CECR21 (*(struct st_mlb_from_cecr0 *)&MLB.CECR21) /* MLB_FROM_CECR21 */
#define MLB_FROM_CECR22 (*(struct st_mlb_from_cecr0 *)&MLB.CECR22) /* MLB_FROM_CECR22 */
#define MLB_FROM_CECR23 (*(struct st_mlb_from_cecr0 *)&MLB.CECR23) /* MLB_FROM_CECR23 */
#define MLB_FROM_CECR24 (*(struct st_mlb_from_cecr0 *)&MLB.CECR24) /* MLB_FROM_CECR24 */
#define MLB_FROM_CECR25 (*(struct st_mlb_from_cecr0 *)&MLB.CECR25) /* MLB_FROM_CECR25 */
#define MLB_FROM_CECR26 (*(struct st_mlb_from_cecr0 *)&MLB.CECR26) /* MLB_FROM_CECR26 */
#define MLB_FROM_CECR27 (*(struct st_mlb_from_cecr0 *)&MLB.CECR27) /* MLB_FROM_CECR27 */
#define MLB_FROM_CECR28 (*(struct st_mlb_from_cecr0 *)&MLB.CECR28) /* MLB_FROM_CECR28 */
#define MLB_FROM_CECR29 (*(struct st_mlb_from_cecr0 *)&MLB.CECR29) /* MLB_FROM_CECR29 */
#define MLB_FROM_CECR30 (*(struct st_mlb_from_cecr0 *)&MLB.CECR30) /* MLB_FROM_CECR30 */
/* End of channnel array defines of MLB */
#define MLBDCCR MLB.DCCR
#define MLBSSCR MLB.SSCR
#define MLBSDCR MLB.SDCR
#define MLBSMCR MLB.SMCR
#define MLBVCCR MLB.VCCR
#define MLBSBCR MLB.SBCR
#define MLBABCR MLB.ABCR
#define MLBCBCR MLB.CBCR
#define MLBIBCR MLB.IBCR
#define MLBCICR MLB.CICR
#define MLBCECR0 MLB.CECR0
#define MLBCSCR0 MLB.CSCR0
#define MLBCCBCR0 MLB.CCBCR0
#define MLBCNBCR0 MLB.CNBCR0
#define MLBCECR1 MLB.CECR1
#define MLBCSCR1 MLB.CSCR1
#define MLBCCBCR1 MLB.CCBCR1
#define MLBCNBCR1 MLB.CNBCR1
#define MLBCECR2 MLB.CECR2
#define MLBCSCR2 MLB.CSCR2
#define MLBCCBCR2 MLB.CCBCR2
#define MLBCNBCR2 MLB.CNBCR2
#define MLBCECR3 MLB.CECR3
#define MLBCSCR3 MLB.CSCR3
#define MLBCCBCR3 MLB.CCBCR3
#define MLBCNBCR3 MLB.CNBCR3
#define MLBCECR4 MLB.CECR4
#define MLBCSCR4 MLB.CSCR4
#define MLBCCBCR4 MLB.CCBCR4
#define MLBCNBCR4 MLB.CNBCR4
#define MLBCECR5 MLB.CECR5
#define MLBCSCR5 MLB.CSCR5
#define MLBCCBCR5 MLB.CCBCR5
#define MLBCNBCR5 MLB.CNBCR5
#define MLBCECR6 MLB.CECR6
#define MLBCSCR6 MLB.CSCR6
#define MLBCCBCR6 MLB.CCBCR6
#define MLBCNBCR6 MLB.CNBCR6
#define MLBCECR7 MLB.CECR7
#define MLBCSCR7 MLB.CSCR7
#define MLBCCBCR7 MLB.CCBCR7
#define MLBCNBCR7 MLB.CNBCR7
#define MLBCECR8 MLB.CECR8
#define MLBCSCR8 MLB.CSCR8
#define MLBCCBCR8 MLB.CCBCR8
#define MLBCNBCR8 MLB.CNBCR8
#define MLBCECR9 MLB.CECR9
#define MLBCSCR9 MLB.CSCR9
#define MLBCCBCR9 MLB.CCBCR9
#define MLBCNBCR9 MLB.CNBCR9
#define MLBCECR10 MLB.CECR10
#define MLBCSCR10 MLB.CSCR10
#define MLBCCBCR10 MLB.CCBCR10
#define MLBCNBCR10 MLB.CNBCR10
#define MLBCECR11 MLB.CECR11
#define MLBCSCR11 MLB.CSCR11
#define MLBCCBCR11 MLB.CCBCR11
#define MLBCNBCR11 MLB.CNBCR11
#define MLBCECR12 MLB.CECR12
#define MLBCSCR12 MLB.CSCR12
#define MLBCCBCR12 MLB.CCBCR12
#define MLBCNBCR12 MLB.CNBCR12
#define MLBCECR13 MLB.CECR13
#define MLBCSCR13 MLB.CSCR13
#define MLBCCBCR13 MLB.CCBCR13
#define MLBCNBCR13 MLB.CNBCR13
#define MLBCECR14 MLB.CECR14
#define MLBCSCR14 MLB.CSCR14
#define MLBCCBCR14 MLB.CCBCR14
#define MLBCNBCR14 MLB.CNBCR14
#define MLBCECR15 MLB.CECR15
#define MLBCSCR15 MLB.CSCR15
#define MLBCCBCR15 MLB.CCBCR15
#define MLBCNBCR15 MLB.CNBCR15
#define MLBCECR16 MLB.CECR16
#define MLBCSCR16 MLB.CSCR16
#define MLBCCBCR16 MLB.CCBCR16
#define MLBCNBCR16 MLB.CNBCR16
#define MLBCECR17 MLB.CECR17
#define MLBCSCR17 MLB.CSCR17
#define MLBCCBCR17 MLB.CCBCR17
#define MLBCNBCR17 MLB.CNBCR17
#define MLBCECR18 MLB.CECR18
#define MLBCSCR18 MLB.CSCR18
#define MLBCCBCR18 MLB.CCBCR18
#define MLBCNBCR18 MLB.CNBCR18
#define MLBCECR19 MLB.CECR19
#define MLBCSCR19 MLB.CSCR19
#define MLBCCBCR19 MLB.CCBCR19
#define MLBCNBCR19 MLB.CNBCR19
#define MLBCECR20 MLB.CECR20
#define MLBCSCR20 MLB.CSCR20
#define MLBCCBCR20 MLB.CCBCR20
#define MLBCNBCR20 MLB.CNBCR20
#define MLBCECR21 MLB.CECR21
#define MLBCSCR21 MLB.CSCR21
#define MLBCCBCR21 MLB.CCBCR21
#define MLBCNBCR21 MLB.CNBCR21
#define MLBCECR22 MLB.CECR22
#define MLBCSCR22 MLB.CSCR22
#define MLBCCBCR22 MLB.CCBCR22
#define MLBCNBCR22 MLB.CNBCR22
#define MLBCECR23 MLB.CECR23
#define MLBCSCR23 MLB.CSCR23
#define MLBCCBCR23 MLB.CCBCR23
#define MLBCNBCR23 MLB.CNBCR23
#define MLBCECR24 MLB.CECR24
#define MLBCSCR24 MLB.CSCR24
#define MLBCCBCR24 MLB.CCBCR24
#define MLBCNBCR24 MLB.CNBCR24
#define MLBCECR25 MLB.CECR25
#define MLBCSCR25 MLB.CSCR25
#define MLBCCBCR25 MLB.CCBCR25
#define MLBCNBCR25 MLB.CNBCR25
#define MLBCECR26 MLB.CECR26
#define MLBCSCR26 MLB.CSCR26
#define MLBCCBCR26 MLB.CCBCR26
#define MLBCNBCR26 MLB.CNBCR26
#define MLBCECR27 MLB.CECR27
#define MLBCSCR27 MLB.CSCR27
#define MLBCCBCR27 MLB.CCBCR27
#define MLBCNBCR27 MLB.CNBCR27
#define MLBCECR28 MLB.CECR28
#define MLBCSCR28 MLB.CSCR28
#define MLBCCBCR28 MLB.CCBCR28
#define MLBCNBCR28 MLB.CNBCR28
#define MLBCECR29 MLB.CECR29
#define MLBCSCR29 MLB.CSCR29
#define MLBCCBCR29 MLB.CCBCR29
#define MLBCNBCR29 MLB.CNBCR29
#define MLBCECR30 MLB.CECR30
#define MLBCSCR30 MLB.CSCR30
#define MLBCCBCR30 MLB.CCBCR30
#define MLBCNBCR30 MLB.CNBCR30
#define MLBLCBCR0 MLB.LCBCR0
#define MLBLCBCR1 MLB.LCBCR1
#define MLBLCBCR2 MLB.LCBCR2
#define MLBLCBCR3 MLB.LCBCR3
#define MLBLCBCR4 MLB.LCBCR4
#define MLBLCBCR5 MLB.LCBCR5
#define MLBLCBCR6 MLB.LCBCR6
#define MLBLCBCR7 MLB.LCBCR7
#define MLBLCBCR8 MLB.LCBCR8
#define MLBLCBCR9 MLB.LCBCR9
#define MLBLCBCR10 MLB.LCBCR10
#define MLBLCBCR11 MLB.LCBCR11
#define MLBLCBCR12 MLB.LCBCR12
#define MLBLCBCR13 MLB.LCBCR13
#define MLBLCBCR14 MLB.LCBCR14
#define MLBLCBCR15 MLB.LCBCR15
#define MLBLCBCR16 MLB.LCBCR16
#define MLBLCBCR17 MLB.LCBCR17
#define MLBLCBCR18 MLB.LCBCR18
#define MLBLCBCR19 MLB.LCBCR19
#define MLBLCBCR20 MLB.LCBCR20
#define MLBLCBCR21 MLB.LCBCR21
#define MLBLCBCR22 MLB.LCBCR22
#define MLBLCBCR23 MLB.LCBCR23
#define MLBLCBCR24 MLB.LCBCR24
#define MLBLCBCR25 MLB.LCBCR25
#define MLBLCBCR26 MLB.LCBCR26
#define MLBLCBCR27 MLB.LCBCR27
#define MLBLCBCR28 MLB.LCBCR28
#define MLBLCBCR29 MLB.LCBCR29
#define MLBLCBCR30 MLB.LCBCR30
/* <-SEC M1.10.1 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : mmc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef MMC_IODEFINE_H
#define MMC_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_mmc
{ /* MMC */
volatile uint16_t CE_CMD_SETH; /* CE_CMD_SETH */
volatile uint16_t CE_CMD_SETL; /* CE_CMD_SETL */
volatile uint8_t dummy182[4]; /* */
volatile uint32_t CE_ARG; /* CE_ARG */
volatile uint32_t CE_ARG_CMD12; /* CE_ARG_CMD12 */
volatile uint32_t CE_CMD_CTRL; /* CE_CMD_CTRL */
volatile uint32_t CE_BLOCK_SET; /* CE_BLOCK_SET */
volatile uint32_t CE_CLK_CTRL; /* CE_CLK_CTRL */
volatile uint32_t CE_BUF_ACC; /* CE_BUF_ACC */
#define MMC_CE_RESPn_COUNT 4
volatile uint32_t CE_RESP3; /* CE_RESP3 */
volatile uint32_t CE_RESP2; /* CE_RESP2 */
volatile uint32_t CE_RESP1; /* CE_RESP1 */
volatile uint32_t CE_RESP0; /* CE_RESP0 */
volatile uint32_t CE_RESP_CMD12; /* CE_RESP_CMD12 */
volatile uint32_t CE_DATA; /* CE_DATA */
volatile uint8_t dummy183[8]; /* */
volatile uint32_t CE_INT; /* CE_INT */
volatile uint32_t CE_INT_EN; /* CE_INT_EN */
volatile uint32_t CE_HOST_STS1; /* CE_HOST_STS1 */
volatile uint32_t CE_HOST_STS2; /* CE_HOST_STS2 */
volatile uint8_t dummy184[12]; /* */
volatile uint32_t CE_DMA_MODE; /* CE_DMA_MODE */
volatile uint8_t dummy185[16]; /* */
volatile uint32_t CE_DETECT; /* CE_DETECT */
volatile uint32_t CE_ADD_MODE; /* CE_ADD_MODE */
volatile uint8_t dummy186[4]; /* */
volatile uint32_t CE_VERSION; /* CE_VERSION */
};
#define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */
#define MMCCE_CMD_SETH MMC.CE_CMD_SETH
#define MMCCE_CMD_SETL MMC.CE_CMD_SETL
#define MMCCE_ARG MMC.CE_ARG
#define MMCCE_ARG_CMD12 MMC.CE_ARG_CMD12
#define MMCCE_CMD_CTRL MMC.CE_CMD_CTRL
#define MMCCE_BLOCK_SET MMC.CE_BLOCK_SET
#define MMCCE_CLK_CTRL MMC.CE_CLK_CTRL
#define MMCCE_BUF_ACC MMC.CE_BUF_ACC
#define MMCCE_RESP3 MMC.CE_RESP3
#define MMCCE_RESP2 MMC.CE_RESP2
#define MMCCE_RESP1 MMC.CE_RESP1
#define MMCCE_RESP0 MMC.CE_RESP0
#define MMCCE_RESP_CMD12 MMC.CE_RESP_CMD12
#define MMCCE_DATA MMC.CE_DATA
#define MMCCE_INT MMC.CE_INT
#define MMCCE_INT_EN MMC.CE_INT_EN
#define MMCCE_HOST_STS1 MMC.CE_HOST_STS1
#define MMCCE_HOST_STS2 MMC.CE_HOST_STS2
#define MMCCE_DMA_MODE MMC.CE_DMA_MODE
#define MMCCE_DETECT MMC.CE_DETECT
#define MMCCE_ADD_MODE MMC.CE_ADD_MODE
#define MMCCE_VERSION MMC.CE_VERSION
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : mtu2_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef MTU2_IODEFINE_H
#define MTU2_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_mtu2
{ /* MTU2 */
volatile uint8_t TCR_2; /* TCR_2 */
volatile uint8_t TMDR_2; /* TMDR_2 */
volatile uint8_t TIOR_2; /* TIOR_2 */
volatile uint8_t dummy520[1]; /* */
volatile uint8_t TIER_2; /* TIER_2 */
volatile uint8_t TSR_2; /* TSR_2 */
volatile uint16_t TCNT_2; /* TCNT_2 */
volatile uint16_t TGRA_2; /* TGRA_2 */
volatile uint16_t TGRB_2; /* TGRB_2 */
volatile uint8_t dummy521[500]; /* */
volatile uint8_t TCR_3; /* TCR_3 */
volatile uint8_t TCR_4; /* TCR_4 */
volatile uint8_t TMDR_3; /* TMDR_3 */
volatile uint8_t TMDR_4; /* TMDR_4 */
volatile uint8_t TIORH_3; /* TIORH_3 */
volatile uint8_t TIORL_3; /* TIORL_3 */
volatile uint8_t TIORH_4; /* TIORH_4 */
volatile uint8_t TIORL_4; /* TIORL_4 */
volatile uint8_t TIER_3; /* TIER_3 */
volatile uint8_t TIER_4; /* TIER_4 */
volatile uint8_t TOER; /* TOER */
volatile uint8_t dummy522[2]; /* */
volatile uint8_t TGCR; /* TGCR */
volatile uint8_t TOCR1; /* TOCR1 */
volatile uint8_t TOCR2; /* TOCR2 */
volatile uint16_t TCNT_3; /* TCNT_3 */
volatile uint16_t TCNT_4; /* TCNT_4 */
volatile uint16_t TCDR; /* TCDR */
volatile uint16_t TDDR; /* TDDR */
volatile uint16_t TGRA_3; /* TGRA_3 */
volatile uint16_t TGRB_3; /* TGRB_3 */
volatile uint16_t TGRA_4; /* TGRA_4 */
volatile uint16_t TGRB_4; /* TGRB_4 */
volatile uint16_t TCNTS; /* TCNTS */
volatile uint16_t TCBR; /* TCBR */
volatile uint16_t TGRC_3; /* TGRC_3 */
volatile uint16_t TGRD_3; /* TGRD_3 */
volatile uint16_t TGRC_4; /* TGRC_4 */
volatile uint16_t TGRD_4; /* TGRD_4 */
volatile uint8_t TSR_3; /* TSR_3 */
volatile uint8_t TSR_4; /* TSR_4 */
volatile uint8_t dummy523[2]; /* */
volatile uint8_t TITCR; /* TITCR */
volatile uint8_t TITCNT; /* TITCNT */
volatile uint8_t TBTER; /* TBTER */
volatile uint8_t dummy524[1]; /* */
volatile uint8_t TDER; /* TDER */
volatile uint8_t dummy525[1]; /* */
volatile uint8_t TOLBR; /* TOLBR */
volatile uint8_t dummy526[1]; /* */
volatile uint8_t TBTM_3; /* TBTM_3 */
volatile uint8_t TBTM_4; /* TBTM_4 */
volatile uint8_t dummy527[6]; /* */
volatile uint16_t TADCR; /* TADCR */
volatile uint8_t dummy528[2]; /* */
volatile uint16_t TADCORA_4; /* TADCORA_4 */
volatile uint16_t TADCORB_4; /* TADCORB_4 */
volatile uint16_t TADCOBRA_4; /* TADCOBRA_4 */
volatile uint16_t TADCOBRB_4; /* TADCOBRB_4 */
volatile uint8_t dummy529[20]; /* */
volatile uint8_t TWCR; /* TWCR */
volatile uint8_t dummy530[31]; /* */
volatile uint8_t TSTR; /* TSTR */
volatile uint8_t TSYR; /* TSYR */
volatile uint8_t dummy531[2]; /* */
volatile uint8_t TRWER; /* TRWER */
volatile uint8_t dummy532[123]; /* */
volatile uint8_t TCR_0; /* TCR_0 */
volatile uint8_t TMDR_0; /* TMDR_0 */
volatile uint8_t TIORH_0; /* TIORH_0 */
volatile uint8_t TIORL_0; /* TIORL_0 */
volatile uint8_t TIER_0; /* TIER_0 */
volatile uint8_t TSR_0; /* TSR_0 */
volatile uint16_t TCNT_0; /* TCNT_0 */
volatile uint16_t TGRA_0; /* TGRA_0 */
volatile uint16_t TGRB_0; /* TGRB_0 */
volatile uint16_t TGRC_0; /* TGRC_0 */
volatile uint16_t TGRD_0; /* TGRD_0 */
volatile uint8_t dummy533[16]; /* */
volatile uint16_t TGRE_0; /* TGRE_0 */
volatile uint16_t TGRF_0; /* TGRF_0 */
volatile uint8_t TIER2_0; /* TIER2_0 */
volatile uint8_t TSR2_0; /* TSR2_0 */
volatile uint8_t TBTM_0; /* TBTM_0 */
volatile uint8_t dummy534[89]; /* */
volatile uint8_t TCR_1; /* TCR_1 */
volatile uint8_t TMDR_1; /* TMDR_1 */
volatile uint8_t TIOR_1; /* TIOR_1 */
volatile uint8_t dummy535[1]; /* */
volatile uint8_t TIER_1; /* TIER_1 */
volatile uint8_t TSR_1; /* TSR_1 */
volatile uint16_t TCNT_1; /* TCNT_1 */
volatile uint16_t TGRA_1; /* TGRA_1 */
volatile uint16_t TGRB_1; /* TGRB_1 */
volatile uint8_t dummy536[4]; /* */
volatile uint8_t TICCR; /* TICCR */
};
#define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */
#define MTU2TCR_2 MTU2.TCR_2
#define MTU2TMDR_2 MTU2.TMDR_2
#define MTU2TIOR_2 MTU2.TIOR_2
#define MTU2TIER_2 MTU2.TIER_2
#define MTU2TSR_2 MTU2.TSR_2
#define MTU2TCNT_2 MTU2.TCNT_2
#define MTU2TGRA_2 MTU2.TGRA_2
#define MTU2TGRB_2 MTU2.TGRB_2
#define MTU2TCR_3 MTU2.TCR_3
#define MTU2TCR_4 MTU2.TCR_4
#define MTU2TMDR_3 MTU2.TMDR_3
#define MTU2TMDR_4 MTU2.TMDR_4
#define MTU2TIORH_3 MTU2.TIORH_3
#define MTU2TIORL_3 MTU2.TIORL_3
#define MTU2TIORH_4 MTU2.TIORH_4
#define MTU2TIORL_4 MTU2.TIORL_4
#define MTU2TIER_3 MTU2.TIER_3
#define MTU2TIER_4 MTU2.TIER_4
#define MTU2TOER MTU2.TOER
#define MTU2TGCR MTU2.TGCR
#define MTU2TOCR1 MTU2.TOCR1
#define MTU2TOCR2 MTU2.TOCR2
#define MTU2TCNT_3 MTU2.TCNT_3
#define MTU2TCNT_4 MTU2.TCNT_4
#define MTU2TCDR MTU2.TCDR
#define MTU2TDDR MTU2.TDDR
#define MTU2TGRA_3 MTU2.TGRA_3
#define MTU2TGRB_3 MTU2.TGRB_3
#define MTU2TGRA_4 MTU2.TGRA_4
#define MTU2TGRB_4 MTU2.TGRB_4
#define MTU2TCNTS MTU2.TCNTS
#define MTU2TCBR MTU2.TCBR
#define MTU2TGRC_3 MTU2.TGRC_3
#define MTU2TGRD_3 MTU2.TGRD_3
#define MTU2TGRC_4 MTU2.TGRC_4
#define MTU2TGRD_4 MTU2.TGRD_4
#define MTU2TSR_3 MTU2.TSR_3
#define MTU2TSR_4 MTU2.TSR_4
#define MTU2TITCR MTU2.TITCR
#define MTU2TITCNT MTU2.TITCNT
#define MTU2TBTER MTU2.TBTER
#define MTU2TDER MTU2.TDER
#define MTU2TOLBR MTU2.TOLBR
#define MTU2TBTM_3 MTU2.TBTM_3
#define MTU2TBTM_4 MTU2.TBTM_4
#define MTU2TADCR MTU2.TADCR
#define MTU2TADCORA_4 MTU2.TADCORA_4
#define MTU2TADCORB_4 MTU2.TADCORB_4
#define MTU2TADCOBRA_4 MTU2.TADCOBRA_4
#define MTU2TADCOBRB_4 MTU2.TADCOBRB_4
#define MTU2TWCR MTU2.TWCR
#define MTU2TSTR MTU2.TSTR
#define MTU2TSYR MTU2.TSYR
#define MTU2TRWER MTU2.TRWER
#define MTU2TCR_0 MTU2.TCR_0
#define MTU2TMDR_0 MTU2.TMDR_0
#define MTU2TIORH_0 MTU2.TIORH_0
#define MTU2TIORL_0 MTU2.TIORL_0
#define MTU2TIER_0 MTU2.TIER_0
#define MTU2TSR_0 MTU2.TSR_0
#define MTU2TCNT_0 MTU2.TCNT_0
#define MTU2TGRA_0 MTU2.TGRA_0
#define MTU2TGRB_0 MTU2.TGRB_0
#define MTU2TGRC_0 MTU2.TGRC_0
#define MTU2TGRD_0 MTU2.TGRD_0
#define MTU2TGRE_0 MTU2.TGRE_0
#define MTU2TGRF_0 MTU2.TGRF_0
#define MTU2TIER2_0 MTU2.TIER2_0
#define MTU2TSR2_0 MTU2.TSR2_0
#define MTU2TBTM_0 MTU2.TBTM_0
#define MTU2TCR_1 MTU2.TCR_1
#define MTU2TMDR_1 MTU2.TMDR_1
#define MTU2TIOR_1 MTU2.TIOR_1
#define MTU2TIER_1 MTU2.TIER_1
#define MTU2TSR_1 MTU2.TSR_1
#define MTU2TCNT_1 MTU2.TCNT_1
#define MTU2TGRA_1 MTU2.TGRA_1
#define MTU2TGRB_1 MTU2.TGRB_1
#define MTU2TICCR MTU2.TICCR
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ostm_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef OSTM_IODEFINE_H
#define OSTM_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_ostm
{ /* OSTM */
volatile uint32_t OSTMnCMP; /* OSTMnCMP */
volatile uint32_t OSTMnCNT; /* OSTMnCNT */
volatile uint8_t dummy1[8]; /* */
volatile uint8_t OSTMnTE; /* OSTMnTE */
volatile uint8_t dummy2[3]; /* */
volatile uint8_t OSTMnTS; /* OSTMnTS */
volatile uint8_t dummy3[3]; /* */
volatile uint8_t OSTMnTT; /* OSTMnTT */
volatile uint8_t dummy4[7]; /* */
volatile uint8_t OSTMnCTL; /* OSTMnCTL */
};
#define OSTM0 (*(struct st_ostm *)0xFCFEC000uL) /* OSTM0 */
#define OSTM1 (*(struct st_ostm *)0xFCFEC400uL) /* OSTM1 */
/* Start of channnel array defines of OSTM */
/* Channnel array defines of OSTM */
/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */
#define OSTM_COUNT 2
#define OSTM_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&OSTM0, &OSTM1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of OSTM */
#define OSTM0CMP OSTM0.OSTMnCMP
#define OSTM0CNT OSTM0.OSTMnCNT
#define OSTM0TE OSTM0.OSTMnTE
#define OSTM0TS OSTM0.OSTMnTS
#define OSTM0TT OSTM0.OSTMnTT
#define OSTM0CTL OSTM0.OSTMnCTL
#define OSTM1CMP OSTM1.OSTMnCMP
#define OSTM1CNT OSTM1.OSTMnCNT
#define OSTM1TE OSTM1.OSTMnTE
#define OSTM1TS OSTM1.OSTMnTS
#define OSTM1TT OSTM1.OSTMnTT
#define OSTM1CTL OSTM1.OSTMnCTL
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : pfv_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef PFV_IODEFINE_H
#define PFV_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_pfv
{ /* PFV */
volatile uint32_t PFVCR; /* PFVCR */
volatile uint32_t PFVICR; /* PFVICR */
volatile uint32_t PFVISR; /* PFVISR */
volatile uint8_t dummy1[20]; /* */
#define PFVID_COUNT 8
volatile uint32_t PFVID0; /* PFVID0 */
volatile uint32_t PFVID1; /* PFVID1 */
volatile uint32_t PFVID2; /* PFVID2 */
volatile uint32_t PFVID3; /* PFVID3 */
volatile uint32_t PFVID4; /* PFVID4 */
volatile uint32_t PFVID5; /* PFVID5 */
volatile uint32_t PFVID6; /* PFVID6 */
volatile uint32_t PFVID7; /* PFVID7 */
#define PFVOD_COUNT 8
volatile uint32_t PFVOD0; /* PFVOD0 */
volatile uint32_t PFVOD1; /* PFVOD1 */
volatile uint32_t PFVOD2; /* PFVOD2 */
volatile uint32_t PFVOD3; /* PFVOD3 */
volatile uint32_t PFVOD4; /* PFVOD4 */
volatile uint32_t PFVOD5; /* PFVOD5 */
volatile uint32_t PFVOD6; /* PFVOD6 */
volatile uint32_t PFVOD7; /* PFVOD7 */
volatile uint8_t dummy2[4]; /* */
volatile uint32_t PFVIFSR; /* PFVIFSR */
volatile uint32_t PFVOFSR; /* PFVOFSR */
volatile uint32_t PFVACR; /* PFVACR */
volatile uint32_t PFV_MTX_MODE; /* PFV_MTX_MODE */
volatile uint32_t PFV_MTX_YG_ADJ0; /* PFV_MTX_YG_ADJ0 */
volatile uint32_t PFV_MTX_YG_ADJ1; /* PFV_MTX_YG_ADJ1 */
volatile uint32_t PFV_MTX_CBB_ADJ0; /* PFV_MTX_CBB_ADJ0 */
volatile uint32_t PFV_MTX_CBB_ADJ1; /* PFV_MTX_CBB_ADJ1 */
volatile uint32_t PFV_MTX_CRR_ADJ0; /* PFV_MTX_CRR_ADJ0 */
volatile uint32_t PFV_MTX_CRR_ADJ1; /* PFV_MTX_CRR_ADJ1 */
volatile uint32_t PFVSZR; /* PFVSZR */
};
#define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */
#define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */
/* Start of channnel array defines of PFV */
/* Channnel array defines of PFV */
/*(Sample) value = PFV[ channel ]->PFVCR; */
#define PFV_COUNT 2
#define PFV_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&PFV0, &PFV1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of PFV */
#define PFV0PFVCR PFV0.PFVCR
#define PFV0PFVICR PFV0.PFVICR
#define PFV0PFVISR PFV0.PFVISR
#define PFV0PFVID0 PFV0.PFVID0
#define PFV0PFVID1 PFV0.PFVID1
#define PFV0PFVID2 PFV0.PFVID2
#define PFV0PFVID3 PFV0.PFVID3
#define PFV0PFVID4 PFV0.PFVID4
#define PFV0PFVID5 PFV0.PFVID5
#define PFV0PFVID6 PFV0.PFVID6
#define PFV0PFVID7 PFV0.PFVID7
#define PFV0PFVOD0 PFV0.PFVOD0
#define PFV0PFVOD1 PFV0.PFVOD1
#define PFV0PFVOD2 PFV0.PFVOD2
#define PFV0PFVOD3 PFV0.PFVOD3
#define PFV0PFVOD4 PFV0.PFVOD4
#define PFV0PFVOD5 PFV0.PFVOD5
#define PFV0PFVOD6 PFV0.PFVOD6
#define PFV0PFVOD7 PFV0.PFVOD7
#define PFV0PFVIFSR PFV0.PFVIFSR
#define PFV0PFVOFSR PFV0.PFVOFSR
#define PFV0PFVACR PFV0.PFVACR
#define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE
#define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0
#define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1
#define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0
#define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1
#define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0
#define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1
#define PFV0PFVSZR PFV0.PFVSZR
#define PFV1PFVCR PFV1.PFVCR
#define PFV1PFVICR PFV1.PFVICR
#define PFV1PFVISR PFV1.PFVISR
#define PFV1PFVID0 PFV1.PFVID0
#define PFV1PFVID1 PFV1.PFVID1
#define PFV1PFVID2 PFV1.PFVID2
#define PFV1PFVID3 PFV1.PFVID3
#define PFV1PFVID4 PFV1.PFVID4
#define PFV1PFVID5 PFV1.PFVID5
#define PFV1PFVID6 PFV1.PFVID6
#define PFV1PFVID7 PFV1.PFVID7
#define PFV1PFVOD0 PFV1.PFVOD0
#define PFV1PFVOD1 PFV1.PFVOD1
#define PFV1PFVOD2 PFV1.PFVOD2
#define PFV1PFVOD3 PFV1.PFVOD3
#define PFV1PFVOD4 PFV1.PFVOD4
#define PFV1PFVOD5 PFV1.PFVOD5
#define PFV1PFVOD6 PFV1.PFVOD6
#define PFV1PFVOD7 PFV1.PFVOD7
#define PFV1PFVIFSR PFV1.PFVIFSR
#define PFV1PFVOFSR PFV1.PFVOFSR
#define PFV1PFVACR PFV1.PFVACR
#define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE
#define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0
#define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1
#define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0
#define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1
#define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0
#define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1
#define PFV1PFVSZR PFV1.PFVSZR
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : pwm_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef PWM_IODEFINE_H
#define PWM_IODEFINE_H
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
union reg16_8_t
{
volatile uint16_t UINT16; /* 16-bit Access */
volatile uint8_t UINT8[2]; /* 8-bit Access */
};
struct st_pwm
{ /* PWM */
volatile uint8_t dummy559[2]; /* */
union reg16_8_t PWBTCR; /* PWBTCR */
volatile uint8_t dummy560[216]; /* */
/* start of struct st_pwm_common */
union reg16_8_t PWCR_1; /* PWCR_1 */
volatile uint8_t dummy561[2]; /* */
union reg16_8_t PWPR_1; /* PWPR_1 */
volatile uint16_t PWCYR_1; /* PWCYR_1 */
volatile uint16_t PWBFR_1A; /* PWBFR_1A */
volatile uint16_t PWBFR_1C; /* PWBFR_1C */
volatile uint16_t PWBFR_1E; /* PWBFR_1E */
volatile uint16_t PWBFR_1G; /* PWBFR_1G */
/* end of struct st_pwm_common */
/* start of struct st_pwm_common */
union reg16_8_t PWCR_2; /* PWCR_2 */
volatile uint8_t dummy562[2]; /* */
union reg16_8_t PWPR_2; /* PWPR_2 */
volatile uint16_t PWCYR_2; /* PWCYR_2 */
volatile uint16_t PWBFR_2A; /* PWBFR_2A */
volatile uint16_t PWBFR_2C; /* PWBFR_2C */
volatile uint16_t PWBFR_2E; /* PWBFR_2E */
volatile uint16_t PWBFR_2G; /* PWBFR_2G */
/* end of struct st_pwm_common */
};
struct st_pwm_common
{
union reg16_8_t PWCR_1; /* PWCR_1 */
volatile uint8_t dummy572[2]; /* */
union reg16_8_t PWPR_1; /* PWPR_1 */
volatile uint16_t PWCYR_1; /* PWCYR_1 */
volatile uint16_t PWBFR_1A; /* PWBFR_1A */
volatile uint16_t PWBFR_1C; /* PWBFR_1C */
volatile uint16_t PWBFR_1E; /* PWBFR_1E */
volatile uint16_t PWBFR_1G; /* PWBFR_1G */
};
#define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */
/* Start of channnel array defines of PWM */
/* Channnel array defines of PWMn */
/*(Sample) value = PWMn[ channel ]->PWCR_1.UINT16; */
#define PWMn_COUNT 2
#define PWMn_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&PWM1, &PWM2 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define PWM1 (*(struct st_pwm_common *)&PWM.PWCR_1) /* PWM1 */
#define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */
/* End of channnel array defines of PWM */
#define PWMPWBTCR PWM.PWBTCR.UINT16
#define PWMPWBTCR_BYTE_L PWM.PWBTCR.UINT8[0]
#define PWMPWBTCR_BYTE_H PWM.PWBTCR.UINT8[1]
#define PWMPWCR_1 PWM.PWCR_1.UINT16
#define PWMPWCR_1_BYTE_L PWM.PWCR_1.UINT8[0]
#define PWMPWCR_1_BYTE_H PWM.PWCR_1.UINT8[1]
#define PWMPWPR_1 PWM.PWPR_1.UINT16
#define PWMPWPR_1_BYTE_L PWM.PWPR_1.UINT8[0]
#define PWMPWPR_1_BYTE_H PWM.PWPR_1.UINT8[1]
#define PWMPWCYR_1 PWM.PWCYR_1
#define PWMPWBFR_1A PWM.PWBFR_1A
#define PWMPWBFR_1C PWM.PWBFR_1C
#define PWMPWBFR_1E PWM.PWBFR_1E
#define PWMPWBFR_1G PWM.PWBFR_1G
#define PWMPWCR_2 PWM.PWCR_2.UINT16
#define PWMPWCR_2_BYTE_L PWM.PWCR_2.UINT8[0]
#define PWMPWCR_2_BYTE_H PWM.PWCR_2.UINT8[1]
#define PWMPWPR_2 PWM.PWPR_2.UINT16
#define PWMPWPR_2_BYTE_L PWM.PWPR_2.UINT8[0]
#define PWMPWPR_2_BYTE_H PWM.PWPR_2.UINT8[1]
#define PWMPWCYR_2 PWM.PWCYR_2
#define PWMPWBFR_2A PWM.PWBFR_2A
#define PWMPWBFR_2C PWM.PWBFR_2C
#define PWMPWBFR_2E PWM.PWBFR_2E
#define PWMPWBFR_2G PWM.PWBFR_2G
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : riic_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef RIIC_IODEFINE_H
#define RIIC_IODEFINE_H
#include "reg32_t.h"
struct st_riic
{ /* RIIC */
#define RIICnCRm_COUNT 2
union reg32_t RIICnCR1; /* RIICnCR1 */
union reg32_t RIICnCR2; /* RIICnCR2 */
#define RIICnMRm_COUNT 3
union reg32_t RIICnMR1; /* RIICnMR1 */
union reg32_t RIICnMR2; /* RIICnMR2 */
union reg32_t RIICnMR3; /* RIICnMR3 */
union reg32_t RIICnFER; /* RIICnFER */
union reg32_t RIICnSER; /* RIICnSER */
union reg32_t RIICnIER; /* RIICnIER */
#define RIICnSRm_COUNT 2
union reg32_t RIICnSR1; /* RIICnSR1 */
union reg32_t RIICnSR2; /* RIICnSR2 */
#define RIICnSARm_COUNT 3
union reg32_t RIICnSAR0; /* RIICnSAR0 */
union reg32_t RIICnSAR1; /* RIICnSAR1 */
union reg32_t RIICnSAR2; /* RIICnSAR2 */
union reg32_t RIICnBRL; /* RIICnBRL */
union reg32_t RIICnBRH; /* RIICnBRH */
union reg32_t RIICnDRT; /* RIICnDRT */
union reg32_t RIICnDRR; /* RIICnDRR */
};
#define RIIC0 (*(struct st_riic *)0xFCFEE000uL) /* RIIC0 */
#define RIIC1 (*(struct st_riic *)0xFCFEE400uL) /* RIIC1 */
#define RIIC2 (*(struct st_riic *)0xFCFEE800uL) /* RIIC2 */
#define RIIC3 (*(struct st_riic *)0xFCFEEC00uL) /* RIIC3 */
/* Start of channnel array defines of RIIC */
/* Channnel array defines of RIIC */
/*(Sample) value = RIIC[ channel ]->RIICnCR1.UINT32; */
#define RIIC_COUNT 4
#define RIIC_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&RIIC0, &RIIC1, &RIIC2, &RIIC3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of RIIC */
#define RIIC0CR1 RIIC0.RIICnCR1.UINT32
#define RIIC0CR1L RIIC0.RIICnCR1.UINT16[L]
#define RIIC0CR1LL RIIC0.RIICnCR1.UINT8[LL]
#define RIIC0CR1LH RIIC0.RIICnCR1.UINT8[LH]
#define RIIC0CR1H RIIC0.RIICnCR1.UINT16[H]
#define RIIC0CR1HL RIIC0.RIICnCR1.UINT8[HL]
#define RIIC0CR1HH RIIC0.RIICnCR1.UINT8[HH]
#define RIIC0CR2 RIIC0.RIICnCR2.UINT32
#define RIIC0CR2L RIIC0.RIICnCR2.UINT16[L]
#define RIIC0CR2LL RIIC0.RIICnCR2.UINT8[LL]
#define RIIC0CR2LH RIIC0.RIICnCR2.UINT8[LH]
#define RIIC0CR2H RIIC0.RIICnCR2.UINT16[H]
#define RIIC0CR2HL RIIC0.RIICnCR2.UINT8[HL]
#define RIIC0CR2HH RIIC0.RIICnCR2.UINT8[HH]
#define RIIC0MR1 RIIC0.RIICnMR1.UINT32
#define RIIC0MR1L RIIC0.RIICnMR1.UINT16[L]
#define RIIC0MR1LL RIIC0.RIICnMR1.UINT8[LL]
#define RIIC0MR1LH RIIC0.RIICnMR1.UINT8[LH]
#define RIIC0MR1H RIIC0.RIICnMR1.UINT16[H]
#define RIIC0MR1HL RIIC0.RIICnMR1.UINT8[HL]
#define RIIC0MR1HH RIIC0.RIICnMR1.UINT8[HH]
#define RIIC0MR2 RIIC0.RIICnMR2.UINT32
#define RIIC0MR2L RIIC0.RIICnMR2.UINT16[L]
#define RIIC0MR2LL RIIC0.RIICnMR2.UINT8[LL]
#define RIIC0MR2LH RIIC0.RIICnMR2.UINT8[LH]
#define RIIC0MR2H RIIC0.RIICnMR2.UINT16[H]
#define RIIC0MR2HL RIIC0.RIICnMR2.UINT8[HL]
#define RIIC0MR2HH RIIC0.RIICnMR2.UINT8[HH]
#define RIIC0MR3 RIIC0.RIICnMR3.UINT32
#define RIIC0MR3L RIIC0.RIICnMR3.UINT16[L]
#define RIIC0MR3LL RIIC0.RIICnMR3.UINT8[LL]
#define RIIC0MR3LH RIIC0.RIICnMR3.UINT8[LH]
#define RIIC0MR3H RIIC0.RIICnMR3.UINT16[H]
#define RIIC0MR3HL RIIC0.RIICnMR3.UINT8[HL]
#define RIIC0MR3HH RIIC0.RIICnMR3.UINT8[HH]
#define RIIC0FER RIIC0.RIICnFER.UINT32
#define RIIC0FERL RIIC0.RIICnFER.UINT16[L]
#define RIIC0FERLL RIIC0.RIICnFER.UINT8[LL]
#define RIIC0FERLH RIIC0.RIICnFER.UINT8[LH]
#define RIIC0FERH RIIC0.RIICnFER.UINT16[H]
#define RIIC0FERHL RIIC0.RIICnFER.UINT8[HL]
#define RIIC0FERHH RIIC0.RIICnFER.UINT8[HH]
#define RIIC0SER RIIC0.RIICnSER.UINT32
#define RIIC0SERL RIIC0.RIICnSER.UINT16[L]
#define RIIC0SERLL RIIC0.RIICnSER.UINT8[LL]
#define RIIC0SERLH RIIC0.RIICnSER.UINT8[LH]
#define RIIC0SERH RIIC0.RIICnSER.UINT16[H]
#define RIIC0SERHL RIIC0.RIICnSER.UINT8[HL]
#define RIIC0SERHH RIIC0.RIICnSER.UINT8[HH]
#define RIIC0IER RIIC0.RIICnIER.UINT32
#define RIIC0IERL RIIC0.RIICnIER.UINT16[L]
#define RIIC0IERLL RIIC0.RIICnIER.UINT8[LL]
#define RIIC0IERLH RIIC0.RIICnIER.UINT8[LH]
#define RIIC0IERH RIIC0.RIICnIER.UINT16[H]
#define RIIC0IERHL RIIC0.RIICnIER.UINT8[HL]
#define RIIC0IERHH RIIC0.RIICnIER.UINT8[HH]
#define RIIC0SR1 RIIC0.RIICnSR1.UINT32
#define RIIC0SR1L RIIC0.RIICnSR1.UINT16[L]
#define RIIC0SR1LL RIIC0.RIICnSR1.UINT8[LL]
#define RIIC0SR1LH RIIC0.RIICnSR1.UINT8[LH]
#define RIIC0SR1H RIIC0.RIICnSR1.UINT16[H]
#define RIIC0SR1HL RIIC0.RIICnSR1.UINT8[HL]
#define RIIC0SR1HH RIIC0.RIICnSR1.UINT8[HH]
#define RIIC0SR2 RIIC0.RIICnSR2.UINT32
#define RIIC0SR2L RIIC0.RIICnSR2.UINT16[L]
#define RIIC0SR2LL RIIC0.RIICnSR2.UINT8[LL]
#define RIIC0SR2LH RIIC0.RIICnSR2.UINT8[LH]
#define RIIC0SR2H RIIC0.RIICnSR2.UINT16[H]
#define RIIC0SR2HL RIIC0.RIICnSR2.UINT8[HL]
#define RIIC0SR2HH RIIC0.RIICnSR2.UINT8[HH]
#define RIIC0SAR0 RIIC0.RIICnSAR0.UINT32
#define RIIC0SAR0L RIIC0.RIICnSAR0.UINT16[L]
#define RIIC0SAR0LL RIIC0.RIICnSAR0.UINT8[LL]
#define RIIC0SAR0LH RIIC0.RIICnSAR0.UINT8[LH]
#define RIIC0SAR0H RIIC0.RIICnSAR0.UINT16[H]
#define RIIC0SAR0HL RIIC0.RIICnSAR0.UINT8[HL]
#define RIIC0SAR0HH RIIC0.RIICnSAR0.UINT8[HH]
#define RIIC0SAR1 RIIC0.RIICnSAR1.UINT32
#define RIIC0SAR1L RIIC0.RIICnSAR1.UINT16[L]
#define RIIC0SAR1LL RIIC0.RIICnSAR1.UINT8[LL]
#define RIIC0SAR1LH RIIC0.RIICnSAR1.UINT8[LH]
#define RIIC0SAR1H RIIC0.RIICnSAR1.UINT16[H]
#define RIIC0SAR1HL RIIC0.RIICnSAR1.UINT8[HL]
#define RIIC0SAR1HH RIIC0.RIICnSAR1.UINT8[HH]
#define RIIC0SAR2 RIIC0.RIICnSAR2.UINT32
#define RIIC0SAR2L RIIC0.RIICnSAR2.UINT16[L]
#define RIIC0SAR2LL RIIC0.RIICnSAR2.UINT8[LL]
#define RIIC0SAR2LH RIIC0.RIICnSAR2.UINT8[LH]
#define RIIC0SAR2H RIIC0.RIICnSAR2.UINT16[H]
#define RIIC0SAR2HL RIIC0.RIICnSAR2.UINT8[HL]
#define RIIC0SAR2HH RIIC0.RIICnSAR2.UINT8[HH]
#define RIIC0BRL RIIC0.RIICnBRL.UINT32
#define RIIC0BRLL RIIC0.RIICnBRL.UINT16[L]
#define RIIC0BRLLL RIIC0.RIICnBRL.UINT8[LL]
#define RIIC0BRLLH RIIC0.RIICnBRL.UINT8[LH]
#define RIIC0BRLH RIIC0.RIICnBRL.UINT16[H]
#define RIIC0BRLHL RIIC0.RIICnBRL.UINT8[HL]
#define RIIC0BRLHH RIIC0.RIICnBRL.UINT8[HH]
#define RIIC0BRH RIIC0.RIICnBRH.UINT32
#define RIIC0BRHL RIIC0.RIICnBRH.UINT16[L]
#define RIIC0BRHLL RIIC0.RIICnBRH.UINT8[LL]
#define RIIC0BRHLH RIIC0.RIICnBRH.UINT8[LH]
#define RIIC0BRHH RIIC0.RIICnBRH.UINT16[H]
#define RIIC0BRHHL RIIC0.RIICnBRH.UINT8[HL]
#define RIIC0BRHHH RIIC0.RIICnBRH.UINT8[HH]
#define RIIC0DRT RIIC0.RIICnDRT.UINT32
#define RIIC0DRTL RIIC0.RIICnDRT.UINT16[L]
#define RIIC0DRTLL RIIC0.RIICnDRT.UINT8[LL]
#define RIIC0DRTLH RIIC0.RIICnDRT.UINT8[LH]
#define RIIC0DRTH RIIC0.RIICnDRT.UINT16[H]
#define RIIC0DRTHL RIIC0.RIICnDRT.UINT8[HL]
#define RIIC0DRTHH RIIC0.RIICnDRT.UINT8[HH]
#define RIIC0DRR RIIC0.RIICnDRR.UINT32
#define RIIC0DRRL RIIC0.RIICnDRR.UINT16[L]
#define RIIC0DRRLL RIIC0.RIICnDRR.UINT8[LL]
#define RIIC0DRRLH RIIC0.RIICnDRR.UINT8[LH]
#define RIIC0DRRH RIIC0.RIICnDRR.UINT16[H]
#define RIIC0DRRHL RIIC0.RIICnDRR.UINT8[HL]
#define RIIC0DRRHH RIIC0.RIICnDRR.UINT8[HH]
#define RIIC1CR1 RIIC1.RIICnCR1.UINT32
#define RIIC1CR1L RIIC1.RIICnCR1.UINT16[L]
#define RIIC1CR1LL RIIC1.RIICnCR1.UINT8[LL]
#define RIIC1CR1LH RIIC1.RIICnCR1.UINT8[LH]
#define RIIC1CR1H RIIC1.RIICnCR1.UINT16[H]
#define RIIC1CR1HL RIIC1.RIICnCR1.UINT8[HL]
#define RIIC1CR1HH RIIC1.RIICnCR1.UINT8[HH]
#define RIIC1CR2 RIIC1.RIICnCR2.UINT32
#define RIIC1CR2L RIIC1.RIICnCR2.UINT16[L]
#define RIIC1CR2LL RIIC1.RIICnCR2.UINT8[LL]
#define RIIC1CR2LH RIIC1.RIICnCR2.UINT8[LH]
#define RIIC1CR2H RIIC1.RIICnCR2.UINT16[H]
#define RIIC1CR2HL RIIC1.RIICnCR2.UINT8[HL]
#define RIIC1CR2HH RIIC1.RIICnCR2.UINT8[HH]
#define RIIC1MR1 RIIC1.RIICnMR1.UINT32
#define RIIC1MR1L RIIC1.RIICnMR1.UINT16[L]
#define RIIC1MR1LL RIIC1.RIICnMR1.UINT8[LL]
#define RIIC1MR1LH RIIC1.RIICnMR1.UINT8[LH]
#define RIIC1MR1H RIIC1.RIICnMR1.UINT16[H]
#define RIIC1MR1HL RIIC1.RIICnMR1.UINT8[HL]
#define RIIC1MR1HH RIIC1.RIICnMR1.UINT8[HH]
#define RIIC1MR2 RIIC1.RIICnMR2.UINT32
#define RIIC1MR2L RIIC1.RIICnMR2.UINT16[L]
#define RIIC1MR2LL RIIC1.RIICnMR2.UINT8[LL]
#define RIIC1MR2LH RIIC1.RIICnMR2.UINT8[LH]
#define RIIC1MR2H RIIC1.RIICnMR2.UINT16[H]
#define RIIC1MR2HL RIIC1.RIICnMR2.UINT8[HL]
#define RIIC1MR2HH RIIC1.RIICnMR2.UINT8[HH]
#define RIIC1MR3 RIIC1.RIICnMR3.UINT32
#define RIIC1MR3L RIIC1.RIICnMR3.UINT16[L]
#define RIIC1MR3LL RIIC1.RIICnMR3.UINT8[LL]
#define RIIC1MR3LH RIIC1.RIICnMR3.UINT8[LH]
#define RIIC1MR3H RIIC1.RIICnMR3.UINT16[H]
#define RIIC1MR3HL RIIC1.RIICnMR3.UINT8[HL]
#define RIIC1MR3HH RIIC1.RIICnMR3.UINT8[HH]
#define RIIC1FER RIIC1.RIICnFER.UINT32
#define RIIC1FERL RIIC1.RIICnFER.UINT16[L]
#define RIIC1FERLL RIIC1.RIICnFER.UINT8[LL]
#define RIIC1FERLH RIIC1.RIICnFER.UINT8[LH]
#define RIIC1FERH RIIC1.RIICnFER.UINT16[H]
#define RIIC1FERHL RIIC1.RIICnFER.UINT8[HL]
#define RIIC1FERHH RIIC1.RIICnFER.UINT8[HH]
#define RIIC1SER RIIC1.RIICnSER.UINT32
#define RIIC1SERL RIIC1.RIICnSER.UINT16[L]
#define RIIC1SERLL RIIC1.RIICnSER.UINT8[LL]
#define RIIC1SERLH RIIC1.RIICnSER.UINT8[LH]
#define RIIC1SERH RIIC1.RIICnSER.UINT16[H]
#define RIIC1SERHL RIIC1.RIICnSER.UINT8[HL]
#define RIIC1SERHH RIIC1.RIICnSER.UINT8[HH]
#define RIIC1IER RIIC1.RIICnIER.UINT32
#define RIIC1IERL RIIC1.RIICnIER.UINT16[L]
#define RIIC1IERLL RIIC1.RIICnIER.UINT8[LL]
#define RIIC1IERLH RIIC1.RIICnIER.UINT8[LH]
#define RIIC1IERH RIIC1.RIICnIER.UINT16[H]
#define RIIC1IERHL RIIC1.RIICnIER.UINT8[HL]
#define RIIC1IERHH RIIC1.RIICnIER.UINT8[HH]
#define RIIC1SR1 RIIC1.RIICnSR1.UINT32
#define RIIC1SR1L RIIC1.RIICnSR1.UINT16[L]
#define RIIC1SR1LL RIIC1.RIICnSR1.UINT8[LL]
#define RIIC1SR1LH RIIC1.RIICnSR1.UINT8[LH]
#define RIIC1SR1H RIIC1.RIICnSR1.UINT16[H]
#define RIIC1SR1HL RIIC1.RIICnSR1.UINT8[HL]
#define RIIC1SR1HH RIIC1.RIICnSR1.UINT8[HH]
#define RIIC1SR2 RIIC1.RIICnSR2.UINT32
#define RIIC1SR2L RIIC1.RIICnSR2.UINT16[L]
#define RIIC1SR2LL RIIC1.RIICnSR2.UINT8[LL]
#define RIIC1SR2LH RIIC1.RIICnSR2.UINT8[LH]
#define RIIC1SR2H RIIC1.RIICnSR2.UINT16[H]
#define RIIC1SR2HL RIIC1.RIICnSR2.UINT8[HL]
#define RIIC1SR2HH RIIC1.RIICnSR2.UINT8[HH]
#define RIIC1SAR0 RIIC1.RIICnSAR0.UINT32
#define RIIC1SAR0L RIIC1.RIICnSAR0.UINT16[L]
#define RIIC1SAR0LL RIIC1.RIICnSAR0.UINT8[LL]
#define RIIC1SAR0LH RIIC1.RIICnSAR0.UINT8[LH]
#define RIIC1SAR0H RIIC1.RIICnSAR0.UINT16[H]
#define RIIC1SAR0HL RIIC1.RIICnSAR0.UINT8[HL]
#define RIIC1SAR0HH RIIC1.RIICnSAR0.UINT8[HH]
#define RIIC1SAR1 RIIC1.RIICnSAR1.UINT32
#define RIIC1SAR1L RIIC1.RIICnSAR1.UINT16[L]
#define RIIC1SAR1LL RIIC1.RIICnSAR1.UINT8[LL]
#define RIIC1SAR1LH RIIC1.RIICnSAR1.UINT8[LH]
#define RIIC1SAR1H RIIC1.RIICnSAR1.UINT16[H]
#define RIIC1SAR1HL RIIC1.RIICnSAR1.UINT8[HL]
#define RIIC1SAR1HH RIIC1.RIICnSAR1.UINT8[HH]
#define RIIC1SAR2 RIIC1.RIICnSAR2.UINT32
#define RIIC1SAR2L RIIC1.RIICnSAR2.UINT16[L]
#define RIIC1SAR2LL RIIC1.RIICnSAR2.UINT8[LL]
#define RIIC1SAR2LH RIIC1.RIICnSAR2.UINT8[LH]
#define RIIC1SAR2H RIIC1.RIICnSAR2.UINT16[H]
#define RIIC1SAR2HL RIIC1.RIICnSAR2.UINT8[HL]
#define RIIC1SAR2HH RIIC1.RIICnSAR2.UINT8[HH]
#define RIIC1BRL RIIC1.RIICnBRL.UINT32
#define RIIC1BRLL RIIC1.RIICnBRL.UINT16[L]
#define RIIC1BRLLL RIIC1.RIICnBRL.UINT8[LL]
#define RIIC1BRLLH RIIC1.RIICnBRL.UINT8[LH]
#define RIIC1BRLH RIIC1.RIICnBRL.UINT16[H]
#define RIIC1BRLHL RIIC1.RIICnBRL.UINT8[HL]
#define RIIC1BRLHH RIIC1.RIICnBRL.UINT8[HH]
#define RIIC1BRH RIIC1.RIICnBRH.UINT32
#define RIIC1BRHL RIIC1.RIICnBRH.UINT16[L]
#define RIIC1BRHLL RIIC1.RIICnBRH.UINT8[LL]
#define RIIC1BRHLH RIIC1.RIICnBRH.UINT8[LH]
#define RIIC1BRHH RIIC1.RIICnBRH.UINT16[H]
#define RIIC1BRHHL RIIC1.RIICnBRH.UINT8[HL]
#define RIIC1BRHHH RIIC1.RIICnBRH.UINT8[HH]
#define RIIC1DRT RIIC1.RIICnDRT.UINT32
#define RIIC1DRTL RIIC1.RIICnDRT.UINT16[L]
#define RIIC1DRTLL RIIC1.RIICnDRT.UINT8[LL]
#define RIIC1DRTLH RIIC1.RIICnDRT.UINT8[LH]
#define RIIC1DRTH RIIC1.RIICnDRT.UINT16[H]
#define RIIC1DRTHL RIIC1.RIICnDRT.UINT8[HL]
#define RIIC1DRTHH RIIC1.RIICnDRT.UINT8[HH]
#define RIIC1DRR RIIC1.RIICnDRR.UINT32
#define RIIC1DRRL RIIC1.RIICnDRR.UINT16[L]
#define RIIC1DRRLL RIIC1.RIICnDRR.UINT8[LL]
#define RIIC1DRRLH RIIC1.RIICnDRR.UINT8[LH]
#define RIIC1DRRH RIIC1.RIICnDRR.UINT16[H]
#define RIIC1DRRHL RIIC1.RIICnDRR.UINT8[HL]
#define RIIC1DRRHH RIIC1.RIICnDRR.UINT8[HH]
#define RIIC2CR1 RIIC2.RIICnCR1.UINT32
#define RIIC2CR1L RIIC2.RIICnCR1.UINT16[L]
#define RIIC2CR1LL RIIC2.RIICnCR1.UINT8[LL]
#define RIIC2CR1LH RIIC2.RIICnCR1.UINT8[LH]
#define RIIC2CR1H RIIC2.RIICnCR1.UINT16[H]
#define RIIC2CR1HL RIIC2.RIICnCR1.UINT8[HL]
#define RIIC2CR1HH RIIC2.RIICnCR1.UINT8[HH]
#define RIIC2CR2 RIIC2.RIICnCR2.UINT32
#define RIIC2CR2L RIIC2.RIICnCR2.UINT16[L]
#define RIIC2CR2LL RIIC2.RIICnCR2.UINT8[LL]
#define RIIC2CR2LH RIIC2.RIICnCR2.UINT8[LH]
#define RIIC2CR2H RIIC2.RIICnCR2.UINT16[H]
#define RIIC2CR2HL RIIC2.RIICnCR2.UINT8[HL]
#define RIIC2CR2HH RIIC2.RIICnCR2.UINT8[HH]
#define RIIC2MR1 RIIC2.RIICnMR1.UINT32
#define RIIC2MR1L RIIC2.RIICnMR1.UINT16[L]
#define RIIC2MR1LL RIIC2.RIICnMR1.UINT8[LL]
#define RIIC2MR1LH RIIC2.RIICnMR1.UINT8[LH]
#define RIIC2MR1H RIIC2.RIICnMR1.UINT16[H]
#define RIIC2MR1HL RIIC2.RIICnMR1.UINT8[HL]
#define RIIC2MR1HH RIIC2.RIICnMR1.UINT8[HH]
#define RIIC2MR2 RIIC2.RIICnMR2.UINT32
#define RIIC2MR2L RIIC2.RIICnMR2.UINT16[L]
#define RIIC2MR2LL RIIC2.RIICnMR2.UINT8[LL]
#define RIIC2MR2LH RIIC2.RIICnMR2.UINT8[LH]
#define RIIC2MR2H RIIC2.RIICnMR2.UINT16[H]
#define RIIC2MR2HL RIIC2.RIICnMR2.UINT8[HL]
#define RIIC2MR2HH RIIC2.RIICnMR2.UINT8[HH]
#define RIIC2MR3 RIIC2.RIICnMR3.UINT32
#define RIIC2MR3L RIIC2.RIICnMR3.UINT16[L]
#define RIIC2MR3LL RIIC2.RIICnMR3.UINT8[LL]
#define RIIC2MR3LH RIIC2.RIICnMR3.UINT8[LH]
#define RIIC2MR3H RIIC2.RIICnMR3.UINT16[H]
#define RIIC2MR3HL RIIC2.RIICnMR3.UINT8[HL]
#define RIIC2MR3HH RIIC2.RIICnMR3.UINT8[HH]
#define RIIC2FER RIIC2.RIICnFER.UINT32
#define RIIC2FERL RIIC2.RIICnFER.UINT16[L]
#define RIIC2FERLL RIIC2.RIICnFER.UINT8[LL]
#define RIIC2FERLH RIIC2.RIICnFER.UINT8[LH]
#define RIIC2FERH RIIC2.RIICnFER.UINT16[H]
#define RIIC2FERHL RIIC2.RIICnFER.UINT8[HL]
#define RIIC2FERHH RIIC2.RIICnFER.UINT8[HH]
#define RIIC2SER RIIC2.RIICnSER.UINT32
#define RIIC2SERL RIIC2.RIICnSER.UINT16[L]
#define RIIC2SERLL RIIC2.RIICnSER.UINT8[LL]
#define RIIC2SERLH RIIC2.RIICnSER.UINT8[LH]
#define RIIC2SERH RIIC2.RIICnSER.UINT16[H]
#define RIIC2SERHL RIIC2.RIICnSER.UINT8[HL]
#define RIIC2SERHH RIIC2.RIICnSER.UINT8[HH]
#define RIIC2IER RIIC2.RIICnIER.UINT32
#define RIIC2IERL RIIC2.RIICnIER.UINT16[L]
#define RIIC2IERLL RIIC2.RIICnIER.UINT8[LL]
#define RIIC2IERLH RIIC2.RIICnIER.UINT8[LH]
#define RIIC2IERH RIIC2.RIICnIER.UINT16[H]
#define RIIC2IERHL RIIC2.RIICnIER.UINT8[HL]
#define RIIC2IERHH RIIC2.RIICnIER.UINT8[HH]
#define RIIC2SR1 RIIC2.RIICnSR1.UINT32
#define RIIC2SR1L RIIC2.RIICnSR1.UINT16[L]
#define RIIC2SR1LL RIIC2.RIICnSR1.UINT8[LL]
#define RIIC2SR1LH RIIC2.RIICnSR1.UINT8[LH]
#define RIIC2SR1H RIIC2.RIICnSR1.UINT16[H]
#define RIIC2SR1HL RIIC2.RIICnSR1.UINT8[HL]
#define RIIC2SR1HH RIIC2.RIICnSR1.UINT8[HH]
#define RIIC2SR2 RIIC2.RIICnSR2.UINT32
#define RIIC2SR2L RIIC2.RIICnSR2.UINT16[L]
#define RIIC2SR2LL RIIC2.RIICnSR2.UINT8[LL]
#define RIIC2SR2LH RIIC2.RIICnSR2.UINT8[LH]
#define RIIC2SR2H RIIC2.RIICnSR2.UINT16[H]
#define RIIC2SR2HL RIIC2.RIICnSR2.UINT8[HL]
#define RIIC2SR2HH RIIC2.RIICnSR2.UINT8[HH]
#define RIIC2SAR0 RIIC2.RIICnSAR0.UINT32
#define RIIC2SAR0L RIIC2.RIICnSAR0.UINT16[L]
#define RIIC2SAR0LL RIIC2.RIICnSAR0.UINT8[LL]
#define RIIC2SAR0LH RIIC2.RIICnSAR0.UINT8[LH]
#define RIIC2SAR0H RIIC2.RIICnSAR0.UINT16[H]
#define RIIC2SAR0HL RIIC2.RIICnSAR0.UINT8[HL]
#define RIIC2SAR0HH RIIC2.RIICnSAR0.UINT8[HH]
#define RIIC2SAR1 RIIC2.RIICnSAR1.UINT32
#define RIIC2SAR1L RIIC2.RIICnSAR1.UINT16[L]
#define RIIC2SAR1LL RIIC2.RIICnSAR1.UINT8[LL]
#define RIIC2SAR1LH RIIC2.RIICnSAR1.UINT8[LH]
#define RIIC2SAR1H RIIC2.RIICnSAR1.UINT16[H]
#define RIIC2SAR1HL RIIC2.RIICnSAR1.UINT8[HL]
#define RIIC2SAR1HH RIIC2.RIICnSAR1.UINT8[HH]
#define RIIC2SAR2 RIIC2.RIICnSAR2.UINT32
#define RIIC2SAR2L RIIC2.RIICnSAR2.UINT16[L]
#define RIIC2SAR2LL RIIC2.RIICnSAR2.UINT8[LL]
#define RIIC2SAR2LH RIIC2.RIICnSAR2.UINT8[LH]
#define RIIC2SAR2H RIIC2.RIICnSAR2.UINT16[H]
#define RIIC2SAR2HL RIIC2.RIICnSAR2.UINT8[HL]
#define RIIC2SAR2HH RIIC2.RIICnSAR2.UINT8[HH]
#define RIIC2BRL RIIC2.RIICnBRL.UINT32
#define RIIC2BRLL RIIC2.RIICnBRL.UINT16[L]
#define RIIC2BRLLL RIIC2.RIICnBRL.UINT8[LL]
#define RIIC2BRLLH RIIC2.RIICnBRL.UINT8[LH]
#define RIIC2BRLH RIIC2.RIICnBRL.UINT16[H]
#define RIIC2BRLHL RIIC2.RIICnBRL.UINT8[HL]
#define RIIC2BRLHH RIIC2.RIICnBRL.UINT8[HH]
#define RIIC2BRH RIIC2.RIICnBRH.UINT32
#define RIIC2BRHL RIIC2.RIICnBRH.UINT16[L]
#define RIIC2BRHLL RIIC2.RIICnBRH.UINT8[LL]
#define RIIC2BRHLH RIIC2.RIICnBRH.UINT8[LH]
#define RIIC2BRHH RIIC2.RIICnBRH.UINT16[H]
#define RIIC2BRHHL RIIC2.RIICnBRH.UINT8[HL]
#define RIIC2BRHHH RIIC2.RIICnBRH.UINT8[HH]
#define RIIC2DRT RIIC2.RIICnDRT.UINT32
#define RIIC2DRTL RIIC2.RIICnDRT.UINT16[L]
#define RIIC2DRTLL RIIC2.RIICnDRT.UINT8[LL]
#define RIIC2DRTLH RIIC2.RIICnDRT.UINT8[LH]
#define RIIC2DRTH RIIC2.RIICnDRT.UINT16[H]
#define RIIC2DRTHL RIIC2.RIICnDRT.UINT8[HL]
#define RIIC2DRTHH RIIC2.RIICnDRT.UINT8[HH]
#define RIIC2DRR RIIC2.RIICnDRR.UINT32
#define RIIC2DRRL RIIC2.RIICnDRR.UINT16[L]
#define RIIC2DRRLL RIIC2.RIICnDRR.UINT8[LL]
#define RIIC2DRRLH RIIC2.RIICnDRR.UINT8[LH]
#define RIIC2DRRH RIIC2.RIICnDRR.UINT16[H]
#define RIIC2DRRHL RIIC2.RIICnDRR.UINT8[HL]
#define RIIC2DRRHH RIIC2.RIICnDRR.UINT8[HH]
#define RIIC3CR1 RIIC3.RIICnCR1.UINT32
#define RIIC3CR1L RIIC3.RIICnCR1.UINT16[L]
#define RIIC3CR1LL RIIC3.RIICnCR1.UINT8[LL]
#define RIIC3CR1LH RIIC3.RIICnCR1.UINT8[LH]
#define RIIC3CR1H RIIC3.RIICnCR1.UINT16[H]
#define RIIC3CR1HL RIIC3.RIICnCR1.UINT8[HL]
#define RIIC3CR1HH RIIC3.RIICnCR1.UINT8[HH]
#define RIIC3CR2 RIIC3.RIICnCR2.UINT32
#define RIIC3CR2L RIIC3.RIICnCR2.UINT16[L]
#define RIIC3CR2LL RIIC3.RIICnCR2.UINT8[LL]
#define RIIC3CR2LH RIIC3.RIICnCR2.UINT8[LH]
#define RIIC3CR2H RIIC3.RIICnCR2.UINT16[H]
#define RIIC3CR2HL RIIC3.RIICnCR2.UINT8[HL]
#define RIIC3CR2HH RIIC3.RIICnCR2.UINT8[HH]
#define RIIC3MR1 RIIC3.RIICnMR1.UINT32
#define RIIC3MR1L RIIC3.RIICnMR1.UINT16[L]
#define RIIC3MR1LL RIIC3.RIICnMR1.UINT8[LL]
#define RIIC3MR1LH RIIC3.RIICnMR1.UINT8[LH]
#define RIIC3MR1H RIIC3.RIICnMR1.UINT16[H]
#define RIIC3MR1HL RIIC3.RIICnMR1.UINT8[HL]
#define RIIC3MR1HH RIIC3.RIICnMR1.UINT8[HH]
#define RIIC3MR2 RIIC3.RIICnMR2.UINT32
#define RIIC3MR2L RIIC3.RIICnMR2.UINT16[L]
#define RIIC3MR2LL RIIC3.RIICnMR2.UINT8[LL]
#define RIIC3MR2LH RIIC3.RIICnMR2.UINT8[LH]
#define RIIC3MR2H RIIC3.RIICnMR2.UINT16[H]
#define RIIC3MR2HL RIIC3.RIICnMR2.UINT8[HL]
#define RIIC3MR2HH RIIC3.RIICnMR2.UINT8[HH]
#define RIIC3MR3 RIIC3.RIICnMR3.UINT32
#define RIIC3MR3L RIIC3.RIICnMR3.UINT16[L]
#define RIIC3MR3LL RIIC3.RIICnMR3.UINT8[LL]
#define RIIC3MR3LH RIIC3.RIICnMR3.UINT8[LH]
#define RIIC3MR3H RIIC3.RIICnMR3.UINT16[H]
#define RIIC3MR3HL RIIC3.RIICnMR3.UINT8[HL]
#define RIIC3MR3HH RIIC3.RIICnMR3.UINT8[HH]
#define RIIC3FER RIIC3.RIICnFER.UINT32
#define RIIC3FERL RIIC3.RIICnFER.UINT16[L]
#define RIIC3FERLL RIIC3.RIICnFER.UINT8[LL]
#define RIIC3FERLH RIIC3.RIICnFER.UINT8[LH]
#define RIIC3FERH RIIC3.RIICnFER.UINT16[H]
#define RIIC3FERHL RIIC3.RIICnFER.UINT8[HL]
#define RIIC3FERHH RIIC3.RIICnFER.UINT8[HH]
#define RIIC3SER RIIC3.RIICnSER.UINT32
#define RIIC3SERL RIIC3.RIICnSER.UINT16[L]
#define RIIC3SERLL RIIC3.RIICnSER.UINT8[LL]
#define RIIC3SERLH RIIC3.RIICnSER.UINT8[LH]
#define RIIC3SERH RIIC3.RIICnSER.UINT16[H]
#define RIIC3SERHL RIIC3.RIICnSER.UINT8[HL]
#define RIIC3SERHH RIIC3.RIICnSER.UINT8[HH]
#define RIIC3IER RIIC3.RIICnIER.UINT32
#define RIIC3IERL RIIC3.RIICnIER.UINT16[L]
#define RIIC3IERLL RIIC3.RIICnIER.UINT8[LL]
#define RIIC3IERLH RIIC3.RIICnIER.UINT8[LH]
#define RIIC3IERH RIIC3.RIICnIER.UINT16[H]
#define RIIC3IERHL RIIC3.RIICnIER.UINT8[HL]
#define RIIC3IERHH RIIC3.RIICnIER.UINT8[HH]
#define RIIC3SR1 RIIC3.RIICnSR1.UINT32
#define RIIC3SR1L RIIC3.RIICnSR1.UINT16[L]
#define RIIC3SR1LL RIIC3.RIICnSR1.UINT8[LL]
#define RIIC3SR1LH RIIC3.RIICnSR1.UINT8[LH]
#define RIIC3SR1H RIIC3.RIICnSR1.UINT16[H]
#define RIIC3SR1HL RIIC3.RIICnSR1.UINT8[HL]
#define RIIC3SR1HH RIIC3.RIICnSR1.UINT8[HH]
#define RIIC3SR2 RIIC3.RIICnSR2.UINT32
#define RIIC3SR2L RIIC3.RIICnSR2.UINT16[L]
#define RIIC3SR2LL RIIC3.RIICnSR2.UINT8[LL]
#define RIIC3SR2LH RIIC3.RIICnSR2.UINT8[LH]
#define RIIC3SR2H RIIC3.RIICnSR2.UINT16[H]
#define RIIC3SR2HL RIIC3.RIICnSR2.UINT8[HL]
#define RIIC3SR2HH RIIC3.RIICnSR2.UINT8[HH]
#define RIIC3SAR0 RIIC3.RIICnSAR0.UINT32
#define RIIC3SAR0L RIIC3.RIICnSAR0.UINT16[L]
#define RIIC3SAR0LL RIIC3.RIICnSAR0.UINT8[LL]
#define RIIC3SAR0LH RIIC3.RIICnSAR0.UINT8[LH]
#define RIIC3SAR0H RIIC3.RIICnSAR0.UINT16[H]
#define RIIC3SAR0HL RIIC3.RIICnSAR0.UINT8[HL]
#define RIIC3SAR0HH RIIC3.RIICnSAR0.UINT8[HH]
#define RIIC3SAR1 RIIC3.RIICnSAR1.UINT32
#define RIIC3SAR1L RIIC3.RIICnSAR1.UINT16[L]
#define RIIC3SAR1LL RIIC3.RIICnSAR1.UINT8[LL]
#define RIIC3SAR1LH RIIC3.RIICnSAR1.UINT8[LH]
#define RIIC3SAR1H RIIC3.RIICnSAR1.UINT16[H]
#define RIIC3SAR1HL RIIC3.RIICnSAR1.UINT8[HL]
#define RIIC3SAR1HH RIIC3.RIICnSAR1.UINT8[HH]
#define RIIC3SAR2 RIIC3.RIICnSAR2.UINT32
#define RIIC3SAR2L RIIC3.RIICnSAR2.UINT16[L]
#define RIIC3SAR2LL RIIC3.RIICnSAR2.UINT8[LL]
#define RIIC3SAR2LH RIIC3.RIICnSAR2.UINT8[LH]
#define RIIC3SAR2H RIIC3.RIICnSAR2.UINT16[H]
#define RIIC3SAR2HL RIIC3.RIICnSAR2.UINT8[HL]
#define RIIC3SAR2HH RIIC3.RIICnSAR2.UINT8[HH]
#define RIIC3BRL RIIC3.RIICnBRL.UINT32
#define RIIC3BRLL RIIC3.RIICnBRL.UINT16[L]
#define RIIC3BRLLL RIIC3.RIICnBRL.UINT8[LL]
#define RIIC3BRLLH RIIC3.RIICnBRL.UINT8[LH]
#define RIIC3BRLH RIIC3.RIICnBRL.UINT16[H]
#define RIIC3BRLHL RIIC3.RIICnBRL.UINT8[HL]
#define RIIC3BRLHH RIIC3.RIICnBRL.UINT8[HH]
#define RIIC3BRH RIIC3.RIICnBRH.UINT32
#define RIIC3BRHL RIIC3.RIICnBRH.UINT16[L]
#define RIIC3BRHLL RIIC3.RIICnBRH.UINT8[LL]
#define RIIC3BRHLH RIIC3.RIICnBRH.UINT8[LH]
#define RIIC3BRHH RIIC3.RIICnBRH.UINT16[H]
#define RIIC3BRHHL RIIC3.RIICnBRH.UINT8[HL]
#define RIIC3BRHHH RIIC3.RIICnBRH.UINT8[HH]
#define RIIC3DRT RIIC3.RIICnDRT.UINT32
#define RIIC3DRTL RIIC3.RIICnDRT.UINT16[L]
#define RIIC3DRTLL RIIC3.RIICnDRT.UINT8[LL]
#define RIIC3DRTLH RIIC3.RIICnDRT.UINT8[LH]
#define RIIC3DRTH RIIC3.RIICnDRT.UINT16[H]
#define RIIC3DRTHL RIIC3.RIICnDRT.UINT8[HL]
#define RIIC3DRTHH RIIC3.RIICnDRT.UINT8[HH]
#define RIIC3DRR RIIC3.RIICnDRR.UINT32
#define RIIC3DRRL RIIC3.RIICnDRR.UINT16[L]
#define RIIC3DRRLL RIIC3.RIICnDRR.UINT8[LL]
#define RIIC3DRRLH RIIC3.RIICnDRR.UINT8[LH]
#define RIIC3DRRH RIIC3.RIICnDRR.UINT16[H]
#define RIIC3DRRHL RIIC3.RIICnDRR.UINT8[HL]
#define RIIC3DRRHH RIIC3.RIICnDRR.UINT8[HH]
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : romdec_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef ROMDEC_IODEFINE_H
#define ROMDEC_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_romdec
{ /* ROMDEC */
volatile uint8_t CROMEN; /* CROMEN */
volatile uint8_t CROMSY0; /* CROMSY0 */
#define ROMDEC_CROMCTL0_COUNT 2
volatile uint8_t CROMCTL0; /* CROMCTL0 */
volatile uint8_t CROMCTL1; /* CROMCTL1 */
volatile uint8_t dummy23[1]; /* */
volatile uint8_t CROMCTL3; /* CROMCTL3 */
volatile uint8_t CROMCTL4; /* CROMCTL4 */
volatile uint8_t CROMCTL5; /* CROMCTL5 */
#define ROMDEC_CROMST0_COUNT 2
volatile uint8_t CROMST0; /* CROMST0 */
volatile uint8_t CROMST1; /* CROMST1 */
volatile uint8_t dummy24[1]; /* */
volatile uint8_t CROMST3; /* CROMST3 */
volatile uint8_t CROMST4; /* CROMST4 */
volatile uint8_t CROMST5; /* CROMST5 */
volatile uint8_t CROMST6; /* CROMST6 */
volatile uint8_t dummy25[5]; /* */
#define ROMDEC_CBUFST0_COUNT 3
volatile uint8_t CBUFST0; /* CBUFST0 */
volatile uint8_t CBUFST1; /* CBUFST1 */
volatile uint8_t CBUFST2; /* CBUFST2 */
volatile uint8_t dummy26[1]; /* */
#define ROMDEC_HEAD00_COUNT 4
volatile uint8_t HEAD00; /* HEAD00 */
volatile uint8_t HEAD01; /* HEAD01 */
volatile uint8_t HEAD02; /* HEAD02 */
volatile uint8_t HEAD03; /* HEAD03 */
#define ROMDEC_SHEAD00_COUNT 8
volatile uint8_t SHEAD00; /* SHEAD00 */
volatile uint8_t SHEAD01; /* SHEAD01 */
volatile uint8_t SHEAD02; /* SHEAD02 */
volatile uint8_t SHEAD03; /* SHEAD03 */
volatile uint8_t SHEAD04; /* SHEAD04 */
volatile uint8_t SHEAD05; /* SHEAD05 */
volatile uint8_t SHEAD06; /* SHEAD06 */
volatile uint8_t SHEAD07; /* SHEAD07 */
#define ROMDEC_HEAD20_COUNT 4
volatile uint8_t HEAD20; /* HEAD20 */
volatile uint8_t HEAD21; /* HEAD21 */
volatile uint8_t HEAD22; /* HEAD22 */
volatile uint8_t HEAD23; /* HEAD23 */
#define ROMDEC_SHEAD20_COUNT 8
volatile uint8_t SHEAD20; /* SHEAD20 */
volatile uint8_t SHEAD21; /* SHEAD21 */
volatile uint8_t SHEAD22; /* SHEAD22 */
volatile uint8_t SHEAD23; /* SHEAD23 */
volatile uint8_t SHEAD24; /* SHEAD24 */
volatile uint8_t SHEAD25; /* SHEAD25 */
volatile uint8_t SHEAD26; /* SHEAD26 */
volatile uint8_t SHEAD27; /* SHEAD27 */
volatile uint8_t dummy27[16]; /* */
#define ROMDEC_CBUFCTL0_COUNT 4
volatile uint8_t CBUFCTL0; /* CBUFCTL0 */
volatile uint8_t CBUFCTL1; /* CBUFCTL1 */
volatile uint8_t CBUFCTL2; /* CBUFCTL2 */
volatile uint8_t CBUFCTL3; /* CBUFCTL3 */
volatile uint8_t dummy28[1]; /* */
volatile uint8_t CROMST0M; /* CROMST0M */
volatile uint8_t dummy29[186]; /* */
volatile uint8_t ROMDECRST; /* ROMDECRST */
volatile uint8_t RSTSTAT; /* RSTSTAT */
volatile uint8_t SSI; /* SSI */
volatile uint8_t dummy30[5]; /* */
volatile uint8_t INTHOLD; /* INTHOLD */
volatile uint8_t INHINT; /* INHINT */
volatile uint8_t dummy31[246]; /* */
#define ROMDEC_STRMDIN0_COUNT 2
volatile uint16_t STRMDIN0; /* STRMDIN0 */
volatile uint16_t STRMDIN2; /* STRMDIN2 */
volatile uint16_t STRMDOUT0; /* STRMDOUT0 */
};
#define ROMDEC (*(struct st_romdec *)0xE8005000uL) /* ROMDEC */
#define ROMDECCROMEN ROMDEC.CROMEN
#define ROMDECCROMSY0 ROMDEC.CROMSY0
#define ROMDECCROMCTL0 ROMDEC.CROMCTL0
#define ROMDECCROMCTL1 ROMDEC.CROMCTL1
#define ROMDECCROMCTL3 ROMDEC.CROMCTL3
#define ROMDECCROMCTL4 ROMDEC.CROMCTL4
#define ROMDECCROMCTL5 ROMDEC.CROMCTL5
#define ROMDECCROMST0 ROMDEC.CROMST0
#define ROMDECCROMST1 ROMDEC.CROMST1
#define ROMDECCROMST3 ROMDEC.CROMST3
#define ROMDECCROMST4 ROMDEC.CROMST4
#define ROMDECCROMST5 ROMDEC.CROMST5
#define ROMDECCROMST6 ROMDEC.CROMST6
#define ROMDECCBUFST0 ROMDEC.CBUFST0
#define ROMDECCBUFST1 ROMDEC.CBUFST1
#define ROMDECCBUFST2 ROMDEC.CBUFST2
#define ROMDECHEAD00 ROMDEC.HEAD00
#define ROMDECHEAD01 ROMDEC.HEAD01
#define ROMDECHEAD02 ROMDEC.HEAD02
#define ROMDECHEAD03 ROMDEC.HEAD03
#define ROMDECSHEAD00 ROMDEC.SHEAD00
#define ROMDECSHEAD01 ROMDEC.SHEAD01
#define ROMDECSHEAD02 ROMDEC.SHEAD02
#define ROMDECSHEAD03 ROMDEC.SHEAD03
#define ROMDECSHEAD04 ROMDEC.SHEAD04
#define ROMDECSHEAD05 ROMDEC.SHEAD05
#define ROMDECSHEAD06 ROMDEC.SHEAD06
#define ROMDECSHEAD07 ROMDEC.SHEAD07
#define ROMDECHEAD20 ROMDEC.HEAD20
#define ROMDECHEAD21 ROMDEC.HEAD21
#define ROMDECHEAD22 ROMDEC.HEAD22
#define ROMDECHEAD23 ROMDEC.HEAD23
#define ROMDECSHEAD20 ROMDEC.SHEAD20
#define ROMDECSHEAD21 ROMDEC.SHEAD21
#define ROMDECSHEAD22 ROMDEC.SHEAD22
#define ROMDECSHEAD23 ROMDEC.SHEAD23
#define ROMDECSHEAD24 ROMDEC.SHEAD24
#define ROMDECSHEAD25 ROMDEC.SHEAD25
#define ROMDECSHEAD26 ROMDEC.SHEAD26
#define ROMDECSHEAD27 ROMDEC.SHEAD27
#define ROMDECCBUFCTL0 ROMDEC.CBUFCTL0
#define ROMDECCBUFCTL1 ROMDEC.CBUFCTL1
#define ROMDECCBUFCTL2 ROMDEC.CBUFCTL2
#define ROMDECCBUFCTL3 ROMDEC.CBUFCTL3
#define ROMDECCROMST0M ROMDEC.CROMST0M
#define ROMDECROMDECRST ROMDEC.ROMDECRST
#define ROMDECRSTSTAT ROMDEC.RSTSTAT
#define ROMDECSSI ROMDEC.SSI
#define ROMDECINTHOLD ROMDEC.INTHOLD
#define ROMDECINHINT ROMDEC.INHINT
#define ROMDECSTRMDIN0 ROMDEC.STRMDIN0
#define ROMDECSTRMDIN2 ROMDEC.STRMDIN2
#define ROMDECSTRMDOUT0 ROMDEC.STRMDOUT0
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : rspi_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef RSPI_IODEFINE_H
#define RSPI_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
#include "reg32_t.h"
struct st_rspi
{ /* RSPI */
volatile uint8_t SPCR; /* SPCR */
volatile uint8_t SSLP; /* SSLP */
volatile uint8_t SPPCR; /* SPPCR */
volatile uint8_t SPSR; /* SPSR */
union reg32_t SPDR; /* SPDR */
volatile uint8_t SPSCR; /* SPSCR */
volatile uint8_t SPSSR; /* SPSSR */
volatile uint8_t SPBR; /* SPBR */
volatile uint8_t SPDCR; /* SPDCR */
volatile uint8_t SPCKD; /* SPCKD */
volatile uint8_t SSLND; /* SSLND */
volatile uint8_t SPND; /* SPND */
volatile uint8_t dummy1[1]; /* */
#define SPCMD_COUNT 4
volatile uint16_t SPCMD0; /* SPCMD0 */
volatile uint16_t SPCMD1; /* SPCMD1 */
volatile uint16_t SPCMD2; /* SPCMD2 */
volatile uint16_t SPCMD3; /* SPCMD3 */
volatile uint8_t dummy2[8]; /* */
volatile uint8_t SPBFCR; /* SPBFCR */
volatile uint8_t dummy3[1]; /* */
volatile uint16_t SPBFDR; /* SPBFDR */
};
#define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */
#define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */
#define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */
#define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */
#define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */
/* Start of channnel array defines of RSPI */
/* Channnel array defines of RSPI */
/*(Sample) value = RSPI[ channel ]->SPCR; */
#define RSPI_COUNT 5
#define RSPI_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of RSPI */
#define SPCR_0 RSPI0.SPCR
#define SSLP_0 RSPI0.SSLP
#define SPPCR_0 RSPI0.SPPCR
#define SPSR_0 RSPI0.SPSR
#define SPDR_0 RSPI0.SPDR.UINT32
#define SPDR_0L RSPI0.SPDR.UINT16[L]
#define SPDR_0H RSPI0.SPDR.UINT16[H]
#define SPDR_0LL RSPI0.SPDR.UINT8[LL]
#define SPDR_0LH RSPI0.SPDR.UINT8[LH]
#define SPDR_0HL RSPI0.SPDR.UINT8[HL]
#define SPDR_0HH RSPI0.SPDR.UINT8[HH]
#define SPSCR_0 RSPI0.SPSCR
#define SPSSR_0 RSPI0.SPSSR
#define SPBR_0 RSPI0.SPBR
#define SPDCR_0 RSPI0.SPDCR
#define SPCKD_0 RSPI0.SPCKD
#define SSLND_0 RSPI0.SSLND
#define SPND_0 RSPI0.SPND
#define SPCMD0_0 RSPI0.SPCMD0
#define SPCMD1_0 RSPI0.SPCMD1
#define SPCMD2_0 RSPI0.SPCMD2
#define SPCMD3_0 RSPI0.SPCMD3
#define SPBFCR_0 RSPI0.SPBFCR
#define SPBFDR_0 RSPI0.SPBFDR
#define SPCR_1 RSPI1.SPCR
#define SSLP_1 RSPI1.SSLP
#define SPPCR_1 RSPI1.SPPCR
#define SPSR_1 RSPI1.SPSR
#define SPDR_1 RSPI1.SPDR.UINT32
#define SPDR_1L RSPI1.SPDR.UINT16[L]
#define SPDR_1H RSPI1.SPDR.UINT16[H]
#define SPDR_1LL RSPI1.SPDR.UINT8[LL]
#define SPDR_1LH RSPI1.SPDR.UINT8[LH]
#define SPDR_1HL RSPI1.SPDR.UINT8[HL]
#define SPDR_1HH RSPI1.SPDR.UINT8[HH]
#define SPSCR_1 RSPI1.SPSCR
#define SPSSR_1 RSPI1.SPSSR
#define SPBR_1 RSPI1.SPBR
#define SPDCR_1 RSPI1.SPDCR
#define SPCKD_1 RSPI1.SPCKD
#define SSLND_1 RSPI1.SSLND
#define SPND_1 RSPI1.SPND
#define SPCMD0_1 RSPI1.SPCMD0
#define SPCMD1_1 RSPI1.SPCMD1
#define SPCMD2_1 RSPI1.SPCMD2
#define SPCMD3_1 RSPI1.SPCMD3
#define SPBFCR_1 RSPI1.SPBFCR
#define SPBFDR_1 RSPI1.SPBFDR
#define SPCR_2 RSPI2.SPCR
#define SSLP_2 RSPI2.SSLP
#define SPPCR_2 RSPI2.SPPCR
#define SPSR_2 RSPI2.SPSR
#define SPDR_2 RSPI2.SPDR.UINT32
#define SPDR_2L RSPI2.SPDR.UINT16[L]
#define SPDR_2H RSPI2.SPDR.UINT16[H]
#define SPDR_2LL RSPI2.SPDR.UINT8[LL]
#define SPDR_2LH RSPI2.SPDR.UINT8[LH]
#define SPDR_2HL RSPI2.SPDR.UINT8[HL]
#define SPDR_2HH RSPI2.SPDR.UINT8[HH]
#define SPSCR_2 RSPI2.SPSCR
#define SPSSR_2 RSPI2.SPSSR
#define SPBR_2 RSPI2.SPBR
#define SPDCR_2 RSPI2.SPDCR
#define SPCKD_2 RSPI2.SPCKD
#define SSLND_2 RSPI2.SSLND
#define SPND_2 RSPI2.SPND
#define SPCMD0_2 RSPI2.SPCMD0
#define SPCMD1_2 RSPI2.SPCMD1
#define SPCMD2_2 RSPI2.SPCMD2
#define SPCMD3_2 RSPI2.SPCMD3
#define SPBFCR_2 RSPI2.SPBFCR
#define SPBFDR_2 RSPI2.SPBFDR
#define SPCR_3 RSPI3.SPCR
#define SSLP_3 RSPI3.SSLP
#define SPPCR_3 RSPI3.SPPCR
#define SPSR_3 RSPI3.SPSR
#define SPDR_3 RSPI3.SPDR.UINT32
#define SPDR_3L RSPI3.SPDR.UINT16[L]
#define SPDR_3H RSPI3.SPDR.UINT16[H]
#define SPDR_3LL RSPI3.SPDR.UINT8[LL]
#define SPDR_3LH RSPI3.SPDR.UINT8[LH]
#define SPDR_3HL RSPI3.SPDR.UINT8[HL]
#define SPDR_3HH RSPI3.SPDR.UINT8[HH]
#define SPSCR_3 RSPI3.SPSCR
#define SPSSR_3 RSPI3.SPSSR
#define SPBR_3 RSPI3.SPBR
#define SPDCR_3 RSPI3.SPDCR
#define SPCKD_3 RSPI3.SPCKD
#define SSLND_3 RSPI3.SSLND
#define SPND_3 RSPI3.SPND
#define SPCMD0_3 RSPI3.SPCMD0
#define SPCMD1_3 RSPI3.SPCMD1
#define SPCMD2_3 RSPI3.SPCMD2
#define SPCMD3_3 RSPI3.SPCMD3
#define SPBFCR_3 RSPI3.SPBFCR
#define SPBFDR_3 RSPI3.SPBFDR
#define SPCR_4 RSPI4.SPCR
#define SSLP_4 RSPI4.SSLP
#define SPPCR_4 RSPI4.SPPCR
#define SPSR_4 RSPI4.SPSR
#define SPDR_4 RSPI4.SPDR.UINT32
#define SPDR_4L RSPI4.SPDR.UINT16[L]
#define SPDR_4H RSPI4.SPDR.UINT16[H]
#define SPDR_4LL RSPI4.SPDR.UINT8[LL]
#define SPDR_4LH RSPI4.SPDR.UINT8[LH]
#define SPDR_4HL RSPI4.SPDR.UINT8[HL]
#define SPDR_4HH RSPI4.SPDR.UINT8[HH]
#define SPSCR_4 RSPI4.SPSCR
#define SPSSR_4 RSPI4.SPSSR
#define SPBR_4 RSPI4.SPBR
#define SPDCR_4 RSPI4.SPDCR
#define SPCKD_4 RSPI4.SPCKD
#define SSLND_4 RSPI4.SSLND
#define SPND_4 RSPI4.SPND
#define SPCMD0_4 RSPI4.SPCMD0
#define SPCMD1_4 RSPI4.SPCMD1
#define SPCMD2_4 RSPI4.SPCMD2
#define SPCMD3_4 RSPI4.SPCMD3
#define SPBFCR_4 RSPI4.SPBFCR
#define SPBFDR_4 RSPI4.SPBFDR
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : rtc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef RTC_IODEFINE_H
#define RTC_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_rtc
{ /* RTC */
volatile uint8_t R64CNT; /* R64CNT */
volatile uint8_t dummy537[1]; /* */
volatile uint8_t RSECCNT; /* RSECCNT */
volatile uint8_t dummy538[1]; /* */
volatile uint8_t RMINCNT; /* RMINCNT */
volatile uint8_t dummy539[1]; /* */
volatile uint8_t RHRCNT; /* RHRCNT */
volatile uint8_t dummy540[1]; /* */
volatile uint8_t RWKCNT; /* RWKCNT */
volatile uint8_t dummy541[1]; /* */
volatile uint8_t RDAYCNT; /* RDAYCNT */
volatile uint8_t dummy542[1]; /* */
volatile uint8_t RMONCNT; /* RMONCNT */
volatile uint8_t dummy543[1]; /* */
volatile uint16_t RYRCNT; /* RYRCNT */
volatile uint8_t RSECAR; /* RSECAR */
volatile uint8_t dummy544[1]; /* */
volatile uint8_t RMINAR; /* RMINAR */
volatile uint8_t dummy545[1]; /* */
volatile uint8_t RHRAR; /* RHRAR */
volatile uint8_t dummy546[1]; /* */
volatile uint8_t RWKAR; /* RWKAR */
volatile uint8_t dummy547[1]; /* */
volatile uint8_t RDAYAR; /* RDAYAR */
volatile uint8_t dummy548[1]; /* */
volatile uint8_t RMONAR; /* RMONAR */
volatile uint8_t dummy549[1]; /* */
volatile uint8_t RCR1; /* RCR1 */
volatile uint8_t dummy550[1]; /* */
volatile uint8_t RCR2; /* RCR2 */
volatile uint8_t dummy551[1]; /* */
volatile uint16_t RYRAR; /* RYRAR */
volatile uint8_t dummy552[2]; /* */
volatile uint8_t RCR3; /* RCR3 */
volatile uint8_t dummy553[1]; /* */
volatile uint8_t RCR5; /* RCR5 */
volatile uint8_t dummy554[3]; /* */
volatile uint16_t RFRH; /* RFRH */
volatile uint16_t RFRL; /* RFRL */
};
#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */
#define RTCR64CNT RTC.R64CNT
#define RTCRSECCNT RTC.RSECCNT
#define RTCRMINCNT RTC.RMINCNT
#define RTCRHRCNT RTC.RHRCNT
#define RTCRWKCNT RTC.RWKCNT
#define RTCRDAYCNT RTC.RDAYCNT
#define RTCRMONCNT RTC.RMONCNT
#define RTCRYRCNT RTC.RYRCNT
#define RTCRSECAR RTC.RSECAR
#define RTCRMINAR RTC.RMINAR
#define RTCRHRAR RTC.RHRAR
#define RTCRWKAR RTC.RWKAR
#define RTCRDAYAR RTC.RDAYAR
#define RTCRMONAR RTC.RMONAR
#define RTCRCR1 RTC.RCR1
#define RTCRCR2 RTC.RCR2
#define RTCRYRAR RTC.RYRAR
#define RTCRCR3 RTC.RCR3
#define RTCRCR5 RTC.RCR5
#define RTCRFRH RTC.RFRH
#define RTCRFRL RTC.RFRL
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : scif_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef SCIF_IODEFINE_H
#define SCIF_IODEFINE_H
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->SEC M1.10.1 : Not magic number */
struct st_scif
{ /* SCIF */
volatile uint16_t SCSMR; /* SCSMR */
volatile uint8_t dummy1[2]; /* */
volatile uint8_t SCBRR; /* SCBRR */
volatile uint8_t dummy2[3]; /* */
volatile uint16_t SCSCR; /* SCSCR */
volatile uint8_t dummy3[2]; /* */
volatile uint8_t SCFTDR; /* SCFTDR */
volatile uint8_t dummy4[3]; /* */
volatile uint16_t SCFSR; /* SCFSR */
volatile uint8_t dummy5[2]; /* */
volatile uint8_t SCFRDR; /* SCFRDR */
volatile uint8_t dummy6[3]; /* */
volatile uint16_t SCFCR; /* SCFCR */
volatile uint8_t dummy7[2]; /* */
volatile uint16_t SCFDR; /* SCFDR */
volatile uint8_t dummy8[2]; /* */
volatile uint16_t SCSPTR; /* SCSPTR */
volatile uint8_t dummy9[2]; /* */
volatile uint16_t SCLSR; /* SCLSR */
volatile uint8_t dummy10[2]; /* */
volatile uint16_t SCEMR; /* SCEMR */
};
#define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */
#define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */
#define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */
#define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */
#define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */
#define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */
#define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */
#define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */
#define P_SCIF0 (0xE8007000uL) /* SCIF0 */
#define P_SCIF1 (0xE8007800uL) /* SCIF1 */
#define P_SCIF2 (0xE8008000uL) /* SCIF2 */
#define P_SCIF3 (0xE8008800uL) /* SCIF3 */
#define P_SCIF4 (0xE8009000uL) /* SCIF4 */
#define P_SCIF5 (0xE8009800uL) /* SCIF5 */
#define P_SCIF6 (0xE800A000uL) /* SCIF6 */
#define P_SCIF7 (0xE800A800uL) /* SCIF7 */
/* Start of channnel array defines of SCIF */
/* Channnel array defines of SCIF */
/*(Sample) value = SCIF[ channel ]->SCSMR; */
#define SCIF_COUNT 8
#define SCIF_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of SCIF */
#define SCSMR_0 SCIF0.SCSMR
#define SCBRR_0 SCIF0.SCBRR
#define SCSCR_0 SCIF0.SCSCR
#define SCFTDR_0 SCIF0.SCFTDR
#define SCFSR_0 SCIF0.SCFSR
#define SCFRDR_0 SCIF0.SCFRDR
#define SCFCR_0 SCIF0.SCFCR
#define SCFDR_0 SCIF0.SCFDR
#define SCSPTR_0 SCIF0.SCSPTR
#define SCLSR_0 SCIF0.SCLSR
#define SCEMR_0 SCIF0.SCEMR
#define SCSMR_1 SCIF1.SCSMR
#define SCBRR_1 SCIF1.SCBRR
#define SCSCR_1 SCIF1.SCSCR
#define SCFTDR_1 SCIF1.SCFTDR
#define SCFSR_1 SCIF1.SCFSR
#define SCFRDR_1 SCIF1.SCFRDR
#define SCFCR_1 SCIF1.SCFCR
#define SCFDR_1 SCIF1.SCFDR
#define SCSPTR_1 SCIF1.SCSPTR
#define SCLSR_1 SCIF1.SCLSR
#define SCEMR_1 SCIF1.SCEMR
#define SCSMR_2 SCIF2.SCSMR
#define SCBRR_2 SCIF2.SCBRR
#define SCSCR_2 SCIF2.SCSCR
#define SCFTDR_2 SCIF2.SCFTDR
#define SCFSR_2 SCIF2.SCFSR
#define SCFRDR_2 SCIF2.SCFRDR
#define SCFCR_2 SCIF2.SCFCR
#define SCFDR_2 SCIF2.SCFDR
#define SCSPTR_2 SCIF2.SCSPTR
#define SCLSR_2 SCIF2.SCLSR
#define SCEMR_2 SCIF2.SCEMR
#define SCSMR_3 SCIF3.SCSMR
#define SCBRR_3 SCIF3.SCBRR
#define SCSCR_3 SCIF3.SCSCR
#define SCFTDR_3 SCIF3.SCFTDR
#define SCFSR_3 SCIF3.SCFSR
#define SCFRDR_3 SCIF3.SCFRDR
#define SCFCR_3 SCIF3.SCFCR
#define SCFDR_3 SCIF3.SCFDR
#define SCSPTR_3 SCIF3.SCSPTR
#define SCLSR_3 SCIF3.SCLSR
#define SCEMR_3 SCIF3.SCEMR
#define SCSMR_4 SCIF4.SCSMR
#define SCBRR_4 SCIF4.SCBRR
#define SCSCR_4 SCIF4.SCSCR
#define SCFTDR_4 SCIF4.SCFTDR
#define SCFSR_4 SCIF4.SCFSR
#define SCFRDR_4 SCIF4.SCFRDR
#define SCFCR_4 SCIF4.SCFCR
#define SCFDR_4 SCIF4.SCFDR
#define SCSPTR_4 SCIF4.SCSPTR
#define SCLSR_4 SCIF4.SCLSR
#define SCEMR_4 SCIF4.SCEMR
#define SCSMR_5 SCIF5.SCSMR
#define SCBRR_5 SCIF5.SCBRR
#define SCSCR_5 SCIF5.SCSCR
#define SCFTDR_5 SCIF5.SCFTDR
#define SCFSR_5 SCIF5.SCFSR
#define SCFRDR_5 SCIF5.SCFRDR
#define SCFCR_5 SCIF5.SCFCR
#define SCFDR_5 SCIF5.SCFDR
#define SCSPTR_5 SCIF5.SCSPTR
#define SCLSR_5 SCIF5.SCLSR
#define SCEMR_5 SCIF5.SCEMR
#define SCSMR_6 SCIF6.SCSMR
#define SCBRR_6 SCIF6.SCBRR
#define SCSCR_6 SCIF6.SCSCR
#define SCFTDR_6 SCIF6.SCFTDR
#define SCFSR_6 SCIF6.SCFSR
#define SCFRDR_6 SCIF6.SCFRDR
#define SCFCR_6 SCIF6.SCFCR
#define SCFDR_6 SCIF6.SCFDR
#define SCSPTR_6 SCIF6.SCSPTR
#define SCLSR_6 SCIF6.SCLSR
#define SCEMR_6 SCIF6.SCEMR
#define SCSMR_7 SCIF7.SCSMR
#define SCBRR_7 SCIF7.SCBRR
#define SCSCR_7 SCIF7.SCSCR
#define SCFTDR_7 SCIF7.SCFTDR
#define SCFSR_7 SCIF7.SCFSR
#define SCFRDR_7 SCIF7.SCFRDR
#define SCFCR_7 SCIF7.SCFCR
#define SCFDR_7 SCIF7.SCFDR
#define SCSPTR_7 SCIF7.SCSPTR
#define SCLSR_7 SCIF7.SCLSR
#define SCEMR_7 SCIF7.SCEMR
/* <-SEC M1.10.1 */
/* <-QAC 0857 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : scim_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef SCIM_IODEFINE_H
#define SCIM_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_scim
{ /* SCIM */
volatile uint8_t SMR; /* SMR */
volatile uint8_t BRR; /* BRR */
volatile uint8_t SCR; /* SCR */
volatile uint8_t TDR; /* TDR */
volatile uint8_t SSR; /* SSR */
volatile uint8_t RDR; /* RDR */
volatile uint8_t SCMR; /* SCMR */
volatile uint8_t SEMR; /* SEMR */
volatile uint8_t SNFR; /* SNFR */
volatile uint8_t dummy1[4]; /* */
volatile uint8_t SECR; /* SECR */
};
#define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */
#define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */
/* Start of channnel array defines of SCIM */
/* Channnel array defines of SCIM */
/*(Sample) value = SCIM[ channel ]->SMR; */
#define SCIM_COUNT 2
#define SCIM_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCIM0, &SCIM1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of SCIM */
#define SMR0 SCIM0.SMR
#define BRR0 SCIM0.BRR
#define SCR0 SCIM0.SCR
#define TDR0 SCIM0.TDR
#define SSR0 SCIM0.SSR
#define RDR0 SCIM0.RDR
#define SCMR0 SCIM0.SCMR
#define SEMR0 SCIM0.SEMR
#define SNFR0 SCIM0.SNFR
#define SECR0 SCIM0.SECR
#define SMR1 SCIM1.SMR
#define BRR1 SCIM1.BRR
#define SCR1 SCIM1.SCR
#define TDR1 SCIM1.TDR
#define SSR1 SCIM1.SSR
#define RDR1 SCIM1.RDR
#define SCMR1 SCIM1.SCMR
#define SEMR1 SCIM1.SEMR
#define SNFR1 SCIM1.SNFR
#define SECR1 SCIM1.SECR
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : scux_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef SCUX_IODEFINE_H
#define SCUX_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->SEC M1.10.1 : Not magic number */
struct st_scux
{ /* SCUX */
/* start of struct st_scux_from_ipcir_ipc0_n */
volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */
volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */
volatile uint8_t dummy259[248]; /* */
/* end of struct st_scux_from_ipcir_ipc0_n */
/* start of struct st_scux_from_ipcir_ipc0_n */
volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */
volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */
volatile uint8_t dummy260[248]; /* */
/* end of struct st_scux_from_ipcir_ipc0_n */
/* start of struct st_scux_from_ipcir_ipc0_n */
volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */
volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */
volatile uint8_t dummy261[248]; /* */
/* end of struct st_scux_from_ipcir_ipc0_n */
/* start of struct st_scux_from_ipcir_ipc0_n */
volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */
volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */
volatile uint8_t dummy262[248]; /* */
/* end of struct st_scux_from_ipcir_ipc0_n */
/* start of struct st_scux_from_opcir_opc0_n */
volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */
volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */
volatile uint8_t dummy263[248]; /* */
/* end of struct st_scux_from_opcir_opc0_n */
/* start of struct st_scux_from_opcir_opc0_n */
volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */
volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */
volatile uint8_t dummy264[248]; /* */
/* end of struct st_scux_from_opcir_opc0_n */
/* start of struct st_scux_from_opcir_opc0_n */
volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */
volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */
volatile uint8_t dummy265[248]; /* */
/* end of struct st_scux_from_opcir_opc0_n */
/* start of struct st_scux_from_opcir_opc0_n */
volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */
volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */
volatile uint8_t dummy266[248]; /* */
/* end of struct st_scux_from_opcir_opc0_n */
/* start of struct st_scux_from_ffdir_ffd0_n */
volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */
volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */
volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */
volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */
volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */
volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */
volatile uint8_t dummy267[4]; /* */
volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */
/* end of struct st_scux_from_ffdir_ffd0_n */
volatile uint8_t dummy268[224]; /* */
/* start of struct st_scux_from_ffdir_ffd0_n */
volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */
volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */
volatile uint32_t DRQSR_FFD0_1; /* DRQSR_FFD0_1 */
volatile uint32_t FFDPR_FFD0_1; /* FFDPR_FFD0_1 */
volatile uint32_t FFDBR_FFD0_1; /* FFDBR_FFD0_1 */
volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */
volatile uint8_t dummy269[4]; /* */
volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */
/* end of struct st_scux_from_ffdir_ffd0_n */
volatile uint8_t dummy270[224]; /* */
/* start of struct st_scux_from_ffdir_ffd0_n */
volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */
volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */
volatile uint32_t DRQSR_FFD0_2; /* DRQSR_FFD0_2 */
volatile uint32_t FFDPR_FFD0_2; /* FFDPR_FFD0_2 */
volatile uint32_t FFDBR_FFD0_2; /* FFDBR_FFD0_2 */
volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */
volatile uint8_t dummy271[4]; /* */
volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */
/* end of struct st_scux_from_ffdir_ffd0_n */
volatile uint8_t dummy272[224]; /* */
/* start of struct st_scux_from_ffdir_ffd0_n */
volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */
volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */
volatile uint32_t DRQSR_FFD0_3; /* DRQSR_FFD0_3 */
volatile uint32_t FFDPR_FFD0_3; /* FFDPR_FFD0_3 */
volatile uint32_t FFDBR_FFD0_3; /* FFDBR_FFD0_3 */
volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */
volatile uint8_t dummy273[4]; /* */
volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */
/* end of struct st_scux_from_ffdir_ffd0_n */
volatile uint8_t dummy274[224]; /* */
/* start of struct st_scux_from_ffuir_ffu0_n */
volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */
volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */
volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */
volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */
volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */
volatile uint8_t dummy275[4]; /* */
volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */
/* end of struct st_scux_from_ffuir_ffu0_n */
volatile uint8_t dummy276[228]; /* */
/* start of struct st_scux_from_ffuir_ffu0_n */
volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */
volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */
volatile uint32_t URQSR_FFU0_1; /* URQSR_FFU0_1 */
volatile uint32_t FFUPR_FFU0_1; /* FFUPR_FFU0_1 */
volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */
volatile uint8_t dummy277[4]; /* */
volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */
/* end of struct st_scux_from_ffuir_ffu0_n */
volatile uint8_t dummy278[228]; /* */
/* start of struct st_scux_from_ffuir_ffu0_n */
volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */
volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */
volatile uint32_t URQSR_FFU0_2; /* URQSR_FFU0_2 */
volatile uint32_t FFUPR_FFU0_2; /* FFUPR_FFU0_2 */
volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */
volatile uint8_t dummy279[4]; /* */
volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */
/* end of struct st_scux_from_ffuir_ffu0_n */
volatile uint8_t dummy280[228]; /* */
/* start of struct st_scux_from_ffuir_ffu0_n */
volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */
volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */
volatile uint32_t URQSR_FFU0_3; /* URQSR_FFU0_3 */
volatile uint32_t FFUPR_FFU0_3; /* FFUPR_FFU0_3 */
volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */
volatile uint8_t dummy281[4]; /* */
volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */
/* end of struct st_scux_from_ffuir_ffu0_n */
volatile uint8_t dummy282[228]; /* */
/* start of struct st_scux_from_srcir0_2src0_n */
volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */
volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */
volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */
volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */
volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */
volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */
volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */
volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */
volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */
volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */
volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */
volatile uint8_t dummy283[4]; /* */
volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */
volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */
volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */
volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */
volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */
volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */
volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */
volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */
volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */
volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */
volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */
volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */
volatile uint8_t dummy284[4]; /* */
volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */
volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */
/* end of struct st_scux_from_srcir0_2src0_n */
volatile uint8_t dummy285[148]; /* */
/* start of struct st_scux_from_srcir0_2src0_n */
volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */
volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */
volatile uint32_t SRCBR0_2SRC0_1; /* SRCBR0_2SRC0_1 */
volatile uint32_t IFSCR0_2SRC0_1; /* IFSCR0_2SRC0_1 */
volatile uint32_t IFSVR0_2SRC0_1; /* IFSVR0_2SRC0_1 */
volatile uint32_t SRCCR0_2SRC0_1; /* SRCCR0_2SRC0_1 */
volatile uint32_t MNFSR0_2SRC0_1; /* MNFSR0_2SRC0_1 */
volatile uint32_t BFSSR0_2SRC0_1; /* BFSSR0_2SRC0_1 */
volatile uint32_t SC2SR0_2SRC0_1; /* SC2SR0_2SRC0_1 */
volatile uint32_t WATSR0_2SRC0_1; /* WATSR0_2SRC0_1 */
volatile uint32_t SEVMR0_2SRC0_1; /* SEVMR0_2SRC0_1 */
volatile uint8_t dummy286[4]; /* */
volatile uint32_t SEVCR0_2SRC0_1; /* SEVCR0_2SRC0_1 */
volatile uint32_t SRCIR1_2SRC0_1; /* SRCIR1_2SRC0_1 */
volatile uint32_t SADIR1_2SRC0_1; /* SADIR1_2SRC0_1 */
volatile uint32_t SRCBR1_2SRC0_1; /* SRCBR1_2SRC0_1 */
volatile uint32_t IFSCR1_2SRC0_1; /* IFSCR1_2SRC0_1 */
volatile uint32_t IFSVR1_2SRC0_1; /* IFSVR1_2SRC0_1 */
volatile uint32_t SRCCR1_2SRC0_1; /* SRCCR1_2SRC0_1 */
volatile uint32_t MNFSR1_2SRC0_1; /* MNFSR1_2SRC0_1 */
volatile uint32_t BFSSR1_2SRC0_1; /* BFSSR1_2SRC0_1 */
volatile uint32_t SC2SR1_2SRC0_1; /* SC2SR1_2SRC0_1 */
volatile uint32_t WATSR1_2SRC0_1; /* WATSR1_2SRC0_1 */
volatile uint32_t SEVMR1_2SRC0_1; /* SEVMR1_2SRC0_1 */
volatile uint8_t dummy287[4]; /* */
volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */
volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */
/* end of struct st_scux_from_srcir0_2src0_n */
volatile uint8_t dummy288[148]; /* */
/* start of struct st_scux_from_dvuir_dvu0_n */
volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */
volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */
volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */
volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */
volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */
volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */
volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */
volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */
volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */
volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */
volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */
volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */
volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */
volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */
volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */
volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */
volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */
volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */
volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */
volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */
volatile uint8_t dummy289[4]; /* */
volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */
/* end of struct st_scux_from_dvuir_dvu0_n */
volatile uint8_t dummy290[168]; /* */
/* start of struct st_scux_from_dvuir_dvu0_n */
volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */
volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */
volatile uint32_t DVUBR_DVU0_1; /* DVUBR_DVU0_1 */
volatile uint32_t DVUCR_DVU0_1; /* DVUCR_DVU0_1 */
volatile uint32_t ZCMCR_DVU0_1; /* ZCMCR_DVU0_1 */
volatile uint32_t VRCTR_DVU0_1; /* VRCTR_DVU0_1 */
volatile uint32_t VRPDR_DVU0_1; /* VRPDR_DVU0_1 */
volatile uint32_t VRDBR_DVU0_1; /* VRDBR_DVU0_1 */
volatile uint32_t VRWTR_DVU0_1; /* VRWTR_DVU0_1 */
volatile uint32_t VOL0R_DVU0_1; /* VOL0R_DVU0_1 */
volatile uint32_t VOL1R_DVU0_1; /* VOL1R_DVU0_1 */
volatile uint32_t VOL2R_DVU0_1; /* VOL2R_DVU0_1 */
volatile uint32_t VOL3R_DVU0_1; /* VOL3R_DVU0_1 */
volatile uint32_t VOL4R_DVU0_1; /* VOL4R_DVU0_1 */
volatile uint32_t VOL5R_DVU0_1; /* VOL5R_DVU0_1 */
volatile uint32_t VOL6R_DVU0_1; /* VOL6R_DVU0_1 */
volatile uint32_t VOL7R_DVU0_1; /* VOL7R_DVU0_1 */
volatile uint32_t DVUER_DVU0_1; /* DVUER_DVU0_1 */
volatile uint32_t DVUSR_DVU0_1; /* DVUSR_DVU0_1 */
volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */
volatile uint8_t dummy291[4]; /* */
volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */
/* end of struct st_scux_from_dvuir_dvu0_n */
volatile uint8_t dummy292[168]; /* */
/* start of struct st_scux_from_dvuir_dvu0_n */
volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */
volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */
volatile uint32_t DVUBR_DVU0_2; /* DVUBR_DVU0_2 */
volatile uint32_t DVUCR_DVU0_2; /* DVUCR_DVU0_2 */
volatile uint32_t ZCMCR_DVU0_2; /* ZCMCR_DVU0_2 */
volatile uint32_t VRCTR_DVU0_2; /* VRCTR_DVU0_2 */
volatile uint32_t VRPDR_DVU0_2; /* VRPDR_DVU0_2 */
volatile uint32_t VRDBR_DVU0_2; /* VRDBR_DVU0_2 */
volatile uint32_t VRWTR_DVU0_2; /* VRWTR_DVU0_2 */
volatile uint32_t VOL0R_DVU0_2; /* VOL0R_DVU0_2 */
volatile uint32_t VOL1R_DVU0_2; /* VOL1R_DVU0_2 */
volatile uint32_t VOL2R_DVU0_2; /* VOL2R_DVU0_2 */
volatile uint32_t VOL3R_DVU0_2; /* VOL3R_DVU0_2 */
volatile uint32_t VOL4R_DVU0_2; /* VOL4R_DVU0_2 */
volatile uint32_t VOL5R_DVU0_2; /* VOL5R_DVU0_2 */
volatile uint32_t VOL6R_DVU0_2; /* VOL6R_DVU0_2 */
volatile uint32_t VOL7R_DVU0_2; /* VOL7R_DVU0_2 */
volatile uint32_t DVUER_DVU0_2; /* DVUER_DVU0_2 */
volatile uint32_t DVUSR_DVU0_2; /* DVUSR_DVU0_2 */
volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */
volatile uint8_t dummy293[4]; /* */
volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */
/* end of struct st_scux_from_dvuir_dvu0_n */
volatile uint8_t dummy294[168]; /* */
/* start of struct st_scux_from_dvuir_dvu0_n */
volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */
volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */
volatile uint32_t DVUBR_DVU0_3; /* DVUBR_DVU0_3 */
volatile uint32_t DVUCR_DVU0_3; /* DVUCR_DVU0_3 */
volatile uint32_t ZCMCR_DVU0_3; /* ZCMCR_DVU0_3 */
volatile uint32_t VRCTR_DVU0_3; /* VRCTR_DVU0_3 */
volatile uint32_t VRPDR_DVU0_3; /* VRPDR_DVU0_3 */
volatile uint32_t VRDBR_DVU0_3; /* VRDBR_DVU0_3 */
volatile uint32_t VRWTR_DVU0_3; /* VRWTR_DVU0_3 */
volatile uint32_t VOL0R_DVU0_3; /* VOL0R_DVU0_3 */
volatile uint32_t VOL1R_DVU0_3; /* VOL1R_DVU0_3 */
volatile uint32_t VOL2R_DVU0_3; /* VOL2R_DVU0_3 */
volatile uint32_t VOL3R_DVU0_3; /* VOL3R_DVU0_3 */
volatile uint32_t VOL4R_DVU0_3; /* VOL4R_DVU0_3 */
volatile uint32_t VOL5R_DVU0_3; /* VOL5R_DVU0_3 */
volatile uint32_t VOL6R_DVU0_3; /* VOL6R_DVU0_3 */
volatile uint32_t VOL7R_DVU0_3; /* VOL7R_DVU0_3 */
volatile uint32_t DVUER_DVU0_3; /* DVUER_DVU0_3 */
volatile uint32_t DVUSR_DVU0_3; /* DVUSR_DVU0_3 */
volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */
volatile uint8_t dummy295[4]; /* */
volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */
/* end of struct st_scux_from_dvuir_dvu0_n */
volatile uint8_t dummy296[168]; /* */
volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */
volatile uint32_t MADIR_MIX0_0; /* MADIR_MIX0_0 */
volatile uint32_t MIXBR_MIX0_0; /* MIXBR_MIX0_0 */
volatile uint32_t MIXMR_MIX0_0; /* MIXMR_MIX0_0 */
volatile uint32_t MVPDR_MIX0_0; /* MVPDR_MIX0_0 */
volatile uint32_t MDBAR_MIX0_0; /* MDBAR_MIX0_0 */
volatile uint32_t MDBBR_MIX0_0; /* MDBBR_MIX0_0 */
volatile uint32_t MDBCR_MIX0_0; /* MDBCR_MIX0_0 */
volatile uint32_t MDBDR_MIX0_0; /* MDBDR_MIX0_0 */
volatile uint32_t MDBER_MIX0_0; /* MDBER_MIX0_0 */
volatile uint32_t MIXSR_MIX0_0; /* MIXSR_MIX0_0 */
volatile uint8_t dummy297[212]; /* */
volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */
volatile uint32_t DMACR_CIM; /* DMACR_CIM */
#define SCUX_DMATDn_CIM_COUNT 4
union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */
union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */
union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */
union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */
#define SCUX_DMATUn_CIM_COUNT 4
union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */
union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */
union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */
union iodefine_reg32_16_t DMATU3_CIM; /* DMATU3_CIM */
volatile uint8_t dummy298[16]; /* */
volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */
#define SCUX_FDTSELn_CIM_COUNT 4
volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */
volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */
volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */
volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */
#define SCUX_FUTSELn_CIM_COUNT 4
volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */
volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */
volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */
volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */
volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */
volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */
#define SCUX_SRCRSELn_CIM_COUNT 4
volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */
volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */
volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */
volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */
volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */
};
struct st_scux_from_ipcir_ipc0_n
{
volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */
volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */
volatile uint8_t dummy1[248]; /* */
};
struct st_scux_from_opcir_opc0_n
{
volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */
volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */
volatile uint8_t dummy1[248]; /* */
};
struct st_scux_from_ffdir_ffd0_n
{
volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */
volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */
volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */
volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */
volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */
volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */
volatile uint8_t dummy1[4]; /* */
volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */
};
struct st_scux_from_ffuir_ffu0_n
{
volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */
volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */
volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */
volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */
volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */
volatile uint8_t dummy1[4]; /* */
volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */
};
struct st_scux_from_srcir0_2src0_n
{
volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */
volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */
volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */
volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */
volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */
volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */
volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */
volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */
volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */
volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */
volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */
volatile uint8_t dummy1[4]; /* */
volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */
volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */
volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */
volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */
volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */
volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */
volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */
volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */
volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */
volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */
volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */
volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */
volatile uint8_t dummy2[4]; /* */
volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */
volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */
};
struct st_scux_from_dvuir_dvu0_n
{
volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */
volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */
volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */
volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */
volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */
volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */
volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */
volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */
volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */
volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */
volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */
volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */
volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */
volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */
volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */
volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */
volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */
volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */
volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */
volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */
volatile uint8_t dummy1[4]; /* */
volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */
};
#define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */
/* Start of channnel array defines of SCUX */
/* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT 4
#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
/* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT 2
#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
/* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT 4
#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
/* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT 4
#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
/* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT 4
#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
/* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT 4
#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
/* End of channnel array defines of SCUX */
#define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0
#define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0
#define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1
#define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1
#define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2
#define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2
#define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3
#define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3
#define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0
#define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0
#define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1
#define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1
#define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2
#define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2
#define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3
#define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3
#define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0
#define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0
#define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0
#define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0
#define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0
#define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0
#define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0
#define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1
#define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1
#define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1
#define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1
#define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1
#define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1
#define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1
#define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2
#define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2
#define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2
#define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2
#define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2
#define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2
#define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2
#define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3
#define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3
#define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3
#define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3
#define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3
#define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3
#define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3
#define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0
#define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0
#define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0
#define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0
#define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0
#define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0
#define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1
#define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1
#define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1
#define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1
#define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1
#define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1
#define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2
#define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2
#define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2
#define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2
#define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2
#define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2
#define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3
#define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3
#define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3
#define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3
#define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3
#define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3
#define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0
#define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0
#define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0
#define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0
#define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0
#define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0
#define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0
#define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0
#define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0
#define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0
#define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0
#define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0
#define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0
#define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0
#define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0
#define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0
#define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0
#define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0
#define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0
#define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0
#define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0
#define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0
#define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0
#define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0
#define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0
#define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1
#define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1
#define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1
#define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1
#define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1
#define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1
#define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1
#define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1
#define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1
#define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1
#define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1
#define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1
#define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1
#define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1
#define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1
#define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1
#define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1
#define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1
#define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1
#define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1
#define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1
#define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1
#define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1
#define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1
#define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1
#define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0
#define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0
#define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0
#define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0
#define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0
#define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0
#define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0
#define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0
#define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0
#define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0
#define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0
#define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0
#define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0
#define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0
#define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0
#define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0
#define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0
#define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0
#define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0
#define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0
#define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0
#define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1
#define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1
#define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1
#define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1
#define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1
#define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1
#define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1
#define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1
#define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1
#define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1
#define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1
#define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1
#define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1
#define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1
#define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1
#define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1
#define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1
#define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1
#define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1
#define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1
#define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1
#define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2
#define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2
#define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2
#define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2
#define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2
#define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2
#define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2
#define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2
#define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2
#define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2
#define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2
#define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2
#define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2
#define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2
#define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2
#define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2
#define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2
#define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2
#define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2
#define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2
#define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2
#define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3
#define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3
#define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3
#define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3
#define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3
#define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3
#define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3
#define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3
#define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3
#define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3
#define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3
#define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3
#define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3
#define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3
#define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3
#define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3
#define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3
#define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3
#define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3
#define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3
#define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3
#define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0
#define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0
#define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0
#define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0
#define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0
#define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0
#define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0
#define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0
#define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0
#define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0
#define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0
#define SCUXSWRSR_CIM SCUX.SWRSR_CIM
#define SCUXDMACR_CIM SCUX.DMACR_CIM
#define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32
#define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L]
#define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H]
#define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32
#define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L]
#define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H]
#define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32
#define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L]
#define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H]
#define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32
#define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L]
#define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H]
#define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32
#define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L]
#define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H]
#define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32
#define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L]
#define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H]
#define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32
#define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L]
#define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H]
#define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32
#define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L]
#define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H]
#define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM
#define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM
#define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM
#define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM
#define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM
#define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM
#define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM
#define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM
#define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM
#define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM
#define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM
#define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM
#define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM
#define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM
#define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM
#define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM
/* <-SEC M1.10.1 */
/* <-QAC 0639 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : sdg_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef SDG_IODEFINE_H
#define SDG_IODEFINE_H
struct st_sdg
{ /* SDG */
volatile uint8_t SGCR1; /* SGCR1 */
volatile uint8_t SGCSR; /* SGCSR */
volatile uint8_t SGCR2; /* SGCR2 */
volatile uint8_t SGLR; /* SGLR */
volatile uint8_t SGTFR; /* SGTFR */
volatile uint8_t SGSFR; /* SGSFR */
};
#define SDG0 (*(struct st_sdg *)0xFCFF4800uL) /* SDG0 */
#define SDG1 (*(struct st_sdg *)0xFCFF4A00uL) /* SDG1 */
#define SDG2 (*(struct st_sdg *)0xFCFF4C00uL) /* SDG2 */
#define SDG3 (*(struct st_sdg *)0xFCFF4E00uL) /* SDG3 */
/* Start of channnel array defines of SDG */
/* Channnel array defines of SDG */
/*(Sample) value = SDG[ channel ]->SGCR1; */
#define SDG_COUNT 4
#define SDG_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SDG0, &SDG1, &SDG2, &SDG3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of SDG */
#define SGCR1_0 SDG0.SGCR1
#define SGCSR_0 SDG0.SGCSR
#define SGCR2_0 SDG0.SGCR2
#define SGLR_0 SDG0.SGLR
#define SGTFR_0 SDG0.SGTFR
#define SGSFR_0 SDG0.SGSFR
#define SGCR1_1 SDG1.SGCR1
#define SGCSR_1 SDG1.SGCSR
#define SGCR2_1 SDG1.SGCR2
#define SGLR_1 SDG1.SGLR
#define SGTFR_1 SDG1.SGTFR
#define SGSFR_1 SDG1.SGSFR
#define SGCR1_2 SDG2.SGCR1
#define SGCSR_2 SDG2.SGCSR
#define SGCR2_2 SDG2.SGCR2
#define SGLR_2 SDG2.SGLR
#define SGTFR_2 SDG2.SGTFR
#define SGSFR_2 SDG2.SGSFR
#define SGCR1_3 SDG3.SGCR1
#define SGCSR_3 SDG3.SGCSR
#define SGCR2_3 SDG3.SGCR2
#define SGLR_3 SDG3.SGLR
#define SGTFR_3 SDG3.SGTFR
#define SGSFR_3 SDG3.SGSFR
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : spdif_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef SPDIF_IODEFINE_H
#define SPDIF_IODEFINE_H
struct st_spdif
{ /* SPDIF */
volatile uint32_t TLCA; /* TLCA */
volatile uint32_t TRCA; /* TRCA */
volatile uint32_t TLCS; /* TLCS */
volatile uint32_t TRCS; /* TRCS */
volatile uint32_t TUI; /* TUI */
volatile uint32_t RLCA; /* RLCA */
volatile uint32_t RRCA; /* RRCA */
volatile uint32_t RLCS; /* RLCS */
volatile uint32_t RRCS; /* RRCS */
volatile uint32_t RUI; /* RUI */
volatile uint32_t CTRL; /* CTRL */
volatile uint32_t STAT; /* STAT */
volatile uint32_t TDAD; /* TDAD */
volatile uint32_t RDAD; /* RDAD */
};
#define SPDIF (*(struct st_spdif *)0xE8012000uL) /* SPDIF */
#define SPDIFTLCA SPDIF.TLCA
#define SPDIFTRCA SPDIF.TRCA
#define SPDIFTLCS SPDIF.TLCS
#define SPDIFTRCS SPDIF.TRCS
#define SPDIFTUI SPDIF.TUI
#define SPDIFRLCA SPDIF.RLCA
#define SPDIFRRCA SPDIF.RRCA
#define SPDIFRLCS SPDIF.RLCS
#define SPDIFRRCS SPDIF.RRCS
#define SPDIFRUI SPDIF.RUI
#define SPDIFCTRL SPDIF.CTRL
#define SPDIFSTAT SPDIF.STAT
#define SPDIFTDAD SPDIF.TDAD
#define SPDIFRDAD SPDIF.RDAD
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : spibsc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef SPIBSC_IODEFINE_H
#define SPIBSC_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_spibsc
{ /* SPIBSC */
volatile uint32_t CMNCR; /* CMNCR */
volatile uint32_t SSLDR; /* SSLDR */
volatile uint32_t SPBCR; /* SPBCR */
volatile uint32_t DRCR; /* DRCR */
volatile uint32_t DRCMR; /* DRCMR */
volatile uint32_t DREAR; /* DREAR */
volatile uint32_t DROPR; /* DROPR */
volatile uint32_t DRENR; /* DRENR */
volatile uint32_t SMCR; /* SMCR */
volatile uint32_t SMCMR; /* SMCMR */
volatile uint32_t SMADR; /* SMADR */
volatile uint32_t SMOPR; /* SMOPR */
volatile uint32_t SMENR; /* SMENR */
volatile uint8_t dummy1[4]; /* */
union iodefine_reg32_t SMRDR0; /* SMRDR0 */
union iodefine_reg32_t SMRDR1; /* SMRDR1 */
union iodefine_reg32_t SMWDR0; /* SMWDR0 */
union iodefine_reg32_t SMWDR1; /* SMWDR1 */
volatile uint32_t CMNSR; /* CMNSR */
volatile uint8_t dummy2[12]; /* */
volatile uint32_t DRDMCR; /* DRDMCR */
volatile uint32_t DRDRENR; /* DRDRENR */
volatile uint32_t SMDMCR; /* SMDMCR */
volatile uint32_t SMDRENR; /* SMDRENR */
};
#define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */
#define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */
/* Start of channnel array defines of SPIBSC */
/* Channnel array defines of SPIBSC */
/*(Sample) value = SPIBSC[ channel ]->CMNCR; */
#define SPIBSC_COUNT 2
#define SPIBSC_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SPIBSC0, &SPIBSC1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of SPIBSC */
#define CMNCR_0 SPIBSC0.CMNCR
#define SSLDR_0 SPIBSC0.SSLDR
#define SPBCR_0 SPIBSC0.SPBCR
#define DRCR_0 SPIBSC0.DRCR
#define DRCMR_0 SPIBSC0.DRCMR
#define DREAR_0 SPIBSC0.DREAR
#define DROPR_0 SPIBSC0.DROPR
#define DRENR_0 SPIBSC0.DRENR
#define SMCR_0 SPIBSC0.SMCR
#define SMCMR_0 SPIBSC0.SMCMR
#define SMADR_0 SPIBSC0.SMADR
#define SMOPR_0 SPIBSC0.SMOPR
#define SMENR_0 SPIBSC0.SMENR
#define SMRDR0_0 SPIBSC0.SMRDR0.UINT32
#define SMRDR0_0L SPIBSC0.SMRDR0.UINT16[L]
#define SMRDR0_0H SPIBSC0.SMRDR0.UINT16[H]
#define SMRDR0_0LL SPIBSC0.SMRDR0.UINT8[LL]
#define SMRDR0_0LH SPIBSC0.SMRDR0.UINT8[LH]
#define SMRDR0_0HL SPIBSC0.SMRDR0.UINT8[HL]
#define SMRDR0_0HH SPIBSC0.SMRDR0.UINT8[HH]
#define SMRDR1_0 SPIBSC0.SMRDR1.UINT32
#define SMRDR1_0L SPIBSC0.SMRDR1.UINT16[L]
#define SMRDR1_0H SPIBSC0.SMRDR1.UINT16[H]
#define SMRDR1_0LL SPIBSC0.SMRDR1.UINT8[LL]
#define SMRDR1_0LH SPIBSC0.SMRDR1.UINT8[LH]
#define SMRDR1_0HL SPIBSC0.SMRDR1.UINT8[HL]
#define SMRDR1_0HH SPIBSC0.SMRDR1.UINT8[HH]
#define SMWDR0_0 SPIBSC0.SMWDR0.UINT32
#define SMWDR0_0L SPIBSC0.SMWDR0.UINT16[L]
#define SMWDR0_0H SPIBSC0.SMWDR0.UINT16[H]
#define SMWDR0_0LL SPIBSC0.SMWDR0.UINT8[LL]
#define SMWDR0_0LH SPIBSC0.SMWDR0.UINT8[LH]
#define SMWDR0_0HL SPIBSC0.SMWDR0.UINT8[HL]
#define SMWDR0_0HH SPIBSC0.SMWDR0.UINT8[HH]
#define SMWDR1_0 SPIBSC0.SMWDR1.UINT32
#define SMWDR1_0L SPIBSC0.SMWDR1.UINT16[L]
#define SMWDR1_0H SPIBSC0.SMWDR1.UINT16[H]
#define SMWDR1_0LL SPIBSC0.SMWDR1.UINT8[LL]
#define SMWDR1_0LH SPIBSC0.SMWDR1.UINT8[LH]
#define SMWDR1_0HL SPIBSC0.SMWDR1.UINT8[HL]
#define SMWDR1_0HH SPIBSC0.SMWDR1.UINT8[HH]
#define CMNSR_0 SPIBSC0.CMNSR
#define DRDMCR_0 SPIBSC0.DRDMCR
#define DRDRENR_0 SPIBSC0.DRDRENR
#define SMDMCR_0 SPIBSC0.SMDMCR
#define SMDRENR_0 SPIBSC0.SMDRENR
#define CMNCR_1 SPIBSC1.CMNCR
#define SSLDR_1 SPIBSC1.SSLDR
#define SPBCR_1 SPIBSC1.SPBCR
#define DRCR_1 SPIBSC1.DRCR
#define DRCMR_1 SPIBSC1.DRCMR
#define DREAR_1 SPIBSC1.DREAR
#define DROPR_1 SPIBSC1.DROPR
#define DRENR_1 SPIBSC1.DRENR
#define SMCR_1 SPIBSC1.SMCR
#define SMCMR_1 SPIBSC1.SMCMR
#define SMADR_1 SPIBSC1.SMADR
#define SMOPR_1 SPIBSC1.SMOPR
#define SMENR_1 SPIBSC1.SMENR
#define SMRDR0_1 SPIBSC1.SMRDR0.UINT32
#define SMRDR0_1L SPIBSC1.SMRDR0.UINT16[L]
#define SMRDR0_1H SPIBSC1.SMRDR0.UINT16[H]
#define SMRDR0_1LL SPIBSC1.SMRDR0.UINT8[LL]
#define SMRDR0_1LH SPIBSC1.SMRDR0.UINT8[LH]
#define SMRDR0_1HL SPIBSC1.SMRDR0.UINT8[HL]
#define SMRDR0_1HH SPIBSC1.SMRDR0.UINT8[HH]
#define SMRDR1_1 SPIBSC1.SMRDR1.UINT32
#define SMRDR1_1L SPIBSC1.SMRDR1.UINT16[L]
#define SMRDR1_1H SPIBSC1.SMRDR1.UINT16[H]
#define SMRDR1_1LL SPIBSC1.SMRDR1.UINT8[LL]
#define SMRDR1_1LH SPIBSC1.SMRDR1.UINT8[LH]
#define SMRDR1_1HL SPIBSC1.SMRDR1.UINT8[HL]
#define SMRDR1_1HH SPIBSC1.SMRDR1.UINT8[HH]
#define SMWDR0_1 SPIBSC1.SMWDR0.UINT32
#define SMWDR0_1L SPIBSC1.SMWDR0.UINT16[L]
#define SMWDR0_1H SPIBSC1.SMWDR0.UINT16[H]
#define SMWDR0_1LL SPIBSC1.SMWDR0.UINT8[LL]
#define SMWDR0_1LH SPIBSC1.SMWDR0.UINT8[LH]
#define SMWDR0_1HL SPIBSC1.SMWDR0.UINT8[HL]
#define SMWDR0_1HH SPIBSC1.SMWDR0.UINT8[HH]
#define SMWDR1_1 SPIBSC1.SMWDR1.UINT32
#define SMWDR1_1L SPIBSC1.SMWDR1.UINT16[L]
#define SMWDR1_1H SPIBSC1.SMWDR1.UINT16[H]
#define SMWDR1_1LL SPIBSC1.SMWDR1.UINT8[LL]
#define SMWDR1_1LH SPIBSC1.SMWDR1.UINT8[LH]
#define SMWDR1_1HL SPIBSC1.SMWDR1.UINT8[HL]
#define SMWDR1_1HH SPIBSC1.SMWDR1.UINT8[HH]
#define CMNSR_1 SPIBSC1.CMNSR
#define DRDMCR_1 SPIBSC1.DRDMCR
#define DRDRENR_1 SPIBSC1.DRDRENR
#define SMDMCR_1 SPIBSC1.SMDMCR
#define SMDRENR_1 SPIBSC1.SMDRENR
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ssif_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef SSIF_IODEFINE_H
#define SSIF_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_ssif
{ /* SSIF */
volatile uint32_t SSICR; /* SSICR */
volatile uint32_t SSISR; /* SSISR */
volatile uint8_t dummy1[8]; /* */
volatile uint32_t SSIFCR; /* SSIFCR */
volatile uint32_t SSIFSR; /* SSIFSR */
volatile uint32_t SSIFTDR; /* SSIFTDR */
volatile uint32_t SSIFRDR; /* SSIFRDR */
volatile uint32_t SSITDMR; /* SSITDMR */
volatile uint32_t SSIFCCR; /* SSIFCCR */
volatile uint32_t SSIFCMR; /* SSIFCMR */
volatile uint32_t SSIFCSR; /* SSIFCSR */
};
#define SSIF0 (*(struct st_ssif *)0xE820B000uL) /* SSIF0 */
#define SSIF1 (*(struct st_ssif *)0xE820B800uL) /* SSIF1 */
#define SSIF2 (*(struct st_ssif *)0xE820C000uL) /* SSIF2 */
#define SSIF3 (*(struct st_ssif *)0xE820C800uL) /* SSIF3 */
#define SSIF4 (*(struct st_ssif *)0xE820D000uL) /* SSIF4 */
#define SSIF5 (*(struct st_ssif *)0xE820D800uL) /* SSIF5 */
/* Start of channnel array defines of SSIF */
/* Channnel array defines of SSIF */
/*(Sample) value = SSIF[ channel ]->SSICR; */
#define SSIF_COUNT 6
#define SSIF_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of SSIF */
#define SSICR_0 SSIF0.SSICR
#define SSISR_0 SSIF0.SSISR
#define SSIFCR_0 SSIF0.SSIFCR
#define SSIFSR_0 SSIF0.SSIFSR
#define SSIFTDR_0 SSIF0.SSIFTDR
#define SSIFRDR_0 SSIF0.SSIFRDR
#define SSITDMR_0 SSIF0.SSITDMR
#define SSIFCCR_0 SSIF0.SSIFCCR
#define SSIFCMR_0 SSIF0.SSIFCMR
#define SSIFCSR_0 SSIF0.SSIFCSR
#define SSICR_1 SSIF1.SSICR
#define SSISR_1 SSIF1.SSISR
#define SSIFCR_1 SSIF1.SSIFCR
#define SSIFSR_1 SSIF1.SSIFSR
#define SSIFTDR_1 SSIF1.SSIFTDR
#define SSIFRDR_1 SSIF1.SSIFRDR
#define SSITDMR_1 SSIF1.SSITDMR
#define SSIFCCR_1 SSIF1.SSIFCCR
#define SSIFCMR_1 SSIF1.SSIFCMR
#define SSIFCSR_1 SSIF1.SSIFCSR
#define SSICR_2 SSIF2.SSICR
#define SSISR_2 SSIF2.SSISR
#define SSIFCR_2 SSIF2.SSIFCR
#define SSIFSR_2 SSIF2.SSIFSR
#define SSIFTDR_2 SSIF2.SSIFTDR
#define SSIFRDR_2 SSIF2.SSIFRDR
#define SSITDMR_2 SSIF2.SSITDMR
#define SSIFCCR_2 SSIF2.SSIFCCR
#define SSIFCMR_2 SSIF2.SSIFCMR
#define SSIFCSR_2 SSIF2.SSIFCSR
#define SSICR_3 SSIF3.SSICR
#define SSISR_3 SSIF3.SSISR
#define SSIFCR_3 SSIF3.SSIFCR
#define SSIFSR_3 SSIF3.SSIFSR
#define SSIFTDR_3 SSIF3.SSIFTDR
#define SSIFRDR_3 SSIF3.SSIFRDR
#define SSITDMR_3 SSIF3.SSITDMR
#define SSIFCCR_3 SSIF3.SSIFCCR
#define SSIFCMR_3 SSIF3.SSIFCMR
#define SSIFCSR_3 SSIF3.SSIFCSR
#define SSICR_4 SSIF4.SSICR
#define SSISR_4 SSIF4.SSISR
#define SSIFCR_4 SSIF4.SSIFCR
#define SSIFSR_4 SSIF4.SSIFSR
#define SSIFTDR_4 SSIF4.SSIFTDR
#define SSIFRDR_4 SSIF4.SSIFRDR
#define SSITDMR_4 SSIF4.SSITDMR
#define SSIFCCR_4 SSIF4.SSIFCCR
#define SSIFCMR_4 SSIF4.SSIFCMR
#define SSIFCSR_4 SSIF4.SSIFCSR
#define SSICR_5 SSIF5.SSICR
#define SSISR_5 SSIF5.SSISR
#define SSIFCR_5 SSIF5.SSIFCR
#define SSIFSR_5 SSIF5.SSIFSR
#define SSIFTDR_5 SSIF5.SSIFTDR
#define SSIFRDR_5 SSIF5.SSIFRDR
#define SSITDMR_5 SSIF5.SSITDMR
#define SSIFCCR_5 SSIF5.SSIFCCR
#define SSIFCMR_5 SSIF5.SSIFCMR
#define SSIFCSR_5 SSIF5.SSIFCSR
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : usb20_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef USB20_IODEFINE_H
#define USB20_IODEFINE_H
/* ->SEC M1.10.1 : Not magic number */
struct st_usb20
{ /* USB20 */
volatile uint16_t SYSCFG0; /* SYSCFG0 */
volatile uint16_t BUSWAIT; /* BUSWAIT */
volatile uint16_t SYSSTS0; /* SYSSTS0 */
volatile uint8_t dummy1[2]; /* */
volatile uint16_t DVSTCTR0; /* DVSTCTR0 */
volatile uint8_t dummy2[2]; /* */
volatile uint16_t TESTMODE; /* TESTMODE */
volatile uint8_t dummy3[2]; /* */
#define USB20_D0FBCFG_COUNT 2
volatile uint16_t D0FBCFG; /* D0FBCFG */
volatile uint16_t D1FBCFG; /* D1FBCFG */
union iodefine_reg32_t CFIFO; /* CFIFO */
#define USB20_D0FIFO_COUNT 2
union iodefine_reg32_t D0FIFO; /* D0FIFO */
union iodefine_reg32_t D1FIFO; /* D1FIFO */
volatile uint16_t CFIFOSEL; /* CFIFOSEL */
volatile uint16_t CFIFOCTR; /* CFIFOCTR */
volatile uint8_t dummy4[4]; /* */
/* start of struct st_usb20_from_d0fifosel */
volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */
volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */
/* end of struct st_usb20_from_d0fifosel */
/* start of struct st_usb20_from_d0fifosel */
volatile uint16_t D1FIFOSEL; /* D1FIFOSEL */
volatile uint16_t D1FIFOCTR; /* D1FIFOCTR */
/* end of struct st_usb20_from_d0fifosel */
#define USB20_INTENB0_COUNT 2
volatile uint16_t INTENB0; /* INTENB0 */
volatile uint16_t INTENB1; /* INTENB1 */
volatile uint8_t dummy5[2]; /* */
volatile uint16_t BRDYENB; /* BRDYENB */
volatile uint16_t NRDYENB; /* NRDYENB */
volatile uint16_t BEMPENB; /* BEMPENB */
volatile uint16_t SOFCFG; /* SOFCFG */
volatile uint8_t dummy6[2]; /* */
#define USB20_INTSTS0_COUNT 2
volatile uint16_t INTSTS0; /* INTSTS0 */
volatile uint16_t INTSTS1; /* INTSTS1 */
volatile uint8_t dummy7[2]; /* */
volatile uint16_t BRDYSTS; /* BRDYSTS */
volatile uint16_t NRDYSTS; /* NRDYSTS */
volatile uint16_t BEMPSTS; /* BEMPSTS */
volatile uint16_t FRMNUM; /* FRMNUM */
volatile uint16_t UFRMNUM; /* UFRMNUM */
volatile uint16_t USBADDR; /* USBADDR */
volatile uint8_t dummy8[2]; /* */
volatile uint16_t USBREQ; /* USBREQ */
volatile uint16_t USBVAL; /* USBVAL */
volatile uint16_t USBINDX; /* USBINDX */
volatile uint16_t USBLENG; /* USBLENG */
volatile uint16_t DCPCFG; /* DCPCFG */
volatile uint16_t DCPMAXP; /* DCPMAXP */
volatile uint16_t DCPCTR; /* DCPCTR */
volatile uint8_t dummy9[2]; /* */
volatile uint16_t PIPESEL; /* PIPESEL */
volatile uint8_t dummy10[2]; /* */
volatile uint16_t PIPECFG; /* PIPECFG */
volatile uint16_t PIPEBUF; /* PIPEBUF */
volatile uint16_t PIPEMAXP; /* PIPEMAXP */
volatile uint16_t PIPEPERI; /* PIPEPERI */
#define USB20_PIPE1CTR_COUNT 0xF
volatile uint16_t PIPE1CTR; /* PIPE1CTR */
volatile uint16_t PIPE2CTR; /* PIPE2CTR */
volatile uint16_t PIPE3CTR; /* PIPE3CTR */
volatile uint16_t PIPE4CTR; /* PIPE4CTR */
volatile uint16_t PIPE5CTR; /* PIPE5CTR */
volatile uint16_t PIPE6CTR; /* PIPE6CTR */
volatile uint16_t PIPE7CTR; /* PIPE7CTR */
volatile uint16_t PIPE8CTR; /* PIPE8CTR */
volatile uint16_t PIPE9CTR; /* PIPE9CTR */
volatile uint16_t PIPEACTR; /* PIPEACTR */
volatile uint16_t PIPEBCTR; /* PIPEBCTR */
volatile uint16_t PIPECCTR; /* PIPECCTR */
volatile uint16_t PIPEDCTR; /* PIPEDCTR */
volatile uint16_t PIPEECTR; /* PIPEECTR */
volatile uint16_t PIPEFCTR; /* PIPEFCTR */
volatile uint8_t dummy11[2]; /* */
/* start of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPE1TRE; /* PIPE1TRE */
volatile uint16_t PIPE1TRN; /* PIPE1TRN */
/* end of struct st_usb20_from_pipe1tre */
/* start of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPE2TRE; /* PIPE2TRE */
volatile uint16_t PIPE2TRN; /* PIPE2TRN */
/* end of struct st_usb20_from_pipe1tre */
/* start of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPE3TRE; /* PIPE3TRE */
volatile uint16_t PIPE3TRN; /* PIPE3TRN */
/* end of struct st_usb20_from_pipe1tre */
/* start of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPE4TRE; /* PIPE4TRE */
volatile uint16_t PIPE4TRN; /* PIPE4TRN */
/* end of struct st_usb20_from_pipe1tre */
/* start of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPE5TRE; /* PIPE5TRE */
volatile uint16_t PIPE5TRN; /* PIPE5TRN */
/* end of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPEBTRE; /* PIPEBTRE */
volatile uint16_t PIPEBTRN; /* PIPEBTRN */
volatile uint16_t PIPECTRE; /* PIPECTRE */
volatile uint16_t PIPECTRN; /* PIPECTRN */
volatile uint16_t PIPEDTRE; /* PIPEDTRE */
volatile uint16_t PIPEDTRN; /* PIPEDTRN */
volatile uint16_t PIPEETRE; /* PIPEETRE */
volatile uint16_t PIPEETRN; /* PIPEETRN */
volatile uint16_t PIPEFTRE; /* PIPEFTRE */
volatile uint16_t PIPEFTRN; /* PIPEFTRN */
volatile uint16_t PIPE9TRE; /* PIPE9TRE */
volatile uint16_t PIPE9TRN; /* PIPE9TRN */
volatile uint16_t PIPEATRE; /* PIPEATRE */
volatile uint16_t PIPEATRN; /* PIPEATRN */
volatile uint8_t dummy12[16]; /* */
#define USB20_DEVADD0_COUNT 0xB
volatile uint16_t DEVADD0; /* DEVADD0 */
volatile uint16_t DEVADD1; /* DEVADD1 */
volatile uint16_t DEVADD2; /* DEVADD2 */
volatile uint16_t DEVADD3; /* DEVADD3 */
volatile uint16_t DEVADD4; /* DEVADD4 */
volatile uint16_t DEVADD5; /* DEVADD5 */
volatile uint16_t DEVADD6; /* DEVADD6 */
volatile uint16_t DEVADD7; /* DEVADD7 */
volatile uint16_t DEVADD8; /* DEVADD8 */
volatile uint16_t DEVADD9; /* DEVADD9 */
volatile uint16_t DEVADDA; /* DEVADDA */
volatile uint8_t dummy13[28]; /* */
volatile uint16_t SUSPMODE; /* SUSPMODE */
volatile uint8_t dummy14[92]; /* */
/* start of struct st_usb20_from_dmfifob0 */
volatile uint32_t D0FIFOB0; /* D0FIFOB0 */
volatile uint32_t D0FIFOB1; /* D0FIFOB1 */
volatile uint32_t D0FIFOB2; /* D0FIFOB2 */
volatile uint32_t D0FIFOB3; /* D0FIFOB3 */
volatile uint32_t D0FIFOB4; /* D0FIFOB4 */
volatile uint32_t D0FIFOB5; /* D0FIFOB5 */
volatile uint32_t D0FIFOB6; /* D0FIFOB6 */
volatile uint32_t D0FIFOB7; /* D0FIFOB7 */
/* end of struct st_usb20_from_dmfifob0 */
/* start of struct st_usb20_from_dmfifob0 */
volatile uint32_t D1FIFOB0; /* D1FIFOB0 */
volatile uint32_t D1FIFOB1; /* D1FIFOB1 */
volatile uint32_t D1FIFOB2; /* D1FIFOB2 */
volatile uint32_t D1FIFOB3; /* D1FIFOB3 */
volatile uint32_t D1FIFOB4; /* D1FIFOB4 */
volatile uint32_t D1FIFOB5; /* D1FIFOB5 */
volatile uint32_t D1FIFOB6; /* D1FIFOB6 */
volatile uint32_t D1FIFOB7; /* D1FIFOB7 */
/* end of struct st_usb20_from_dmfifob0 */
};
struct st_usb20_from_d0fifosel
{
volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */
volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */
};
struct st_usb20_from_pipe1tre
{
volatile uint16_t PIPE1TRE; /* PIPE1TRE */
volatile uint16_t PIPE1TRN; /* PIPE1TRN */
};
struct st_usb20_from_dmfifob0
{
#define USB20_D0FIFOB0_COUNT 0x8
volatile uint32_t D0FIFOB0; /* D0FIFOB0 */
volatile uint32_t D0FIFOB1; /* D0FIFOB1 */
volatile uint32_t D0FIFOB2; /* D0FIFOB2 */
volatile uint32_t D0FIFOB3; /* D0FIFOB3 */
volatile uint32_t D0FIFOB4; /* D0FIFOB4 */
volatile uint32_t D0FIFOB5; /* D0FIFOB5 */
volatile uint32_t D0FIFOB6; /* D0FIFOB6 */
volatile uint32_t D0FIFOB7; /* D0FIFOB7 */
};
#define USB200 (*(struct st_usb20 *)0xE8010000uL) /* USB200 */
#define USB201 (*(struct st_usb20 *)0xE8207000uL) /* USB201 */
/* Start of channnel array defines of USB20 */
/* Channnel array defines of USB20 */
/*(Sample) value = USB20[ channel ]->SYSCFG0; */
#define USB20_COUNT 2
#define USB20_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&USB200, &USB201 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* Channnel array defines of USB20_FROM_D0FIFOB0 */
/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */
#define USB20_FROM_D0FIFOB0_COUNT 2
#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
{ \
&USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \
&USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \
} \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */
#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */
#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */
#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */
/* Channnel array defines of USB20_FROM_PIPE1ATRE */
/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */
#define USB20_FROM_PIPE1ATRE_COUNT 5
#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
{ \
&USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \
&USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \
} \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */
#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */
#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */
#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */
#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */
#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */
#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */
#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */
#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */
#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */
/* Channnel array defines of USB20_FROM_D0FIFOSEL */
/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */
#define USB20_FROM_D0FIFOSEL_COUNT 2
#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
{ \
&USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \
&USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \
} \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */
#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */
#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */
#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */
/* End of channnel array defines of USB20 */
#define SYSCFG0_0 USB200.SYSCFG0
#define BUSWAIT_0 USB200.BUSWAIT
#define SYSSTS0_0 USB200.SYSSTS0
#define DVSTCTR0_0 USB200.DVSTCTR0
#define TESTMODE_0 USB200.TESTMODE
#define D0FBCFG_0 USB200.D0FBCFG
#define D1FBCFG_0 USB200.D1FBCFG
#define CFIFO_0 USB200.CFIFO.UINT32
#define CFIFO_0L USB200.CFIFO.UINT16[L]
#define CFIFO_0H USB200.CFIFO.UINT16[H]
#define CFIFO_0LL USB200.CFIFO.UINT8[LL]
#define CFIFO_0LH USB200.CFIFO.UINT8[LH]
#define CFIFO_0HL USB200.CFIFO.UINT8[HL]
#define CFIFO_0HH USB200.CFIFO.UINT8[HH]
#define D0FIFO_0 USB200.D0FIFO.UINT32
#define D0FIFO_0L USB200.D0FIFO.UINT16[L]
#define D0FIFO_0H USB200.D0FIFO.UINT16[H]
#define D0FIFO_0LL USB200.D0FIFO.UINT8[LL]
#define D0FIFO_0LH USB200.D0FIFO.UINT8[LH]
#define D0FIFO_0HL USB200.D0FIFO.UINT8[HL]
#define D0FIFO_0HH USB200.D0FIFO.UINT8[HH]
#define D1FIFO_0 USB200.D1FIFO.UINT32
#define D1FIFO_0L USB200.D1FIFO.UINT16[L]
#define D1FIFO_0H USB200.D1FIFO.UINT16[H]
#define D1FIFO_0LL USB200.D1FIFO.UINT8[LL]
#define D1FIFO_0LH USB200.D1FIFO.UINT8[LH]
#define D1FIFO_0HL USB200.D1FIFO.UINT8[HL]
#define D1FIFO_0HH USB200.D1FIFO.UINT8[HH]
#define CFIFOSEL_0 USB200.CFIFOSEL
#define CFIFOCTR_0 USB200.CFIFOCTR
#define D0FIFOSEL_0 USB200.D0FIFOSEL
#define D0FIFOCTR_0 USB200.D0FIFOCTR
#define D1FIFOSEL_0 USB200.D1FIFOSEL
#define D1FIFOCTR_0 USB200.D1FIFOCTR
#define INTENB0_0 USB200.INTENB0
#define INTENB1_0 USB200.INTENB1
#define BRDYENB_0 USB200.BRDYENB
#define NRDYENB_0 USB200.NRDYENB
#define BEMPENB_0 USB200.BEMPENB
#define SOFCFG_0 USB200.SOFCFG
#define INTSTS0_0 USB200.INTSTS0
#define INTSTS1_0 USB200.INTSTS1
#define BRDYSTS_0 USB200.BRDYSTS
#define NRDYSTS_0 USB200.NRDYSTS
#define BEMPSTS_0 USB200.BEMPSTS
#define FRMNUM_0 USB200.FRMNUM
#define UFRMNUM_0 USB200.UFRMNUM
#define USBADDR_0 USB200.USBADDR
#define USBREQ_0 USB200.USBREQ
#define USBVAL_0 USB200.USBVAL
#define USBINDX_0 USB200.USBINDX
#define USBLENG_0 USB200.USBLENG
#define DCPCFG_0 USB200.DCPCFG
#define DCPMAXP_0 USB200.DCPMAXP
#define DCPCTR_0 USB200.DCPCTR
#define PIPESEL_0 USB200.PIPESEL
#define PIPECFG_0 USB200.PIPECFG
#define PIPEBUF_0 USB200.PIPEBUF
#define PIPEMAXP_0 USB200.PIPEMAXP
#define PIPEPERI_0 USB200.PIPEPERI
#define PIPE1CTR_0 USB200.PIPE1CTR
#define PIPE2CTR_0 USB200.PIPE2CTR
#define PIPE3CTR_0 USB200.PIPE3CTR
#define PIPE4CTR_0 USB200.PIPE4CTR
#define PIPE5CTR_0 USB200.PIPE5CTR
#define PIPE6CTR_0 USB200.PIPE6CTR
#define PIPE7CTR_0 USB200.PIPE7CTR
#define PIPE8CTR_0 USB200.PIPE8CTR
#define PIPE9CTR_0 USB200.PIPE9CTR
#define PIPEACTR_0 USB200.PIPEACTR
#define PIPEBCTR_0 USB200.PIPEBCTR
#define PIPECCTR_0 USB200.PIPECCTR
#define PIPEDCTR_0 USB200.PIPEDCTR
#define PIPEECTR_0 USB200.PIPEECTR
#define PIPEFCTR_0 USB200.PIPEFCTR
#define PIPE1TRE_0 USB200.PIPE1TRE
#define PIPE1TRN_0 USB200.PIPE1TRN
#define PIPE2TRE_0 USB200.PIPE2TRE
#define PIPE2TRN_0 USB200.PIPE2TRN
#define PIPE3TRE_0 USB200.PIPE3TRE
#define PIPE3TRN_0 USB200.PIPE3TRN
#define PIPE4TRE_0 USB200.PIPE4TRE
#define PIPE4TRN_0 USB200.PIPE4TRN
#define PIPE5TRE_0 USB200.PIPE5TRE
#define PIPE5TRN_0 USB200.PIPE5TRN
#define PIPEBTRE_0 USB200.PIPEBTRE
#define PIPEBTRN_0 USB200.PIPEBTRN
#define PIPECTRE_0 USB200.PIPECTRE
#define PIPECTRN_0 USB200.PIPECTRN
#define PIPEDTRE_0 USB200.PIPEDTRE
#define PIPEDTRN_0 USB200.PIPEDTRN
#define PIPEETRE_0 USB200.PIPEETRE
#define PIPEETRN_0 USB200.PIPEETRN
#define PIPEFTRE_0 USB200.PIPEFTRE
#define PIPEFTRN_0 USB200.PIPEFTRN
#define PIPE9TRE_0 USB200.PIPE9TRE
#define PIPE9TRN_0 USB200.PIPE9TRN
#define PIPEATRE_0 USB200.PIPEATRE
#define PIPEATRN_0 USB200.PIPEATRN
#define DEVADD0_0 USB200.DEVADD0
#define DEVADD1_0 USB200.DEVADD1
#define DEVADD2_0 USB200.DEVADD2
#define DEVADD3_0 USB200.DEVADD3
#define DEVADD4_0 USB200.DEVADD4
#define DEVADD5_0 USB200.DEVADD5
#define DEVADD6_0 USB200.DEVADD6
#define DEVADD7_0 USB200.DEVADD7
#define DEVADD8_0 USB200.DEVADD8
#define DEVADD9_0 USB200.DEVADD9
#define DEVADDA_0 USB200.DEVADDA
#define SUSPMODE_0 USB200.SUSPMODE
#define D0FIFOB0_0 USB200.D0FIFOB0
#define D0FIFOB1_0 USB200.D0FIFOB1
#define D0FIFOB2_0 USB200.D0FIFOB2
#define D0FIFOB3_0 USB200.D0FIFOB3
#define D0FIFOB4_0 USB200.D0FIFOB4
#define D0FIFOB5_0 USB200.D0FIFOB5
#define D0FIFOB6_0 USB200.D0FIFOB6
#define D0FIFOB7_0 USB200.D0FIFOB7
#define D1FIFOB0_0 USB200.D1FIFOB0
#define D1FIFOB1_0 USB200.D1FIFOB1
#define D1FIFOB2_0 USB200.D1FIFOB2
#define D1FIFOB3_0 USB200.D1FIFOB3
#define D1FIFOB4_0 USB200.D1FIFOB4
#define D1FIFOB5_0 USB200.D1FIFOB5
#define D1FIFOB6_0 USB200.D1FIFOB6
#define D1FIFOB7_0 USB200.D1FIFOB7
#define SYSCFG0_1 USB201.SYSCFG0
#define BUSWAIT_1 USB201.BUSWAIT
#define SYSSTS0_1 USB201.SYSSTS0
#define DVSTCTR0_1 USB201.DVSTCTR0
#define TESTMODE_1 USB201.TESTMODE
#define D0FBCFG_1 USB201.D0FBCFG
#define D1FBCFG_1 USB201.D1FBCFG
#define CFIFO_1 USB201.CFIFO.UINT32
#define CFIFO_1L USB201.CFIFO.UINT16[L]
#define CFIFO_1H USB201.CFIFO.UINT16[H]
#define CFIFO_1LL USB201.CFIFO.UINT8[LL]
#define CFIFO_1LH USB201.CFIFO.UINT8[LH]
#define CFIFO_1HL USB201.CFIFO.UINT8[HL]
#define CFIFO_1HH USB201.CFIFO.UINT8[HH]
#define D0FIFO_1 USB201.D0FIFO.UINT32
#define D0FIFO_1L USB201.D0FIFO.UINT16[L]
#define D0FIFO_1H USB201.D0FIFO.UINT16[H]
#define D0FIFO_1LL USB201.D0FIFO.UINT8[LL]
#define D0FIFO_1LH USB201.D0FIFO.UINT8[LH]
#define D0FIFO_1HL USB201.D0FIFO.UINT8[HL]
#define D0FIFO_1HH USB201.D0FIFO.UINT8[HH]
#define D1FIFO_1 USB201.D1FIFO.UINT32
#define D1FIFO_1L USB201.D1FIFO.UINT16[L]
#define D1FIFO_1H USB201.D1FIFO.UINT16[H]
#define D1FIFO_1LL USB201.D1FIFO.UINT8[LL]
#define D1FIFO_1LH USB201.D1FIFO.UINT8[LH]
#define D1FIFO_1HL USB201.D1FIFO.UINT8[HL]
#define D1FIFO_1HH USB201.D1FIFO.UINT8[HH]
#define CFIFOSEL_1 USB201.CFIFOSEL
#define CFIFOCTR_1 USB201.CFIFOCTR
#define D0FIFOSEL_1 USB201.D0FIFOSEL
#define D0FIFOCTR_1 USB201.D0FIFOCTR
#define D1FIFOSEL_1 USB201.D1FIFOSEL
#define D1FIFOCTR_1 USB201.D1FIFOCTR
#define INTENB0_1 USB201.INTENB0
#define INTENB1_1 USB201.INTENB1
#define BRDYENB_1 USB201.BRDYENB
#define NRDYENB_1 USB201.NRDYENB
#define BEMPENB_1 USB201.BEMPENB
#define SOFCFG_1 USB201.SOFCFG
#define INTSTS0_1 USB201.INTSTS0
#define INTSTS1_1 USB201.INTSTS1
#define BRDYSTS_1 USB201.BRDYSTS
#define NRDYSTS_1 USB201.NRDYSTS
#define BEMPSTS_1 USB201.BEMPSTS
#define FRMNUM_1 USB201.FRMNUM
#define UFRMNUM_1 USB201.UFRMNUM
#define USBADDR_1 USB201.USBADDR
#define USBREQ_1 USB201.USBREQ
#define USBVAL_1 USB201.USBVAL
#define USBINDX_1 USB201.USBINDX
#define USBLENG_1 USB201.USBLENG
#define DCPCFG_1 USB201.DCPCFG
#define DCPMAXP_1 USB201.DCPMAXP
#define DCPCTR_1 USB201.DCPCTR
#define PIPESEL_1 USB201.PIPESEL
#define PIPECFG_1 USB201.PIPECFG
#define PIPEBUF_1 USB201.PIPEBUF
#define PIPEMAXP_1 USB201.PIPEMAXP
#define PIPEPERI_1 USB201.PIPEPERI
#define PIPE1CTR_1 USB201.PIPE1CTR
#define PIPE2CTR_1 USB201.PIPE2CTR
#define PIPE3CTR_1 USB201.PIPE3CTR
#define PIPE4CTR_1 USB201.PIPE4CTR
#define PIPE5CTR_1 USB201.PIPE5CTR
#define PIPE6CTR_1 USB201.PIPE6CTR
#define PIPE7CTR_1 USB201.PIPE7CTR
#define PIPE8CTR_1 USB201.PIPE8CTR
#define PIPE9CTR_1 USB201.PIPE9CTR
#define PIPEACTR_1 USB201.PIPEACTR
#define PIPEBCTR_1 USB201.PIPEBCTR
#define PIPECCTR_1 USB201.PIPECCTR
#define PIPEDCTR_1 USB201.PIPEDCTR
#define PIPEECTR_1 USB201.PIPEECTR
#define PIPEFCTR_1 USB201.PIPEFCTR
#define PIPE1TRE_1 USB201.PIPE1TRE
#define PIPE1TRN_1 USB201.PIPE1TRN
#define PIPE2TRE_1 USB201.PIPE2TRE
#define PIPE2TRN_1 USB201.PIPE2TRN
#define PIPE3TRE_1 USB201.PIPE3TRE
#define PIPE3TRN_1 USB201.PIPE3TRN
#define PIPE4TRE_1 USB201.PIPE4TRE
#define PIPE4TRN_1 USB201.PIPE4TRN
#define PIPE5TRE_1 USB201.PIPE5TRE
#define PIPE5TRN_1 USB201.PIPE5TRN
#define PIPEBTRE_1 USB201.PIPEBTRE
#define PIPEBTRN_1 USB201.PIPEBTRN
#define PIPECTRE_1 USB201.PIPECTRE
#define PIPECTRN_1 USB201.PIPECTRN
#define PIPEDTRE_1 USB201.PIPEDTRE
#define PIPEDTRN_1 USB201.PIPEDTRN
#define PIPEETRE_1 USB201.PIPEETRE
#define PIPEETRN_1 USB201.PIPEETRN
#define PIPEFTRE_1 USB201.PIPEFTRE
#define PIPEFTRN_1 USB201.PIPEFTRN
#define PIPE9TRE_1 USB201.PIPE9TRE
#define PIPE9TRN_1 USB201.PIPE9TRN
#define PIPEATRE_1 USB201.PIPEATRE
#define PIPEATRN_1 USB201.PIPEATRN
#define DEVADD0_1 USB201.DEVADD0
#define DEVADD1_1 USB201.DEVADD1
#define DEVADD2_1 USB201.DEVADD2
#define DEVADD3_1 USB201.DEVADD3
#define DEVADD4_1 USB201.DEVADD4
#define DEVADD5_1 USB201.DEVADD5
#define DEVADD6_1 USB201.DEVADD6
#define DEVADD7_1 USB201.DEVADD7
#define DEVADD8_1 USB201.DEVADD8
#define DEVADD9_1 USB201.DEVADD9
#define DEVADDA_1 USB201.DEVADDA
#define SUSPMODE_1 USB201.SUSPMODE
#define D0FIFOB0_1 USB201.D0FIFOB0
#define D0FIFOB1_1 USB201.D0FIFOB1
#define D0FIFOB2_1 USB201.D0FIFOB2
#define D0FIFOB3_1 USB201.D0FIFOB3
#define D0FIFOB4_1 USB201.D0FIFOB4
#define D0FIFOB5_1 USB201.D0FIFOB5
#define D0FIFOB6_1 USB201.D0FIFOB6
#define D0FIFOB7_1 USB201.D0FIFOB7
#define D1FIFOB0_1 USB201.D1FIFOB0
#define D1FIFOB1_1 USB201.D1FIFOB1
#define D1FIFOB2_1 USB201.D1FIFOB2
#define D1FIFOB3_1 USB201.D1FIFOB3
#define D1FIFOB4_1 USB201.D1FIFOB4
#define D1FIFOB5_1 USB201.D1FIFOB5
#define D1FIFOB6_1 USB201.D1FIFOB6
#define D1FIFOB7_1 USB201.D1FIFOB7
/* <-SEC M1.10.1 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : wdt_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
******************************************************************************/
#ifndef WDT_IODEFINE_H
#define WDT_IODEFINE_H
struct st_wdt
{ /* WDT */
volatile uint16_t WTCSR; /* WTCSR */
volatile uint16_t WTCNT; /* WTCNT */
volatile uint16_t WRCSR; /* WRCSR */
};
#define WDT (*(struct st_wdt *)0xFCFE0000uL) /* WDT */
#define WDTWTCSR WDT.WTCSR
#define WDTWTCNT WDT.WTCNT
#define WDTWRCSR WDT.WRCSR
#endif

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#ifndef __REG32_T
#define __REG32_T
union reg32_t {
volatile uint32_t UINT32;
volatile uint16_t UINT16[2];
volatile uint8_t UINT8[4];
};
#endif

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/**************************************************************************//**
* @file mmu_Renesas_RZ_A1.c
* @brief MMU Startup File for
* mmu_Renesas_RZ_A1 Device Series
* @version V1.01
* @date 2 Aug 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
#define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
#define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
#define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
// Write-Through support *not* available
// Write-Back support available.
// Read allocation support available.
// Write allocation support available.
//Note: You should use the Shareable attribute carefully.
//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless the inner cache settings.
//CA9-RTX uses LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
//Some A9 implementations does not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
//Following MMU configuration is expected
//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
//Domain 0 is always the Client domain
//Descriptors place all memory in domain 0
//There are no restrictions by privilege level (PL0 can access all memory)
#include <stdint.h>
#include "MBRZA1H.h"
//Import symbols from linker
extern uint32_t Image$$VECTORS$$Base;
extern uint32_t Image$$RO_DATA$$Base;
extern uint32_t Image$$RW_DATA$$Base;
extern uint32_t Image$$ZI_DATA$$Base;
extern uint32_t Image$$TTB$$ZI$$Base;
static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0
static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
/* Define global descriptors */
static uint32_t Page_L1_4k = 0x0; //generic
static uint32_t Page_L1_64k = 0x0; //generic
static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
void create_translation_table(void)
{
mmu_region_attributes_Type region;
/*
* Generate descriptors. Refer to MBRZA1H.h to get information about attributes
*
*/
//Create descriptors for Vectors, RO, RW, ZI sections
section_normal(Sect_Normal, region);
section_normal_cod(Sect_Normal_Cod, region);
section_normal_ro(Sect_Normal_RO, region);
section_normal_rw(Sect_Normal_RW, region);
//Create descriptors for peripherals
section_device_ro(Sect_Device_RO, region);
section_device_rw(Sect_Device_RW, region);
section_normal_nc(Sect_Normal_NC, region);
//Create descriptors for 64k pages
page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
//Create descriptors for 4k pages
page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
/*
* Define MMU flat-map regions and attributes
*
*/
//Create 4GB of faulting entries
__TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
// R7S72100 memory map.
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA0 , 64, Sect_Normal_RW);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA1 , 64, Sect_Normal_RW);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO0 , 64, Sect_Normal_RO);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO1 , 64, Sect_Normal_RO);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_BSC_BASE , 1, Sect_Device_RW);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW);
//Define Image
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 1, Sect_Normal_Cod);
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, 1, Sect_Normal_RO);
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW);
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC);
/* Set location of level 1 page table
; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
; 13:7 - 0x0
; 6 - IRGN[0] 0x0 (Inner WB WA)
; 5 - NOS 0x0 (Non-shared)
; 4:3 - RGN 0x1 (Outer WB WA)
; 2 - IMP 0x0 (Implementation Defined)
; 1 - S 0x0 (Non-shared)
; 0 - IRGN[1] 0x1 (Inner WB WA) */
__set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
/* Set up domain access control register
; We set domain 0 to Client and all other domains to No Access.
; All translation table entries specify domain 0 */
__set_DACR(1);
}
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

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/**************************************************************************//**
* @file pl310.c
* @brief Implementation of pl310 functions
* @version
* @date 11 June 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#include "MBRZA1H.h"
//Cache Sync operation
void PL310_Sync(void)
{
PL310->CACHE_SYNC = 0x0;
}
//return Cache controller cache ID
int PL310_GetID (void)
{
return PL310->CACHE_ID;
}
//return Cache controller cache Type
int PL310_GetType (void)
{
return PL310->CACHE_TYPE;
}
//Invalidate all cache by way
void PL310_InvAllByWay (void)
{
unsigned int assoc;
if (PL310->AUX_CNT & (1<<16))
assoc = 16;
else
assoc = 8;
PL310->INV_WAY = (1 << assoc) - 1;
while(PL310->INV_WAY && ((1 << assoc) - 1)); //poll invalidate
PL310_Sync();
}
//Clean and Invalidate all cache by way
void PL310_CleanInvAllByWay (void)
{
unsigned int assoc;
if (PL310->AUX_CNT & (1<<16))
assoc = 16;
else
assoc = 8;
PL310->CLEAN_INV_WAY = (1 << assoc) - 1;
while(PL310->CLEAN_INV_WAY && ((1 << assoc) - 1)); //poll invalidate
PL310_Sync();
}
//Enable Cache
void PL310_Enable(void)
{
PL310->CONTROL = 0;
PL310->INTERRUPT_CLEAR = 0;
PL310->DEBUG_CONTROL = 0;
PL310->DATA_LOCK_0_WAY = 0;
PL310->CACHE_SYNC = 0;
PL310->CONTROL = 0x01;
PL310_Sync();
}
//Disable Cache
void PL310_Disable(void)
{
PL310->CONTROL = 0x00;
PL310_Sync();
}
//Invalidate cache by physical address
void PL310_InvPa (void *pa)
{
PL310->INV_LINE_PA = (unsigned int)pa;
PL310_Sync();
}
//Clean cache by physical address
void PL310_CleanPa (void *pa)
{
PL310->CLEAN_LINE_PA = (unsigned int)pa;
PL310_Sync();
}
//Clean and invalidate cache by physical address
void PL310_CleanInvPa (void *pa)
{
PL310->CLEAN_INV_LINE_PA = (unsigned int)pa;
PL310_Sync();
}

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/**************************************************************************//**
* @file pl310.h
* @brief Implementation of pl310 functions
* @version
* @date 11 June 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __PL310
#define __PL310
typedef struct
{
__I uint32_t CACHE_ID; /*!< Offset: 0x0000 Cache ID Register */
__I uint32_t CACHE_TYPE; /*!< Offset: 0x0004 Cache Type Register */
uint32_t RESERVED0[0x3e];
__IO uint32_t CONTROL; /*!< Offset: 0x0100 Control Register */
__IO uint32_t AUX_CNT; /*!< Offset: 0x0104 Auxiliary Control */
uint32_t RESERVED1[0x3e];
__IO uint32_t EVENT_CONTROL; /*!< Offset: 0x0200 Event Counter Control */
__IO uint32_t EVENT_COUNTER1_CONF; /*!< Offset: 0x0204 Event Counter 1 Configuration */
__IO uint32_t EVENT_COUNTER0_CONF; /*!< Offset: 0x0208 Event Counter 1 Configuration */
uint32_t RESERVED2[0x2];
__IO uint32_t INTERRUPT_MASK; /*!< Offset: 0x0214 Interrupt Mask */
__I uint32_t MASKED_INT_STATUS; /*!< Offset: 0x0218 Masked Interrupt Status */
__I uint32_t RAW_INT_STATUS; /*!< Offset: 0x021c Raw Interrupt Status */
__O uint32_t INTERRUPT_CLEAR; /*!< Offset: 0x0220 Interrupt Clear */
uint32_t RESERVED3[0x143];
__IO uint32_t CACHE_SYNC; /*!< Offset: 0x0730 Cache Sync */
uint32_t RESERVED4[0xf];
__IO uint32_t INV_LINE_PA; /*!< Offset: 0x0770 Invalidate Line By PA */
uint32_t RESERVED6[2];
__IO uint32_t INV_WAY; /*!< Offset: 0x077c Invalidate by Way */
uint32_t RESERVED5[0xc];
__IO uint32_t CLEAN_LINE_PA; /*!< Offset: 0x07b0 Clean Line by PA */
uint32_t RESERVED7[1];
__IO uint32_t CLEAN_LINE_INDEX_WAY; /*!< Offset: 0x07b8 Clean Line by Index/Way */
__IO uint32_t CLEAN_WAY; /*!< Offset: 0x07bc Clean by Way */
uint32_t RESERVED8[0xc];
__IO uint32_t CLEAN_INV_LINE_PA; /*!< Offset: 0x07f0 Clean and Invalidate Line by PA */
uint32_t RESERVED9[1];
__IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< Offset: 0x07f8 Clean and Invalidate Line by Index/Way */
__IO uint32_t CLEAN_INV_WAY; /*!< Offset: 0x07fc Clean and Invalidate by Way */
uint32_t RESERVED10[0x40];
__IO uint32_t DATA_LOCK_0_WAY; /*!< Offset: 0x0900 Data Lockdown 0 by Way */
__IO uint32_t INST_LOCK_0_WAY; /*!< Offset: 0x0904 Instruction Lockdown 0 by Way */
__IO uint32_t DATA_LOCK_1_WAY; /*!< Offset: 0x0908 Data Lockdown 1 by Way */
__IO uint32_t INST_LOCK_1_WAY; /*!< Offset: 0x090c Instruction Lockdown 1 by Way */
__IO uint32_t DATA_LOCK_2_WAY; /*!< Offset: 0x0910 Data Lockdown 2 by Way */
__IO uint32_t INST_LOCK_2_WAY; /*!< Offset: 0x0914 Instruction Lockdown 2 by Way */
__IO uint32_t DATA_LOCK_3_WAY; /*!< Offset: 0x0918 Data Lockdown 3 by Way */
__IO uint32_t INST_LOCK_3_WAY; /*!< Offset: 0x091c Instruction Lockdown 3 by Way */
__IO uint32_t DATA_LOCK_4_WAY; /*!< Offset: 0x0920 Data Lockdown 4 by Way */
__IO uint32_t INST_LOCK_4_WAY; /*!< Offset: 0x0924 Instruction Lockdown 4 by Way */
__IO uint32_t DATA_LOCK_5_WAY; /*!< Offset: 0x0928 Data Lockdown 5 by Way */
__IO uint32_t INST_LOCK_5_WAY; /*!< Offset: 0x092c Instruction Lockdown 5 by Way */
__IO uint32_t DATA_LOCK_6_WAY; /*!< Offset: 0x0930 Data Lockdown 5 by Way */
__IO uint32_t INST_LOCK_6_WAY; /*!< Offset: 0x0934 Instruction Lockdown 5 by Way */
__IO uint32_t DATA_LOCK_7_WAY; /*!< Offset: 0x0938 Data Lockdown 6 by Way */
__IO uint32_t INST_LOCK_7_WAY; /*!< Offset: 0x093c Instruction Lockdown 6 by Way */
uint32_t RESERVED11[0x4];
__IO uint32_t LOCK_LINE_EN; /*!< Offset: 0x0950 Lockdown by Line Enable */
__IO uint32_t UNLOCK_ALL_BY_WAY; /*!< Offset: 0x0954 Unlock All Lines by Way */
uint32_t RESERVED12[0xaa];
__IO uint32_t ADDRESS_FILTER_START; /*!< Offset: 0x0c00 Address Filtering Start */
__IO uint32_t ADDRESS_FILTER_END; /*!< Offset: 0x0c04 Address Filtering End */
uint32_t RESERVED13[0xce];
__IO uint32_t DEBUG_CONTROL; /*!< Offset: 0x0f40 Debug Control Register */
} PL310_TypeDef;
#define PL310 ((PL310_TypeDef *)Renesas_RZ_A1_PL310_BASE) /*!< PL310 Declaration */
extern int PL310_GetID (void);
extern int PL310_GetType (void);
extern void PL310_InvAllByWay (void);
extern void PL310_CleanInvAllByWay(void);
extern void PL310_Enable(void);
extern void PL310_Disable(void);
extern void PL310_InvPa (void *);
extern void PL310_CleanPa (void *);
extern void PL310_CleanInvPa (void *);
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2013 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : r_typedefs.h
* $Rev: 788 $
* $Date:: 2014-04-07 18:57:13 +0900#$
* Description : basic type definition
******************************************************************************/
#ifndef R_TYPEDEFS_H
#define R_TYPEDEFS_H
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#if defined(__ARM_NEON__)
#include <arm_neon.h>
#else /* __ARM_NEON__ */
typedef float float32_t;
typedef double float64_t;
#endif /* __ARM_NEON__ */
/******************************************************************************
Typedef definitions
******************************************************************************/
typedef char char_t;
typedef int bool_t;
typedef int int_t;
typedef long double float128_t;
typedef signed long long_t;
typedef unsigned long ulong_t;
#endif /* R_TYPEDEFS_H */

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/**************************************************************************//**
* @file system_Renesas_RZ_A1.c
* @brief CMSIS Device System Source File for
* ARMCA9 Device Series
* @version V1.00
* @date 19 Sept 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#include <stdint.h>
#include "MBRZA1H.h"
#include "RZ_A1_Init.h"
extern void $Super$$main(void);
__asm void FPUEnable(void);
uint32_t IRQNestLevel;
/**
* Initialize the cache.
*
* @param none
* @return none
*
* @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode.
*/
#pragma push
#pragma arm
void InitMemorySubsystem(void) {
/* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
* enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
* You are not required to invalidate the main TLB, even though it is recommended for safety
* reasons. This ensures compatibility with future revisions of the processor. */
unsigned int l2_id;
/* Invalidate undefined data */
__ca9u_inv_tlb_all();
__v7_inv_icache_all();
__v7_inv_dcache_all();
__v7_inv_btac();
/* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
* invalidate in order to flush the valid data to the next level cache.
*/
__enable_mmu();
/* After MMU is enabled and data has been invalidated, enable caches and BTAC */
__enable_caches();
__enable_btac();
/* If present, you may also need to Invalidate and Enable L2 cache here */
l2_id = PL310_GetID();
if (l2_id)
{
PL310_InvAllByWay();
PL310_Enable();
}
}
#pragma pop
IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
uint32_t IRQCount = sizeof IRQTable / 4;
uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
{
if (irq < IRQCount) {
IRQTable[irq] = handler;
return 0;
}
else {
return 1;
}
}
uint32_t InterruptHandlerUnregister (IRQn_Type irq)
{
if (irq < IRQCount) {
IRQTable[irq] = 0;
return 0;
}
else {
return 1;
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
IRQNestLevel = 0;
/* do not use global variables because this function is called before
reaching pre-main. RW section maybe overwritten afterwards. */
RZ_A1_InitClock();
RZ_A1_InitBus();
//Configure GIC ICDICFR GIC_SetICDICFR()
GIC_Enable();
__enable_irq();
}
//Fault Status Register (IFSR/DFSR) definitions
#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup
#define FSR_INSTRUCTION_CACHE_MAINTAINANCE 0x04 //DFSR only - async/external
#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external
#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external
#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external
#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external
#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal
#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal
#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal
#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal
#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal
#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal
#define FSR_PERMISION_FAULT_FIRST 0x0f //MMU Fault - internal
#define FSR_PERMISION_FAULT_SECOND 0x0d //MMU Fault - internal
#define FSR_DEBUG_EVENT 0x02 //internal
#define FSR_SYNC_EXT_ABORT 0x08 //sync/external
#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external
#define FSR_LOCKDOWN 0x14 //internal
#define FSR_COPROCESSOR_ABORT 0x1a //internal
#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external
#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external
#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external
void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status
switch(FS) {
//Synchronous parity errors - retry
case FSR_SYNC_PARITY_ERROR:
case FSR_SYNC_PARITY_TTB_WALK_FIRST:
case FSR_SYNC_PARITY_TTB_WALK_SECOND:
return;
//Your code here. Value in DFAR is invalid for some fault statuses.
case FSR_ALIGNMENT_FAULT:
case FSR_INSTRUCTION_CACHE_MAINTAINANCE:
case FSR_SYNC_EXT_TTB_WALK_FIRST:
case FSR_SYNC_EXT_TTB_WALK_SECOND:
case FSR_TRANSLATION_FAULT_FIRST:
case FSR_TRANSLATION_FAULT_SECOND:
case FSR_ACCESS_FLAG_FAULT_FIRST:
case FSR_ACCESS_FLAG_FAULT_SECOND:
case FSR_DOMAIN_FAULT_FIRST:
case FSR_DOMAIN_FAULT_SECOND:
case FSR_PERMISION_FAULT_FIRST:
case FSR_PERMISION_FAULT_SECOND:
case FSR_DEBUG_EVENT:
case FSR_SYNC_EXT_ABORT:
case FSR_TLB_CONFLICT_ABORT:
case FSR_LOCKDOWN:
case FSR_COPROCESSOR_ABORT:
case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
case FSR_ASYNC_PARITY_ERROR: //DFAR invalid
default:
while(1);
}
}
void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status
switch(FS) {
//Synchronous parity errors - retry
case FSR_SYNC_PARITY_ERROR:
case FSR_SYNC_PARITY_TTB_WALK_FIRST:
case FSR_SYNC_PARITY_TTB_WALK_SECOND:
return;
//Your code here. Value in IFAR is invalid for some fault statuses.
case FSR_SYNC_EXT_TTB_WALK_FIRST:
case FSR_SYNC_EXT_TTB_WALK_SECOND:
case FSR_TRANSLATION_FAULT_FIRST:
case FSR_TRANSLATION_FAULT_SECOND:
case FSR_ACCESS_FLAG_FAULT_FIRST:
case FSR_ACCESS_FLAG_FAULT_SECOND:
case FSR_DOMAIN_FAULT_FIRST:
case FSR_DOMAIN_FAULT_SECOND:
case FSR_PERMISION_FAULT_FIRST:
case FSR_PERMISION_FAULT_SECOND:
case FSR_DEBUG_EVENT: //IFAR invalid
case FSR_SYNC_EXT_ABORT:
case FSR_TLB_CONFLICT_ABORT:
case FSR_LOCKDOWN:
case FSR_COPROCESSOR_ABORT:
default:
while(1);
}
}
//returns amount to decrement lr by
//this will be 0 when we have emulated the instruction and simply want to execute the next instruction
//this will be 2 when we have performed some maintenance and want to retry the instruction in thumb (state == 2)
//this will be 4 when we have performed some maintenance and want to retry the instruction in arm (state == 4)
uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
const int THUMB = 2;
const int ARM = 4;
//Lazy VFP/NEON initialisation and switching
if ((state == ARM && ((opcode & 0x0C000000)) >> 26 == 0x03) ||
(state == THUMB && ((opcode & 0xEC000000)) >> 26 == 0x3B)) {
if (((opcode & 0x00000E00) >> 9) == 5) { //fp instruction?
FPUEnable();
return state;
}
}
//Add code here for other Undef cases
while(1);
}
#pragma push
#pragma arm
//Critical section, called from undef handler, so systick is disabled
__asm void FPUEnable(void) {
ARM
//Permit access to VFP registers by modifying CPACR
MRC p15,0,R1,c1,c0,2
ORR R1,R1,#0x00F00000
MCR p15,0,R1,c1,c0,2
//Enable VFP
VMRS R1,FPEXC
ORR R1,R1,#0x40000000
VMSR FPEXC,R1
//Initialise VFP registers to 0
MOV R2,#0
VMOV D0, R2,R2
VMOV D1, R2,R2
VMOV D2, R2,R2
VMOV D3, R2,R2
VMOV D4, R2,R2
VMOV D5, R2,R2
VMOV D6, R2,R2
VMOV D7, R2,R2
VMOV D8, R2,R2
VMOV D9, R2,R2
VMOV D10,R2,R2
VMOV D11,R2,R2
VMOV D12,R2,R2
VMOV D13,R2,R2
VMOV D14,R2,R2
VMOV D15,R2,R2
//Initialise FPSCR to a known state
VMRS R2,FPSCR
LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
AND R2,R2,R3
VMSR FPSCR,R2
BX LR
}
#pragma pop

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/**************************************************************************//**
* @file system_MBRZA1H.h
* @brief CMSIS Device System Header File for
* ARMCA9 Device Series
* @version V1.00
* @date 11 June 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __SYSTEM_MBRZA1H
#define __SYSTEM_MBRZA1H
#ifdef __cplusplus
extern "C" {
#endif
typedef void(*IRQHandler)();
uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
uint32_t InterruptHandlerUnregister(IRQn_Type);
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the Systd short int16_t;emCoreClock variable.
*/
extern void SystemInit (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_MBRZA1H */

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/**************************************************************************//**
* @file core_ca9.h
* @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
* @version
* @date 25 March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CA9_H_GENERIC
#define __CORE_CA9_H_GENERIC
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex_A9
@{
*/
/* CMSIS CA9 definitions */
#define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
#define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
__CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_A (0x09) /*!< Cortex-A Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#define __STATIC_ASM static __asm
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#define __STATIC_ASM static __asm
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#define __STATIC_ASM static __asm
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#define __STATIC_ASM static __asm
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#define __STATIC_ASM static __asm
#endif
/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
*/
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#if (__FPU_PRESENT == 1)
#define __FPU_USED 1
#else
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0
#endif
#else
#define __FPU_USED 0
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#if (__FPU_PRESENT == 1)
#define __FPU_USED 1
#else
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0
#endif
#else
#define __FPU_USED 0
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#if (__FPU_PRESENT == 1)
#define __FPU_USED 1
#else
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0
#endif
#else
#define __FPU_USED 0
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#if (__FPU_PRESENT == 1)
#define __FPU_USED 1
#else
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0
#endif
#else
#define __FPU_USED 0
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#if (__FPU_PRESENT == 1)
#define __FPU_USED 1
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0
#endif
#else
#define __FPU_USED 0
#endif
#endif
#include <stdint.h> /*!< standard types definitions */
#include "core_caInstr.h" /*!< Core Instruction Access */
#include "core_caFunc.h" /*!< Core Function Access */
#include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
#endif /* __CORE_CA9_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CA9_H_DEPENDANT
#define __CORE_CA9_H_DEPENDANT
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CA9_REV
#define __CA9_REV 0x0000
#warning "__CA9_REV not defined in device header file; using default!"
#endif
#ifndef __FPU_PRESENT
#define __FPU_PRESENT 1
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 1
#endif
#if __Vendor_SysTickConfig == 0
#error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex_A9 */
/*******************************************************************************
* Register Abstraction
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-A processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/*@} end of group CMSIS_CORE */
/*@} end of CMSIS_Core_FPUFunctions */
#endif /* __CORE_CA9_H_GENERIC */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file core_caFunc.h
* @brief CMSIS Cortex-A Core Function Access Header File
* @version V3.10
* @date 9 May 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CAFUNC_H__
#define __CORE_CAFUNC_H__
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
#define MODE_USR 0x10
#define MODE_FIQ 0x11
#define MODE_IRQ 0x12
#define MODE_SVC 0x13
#define MODE_MON 0x16
#define MODE_ABT 0x17
#define MODE_HYP 0x1A
#define MODE_UND 0x1B
#define MODE_SYS 0x1F
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get CPSR Register
This function returns the content of the CPSR Register.
\return CPSR Register value
*/
__STATIC_INLINE uint32_t __get_CPSR(void)
{
register uint32_t __regCPSR __ASM("cpsr");
return(__regCPSR);
}
/** \brief Set Stack Pointer
This function assigns the given value to the current stack pointer.
\param [in] topOfStack Stack Pointer value to set
*/
register uint32_t __regSP __ASM("sp");
__STATIC_INLINE void __set_SP(uint32_t topOfStack)
{
__regSP = topOfStack;
}
/** \brief Get link register
This function returns the value of the link register
\return Value of link register
*/
register uint32_t __reglr __ASM("lr");
__STATIC_INLINE uint32_t __get_LR(void)
{
return(__reglr);
}
/** \brief Set link register
This function sets the value of the link register
\param [in] lr LR value to set
*/
__STATIC_INLINE void __set_LR(uint32_t lr)
{
__reglr = lr;
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the USR/SYS Stack Pointer (PSP).
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
__STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
{
ARM
PRESERVE8
BIC R0, R0, #7 ;ensure stack is 8-byte aligned
MRS R1, CPSR
CPS #MODE_SYS ;no effect in USR mode
MOV SP, R0
MSR CPSR_c, R1 ;no effect in USR mode
ISB
BX LR
}
/** \brief Set User Mode
This function changes the processor state to User Mode
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
__STATIC_ASM void __set_CPS_USR(void)
{
ARM
CPS #MODE_USR
BX LR
}
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
/** \brief Get FPEXC
This function returns the current value of the Floating Point Exception Control register.
\return Floating Point Exception Control register value
*/
__STATIC_INLINE uint32_t __get_FPEXC(void)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpexc __ASM("fpexc");
return(__regfpexc);
#else
return(0);
#endif
}
/** \brief Set FPEXC
This function assigns the given value to the Floating Point Exception Control register.
\param [in] fpscr Floating Point Exception Control value to set
*/
__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpexc __ASM("fpexc");
__regfpexc = (fpexc);
#endif
}
/** \brief Get CPACR
This function returns the current value of the Coprocessor Access Control register.
\return Coprocessor Access Control register value
*/
__STATIC_INLINE uint32_t __get_CPACR(void)
{
register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
return __regCPACR;
}
/** \brief Set CPACR
This function assigns the given value to the Coprocessor Access Control register.
\param [in] cpacr Coporcessor Acccess Control value to set
*/
__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
{
register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
__regCPACR = cpacr;
__ISB();
}
/** \brief Get CBAR
This function returns the value of the Configuration Base Address register.
\return Configuration Base Address register value
*/
__STATIC_INLINE uint32_t __get_CBAR() {
register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
return(__regCBAR);
}
/** \brief Get TTBR0
This function returns the value of the Configuration Base Address register.
\return Translation Table Base Register 0 value
*/
__STATIC_INLINE uint32_t __get_TTBR0() {
register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
return(__regTTBR0);
}
/** \brief Set TTBR0
This function assigns the given value to the Coprocessor Access Control register.
\param [in] ttbr0 Translation Table Base Register 0 value to set
*/
__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
__regTTBR0 = ttbr0;
__ISB();
}
/** \brief Get DACR
This function returns the value of the Domain Access Control Register.
\return Domain Access Control Register value
*/
__STATIC_INLINE uint32_t __get_DACR() {
register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
return(__regDACR);
}
/** \brief Set DACR
This function assigns the given value to the Coprocessor Access Control register.
\param [in] dacr Domain Access Control Register value to set
*/
__STATIC_INLINE void __set_DACR(uint32_t dacr) {
register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
__regDACR = dacr;
__ISB();
}
/******************************** Cache and BTAC enable ****************************************************/
/** \brief Set SCTLR
This function assigns the given value to the System Control Register.
\param [in] sctlr System Control Register, value to set
*/
__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
{
register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
__regSCTLR = sctlr;
}
/** \brief Get SCTLR
This function returns the value of the System Control Register.
\return System Control Register value
*/
__STATIC_INLINE uint32_t __get_SCTLR() {
register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
return(__regSCTLR);
}
/** \brief Enable Caches
Enable Caches
*/
__STATIC_INLINE void __enable_caches(void) {
// Set I bit 12 to enable I Cache
// Set C bit 2 to enable D Cache
__set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
}
/** \brief Disable Caches
Disable Caches
*/
__STATIC_INLINE void __disable_caches(void) {
// Clear I bit 12 to disable I Cache
// Clear C bit 2 to disable D Cache
__set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
__ISB();
}
/** \brief Enable BTAC
Enable BTAC
*/
__STATIC_INLINE void __enable_btac(void) {
// Set Z bit 11 to enable branch prediction
__set_SCTLR( __get_SCTLR() | (1 << 11));
__ISB();
}
/** \brief Disable BTAC
Disable BTAC
*/
__STATIC_INLINE void __disable_btac(void) {
// Clear Z bit 11 to disable branch prediction
__set_SCTLR( __get_SCTLR() & ~(1 << 11));
}
/** \brief Enable MMU
Enable MMU
*/
__STATIC_INLINE void __enable_mmu(void) {
// Set M bit 0 to enable the MMU
// Set AFE bit to enable simplified access permissions model
// Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
__set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
__ISB();
}
/** \brief Enable MMU
Enable MMU
*/
__STATIC_INLINE void __disable_mmu(void) {
// Clear M bit 0 to disable the MMU
__set_SCTLR( __get_SCTLR() & ~1);
__ISB();
}
/******************************** TLB maintenance operations ************************************************/
/** \brief Invalidate the whole tlb
TLBIALL. Invalidate the whole tlb
*/
__STATIC_INLINE void __ca9u_inv_tlb_all(void) {
register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
__TLBIALL = 0;
__DSB();
__ISB();
}
/******************************** BTB maintenance operations ************************************************/
/** \brief Invalidate entire branch predictor array
BPIALL. Branch Predictor Invalidate All.
*/
__STATIC_INLINE void __v7_inv_btac(void) {
register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
__BPIALL = 0;
__DSB(); //ensure completion of the invalidation
__ISB(); //ensure instruction fetch path sees new state
}
/******************************** L1 cache operations ******************************************************/
/** \brief Invalidate the whole I$
ICIALLU. Instruction Cache Invalidate All to PoU
*/
__STATIC_INLINE void __v7_inv_icache_all(void) {
register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
__ICIALLU = 0;
__DSB(); //ensure completion of the invalidation
__ISB(); //ensure instruction fetch path sees new I cache state
}
/** \brief Clean D$ by MVA
DCCMVAC. Data cache clean by MVA to PoC
*/
__STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
__DCCMVAC = (uint32_t)va;
__DMB(); //ensure the ordering of data cache maintenance operations and their effects
}
/** \brief Invalidate D$ by MVA
DCIMVAC. Data cache invalidate by MVA to PoC
*/
__STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
__DCIMVAC = (uint32_t)va;
__DMB(); //ensure the ordering of data cache maintenance operations and their effects
}
/** \brief Clean and Invalidate D$ by MVA
DCCIMVAC. Data cache clean and invalidate by MVA to PoC
*/
__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
__DCCIMVAC = (uint32_t)va;
__DMB(); //ensure the ordering of data cache maintenance operations and their effects
}
/** \brief
* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
*/
#pragma push
#pragma arm
__STATIC_ASM void __v7_all_cache(uint32_t op) {
ARM
PUSH {R4-R11}
MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
ANDS R3, R6, #0x07000000 // Extract coherency level
MOV R3, R3, LSR #23 // Total cache levels << 1
BEQ Finished // If 0, no need to clean
MOV R10, #0 // R10 holds current cache level << 1
Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
AND R1, R1, #7 // Isolate those lower 3 bits
CMP R1, #2
BLT Skip // No cache or only instruction cache at this level
MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
ISB // ISB to sync the change to the CacheSizeID reg
MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
AND R2, R1, #7 // Extract the line length field
ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
LDR R4, =0x3FF
ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
CLZ R5, R4 // R5 is the bit position of the way size increment
LDR R7, =0x7FFF
ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
ORR R11, R11, R7, LSL R2 // Factor in the Set number
CMP R0, #0
BNE Dccsw
MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
B cont
Dccsw CMP R0, #1
BNE Dccisw
MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
B cont
Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
cont SUBS R9, R9, #1 // Decrement the Way number
BGE Loop3
SUBS R7, R7, #1 // Decrement the Set number
BGE Loop2
Skip ADD R10, R10, #2 // increment the cache number
CMP R3, R10
BGT Loop1
Finished
DSB
POP {R4-R11}
BX lr
}
#pragma pop
/** \brief __v7_all_cache - helper function
*/
/** \brief Invalidate the whole D$
DCISW. Invalidate by Set/Way
*/
__STATIC_INLINE void __v7_inv_dcache_all(void) {
__v7_all_cache(0);
}
/** \brief Clean the whole D$
DCCSW. Clean by Set/Way
*/
__STATIC_INLINE void __v7_clean_dcache_all(void) {
__v7_all_cache(1);
}
/** \brief Clean and invalidate the whole D$
DCCISW. Clean and Invalidate by Set/Way
*/
__STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
__v7_all_cache(2);
}
#include "core_ca_mmu.h"
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
#error IAR Compiler support not implemented for Cortex-A
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
//#error GNU Compiler support not implemented for Cortex-A
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
#error TASKING Compiler support not implemented for Cortex-A
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CAFUNC_H__ */

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/**************************************************************************//**
* @file core_caInstr.h
* @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
* @version
* @date 04. December 2012
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CAINSTR_H__
#define __CORE_CAINSTR_H__
#define __CORTEX_M 0x3
#include "core_cmInstr.h"
#undef __CORTEX_M
#endif

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;/**************************************************************************//**
; * @file core_ca_mmu.h
; * @brief MMU Startup File for
; * VE_A9_MP Device Series
; * @version V1.01
; * @date 25 March 2013
; *
; * @note
; *
; ******************************************************************************/
;/* Copyright (c) 2012 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _MMU_FUNC_H
#define _MMU_FUNC_H
#define SECTION_DESCRIPTOR (0x2)
#define SECTION_MASK (0xFFFFFFFC)
#define SECTION_TEXCB_MASK (0xFFFF8FF3)
#define SECTION_B_SHIFT (2)
#define SECTION_C_SHIFT (3)
#define SECTION_TEX0_SHIFT (12)
#define SECTION_TEX1_SHIFT (13)
#define SECTION_TEX2_SHIFT (14)
#define SECTION_XN_MASK (0xFFFFFFEF)
#define SECTION_XN_SHIFT (4)
#define SECTION_DOMAIN_MASK (0xFFFFFE1F)
#define SECTION_DOMAIN_SHIFT (5)
#define SECTION_P_MASK (0xFFFFFDFF)
#define SECTION_P_SHIFT (9)
#define SECTION_AP_MASK (0xFFFF73FF)
#define SECTION_AP_SHIFT (10)
#define SECTION_AP2_SHIFT (15)
#define SECTION_S_MASK (0xFFFEFFFF)
#define SECTION_S_SHIFT (16)
#define SECTION_NG_MASK (0xFFFDFFFF)
#define SECTION_NG_SHIFT (17)
#define SECTION_NS_MASK (0xFFF7FFFF)
#define SECTION_NS_SHIFT (19)
#define PAGE_L1_DESCRIPTOR (0x1)
#define PAGE_L1_MASK (0xFFFFFFFC)
#define PAGE_L2_4K_DESC (0x2)
#define PAGE_L2_4K_MASK (0xFFFFFFFD)
#define PAGE_L2_64K_DESC (0x1)
#define PAGE_L2_64K_MASK (0xFFFFFFFC)
#define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
#define PAGE_4K_B_SHIFT (2)
#define PAGE_4K_C_SHIFT (3)
#define PAGE_4K_TEX0_SHIFT (6)
#define PAGE_4K_TEX1_SHIFT (7)
#define PAGE_4K_TEX2_SHIFT (8)
#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
#define PAGE_64K_B_SHIFT (2)
#define PAGE_64K_C_SHIFT (3)
#define PAGE_64K_TEX0_SHIFT (12)
#define PAGE_64K_TEX1_SHIFT (13)
#define PAGE_64K_TEX2_SHIFT (14)
#define PAGE_TEXCB_MASK (0xFFFF8FF3)
#define PAGE_B_SHIFT (2)
#define PAGE_C_SHIFT (3)
#define PAGE_TEX_SHIFT (12)
#define PAGE_XN_4K_MASK (0xFFFFFFFE)
#define PAGE_XN_4K_SHIFT (0)
#define PAGE_XN_64K_MASK (0xFFFF7FFF)
#define PAGE_XN_64K_SHIFT (15)
#define PAGE_DOMAIN_MASK (0xFFFFFE1F)
#define PAGE_DOMAIN_SHIFT (5)
#define PAGE_P_MASK (0xFFFFFDFF)
#define PAGE_P_SHIFT (9)
#define PAGE_AP_MASK (0xFFFFFDCF)
#define PAGE_AP_SHIFT (4)
#define PAGE_AP2_SHIFT (9)
#define PAGE_S_MASK (0xFFFFFBFF)
#define PAGE_S_SHIFT (10)
#define PAGE_NG_MASK (0xFFFFF7FF)
#define PAGE_NG_SHIFT (11)
#define PAGE_NS_MASK (0xFFFFFFF7)
#define PAGE_NS_SHIFT (3)
#define OFFSET_1M (0x00100000)
#define OFFSET_64K (0x00010000)
#define OFFSET_4K (0x00001000)
#define DESCRIPTOR_FAULT (0x00000000)
/* ########################### MMU Function Access ########################### */
/** \ingroup MMU_FunctionInterface
\defgroup MMU_Functions MMU Functions Interface
@{
*/
/* Attributes enumerations */
/* Region size attributes */
typedef enum
{
SECTION,
PAGE_4k,
PAGE_64k,
} mmu_region_size_Type;
/* Region type attributes */
typedef enum
{
NORMAL,
DEVICE,
SHARED_DEVICE,
NON_SHARED_DEVICE,
STRONGLY_ORDERED
} mmu_memory_Type;
/* Region cacheability attributes */
typedef enum
{
NON_CACHEABLE,
WB_WA,
WT,
WB_NO_WA,
} mmu_cacheability_Type;
/* Region parity check attributes */
typedef enum
{
ECC_DISABLED,
ECC_ENABLED,
} mmu_ecc_check_Type;
/* Region execution attributes */
typedef enum
{
EXECUTE,
NON_EXECUTE,
} mmu_execute_Type;
/* Region global attributes */
typedef enum
{
GLOBAL,
NON_GLOBAL,
} mmu_global_Type;
/* Region shareability attributes */
typedef enum
{
NON_SHARED,
SHARED,
} mmu_shared_Type;
/* Region security attributes */
typedef enum
{
SECURE,
NON_SECURE,
} mmu_secure_Type;
/* Region access attributes */
typedef enum
{
NO_ACCESS,
RW,
READ,
} mmu_access_Type;
/* Memory Region definition */
typedef struct RegionStruct {
mmu_region_size_Type rg_t;
mmu_memory_Type mem_t;
uint8_t domain;
mmu_cacheability_Type inner_norm_t;
mmu_cacheability_Type outer_norm_t;
mmu_ecc_check_Type e_t;
mmu_execute_Type xn_t;
mmu_global_Type g_t;
mmu_secure_Type sec_t;
mmu_access_Type priv_t;
mmu_access_Type user_t;
mmu_shared_Type sh_t;
} mmu_region_attributes_Type;
/** \brief Set section execution-never attribute
The function sets section execution-never attribute
\param [out] descriptor_l1 L1 descriptor.
\param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
\return 0
*/
__STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
{
*descriptor_l1 &= SECTION_XN_MASK;
*descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
return 0;
}
/** \brief Set section domain
The function sets section domain
\param [out] descriptor_l1 L1 descriptor.
\param [in] domain Section domain
\return 0
*/
__STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
{
*descriptor_l1 &= SECTION_DOMAIN_MASK;
*descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
return 0;
}
/** \brief Set section parity check
The function sets section parity check
\param [out] descriptor_l1 L1 descriptor.
\param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
\return 0
*/
__STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
{
*descriptor_l1 &= SECTION_P_MASK;
*descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
return 0;
}
/** \brief Set section access privileges
The function sets section access privileges
\param [out] descriptor_l1 L1 descriptor.
\param [in] user User Level Access: NO_ACCESS, RW, READ
\param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
\param [in] afe Access flag enable
\return 0
*/
__STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
{
uint32_t ap = 0;
if (afe == 0) { //full access
if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
else if ((priv == RW) && (user == READ)) { ap = 0x2; }
else if ((priv == RW) && (user == RW)) { ap = 0x3; }
else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
else if ((priv == READ) && (user == READ)) { ap = 0x6; }
}
else { //Simplified access
if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
else if ((priv == RW) && (user == RW)) { ap = 0x3; }
else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
else if ((priv == READ) && (user == READ)) { ap = 0x7; }
}
*descriptor_l1 &= SECTION_AP_MASK;
*descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
*descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
return 0;
}
/** \brief Set section shareability
The function sets section shareability
\param [out] descriptor_l1 L1 descriptor.
\param [in] s_bit Section shareability: NON_SHARED, SHARED
\return 0
*/
__STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
{
*descriptor_l1 &= SECTION_S_MASK;
*descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
return 0;
}
/** \brief Set section Global attribute
The function sets section Global attribute
\param [out] descriptor_l1 L1 descriptor.
\param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
\return 0
*/
__STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
{
*descriptor_l1 &= SECTION_NG_MASK;
*descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
return 0;
}
/** \brief Set section Security attribute
The function sets section Global attribute
\param [out] descriptor_l1 L1 descriptor.
\param [in] s_bit Section Security attribute: SECURE, NON_SECURE
\return 0
*/
__STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
{
*descriptor_l1 &= SECTION_NS_MASK;
*descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
return 0;
}
/* Page 4k or 64k */
/** \brief Set 4k/64k page execution-never attribute
The function sets 4k/64k page execution-never attribute
\param [out] descriptor_l2 L2 descriptor.
\param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
\param [in] page Page size: PAGE_4k, PAGE_64k,
\return 0
*/
__STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
{
if (page == PAGE_4k)
{
*descriptor_l2 &= PAGE_XN_4K_MASK;
*descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
}
else
{
*descriptor_l2 &= PAGE_XN_64K_MASK;
*descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
}
return 0;
}
/** \brief Set 4k/64k page domain
The function sets 4k/64k page domain
\param [out] descriptor_l1 L1 descriptor.
\param [in] domain Page domain
\return 0
*/
__STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
{
*descriptor_l1 &= PAGE_DOMAIN_MASK;
*descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
return 0;
}
/** \brief Set 4k/64k page parity check
The function sets 4k/64k page parity check
\param [out] descriptor_l1 L1 descriptor.
\param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
\return 0
*/
__STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
{
*descriptor_l1 &= SECTION_P_MASK;
*descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
return 0;
}
/** \brief Set 4k/64k page access privileges
The function sets 4k/64k page access privileges
\param [out] descriptor_l2 L2 descriptor.
\param [in] user User Level Access: NO_ACCESS, RW, READ
\param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
\param [in] afe Access flag enable
\return 0
*/
__STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
{
uint32_t ap = 0;
if (afe == 0) { //full access
if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
else if ((priv == RW) && (user == READ)) { ap = 0x2; }
else if ((priv == RW) && (user == RW)) { ap = 0x3; }
else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
else if ((priv == READ) && (user == READ)) { ap = 0x6; }
}
else { //Simplified access
if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
else if ((priv == RW) && (user == RW)) { ap = 0x3; }
else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
else if ((priv == READ) && (user == READ)) { ap = 0x7; }
}
*descriptor_l2 &= PAGE_AP_MASK;
*descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
*descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
return 0;
}
/** \brief Set 4k/64k page shareability
The function sets 4k/64k page shareability
\param [out] descriptor_l2 L2 descriptor.
\param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
\return 0
*/
__STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
{
*descriptor_l2 &= PAGE_S_MASK;
*descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
return 0;
}
/** \brief Set 4k/64k page Global attribute
The function sets 4k/64k page Global attribute
\param [out] descriptor_l2 L2 descriptor.
\param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
\return 0
*/
__STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
{
*descriptor_l2 &= PAGE_NG_MASK;
*descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
return 0;
}
/** \brief Set 4k/64k page Security attribute
The function sets 4k/64k page Global attribute
\param [out] descriptor_l1 L1 descriptor.
\param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
\return 0
*/
__STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
{
*descriptor_l1 &= PAGE_NS_MASK;
*descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
return 0;
}
/** \brief Set Section memory attributes
The function sets section memory attributes
\param [out] descriptor_l1 L1 descriptor.
\param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
\param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
\param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
\return 0
*/
__STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
{
*descriptor_l1 &= SECTION_TEXCB_MASK;
if (STRONGLY_ORDERED == mem)
{
return 0;
}
else if (SHARED_DEVICE == mem)
{
*descriptor_l1 |= (1 << SECTION_B_SHIFT);
}
else if (NON_SHARED_DEVICE == mem)
{
*descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
}
else if (NORMAL == mem)
{
*descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
switch(inner)
{
case NON_CACHEABLE:
break;
case WB_WA:
*descriptor_l1 |= (1 << SECTION_B_SHIFT);
break;
case WT:
*descriptor_l1 |= 1 << SECTION_C_SHIFT;
break;
case WB_NO_WA:
*descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
break;
}
switch(outer)
{
case NON_CACHEABLE:
break;
case WB_WA:
*descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
break;
case WT:
*descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
break;
case WB_NO_WA:
*descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
break;
}
}
return 0;
}
/** \brief Set 4k/64k page memory attributes
The function sets 4k/64k page memory attributes
\param [out] descriptor_l2 L2 descriptor.
\param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
\param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
\param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
\return 0
*/
__STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
{
*descriptor_l2 &= PAGE_4K_TEXCB_MASK;
if (page == PAGE_64k)
{
//same as section
__memory_section(descriptor_l2, mem, outer, inner);
}
else
{
if (STRONGLY_ORDERED == mem)
{
return 0;
}
else if (SHARED_DEVICE == mem)
{
*descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
}
else if (NON_SHARED_DEVICE == mem)
{
*descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
}
else if (NORMAL == mem)
{
*descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
switch(inner)
{
case NON_CACHEABLE:
break;
case WB_WA:
*descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
break;
case WT:
*descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
break;
case WB_NO_WA:
*descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
break;
}
switch(outer)
{
case NON_CACHEABLE:
break;
case WB_WA:
*descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
break;
case WT:
*descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
break;
case WB_NO_WA:
*descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
break;
}
}
}
return 0;
}
/** \brief Create a L1 section descriptor
The function creates a section descriptor.
Assumptions:
- 16MB super sections not suported
- TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
- Functions always return 0
\param [out] descriptor L1 descriptor
\param [out] descriptor2 L2 descriptor
\param [in] reg Section attributes
\return 0
*/
__STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
{
*descriptor = 0;
__memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
__xn_section(descriptor,reg.xn_t);
__domain_section(descriptor, reg.domain);
__p_section(descriptor, reg.e_t);
__ap_section(descriptor, reg.priv_t, reg.user_t, 1);
__shared_section(descriptor,reg.sh_t);
__global_section(descriptor,reg.g_t);
__secure_section(descriptor,reg.sec_t);
*descriptor &= SECTION_MASK;
*descriptor |= SECTION_DESCRIPTOR;
return 0;
}
/** \brief Create a L1 and L2 4k/64k page descriptor
The function creates a 4k/64k page descriptor.
Assumptions:
- TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
- Functions always return 0
\param [out] descriptor L1 descriptor
\param [out] descriptor2 L2 descriptor
\param [in] reg 4k/64k page attributes
\return 0
*/
__STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
{
*descriptor = 0;
*descriptor2 = 0;
switch (reg.rg_t)
{
case PAGE_4k:
__memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
__xn_page(descriptor2, reg.xn_t, PAGE_4k);
__domain_page(descriptor, reg.domain);
__p_page(descriptor, reg.e_t);
__ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
__shared_page(descriptor2,reg.sh_t);
__global_page(descriptor2,reg.g_t);
__secure_page(descriptor,reg.sec_t);
*descriptor &= PAGE_L1_MASK;
*descriptor |= PAGE_L1_DESCRIPTOR;
*descriptor2 &= PAGE_L2_4K_MASK;
*descriptor2 |= PAGE_L2_4K_DESC;
break;
case PAGE_64k:
__memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
__xn_page(descriptor2, reg.xn_t, PAGE_64k);
__domain_page(descriptor, reg.domain);
__p_page(descriptor, reg.e_t);
__ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
__shared_page(descriptor2,reg.sh_t);
__global_page(descriptor2,reg.g_t);
__secure_page(descriptor,reg.sec_t);
*descriptor &= PAGE_L1_MASK;
*descriptor |= PAGE_L1_DESCRIPTOR;
*descriptor2 &= PAGE_L2_64K_MASK;
*descriptor2 |= PAGE_L2_64K_DESC;
break;
case SECTION:
//error
break;
}
return 0;
}
/** \brief Create a 1MB Section
\param [in] ttb Translation table base address
\param [in] base_address Section base address
\param [in] count Number of sections to create
\param [in] descriptor_l1 L1 descriptor (region attributes)
*/
__STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
{
uint32_t offset;
uint32_t entry;
uint32_t i;
offset = base_address >> 20;
entry = (base_address & 0xFFF00000) | descriptor_l1;
//4 bytes aligned
ttb = ttb + offset;
for (i = 0; i < count; i++ )
{
//4 bytes aligned
*ttb++ = entry;
entry += OFFSET_1M;
}
}
/** \brief Create a 4k page entry
\param [in] ttb L1 table base address
\param [in] base_address 4k base address
\param [in] count Number of 4k pages to create
\param [in] descriptor_l1 L1 descriptor (region attributes)
\param [in] ttb_l2 L2 table base address
\param [in] descriptor_l2 L2 descriptor (region attributes)
*/
__STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
{
uint32_t offset, offset2;
uint32_t entry, entry2;
uint32_t i;
offset = base_address >> 20;
entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
//4 bytes aligned
ttb += offset;
//create l1_entry
*ttb = entry;
offset2 = (base_address & 0xff000) >> 12;
ttb_l2 += offset2;
entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
for (i = 0; i < count; i++ )
{
//4 bytes aligned
*ttb_l2++ = entry2;
entry2 += OFFSET_4K;
}
}
/** \brief Create a 64k page entry
\param [in] ttb L1 table base address
\param [in] base_address 64k base address
\param [in] count Number of 64k pages to create
\param [in] descriptor_l1 L1 descriptor (region attributes)
\param [in] ttb_l2 L2 table base address
\param [in] descriptor_l2 L2 descriptor (region attributes)
*/
__STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
{
uint32_t offset, offset2;
uint32_t entry, entry2;
uint32_t i,j;
offset = base_address >> 20;
entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
//4 bytes aligned
ttb += offset;
//create l1_entry
*ttb = entry;
offset2 = (base_address & 0xff000) >> 12;
ttb_l2 += offset2;
entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
for (i = 0; i < count; i++ )
{
//create 16 entries
for (j = 0; j < 16; j++)
//4 bytes aligned
*ttb_l2++ = entry2;
entry2 += OFFSET_64K;
}
}
/*@} end of MMU_Functions */
#endif
#ifdef __cplusplus
}
#endif