mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #170 from sg-/kl05_uarm
Added uARM support for KL05Z and added target to build_release.py. Also ...pull/173/head
Emilio Monti
commit
18bc485181
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@ -0,0 +1,12 @@
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LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
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ER_IROM1 0x00000000 0x8000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
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; 0x1000 - 0xC0 = 0xF40
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RW_IRAM1 0x1FFFFCC0 0xF40 {
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.ANY (+RW +ZI)
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}
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}
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@ -0,0 +1,348 @@
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;/*****************************************************************************
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; * @file: startup_MKL25Z4.s
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; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
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; * MKL05Z4
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; * @version: 1.1
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; * @date: 2012-6-21
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; *
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; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
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;*
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; *****************************************************************************/
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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EXPORT __initial_sp
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Stack_Mem SPACE Stack_Size
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__initial_sp EQU 0x20000C00 ; Top of RAM
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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EXPORT __heap_base
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EXPORT __heap_limit
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
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DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
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DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
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DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
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DCD Reserved20_IRQHandler ; Reserved interrupt 20
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DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
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DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
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DCD LLW_IRQHandler ; Low Leakage Wakeup
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DCD I2C0_IRQHandler ; I2C0 interrupt
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DCD Reserved_25_IRQHandler ; Reserved interrupt 25
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DCD SPI0_IRQHandler ; SPI0 interrupt
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DCD Reserved_27_IRQHandler ; Reserved interrupt 27
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DCD UART0_IRQHandler ; UART0 status and error interrupt
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DCD Reserved_29_IRQHandler ; Reserved interrupt 29
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DCD Reserved_30_IRQHandler ; Reserved interrupt 30
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DCD ADC0_IRQHandler ; ADC0 interrupt
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DCD CMP0_IRQHandler ; CMP0 interrupt
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DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
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DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
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DCD Reserved_35_IRQHandler ; Reserved interrupt 35
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DCD RTC_IRQHandler ; RTC interrupt
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DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
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DCD PIT_IRQHandler ; PIT timer channel 0 interrupt
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DCD Reserved_39_IRQHandler ; Reserved interrupt 39
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DCD Reserved_40_IRQHandler ; Reserved interrupt 40
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DCD DAC0_IRQHandler ; DAC0 interrupt
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DCD TSI0_IRQHandler ; TSI0 interrupt
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DCD MCG_IRQHandler ; MCG interrupt
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DCD LPTimer_IRQHandler ; LPTimer interrupt
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DCD Reserved_45_IRQHandler ; Reserved interrupt 45
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DCD PORTA_IRQHandler ; Port A interrupt
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DCD PORTB_IRQHandler ; Port B interrupt
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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; <h> Flash Configuration
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; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
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; <i> and security information that allows the MCU to restrict acces to the FTFL module.
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; <h> Backdoor Comparison Key
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; <o0> Backdoor Key 0 <0x0-0xFF:2>
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; <o1> Backdoor Key 1 <0x0-0xFF:2>
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; <o2> Backdoor Key 2 <0x0-0xFF:2>
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; <o3> Backdoor Key 3 <0x0-0xFF:2>
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; <o4> Backdoor Key 4 <0x0-0xFF:2>
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; <o5> Backdoor Key 5 <0x0-0xFF:2>
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; <o6> Backdoor Key 6 <0x0-0xFF:2>
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; <o7> Backdoor Key 7 <0x0-0xFF:2>
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BackDoorK0 EQU 0xFF
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BackDoorK1 EQU 0xFF
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BackDoorK2 EQU 0xFF
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BackDoorK3 EQU 0xFF
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BackDoorK4 EQU 0xFF
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BackDoorK5 EQU 0xFF
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BackDoorK6 EQU 0xFF
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BackDoorK7 EQU 0xFF
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; </h>
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; <h> Program flash protection bytes (FPROT)
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; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
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; <i> Each bit protects a 1/32 region of the program flash memory.
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; <h> FPROT0
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; <i> Program flash protection bytes
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; <i> 1/32 - 8/32 region
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; <o.0> FPROT0.0
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; <o.1> FPROT0.1
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; <o.2> FPROT0.2
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; <o.3> FPROT0.3
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; <o.4> FPROT0.4
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; <o.5> FPROT0.5
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; <o.6> FPROT0.6
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; <o.7> FPROT0.7
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nFPROT0 EQU 0x00
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FPROT0 EQU nFPROT0:EOR:0xFF
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; </h>
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; <h> FPROT1
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; <i> Program Flash Region Protect Register 1
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; <i> 9/32 - 16/32 region
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; <o.0> FPROT1.0
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; <o.1> FPROT1.1
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; <o.2> FPROT1.2
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; <o.3> FPROT1.3
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; <o.4> FPROT1.4
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; <o.5> FPROT1.5
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; <o.6> FPROT1.6
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; <o.7> FPROT1.7
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nFPROT1 EQU 0x00
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FPROT1 EQU nFPROT1:EOR:0xFF
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; </h>
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; <h> FPROT2
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; <i> Program Flash Region Protect Register 2
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; <i> 17/32 - 24/32 region
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; <o.0> FPROT2.0
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; <o.1> FPROT2.1
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; <o.2> FPROT2.2
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; <o.3> FPROT2.3
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; <o.4> FPROT2.4
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; <o.5> FPROT2.5
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; <o.6> FPROT2.6
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; <o.7> FPROT2.7
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nFPROT2 EQU 0x00
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FPROT2 EQU nFPROT2:EOR:0xFF
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; </h>
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; <h> FPROT3
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; <i> Program Flash Region Protect Register 3
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; <i> 25/32 - 32/32 region
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; <o.0> FPROT3.0
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; <o.1> FPROT3.1
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; <o.2> FPROT3.2
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; <o.3> FPROT3.3
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; <o.4> FPROT3.4
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; <o.5> FPROT3.5
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; <o.6> FPROT3.6
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; <o.7> FPROT3.7
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nFPROT3 EQU 0x00
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FPROT3 EQU nFPROT3:EOR:0xFF
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; </h>
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; </h>
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; </h>
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; <h> Flash nonvolatile option byte (FOPT)
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; <i> Allows the user to customize the operation of the MCU at boot time.
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; <o.0> LPBOOT0
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; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
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; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
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; <o.4> LPBOOT1
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; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
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; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
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; <o.2> NMI_DIS
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; <0=> NMI interrupts are always blocked
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; <1=> NMI pin/interrupts reset default to enabled
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||||||
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; <o.3> RESET_PIN_CFG
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||||||
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; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
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||||||
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; <1=> RESET pin is dedicated
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||||||
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; <o.3> FAST_INIT
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; <0=> Slower initialization
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; <1=> Fast Initialization
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FOPT EQU 0xFF
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||||||
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; </h>
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||||||
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; <h> Flash security byte (FSEC)
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||||||
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; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
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||||||
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; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
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||||||
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; <o.0..1> SEC
|
||||||
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; <2=> MCU security status is unsecure
|
||||||
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; <3=> MCU security status is secure
|
||||||
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; <i> Flash Security
|
||||||
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; <i> This bits define the security state of the MCU.
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||||||
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; <o.2..3> FSLACC
|
||||||
|
; <2=> Freescale factory access denied
|
||||||
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; <3=> Freescale factory access granted
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||||||
|
; <i> Freescale Failure Analysis Access Code
|
||||||
|
; <i> This bits define the security state of the MCU.
|
||||||
|
; <o.4..5> MEEN
|
||||||
|
; <2=> Mass erase is disabled
|
||||||
|
; <3=> Mass erase is enabled
|
||||||
|
; <i> Mass Erase Enable Bits
|
||||||
|
; <i> Enables and disables mass erase capability of the FTFL module
|
||||||
|
; <o.6..7> KEYEN
|
||||||
|
; <2=> Backdoor key access enabled
|
||||||
|
; <3=> Backdoor key access disabled
|
||||||
|
; <i> Backdoor key Security Enable
|
||||||
|
; <i> These bits enable and disable backdoor key access to the FTFL module.
|
||||||
|
FSEC EQU 0xFE
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
IF :LNOT::DEF:RAM_TARGET
|
||||||
|
AREA |.ARM.__at_0x400|, CODE, READONLY
|
||||||
|
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
||||||
|
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
||||||
|
DCB FPROT0, FPROT1, FPROT2, FPROT3
|
||||||
|
DCB FSEC, FOPT, 0xFF, 0xFF
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
|
||||||
|
; Reset Handler
|
||||||
|
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
EXPORT DMA0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA3_IRQHandler [WEAK]
|
||||||
|
EXPORT Reserved20_IRQHandler [WEAK]
|
||||||
|
EXPORT FTFA_IRQHandler [WEAK]
|
||||||
|
EXPORT LVD_LVW_IRQHandler [WEAK]
|
||||||
|
EXPORT LLW_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C0_IRQHandler [WEAK]
|
||||||
|
EXPORT Reserved_25_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI0_IRQHandler [WEAK]
|
||||||
|
EXPORT Reserved_27_IRQHandler [WEAK]
|
||||||
|
EXPORT UART0_IRQHandler [WEAK]
|
||||||
|
EXPORT Reserved_29_IRQHandler [WEAK]
|
||||||
|
EXPORT Reserved_30_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC0_IRQHandler [WEAK]
|
||||||
|
EXPORT CMP0_IRQHandler [WEAK]
|
||||||
|
EXPORT TPM0_IRQHandler [WEAK]
|
||||||
|
EXPORT TPM1_IRQHandler [WEAK]
|
||||||
|
EXPORT Reserved_35_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Seconds_IRQHandler [WEAK]
|
||||||
|
EXPORT PIT_IRQHandler [WEAK]
|
||||||
|
EXPORT Reserved_39_IRQHandler [WEAK]
|
||||||
|
EXPORT Reserved_40_IRQHandler [WEAK]
|
||||||
|
EXPORT DAC0_IRQHandler [WEAK]
|
||||||
|
EXPORT TSI0_IRQHandler [WEAK]
|
||||||
|
EXPORT MCG_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTimer_IRQHandler [WEAK]
|
||||||
|
EXPORT Reserved_45_IRQHandler [WEAK]
|
||||||
|
EXPORT PORTA_IRQHandler [WEAK]
|
||||||
|
EXPORT PORTB_IRQHandler [WEAK]
|
||||||
|
EXPORT DefaultISR [WEAK]
|
||||||
|
|
||||||
|
DMA0_IRQHandler
|
||||||
|
DMA1_IRQHandler
|
||||||
|
DMA2_IRQHandler
|
||||||
|
DMA3_IRQHandler
|
||||||
|
Reserved20_IRQHandler
|
||||||
|
FTFA_IRQHandler
|
||||||
|
LVD_LVW_IRQHandler
|
||||||
|
LLW_IRQHandler
|
||||||
|
I2C0_IRQHandler
|
||||||
|
Reserved_25_IRQHandler
|
||||||
|
SPI0_IRQHandler
|
||||||
|
Reserved_27_IRQHandler
|
||||||
|
UART0_IRQHandler
|
||||||
|
Reserved_29_IRQHandler
|
||||||
|
Reserved_30_IRQHandler
|
||||||
|
ADC0_IRQHandler
|
||||||
|
CMP0_IRQHandler
|
||||||
|
TPM0_IRQHandler
|
||||||
|
TPM1_IRQHandler
|
||||||
|
Reserved_35_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
RTC_Seconds_IRQHandler
|
||||||
|
PIT_IRQHandler
|
||||||
|
Reserved_39_IRQHandler
|
||||||
|
Reserved_40_IRQHandler
|
||||||
|
DAC0_IRQHandler
|
||||||
|
TSI0_IRQHandler
|
||||||
|
MCG_IRQHandler
|
||||||
|
LPTimer_IRQHandler
|
||||||
|
Reserved_45_IRQHandler
|
||||||
|
PORTA_IRQHandler
|
||||||
|
PORTB_IRQHandler
|
||||||
|
DefaultISR
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/* mbed Microcontroller Library - stackheap
|
||||||
|
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* Setup a fixed single stack/heap memory model,
|
||||||
|
* between the top of the RW/ZI region and the stackpointer
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rt_misc.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||||
|
|
||||||
|
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||||
|
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||||
|
uint32_t sp_limit = __current_sp();
|
||||||
|
|
||||||
|
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||||
|
|
||||||
|
struct __initial_stackheap r;
|
||||||
|
r.heap_base = zi_limit;
|
||||||
|
r.heap_limit = sp_limit;
|
||||||
|
return r;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -36,6 +36,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = (
|
||||||
('LPC1114', ('uARM',)),
|
('LPC1114', ('uARM',)),
|
||||||
('LPC11U35_401', ('ARM', 'uARM')),
|
('LPC11U35_401', ('ARM', 'uARM')),
|
||||||
|
|
||||||
|
('KL05Z', ('ARM', 'uARM', 'GCC_ARM')),
|
||||||
('KL25Z', ('ARM', 'GCC_ARM')),
|
('KL25Z', ('ARM', 'GCC_ARM')),
|
||||||
('KL46Z', ('ARM', 'GCC_ARM')),
|
('KL46Z', ('ARM', 'GCC_ARM')),
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -21,7 +21,7 @@ from os.path import basename
|
||||||
class Uvision4(Exporter):
|
class Uvision4(Exporter):
|
||||||
NAME = 'uVision4'
|
NAME = 'uVision4'
|
||||||
|
|
||||||
TARGETS = ['LPC1768', 'LPC11U24', 'KL05Z', 'KL25Z', 'KL46Z', 'K20D5M', 'LPC1347', 'LPC1114', 'LPC11C24', 'LPC4088', 'LPC812', 'NUCLEO_F103RB', 'NUCLEO_L152RE', 'NUCLEO_F030R8', 'NUCLEO_F401RE', 'C027']
|
TARGETS = ['LPC1768', 'LPC11U24', 'KL05Z', 'KL25Z', 'KL46Z', 'K20D5M', 'LPC1347', 'LPC1114', 'LPC11C24', 'LPC4088', 'LPC812', 'NUCLEO_F103RB', 'NUCLEO_L152RE', 'NUCLEO_F030R8', 'NUCLEO_F401RE', 'UBLOX_C027']
|
||||||
|
|
||||||
USING_MICROLIB = ['LPC11U24', 'LPC1114', 'LPC11C24', 'LPC812', 'NUCLEO_F103RB', 'NUCLEO_L152RE', 'NUCLEO_F030R8', 'NUCLEO_F401RE']
|
USING_MICROLIB = ['LPC11U24', 'LPC1114', 'LPC11C24', 'LPC812', 'NUCLEO_F103RB', 'NUCLEO_L152RE', 'NUCLEO_F030R8', 'NUCLEO_F401RE']
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -108,7 +108,7 @@ class KL05Z(Target):
|
||||||
|
|
||||||
self.extra_labels = ['Freescale', 'KLXX']
|
self.extra_labels = ['Freescale', 'KLXX']
|
||||||
|
|
||||||
self.supported_toolchains = ["ARM", "GCC_ARM"]
|
self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"]
|
||||||
|
|
||||||
self.is_disk_virtual = True
|
self.is_disk_virtual = True
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue