mirror of https://github.com/ARMmbed/mbed-os.git
Support Flash iAP for GR-PEACH and GR-LYCHEE
The mainly changes is below: - Add flash_api.c - Add the definition of SPI multi I/O Bus controller that is used for flash access - Add "FLASH" as device feature - Add the macro regarding information of the incorporated Flash - Add the processing to expand code to RAMpull/6925/head
TomoYamanaka
parent
e8ec3614b0
commit
18a8eac72b
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@ -32,7 +32,10 @@ SFLASH __ROM_BASE __ROM_SIZE ; load region size_region
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RO_DATA +0
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RO_DATA +0
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{ * (+RO-DATA) } ; Application RO data (.constdata)
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{ * (+RO-DATA) } ; Application RO data (.constdata)
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RW_DATA 0x20020000
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RAM_CODE 0x20020000
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{ * (RAM_CODE) } ; Application RAM_CODE
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RW_DATA +0 ALIGN 0x4
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{ * (+RW) } ; Application RW data (.data)
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{ * (+RW) } ; Application RW data (.data)
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RW_IRAM1 +0 ALIGN 0x10
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RW_IRAM1 +0 ALIGN 0x10
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@ -105,6 +105,9 @@ SECTIONS
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LONG (__etext2)
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LONG (__etext2)
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LONG (__nc_data_start)
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LONG (__nc_data_start)
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LONG (__nc_data_end - __nc_data_start)
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LONG (__nc_data_end - __nc_data_start)
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LONG (LOADADDR(.ram_code))
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LONG (ADDR(.ram_code))
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LONG (SIZEOF(.ram_code))
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__copy_table_end__ = .;
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__copy_table_end__ = .;
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} > SFLASH
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} > SFLASH
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@ -119,8 +122,22 @@ SECTIONS
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__zero_table_end__ = .;
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__zero_table_end__ = .;
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} > SFLASH
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} > SFLASH
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__etext = .;
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.ram_code : ALIGN( 0x4 ) {
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__ram_code_load = .;
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__ram_code_start = LOADADDR(.ram_code) + ( __ram_code_load - ADDR(.ram_code) );
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*(RAM_CODE)
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*(RAM_CONST)
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. = ALIGN( 0x4 );
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__ram_code_end = LOADADDR(.ram_code) + ( . - ADDR(.ram_code) );
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} > RAM AT > SFLASH
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Load$$SEC_RAM_CODE$$Base = LOADADDR(.ram_code);
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Image$$SEC_RAM_CODE$$Base = ADDR(.ram_code);
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Load$$SEC_RAM_CODE$$Length = SIZEOF(.ram_code);
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.ttb :
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.ttb :
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{
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{
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Image$$TTB$$ZI$$Base = .;
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Image$$TTB$$ZI$$Base = .;
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@ -128,6 +145,8 @@ SECTIONS
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Image$$TTB$$ZI$$Limit = .;
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Image$$TTB$$ZI$$Limit = .;
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} > L_TTB
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} > L_TTB
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__etext = Load$$SEC_RAM_CODE$$Base + SIZEOF(.ram_code);
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.data : AT (__etext)
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.data : AT (__etext)
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{
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{
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Image$$RW_DATA$$Base = .;
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Image$$RW_DATA$$Base = .;
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@ -0,0 +1,250 @@
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/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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*
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* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* File Name : spibsc_iobitmask.h
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* $Rev: 6 $
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* $Date:: 2016-05-10 12:25:41 +0900#$
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* Description : SPI multi I/O bus controller register define header(for RZ/A1LU)
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*******************************************************************************/
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#ifndef __SPIBSC_IOBITMASK_H__
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#define __SPIBSC_IOBITMASK_H__
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/* ==== Mask values for IO registers ==== */
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#define SPIBSC_CMNCR_BSZ (0x00000003uL)
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#define SPIBSC_CMNCR_CPOL (0x00000008uL)
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#define SPIBSC_CMNCR_SSLP (0x00000010uL)
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#define SPIBSC_CMNCR_CPHAR (0x00000020uL)
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#define SPIBSC_CMNCR_CPHAT (0x00000040uL)
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#define SPIBSC_CMNCR_IO0FV (0x00000300uL)
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#define SPIBSC_CMNCR_IO2FV (0x00003000uL)
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#define SPIBSC_CMNCR_IO3FV (0x0000C000uL)
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#define SPIBSC_CMNCR_MOIIO0 (0x00030000uL)
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#define SPIBSC_CMNCR_MOIIO1 (0x000C0000uL)
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#define SPIBSC_CMNCR_MOIIO2 (0x00300000uL)
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#define SPIBSC_CMNCR_MOIIO3 (0x00C00000uL)
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#define SPIBSC_CMNCR_SFDE (0x01000000uL)
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#define SPIBSC_CMNCR_MD (0x80000000uL)
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#define SPIBSC_SSLDR_SCKDL (0x00000007uL)
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#define SPIBSC_SSLDR_SLNDL (0x00000700uL)
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#define SPIBSC_SSLDR_SPNDL (0x00070000uL)
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#define SPIBSC_SPBCR_BRDV (0x00000003uL)
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#define SPIBSC_SPBCR_SPBR (0x0000FF00uL)
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#define SPIBSC_DRCR_SSLE (0x00000001uL)
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#define SPIBSC_DRCR_RBE (0x00000100uL)
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#define SPIBSC_DRCR_RCF (0x00000200uL)
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#define SPIBSC_DRCR_RBURST (0x000F0000uL)
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#define SPIBSC_DRCR_SSLN (0x01000000uL)
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#define SPIBSC_DRCMR_OCMD (0x000000FFuL)
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#define SPIBSC_DRCMR_CMD (0x00FF0000uL)
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#define SPIBSC_DREAR_EAC (0x00000007uL)
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#define SPIBSC_DREAR_EAV (0x00FF0000uL)
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#define SPIBSC_DROPR_OPD0 (0x000000FFuL)
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#define SPIBSC_DROPR_OPD1 (0x0000FF00uL)
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#define SPIBSC_DROPR_OPD2 (0x00FF0000uL)
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#define SPIBSC_DROPR_OPD3 (0xFF000000uL)
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#define SPIBSC_DRENR_OPDE (0x000000F0uL)
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#define SPIBSC_DRENR_ADE (0x00000F00uL)
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#define SPIBSC_DRENR_OCDE (0x00001000uL)
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#define SPIBSC_DRENR_CDE (0x00004000uL)
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#define SPIBSC_DRENR_DME (0x00008000uL)
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#define SPIBSC_DRENR_DRDB (0x00030000uL)
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#define SPIBSC_DRENR_OPDB (0x00300000uL)
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#define SPIBSC_DRENR_ADB (0x03000000uL)
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#define SPIBSC_DRENR_OCDB (0x30000000uL)
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#define SPIBSC_DRENR_CDB (0xC0000000uL)
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#define SPIBSC_SMCR_SPIE (0x00000001uL)
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#define SPIBSC_SMCR_SPIWE (0x00000002uL)
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#define SPIBSC_SMCR_SPIRE (0x00000004uL)
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#define SPIBSC_SMCR_SSLKP (0x00000100uL)
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#define SPIBSC_SMCMR_OCMD (0x000000FFuL)
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#define SPIBSC_SMCMR_CMD (0x00FF0000uL)
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#define SPIBSC_SMADR_ADR (0xFFFFFFFFuL)
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#define SPIBSC_SMOPR_OPD0 (0x000000FFuL)
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#define SPIBSC_SMOPR_OPD1 (0x0000FF00uL)
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#define SPIBSC_SMOPR_OPD2 (0x00FF0000uL)
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#define SPIBSC_SMOPR_OPD3 (0xFF000000uL)
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#define SPIBSC_SMENR_SPIDE (0x0000000FuL)
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#define SPIBSC_SMENR_OPDE (0x000000F0uL)
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#define SPIBSC_SMENR_ADE (0x00000F00uL)
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#define SPIBSC_SMENR_OCDE (0x00001000uL)
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#define SPIBSC_SMENR_CDE (0x00004000uL)
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#define SPIBSC_SMENR_DME (0x00008000uL)
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#define SPIBSC_SMENR_SPIDB (0x00030000uL)
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#define SPIBSC_SMENR_OPDB (0x00300000uL)
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#define SPIBSC_SMENR_ADB (0x03000000uL)
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#define SPIBSC_SMENR_OCDB (0x30000000uL)
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#define SPIBSC_SMENR_CDB (0xC0000000uL)
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#define SPIBSC_SMRDR0_RDATA0 (0xFFFFFFFFuL)
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#define SPIBSC_SMRDR1_RDATA1 (0xFFFFFFFFuL)
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#define SPIBSC_SMWDR0_WDATA0 (0xFFFFFFFFuL)
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#define SPIBSC_SMWDR1_WDATA1 (0xFFFFFFFFuL)
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#define SPIBSC_CMNSR_TEND (0x00000001uL)
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#define SPIBSC_CMNSR_SSLF (0x00000002uL)
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#define SPIBSC_CKDLY_CKDLY (0x0000000fuL)
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#define SPIBSC_CKDLY_GB (0x00ff0000uL)
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#define SPIBSC_DRDMCR_DMCYC (0x00000007uL)
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#define SPIBSC_DRDMCR_DMDB (0x00030000uL)
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#define SPIBSC_DRDRENR_DRDRE (0x00000001uL)
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#define SPIBSC_DRDRENR_OPDRE (0x00000010uL)
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#define SPIBSC_DRDRENR_ADDRE (0x00000100uL)
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#define SPIBSC_SMDMCR_DMCYC (0x00000007uL)
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#define SPIBSC_SMDMCR_DMDB (0x00030000uL)
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#define SPIBSC_SMDRENR_SPIDRE (0x00000001uL)
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#define SPIBSC_SMDRENR_OPDRE (0x00000010uL)
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#define SPIBSC_SMDRENR_ADDRE (0x00000100uL)
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#define SPIBSC_SPODLY_SPODLY (0x0000ffffuL)
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#define SPIBSC_SPODLY_GB (0xff000000uL)
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/* Shift parameter */
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#define SPIBSC_CMNCR_BSZ_SHIFT (0u)
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#define SPIBSC_CMNCR_CPOL_SHIFT (3u)
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#define SPIBSC_CMNCR_SSLP_SHIFT (4u)
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#define SPIBSC_CMNCR_CPHAR_SHIFT (5u)
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#define SPIBSC_CMNCR_CPHAT_SHIFT (6u)
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#define SPIBSC_CMNCR_IO0FV_SHIFT (8u)
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#define SPIBSC_CMNCR_IO2FV_SHIFT (12u)
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#define SPIBSC_CMNCR_IO3FV_SHIFT (14u)
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#define SPIBSC_CMNCR_MOIIO0_SHIFT (16u)
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#define SPIBSC_CMNCR_MOIIO1_SHIFT (18u)
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#define SPIBSC_CMNCR_MOIIO2_SHIFT (20u)
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#define SPIBSC_CMNCR_MOIIO3_SHIFT (22u)
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#define SPIBSC_CMNCR_SFDE_SHIFT (24u)
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#define SPIBSC_CMNCR_MD_SHIFT (31u)
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#define SPIBSC_SSLDR_SCKDL_SHIFT (0u)
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#define SPIBSC_SSLDR_SLNDL_SHIFT (8u)
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#define SPIBSC_SSLDR_SPNDL_SHIFT (16u)
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#define SPIBSC_SPBCR_BRDV_SHIFT (0u)
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#define SPIBSC_SPBCR_SPBR_SHIFT (8u)
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#define SPIBSC_DRCR_SSLE_SHIFT (0u)
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#define SPIBSC_DRCR_RBE_SHIFT (8u)
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#define SPIBSC_DRCR_RCF_SHIFT (9u)
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#define SPIBSC_DRCR_RBURST_SHIFT (16u)
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#define SPIBSC_DRCR_SSLN_SHIFT (24u)
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#define SPIBSC_DRCMR_OCMD_SHIFT (0u)
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#define SPIBSC_DRCMR_CMD_SHIFT (16u)
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#define SPIBSC_DREAR_EAC_SHIFT (0u)
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#define SPIBSC_DREAR_EAV_SHIFT (16u)
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#define SPIBSC_DROPR_OPD0_SHIFT (0u)
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#define SPIBSC_DROPR_OPD1_SHIFT (8u)
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#define SPIBSC_DROPR_OPD2_SHIFT (16u)
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#define SPIBSC_DROPR_OPD3_SHIFT (24u)
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#define SPIBSC_DRENR_OPDE_SHIFT (4u)
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#define SPIBSC_DRENR_ADE_SHIFT (8u)
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#define SPIBSC_DRENR_OCDE_SHIFT (12u)
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#define SPIBSC_DRENR_CDE_SHIFT (14u)
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#define SPIBSC_DRENR_DME_SHIFT (15u)
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#define SPIBSC_DRENR_DRDB_SHIFT (16u)
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#define SPIBSC_DRENR_OPDB_SHIFT (20u)
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#define SPIBSC_DRENR_ADB_SHIFT (24u)
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#define SPIBSC_DRENR_OCDB_SHIFT (28u)
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#define SPIBSC_DRENR_CDB_SHIFT (30u)
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#define SPIBSC_SMCR_SPIE_SHIFT (0u)
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#define SPIBSC_SMCR_SPIWE_SHIFT (1u)
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#define SPIBSC_SMCR_SPIRE_SHIFT (2u)
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#define SPIBSC_SMCR_SSLKP_SHIFT (8u)
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#define SPIBSC_SMCMR_OCMD_SHIFT (0u)
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#define SPIBSC_SMCMR_CMD_SHIFT (16u)
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#define SPIBSC_SMADR_ADR_SHIFT (0u)
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#define SPIBSC_SMOPR_OPD0_SHIFT (0u)
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#define SPIBSC_SMOPR_OPD1_SHIFT (8u)
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#define SPIBSC_SMOPR_OPD2_SHIFT (16u)
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#define SPIBSC_SMOPR_OPD3_SHIFT (24u)
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#define SPIBSC_SMENR_SPIDE_SHIFT (0u)
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#define SPIBSC_SMENR_OPDE_SHIFT (4u)
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#define SPIBSC_SMENR_ADE_SHIFT (8u)
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#define SPIBSC_SMENR_OCDE_SHIFT (12u)
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#define SPIBSC_SMENR_CDE_SHIFT (14u)
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#define SPIBSC_SMENR_DME_SHIFT (15u)
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#define SPIBSC_SMENR_SPIDB_SHIFT (16u)
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#define SPIBSC_SMENR_OPDB_SHIFT (20u)
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#define SPIBSC_SMENR_ADB_SHIFT (24u)
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#define SPIBSC_SMENR_OCDB_SHIFT (28u)
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#define SPIBSC_SMENR_CDB_SHIFT (30u)
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#define SPIBSC_SMRDR0_RDATA0_SHIFT (0u)
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#define SPIBSC_SMRDR1_RDATA1_SHIFT (0u)
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#define SPIBSC_SMWDR0_WDATA0_SHIFT (0u)
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#define SPIBSC_SMWDR1_WDATA1_SHIFT (0u)
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#define SPIBSC_CMNSR_TEND_SHIFT (0u)
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#define SPIBSC_CMNSR_SSLF_SHIFT (1u)
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#define SPIBSC_CKDLY_CKDLY_SHIFT (0u)
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#define SPIBSC_CKDLY_GB_SHIFT (8u)
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#define SPIBSC_DRDMCR_DMCYC_SHIFT (0u)
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#define SPIBSC_DRDMCR_DMDB_SHIFT (16u)
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#define SPIBSC_DRDRENR_DRDRE_SHIFT (0u)
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#define SPIBSC_DRDRENR_OPDRE_SHIFT (4u)
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#define SPIBSC_DRDRENR_ADDRE_SHIFT (8u)
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#define SPIBSC_SMDMCR_DMCYC_SHIFT (0u)
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#define SPIBSC_SMDMCR_DMDB_SHIFT (16u)
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#define SPIBSC_SMDRENR_SPIDRE_SHIFT (0u)
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||||||
|
#define SPIBSC_SMDRENR_OPDRE_SHIFT (4u)
|
||||||
|
#define SPIBSC_SMDRENR_ADDRE_SHIFT (8u)
|
||||||
|
|
||||||
|
|
||||||
|
#define SPIBSC_SPODLY_SPODLY_SHIFT (0u)
|
||||||
|
#define SPIBSC_SPODLY_GB_SHIFT (24u)
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __SPIBSC_IOBITMASK_H__ */
|
||||||
|
|
||||||
|
/* End of File */
|
||||||
|
|
@ -204,7 +204,7 @@ void MMU_CreateTranslationTable(void)
|
||||||
section_normal(Sect_Normal, region);
|
section_normal(Sect_Normal, region);
|
||||||
section_normal_cod(Sect_Normal_Cod, region);
|
section_normal_cod(Sect_Normal_Cod, region);
|
||||||
section_normal_ro(Sect_Normal_RO, region);
|
section_normal_ro(Sect_Normal_RO, region);
|
||||||
section_normal_rw(Sect_Normal_RW, region);
|
section_normal(Sect_Normal_RW, region);
|
||||||
//Create descriptors for peripherals
|
//Create descriptors for peripherals
|
||||||
section_device_ro(Sect_Device_RO, region);
|
section_device_ro(Sect_Device_RO, region);
|
||||||
section_device_rw(Sect_Device_RW, region);
|
section_device_rw(Sect_Device_RW, region);
|
||||||
|
|
|
||||||
|
|
@ -155,3 +155,9 @@ void SystemInit (void)
|
||||||
// IRQ Initialize
|
// IRQ Initialize
|
||||||
IRQ_Initialize();
|
IRQ_Initialize();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void mbed_sdk_init(void) {
|
||||||
|
L1C_CleanDCacheAll();
|
||||||
|
L1C_InvalidateICacheAll();
|
||||||
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -34,4 +34,10 @@
|
||||||
|
|
||||||
#define RENESAS_RZ_A1_P0_CLK CM1_RENESAS_RZ_A1_P0_CLK
|
#define RENESAS_RZ_A1_P0_CLK CM1_RENESAS_RZ_A1_P0_CLK
|
||||||
|
|
||||||
|
/* flash (W25Q64JV) */
|
||||||
|
#define FLASH_BASE (0x18000000UL) /**< Flash Base Address */
|
||||||
|
#define FLASH_SIZE (0x00800000UL) /**< Available Flash Memory */
|
||||||
|
#define FLASH_PAGE_SIZE 256 /**< Flash Memory page size (interleaving off) */
|
||||||
|
#define FLASH_SECTOR_SIZE 4096 /**< Flash Memory sector size (interleaving off) */
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -32,7 +32,10 @@ SFLASH __ROM_BASE __ROM_SIZE ; load region size_region
|
||||||
RO_DATA +0
|
RO_DATA +0
|
||||||
{ * (+RO-DATA) } ; Application RO data (.constdata)
|
{ * (+RO-DATA) } ; Application RO data (.constdata)
|
||||||
|
|
||||||
RW_DATA 0x20020000
|
RAM_CODE 0x20020000
|
||||||
|
{ * (RAM_CODE) } ; Application RAM_CODE
|
||||||
|
|
||||||
|
RW_DATA +0 ALIGN 0x4
|
||||||
{ * (+RW) } ; Application RW data (.data)
|
{ * (+RW) } ; Application RW data (.data)
|
||||||
|
|
||||||
RW_IRAM1 +0 ALIGN 0x10
|
RW_IRAM1 +0 ALIGN 0x10
|
||||||
|
|
|
||||||
|
|
@ -105,6 +105,9 @@ SECTIONS
|
||||||
LONG (__etext2)
|
LONG (__etext2)
|
||||||
LONG (__nc_data_start)
|
LONG (__nc_data_start)
|
||||||
LONG (__nc_data_end - __nc_data_start)
|
LONG (__nc_data_end - __nc_data_start)
|
||||||
|
LONG (LOADADDR(.ram_code))
|
||||||
|
LONG (ADDR(.ram_code))
|
||||||
|
LONG (SIZEOF(.ram_code))
|
||||||
__copy_table_end__ = .;
|
__copy_table_end__ = .;
|
||||||
} > SFLASH
|
} > SFLASH
|
||||||
|
|
||||||
|
|
@ -119,8 +122,22 @@ SECTIONS
|
||||||
__zero_table_end__ = .;
|
__zero_table_end__ = .;
|
||||||
} > SFLASH
|
} > SFLASH
|
||||||
|
|
||||||
__etext = .;
|
.ram_code : ALIGN( 0x4 ) {
|
||||||
|
__ram_code_load = .;
|
||||||
|
__ram_code_start = LOADADDR(.ram_code) + ( __ram_code_load - ADDR(.ram_code) );
|
||||||
|
|
||||||
|
*(RAM_CODE)
|
||||||
|
|
||||||
|
*(RAM_CONST)
|
||||||
|
|
||||||
|
. = ALIGN( 0x4 );
|
||||||
|
__ram_code_end = LOADADDR(.ram_code) + ( . - ADDR(.ram_code) );
|
||||||
|
} > RAM AT > SFLASH
|
||||||
|
|
||||||
|
Load$$SEC_RAM_CODE$$Base = LOADADDR(.ram_code);
|
||||||
|
Image$$SEC_RAM_CODE$$Base = ADDR(.ram_code);
|
||||||
|
Load$$SEC_RAM_CODE$$Length = SIZEOF(.ram_code);
|
||||||
|
|
||||||
.ttb :
|
.ttb :
|
||||||
{
|
{
|
||||||
Image$$TTB$$ZI$$Base = .;
|
Image$$TTB$$ZI$$Base = .;
|
||||||
|
|
@ -128,6 +145,8 @@ SECTIONS
|
||||||
Image$$TTB$$ZI$$Limit = .;
|
Image$$TTB$$ZI$$Limit = .;
|
||||||
} > L_TTB
|
} > L_TTB
|
||||||
|
|
||||||
|
__etext = Load$$SEC_RAM_CODE$$Base + SIZEOF(.ram_code);
|
||||||
|
|
||||||
.data : AT (__etext)
|
.data : AT (__etext)
|
||||||
{
|
{
|
||||||
Image$$RW_DATA$$Base = .;
|
Image$$RW_DATA$$Base = .;
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,292 @@
|
||||||
|
/*******************************************************************************
|
||||||
|
* DISCLAIMER
|
||||||
|
* This software is supplied by Renesas Electronics Corporation and is only
|
||||||
|
* intended for use with Renesas products. No other uses are authorized. This
|
||||||
|
* software is owned by Renesas Electronics Corporation and is protected under
|
||||||
|
* all applicable laws, including copyright laws.
|
||||||
|
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||||
|
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||||
|
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||||
|
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||||
|
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||||
|
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||||
|
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||||
|
* Renesas reserves the right, without notice, to make changes to this software
|
||||||
|
* and to discontinue the availability of this software. By using this software,
|
||||||
|
* you agree to the additional terms and conditions found by accessing the
|
||||||
|
* following link:
|
||||||
|
* http://www.renesas.com/disclaimer
|
||||||
|
*
|
||||||
|
* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
|
||||||
|
*******************************************************************************/
|
||||||
|
/*******************************************************************************
|
||||||
|
* File Name : spibsc_iobitmask.h
|
||||||
|
* $Rev: $
|
||||||
|
* $Date:: $
|
||||||
|
* Description : SPI multi I/O bus controller register define header
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef SPIBSC_IOBITMASK_H
|
||||||
|
#define SPIBSC_IOBITMASK_H
|
||||||
|
|
||||||
|
|
||||||
|
/* ==== Mask values for IO registers ==== */
|
||||||
|
#define SPIBSC_CMNCR_BSZ (0x00000003uL)
|
||||||
|
|
||||||
|
#define SPIBSC_CMNCR_CPOL (0x00000008uL)
|
||||||
|
#define SPIBSC_CMNCR_SSLP (0x00000010uL)
|
||||||
|
#define SPIBSC_CMNCR_CPHAR (0x00000020uL)
|
||||||
|
#define SPIBSC_CMNCR_CPHAT (0x00000040uL)
|
||||||
|
|
||||||
|
#define SPIBSC_CMNCR_IO0FV (0x00000300uL)
|
||||||
|
|
||||||
|
#define SPIBSC_CMNCR_IO2FV (0x00003000uL)
|
||||||
|
#define SPIBSC_CMNCR_IO3FV (0x0000C000uL)
|
||||||
|
#define SPIBSC_CMNCR_MOIIO0 (0x00030000uL)
|
||||||
|
#define SPIBSC_CMNCR_MOIIO1 (0x000C0000uL)
|
||||||
|
#define SPIBSC_CMNCR_MOIIO2 (0x00300000uL)
|
||||||
|
#define SPIBSC_CMNCR_MOIIO3 (0x00C00000uL)
|
||||||
|
#define SPIBSC_CMNCR_SFDE (0x01000000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_CMNCR_MD (0x80000000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SSLDR_SCKDL (0x00000007uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SSLDR_SLNDL (0x00000700uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SSLDR_SPNDL (0x00070000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SPBCR_BRDV (0x00000003uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SPBCR_SPBR (0x0000FF00uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DRCR_SSLE (0x00000001uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DRCR_RBE (0x00000100uL)
|
||||||
|
#define SPIBSC_DRCR_RCF (0x00000200uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DRCR_RBURST (0x000F0000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DRCR_SSLN (0x01000000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DRCMR_OCMD (0x000000FFuL)
|
||||||
|
|
||||||
|
#define SPIBSC_DRCMR_CMD (0x00FF0000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DREAR_EAC (0x00000007uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DREAR_EAV (0x00FF0000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DROPR_OPD0 (0x000000FFuL)
|
||||||
|
#define SPIBSC_DROPR_OPD1 (0x0000FF00uL)
|
||||||
|
#define SPIBSC_DROPR_OPD2 (0x00FF0000uL)
|
||||||
|
#define SPIBSC_DROPR_OPD3 (0xFF000000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DRENR_OPDE (0x000000F0uL)
|
||||||
|
#define SPIBSC_DRENR_ADE (0x00000F00uL)
|
||||||
|
#define SPIBSC_DRENR_OCDE (0x00001000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DRENR_CDE (0x00004000uL)
|
||||||
|
#define SPIBSC_DRENR_DME (0x00008000uL)
|
||||||
|
#define SPIBSC_DRENR_DRDB (0x00030000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DRENR_OPDB (0x00300000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DRENR_ADB (0x03000000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DRENR_OCDB (0x30000000uL)
|
||||||
|
#define SPIBSC_DRENR_CDB (0xC0000000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SMCR_SPIE (0x00000001uL)
|
||||||
|
#define SPIBSC_SMCR_SPIWE (0x00000002uL)
|
||||||
|
#define SPIBSC_SMCR_SPIRE (0x00000004uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SMCR_SSLKP (0x00000100uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SMCMR_OCMD (0x000000FFuL)
|
||||||
|
|
||||||
|
#define SPIBSC_SMCMR_CMD (0x00FF0000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SMADR_ADR (0xFFFFFFFFuL)
|
||||||
|
|
||||||
|
#define SPIBSC_SMOPR_OPD0 (0x000000FFuL)
|
||||||
|
#define SPIBSC_SMOPR_OPD1 (0x0000FF00uL)
|
||||||
|
#define SPIBSC_SMOPR_OPD2 (0x00FF0000uL)
|
||||||
|
#define SPIBSC_SMOPR_OPD3 (0xFF000000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SMENR_SPIDE (0x0000000FuL)
|
||||||
|
#define SPIBSC_SMENR_OPDE (0x000000F0uL)
|
||||||
|
#define SPIBSC_SMENR_ADE (0x00000F00uL)
|
||||||
|
#define SPIBSC_SMENR_OCDE (0x00001000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SMENR_CDE (0x00004000uL)
|
||||||
|
#define SPIBSC_SMENR_DME (0x00008000uL)
|
||||||
|
#define SPIBSC_SMENR_SPIDB (0x00030000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SMENR_OPDB (0x00300000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SMENR_ADB (0x03000000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SMENR_OCDB (0x30000000uL)
|
||||||
|
#define SPIBSC_SMENR_CDB (0xC0000000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SMRDR0_RDATA0 (0xFFFFFFFFuL)
|
||||||
|
#define SPIBSC_SMRDR1_RDATA1 (0xFFFFFFFFuL)
|
||||||
|
#define SPIBSC_SMWDR0_WDATA0 (0xFFFFFFFFuL)
|
||||||
|
#define SPIBSC_SMWDR1_WDATA1 (0xFFFFFFFFuL)
|
||||||
|
|
||||||
|
#define SPIBSC_CMNSR_TEND (0x00000001uL)
|
||||||
|
#define SPIBSC_CMNSR_SSLF (0x00000002uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DRDMCR_DMCYC (0x00000007uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DRDMCR_DMDB (0x00030000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DRDRENR_DRDRE (0x00000001uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DRDRENR_OPDRE (0x00000010uL)
|
||||||
|
|
||||||
|
#define SPIBSC_DRDRENR_ADDRE (0x00000100uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SMDMCR_DMCYC (0x00000007uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SMDMCR_DMDB (0x00030000uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SMDRENR_SPIDRE (0x00000001uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SMDRENR_OPDRE (0x00000010uL)
|
||||||
|
|
||||||
|
#define SPIBSC_SMDRENR_ADDRE (0x00000100uL)
|
||||||
|
|
||||||
|
/* Shift parameter */
|
||||||
|
#define SPIBSC_CMNCR_BSZ_SHIFT (0u)
|
||||||
|
|
||||||
|
#define SPIBSC_CMNCR_CPOL_SHIFT (3u)
|
||||||
|
#define SPIBSC_CMNCR_SSLP_SHIFT (4u)
|
||||||
|
#define SPIBSC_CMNCR_CPHAR_SHIFT (5u)
|
||||||
|
#define SPIBSC_CMNCR_CPHAT_SHIFT (6u)
|
||||||
|
|
||||||
|
#define SPIBSC_CMNCR_IO0FV_SHIFT (8u)
|
||||||
|
|
||||||
|
#define SPIBSC_CMNCR_IO2FV_SHIFT (12u)
|
||||||
|
#define SPIBSC_CMNCR_IO3FV_SHIFT (14u)
|
||||||
|
#define SPIBSC_CMNCR_MOIIO0_SHIFT (16u)
|
||||||
|
#define SPIBSC_CMNCR_MOIIO1_SHIFT (18u)
|
||||||
|
#define SPIBSC_CMNCR_MOIIO2_SHIFT (20u)
|
||||||
|
#define SPIBSC_CMNCR_MOIIO3_SHIFT (22u)
|
||||||
|
#define SPIBSC_CMNCR_SFDE_SHIFT (24u)
|
||||||
|
|
||||||
|
#define SPIBSC_CMNCR_MD_SHIFT (31u)
|
||||||
|
|
||||||
|
#define SPIBSC_SSLDR_SCKDL_SHIFT (0u)
|
||||||
|
|
||||||
|
#define SPIBSC_SSLDR_SLNDL_SHIFT (8u)
|
||||||
|
|
||||||
|
#define SPIBSC_SSLDR_SPNDL_SHIFT (16u)
|
||||||
|
|
||||||
|
#define SPIBSC_SPBCR_BRDV_SHIFT (0u)
|
||||||
|
|
||||||
|
#define SPIBSC_SPBCR_SPBR_SHIFT (8u)
|
||||||
|
|
||||||
|
#define SPIBSC_DRCR_SSLE_SHIFT (0u)
|
||||||
|
|
||||||
|
#define SPIBSC_DRCR_RBE_SHIFT (8u)
|
||||||
|
#define SPIBSC_DRCR_RCF_SHIFT (9u)
|
||||||
|
|
||||||
|
#define SPIBSC_DRCR_RBURST_SHIFT (16u)
|
||||||
|
|
||||||
|
#define SPIBSC_DRCR_SSLN_SHIFT (24u)
|
||||||
|
|
||||||
|
#define SPIBSC_DRCMR_OCMD_SHIFT (0u)
|
||||||
|
|
||||||
|
#define SPIBSC_DRCMR_CMD_SHIFT (16u)
|
||||||
|
|
||||||
|
#define SPIBSC_DREAR_EAC_SHIFT (0u)
|
||||||
|
|
||||||
|
#define SPIBSC_DREAR_EAV_SHIFT (16u)
|
||||||
|
|
||||||
|
#define SPIBSC_DROPR_OPD0_SHIFT (0u)
|
||||||
|
#define SPIBSC_DROPR_OPD1_SHIFT (8u)
|
||||||
|
#define SPIBSC_DROPR_OPD2_SHIFT (16u)
|
||||||
|
#define SPIBSC_DROPR_OPD3_SHIFT (24u)
|
||||||
|
|
||||||
|
#define SPIBSC_DRENR_OPDE_SHIFT (4u)
|
||||||
|
#define SPIBSC_DRENR_ADE_SHIFT (8u)
|
||||||
|
#define SPIBSC_DRENR_OCDE_SHIFT (12u)
|
||||||
|
|
||||||
|
#define SPIBSC_DRENR_CDE_SHIFT (14u)
|
||||||
|
#define SPIBSC_DRENR_DME_SHIFT (15u)
|
||||||
|
#define SPIBSC_DRENR_DRDB_SHIFT (16u)
|
||||||
|
|
||||||
|
#define SPIBSC_DRENR_OPDB_SHIFT (20u)
|
||||||
|
|
||||||
|
#define SPIBSC_DRENR_ADB_SHIFT (24u)
|
||||||
|
|
||||||
|
#define SPIBSC_DRENR_OCDB_SHIFT (28u)
|
||||||
|
#define SPIBSC_DRENR_CDB_SHIFT (30u)
|
||||||
|
|
||||||
|
#define SPIBSC_SMCR_SPIE_SHIFT (0u)
|
||||||
|
#define SPIBSC_SMCR_SPIWE_SHIFT (1u)
|
||||||
|
#define SPIBSC_SMCR_SPIRE_SHIFT (2u)
|
||||||
|
|
||||||
|
#define SPIBSC_SMCR_SSLKP_SHIFT (8u)
|
||||||
|
|
||||||
|
#define SPIBSC_SMCMR_OCMD_SHIFT (0u)
|
||||||
|
|
||||||
|
#define SPIBSC_SMCMR_CMD_SHIFT (16u)
|
||||||
|
|
||||||
|
#define SPIBSC_SMADR_ADR_SHIFT (0u)
|
||||||
|
|
||||||
|
#define SPIBSC_SMOPR_OPD0_SHIFT (0u)
|
||||||
|
#define SPIBSC_SMOPR_OPD1_SHIFT (8u)
|
||||||
|
#define SPIBSC_SMOPR_OPD2_SHIFT (16u)
|
||||||
|
#define SPIBSC_SMOPR_OPD3_SHIFT (24u)
|
||||||
|
|
||||||
|
#define SPIBSC_SMENR_SPIDE_SHIFT (0u)
|
||||||
|
#define SPIBSC_SMENR_OPDE_SHIFT (4u)
|
||||||
|
#define SPIBSC_SMENR_ADE_SHIFT (8u)
|
||||||
|
#define SPIBSC_SMENR_OCDE_SHIFT (12u)
|
||||||
|
|
||||||
|
#define SPIBSC_SMENR_CDE_SHIFT (14u)
|
||||||
|
#define SPIBSC_SMENR_DME_SHIFT (15u)
|
||||||
|
#define SPIBSC_SMENR_SPIDB_SHIFT (16u)
|
||||||
|
|
||||||
|
#define SPIBSC_SMENR_OPDB_SHIFT (20u)
|
||||||
|
|
||||||
|
#define SPIBSC_SMENR_ADB_SHIFT (24u)
|
||||||
|
|
||||||
|
#define SPIBSC_SMENR_OCDB_SHIFT (28u)
|
||||||
|
#define SPIBSC_SMENR_CDB_SHIFT (30u)
|
||||||
|
|
||||||
|
#define SPIBSC_SMRDR0_RDATA0_SHIFT (0u)
|
||||||
|
#define SPIBSC_SMRDR1_RDATA1_SHIFT (0u)
|
||||||
|
#define SPIBSC_SMWDR0_WDATA0_SHIFT (0u)
|
||||||
|
#define SPIBSC_SMWDR1_WDATA1_SHIFT (0u)
|
||||||
|
|
||||||
|
#define SPIBSC_CMNSR_TEND_SHIFT (0u)
|
||||||
|
#define SPIBSC_CMNSR_SSLF_SHIFT (1u)
|
||||||
|
|
||||||
|
#define SPIBSC_DRDMCR_DMCYC_SHIFT (0u)
|
||||||
|
|
||||||
|
#define SPIBSC_DRDMCR_DMDB_SHIFT (16u)
|
||||||
|
|
||||||
|
#define SPIBSC_DRDRENR_DRDRE_SHIFT (0u)
|
||||||
|
|
||||||
|
#define SPIBSC_DRDRENR_OPDRE_SHIFT (4u)
|
||||||
|
|
||||||
|
#define SPIBSC_DRDRENR_ADDRE_SHIFT (8u)
|
||||||
|
|
||||||
|
#define SPIBSC_SMDMCR_DMCYC_SHIFT (0u)
|
||||||
|
|
||||||
|
#define SPIBSC_SMDMCR_DMDB_SHIFT (16u)
|
||||||
|
|
||||||
|
#define SPIBSC_SMDRENR_SPIDRE_SHIFT (0u)
|
||||||
|
|
||||||
|
#define SPIBSC_SMDRENR_OPDRE_SHIFT (4u)
|
||||||
|
|
||||||
|
#define SPIBSC_SMDRENR_ADDRE_SHIFT (8u)
|
||||||
|
|
||||||
|
#endif /* SPIBSC_IOBITMASK_H */
|
||||||
|
|
||||||
|
/* End of File */
|
||||||
|
|
@ -204,7 +204,7 @@ void MMU_CreateTranslationTable(void)
|
||||||
section_normal(Sect_Normal, region);
|
section_normal(Sect_Normal, region);
|
||||||
section_normal_cod(Sect_Normal_Cod, region);
|
section_normal_cod(Sect_Normal_Cod, region);
|
||||||
section_normal_ro(Sect_Normal_RO, region);
|
section_normal_ro(Sect_Normal_RO, region);
|
||||||
section_normal_rw(Sect_Normal_RW, region);
|
section_normal(Sect_Normal_RW, region);
|
||||||
//Create descriptors for peripherals
|
//Create descriptors for peripherals
|
||||||
section_device_ro(Sect_Device_RO, region);
|
section_device_ro(Sect_Device_RO, region);
|
||||||
section_device_rw(Sect_Device_RW, region);
|
section_device_rw(Sect_Device_RW, region);
|
||||||
|
|
|
||||||
|
|
@ -155,3 +155,8 @@ void SystemInit (void)
|
||||||
// IRQ Initialize
|
// IRQ Initialize
|
||||||
IRQ_Initialize();
|
IRQ_Initialize();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void mbed_sdk_init(void) {
|
||||||
|
L1C_CleanDCacheAll();
|
||||||
|
L1C_InvalidateICacheAll();
|
||||||
|
}
|
||||||
|
|
|
||||||
|
|
@ -34,4 +34,10 @@
|
||||||
|
|
||||||
#define RENESAS_RZ_A1_P0_CLK CM0_RENESAS_RZ_A1_P0_CLK
|
#define RENESAS_RZ_A1_P0_CLK CM0_RENESAS_RZ_A1_P0_CLK
|
||||||
|
|
||||||
|
/* flash (MX25L6433FM2I) */
|
||||||
|
#define FLASH_BASE (0x18000000UL) /**< Flash Base Address */
|
||||||
|
#define FLASH_SIZE (0x00800000UL) /**< Available Flash Memory */
|
||||||
|
#define FLASH_PAGE_SIZE 256 /**< Flash Memory page size (interleaving off) */
|
||||||
|
#define FLASH_SECTOR_SIZE 4096 /**< Flash Memory sector size (interleaving off) */
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,726 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2018 ARM Limited
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "flash_api.h"
|
||||||
|
#include "mbed_critical.h"
|
||||||
|
|
||||||
|
#if DEVICE_FLASH
|
||||||
|
#include "iodefine.h"
|
||||||
|
#include "spibsc_iobitmask.h"
|
||||||
|
#include "spibsc.h"
|
||||||
|
#include "mbed_drv_cfg.h"
|
||||||
|
|
||||||
|
/* ---- serial flash command ---- */
|
||||||
|
#define SFLASHCMD_SECTOR_ERASE (0x20u) /* SE 3-byte address(1bit) */
|
||||||
|
#define SFLASHCMD_PAGE_PROGRAM (0x02u) /* PP 3-byte address(1bit), data(1bit) */
|
||||||
|
#define SFLASHCMD_READ_STATUS_REG (0x05u) /* RDSR data(1bit) */
|
||||||
|
#define SFLASHCMD_WRITE_ENABLE (0x06u) /* WREN */
|
||||||
|
/* ---- serial flash register definitions ---- */
|
||||||
|
#define STREG_BUSY_BIT (0x01u) /* SR.[0]BUSY Erase/Write In Progress (RO) */
|
||||||
|
|
||||||
|
/* Definition of the base address for the MMU translation table */
|
||||||
|
#if defined(__CC_ARM) || defined(__GNUC__)
|
||||||
|
extern uint32_t Image$$TTB$$ZI$$Base;
|
||||||
|
#define TTB ((uint32_t)&Image$$TTB$$ZI$$Base) /* using linker symbol */
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
#pragma section="TTB"
|
||||||
|
#define TTB ((uint32_t)__section_begin("TTB"))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
uint32_t cdb; /* bit-width : command */
|
||||||
|
uint32_t ocdb; /* bit-width : optional command */
|
||||||
|
uint32_t adb; /* bit-width : address */
|
||||||
|
uint32_t opdb; /* bit-width : option data */
|
||||||
|
uint32_t spidb; /* bit-width : data */
|
||||||
|
|
||||||
|
uint32_t cde; /* Enable : command */
|
||||||
|
uint32_t ocde; /* Enable : optional command */
|
||||||
|
uint32_t ade; /* Enable : address */
|
||||||
|
uint32_t opde; /* Enable : option data */
|
||||||
|
uint32_t spide; /* Enable : data */
|
||||||
|
|
||||||
|
uint32_t sslkp; /* SPBSSL level */
|
||||||
|
uint32_t spire; /* Enable data read */
|
||||||
|
uint32_t spiwe; /* Enable data write */
|
||||||
|
|
||||||
|
uint32_t dme; /* Enable : dummy cycle */
|
||||||
|
|
||||||
|
uint32_t addre; /* DDR enable : address */
|
||||||
|
uint32_t opdre; /* DDR enable : option data */
|
||||||
|
uint32_t spidre; /* DDR enable : data */
|
||||||
|
|
||||||
|
uint8_t dmdb; /* bit-width : dummy cycle */
|
||||||
|
uint8_t dmcyc; /* number of dummy cycles */
|
||||||
|
|
||||||
|
uint8_t cmd; /* command */
|
||||||
|
uint8_t ocmd; /* optional command */
|
||||||
|
uint32_t addr; /* address */
|
||||||
|
uint8_t opd[4]; /* option data 3/2/1/0 */
|
||||||
|
uint32_t smrdr[2]; /* read data */
|
||||||
|
uint32_t smwdr[2]; /* write data */
|
||||||
|
} st_spibsc_spimd_reg_t;
|
||||||
|
|
||||||
|
/* SPI Multi-I/O bus address space address definitions */
|
||||||
|
#define SPIBSC_ADDR_START (0x18000000uL)
|
||||||
|
#define SPIBSC_ADDR_END (0x1BFFFFFFuL)
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
uint32_t b0 : 1 ; /* bit 0 : - (0) */
|
||||||
|
uint32_t b1 : 1 ; /* bit 1 : - (1) */
|
||||||
|
uint32_t B : 1 ; /* bit 2 : B Memory region attribute bit */
|
||||||
|
uint32_t C : 1 ; /* bit 3 : C Memory region attribute bit */
|
||||||
|
uint32_t XN : 1 ; /* bit 4 : XN Execute-never bit */
|
||||||
|
uint32_t Domain : 4 ; /* bit 8-5 : Domain Domain field */
|
||||||
|
uint32_t b9 : 1 ; /* bit 9 : IMP IMPLEMENTATION DEFINED */
|
||||||
|
uint32_t AP1_0 : 2 ; /* bit 11-10 : AP[1:0] Access permissions bits:bit1-0 */
|
||||||
|
uint32_t TEX : 3 ; /* bit 14-12 : TEX[2:0] Memory region attribute bits */
|
||||||
|
uint32_t AP2 : 1 ; /* bit 15 : AP[2] Access permissions bits:bit2 */
|
||||||
|
uint32_t S : 1 ; /* bit 16 : S Shareable bit */
|
||||||
|
uint32_t nG : 1 ; /* bit 17 : nG Not global bit */
|
||||||
|
uint32_t b18 : 1 ; /* bit 18 : - (0) */
|
||||||
|
uint32_t NS : 1 ; /* bit 19 : NS Non-secure bit */
|
||||||
|
uint32_t base_addr : 12; /* bit 31-20 : PA[31:20] PA(physical address) bits:bit31-20 */
|
||||||
|
} mmu_ttbl_desc_section_t;
|
||||||
|
|
||||||
|
static mmu_ttbl_desc_section_t desc_tbl[(SPIBSC_ADDR_END >> 20) - (SPIBSC_ADDR_START >> 20) + 1];
|
||||||
|
static volatile struct st_spibsc* SPIBSC = &SPIBSC0;
|
||||||
|
static st_spibsc_spimd_reg_t spimd_reg;
|
||||||
|
|
||||||
|
#if defined(__ICCARM__)
|
||||||
|
#define RAM_CODE_SEC __ramfunc
|
||||||
|
#else
|
||||||
|
#define RAM_CODE_SEC __attribute__((section("RAM_CODE")))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Global function for optimization */
|
||||||
|
RAM_CODE_SEC int32_t _sector_erase(uint32_t addr);
|
||||||
|
RAM_CODE_SEC int32_t _page_program(uint32_t addr, const uint8_t * buf, int32_t size);
|
||||||
|
|
||||||
|
static RAM_CODE_SEC int32_t write_enable(void);
|
||||||
|
static RAM_CODE_SEC int32_t busy_wait(void);
|
||||||
|
static RAM_CODE_SEC int32_t read_register(uint8_t cmd, uint8_t * status);
|
||||||
|
static RAM_CODE_SEC int32_t data_send(uint32_t bit_width, uint32_t spbssl_level, const uint8_t * buf, int32_t size);
|
||||||
|
static RAM_CODE_SEC void spi_mode(void);
|
||||||
|
static RAM_CODE_SEC void ex_mode(void);
|
||||||
|
static RAM_CODE_SEC void clear_spimd_reg(st_spibsc_spimd_reg_t * regset);
|
||||||
|
static RAM_CODE_SEC int32_t spibsc_transfer(st_spibsc_spimd_reg_t * regset);
|
||||||
|
static RAM_CODE_SEC uint32_t RegRead_32(volatile uint32_t * ioreg, uint32_t shift, uint32_t mask);
|
||||||
|
static RAM_CODE_SEC void RegWwrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask);
|
||||||
|
static RAM_CODE_SEC void change_mmu_ttbl_spibsc(uint32_t type);
|
||||||
|
static RAM_CODE_SEC void spibsc_stop(void);
|
||||||
|
static RAM_CODE_SEC void cache_control(void);
|
||||||
|
|
||||||
|
int32_t flash_init(flash_t *obj)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int32_t flash_free(flash_t *obj)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int32_t flash_erase_sector(flash_t *obj, uint32_t address)
|
||||||
|
{
|
||||||
|
int32_t ret;
|
||||||
|
|
||||||
|
core_util_critical_section_enter();
|
||||||
|
ret = _sector_erase(address - FLASH_BASE);
|
||||||
|
core_util_critical_section_exit();
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
|
||||||
|
{
|
||||||
|
int32_t ret;
|
||||||
|
|
||||||
|
core_util_critical_section_enter();
|
||||||
|
ret = _page_program(address - FLASH_BASE, data, size);
|
||||||
|
core_util_critical_section_exit();
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
|
||||||
|
{
|
||||||
|
if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
|
||||||
|
return MBED_FLASH_INVALID_SIZE;
|
||||||
|
}
|
||||||
|
|
||||||
|
return FLASH_SECTOR_SIZE;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t flash_get_page_size(const flash_t *obj)
|
||||||
|
{
|
||||||
|
return FLASH_PAGE_SIZE;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t flash_get_start_address(const flash_t *obj)
|
||||||
|
{
|
||||||
|
return FLASH_BASE;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t flash_get_size(const flash_t *obj)
|
||||||
|
{
|
||||||
|
return FLASH_SIZE;
|
||||||
|
}
|
||||||
|
|
||||||
|
int32_t _sector_erase(uint32_t addr)
|
||||||
|
{
|
||||||
|
int32_t ret;
|
||||||
|
|
||||||
|
spi_mode();
|
||||||
|
|
||||||
|
/* ---- Write enable ---- */
|
||||||
|
ret = write_enable(); /* WREN Command */
|
||||||
|
if (ret != 0) {
|
||||||
|
ex_mode();
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ---- spimd_reg init ---- */
|
||||||
|
clear_spimd_reg(&spimd_reg);
|
||||||
|
|
||||||
|
/* ---- command ---- */
|
||||||
|
spimd_reg.cde = SPIBSC_OUTPUT_ENABLE;
|
||||||
|
spimd_reg.cdb = SPIBSC_1BIT;
|
||||||
|
spimd_reg.cmd = SFLASHCMD_SECTOR_ERASE;
|
||||||
|
|
||||||
|
/* ---- address ---- */
|
||||||
|
spimd_reg.ade = SPIBSC_OUTPUT_ADDR_24;
|
||||||
|
spimd_reg.addre = SPIBSC_SDR_TRANS; /* SDR */
|
||||||
|
spimd_reg.adb = SPIBSC_1BIT;
|
||||||
|
spimd_reg.addr = addr;
|
||||||
|
|
||||||
|
ret = spibsc_transfer(&spimd_reg);
|
||||||
|
if (ret != 0) {
|
||||||
|
ex_mode();
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = busy_wait();
|
||||||
|
|
||||||
|
ex_mode();
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
int32_t _page_program(uint32_t addr, const uint8_t * buf, int32_t size)
|
||||||
|
{
|
||||||
|
int32_t ret;
|
||||||
|
|
||||||
|
spi_mode();
|
||||||
|
|
||||||
|
/* ---- Write enable ---- */
|
||||||
|
ret = write_enable(); /* WREN Command */
|
||||||
|
if (ret != 0) {
|
||||||
|
ex_mode();
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ----------- 1. Command, Address ---------------*/
|
||||||
|
/* ---- spimd_reg init ---- */
|
||||||
|
clear_spimd_reg(&spimd_reg);
|
||||||
|
|
||||||
|
/* ---- command ---- */
|
||||||
|
spimd_reg.cde = SPIBSC_OUTPUT_ENABLE;
|
||||||
|
spimd_reg.cdb = SPIBSC_1BIT;
|
||||||
|
spimd_reg.cmd = SFLASHCMD_PAGE_PROGRAM;
|
||||||
|
|
||||||
|
/* ---- address ---- */
|
||||||
|
spimd_reg.ade = SPIBSC_OUTPUT_ADDR_24;
|
||||||
|
spimd_reg.addre = SPIBSC_SDR_TRANS; /* SDR */
|
||||||
|
spimd_reg.adb = SPIBSC_1BIT;
|
||||||
|
spimd_reg.addr = addr;
|
||||||
|
|
||||||
|
/* ---- Others ---- */
|
||||||
|
spimd_reg.sslkp = SPIBSC_SPISSL_KEEP; /* SPBSSL level */
|
||||||
|
|
||||||
|
ret = spibsc_transfer(&spimd_reg); /* Command,Address */
|
||||||
|
if (ret != 0) {
|
||||||
|
ex_mode();
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ----------- 2. Data ---------------*/
|
||||||
|
ret = data_send(SPIBSC_1BIT, SPIBSC_SPISSL_NEGATE, buf, size);
|
||||||
|
if (ret != 0) {
|
||||||
|
ex_mode();
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = busy_wait();
|
||||||
|
|
||||||
|
ex_mode();
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int32_t write_enable(void)
|
||||||
|
{
|
||||||
|
int32_t ret;
|
||||||
|
|
||||||
|
/* ---- spimd_reg init ---- */
|
||||||
|
clear_spimd_reg(&spimd_reg);
|
||||||
|
|
||||||
|
/* ---- command ---- */
|
||||||
|
spimd_reg.cde = SPIBSC_OUTPUT_ENABLE;
|
||||||
|
spimd_reg.cdb = SPIBSC_1BIT;
|
||||||
|
spimd_reg.cmd = SFLASHCMD_WRITE_ENABLE;
|
||||||
|
|
||||||
|
ret = spibsc_transfer(&spimd_reg);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int32_t busy_wait(void)
|
||||||
|
{
|
||||||
|
int32_t ret;
|
||||||
|
uint8_t st_reg;
|
||||||
|
|
||||||
|
while (1) {
|
||||||
|
ret = read_register(SFLASHCMD_READ_STATUS_REG, &st_reg);
|
||||||
|
if (ret != 0) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
if ((st_reg & STREG_BUSY_BIT) == 0) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int32_t read_register(uint8_t cmd, uint8_t * status)
|
||||||
|
{
|
||||||
|
int32_t ret;
|
||||||
|
|
||||||
|
/* ---- spimd_reg init ---- */
|
||||||
|
clear_spimd_reg(&spimd_reg);
|
||||||
|
|
||||||
|
/* ---- command ---- */
|
||||||
|
spimd_reg.cde = SPIBSC_OUTPUT_ENABLE;
|
||||||
|
spimd_reg.cdb = SPIBSC_1BIT;
|
||||||
|
spimd_reg.cmd = cmd;
|
||||||
|
|
||||||
|
/* ---- Others ---- */
|
||||||
|
spimd_reg.sslkp = SPIBSC_SPISSL_NEGATE; /* SPBSSL level */
|
||||||
|
spimd_reg.spire = SPIBSC_SPIDATA_ENABLE; /* read enable/disable */
|
||||||
|
spimd_reg.spiwe = SPIBSC_SPIDATA_ENABLE; /* write enable/disable */
|
||||||
|
|
||||||
|
/* ---- data ---- */
|
||||||
|
spimd_reg.spide = SPIBSC_OUTPUT_SPID_8; /* Enable(8bit) */
|
||||||
|
spimd_reg.spidre = SPIBSC_SDR_TRANS; /* SDR */
|
||||||
|
spimd_reg.spidb = SPIBSC_1BIT;
|
||||||
|
spimd_reg.smwdr[0] = 0x00; /* Output 0 in read status */
|
||||||
|
spimd_reg.smwdr[1] = 0x00; /* Output 0 in read status */
|
||||||
|
|
||||||
|
ret = spibsc_transfer(&spimd_reg);
|
||||||
|
if (ret == 0) {
|
||||||
|
*status = (uint8_t)(spimd_reg.smrdr[0]); /* Data[7:0] */
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int32_t data_send(uint32_t bit_width, uint32_t spbssl_level, const uint8_t * buf, int32_t size)
|
||||||
|
{
|
||||||
|
int32_t ret = 0;
|
||||||
|
int32_t unit;
|
||||||
|
uint8_t *buf_b;
|
||||||
|
uint16_t *buf_s;
|
||||||
|
uint32_t *buf_l;
|
||||||
|
|
||||||
|
/* ---- spimd_reg init ---- */
|
||||||
|
clear_spimd_reg(&spimd_reg);
|
||||||
|
|
||||||
|
/* ---- Others ---- */
|
||||||
|
spimd_reg.sslkp = SPIBSC_SPISSL_KEEP; /* SPBSSL level */
|
||||||
|
spimd_reg.spiwe = SPIBSC_SPIDATA_ENABLE; /* write enable/disable */
|
||||||
|
|
||||||
|
/* ---- data ---- */
|
||||||
|
spimd_reg.spidb = bit_width;
|
||||||
|
spimd_reg.spidre= SPIBSC_SDR_TRANS; /* SDR */
|
||||||
|
|
||||||
|
if (((uint32_t)size & 0x3) == 0) {
|
||||||
|
spimd_reg.spide = SPIBSC_OUTPUT_SPID_32; /* Enable(32bit) */
|
||||||
|
unit = 4;
|
||||||
|
} else if (((uint32_t)size & 0x1) == 0) {
|
||||||
|
spimd_reg.spide = SPIBSC_OUTPUT_SPID_16; /* Enable(16bit) */
|
||||||
|
unit = 2;
|
||||||
|
} else {
|
||||||
|
spimd_reg.spide = SPIBSC_OUTPUT_SPID_8; /* Enable(8bit) */
|
||||||
|
unit = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
while (size > 0) {
|
||||||
|
if (unit == 1) {
|
||||||
|
buf_b = (uint8_t *)buf;
|
||||||
|
spimd_reg.smwdr[0] = (uint32_t)(((uint32_t)*buf_b) & 0x000000FF);
|
||||||
|
} else if (unit == 2) {
|
||||||
|
buf_s = (uint16_t *)buf;
|
||||||
|
spimd_reg.smwdr[0] = (uint32_t)(((uint32_t)*buf_s) & 0x0000FFFF);
|
||||||
|
} else if (unit == 4) {
|
||||||
|
buf_l = (uint32_t *)buf;
|
||||||
|
spimd_reg.smwdr[0] = (uint32_t)(((uint32_t)(*buf_l)) & 0xfffffffful);
|
||||||
|
} else {
|
||||||
|
/* Do Nothing */
|
||||||
|
}
|
||||||
|
|
||||||
|
buf += unit;
|
||||||
|
size -= unit;
|
||||||
|
|
||||||
|
if (size <= 0) {
|
||||||
|
spimd_reg.sslkp = spbssl_level;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = spibsc_transfer(&spimd_reg); /* Data */
|
||||||
|
if (ret != 0) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void spi_mode(void)
|
||||||
|
{
|
||||||
|
volatile uint32_t dummy_read_32;
|
||||||
|
|
||||||
|
if (RegRead_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD) != SPIBSC_CMNCR_MD_SPI) {
|
||||||
|
/* ==== Change the MMU translation table SPI Multi-I/O bus space settings
|
||||||
|
for use in SPI operating mode ==== */
|
||||||
|
change_mmu_ttbl_spibsc(0);
|
||||||
|
|
||||||
|
/* ==== Cleaning and invalidation of cache ==== */
|
||||||
|
cache_control();
|
||||||
|
|
||||||
|
/* ==== Switch to SPI operating mode ==== */
|
||||||
|
spibsc_stop();
|
||||||
|
|
||||||
|
dummy_read_32 = SPIBSC->CMNCR; /* dummy read */
|
||||||
|
/* SPI Mode */
|
||||||
|
RegWwrite_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_SPI, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD);
|
||||||
|
dummy_read_32 = SPIBSC->CMNCR; /* dummy read */
|
||||||
|
|
||||||
|
}
|
||||||
|
(void)dummy_read_32;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void ex_mode(void)
|
||||||
|
{
|
||||||
|
volatile uint32_t dummy_read_32;
|
||||||
|
|
||||||
|
if (RegRead_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD) != SPIBSC_CMNCR_MD_EXTRD) {
|
||||||
|
/* ==== Switch to external address space read mode and clear SPIBSC read cache ==== */
|
||||||
|
spibsc_stop();
|
||||||
|
|
||||||
|
/* Flush SPIBSC's read cache */
|
||||||
|
RegWwrite_32(&SPIBSC->DRCR, SPIBSC_DRCR_RCF_EXE, SPIBSC_DRCR_RCF_SHIFT, SPIBSC_DRCR_RCF);
|
||||||
|
dummy_read_32 = SPIBSC->DRCR; /* dummy read */
|
||||||
|
|
||||||
|
/* External address space read mode */
|
||||||
|
RegWwrite_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_EXTRD, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD);
|
||||||
|
dummy_read_32 = SPIBSC->CMNCR; /* dummy read */
|
||||||
|
|
||||||
|
/* ==== Change the MMU translation table SPI Multi-I/O bus space settings
|
||||||
|
for use in external address space read mode ==== */
|
||||||
|
change_mmu_ttbl_spibsc(1);
|
||||||
|
|
||||||
|
/* ==== Cleaning and invalidation of cache ==== */
|
||||||
|
cache_control();
|
||||||
|
}
|
||||||
|
(void)dummy_read_32;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void clear_spimd_reg(st_spibsc_spimd_reg_t * regset)
|
||||||
|
{
|
||||||
|
/* ---- command ---- */
|
||||||
|
regset->cde = SPIBSC_OUTPUT_DISABLE;
|
||||||
|
regset->cdb = SPIBSC_1BIT;
|
||||||
|
regset->cmd = 0x00;
|
||||||
|
|
||||||
|
/* ---- optional command ---- */
|
||||||
|
regset->ocde = SPIBSC_OUTPUT_DISABLE;
|
||||||
|
regset->ocdb = SPIBSC_1BIT;
|
||||||
|
regset->ocmd = 0x00;
|
||||||
|
|
||||||
|
/* ---- address ---- */
|
||||||
|
regset->ade = SPIBSC_OUTPUT_DISABLE;
|
||||||
|
regset->addre = SPIBSC_SDR_TRANS; /* SDR */
|
||||||
|
regset->adb = SPIBSC_1BIT;
|
||||||
|
regset->addr = 0x00000000;
|
||||||
|
|
||||||
|
/* ---- option data ---- */
|
||||||
|
regset->opde = SPIBSC_OUTPUT_DISABLE;
|
||||||
|
regset->opdre = SPIBSC_SDR_TRANS; /* SDR */
|
||||||
|
regset->opdb = SPIBSC_1BIT;
|
||||||
|
regset->opd[0] = 0x00; /* OPD3 */
|
||||||
|
regset->opd[1] = 0x00; /* OPD2 */
|
||||||
|
regset->opd[2] = 0x00; /* OPD1 */
|
||||||
|
regset->opd[3] = 0x00; /* OPD0 */
|
||||||
|
|
||||||
|
/* ---- dummy cycle ---- */
|
||||||
|
regset->dme = SPIBSC_DUMMY_CYC_DISABLE;
|
||||||
|
regset->dmdb = SPIBSC_1BIT;
|
||||||
|
regset->dmcyc = SPIBSC_DUMMY_1CYC;
|
||||||
|
|
||||||
|
/* ---- data ---- */
|
||||||
|
regset->spide = SPIBSC_OUTPUT_DISABLE;
|
||||||
|
regset->spidre = SPIBSC_SDR_TRANS; /* SDR */
|
||||||
|
regset->spidb = SPIBSC_1BIT;
|
||||||
|
|
||||||
|
/* ---- Others ---- */
|
||||||
|
regset->sslkp = SPIBSC_SPISSL_NEGATE; /* SPBSSL level */
|
||||||
|
regset->spire = SPIBSC_SPIDATA_DISABLE; /* read enable/disable */
|
||||||
|
regset->spiwe = SPIBSC_SPIDATA_DISABLE; /* write enable/disable */
|
||||||
|
}
|
||||||
|
|
||||||
|
static int32_t spibsc_transfer(st_spibsc_spimd_reg_t * regset)
|
||||||
|
{
|
||||||
|
if (RegRead_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD) != SPIBSC_CMNCR_MD_SPI) {
|
||||||
|
if (RegRead_32(&SPIBSC->CMNSR, SPIBSC_CMNSR_SSLF_SHIFT, SPIBSC_CMNSR_SSLF) != SPIBSC_SSL_NEGATE) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
/* SPI Mode */
|
||||||
|
RegWwrite_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_SPI, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (RegRead_32(&SPIBSC->CMNSR, SPIBSC_CMNSR_TEND_SHIFT, SPIBSC_CMNSR_TEND) != SPIBSC_TRANS_END) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ---- Command ---- */
|
||||||
|
/* Enable/Disable */
|
||||||
|
RegWwrite_32(&SPIBSC->SMENR, regset->cde, SPIBSC_SMENR_CDE_SHIFT, SPIBSC_SMENR_CDE);
|
||||||
|
if (regset->cde != SPIBSC_OUTPUT_DISABLE) {
|
||||||
|
/* Command */
|
||||||
|
RegWwrite_32(&SPIBSC->SMCMR, regset->cmd, SPIBSC_SMCMR_CMD_SHIFT, SPIBSC_SMCMR_CMD);
|
||||||
|
/* Single/Dual/Quad */
|
||||||
|
RegWwrite_32(&SPIBSC->SMENR, regset->cdb, SPIBSC_SMENR_CDB_SHIFT, SPIBSC_SMENR_CDB);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ---- Option Command ---- */
|
||||||
|
/* Enable/Disable */
|
||||||
|
RegWwrite_32(&SPIBSC->SMENR, regset->ocde, SPIBSC_SMENR_OCDE_SHIFT, SPIBSC_SMENR_OCDE);
|
||||||
|
if (regset->ocde != SPIBSC_OUTPUT_DISABLE) {
|
||||||
|
/* Option Command */
|
||||||
|
RegWwrite_32(&SPIBSC->SMCMR, regset->ocmd, SPIBSC_SMCMR_OCMD_SHIFT, SPIBSC_SMCMR_OCMD);
|
||||||
|
/* Single/Dual/Quad */
|
||||||
|
RegWwrite_32(&SPIBSC->SMENR, regset->ocdb, SPIBSC_SMENR_OCDB_SHIFT, SPIBSC_SMENR_OCDB);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ---- Address ---- */
|
||||||
|
/* Enable/Disable */
|
||||||
|
RegWwrite_32(&SPIBSC->SMENR, regset->ade, SPIBSC_SMENR_ADE_SHIFT, SPIBSC_SMENR_ADE);
|
||||||
|
if (regset->ade != SPIBSC_OUTPUT_DISABLE) {
|
||||||
|
/* Address */
|
||||||
|
RegWwrite_32(&SPIBSC->SMADR, regset->addr, SPIBSC_SMADR_ADR_SHIFT, SPIBSC_SMADR_ADR);
|
||||||
|
/* Single/Dual/Quad */
|
||||||
|
RegWwrite_32(&SPIBSC->SMENR, regset->adb, SPIBSC_SMENR_ADB_SHIFT, SPIBSC_SMENR_ADB);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ---- Option Data ---- */
|
||||||
|
/* Enable/Disable */
|
||||||
|
RegWwrite_32(&SPIBSC->SMENR, regset->opde, SPIBSC_SMENR_OPDE_SHIFT, SPIBSC_SMENR_OPDE);
|
||||||
|
if (regset->opde != SPIBSC_OUTPUT_DISABLE) {
|
||||||
|
/* Option Data */
|
||||||
|
RegWwrite_32(&SPIBSC->SMOPR, regset->opd[0], SPIBSC_SMOPR_OPD3_SHIFT, SPIBSC_SMOPR_OPD3);
|
||||||
|
RegWwrite_32(&SPIBSC->SMOPR, regset->opd[1], SPIBSC_SMOPR_OPD2_SHIFT, SPIBSC_SMOPR_OPD2);
|
||||||
|
RegWwrite_32(&SPIBSC->SMOPR, regset->opd[2], SPIBSC_SMOPR_OPD1_SHIFT, SPIBSC_SMOPR_OPD1);
|
||||||
|
RegWwrite_32(&SPIBSC->SMOPR, regset->opd[3], SPIBSC_SMOPR_OPD0_SHIFT, SPIBSC_SMOPR_OPD0);
|
||||||
|
/* Single/Dual/Quad */
|
||||||
|
RegWwrite_32(&SPIBSC->SMENR, regset->opdb, SPIBSC_SMENR_OPDB_SHIFT, SPIBSC_SMENR_OPDB);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ---- Dummy ---- */
|
||||||
|
/* Enable/Disable */
|
||||||
|
RegWwrite_32(&SPIBSC->SMENR, regset->dme, SPIBSC_SMENR_DME_SHIFT, SPIBSC_SMENR_DME);
|
||||||
|
if (regset->dme != SPIBSC_DUMMY_CYC_DISABLE) {
|
||||||
|
RegWwrite_32(&SPIBSC->SMDMCR, regset->dmdb, SPIBSC_SMDMCR_DMDB_SHIFT, SPIBSC_SMDMCR_DMDB);
|
||||||
|
/* Dummy Cycle */
|
||||||
|
RegWwrite_32(&SPIBSC->SMDMCR, regset->dmcyc, SPIBSC_SMDMCR_DMCYC_SHIFT, SPIBSC_SMDMCR_DMCYC);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ---- Data ---- */
|
||||||
|
/* Enable/Disable */
|
||||||
|
RegWwrite_32(&SPIBSC->SMENR, regset->spide, SPIBSC_SMENR_SPIDE_SHIFT, SPIBSC_SMENR_SPIDE);
|
||||||
|
if (regset->spide != SPIBSC_OUTPUT_DISABLE) {
|
||||||
|
if (SPIBSC_OUTPUT_SPID_8 == regset->spide) {
|
||||||
|
if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
|
||||||
|
SPIBSC->SMWDR0.UINT8[0] = (uint8_t)(regset->smwdr[0]);
|
||||||
|
} else {
|
||||||
|
SPIBSC->SMWDR0.UINT16[0] = (uint16_t)(regset->smwdr[0]);
|
||||||
|
}
|
||||||
|
} else if (regset->spide == SPIBSC_OUTPUT_SPID_16) {
|
||||||
|
if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
|
||||||
|
SPIBSC->SMWDR0.UINT16[0] = (uint16_t)(regset->smwdr[0]);
|
||||||
|
} else {
|
||||||
|
SPIBSC->SMWDR0.UINT32 = regset->smwdr[0];
|
||||||
|
}
|
||||||
|
} else if (regset->spide == SPIBSC_OUTPUT_SPID_32) {
|
||||||
|
if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
|
||||||
|
SPIBSC->SMWDR0.UINT32 = (uint32_t)(regset->smwdr[0]);
|
||||||
|
} else {
|
||||||
|
SPIBSC->SMWDR0.UINT32 = (uint32_t)(regset->smwdr[0]);
|
||||||
|
SPIBSC->SMWDR1.UINT32 = (uint32_t)(regset->smwdr[1]); /* valid in two serial-flash */
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
/* none */
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Single/Dual/Quad */
|
||||||
|
RegWwrite_32(&SPIBSC->SMENR, regset->spidb, SPIBSC_SMENR_SPIDB_SHIFT, SPIBSC_SMENR_SPIDB);
|
||||||
|
}
|
||||||
|
|
||||||
|
RegWwrite_32(&SPIBSC->SMCR, regset->sslkp, SPIBSC_SMCR_SSLKP_SHIFT, SPIBSC_SMCR_SSLKP);
|
||||||
|
|
||||||
|
if ((regset->spidb != SPIBSC_1BIT) && (regset->spide != SPIBSC_OUTPUT_DISABLE)) {
|
||||||
|
if ((regset->spire == SPIBSC_SPIDATA_ENABLE) && (regset->spiwe == SPIBSC_SPIDATA_ENABLE)) {
|
||||||
|
/* not set in same time */
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
RegWwrite_32(&SPIBSC->SMCR, regset->spire, SPIBSC_SMCR_SPIRE_SHIFT, SPIBSC_SMCR_SPIRE);
|
||||||
|
RegWwrite_32(&SPIBSC->SMCR, regset->spiwe, SPIBSC_SMCR_SPIWE_SHIFT, SPIBSC_SMCR_SPIWE);
|
||||||
|
|
||||||
|
/* SDR Transmission/DDR Transmission Setting */
|
||||||
|
RegWwrite_32(&SPIBSC->SMDRENR, regset->addre, SPIBSC_SMDRENR_ADDRE_SHIFT, SPIBSC_SMDRENR_ADDRE);
|
||||||
|
RegWwrite_32(&SPIBSC->SMDRENR, regset->opdre, SPIBSC_SMDRENR_OPDRE_SHIFT, SPIBSC_SMDRENR_OPDRE);
|
||||||
|
RegWwrite_32(&SPIBSC->SMDRENR, regset->spidre, SPIBSC_SMDRENR_SPIDRE_SHIFT, SPIBSC_SMDRENR_SPIDRE);
|
||||||
|
|
||||||
|
/* execute after setting SPNDL bit */
|
||||||
|
RegWwrite_32(&SPIBSC->SMCR, SPIBSC_SPI_ENABLE, SPIBSC_SMCR_SPIE_SHIFT, SPIBSC_SMCR_SPIE);
|
||||||
|
|
||||||
|
/* wait for transfer-start */
|
||||||
|
while (RegRead_32(&SPIBSC->CMNSR, SPIBSC_CMNSR_TEND_SHIFT, SPIBSC_CMNSR_TEND) != SPIBSC_TRANS_END) {
|
||||||
|
/* wait for transfer-end */
|
||||||
|
}
|
||||||
|
|
||||||
|
if (SPIBSC_OUTPUT_SPID_8 == regset->spide) {
|
||||||
|
if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
|
||||||
|
regset->smrdr[0] = SPIBSC->SMRDR0.UINT8[0];
|
||||||
|
} else {
|
||||||
|
regset->smrdr[0] = SPIBSC->SMRDR0.UINT16[0]; /* valid in two serial-flash */
|
||||||
|
}
|
||||||
|
} else if (regset->spide == SPIBSC_OUTPUT_SPID_16) {
|
||||||
|
if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
|
||||||
|
regset->smrdr[0] = SPIBSC->SMRDR0.UINT16[0];
|
||||||
|
} else {
|
||||||
|
regset->smrdr[0] = SPIBSC->SMRDR0.UINT32; /* valid in two serial-flash */
|
||||||
|
}
|
||||||
|
} else if (regset->spide == SPIBSC_OUTPUT_SPID_32) {
|
||||||
|
if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
|
||||||
|
regset->smrdr[0] = SPIBSC->SMRDR0.UINT32;
|
||||||
|
} else {
|
||||||
|
regset->smrdr[0] = SPIBSC->SMRDR0.UINT32; /* valid in two serial-flash */
|
||||||
|
regset->smrdr[1] = SPIBSC->SMRDR1.UINT32;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
/* none */
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint32_t RegRead_32(volatile uint32_t * ioreg, uint32_t shift, uint32_t mask)
|
||||||
|
{
|
||||||
|
uint32_t reg_value;
|
||||||
|
|
||||||
|
reg_value = *ioreg; /* Read from register */
|
||||||
|
reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */
|
||||||
|
|
||||||
|
return reg_value;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void RegWwrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask)
|
||||||
|
{
|
||||||
|
uint32_t reg_value;
|
||||||
|
|
||||||
|
reg_value = *ioreg; /* Read from register */
|
||||||
|
reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */
|
||||||
|
*ioreg = reg_value; /* Write to register */
|
||||||
|
}
|
||||||
|
|
||||||
|
static void change_mmu_ttbl_spibsc(uint32_t type)
|
||||||
|
{
|
||||||
|
uint32_t index; /* Loop variable: table index */
|
||||||
|
mmu_ttbl_desc_section_t desc; /* Loop variable: descriptor */
|
||||||
|
mmu_ttbl_desc_section_t * table = (mmu_ttbl_desc_section_t *)TTB;
|
||||||
|
|
||||||
|
/* ==== Modify SPI Multi-I/O bus space settings in the MMU translation table ==== */
|
||||||
|
for (index = (SPIBSC_ADDR_START >> 20); index <= (SPIBSC_ADDR_END >> 20); index++) {
|
||||||
|
/* Modify memory attribute descriptor */
|
||||||
|
if (type == 0) { /* Spi */
|
||||||
|
desc = table[index];
|
||||||
|
desc_tbl[index - (SPIBSC_ADDR_START >> 20)] = desc;
|
||||||
|
desc.AP1_0 = 0x0u; /* AP[2:0] = b'000 (No access) */
|
||||||
|
desc.AP2 = 0x0u;
|
||||||
|
desc.XN = 0x1u; /* XN = 1 (Execute never) */
|
||||||
|
} else { /* Xip */
|
||||||
|
desc = desc_tbl[index - (SPIBSC_ADDR_START >> 20)];
|
||||||
|
}
|
||||||
|
/* Write descriptor back to translation table */
|
||||||
|
table[index] = desc;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void spibsc_stop(void)
|
||||||
|
{
|
||||||
|
if (((SPIBSC->DRCR & SPIBSC_DRCR_RBE) != 0) &&
|
||||||
|
((SPIBSC->DRCR & SPIBSC_DRCR_SSLE) != 0)) {
|
||||||
|
RegWwrite_32(&SPIBSC->DRCR, 1, SPIBSC_DRCR_SSLN_SHIFT, SPIBSC_DRCR_SSLN);
|
||||||
|
}
|
||||||
|
|
||||||
|
while (RegRead_32(&SPIBSC->CMNSR, SPIBSC_CMNSR_SSLF_SHIFT, SPIBSC_CMNSR_SSLF) != SPIBSC_SSL_NEGATE) {
|
||||||
|
;
|
||||||
|
}
|
||||||
|
|
||||||
|
while (RegRead_32(&SPIBSC->CMNSR, SPIBSC_CMNSR_TEND_SHIFT, SPIBSC_CMNSR_TEND) != SPIBSC_TRANS_END) {
|
||||||
|
;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void cache_control(void)
|
||||||
|
{
|
||||||
|
unsigned int assoc;
|
||||||
|
|
||||||
|
/* ==== Cleaning and invalidation of the L1 data cache ==== */
|
||||||
|
L1C_CleanInvalidateDCacheAll();
|
||||||
|
__DSB();
|
||||||
|
|
||||||
|
/* ==== Cleaning and invalidation of the L2 cache ==== */
|
||||||
|
if (L2C_310->AUX_CNT & (1U << 16U)) {
|
||||||
|
assoc = 16U;
|
||||||
|
} else {
|
||||||
|
assoc = 8U;
|
||||||
|
}
|
||||||
|
L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U;
|
||||||
|
while (L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); // poll invalidate
|
||||||
|
L2C_310->CACHE_SYNC = 0x0;
|
||||||
|
|
||||||
|
/* ==== Invalidate all TLB entries ==== */
|
||||||
|
__set_TLBIALL(0);
|
||||||
|
__DSB(); // ensure completion of the invalidation
|
||||||
|
__ISB(); // ensure instruction fetch path sees new state
|
||||||
|
|
||||||
|
/* ==== Invalidate the L1 instruction cache ==== */
|
||||||
|
__set_ICIALLU(0);
|
||||||
|
__DSB(); // ensure completion of the invalidation
|
||||||
|
__ISB(); // ensure instruction fetch path sees new I cache state
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -81,6 +81,10 @@ struct trng_s {
|
||||||
uint8_t dummy;
|
uint8_t dummy;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
struct flash_s {
|
||||||
|
uint8_t dummy;
|
||||||
|
};
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,154 @@
|
||||||
|
/*******************************************************************************
|
||||||
|
* DISCLAIMER
|
||||||
|
* This software is supplied by Renesas Electronics Corporation and is only
|
||||||
|
* intended for use with Renesas products. No other uses are authorized. This
|
||||||
|
* software is owned by Renesas Electronics Corporation and is protected under
|
||||||
|
* all applicable laws, including copyright laws.
|
||||||
|
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||||
|
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||||
|
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||||
|
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||||
|
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||||
|
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||||
|
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||||
|
* Renesas reserves the right, without notice, to make changes to this software
|
||||||
|
* and to discontinue the availability of this software. By using this software,
|
||||||
|
* you agree to the additional terms and conditions found by accessing the
|
||||||
|
* following link:
|
||||||
|
* http://www.renesas.com/disclaimer
|
||||||
|
*
|
||||||
|
* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
|
||||||
|
*******************************************************************************/
|
||||||
|
/******************************************************************************
|
||||||
|
* File Name : spibsc.h
|
||||||
|
* $Rev: 12 $
|
||||||
|
* $Date:: 2016-05-19 17:26:37 +0900#$
|
||||||
|
* Description :
|
||||||
|
******************************************************************************/
|
||||||
|
#ifndef _SPIBSC_H_
|
||||||
|
#define _SPIBSC_H_
|
||||||
|
|
||||||
|
/******************************************************************************
|
||||||
|
Includes <System Includes> , "Project Includes"
|
||||||
|
******************************************************************************/
|
||||||
|
#include "iodefine.h"
|
||||||
|
|
||||||
|
/******************************************************************************
|
||||||
|
Macro definitions
|
||||||
|
******************************************************************************/
|
||||||
|
#define SPIBSC_CMNCR_MD_EXTRD (0u)
|
||||||
|
#define SPIBSC_CMNCR_MD_SPI (1u)
|
||||||
|
|
||||||
|
#define SPIBSC_OUTPUT_LOW (0u)
|
||||||
|
#define SPIBSC_OUTPUT_HIGH (1u)
|
||||||
|
#define SPIBSC_OUTPUT_LAST (2u)
|
||||||
|
#define SPIBSC_OUTPUT_HiZ (3u)
|
||||||
|
|
||||||
|
#define SPIBSC_CMNCR_CPHAT_EVEN (0u)
|
||||||
|
#define SPIBSC_CMNCR_CPHAT_ODD (1u)
|
||||||
|
|
||||||
|
#define SPIBSC_CMNCR_CPHAR_ODD (0u)
|
||||||
|
#define SPIBSC_CMNCR_CPHAR_EVEN (1u)
|
||||||
|
|
||||||
|
#define SPIBSC_CMNCR_SSLP_LOW (0u)
|
||||||
|
#define SPIBSC_CMNCR_SSLP_HIGH (1u)
|
||||||
|
|
||||||
|
#define SPIBSC_CMNCR_CPOL_LOW (0u)
|
||||||
|
#define SPIBSC_CMNCR_CPOL_HIGH (1u)
|
||||||
|
|
||||||
|
#define SPIBSC_CMNCR_BSZ_SINGLE (0u)
|
||||||
|
#define SPIBSC_CMNCR_BSZ_DUAL (1u)
|
||||||
|
|
||||||
|
#define SPIBSC_DELAY_1SPBCLK (0u)
|
||||||
|
#define SPIBSC_DELAY_2SPBCLK (1u)
|
||||||
|
#define SPIBSC_DELAY_3SPBCLK (2u)
|
||||||
|
#define SPIBSC_DELAY_4SPBCLK (3u)
|
||||||
|
#define SPIBSC_DELAY_5SPBCLK (4u)
|
||||||
|
#define SPIBSC_DELAY_6SPBCLK (5u)
|
||||||
|
#define SPIBSC_DELAY_7SPBCLK (6u)
|
||||||
|
#define SPIBSC_DELAY_8SPBCLK (7u)
|
||||||
|
|
||||||
|
|
||||||
|
#define SPIBSC_BURST_1 (0x00u)
|
||||||
|
#define SPIBSC_BURST_2 (0x01u)
|
||||||
|
#define SPIBSC_BURST_3 (0x02u)
|
||||||
|
#define SPIBSC_BURST_4 (0x03u)
|
||||||
|
#define SPIBSC_BURST_5 (0x04u)
|
||||||
|
#define SPIBSC_BURST_6 (0x05u)
|
||||||
|
#define SPIBSC_BURST_7 (0x06u)
|
||||||
|
#define SPIBSC_BURST_8 (0x07u)
|
||||||
|
#define SPIBSC_BURST_9 (0x08u)
|
||||||
|
#define SPIBSC_BURST_10 (0x09u)
|
||||||
|
#define SPIBSC_BURST_11 (0x0au)
|
||||||
|
#define SPIBSC_BURST_12 (0x0bu)
|
||||||
|
#define SPIBSC_BURST_13 (0x0cu)
|
||||||
|
#define SPIBSC_BURST_14 (0x0du)
|
||||||
|
#define SPIBSC_BURST_15 (0x0eu)
|
||||||
|
#define SPIBSC_BURST_16 (0x0fu)
|
||||||
|
|
||||||
|
#define SPIBSC_BURST_DISABLE (0u)
|
||||||
|
#define SPIBSC_BURST_ENABLE (1u)
|
||||||
|
|
||||||
|
#define SPIBSC_DRCR_RCF_EXE (1u)
|
||||||
|
|
||||||
|
#define SPIBSC_SSL_NEGATE (0u)
|
||||||
|
#define SPIBSC_TRANS_END (1u)
|
||||||
|
|
||||||
|
#define SPIBSC_1BIT (0u)
|
||||||
|
#define SPIBSC_2BIT (1u)
|
||||||
|
#define SPIBSC_4BIT (2u)
|
||||||
|
|
||||||
|
#define SPIBSC_OUTPUT_DISABLE (0u)
|
||||||
|
#define SPIBSC_OUTPUT_ENABLE (1u)
|
||||||
|
#define SPIBSC_OUTPUT_ADDR_24 (0x07u)
|
||||||
|
#define SPIBSC_OUTPUT_ADDR_32 (0x0fu)
|
||||||
|
#define SPIBSC_OUTPUT_OPD_3 (0x08u)
|
||||||
|
#define SPIBSC_OUTPUT_OPD_32 (0x0cu)
|
||||||
|
#define SPIBSC_OUTPUT_OPD_321 (0x0eu)
|
||||||
|
#define SPIBSC_OUTPUT_OPD_3210 (0x0fu)
|
||||||
|
|
||||||
|
#define SPIBSC_OUTPUT_SPID_8 (0x08u)
|
||||||
|
#define SPIBSC_OUTPUT_SPID_16 (0x0cu)
|
||||||
|
#define SPIBSC_OUTPUT_SPID_32 (0x0fu)
|
||||||
|
|
||||||
|
#define SPIBSC_SPISSL_NEGATE (0u)
|
||||||
|
#define SPIBSC_SPISSL_KEEP (1u)
|
||||||
|
|
||||||
|
#define SPIBSC_SPIDATA_DISABLE (0u)
|
||||||
|
#define SPIBSC_SPIDATA_ENABLE (1u)
|
||||||
|
|
||||||
|
#define SPIBSC_SPI_DISABLE (0u)
|
||||||
|
#define SPIBSC_SPI_ENABLE (1u)
|
||||||
|
|
||||||
|
|
||||||
|
/* Use for setting of the DME bit of "data read enable register"(DRENR) */
|
||||||
|
#define SPIBSC_DUMMY_CYC_DISABLE (0u)
|
||||||
|
#define SPIBSC_DUMMY_CYC_ENABLE (1u)
|
||||||
|
|
||||||
|
/* Use for setting of the DMCYC [2:0] bit of "data read dummy cycle register"(DRDMCR) */
|
||||||
|
#define SPIBSC_DUMMY_1CYC (0u)
|
||||||
|
#define SPIBSC_DUMMY_2CYC (1u)
|
||||||
|
#define SPIBSC_DUMMY_3CYC (2u)
|
||||||
|
#define SPIBSC_DUMMY_4CYC (3u)
|
||||||
|
#define SPIBSC_DUMMY_5CYC (4u)
|
||||||
|
#define SPIBSC_DUMMY_6CYC (5u)
|
||||||
|
#define SPIBSC_DUMMY_7CYC (6u)
|
||||||
|
#define SPIBSC_DUMMY_8CYC (7u)
|
||||||
|
|
||||||
|
/* Use for setting of "data read DDR enable register"(DRDRENR) */
|
||||||
|
#define SPIBSC_SDR_TRANS (0u)
|
||||||
|
#define SPIBSC_DDR_TRANS (1u)
|
||||||
|
|
||||||
|
/* Use for setting the CKDLY regsiter */
|
||||||
|
#define SPIBSC_CKDLY_DEFAULT (0x0000A504uL) /* Initial value */
|
||||||
|
#define SPIBSC_CKDLY_TUNING (0x0000A50AuL) /* Shorten the data input setup time and extend the data hold time */
|
||||||
|
|
||||||
|
/* Use for setting the SPODLY regsiter */
|
||||||
|
#define SPIBSC_SPODLY_DEFAULT (0xA5000000uL) /* Initial value */
|
||||||
|
#define SPIBSC_SPODLY_TUNING (0xA5001111uL) /* Delay the data output delay/hold/buffer-on/buffer-off time */
|
||||||
|
|
||||||
|
#endif /* _SPIBSC_H_ */
|
||||||
|
|
||||||
|
/* End of File */
|
||||||
|
|
@ -2844,7 +2844,7 @@
|
||||||
"inherits": ["RZ_A1XX"],
|
"inherits": ["RZ_A1XX"],
|
||||||
"supported_form_factors": ["ARDUINO"],
|
"supported_form_factors": ["ARDUINO"],
|
||||||
"extra_labels_add": ["RZA1H", "MBRZA1H", "RZ_A1_EMAC"],
|
"extra_labels_add": ["RZA1H", "MBRZA1H", "RZ_A1_EMAC"],
|
||||||
"device_has_add": ["EMAC"],
|
"device_has_add": ["EMAC", "FLASH"],
|
||||||
"release_versions": ["2", "5"]
|
"release_versions": ["2", "5"]
|
||||||
},
|
},
|
||||||
"VK_RZ_A1H": {
|
"VK_RZ_A1H": {
|
||||||
|
|
@ -2857,7 +2857,7 @@
|
||||||
"inherits": ["RZ_A1XX"],
|
"inherits": ["RZ_A1XX"],
|
||||||
"supported_form_factors": ["ARDUINO"],
|
"supported_form_factors": ["ARDUINO"],
|
||||||
"extra_labels_add": ["RZA1UL", "MBRZA1LU"],
|
"extra_labels_add": ["RZA1UL", "MBRZA1LU"],
|
||||||
"device_has_add": ["TRNG"],
|
"device_has_add": ["TRNG", "FLASH"],
|
||||||
"device_has_remove": ["ETHERNET"],
|
"device_has_remove": ["ETHERNET"],
|
||||||
"features_remove": ["LWIP"],
|
"features_remove": ["LWIP"],
|
||||||
"release_versions": ["2", "5"],
|
"release_versions": ["2", "5"],
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue