diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c index 4795a9c4d2..890c0e7842 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c @@ -258,8 +258,8 @@ const PinMap PinMap_UART_TX[] = { {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // ARDUINO D1 - {PG_7, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PG_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX + {PG_7, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX + {PG_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h index 741cd43383..e51ea37f50 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h @@ -266,6 +266,15 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_NOE_ALT = PA_13, + USB_OTG_FS_SOF_ALT = PA_14, + USB_OTG_FS_NOE = PC_9, + // Not connected NC = (int)0xFFFFFFFF } PinName; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c index e80f723dde..e8d5be0049 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c @@ -190,10 +190,10 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { return 0; // FAIL } @@ -217,6 +217,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update HAL_RCC_OscConfig(&RCC_OscInitStruct); + /* Select HSI as clock source for LPUART1 */ + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 2 if (bypass == 0) @@ -289,6 +296,13 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update HAL_RCC_OscConfig(&RCC_OscInitStruct); + /* Select HSI as clock source for LPUART1 */ + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 3 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz @@ -322,7 +336,6 @@ uint8_t SetSysClock_PLL_MSI(void) RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.HSEState = RCC_HSE_OFF; RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; @@ -342,11 +355,6 @@ uint8_t SetSysClock_PLL_MSI(void) PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - /* Select LSE as clock source for LPUART1 */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ @@ -357,6 +365,13 @@ uint8_t SetSysClock_PLL_MSI(void) return 0; // FAIL } + /* Select LSE as clock source for LPUART1 */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + return 0; // FAIL + } + // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 4 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz diff --git a/targets/targets.json b/targets/targets.json index dbfaa724fa..97ad2d6562 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3396,6 +3396,10 @@ "release_versions": ["2", "5"], "device_name": "STM32L496ZG" }, + "NUCLEO_L496ZG_P": { + "inherits": ["NUCLEO_L496ZG"], + "detect_code": ["0828"] + }, "VBLUNO52": { "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF52"], diff --git a/tools/export/sw4stm32/__init__.py b/tools/export/sw4stm32/__init__.py index ce15e09657..9d55dae8fe 100644 --- a/tools/export/sw4stm32/__init__.py +++ b/tools/export/sw4stm32/__init__.py @@ -259,6 +259,11 @@ class Sw4STM32(GNUARMEclipse): 'name': 'NUCLEO-L496ZG', 'mcuId': 'STM32L496ZGTx' }, + 'NUCLEO_L496ZG_P': + { + 'name': 'NUCLEO-L496ZG', + 'mcuId': 'STM32L496ZGTx' + }, } TARGETS = BOARDS.keys()