From 16a40c9f9c3883ba1cbdb775d22c1884911dfc63 Mon Sep 17 00:00:00 2001
From: MarceloSalazar <Marcelo.Salazar@arm.com>
Date: Tue, 21 Apr 2020 09:21:10 +0100
Subject: [PATCH] Remove LPC4337 target
---
targets/TARGET_NXP/TARGET_LPC43XX/PortNames.h | 37 -
targets/TARGET_NXP/TARGET_LPC43XX/README.txt | 81 -
.../TARGET_LPC4337/PeripheralNames.h | 152 --
.../TARGET_LPC43XX/TARGET_LPC4337/PinNames.h | 542 -----
.../TARGET_LPC43XX/TARGET_LPC4337/device.h | 40 -
.../TARGET_NXP/TARGET_LPC43XX/analogin_api.c | 169 --
.../TARGET_NXP/TARGET_LPC43XX/analogout_api.c | 91 -
.../TARGET_LPC43XX/device/LPC43xx.h | 2113 -----------------
.../TOOLCHAIN_ARM_STD/LPC43xx_spifi.ini | 12 -
.../TARGET_LPC4337/LPC4337.sct | 32 -
.../TARGET_LPC4337/startup_LPC4337.S | 288 ---
.../device/TOOLCHAIN_IAR/LPC43xx.icf | 39 -
.../device/TOOLCHAIN_IAR/startup_LPC43xx.S | 292 ---
.../TARGET_NXP/TARGET_LPC43XX/device/cmsis.h | 15 -
.../TARGET_LPC43XX/device/cmsis_nvic.h | 37 -
.../TARGET_LPC43XX/device/system_LPC43xx.c | 373 ---
.../TARGET_LPC43XX/device/system_LPC43xx.h | 90 -
targets/TARGET_NXP/TARGET_LPC43XX/gpio_api.c | 63 -
.../TARGET_NXP/TARGET_LPC43XX/gpio_irq_api.c | 154 --
.../TARGET_NXP/TARGET_LPC43XX/gpio_object.h | 56 -
targets/TARGET_NXP/TARGET_LPC43XX/i2c_api.c | 426 ----
targets/TARGET_NXP/TARGET_LPC43XX/objects.h | 79 -
targets/TARGET_NXP/TARGET_LPC43XX/pinmap.c | 42 -
targets/TARGET_NXP/TARGET_LPC43XX/port_api.c | 146 --
.../TARGET_NXP/TARGET_LPC43XX/pwmout_api.c | 276 ---
targets/TARGET_NXP/TARGET_LPC43XX/rtc_api.c | 135 --
.../TARGET_NXP/TARGET_LPC43XX/serial_api.c | 433 ----
targets/TARGET_NXP/TARGET_LPC43XX/sleep.c | 36 -
targets/TARGET_NXP/TARGET_LPC43XX/spi_api.c | 269 ---
targets/TARGET_NXP/TARGET_LPC43XX/us_ticker.c | 74 -
targets/TARGET_NXP/mbed_rtx.h | 6 -
targets/targets.json | 40 -
32 files changed, 6638 deletions(-)
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/PortNames.h
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/README.txt
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4337/PeripheralNames.h
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4337/PinNames.h
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4337/device.h
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/analogin_api.c
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/analogout_api.c
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/device/LPC43xx.h
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_ARM_STD/LPC43xx_spifi.ini
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_ARM_STD/TARGET_LPC4337/LPC4337.sct
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_ARM_STD/TARGET_LPC4337/startup_LPC4337.S
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_IAR/LPC43xx.icf
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_IAR/startup_LPC43xx.S
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/device/cmsis.h
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/device/cmsis_nvic.h
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/device/system_LPC43xx.c
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/device/system_LPC43xx.h
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/gpio_api.c
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/gpio_irq_api.c
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/gpio_object.h
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/i2c_api.c
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/objects.h
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/pinmap.c
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/port_api.c
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/pwmout_api.c
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/rtc_api.c
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/serial_api.c
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/sleep.c
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/spi_api.c
delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/us_ticker.c
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/PortNames.h b/targets/TARGET_NXP/TARGET_LPC43XX/PortNames.h
deleted file mode 100644
index 1c2413c94d..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/PortNames.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- Port0 = 0,
- Port1 = 1,
- Port2 = 2,
- Port3 = 3,
- Port4 = 4,
- Port5 = 5,
- Port6 = 6,
- Port7 = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/README.txt b/targets/TARGET_NXP/TARGET_LPC43XX/README.txt
deleted file mode 100644
index 18281032a6..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/README.txt
+++ /dev/null
@@ -1,81 +0,0 @@
-mbed port to NXP LPC43xx
-========================
-Updated: 07/11/14
-
-The NXP LPC43xx microcontrollers includes multiple Cortex-M cores in a single
-microcontroller package. This port allows mbed developers to take advantage
-of the LPC43xx in their application using APIs that they are familiar with.
-Some of the key features of the LPC43xx include:
-
-* Dual core ARM Cortex-M4/M0 both capable of up to 204 MHz
-* Up to 264 KB SRAM, 1 MB internal flash
-* Two High-speed USB 2.0 interfaces
-* Ethernet MAC
-* LCD interface
-* Quad-SPI Flash Interface (SPIFI)
-* State Configurable Timer (SCT)
-* Serial GPIO (SGPIO)
-* Up to 164 GPIO
-
-The NXP LPC18xx is a single core Cortex-M3 implementation that is compatible
-with the LPC43XX for cost-sensitive applications not requiring multiple cores.
-
-mbed port to the LPC43XX - Micromint USA <support@micromint.com>
-
-Compatibility
--------------
-* This port has been tested with the following boards:
- Board MCU RAM/Flash
- Micromint Bambino 200 LPC4330 264K SRAM/4 MB SPIFI flash
- Micromint Bambino 200E LPC4330 264K SRAM/8 MB SPIFI flash
- Micromint Bambino 210 LPC4330 264K SRAM/4 MB SPIFI flash
- Micromint Bambino 210E LPC4330 264K SRAM/8 MB SPIFI flash
-
-* CMSIS-DAP debugging is implemented with the Micromint Bambino 210/210E.
- To debug other LPC4330 targets, use a JTAG. The NXP DFU tool can be used
- for flash programming.
-
-* This port should support NXP LPC43XX and LPC18XX variants with a single
- codebase. The core declaration specifies the binaries to be built:
- mbed define CMSIS define MCU Target
- __CORTEX_M4 CORE_M4 LPC43xx Cortex-M4
- __CORTEX_M0 CORE_M0 LPC43xx Cortex-M0
- __CORTEX_M3 CORE_M3 LPC18xx Cortex-M3
- These MCUs all share the peripheral IP, common driver code is feasible.
- Yet each variant can have different memory segments, peripherals, etc.
- Plus, each board design can integrate different external peripherals
- or interfaces. A future release of the mbed SDK and its build tools will
- support specifying the target board when building binaries. At this time
- building binaries for different targets requires an external project or
- Makefile.
-
-* No testing has been done with LPC18xx hardware.
-
-Notes
------
-* On the LPC43xx the hardware pin name and the GPIO pin name are not the same,
- requiring different offsets for the SCU and GPIO registers. To simplify logic
- the pin identifier encodes the offsets. Macros are used for decoding.
- For example, P6_11 corresponds to GPIO3[7] and is encoded/decoded as follows:
-
- P6_11 = MBED_PIN(0x06, 11, 3, 7) = 0x032C0067
-
- MBED_SCU_REG(P6_11) = 0x4008632C MBED_GPIO_PORT(P6_11) = 3
- MBED_GPIO_REG(P6_11) = 0x400F4000 MBED_GPIO_PIN(P6_11) = 7
-
-* Pin names use multiple aliases to support Arduino naming conventions as well
- as others. For example, to use pin p21 on the Bambino 210 from mbed applications
- the following aliases are equivalent: p21, D0, UART0_TX, COM1_TX, P6_4.
- See the board pinout graphic and the PinNames.h for available aliases.
-
-* The LPC43xx implements GPIO pin and group interrupts. Any pin in the 8 32-bit
- GPIO ports can interrupt (LPC4350 supports up to 164). On group interrupts a
- pin can only interrupt on the rising or falling edge, not both as required
- by the mbed InterruptIn class. Also, group interrupts can't be cleared
- individually. This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
- A future implementation may provide group interrupt support.
-
-* The LPC3xx PWM driver uses the State Configurable Timer (SCT). The default
- build (PWM_MODE=0) uses the unified 32-bit times. Applications that use PWM
- and require other SCT uses can use the dual 16-bit mode by changing PWM_MODE
- when building the library.
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4337/PeripheralNames.h b/targets/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4337/PeripheralNames.h
deleted file mode 100644
index 75466344c2..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4337/PeripheralNames.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- UART_0 = (int)LPC_USART0_BASE,
- UART_1 = (int)LPC_UART1_BASE,
- UART_2 = (int)LPC_USART2_BASE,
- UART_3 = (int)LPC_USART3_BASE
-} UARTName;
-
-typedef enum {
- ADC0_0 = 0,
- ADC0_1,
- ADC0_2,
- ADC0_3,
- ADC0_4,
- ADC0_5,
- ADC0_6,
- ADC0_7,
- ADC1_0,
- ADC1_1,
- ADC1_2,
- ADC1_3,
- ADC1_4,
- ADC1_5,
- ADC1_6,
- ADC1_7,
- ADC_pin0_0,
- ADC_pin0_1,
- ADC_pin0_2,
- ADC_pin0_3,
- ADC_pin0_4,
- ADC_pin0_5,
- ADC_pin0_6,
- ADC_pin0_7,
- ADC_pin1_0,
- ADC_pin1_1,
- ADC_pin1_2,
- ADC_pin1_3,
- ADC_pin1_4,
- ADC_pin1_5,
- ADC_pin1_6,
- ADC_pin1_7
-} ADCName;
-
-typedef enum {
- DAC_0 = 0
-} DACName;
-
-typedef enum {
- SPI_0 = (int)LPC_SSP0_BASE,
- SPI_1 = (int)LPC_SSP1_BASE
-} SPIName;
-
-typedef enum {
- I2C_0 = (int)LPC_I2C0_BASE,
- I2C_1 = (int)LPC_I2C1_BASE
-} I2CName;
-
-typedef enum {
- PWM_0,
- PWM_1,
- PWM_2,
- PWM_3,
- PWM_4,
- PWM_5,
- PWM_6,
- PWM_7,
- PWM_8,
- PWM_9,
- PWM_10,
- PWM_11,
- PWM_12,
- PWM_13,
- PWM_14,
- PWM_15
-} PWMName;
-
-typedef enum {
- CAN_0 = (int)LPC_C_CAN0_BASE,
- CAN_1 = (int)LPC_C_CAN1_BASE
-} CANName;
-
-#define STDIO_UART_TX USBTX
-#define STDIO_UART_RX USBRX
-#define STDIO_UART UART_0
-#define STDIO_BAUD 9600
-
-// Default peripherals
-#define MBED_SPI0 SPI0_MOSI, SPI0_MISO, SPI0_SCK, SPI0_SSEL
-#define MBED_SPI1 SPI1_MOSI, SPI1_MISO, SPI1_SCK, SPI1_SSEL
-
-#define MBED_UART0 UART0_TX, UART0_RX
-#define MBED_UART1 UART1_TX, UART1_RX
-#define MBED_UART2 UART2_TX, UART2_RX
-#define MBED_UART3 UART3_TX, UART3_RX
-#define MBED_UARTUSB USBTX, USBRX
-
-#define COM1 MBED_UART0
-#define COM2 MBED_UART1
-#define COM3 MBED_UART2
-#define COM4 MBED_UART3
-
-#define MBED_I2C0 I2C0_SDA, I2C0_SCL
-#define MBED_I2C1 I2C1_SDA, I2C1_SCL
-
-#define MBED_CAN0 p30, p29
-
-#define MBED_ANALOGOUT0 DAC0
-
-#define MBED_ANALOGIN0 ADC0
-#define MBED_ANALOGIN1 ADC1
-#define MBED_ANALOGIN2 ADC2
-#define MBED_ANALOGIN3 ADC3
-#define MBED_ANALOGIN4 ADC4
-#define MBED_ANALOGIN5 ADC5
-#define MBED_ANALOGIN6 ADC6
-#define MBED_ANALOGIN7 ADC7
-
-#define MBED_PWMOUT0 p26
-#define MBED_PWMOUT1 p25
-#define MBED_PWMOUT2 p24
-#define MBED_PWMOUT3 p23
-#define MBED_PWMOUT4 p22
-#define MBED_PWMOUT5 p21
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4337/PinNames.h b/targets/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4337/PinNames.h
deleted file mode 100644
index 7a58224d6e..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4337/PinNames.h
+++ /dev/null
@@ -1,542 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
-#define PORT_SHIFT 5
-#define NO_GPIO 15
-#define NO_PORT 0xFF
-
-// On the LPC43xx the MCU pin name and the GPIO pin name are not the same.
-// Encode SCU and GPIO offsets as a pin identifier
-#define MBED_PIN(group, num, port, pin) ((SCU_OFF(group,num) << 16) + GPIO_OFF(port,pin))
-
-// Decode pin identifier into register, port and pin values
-#define MBED_SCU_REG(MBED_PIN) (LPC_SCU_BASE + (MBED_PIN >> 16))
-#define MBED_GPIO_REG(MBED_PIN) (LPC_GPIO_PORT_BASE + 0x2000 + ((MBED_PIN >> (PORT_SHIFT - 2)) & 0x0000003C))
-#define MBED_GPIO_PORT(MBED_PIN) ((MBED_PIN >> PORT_SHIFT) & 0x0000000F)
-#define MBED_GPIO_PIN(MBED_PIN) (MBED_PIN & 0x0000001F)
-
-typedef enum {
- // LPC43xx Pin Names
- // All pins defined. Package determines which are available.
- // LBGA256 TFBGA180 TFBGA100 LQFP208 LQFP144
- // GPIO0 [15:0] [15:0] [15:6] [15:0] [15:0]
- // [4:0]
- // GPIO1 [15:0] [15:0] [15:0] [15:0] [15:0]
- // GPIO2 [15:0] [15:0] [15:0] [15:0]
- // GPIO3 [15:0] [15:0] [7] [15:0] [15:0]
- // [5:3]
- // [1:0]
- // GPIO4 [15:0] [15:0] [15:0] [11]
- // GPIO5 [26:0] [26:0] [11:0] [25:0] [18]
- // [16:0]
- // GPIO6 [30:0] [30:28] [30:20]
- // [26:25] [5:0]
- // GPIO7 [25:0] [4:0] [25:23]
- // [21:17]
- // --- --- --- --- ---
- // Total 164 117 49 131 83
-
- // Groups 0x00 - 0x0F : Digital pins
- // * Digital pins support up to 8 functions
- // Use func=0 for GPIO0-GPIO4, func=4 for GPIO5-GPIO7
- // * High-drive pins default to 4 mA but can support 8, 14, 20 mA
- P0_0 = MBED_PIN(0x00, 0, 0, 0), // GPIO0[0]
- P0_1 = MBED_PIN(0x00, 1, 0, 1), // GPIO0[1]
-
- P1_0 = MBED_PIN(0x01, 0, 0, 4), // GPIO0[4]
- P1_1 = MBED_PIN(0x01, 1, 0, 8), // GPIO0[8]
- P1_2 = MBED_PIN(0x01, 2, 0, 9), // GPIO0[9]
- P1_3 = MBED_PIN(0x01, 3, 0, 10), // GPIO0[10]
- P1_4 = MBED_PIN(0x01, 4, 0, 11), // GPIO0[11]
- P1_5 = MBED_PIN(0x01, 5, 1, 8), // GPIO1[8]
- P1_6 = MBED_PIN(0x01, 6, 1, 9), // GPIO1[9]
- P1_7 = MBED_PIN(0x01, 7, 1, 0), // GPIO1[0]
- P1_8 = MBED_PIN(0x01, 8, 1, 1), // GPIO1[1]
- P1_9 = MBED_PIN(0x01, 9, 1, 2), // GPIO1[2]
- P1_10 = MBED_PIN(0x01, 10, 1, 3), // GPIO1[3]
- P1_11 = MBED_PIN(0x01, 11, 1, 4), // GPIO1[4]
- P1_12 = MBED_PIN(0x01, 12, 1, 5), // GPIO1[5]
- P1_13 = MBED_PIN(0x01, 13, 1, 6), // GPIO1[6]
- P1_14 = MBED_PIN(0x01, 14, 1, 7), // GPIO1[7]
- P1_15 = MBED_PIN(0x01, 15, 0, 2), // GPIO0[2]
- P1_16 = MBED_PIN(0x01, 16, 0, 3), // GPIO0[3]
- P1_17 = MBED_PIN(0x01, 17, 0, 12), // GPIO0[12] high-drive
- P1_18 = MBED_PIN(0x01, 18, 0, 13), // GPIO0[13]
- P1_19 = MBED_PIN(0x01, 19, NO_GPIO, 0),
- P1_20 = MBED_PIN(0x01, 20, 0, 15), // GPIO0[15]
-
- P2_0 = MBED_PIN(0x02, 0, 5, 0), // GPIO5[0]
- P2_1 = MBED_PIN(0x02, 1, 5, 1), // GPIO5[1]
- P2_2 = MBED_PIN(0x02, 2, 5, 2), // GPIO5[2]
- P2_3 = MBED_PIN(0x02, 3, 5, 3), // GPIO5[3] high-drive
- P2_4 = MBED_PIN(0x02, 4, 5, 4), // GPIO5[4] high-drive
- P2_5 = MBED_PIN(0x02, 5, 5, 5), // GPIO5[5] high-drive
- P2_6 = MBED_PIN(0x02, 6, 5, 6), // GPIO5[6]
- P2_7 = MBED_PIN(0x02, 7, 0, 7), // GPIO0[7]
- P2_8 = MBED_PIN(0x02, 8, 5, 7), // GPIO5[7]
- P2_9 = MBED_PIN(0x02, 9, 1, 10), // GPIO1[10]
- P2_10 = MBED_PIN(0x02, 10, 0, 14), // GPIO0[14]
- P2_11 = MBED_PIN(0x02, 11, 1, 11), // GPIO1[11]
- P2_12 = MBED_PIN(0x02, 12, 1, 12), // GPIO1[12]
- P2_13 = MBED_PIN(0x02, 13, 1, 13), // GPIO1[13]
-
- P3_0 = MBED_PIN(0x03, 0, NO_GPIO, 0),
- P3_1 = MBED_PIN(0x03, 1, 5, 8), // GPIO5[8]
- P3_2 = MBED_PIN(0x03, 2, 5, 9), // GPIO5[9]
- P3_3 = MBED_PIN(0x03, 3, NO_GPIO, 0),
- P3_4 = MBED_PIN(0x03, 4, 1, 14), // GPIO1[14]
- P3_5 = MBED_PIN(0x03, 5, 1, 15), // GPIO1[15]
- P3_6 = MBED_PIN(0x03, 6, 0, 6), // GPIO0[6]
- P3_7 = MBED_PIN(0x03, 7, 5, 10), // GPIO5[10]
- P3_8 = MBED_PIN(0x03, 8, 5, 11), // GPIO5[11]
-
- P4_0 = MBED_PIN(0x04, 0, 2, 0), // GPIO2[0]
- P4_1 = MBED_PIN(0x04, 1, 2, 1), // GPIO2[1]
- P4_2 = MBED_PIN(0x04, 2, 2, 2), // GPIO2[2]
- P4_3 = MBED_PIN(0x04, 3, 2, 3), // GPIO2[3]
- P4_4 = MBED_PIN(0x04, 4, 2, 4), // GPIO2[4]
- P4_5 = MBED_PIN(0x04, 5, 2, 5), // GPIO2[5]
- P4_6 = MBED_PIN(0x04, 6, 2, 6), // GPIO2[6]
- P4_7 = MBED_PIN(0x04, 7, NO_GPIO, 0),
- P4_8 = MBED_PIN(0x04, 8, 5, 12), // GPIO5[12]
- P4_9 = MBED_PIN(0x04, 9, 5, 13), // GPIO5[13]
- P4_10 = MBED_PIN(0x04, 10, 5, 14), // GPIO5[14]
-
- P5_0 = MBED_PIN(0x05, 0, 2, 9), // GPIO2[9]
- P5_1 = MBED_PIN(0x05, 1, 2, 10), // GPIO2[10]
- P5_2 = MBED_PIN(0x05, 2, 2, 11), // GPIO2[11]
- P5_3 = MBED_PIN(0x05, 3, 2, 12), // GPIO2[12]
- P5_4 = MBED_PIN(0x05, 4, 2, 13), // GPIO2[13]
- P5_5 = MBED_PIN(0x05, 5, 2, 14), // GPIO2[14]
- P5_6 = MBED_PIN(0x05, 6, 2, 15), // GPIO2[15]
- P5_7 = MBED_PIN(0x05, 7, 2, 7), // GPIO2[7]
-
- P6_0 = MBED_PIN(0x06, 0, NO_GPIO, 0),
- P6_1 = MBED_PIN(0x06, 1, 3, 0), // GPIO3[0]
- P6_2 = MBED_PIN(0x06, 2, 3, 1), // GPIO3[1]
- P6_3 = MBED_PIN(0x06, 3, 3, 2), // GPIO3[2]
- P6_4 = MBED_PIN(0x06, 4, 3, 3), // GPIO3[3]
- P6_5 = MBED_PIN(0x06, 5, 3, 4), // GPIO3[4]
- P6_6 = MBED_PIN(0x06, 6, 0, 5), // GPIO0[5]
- P6_7 = MBED_PIN(0x06, 7, 5, 15), // GPIO5[15]
- P6_8 = MBED_PIN(0x06, 8, 5, 16), // GPIO5[16]
- P6_9 = MBED_PIN(0x06, 9, 3, 5), // GPIO3[5]
- P6_10 = MBED_PIN(0x06, 10, 3, 6), // GPIO3[6]
- P6_11 = MBED_PIN(0x06, 11, 3, 7), // GPIO3[7]
- P6_12 = MBED_PIN(0x06, 12, 2, 8), // GPIO2[8]
-
- P7_0 = MBED_PIN(0x07, 0, 3, 8), // GPIO3[8]
- P7_1 = MBED_PIN(0x07, 1, 3, 9), // GPIO3[9]
- P7_2 = MBED_PIN(0x07, 2, 3, 10), // GPIO3[10]
- P7_3 = MBED_PIN(0x07, 3, 3, 11), // GPIO3[11]
- P7_4 = MBED_PIN(0x07, 4, 3, 12), // GPIO3[12]
- P7_5 = MBED_PIN(0x07, 5, 3, 13), // GPIO3[13]
- P7_6 = MBED_PIN(0x07, 6, 3, 14), // GPIO3[14]
- P7_7 = MBED_PIN(0x07, 7, 3, 15), // GPIO3[15]
-
- P8_0 = MBED_PIN(0x08, 8, 4, 0), // GPIO4[0] high-drive
- P8_1 = MBED_PIN(0x09, 0, 4, 1), // GPIO4[1] high-drive
- P8_2 = MBED_PIN(0x09, 1, 4, 2), // GPIO4[2] high-drive
- P8_3 = MBED_PIN(0x09, 2, 4, 3), // GPIO4[3]
- P8_4 = MBED_PIN(0x08, 4, 4, 4), // GPIO4[4]
- P8_5 = MBED_PIN(0x08, 5, 4, 5), // GPIO4[5]
- P8_6 = MBED_PIN(0x08, 6, 4, 6), // GPIO4[6]
- P8_7 = MBED_PIN(0x08, 7, 4, 7), // GPIO4[7]
- P8_8 = MBED_PIN(0x08, 8, NO_GPIO, 0),
-
- P9_0 = MBED_PIN(0x09, 0, 4, 12), // GPIO4[12]
- P9_1 = MBED_PIN(0x09, 1, 4, 13), // GPIO4[13]
- P9_2 = MBED_PIN(0x09, 2, 4, 14), // GPIO4[14]
- P9_3 = MBED_PIN(0x09, 3, 4, 15), // GPIO4[15]
- P9_4 = MBED_PIN(0x09, 4, 5, 17), // GPIO5[17]
- P9_5 = MBED_PIN(0x09, 5, 5, 18), // GPIO5[18]
- P9_6 = MBED_PIN(0x09, 6, 4, 11), // GPIO4[11]
-
- PA_0 = MBED_PIN(0x0A, 0, NO_GPIO, 0),
- PA_1 = MBED_PIN(0x0A, 1, 4, 8), // GPIO4[8] high-drive
- PA_2 = MBED_PIN(0x0A, 2, 4, 9), // GPIO4[9] high-drive
- PA_3 = MBED_PIN(0x0A, 3, 4, 10), // GPIO4[10] high-drive
- PA_4 = MBED_PIN(0x0A, 4, 5, 19), // GPIO5[19]
-
- PB_0 = MBED_PIN(0x0B, 0, 5, 20), // GPIO5[20]
- PB_1 = MBED_PIN(0x0B, 1, 5, 21), // GPIO5[21]
- PB_2 = MBED_PIN(0x0B, 2, 5, 22), // GPIO5[22]
- PB_3 = MBED_PIN(0x0B, 3, 5, 23), // GPIO5[23]
- PB_4 = MBED_PIN(0x0B, 4, 5, 24), // GPIO5[24]
- PB_5 = MBED_PIN(0x0B, 5, 5, 25), // GPIO5[25]
- PB_6 = MBED_PIN(0x0B, 6, 5, 26), // GPIO5[26]
-
- PC_0 = MBED_PIN(0x0C, 0, NO_GPIO, 0),
- PC_1 = MBED_PIN(0x0C, 1, 6, 0), // GPIO6[0]
- PC_2 = MBED_PIN(0x0C, 2, 6, 1), // GPIO6[1]
- PC_3 = MBED_PIN(0x0C, 3, 6, 2), // GPIO6[2]
- PC_4 = MBED_PIN(0x0C, 4, 6, 3), // GPIO6[3]
- PC_5 = MBED_PIN(0x0C, 5, 6, 4), // GPIO6[4]
- PC_6 = MBED_PIN(0x0C, 6, 6, 5), // GPIO6[5]
- PC_7 = MBED_PIN(0x0C, 7, 6, 6), // GPIO6[6]
- PC_8 = MBED_PIN(0x0C, 8, 6, 7), // GPIO6[7]
- PC_9 = MBED_PIN(0x0C, 9, 6, 8), // GPIO6[8]
- PC_10 = MBED_PIN(0x0C, 10, 6, 9), // GPIO6[9]
- PC_11 = MBED_PIN(0x0C, 11, 6, 10), // GPIO6[10]
- PC_12 = MBED_PIN(0x0C, 12, 6, 11), // GPIO6[11]
- PC_13 = MBED_PIN(0x0C, 13, 6, 12), // GPIO6[12]
- PC_14 = MBED_PIN(0x0C, 14, 6, 13), // GPIO6[13]
-
- PD_0 = MBED_PIN(0x0D, 0, 6, 14), // GPIO6[14]
- PD_1 = MBED_PIN(0x0D, 1, 6, 15), // GPIO6[15]
- PD_2 = MBED_PIN(0x0D, 2, 6, 16), // GPIO6[16]
- PD_3 = MBED_PIN(0x0D, 3, 6, 17), // GPIO6[17]
- PD_4 = MBED_PIN(0x0D, 4, 6, 18), // GPIO6[18]
- PD_5 = MBED_PIN(0x0D, 5, 6, 19), // GPIO6[19]
- PD_6 = MBED_PIN(0x0D, 6, 6, 20), // GPIO6[20]
- PD_7 = MBED_PIN(0x0D, 7, 6, 21), // GPIO6[21]
- PD_8 = MBED_PIN(0x0D, 8, 6, 22), // GPIO6[22]
- PD_9 = MBED_PIN(0x0D, 9, 6, 23), // GPIO6[23]
- PD_10 = MBED_PIN(0x0D, 10, 6, 24), // GPIO6[24]
- PD_11 = MBED_PIN(0x0D, 11, 6, 25), // GPIO6[25]
- PD_12 = MBED_PIN(0x0D, 12, 6, 26), // GPIO6[26]
- PD_13 = MBED_PIN(0x0D, 13, 6, 27), // GPIO6[27]
- PD_14 = MBED_PIN(0x0D, 14, 6, 28), // GPIO6[28]
- PD_15 = MBED_PIN(0x0D, 15, 6, 29), // GPIO6[29]
- PD_16 = MBED_PIN(0x0D, 16, 6, 30), // GPIO6[30]
-
- PE_0 = MBED_PIN(0x0E, 0, 7, 0), // GPIO7[0]
- PE_1 = MBED_PIN(0x0E, 1, 7, 1), // GPIO7[1]
- PE_2 = MBED_PIN(0x0E, 2, 7, 2), // GPIO7[2]
- PE_3 = MBED_PIN(0x0E, 3, 7, 3), // GPIO7[3]
- PE_4 = MBED_PIN(0x0E, 4, 7, 4), // GPIO7[4]
- PE_5 = MBED_PIN(0x0E, 5, 7, 5), // GPIO7[5]
- PE_6 = MBED_PIN(0x0E, 6, 7, 6), // GPIO7[6]
- PE_7 = MBED_PIN(0x0E, 7, 7, 7), // GPIO7[7]
- PE_8 = MBED_PIN(0x0E, 8, 7, 8), // GPIO7[8]
- PE_9 = MBED_PIN(0x0E, 9, 7, 9), // GPIO7[9]
- PE_10 = MBED_PIN(0x0E, 10, 7, 10), // GPIO7[10]
- PE_11 = MBED_PIN(0x0E, 11, 7, 11), // GPIO7[11]
- PE_12 = MBED_PIN(0x0E, 12, 7, 12), // GPIO7[12]
- PE_13 = MBED_PIN(0x0E, 13, 7, 13), // GPIO7[13]
- PE_14 = MBED_PIN(0x0E, 14, 7, 14), // GPIO7[14]
- PE_15 = MBED_PIN(0x0E, 15, 7, 15), // GPIO7[15]
-
- PF_0 = MBED_PIN(0x0F, 0, NO_GPIO, 0),
- PF_1 = MBED_PIN(0x0F, 1, 7, 16), // GPIO7[16]
- PF_2 = MBED_PIN(0x0F, 2, 7, 17), // GPIO7[17]
- PF_3 = MBED_PIN(0x0F, 3, 7, 18), // GPIO7[18]
- PF_4 = MBED_PIN(0x0F, 4, NO_GPIO, 0),
- PF_5 = MBED_PIN(0x0F, 5, 7, 19), // GPIO7[19]
- PF_6 = MBED_PIN(0x0F, 6, 7, 20), // GPIO7[20]
- PF_7 = MBED_PIN(0x0F, 7, 7, 21), // GPIO7[21]
- PF_8 = MBED_PIN(0x0F, 8, 7, 22), // GPIO7[22]
- PF_9 = MBED_PIN(0x0F, 9, 7, 23), // GPIO7[23]
- PF_10 = MBED_PIN(0x0F, 10, 7, 24), // GPIO7[24]
- PF_11 = MBED_PIN(0x0F, 11, 7, 25), // GPIO7[25]
-
- // GPIO pins from MCU pins
- GPIO0_0 = P0_0,
- GPIO0_1 = P0_1 ,
- GPIO0_2 = P1_15,
- GPIO0_3 = P1_16,
- GPIO0_4 = P1_0,
- GPIO0_5 = P6_6,
- GPIO0_6 = P3_6,
- GPIO0_7 = P2_7,
- GPIO0_8 = P1_1,
- GPIO0_9 = P1_2,
- GPIO0_10 = P1_3,
- GPIO0_11 = P1_4,
- GPIO0_12 = P1_17,
- GPIO0_13 = P1_18,
- GPIO0_14 = P2_10,
- GPIO0_15 = P1_20,
-
- GPIO1_0 = P1_7,
- GPIO1_1 = P1_8,
- GPIO1_2 = P1_9,
- GPIO1_3 = P1_10,
- GPIO1_4 = P1_11,
- GPIO1_5 = P1_12,
- GPIO1_6 = P1_13,
- GPIO1_7 = P1_14,
- GPIO1_8 = P1_5,
- GPIO1_9 = P1_6,
- GPIO1_10 = P2_9,
- GPIO1_11 = P2_11,
- GPIO1_12 = P2_12,
- GPIO1_13 = P2_13,
- GPIO1_14 = P3_4,
- GPIO1_15 = P3_5,
-
- GPIO2_0 = P4_0,
- GPIO2_1 = P4_1,
- GPIO2_2 = P4_2,
- GPIO2_3 = P4_3,
- GPIO2_4 = P4_4,
- GPIO2_5 = P4_5,
- GPIO2_6 = P4_6,
- GPIO2_7 = P5_7,
- GPIO2_8 = P6_12,
- GPIO2_9 = P5_0,
- GPIO2_10 = P5_1,
- GPIO2_11 = P5_2,
- GPIO2_12 = P5_3,
- GPIO2_13 = P5_4,
- GPIO2_14 = P5_5,
- GPIO2_15 = P5_6,
-
- GPIO3_0 = P6_1,
- GPIO3_1 = P6_2,
- GPIO3_2 = P6_3,
- GPIO3_3 = P6_4,
- GPIO3_4 = P6_5,
- GPIO3_5 = P6_9,
- GPIO3_6 = P6_10,
- GPIO3_7 = P6_11,
- GPIO3_8 = P7_0,
- GPIO3_9 = P7_1,
- GPIO3_10 = P7_2,
- GPIO3_11 = P7_3,
- GPIO3_12 = P7_4,
- GPIO3_13 = P7_5,
- GPIO3_14 = P7_6,
- GPIO3_15 = P7_7,
-
- GPIO4_0 = P8_0,
- GPIO4_1 = P8_1,
- GPIO4_2 = P8_2,
- GPIO4_3 = P8_3,
- GPIO4_4 = P8_4,
- GPIO4_5 = P8_5,
- GPIO4_6 = P8_6,
- GPIO4_7 = P8_7,
- GPIO4_8 = PA_1,
- GPIO4_9 = PA_2,
- GPIO4_10 = PA_3,
- GPIO4_11 = P9_6,
- GPIO4_12 = P9_0,
- GPIO4_13 = P9_1,
- GPIO4_14 = P9_2,
- GPIO4_15 = P9_3,
-
- GPIO5_0 = P2_0,
- GPIO5_1 = P2_1,
- GPIO5_2 = P2_2,
- GPIO5_3 = P2_3,
- GPIO5_4 = P2_4,
- GPIO5_5 = P2_5,
- GPIO5_6 = P2_6,
- GPIO5_7 = P2_8,
- GPIO5_8 = P3_1,
- GPIO5_9 = P3_2,
- GPIO5_10 = P3_7,
- GPIO5_11 = P3_8,
- GPIO5_12 = P4_8,
- GPIO5_13 = P4_9,
- GPIO5_14 = P4_10,
- GPIO5_15 = P6_7,
- GPIO5_16 = P6_8,
- GPIO5_17 = P9_4,
- GPIO5_18 = P9_5,
- GPIO5_19 = PA_4,
- GPIO5_20 = PB_0,
- GPIO5_21 = PB_1,
- GPIO5_22 = PB_2,
- GPIO5_23 = PB_3,
- GPIO5_24 = PB_4,
- GPIO5_25 = PB_5,
- GPIO5_26 = PB_6,
-
- GPIO6_0 = PC_1,
- GPIO6_1 = PC_2,
- GPIO6_2 = PC_3,
- GPIO6_3 = PC_4,
- GPIO6_4 = PC_5,
- GPIO6_5 = PC_6,
- GPIO6_6 = PC_7,
- GPIO6_7 = PC_8,
- GPIO6_8 = PC_9,
- GPIO6_9 = PC_10,
- GPIO6_10 = PC_11,
- GPIO6_11 = PC_12,
- GPIO6_12 = PC_13,
- GPIO6_13 = PC_14,
- GPIO6_14 = PD_0,
- GPIO6_15 = PD_1,
- GPIO6_16 = PD_2,
- GPIO6_17 = PD_3,
- GPIO6_18 = PD_4,
- GPIO6_19 = PD_5,
- GPIO6_20 = PD_6,
- GPIO6_21 = PD_7,
- GPIO6_22 = PD_8,
- GPIO6_23 = PD_9,
- GPIO6_24 = PD_10,
- GPIO6_25 = PD_11,
- GPIO6_26 = PD_12,
- GPIO6_27 = PD_13,
- GPIO6_28 = PD_14,
- GPIO6_29 = PD_15,
- GPIO6_30 = PD_16,
-
- GPIO7_0 = PE_0,
- GPIO7_1 = PE_1,
- GPIO7_2 = PE_2,
- GPIO7_3 = PE_3,
- GPIO7_4 = PE_4,
- GPIO7_5 = PE_5,
- GPIO7_6 = PE_5,
- GPIO7_7 = PE_7,
- GPIO7_8 = PE_8,
- GPIO7_9 = PE_9,
- GPIO7_10 = PE_10,
- GPIO7_11 = PE_11,
- GPIO7_12 = PE_12,
- GPIO7_13 = PE_13,
- GPIO7_14 = PE_14,
- GPIO7_15 = PE_15,
- GPIO7_16 = PF_1,
- GPIO7_17 = PF_2,
- GPIO7_18 = PF_3,
- GPIO7_19 = PF_5,
- GPIO7_20 = PF_6,
- GPIO7_21 = PF_7,
- GPIO7_22 = PF_8,
- GPIO7_23 = PF_9,
- GPIO7_24 = PF_10,
- GPIO7_25 = PF_11,
-
- // Map mbed pin names to LPC43xx board signals
-
- // Group 0x18 : CLKn pins
- SFP_CLK0 = MBED_PIN(0x18, 0, 0, 0),
- SFP_CLK1 = MBED_PIN(0x18, 1, 0, 0),
- SFP_CLK2 = MBED_PIN(0x18, 2, 0, 0),
- SFP_CLK3 = MBED_PIN(0x18, 3, 0, 0),
-
- // Group 0x19 : USB1, I2C0, ADC0, ADC1
- SFP_USB1 = MBED_PIN(0x19, 0, 0, 0),
- SFP_I2C0 = MBED_PIN(0x19, 1, 0, 0),
- SFP_AIO0 = MBED_PIN(0x19, 2, 0, 0), // ADC0 function select register
- SFP_AIO1 = MBED_PIN(0x19, 3, 0, 0), // ADC1 function select register
- SFP_AIO2 = MBED_PIN(0x19, 4, 0, 0), // Analog function select register
-
- SFP_EMCD = MBED_PIN(0x1A, 0, 0, 0), // EMC clock delay register
-
- SFP_INS0 = MBED_PIN(0x1C, 0, 0, 0), // Interrupt select for pin interrupts 0 to 3
- SFP_INS1 = MBED_PIN(0x1C, 1, 0, 0), // Interrupt select for pin interrupts 4 to 7
-
- // Dedicated pin (no GPIO)
- P_DED = MBED_PIN(0, 0, NO_GPIO, 0),
-
- // Not connected
- NC = (int)0xFFFFFFFF,
-
- // ---------- LPCXpresso 4337 pins ----------
-
- D0 = P2_11,
- D1 = P2_10,
- D2 = P2_13,
- D3 = P1_8,
- D4 = P2_2,
- D5 = P1_7,
- D6 = P2_9,
- D7 = P2_12,
-
- D8 = P2_6,
- D9 = P6_5,
- D10 = P1_5,
- D11 = P1_4,
- D12 = P1_3,
- D13 = PF_4,
- D14 = P2_3,
- D15 = P2_4,
- SDA = P2_3,
- SCL = P2_4,
-
- A0 = P4_3,
- A1 = P4_1,
- A2 = PF_8,
- A3 = P7_5,
- A4 = NC,
- A5 = P2_5,
-
- LED_GREEN = P2_7,
- LED_RED = P6_11,
- LED_BLUE = P6_9,
-
- // Serial pins
- UART0_TX = P6_4,
- UART0_RX = P2_1,
- UART1_TX = D1,
- UART1_RX = D0,
- USBTX = UART0_TX,
- USBRX = UART0_RX,
-
- I2C_SDA = SDA,
- I2C_SDL = SCL,
-
- LED1 = LED_RED,
- LED2 = LED_BLUE,
- LED3 = LED_GREEN,
- LED4 = LED_RED,
-
- // Analog Only pins
- adc0_0 = MBED_PIN(NO_PORT, 0, NO_GPIO, 0),
- adc0_1 = MBED_PIN(NO_PORT, 1, NO_GPIO, 0),
- adc0_2 = MBED_PIN(NO_PORT, 2, NO_GPIO, 0),
- adc0_3 = MBED_PIN(NO_PORT, 3, NO_GPIO, 0),
- adc0_4 = MBED_PIN(NO_PORT, 4, NO_GPIO, 0),
- adc0_5 = MBED_PIN(NO_PORT, 5, NO_GPIO, 0),
- adc0_6 = MBED_PIN(NO_PORT, 6, NO_GPIO, 0),
- adc0_7 = MBED_PIN(NO_PORT, 7, NO_GPIO, 0),
- adc1_0 = MBED_PIN(NO_PORT, 8, NO_GPIO, 0),
- adc1_1 = MBED_PIN(NO_PORT, 9, NO_GPIO, 0),
- adc1_2 = MBED_PIN(NO_PORT, 10, NO_GPIO, 0),
- adc1_3 = MBED_PIN(NO_PORT, 11, NO_GPIO, 0),
- adc1_4 = MBED_PIN(NO_PORT, 12, NO_GPIO, 0),
- adc1_5 = MBED_PIN(NO_PORT, 13, NO_GPIO, 0),
- adc1_6 = MBED_PIN(NO_PORT, 14, NO_GPIO, 0),
- adc1_7 = MBED_PIN(NO_PORT, 15, NO_GPIO, 0),
-
- // ---------- End of LPCXpresso 4337 pins ----------
-} PinName;
-
-typedef enum {
- PullUp = 0,
- PullDown = 3,
- PullNone = 2,
- Repeater = 1,
- OpenDrain = 4,
- PullDefault = PullDown
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4337/device.h b/targets/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4337/device.h
deleted file mode 100644
index 5d57c9de57..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4337/device.h
+++ /dev/null
@@ -1,40 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-#define DEVICE_ID_LENGTH 32
-#define DEVICE_MAC_OFFSET 20
-
-
-
-
-
-#include "objects.h"
-
-#endif
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/analogin_api.c b/targets/TARGET_NXP/TARGET_LPC43XX/analogin_api.c
deleted file mode 100644
index e36280b210..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/analogin_api.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
- */
-#include "mbed_assert.h"
-#include "analogin_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "gpio_api.h"
-
-#define ANALOGIN_MEDIAN_FILTER 1
-
-static inline int div_round_up(int x, int y) {
- return (x + (y - 1)) / y;
-}
-
-static const PinMap PinMap_ADC[] = {
- {P4_3, ADC0_0, 0},
- {P4_1, ADC0_1, 0},
- {PF_8, ADC0_2, 0},
- {P7_5, ADC0_3, 0},
- {P7_4, ADC0_4, 0},
- {PF_10, ADC0_5, 0},
- {PB_6, ADC0_6, 0},
- {PC_3, ADC1_0, 0},
- {PC_0, ADC1_1, 0},
- {PF_9, ADC1_2, 0},
- {PF_6, ADC1_3, 0},
- {PF_5, ADC1_4, 0},
- {PF_11, ADC1_5, 0},
- {P7_7, ADC1_6, 0},
- {PF_7, ADC1_7, 0},
- {adc0_0, ADC_pin0_0, 0},
- {adc0_1, ADC_pin0_1, 0},
- {adc0_2, ADC_pin0_2, 0},
- {adc0_3, ADC_pin0_3, 0},
- {adc0_4, ADC_pin0_4, 0},
- {adc0_5, ADC_pin0_5, 0},
- {adc0_6, ADC_pin0_6, 0},
- {adc0_7, ADC_pin0_7, 0},
- {adc1_0, ADC_pin1_0, 0},
- {adc1_1, ADC_pin1_1, 0},
- {adc1_2, ADC_pin1_2, 0},
- {adc1_3, ADC_pin1_3, 0},
- {adc1_4, ADC_pin1_4, 0},
- {adc1_5, ADC_pin1_5, 0},
- {adc1_6, ADC_pin1_6, 0},
- {adc1_7, ADC_pin1_7, 0},
- {NC, NC, 0 }
-};
-
-void analogin_init(analogin_t *obj, PinName pin) {
- ADCName name;
-
- name = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
- MBED_ASSERT(obj->adc != (LPC_ADC_T *)NC);
-
- // Set ADC number
- if(name < ADC1_0) {
- obj->num = 0;
- } else if(name < ADC_pin0_0 && name > ADC0_6) {
- obj->num = 1;
- } else if(name < ADC_pin1_1 && name > ADC1_7) {
- obj->num = 0;
- } else if(name > ADC_pin0_7) {
- obj->num = 1;
- }
-
- //ADC register and channel
- obj->ch = name % (ADC0_7 + 1);
- obj->adc = (LPC_ADC_T *) (obj->num > 0) ? LPC_ADC1 : LPC_ADC0;
-
- // Reset pin function to GPIO if it is a GPIO pin. for adc only pins it is not necessary
- if(name < ADC_pin0_0) {
- gpio_set(pin);
- // Select ADC on analog function select register in SCU
- LPC_SCU->ENAIO[obj->num] |= (1 << obj->ch);
- } else {
- LPC_SCU->ENAIO[obj->num] &= ~(1 << obj->ch);
- }
-
- // Calculate minimum clock divider
- // clkdiv = divider - 1
- uint32_t PCLK = SystemCoreClock;
- uint32_t adcRate = 400000;
- uint32_t clkdiv = div_round_up(PCLK, adcRate) - 1;
-
- // Set the generic software-controlled ADC settings
- obj->adc->CR = (0 << 0) // SEL: 0 = no channels selected
- | (clkdiv << 8) // CLKDIV:
- | (0 << 16) // BURST: 0 = software control
- | (1 << 21) // PDN: 1 = operational
- | (0 << 24) // START: 0 = no start
- | (0 << 27); // EDGE: not applicable
-}
-
-static inline uint32_t adc_read(analogin_t *obj) {
- uint32_t temp;
- uint8_t channel = obj->ch;
- LPC_ADC_T *pADC = obj->adc;
-
- // Select the appropriate channel and start conversion
- pADC->CR |= ADC_CR_CH_SEL(channel);
- temp = pADC->CR & ~ADC_CR_START_MASK;
- pADC->CR = temp | (ADC_CR_START_MODE_SEL(ADC_START_NOW));
-
- // Wait for DONE bit and read data
- while (!(pADC->STAT & ADC_CR_CH_SEL(channel)));
- temp = pADC->DR[channel];
-
- // Deselect channel and return result
- pADC->CR &= ~ADC_CR_START_MASK;
- pADC->CR &= ~ADC_CR_CH_SEL(channel);
- return ADC_DR_RESULT(temp);
-}
-
-static inline void order(uint32_t *a, uint32_t *b) {
- if (*a > *b) {
- uint32_t t = *a;
- *a = *b;
- *b = t;
- }
-}
-
-static inline uint32_t adc_read_u32(analogin_t *obj) {
- uint32_t value;
-#if ANALOGIN_MEDIAN_FILTER
- uint32_t v1 = adc_read(obj);
- uint32_t v2 = adc_read(obj);
- uint32_t v3 = adc_read(obj);
- order(&v1, &v2);
- order(&v2, &v3);
- order(&v1, &v2);
- value = v2;
-#else
- value = adc_read(obj);
-#endif
- return value;
-}
-
-uint16_t analogin_read_u16(analogin_t *obj) {
- uint32_t value = adc_read_u32(obj);
-
- return (value << 6) | ((value >> 4) & 0x003F); // 10 bit
-}
-
-float analogin_read(analogin_t *obj) {
- uint32_t value = adc_read_u32(obj);
- return (float)value * (1.0f / (float)ADC_RANGE);
-}
-
-const PinMap *analogin_pinmap()
-{
- return PinMap_ADC;
-}
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/analogout_api.c b/targets/TARGET_NXP/TARGET_LPC43XX/analogout_api.c
deleted file mode 100644
index 2b62c2c976..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/analogout_api.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
- */
-#include "mbed_assert.h"
-#include "analogout_api.h"
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "gpio_api.h"
-
-static const PinMap PinMap_DAC[] = {
-#ifdef TARGET_LPC4337
- {P4_3, DAC_0, 0},
-#else
- {P4_4, DAC_0, 0},
-#endif
- {NC, NC, 0}
-};
-
-void analogout_init(dac_t *obj, PinName pin) {
- obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
- MBED_ASSERT(obj->dac != (DACName)NC);
-
- // Reset pin function to GPIO
- gpio_set(pin);
- // Select DAC on analog function select register in SCU
- LPC_SCU->ENAIO[2] |= 1; // Sets pin as DAC
-
- // Set bias=0 for maximum DAC update rate (1 MHz)
- LPC_DAC->CR &= ~DAC_BIAS_EN;
- // Enable DAC and DMA
- LPC_DAC->CTRL |= DAC_DMA_ENA;
-
- analogout_write_u16(obj, 0);
-}
-
-void analogout_free(dac_t *obj) {}
-
-static inline void dac_write(int value) {
-
- // Set the DAC output
- LPC_DAC->CR = DAC_SET(value);
-}
-
-static inline int dac_read() {
- return (DAC_GET(LPC_DAC->CR));
-}
-
-void analogout_write(dac_t *obj, float value) {
- if (value < 0.0f) {
- dac_write(0);
- } else if (value > 1.0f) {
- dac_write(DAC_RANGE);
- } else {
- dac_write(value * (float)DAC_RANGE);
- }
-}
-
-void analogout_write_u16(dac_t *obj, uint16_t value) {
- dac_write(value >> 6); // 10-bit
-}
-
-float analogout_read(dac_t *obj) {
- uint32_t value = dac_read();
- return (float)value * (1.0f / (float)DAC_RANGE);
-}
-
-uint16_t analogout_read_u16(dac_t *obj) {
- uint32_t value = dac_read(); // 10-bit
- return (value << 6) | ((value >> 4) & 0x003F);
-}
-
-const PinMap *analogout_pinmap()
-{
- return PinMap_DAC;
-}
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/device/LPC43xx.h b/targets/TARGET_NXP/TARGET_LPC43XX/device/LPC43xx.h
deleted file mode 100644
index 2b8072914b..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/device/LPC43xx.h
+++ /dev/null
@@ -1,2113 +0,0 @@
-/*
- * LPC43xx/LPC18xx MCU header
- *
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- *
- * Simplified version of NXP LPCOPEN LPC43XX/LPC18XX headers
- * 05/15/13 Micromint USA <support@micromint.com>
- */
-
-#ifndef __LPC43XX_H
-#define __LPC43XX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Treat __CORE_Mx as CORE_Mx */
-#if defined(__CORTEX_M0) && !defined(CORE_M0)
- #define CORE_M0
-#endif
-#if defined(__CORTEX_M3) && !defined(CORE_M3)
- #define CORE_M3
-#endif
-/* Default to M4 core if no core explicitly declared */
-#if !defined(CORE_M0) && !defined(CORE_M3)
- #define CORE_M4
-#endif
-
-/* Define LPC18XX or LPC43XX according to core type */
-#if (defined(CORE_M4) || defined(CORE_M0)) && !defined(__LPC43XX__)
- #define __LPC43XX__
-#endif
-#if defined(CORE_M3) && !defined(__LPC18XX__)
- #define __LPC18XX__
-#endif
-
-/* Start of section using anonymous unions */
-#if defined(__ARMCC_VERSION)
-// Kill warning "#pragma push with no matching #pragma pop"
- #pragma diag_suppress 2525
- #pragma push
- #pragma anon_unions
-#elif defined(__CWCC__)
- #pragma push
- #pragma cpp_extensions on
-#elif defined(__IAR_SYSTEMS_ICC__)
- //#pragma push // FIXME not usable for IAR
- #pragma language=extended
-#else /* defined(__GNUC__) and others */
- /* Assume anonymous unions are enabled by default */
-#endif
-
-#if defined(CORE_M4)
-/* ---------------------------------------------------------------------------
- * LPC43xx (M4 Core) Cortex CMSIS definitions
- */
-
-#define __CM4_REV 0x0000 /* Cortex-M4 Core Revision */
-#define __MPU_PRESENT 1 /* MPU present or not */
-#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /* FPU present or not */
-#define CHIP_LPC43XX /* LPCOPEN compatibility */
-
-/* ---------------------------------------------------------------------------
- * LPC43xx peripheral interrupt numbers
- */
-
-typedef enum {
- /* --------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
- Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
- BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
- UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
- PendSV_IRQn = -2,/* 14 Pendable request for system service */
- SysTick_IRQn = -1,/* 15 System Tick Timer */
-
- /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
- DAC_IRQn = 0,/* 0 DAC */
- M0CORE_IRQn = 1,/* 1 M0a */
- DMA_IRQn = 2,/* 2 DMA */
- RESERVED1_IRQn = 3,/* 3 EZH/EDM */
- RESERVED2_IRQn = 4,
- ETHERNET_IRQn = 5,/* 5 ETHERNET */
- SDIO_IRQn = 6,/* 6 SDIO */
- LCD_IRQn = 7,/* 7 LCD */
- USB0_IRQn = 8,/* 8 USB0 */
- USB1_IRQn = 9,/* 9 USB1 */
- SCT_IRQn = 10,/* 10 SCT */
- RITIMER_IRQn = 11,/* 11 RITIMER */
- TIMER0_IRQn = 12,/* 12 TIMER0 */
- TIMER1_IRQn = 13,/* 13 TIMER1 */
- TIMER2_IRQn = 14,/* 14 TIMER2 */
- TIMER3_IRQn = 15,/* 15 TIMER3 */
- MCPWM_IRQn = 16,/* 16 MCPWM */
- ADC0_IRQn = 17,/* 17 ADC0 */
- I2C0_IRQn = 18,/* 18 I2C0 */
- I2C1_IRQn = 19,/* 19 I2C1 */
- SPI_INT_IRQn = 20,/* 20 SPI_INT */
- ADC1_IRQn = 21,/* 21 ADC1 */
- SSP0_IRQn = 22,/* 22 SSP0 */
- SSP1_IRQn = 23,/* 23 SSP1 */
- USART0_IRQn = 24,/* 24 USART0 */
- UART1_IRQn = 25,/* 25 UART1 */
- USART2_IRQn = 26,/* 26 USART2 */
- USART3_IRQn = 27,/* 27 USART3 */
- I2S0_IRQn = 28,/* 28 I2S0 */
- I2S1_IRQn = 29,/* 29 I2S1 */
- RESERVED4_IRQn = 30,
- SGPIO_INT_IRQn = 31,/* 31 SGPIO_IINT */
- PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
- PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
- PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
- PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
- PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
- PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
- PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
- PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
- GINT0_IRQn = 40,/* 40 GINT0 */
- GINT1_IRQn = 41,/* 41 GINT1 */
- EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
- C_CAN1_IRQn = 43,/* 43 C_CAN1 */
- RESERVED6_IRQn = 44,
- RESERVED7_IRQn = 45,/* 45 VADC */
- ATIMER_IRQn = 46,/* 46 ATIMER */
- RTC_IRQn = 47,/* 47 RTC */
- RESERVED8_IRQn = 48,
- WWDT_IRQn = 49,/* 49 WWDT */
- RESERVED9_IRQn = 50,
- C_CAN0_IRQn = 51,/* 51 C_CAN0 */
- QEI_IRQn = 52,/* 52 QEI */
-} IRQn_Type;
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-
-#elif defined(CORE_M3)
-/* ---------------------------------------------------------------------------
- * LPC18xx (M3 Core) Cortex CMSIS definitions
- */
-#define __MPU_PRESENT 1 /* MPU present or not */
-#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 0 /* FPU present or not */
-#define CHIP_LPC18XX /* LPCOPEN compatibility */
-
-/* ---------------------------------------------------------------------------
- * LPC18xx peripheral interrupt numbers
- */
-
-typedef enum {
- /* --------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
- Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
- BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
- UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
- PendSV_IRQn = -2,/* 14 Pendable request for system service */
- SysTick_IRQn = -1,/* 15 System Tick Timer */
-
- /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
- DAC_IRQn = 0,/* 0 DAC */
- RESERVED0_IRQn = 1,
- DMA_IRQn = 2,/* 2 DMA */
- RESERVED1_IRQn = 3,/* 3 EZH/EDM */
- RESERVED2_IRQn = 4,
- ETHERNET_IRQn = 5,/* 5 ETHERNET */
- SDIO_IRQn = 6,/* 6 SDIO */
- LCD_IRQn = 7,/* 7 LCD */
- USB0_IRQn = 8,/* 8 USB0 */
- USB1_IRQn = 9,/* 9 USB1 */
- SCT_IRQn = 10,/* 10 SCT */
- RITIMER_IRQn = 11,/* 11 RITIMER */
- TIMER0_IRQn = 12,/* 12 TIMER0 */
- TIMER1_IRQn = 13,/* 13 TIMER1 */
- TIMER2_IRQn = 14,/* 14 TIMER2 */
- TIMER3_IRQn = 15,/* 15 TIMER3 */
- MCPWM_IRQn = 16,/* 16 MCPWM */
- ADC0_IRQn = 17,/* 17 ADC0 */
- I2C0_IRQn = 18,/* 18 I2C0 */
- I2C1_IRQn = 19,/* 19 I2C1 */
- RESERVED3_IRQn = 20,
- ADC1_IRQn = 21,/* 21 ADC1 */
- SSP0_IRQn = 22,/* 22 SSP0 */
- SSP1_IRQn = 23,/* 23 SSP1 */
- USART0_IRQn = 24,/* 24 USART0 */
- UART1_IRQn = 25,/* 25 UART1 */
- USART2_IRQn = 26,/* 26 USART2 */
- USART3_IRQn = 27,/* 27 USART3 */
- I2S0_IRQn = 28,/* 28 I2S0 */
- I2S1_IRQn = 29,/* 29 I2S1 */
- RESERVED4_IRQn = 30,
- RESERVED5_IRQn = 31,
- PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
- PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
- PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
- PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
- PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
- PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
- PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
- PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
- GINT0_IRQn = 40,/* 40 GINT0 */
- GINT1_IRQn = 41,/* 41 GINT1 */
- EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
- C_CAN1_IRQn = 43,/* 43 C_CAN1 */
- RESERVED6_IRQn = 44,
- RESERVED7_IRQn = 45,/* 45 VADC */
- ATIMER_IRQn = 46,/* 46 ATIMER */
- RTC_IRQn = 47,/* 47 RTC */
- RESERVED8_IRQn = 48,
- WWDT_IRQn = 49,/* 49 WWDT */
- RESERVED9_IRQn = 50,
- C_CAN0_IRQn = 51,/* 51 C_CAN0 */
- QEI_IRQn = 52,/* 52 QEI */
-} IRQn_Type;
-
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
-
-#elif defined(CORE_M0)
-/* ---------------------------------------------------------------------------
- * LPC43xx (M0 Core) Cortex CMSIS definitions
- */
-
-#define __MPU_PRESENT 0 /* MPU present or not */
-#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 0 /* FPU present or not */
-#define CHIP_LPC43XX /* LPCOPEN compatibility */
-
-/* ---------------------------------------------------------------------------
- * LPC43xx (M0 Core) peripheral interrupt numbers
- */
-
-typedef enum {
- /* --------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
- Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
- SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
- PendSV_IRQn = -2,/* 14 Pendable request for system service */
- SysTick_IRQn = -1,/* 15 System Tick Timer */
-
- /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
- DAC_IRQn = 0,/* 0 DAC */
- M0_M4CORE_IRQn = 1,/* 1 M0a */
- DMA_IRQn = 2,/* 2 DMA r */
- RESERVED1_IRQn = 3,/* 3 EZH/EDM */
- FLASHEEPROM_IRQn = 4,/* 4 ORed Flash EEPROM Bank A, B, EEPROM */
- ETHERNET_IRQn = 5,/* 5 ETHERNET */
- SDIO_IRQn = 6,/* 6 SDIO */
- LCD_IRQn = 7,/* 7 LCD */
- USB0_IRQn = 8,/* 8 USB0 */
- USB1_IRQn = 9,/* 9 USB1 */
- SCT_IRQn = 10,/* 10 SCT */
- RITIMER_IRQn = 11,/* 11 ORed RITIMER, WDT */
- TIMER0_IRQn = 12,/* 12 TIMER0 */
- GINT1_IRQn = 13,/* 13 GINT1 */
- PIN_INT4_IRQn = 14,/* 14 GPIO 4 */
- TIMER3_IRQn = 15,/* 15 TIMER3 */
- MCPWM_IRQn = 16,/* 16 MCPWM */
- ADC0_IRQn = 17,/* 17 ADC0 */
- I2C0_IRQn = 18,/* 18 ORed I2C0, I2C1 */
- SGPIO_INT_IRQn = 19,/* 19 SGPIO */
- SPI_INT_IRQn = 20,/* 20 SPI_INT */
- ADC1_IRQn = 21,/* 21 ADC1 */
- SSP0_IRQn = 22,/* 22 ORed SSP0, SSP1 */
- EVENTROUTER_IRQn = 23,/* 23 EVENTROUTER */
- USART0_IRQn = 24,/* 24 USART0 */
- UART1_IRQn = 25,/* 25 UART1 */
- USART2_IRQn = 26,/* 26 USART2 */
- USART3_IRQn = 27,/* 27 USART3 */
- I2S0_IRQn = 28,/* 28 ORed I2S0, I2S1 */
- C_CAN0_IRQn = 29,/* 29 C_CAN0 */
- I2S1_IRQn = 29,/* 29 I2S1 */
- RESERVED2_IRQn = 30,
- RESERVED3_IRQn = 31,
-} IRQn_Type;
-
-#include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
-#else
-#error Please #define CORE_M0, CORE_M3 or CORE_M4
-#endif
-
-#include "system_LPC43xx.h"
-
-/* ---------------------------------------------------------------------------
- * State Configurable Timer register block structure
- */
-#define LPC_SCT_BASE 0x40000000
-#define CONFIG_SCT_nEV (16) /* Number of events */
-#define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
-#define CONFIG_SCT_nOU (16) /* Number of outputs */
-
-typedef struct {
- __IO uint32_t CONFIG; /* Configuration Register */
- union {
- __IO uint32_t CTRL_U; /* Control Register */
- struct {
- __IO uint16_t CTRL_L; /* Low control register */
- __IO uint16_t CTRL_H; /* High control register */
- };
-
- };
-
- __IO uint16_t LIMIT_L; /* limit register for counter L */
- __IO uint16_t LIMIT_H; /* limit register for counter H */
- __IO uint16_t HALT_L; /* halt register for counter L */
- __IO uint16_t HALT_H; /* halt register for counter H */
- __IO uint16_t STOP_L; /* stop register for counter L */
- __IO uint16_t STOP_H; /* stop register for counter H */
- __IO uint16_t START_L; /* start register for counter L */
- __IO uint16_t START_H; /* start register for counter H */
- uint32_t RESERVED1[10]; /* 0x03C reserved */
- union {
- __IO uint32_t COUNT_U; /* counter register */
- struct {
- __IO uint16_t COUNT_L; /* counter register for counter L */
- __IO uint16_t COUNT_H; /* counter register for counter H */
- };
-
- };
-
- __IO uint16_t STATE_L; /* state register for counter L */
- __IO uint16_t STATE_H; /* state register for counter H */
- __I uint32_t INPUT; /* input register */
- __IO uint16_t REGMODE_L; /* match - capture registers mode register L */
- __IO uint16_t REGMODE_H; /* match - capture registers mode register H */
- __IO uint32_t OUTPUT; /* output register */
- __IO uint32_t OUTPUTDIRCTRL; /* output counter direction Control Register */
- __IO uint32_t RES; /* conflict resolution register */
- __IO uint32_t DMA0REQUEST; /* DMA0 Request Register */
- __IO uint32_t DMA1REQUEST; /* DMA1 Request Register */
- uint32_t RESERVED2[35];
- __IO uint32_t EVEN; /* event enable register */
- __IO uint32_t EVFLAG; /* event flag register */
- __IO uint32_t CONEN; /* conflict enable register */
- __IO uint32_t CONFLAG; /* conflict flag register */
- union {
- __IO union { /* ... Match / Capture value */
- uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
- struct {
- uint16_t L; /* SCTMATCH[i].L Access to L value */
- uint16_t H; /* SCTMATCH[i].H Access to H value */
- };
-
- } MATCH[CONFIG_SCT_nRG];
-
- __I union {
- uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
- struct {
- uint16_t L; /* SCTCAP[i].L Access to L value */
- uint16_t H; /* SCTCAP[i].H Access to H value */
- };
-
- } CAP[CONFIG_SCT_nRG];
-
- };
-
- uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /* ...-0x17C reserved */
- union {
- __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
- __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
- };
-
- uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
- union {
- __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
- __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
- };
-
- uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
- union {
- __IO union { /* 0x200-... Match Reload / Capture Control value */
- uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
- struct {
- uint16_t L; /* SCTMATCHREL[i].L Access to L value */
- uint16_t H; /* SCTMATCHREL[i].H Access to H value */
- };
-
- } MATCHREL[CONFIG_SCT_nRG];
-
- __IO union {
- uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
- struct {
- uint16_t L; /* SCTCAPCTRL[i].L Access to L value */
- uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
- };
-
- } CAPCTRL[CONFIG_SCT_nRG];
-
- };
-
- uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /* ...-0x27C reserved */
- union {
- __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
- __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
- };
-
- uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
- union {
- __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
- __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
- };
-
- uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
- __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
- uint32_t STATE; /* Event State Register */
- uint32_t CTRL; /* Event Control Register */
- } EVENT[CONFIG_SCT_nEV];
-
- uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
- __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
- uint32_t SET; /* Output n Set Register */
- uint32_t CLR; /* Output n Clear Register */
- } OUT[CONFIG_SCT_nOU];
-
- uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
- __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
-} LPC_SCT_T;
-
-/* Macro defines for SCT configuration register */
-#define SCT_CONFIG_16BIT_COUNTER 0x00000000 /* Operate as 2 16-bit counters */
-#define SCT_CONFIG_32BIT_COUNTER 0x00000001 /* Operate as 1 32-bit counter */
-
-#define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /* Bus clock */
-#define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /* SCT clock */
-#define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /* Input clock selected in CLKSEL field */
-#define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /* Input clock edge selected in CLKSEL field */
-
-#define SCT_CONFIG_NORELOADL_U (0x1 << 7) /* Operate as 1 32-bit counter */
-#define SCT_CONFIG_NORELOADH (0x1 << 8) /* Operate as 1 32-bit counter */
-
-/* Macro defines for SCT control register */
-#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for low or unified counter */
-#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
-
-#define SCT_CTRL_STOP_L (1 << 1) /* Stop low counter */
-#define SCT_CTRL_HALT_L (1 << 2) /* Halt low counter */
-#define SCT_CTRL_CLRCTR_L (1 << 3) /* Clear low or unified counter */
-#define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /* Bidirectional bit */
-#define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /* Prescale clock for low or unified counter */
-
-#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for high counter */
-#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
-#define SCT_CTRL_STOP_H (1 << 17) /* Stop high counter */
-#define SCT_CTRL_HALT_H (1 << 18) /* Halt high counter */
-#define SCT_CTRL_CLRCTR_H (1 << 19) /* Clear high counter */
-#define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
-#define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /* Prescale clock for high counter */
-
-/* Macro defines for SCT Conflict resolution register */
-#define SCT_RES_NOCHANGE (0)
-#define SCT_RES_SET_OUTPUT (1)
-#define SCT_RES_CLEAR_OUTPUT (2)
-#define SCT_RES_TOGGLE_OUTPUT (3)
-
-/* ---------------------------------------------------------------------------
- * GPDMA Channel register block structure
- */
-#define LPC_GPDMA_BASE 0x40002000
-
-typedef struct {
- __IO uint32_t SRCADDR; /* DMA Channel Source Address Register */
- __IO uint32_t DESTADDR; /* DMA Channel Destination Address Register */
- __IO uint32_t LLI; /* DMA Channel Linked List Item Register */
- __IO uint32_t CONTROL; /* DMA Channel Control Register */
- __IO uint32_t CONFIG; /* DMA Channel Configuration Register */
- __I uint32_t RESERVED1[3];
-} LPC_GPDMA_CH_T;
-
-#define GPDMA_CHANNELS 8
-
-/* ---------------------------------------------------------------------------
- * GPDMA register block
- */
-typedef struct { /* GPDMA Structure */
- __I uint32_t INTSTAT; /* DMA Interrupt Status Register */
- __I uint32_t INTTCSTAT; /* DMA Interrupt Terminal Count Request Status Register */
- __O uint32_t INTTCCLEAR; /* DMA Interrupt Terminal Count Request Clear Register */
- __I uint32_t INTERRSTAT; /* DMA Interrupt Error Status Register */
- __O uint32_t INTERRCLR; /* DMA Interrupt Error Clear Register */
- __I uint32_t RAWINTTCSTAT; /* DMA Raw Interrupt Terminal Count Status Register */
- __I uint32_t RAWINTERRSTAT; /* DMA Raw Error Interrupt Status Register */
- __I uint32_t ENBLDCHNS; /* DMA Enabled Channel Register */
- __IO uint32_t SOFTBREQ; /* DMA Software Burst Request Register */
- __IO uint32_t SOFTSREQ; /* DMA Software Single Request Register */
- __IO uint32_t SOFTLBREQ; /* DMA Software Last Burst Request Register */
- __IO uint32_t SOFTLSREQ; /* DMA Software Last Single Request Register */
- __IO uint32_t CONFIG; /* DMA Configuration Register */
- __IO uint32_t SYNC; /* DMA Synchronization Register */
- __I uint32_t RESERVED0[50];
- LPC_GPDMA_CH_T CH[GPDMA_CHANNELS];
-} LPC_GPDMA_T;
-
-/* ---------------------------------------------------------------------------
- * SPIFI register block structure
- */
-#define LPC_SPIFI_BASE 0x40003000
-
-typedef struct { /* SPIFI Structure */
- __IO uint32_t CTRL; /* Control register */
- __IO uint32_t CMD; /* Command register */
- __IO uint32_t ADDR; /* Address register */
- __IO uint32_t IDATA; /* Intermediate data register */
- __IO uint32_t CLIMIT; /* Cache limit register */
- union {
- __IO uint32_t DATA;
- __IO uint16_t DATA_HWORD;
- __IO uint8_t DATA_BYTE;
- }; /* Data register */
- __IO uint32_t MCMD; /* Memory command register */
- __IO uint32_t STAT; /* Status register */
-} LPC_SPIFI_T;
-
-/* ---------------------------------------------------------------------------
- * SD/MMC & SDIO register block structure
- */
-#define LPC_SDMMC_BASE 0x40004000
-
-typedef struct { /* SDMMC Structure */
- __IO uint32_t CTRL; /* Control Register */
- __IO uint32_t PWREN; /* Power Enable Register */
- __IO uint32_t CLKDIV; /* Clock Divider Register */
- __IO uint32_t CLKSRC; /* SD Clock Source Register */
- __IO uint32_t CLKENA; /* Clock Enable Register */
- __IO uint32_t TMOUT; /* Timeout Register */
- __IO uint32_t CTYPE; /* Card Type Register */
- __IO uint32_t BLKSIZ; /* Block Size Register */
- __IO uint32_t BYTCNT; /* Byte Count Register */
- __IO uint32_t INTMASK; /* Interrupt Mask Register */
- __IO uint32_t CMDARG; /* Command Argument Register */
- __IO uint32_t CMD; /* Command Register */
- __I uint32_t RESP0; /* Response Register 0 */
- __I uint32_t RESP1; /* Response Register 1 */
- __I uint32_t RESP2; /* Response Register 2 */
- __I uint32_t RESP3; /* Response Register 3 */
- __I uint32_t MINTSTS; /* Masked Interrupt Status Register */
- __IO uint32_t RINTSTS; /* Raw Interrupt Status Register */
- __I uint32_t STATUS; /* Status Register */
- __IO uint32_t FIFOTH; /* FIFO Threshold Watermark Register */
- __I uint32_t CDETECT; /* Card Detect Register */
- __I uint32_t WRTPRT; /* Write Protect Register */
- __IO uint32_t GPIO; /* General Purpose Input/Output Register */
- __I uint32_t TCBCNT; /* Transferred CIU Card Byte Count Register */
- __I uint32_t TBBCNT; /* Transferred Host to BIU-FIFO Byte Count Register */
- __IO uint32_t DEBNCE; /* Debounce Count Register */
- __IO uint32_t USRID; /* User ID Register */
- __I uint32_t VERID; /* Version ID Register */
- __I uint32_t RESERVED0;
- __IO uint32_t UHS_REG; /* UHS-1 Register */
- __IO uint32_t RST_N; /* Hardware Reset */
- __I uint32_t RESERVED1;
- __IO uint32_t BMOD; /* Bus Mode Register */
- __O uint32_t PLDMND; /* Poll Demand Register */
- __IO uint32_t DBADDR; /* Descriptor List Base Address Register */
- __IO uint32_t IDSTS; /* Internal DMAC Status Register */
- __IO uint32_t IDINTEN; /* Internal DMAC Interrupt Enable Register */
- __I uint32_t DSCADDR; /* Current Host Descriptor Address Register */
- __I uint32_t BUFADDR; /* Current Buffer Descriptor Address Register */
-} LPC_SDMMC_T;
-
-/* ---------------------------------------------------------------------------
- * External Memory Controller (EMC) register block structure
- */
-#define LPC_EMC_BASE 0x40005000
-
-typedef struct { /* EMC Structure */
- __IO uint32_t CONTROL; /* Controls operation of the memory controller. */
- __I uint32_t STATUS; /* Provides EMC status information. */
- __IO uint32_t CONFIG; /* Configures operation of the memory controller. */
- __I uint32_t RESERVED0[5];
- __IO uint32_t DYNAMICCONTROL; /* Controls dynamic memory operation. */
- __IO uint32_t DYNAMICREFRESH; /* Configures dynamic memory refresh operation. */
- __IO uint32_t DYNAMICREADCONFIG; /* Configures the dynamic memory read strategy. */
- __I uint32_t RESERVED1;
- __IO uint32_t DYNAMICRP; /* Selects the precharge command period. */
- __IO uint32_t DYNAMICRAS; /* Selects the active to precharge command period. */
- __IO uint32_t DYNAMICSREX; /* Selects the self-refresh exit time. */
- __IO uint32_t DYNAMICAPR; /* Selects the last-data-out to active command time. */
- __IO uint32_t DYNAMICDAL; /* Selects the data-in to active command time. */
- __IO uint32_t DYNAMICWR; /* Selects the write recovery time. */
- __IO uint32_t DYNAMICRC; /* Selects the active to active command period. */
- __IO uint32_t DYNAMICRFC; /* Selects the auto-refresh period. */
- __IO uint32_t DYNAMICXSR; /* Selects the exit self-refresh to active command time. */
- __IO uint32_t DYNAMICRRD; /* Selects the active bank A to active bank B latency. */
- __IO uint32_t DYNAMICMRD; /* Selects the load mode register to active command time. */
- __I uint32_t RESERVED2[9];
- __IO uint32_t STATICEXTENDEDWAIT; /* Selects time for long static memory read and write transfers. */
- __I uint32_t RESERVED3[31];
- __IO uint32_t DYNAMICCONFIG0; /* Selects the configuration information for dynamic memory chip select n. */
- __IO uint32_t DYNAMICRASCAS0; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
- __I uint32_t RESERVED4[6];
- __IO uint32_t DYNAMICCONFIG1; /* Selects the configuration information for dynamic memory chip select n. */
- __IO uint32_t DYNAMICRASCAS1; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
- __I uint32_t RESERVED5[6];
- __IO uint32_t DYNAMICCONFIG2; /* Selects the configuration information for dynamic memory chip select n. */
- __IO uint32_t DYNAMICRASCAS2; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
- __I uint32_t RESERVED6[6];
- __IO uint32_t DYNAMICCONFIG3; /* Selects the configuration information for dynamic memory chip select n. */
- __IO uint32_t DYNAMICRASCAS3; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
- __I uint32_t RESERVED7[38];
- __IO uint32_t STATICCONFIG0; /* Selects the memory configuration for static chip select n. */
- __IO uint32_t STATICWAITWEN0; /* Selects the delay from chip select n to write enable. */
- __IO uint32_t STATICWAITOEN0; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
- __IO uint32_t STATICWAITRD0; /* Selects the delay from chip select n to a read access. */
- __IO uint32_t STATICWAITPAG0; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
- __IO uint32_t STATICWAITWR0; /* Selects the delay from chip select n to a write access. */
- __IO uint32_t STATICWAITTURN0; /* Selects bus turnaround cycles */
- __I uint32_t RESERVED8;
- __IO uint32_t STATICCONFIG1; /* Selects the memory configuration for static chip select n. */
- __IO uint32_t STATICWAITWEN1; /* Selects the delay from chip select n to write enable. */
- __IO uint32_t STATICWAITOEN1; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
- __IO uint32_t STATICWAITRD1; /* Selects the delay from chip select n to a read access. */
- __IO uint32_t STATICWAITPAG1; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
- __IO uint32_t STATICWAITWR1; /* Selects the delay from chip select n to a write access. */
- __IO uint32_t STATICWAITTURN1; /* Selects bus turnaround cycles */
- __I uint32_t RESERVED9;
- __IO uint32_t STATICCONFIG2; /* Selects the memory configuration for static chip select n. */
- __IO uint32_t STATICWAITWEN2; /* Selects the delay from chip select n to write enable. */
- __IO uint32_t STATICWAITOEN2; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
- __IO uint32_t STATICWAITRD2; /* Selects the delay from chip select n to a read access. */
- __IO uint32_t STATICWAITPAG2; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
- __IO uint32_t STATICWAITWR2; /* Selects the delay from chip select n to a write access. */
- __IO uint32_t STATICWAITTURN2; /* Selects bus turnaround cycles */
- __I uint32_t RESERVED10;
- __IO uint32_t STATICCONFIG3; /* Selects the memory configuration for static chip select n. */
- __IO uint32_t STATICWAITWEN3; /* Selects the delay from chip select n to write enable. */
- __IO uint32_t STATICWAITOEN3; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
- __IO uint32_t STATICWAITRD3; /* Selects the delay from chip select n to a read access. */
- __IO uint32_t STATICWAITPAG3; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
- __IO uint32_t STATICWAITWR3; /* Selects the delay from chip select n to a write access. */
- __IO uint32_t STATICWAITTURN3; /* Selects bus turnaround cycles */
-} LPC_EMC_T;
-
-/* ---------------------------------------------------------------------------
- * USB High-Speed register block structure
- */
-#define LPC_USB0_BASE 0x40006000
-#define LPC_USB1_BASE 0x40007000
-
-typedef struct { /* USB Structure */
- __I uint32_t RESERVED0[64];
- __I uint32_t CAPLENGTH; /* Capability register length */
- __I uint32_t HCSPARAMS; /* Host controller structural parameters */
- __I uint32_t HCCPARAMS; /* Host controller capability parameters */
- __I uint32_t RESERVED1[5];
- __I uint32_t DCIVERSION; /* Device interface version number */
- __I uint32_t RESERVED2[7];
- union {
- __IO uint32_t USBCMD_H; /* USB command (host mode) */
- __IO uint32_t USBCMD_D; /* USB command (device mode) */
- };
-
- union {
- __IO uint32_t USBSTS_H; /* USB status (host mode) */
- __IO uint32_t USBSTS_D; /* USB status (device mode) */
- };
-
- union {
- __IO uint32_t USBINTR_H; /* USB interrupt enable (host mode) */
- __IO uint32_t USBINTR_D; /* USB interrupt enable (device mode) */
- };
-
- union {
- __IO uint32_t FRINDEX_H; /* USB frame index (host mode) */
- __I uint32_t FRINDEX_D; /* USB frame index (device mode) */
- };
-
- __I uint32_t RESERVED3;
- union {
- __IO uint32_t PERIODICLISTBASE; /* Frame list base address */
- __IO uint32_t DEVICEADDR; /* USB device address */
- };
-
- union {
- __IO uint32_t ASYNCLISTADDR; /* Address of endpoint list in memory (host mode) */
- __IO uint32_t ENDPOINTLISTADDR; /* Address of endpoint list in memory (device mode) */
- };
-
- __IO uint32_t TTCTRL; /* Asynchronous buffer status for embedded TT (host mode) */
- __IO uint32_t BURSTSIZE; /* Programmable burst size */
- __IO uint32_t TXFILLTUNING; /* Host transmit pre-buffer packet tuning (host mode) */
- __I uint32_t RESERVED4[2];
- __IO uint32_t ULPIVIEWPORT; /* ULPI viewport */
- __IO uint32_t BINTERVAL; /* Length of virtual frame */
- __IO uint32_t ENDPTNAK; /* Endpoint NAK (device mode) */
- __IO uint32_t ENDPTNAKEN; /* Endpoint NAK Enable (device mode) */
- __I uint32_t RESERVED5;
- union {
- __IO uint32_t PORTSC1_H; /* Port 1 status/control (host mode) */
- __IO uint32_t PORTSC1_D; /* Port 1 status/control (device mode) */
- };
-
- __I uint32_t RESERVED6[7];
- __IO uint32_t OTGSC; /* OTG status and control */
- union {
- __IO uint32_t USBMODE_H; /* USB mode (host mode) */
- __IO uint32_t USBMODE_D; /* USB mode (device mode) */
- };
-
- __IO uint32_t ENDPTSETUPSTAT; /* Endpoint setup status */
- __IO uint32_t ENDPTPRIME; /* Endpoint initialization */
- __IO uint32_t ENDPTFLUSH; /* Endpoint de-initialization */
- __I uint32_t ENDPTSTAT; /* Endpoint status */
- __IO uint32_t ENDPTCOMPLETE; /* Endpoint complete */
- __IO uint32_t ENDPTCTRL[6]; /* Endpoint control 0 */
-} LPC_USBHS_T;
-
-/* ---------------------------------------------------------------------------
- * LCD Controller register block structure
- */
-#define LPC_LCD_BASE 0x40008000
-
-typedef struct { /* LCD Structure */
- __IO uint32_t TIMH; /* Horizontal Timing Control register */
- __IO uint32_t TIMV; /* Vertical Timing Control register */
- __IO uint32_t POL; /* Clock and Signal Polarity Control register */
- __IO uint32_t LE; /* Line End Control register */
- __IO uint32_t UPBASE; /* Upper Panel Frame Base Address register */
- __IO uint32_t LPBASE; /* Lower Panel Frame Base Address register */
- __IO uint32_t CTRL; /* LCD Control register */
- __IO uint32_t INTMSK; /* Interrupt Mask register */
- __I uint32_t INTRAW; /* Raw Interrupt Status register */
- __I uint32_t INTSTAT; /* Masked Interrupt Status register */
- __O uint32_t INTCLR; /* Interrupt Clear register */
- __I uint32_t UPCURR; /* Upper Panel Current Address Value register */
- __I uint32_t LPCURR; /* Lower Panel Current Address Value register */
- __I uint32_t RESERVED0[115];
- __IO uint16_t PAL[256]; /* 256x16-bit Color Palette registers */
- __I uint32_t RESERVED1[256];
- __IO uint32_t CRSR_IMG[256];/* Cursor Image registers */
- __IO uint32_t CRSR_CTRL; /* Cursor Control register */
- __IO uint32_t CRSR_CFG; /* Cursor Configuration register */
- __IO uint32_t CRSR_PAL0; /* Cursor Palette register 0 */
- __IO uint32_t CRSR_PAL1; /* Cursor Palette register 1 */
- __IO uint32_t CRSR_XY; /* Cursor XY Position register */
- __IO uint32_t CRSR_CLIP; /* Cursor Clip Position register */
- __I uint32_t RESERVED2[2];
- __IO uint32_t CRSR_INTMSK; /* Cursor Interrupt Mask register */
- __O uint32_t CRSR_INTCLR; /* Cursor Interrupt Clear register */
- __I uint32_t CRSR_INTRAW; /* Cursor Raw Interrupt Status register */
- __I uint32_t CRSR_INTSTAT;/* Cursor Masked Interrupt Status register */
-} LPC_LCD_T;
-
-/* ---------------------------------------------------------------------------
- * EEPROM register block structure
- */
-#define LPC_EEPROM_BASE 0x4000E000
-
-typedef struct { /* EEPROM Structure */
- __IO uint32_t CMD; /* EEPROM command register */
- uint32_t RESERVED0;
- __IO uint32_t RWSTATE; /* EEPROM read wait state register */
- __IO uint32_t AUTOPROG; /* EEPROM auto programming register */
- __IO uint32_t WSTATE; /* EEPROM wait state register */
- __IO uint32_t CLKDIV; /* EEPROM clock divider register */
- __IO uint32_t PWRDWN; /* EEPROM power-down register */
- uint32_t RESERVED2[1007];
- __O uint32_t INTENCLR; /* EEPROM interrupt enable clear */
- __O uint32_t INTENSET; /* EEPROM interrupt enable set */
- __I uint32_t INTSTAT; /* EEPROM interrupt status */
- __I uint32_t INTEN; /* EEPROM interrupt enable */
- __O uint32_t INTSTATCLR; /* EEPROM interrupt status clear */
- __O uint32_t INTSTATSET; /* EEPROM interrupt status set */
-} LPC_EEPROM_T;
-
-/* ---------------------------------------------------------------------------
- * 10/100 MII & RMII Ethernet with timestamping register block structure
- */
-#define LPC_ETHERNET_BASE 0x40010000
-
-typedef struct { /* ETHERNET Structure */
- __IO uint32_t MAC_CONFIG; /* MAC configuration register */
- __IO uint32_t MAC_FRAME_FILTER; /* MAC frame filter */
- __IO uint32_t MAC_HASHTABLE_HIGH; /* Hash table high register */
- __IO uint32_t MAC_HASHTABLE_LOW; /* Hash table low register */
- __IO uint32_t MAC_MII_ADDR; /* MII address register */
- __IO uint32_t MAC_MII_DATA; /* MII data register */
- __IO uint32_t MAC_FLOW_CTRL; /* Flow control register */
- __IO uint32_t MAC_VLAN_TAG; /* VLAN tag register */
- __I uint32_t RESERVED0;
- __I uint32_t MAC_DEBUG; /* Debug register */
- __IO uint32_t MAC_RWAKE_FRFLT; /* Remote wake-up frame filter */
- __IO uint32_t MAC_PMT_CTRL_STAT; /* PMT control and status */
- __I uint32_t RESERVED1[2];
- __I uint32_t MAC_INTR; /* Interrupt status register */
- __IO uint32_t MAC_INTR_MASK; /* Interrupt mask register */
- __IO uint32_t MAC_ADDR0_HIGH; /* MAC address 0 high register */
- __IO uint32_t MAC_ADDR0_LOW; /* MAC address 0 low register */
- __I uint32_t RESERVED2[430];
- __IO uint32_t MAC_TIMESTP_CTRL; /* Time stamp control register */
- __IO uint32_t SUBSECOND_INCR; /* Sub-second increment register */
- __I uint32_t SECONDS; /* System time seconds register */
- __I uint32_t NANOSECONDS; /* System time nanoseconds register */
- __IO uint32_t SECONDSUPDATE; /* System time seconds update register */
- __IO uint32_t NANOSECONDSUPDATE; /* System time nanoseconds update register */
- __IO uint32_t ADDEND; /* Time stamp addend register */
- __IO uint32_t TARGETSECONDS; /* Target time seconds register */
- __IO uint32_t TARGETNANOSECONDS; /* Target time nanoseconds register */
- __IO uint32_t HIGHWORD; /* System time higher word seconds register */
- __I uint32_t TIMESTAMPSTAT; /* Time stamp status register */
- __IO uint32_t PPSCTRL; /* PPS control register */
- __I uint32_t AUXNANOSECONDS; /* Auxiliary time stamp nanoseconds register */
- __I uint32_t AUXSECONDS; /* Auxiliary time stamp seconds register */
- __I uint32_t RESERVED3[562];
- __IO uint32_t DMA_BUS_MODE; /* Bus Mode Register */
- __IO uint32_t DMA_TRANS_POLL_DEMAND; /* Transmit poll demand register */
- __IO uint32_t DMA_REC_POLL_DEMAND; /* Receive poll demand register */
- __IO uint32_t DMA_REC_DES_ADDR; /* Receive descriptor list address register */
- __IO uint32_t DMA_TRANS_DES_ADDR; /* Transmit descriptor list address register */
- __IO uint32_t DMA_STAT; /* Status register */
- __IO uint32_t DMA_OP_MODE; /* Operation mode register */
- __IO uint32_t DMA_INT_EN; /* Interrupt enable register */
- __I uint32_t DMA_MFRM_BUFOF; /* Missed frame and buffer overflow register */
- __IO uint32_t DMA_REC_INT_WDT; /* Receive interrupt watchdog timer register */
- __I uint32_t RESERVED4[8];
- __I uint32_t DMA_CURHOST_TRANS_DES; /* Current host transmit descriptor register */
- __I uint32_t DMA_CURHOST_REC_DES; /* Current host receive descriptor register */
- __I uint32_t DMA_CURHOST_TRANS_BUF; /* Current host transmit buffer address register */
- __I uint32_t DMA_CURHOST_REC_BUF; /* Current host receive buffer address register */
-} LPC_ENET_T;
-
-/* ---------------------------------------------------------------------------
- * Alarm Timer register block structure
- */
-#define LPC_ATIMER_BASE 0x40040000
-
-typedef struct { /* ATIMER Structure */
- __IO uint32_t DOWNCOUNTER; /* Downcounter register */
- __IO uint32_t PRESET; /* Preset value register */
- __I uint32_t RESERVED0[1012];
- __O uint32_t CLR_EN; /* Interrupt clear enable register */
- __O uint32_t SET_EN; /* Interrupt set enable register */
- __I uint32_t STATUS; /* Status register */
- __I uint32_t ENABLE; /* Enable register */
- __O uint32_t CLR_STAT; /* Clear register */
- __O uint32_t SET_STAT; /* Set register */
-} LPC_ATIMER_T;
-
-/* ---------------------------------------------------------------------------
- * Register File register block structure
- */
-#define LPC_REGFILE_BASE 0x40041000
-
-typedef struct {
- __IO uint32_t REGFILE[64]; /* General purpose storage register */
-} LPC_REGFILE_T;
-
-/* ---------------------------------------------------------------------------
- * Power Management Controller register block structure
- */
-#define LPC_PMC_BASE 0x40042000
-
-typedef struct { /* PMC Structure */
- __IO uint32_t PD0_SLEEP0_HW_ENA; /* Hardware sleep event enable register */
- __I uint32_t RESERVED0[6];
- __IO uint32_t PD0_SLEEP0_MODE; /* Sleep power mode register */
-} LPC_PMC_T;
-
-/* ---------------------------------------------------------------------------
- * CREG Register Block
- */
-#define LPC_CREG_BASE 0x40043000
-
-typedef struct { /* CREG Structure */
- __I uint32_t RESERVED0;
- __IO uint32_t CREG0; /* Chip configuration register 32 kHz oscillator output and BOD control register. */
- __I uint32_t RESERVED1[62];
- __IO uint32_t MXMEMMAP; /* ARM Cortex-M3/M4 memory mapping */
-#if defined(CHIP_LPC18XX)
- __I uint32_t RESERVED2[5];
-#else
- __I uint32_t RESERVED2;
- __I uint32_t CREG1; /* Configuration Register 1 */
- __I uint32_t CREG2; /* Configuration Register 2 */
- __I uint32_t CREG3; /* Configuration Register 3 */
- __I uint32_t CREG4; /* Configuration Register 4 */
-#endif
- __IO uint32_t CREG5; /* Chip configuration register 5. Controls JTAG access. */
- __IO uint32_t DMAMUX; /* DMA muxing control */
- __IO uint32_t FLASHCFGA; /* Flash accelerator configuration register for flash bank A */
- __IO uint32_t FLASHCFGB; /* Flash accelerator configuration register for flash bank B */
- __IO uint32_t ETBCFG; /* ETB RAM configuration */
- __IO uint32_t CREG6; /* Chip configuration register 6. */
-#if defined(CHIP_LPC18XX)
- __I uint32_t RESERVED4[52];
-#else
- __IO uint32_t M4TXEVENT; /* M4 IPC event register */
- __I uint32_t RESERVED4[51];
-#endif
- __I uint32_t CHIPID; /* Part ID */
-#if defined(CHIP_LPC18XX)
- __I uint32_t RESERVED5[191];
-#else
- __I uint32_t RESERVED5[127];
- __IO uint32_t M0TXEVENT; /* M0 IPC Event register */
- __IO uint32_t M0APPMEMMAP; /* ARM Cortex M0 memory mapping */
- __I uint32_t RESERVED6[62];
-#endif
- __IO uint32_t USB0FLADJ; /* USB0 frame length adjust register */
- __I uint32_t RESERVED7[63];
- __IO uint32_t USB1FLADJ; /* USB1 frame length adjust register */
-} LPC_CREG_T;
-
-/* ---------------------------------------------------------------------------
- * Event Router register structure
- */
-#define LPC_EVRT_BASE 0x40044000
-
-typedef struct { /* EVENTROUTER Structure */
- __IO uint32_t HILO; /* Level configuration register */
- __IO uint32_t EDGE; /* Edge configuration */
- __I uint32_t RESERVED0[1012];
- __O uint32_t CLR_EN; /* Event clear enable register */
- __O uint32_t SET_EN; /* Event set enable register */
- __I uint32_t STATUS; /* Status register */
- __I uint32_t ENABLE; /* Enable register */
- __O uint32_t CLR_STAT; /* Clear register */
- __O uint32_t SET_STAT; /* Set register */
-} LPC_EVRT_T;
-
-/* ---------------------------------------------------------------------------
- * Real Time Clock register block structure
- */
-#define LPC_RTC_BASE 0x40046000
-#define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
-
-typedef enum RTC_TIMEINDEX {
- RTC_TIMETYPE_SECOND, /* Second */
- RTC_TIMETYPE_MINUTE, /* Month */
- RTC_TIMETYPE_HOUR, /* Hour */
- RTC_TIMETYPE_DAYOFMONTH, /* Day of month */
- RTC_TIMETYPE_DAYOFWEEK, /* Day of week */
- RTC_TIMETYPE_DAYOFYEAR, /* Day of year */
- RTC_TIMETYPE_MONTH, /* Month */
- RTC_TIMETYPE_YEAR, /* Year */
- RTC_TIMETYPE_LAST
-} RTC_TIMEINDEX_T;
-
-#if RTC_EV_SUPPORT
-typedef enum LPC_RTC_EV_CHANNEL {
- RTC_EV_CHANNEL_1 = 0,
- RTC_EV_CHANNEL_2,
- RTC_EV_CHANNEL_3,
- RTC_EV_CHANNEL_NUM,
-} LPC_RTC_EV_CHANNEL_T;
-#endif /*RTC_EV_SUPPORT*/
-
-typedef struct { /* RTC Structure */
- __IO uint32_t ILR; /* Interrupt Location Register */
- __I uint32_t RESERVED0;
- __IO uint32_t CCR; /* Clock Control Register */
- __IO uint32_t CIIR; /* Counter Increment Interrupt Register */
- __IO uint32_t AMR; /* Alarm Mask Register */
- __I uint32_t CTIME[3]; /* Consolidated Time Register 0,1,2 */
- __IO uint32_t TIME[RTC_TIMETYPE_LAST]; /* Timer field registers */
- __IO uint32_t CALIBRATION; /* Calibration Value Register */
- __I uint32_t RESERVED1[7];
- __IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /* Alarm field registers */
-#if RTC_EV_SUPPORT
- __IO uint32_t ERSTATUS; /* Event Monitor/Recorder Status register*/
- __IO uint32_t ERCONTROL; /* Event Monitor/Recorder Control register*/
- __I uint32_t ERCOUNTERS; /* Event Monitor/Recorder Counters register*/
- __I uint32_t RESERVED2;
- __I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder First Stamp registers*/
- __I uint32_t RESERVED3;
- __I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder Last Stamp registers*/
-#endif /*RTC_EV_SUPPORT*/
-} LPC_RTC_T;
-
-/* ---------------------------------------------------------------------------
- * LPC18XX/43XX CGU register block structure
- */
-#define LPC_CGU_BASE 0x40050000
-#define LPC_CCU1_BASE 0x40051000
-#define LPC_CCU2_BASE 0x40052000
-/*
- * Input clocks for the CGU and can come from both external (crystal) and
- * internal (PLL) sources. Can be routed to the base clocks.
- */
-typedef enum CGU_CLKIN {
- CLKIN_32K, /* External 32KHz input */
- CLKIN_IRC, /* Internal IRC (12MHz) input */
- CLKIN_ENET_RX, /* External ENET_RX pin input */
- CLKIN_ENET_TX, /* External ENET_TX pin input */
- CLKIN_CLKIN, /* External GPCLKIN pin input */
- CLKIN_RESERVED1,
- CLKIN_CRYSTAL, /* External (main) crystal pin input */
- CLKIN_USBPLL, /* Internal USB PLL input */
- CLKIN_AUDIOPLL, /* Internal Audio PLL input */
- CLKIN_MAINPLL, /* Internal Main PLL input */
- CLKIN_RESERVED2,
- CLKIN_RESERVED3,
- CLKIN_IDIVA, /* Internal divider A input */
- CLKIN_IDIVB, /* Internal divider B input */
- CLKIN_IDIVC, /* Internal divider C input */
- CLKIN_IDIVD, /* Internal divider D input */
- CLKIN_IDIVE, /* Internal divider E input */
- CLKINPUT_PD /* External 32KHz input */
-} CGU_CLKIN_T;
-
-#define CLKIN_PLL0USB CLKIN_USBPLL
-#define CLKIN_PLL0AUDIO CLKIN_AUDIOPLL
-#define CLKIN_PLL1 CLKIN_MAINPLL
-
-/*
- * CGU base clocks are clocks that are associated with a single input clock
- * and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
- * clock can be configured to use the CLKIN_MAINPLL input clock, which will in
- * turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
- * CLK_PERIPH_SGPIO periphral clocks.
- */
-typedef enum CGU_BASE_CLK {
- CLK_BASE_SAFE, /* Base clock for WDT oscillator, IRC input only */
- CLK_BASE_USB0, /* Base USB clock for USB0, USB PLL input only */
-#if defined(CHIP_LPC43XX)
- CLK_BASE_PERIPH, /* Base clock for SGPIO */
-#else
- CLK_BASE_RESERVED1,
-#endif
- CLK_BASE_USB1, /* Base USB clock for USB1 */
- CLK_BASE_MX, /* Base clock for CPU core */
- CLK_BASE_SPIFI, /* Base clock for SPIFI */
-#if defined(CHIP_LPC43XX)
- CLK_BASE_SPI, /* Base clock for SPI */
-#else
- CLK_BASE_RESERVED2,
-#endif
- CLK_BASE_PHY_RX, /* Base clock for PHY RX */
- CLK_BASE_PHY_TX, /* Base clock for PHY TX */
- CLK_BASE_APB1, /* Base clock for APB1 group */
- CLK_BASE_APB3, /* Base clock for APB3 group */
- CLK_BASE_LCD, /* Base clock for LCD pixel clock */
-#if defined(CHIP_LPC43XX)
- CLK_BASE_VADC, /* Base clock for VADC */
-#else
- CLK_BASE_RESERVED3,
-#endif
- CLK_BASE_SDIO, /* Base clock for SDIO */
- CLK_BASE_SSP0, /* Base clock for SSP0 */
- CLK_BASE_SSP1, /* Base clock for SSP1 */
- CLK_BASE_UART0, /* Base clock for UART0 */
- CLK_BASE_UART1, /* Base clock for UART1 */
- CLK_BASE_UART2, /* Base clock for UART2 */
- CLK_BASE_UART3, /* Base clock for UART3 */
- CLK_BASE_OUT, /* Base clock for CLKOUT pin */
- CLK_BASE_RESERVED4,
- CLK_BASE_RESERVED5,
- CLK_BASE_RESERVED6,
- CLK_BASE_RESERVED7,
- CLK_BASE_APLL, /* Base clock for audio PLL */
- CLK_BASE_CGU_OUT0, /* Base clock for CGUOUT0 pin */
- CLK_BASE_CGU_OUT1, /* Base clock for CGUOUT1 pin */
- CLK_BASE_LAST,
- CLK_BASE_NONE = CLK_BASE_LAST
-} CGU_BASE_CLK_T;
-
-/*
- * CGU dividers provide an extra clock state where a specific clock can be
- * divided before being routed to a peripheral group. A divider accepts an
- * input clock and then divides it. To use the divided clock for a base clock
- * group, use the divider as the input clock for the base clock (for example,
- * use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
- */
-typedef enum CGU_IDIV {
- CLK_IDIV_A, /* CGU clock divider A */
- CLK_IDIV_B, /* CGU clock divider B */
- CLK_IDIV_C, /* CGU clock divider A */
- CLK_IDIV_D, /* CGU clock divider D */
- CLK_IDIV_E, /* CGU clock divider E */
- CLK_IDIV_LAST
-} CGU_IDIV_T;
-
-/*
- * Peripheral clocks are individual clocks routed to peripherals. Although
- * multiple peripherals may share a same base clock, each peripheral's clock
- * can be enabled or disabled individually. Some peripheral clocks also have
- * additional dividers associated with them.
- */
-typedef enum CCU_CLK {
- /* CCU1 clocks */
- CLK_APB3_BUS, /* APB3 bus clock from base clock CLK_BASE_APB3 */
- CLK_APB3_I2C1, /* I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
- CLK_APB3_DAC, /* DAC peripheral clock from base clock CLK_BASE_APB3 */
- CLK_APB3_ADC0, /* ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
- CLK_APB3_ADC1, /* ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
- CLK_APB3_CAN0, /* CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
- CLK_APB1_BUS = 32, /* APB1 bus clock clock from base clock CLK_BASE_APB1 */
- CLK_APB1_MOTOCON, /* Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
- CLK_APB1_I2C0, /* I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
- CLK_APB1_I2S, /* I2S register/perigheral clock from base clock CLK_BASE_APB1 */
- CLK_APB1_CAN1, /* CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
- CLK_SPIFI = 64, /* SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
- CLK_MX_BUS = 96, /* M3/M4 BUS core clock from base clock CLK_BASE_MX */
- CLK_MX_SPIFI, /* SPIFI register clock from base clock CLK_BASE_MX */
- CLK_MX_GPIO, /* GPIO register clock from base clock CLK_BASE_MX */
- CLK_MX_LCD, /* LCD register clock from base clock CLK_BASE_MX */
- CLK_MX_ETHERNET, /* ETHERNET register clock from base clock CLK_BASE_MX */
- CLK_MX_USB0, /* USB0 register clock from base clock CLK_BASE_MX */
- CLK_MX_EMC, /* EMC clock from base clock CLK_BASE_MX */
- CLK_MX_SDIO, /* SDIO register clock from base clock CLK_BASE_MX */
- CLK_MX_DMA, /* DMA register clock from base clock CLK_BASE_MX */
- CLK_MX_MXCORE, /* M3/M4 CPU core clock from base clock CLK_BASE_MX */
- RESERVED_ALIGN = CLK_MX_MXCORE + 3,
- CLK_MX_SCT, /* SCT register clock from base clock CLK_BASE_MX */
- CLK_MX_USB1, /* USB1 register clock from base clock CLK_BASE_MX */
- CLK_MX_EMC_DIV, /* ENC divider clock from base clock CLK_BASE_MX */
- CLK_MX_FLASHA, /* FLASHA bank clock from base clock CLK_BASE_MX */
- CLK_MX_FLASHB, /* FLASHB bank clock from base clock CLK_BASE_MX */
-#if defined(CHIP_LPC43XX)
- CLK_M4_M0APP, /* M0 app CPU core clock from base clock CLK_BASE_MX */
- CLK_MX_VADC, /* VADC clock from base clock CLK_BASE_MX */
-#else
- CLK_RESERVED1,
- CLK_RESERVED2,
-#endif
- CLK_MX_EEPROM, /* EEPROM clock from base clock CLK_BASE_MX */
- CLK_MX_WWDT = 128, /* WWDT register clock from base clock CLK_BASE_MX */
- CLK_MX_UART0, /* UART0 register clock from base clock CLK_BASE_MX */
- CLK_MX_UART1, /* UART1 register clock from base clock CLK_BASE_MX */
- CLK_MX_SSP0, /* SSP0 register clock from base clock CLK_BASE_MX */
- CLK_MX_TIMER0, /* TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_TIMER1, /* TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_SCU, /* SCU register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_CREG, /* CREG clock from base clock CLK_BASE_MX */
- CLK_MX_RITIMER = 160, /* RITIMER register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_UART2, /* UART3 register clock from base clock CLK_BASE_MX */
- CLK_MX_UART3, /* UART4 register clock from base clock CLK_BASE_MX */
- CLK_MX_TIMER2, /* TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_TIMER3, /* TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_SSP1, /* SSP1 register clock from base clock CLK_BASE_MX */
- CLK_MX_QEI, /* QEI register/perigheral clock from base clock CLK_BASE_MX */
-#if defined(CHIP_LPC43XX)
- CLK_PERIPH_BUS = 192, /* Peripheral bus clock from base clock CLK_BASE_PERIPH */
- CLK_RESERVED3,
- CLK_PERIPH_CORE, /* Peripheral core clock from base clock CLK_BASE_PERIPH */
- CLK_PERIPH_SGPIO, /* SGPIO clock from base clock CLK_BASE_PERIPH */
-#else
- CLK_RESERVED3 = 192,
- CLK_RESERVED3A,
- CLK_RESERVED4,
- CLK_RESERVED5,
-#endif
- CLK_USB0 = 224, /* USB0 clock from base clock CLK_BASE_USB0 */
- CLK_USB1 = 256, /* USB1 clock from base clock CLK_BASE_USB1 */
-#if defined(CHIP_LPC43XX)
- CLK_SPI = 288, /* SPI clock from base clock CLK_BASE_SPI */
- CLK_VADC, /* VADC clock from base clock CLK_BASE_VADC */
-#else
- CLK_RESERVED7 = 320,
- CLK_RESERVED8,
-#endif
- CLK_CCU1_LAST,
-
- /* CCU2 clocks */
- CLK_CCU2_START,
- CLK_APLL = CLK_CCU2_START, /* Audio PLL clock from base clock CLK_BASE_APLL */
- RESERVED_ALIGNB = CLK_CCU2_START + 31,
- CLK_APB2_UART3, /* UART3 clock from base clock CLK_BASE_UART3 */
- RESERVED_ALIGNC = CLK_CCU2_START + 63,
- CLK_APB2_UART2, /* UART2 clock from base clock CLK_BASE_UART2 */
- RESERVED_ALIGND = CLK_CCU2_START + 95,
- CLK_APB0_UART1, /* UART1 clock from base clock CLK_BASE_UART1 */
- RESERVED_ALIGNE = CLK_CCU2_START + 127,
- CLK_APB0_UART0, /* UART0 clock from base clock CLK_BASE_UART0 */
- RESERVED_ALIGNF = CLK_CCU2_START + 159,
- CLK_APB2_SSP1, /* SSP1 clock from base clock CLK_BASE_SSP1 */
- RESERVED_ALIGNG = CLK_CCU2_START + 191,
- CLK_APB0_SSP0, /* SSP0 clock from base clock CLK_BASE_SSP0 */
- RESERVED_ALIGNH = CLK_CCU2_START + 223,
- CLK_APB2_SDIO, /* SDIO clock from base clock CLK_BASE_SDIO */
- CLK_CCU2_LAST
-} CCU_CLK_T;
-
-/*
- * Audio or USB PLL selection
- */
-typedef enum CGU_USB_AUDIO_PLL {
- CGU_USB_PLL,
- CGU_AUDIO_PLL
-} CGU_USB_AUDIO_PLL_T;
-
-/*
- * PLL register block
- */
-typedef struct {
- __I uint32_t PLL_STAT; /* PLL status register */
- __IO uint32_t PLL_CTRL; /* PLL control register */
- __IO uint32_t PLL_MDIV; /* PLL M-divider register */
- __IO uint32_t PLL_NP_DIV; /* PLL N/P-divider register */
-} CGU_PLL_REG_T;
-
-typedef struct { /* (@ 0x40050000) CGU Structure */
- __I uint32_t RESERVED0[5];
- __IO uint32_t FREQ_MON; /* (@ 0x40050014) Frequency monitor register */
- __IO uint32_t XTAL_OSC_CTRL; /* (@ 0x40050018) Crystal oscillator control register */
- CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /* (@ 0x4005001C) USB and audio PLL blocks */
- __IO uint32_t PLL0AUDIO_FRAC; /* (@ 0x4005003C) PLL0 (audio) */
- __I uint32_t PLL1_STAT; /* (@ 0x40050040) PLL1 status register */
- __IO uint32_t PLL1_CTRL; /* (@ 0x40050044) PLL1 control register */
- __IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/* (@ 0x40050048) Integer divider A-E control registers */
- __IO uint32_t BASE_CLK[CLK_BASE_LAST]; /* (@ 0x4005005C) Start of base clock registers */
-} LPC_CGU_T;
-
-/* ---------------------------------------------------------------------------
- * CCU clock config/status register pair
- */
-typedef struct {
- __IO uint32_t CFG; /* CCU clock configuration register */
- __I uint32_t STAT; /* CCU clock status register */
-} CCU_CFGSTAT_T;
-
-/* ---------------------------------------------------------------------------
- * CCU1 register block structure
- */
-typedef struct { /* (@ 0x40051000) CCU1 Structure */
- __IO uint32_t PM; /* (@ 0x40051000) CCU1 power mode register */
- __I uint32_t BASE_STAT; /* (@ 0x40051004) CCU1 base clocks status register */
- __I uint32_t RESERVED0[62];
- CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /* (@ 0x40051100) Start of CCU1 clock registers */
-} LPC_CCU1_T;
-
-/* ---------------------------------------------------------------------------
- * CCU2 register block structure
- */
-typedef struct { /* (@ 0x40052000) CCU2 Structure */
- __IO uint32_t PM; /* (@ 0x40052000) Power mode register */
- __I uint32_t BASE_STAT; /* (@ 0x40052004) CCU base clocks status register */
- __I uint32_t RESERVED0[62];
- CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /* (@ 0x40052100) Start of CCU2 clock registers */
-} LPC_CCU2_T;
-
-/* ---------------------------------------------------------------------------
- * RGU register structure
- */
-#define LPC_RGU_BASE 0x40053000
-
-typedef enum RGU_RST {
- RGU_CORE_RST,
- RGU_PERIPH_RST,
- RGU_MASTER_RST,
- RGU_WWDT_RST = 4,
- RGU_CREG_RST,
- RGU_BUS_RST = 8,
- RGU_SCU_RST,
- RGU_M3_RST = 13,
- RGU_LCD_RST = 16,
- RGU_USB0_RST,
- RGU_USB1_RST,
- RGU_DMA_RST,
- RGU_SDIO_RST,
- RGU_EMC_RST,
- RGU_ETHERNET_RST,
- RGU_FLASHA_RST = 25,
- RGU_EEPROM_RST = 27,
- RGU_GPIO_RST,
- RGU_FLASHB_RST,
- RGU_TIMER0_RST = 32,
- RGU_TIMER1_RST,
- RGU_TIMER2_RST,
- RGU_TIMER3_RST,
- RGU_RITIMER_RST,
- RGU_SCT_RST,
- RGU_MOTOCONPWM_RST,
- RGU_QEI_RST,
- RGU_ADC0_RST,
- RGU_ADC1_RST,
- RGU_DAC_RST,
- RGU_UART0_RST = 44,
- RGU_UART1_RST,
- RGU_UART2_RST,
- RGU_UART3_RST,
- RGU_I2C0_RST,
- RGU_I2C1_RST,
- RGU_SSP0_RST,
- RGU_SSP1_RST,
- RGU_I2S_RST,
- RGU_SPIFI_RST,
- RGU_CAN1_RST,
- RGU_CAN0_RST,
-#ifdef CHIP_LPC43XX
- RGU_M0APP_RST,
- RGU_SGPIO_RST,
- RGU_SPI_RST,
-#endif
- RGU_LAST_RST = 63,
-} RGU_RST_T;
-
-typedef struct { /* RGU Structure */
- __I uint32_t RESERVED0[64];
- __O uint32_t RESET_CTRL0; /* Reset control register 0 */
- __O uint32_t RESET_CTRL1; /* Reset control register 1 */
- __I uint32_t RESERVED1[2];
- __IO uint32_t RESET_STATUS0; /* Reset status register 0 */
- __IO uint32_t RESET_STATUS1; /* Reset status register 1 */
- __IO uint32_t RESET_STATUS2; /* Reset status register 2 */
- __IO uint32_t RESET_STATUS3; /* Reset status register 3 */
- __I uint32_t RESERVED2[12];
- __I uint32_t RESET_ACTIVE_STATUS0;/* Reset active status register 0 */
- __I uint32_t RESET_ACTIVE_STATUS1;/* Reset active status register 1 */
- __I uint32_t RESERVED3[170];
- __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/* Reset external status registers */
-} LPC_RGU_T;
-
-/* ---------------------------------------------------------------------------
- * Windowed Watchdog register block structure
- */
-#define LPC_WWDT_BASE 0x40080000
-
-typedef struct { /* WWDT Structure */
- __IO uint32_t MOD; /* Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
- __IO uint32_t TC; /* Watchdog timer constant register. This register determines the time-out value. */
- __O uint32_t FEED; /* Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
- __I uint32_t TV; /* Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
-#ifdef WATCHDOG_CLKSEL_SUPPORT
- __IO uint32_t CLKSEL; /* Watchdog clock select register. */
-#else
- __I uint32_t RESERVED0;
-#endif
-#ifdef WATCHDOG_WINDOW_SUPPORT
- __IO uint32_t WARNINT; /* Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
- __IO uint32_t WINDOW; /* Watchdog timer window register. This register contains the Watchdog window value. */
-#endif
-} LPC_WWDT_T;
-
-/* ---------------------------------------------------------------------------
- * USART register block structure
- */
-#define LPC_USART0_BASE 0x40081000
-#define LPC_UART1_BASE 0x40082000
-#define LPC_USART2_BASE 0x400C1000
-#define LPC_USART3_BASE 0x400C2000
-
-typedef struct { /* USARTn Structure */
-
- union {
- __IO uint32_t DLL; /* Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
- __O uint32_t THR; /* Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
- __I uint32_t RBR; /* Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
- };
-
- union {
- __IO uint32_t IER; /* Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
- __IO uint32_t DLM; /* Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
- };
-
- union {
- __O uint32_t FCR; /* FIFO Control Register. Controls UART FIFO usage and modes. */
- __I uint32_t IIR; /* Interrupt ID Register. Identifies which interrupt(s) are pending. */
- };
-
- __IO uint32_t LCR; /* Line Control Register. Contains controls for frame formatting and break generation. */
- __IO uint32_t MCR; /* Modem Control Register. Only present on USART ports with full modem support. */
- __I uint32_t LSR; /* Line Status Register. Contains flags for transmit and receive status, including line errors. */
- __I uint32_t MSR; /* Modem Status Register. Only present on USART ports with full modem support. */
- __IO uint32_t SCR; /* Scratch Pad Register. Eight-bit temporary storage for software. */
- __IO uint32_t ACR; /* Auto-baud Control Register. Contains controls for the auto-baud feature. */
- __IO uint32_t ICR; /* IrDA control register (not all UARTS) */
- __IO uint32_t FDR; /* Fractional Divider Register. Generates a clock input for the baud rate divider. */
- __IO uint32_t OSR; /* Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
- __IO uint32_t TER1; /* Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
- uint32_t RESERVED0[3];
- __IO uint32_t HDEN; /* Half-duplex enable Register- only on some UARTs */
- __I uint32_t RESERVED1[1];
- __IO uint32_t SCICTRL; /* Smart card interface control register- only on some UARTs */
- __IO uint32_t RS485CTRL; /* RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
- __IO uint32_t RS485ADRMATCH; /* RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
- __IO uint32_t RS485DLY; /* RS-485/EIA-485 direction control delay. */
- union {
- __IO uint32_t SYNCCTRL; /* Synchronous mode control register. Only on USARTs. */
- __I uint32_t FIFOLVL; /* FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
- };
-
- __IO uint32_t TER2; /* Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
-} LPC_USART_T;
-
-/* ---------------------------------------------------------------------------
- * SSP register block structure
- */
-#define LPC_SSP0_BASE 0x40083000
-#define LPC_SSP1_BASE 0x400C5000
-
-typedef struct { /* SSPn Structure */
- __IO uint32_t CR0; /* Control Register 0. Selects the serial clock rate, bus type, and data size. */
- __IO uint32_t CR1; /* Control Register 1. Selects master/slave and other modes. */
- __IO uint32_t DR; /* Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
- __I uint32_t SR; /* Status Register */
- __IO uint32_t CPSR; /* Clock Prescale Register */
- __IO uint32_t IMSC; /* Interrupt Mask Set and Clear Register */
- __I uint32_t RIS; /* Raw Interrupt Status Register */
- __I uint32_t MIS; /* Masked Interrupt Status Register */
- __O uint32_t ICR; /* SSPICR Interrupt Clear Register */
- __IO uint32_t DMACR; /* SSPn DMA control register */
-} LPC_SSP_T;
-
-/* ---------------------------------------------------------------------------
- * 32-bit Standard timer register block structure
- */
-#define LPC_TIMER0_BASE 0x40084000
-#define LPC_TIMER1_BASE 0x40085000
-#define LPC_TIMER2_BASE 0x400C3000
-#define LPC_TIMER3_BASE 0x400C4000
-
-typedef struct { /* TIMERn Structure */
- __IO uint32_t IR; /* Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
- __IO uint32_t TCR; /* Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
- __IO uint32_t TC; /* Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
- __IO uint32_t PR; /* Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
- __IO uint32_t PC; /* Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
- __IO uint32_t MCR; /* Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
- __IO uint32_t MR[4]; /* Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
- __IO uint32_t CCR; /* Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
- __IO uint32_t CR[4]; /* Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
- __IO uint32_t EMR; /* External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
- __I uint32_t RESERVED0[12];
- __IO uint32_t CTCR; /* Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
-} LPC_TIMER_T;
-
-/* ---------------------------------------------------------------------------
- * System Control Unit register block
- */
-#define LPC_SCU_BASE 0x40086000
-
-typedef struct {
- __IO uint32_t SFSP[16][32];
- __I uint32_t RESERVED0[256];
- __IO uint32_t SFSCLK[4]; /* Pin configuration register for pins CLK0-3 */
- __I uint32_t RESERVED16[28];
- __IO uint32_t SFSUSB; /* Pin configuration register for USB */
- __IO uint32_t SFSI2C0; /* Pin configuration register for I2C0-bus pins */
- __IO uint32_t ENAIO[3]; /* Analog function select registers */
- __I uint32_t RESERVED17[27];
- __IO uint32_t EMCDELAYCLK; /* EMC clock delay register */
- __I uint32_t RESERVED18[63];
- __IO uint32_t PINTSEL0; /* Pin interrupt select register for pin interrupts 0 to 3. */
- __IO uint32_t PINTSEL1; /* Pin interrupt select register for pin interrupts 4 to 7. */
-} LPC_SCU_T;
-
-/*
- * SCU function and mode selection definitions
- * See the User Manual for specific modes and functions supoprted by the
- * various LPC18xx/43xx devices. Functionality can vary per device.
- */
-#define SCU_MODE_PULLUP (0x0 << 3) /* Enable pull-up resistor at pad */
-#define SCU_MODE_REPEATER (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
-#define SCU_MODE_INACT (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
-#define SCU_MODE_PULLDOWN (0x3 << 3) /* Enable pull-down resistor at pad */
-#define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /* Enable high-speed slew */
-#define SCU_MODE_INBUFF_EN (0x1 << 6) /* Enable Input buffer */
-#define SCU_MODE_ZIF_DIS (0x1 << 7) /* Disable input glitch filter */
-#define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /* Normal drive: 4mA drive strength */
-#define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /* Medium drive: 8mA drive strength */
-#define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /* High drive: 14mA drive strength */
-#define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /* Ultra high- drive: 20mA drive strength */
-
-#define SCU_MODE_FUNC0 0x0 /* Selects pin function 0 */
-#define SCU_MODE_FUNC1 0x1 /* Selects pin function 1 */
-#define SCU_MODE_FUNC2 0x2 /* Selects pin function 2 */
-#define SCU_MODE_FUNC3 0x3 /* Selects pin function 3 */
-#define SCU_MODE_FUNC4 0x4 /* Selects pin function 4 */
-#define SCU_MODE_FUNC5 0x5 /* Selects pin function 5 */
-#define SCU_MODE_FUNC6 0x6 /* Selects pin function 6 */
-#define SCU_MODE_FUNC7 0x7 /* Selects pin function 7 */
-
-/* Common SCU configurations */
-#define SCU_PINIO_FAST (SCU_MODE_INACT | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS)
-#define SCU_PINIO_PULLUP (SCU_MODE_INBUFF_EN)
-#define SCU_PINIO_PULLDOWN (SCU_MODE_PULLDOWN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
-#define SCU_PINIO_PULLNONE (SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
-
-/* Calculate SCU offset and register address from group and pin number */
-#define SCU_OFF(group, num) ((group << 7) + (num << 2))
-#define SCU_REG(group, num) ((__IO uint32_t *)(LPC_SCU_BASE + SCU_OFF(group, num)))
-
-/**
- * SCU function and mode selection definitions (old)
- * For backwards compatibility.
- */
-#define MD_PUP (0x0 << 3) /* Enable pull-up resistor at pad */
-#define MD_BUK (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
-#define MD_PLN (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
-#define MD_PDN (0x3 << 3) /* Enable pull-down resistor at pad */
-#define MD_EHS (0x1 << 5) /* Enable fast slew rate */
-#define MD_EZI (0x1 << 6) /* Input buffer enable */
-#define MD_ZI (0x1 << 7) /* Disable input glitch filter */
-#define MD_EHD0 (0x1 << 8) /* EHD driver strength low bit */
-#define MD_EHD1 (0x1 << 8) /* EHD driver strength high bit */
-#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
-#define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11) /* Pin configuration for STANDARD/FAST mode I2C */
-#define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11) /* Pin configuration for Fast-mode Plus I2C */
-
-#define FUNC0 0x0 /* Pin function 0 */
-#define FUNC1 0x1 /* Pin function 1 */
-#define FUNC2 0x2 /* Pin function 2 */
-#define FUNC3 0x3 /* Pin function 3 */
-#define FUNC4 0x4 /* Pin function 4 */
-#define FUNC5 0x5 /* Pin function 5 */
-#define FUNC6 0x6 /* Pin function 6 */
-#define FUNC7 0x7 /* Pin function 7 */
-
-#define PORT_OFFSET 0x80 /* Port offset definition */
-#define PIN_OFFSET 0x04 /* Pin offset definition */
-
-/* Returns the SFSP register address in the SCU for a pin and port,
- recommend using (*(volatile int *) &LPC_SCU->SFSP[po][pi];) */
-#define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) \
- (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
-
-/* Returns the address in the SCU for a SFSCLK clock register,
- recommend using (*(volatile int *) &LPC_SCU->SFSCLK[c];) */
-#define LPC_SCU_CLK(LPC_SCU_BASE, c) \
- (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
-
-/* ---------------------------------------------------------------------------
- * GPIO pin interrupt register block structure
- */
-#define LPC_GPIO_PIN_INT_BASE 0x40087000
-
-typedef struct { /* GPIO_PIN_INT Structure */
- __IO uint32_t ISEL; /* Pin Interrupt Mode register */
- __IO uint32_t IENR; /* Pin Interrupt Enable (Rising) register */
- __O uint32_t SIENR; /* Set Pin Interrupt Enable (Rising) register */
- __O uint32_t CIENR; /* Clear Pin Interrupt Enable (Rising) register */
- __IO uint32_t IENF; /* Pin Interrupt Enable Falling Edge / Active Level register */
- __O uint32_t SIENF; /* Set Pin Interrupt Enable Falling Edge / Active Level register */
- __O uint32_t CIENF; /* Clear Pin Interrupt Enable Falling Edge / Active Level address */
- __IO uint32_t RISE; /* Pin Interrupt Rising Edge register */
- __IO uint32_t FALL; /* Pin Interrupt Falling Edge register */
- __IO uint32_t IST; /* Pin Interrupt Status register */
-} LPC_GPIOPININT_T;
-
-typedef enum LPC_GPIOPININT_MODE {
- GPIOPININT_RISING_EDGE = 0x01,
- GPIOPININT_FALLING_EDGE = 0x02,
- GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
- GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
-} LPC_GPIOPININT_MODE_T;
-
-/* ---------------------------------------------------------------------------
- * GPIO grouped interrupt register block structure
- */
-#define LPC_GPIO_GROUP_INT0_BASE 0x40088000
-#define LPC_GPIO_GROUP_INT1_BASE 0x40089000
-
-typedef struct { /* GPIO_GROUP_INTn Structure */
- __IO uint32_t CTRL; /* GPIO grouped interrupt control register */
- __I uint32_t RESERVED0[7];
- __IO uint32_t PORT_POL[8]; /* GPIO grouped interrupt port polarity register */
- __IO uint32_t PORT_ENA[8]; /* GPIO grouped interrupt port m enable register */
-} LPC_GPIOGROUPINT_T;
-
-/* ---------------------------------------------------------------------------
- * Motor Control PWM register block structure
- */
-#define LPC_MCPWM_BASE 0x400A0000
-
-typedef struct { /* MCPWM Structure */
- __I uint32_t CON; /* PWM Control read address */
- __O uint32_t CON_SET; /* PWM Control set address */
- __O uint32_t CON_CLR; /* PWM Control clear address */
- __I uint32_t CAPCON; /* Capture Control read address */
- __O uint32_t CAPCON_SET; /* Capture Control set address */
- __O uint32_t CAPCON_CLR; /* Event Control clear address */
- __IO uint32_t TC[3]; /* Timer Counter register */
- __IO uint32_t LIM[3]; /* Limit register */
- __IO uint32_t MAT[3]; /* Match register */
- __IO uint32_t DT; /* Dead time register */
- __IO uint32_t CCP; /* Communication Pattern register */
- __I uint32_t CAP[3]; /* Capture register */
- __I uint32_t INTEN; /* Interrupt Enable read address */
- __O uint32_t INTEN_SET; /* Interrupt Enable set address */
- __O uint32_t INTEN_CLR; /* Interrupt Enable clear address */
- __I uint32_t CNTCON; /* Count Control read address */
- __O uint32_t CNTCON_SET; /* Count Control set address */
- __O uint32_t CNTCON_CLR; /* Count Control clear address */
- __I uint32_t INTF; /* Interrupt flags read address */
- __O uint32_t INTF_SET; /* Interrupt flags set address */
- __O uint32_t INTF_CLR; /* Interrupt flags clear address */
- __O uint32_t CAP_CLR; /* Capture clear address */
-} LPC_MCPWM_T;
-
-/* ---------------------------------------------------------------------------
- * I2C register block structure
- */
-#define LPC_I2C0_BASE 0x400A1000
-#define LPC_I2C1_BASE 0x400E0000
-
-typedef struct { /* I2C0 Structure */
- __IO uint32_t CONSET; /* I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
- __I uint32_t STAT; /* I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
- __IO uint32_t DAT; /* I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
- __IO uint32_t ADR0; /* I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
- __IO uint32_t SCLH; /* SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
- __IO uint32_t SCLL; /* SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
- __O uint32_t CONCLR; /* I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
- __IO uint32_t MMCTRL; /* Monitor mode control register. */
- __IO uint32_t ADR1; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
- __IO uint32_t ADR2; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
- __IO uint32_t ADR3; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
- __I uint32_t DATA_BUFFER; /* Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
- __IO uint32_t MASK[4]; /* I2C Slave address mask register */
-} LPC_I2C_T;
-
-/* ---------------------------------------------------------------------------
- * I2S register block structure
- */
-#define LPC_I2S0_BASE 0x400A2000
-#define LPC_I2S1_BASE 0x400A3000
-
-typedef struct { /* I2S Structure */
- __IO uint32_t DAO; /* I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
- __IO uint32_t DAI; /* I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
- __O uint32_t TXFIFO; /* I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
- __I uint32_t RXFIFO; /* I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
- __I uint32_t STATE; /* I2S Status Feedback Register. Contains status information about the I2S interface */
- __IO uint32_t DMA1; /* I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
- __IO uint32_t DMA2; /* I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
- __IO uint32_t IRQ; /* I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
- __IO uint32_t TXRATE; /* I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
- __IO uint32_t RXRATE; /* I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
- __IO uint32_t TXBITRATE; /* I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
- __IO uint32_t RXBITRATE; /* I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
- __IO uint32_t TXMODE; /* I2S Transmit mode control */
- __IO uint32_t RXMODE; /* I2S Receive mode control */
-} LPC_I2S_T;
-
-/* ---------------------------------------------------------------------------
- * CCAN Controller Area Network register block structure
- */
-#define LPC_C_CAN1_BASE 0x400A4000
-#define LPC_C_CAN0_BASE 0x400E2000
-
-typedef struct { /* C_CAN message interface Structure */
- __IO uint32_t IF_CMDREQ; /* Message interface command request */
- union {
- __IO uint32_t IF_CMDMSK_R; /* Message interface command mask (read direction) */
- __IO uint32_t IF_CMDMSK_W; /* Message interface command mask (write direction) */
- };
-
- __IO uint32_t IF_MSK1; /* Message interface mask 1 */
- __IO uint32_t IF_MSK2; /* Message interface mask 2 */
- __IO uint32_t IF_ARB1; /* Message interface arbitration 1 */
- __IO uint32_t IF_ARB2; /* Message interface arbitration 2 */
- __IO uint32_t IF_MCTRL; /* Message interface message control */
- __IO uint32_t IF_DA1; /* Message interface data A1 */
- __IO uint32_t IF_DA2; /* Message interface data A2 */
- __IO uint32_t IF_DB1; /* Message interface data B1 */
- __IO uint32_t IF_DB2; /* Message interface data B2 */
- __I uint32_t RESERVED[13];
-} LPC_CCAN_IF_T;
-
-typedef struct { /* C_CAN Structure */
- __IO uint32_t CNTL; /* CAN control */
- __IO uint32_t STAT; /* Status register */
- __I uint32_t EC; /* Error counter */
- __IO uint32_t BT; /* Bit timing register */
- __I uint32_t INT; /* Interrupt register */
- __IO uint32_t TEST; /* Test register */
- __IO uint32_t BRPE; /* Baud rate prescaler extension register */
- __I uint32_t RESERVED0;
- LPC_CCAN_IF_T IF[2];
- __I uint32_t RESERVED2[8];
- __I uint32_t TXREQ1; /* Transmission request 1 */
- __I uint32_t TXREQ2; /* Transmission request 2 */
- __I uint32_t RESERVED3[6];
- __I uint32_t ND1; /* New data 1 */
- __I uint32_t ND2; /* New data 2 */
- __I uint32_t RESERVED4[6];
- __I uint32_t IR1; /* Interrupt pending 1 */
- __I uint32_t IR2; /* Interrupt pending 2 */
- __I uint32_t RESERVED5[6];
- __I uint32_t MSGV1; /* Message valid 1 */
- __I uint32_t MSGV2; /* Message valid 2 */
- __I uint32_t RESERVED6[6];
- __IO uint32_t CLKDIV; /* CAN clock divider register */
-} LPC_CCAN_T;
-
-/* ---------------------------------------------------------------------------
- * Repetitive Interrupt Timer register block structure
- */
-#define LPC_RITIMER_BASE 0x400C0000
-
-typedef struct { /* RITIMER Structure */
- __IO uint32_t COMPVAL; /* Compare register */
- __IO uint32_t MASK; /* Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
- __IO uint32_t CTRL; /* Control register. */
- __IO uint32_t COUNTER; /* 32-bit counter */
-} LPC_RITIMER_T;
-
-/* ---------------------------------------------------------------------------
- * Quadrature Encoder Interface register block structure
- */
-#define LPC_QEI_BASE 0x400C6000
-
-typedef struct { /* QEI Structure */
- __O uint32_t CON; /* Control register */
- __I uint32_t STAT; /* Encoder status register */
- __IO uint32_t CONF; /* Configuration register */
- __I uint32_t POS; /* Position register */
- __IO uint32_t MAXPOS; /* Maximum position register */
- __IO uint32_t CMPOS0; /* position compare register 0 */
- __IO uint32_t CMPOS1; /* position compare register 1 */
- __IO uint32_t CMPOS2; /* position compare register 2 */
- __I uint32_t INXCNT; /* Index count register */
- __IO uint32_t INXCMP0; /* Index compare register 0 */
- __IO uint32_t LOAD; /* Velocity timer reload register */
- __I uint32_t TIME; /* Velocity timer register */
- __I uint32_t VEL; /* Velocity counter register */
- __I uint32_t CAP; /* Velocity capture register */
- __IO uint32_t VELCOMP; /* Velocity compare register */
- __IO uint32_t FILTERPHA; /* Digital filter register on input phase A (QEI_A) */
- __IO uint32_t FILTERPHB; /* Digital filter register on input phase B (QEI_B) */
- __IO uint32_t FILTERINX; /* Digital filter register on input index (QEI_IDX) */
- __IO uint32_t WINDOW; /* Index acceptance window register */
- __IO uint32_t INXCMP1; /* Index compare register 1 */
- __IO uint32_t INXCMP2; /* Index compare register 2 */
- __I uint32_t RESERVED0[993];
- __O uint32_t IEC; /* Interrupt enable clear register */
- __O uint32_t IES; /* Interrupt enable set register */
- __I uint32_t INTSTAT; /* Interrupt status register */
- __I uint32_t IE; /* Interrupt enable register */
- __O uint32_t CLR; /* Interrupt status clear register */
- __O uint32_t SET; /* Interrupt status set register */
-} LPC_QEI_T;
-
-/* ---------------------------------------------------------------------------
- * Global Input Multiplexer Array (GIMA) register block structure
- */
-#define LPC_GIMA_BASE 0x400C7000
-
-typedef struct { /* GIMA Structure */
- __IO uint32_t CAP0_IN[4][4]; /* Timer x CAP0_y capture input multiplexer (GIMA output ((x*4)+y)) */
- __IO uint32_t CTIN_IN[8]; /* SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */
- __IO uint32_t VADC_TRIGGER_IN; /* VADC trigger input multiplexer (GIMA output 24) */
- __IO uint32_t EVENTROUTER_13_IN; /* Event router input 13 multiplexer (GIMA output 25) */
- __IO uint32_t EVENTROUTER_14_IN; /* Event router input 14 multiplexer (GIMA output 26) */
- __IO uint32_t EVENTROUTER_16_IN; /* Event router input 16 multiplexer (GIMA output 27) */
- __IO uint32_t ADCSTART0_IN; /* ADC start0 input multiplexer (GIMA output 28) */
- __IO uint32_t ADCSTART1_IN; /* ADC start1 input multiplexer (GIMA output 29) */
-} LPC_GIMA_T;
-
-/* ---------------------------------------------------------------------------
- * DAC register block structure
- */
-#define LPC_DAC_BASE 0x400E1000
-
-typedef struct { /* DAC Structure */
- __IO uint32_t CR; /* DAC register. Holds the conversion data. */
- __IO uint32_t CTRL; /* DAC control register. */
- __IO uint32_t CNTVAL; /* DAC counter value register. */
-} LPC_DAC_T;
-
-/* After the selected settling time after this field is written with a
- * new VALUE, the voltage on the AOUT pin (with respect to VSSA)
- * is VALUE/1024 ? VREF
- */
-#define DAC_RANGE 0x3FF
-#define DAC_SET(n) ((uint32_t) ((n & DAC_RANGE) << 6))
-#define DAC_GET(n) ((uint32_t) ((n >> 6) & DAC_RANGE))
-#define DAC_VALUE(n) DAC_SET(n)
-/* If this bit = 0: The settling time of the DAC is 1 microsecond max,
- * and the maximum current is 700 microAmpere
- * If this bit = 1: The settling time of the DAC is 2.5 microsecond
- * and the maximum current is 350 microAmpere
- */
-#define DAC_BIAS_EN ((uint32_t) (1 << 16))
-/* Value to reload interrupt DMA counter */
-#define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))
-
-#define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))
-#define DAC_CNT_ENA ((uint32_t) (1 << 2))
-#define DAC_DMA_ENA ((uint32_t) (1 << 3))
-#define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
-
-/* Current option in DAC configuration option */
-typedef enum DAC_CURRENT_OPT {
- DAC_MAX_UPDATE_RATE_1MHz = 0, /* Shorter settling times and higher power consumption;
- allows for a maximum update rate of 1 MHz */
- DAC_MAX_UPDATE_RATE_400kHz /* Longer settling times and lower power consumption;
- allows for a maximum update rate of 400 kHz */
-} DAC_CURRENT_OPT_T;
-
-/* ---------------------------------------------------------------------------
- * ADC register block structure
- */
-#define LPC_ADC0_BASE 0x400E3000
-#define LPC_ADC1_BASE 0x400E4000
-#define ADC_ACC_10BITS
-
-/* ---------------------------------------------------------------------------
- * 10 or 12-bit ADC register block structure
- */
-typedef struct { /* ADCn Structure */
- __IO uint32_t CR; /* A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
- __I uint32_t GDR; /* A/D Global Data Register. Contains the result of the most recent A/D conversion. */
- __I uint32_t RESERVED0;
- __IO uint32_t INTEN; /* A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
- __I uint32_t DR[8]; /* A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
- __I uint32_t STAT; /* A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
-} LPC_ADC_T;
-
-/* ADC register support bitfields and mask */
-#define ADC_RANGE 0x3FF
-#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /* Mask for getting the 10 bits ADC data read value */
-#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /* Number of ADC accuracy bits */
-#define ADC_DR_DONE(n) (((n) >> 31)) /* Mask for reading the ADC done status */
-#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /* Mask for reading the ADC overrun status */
-#define ADC_CR_CH_SEL(n) ((1UL << (n))) /* Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
-#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /* The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
-#define ADC_CR_BURST ((1UL << 16)) /* Repeated conversions A/D enable bit */
-#define ADC_CR_PDN ((1UL << 21)) /* ADC convert is operational */
-#define ADC_CR_START_MASK ((7UL << 24)) /* ADC start mask bits */
-#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /* Select Start Mode */
-#define ADC_CR_START_NOW ((1UL << 24)) /* Start conversion now */
-#define ADC_CR_START_CTOUT15 ((2UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
-#define ADC_CR_START_CTOUT8 ((3UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
-#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
-#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
-#define ADC_CR_START_MCOA2 ((6UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
-#define ADC_CR_EDGE ((1UL << 27)) /* Start conversion on a falling edge on the selected CAP/MAT signal */
-#define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07) | ADC_CR_PDN)
-
-/* ADC status register used for IP drivers */
-typedef enum ADC_STATUS {
- ADC_DR_DONE_STAT, /* ADC data register staus */
- ADC_DR_OVERRUN_STAT,/* ADC data overrun staus */
- ADC_DR_ADINT_STAT /* ADC interrupt status */
-} ADC_STATUS_T;
-
-/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
-typedef enum ADC_START_MODE {
- ADC_NO_START = 0,
- ADC_START_NOW, /* Start conversion now */
- ADC_START_ON_CTOUT15, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
- ADC_START_ON_CTOUT8, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
- ADC_START_ON_ADCTRIG0, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
- ADC_START_ON_ADCTRIG1, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
- ADC_START_ON_MCOA2 /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
-} ADC_START_MODE_T;
-
-/* ---------------------------------------------------------------------------
- * GPIO port register block structure
- */
-#define LPC_GPIO_PORT_BASE 0x400F4000
-#define LPC_GPIO0_BASE (LPC_GPIO_PORT_BASE)
-#define LPC_GPIO1_BASE (LPC_GPIO_PORT_BASE + 0x04)
-#define LPC_GPIO2_BASE (LPC_GPIO_PORT_BASE + 0x08)
-#define LPC_GPIO3_BASE (LPC_GPIO_PORT_BASE + 0x0C)
-#define LPC_GPIO4_BASE (LPC_GPIO_PORT_BASE + 0x10)
-#define LPC_GPIO5_BASE (LPC_GPIO_PORT_BASE + 0x14)
-#define LPC_GPIO6_BASE (LPC_GPIO_PORT_BASE + 0x18)
-#define LPC_GPIO7_BASE (LPC_GPIO_PORT_BASE + 0x1C)
-
-typedef struct { /* GPIO_PORT Structure */
- __IO uint8_t B[128][32]; /* Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
- __IO uint32_t W[32][32]; /* Offset 0x1000: Word pin registers port 0 to n */
- __IO uint32_t DIR[32]; /* Offset 0x2000: Direction registers port n */
- __IO uint32_t MASK[32]; /* Offset 0x2080: Mask register port n */
- __IO uint32_t PIN[32]; /* Offset 0x2100: Portpin register port n */
- __IO uint32_t MPIN[32]; /* Offset 0x2180: Masked port register port n */
- __IO uint32_t SET[32]; /* Offset 0x2200: Write: Set register for port n Read: output bits for port n */
- __O uint32_t CLR[32]; /* Offset 0x2280: Clear port n */
- __O uint32_t NOT[32]; /* Offset 0x2300: Toggle port n */
-} LPC_GPIO_T;
-
-/* Calculate GPIO offset and port register address from group and pin number */
-#define GPIO_OFF(port, pin) ((port << 5) + pin)
-#define GPIO_REG(port, pin) ((__IO uint32_t *)(LPC_GPIO_PORT_BASE + 0x2000 + GPIO_OFF(port, pin)))
-
-/* ---------------------------------------------------------------------------
- * SPI register block structure
- */
-#define LPC_SPI_BASE 0x40100000
-
-typedef struct { /* SPI Structure */
- __IO uint32_t CR; /* SPI Control Register. This register controls the operation of the SPI. */
- __I uint32_t SR; /* SPI Status Register. This register shows the status of the SPI. */
- __IO uint32_t DR; /* SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. */
- __IO uint32_t CCR; /* SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
- __I uint32_t RESERVED0[3];
- __IO uint32_t INT; /* SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
-} LPC_SPI_T;
-
-/* SPI CFG Register BitMask */
-#define SPI_CR_BITMASK ((uint32_t) 0xFFC)
-/* Enable of controlling the number of bits per transfer */
-#define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
-/* Mask of field of bit controlling */
-#define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
-/* Set the number of bits per a transfer */
-#define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
-/* SPI Clock Phase Select*/
-#define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
-#define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /* Change data on the first edge, Capture data on the following edge*/
-/* SPI Clock Polarity Select*/
-#define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
-#define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
-/* SPI Slave Mode Select */
-#define SPI_CR_SLAVE_EN ((uint32_t) 0)
-/* SPI Master Mode Select */
-#define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
-/* SPI MSB First mode enable */
-#define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /* Data will be transmitted and received in standard order (MSB first).*/
-/* SPI LSB First mode enable */
-#define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /* Data will be transmitted and received in reverse order (LSB first).*/
-/* SPI interrupt enable */
-#define SPI_CR_INT_EN ((uint32_t) (1 << 7))
-/* SPI STAT Register BitMask */
-#define SPI_SR_BITMASK ((uint32_t) 0xF8)
-/* Slave abort Flag */
-#define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
-/* Mode fault Flag */
-#define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
-/* Read overrun flag*/
-#define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
-/* Write collision flag. */
-#define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
-/* SPI transfer complete flag. */
-#define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
-/* SPI error flag */
-#define SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)
-/* Enable SPI Test Mode */
-#define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
-/* SPI interrupt flag */
-#define SPI_INT_SPIF ((uint32_t) (1 << 0))
-/* Receiver Data */
-#define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
-
-/* SPI Mode*/
-typedef enum LPC_SPI_MODE {
- SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
- SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
-} LPC_SPI_MODE_T;
-
-/* SPI Clock Mode*/
-typedef enum LPC_SPI_CLOCK_MODE {
- SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 0 */
- SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 1 */
- SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 0 */
- SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 1 */
- SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /* alias */
- SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /* alias */
- SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /* alias */
- SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /* alias */
-} LPC_SPI_CLOCK_MODE_T;
-
-/* SPI Data Order Mode*/
-typedef enum LPC_SPI_DATA_ORDER {
- SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
- SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
-} LPC_SPI_DATA_ORDER_T;
-
-/* ---------------------------------------------------------------------------
- * Serial GPIO register block structure
- */
-#define LPC_SGPIO_BASE 0x40101000
-
-typedef struct { /* SGPIO Structure */
- __IO uint32_t OUT_MUX_CFG[16]; /* Pin multiplexer configurationregisters. */
- __IO uint32_t SGPIO_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. */
- __IO uint32_t SLICE_MUX_CFG[16]; /* Slice multiplexer configuration registers. */
- __IO uint32_t REG[16]; /* Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
- __IO uint32_t REG_SS[16]; /* Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
- __IO uint32_t PRESET[16]; /* Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
- __IO uint32_t COUNT[16]; /* Down counter, counts down each clock cycle. */
- __IO uint32_t POS[16]; /* Each time COUNT0 reaches 0x0 */
- __IO uint32_t MASK_A; /* Mask for pattern match function of slice A */
- __IO uint32_t MASK_H; /* Mask for pattern match function of slice H */
- __IO uint32_t MASK_I; /* Mask for pattern match function of slice I */
- __IO uint32_t MASK_P; /* Mask for pattern match function of slice P */
- __I uint32_t GPIO_INREG; /* GPIO input status register */
- __IO uint32_t GPIO_OUTREG; /* GPIO output control register */
- __IO uint32_t GPIO_OENREG; /* GPIO OE control register */
- __IO uint32_t CTRL_ENABLED; /* Enables the slice COUNT counter */
- __IO uint32_t CTRL_DISABLED; /* Disables the slice COUNT counter */
- __I uint32_t RESERVED0[823];
- __O uint32_t CLR_EN_0; /* Shift clock interrupt clear mask */
- __O uint32_t SET_EN_0; /* Shift clock interrupt set mask */
- __I uint32_t ENABLE_0; /* Shift clock interrupt enable */
- __I uint32_t STATUS_0; /* Shift clock interrupt status */
- __O uint32_t CTR_STATUS_0; /* Shift clock interrupt clear status */
- __O uint32_t SET_STATUS_0; /* Shift clock interrupt set status */
- __I uint32_t RESERVED1[2];
- __O uint32_t CLR_EN_1; /* Capture clock interrupt clear mask */
- __O uint32_t SET_EN_1; /* Capture clock interrupt set mask */
- __I uint32_t ENABLE_1; /* Capture clock interrupt enable */
- __I uint32_t STATUS_1; /* Capture clock interrupt status */
- __O uint32_t CTR_STATUS_1; /* Capture clock interrupt clear status */
- __O uint32_t SET_STATUS_1; /* Capture clock interrupt set status */
- __I uint32_t RESERVED2[2];
- __O uint32_t CLR_EN_2; /* Pattern match interrupt clear mask */
- __O uint32_t SET_EN_2; /* Pattern match interrupt set mask */
- __I uint32_t ENABLE_2; /* Pattern match interrupt enable */
- __I uint32_t STATUS_2; /* Pattern match interrupt status */
- __O uint32_t CTR_STATUS_2; /* Pattern match interrupt clear status */
- __O uint32_t SET_STATUS_2; /* Pattern match interrupt set status */
- __I uint32_t RESERVED3[2];
- __O uint32_t CLR_EN_3; /* Input interrupt clear mask */
- __O uint32_t SET_EN_3; /* Input bit match interrupt set mask */
- __I uint32_t ENABLE_3; /* Input bit match interrupt enable */
- __I uint32_t STATUS_3; /* Input bit match interrupt status */
- __O uint32_t CTR_STATUS_3; /* Input bit match interrupt clear status */
- __O uint32_t SET_STATUS_3; /* Shift clock interrupt set status */
-} LPC_SGPIO_T;
-
-/* End of section using anonymous unions */
-#if defined(__ARMCC_VERSION)
- #pragma pop
-#elif defined(__CWCC__)
- #pragma pop
-#elif defined(__IAR_SYSTEMS_ICC__)
- //#pragma pop // FIXME not usable for IAR
-#else /* defined(__GNUC__) and others */
- /* Leave anonymous unions enabled */
-#endif
-
-/* ---------------------------------------------------------------------------
- * LPC43xx Peripheral register set declarations
- */
-#define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE)
-#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
-#define LPC_SPIFI ((LPC_SPIFI_T *) LPC_SPIFI_BASE)
-#define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE)
-#define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
-#define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE)
-#define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE)
-#define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
-#define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
-#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE)
-#define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE)
-#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
-#define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE)
-#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
-#define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
-#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
-#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
-#define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
-#define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
-#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
-#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
-#define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE)
-#define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
-#define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE)
-#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
-#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
-#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
-#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
-#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
-#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
-#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
-#define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
-#define LPC_GPIO_PIN_INT ((LPC_GPIOPININT_T *) LPC_GPIO_PIN_INT_BASE)
-#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
-#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
-#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
-#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
-#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
-#define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE)
-#define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE)
-#define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE)
-#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
-#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
-#define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE)
-#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
-#define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE)
-#define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE)
-#define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE)
-#define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
-#define LPC_GPIO0 ((LPC_GPIO_T *) LPC_GPIO0_BASE)
-#define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
-#define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
-#define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
-#define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
-#define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
-#define LPC_GPIO6 ((LPC_GPIO_T *) LPC_GPIO6_BASE)
-#define LPC_GPIO7 ((LPC_GPIO_T *) LPC_GPIO7_BASE)
-#define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
-#define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC43XX_H */
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_ARM_STD/LPC43xx_spifi.ini b/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_ARM_STD/LPC43xx_spifi.ini
deleted file mode 100644
index a5c3700b65..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_ARM_STD/LPC43xx_spifi.ini
+++ /dev/null
@@ -1,12 +0,0 @@
-
-FUNC void Setup (unsigned int region) {
- region &= 0xFF000000;
- _WDWORD(0x40043100, region); // Set the shadow pointer
- _WDWORD(0xE000ED08, 0); // Set the vector table offset to 0
- SP = _RDWORD(0); // Setup Stack Pointer
- PC = _RDWORD(4); // Setup Program Counter
-}
-
-LOAD %L INCREMENTAL
-Setup(0x14000000); // Get ready to execute image in QSPI
-
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_ARM_STD/TARGET_LPC4337/LPC4337.sct b/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_ARM_STD/TARGET_LPC4337/LPC4337.sct
deleted file mode 100644
index 2acea5e300..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_ARM_STD/TARGET_LPC4337/LPC4337.sct
+++ /dev/null
@@ -1,32 +0,0 @@
-#! armcc -E
-
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define Stack_Size MBED_BOOT_STACK_SIZE
-
-LR_IROM1 0x1A000000 0x00080000 { ; load region size_region
- ER_IROM1 0x1A000000 0x00080000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
-; ER_IROM2 0x1B000000 0x00080000 { ; load address = execution address
-; .ANY (+RO)
-; }
-
- ; 8_byte_aligned(69 vect * 4 bytes) = 8_byte_aligned(0x0114) = 0x0118
- RW_IRAM1 0x10000000+0x118 0x8000-0x118-Stack_Size {
- .ANY (+RW +ZI)
- }
- ARM_LIB_STACK (0x10000000+0x8000) EMPTY -Stack_Size { ; stack
- }
-
-; RW_IRAM2 0x10080000 0xA000 { ; RW data
-; .ANY (IRAM2)
-; }
-; RW_IRAM3 0x20000000 0x10000 { ; RW data
-; .ANY (AHBSRAM)
-; }
-}
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_ARM_STD/TARGET_LPC4337/startup_LPC4337.S b/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_ARM_STD/TARGET_LPC4337/startup_LPC4337.S
deleted file mode 100644
index 4cab776116..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_ARM_STD/TARGET_LPC4337/startup_LPC4337.S
+++ /dev/null
@@ -1,288 +0,0 @@
-;/***********************************************************************
-; * @brief: LPC18xx/43xx M3/M4 startup code
-; *
-; * @note
-; * Copyright(C) NXP Semiconductors, 2012
-; * All rights reserved.
-; *
-; * @par
-; * Software that is described herein is for illustrative purposes only
-; * which provides customers with programming information regarding the
-; * LPC products. This software is supplied "AS IS" without any warranties of
-; * any kind, and NXP Semiconductors and its licensor disclaim any and
-; * all warranties, express or implied, including all implied warranties of
-; * merchantability, fitness for a particular purpose and non-infringement of
-; * intellectual property rights. NXP Semiconductors assumes no responsibility
-; * or liability for the use of the software, conveys no license or rights under any
-; * patent, copyright, mask work right, or any other intellectual property rights in
-; * or to any products. NXP Semiconductors reserves the right to make changes
-; * in the software without notification. NXP Semiconductors also makes no
-; * representation or warranty that such application will be suitable for the
-; * specified use without further testing or modification.
-; *
-; * @par
-; * Permission to use, copy, modify, and distribute this software and its
-; * documentation is hereby granted, under NXP Semiconductors' and its
-; * licensor's relevant copyrights in the software, without fee, provided that it
-; * is used in conjunction with NXP Semiconductors microcontrollers. This
-; * copyright, permission, and disclaimer notice must appear in all copies of
-; * this code.
-; */
-
- PRESERVE8
- THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
-
-Sign_Value EQU 0x5A5A5A5A
-
-__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; 0 Top of Stack
- DCD Reset_Handler ; 1 Reset Handler
- DCD NMI_Handler ; 2 NMI Handler
- DCD HardFault_Handler ; 3 Hard Fault Handler
- DCD MemManage_Handler ; 4 MPU Fault Handler
- DCD BusFault_Handler ; 5 Bus Fault Handler
- DCD UsageFault_Handler ; 6 Usage Fault Handler
- DCD Sign_Value ; 7 Reserved
- DCD UnHandled_Vector ; 8 Reserved
- DCD UnHandled_Vector ; 9 Reserved
- DCD UnHandled_Vector ; 10 Reserved
- DCD SVC_Handler ; 11 SVCall Handler
- DCD DebugMon_Handler ; 12 Debug Monitor Handler
- DCD UnHandled_Vector ; 13 Reserved
- DCD PendSV_Handler ; 14 PendSV Handler
- DCD SysTick_Handler ; 15 SysTick Handler
-
- ; External Interrupts
- DCD DAC_IRQHandler ; 16 D/A Converter
- DCD MX_CORE_IRQHandler ; 17 M0/M4 IRQ handler (LPC43XX ONLY)
- DCD DMA_IRQHandler ; 18 General Purpose DMA
- DCD UnHandled_Vector ; 19 Reserved
- DCD FLASHEEPROM_IRQHandler ; 20 ORed flash bank A, flash bank B, EEPROM interrupts
- DCD ETH_IRQHandler ; 21 Ethernet
- DCD SDIO_IRQHandler ; 22 SD/MMC
- DCD LCD_IRQHandler ; 23 LCD
- DCD USB0_IRQHandler ; 24 USB0
- DCD USB1_IRQHandler ; 25 USB1
- DCD SCT_IRQHandler ; 26 State Configurable Timer
- DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
- DCD TIMER0_IRQHandler ; 28 Timer0
- DCD TIMER1_IRQHandler ; 29 Timer1
- DCD TIMER2_IRQHandler ; 30 Timer2
- DCD TIMER3_IRQHandler ; 31 Timer3
- DCD MCPWM_IRQHandler ; 32 Motor Control PWM
- DCD ADC0_IRQHandler ; 33 A/D Converter 0
- DCD I2C0_IRQHandler ; 34 I2C0
- DCD I2C1_IRQHandler ; 35 I2C1
- DCD SPI_IRQHandler ; 36 SPI (LPC43XX ONLY)
- DCD ADC1_IRQHandler ; 37 A/D Converter 1
- DCD SSP0_IRQHandler ; 38 SSP0
- DCD SSP1_IRQHandler ; 39 SSP1
- DCD UART0_IRQHandler ; 40 UART0
- DCD UART1_IRQHandler ; 41 UART1
- DCD UART2_IRQHandler ; 42 UART2
- DCD UART3_IRQHandler ; 43 UART3
- DCD I2S0_IRQHandler ; 44 I2S0
- DCD I2S1_IRQHandler ; 45 I2S1
- DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
- DCD SGPIO_IRQHandler ; 47 SGPIO (LPC43XX ONLY)
- DCD GPIO0_IRQHandler ; 48 GPIO0
- DCD GPIO1_IRQHandler ; 49 GPIO1
- DCD GPIO2_IRQHandler ; 50 GPIO2
- DCD GPIO3_IRQHandler ; 51 GPIO3
- DCD GPIO4_IRQHandler ; 52 GPIO4
- DCD GPIO5_IRQHandler ; 53 GPIO5
- DCD GPIO6_IRQHandler ; 54 GPIO6
- DCD GPIO7_IRQHandler ; 55 GPIO7
- DCD GINT0_IRQHandler ; 56 GINT0
- DCD GINT1_IRQHandler ; 57 GINT1
- DCD EVRT_IRQHandler ; 58 Event Router
- DCD CAN1_IRQHandler ; 59 C_CAN1
- DCD UnHandled_Vector ; 60 Reserved
- DCD VADC_IRQHandler ; 61 VADC
- DCD ATIMER_IRQHandler ; 62 ATIMER
- DCD RTC_IRQHandler ; 63 RTC
- DCD UnHandled_Vector ; 64 Reserved
- DCD WDT_IRQHandler ; 65 WDT
- DCD UnHandled_Vector ; 66 M0s
- DCD CAN0_IRQHandler ; 67 C_CAN0
- DCD QEI_IRQHandler ; 68 QEI
-
-; IF :LNOT::DEF:NO_CRP
-; AREA |.ARM.__at_0x02FC|, CODE, READONLY
-;CRP_Key DCD 0xFFFFFFFF
-; ENDIF
-
- AREA |.text|, CODE, READONLY
-
-; Reset Handler
-
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-UnHandled_Vector PROC
- EXPORT UnHandled_Vector [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT DAC_IRQHandler [WEAK]
- EXPORT MX_CORE_IRQHandler [WEAK]
- EXPORT DMA_IRQHandler [WEAK]
- EXPORT FLASHEEPROM_IRQHandler [WEAK]
- EXPORT ETH_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT LCD_IRQHandler [WEAK]
- EXPORT USB0_IRQHandler [WEAK]
- EXPORT USB1_IRQHandler [WEAK]
- EXPORT SCT_IRQHandler [WEAK]
- EXPORT RIT_IRQHandler [WEAK]
- EXPORT TIMER0_IRQHandler [WEAK]
- EXPORT TIMER1_IRQHandler [WEAK]
- EXPORT TIMER2_IRQHandler [WEAK]
- EXPORT TIMER3_IRQHandler [WEAK]
- EXPORT MCPWM_IRQHandler [WEAK]
- EXPORT ADC0_IRQHandler [WEAK]
- EXPORT I2C0_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT SPI_IRQHandler [WEAK]
- EXPORT ADC1_IRQHandler [WEAK]
- EXPORT SSP0_IRQHandler [WEAK]
- EXPORT SSP1_IRQHandler [WEAK]
- EXPORT UART0_IRQHandler [WEAK]
- EXPORT UART1_IRQHandler [WEAK]
- EXPORT UART2_IRQHandler [WEAK]
- EXPORT UART3_IRQHandler [WEAK]
- EXPORT I2S0_IRQHandler [WEAK]
- EXPORT I2S1_IRQHandler [WEAK]
- EXPORT SPIFI_IRQHandler [WEAK]
- EXPORT SGPIO_IRQHandler [WEAK]
- EXPORT GPIO0_IRQHandler [WEAK]
- EXPORT GPIO1_IRQHandler [WEAK]
- EXPORT GPIO2_IRQHandler [WEAK]
- EXPORT GPIO3_IRQHandler [WEAK]
- EXPORT GPIO4_IRQHandler [WEAK]
- EXPORT GPIO5_IRQHandler [WEAK]
- EXPORT GPIO6_IRQHandler [WEAK]
- EXPORT GPIO7_IRQHandler [WEAK]
- EXPORT GINT0_IRQHandler [WEAK]
- EXPORT GINT1_IRQHandler [WEAK]
- EXPORT EVRT_IRQHandler [WEAK]
- EXPORT CAN1_IRQHandler [WEAK]
- EXPORT VADC_IRQHandler [WEAK]
- EXPORT ATIMER_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT WDT_IRQHandler [WEAK]
- EXPORT CAN0_IRQHandler [WEAK]
- EXPORT QEI_IRQHandler [WEAK]
-
-DAC_IRQHandler
-MX_CORE_IRQHandler
-DMA_IRQHandler
-FLASHEEPROM_IRQHandler
-ETH_IRQHandler
-SDIO_IRQHandler
-LCD_IRQHandler
-USB0_IRQHandler
-USB1_IRQHandler
-SCT_IRQHandler
-RIT_IRQHandler
-TIMER0_IRQHandler
-TIMER1_IRQHandler
-TIMER2_IRQHandler
-TIMER3_IRQHandler
-MCPWM_IRQHandler
-ADC0_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-SPI_IRQHandler
-ADC1_IRQHandler
-SSP0_IRQHandler
-SSP1_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-I2S0_IRQHandler
-I2S1_IRQHandler
-SPIFI_IRQHandler
-SGPIO_IRQHandler
-GPIO0_IRQHandler
-GPIO1_IRQHandler
-GPIO2_IRQHandler
-GPIO3_IRQHandler
-GPIO4_IRQHandler
-GPIO5_IRQHandler
-GPIO6_IRQHandler
-GPIO7_IRQHandler
-GINT0_IRQHandler
-GINT1_IRQHandler
-EVRT_IRQHandler
-CAN1_IRQHandler
-VADC_IRQHandler
-ATIMER_IRQHandler
-RTC_IRQHandler
-WDT_IRQHandler
-CAN0_IRQHandler
-QEI_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
- END
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_IAR/LPC43xx.icf b/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_IAR/LPC43xx.icf
deleted file mode 100644
index 5ed1599b48..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_IAR/LPC43xx.icf
+++ /dev/null
@@ -1,39 +0,0 @@
-/* [ROM] */
-define symbol __intvec_start__ = 0x14000000;
-define symbol __region_ROM_start__ = 0x14000000;
-define symbol __region_ROM_end__ = 0x143FFFFF;
-
-/* [RAM] Vector table dynamic copy: 8_byte_aligned(69 vect * 4 bytes) = 8_byte_aligned(0x0114) = 0x0118*/
-define symbol __NVIC_start__ = 0x10000000;
-define symbol __NVIC_end__ = 0x10000117;
-define symbol __region_RAM_start__ = 0x10000118;
-define symbol __region_RAM_end__ = 0x1001FFDF;
-define symbol _AHB_RAM_start__ = 0x20000000;
-define symbol _AHB_RAM_end__ = 0x20007FFF;
-
-/* Memory regions */
-define memory mem with size = 4G;
-
-define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-
-define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
-define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__];
-
-/* Stack and Heap */
-if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
- define symbol MBED_BOOT_STACK_SIZE = 0x400;
-}
-
-define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE;
-define symbol __size_heap__ = 0x8000;
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block STACKHEAP with fixed order { block HEAP, block CSTACK };
-
-initialize by copy with packing = zeros { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__intvec_start__ { section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite, block STACKHEAP };
-place in AHB_RAM_region { section USB_RAM };
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_IAR/startup_LPC43xx.S b/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_IAR/startup_LPC43xx.S
deleted file mode 100644
index 5bcb0670a0..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_IAR/startup_LPC43xx.S
+++ /dev/null
@@ -1,292 +0,0 @@
-/**************************************************
- *
- * Part one of the system initialization code, contains low-level
- * initialization, plain thumb variant.
- *
- * Copyright 2011 IAR Systems. All rights reserved.
- *
- * $Revision: 47876 $
- *
- **************************************************/
-
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
- PUBLIC __vector_table_0x1c
- PUBLIC __Vectors
- PUBLIC __Vectors_End
- PUBLIC __Vectors_Size
-
- DATA
-
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler
- DCD NMI_Handler
- DCD HardFault_Handler
- DCD MemManage_Handler
- DCD BusFault_Handler
- DCD UsageFault_Handler
-__vector_table_0x1c
- DCD 0
- DCD 0
- DCD 0
- DCD 0
- DCD SVC_Handler
- DCD DebugMon_Handler
- DCD 0
- DCD PendSV_Handler
- DCD SysTick_Handler
-
- ; External Interrupts
- DCD DAC_IRQHandler ; 16 D/A Converter
- DCD MX_CORE_IRQHandler ; 17 CortexM0 (LPC43XX ONLY)
- DCD DMA_IRQHandler ; 18 General Purpose DMA
- DCD 0 ; 19 Reserved
- DCD FLASHEEPROM_IRQHandler ; 20 ORed flash bank A, flash bank B, EEPROM interrupts
- DCD ETH_IRQHandler ; 21 Ethernet
- DCD SDIO_IRQHandler ; 22 SD/MMC
- DCD LCD_IRQHandler ; 23 LCD
- DCD USB0_IRQHandler ; 24 USB0
- DCD USB1_IRQHandler ; 25 USB1
- DCD SCT_IRQHandler ; 26 State Configurable Timer
- DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
- DCD TIMER0_IRQHandler ; 28 Timer0
- DCD TIMER1_IRQHandler ; 29 Timer1
- DCD TIMER2_IRQHandler ; 30 Timer2
- DCD TIMER3_IRQHandler ; 31 Timer3
- DCD MCPWM_IRQHandler ; 32 Motor Control PWM
- DCD ADC0_IRQHandler ; 33 A/D Converter 0
- DCD I2C0_IRQHandler ; 34 I2C0
- DCD I2C1_IRQHandler ; 35 I2C1
- DCD SPI_IRQHandler ; 36 SPI (LPC43XX ONLY)
- DCD ADC1_IRQHandler ; 37 A/D Converter 1
- DCD SSP0_IRQHandler ; 38 SSP0
- DCD SSP1_IRQHandler ; 39 SSP1
- DCD UART0_IRQHandler ; 40 UART0
- DCD UART1_IRQHandler ; 41 UART1
- DCD UART2_IRQHandler ; 42 UART2
- DCD UART3_IRQHandler ; 43 UART3
- DCD I2S0_IRQHandler ; 44 I2S0
- DCD I2S1_IRQHandler ; 45 I2S1
- DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
- DCD SGPIO_IRQHandler ; 47 SGPIO (LPC43XX ONLY)
- DCD GPIO0_IRQHandler ; 48 GPIO0
- DCD GPIO1_IRQHandler ; 49 GPIO1
- DCD GPIO2_IRQHandler ; 50 GPIO2
- DCD GPIO3_IRQHandler ; 51 GPIO3
- DCD GPIO4_IRQHandler ; 52 GPIO4
- DCD GPIO5_IRQHandler ; 53 GPIO5
- DCD GPIO6_IRQHandler ; 54 GPIO6
- DCD GPIO7_IRQHandler ; 55 GPIO7
- DCD GINT0_IRQHandler ; 56 GINT0
- DCD GINT1_IRQHandler ; 57 GINT1
- DCD EVRT_IRQHandler ; 58 Event Router
- DCD CAN1_IRQHandler ; 59 C_CAN1
- DCD 0
- DCD 0
- DCD ATIMER_IRQHandler ; 62 ATIMER
- DCD RTC_IRQHandler ; 63 RTC
- DCD 0
- DCD WDT_IRQHandler ; 65 WDT
- DCD 0
- DCD CAN0_IRQHandler ; 67 C_CAN0
- DCD QEI_IRQHandler ; 68 QEI
-__Vectors_End
-
-__Vectors EQU __vector_table
-__Vectors_Size EQU __Vectors_End - __Vectors
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- PUBWEAK HardFault_Handler
- PUBWEAK MemManage_Handler
- PUBWEAK BusFault_Handler
- PUBWEAK UsageFault_Handler
- PUBWEAK SVC_Handler
- PUBWEAK DebugMon_Handler
- PUBWEAK PendSV_Handler
- PUBWEAK SysTick_Handler
- PUBWEAK DAC_IRQHandler
- PUBWEAK MX_CORE_IRQHandler
- PUBWEAK DMA_IRQHandler
- PUBWEAK FLASHEEPROM_IRQHandler
- PUBWEAK ETH_IRQHandler
- PUBWEAK SDIO_IRQHandler
- PUBWEAK LCD_IRQHandler
- PUBWEAK USB0_IRQHandler
- PUBWEAK USB1_IRQHandler
- PUBWEAK SCT_IRQHandler
- PUBWEAK RIT_IRQHandler
- PUBWEAK TIMER0_IRQHandler
- PUBWEAK TIMER1_IRQHandler
- PUBWEAK TIMER2_IRQHandler
- PUBWEAK TIMER3_IRQHandler
- PUBWEAK MCPWM_IRQHandler
- PUBWEAK ADC0_IRQHandler
- PUBWEAK I2C0_IRQHandler
- PUBWEAK I2C1_IRQHandler
- PUBWEAK SPI_IRQHandler
- PUBWEAK ADC1_IRQHandler
- PUBWEAK SSP0_IRQHandler
- PUBWEAK SSP1_IRQHandler
- PUBWEAK UART0_IRQHandler
- PUBWEAK UART1_IRQHandler
- PUBWEAK UART2_IRQHandler
- PUBWEAK UART3_IRQHandler
- PUBWEAK I2S0_IRQHandler
- PUBWEAK I2S1_IRQHandler
- PUBWEAK SPIFI_IRQHandler
- PUBWEAK SGPIO_IRQHandler
- PUBWEAK GPIO0_IRQHandler
- PUBWEAK GPIO1_IRQHandler
- PUBWEAK GPIO2_IRQHandler
- PUBWEAK GPIO3_IRQHandler
- PUBWEAK GPIO4_IRQHandler
- PUBWEAK GPIO5_IRQHandler
- PUBWEAK GPIO6_IRQHandler
- PUBWEAK GPIO7_IRQHandler
- PUBWEAK GINT0_IRQHandler
- PUBWEAK GINT1_IRQHandler
- PUBWEAK EVRT_IRQHandler
- PUBWEAK CAN1_IRQHandler
- PUBWEAK ATIMER_IRQHandler
- PUBWEAK RTC_IRQHandler
- PUBWEAK WDT_IRQHandler
- PUBWEAK CAN0_IRQHandler
- PUBWEAK QEI_IRQHandler
- SECTION .text:CODE:REORDER(1)
-NMI_Handler
- B NMI_Handler
-SVC_Handler
- B SVC_Handler
-DebugMon_Handler
- B DebugMon_Handler
-PendSV_Handler
- B PendSV_Handler
-SysTick_Handler
- B SysTick_Handler
-HardFault_Handler
- B HardFault_Handler
-MemManage_Handler
- B MemManage_Handler
-BusFault_Handler
- B BusFault_Handler
-UsageFault_Handler
-DAC_IRQHandler
-MX_CORE_IRQHandler
-DMA_IRQHandler
-FLASHEEPROM_IRQHandler
-ETH_IRQHandler
-SDIO_IRQHandler
-LCD_IRQHandler
-USB0_IRQHandler
-USB1_IRQHandler
-SCT_IRQHandler
-RIT_IRQHandler
-TIMER0_IRQHandler
-TIMER1_IRQHandler
-TIMER2_IRQHandler
-TIMER3_IRQHandler
-MCPWM_IRQHandler
-ADC0_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-SPI_IRQHandler
-ADC1_IRQHandler
-SSP0_IRQHandler
-SSP1_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-I2S0_IRQHandler
-I2S1_IRQHandler
-SPIFI_IRQHandler
-SGPIO_IRQHandler
-GPIO0_IRQHandler
-GPIO1_IRQHandler
-GPIO2_IRQHandler
-GPIO3_IRQHandler
-GPIO4_IRQHandler
-GPIO5_IRQHandler
-GPIO6_IRQHandler
-GPIO7_IRQHandler
-GINT0_IRQHandler
-GINT1_IRQHandler
-EVRT_IRQHandler
-CAN1_IRQHandler
-ATIMER_IRQHandler
-RTC_IRQHandler
-WDT_IRQHandler
-CAN0_IRQHandler
-QEI_IRQHandler
-Default_IRQHandler
- B Default_IRQHandler
-
-/* CRP Section - not needed for flashless devices */
-
-;;; SECTION .crp:CODE:ROOT(2)
-;;; DATA
-/* Code Read Protection
-NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
-CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
- - Copy RAM to flash command can not write to Sector 0.
- - Erase command can erase Sector 0 only when all sectors
- are selected for erase.
- - Compare command is disabled.
- - Read Memory command is disabled.
-CRP2 0x87654321 - Read Memory is disabled.
- - Write to RAM is disabled.
- - "Go" command is disabled.
- - Copy RAM to flash is disabled.
- - Compare is disabled.
-CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
- by pulling PIO0_1 LOW is disabled if a valid user code is
- present in flash sector 0.
-Caution: If CRP3 is selected, no future factory testing can be
-performed on the device.
-*/
-;;; DCD 0xFFFFFFFF
-;;;
-
- END
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/device/cmsis.h b/targets/TARGET_NXP/TARGET_LPC43XX/device/cmsis.h
deleted file mode 100644
index 40d5b86a69..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/device/cmsis.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* mbed Microcontroller Library - CMSIS
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * A generic CMSIS include header, pulling in LPC43xx specifics
- *
- * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "LPC43xx.h"
-#include "cmsis_nvic.h"
-
-#endif
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/device/cmsis_nvic.h b/targets/TARGET_NXP/TARGET_LPC43XX/device/cmsis_nvic.h
deleted file mode 100644
index ff5f53492c..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/device/cmsis_nvic.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2011 ARM Limited. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of ARM Limited nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#define NVIC_NUM_VECTORS (16 + 53) // CORE + MCU Peripherals
-#define NVIC_RAM_VECTOR_ADDRESS 0x10000000 // Location of vectors in RAM
-
-#endif
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/device/system_LPC43xx.c b/targets/TARGET_NXP/TARGET_LPC43XX/device/system_LPC43xx.c
deleted file mode 100644
index e8d591a513..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/device/system_LPC43xx.c
+++ /dev/null
@@ -1,373 +0,0 @@
-/*
- * @brief LPC43xx System Initialization
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- *
- * Modified by Micromint USA <support@micromint.com>
- */
-#include "LPC43xx.h"
-
-#define COUNT_OF(a) (sizeof(a)/sizeof(a[0]))
-
-/* Clock variables */
-#if (CLOCK_SETUP)
-uint32_t SystemCoreClock = MAX_CLOCK_FREQ;
-#else
-uint32_t SystemCoreClock = CRYSTAL_MAIN_FREQ_IN;
-#endif
-
-#if !defined(CORE_M0)
-/* SCU pin definitions for pin muxing */
-typedef struct {
- __IO uint32_t *reg; /* SCU register address */
- uint16_t mode; /* SCU pin mode and function */
-} PINMUX_GRP_T;
-
-/* Pins to initialize before clocks are configured */
-static const PINMUX_GRP_T pre_clock_mux[] = {
- /* SPIFI pins */
- {SCU_REG(0x3, 3), (SCU_PINIO_FAST | 0x3)}, /* P3_3 SPIFI CLK */
- {SCU_REG(0x3, 4), (SCU_PINIO_FAST | 0x3)}, /* P3_4 SPIFI D3 */
- {SCU_REG(0x3, 5), (SCU_PINIO_FAST | 0x3)}, /* P3_5 SPIFI D2 */
- {SCU_REG(0x3, 6), (SCU_PINIO_FAST | 0x3)}, /* P3_6 SPIFI D1 */
- {SCU_REG(0x3, 7), (SCU_PINIO_FAST | 0x3)}, /* P3_7 SPIFI D0 */
- {SCU_REG(0x3, 8), (SCU_PINIO_FAST | 0x3)} /* P3_8 SPIFI CS/SSEL */
-};
-
-/* Pins to initialize after clocks are configured */
-static const PINMUX_GRP_T post_clock_mux[] = {
- /* Boot pins */
- {SCU_REG(0x1, 1), (SCU_PINIO_FAST | 0x0)}, /* P1_1 BOOT0 */
- {SCU_REG(0x1, 2), (SCU_PINIO_FAST | 0x0)}, /* P1_2 BOOT1 */
- {SCU_REG(0x2, 8), (SCU_PINIO_FAST | 0x0)}, /* P2_8 BOOT2 */
- {SCU_REG(0x2, 9), (SCU_PINIO_FAST | 0x0)}, /* P2_9 BOOT3 */
- /* Micromint Bambino 200/210 */
- {SCU_REG(0x6, 11), (SCU_PINIO_FAST | 0x0)}, /* P6_11 LED1 */
- {SCU_REG(0x2, 5), (SCU_PINIO_FAST | 0x0)}, /* P2_5 LED2 */
- {SCU_REG(0x2, 7), (SCU_PINIO_FAST | 0x0)}, /* P2_7 BTN1 */
- /* Micromint Bambino 210 */
- {SCU_REG(0x6, 1), (SCU_PINIO_FAST | 0x0)}, /* P6_1 LED3 */
- {SCU_REG(0x6, 2), (SCU_PINIO_FAST | 0x0)}, /* P6_2 LED4 */
-};
-
-#if (CLOCK_SETUP)
-/* Structure for initial base clock states */
-struct CLK_BASE_STATES {
- CGU_BASE_CLK_T clk; /* Base clock */
- CGU_CLKIN_T clkin; /* Base clock source */
- uint8_t powerdn; /* Set to 1 if base clock is initially powered down */
-};
-
-/* Initial base clock states are mostly on */
-static const struct CLK_BASE_STATES clock_states[] = {
- {CLK_BASE_SAFE, CLKIN_IRC, 0},
- {CLK_BASE_APB1, CLKIN_MAINPLL, 0},
- {CLK_BASE_APB3, CLKIN_MAINPLL, 0},
- {CLK_BASE_USB0, CLKIN_USBPLL, 1},
- {CLK_BASE_PERIPH, CLKIN_MAINPLL, 0},
- {CLK_BASE_SPI, CLKIN_MAINPLL, 0},
- {CLK_BASE_PHY_TX, CLKIN_ENET_TX, 0},
-#if defined(USE_RMII)
- {CLK_BASE_PHY_RX, CLKIN_ENET_TX, 0},
-#else
- {CLK_BASE_PHY_RX, CLKIN_ENET_RX, 0},
-#endif
- {CLK_BASE_SDIO, CLKIN_MAINPLL, 0},
- {CLK_BASE_SSP0, CLKIN_IDIVC, 0},
- {CLK_BASE_SSP1, CLKIN_IDIVC, 0},
- {CLK_BASE_UART0, CLKIN_MAINPLL, 0},
- {CLK_BASE_UART1, CLKIN_MAINPLL, 0},
- {CLK_BASE_UART2, CLKIN_MAINPLL, 0},
- {CLK_BASE_UART3, CLKIN_MAINPLL, 0},
- {CLK_BASE_OUT, CLKINPUT_PD, 0},
- {CLK_BASE_APLL, CLKINPUT_PD, 0},
- {CLK_BASE_CGU_OUT0, CLKINPUT_PD, 0},
- {CLK_BASE_CGU_OUT1, CLKINPUT_PD, 0},
-
- /* Clocks derived from dividers */
- {CLK_BASE_LCD, CLKIN_IDIVC, 0},
- {CLK_BASE_USB1, CLKIN_IDIVD, 1}
-};
-#endif /* defined(CLOCK_SETUP) */
-
-/* Local functions */
-static uint32_t SystemGetMainPLLHz(void);
-static void SystemSetupClock(void);
-static void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n);
-static void SystemSetupMemory(void);
-static void WaitUs(uint32_t us);
-
-#endif /* !defined(CORE_M0) */
-
-/*
- * SystemInit() - Initialize the system
- */
-void SystemInit(void)
-{
-#if !defined(CORE_M0)
-
- /* Initialize vector table in flash */
-#if defined(__ARMCC_VERSION)
- extern void *__Vectors;
-
- SCB->VTOR = (unsigned int) &__Vectors;
-#elif defined(__IAR_SYSTEMS_ICC__)
- extern void *__vector_table;
-
- SCB->VTOR = (unsigned int) &__vector_table;
-#elif defined(TOOLCHAIN_GCC_ARM)
- extern void *__isr_vector;
-
- SCB->VTOR = (unsigned int) &__isr_vector;
-#else /* defined(__GNUC__) and others */
- extern void *g_pfnVectors;
-
- SCB->VTOR = (unsigned int) &g_pfnVectors;
-#endif
-
-#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
- /* Initialize floating point */
- fpuInit();
-#endif
-
- SystemSetupPins(pre_clock_mux, COUNT_OF(pre_clock_mux)); /* Configure pins */
- SystemSetupClock(); /* Configure processor and peripheral clocks */
- SystemSetupPins(post_clock_mux, COUNT_OF(post_clock_mux)); /* Configure pins */
- SystemSetupMemory(); /* Configure external memory */
-#endif /* !defined(CORE_M0) */
-
- SystemCoreClockUpdate(); /* Update SystemCoreClock variable */
-}
-
-/*
- * SystemCoreClockUpdate() - Update SystemCoreClock variable
- */
-void SystemCoreClockUpdate(void)
-{
- uint32_t reg, div, rate;
-
- /* Get main PLL rate */
- rate = SystemGetMainPLLHz();
-
- /* Get clock divider */
- reg = LPC_CCU1->CLKCCU[CLK_MX_MXCORE].CFG;
- if (((reg >> 5) & 0x7) == 0) {
- div = 1;
- }
- else {
- div = 2;
- }
- rate = rate / div;
-
- SystemCoreClock = rate;
-}
-
-/* Returns the frequency of the main PLL */
-uint32_t SystemGetMainPLLHz(void)
-{
- uint32_t PLLReg = LPC_CGU->PLL1_CTRL;
- uint32_t freq = CRYSTAL_MAIN_FREQ_IN;
- uint32_t msel, nsel, psel, direct, fbsel;
- uint32_t m, n, p;
- const uint8_t ptab[] = {1, 2, 4, 8};
-
- msel = (PLLReg >> 16) & 0xFF;
- nsel = (PLLReg >> 12) & 0x3;
- psel = (PLLReg >> 8) & 0x3;
- direct = (PLLReg >> 7) & 0x1;
- fbsel = (PLLReg >> 6) & 0x1;
-
- m = msel + 1;
- n = nsel + 1;
- p = ptab[psel];
-
- if (direct || fbsel) {
- return m * (freq / n);
- }
-
- return (m / (2 * p)) * (freq / n);
-}
-
-#if !defined(CORE_M0)
-/*
- * SystemSetupClock() - Set processor and peripheral clocks
- *
- * Clock Frequency Source
- * CLK_BASE_MX 204 MHz CLKIN_MAINPLL (CLKIN_PLL1)
- * CLK_BASE_SPIFI 102 MHz CLKIN_IDIVE
- * CLK_BASE_USB0 480 MHz CLKIN_USBPLL (Disabled) (CLKIN_PLL0USB)
- * CLK_BASE_USB1 60 MHz CLKIN_IDIVE (Disabled)
- * 120 MHz CLKIN_IDIVD (Disabled)
- *
- * 12 MHz CLKIN_IDIVB
- * 12 MHz CLKIN_IDIVC
- *
- */
-void SystemSetupClock(void)
-{
-#if (CLOCK_SETUP)
- uint32_t i;
-
- /* Switch main clock to Internal RC (IRC) while setting up PLL1 */
- LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_IRC << 24);
- /* Set prescaler/divider on SSP1 assuming 204 MHz clock */
- LPC_SSP1->CR1 &= ~(1 << 1);
- LPC_SSP1->CPSR = 0x0002;
- LPC_SSP1->CR0 = 0x00006507;
- LPC_SSP1->CR1 |= (1 << 1);
-
- /* Enable the oscillator and wait 100 us */
- LPC_CGU->XTAL_OSC_CTRL = 0;
- WaitUs(100);
-
-#if (SPIFI_INIT)
- /* Setup SPIFI control register and no-opcode mode */
- LPC_SPIFI->CTRL = (0x100 << 0) | (1 << 16) | (1 << 29) | (1 << 30);
- LPC_SPIFI->IDATA = 0xA5;
- /* Switch IDIVE clock to IRC and connect to SPIFI clock */
- LPC_CGU->IDIV_CTRL[CLK_IDIV_E] = ((1 << 11) | (CLKIN_IRC << 24));
- LPC_CGU->BASE_CLK[CLK_BASE_SPIFI] = ((1 << 11) | (CLKIN_IDIVE << 24));
-#endif /* SPIFI_INIT */
-
- /* Configure PLL1 (MAINPLL) for main clock */
- LPC_CGU->PLL1_CTRL |= 1; /* Power down PLL1 */
-
- /* Change PLL1 to 108 Mhz (msel=9, 12 MHz*9=108 MHz) */
- LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (8 << 16)
- | (CLKIN_MAINPLL << 24);
- while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
- WaitUs(100);
-
- /* Change PLL1 to 204 Mhz (msel=17, 12 MHz*17=204 MHz) */
- LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (16 << 16)
- | (CLKIN_MAINPLL << 24);
- while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
-
- /* Connect main clock to PLL1 */
- LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_MAINPLL << 24);
-
- /* Set USB PLL dividers for 480 MHz (for USB0) */
- LPC_CGU->PLL[CGU_USB_PLL].PLL_MDIV = 0x06167FFA;
- LPC_CGU->PLL[CGU_USB_PLL].PLL_NP_DIV = 0x00302062;
- LPC_CGU->PLL[CGU_USB_PLL].PLL_CTRL = 0x0000081D | (CLKIN_CRYSTAL << 24);
-
- /* Set IDIVE clock to PLL1/2 = 102 MHz */
- LPC_CGU->IDIV_CTRL[CLK_IDIV_E] = (1 << 2) | (1 << 11) | (CLKIN_MAINPLL << 24); /* PLL1/2 */
-
- /* Set IDIVD clock to ((USBPLL/4) / 2) = 60 MHz (for USB1) */
- LPC_CGU->IDIV_CTRL[CLK_IDIV_A] = (3 << 2) | (1 << 11) | (CLKIN_USBPLL << 24); /* USBPLL/4 */
- LPC_CGU->IDIV_CTRL[CLK_IDIV_D] = (1 << 2) | (1 << 11) | (CLKIN_IDIVA << 24); /* IDIVA/2 */
-
- /* Configure remaining integer dividers */
- LPC_CGU->IDIV_CTRL[CLK_IDIV_B] = (0 << 2) | (1 << 11) | (CLKIN_IRC << 24); /* IRC */
- LPC_CGU->IDIV_CTRL[CLK_IDIV_C] = (1 << 2) | (1 << 11) | (CLKIN_MAINPLL << 24); /* PLL1/2 */
-
- /* Connect base clocks */
- for (i = 0; i < COUNT_OF(clock_states); i++) {
- LPC_CGU->BASE_CLK[clock_states[i].clk] =
- ( clock_states[i].powerdn << 0)
- | (1 << 11) | (clock_states[i].clkin << 24);
- }
-#endif /* CLOCK_SETUP */
- /* Reset peripherals */
- LPC_RGU->RESET_CTRL0 = 0x105F0000;
- LPC_RGU->RESET_CTRL1 = 0x01DFF7FF;
-}
-
-/*
- * SystemSetupPins() - Configure MCU pins
- */
-void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n)
-{
- uint32_t i;
-
- for (i = 0; i < n; i++) {
- *(mux[i].reg) = mux[i].mode;
- }
-}
-
-/*
- * SystemSetupMemory() - Configure external memory
- */
-void SystemSetupMemory(void)
-{
-#if (MEMORY_SETUP)
- /* None required for boards without external memory */
-#endif /* MEMORY_SETUP */
-}
-
-#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
-/*
- * fpuInit() - Early initialization of the FPU
- */
-void fpuInit(void)
-{
- /*
- * from ARM TRM manual:
- * ; CPACR is located at address 0xE000ED88
- * LDR.W R0, =0xE000ED88
- * ; Read CPACR
- * LDR R1, [R0]
- * ; Set bits 20-23 to enable CP10 and CP11 coprocessors
- * ORR R1, R1, #(0xF << 20)
- * ; Write back the modified value to the CPACR
- * STR R1, [R0]
- */
-
- volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
- volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
- volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
- volatile uint32_t Cpacr;
- volatile uint32_t Mvfr0;
- volatile uint32_t Mvfr1;
- char vfpPresent = 0;
-
- Mvfr0 = *regMvfr0;
- Mvfr1 = *regMvfr1;
-
- vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
-
- if (vfpPresent) {
- Cpacr = *regCpacr;
- Cpacr |= (0xF << 20);
- *regCpacr = Cpacr; /* enable CP10 and CP11 for full access */
- }
-}
-#endif /* defined(__FPU_PRESENT) && __FPU_PRESENT == 1 */
-
-/* Approximate delay function */
-#define CPU_NANOSEC(x) (((uint64_t) (x) * SystemCoreClock) / 1000000000)
-
-static void WaitUs(uint32_t us)
-{
- volatile uint32_t cyc = us * CPU_NANOSEC(1000) / 4;
- while (cyc--)
- ;
-}
-
-#endif /* !defined(CORE_M0) */
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/device/system_LPC43xx.h b/targets/TARGET_NXP/TARGET_LPC43XX/device/system_LPC43xx.h
deleted file mode 100644
index dcea2ffd4a..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/device/system_LPC43xx.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * @brief LPC43xx/LPC18xx mcu header
- *
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SYSTEM_LPC43XX_H
-#define __SYSTEM_LPC43XX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* System initialization options */
-#define PIN_SETUP 1 /* Configure pins during initialization */
-#define CLOCK_SETUP 1 /* Configure clocks during initialization */
-#define MEMORY_SETUP 0 /* Configure external memory during init */
-#define SPIFI_INIT 1 /* Initialize SPIFI */
-
-/* Crystal frequency into device */
-#define CRYSTAL_MAIN_FREQ_IN 12000000
-
-/* Crystal frequency into device for RTC/32K input */
-#define CRYSTAL_32K_FREQ_IN 32768
-
-/* Default CPU clock frequency */
-#if defined(CHIP_LPC43XX)
-#define MAX_CLOCK_FREQ (204000000)
-#else
-#define MAX_CLOCK_FREQ (180000000)
-#endif
-
-#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
- /* FPU declarations */
- #define LPC_CPACR 0xE000ED88
-
- #define SCB_MVFR0 0xE000EF40
- #define SCB_MVFR0_RESET 0x10110021
-
- #define SCB_MVFR1 0xE000EF44
- #define SCB_MVFR1_RESET 0x11000011
-
- #if defined(__ARMCC_VERSION)
- void fpuInit(void) __attribute__ ((section("BOOTSTRAP_CODE")));
- #else
- extern void fpuInit(void);
- #endif
-#endif
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-extern void SystemCoreClockUpdate(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC43XX_H */
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/gpio_api.c b/targets/TARGET_NXP/TARGET_LPC43XX/gpio_api.c
deleted file mode 100644
index 7c27b19661..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/gpio_api.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
- */
-#include "mbed_assert.h"
-#include "gpio_api.h"
-#include "pinmap.h"
-
-uint32_t gpio_set(PinName pin) {
- MBED_ASSERT(pin != (PinName)NC);
- int f = 0;
- unsigned int port = (unsigned int)MBED_GPIO_PORT(pin);
-
- f = SCU_PINIO_FAST | ((port > 4) ? (4) : (0));
- pin_function(pin, f);
-
- return (1 << ((int)pin & 0x1F));
-}
-
-void gpio_init(gpio_t *obj, PinName pin) {
- obj->pin = pin;
- if (pin == (PinName)NC)
- return;
-
- obj->mask = gpio_set(pin);
-
- LPC_GPIO_T *port_reg = (LPC_GPIO_T *)(LPC_GPIO_PORT_BASE);
- unsigned int port = (unsigned int)MBED_GPIO_PORT(pin);
-
- obj->reg_set = &port_reg->SET[port];
- obj->reg_clr = &port_reg->CLR[port];
- obj->reg_in = &port_reg->PIN[port];
- obj->reg_dir = &port_reg->DIR[port];
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode) {
- pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction) {
- MBED_ASSERT(obj->pin != (PinName)NC);
- switch (direction) {
- case PIN_INPUT :
- *obj->reg_dir &= ~obj->mask;
- break;
- case PIN_OUTPUT:
- *obj->reg_dir |= obj->mask;
- break;
- }
-}
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/gpio_irq_api.c b/targets/TARGET_NXP/TARGET_LPC43XX/gpio_irq_api.c
deleted file mode 100644
index 11979304ae..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/gpio_irq_api.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
- */
-#include <stddef.h>
-#include "gpio_irq_api.h"
-#include "mbed_error.h"
-#include "cmsis.h"
-
-/* The LPC43xx implements GPIO pin and group interrupts. Any pin in the
- * 8 32-bit GPIO ports can interrupt. On group interrupts a pin can
- * only interrupt on the rising or falling edge, not both as required
- * by mbed. Also, group interrupts can't be cleared individually.
- * This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
- * A future implementation may provide group interrupt support.
- */
-#if !defined(CORE_M0)
-#define CHANNEL_MAX 8
-#else
-#define CHANNEL_MAX 1
-#endif
-
-static uint32_t channel_ids[CHANNEL_MAX] = {0};
-static uint8_t channel = 0;
-static gpio_irq_handler irq_handler;
-
-static void handle_interrupt_in(void) {
- uint32_t rise = LPC_GPIO_PIN_INT->RISE;
- uint32_t fall = LPC_GPIO_PIN_INT->FALL;
- uint32_t pmask;
- int i;
-
- for (i = 0; i < CHANNEL_MAX; i++) {
- pmask = (1 << i);
- if (rise & pmask) {
- /* Rising edge interrupts */
- if (channel_ids[i] != 0) {
- irq_handler(channel_ids[i], IRQ_RISE);
- }
- /* Clear rising edge detected */
- LPC_GPIO_PIN_INT->RISE = pmask;
- }
- if (fall & pmask) {
- /* Falling edge interrupts */
- if (channel_ids[i] != 0) {
- irq_handler(channel_ids[i], IRQ_FALL);
- }
- /* Clear falling edge detected */
- LPC_GPIO_PIN_INT->FALL = pmask;
- }
- }
-}
-
-int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
- uint32_t portnum, pinnum; //, pmask;
-
- if (pin == NC) return -1;
-
- irq_handler = handler;
-
- /* Set port and pin numbers */
- obj->port = portnum = MBED_GPIO_PORT(pin);
- obj->pin = pinnum = MBED_GPIO_PIN(pin);
-
- /* Add to channel table */
- channel_ids[channel] = id;
- obj->ch = channel;
-
- /* Clear rising and falling edge detection */
- //pmask = (1 << channel);
- //LPC_GPIO_PIN_INT->IST = pmask;
-
- /* Set SCU */
- if (channel < 4) {
- LPC_SCU->PINTSEL0 &= ~(0xFF << (portnum << 3));
- LPC_SCU->PINTSEL0 |= (((portnum << 5) | pinnum) << (channel << 3));
- } else {
- LPC_SCU->PINTSEL1 &= ~(0xFF << ((portnum - 4) << 3));
- LPC_SCU->PINTSEL1 |= (((portnum << 5) | pinnum) << ((channel - 4) << 3));
- }
-
-#if !defined(CORE_M0)
- NVIC_SetVector((IRQn_Type)(PIN_INT0_IRQn + channel), (uint32_t)handle_interrupt_in);
- NVIC_EnableIRQ((IRQn_Type)(PIN_INT0_IRQn + channel));
-#else
- NVIC_SetVector((IRQn_Type)PIN_INT4_IRQn, (uint32_t)handle_interrupt_in);
- NVIC_EnableIRQ((IRQn_Type)PIN_INT4_IRQn);
-#endif
-
- // Increment channel number
- channel++;
- channel %= CHANNEL_MAX;
-
- return 0;
-}
-
-void gpio_irq_free(gpio_irq_t *obj) {
- channel_ids[obj->ch] = 0;
-}
-
-void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
- uint32_t pmask;
-
- /* Clear pending interrupts */
- pmask = (1 << obj->ch);
- LPC_GPIO_PIN_INT->IST = pmask;
-
- /* Configure pin interrupt */
- LPC_GPIO_PIN_INT->ISEL &= ~pmask;
- if (event == IRQ_RISE) {
- /* Rising edge interrupts */
- if (enable) {
- LPC_GPIO_PIN_INT->SIENR |= pmask;
- } else {
- LPC_GPIO_PIN_INT->CIENR |= pmask;
- }
- } else {
- /* Falling edge interrupts */
- if (enable) {
- LPC_GPIO_PIN_INT->SIENF |= pmask;
- } else {
- LPC_GPIO_PIN_INT->CIENF |= pmask;
- }
- }
-}
-
-void gpio_irq_enable(gpio_irq_t *obj) {
-#if !defined(CORE_M0)
- NVIC_EnableIRQ((IRQn_Type)(PIN_INT0_IRQn + obj->ch));
-#else
- NVIC_EnableIRQ((IRQn_Type)(PIN_INT4_IRQn + obj->ch));
-#endif
-}
-
-void gpio_irq_disable(gpio_irq_t *obj) {
-#if !defined(CORE_M0)
- NVIC_DisableIRQ((IRQn_Type)(PIN_INT0_IRQn + obj->ch));
-#else
- NVIC_DisableIRQ((IRQn_Type)(PIN_INT4_IRQn + obj->ch));
-#endif
-}
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/gpio_object.h b/targets/TARGET_NXP/TARGET_LPC43XX/gpio_object.h
deleted file mode 100644
index fe6d6c1e05..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/gpio_object.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
-
- __IO uint32_t *reg_dir;
- __IO uint32_t *reg_set;
- __IO uint32_t *reg_clr;
- __I uint32_t *reg_in;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value) {
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (value)
- *obj->reg_set = obj->mask;
- else
- *obj->reg_clr = obj->mask;
-}
-
-static inline int gpio_read(gpio_t *obj) {
- MBED_ASSERT(obj->pin != (PinName)NC);
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-static inline int gpio_is_connected(const gpio_t *obj) {
- return obj->pin != (PinName)NC;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC43XX/i2c_api.c
deleted file mode 100644
index 3103423740..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/i2c_api.c
+++ /dev/null
@@ -1,426 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
- */
-#include "i2c_api.h"
-
-#if DEVICE_I2C
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-// SCU mode for I2C SCL/SDA pins
-#define SCU_PINIO_I2C SCU_PINIO_PULLNONE
-
-static const PinMap PinMap_I2C_SDA[] = {
- {P_DED, I2C_0, 0},
- {P2_3, I2C_1, (SCU_PINIO_I2C | 1)},
- {PE_13, I2C_1, (SCU_PINIO_I2C | 2)},
- {NC, NC, 0}
-};
-
-static const PinMap PinMap_I2C_SCL[] = {
- {P_DED, I2C_0, 0},
- {P2_4, I2C_1, (SCU_PINIO_I2C | 1)},
- {PE_14, I2C_1, (SCU_PINIO_I2C | 2)},
- {NC, NC, 0}
-};
-
-#define I2C_CONSET(x) (x->i2c->CONSET)
-#define I2C_CONCLR(x) (x->i2c->CONCLR)
-#define I2C_STAT(x) (x->i2c->STAT)
-#define I2C_DAT(x) (x->i2c->DAT)
-#define I2C_SCLL(x, val) (x->i2c->SCLL = val)
-#define I2C_SCLH(x, val) (x->i2c->SCLH = val)
-
-static const uint32_t I2C_addr_offset[2][4] = {
- {0x0C, 0x20, 0x24, 0x28},
- {0x30, 0x34, 0x38, 0x3C}
-};
-
-static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
- I2C_CONCLR(obj) = (start << 5)
- | (stop << 4)
- | (interrupt << 3)
- | (acknowledge << 2);
-}
-
-static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
- I2C_CONSET(obj) = (start << 5)
- | (stop << 4)
- | (interrupt << 3)
- | (acknowledge << 2);
-}
-
-// Clear the Serial Interrupt (SI)
-static inline void i2c_clear_SI(i2c_t *obj) {
- i2c_conclr(obj, 0, 0, 1, 0);
-}
-
-static inline int i2c_status(i2c_t *obj) {
- return I2C_STAT(obj);
-}
-
-// Wait until the Serial Interrupt (SI) is set
-static int i2c_wait_SI(i2c_t *obj) {
- int timeout = 0;
- while (!(I2C_CONSET(obj) & (1 << 3))) {
- timeout++;
- if (timeout > 100000) return -1;
- }
- return 0;
-}
-
-static inline void i2c_interface_enable(i2c_t *obj) {
- I2C_CONSET(obj) = 0x40;
-}
-
-void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
- // determine the SPI to use
- I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
- I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
- obj->i2c = (LPC_I2C_T *)pinmap_merge(i2c_sda, i2c_scl);
-
- if ((int)obj->i2c == NC) {
- error("I2C pin mapping failed");
- }
-
- // set default frequency at 100k
- i2c_frequency(obj, 100000);
- i2c_conclr(obj, 1, 1, 1, 1);
- i2c_interface_enable(obj);
-
- // Set SCU functions
- if (scl == P_DED) {
- // Enable dedicated I2C0 SDA and SCL pins (open drain)
- LPC_SCU->SFSI2C0 = (1 << 11) | (1 << 3);
- } else {
- pinmap_pinout(sda, PinMap_I2C_SDA);
- pinmap_pinout(scl, PinMap_I2C_SCL);
- }
-}
-
-inline int i2c_start(i2c_t *obj) {
- int status = 0;
- int isInterrupted = I2C_CONSET(obj) & (1 << 3);
-
- // 8.1 Before master mode can be entered, I2CON must be initialised to:
- // - I2EN STA STO SI AA - -
- // - 1 0 0 x x - -
- // if AA = 0, it can't enter slave mode
- i2c_conclr(obj, 1, 1, 0, 1);
-
- // The master mode may now be entered by setting the STA bit
- // this will generate a start condition when the bus becomes free
- i2c_conset(obj, 1, 0, 0, 1);
- // Clearing SI bit when it wasn't set on entry can jump past state
- // 0x10 or 0x08 and erroneously send uninitialized slave address.
- if (isInterrupted)
- i2c_clear_SI(obj);
-
- i2c_wait_SI(obj);
- status = i2c_status(obj);
-
- // Clear start bit now that it's transmitted
- i2c_conclr(obj, 1, 0, 0, 0);
- return status;
-}
-
-inline int i2c_stop(i2c_t *obj) {
- int timeout = 0;
-
- // write the stop bit
- i2c_conset(obj, 0, 1, 0, 0);
- i2c_clear_SI(obj);
-
- // wait for STO bit to reset
- while(I2C_CONSET(obj) & (1 << 4)) {
- timeout ++;
- if (timeout > 100000) return 1;
- }
-
- return 0;
-}
-
-static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
- // write the data
- I2C_DAT(obj) = value;
-
- // clear SI to init a send
- i2c_clear_SI(obj);
-
- // wait and return status
- i2c_wait_SI(obj);
- return i2c_status(obj);
-}
-
-static inline int i2c_do_read(i2c_t *obj, int last) {
- // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
- if(last) {
- i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
- } else {
- i2c_conset(obj, 0, 0, 0, 1); // send a ACK
- }
-
- // accept byte
- i2c_clear_SI(obj);
-
- // wait for it to arrive
- i2c_wait_SI(obj);
-
- // return the data
- return (I2C_DAT(obj) & 0xFF);
-}
-
-void i2c_frequency(i2c_t *obj, int hz) {
- // [TODO] set pclk to /4
- uint32_t PCLK = SystemCoreClock / 4;
-
- uint32_t pulse = PCLK / (hz * 2);
-
- // I2C Rate
- I2C_SCLL(obj, pulse);
- I2C_SCLH(obj, pulse);
-}
-
-// The I2C does a read or a write as a whole operation
-// There are two types of error conditions it can encounter
-// 1) it can not obtain the bus
-// 2) it gets error responses at part of the transmission
-//
-// We tackle them as follows:
-// 1) we retry until we get the bus. we could have a "timeout" if we can not get it
-// which basically turns it in to a 2)
-// 2) on error, we use the standard error mechanisms to report/debug
-//
-// Therefore an I2C transaction should always complete. If it doesn't it is usually
-// because something is setup wrong (e.g. wiring), and we don't need to programatically
-// check for that
-
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
- int count, status;
-
- status = i2c_start(obj);
-
- if ((status != 0x10) && (status != 0x08)) {
- i2c_stop(obj);
- return I2C_ERROR_BUS_BUSY;
- }
-
- status = i2c_do_write(obj, (address | 0x01), 1);
- if (status != 0x40) {
- i2c_stop(obj);
- return I2C_ERROR_NO_SLAVE;
- }
-
- // Read in all except last byte
- for (count = 0; count < (length - 1); count++) {
- int value = i2c_do_read(obj, 0);
- status = i2c_status(obj);
- if (status != 0x50) {
- i2c_stop(obj);
- return count;
- }
- data[count] = (char) value;
- }
-
- // read in last byte
- int value = i2c_do_read(obj, 1);
- status = i2c_status(obj);
- if (status != 0x58) {
- i2c_stop(obj);
- return length - 1;
- }
-
- data[count] = (char) value;
-
- // If not repeated start, send stop.
- if (stop) {
- i2c_stop(obj);
- }
-
- return length;
-}
-
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
- int i, status;
-
- status = i2c_start(obj);
-
- if ((status != 0x10) && (status != 0x08)) {
- i2c_stop(obj);
- return I2C_ERROR_BUS_BUSY;
- }
-
- status = i2c_do_write(obj, (address & 0xFE), 1);
- if (status != 0x18) {
- i2c_stop(obj);
- return I2C_ERROR_NO_SLAVE;
- }
-
- for (i=0; i<length; i++) {
- status = i2c_do_write(obj, data[i], 0);
- if(status != 0x28) {
- i2c_stop(obj);
- return i;
- }
- }
-
- // clearing the serial interrupt here might cause an unintended rewrite of the last byte
- // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
- // i2c_clear_SI(obj);
-
- // If not repeated start, send stop.
- if (stop) {
- i2c_stop(obj);
- }
-
- return length;
-}
-
-void i2c_reset(i2c_t *obj) {
- i2c_stop(obj);
-}
-
-int i2c_byte_read(i2c_t *obj, int last) {
- return (i2c_do_read(obj, last) & 0xFF);
-}
-
-int i2c_byte_write(i2c_t *obj, int data) {
- int ack;
- int status = i2c_do_write(obj, (data & 0xFF), 0);
-
- switch(status) {
- case 0x18: case 0x28: // Master transmit ACKs
- ack = 1;
- break;
- case 0x40: // Master receive address transmitted ACK
- ack = 1;
- break;
- case 0xB8: // Slave transmit ACK
- ack = 1;
- break;
- default:
- ack = 0;
- break;
- }
-
- return ack;
-}
-
-void i2c_slave_mode(i2c_t *obj, int enable_slave) {
- if (enable_slave != 0) {
- i2c_conclr(obj, 1, 1, 1, 0);
- i2c_conset(obj, 0, 0, 0, 1);
- } else {
- i2c_conclr(obj, 1, 1, 1, 1);
- }
-}
-
-int i2c_slave_receive(i2c_t *obj) {
- int status;
- int retval;
-
- status = i2c_status(obj);
- switch(status) {
- case 0x60: retval = 3; break;
- case 0x70: retval = 2; break;
- case 0xA8: retval = 1; break;
- default : retval = 0; break;
- }
-
- return(retval);
-}
-
-int i2c_slave_read(i2c_t *obj, char *data, int length) {
- int count = 0;
- int status;
-
- do {
- i2c_clear_SI(obj);
- i2c_wait_SI(obj);
- status = i2c_status(obj);
- if((status == 0x80) || (status == 0x90)) {
- data[count] = I2C_DAT(obj) & 0xFF;
- }
- count++;
- } while (((status == 0x80) || (status == 0x90) ||
- (status == 0x060) || (status == 0x70)) && (count < length));
-
- if(status != 0xA0) {
- i2c_stop(obj);
- }
-
- i2c_clear_SI(obj);
-
- return count;
-}
-
-int i2c_slave_write(i2c_t *obj, const char *data, int length) {
- int count = 0;
- int status;
-
- if(length <= 0) {
- return(0);
- }
-
- do {
- status = i2c_do_write(obj, data[count], 0);
- count++;
- } while ((count < length) && (status == 0xB8));
-
- if ((status != 0xC0) && (status != 0xC8)) {
- i2c_stop(obj);
- }
-
- i2c_clear_SI(obj);
-
- return(count);
-}
-
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
- uint32_t addr;
-
- if ((idx >= 0) && (idx <= 3)) {
- addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
- *((uint32_t *) addr) = address & 0xFF;
- addr = ((uint32_t)obj->i2c) + I2C_addr_offset[1][idx];
- *((uint32_t *) addr) = mask & 0xFE;
- }
-}
-
-const PinMap *i2c_master_sda_pinmap()
-{
- return PinMap_I2C_SDA;
-}
-
-const PinMap *i2c_master_scl_pinmap()
-{
- return PinMap_I2C_SCL;
-}
-
-const PinMap *i2c_slave_sda_pinmap()
-{
- return PinMap_I2C_SDA;
-}
-
-const PinMap *i2c_slave_scl_pinmap()
-{
- return PinMap_I2C_SCL;
-}
-
-#endif // #if DEVICE_I2C
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/objects.h b/targets/TARGET_NXP/TARGET_LPC43XX/objects.h
deleted file mode 100644
index 189b1b5aa5..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/objects.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
- uint32_t port;
- uint32_t pin;
- uint32_t ch;
-};
-
-struct port_s {
- __IO uint32_t *reg_dir;
- __IO uint32_t *reg_out;
- __I uint32_t *reg_in;
- PortName port;
- uint32_t mask;
-};
-
-struct pwmout_s {
- PWMName pwm;
- uint8_t mr;
-};
-
-struct serial_s {
- LPC_USART_T *uart;
- int index;
-};
-
-struct analogin_s {
- LPC_ADC_T *adc;
- uint8_t num;
- uint8_t ch;
-};
-
-struct dac_s {
- DACName dac;
-};
-
-struct can_s {
- LPC_CCAN_T *dev;
-};
-
-struct i2c_s {
- LPC_I2C_T *i2c;
-};
-
-struct spi_s {
- LPC_SSP_T *spi;
-};
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/pinmap.c b/targets/TARGET_NXP/TARGET_LPC43XX/pinmap.c
deleted file mode 100644
index fd3ff7532e..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/pinmap.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
- */
-#include "mbed_assert.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-void pin_function(PinName pin, int function) {
- MBED_ASSERT(pin != (PinName)NC);
-
- __IO uint32_t *reg = (__IO uint32_t*) MBED_SCU_REG(pin);
-
- // Set pin function
- *reg = function;
-}
-
-void pin_mode(PinName pin, PinMode mode) {
- MBED_ASSERT(pin != (PinName)NC); // && (mode != OpenDrain));
-
- __IO uint32_t *reg = (__IO uint32_t*) MBED_SCU_REG(pin);
- uint32_t tmp = *reg;
-
- // pin mode bits: [4:3] -> 11000 = (0x3 << 3)
- tmp &= ~(0x3 << 3);
- tmp |= (mode & 0x3) << 3;
-
- *reg = tmp;
-}
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/port_api.c b/targets/TARGET_NXP/TARGET_LPC43XX/port_api.c
deleted file mode 100644
index b25ec5d816..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/port_api.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
- */
-#include "mbed_assert.h"
-#include "port_api.h"
-#include "pinmap.h"
-#include "gpio_api.h"
-
-// Lookup table to determine SCU offset for GPIO [port][pin]
-// Supports eight 16-bit ports to limit table size
-#define _SO(MBED_PIN) (MBED_PIN >> 18)
-
-static const uint8_t _scu_off[][16] =
-{ // GPIO0 to GPIO3
- { _SO(GPIO0_0), _SO(GPIO0_1), _SO(GPIO0_2), _SO(GPIO0_3),
- _SO(GPIO0_4), _SO(GPIO0_5), _SO(GPIO0_6), _SO(GPIO0_7),
- _SO(GPIO0_8), _SO(GPIO0_9), _SO(GPIO0_10), _SO(GPIO0_11),
- _SO(GPIO0_12), _SO(GPIO0_13), _SO(GPIO0_14), _SO(GPIO0_15)
- },
- { _SO(GPIO1_0), _SO(GPIO1_1), _SO(GPIO1_2), _SO(GPIO1_3),
- _SO(GPIO1_4), _SO(GPIO1_5), _SO(GPIO1_6), _SO(GPIO1_7),
- _SO(GPIO1_8), _SO(GPIO1_9), _SO(GPIO1_10), _SO(GPIO1_11),
- _SO(GPIO1_12), _SO(GPIO1_13), _SO(GPIO1_14), _SO(GPIO1_15)
- },
- { _SO(GPIO2_0), _SO(GPIO2_1), _SO(GPIO2_2), _SO(GPIO2_3),
- _SO(GPIO2_4), _SO(GPIO2_5), _SO(GPIO2_6), _SO(GPIO2_7),
- _SO(GPIO2_8), _SO(GPIO2_9), _SO(GPIO2_10), _SO(GPIO2_11),
- _SO(GPIO2_12), _SO(GPIO2_13), _SO(GPIO2_14), _SO(GPIO2_15)
- },
- { _SO(GPIO3_0), _SO(GPIO3_1), _SO(GPIO3_2), _SO(GPIO3_3),
- _SO(GPIO3_4), _SO(GPIO3_5), _SO(GPIO3_6), _SO(GPIO3_7),
- _SO(GPIO3_8), _SO(GPIO3_9), _SO(GPIO3_10), _SO(GPIO3_11),
- _SO(GPIO3_12), _SO(GPIO3_13), _SO(GPIO3_14), _SO(GPIO3_15)
- },
-};
-
-// Use alternate encoding for ports 4 to 7 so lookup stays within uint8
-#define _S2(MBED_PIN) (((MBED_PIN >> 19) & 0xf0) | ((MBED_PIN >> 18) & 0x0f))
-
-static const uint8_t _scu_off2[][16] =
-{ // GPIO4 to GPIO7
- { _S2(GPIO4_0), _S2(GPIO4_1), _S2(GPIO4_2), _S2(GPIO4_3),
- _S2(GPIO4_4), _S2(GPIO4_5), _S2(GPIO4_6), _S2(GPIO4_7),
- _S2(GPIO4_8), _S2(GPIO4_9), _S2(GPIO4_10), _S2(GPIO4_11),
- _S2(GPIO4_12), _S2(GPIO4_13), _S2(GPIO4_14), _S2(GPIO4_15)
- },
- { _S2(GPIO5_0), _S2(GPIO5_1), _S2(GPIO5_2), _S2(GPIO5_3),
- _S2(GPIO5_4), _S2(GPIO5_5), _S2(GPIO5_6), _S2(GPIO5_7),
- _S2(GPIO5_8), _S2(GPIO5_9), _S2(GPIO5_10), _S2(GPIO5_11),
- _S2(GPIO5_12), _S2(GPIO5_13), _S2(GPIO5_14), _S2(GPIO5_15)
- },
- { _S2(GPIO6_0), _S2(GPIO6_1), _S2(GPIO6_2), _S2(GPIO6_3),
- _S2(GPIO6_4), _S2(GPIO6_5), _S2(GPIO6_6), _S2(GPIO6_7),
- _S2(GPIO6_8), _S2(GPIO6_9), _S2(GPIO6_10), _S2(GPIO6_11),
- _S2(GPIO6_12), _S2(GPIO6_13), _S2(GPIO6_14), _S2(GPIO6_15)
- },
- { _S2(GPIO7_0), _S2(GPIO7_1), _S2(GPIO7_2), _S2(GPIO7_3),
- _S2(GPIO7_4), _S2(GPIO7_5), _S2(GPIO7_6), _S2(GPIO7_7),
- _S2(GPIO7_8), _S2(GPIO7_9), _S2(GPIO7_10), _S2(GPIO7_11),
- _S2(GPIO7_12), _S2(GPIO7_13), _S2(GPIO7_14), _S2(GPIO7_15)
- },
-};
-
-PinName port_pin(PortName port, int pin_n) {
- MBED_ASSERT((port <= Port7) && (pin_n < 32));
- int offset = 0;
-
- // Lookup table only maps pins 0 to 15
- if (pin_n > 15) {
- return NC;
- }
-
- // Lookup SCU offset
- if (port < Port4) {
- offset = _scu_off[port][pin_n];
- } else {
- offset = _scu_off2[port - Port4][pin_n];
- offset = ((offset & 0xf0) << 1) | (offset & 0x0f);
- }
-
- // Return pin name
- return (PinName)((offset << 18) | GPIO_OFF(port, pin_n));
-}
-
-void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
- obj->port = port;
- obj->mask = mask;
-
- LPC_GPIO_T *port_reg = (LPC_GPIO_T *)(LPC_GPIO_PORT_BASE);
-
- // Do not use masking, because it prevents the use of the unmasked pins
- // port_reg->MASK[port] = ~mask;
-
- obj->reg_out = &port_reg->PIN[port];
- obj->reg_in = &port_reg->PIN[port];
- obj->reg_dir = &port_reg->DIR[port];
-
- uint32_t i;
- // The function is set per pin: reuse gpio logic
- for (i=0; i<32; i++) {
- if (obj->mask & (1<<i)) {
- gpio_set(port_pin(obj->port, i));
- }
- }
-
- port_dir(obj, dir);
-}
-
-void port_mode(port_t *obj, PinMode mode) {
- uint32_t i;
- // The mode is set per pin: reuse pinmap logic
- for (i=0; i<32; i++) {
- if (obj->mask & (1<<i)) {
- pin_mode(port_pin(obj->port, i), mode);
- }
- }
-}
-
-void port_dir(port_t *obj, PinDirection dir) {
- switch (dir) {
- case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
- case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
- }
-}
-
-void port_write(port_t *obj, int value) {
- *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask);
-}
-
-int port_read(port_t *obj) {
- return (*obj->reg_in & obj->mask);
-}
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/pwmout_api.c b/targets/TARGET_NXP/TARGET_LPC43XX/pwmout_api.c
deleted file mode 100644
index 2bc52b3b41..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/pwmout_api.c
+++ /dev/null
@@ -1,276 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
- */
-#include "mbed_assert.h"
-#include "pwmout_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-// PWM implementation for the LPC43xx using State Configurable Timer (SCT)
-// * PWM_0 to PWM_15 on mbed use CTOUT_0 to CTOUT_15 outputs on LPC43xx
-// * Event 0 is PWM period, events 1 to PWM_EVENT_MAX are PWM channels
-// * Default is unified 32-bit timer, but could be configured to use
-// a 16-bit timer so a timer is available for other SCT functions
-
-// configuration options
-#define PWM_FREQ_BASE 1000000 // Base frequency 1 MHz = 1000000
-#ifndef PWM_MODE
- #define PWM_MODE 1 // 0 = 32-bit, 1 = 16-bit low, 2 = 16-bit high
-#endif
-
-// macros
-#define PWM_SETCOUNT(x) (x - 1) // set count value
-#define PWM_GETCOUNT(x) (x + 1) // get count value
-#if (PWM_MODE == 0) // unified 32-bit counter, events 1 to 15
- #define PWM_EVENT_MAX (CONFIG_SCT_nEV - 1) // Max PWM channels
- #define PWM_CONFIG SCT_CONFIG_32BIT_COUNTER // default config
- #define PWM_CTRL &LPC_SCT->CTRL_U // control register
- #define PWM_HALT SCT_CTRL_HALT_L // halt counter
- #define PWM_CLEAR SCT_CTRL_CLRCTR_L // clock clear
- #define PWM_PRE(x) SCT_CTRL_PRE_L(x) // clock prescale
- #define PWM_EVT_MASK (1 << 12) // event control mask
- #define PWM_LIMIT &LPC_SCT->LIMIT_L // limit register
- #define PWM_MATCH(x) &LPC_SCT->MATCH[x].U // match register
- #define PWM_MR(x) &LPC_SCT->MATCHREL[x].U // 32-bit match reload register
-#elif (PWM_MODE == 1) // 16-bit low counter, events 1 to 7
- #define PWM_EVENT_MAX (CONFIG_SCT_nEV/2 - 1) // Max PWM channels
- #define PWM_CONFIG SCT_CONFIG_16BIT_COUNTER // default config
- #define PWM_CTRL &LPC_SCT->CTRL_L // control register
- #define PWM_HALT SCT_CTRL_HALT_L // halt counter
- #define PWM_CLEAR SCT_CTRL_CLRCTR_L // clock clear
- #define PWM_PRE(x) SCT_CTRL_PRE_L(x) // clock prescale
- #define PWM_EVT_MASK (1 << 12) // event control mask
- #define PWM_LIMIT &LPC_SCT->LIMIT_L // limit register
- #define PWM_MATCH(x) &LPC_SCT->MATCH[x].L // match register
- #define PWM_MR(x) &LPC_SCT->MATCHREL[x].L // 16-bit match reload register
-#elif (PWM_MODE == 2) // 16-bit high counter, events 1 to 7
- // [TODO] use events 8 to 15 on mode 2
- #define PWM_EVENT_MAX (CONFIG_SCT_nEV/2 - 1) // Max PWM channels
- #define PWM_CONFIG SCT_CONFIG_16BIT_COUNTER // default config
- #define PWM_CTRL &LPC_SCT->CTRL_H // control register
- #define PWM_HALT SCT_CTRL_HALT_L // halt counter
- #define PWM_CLEAR SCT_CTRL_CLRCTR_L // clock clear
- #define PWM_PRE(x) SCT_CTRL_PRE_L(x) // clock prescale
- #define PWM_EVT_MASK ((1 << 4) | (1 << 12)) // event control mask
- #define PWM_LIMIT &LPC_SCT->LIMIT_H // limit register
- #define PWM_MATCH(x) &LPC_SCT->MATCH[x].H // match register
- #define PWM_MR(x) &LPC_SCT->MATCHREL[x].H // 16-bit match reload register
-#else
- #error "PWM mode not implemented"
-#endif
-#define PWM_MR0 PWM_MR(0) // MR register 0 is for period
-
-static uint8_t event = 0;
-
-// PORT ID, PWM ID, Pin function
-static const PinMap PinMap_PWM[] = {
- {P1_1, PWM_7, (SCU_PINIO_FAST | 1)},
- {P1_2, PWM_6, (SCU_PINIO_FAST | 1)},
- {P1_3, PWM_8, (SCU_PINIO_FAST | 1)},
- {P1_4, PWM_9, (SCU_PINIO_FAST | 1)},
- {P1_5, PWM_10, (SCU_PINIO_FAST | 1)},
- {P1_7, PWM_13, (SCU_PINIO_FAST | 2)},
- {P1_8, PWM_12, (SCU_PINIO_FAST | 2)},
- {P1_9, PWM_11, (SCU_PINIO_FAST | 2)},
- {P1_10, PWM_14, (SCU_PINIO_FAST | 2)},
- {P1_11, PWM_15, (SCU_PINIO_FAST | 2)},
- {P2_7, PWM_1, (SCU_PINIO_FAST | 1)},
- {P2_8, PWM_0, (SCU_PINIO_FAST | 1)},
- {P2_9, PWM_3, (SCU_PINIO_FAST | 1)},
- {P2_10, PWM_2, (SCU_PINIO_FAST | 1)},
- {P2_11, PWM_5, (SCU_PINIO_FAST | 1)},
- {P2_12, PWM_4, (SCU_PINIO_FAST | 1)},
- {P4_1, PWM_1, (SCU_PINIO_FAST | 1)},
- {P4_2, PWM_0, (SCU_PINIO_FAST | 1)},
- {P4_3, PWM_3, (SCU_PINIO_FAST | 1)},
- {P4_4, PWM_2, (SCU_PINIO_FAST | 1)},
- {P4_5, PWM_5, (SCU_PINIO_FAST | 1)},
- {P4_6, PWM_4, (SCU_PINIO_FAST | 1)},
- {P6_5, PWM_6, (SCU_PINIO_FAST | 1)},
- {P6_12, PWM_7, (SCU_PINIO_FAST | 1)},
- {P7_0, PWM_14, (SCU_PINIO_FAST | 1)},
- {P7_1, PWM_15, (SCU_PINIO_FAST | 1)},
- {P7_4, PWM_13, (SCU_PINIO_FAST | 1)},
- {P7_5, PWM_12, (SCU_PINIO_FAST | 1)},
- {P7_6, PWM_11, (SCU_PINIO_FAST | 1)},
- {P7_7, PWM_8, (SCU_PINIO_FAST | 1)},
- {PA_4, PWM_9, (SCU_PINIO_FAST | 1)},
- {PB_0, PWM_10, (SCU_PINIO_FAST | 1)},
- {PB_1, PWM_6, (SCU_PINIO_FAST | 5)},
- {PB_2, PWM_7, (SCU_PINIO_FAST | 5)},
- {PB_3, PWM_8, (SCU_PINIO_FAST | 5)},
- {PD_0, PWM_15, (SCU_PINIO_FAST | 1)},
- {PD_2, PWM_7, (SCU_PINIO_FAST | 1)},
- {PD_3, PWM_6, (SCU_PINIO_FAST | 1)},
- {PD_4, PWM_8, (SCU_PINIO_FAST | 1)},
- {PD_5, PWM_9, (SCU_PINIO_FAST | 1)},
- {PD_6, PWM_10, (SCU_PINIO_FAST | 1)},
- {PD_9, PWM_13, (SCU_PINIO_FAST | 1)},
- {PD_11, PWM_14, (SCU_PINIO_FAST | 6)},
- {PD_12, PWM_10, (SCU_PINIO_FAST | 6)},
- {PD_13, PWM_13, (SCU_PINIO_FAST | 6)},
- {PD_14, PWM_11, (SCU_PINIO_FAST | 6)},
- {PD_15, PWM_8, (SCU_PINIO_FAST | 6)},
- {PD_16, PWM_12, (SCU_PINIO_FAST | 6)},
- {PE_5, PWM_3, (SCU_PINIO_FAST | 1)},
- {PE_6, PWM_2, (SCU_PINIO_FAST | 1)},
- {PE_7, PWM_5, (SCU_PINIO_FAST | 1)},
- {PE_8, PWM_4, (SCU_PINIO_FAST | 1)},
- {PE_11, PWM_12, (SCU_PINIO_FAST | 1)},
- {PE_12, PWM_11, (SCU_PINIO_FAST | 1)},
- {PE_13, PWM_14, (SCU_PINIO_FAST | 1)},
- {PE_15, PWM_0, (SCU_PINIO_FAST | 1)},
- {PF_9, PWM_1, (SCU_PINIO_FAST | 2)},
- {NC, NC, 0}
-};
-
-static unsigned int pwm_clock_mhz;
-
-static void _pwmout_dev_init() {
- uint32_t i;
-
- // set SCT clock and config
- LPC_CCU1->CLKCCU[CLK_MX_SCT].CFG = (1 << 0); // enable SCT clock in CCU1
- LPC_SCT->CONFIG |= PWM_CONFIG; // set config options
- *PWM_CTRL |= PWM_HALT; // set HALT bit to stop counter
- // clear counter and set prescaler for desired freq
- *PWM_CTRL |= PWM_CLEAR | PWM_PRE(SystemCoreClock / PWM_FREQ_BASE - 1);
- pwm_clock_mhz = PWM_FREQ_BASE / 1000000;
-
- // configure SCT events
- for (i = 0; i < PWM_EVENT_MAX; i++) {
- *PWM_MATCH(i) = 0; // match register
- *PWM_MR(i) = 0; // match reload register
- LPC_SCT->EVENT[i].STATE = 0xFFFFFFFF; // event happens in all states
- LPC_SCT->EVENT[i].CTRL = (i << 0) | PWM_EVT_MASK; // match condition only
- }
- *PWM_LIMIT = (1 << 0) ; // set event 0 as limit
- // initialize period to 20ms: standard for servos, and fine for e.g. brightness control
- *PWM_MR0 = PWM_SETCOUNT((uint32_t)(((20 * PWM_FREQ_BASE) / 1000000) * 1000));
-
- // initialize SCT outputs
- for (i = 0; i < CONFIG_SCT_nOU; i++) {
- LPC_SCT->OUT[i].SET = 0; // defer set event until pulsewidth defined
- LPC_SCT->OUT[i].CLR = (1 << 0); // event 0 clears PWM pin
- }
- LPC_SCT->OUTPUT = 0; // default outputs to clear
-
- *PWM_CTRL &= ~PWM_HALT; // clear HALT bit to start counter
-}
-
-void pwmout_init(pwmout_t* obj, PinName pin) {
- // determine the channel
- PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
- MBED_ASSERT((pwm != (PWMName)NC) && (event < PWM_EVENT_MAX));
-
- // init SCT clock and outputs on first PWM init
- if (event == 0) {
- _pwmout_dev_init();
- }
- // init PWM object
- event++;
- obj->pwm = pwm; // pwm output
- obj->mr = event; // index of match reload register
-
- // initial duty cycle is 0
- pwmout_write(obj, 0);
-
- // Wire pinout
- pinmap_pinout(pin, PinMap_PWM);
-}
-
-void pwmout_free(pwmout_t* obj) {
- // [TODO]
-}
-
-void pwmout_write(pwmout_t* obj, float value) {
- if (value < 0.0f) {
- value = 0.0;
- } else if (value > 1.0f) {
- value = 1.0;
- }
-
- // set new pulse width
- uint32_t us = (uint32_t)((float)PWM_GETCOUNT(*PWM_MR0) * value) * pwm_clock_mhz;
- pwmout_pulsewidth_us(obj, us);
-}
-
-float pwmout_read(pwmout_t* obj) {
- float v = (float)PWM_GETCOUNT(*PWM_MR(obj->mr)) / (float)PWM_GETCOUNT(*PWM_MR0);
- return (v > 1.0f) ? (1.0f) : (v);
-}
-
-void pwmout_period(pwmout_t* obj, float seconds) {
- pwmout_period_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_period_ms(pwmout_t* obj, int ms) {
- pwmout_period_us(obj, ms * 1000);
-}
-
-// Set the PWM period, keeping the duty cycle the same.
-void pwmout_period_us(pwmout_t* obj, int us) {
- // calculate number of ticks
- uint32_t ticks = pwm_clock_mhz * us;
- uint32_t old_ticks = PWM_GETCOUNT(*PWM_MR0);
- uint32_t i, v;
-
- // set new period
- *PWM_MR0 = PWM_SETCOUNT(ticks);
-
- // Scale pulse widths to preserve the duty ratio
- for (i = 1; i < PWM_EVENT_MAX; i++) {
- v = PWM_GETCOUNT(*PWM_MR(i));
- if (v > 1) {
- v = (v * ticks) / old_ticks;
- *PWM_MR(i) = PWM_SETCOUNT(v);
- }
- }
-}
-
-void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
- pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
- pwmout_pulsewidth_us(obj, ms * 1000);
-}
-
-void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
- // calculate number of ticks
- uint32_t v = pwm_clock_mhz * us;
- uint32_t i = obj->pwm;
- //MBED_ASSERT(PWM_GETCOUNT(*PWM_MR0) >= v);
-
- if (v > 0) {
- // set new match register value and enable SCT output
- *PWM_MR(obj->mr) = PWM_SETCOUNT(v);
- LPC_SCT->OUT[i].SET = (1 << 0); // event 0 sets PWM pin
- LPC_SCT->OUT[i].CLR = (1 << obj->mr); // match event clears PWM pin
- } else {
- // set match to zero and clear SCT output
- *PWM_MR(obj->mr) = 0;
- LPC_SCT->OUT[i].SET = 0; // no set event if no pulsewidth defined
- LPC_SCT->OUT[i].CLR = (1 << 0); // event 0 clears PWM pin
- }
-}
-
-const PinMap *pwmout_pinmap()
-{
- return PinMap_PWM;
-}
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/rtc_api.c b/targets/TARGET_NXP/TARGET_LPC43XX/rtc_api.c
deleted file mode 100644
index cc4a06d2e2..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/rtc_api.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
- */
-#include "rtc_api.h"
-#include "mbed_mktime.h"
-
-// ensure rtc is running (unchanged if already running)
-
-/* Setup the RTC based on a time structure, ensuring RTC is enabled
- *
- * Can be clocked by a 32.768KHz oscillator or prescale divider based on the APB clock
- * - We want to use the 32khz clock, allowing for sleep mode
- *
- * Most registers are not changed by a Reset
- * - We must initialize these registers between power-on and setting the RTC into operation
-
- * Clock Control Register
- * RTC_CCR[0] : Enable - 0 = Disabled, 1 = Enabled
- * RTC_CCR[1] : Reset - 0 = Normal, 1 = Reset
- * RTC_CCR[4] : Clock Source - 0 = Prescaler, 1 = 32k Xtal
- *
- * The RTC may already be running, so we should set it up
- * without impacting if it is the case
- */
-
-void rtc_init(void) {
- // Return, if already enabled
- if (LPC_RTC->CCR & 1)
- return;
-
- // Enable 1kHz output of 32kHz oscillator
- LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
- LPC_CREG->CREG0 |= (0x03 << 6) | (1 << 1) | (1 << 0);
-
- // Enable RTC
- do {
- LPC_RTC->CCR |= 1 << 0;
- } while ((LPC_RTC->CCR & 1) == 0);
-}
-
-void rtc_free(void) {
- // [TODO]
-}
-
-/*
- * Little check routine to see if the RTC has been enabled
- *
- * Clock Control Register
- * RTC_CCR[0] : 0 = Disabled, 1 = Enabled
- *
- */
-int rtc_isenabled(void) {
- return(((LPC_RTC->CCR) & 0x01) != 0);
-}
-
-/*
- * RTC Registers
- * RTC_SEC Seconds 0-59
- * RTC_MIN Minutes 0-59
- * RTC_HOUR Hour 0-23
- * RTC_DOM Day of Month 1-28..31
- * RTC_DOW Day of Week 0-6
- * RTC_DOY Day of Year 1-365
- * RTC_MONTH Month 1-12
- * RTC_YEAR Year 0-4095
- *
- * struct tm
- * tm_sec seconds after the minute 0-61
- * tm_min minutes after the hour 0-59
- * tm_hour hours since midnight 0-23
- * tm_mday day of the month 1-31
- * tm_mon months since January 0-11
- * tm_year years since 1900
- * tm_wday days since Sunday 0-6
- * tm_yday days since January 1 0-365
- * tm_isdst Daylight Saving Time flag
- */
-time_t rtc_read(void) {
- // Setup a tm structure based on the RTC
- struct tm timeinfo;
- timeinfo.tm_sec = LPC_RTC->TIME[RTC_TIMETYPE_SECOND];
- timeinfo.tm_min = LPC_RTC->TIME[RTC_TIMETYPE_MINUTE];
- timeinfo.tm_hour = LPC_RTC->TIME[RTC_TIMETYPE_HOUR];
- timeinfo.tm_mday = LPC_RTC->TIME[RTC_TIMETYPE_DAYOFMONTH];
- timeinfo.tm_wday = LPC_RTC->TIME[RTC_TIMETYPE_DAYOFWEEK];
- timeinfo.tm_yday = LPC_RTC->TIME[RTC_TIMETYPE_DAYOFYEAR];
- timeinfo.tm_mon = LPC_RTC->TIME[RTC_TIMETYPE_MONTH] - 1;
- timeinfo.tm_year = LPC_RTC->TIME[RTC_TIMETYPE_YEAR] - 1900;
-
- // Convert to timestamp
- time_t t;
- if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
- return 0;
- }
-
- return t;
-}
-
-void rtc_write(time_t t) {
- // Convert the time in to a tm
- struct tm timeinfo;
- if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
- return;
- }
-
- // Pause clock, and clear counter register (clears us count)
- LPC_RTC->CCR |= 2;
-
- // Set the RTC
- LPC_RTC->TIME[RTC_TIMETYPE_SECOND] = timeinfo.tm_sec;
- LPC_RTC->TIME[RTC_TIMETYPE_MINUTE] = timeinfo.tm_min;
- LPC_RTC->TIME[RTC_TIMETYPE_HOUR] = timeinfo.tm_hour;
- LPC_RTC->TIME[RTC_TIMETYPE_DAYOFMONTH] = timeinfo.tm_mday;
- LPC_RTC->TIME[RTC_TIMETYPE_DAYOFWEEK] = timeinfo.tm_wday;
- LPC_RTC->TIME[RTC_TIMETYPE_DAYOFYEAR] = timeinfo.tm_yday;
- LPC_RTC->TIME[RTC_TIMETYPE_MONTH] = timeinfo.tm_mon + 1;
- LPC_RTC->TIME[RTC_TIMETYPE_YEAR] = timeinfo.tm_year + 1900;
-
- // Restart clock
- LPC_RTC->CCR &= ~((uint32_t)2);
-}
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/serial_api.c b/targets/TARGET_NXP/TARGET_LPC43XX/serial_api.c
deleted file mode 100644
index 80cc76b731..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/serial_api.c
+++ /dev/null
@@ -1,433 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
- */
-// math.h required for floating point operations for baud rate calculation
-#include <math.h>
-#include <string.h>
-#include <stdlib.h>
-
-#include "serial_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "gpio_api.h"
-
-/******************************************************************************
- * INITIALIZATION
- ******************************************************************************/
-#define UART_NUM 4
-
-// SCU mode for UART pins
-#define SCU_PINIO_UART_TX SCU_MODE_PULLDOWN
-#define SCU_PINIO_UART_RX SCU_PINIO_PULLNONE
-
-static const PinMap PinMap_UART_TX[] = {
- {P1_13, UART_1, (SCU_PINIO_UART_TX | 1)},
- {P1_15, UART_2, (SCU_PINIO_UART_TX | 1)},
- {P2_0, UART_0, (SCU_PINIO_UART_TX | 1)},
- {P2_3, UART_3, (SCU_PINIO_UART_TX | 2)},
- {P2_10, UART_2, (SCU_PINIO_UART_TX | 2)},
- {P3_4, UART_1, (SCU_PINIO_UART_TX | 4)},
- {P4_1, UART_3, (SCU_PINIO_UART_TX | 6)},
- {P5_6, UART_1, (SCU_PINIO_UART_TX | 4)},
- {P6_4, UART_0, (SCU_PINIO_UART_TX | 2)},
- {P7_1, UART_2, (SCU_PINIO_UART_TX | 6)},
- {P9_3, UART_3, (SCU_PINIO_UART_TX | 7)},
- {P9_5, UART_0, (SCU_PINIO_UART_TX | 7)},
- {PA_1, UART_2, (SCU_PINIO_UART_TX | 3)},
- {PC_13, UART_1, (SCU_PINIO_UART_TX | 2)},
- {PE_11, UART_1, (SCU_PINIO_UART_TX | 2)},
- {PF_2, UART_3, (SCU_PINIO_UART_TX | 1)},
- {PF_10, UART_0, (SCU_PINIO_UART_TX | 1)},
- {NC, NC, 0}
-};
-
-static const PinMap PinMap_UART_RX[] = {
- {P1_14, UART_1, (SCU_PINIO_UART_RX | 1)},
- {P1_16, UART_2, (SCU_PINIO_UART_RX | 1)},
- {P2_1, UART_0, (SCU_PINIO_UART_RX | 1)},
- {P2_4, UART_3, (SCU_PINIO_UART_RX | 2)},
- {P2_11, UART_2, (SCU_PINIO_UART_RX | 2)},
- {P3_5, UART_1, (SCU_PINIO_UART_RX | 4)},
- {P4_2, UART_3, (SCU_PINIO_UART_RX | 6)},
- {P5_7, UART_1, (SCU_PINIO_UART_RX | 4)},
- {P6_5, UART_0, (SCU_PINIO_UART_RX | 2)},
- {P7_2, UART_2, (SCU_PINIO_UART_RX | 6)},
- {P9_4, UART_3, (SCU_PINIO_UART_RX | 7)},
- {P9_6, UART_0, (SCU_PINIO_UART_RX | 7)},
- {PA_2, UART_2, (SCU_PINIO_UART_RX | 3)},
- {PC_14, UART_1, (SCU_PINIO_UART_RX | 2)},
- {PE_12, UART_1, (SCU_PINIO_UART_RX | 2)},
- {PF_3, UART_3, (SCU_PINIO_UART_RX | 1)},
- {PF_11, UART_0, (SCU_PINIO_UART_RX | 1)},
- {NC, NC, 0}
-};
-
-// RTS/CTS PinMap for flow control
-static const PinMap PinMap_UART_RTS[] = {
-#if (DEVICE_SERIAL_FC)
- {P1_9, UART_1, (SCU_PINIO_FAST | 1)},
- {P5_2, UART_1, (SCU_PINIO_FAST | 4)},
- {PC_3, UART_1, (SCU_PINIO_FAST | 2)},
- {PE_5, UART_1, (SCU_PINIO_FAST | 2)},
-#endif
- {NC, NC, 0}
-};
-
-static const PinMap PinMap_UART_CTS[] = {
-#if (DEVICE_SERIAL_FC)
- {P1_11, UART_1, (SCU_PINIO_FAST | 1)},
- {P5_4, UART_1, (SCU_PINIO_FAST | 4)},
- {PC_2, UART_1, (SCU_PINIO_FAST | 2)},
- {PE_7, UART_1, (SCU_PINIO_FAST | 2)},
-#endif
- {NC, NC, 0}
-};
-
-static uart_irq_handler irq_handler;
-
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-struct serial_global_data_s {
- uint32_t serial_irq_id;
- gpio_t sw_rts, sw_cts;
- uint8_t count, rx_irq_set_flow, rx_irq_set_api;
-};
-
-static struct serial_global_data_s uart_data[UART_NUM];
-
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
- int is_stdio_uart = 0;
-
- // determine the UART to use
- UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
- UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
- UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
- if ((int)uart == NC) {
- error("Serial pinout mapping failed");
- }
-
- obj->uart = (LPC_USART_T *)uart;
-
- // enable fifos and default rx trigger level
- obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
- | 0 << 1 // Rx Fifo Reset
- | 0 << 2 // Tx Fifo Reset
- | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
-
- // disable irqs
- obj->uart->IER = 0 << 0 // Rx Data available irq enable
- | 0 << 1 // Tx Fifo empty irq enable
- | 0 << 2; // Rx Line Status irq enable
-
- // set default baud rate and format
- serial_baud (obj, 9600);
- serial_format(obj, 8, ParityNone, 1);
-
- // pinout the chosen uart
- pinmap_pinout(tx, PinMap_UART_TX);
- pinmap_pinout(rx, PinMap_UART_RX);
-
- // set rx/tx pins in PullUp mode
- if (tx != NC) {
- pin_mode(tx, PullUp);
- }
- if (rx != NC) {
- pin_mode(rx, PullUp);
- }
-
- switch (uart) {
- case UART_0: obj->index = 0; break;
- case UART_1: obj->index = 1; break;
- case UART_2: obj->index = 2; break;
- case UART_3: obj->index = 3; break;
- }
- uart_data[obj->index].sw_rts.pin = NC;
- uart_data[obj->index].sw_cts.pin = NC;
- serial_set_flow_control(obj, FlowControlNone, NC, NC);
-
- is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
-
- if (is_stdio_uart) {
- stdio_uart_inited = 1;
- serial_baud (obj, STDIO_BAUD);
- memcpy(&stdio_uart, obj, sizeof(serial_t));
- }
-}
-
-void serial_free(serial_t *obj) {
- uart_data[obj->index].serial_irq_id = 0;
-}
-
-// serial_baud
-// set the baud rate, taking in to account the current SystemFrequency
-void serial_baud(serial_t *obj, int baudrate) {
- uint32_t PCLK = SystemCoreClock;
-
- // First we check to see if the basic divide with no DivAddVal/MulVal
- // ratio gives us an integer result. If it does, we set DivAddVal = 0,
- // MulVal = 1. Otherwise, we search the valid ratio value range to find
- // the closest match. This could be more elegant, using search methods
- // and/or lookup tables, but the brute force method is not that much
- // slower, and is more maintainable.
- uint16_t DL = PCLK / (16 * baudrate);
-
- uint8_t DivAddVal = 0;
- uint8_t MulVal = 1;
- int hit = 0;
- uint16_t dlv;
- uint8_t mv, dav;
- if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder
- int err_best = baudrate, b;
- for (mv = 1; mv < 16 && !hit; mv++)
- {
- for (dav = 0; dav < mv; dav++)
- {
- // baudrate = PCLK / (16 * dlv * (1 + (DivAdd / Mul))
- // solving for dlv, we get dlv = mul * PCLK / (16 * baudrate * (divadd + mul))
- // mul has 4 bits, PCLK has 27 so we have 1 bit headroom which can be used for rounding
- // for many values of mul and PCLK we have 2 or more bits of headroom which can be used to improve precision
- // note: X / 32 doesn't round correctly. Instead, we use ((X / 16) + 1) / 2 for correct rounding
-
- if ((mv * PCLK * 2) & 0x80000000) // 1 bit headroom
- dlv = ((((2 * mv * PCLK) / (baudrate * (dav + mv))) / 16) + 1) / 2;
- else // 2 bits headroom, use more precision
- dlv = ((((4 * mv * PCLK) / (baudrate * (dav + mv))) / 32) + 1) / 2;
-
- // datasheet says if DLL==DLM==0, then 1 is used instead since divide by zero is ungood
- if (dlv == 0)
- dlv = 1;
-
- // datasheet says if dav > 0 then DL must be >= 2
- if ((dav > 0) && (dlv < 2))
- dlv = 2;
-
- // integer rearrangement of the baudrate equation (with rounding)
- b = ((PCLK * mv / (dlv * (dav + mv) * 8)) + 1) / 2;
-
- // check to see how we went
- b = abs(b - baudrate);
- if (b < err_best)
- {
- err_best = b;
-
- DL = dlv;
- MulVal = mv;
- DivAddVal = dav;
-
- if (b == baudrate)
- {
- hit = 1;
- break;
- }
- }
- }
- }
- }
-
- // set LCR[DLAB] to enable writing to divider registers
- obj->uart->LCR |= (1 << 7);
-
- // set divider values
- obj->uart->DLM = (DL >> 8) & 0xFF;
- obj->uart->DLL = (DL >> 0) & 0xFF;
- obj->uart->FDR = (uint32_t) DivAddVal << 0
- | (uint32_t) MulVal << 4;
-
- // clear LCR[DLAB]
- obj->uart->LCR &= ~(1 << 7);
-}
-
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
- // 0: 1 stop bits, 1: 2 stop bits
- if (stop_bits != 1 && stop_bits != 2) {
- error("Invalid stop bits specified");
- }
- stop_bits -= 1;
-
- // 0: 5 data bits ... 3: 8 data bits
- if (data_bits < 5 || data_bits > 8) {
- error("Invalid number of bits (%d) in serial format, should be 5..8", data_bits);
- }
- data_bits -= 5;
-
- int parity_enable = 0, parity_select = 0;
- switch (parity) {
- case ParityNone: parity_enable = 0; parity_select = 0; break;
- case ParityOdd : parity_enable = 1; parity_select = 0; break;
- case ParityEven: parity_enable = 1; parity_select = 1; break;
- case ParityForced1: parity_enable = 1; parity_select = 2; break;
- case ParityForced0: parity_enable = 1; parity_select = 3; break;
- default:
- break;
- }
-
- obj->uart->LCR = data_bits << 0
- | stop_bits << 2
- | parity_enable << 3
- | parity_select << 4;
-}
-
-/******************************************************************************
- * INTERRUPTS HANDLING
- ******************************************************************************/
-static inline void uart_irq(uint32_t iir, uint32_t index, LPC_USART_T *puart) {
- // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
- SerialIrq irq_type;
- switch (iir) {
- case 1: irq_type = TxIrq; break;
- case 2: irq_type = RxIrq; break;
- default: return;
- }
- if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) {
- gpio_write(&uart_data[index].sw_rts, 1);
- // Disable interrupt if it wasn't enabled by other part of the application
- if (!uart_data[index].rx_irq_set_api)
- puart->IER &= ~(1 << RxIrq);
- }
- if (uart_data[index].serial_irq_id != 0)
- if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
- irq_handler(uart_data[index].serial_irq_id, irq_type);
-}
-
-void uart0_irq() {uart_irq((LPC_USART0->IIR >> 1) & 0x7, 0, (LPC_USART_T*)LPC_USART0);}
-void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1, (LPC_USART_T*)LPC_UART1);}
-void uart2_irq() {uart_irq((LPC_USART2->IIR >> 1) & 0x7, 2, (LPC_USART_T*)LPC_USART2);}
-void uart3_irq() {uart_irq((LPC_USART3->IIR >> 1) & 0x7, 3, (LPC_USART_T*)LPC_USART3);}
-
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
- irq_handler = handler;
- uart_data[obj->index].serial_irq_id = id;
-}
-
-static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
- IRQn_Type irq_n = (IRQn_Type)0;
- uint32_t vector = 0;
- switch ((int)obj->uart) {
- case UART_0: irq_n=USART0_IRQn; vector = (uint32_t)&uart0_irq; break;
- case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
- case UART_2: irq_n=USART2_IRQn; vector = (uint32_t)&uart2_irq; break;
- case UART_3: irq_n=USART3_IRQn; vector = (uint32_t)&uart3_irq; break;
- }
-
- if (enable) {
- obj->uart->IER |= 1 << irq;
- NVIC_SetVector(irq_n, vector);
- NVIC_EnableIRQ(irq_n);
- } else if ((TxIrq == irq) || (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable
- int all_disabled = 0;
- SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
- obj->uart->IER &= ~(1 << irq);
- all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
- if (all_disabled)
- NVIC_DisableIRQ(irq_n);
- }
-}
-
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
- if (RxIrq == irq)
- uart_data[obj->index].rx_irq_set_api = enable;
- serial_irq_set_internal(obj, irq, enable);
-}
-
-#if (DEVICE_SERIAL_FC)
-static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {
- uart_data[obj->index].rx_irq_set_flow = enable;
- serial_irq_set_internal(obj, RxIrq, enable);
-}
-#endif
-
-/******************************************************************************
- * READ/WRITE
- ******************************************************************************/
-int serial_getc(serial_t *obj) {
- while (!serial_readable(obj));
- int data = obj->uart->RBR;
- if (NC != uart_data[obj->index].sw_rts.pin) {
- gpio_write(&uart_data[obj->index].sw_rts, 0);
- obj->uart->IER |= 1 << RxIrq;
- }
- return data;
-}
-
-void serial_putc(serial_t *obj, int c) {
- while (!serial_writable(obj));
- obj->uart->THR = c;
- uart_data[obj->index].count++;
-}
-
-int serial_readable(serial_t *obj) {
- return obj->uart->LSR & 0x01;
-}
-
-int serial_writable(serial_t *obj) {
- int isWritable = 1;
- if (NC != uart_data[obj->index].sw_cts.pin)
- isWritable = (gpio_read(&uart_data[obj->index].sw_cts) == 0) && (obj->uart->LSR & 0x40); //If flow control: writable if CTS low + UART done
- else {
- if (obj->uart->LSR & 0x20)
- uart_data[obj->index].count = 0;
- else if (uart_data[obj->index].count >= 16)
- isWritable = 0;
- }
- return isWritable;
-}
-
-void serial_clear(serial_t *obj) {
- obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
- | 1 << 1 // rx FIFO reset
- | 1 << 2 // tx FIFO reset
- | 0 << 6; // interrupt depth
-}
-
-void serial_pinout_tx(PinName tx) {
- pinmap_pinout(tx, PinMap_UART_TX);
-}
-
-void serial_break_set(serial_t *obj) {
- obj->uart->LCR |= (1 << 6);
-}
-
-void serial_break_clear(serial_t *obj) {
- obj->uart->LCR &= ~(1 << 6);
-}
-
-void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
-#if (DEVICE_SERIAL_FC)
-#endif
-}
-
-const PinMap *serial_tx_pinmap()
-{
- return PinMap_UART_TX;
-}
-
-const PinMap *serial_rx_pinmap()
-{
- return PinMap_UART_RX;
-}
-
-const PinMap *serial_cts_pinmap()
-{
- return PinMap_UART_CTS;
-}
-
-const PinMap *serial_rts_pinmap()
-{
- return PinMap_UART_RTS;
-}
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/sleep.c b/targets/TARGET_NXP/TARGET_LPC43XX/sleep.c
deleted file mode 100644
index deafdb50db..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/sleep.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
- */
-#include "sleep_api.h"
-#include "cmsis.h"
-#include "mbed_interface.h"
-
-void hal_sleep(void) {
-
- // SRC[SLEEPDEEP] set to 0 = sleep
- SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
-
- // wait for interrupt
- __WFI();
-}
-
-/*
- * ToDo: Implement deepsleep()
- */
-void hal_deepsleep(void) {
- hal_sleep();
-}
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/spi_api.c b/targets/TARGET_NXP/TARGET_LPC43XX/spi_api.c
deleted file mode 100644
index 680d2c3e90..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/spi_api.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
- */
-#include "mbed_assert.h"
-#include <math.h>
-
-#include "spi_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-// SCU mode for SPI pins
-#define SCU_PINIO_SPI SCU_PINIO_FAST
-
-static const PinMap PinMap_SPI_SCLK[] = {
- {P1_19, SPI_1, (SCU_PINIO_SPI | 1)},
- {P3_0, SPI_0, (SCU_PINIO_SPI | 4)},
- {P3_3, SPI_0, (SCU_PINIO_SPI | 2)},
- {PF_0, SPI_0, (SCU_PINIO_SPI | 0)},
- {PF_4, SPI_1, (SCU_PINIO_SPI | 0)},
- {NC, NC, 0}
-};
-
-static const PinMap PinMap_SPI_MOSI[] = {
- {P0_1, SPI_1, (SCU_PINIO_SPI | 1)},
- {P1_2, SPI_0, (SCU_PINIO_SPI | 5)},
- {P1_4, SPI_1, (SCU_PINIO_SPI | 5)},
- {P3_7, SPI_0, (SCU_PINIO_SPI | 5)},
- {P3_8, SPI_0, (SCU_PINIO_SPI | 2)},
- {P9_2, SPI_0, (SCU_PINIO_SPI | 7)},
- {PF_3, SPI_0, (SCU_PINIO_SPI | 2)},
- {PF_7, SPI_1, (SCU_PINIO_SPI | 2)},
- {NC, NC, 0}
-};
-
-static const PinMap PinMap_SPI_MISO[] = {
- {P0_0, SPI_1, (SCU_PINIO_SPI | 1)},
- {P1_1, SPI_0, (SCU_PINIO_SPI | 5)},
- {P1_3, SPI_1, (SCU_PINIO_SPI | 5)},
- {P3_6, SPI_0, (SCU_PINIO_SPI | 5)},
- {P3_7, SPI_0, (SCU_PINIO_SPI | 2)},
- {P9_1, SPI_0, (SCU_PINIO_SPI | 7)},
- {PF_2, SPI_0, (SCU_PINIO_SPI | 2)},
- {PF_6, SPI_1, (SCU_PINIO_SPI | 2)},
- {NC, NC, 0}
-};
-
-static const PinMap PinMap_SPI_SSEL[] = {
- {P1_0, SPI_0, (SCU_PINIO_SPI | 5)},
- {P1_5, SPI_1, (SCU_PINIO_SPI | 5)},
- {P1_20, SPI_1, (SCU_PINIO_SPI | 2)},
- {P3_6, SPI_0, (SCU_PINIO_SPI | 2)},
- {P3_8, SPI_0, (SCU_PINIO_SPI | 5)},
- {P9_0, SPI_0, (SCU_PINIO_SPI | 7)},
- {PF_1, SPI_0, (SCU_PINIO_SPI | 2)},
- {PF_5, SPI_1, (SCU_PINIO_SPI | 2)},
- {NC, NC, 0}
-};
-
-static inline int ssp_disable(spi_t *obj);
-static inline int ssp_enable(spi_t *obj);
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
- // determine the SPI to use
- SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
- SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
- SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
- SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
- SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
- SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-
- obj->spi = (LPC_SSP_T*)pinmap_merge(spi_data, spi_cntl);
- MBED_ASSERT((int)obj->spi != NC);
-
- // enable clocking
- switch ((int)obj->spi) {
- case SPI_0: LPC_CGU->BASE_CLK[CLK_BASE_SSP0] = (1 << 11) | (CLKIN_MAINPLL << 24); break;
- case SPI_1: LPC_CGU->BASE_CLK[CLK_BASE_SSP1] = (1 << 11) | (CLKIN_MAINPLL << 24); break;
- }
-
- // pin out the spi pins
- pinmap_pinout(mosi, PinMap_SPI_MOSI);
- pinmap_pinout(miso, PinMap_SPI_MISO);
- pinmap_pinout(sclk, PinMap_SPI_SCLK);
- if (ssel != NC) {
- pinmap_pinout(ssel, PinMap_SPI_SSEL);
- }
-}
-
-void spi_free(spi_t *obj) {}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
- MBED_ASSERT(((bits >= 4) && (bits <= 16)) || ((mode >= 0) && (mode <= 3)));
- ssp_disable(obj);
-
- int polarity = (mode & 0x2) ? 1 : 0;
- int phase = (mode & 0x1) ? 1 : 0;
-
- // set it up
- int DSS = bits - 1; // DSS (data select size)
- int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
- int SPH = (phase) ? 1 : 0; // SPH - clock out phase
-
- int FRF = 0; // FRF (frame format) = SPI
- uint32_t tmp = obj->spi->CR0;
- tmp &= ~(0x00FF); // Clear DSS, FRF, CPOL and CPHA [7:0]
- tmp |= DSS << 0
- | FRF << 4
- | SPO << 6
- | SPH << 7;
- obj->spi->CR0 = tmp;
-
- tmp = obj->spi->CR1;
- tmp &= ~(0xD);
- tmp |= 0 << 0 // LBM - loop back mode - off
- | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
- | 0 << 3; // SOD - slave output disable - na
- obj->spi->CR1 = tmp;
- ssp_enable(obj);
-}
-
-void spi_frequency(spi_t *obj, int hz) {
- ssp_disable(obj);
-
- uint32_t PCLK = SystemCoreClock;
-
- int prescaler;
-
- for (prescaler = 2; prescaler <= 254; prescaler += 2) {
- int prescale_hz = PCLK / prescaler;
-
- // calculate the divider
- int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
-
- // check we can support the divider
- if (divider < 256) {
- // prescaler
- obj->spi->CPSR = prescaler;
-
- // divider
- obj->spi->CR0 &= ~(0xFF00); // Clear SCR: Serial clock rate [15:8]
- obj->spi->CR0 |= (divider - 1) << 8;
- ssp_enable(obj);
- return;
- }
- }
- error("Couldn't setup requested SPI frequency");
-}
-
-static inline int ssp_disable(spi_t *obj) {
- return obj->spi->CR1 &= ~(1 << 1);
-}
-
-static inline int ssp_enable(spi_t *obj) {
- return obj->spi->CR1 |= (1 << 1);
-}
-
-static inline int ssp_readable(spi_t *obj) {
- return obj->spi->SR & (1 << 2);
-}
-
-static inline int ssp_writeable(spi_t *obj) {
- return obj->spi->SR & (1 << 1);
-}
-
-static inline void ssp_write(spi_t *obj, int value) {
- while (!ssp_writeable(obj));
- obj->spi->DR = value;
-}
-
-static inline int ssp_read(spi_t *obj) {
- while (!ssp_readable(obj));
- return obj->spi->DR;
-}
-
-static inline int ssp_busy(spi_t *obj) {
- return (obj->spi->SR & (1 << 4)) ? (1) : (0);
-}
-
-int spi_master_write(spi_t *obj, int value) {
- ssp_write(obj, value);
- return ssp_read(obj);
-}
-
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
- char *rx_buffer, int rx_length, char write_fill) {
- int total = (tx_length > rx_length) ? tx_length : rx_length;
-
- for (int i = 0; i < total; i++) {
- char out = (i < tx_length) ? tx_buffer[i] : write_fill;
- char in = spi_master_write(obj, out);
- if (i < rx_length) {
- rx_buffer[i] = in;
- }
- }
-
- return total;
-}
-
-int spi_slave_receive(spi_t *obj) {
- return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
-}
-
-int spi_slave_read(spi_t *obj) {
- return obj->spi->DR;
-}
-
-void spi_slave_write(spi_t *obj, int value) {
- while (ssp_writeable(obj) == 0) ;
- obj->spi->DR = value;
-}
-
-int spi_busy(spi_t *obj) {
- return ssp_busy(obj);
-}
-
-const PinMap *spi_master_mosi_pinmap()
-{
- return PinMap_SPI_MOSI;
-}
-
-const PinMap *spi_master_miso_pinmap()
-{
- return PinMap_SPI_MISO;
-}
-
-const PinMap *spi_master_clk_pinmap()
-{
- return PinMap_SPI_SCLK;
-}
-
-const PinMap *spi_master_cs_pinmap()
-{
- return PinMap_SPI_SSEL;
-}
-
-const PinMap *spi_slave_mosi_pinmap()
-{
- return PinMap_SPI_MOSI;
-}
-
-const PinMap *spi_slave_miso_pinmap()
-{
- return PinMap_SPI_MISO;
-}
-
-const PinMap *spi_slave_clk_pinmap()
-{
- return PinMap_SPI_SCLK;
-}
-
-const PinMap *spi_slave_cs_pinmap()
-{
- return PinMap_SPI_SSEL;
-}
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/us_ticker.c b/targets/TARGET_NXP/TARGET_LPC43XX/us_ticker.c
deleted file mode 100644
index fb21b0e64a..0000000000
--- a/targets/TARGET_NXP/TARGET_LPC43XX/us_ticker.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
- */
-#include <stddef.h>
-#include "us_ticker_api.h"
-#include "PeripheralNames.h"
-
-#define US_TICKER_TIMER ((LPC_TIMER_T *)LPC_TIMER3_BASE)
-#define US_TICKER_TIMER_IRQn TIMER3_IRQn
-
-int us_ticker_inited = 0;
-
-void us_ticker_init(void) {
- if (us_ticker_inited) return;
- us_ticker_inited = 1;
-
- US_TICKER_TIMER->CTCR = 0x0; // timer mode
- uint32_t PCLK = SystemCoreClock;
-
- US_TICKER_TIMER->TCR = 0x2; // reset
-
- uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks)
- US_TICKER_TIMER->PR = prescale - 1;
- US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0
-
- NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
- NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
-}
-
-uint32_t us_ticker_read() {
- if (!us_ticker_inited)
- us_ticker_init();
-
- return US_TICKER_TIMER->TC;
-}
-
-void us_ticker_set_interrupt(timestamp_t timestamp) {
- // set match value
- US_TICKER_TIMER->MR[0] = (uint32_t)timestamp;
- // enable match interrupt
- US_TICKER_TIMER->MCR |= 1;
-}
-
-void us_ticker_fire_interrupt(void)
-{
- NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
-}
-
-void us_ticker_disable_interrupt(void) {
- US_TICKER_TIMER->MCR &= ~1;
-}
-
-void us_ticker_clear_interrupt(void) {
- US_TICKER_TIMER->IR = 1;
-}
-
-void us_ticker_free(void)
-{
-
-}
diff --git a/targets/TARGET_NXP/mbed_rtx.h b/targets/TARGET_NXP/mbed_rtx.h
index 15e0a8e472..4423168776 100644
--- a/targets/TARGET_NXP/mbed_rtx.h
+++ b/targets/TARGET_NXP/mbed_rtx.h
@@ -47,12 +47,6 @@
#define INITIAL_SP (0x10008000UL)
#endif
-#elif defined(TARGET_LPC4337)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP (0x10008000UL)
-#endif
-
#elif defined(TARGET_SSCI824)
#ifndef INITIAL_SP
diff --git a/targets/targets.json b/targets/targets.json
index c024e40b88..44a8bfc922 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -538,46 +538,6 @@
"1235"
]
},
- "LPC4337": {
- "inherits": [
- "LPCTarget"
- ],
- "core": "Cortex-M4F",
- "extra_labels": [
- "NXP",
- "LPC43XX",
- "LPC4337"
- ],
- "supported_toolchains": [
- "ARM"
- ],
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "DEBUG_AWARENESS",
- "ETHERNET",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "MPU"
- ],
- "release_versions": [
- "2"
- ],
- "device_name": "LPC4337",
- "detect_code": [
- "4337"
- ]
- },
"LPC11U37H_401": {
"supported_form_factors": [
"ARDUINO"