From 1bbb0ee1099cb8ec66f8af42511b57b3418860e8 Mon Sep 17 00:00:00 2001 From: Jeremy Brodt Date: Tue, 17 Mar 2015 13:41:40 -0500 Subject: [PATCH 01/13] Added macros to alias the endpoint callback functions to support configurability. --- libraries/USBDevice/USBAudio/USBAudio.cpp | 4 ++-- libraries/USBDevice/USBAudio/USBAudio.h | 4 ++-- libraries/USBDevice/USBDevice/USBEndpoints_KL25Z.h | 6 ++++++ libraries/USBDevice/USBDevice/USBEndpoints_LPC11U.h | 6 ++++++ libraries/USBDevice/USBDevice/USBEndpoints_LPC17_LPC23.h | 6 ++++++ libraries/USBDevice/USBDevice/USBEndpoints_RZ_A1H.h | 6 ++++++ libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h | 6 ++++++ libraries/USBDevice/USBHID/USBKeyboard.cpp | 2 +- libraries/USBDevice/USBHID/USBKeyboard.h | 2 +- libraries/USBDevice/USBHID/USBMouseKeyboard.cpp | 2 +- libraries/USBDevice/USBHID/USBMouseKeyboard.h | 2 +- libraries/USBDevice/USBMIDI/USBMIDI.cpp | 2 +- libraries/USBDevice/USBMIDI/USBMIDI.h | 2 +- libraries/USBDevice/USBMSD/USBMSD.cpp | 4 ++-- libraries/USBDevice/USBMSD/USBMSD.h | 4 ++-- libraries/USBDevice/USBSerial/USBSerial.cpp | 2 +- libraries/USBDevice/USBSerial/USBSerial.h | 2 +- 17 files changed, 46 insertions(+), 16 deletions(-) diff --git a/libraries/USBDevice/USBAudio/USBAudio.cpp b/libraries/USBDevice/USBAudio/USBAudio.cpp index fc383b6c13..aab9e774e3 100644 --- a/libraries/USBDevice/USBAudio/USBAudio.cpp +++ b/libraries/USBDevice/USBAudio/USBAudio.cpp @@ -119,7 +119,7 @@ float USBAudio::getVolume() { } -bool USBAudio::EP3_OUT_callback() { +bool USBAudio::EPISO_OUT_callback() { uint32_t size = 0; interruptOUT = true; if (buf_stream_in != NULL) { @@ -132,7 +132,7 @@ bool USBAudio::EP3_OUT_callback() { } -bool USBAudio::EP3_IN_callback() { +bool USBAudio::EPISO_IN_callback() { interruptIN = true; writeIN = true; return true; diff --git a/libraries/USBDevice/USBAudio/USBAudio.h b/libraries/USBDevice/USBAudio/USBAudio.h index 6b6b4bcc45..5038f053c8 100644 --- a/libraries/USBDevice/USBAudio/USBAudio.h +++ b/libraries/USBDevice/USBAudio/USBAudio.h @@ -216,12 +216,12 @@ protected: /* * Callback called when a packet is received */ - virtual bool EP3_OUT_callback(); + virtual bool EPISO_OUT_callback(); /* * Callback called when a packet has been sent */ - virtual bool EP3_IN_callback(); + virtual bool EPISO_IN_callback(); private: diff --git a/libraries/USBDevice/USBDevice/USBEndpoints_KL25Z.h b/libraries/USBDevice/USBDevice/USBEndpoints_KL25Z.h index 5cb3f7b395..87721a21c5 100644 --- a/libraries/USBDevice/USBDevice/USBEndpoints_KL25Z.h +++ b/libraries/USBDevice/USBDevice/USBEndpoints_KL25Z.h @@ -81,12 +81,18 @@ /* Bulk endpoints */ #define EPBULK_OUT (EP2OUT) #define EPBULK_IN (EP2IN) +#define EPBULK_OUT_callback EP2_OUT_callback +#define EPBULK_IN_callback EP2_IN_callback /* Interrupt endpoints */ #define EPINT_OUT (EP1OUT) #define EPINT_IN (EP1IN) +#define EPINT_OUT_callback EP1_OUT_callback +#define EPINT_IN_callback EP1_IN_callback /* Isochronous endpoints */ #define EPISO_OUT (EP3OUT) #define EPISO_IN (EP3IN) +#define EPISO_OUT_callback EP3_OUT_callback +#define EPISO_IN_callback EP3_IN_callback #define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2) #define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1) diff --git a/libraries/USBDevice/USBDevice/USBEndpoints_LPC11U.h b/libraries/USBDevice/USBDevice/USBEndpoints_LPC11U.h index 5f642df15a..b4ddaa5142 100644 --- a/libraries/USBDevice/USBDevice/USBEndpoints_LPC11U.h +++ b/libraries/USBDevice/USBDevice/USBEndpoints_LPC11U.h @@ -53,12 +53,18 @@ /* Bulk endpoint */ #define EPBULK_OUT (EP2OUT) #define EPBULK_IN (EP2IN) +#define EPBULK_OUT_callback EP2_OUT_callback +#define EPBULK_IN_callback EP2_IN_callback /* Interrupt endpoint */ #define EPINT_OUT (EP1OUT) #define EPINT_IN (EP1IN) +#define EPINT_OUT_callback EP1_OUT_callback +#define EPINT_IN_callback EP1_IN_callback /* Isochronous endpoint */ #define EPISO_OUT (EP3OUT) #define EPISO_IN (EP3IN) +#define EPISO_OUT_callback EP3_OUT_callback +#define EPISO_IN_callback EP3_IN_callback #define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2) #define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1) diff --git a/libraries/USBDevice/USBDevice/USBEndpoints_LPC17_LPC23.h b/libraries/USBDevice/USBDevice/USBEndpoints_LPC17_LPC23.h index 3f7aa6ba4d..383b7e36fc 100644 --- a/libraries/USBDevice/USBDevice/USBEndpoints_LPC17_LPC23.h +++ b/libraries/USBDevice/USBDevice/USBEndpoints_LPC17_LPC23.h @@ -81,12 +81,18 @@ /* Bulk endpoints */ #define EPBULK_OUT (EP2OUT) #define EPBULK_IN (EP2IN) +#define EPBULK_OUT_callback EP2_OUT_callback +#define EPBULK_IN_callback EP2_IN_callback /* Interrupt endpoints */ #define EPINT_OUT (EP1OUT) #define EPINT_IN (EP1IN) +#define EPINT_OUT_callback EP1_OUT_callback +#define EPINT_IN_callback EP1_IN_callback /* Isochronous endpoints */ #define EPISO_OUT (EP3OUT) #define EPISO_IN (EP3IN) +#define EPISO_OUT_callback EP3_OUT_callback +#define EPISO_IN_callback EP3_IN_callback #define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2) #define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1) diff --git a/libraries/USBDevice/USBDevice/USBEndpoints_RZ_A1H.h b/libraries/USBDevice/USBDevice/USBEndpoints_RZ_A1H.h index e939c7673e..f25a3d8623 100644 --- a/libraries/USBDevice/USBDevice/USBEndpoints_RZ_A1H.h +++ b/libraries/USBDevice/USBDevice/USBEndpoints_RZ_A1H.h @@ -65,12 +65,18 @@ /* Bulk endpoints */ #define EPBULK_OUT (EP2OUT) #define EPBULK_IN (EP2IN) +#define EPBULK_OUT_callback EP2_OUT_callback +#define EPBULK_IN_callback EP2_IN_callback /* Interrupt endpoints */ #define EPINT_OUT (EP1OUT) #define EPINT_IN (EP1IN) +#define EPINT_OUT_callback EP1_OUT_callback +#define EPINT_IN_callback EP1_IN_callback /* Isochronous endpoints */ #define EPISO_OUT (EP3OUT) #define EPISO_IN (EP3IN) +#define EPISO_OUT_callback EP3_OUT_callback +#define EPISO_IN_callback EP3_IN_callback #define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2) #define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1) diff --git a/libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h b/libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h index 1c95f2c807..1d520d11c9 100644 --- a/libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h +++ b/libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h @@ -49,12 +49,18 @@ /* Bulk endpoint */ #define EPBULK_OUT (EP2OUT) #define EPBULK_IN (EP2IN) +#define EPBULK_OUT_callback EP2_OUT_callback +#define EPBULK_IN_callback EP2_IN_callback /* Interrupt endpoint */ #define EPINT_OUT (EP1OUT) #define EPINT_IN (EP1IN) +#define EPINT_OUT_callback EP1_OUT_callback +#define EPINT_IN_callback EP1_IN_callback /* Isochronous endpoint */ #define EPISO_OUT (EP3OUT) #define EPISO_IN (EP3IN) +#define EPISO_OUT_callback EP3_OUT_callback +#define EPISO_IN_callback EP3_IN_callback #define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2) #define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1) diff --git a/libraries/USBDevice/USBHID/USBKeyboard.cpp b/libraries/USBDevice/USBHID/USBKeyboard.cpp index 81857095bc..df4ca4798b 100644 --- a/libraries/USBDevice/USBHID/USBKeyboard.cpp +++ b/libraries/USBDevice/USBHID/USBKeyboard.cpp @@ -420,7 +420,7 @@ uint8_t * USBKeyboard::reportDesc() { } -bool USBKeyboard::EP1_OUT_callback() { +bool USBKeyboard::EPINT_OUT_callback() { uint32_t bytesRead = 0; uint8_t led[65]; USBDevice::readEP(EPINT_OUT, led, &bytesRead, MAX_HID_REPORT_SIZE); diff --git a/libraries/USBDevice/USBHID/USBKeyboard.h b/libraries/USBDevice/USBHID/USBKeyboard.h index c9e08b16bc..c58ae56f0e 100644 --- a/libraries/USBDevice/USBHID/USBKeyboard.h +++ b/libraries/USBDevice/USBHID/USBKeyboard.h @@ -150,7 +150,7 @@ public: * * @returns if handle by subclass, return true */ - virtual bool EP1_OUT_callback(); + virtual bool EPINT_OUT_callback(); /** * Read status of lock keys. Useful to switch-on/off leds according to key pressed. Only the first three bits of the result is important: diff --git a/libraries/USBDevice/USBHID/USBMouseKeyboard.cpp b/libraries/USBDevice/USBHID/USBMouseKeyboard.cpp index 848d81a686..cd68091202 100644 --- a/libraries/USBDevice/USBHID/USBMouseKeyboard.cpp +++ b/libraries/USBDevice/USBHID/USBMouseKeyboard.cpp @@ -548,7 +548,7 @@ uint8_t * USBMouseKeyboard::reportDesc() { return NULL; } -bool USBMouseKeyboard::EP1_OUT_callback() { +bool USBMouseKeyboard::EPINT_OUT_callback() { uint32_t bytesRead = 0; uint8_t led[65]; USBDevice::readEP(EPINT_OUT, led, &bytesRead, MAX_HID_REPORT_SIZE); diff --git a/libraries/USBDevice/USBHID/USBMouseKeyboard.h b/libraries/USBDevice/USBHID/USBMouseKeyboard.h index 7eaa355e37..1b19b10db2 100644 --- a/libraries/USBDevice/USBHID/USBMouseKeyboard.h +++ b/libraries/USBDevice/USBHID/USBMouseKeyboard.h @@ -202,7 +202,7 @@ class USBMouseKeyboard: public USBHID, public Stream * * @returns if handle by subclass, return true */ - virtual bool EP1_OUT_callback(); + virtual bool EPINT_OUT_callback(); private: diff --git a/libraries/USBDevice/USBMIDI/USBMIDI.cpp b/libraries/USBDevice/USBMIDI/USBMIDI.cpp index 09594805fb..048ab728bc 100644 --- a/libraries/USBDevice/USBMIDI/USBMIDI.cpp +++ b/libraries/USBDevice/USBMIDI/USBMIDI.cpp @@ -35,7 +35,7 @@ void USBMIDI::attach(void (*fptr)(MIDIMessage)) { } -bool USBMIDI::EP2_OUT_callback() { +bool USBMIDI::EPBULK_OUT_callback() { uint8_t buf[64]; uint32_t len; readEP(EPBULK_OUT, buf, &len, 64); diff --git a/libraries/USBDevice/USBMIDI/USBMIDI.h b/libraries/USBDevice/USBMIDI/USBMIDI.h index fdf5d6d6bb..6b673b63c8 100644 --- a/libraries/USBDevice/USBMIDI/USBMIDI.h +++ b/libraries/USBDevice/USBMIDI/USBMIDI.h @@ -78,7 +78,7 @@ public: protected: - virtual bool EP2_OUT_callback(); + virtual bool EPBULK_OUT_callback(); virtual bool USBCallback_setConfiguration(uint8_t configuration); /* * Get string product descriptor diff --git a/libraries/USBDevice/USBMSD/USBMSD.cpp b/libraries/USBDevice/USBMSD/USBMSD.cpp index c5ce390846..f2b6e3d791 100644 --- a/libraries/USBDevice/USBMSD/USBMSD.cpp +++ b/libraries/USBDevice/USBMSD/USBMSD.cpp @@ -147,7 +147,7 @@ void USBMSD::reset() { // Called in ISR context called when a data is received -bool USBMSD::EP2_OUT_callback() { +bool USBMSD::EPBULK_OUT_callback() { uint32_t size = 0; uint8_t buf[MAX_PACKET_SIZE_EPBULK]; readEP(EPBULK_OUT, buf, &size, MAX_PACKET_SIZE_EPBULK); @@ -184,7 +184,7 @@ bool USBMSD::EP2_OUT_callback() { } // Called in ISR context when a data has been transferred -bool USBMSD::EP2_IN_callback() { +bool USBMSD::EPBULK_IN_callback() { switch (stage) { // the device has to send data to the host diff --git a/libraries/USBDevice/USBMSD/USBMSD.h b/libraries/USBDevice/USBMSD/USBMSD.h index 9bf48ed373..ff750026c1 100644 --- a/libraries/USBDevice/USBMSD/USBMSD.h +++ b/libraries/USBDevice/USBMSD/USBMSD.h @@ -158,12 +158,12 @@ protected: /* * Callback called when a packet is received */ - virtual bool EP2_OUT_callback(); + virtual bool EPBULK_OUT_callback(); /* * Callback called when a packet has been sent */ - virtual bool EP2_IN_callback(); + virtual bool EPBULK_IN_callback(); /* * Set configuration of device. Add endpoints diff --git a/libraries/USBDevice/USBSerial/USBSerial.cpp b/libraries/USBDevice/USBSerial/USBSerial.cpp index 3a1acfd829..4dc28b9e3c 100644 --- a/libraries/USBDevice/USBSerial/USBSerial.cpp +++ b/libraries/USBDevice/USBSerial/USBSerial.cpp @@ -46,7 +46,7 @@ bool USBSerial::writeBlock(uint8_t * buf, uint16_t size) { -bool USBSerial::EP2_OUT_callback() { +bool USBSerial::EPBULK_OUT_callback() { uint8_t c[65]; uint32_t size = 0; diff --git a/libraries/USBDevice/USBSerial/USBSerial.h b/libraries/USBDevice/USBSerial/USBSerial.h index d5e2ec71d1..e83aea6b18 100644 --- a/libraries/USBDevice/USBSerial/USBSerial.h +++ b/libraries/USBDevice/USBSerial/USBSerial.h @@ -145,7 +145,7 @@ public: } protected: - virtual bool EP2_OUT_callback(); + virtual bool EPBULK_OUT_callback(); virtual void lineCodingChanged(int baud, int bits, int parity, int stop){ if (settingsChangedCallback) { settingsChangedCallback(baud, bits, parity, stop); From 79a05aa39cc7c3f61ddcd6d148590b8aae5cafb9 Mon Sep 17 00:00:00 2001 From: Rohit Grover Date: Thu, 8 Jan 2015 11:57:54 +0000 Subject: [PATCH 02/13] fixes #984: updating to v7.1 of the Nordic SDK. Re-organized file layout to match that from the SDK. --- .../TARGET_MCU_NORDIC_32K/startup_nRF51822.s | 25 +- .../TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h | 4 +- .../TARGET_MCU_NRF51822/cmsis_nvic.h | 2 +- .../compiler_abstraction.h | 124 +- .../TARGET_MCU_NRF51822/nordic_global.h | 17 - .../TARGET_NORDIC/TARGET_MCU_NRF51822/nrf.h | 48 + .../TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h | 316 +++-- .../TARGET_MCU_NRF51822/nrf51822.h | 27 - .../TARGET_MCU_NRF51822/nrf51_bitfields.h | 1240 +++++++++++++---- .../TARGET_MCU_NRF51822}/nrf_delay.h | 2 +- .../{system_nrf51822.c => system_nrf51.c} | 62 +- .../TARGET_MCU_NRF51822/system_nrf51.h | 68 + .../TARGET_MCU_NRF51822/system_nrf51822.h | 58 - .../components/libraries/crc16}/crc16.h | 0 .../libraries/scheduler}/app_scheduler.h | 26 +- .../components/libraries/util}/app_error.h | 56 +- .../components/libraries/util}/app_util.h | 6 +- .../Lib/nrf-sdk/app_common/app_button.h | 187 --- .../Lib/nrf-sdk/app_common/app_fifo.h | 83 -- .../Lib/nrf-sdk/app_common/app_gpiote.h | 226 --- .../Lib/nrf-sdk/app_common/app_timer.h | 313 ----- .../Lib/nrf-sdk/app_common/app_trace.h | 55 - .../Lib/nrf-sdk/app_common/app_uart.h | 286 ---- .../Lib/nrf-sdk/app_common/hal_transport.h | 227 --- .../Lib/nrf-sdk/app_common/hci_mem_pool.h | 132 -- .../app_common/hci_mem_pool_internal.h | 32 - .../Lib/nrf-sdk/app_common/hci_slip.h | 129 -- .../Lib/nrf-sdk/app_common/hci_transport.h | 220 --- .../Lib/nrf-sdk/app_common/pstorage.h | 381 ----- .../Lib/nrf-sdk/sd_common/app_util_platform.h | 110 -- .../TARGET_MCU_NRF51822/serial_api.c | 12 +- workspace_tools/targets.py | 22 +- 32 files changed, 1512 insertions(+), 2984 deletions(-) delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nordic_global.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51822.h rename libraries/mbed/targets/{hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk => cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822}/nrf_delay.h (99%) rename libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/{system_nrf51822.c => system_nrf51.c} (54%) create mode 100644 libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.h rename libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/{nrf-sdk/app_common => nordic_sdk/components/libraries/crc16}/crc16.h (100%) mode change 100755 => 100644 rename libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/{nrf-sdk/app_common => nordic_sdk/components/libraries/scheduler}/app_scheduler.h (85%) mode change 100755 => 100644 rename libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/{nrf-sdk/app_common => nordic_sdk/components/libraries/util}/app_error.h (67%) mode change 100755 => 100644 rename libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/{nrf-sdk/app_common => nordic_sdk/components/libraries/util}/app_util.h (97%) mode change 100755 => 100644 delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_button.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_fifo.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_gpiote.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_timer.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_trace.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_uart.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hal_transport.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool_internal.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_slip.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_transport.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/pstorage.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/sd_common/app_util_platform.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.s b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.s index 90f77553ba..ea211543df 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.s +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.s @@ -62,7 +62,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD WDT_IRQHandler ;WDT DCD RTC1_IRQHandler ;RTC1 DCD QDEC_IRQHandler ;QDEC - DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP + DCD LPCOMP_IRQHandler ;LPCOMP DCD SWI0_IRQHandler ;SWI0 DCD SWI1_IRQHandler ;SWI1 DCD SWI2_IRQHandler ;SWI2 @@ -85,19 +85,28 @@ __Vectors_Size EQU __Vectors_End - __Vectors ; Reset Handler -NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address -NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask +NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address +NRF_POWER_RAMONB_ADDRESS EQU 0x40000554 ; NRF_POWER->RAMONB address +NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask Reset_Handler PROC EXPORT Reset_Handler [WEAK] - IMPORT SystemInit + IMPORT SystemInit IMPORT __main + + MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk + LDR R0, =NRF_POWER_RAMON_ADDRESS LDR R2, [R0] - MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk ORRS R2, R2, R1 STR R2, [R0] - LDR R0, =SystemInit + + LDR R0, =NRF_POWER_RAMONB_ADDRESS + LDR R2, [R0] + ORRS R2, R2, R1 + STR R2, [R0] + + LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 @@ -147,7 +156,7 @@ Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC1_IRQHandler [WEAK] EXPORT QDEC_IRQHandler [WEAK] - EXPORT LPCOMP_COMP_IRQHandler [WEAK] + EXPORT LPCOMP_IRQHandler [WEAK] EXPORT SWI0_IRQHandler [WEAK] EXPORT SWI1_IRQHandler [WEAK] EXPORT SWI2_IRQHandler [WEAK] @@ -172,7 +181,7 @@ CCM_AAR_IRQHandler WDT_IRQHandler RTC1_IRQHandler QDEC_IRQHandler -LPCOMP_COMP_IRQHandler +LPCOMP_IRQHandler SWI0_IRQHandler SWI1_IRQHandler SWI2_IRQHandler diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h index 137286f6a7..b73fdadde8 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h @@ -1,13 +1,13 @@ /* mbed Microcontroller Library - CMSIS * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * + * * A generic CMSIS include header, pulling in LPC407x_8x specifics */ #ifndef MBED_CMSIS_H #define MBED_CMSIS_H -#include "nrf51822.h" +#include "nrf.h" #include "cmsis_nvic.h" #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.h index f80068b65d..ab365b2a79 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.h +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.h @@ -35,7 +35,7 @@ #define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals #define NVIC_USER_IRQ_OFFSET 16 -#include "nrf51822.h" +#include "nrf51.h" #include "cmsis.h" diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/compiler_abstraction.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/compiler_abstraction.h index 9c64181ea7..18d70eb207 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/compiler_abstraction.h +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/compiler_abstraction.h @@ -1,47 +1,107 @@ -/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. +/* Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. * - * The information contained herein is confidential property of Nordic - * Semiconductor ASA.Terms and conditions of usage are described in detail - * in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ - #ifndef _COMPILER_ABSTRACTION_H #define _COMPILER_ABSTRACTION_H /*lint ++flb "Enter library region" */ #if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - #define __current_sp() __get_SP() + + #ifndef __ASM + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #endif + + #ifndef __INLINE + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #endif + + #ifndef __WEAK + #define __WEAK __weak /*!< weak keyword for ARM Compiler */ + #endif + + #define GET_SP() __current_sp() /*!> read current SP function for ARM Compiler */ -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -static __INLINE unsigned int __current_sp(void) - { - register unsigned sp asm("sp"); - return sp; - } - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #endif + + #ifndef __INLINE + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #endif + + #ifndef __WEAK + #define __WEAK __weak /*!> define weak function for IAR Compiler */ + #endif + + #define GET_SP() __get_SP() /*!> read current SP function for IAR Compiler */ + +#elif defined ( __GNUC__ ) + + #ifndef __ASM + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #endif + + #ifndef __INLINE + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) /*!< weak keyword for GNU Compiler */ + #endif + + #define GET_SP() gcc_current_sp() /*!> read current SP function for GNU Compiler */ + static inline unsigned int gcc_current_sp(void) + { + register unsigned sp asm("sp"); + return sp; + } + +#elif defined ( __TASKING__ ) + + #ifndef __ASM + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #endif + + #ifndef __INLINE + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) /*!< weak keyword for TASKING Compiler */ + #endif + + #define GET_SP() __get_MSP() /*!> read current SP function for TASKING Compiler */ + #endif /*lint --flb "Leave library region" */ diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nordic_global.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nordic_global.h deleted file mode 100644 index 46235d4f5c..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nordic_global.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _NORDIC_GLOBAL_H_ -#define _NORDIC_GLOBAL_H_ - -/* There are no global defines in mbed, so we need to define */ -/* mandatory conditional compilation flags here */ -//#define NRF51 -#ifndef DEBUG_NRF_USER -#define DEBUG_NRF_USER -#endif -#ifndef BLE_STACK_SUPPORT_REQD -#define BLE_STACK_SUPPORT_REQD -#endif -#ifndef BOARD_PCA10001 -#define BOARD_PCA10001 -#endif - -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf.h new file mode 100644 index 0000000000..e77307f3f6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf.h @@ -0,0 +1,48 @@ +/* Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_H +#define NRF_H + +#ifndef _WIN32 + +/* Family selection for main includes. NRF51 must be selected. */ +#ifdef NRF51 + #include "nrf51.h" + #include "nrf51_bitfields.h" +#else + #error "Device family must be defined. See nrf.h." +#endif /* NRF51 */ + +#include "compiler_abstraction.h" + +#endif /* _WIN32 */ + +#endif /* NRF_H */ + diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h index 1027f03ef7..266d8f0ed1 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h @@ -1,14 +1,46 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + +/****************************************************************************************************//** + * @file nRF51.h * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for + * nRF51 from Nordic Semiconductor. * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. + * @version V522 + * @date 31. October 2014 * - */ + * @note Generated with SVDConv V2.81d + * from CMSIS SVD File 'nRF51.xml' Version 522, + * + * @par Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + *******************************************************************************************************/ @@ -58,7 +90,7 @@ typedef enum { WDT_IRQn = 16, /*!< 16 WDT */ RTC1_IRQn = 17, /*!< 17 RTC1 */ QDEC_IRQn = 18, /*!< 18 QDEC */ - LPCOMP_COMP_IRQn = 19, /*!< 19 LPCOMP_COMP */ + LPCOMP_IRQn = 19, /*!< 19 LPCOMP */ SWI0_IRQn = 20, /*!< 20 SWI0 */ SWI1_IRQn = 21, /*!< 21 SWI1 */ SWI2_IRQn = 22, /*!< 22 SWI2 */ @@ -77,16 +109,15 @@ typedef enum { /* ================ Processor and Core Peripheral Section ================ */ /* ================================================================================ */ -/* ----------------Configuration of the cm0 Processor and Core Peripherals---------------- */ +/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< Cortex-M0 processor and core peripherals */ -#include "system_nrf51822.h" /*!< nRF51 System */ - +#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ +#include "system_nrf51.h" /*!< nRF51 System */ /* ================================================================================ */ /* ================ Device Specific Peripheral Section ================ */ @@ -124,6 +155,24 @@ typedef struct { __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */ } AMLI_RAMPRI_Type; +typedef struct { + __IO uint32_t SCK; /*!< Pin select for SCK. */ + __IO uint32_t MOSI; /*!< Pin select for MOSI. */ + __IO uint32_t MISO; /*!< Pin select for MISO. */ +} SPIM_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer. */ + __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */ + __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */ +} SPIM_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer. */ + __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */ + __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */ +} SPIM_TXD_Type; + typedef struct { __O uint32_t EN; /*!< Enable channel group. */ __O uint32_t DIS; /*!< Disable channel group. */ @@ -134,6 +183,15 @@ typedef struct { __IO uint32_t TEP; /*!< Channel task end-point. */ } PPI_CH_Type; +typedef struct { + __I uint32_t PART; /*!< Part code */ + __I uint32_t VARIANT; /*!< Part variant */ + __I uint32_t PACKAGE; /*!< Package option */ + __I uint32_t RAM; /*!< RAM variant */ + __I uint32_t FLASH; /*!< Flash variant */ + __I uint32_t RESERVED[3]; /*!< Reserved */ +} FICR_INFO_Type; + /* ================================================================================ */ /* ================ POWER ================ */ @@ -155,20 +213,26 @@ typedef struct { /*!< POWER Structure __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ __I uint32_t RESERVED3[61]; __IO uint32_t RESETREAS; /*!< Reset reason. */ - __I uint32_t RESERVED4[63]; + __I uint32_t RESERVED4[9]; + __I uint32_t RAMSTATUS; /*!< Ram status register. */ + __I uint32_t RESERVED5[53]; __O uint32_t SYSTEMOFF; /*!< System off register. */ - __I uint32_t RESERVED5[3]; + __I uint32_t RESERVED6[3]; __IO uint32_t POFCON; /*!< Power failure configuration. */ - __I uint32_t RESERVED6[2]; + __I uint32_t RESERVED7[2]; __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained register. */ - __I uint32_t RESERVED7; + __I uint32_t RESERVED8; __IO uint32_t RAMON; /*!< Ram on/off. */ - __I uint32_t RESERVED8[7]; + __I uint32_t RESERVED9[7]; __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register is a retained register. */ - __I uint32_t RESERVED9[12]; + __I uint32_t RESERVED10[3]; + __IO uint32_t RAMONB; /*!< Ram on/off. */ + __I uint32_t RESERVED11[8]; __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */ + __I uint32_t RESERVED12[291]; + __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */ } NRF_POWER_Type; @@ -193,16 +257,20 @@ typedef struct { /*!< CLOCK Structure __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */ __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */ __I uint32_t RESERVED1; - __IO uint32_t EVENTS_DONE; /*!< Callibration of LFCLK RC oscillator completed. */ - __IO uint32_t EVENTS_CTTO; /*!< Callibration timer timeout. */ + __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */ + __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */ __I uint32_t RESERVED2[124]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[64]; + __I uint32_t RESERVED3[63]; + __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */ __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */ - __I uint32_t RESERVED4[2]; + __I uint32_t RESERVED4; + __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */ __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */ - __I uint32_t RESERVED5[63]; + __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is + triggered. */ + __I uint32_t RESERVED5[62]; __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */ __I uint32_t RESERVED6[7]; __IO uint32_t CTIV; /*!< Calibration timer interval. */ @@ -225,9 +293,10 @@ typedef struct { /*!< MPU Structure __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */ __IO uint32_t RLENR0; /*!< Length of RAM region 0. */ __I uint32_t RESERVED1[52]; - __IO uint32_t PROTENSET0; /*!< Protection bit enable set register for low addresses. */ - __IO uint32_t PROTENSET1; /*!< Protection bit enable set register for high addresses. */ - __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug mode. */ + __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */ + __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */ + __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */ + __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */ } NRF_MPU_Type; @@ -299,17 +368,17 @@ typedef struct { /*!< RADIO Structure __I uint32_t RESERVED1[2]; __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */ __I uint32_t RESERVED2[53]; - __IO uint32_t SHORTS; /*!< Shortcut for the radio. */ + __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */ __I uint32_t RESERVED3[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ __I uint32_t RESERVED4[61]; __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */ - __I uint32_t RESERVED5; + __I uint32_t CD; /*!< Carrier detect. */ __I uint32_t RXMATCH; /*!< Received address. */ __I uint32_t RXCRC; /*!< Received CRC. */ - __IO uint32_t DAI; /*!< Device address match index. */ - __I uint32_t RESERVED6[60]; + __I uint32_t DAI; /*!< Device address match index. */ + __I uint32_t RESERVED5[60]; __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */ __IO uint32_t FREQUENCY; /*!< Frequency. */ __IO uint32_t TXPOWER; /*!< Output power. */ @@ -327,23 +396,23 @@ typedef struct { /*!< RADIO Structure __IO uint32_t CRCINIT; /*!< CRC initial value. */ __IO uint32_t TEST; /*!< Test features enable register. */ __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */ - __IO uint32_t RSSISAMPLE; /*!< RSSI sample. */ - __I uint32_t RESERVED7; + __I uint32_t RSSISAMPLE; /*!< RSSI sample. */ + __I uint32_t RESERVED6; __I uint32_t STATE; /*!< Current radio state. */ __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */ - __I uint32_t RESERVED8[2]; + __I uint32_t RESERVED7[2]; __IO uint32_t BCC; /*!< Bit counter compare. */ - __I uint32_t RESERVED9[39]; + __I uint32_t RESERVED8[39]; __IO uint32_t DAB[8]; /*!< Device address base segment. */ __IO uint32_t DAP[8]; /*!< Device address prefix. */ __IO uint32_t DACNF; /*!< Device address match configuration. */ - __I uint32_t RESERVED10[56]; + __I uint32_t RESERVED9[56]; __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */ __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */ __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */ __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */ __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */ - __I uint32_t RESERVED11[561]; + __I uint32_t RESERVED10[561]; __IO uint32_t POWER; /*!< Peripheral power control. */ } NRF_RADIO_Type; @@ -375,9 +444,8 @@ typedef struct { /*!< UART Structure __I uint32_t RESERVED4[7]; __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */ __I uint32_t RESERVED5[46]; - __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */ - __I uint32_t RESERVED6[63]; - __IO uint32_t INTEN; /*!< Interrupt enable register. */ + __IO uint32_t SHORTS; /*!< Shortcuts for UART. */ + __I uint32_t RESERVED6[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ __I uint32_t RESERVED7[93]; @@ -390,7 +458,7 @@ typedef struct { /*!< UART Structure __IO uint32_t PSELCTS; /*!< Pin select for CTS. */ __IO uint32_t PSELRXD; /*!< Pin select for RXD. */ __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced. - Once read the character is consummed. If read when no character + Once read the character is consumed. If read when no character available, the UART will stop working. */ __O uint32_t TXD; /*!< TXD register. */ __I uint32_t RESERVED10; @@ -424,7 +492,7 @@ typedef struct { /*!< SPI Structure __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */ __IO uint32_t PSELMISO; /*!< Pin select for MISO. */ __I uint32_t RESERVED4; - __IO uint32_t RXD; /*!< RX data. */ + __I uint32_t RXD; /*!< RX data. */ __IO uint32_t TXD; /*!< TX data. */ __I uint32_t RESERVED5; __IO uint32_t FREQUENCY; /*!< SPI frequency */ @@ -462,26 +530,28 @@ typedef struct { /*!< TWI Structure __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */ __I uint32_t RESERVED6[4]; __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */ - __I uint32_t RESERVED7[49]; + __I uint32_t RESERVED7[3]; + __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */ + __I uint32_t RESERVED8[45]; __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */ - __I uint32_t RESERVED8[64]; + __I uint32_t RESERVED9[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED9[110]; + __I uint32_t RESERVED10[110]; __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */ - __I uint32_t RESERVED10[14]; + __I uint32_t RESERVED11[14]; __IO uint32_t ENABLE; /*!< Enable two-wire master. */ - __I uint32_t RESERVED11; + __I uint32_t RESERVED12; __IO uint32_t PSELSCL; /*!< Pin select for SCL. */ __IO uint32_t PSELSDA; /*!< Pin select for SDA. */ - __I uint32_t RESERVED12[2]; - __IO uint32_t RXD; /*!< RX data register. */ + __I uint32_t RESERVED13[2]; + __I uint32_t RXD; /*!< RX data register. */ __IO uint32_t TXD; /*!< TX data register. */ - __I uint32_t RESERVED13; + __I uint32_t RESERVED14; __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */ - __I uint32_t RESERVED14[24]; + __I uint32_t RESERVED15[24]; __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */ - __I uint32_t RESERVED15[668]; + __I uint32_t RESERVED16[668]; __IO uint32_t POWER; /*!< Peripheral power control. */ } NRF_TWI_Type; @@ -522,11 +592,11 @@ typedef struct { /*!< SPIS Structure __I uint32_t RESERVED9[7]; __IO uint32_t RXDPTR; /*!< RX data pointer. */ __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */ - __IO uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */ + __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */ __I uint32_t RESERVED10; __IO uint32_t TXDPTR; /*!< TX data pointer. */ __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */ - __IO uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */ + __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */ __I uint32_t RESERVED11; __IO uint32_t CONFIG; /*!< Configuration register. */ __I uint32_t RESERVED12; @@ -538,6 +608,59 @@ typedef struct { /*!< SPIS Structure } NRF_SPIS_Type; +/* ================================================================================ */ +/* ================ SPIM ================ */ +/* ================================================================================ */ + + +/** + * @brief SPI master with easyDMA 1. (SPIM) + */ + +typedef struct { /*!< SPIM Structure */ + __I uint32_t RESERVED0[4]; + __O uint32_t TASKS_START; /*!< Start SPI transaction. */ + __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */ + __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */ + __I uint32_t RESERVED2[56]; + __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */ + __I uint32_t RESERVED4; + __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */ + __I uint32_t RESERVED6[10]; + __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */ + __I uint32_t RESERVED7[44]; + __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */ + __I uint32_t RESERVED8[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED9[125]; + __IO uint32_t ENABLE; /*!< Enable SPIM. */ + __I uint32_t RESERVED10; + SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */ + __I uint32_t RESERVED11; + __I uint32_t RXDDATA; /*!< RXD register. */ + __IO uint32_t TXDDATA; /*!< TXD register. */ + __I uint32_t RESERVED12; + __IO uint32_t FREQUENCY; /*!< SPI frequency. */ + __I uint32_t RESERVED13[3]; + SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */ + __I uint32_t RESERVED14; + SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */ + __I uint32_t RESERVED15; + __IO uint32_t CONFIG; /*!< Configuration register. */ + __I uint32_t RESERVED16[26]; + __IO uint32_t ORC; /*!< Over-read character. */ + __I uint32_t RESERVED17[654]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_SPIM_Type; + + /* ================================================================================ */ /* ================ GPIOTE ================ */ /* ================================================================================ */ @@ -605,7 +728,8 @@ typedef struct { /*!< TIMER Structure __O uint32_t TASKS_STOP; /*!< Stop Timer. */ __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */ __O uint32_t TASKS_CLEAR; /*!< Clear timer. */ - __I uint32_t RESERVED0[12]; + __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */ + __I uint32_t RESERVED0[11]; __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */ __I uint32_t RESERVED1[60]; __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ @@ -656,7 +780,7 @@ typedef struct { /*!< RTC Structure __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register gives the value of EVTEN. */ __I uint32_t RESERVED4[110]; - __IO uint32_t COUNTER; /*!< Current COUNTER value. */ + __I uint32_t COUNTER; /*!< Current COUNTER value. */ __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */ __I uint32_t RESERVED5[13]; @@ -705,7 +829,7 @@ typedef struct { /*!< RNG Structure __I uint32_t RESERVED0[62]; __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */ __I uint32_t RESERVED1[63]; - __IO uint32_t SHORTS; /*!< Shortcut for the RNG. */ + __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */ __I uint32_t RESERVED2[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */ @@ -775,8 +899,8 @@ typedef struct { /*!< AAR Structure __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */ __I uint32_t RESERVED5; __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */ - __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during - resolution. A minimum of 3 bytes must be reserved. */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage + during resolution. A minimum of 3 bytes must be reserved. */ __I uint32_t RESERVED6[697]; __IO uint32_t POWER; /*!< Peripheral power control. */ } NRF_AAR_Type; @@ -802,7 +926,7 @@ typedef struct { /*!< CCM Structure __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */ __IO uint32_t EVENTS_ERROR; /*!< Error happened. */ __I uint32_t RESERVED1[61]; - __IO uint32_t SHORTS; /*!< Shortcut for the CCM. */ + __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */ __I uint32_t RESERVED2[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ @@ -811,11 +935,11 @@ typedef struct { /*!< CCM Structure __I uint32_t RESERVED4[63]; __IO uint32_t ENABLE; /*!< CCM enable. */ __IO uint32_t MODE; /*!< Operation mode. */ - __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector. */ - __IO uint32_t INPTR; /*!< Pointer to input packet. */ - __IO uint32_t OUTPTR; /*!< Pointer to output packet. */ - __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during - resolution. A minimum of 43 bytes must be reserved. */ + __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */ + __IO uint32_t INPTR; /*!< Pointer to the input packet. */ + __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage + during resolution. A minimum of 43 bytes must be reserved. */ __I uint32_t RESERVED5[697]; __IO uint32_t POWER; /*!< Peripheral power control. */ } NRF_CCM_Type; @@ -871,7 +995,7 @@ typedef struct { /*!< QDEC Structure ACC register different than zero. */ __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */ __I uint32_t RESERVED1[61]; - __IO uint32_t SHORTS; /*!< Shortcut for the QDEC. */ + __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */ __I uint32_t RESERVED2[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ @@ -904,7 +1028,7 @@ typedef struct { /*!< QDEC Structure /** - * @brief Wakeup Comparator. (LPCOMP) + * @brief Low power comparator. (LPCOMP) */ typedef struct { /*!< LPCOMP Structure */ @@ -917,7 +1041,7 @@ typedef struct { /*!< LPCOMP Structure __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */ __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */ __I uint32_t RESERVED1[60]; - __IO uint32_t SHORTS; /*!< Shortcut for the LPCOMP. */ + __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */ __I uint32_t RESERVED2[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ @@ -935,44 +1059,6 @@ typedef struct { /*!< LPCOMP Structure } NRF_LPCOMP_Type; -/* ================================================================================ */ -/* ================ COMP ================ */ -/* ================================================================================ */ - - -/** - * @brief Comparator. (COMP) - */ - -typedef struct { /*!< COMP Structure */ - __O uint32_t TASKS_START; /*!< Start the comparator. */ - __O uint32_t TASKS_STOP; /*!< Stop the comparator. */ - __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */ - __I uint32_t RESERVED0[61]; - __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid. */ - __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */ - __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */ - __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */ - __I uint32_t RESERVED1[60]; - __IO uint32_t SHORTS; /*!< Shortcut for the COMP. */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[61]; - __I uint32_t RESULT; /*!< Compare result. */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< Enable the COMP. */ - __IO uint32_t PSEL; /*!< Input pin select. */ - __IO uint32_t REFSEL; /*!< Reference select. */ - __IO uint32_t EXTREFSEL; /*!< External reference select. */ - __I uint32_t RESERVED5[8]; - __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit. */ - __IO uint32_t MODE; /*!< Mode configuration. */ - __I uint32_t RESERVED6[689]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_COMP_Type; - - /* ================================================================================ */ /* ================ SWI ================ */ /* ================================================================================ */ @@ -1048,7 +1134,13 @@ typedef struct { /*!< FICR Structure __I uint32_t PPFC; /*!< Pre-programmed factory code present. */ __I uint32_t RESERVED2; __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */ - __I uint32_t SIZERAMBLOCK[4]; /*!< Size of RAM block in bytes. */ + + union { + __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is + kept for backward compatinility purposes. Use SIZERAMBLOCKS + instead. */ + __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */ + }; __I uint32_t RESERVED3[5]; __I uint32_t CONFIGID; /*!< Configuration identifier. */ __I uint32_t DEVICEID[2]; /*!< Device identifier. */ @@ -1058,9 +1150,12 @@ typedef struct { /*!< FICR Structure __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */ __I uint32_t DEVICEADDR[2]; /*!< Device address. */ __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */ - __I uint32_t RESERVED5[15]; + __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit + mode. */ + __I uint32_t RESERVED5[10]; __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit mode. */ + FICR_INFO_Type INFO; /*!< Device info */ } NRF_FICR_Type; @@ -1140,6 +1235,7 @@ typedef struct { /*!< GPIO Structure #define NRF_SPI1_BASE 0x40004000UL #define NRF_TWI1_BASE 0x40004000UL #define NRF_SPIS1_BASE 0x40004000UL +#define NRF_SPIM1_BASE 0x40004000UL #define NRF_GPIOTE_BASE 0x40006000UL #define NRF_ADC_BASE 0x40007000UL #define NRF_TIMER0_BASE 0x40008000UL @@ -1155,7 +1251,6 @@ typedef struct { /*!< GPIO Structure #define NRF_RTC1_BASE 0x40011000UL #define NRF_QDEC_BASE 0x40012000UL #define NRF_LPCOMP_BASE 0x40013000UL -#define NRF_COMP_BASE 0x40013000UL #define NRF_SWI_BASE 0x40014000UL #define NRF_NVMC_BASE 0x4001E000UL #define NRF_PPI_BASE 0x4001F000UL @@ -1180,6 +1275,7 @@ typedef struct { /*!< GPIO Structure #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE) #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) @@ -1195,7 +1291,6 @@ typedef struct { /*!< GPIO Structure #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) -#define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE) #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE) #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) @@ -1214,3 +1309,4 @@ typedef struct { /*!< GPIO Structure #endif /* nRF51_H */ + diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51822.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51822.h deleted file mode 100644 index 43e6bd3c31..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51822.h +++ /dev/null @@ -1,27 +0,0 @@ -/* mbed Microcontroller Library - - * Copyright (c) 2013 Nordic Semiconductor. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#ifndef NRF_H -#define NRF_H - -#include "nordic_global.h" -#include "compiler_abstraction.h" -#include "nrf51.h" -#include "nrf51_bitfields.h" -#endif /* NRF_H */ - diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h index 8f88a8e5f8..52aa653943 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h @@ -1,22 +1,38 @@ -/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. +/* Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ - - #ifndef __NRF51_BITS_H #define __NRF51_BITS_H /*lint ++flb "Enter library region */ -//#include +#include /* Peripheral: AAR */ /* Description: Accelerated Address Resolver. */ @@ -213,124 +229,604 @@ /* Register: AMLI_RAMPRI_CPU0 */ /* Description: Configurable priority configuration register for CPU0. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Register: AMLI_RAMPRI_SPIS1 */ /* Description: Configurable priority configuration register for SPIS1. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Register: AMLI_RAMPRI_RADIO */ /* Description: Configurable priority configuration register for RADIO. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Register: AMLI_RAMPRI_ECB */ /* Description: Configurable priority configuration register for ECB. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Register: AMLI_RAMPRI_CCM */ /* Description: Configurable priority configuration register for CCM. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Register: AMLI_RAMPRI_AAR */ /* Description: Configurable priority configuration register for AAR. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Peripheral: CCM */ /* Description: AES CCM Mode Encryption. */ /* Register: CCM_SHORTS */ -/* Description: Shortcut for the CCM. */ +/* Description: Shortcuts for the CCM. */ -/* Bit 0 : Short-cut between ENDKSGEN event and CRYPT task. */ +/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */ @@ -486,6 +982,15 @@ #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ +/* Register: CLOCK_HFCLKRUN */ +/* Description: Task HFCLKSTART trigger status. */ + +/* Bit 0 : Task HFCLKSTART trigger status. */ +#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */ + /* Register: CLOCK_HFCLKSTAT */ /* Description: High frequency clock status. */ @@ -501,6 +1006,15 @@ #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */ #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */ +/* Register: CLOCK_LFCLKRUN */ +/* Description: Task LFCLKSTART triggered status. */ + +/* Bit 0 : Task LFCLKSTART triggered status. */ +#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */ + /* Register: CLOCK_LFCLKSTAT */ /* Description: Low frequency clock status. */ @@ -517,6 +1031,16 @@ #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */ #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */ +/* Register: CLOCK_LFCLKSRCCOPY */ +/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ + +/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ + /* Register: CLOCK_LFCLKSRC */ /* Description: Clock source for the LFCLK clock. */ @@ -540,197 +1064,8 @@ /* Bits 7..0 : External Xtal frequency selection. */ #define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ #define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ -#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used. */ -#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used. */ - - -/* Peripheral: COMP */ -/* Description: Comparator. */ - -/* Register: COMP_SHORTS */ -/* Description: Shortcut for the COMP. */ - -/* Bit 4 : Short-cut between CROSS event and STOP task. */ -#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ -#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ -#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 3 : Short-cut between UP event and STOP task. */ -#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ -#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ -#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 2 : Short-cut between DOWN event and STOP task. */ -#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ -#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ -#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 1 : Short-cut between RADY event and STOP task. */ -#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ -#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ -#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Short-cut between READY event and SAMPLE task. */ -#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ -#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ -#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: COMP_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 3 : Enable interrupt on CROSS event. */ -#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on UP event. */ -#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ -#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ -#define COMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on DOWN event. */ -#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on READY event. */ -#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ -#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define COMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: COMP_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 3 : Disable interrupt on CROSS event. */ -#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on UP event. */ -#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ -#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ -#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on DOWN event. */ -#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on READY event. */ -#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ -#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: COMP_RESULT */ -/* Description: Compare result. */ - -/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ -#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ -#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ -#define COMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */ -#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */ - -/* Register: COMP_ENABLE */ -/* Description: Enable the COMP. */ - -/* Bits 1..0 : Enable or disable COMP. */ -#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define COMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled COMP. */ -#define COMP_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable COMP. */ - -/* Register: COMP_PSEL */ -/* Description: Input pin select. */ - -/* Bits 2..0 : Analog input pin select. */ -#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ -#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ -#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */ - -/* Register: COMP_REFSEL */ -/* Description: Reference select. */ - -/* Bits 2..0 : Reference select. */ -#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ -#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ -#define COMP_REFSEL_REFSEL_Int1V5 (0UL) /*!< Use internal 1V5 as reference. */ -#define COMP_REFSEL_REFSEL_Int2V0 (1UL) /*!< Use internal 2V0 as reference. */ -#define COMP_REFSEL_REFSEL_Int2V5 (2UL) /*!< Use internal 2V5 as reference. */ -#define COMP_REFSEL_REFSEL_Supply (4UL) /*!< Use supply as reference. */ -#define COMP_REFSEL_REFSEL_ARef (5UL) /*!< Use external analog reference as reference. */ - -/* Register: COMP_EXTREFSEL */ -/* Description: External reference select. */ - -/* Bit 0 : External analog reference pin selection. */ -#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ -#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */ - -/* Register: COMP_TH */ -/* Description: Threshold configuration for hysteresis unit. */ - -/* Bits 13..8 : VDOWN configuration. */ -#define COMP_TH_THDOWN_Pos (8UL) /*!< Position of THDOWN field. */ -#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ - -/* Bits 5..0 : VUP configuration. */ -#define COMP_TH_THUP_Pos (0UL) /*!< Position of THUP field. */ -#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ - -/* Register: COMP_MODE */ -/* Description: Mode configuration. */ - -/* Bit 8 : Main operation mode. */ -#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ -#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ -#define COMP_MODE_MAIN_Single (0UL) /*!< Single ended mode. */ -#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode. */ - -/* Bits 1..0 : Speed and power mode. */ -#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ -#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ -#define COMP_MODE_SP_Low (0UL) /*!< Low power mode. */ -#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode. */ -#define COMP_MODE_SP_High (2UL) /*!< High speed mode. */ - -/* Register: COMP_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define COMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define COMP_POWER_POWER_Msk (0x1UL << COMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define COMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define COMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ +#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */ +#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */ /* Peripheral: ECB */ @@ -821,6 +1156,66 @@ #define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */ #define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */ +/* Bit 0 : Override default values for NRF_1Mbit mode. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */ + +/* Register: FICR_INFO_PART */ +/* Description: Part code */ + +/* Bits 31..0 : Part code */ +#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ +#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N51822 (0x51822UL) /*!< nRF51822 */ +#define FICR_INFO_PART_PART_N51422 (0x51422UL) /*!< nRF51422 */ +#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_VARIANT */ +/* Description: Part variant */ + +/* Bits 31..0 : Part variant */ +#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /*!< nRF51-C (XLR3) */ +#define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /*!< nRF51-D (L3) */ +#define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /*!< nRF51-E (XLR3P) */ +#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_PACKAGE */ +/* Description: Package option */ + +/* Bits 31..0 : Package option */ +#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /*!< 48-pin QFN with 31 GPIO */ +#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /*!< nRF51x22 CDxx - WLCSP 56 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /*!< nRF51x22 CExx - WLCSP 62 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /*!< nRF51x22 CFxx - WLCSP 62 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /*!< nRF51x22 CTxx - WLCSP 62 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_RAM */ +/* Description: RAM variant */ + +/* Bits 31..0 : RAM variant */ +#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ +#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ +#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ +#define FICR_INFO_RAM_RAM_K16 (16UL) /*!< 16 kByte RAM. */ +#define FICR_INFO_RAM_RAM_K32 (32UL) /*!< 32 kByte RAM. */ + +/* Register: FICR_INFO_FLASH */ +/* Description: Flash variant */ + +/* Bits 31..0 : Flash variant */ +#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ +#define FICR_INFO_FLASH_FLASH_K128 (128UL) /*!< 128 kByte FLASH. */ +#define FICR_INFO_FLASH_FLASH_K256 (256UL) /*!< 256 kByte FLASH. */ + /* Peripheral: GPIO */ /* Description: General purpose input and output. */ @@ -2477,36 +2872,36 @@ /* Peripheral: LPCOMP */ -/* Description: Wakeup Comparator. */ +/* Description: Low power comparator. */ /* Register: LPCOMP_SHORTS */ -/* Description: Shortcut for the LPCOMP. */ +/* Description: Shortcuts for the LPCOMP. */ -/* Bit 4 : Short-cut between CROSS event and STOP task. */ +/* Bit 4 : Shortcut between CROSS event and STOP task. */ #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */ #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */ -/* Bit 3 : Short-cut between UP event and STOP task. */ +/* Bit 3 : Shortcut between UP event and STOP task. */ #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */ #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */ -/* Bit 2 : Short-cut between DOWN event and STOP task. */ +/* Bit 2 : Shortcut between DOWN event and STOP task. */ #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */ #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */ -/* Bit 1 : Short-cut between RADY event and STOP task. */ +/* Bit 1 : Shortcut between RADY event and STOP task. */ #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ -/* Bit 0 : Short-cut between READY event and SAMPLE task. */ +/* Bit 0 : Shortcut between READY event and SAMPLE task. */ #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */ @@ -2613,13 +3008,13 @@ /* Bits 2..0 : Reference select. */ #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ #define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ -#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use analog supply with a 1/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use analog supply with a 2/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use analog supply with a 3/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use analog supply with a 4/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use analog supply with a 5/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use analog supply with a 6/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use analog supply with a 7/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */ #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */ /* Register: LPCOMP_EXTREFSEL */ @@ -2669,11 +3064,11 @@ #define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ #define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ -/* Bit 19 : LPCOMP_COMP region configuration. */ -#define MPU_PERR0_LPCOMP_COMP_Pos (19UL) /*!< Position of LPCOMP_COMP field. */ -#define MPU_PERR0_LPCOMP_COMP_Msk (0x1UL << MPU_PERR0_LPCOMP_COMP_Pos) /*!< Bit mask of LPCOMP_COMP field. */ -#define MPU_PERR0_LPCOMP_COMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_LPCOMP_COMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ +/* Bit 19 : LPCOMP region configuration. */ +#define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */ +#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ +#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ /* Bit 18 : QDEC region configuration. */ #define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */ @@ -2784,7 +3179,7 @@ #define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ /* Register: MPU_PROTENSET0 */ -/* Description: Protection bit enable set register for low addresses. */ +/* Description: Erase and write protection bit enable set register. */ /* Bit 31 : Protection enable for region 31. */ #define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */ @@ -3011,7 +3406,7 @@ #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */ /* Register: MPU_PROTENSET1 */ -/* Description: Protection bit enable set register for high addresses. */ +/* Description: Erase and write protection bit enable set register. */ /* Bit 31 : Protection enable for region 63. */ #define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */ @@ -3238,7 +3633,7 @@ #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */ /* Register: MPU_DISABLEINDEBUG */ -/* Description: Disable protection mechanism in debug mode. */ +/* Description: Disable erase and write protection mechanism in debug mode. */ /* Bit 0 : Disable protection mechanism in debug mode. */ #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ @@ -3246,6 +3641,14 @@ #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */ #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */ +/* Register: MPU_PROTBLOCKSIZE */ +/* Description: Erase and write protection block size. */ + +/* Bits 1..0 : Erase and write protection block size. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */ + /* Peripheral: NVMC */ /* Description: Non Volatile Memory Controller. */ @@ -3342,6 +3745,33 @@ #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +/* Register: POWER_RAMSTATUS */ +/* Description: Ram status register. */ + +/* Bit 3 : RAM block 3 status. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */ + +/* Bit 2 : RAM block 2 status. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */ + +/* Bit 1 : RAM block 1 status. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */ + +/* Bit 0 : RAM block 0 status. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */ + /* Register: POWER_SYSTEMOFF */ /* Description: System off register. */ @@ -3377,18 +3807,6 @@ /* Register: POWER_RAMON */ /* Description: Ram on/off. */ -/* Bit 19 : RAM block 3 behaviour in OFF mode. */ -#define POWER_RAMON_OFFRAM3_Pos (19UL) /*!< Position of OFFRAM3 field. */ -#define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ -#define POWER_RAMON_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */ -#define POWER_RAMON_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */ - -/* Bit 18 : RAM block 2 behaviour in OFF mode. */ -#define POWER_RAMON_OFFRAM2_Pos (18UL) /*!< Position of OFFRAM2 field. */ -#define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ -#define POWER_RAMON_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */ -#define POWER_RAMON_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */ - /* Bit 17 : RAM block 1 behaviour in OFF mode. */ #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ @@ -3401,18 +3819,6 @@ #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */ #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */ -/* Bit 3 : RAM block 3 behaviour in ON mode. */ -#define POWER_RAMON_ONRAM3_Pos (3UL) /*!< Position of ONRAM3 field. */ -#define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ -#define POWER_RAMON_ONRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in ON mode. */ -#define POWER_RAMON_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */ - -/* Bit 2 : RAM block 2 behaviour in ON mode. */ -#define POWER_RAMON_ONRAM2_Pos (2UL) /*!< Position of ONRAM2 field. */ -#define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ -#define POWER_RAMON_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */ -#define POWER_RAMON_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */ - /* Bit 1 : RAM block 1 behaviour in ON mode. */ #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ @@ -3428,12 +3834,39 @@ /* Register: POWER_RESET */ /* Description: Pin reset functionality configuration register. This register is a retained register. */ -/* Bit 0 : Enable pin reset in debug interface mode. */ +/* Bit 0 : Enable or disable pin reset in debug interface mode. */ #define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ #define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ #define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */ #define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */ +/* Register: POWER_RAMONB */ +/* Description: Ram on/off. */ + +/* Bit 17 : RAM block 3 behaviour in OFF mode. */ +#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */ +#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */ + +/* Bit 16 : RAM block 2 behaviour in OFF mode. */ +#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */ +#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */ + +/* Bit 1 : RAM block 3 behaviour in ON mode. */ +#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */ +#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */ + +/* Bit 0 : RAM block 2 behaviour in ON mode. */ +#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */ +#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */ + /* Register: POWER_DCDCEN */ /* Description: DCDC converter enable configuration register. */ @@ -3443,6 +3876,21 @@ #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */ #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */ +/* Register: POWER_DCDCFORCE */ +/* Description: DCDC power-up force register. */ + +/* Bit 1 : DCDC power-up force on. */ +#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */ +#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */ +#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */ +#define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */ + +/* Bit 0 : DCDC power-up force off. */ +#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ +#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ +#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */ +#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */ + /* Peripheral: PPI */ /* Description: PPI controller. */ @@ -4372,15 +4820,15 @@ /* Description: Rotary decoder. */ /* Register: QDEC_SHORTS */ -/* Description: Shortcut for the QDEC. */ +/* Description: Shortcuts for the QDEC. */ -/* Bit 1 : Short-cut between SAMPLERDY event and STOP task. */ +/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ -/* Bit 0 : Short-cut between REPORTRDY event and READCLRACC task. */ +/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */ @@ -4501,9 +4949,9 @@ /* Register: QDEC_LEDPRE */ /* Description: Time LED is switched ON before the sample. */ -/* Bits 7..0 : Period in us the LED in switched on prior to sampling. */ +/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */ #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ -#define QDEC_LEDPRE_LEDPRE_Msk (0xFFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ +#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ /* Register: QDEC_ACCDBL */ /* Description: Accumulated double (error) transitions register. */ @@ -4533,7 +4981,7 @@ /* Description: The radio. */ /* Register: RADIO_SHORTS */ -/* Description: Shortcut for the radio. */ +/* Description: Shortcuts for the radio. */ /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ @@ -4724,6 +5172,13 @@ #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */ #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */ +/* Register: RADIO_CD */ +/* Description: Carrier detect. */ + +/* Bit 0 : Carrier detect. */ +#define RADIO_CD_CD_Pos (0UL) /*!< Position of CD field. */ +#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /*!< Bit mask of CD field. */ + /* Register: RADIO_RXMATCH */ /* Description: Received address. */ @@ -4741,7 +5196,7 @@ /* Register: RADIO_DAI */ /* Description: Device address match index. */ -/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that got an address match. */ +/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */ #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ @@ -4920,10 +5375,10 @@ /* Description: CRC configuration. */ /* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */ -#define RADIO_CRCCNF_SKIP_ADDR_Pos (8UL) /*!< Position of SKIP_ADDR field. */ -#define RADIO_CRCCNF_SKIP_ADDR_Msk (0x1UL << RADIO_CRCCNF_SKIP_ADDR_Pos) /*!< Bit mask of SKIP_ADDR field. */ -#define RADIO_CRCCNF_SKIP_ADDR_Include (0UL) /*!< Include packet address in CRC calculation. */ -#define RADIO_CRCCNF_SKIP_ADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */ +#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */ +#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */ /* Bits 1..0 : CRC length. Decision point: START task. */ #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ @@ -4936,9 +5391,9 @@ /* Register: RADIO_CRCPOLY */ /* Description: CRC polynomial. */ -/* Bits 23..1 : CRC polynomial. Decision point: START task. */ -#define RADIO_CRCPOLY_CRCPOLY_Pos (1UL) /*!< Position of CRCPOLY field. */ -#define RADIO_CRCPOLY_CRCPOLY_Msk (0x7FFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ +/* Bits 23..0 : CRC polynomial. Decision point: START task. */ +#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ +#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ /* Register: RADIO_CRCINIT */ /* Description: CRC initial value. */ @@ -4951,16 +5406,16 @@ /* Description: Test features enable register. */ /* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */ -#define RADIO_TEST_PLL_LOCK_Pos (1UL) /*!< Position of PLL_LOCK field. */ -#define RADIO_TEST_PLL_LOCK_Msk (0x1UL << RADIO_TEST_PLL_LOCK_Pos) /*!< Bit mask of PLL_LOCK field. */ -#define RADIO_TEST_PLL_LOCK_Disabled (0UL) /*!< PLL lock disabled. */ -#define RADIO_TEST_PLL_LOCK_Enabled (1UL) /*!< PLL lock enabled. */ +#define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */ +#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */ +#define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */ +#define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */ /* Bit 0 : Constant carrier. Decision point: TXEN task. */ -#define RADIO_TEST_CONST_CARRIER_Pos (0UL) /*!< Position of CONST_CARRIER field. */ -#define RADIO_TEST_CONST_CARRIER_Msk (0x1UL << RADIO_TEST_CONST_CARRIER_Pos) /*!< Bit mask of CONST_CARRIER field. */ -#define RADIO_TEST_CONST_CARRIER_Disabled (0UL) /*!< Constant carrier disabled. */ -#define RADIO_TEST_CONST_CARRIER_Enabled (1UL) /*!< Constant carrier enabled. */ +#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */ +#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */ +#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */ +#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */ /* Register: RADIO_TIFS */ /* Description: Inter Frame Spacing in microseconds. */ @@ -4995,9 +5450,9 @@ /* Register: RADIO_DATAWHITEIV */ /* Description: Data whitening initial value. */ -/* Bits 5..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */ +/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */ #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ -#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x3FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ /* Register: RADIO_DAP */ /* Description: Device address prefix. */ @@ -5092,28 +5547,28 @@ /* Register: RADIO_OVERRIDE0 */ /* Description: Trim value override register 0. */ -/* Bits 31..0 : Trim value override register 0. */ +/* Bits 31..0 : Trim value override 0. */ #define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */ #define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */ /* Register: RADIO_OVERRIDE1 */ /* Description: Trim value override register 1. */ -/* Bits 31..0 : Trim value override register 1. */ +/* Bits 31..0 : Trim value override 1. */ #define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */ #define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */ /* Register: RADIO_OVERRIDE2 */ /* Description: Trim value override register 2. */ -/* Bits 31..0 : Trim value override register 2. */ +/* Bits 31..0 : Trim value override 2. */ #define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */ #define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */ /* Register: RADIO_OVERRIDE3 */ /* Description: Trim value override register 3. */ -/* Bits 31..0 : Trim value override register 3. */ +/* Bits 31..0 : Trim value override 3. */ #define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */ #define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */ @@ -5126,7 +5581,7 @@ #define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */ #define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */ -/* Bits 27..0 : Trim value override register 4. */ +/* Bits 27..0 : Trim value override 4. */ #define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */ #define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */ @@ -5144,9 +5599,9 @@ /* Description: Random Number Generator. */ /* Register: RNG_SHORTS */ -/* Description: Shortcut for the RNG. */ +/* Description: Shortcuts for the RNG. */ -/* Bit 0 : Short-cut between VALRDY event and STOP task. */ +/* Bit 0 : Shortcut between VALRDY event and STOP task. */ #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ @@ -5542,6 +5997,211 @@ #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ +/* Peripheral: SPIM */ +/* Description: SPI master with easyDMA 1. */ + +/* Register: SPIM_SHORTS */ +/* Description: Shortcuts for SPIM. */ + +/* Bit 17 : Shortcut between END event and START task. */ +#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ +#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */ +#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: SPIM_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 19 : Enable interrupt on STARTED event. */ +#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 8 : Enable interrupt on ENDTX event. */ +#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 6 : Enable interrupt on END event. */ +#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 4 : Enable interrupt on ENDRX event. */ +#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on STOPPED event. */ +#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: SPIM_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 19 : Disable interrupt on STARTED event. */ +#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 8 : Disable interrupt on ENDTX event. */ +#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 6 : Disable interrupt on END event. */ +#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 4 : Disable interrupt on ENDRX event. */ +#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on STOPPED event. */ +#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: SPIM_ENABLE */ +/* Description: Enable SPIM. */ + +/* Bits 3..0 : Enable or disable SPIM. */ +#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */ +#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */ + +/* Register: SPIM_RXDDATA */ +/* Description: RXD register. */ + +/* Bits 7..0 : RX data received. Double buffered. */ +#define SPIM_RXDDATA_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: SPIM_TXDDATA */ +/* Description: TXD register. */ + +/* Bits 7..0 : TX data to send. Double buffered. */ +#define SPIM_TXDDATA_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: SPIM_FREQUENCY */ +/* Description: SPI frequency. */ + +/* Bits 31..0 : SPI master data rate. */ +#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */ + +/* Register: SPIM_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 2 : Serial clock (SCK) polarity. */ +#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ +#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ + +/* Bit 1 : Serial clock (SCK) phase. */ +#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ +#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ + +/* Bit 0 : Bit order. */ +#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ +#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ + +/* Register: SPIM_ORC */ +/* Description: Over-read character. */ + +/* Bits 7..0 : Over-read character. */ +#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + +/* Register: SPIM_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + +/* Register: SPIM_RXD_PTR */ +/* Description: Data pointer. */ + +/* Bits 31..0 : Data pointer. */ +#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_RXD_MAXCNT */ +/* Description: Maximum number of buffer bytes to receive. */ + +/* Bits 7..0 : Maximum number of buffer bytes to receive. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_RXD_AMOUNT */ +/* Description: Number of bytes received in the last transaction. */ + +/* Bits 7..0 : Number of bytes received in the last transaction. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_TXD_PTR */ +/* Description: Data pointer. */ + +/* Bits 31..0 : Data pointer. */ +#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_TXD_MAXCNT */ +/* Description: Maximum number of buffer bytes to send. */ + +/* Bits 7..0 : Maximum number of buffer bytes to send. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_TXD_AMOUNT */ +/* Description: Number of bytes sent in the last transaction. */ + +/* Bits 7..0 : Number of bytes sent in the last transaction. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + /* Peripheral: SPIS */ /* Description: SPI slave 1. */ @@ -5905,6 +6565,13 @@ /* Register: TWI_INTENSET */ /* Description: Interrupt enable set register. */ +/* Bit 18 : Enable interrupt on SUSPENDED event. */ +#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */ + /* Bit 14 : Enable interrupt on BB event. */ #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ @@ -5943,6 +6610,13 @@ /* Register: TWI_INTENCLR */ /* Description: Interrupt enable clear register. */ +/* Bit 18 : Disable interrupt on SUSPENDED event. */ +#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */ + /* Bit 14 : Disable interrupt on BB event. */ #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ @@ -6049,7 +6723,7 @@ /* Description: Universal Asynchronous Receiver/Transmitter. */ /* Register: UART_SHORTS */ -/* Description: Shortcuts for TWI. */ +/* Description: Shortcuts for UART. */ /* Bit 4 : Shortcut between NCTS event and the STOPRX task. */ #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ @@ -6194,7 +6868,7 @@ #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */ /* Register: UART_RXD */ -/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consummed. If read when no character available, the UART will stop working. */ +/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */ /* Bits 7..0 : RX data from previous transfer. Double buffered. */ #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/nrf_delay.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf_delay.h similarity index 99% rename from libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/nrf_delay.h rename to libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf_delay.h index b97e96924b..c9b0123341 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/nrf_delay.h +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf_delay.h @@ -47,7 +47,7 @@ __ASM ( #elif defined ( __GNUC__ ) static void __INLINE nrf_delay_us(uint32_t volatile number_of_us) { - do + do { __ASM volatile ( "NOP\n\t" diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.c similarity index 54% rename from libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c rename to libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.c index 3664b28158..cb98405feb 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.c @@ -1,25 +1,42 @@ -/* mbed Microcontroller Library - - * Copyright (c) 2015 Nordic Semiconductor. +/* Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * - * http://www.apache.org/licenses/LICENSE-2.0 + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. */ +/* NOTE: Template files (including this one) are application specific and therefore expected to + be copied into the application project folder prior to its use! */ #include #include -#include "nrf51822.h" -#include "system_nrf51822.h" +#include "nrf.h" +#include "system_nrf51.h" + +/*lint ++flb "Enter library region" */ #define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */ @@ -45,20 +62,20 @@ void SystemInit(void) /* If desired, switch off the unused RAM to lower consumption by the use of RAMON register. It can also be done in the application main() function. */ - // Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required - // to enable the use of peripherals" found at Product Anomaly document for your device found at - // https://www.nordicsemi.com/. The side effect of executing these instructions in the devices - // that do not need it is that the new peripherals in the second generation devices (LPCOMP for - // example) will not be available. + /* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required + to enable the use of peripherals" found at Product Anomaly document for your device found at + https://www.nordicsemi.com/. The side effect of executing these instructions in the devices + that do not need it is that the new peripherals in the second generation devices (LPCOMP for + example) will not be available. */ if (is_manual_peripheral_setup_needed()) { *(uint32_t volatile *)0x40000504 = 0xC007FFDF; *(uint32_t volatile *)0x40006C18 = 0x00008000; } - // Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG - // register is incorrect" found at Product Anomaly document four your device found at - // https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. + /* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG + register is incorrect" found at Product Anomaly document four your device found at + https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */ if (is_disabled_in_debug_needed()) { NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos; @@ -114,3 +131,4 @@ static bool is_disabled_in_debug_needed(void) return false; } +/*lint --flb "Leave library region" */ diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.h new file mode 100644 index 0000000000..ae613609dd --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.h @@ -0,0 +1,68 @@ +/* Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef SYSTEM_NRF51_H +#define SYSTEM_NRF51_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_NRF51_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.h deleted file mode 100644 index 4c8ef343a6..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.h +++ /dev/null @@ -1,58 +0,0 @@ -/* mbed Microcontroller Library - - * Copyright (c) 2013 Nordic Semiconductor. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#ifndef SYSTEM_NRF51_H -#define SYSTEM_NRF51_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_NRF51_H */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/crc16.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/crc16/crc16.h old mode 100755 new mode 100644 similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/crc16.h rename to libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/crc16/crc16.h diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_scheduler.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/scheduler/app_scheduler.h old mode 100755 new mode 100644 similarity index 85% rename from libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_scheduler.h rename to libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/scheduler/app_scheduler.h index 53ff42df3d..05117cb48f --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_scheduler.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/scheduler/app_scheduler.h @@ -19,7 +19,7 @@ * @brief The scheduler is used for transferring execution from the interrupt context to the main * context. * - * @details See @ref ble_sdk_apps_seq_diagrams for sequence diagrams illustrating the flow of events + * @details See @ref seq_diagrams_sched for sequence diagrams illustrating the flow of events * when using the Scheduler. * * @section app_scheduler_req Requirements: @@ -39,8 +39,10 @@ * scheduler's queue. The app_sched_execute() function will pull this event and call its * handler in the main context. * - * For an example usage of the scheduler, please see the implementations of + * @if (SD_S110 && !SD_S310) + * For an example usage of the scheduler, see the implementations of * @ref ble_sdk_app_hids_mouse and @ref ble_sdk_app_hids_keyboard. + * @endif * * @image html scheduler_working.jpg The high level design of the scheduler */ @@ -95,7 +97,7 @@ typedef void (*app_sched_event_handler_t)(void * p_event_data, uint16_t event_si * @param[in] max_event_size Maximum size of events to be passed through the scheduler. * @param[in] queue_size Number of entries in scheduler queue (i.e. the maximum number of * events that can be scheduled for execution). - * @param[in] p_event_buffer Pointer to memory buffer for holding the scheduler queue. It must + * @param[in] p_evt_buffer Pointer to memory buffer for holding the scheduler queue. It must * be dimensioned using the APP_SCHED_BUFFER_SIZE() macro. The buffer * must be aligned to a 4 byte boundary. * @@ -120,7 +122,7 @@ void app_sched_execute(void); * @details Puts an event into the event queue. * * @param[in] p_event_data Pointer to event data to be scheduled. - * @param[in] p_event_size Size of event data to be scheduled. + * @param[in] event_size Size of event data to be scheduled. * @param[in] handler Event handler to receive the event. * * @return NRF_SUCCESS on success, otherwise an error code. @@ -129,6 +131,22 @@ uint32_t app_sched_event_put(void * p_event_data, uint16_t event_size, app_sched_event_handler_t handler); +#ifdef APP_SCHEDULER_WITH_PAUSE +/**@brief A function to pause the scheduler. + * + * @details When the scheduler is paused events are not pulled from the scheduler queue for + * processing. The function can be called multiple times. To unblock the scheduler the + * function @ref app_sched_resume has to be called the same number of times. + */ +void app_sched_pause(void); + +/**@brief A function to resume a scheduler. + * + * @details To unblock the scheduler this function has to be called the same number of times as + * @ref app_sched_pause function. + */ +void app_sched_resume(void); +#endif #endif // APP_SCHEDULER_H__ /** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_error.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_error.h old mode 100755 new mode 100644 similarity index 67% rename from libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_error.h rename to libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_error.h index c4d0e9a974..616634c887 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_error.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_error.h @@ -1,5 +1,6 @@ /* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. * + * The information contained herein is property of Nordic Semiconductor ASA. * Terms and conditions of usage are described in detail in NORDIC * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. * @@ -8,7 +9,7 @@ * the file. * */ - + /** @file * * @defgroup app_error Common application error handler @@ -25,36 +26,35 @@ #include #include "nrf_error.h" -#ifdef __cplusplus -extern "C" { -#endif - -/**@brief Function for error handling, which is called when an error has occurred. +/**@brief Function for error handling, which is called when an error has occurred. * * @param[in] error_code Error code supplied to the handler. * @param[in] line_num Line number where the handler is called. - * @param[in] p_file_name Pointer to the file name. + * @param[in] p_file_name Pointer to the file name. */ void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name); -#ifdef __cplusplus -} -#endif - -/**@brief Macro for calling error handler function. +/**@brief Macro for calling error handler function. * * @param[in] ERR_CODE Error code supplied to the error handler. */ +#ifdef DEBUG #define APP_ERROR_HANDLER(ERR_CODE) \ do \ { \ - /* app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__); */ \ + app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__); \ } while (0) - -/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS. +#else +#define APP_ERROR_HANDLER(ERR_CODE) \ + do \ + { \ + app_error_handler((ERR_CODE), 0, 0); \ + } while (0) +#endif +/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS. * * @param[in] ERR_CODE Error code supplied to the error handler. - */ + */ #define APP_ERROR_CHECK(ERR_CODE) \ do \ { \ @@ -63,21 +63,21 @@ void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p { \ APP_ERROR_HANDLER(LOCAL_ERR_CODE); \ } \ - } while (0) - -/**@brief Macro for calling error handler function if supplied boolean value is false. + } while (0) + +/**@brief Macro for calling error handler function if supplied boolean value is false. * * @param[in] BOOLEAN_VALUE Boolean value to be evaluated. */ -#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE) \ - do \ - { \ - const bool LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \ - if (!LOCAL_BOOLEAN_VALUE) \ - { \ - APP_ERROR_HANDLER(0); \ - } \ - } while (0) +#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE) \ + do \ + { \ + const uint32_t LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \ + if (!LOCAL_BOOLEAN_VALUE) \ + { \ + APP_ERROR_HANDLER(0); \ + } \ + } while (0) #endif // APP_ERROR_H__ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_util.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_util.h old mode 100755 new mode 100644 similarity index 97% rename from libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_util.h rename to libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_util.h index f6405439df..c4b1022eb1 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_util.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_util.h @@ -86,9 +86,9 @@ typedef struct */ #define IS_POWER_OF_TWO(A) ( ((A) != 0) && ((((A) - 1) & (A)) == 0) ) -/**@brief To convert ticks to millisecond - * @param[in] time Number of millseconds that needs to be converted. - * @param[in] resolution Units to be converted. +/**@brief To convert milliseconds to ticks. + * @param[in] TIME Number of milliseconds to convert. + * @param[in] RESOLUTION Unit to be converted to in [us/ticks]. */ #define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION)) diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_button.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_button.h deleted file mode 100755 index 5ddff8960d..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_button.h +++ /dev/null @@ -1,187 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup app_button Button Handler - * @{ - * @ingroup app_common - * - * @brief Buttons handling module. - * - * @details The button handler uses the @ref app_gpiote to detect that a button has been - * pushed. To handle debouncing, it will start a timer in the GPIOTE event handler. - * The button will only be reported as pushed if the corresponding pin is still active when - * the timer expires. If there is a new GPIOTE event while the timer is running, the timer - * is restarted. - * Use the USE_SCHEDULER parameter of the APP_BUTTON_INIT() macro to select if the - * @ref app_scheduler is to be used or not. - * - * @note The app_button module uses the app_timer module. The user must ensure that the queue in - * app_timer is large enough to hold the app_timer_stop() / app_timer_start() operations - * which will be executed on each event from GPIOTE module (2 operations), as well as other - * app_timer operations queued simultaneously in the application. - * - * @note Even if the scheduler is not used, app_button.h will include app_scheduler.h, so when - * compiling, app_scheduler.h must be available in one of the compiler include paths. - */ - -#ifndef APP_BUTTON_H__ -#define APP_BUTTON_H__ - -#include -#include -#include "app_error.h" -#include "app_scheduler.h" -#include "nrf_gpio.h" - -#define APP_BUTTON_SCHED_EVT_SIZE sizeof(app_button_event_t) /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). */ -#define APP_BUTTON_PUSH 1 /**< Indicates that a button is pushed. */ -#define APP_BUTTON_RELEASE 0 /**< Indicates that a button is released. */ -#define APP_BUTTON_ACTIVE_HIGH 1 /**< Indicates that a button is active high. */ -#define APP_BUTTON_ACTIVE_LOW 0 /**< Indicates that a button is active low. */ - -/**@brief Button event handler type. */ -typedef void (*app_button_handler_t)(uint8_t pin_no, uint8_t button_action); - -/**@brief Type of function for passing events from the Button Handler module to the scheduler. */ -typedef uint32_t (*app_button_evt_schedule_func_t) (app_button_handler_t button_handler, - uint8_t pin_no, - uint8_t button_action); - -/**@brief Button configuration structure. */ -typedef struct -{ - uint8_t pin_no; /**< Pin to be used as a button. */ - uint8_t active_state; /**< APP_BUTTON_ACTIVE_HIGH or APP_BUTTON_ACTIVE_LOW. */ - nrf_gpio_pin_pull_t pull_cfg; /**< Pull-up or -down configuration. */ - app_button_handler_t button_handler; /**< Handler to be called when button is pushed. */ -} app_button_cfg_t; - -/**@brief Pin transition direction struct. */ -typedef struct -{ - uint32_t high_to_low; /**Pin went from high to low */ - uint32_t low_to_high; /**Pin went from low to high */ -} pin_transition_t; - -/**@brief Macro for initializing the Button Handler module. - * - * @details It will initialize the specified pins as buttons, and configure the Button Handler - * module as a GPIOTE user (but it will not enable button detection). It will also connect - * the Button Handler module to the scheduler (if specified). - * - * @param[in] BUTTONS Array of buttons to be used (type app_button_cfg_t, must be - * static!). - * @param[in] BUTTON_COUNT Number of buttons. - * @param[in] DETECTION_DELAY Delay from a GPIOTE event until a button is reported as pushed. - * @param[in] USE_SCHEDULER TRUE if the application is using the event scheduler, - * FALSE otherwise. - */ -/*lint -emacro(506, APP_BUTTON_INIT) */ /* Suppress "Constant value Boolean */ -#define APP_BUTTON_INIT(BUTTONS, BUTTON_COUNT, DETECTION_DELAY, USE_SCHEDULER) \ - do \ - { \ - uint32_t ERR_CODE = app_button_init((BUTTONS), \ - (BUTTON_COUNT), \ - (DETECTION_DELAY), \ - (USE_SCHEDULER) ? app_button_evt_schedule : NULL); \ - APP_ERROR_CHECK(ERR_CODE); \ - } while (0) - -/**@brief Function for initializing the Buttons. - * - * @details This function will initialize the specified pins as buttons, and configure the Button - * Handler module as a GPIOTE user (but it will not enable button detection). - * - * @note Normally initialization should be done using the APP_BUTTON_INIT() macro, as that will take - * care of connecting the Buttons module to the scheduler (if specified). - * - * @note app_button_enable() function must be called in order to enable the button detection. - * - * @param[in] p_buttons Array of buttons to be used (NOTE: Must be static!). - * @param[in] button_count Number of buttons. - * @param[in] detection_delay Delay from a GPIOTE event until a button is reported as pushed. - * @param[in] evt_schedule_func Function for passing button events to the scheduler. Point to - * app_button_evt_schedule() to connect to the scheduler. Set to - * NULL to make the Buttons module call the event handler directly - * from the delayed button push detection timeout handler. - * - * @return NRF_SUCCESS on success, otherwise an error code. - */ -uint32_t app_button_init(app_button_cfg_t * p_buttons, - uint8_t button_count, - uint32_t detection_delay, - app_button_evt_schedule_func_t evt_schedule_func); - -/**@brief Function for enabling button detection. - * - * @retval NRF_ERROR_INVALID_PARAM GPIOTE has to many users. - * @retval NRF_ERROR_INVALID_STATE Button or GPIOTE not initialized. - * @retval NRF_SUCCESS Button detection successfully enabled. - */ -uint32_t app_button_enable(void); - -/**@brief Function for disabling button detection. - * - * @retval NRF_ERROR_INVALID_PARAM GPIOTE has to many users. - * @retval NRF_ERROR_INVALID_STATE Button or GPIOTE not initialized. - * @retval NRF_SUCCESS Button detection successfully enabled. - */ -uint32_t app_button_disable(void); - -/**@brief Function for checking if a button is currently being pushed. - * - * @param[in] pin_no Button pin to be checked. - * @param[out] p_is_pushed Button state. - * - * @retval NRF_SUCCESS State successfully read. - * @retval NRF_ERROR_INVALID_PARAM Invalid pin_no. - */ -uint32_t app_button_is_pushed(uint8_t pin_no, bool * p_is_pushed); - - -// Type and functions for connecting the Buttons module to the scheduler: - -/**@cond NO_DOXYGEN */ -typedef struct -{ - app_button_handler_t button_handler; - uint8_t pin_no; - uint8_t button_action; -} app_button_event_t; - -static __INLINE void app_button_evt_get(void * p_event_data, uint16_t event_size) -{ - app_button_event_t * p_buttons_event = (app_button_event_t *)p_event_data; - - APP_ERROR_CHECK_BOOL(event_size == sizeof(app_button_event_t)); - p_buttons_event->button_handler(p_buttons_event->pin_no, p_buttons_event->button_action); -} - -static __INLINE uint32_t app_button_evt_schedule(app_button_handler_t button_handler, - uint8_t pin_no, - uint8_t button_action) -{ - app_button_event_t buttons_event; - - buttons_event.button_handler = button_handler; - buttons_event.pin_no = pin_no; - buttons_event.button_action = button_action; - - return app_sched_event_put(&buttons_event, sizeof(buttons_event), app_button_evt_get); -} -/**@endcond */ - -#endif // APP_BUTTON_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_fifo.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_fifo.h deleted file mode 100755 index 4825379c61..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_fifo.h +++ /dev/null @@ -1,83 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup app_fifo FIFO implementation - * @{ - * @ingroup app_common - * - * @brief FIFO implementation. - */ - -#ifndef APP_FIFO_H__ -#define APP_FIFO_H__ - -#include -#include -#include "nrf_error.h" - -/**@brief A FIFO instance structure. Keeps track of which bytes to read and write next. - * Also it keeps the information about which memory is allocated for the buffer - * and its size. This needs to be initialized by app_fifo_init() before use. - */ -typedef struct -{ - uint8_t * p_buf; /**< Pointer to FIFO buffer memory. */ - uint16_t buf_size_mask; /**< Read/write index mask. Also used for size checking. */ - volatile uint32_t read_pos; /**< Next read position in the FIFO buffer. */ - volatile uint32_t write_pos; /**< Next write position in the FIFO buffer. */ -} app_fifo_t; - -/**@brief Function for initializing the FIFO. - * - * @param[out] p_fifo FIFO object. - * @param[in] p_buf FIFO buffer for storing data. The buffer size has to be a power of two. - * @param[in] buf_size Size of the FIFO buffer provided, has to be a power of 2. - * - * @retval NRF_SUCCESS If initialization was successful. - * @retval NRF_ERROR_NULL If a NULL pointer is provided as buffer. - * @retval NRF_ERROR_INVALID_LENGTH If size of buffer provided is not a power of two. - */ -uint32_t app_fifo_init(app_fifo_t * p_fifo, uint8_t * p_buf, uint16_t buf_size); - -/**@brief Function for adding an element to the FIFO. - * - * @param[in] p_fifo Pointer to the FIFO. - * @param[in] byte Data byte to add to the FIFO. - * - * @retval NRF_SUCCESS If an element has been successfully added to the FIFO. - * @retval NRF_ERROR_NO_MEM If the FIFO is full. - */ -uint32_t app_fifo_put(app_fifo_t * p_fifo, uint8_t byte); - -/**@brief Function for getting the next element from the FIFO. - * - * @param[in] p_fifo Pointer to the FIFO. - * @param[out] p_byte Byte fetched from the FIFO. - * - * @retval NRF_SUCCESS If an element was returned. - * @retval NRF_ERROR_NOT_FOUND If there is no more elements in the queue. - */ -uint32_t app_fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte); - -/**@brief Function for flushing the FIFO. - * - * @param[in] p_fifo Pointer to the FIFO. - * - * @retval NRF_SUCCESS If the FIFO flushed successfully. - */ -uint32_t app_fifo_flush(app_fifo_t * p_fifo); - -#endif // APP_FIFO_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_gpiote.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_gpiote.h deleted file mode 100755 index 4a20776f53..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_gpiote.h +++ /dev/null @@ -1,226 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup app_gpiote GPIOTE Handler - * @{ - * @ingroup app_common - * - * @brief GPIOTE handler module. - * - * @details The GPIOTE handler allows several modules ("users") to share the GPIOTE interrupt, - * each user defining a set of pins able to generate events to the user. - * When a GPIOTE interrupt occurs, the GPIOTE interrupt handler will call the event handler - * of each user for which at least one of the pins generated an event. - * - * The GPIOTE users are responsible for configuring all their corresponding pins, except - * the SENSE field, which should be initialized to GPIO_PIN_CNF_SENSE_Disabled. - * The SENSE field will be updated by the GPIOTE module when it is enabled or disabled, - * and also while it is enabled. - * - * The module specifies on which pins events should be generated if the pin(s) goes - * from low->high or high->low or both directions. - * - * @note Even if the application is using the @ref app_scheduler, the GPIOTE event handlers will - * be called directly from the GPIOTE interrupt handler. - * - * @warning If multiple users registers for the same pins the behavior for those pins are undefined. - */ - -#ifndef APP_GPIOTE_H__ -#define APP_GPIOTE_H__ - -#include -#include -// #include "nrf.h" -#include "app_error.h" -#include "app_util.h" - -#ifdef __cpluplus -extern "C" { -#endif - -#define GPIOTE_USER_NODE_SIZE 20 /**< Size of app_gpiote.gpiote_user_t (only for use inside APP_GPIOTE_BUF_SIZE()). */ -#define NO_OF_PINS 32 /**< Number of GPIO pins on the nRF51 chip. */ - -/**@brief Compute number of bytes required to hold the GPIOTE data structures. - * - * @param[in] MAX_USERS Maximum number of GPIOTE users. - * - * @return Required buffer size (in bytes). - */ -#define APP_GPIOTE_BUF_SIZE(MAX_USERS) ((MAX_USERS) * GPIOTE_USER_NODE_SIZE) - -typedef uint8_t app_gpiote_user_id_t; - -/**@brief GPIOTE event handler type. */ -typedef void (*app_gpiote_event_handler_t)(uint32_t event_pins_low_to_high, - uint32_t event_pins_high_to_low); - -/**@brief GPIOTE input event handler type. */ -typedef void (*app_gpiote_input_event_handler_t)(void); - -/**@brief Macro for initializing the GPIOTE module. - * - * @details It will handle dimensioning and allocation of the memory buffer required by the module, - * making sure that the buffer is correctly aligned. - * - * @param[in] MAX_USERS Maximum number of GPIOTE users. - * - * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it - * several times as long as it is from the same location, e.g. to do a reinitialization). - */ -/*lint -emacro(506, APP_GPIOTE_INIT) */ /* Suppress "Constant value Boolean */ -#define APP_GPIOTE_INIT(MAX_USERS) \ - do \ - { \ - static uint32_t app_gpiote_buf[CEIL_DIV(APP_GPIOTE_BUF_SIZE(MAX_USERS), sizeof(uint32_t))];\ - uint32_t ERR_CODE = app_gpiote_init((MAX_USERS), app_gpiote_buf); \ - APP_ERROR_CHECK(ERR_CODE); \ - } while (0) - -/**@brief Function for initializing the GPIOTE module. - * - * @note Normally initialization should be done using the APP_GPIOTE_INIT() macro, as that will - * allocate the buffer needed by the GPIOTE module (including aligning the buffer correctly). - * - * @param[in] max_users Maximum number of GPIOTE users. - * @param[in] p_buffer Pointer to memory buffer for internal use in the app_gpiote - * module. The size of the buffer can be computed using the - * APP_GPIOTE_BUF_SIZE() macro. The buffer must be aligned to - * a 4 byte boundary. - * - * @retval NRF_SUCCESS Successful initialization. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte - * boundary). - */ -uint32_t app_gpiote_init(uint8_t max_users, void * p_buffer); - -/**@brief Function for registering a GPIOTE user. - * - * @param[out] p_user_id Id for the new GPIOTE user. - * @param[in] pins_low_to_high_mask Mask defining which pins will generate events to this user - * when state is changed from low->high. - * @param[in] pins_high_to_low_mask Mask defining which pins will generate events to this user - * when state is changed from high->low. - * @param[in] event_handler Pointer to function to be executed when an event occurs. - * - * @retval NRF_SUCCESS Successful initialization. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte boundary). - * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE - * module. - * @retval NRF_ERROR_NO_MEM Returned if the application tries to register more users - * than defined when the GPIOTE module was initialized in - * @ref app_gpiote_init. - */ -uint32_t app_gpiote_user_register(app_gpiote_user_id_t * p_user_id, - uint32_t pins_low_to_high_mask, - uint32_t pins_high_to_low_mask, - app_gpiote_event_handler_t event_handler); - -/**@brief Function for informing the GPIOTE module that the specified user wants to use the GPIOTE module. - * - * @param[in] user_id Id of user to enable. - * - * @retval NRF_SUCCESS On success. - * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user. - * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE - * module. - */ -uint32_t app_gpiote_user_enable(app_gpiote_user_id_t user_id); - -/**@brief Function for informing the GPIOTE module that the specified user is done using the GPIOTE module. - * - * @param[in] user_id Id of user to enable. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user. - * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE - * module. - */ -uint32_t app_gpiote_user_disable(app_gpiote_user_id_t user_id); - -/**@brief Function for getting the state of the pins which are registered for the specified user. - * - * @param[in] user_id Id of user to check. - * @param[out] p_pins Bit mask corresponding to the pins configured to generate events to - * the specified user. All bits corresponding to pins in the state - * 'high' will have value '1', all others will have value '0'. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user. - * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE - * module. - */ -uint32_t app_gpiote_pins_state_get(app_gpiote_user_id_t user_id, uint32_t * p_pins); - -/**@brief Function for registering event handlers for GPIOTE IN events. - * - * @param[in] channel GPIOTE channel [0..3]. - * @param[in] pin Pins associated with GPIOTE channel. Changes on following pins will generate events. - * @param[in] polarity Specify operation on input that shall trigger IN event. - * @param[in] event_handler Event handler invoked on the IN event in the GPIOTE interrupt. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_INVALID_PARAM Invalid channel or pin number. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events. - */ -uint32_t app_gpiote_input_event_handler_register(const uint8_t channel, - const uint32_t pin, - const uint32_t polarity, - app_gpiote_input_event_handler_t event_handler); - -/**@brief Function for unregistering event handlers for GPIOTE IN events. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events. - */ -uint32_t app_gpiote_input_event_handler_unregister(const uint8_t channel); - -/**@brief Function for registering event handler invoked at the end of a GPIOTE interrupt. - * - * @param[in] event_handler Event handler invoked at the end of the GPIOTE interrupt. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events. - */ -uint32_t app_gpiote_end_irq_event_handler_register(app_gpiote_input_event_handler_t event_handler); - -/**@brief Function for unregistering event handler invoked at the end of a GPIOTE interrupt. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events. - */ -uint32_t app_gpiote_end_irq_event_handler_unregister(void); - -/**@brief Function for enabling interrupts in the GPIOTE driver. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support. - */ -uint32_t app_gpiote_enable_interrupts(void); - -/**@brief Function for disabling interrupts in the GPIOTE driver. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support. - */ -uint32_t app_gpiote_disable_interrupts(void); - -#ifdef __cpluplus -} -#endif - -#endif // APP_GPIOTE_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_timer.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_timer.h deleted file mode 100755 index b2a3c75589..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_timer.h +++ /dev/null @@ -1,313 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup app_timer Application Timer - * @{ - * @ingroup app_common - * - * @brief Application timer functionality. - * - * @details It enables the application to create multiple timer instances based on the RTC1 - * peripheral. Checking for timeouts and invokation of user timeout handlers is performed - * in the RTC1 interrupt handler. List handling is done using a software interrupt (SWI0). - * Both interrupt handlers are running in APP_LOW priority level. - * - * @note When calling app_timer_start() or app_timer_stop(), the timer operation is just queued, - * and the software interrupt is triggered. The actual timer start/stop operation is - * executed by the SWI0 interrupt handler. Since the SWI0 interrupt is running in APP_LOW, - * if the application code calling the timer function is running in APP_LOW or APP_HIGH, - * the timer operation will not be performed until the application handler has returned. - * This will be the case e.g. when stopping a timer from a timeout handler when not using - * the scheduler. - * - * @details Use the USE_SCHEDULER parameter of the APP_TIMER_INIT() macro to select if the - * @ref app_scheduler is to be used or not. - * - * @note Even if the scheduler is not used, app_timer.h will include app_scheduler.h, so when - * compiling, app_scheduler.h must be available in one of the compiler include paths. - */ - -#ifndef APP_TIMER_H__ -#define APP_TIMER_H__ - -#include -#include -#include -#include "app_error.h" -#include "app_util.h" -#include "app_scheduler.h" -#include "compiler_abstraction.h" - -#ifdef __cplusplus -extern "C" { -#endif // #ifdef __cplusplus - -#define APP_TIMER_SCHED_EVT_SIZE sizeof(app_timer_event_t) /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). */ -#define APP_TIMER_CLOCK_FREQ 32768 /**< Clock frequency of the RTC timer used to implement the app timer module. */ -#define APP_TIMER_MIN_TIMEOUT_TICKS 5 /**< Minimum value of the timeout_ticks parameter of app_timer_start(). */ - -#define APP_TIMER_NODE_SIZE 40 /**< Size of app_timer.timer_node_t (only for use inside APP_TIMER_BUF_SIZE()). */ -#define APP_TIMER_USER_OP_SIZE 24 /**< Size of app_timer.timer_user_op_t (only for use inside APP_TIMER_BUF_SIZE()). */ -#define APP_TIMER_USER_SIZE 8 /**< Size of app_timer.timer_user_t (only for use inside APP_TIMER_BUF_SIZE()). */ -#define APP_TIMER_INT_LEVELS 3 /**< Number of interrupt levels from where timer operations may be initiated (only for use inside APP_TIMER_BUF_SIZE()). */ - -#define MAX_RTC_COUNTER_VAL 0x00FFFFFF /**< Maximum value of the RTC counter. */ - -/**@brief Compute number of bytes required to hold the application timer data structures. - * - * @param[in] MAX_TIMERS Maximum number of timers that can be created at any given time. - * @param[in] OP_QUEUE_SIZE Size of queues holding timer operations that are pending execution. - * NOTE: Due to the queue implementation, this size must be one more - * than the size that is actually needed. - * - * @return Required application timer buffer size (in bytes). - */ -#define APP_TIMER_BUF_SIZE(MAX_TIMERS, OP_QUEUE_SIZE) \ - ( \ - ((MAX_TIMERS) * APP_TIMER_NODE_SIZE) \ - + \ - ( \ - APP_TIMER_INT_LEVELS \ - * \ - (APP_TIMER_USER_SIZE + ((OP_QUEUE_SIZE) + 1) * APP_TIMER_USER_OP_SIZE) \ - ) \ - ) - -/**@brief Convert milliseconds to timer ticks. - * - * @note This macro uses 64 bit integer arithmetic, but as long as the macro parameters are - * constants (i.e. defines), the computation will be done by the preprocessor. - * - * @param[in] MS Milliseconds. - * @param[in] PRESCALER Value of the RTC1 PRESCALER register (must be the same value that was - * passed to APP_TIMER_INIT()). - * - * @note When using this macro, it is the responsibility of the developer to ensure that the - * values provided as input result in an output value that is supported by the - * @ref app_timer_start function. For example, when the ticks for 1 ms is needed, the - * maximum possible value of PRESCALER must be 6, when @ref APP_TIMER_CLOCK_FREQ is 32768. - * This will result in a ticks value as 5. Any higher value for PRESCALER will result in a - * ticks value that is not supported by this module. - * - * @return Number of timer ticks. - */ -#define APP_TIMER_TICKS(MS, PRESCALER)\ - ((uint32_t)ROUNDED_DIV((MS) * (uint64_t)APP_TIMER_CLOCK_FREQ, ((PRESCALER) + 1) * 1000)) - -/**@brief Timer id type. */ -typedef uint32_t app_timer_id_t; - -#define TIMER_NULL ((app_timer_id_t)(0 - 1)) /**< Invalid timer id. */ - -/**@brief Application timeout handler type. */ -typedef void (*app_timer_timeout_handler_t)(void * p_context); - -/**@brief Type of function for passing events from the timer module to the scheduler. */ -typedef uint32_t (*app_timer_evt_schedule_func_t) (app_timer_timeout_handler_t timeout_handler, - void * p_context); - -/**@brief Timer modes. */ -typedef enum -{ - APP_TIMER_MODE_SINGLE_SHOT, /**< The timer will expire only once. */ - APP_TIMER_MODE_REPEATED /**< The timer will restart each time it expires. */ -} app_timer_mode_t; - -/**@brief Macro for initializing the application timer module. - * - * @details It will handle dimensioning and allocation of the memory buffer required by the timer, - * making sure that the buffer is correctly aligned. It will also connect the timer module - * to the scheduler (if specified). - * - * @note This module assumes that the LFCLK is already running. If it isn't, the module will - * be non-functional, since the RTC will not run. If you don't use a softdevice, you'll - * have to start the LFCLK manually. See the rtc_example's \ref lfclk_config() function - * for an example of how to do this. If you use a softdevice, the LFCLK is started on - * softdevice init. - * - * - * @param[in] PRESCALER Value of the RTC1 PRESCALER register. This will decide the - * timer tick rate. Set to 0 for no prescaling. - * @param[in] MAX_TIMERS Maximum number of timers that can be created at any given time. - * @param[in] OP_QUEUES_SIZE Size of queues holding timer operations that are pending execution. - * @param[in] USE_SCHEDULER TRUE if the application is using the event scheduler, - * FALSE otherwise. - * - * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it - * several times as long as it is from the same location, e.g. to do a reinitialization). - */ -/*lint -emacro(506, APP_TIMER_INIT) */ /* Suppress "Constant value Boolean */ -#define APP_TIMER_INIT(PRESCALER, MAX_TIMERS, OP_QUEUES_SIZE, USE_SCHEDULER) \ - do \ - { \ - static uint32_t APP_TIMER_BUF[CEIL_DIV(APP_TIMER_BUF_SIZE((MAX_TIMERS), \ - (OP_QUEUES_SIZE) + 1), \ - sizeof(uint32_t))]; \ - uint32_t ERR_CODE = app_timer_init((PRESCALER), \ - (MAX_TIMERS), \ - (OP_QUEUES_SIZE) + 1, \ - APP_TIMER_BUF, \ - (USE_SCHEDULER) ? app_timer_evt_schedule : NULL); \ - APP_ERROR_CHECK(ERR_CODE); \ - } while (0) - -/**@brief Function for initializing the timer module. - * - * @note Normally initialization should be done using the APP_TIMER_INIT() macro, as that will both - * allocate the buffers needed by the timer module (including aligning the buffers correctly, - * and also take care of connecting the timer module to the scheduler (if specified). - * - * @param[in] prescaler Value of the RTC1 PRESCALER register. Set to 0 for no prescaling. - * @param[in] max_timers Maximum number of timers that can be created at any given time. - * @param[in] op_queues_size Size of queues holding timer operations that are pending - * execution. NOTE: Due to the queue implementation, this size must - * be one more than the size that is actually needed. - * @param[in] p_buffer Pointer to memory buffer for internal use in the app_timer - * module. The size of the buffer can be computed using the - * APP_TIMER_BUF_SIZE() macro. The buffer must be aligned to a - * 4 byte boundary. - * @param[in] evt_schedule_func Function for passing timeout events to the scheduler. Point to - * app_timer_evt_schedule() to connect to the scheduler. Set to NULL - * to make the timer module call the timeout handler directly from - * the timer interrupt handler. - * - * @retval NRF_SUCCESS Successful initialization. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte - * boundary or NULL). - */ -uint32_t app_timer_init(uint32_t prescaler, - uint8_t max_timers, - uint8_t op_queues_size, - void * p_buffer, - app_timer_evt_schedule_func_t evt_schedule_func); - -/**@brief Function for creating a timer instance. - * - * @param[out] p_timer_id Id of the newly created timer. - * @param[in] mode Timer mode. - * @param[in] timeout_handler Function to be executed when the timer expires. - * - * @retval NRF_SUCCESS Timer was successfully created. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter. - * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized. - * @retval NRF_ERROR_NO_MEM Maximum number of timers has already been reached. - * - * @note This function does the timer allocation in the caller's context. It is also not protected - * by a critical region. Therefore care must be taken not to call it from several interrupt - * levels simultaneously. - */ -uint32_t app_timer_create(app_timer_id_t * p_timer_id, - app_timer_mode_t mode, - app_timer_timeout_handler_t timeout_handler); - -/**@brief Function for starting a timer. - * - * @param[in] timer_id Id of timer to start. - * @param[in] timeout_ticks Number of ticks (of RTC1, including prescaling) to timeout event - * (minimum 5 ticks). - * @param[in] p_context General purpose pointer. Will be passed to the timeout handler when - * the timer expires. - * - * @retval NRF_SUCCESS Timer was successfully started. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter. - * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized, or timer - * has not been created. - * @retval NRF_ERROR_NO_MEM Timer operations queue was full. - * - * @note The minimum timeout_ticks value is 5. - * @note For multiple active timers, timeouts occurring in close proximity to each other (in the - * range of 1 to 3 ticks) will have a positive jitter of maximum 3 ticks. - * @note When calling this method on a timer which is already running, the second start operation - * will be ignored. - */ -uint32_t app_timer_start(app_timer_id_t timer_id, uint32_t timeout_ticks, void * p_context); - -/**@brief Function for stopping the specified timer. - * - * @param[in] timer_id Id of timer to stop. - * - * @retval NRF_SUCCESS Timer was successfully stopped. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter. - * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized, or timer - * has not been created. - * @retval NRF_ERROR_NO_MEM Timer operations queue was full. - */ -uint32_t app_timer_stop(app_timer_id_t timer_id); - -/**@brief Function for stopping all running timers. - * - * @retval NRF_SUCCESS All timers were successfully stopped. - * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized. - * @retval NRF_ERROR_NO_MEM Timer operations queue was full. - */ -uint32_t app_timer_stop_all(void); - -/**@brief Function for returning the current value of the RTC1 counter. The - * value includes overflow bits to extend the range to 64-bits. - * - * @param[out] p_ticks Current value of the RTC1 counter. - * - * @retval NRF_SUCCESS Counter was successfully read. - */ -uint32_t app_timer_cnt_get(uint64_t * p_ticks); - -/**@brief Function for computing the difference between two RTC1 counter values. - * - * @param[in] ticks_to Value returned by app_timer_cnt_get(). - * @param[in] ticks_from Value returned by app_timer_cnt_get(). - * @param[out] p_ticks_diff Number of ticks from ticks_from to ticks_to. - * - * @retval NRF_SUCCESS Counter difference was successfully computed. - */ -uint32_t app_timer_cnt_diff_compute(uint32_t ticks_to, - uint32_t ticks_from, - uint32_t * p_ticks_diff); - - -// Type and functions for connecting the timer to the scheduler: - -/**@cond NO_DOXYGEN */ -typedef struct -{ - app_timer_timeout_handler_t timeout_handler; - void * p_context; -} app_timer_event_t; - -static __INLINE void app_timer_evt_get(void * p_event_data, uint16_t event_size) -{ - app_timer_event_t * p_timer_event = (app_timer_event_t *)p_event_data; - - APP_ERROR_CHECK_BOOL(event_size == sizeof(app_timer_event_t)); - p_timer_event->timeout_handler(p_timer_event->p_context); -} - -static __INLINE uint32_t app_timer_evt_schedule(app_timer_timeout_handler_t timeout_handler, - void * p_context) -{ - app_timer_event_t timer_event; - - timer_event.timeout_handler = timeout_handler; - timer_event.p_context = p_context; - - return app_sched_event_put(&timer_event, sizeof(timer_event), app_timer_evt_get); -} -/**@endcond */ - -#ifdef __cplusplus -} -#endif // #ifdef __cplusplus - -#endif // APP_TIMER_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_trace.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_trace.h deleted file mode 100755 index 6e755b4b2c..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_trace.h +++ /dev/null @@ -1,55 +0,0 @@ -#ifndef __DEBUG_H_ -#define __DEBUG_H_ - -#include -#include - -/** - * @defgroup app_trace Debug Logger - * @ingroup app_common - * @{ - * @brief Enables debug logs/ trace over UART. - * @details Enables debug logs/ trace over UART. Tracing is enabled only if - * ENABLE_DEBUG_LOG_SUPPORT is defined in the project. - */ -#ifdef ENABLE_DEBUG_LOG_SUPPORT -/** - * @brief Module Initialization. - * - * @details Initializes the module to use UART as trace output. - * - * @warning This function will configure UART using default board configuration (described in @ref nrf51_setups). - * Do not call this function if UART is configured from a higher level in the application. - */ -void app_trace_init(void); - -/** - * @brief Log debug messages. - * - * @details This API logs messages over UART. The module must be initialized before using this API. - * - * @note Though this is currently a macro, it should be used used and treated as function. - */ -#define app_trace_log printf - -/** - * @brief Dump auxiliary byte buffer to the debug trace. - * - * @details This API logs messages over UART. The module must be initialized before using this API. - * - * @param[in] p_buffer Buffer to be dumped on the debug trace. - * @param[in] len Size of the buffer. - */ -void app_trace_dump(uint8_t * p_buffer, uint32_t len); - -#else // ENABLE_DEBUG_LOG_SUPPORT - -#define app_trace_init(...) -#define app_trace_log(...) -#define app_trace_dump(...) - -#endif // ENABLE_DEBUG_LOG_SUPPORT - -/** @} */ - -#endif //__DEBUG_H_ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_uart.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_uart.h deleted file mode 100755 index 39ec3c1ce8..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_uart.h +++ /dev/null @@ -1,286 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup app_uart UART module - * @{ - * @ingroup app_common - * - * @brief UART module interface. - */ - -#ifndef APP_UART_H__ -#define APP_UART_H__ - -#include -#include -#include "app_util_platform.h" - -#define UART_PIN_DISCONNECTED 0xFFFFFFFF /**< Value indicating that no pin is connected to this UART register. */ - -/**@brief UART Flow Control modes for the peripheral. - */ -typedef enum -{ - APP_UART_FLOW_CONTROL_DISABLED, /**< UART Hw Flow Control is disabled. */ - APP_UART_FLOW_CONTROL_ENABLED, /**< Standard UART Hw Flow Control is enabled. */ - APP_UART_FLOW_CONTROL_LOW_POWER /**< Specialized UART Hw Flow Control is used. The Low Power setting allows the nRF51 to Power Off the UART module when CTS is in-active, and re-enabling the UART when the CTS signal becomes active. This allows the nRF51 to safe power by only using the UART module when it is needed by the remote site. */ -} app_uart_flow_control_t; - -/**@brief UART communication structure holding configuration settings for the peripheral. - */ -typedef struct -{ - uint8_t rx_pin_no; /**< RX pin number. */ - uint8_t tx_pin_no; /**< TX pin number. */ - uint8_t rts_pin_no; /**< RTS pin number, only used if flow control is enabled. */ - uint8_t cts_pin_no; /**< CTS pin number, only used if flow control is enabled. */ - app_uart_flow_control_t flow_control; /**< Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */ - bool use_parity; /**< Even parity if TRUE, no parity if FALSE. */ - uint32_t baud_rate; /**< Baud rate configuration. */ -} app_uart_comm_params_t; - -/**@brief UART buffer for transmitting/receiving data. - */ -typedef struct -{ - uint8_t * rx_buf; /**< Pointer to the RX buffer. */ - uint32_t rx_buf_size; /**< Size of the RX buffer. */ - uint8_t * tx_buf; /**< Pointer to the TX buffer. */ - uint32_t tx_buf_size; /**< Size of the TX buffer. */ -} app_uart_buffers_t; - -/**@brief Enumeration describing current state of the UART. - * - * @details The connection state can be fetched by the application using the function call - * @ref app_uart_get_connection_state. - * When hardware flow control is used - * - APP_UART_CONNECTED: Communication is ongoing. - * - APP_UART_DISCONNECTED: No communication is ongoing. - * - * When no hardware flow control is used - * - APP_UART_CONNECTED: Always returned as bytes can always be received/transmitted. - */ -typedef enum -{ - APP_UART_DISCONNECTED, /**< State indicating that the UART is disconnected and cannot receive or transmit bytes. */ - APP_UART_CONNECTED /**< State indicating that the UART is connected and ready to receive or transmit bytes. If flow control is disabled, the state will always be connected. */ -} app_uart_connection_state_t; - -/**@brief Enumeration which defines events used by the UART module upon data reception or error. - * - * @details The event type is used to indicate the type of additional information in the event - * @ref app_uart_evt_t. - */ -typedef enum -{ - APP_UART_DATA_READY, /**< An event indicating that UART data has been received. The data is available in the FIFO and can be fetched using @ref app_uart_get. */ - APP_UART_FIFO_ERROR, /**< An error in the FIFO module used by the app_uart module has occured. The FIFO error code is stored in app_uart_evt_t.data.error_code field. */ - APP_UART_COMMUNICATION_ERROR, /**< An communication error has occured during reception. The error is stored in app_uart_evt_t.data.error_communication field. */ - APP_UART_TX_EMPTY, /**< An event indicating that UART has completed transmission of all available data in the TX FIFO. */ - APP_UART_DATA, /**< An event indicating that UART data has been received, and data is present in data field. This event is only used when no FIFO is configured. */ -} app_uart_evt_type_t; - -/**@brief Struct containing events from the UART module. - * - * @details The app_uart_evt_t is used to notify the application of asynchronous events when data - * are received on the UART peripheral or in case an error occured during data reception. - */ -typedef struct -{ - app_uart_evt_type_t evt_type; /**< Type of event. */ - union - { - uint32_t error_communication; /**< Field used if evt_type is: APP_UART_COMMUNICATION_ERROR. This field contains the value in the ERRORSRC register for the UART peripheral. The UART_ERRORSRC_x defines from @ref nrf51_bitfields.h can be used to parse the error code. See also the nRF51 Series Reference Manual for specification. */ - uint32_t error_code; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */ - uint8_t value; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */ - } data; -} app_uart_evt_t; - -/**@brief Function for handling app_uart event callback. - * - * @details Upon an event in the app_uart module this callback function will be called to notify - * the applicatioon about the event. - * - * @param[in] p_app_uart_event Pointer to UART event. - */ - - -typedef void (* app_uart_event_handler_t) (app_uart_evt_t * p_app_uart_event); - -/**@brief Macro for safe initialization of the UART module in a single user instance when using - * a FIFO together with UART. - * - * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t - * @param[in] RX_BUF_SIZE Size of desired RX buffer, must be a power of 2 or ZERO (No FIFO). - * @param[in] TX_BUF_SIZE Size of desired TX buffer, must be a power of 2 or ZERO (No FIFO). - * @param[in] EVENT_HANDLER Event handler function to be called when an event occurs in the - * UART module. - * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler. - * @param[out] ERR_CODE The return value of the UART initialization function will be - * written to this parameter. - * - * @note Since this macro allocates a buffer and registers the module as a GPIOTE user when flow - * control is enabled, it must only be called once. - */ -#define APP_UART_FIFO_INIT(P_COMM_PARAMS, RX_BUF_SIZE, TX_BUF_SIZE, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \ - do \ - { \ - uint16_t APP_UART_UID = 0; \ - app_uart_buffers_t buffers; \ - static uint8_t rx_buf[RX_BUF_SIZE]; \ - static uint8_t tx_buf[TX_BUF_SIZE]; \ - \ - buffers.rx_buf = rx_buf; \ - buffers.rx_buf_size = sizeof (rx_buf); \ - buffers.tx_buf = tx_buf; \ - buffers.tx_buf_size = sizeof (tx_buf); \ - ERR_CODE = app_uart_init(P_COMM_PARAMS, &buffers, EVT_HANDLER, IRQ_PRIO, &APP_UART_UID); \ - } while (0) - -/**@brief Macro for safe initialization of the UART module in a single user instance. - * - * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t - * @param[in] EVENT_HANDLER Event handler function to be called when an event occurs in the - * UART module. - * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler. - * @param[out] ERR_CODE The return value of the UART initialization function will be - * written to this parameter. - * - * @note Since this macro allocates registers the module as a GPIOTE user when flow control is - * enabled, it must only be called once. - */ -#define APP_UART_INIT(P_COMM_PARAMS, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \ - do \ - { \ - uint16_t APP_UART_UID = 0; \ - ERR_CODE = app_uart_init(P_COMM_PARAMS, NULL, EVT_HANDLER, IRQ_PRIO, &APP_UART_UID); \ - } while (0) - -/**@brief Function for initializing the UART module. Use this initialization when several instances of the UART - * module are needed. - * - * @details This initialization will return a UART user id for the caller. The UART user id must be - * used upon re-initialization of the UART or closing of the module for the user. - * If single instance usage is needed, the APP_UART_INIT() macro should be used instead. - * - * @note Normally single instance initialization should be done using the APP_UART_INIT() or - * APP_UART_INIT_FIFO() macro depending on whether the FIFO should be used by the UART, as - * that will allocate the buffers needed by the UART module (including aligning the buffer - * correctly). - - * @param[in] p_comm_params Pin and communication parameters. - * @param[in] p_buffers RX and TX buffers, NULL is FIFO is not used. - * @param[in] error_handler Function to be called in case of an error. - * @param[in] app_irq_priority Interrupt priority level. - * @param[in,out] p_uart_uid User id for the UART module. The p_uart_uid must be used if - * re-initialization and/or closing of the UART module is needed. - * If the value pointed to by p_uart_uid is zero, this is - * considdered a first time initialization. Otherwise this is - * considered a re-initialization for the user with id *p_uart_uid. - * - * @retval NRF_SUCCESS If successful initialization. - * @retval NRF_ERROR_INVALID_LENGTH If a provided buffer is not a power of two. - * @retval NRF_ERROR_NULL If one of the provided buffers is a NULL pointer. - * - * Those errors are propagated by the UART module to the caller upon registration when Hardware Flow - * Control is enabled. When Hardware Flow Control is not used, those errors cannot occur. - * @retval NRF_ERROR_INVALID_STATE The GPIOTE module is not in a valid state when registering - * the UART module as a user. - * @retval NRF_ERROR_INVALID_PARAM The UART module provides an invalid callback function when - * registering the UART module as a user. - * Or the value pointed to by *p_uart_uid is not a valid - * GPIOTE number. - * @retval NRF_ERROR_NO_MEM GPIOTE module has reached the maximum number of users. - */ -uint32_t app_uart_init(const app_uart_comm_params_t * p_comm_params, - app_uart_buffers_t * p_buffers, - app_uart_event_handler_t error_handler, - app_irq_priority_t irq_priority, - uint16_t * p_uart_uid); - -/**@brief Function for getting a byte from the UART. - * - * @details This function will get the next byte from the RX buffer. If the RX buffer is empty - * an error code will be returned and the app_uart module will generate an event upon - * reception of the first byte which is added to the RX buffer. - * - * @param[out] p_byte Pointer to an address where next byte received on the UART will be copied. - * - * @retval NRF_SUCCESS If a byte has been received and pushed to the pointer provided. - * @retval NRF_ERROR_NOT_FOUND If no byte is available in the RX buffer of the app_uart module. - */ -uint32_t app_uart_get(uint8_t * p_byte); - -/**@brief Function for putting a byte on the UART. - * - * @details This call is non-blocking. - * - * @param[in] byte Byte to be transmitted on the UART. - * - * @retval NRF_SUCCESS If the byte was succesfully put on the TX buffer for transmission. - * @retval NRF_ERROR_NO_MEM If no more space is available in the TX buffer. - * NRF_ERROR_NO_MEM may occur if flow control is enabled and CTS signal - * is high for a long period and the buffer fills up. - */ -uint32_t app_uart_put(uint8_t byte); - -/**@brief Function for getting the current state of the UART. - * - * @details If flow control is disabled, the state is assumed to always be APP_UART_CONNECTED. - * - * When using flow control the state will be controlled by the CTS. If CTS is set active - * by the remote side, or the app_uart module is in the process of transmitting a byte, - * app_uart is in APP_UART_CONNECTED state. If CTS is set inactive by remote side app_uart - * will not get into APP_UART_DISCONNECTED state until the last byte in the TXD register - * is fully transmitted. - * - * Internal states in the state machine are mapped to the general connected/disconnected - * states in the following ways: - * - * - UART_ON = CONNECTED - * - UART_READY = CONNECTED - * - UART_WAIT = CONNECTED - * - UART_OFF = DISCONNECTED. - * - * @param[out] p_connection_state Current connection state of the UART. - * - * @retval NRF_SUCCESS The connection state was succesfully retrieved. - */ -uint32_t app_uart_get_connection_state(app_uart_connection_state_t * p_connection_state); - -/**@brief Function for flushing the RX and TX buffers (Only valid if FIFO is used). - * This function does nothing if FIFO is not used. - * - * @retval NRF_SUCCESS Flushing completed (Current implementation will always succeed). - */ -uint32_t app_uart_flush(void); - -/**@brief Function for closing the UART module. - * - * @details This function will close any on-going UART transmissions and disable itself in the - * GPTIO module. - * - * @param[in] app_uart_uid User id for the UART module. The app_uart_uid must be identical to the - * UART id returned on initialization and which is currently in use. - - * @retval NRF_SUCCESS If successfully closed. - * @retval NRF_ERROR_INVALID_PARAM If an invalid user id is provided or the user id differs from - * the current active user. - */ -uint32_t app_uart_close(uint16_t app_uart_id); - - -#endif //APP_UART_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hal_transport.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hal_transport.h deleted file mode 100755 index 8dcc025aab..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hal_transport.h +++ /dev/null @@ -1,227 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup hci_transport HCI Transport - * @{ - * @ingroup app_common - * - * @brief HCI transport module implementation. - * - * This module implements certain specific features from the three-wire UART transport layer, - * defined by the Bluetooth specification version 4.0 [Vol 4] part D. - * - * \par Features supported - * - Transmission and reception of Vendor Specific HCI packet type application packets. - * - Transmission and reception of reliable packets: defined by chapter 6 of the specification. - * - * \par Features not supported - * - Link establishment procedure: defined by chapter 8 of the specification. - * - Low power: defined by chapter 9 of the specification. - * - * \par Implementation specific behaviour - * - As Link establishment procedure is not supported following static link configuration parameters - * are used: - * + TX window size is 1. - * + 16 bit CCITT-CRC must be used. - * + Out of frame software flow control not supported. - * + Parameters specific for resending reliable packets are compile time configurable (clarifed - * later in this document). - * + Acknowledgement packet transmissions are not timeout driven , meaning they are delivered for - * transmission within same context which the corresponding application packet was received. - * - * \par Implementation specific limitations - * Current implementation has the following limitations which will have impact to system wide - * behaviour: - * - Delayed acknowledgement scheduling not implemented: - * There exists a possibility that acknowledgement TX packet and application TX packet will collide - * in the TX pipeline having the end result that acknowledgement packet will be excluded from the TX - * pipeline which will trigger the retransmission algorithm within the peer protocol entity. - * - Delayed retransmission scheduling not implemented: - * There exists a possibility that retransmitted application TX packet and acknowledgement TX packet - * will collide in the TX pipeline having the end result that retransmitted application TX packet - * will be excluded from the TX pipeline. - * - Processing of the acknowledgement number from RX application packets: - * Acknowledgement number is not processed from the RX application packets having the end result - * that unnecessary application packet retransmissions can occur. - * - * The application TX packet processing flow is illustrated by the statemachine below. - * - * @image html hci_transport_tx_sm.png "TX - application packet statemachine" - * - * \par Component specific configuration options - * - * The following compile time configuration options are available, and used to configure the - * application TX packet retransmission interval, in order to suite various application specific - * implementations: - * - MAC_PACKET_SIZE_IN_BITS Maximum size of a single application packet in bits. - * - USED_BAUD_RATE Used uart baudrate. - * - * The following compile time configuration option is available to configure module specific - * behaviour: - * - MAX_RETRY_COUNT Max retransmission retry count for applicaton packets. - */ - -#ifndef HCI_TRANSPORT_H__ -#define HCI_TRANSPORT_H__ - -#include -#include "nrf_error.h" - -#define HCI_TRANSPORT_PKT_HEADER_SIZE (2) /**< Size of transport packet header */ - -/**@brief Generic event callback function events. */ -typedef enum -{ - HCI_TRANSPORT_RX_RDY, /**< An event indicating that RX packet is ready for read. */ - HCI_TRANSPORT_EVT_TYPE_MAX /**< Enumeration upper bound. */ -} hci_transport_evt_type_t; - -/**@brief Struct containing events from the Transport layer. - */ -typedef struct -{ - hci_transport_evt_type_t evt_type; /**< Type of event. */ -} hci_transport_evt_t; - -/**@brief Transport layer generic event callback function type. - * - * @param[in] event Transport layer event. - */ -typedef void (*hci_transport_event_handler_t)(hci_transport_evt_t event); - -/**@brief TX done event callback function result codes. */ -typedef enum -{ - HCI_TRANSPORT_TX_DONE_SUCCESS, /**< Transmission success, peer transport entity has acknowledged the transmission. */ - HCI_TRANSPORT_TX_DONE_FAILURE /**< Transmission failure. */ -} hci_transport_tx_done_result_t; - -/**@brief Transport layer TX done event callback function type. - * - * @param[in] result TX done event result code. - */ -typedef void (*hci_transport_tx_done_handler_t)(hci_transport_tx_done_result_t result); - -/**@brief Function for registering a generic event handler. - * - * @note Multiple registration requests will overwrite any possible existing registration. - * - * @param[in] event_handler The function to be called by the transport layer upon an event. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler); - -/**@brief Function for registering a handler for TX done event. - * - * @note Multiple registration requests will overwrite any possible existing registration. - * - * @param[in] event_handler The function to be called by the transport layer upon TX done - * event. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler); - -/**@brief Function for opening the transport channel and initializing the transport layer. - * - * @warning Must not be called for a channel which has been allready opened. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_INTERNAL Operation failure. Internal error ocurred. - */ -uint32_t hci_transport_open(void); - -/**@brief Function for closing the transport channel. - * - * @note Can be called multiple times and also for not opened channel. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_transport_close(void); - -/**@brief Function for allocating tx packet memory. - * - * @param[out] pp_memory Pointer to the packet data. - * - * @retval NRF_SUCCESS Operation success. Memory was allocated. - * @retval NRF_ERROR_NO_MEM Operation failure. No memory available. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory); - -/**@brief Function for freeing tx packet memory. - * - * @note Memory management works in FIFO principle meaning that free order must match the alloc - * order. - * - * @retval NRF_SUCCESS Operation success. Memory was freed. - */ -uint32_t hci_transport_tx_free(void); - -/**@brief Function for writing a packet. - * - * @note Completion of this method does not guarantee that actual peripheral transmission would - * have completed. - * - * @note In case of 0 byte packet length write request, message will consist of only transport - * module specific headers. - * - * @note The buffer provided to this function must be allocated through @ref hci_transport_tx_alloc - * function. - * - * @retval NRF_SUCCESS Operation success. Packet was added to the transmission queue - * and an event will be send upon transmission completion. - * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not - * added to the transmission queue. User should wait for - * a appropriate event prior issuing this operation again. - * @retval NRF_ERROR_DATA_SIZE Operation failure. Packet size exceeds limit. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - * @retval NRF_ERROR_INVALID_STATE Operation failure. Channel is not open. - * @retval NRF_ERROR_INVALID_ADDR Operation failure. Buffer provided is not allocated through - * hci_transport_tx_alloc function. - */ -uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint16_t length); - -/**@brief Function for extracting received packet. - * - * @note Extracted memory can't be reused by the underlying transport layer untill freed by call to - * hci_transport_rx_pkt_consume(). - * - * @param[out] pp_buffer Pointer to the packet data. - * @param[out] p_length Length of packet data in bytes. - * - * @retval NRF_SUCCESS Operation success. Packet was extracted. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint16_t * p_length); - -/**@brief Function for consuming extracted packet described by p_buffer. - * - * RX memory pointed to by p_buffer is freed and can be reused by the underlying transport layer. - * - * @param[in] p_buffer Pointer to the buffer that has been consumed. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to consume. - * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer. - */ -uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer); - -#endif // HCI_TRANSPORT_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool.h deleted file mode 100755 index bc178d0bac..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool.h +++ /dev/null @@ -1,132 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup memory_pool Memory pool - * @{ - * @ingroup app_common - * - * @brief Memory pool implementation - * - * Memory pool implementation, based on circular buffer data structure, which supports asynchronous - * processing of RX data. The current default implementation supports 1 TX buffer and 4 RX buffers. - * The memory managed by the pool is allocated from static storage instead of heap. The internal - * design of the circular buffer implementing the RX memory layout is illustrated in the picture - * below. - * - * @image html memory_pool.png "Circular buffer design" - * - * The expected call order for the RX APIs is as follows: - * - hci_mem_pool_rx_produce - * - hci_mem_pool_rx_data_size_set - * - hci_mem_pool_rx_extract - * - hci_mem_pool_rx_consume - * - * @warning If the above mentioned expected call order is violated the end result can be undefined. - * - * \par Component specific configuration options - * - * The following compile time configuration options are available to suit various implementations: - * - TX_BUF_SIZE TX buffer size in bytes. - * - RX_BUF_SIZE RX buffer size in bytes. - * - RX_BUF_QUEUE_SIZE RX buffer element size. - */ - -#ifndef HCI_MEM_POOL_H__ -#define HCI_MEM_POOL_H__ - -#include -#include "nrf_error.h" - -/**@brief Function for opening the module. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_mem_pool_open(void); - -/**@brief Function for closing the module. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_mem_pool_close(void); - -/**@brief Function for allocating requested amount of TX memory. - * - * @param[out] pp_buffer Pointer to the allocated memory. - * - * @retval NRF_SUCCESS Operation success. Memory was allocated. - * @retval NRF_ERROR_NO_MEM Operation failure. No memory available for allocation. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer); - -/**@brief Function for freeing previously allocated TX memory. - * - * @note Memory management follows the FIFO principle meaning that free() order must match the - * alloc(...) order, which is the reason for omitting exact memory block identifier as an - * input parameter. - * - * @retval NRF_SUCCESS Operation success. Memory was freed. - */ -uint32_t hci_mem_pool_tx_free(void); - -/**@brief Function for producing a free RX memory block for usage. - * - * @note Upon produce request amount being 0, NRF_SUCCESS is returned. - * - * @param[in] length Amount, in bytes, of free memory to be produced. - * @param[out] pp_buffer Pointer to the allocated memory. - * - * @retval NRF_SUCCESS Operation success. Free RX memory block produced. - * @retval NRF_ERROR_NO_MEM Operation failure. No suitable memory available for allocation. - * @retval NRF_ERROR_DATA_SIZE Operation failure. Request size exceeds limit. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer); - -/**@brief Function for setting the length of the last produced RX memory block. - * - * @warning If call to this API is omitted the end result is that the following call to - * mem_pool_rx_extract will return incorrect data in the p_length output parameter. - * - * @param[in] length Amount, in bytes, of actual memory used. - * - * @retval NRF_SUCCESS Operation success. Length was set. - */ -uint32_t hci_mem_pool_rx_data_size_set(uint32_t length); - -/**@brief Function for extracting a packet, which has been filled with read data, for further - * processing. - * - * @param[out] pp_buffer Pointer to the packet data. - * @param[out] p_length Length of packet data in bytes. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length); - -/**@brief Function for freeing previously extracted packet, which has been filled with read data. - * - * @param[in] p_buffer Pointer to consumed buffer. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to free. - * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer. - */ -uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer); - -#endif // HCI_MEM_POOL_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool_internal.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool_internal.h deleted file mode 100755 index f1fa77fea6..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool_internal.h +++ /dev/null @@ -1,32 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup memory_pool_internal Memory Pool Internal - * @{ - * @ingroup memory_pool - * - * @brief Memory pool internal definitions - */ - -#ifndef MEM_POOL_INTERNAL_H__ -#define MEM_POOL_INTERNAL_H__ - -#define TX_BUF_SIZE 600u /**< TX buffer size in bytes. */ -#define RX_BUF_SIZE TX_BUF_SIZE /**< RX buffer size in bytes. */ - -#define RX_BUF_QUEUE_SIZE 4u /**< RX buffer element size. */ - -#endif // MEM_POOL_INTERNAL_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_slip.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_slip.h deleted file mode 100755 index ad26f3be20..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_slip.h +++ /dev/null @@ -1,129 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup hci_slip SLIP module - * @{ - * @ingroup app_common - * - * @brief SLIP layer for supporting packet framing in HCI transport. - * - * @details This module implements SLIP packet framing as described in the Bluetooth Core - * Specification 4.0, Volume 4, Part D, Chapter 3 SLIP Layer. - * - * SLIP framing ensures that all packets sent on the UART are framed as: - * <0xC0> SLIP packet 1 <0xC0> <0xC0> SLIP packet 2 <0xC0>. - * - * The SLIP layer uses events to notify the upper layer when data transmission is complete - * and when a SLIP packet is received. - */ - -#ifndef HCI_SLIP_H__ -#define HCI_SLIP_H__ - -#include - -/**@brief Event types from the SLIP Layer. */ -typedef enum -{ - HCI_SLIP_RX_RDY, /**< An event indicating that an RX packet is ready to be read. */ - HCI_SLIP_TX_DONE, /**< An event indicating write completion of the TX packet provided in the function call \ref hci_slip_write . */ - HCI_SLIP_RX_OVERFLOW, /**< An event indicating that RX data has been discarded due to lack of free RX memory. */ - HCI_SLIP_ERROR, /**< An event indicating that an unrecoverable error has occurred. */ - HCI_SLIP_EVT_TYPE_MAX /**< Enumeration upper bound. */ -} hci_slip_evt_type_t; - -/**@brief Structure containing an event from the SLIP layer. - */ -typedef struct -{ - hci_slip_evt_type_t evt_type; /**< Type of event. */ - const uint8_t * packet; /**< This field contains a pointer to the packet for which the event relates, i.e. SLIP_TX_DONE: the packet transmitted, SLIP_RX_RDY: the packet received, SLIP_RX_OVERFLOW: The packet which overflow/or NULL if no receive buffer is available. */ - uint32_t packet_length; /**< Packet length, i.e. SLIP_TX_DONE: Bytes transmitted, SLIP_RX_RDY: Bytes received, SLIP_RX_OVERFLOW: index at which the packet overflowed. */ -} hci_slip_evt_t; - -/**@brief Function for the SLIP layer event callback. - */ -typedef void (*hci_slip_event_handler_t)(hci_slip_evt_t event); - -/**@brief Function for registering the event handler provided as parameter and this event handler - * will be used by SLIP layer to send events described in \ref hci_slip_evt_type_t. - * - * @note Multiple registration requests will overwrite any existing registration. - * - * @param[in] event_handler This function is called by the SLIP layer upon an event. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_slip_evt_handler_register(hci_slip_event_handler_t event_handler); - -/**@brief Function for opening the SLIP layer. This function must be called before - * \ref hci_slip_write and before any data can be received. - * - * @note Can be called multiple times. - * - * @retval NRF_SUCCESS Operation success. - * - * The SLIP layer module will propagate errors from underlying sub-modules. - * This implementation is using UART module as a physical transmission layer, and hci_slip_open - * executes \ref app_uart_init . For an extended error list, please refer to \ref app_uart_init . - */ -uint32_t hci_slip_open(void); - -/**@brief Function for closing the SLIP layer. After this function is called no data can be - * transmitted or received in this layer. - * - * @note This function can be called multiple times and also for an unopened channel. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_slip_close(void); - -/**@brief Function for writing a packet with SLIP encoding. Packet transmission is confirmed when - * the HCI_SLIP_TX_DONE event is received by the function caller. - * - * @param[in] p_buffer Pointer to the packet to transmit. - * @param[in] length Packet length, in bytes. - * - * @retval NRF_SUCCESS Operation success. Packet was encoded and added to the - * transmission queue and an event will be sent upon transmission - * completion. - * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not - * added to the transmission queue. Application shall wait for - * the \ref HCI_SLIP_TX_DONE event. After HCI_SLIP_TX_DONE this - * function can be executed for transmission of next packet. - * @retval NRF_ERROR_INVALID_ADDR If a NULL pointer is provided. - * @retval NRF_ERROR_INVALID_STATE Operation failure. Module is not open. - */ -uint32_t hci_slip_write(const uint8_t * p_buffer, uint32_t length); - -/**@brief Function for registering a receive buffer. The receive buffer will be used for storage of - * received and SLIP decoded data. - * No data can be received by the SLIP layer until a receive buffer has been registered. - * - * @note The lifetime of the buffer must be valid during complete reception of data. A static - * buffer is recommended. - * - * @warning Multiple registration requests will overwrite any existing registration. - * - * @param[in] p_buffer Pointer to receive buffer. The received and SLIP decoded packet - * will be placed in this buffer. - * @param[in] length Buffer length, in bytes. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_slip_rx_buffer_register(uint8_t * p_buffer, uint32_t length); - -#endif // HCI_SLIP_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_transport.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_transport.h deleted file mode 100755 index 60d3d24c4f..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_transport.h +++ /dev/null @@ -1,220 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup hci_transport HCI Transport - * @{ - * @ingroup app_common - * - * @brief HCI transport module implementation. - * - * This module implements certain specific features from the three-wire UART transport layer, - * defined by the Bluetooth specification version 4.0 [Vol 4] part D. - * - * \par Features supported - * - Transmission and reception of Vendor Specific HCI packet type application packets. - * - Transmission and reception of reliable packets: defined by chapter 6 of the specification. - * - * \par Features not supported - * - Link establishment procedure: defined by chapter 8 of the specification. - * - Low power: defined by chapter 9 of the specification. - * - * \par Implementation specific behaviour - * - As Link establishment procedure is not supported following static link configuration parameters - * are used: - * + TX window size is 1. - * + 16 bit CCITT-CRC must be used. - * + Out of frame software flow control not supported. - * + Parameters specific for resending reliable packets are compile time configurable (clarifed - * later in this document). - * + Acknowledgement packet transmissions are not timeout driven , meaning they are delivered for - * transmission within same context which the corresponding application packet was received. - * - * \par Implementation specific limitations - * Current implementation has the following limitations which will have impact to system wide - * behaviour: - * - Delayed acknowledgement scheduling not implemented: - * There exists a possibility that acknowledgement TX packet and application TX packet will collide - * in the TX pipeline having the end result that acknowledgement packet will be excluded from the TX - * pipeline which will trigger the retransmission algorithm within the peer protocol entity. - * - Delayed retransmission scheduling not implemented: - * There exists a possibility that retransmitted application TX packet and acknowledgement TX packet - * will collide in the TX pipeline having the end result that retransmitted application TX packet - * will be excluded from the TX pipeline. - * - Processing of the acknowledgement number from RX application packets: - * Acknowledgement number is not processed from the RX application packets having the end result - * that unnecessary application packet retransmissions can occur. - * - * The application TX packet processing flow is illustrated by the statemachine below. - * - * @image html hci_transport_tx_sm.png "TX - application packet statemachine" - * - * \par Component specific configuration options - * - * The following compile time configuration options are available, and used to configure the - * application TX packet retransmission interval, in order to suite various application specific - * implementations: - * - MAC_PACKET_SIZE_IN_BITS Maximum size of a single application packet in bits. - * - USED_BAUD_RATE Used uart baudrate. - * - * The following compile time configuration option is available to configure module specific - * behaviour: - * - MAX_RETRY_COUNT Max retransmission retry count for applicaton packets. - */ - -#ifndef HCI_TRANSPORT_H__ -#define HCI_TRANSPORT_H__ - -#include -#include "nrf_error.h" - -/**@brief Generic event callback function events. */ -typedef enum -{ - HCI_TRANSPORT_RX_RDY, /**< An event indicating that RX packet is ready for read. */ - HCI_TRANSPORT_EVT_TYPE_MAX /**< Enumeration upper bound. */ -} hci_transport_evt_type_t; - -/**@brief Struct containing events from the Transport layer. - */ -typedef struct -{ - hci_transport_evt_type_t evt_type; /**< Type of event. */ -} hci_transport_evt_t; - -/**@brief Transport layer generic event callback function type. - * - * @param[in] event Transport layer event. - */ -typedef void (*hci_transport_event_handler_t)(hci_transport_evt_t event); - -/**@brief TX done event callback function result codes. */ -typedef enum -{ - HCI_TRANSPORT_TX_DONE_SUCCESS, /**< Transmission success, peer transport entity has acknowledged the transmission. */ - HCI_TRANSPORT_TX_DONE_FAILURE /**< Transmission failure. */ -} hci_transport_tx_done_result_t; - -/**@brief Transport layer TX done event callback function type. - * - * @param[in] result TX done event result code. - */ -typedef void (*hci_transport_tx_done_handler_t)(hci_transport_tx_done_result_t result); - -/**@brief Function for registering a generic event handler. - * - * @note Multiple registration requests will overwrite any possible existing registration. - * - * @param[in] event_handler The function to be called by the transport layer upon an event. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler); - -/**@brief Function for registering a handler for TX done event. - * - * @note Multiple registration requests will overwrite any possible existing registration. - * - * @param[in] event_handler The function to be called by the transport layer upon TX done - * event. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler); - -/**@brief Function for opening the transport channel and initializing the transport layer. - * - * @warning Must not be called for a channel which has been allready opened. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_INTERNAL Operation failure. Internal error ocurred. - */ -uint32_t hci_transport_open(void); - -/**@brief Function for closing the transport channel. - * - * @note Can be called multiple times and also for not opened channel. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_transport_close(void); - -/**@brief Function for allocating tx packet memory. - * - * @param[out] pp_memory Pointer to the packet data. - * - * @retval NRF_SUCCESS Operation success. Memory was allocated. - * @retval NRF_ERROR_NO_MEM Operation failure. No memory available. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory); - -/**@brief Function for freeing tx packet memory. - * - * @note Memory management works in FIFO principle meaning that free order must match the alloc - * order. - * - * @retval NRF_SUCCESS Operation success. Memory was freed. - */ -uint32_t hci_transport_tx_free(void); - -/**@brief Function for writing a packet. - * - * @note Completion of this method does not guarantee that actual peripheral transmission would - * have completed. - * - * @note In case of 0 byte packet length write request, message will consist of only transport - * module specific headers. - * - * @retval NRF_SUCCESS Operation success. Packet was added to the transmission queue - * and an event will be send upon transmission completion. - * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not - * added to the transmission queue. User should wait for - * a appropriate event prior issuing this operation again. - * @retval NRF_ERROR_DATA_SIZE Operation failure. Packet size exceeds limit. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - * @retval NRF_ERROR_INVALID_STATE Operation failure. Channel is not open. - */ -uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint32_t length); - -/**@brief Function for extracting received packet. - * - * @note Extracted memory can't be reused by the underlying transport layer untill freed by call to - * hci_transport_rx_pkt_consume(). - * - * @param[out] pp_buffer Pointer to the packet data. - * @param[out] p_length Length of packet data in bytes. - * - * @retval NRF_SUCCESS Operation success. Packet was extracted. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint32_t * p_length); - -/**@brief Function for consuming extracted packet described by p_buffer. - * - * RX memory pointed to by p_buffer is freed and can be reused by the underlying transport layer. - * - * @param[in] p_buffer Pointer to the buffer that has been consumed. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to consume. - * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer. - */ -uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer); - -#endif // HCI_TRANSPORT_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/pstorage.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/pstorage.h deleted file mode 100755 index df0c8b3994..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/pstorage.h +++ /dev/null @@ -1,381 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup persistent_storage Persistent Storage Interface - * @{ - * @ingroup app_common - * @brief Abstracted flash interface. - * - * @details In order to ensure that the SDK and application be moved to alternate persistent storage - * options other than the default provided with NRF solution, an abstracted interface is provided - * by the module to ensure SDK modules and application can be ported to alternate option with ease. - */ - -#ifndef PSTORAGE_H__ -#define PSTORAGE_H__ - -#ifdef __cplusplus -extern "C" { -#endif /* #ifdef __cplusplus */ - -#include "pstorage_platform.h" - - -/**@defgroup ps_opcode Persistent Storage Access Operation Codes - * @{ - * @brief Persistent Storage Access Operation Codes. These are used to report any error during - * a persistent storage access operation or any general error that may occur in the - * interface. - * - * @details Persistent Storage Access Operation Codes used in error notification callback - * registered with the interface to report any error during an persistent storage access - * operation or any general error that may occur in the interface. - */ -#define PSTORAGE_ERROR_OP_CODE 0x01 /**< General Error Code */ -#define PSTORAGE_STORE_OP_CODE 0x02 /**< Error when Store Operation was requested */ -#define PSTORAGE_LOAD_OP_CODE 0x03 /**< Error when Load Operation was requested */ -#define PSTORAGE_CLEAR_OP_CODE 0x04 /**< Error when Clear Operation was requested */ -#define PSTORAGE_UPDATE_OP_CODE 0x05 /**< Update an already touched storage block */ - -/**@} */ - -/**@defgroup pstorage_data_types Persistent Memory Interface Data Types - * @{ - * @brief Data Types needed for interfacing with persistent memory. - * - * @details Data Types needed for interfacing with persistent memory. - */ - -/**@brief Persistent Storage Error Reporting Callback - * - * @details Persistent Storage Error Reporting Callback that is used by the interface to report - * success or failure of a flash operation. Therefore, for any operations, application - * can know when the procedure was complete. For store operation, since no data copy - * is made, receiving a success or failure notification, indicated by the reason - * parameter of callback is an indication that the resident memory could now be reused - * or freed, as the case may be. - * - * @param[in] handle Identifies module and block for which callback is received. - * @param[in] op_code Identifies the operation for which the event is notified. - * @param[in] result Identifies the result of flash access operation. - * NRF_SUCCESS implies, operation succeeded. - * @param[in] p_data Identifies the application data pointer. In case of store operation, this - * points to the resident source of application memory that application can now - * free or reuse. In case of clear, this is NULL as no application pointer is - * needed for this operation. - * @param[in] data_len Length data application had provided for the operation. - * - */ -typedef void (*pstorage_ntf_cb_t)(pstorage_handle_t * p_handle, - uint8_t op_code, - uint32_t result, - uint8_t * p_data, - uint32_t data_len); - - -typedef struct -{ - pstorage_ntf_cb_t cb; /**< Callback registered with the module to be notified of any error occurring in persistent memory management */ - pstorage_size_t block_size; /**< Desired block size for persistent memory storage, for example, if a module has a table with 10 entries, each entry is size 64 bytes, - * it can request 10 blocks with block size 64 bytes. On the other hand, the module can also request one block of size 640 based on - * how it would like to access or alter memory in persistent memory. - * First option is preferred when single entries that need to be updated often when having no impact on the other entries. - * While second option is preferred when entries of table are not changed on individually but have common point of loading and storing - * data. */ - pstorage_size_t block_count; /** Number of blocks requested by the module, minimum values is 1. */ -} pstorage_module_param_t; - -/**@} */ - -/**@defgroup pstorage_routines Persistent Storage Access Routines - * @{ - * @brief Functions/Interface SDK modules use to persistently store data. - * - * @details Interface for Application & SDK module to load/store information persistently. - * Note: that while implementation of each of the persistent storage access function - * depends on the system and can specific to system/solution, the signature of the - * interface routines should not be altered. - */ - -/**@brief Module Initialization Routine. - * - * @details Initializes module. To be called once before any other APIs of the module are used. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - */ -uint32_t pstorage_init(void); - - -/**@brief Register with persistent storage interface. - * - * @param[in] p_module_param Module registration param. - * @param[out] p_block_id Block identifier to identify persistent memory blocks in case - * registration succeeds. Application is expected to use the block ids - * for subsequent operations on requested persistent memory. Maximum - * registrations permitted is determined by configuration parameter - * PSTORAGE_MAX_APPLICATIONS. - * In case more than one memory blocks are requested, the identifier provided here is - * the base identifier for the first block and to identify subsequent block, - * application shall use \@ref pstorage_block_identifier_get with this base identifier - * and block number. Therefore if 10 blocks of size 64 are requested and application - * wishes to store memory in 6th block, it shall use - * \@ref pstorage_block_identifier_get with based id and provide a block number of 5. - * This way application is only expected to remember the base block identifier. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_NO_MEM in case no more registrations can be supported. - */ -uint32_t pstorage_register(pstorage_module_param_t * p_module_param, - pstorage_handle_t * p_block_id); - - -/** - * @brief Function to get block id with reference to base block identifier provided at time of - * registration. - * - * @details Function to get block id with reference to base block identifier provided at time of - * registration. - * In case more than one memory blocks were requested when registering, the identifier - * provided here is the base identifier for the first block and to identify subsequent - * block, application shall use this routine to get block identifier providing input as - * base identifier and block number. Therefore if 10 blocks of size 64 are requested and - * application wishes to store memory in 6th block, it shall use - * \@ref pstorage_block_identifier_get with based id and provide a block number of 5. - * This way application is only expected to remember the base block identifier. - * - * @param[in] p_base_id Base block id received at the time of registration. - * @param[in] block_num Block Number, with first block numbered zero. - * @param[out] p_block_id Block identifier for the block number requested in case the API succeeds. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - */ -uint32_t pstorage_block_identifier_get(pstorage_handle_t * p_base_id, - pstorage_size_t block_num, - pstorage_handle_t * p_block_id); - - -/**@brief Routine to persistently store data of length 'size' contained in 'p_src' address - * in storage module at 'p_dest' address; Equivalent to Storage Write. - * - * @param[in] p_dest Destination address where data is to be stored persistently. - * @param[in] p_src Source address containing data to be stored. API assumes this to be resident - * memory and no intermediate copy of data is made by the API. - * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned. - * @param[in] offset Offset in bytes to be applied when writing to the block. - * For example, if within a block of 100 bytes, application wishes to - * write 20 bytes at offset of 12, then this field should be set to 12. - * Should be word aligned. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - * - * @warning No copy of the data is made, and hence memory provided for data source to be written - * to flash cannot be freed or reused by the application until this procedure - * is complete. End of this procedure is notified to the application using the - * notification callback registered by the application. - */ -uint32_t pstorage_store(pstorage_handle_t * p_dest, - uint8_t * p_src, - pstorage_size_t size, - pstorage_size_t offset); - -/**@brief Routine to update persistently stored data of length 'size' contained in 'p_src' address - * in storage module at 'p_dest' address. - * - * @param[in] p_dest Destination address where data is to be updated. - * @param[in] p_src Source address containing data to be stored. API assumes this to be resident - * memory and no intermediate copy of data is made by the API. - * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned. - * @param[in] offset Offset in bytes to be applied when writing to the block. - * For example, if within a block of 100 bytes, application wishes to - * write 20 bytes at offset of 12, then this field should be set to 12. - * Should be word aligned. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - * - * @warning No copy of the data is made, and hence memory provided for data source to be written - * to flash cannot be freed or reused by the application until this procedure - * is complete. End of this procedure is notified to the application using the - * notification callback registered by the application. - */ -uint32_t pstorage_update(pstorage_handle_t * p_dest, - uint8_t * p_src, - pstorage_size_t size, - pstorage_size_t offset); - -/**@brief Routine to load persistently stored data of length 'size' from 'p_src' address - * to 'p_dest' address; Equivalent to Storage Read. - * - * @param[in] p_dest Destination address where persistently stored data is to be loaded. - * @param[in] p_src Source from where data is to be loaded from persistent memory. - * @param[in] size Size of data to be loaded from persistent memory expressed in bytes. - * Should be word aligned. - * @param[in] offset Offset in bytes to be applied when loading from the block. - * For example, if within a block of 100 bytes, application wishes to - * load 20 bytes from offset of 12, then this field should be set to 12. - * Should be word aligned. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_dst' is not aligned. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - */ -uint32_t pstorage_load(uint8_t * p_dest, - pstorage_handle_t * p_src, - pstorage_size_t size, - pstorage_size_t offset); - -/**@brief Routine to clear data in persistent memory. - * - * @param[in] p_base_id Base block identifier in persistent memory that needs to cleared; - * Equivalent to an Erase Operation. - * - * @param[in] size Size of data to be cleared from persistent memory expressed in bytes. - * This parameter is to provision for clearing of certain blocks - * of memory, or all memory blocks in a registered module. If the total size - * of the application module is used (blocks * block size) in combination with - * the identifier for the first block in the module, all blocks in the - * module will be erased. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_dst' is not aligned. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - * - * @note Clear operations may take time. This API however, does not block until the clear - * procedure is complete. Application is notified of procedure completion using - * notification callback registered by the application. 'result' parameter of the - * callback suggests if the procedure was successful or not. - */ -uint32_t pstorage_clear(pstorage_handle_t * p_base_id, pstorage_size_t size); - -/** - * @brief API to get status of number of pending operations with the module. - * - * @param[out] p_count Number of storage operations pending with the module, if 0, - * there are no outstanding requests. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - */ -uint32_t pstorage_access_status_get(uint32_t * p_count); - -#ifdef PSTORAGE_RAW_MODE_ENABLE - -/**@brief Function for registering with persistent storage interface. - * - * @param[in] p_module_param Module registration param. - * @param[out] p_block_id Block identifier to identify persistent memory blocks in case - * registration succeeds. Application is expected to use the block ids - * for subsequent operations on requested persistent memory. - * In case more than one memory blocks are requested, the identifier provided here is - * the base identifier for the first block and to identify subsequent block, - * application shall use \@ref pstorage_block_identifier_get with this base identifier - * and block number. Therefore if 10 blocks of size 64 are requested and application - * wishes to store memory in 6th block, it shall use - * \@ref pstorage_block_identifier_get with based id and provide a block number of 5. - * This way application is only expected to remember the base block identifier. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_NO_MEM in case no more registrations can be supported. - */ -uint32_t pstorage_raw_register(pstorage_module_param_t * p_module_param, - pstorage_handle_t * p_block_id); - -/**@brief Raw mode function for persistently storing data of length 'size' contained in 'p_src' - * address in storage module at 'p_dest' address; Equivalent to Storage Write. - * - * @param[in] p_dest Destination address where data is to be stored persistently. - * @param[in] p_src Source address containing data to be stored. API assumes this to be resident - * memory and no intermediate copy of data is made by the API. - * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned. - * @param[in] offset Offset in bytes to be applied when writing to the block. - * For example, if within a block of 100 bytes, application wishes to - * write 20 bytes at offset of 12, then this field should be set to 12. - * Should be word aligned. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - * - * @warning No copy of the data is made, and hence memory provided for data source to be written - * to flash cannot be freed or reused by the application until this procedure - * is complete. End of this procedure is notified to the application using the - * notification callback registered by the application. - */ -uint32_t pstorage_raw_store(pstorage_handle_t * p_dest, - uint8_t * p_src, - pstorage_size_t size, - pstorage_size_t offset); - -/**@brief Function for clearing data in persistent memory in raw mode. - * - * @param[in] p_dest Base block identifier in persistent memory that needs to cleared; - * Equivalent to an Erase Operation. - * @param[in] size Size of data to be cleared from persistent memory expressed in bytes. - * This is currently unused. And a clear would mean clearing all blocks, - * however, this parameter is to provision for clearing of certain blocks - * of memory only and not all if need be. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - * - * @note Clear operations may take time. This API however, does not block until the clear - * procedure is complete. Application is notified of procedure completion using - * notification callback registered by the application. 'result' parameter of the - * callback suggests if the procedure was successful or not. - */ -uint32_t pstorage_raw_clear(pstorage_handle_t * p_dest, pstorage_size_t size); - -#endif // PSTORAGE_RAW_MODE_ENABLE - -#ifdef __cplusplus -} -#endif /* #ifdef __cplusplus */ - - -/**@} */ -/**@} */ - -#endif // PSTORAGE_H__ - diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/sd_common/app_util_platform.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/sd_common/app_util_platform.h deleted file mode 100644 index 44abff6e46..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/sd_common/app_util_platform.h +++ /dev/null @@ -1,110 +0,0 @@ -/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup app_util_platform Utility Functions and Definitions (Platform) - * @{ - * @ingroup app_common - * - * @brief Various types and definitions available to all applications when using SoftDevice. - */ - -#ifndef APP_UTIL_PLATFORM_H__ -#define APP_UTIL_PLATFORM_H__ - -#include -#include "compiler_abstraction.h" -#include "nrf51.h" -#include "app_error.h" - -/**@brief The interrupt priorities available to the application while the SoftDevice is active. */ -typedef enum -{ - APP_IRQ_PRIORITY_HIGH = 1, - APP_IRQ_PRIORITY_LOW = 3 -} app_irq_priority_t; - -#define NRF_APP_PRIORITY_THREAD 4 /**< "Interrupt level" when running in Thread Mode. */ - -/**@cond NO_DOXYGEN */ -#define EXTERNAL_INT_VECTOR_OFFSET 16 -/**@endcond */ - -#define PACKED(TYPE) __packed TYPE - -/**@brief Macro for entering a critical region. - * - * @note Due to implementation details, there must exist one and only one call to - * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located - * in the same scope. - */ -#define CRITICAL_REGION_ENTER() \ - { \ - uint8_t IS_NESTED_CRITICAL_REGION = 0; \ - uint32_t CURRENT_INT_PRI = current_int_priority_get(); \ - if (CURRENT_INT_PRI != APP_IRQ_PRIORITY_HIGH) \ - { \ - uint32_t ERR_CODE = sd_nvic_critical_region_enter(&IS_NESTED_CRITICAL_REGION); \ - if (ERR_CODE == NRF_ERROR_SOFTDEVICE_NOT_ENABLED) \ - { \ - __disable_irq(); \ - } \ - else \ - { \ - APP_ERROR_CHECK(ERR_CODE); \ - } \ - } - -/**@brief Macro for leaving a critical region. - * - * @note Due to implementation details, there must exist one and only one call to - * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located - * in the same scope. - */ -#define CRITICAL_REGION_EXIT() \ - if (CURRENT_INT_PRI != APP_IRQ_PRIORITY_HIGH) \ - { \ - uint32_t ERR_CODE; \ - __enable_irq(); \ - ERR_CODE = sd_nvic_critical_region_exit(IS_NESTED_CRITICAL_REGION); \ - if (ERR_CODE != NRF_ERROR_SOFTDEVICE_NOT_ENABLED) \ - { \ - APP_ERROR_CHECK(ERR_CODE); \ - } \ - } \ - } - -/**@brief Function for finding the current interrupt level. - * - * @return Current interrupt level. - * @retval APP_IRQ_PRIORITY_HIGH We are running in Application High interrupt level. - * @retval APP_IRQ_PRIORITY_LOW We are running in Application Low interrupt level. - * @retval APP_IRQ_PRIORITY_THREAD We are running in Thread Mode. - */ -static __INLINE uint8_t current_int_priority_get(void) -{ - uint32_t isr_vector_num = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); - if (isr_vector_num > 0) - { - int32_t irq_type = ((int32_t)isr_vector_num - EXTERNAL_INT_VECTOR_OFFSET); - return (NVIC_GetPriority((IRQn_Type)irq_type) & 0xFF); - } - else - { - return NRF_APP_PRIORITY_THREAD; - } -} - -#endif // APP_UTIL_PLATFORM_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c index 948c8424ff..8e3e8c34c7 100755 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c @@ -194,10 +194,10 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) if (enable) { switch (irq) { case RxIrq: - obj->uart->INTEN |= (UART_INTENSET_RXDRDY_Msk); + obj->uart->INTENSET = (UART_INTENSET_RXDRDY_Msk); break; case TxIrq: - obj->uart->INTEN |= (UART_INTENSET_TXDRDY_Msk); + obj->uart->INTENSET = (UART_INTENSET_TXDRDY_Msk); break; } NVIC_SetPriority(irq_n, 3); @@ -209,12 +209,12 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) int all_disabled = 0; switch (irq) { case RxIrq: - obj->uart->INTEN &= ~(UART_INTENCLR_RXDRDY_Msk); - all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_TXDRDY_Msk)) == 0; + obj->uart->INTENCLR = (UART_INTENCLR_RXDRDY_Msk); + all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_TXDRDY_Msk)) == 0; break; case TxIrq: - obj->uart->INTEN &= ~(UART_INTENCLR_TXDRDY_Msk); - all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_RXDRDY_Msk)) == 0; + obj->uart->INTENCLR = (UART_INTENCLR_TXDRDY_Msk); + all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_RXDRDY_Msk)) == 0; break; } diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index b6dba7b2c4..1d5164ffaf 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -763,6 +763,8 @@ class NRF51822(Target): Target.__init__(self) self.core = "Cortex-M0" self.extra_labels = ["NORDIC", "NRF51822_MKIT", "MCU_NRF51822", "MCU_NORDIC_16K"] + self.common_macros = ['NRF51'] + self.macros = self.common_macros self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] self.is_disk_virtual = True self.detect_code = ["1070"] @@ -816,6 +818,7 @@ class NRF51822_BOOT(NRF51822): self.core = "Cortex-M0" self.extra_labels = ["NORDIC", "NRF51822_MKIT", "MCU_NRF51822", "MCU_NORDIC_16K", "NRF51822"] self.macros = ['TARGET_NRF51822', 'TARGET_OTA_ENABLED'] + self.macros += self.common_macros self.supported_toolchains = ["ARM", "GCC_ARM"] self.MERGE_SOFT_DEVICE = True self.MERGE_BOOTLOADER = True @@ -826,6 +829,7 @@ class NRF51822_OTA(NRF51822): self.core = "Cortex-M0" self.extra_labels = ["NORDIC", "NRF51822_MKIT", "MCU_NRF51822", "MCU_NORDIC_16K", "NRF51822"] self.macros = ['TARGET_NRF51822', 'TARGET_OTA_ENABLED'] + self.macros += self.common_macros self.supported_toolchains = ["ARM", "GCC_ARM"] self.MERGE_SOFT_DEVICE = False @@ -834,6 +838,7 @@ class NRF51_DK(NRF51822): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_32K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros self.supported_form_factors = ["ARDUINO"] class NRF51_DK_BOOT(NRF51822): @@ -842,6 +847,7 @@ class NRF51_DK_BOOT(NRF51822): self.core = "Cortex-M0" self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_32K', 'NRF51_DK'] self.macros = ['TARGET_NRF51822', 'TARGET_NRF51_DK', 'TARGET_OTA_ENABLED'] + self.macros += self.common_macros self.supported_toolchains = ["ARM", "GCC_ARM"] self.MERGE_SOFT_DEVICE = True self.MERGE_BOOTLOADER = True @@ -852,6 +858,7 @@ class NRF51_DK_OTA(NRF51822): self.core = "Cortex-M0" self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_32K', 'NRF51_DK'] self.macros = ['TARGET_NRF51822', 'TARGET_NRF51_DK', 'TARGET_OTA_ENABLED'] + self.macros += self.common_macros self.supported_toolchains = ["ARM", "GCC_ARM"] self.MERGE_SOFT_DEVICE = False @@ -860,12 +867,14 @@ class NRF51_DONGLE(NRF51822): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_32K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros class ARCH_BLE(NRF51822): def __init__(self): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros self.supported_form_factors = ["ARDUINO"] class SEEED_TINY_BLE(NRF51822): @@ -873,12 +882,14 @@ class SEEED_TINY_BLE(NRF51822): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros class SEEED_TINY_BLE_BOOT(NRF51822): def __init__(self): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'SEEED_TINY_BLE'] self.macros = ['TARGET_NRF51822', 'TARGET_SEEED_TINY_BLE', 'TARGET_OTA_ENABLED'] + self.macros += self.common_macros self.MERGE_SOFT_DEVICE = True self.MERGE_BOOTLOADER = True @@ -887,6 +898,7 @@ class SEEED_TINY_BLE_OTA(NRF51822): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'SEEED_TINY_BLE'] self.macros = ['TARGET_NRF51822', 'TARGET_SEEED_TINY_BLE', 'TARGET_OTA_ENABLED'] + self.macros += self.common_macros self.MERGE_SOFT_DEVICE = False class HRM1017(NRF51822): @@ -894,12 +906,14 @@ class HRM1017(NRF51822): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros class RBLAB_NRF51822(NRF51822): def __init__(self): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros self.supported_form_factors = ["ARDUINO"] class RBLAB_BLENANO(NRF51822): @@ -907,12 +921,14 @@ class RBLAB_BLENANO(NRF51822): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros class NRF51822_Y5_MBUG(NRF51822): def __init__(self): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros class XADOW_M0(LPCTarget): def __init__(self): @@ -927,6 +943,7 @@ class WALLBOT_BLE(NRF51822): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros class DELTA_DFCM_NNN40(NRF51822): def __init__(self): @@ -934,6 +951,7 @@ class DELTA_DFCM_NNN40(NRF51822): self.core = "Cortex-M0" self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros class DELTA_DFCM_NNN40_OTA(NRF51822): def __init__(self): @@ -941,13 +959,15 @@ class DELTA_DFCM_NNN40_OTA(NRF51822): self.core = "Cortex-M0" self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'DELTA_DFCM_NNN40'] self.MERGE_SOFT_DEVICE = False + self.macros += self.common_macros + class DELTA_DFCM_NNN40_OTA(NRF51822): def __init__(self): NRF51822.__init__(self) self.core = "Cortex-M0" self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'DELTA_DFCM_NNN40'] self.MERGE_SOFT_DEVICE = False - + self.macros += self.common_macros ### ARM ### From e8348cffee9a7f2e55e7543b9b561a0462241ae6 Mon Sep 17 00:00:00 2001 From: Mike Fiore Date: Wed, 1 Apr 2015 15:29:49 -0500 Subject: [PATCH 03/13] [MTS_DRAGONFLY_F411RE][MTS_MDOT_F411RE] add explicit seek() call when combining bootloader and application binaries so Windows builds succeed --- workspace_tools/targets.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 3a3286a625..ef8b759249 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -734,6 +734,7 @@ class MTS_MDOT_F411RE(Target): part.close() outbin.seek(0, 0) data = outbin.read() + outbin.seek(0, 1) crc = struct.pack(' Date: Fri, 3 Apr 2015 13:27:35 +0900 Subject: [PATCH 04/13] Fix a bug that build error will occur in GCC. When export RZ/A1H project of GCC from web compiler, build will be error because some assembler file use // comments. --- .../TOOLCHAIN_GCC_ARM/startup_RZ1AH.s | 16 +++--- .../TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.s | 52 +++++++++---------- 2 files changed, 34 insertions(+), 34 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s index 95326c0287..f6cf2082bf 100644 --- a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s @@ -113,14 +113,14 @@ __HeapLimit: .align 2 .globl __isr_vector __isr_vector: - .long 0xe59ff018 // 0x00 - .long 0xe59ff018 // 0x04 - .long 0xe59ff018 // 0x08 - .long 0xe59ff018 // 0x0c - .long 0xe59ff018 // 0x10 - .long 0xe59ff018 // 0x14 - .long 0xe59ff018 // 0x18 - .long 0xe59ff018 // 0x1c + .long 0xe59ff018 /* 0x00 */ + .long 0xe59ff018 /* 0x04 */ + .long 0xe59ff018 /* 0x08 */ + .long 0xe59ff018 /* 0x0c */ + .long 0xe59ff018 /* 0x10 */ + .long 0xe59ff018 /* 0x14 */ + .long 0xe59ff018 /* 0x18 */ + .long 0xe59ff018 /* 0x1c */ .long Reset_Handler /* 0x20 */ .long Undef_Handler /* 0x24 */ diff --git a/libraries/mbed/targets/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.s b/libraries/mbed/targets/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.s index 47963d724a..d37f889191 100644 --- a/libraries/mbed/targets/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.s +++ b/libraries/mbed/targets/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.s @@ -38,47 +38,47 @@ __v7_all_cache: PUSH {R4-R11} - MRC p15, 1, R6, c0, c0, 1 // Read CLIDR - ANDS R3, R6, #0x07000000 // Extract coherency level - MOV R3, R3, LSR #23 // Total cache levels << 1 - BEQ Finished // If 0, no need to clean + MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */ + ANDS R3, R6, #0x07000000 /* Extract coherency level */ + MOV R3, R3, LSR #23 /* Total cache levels << 1 */ + BEQ Finished /* If 0, no need to clean */ - MOV R10, #0 // R10 holds current cache level << 1 -Loop1: ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position - MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level - AND R1, R1, #7 // Isolate those lower 3 bits + MOV R10, #0 /* R10 holds current cache level << 1 */ +Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */ + MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */ + AND R1, R1, #7 /* Isolate those lower 3 bits */ CMP R1, #2 - BLT Skip // No cache or only instruction cache at this level + BLT Skip /* No cache or only instruction cache at this level */ - MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register - ISB // ISB to sync the change to the CacheSizeID reg - MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register - AND R2, R1, #7 // Extract the line length field - ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes) + MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */ + ISB /* ISB to sync the change to the CacheSizeID reg */ + MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */ + AND R2, R1, #7 /* Extract the line length field */ + ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */ LDR R4, =0x3FF - ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned) - CLZ R5, R4 // R5 is the bit position of the way size increment + ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */ + CLZ R5, R4 /* R5 is the bit position of the way size increment */ LDR R7, =0x7FFF - ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned) + ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */ -Loop2: MOV R9, R4 // R9 working copy of the max way size (right aligned) +Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */ -Loop3: ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11 - ORR R11, R11, R7, LSL R2 // Factor in the Set number +Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */ + ORR R11, R11, R7, LSL R2 /* Factor in the Set number */ CMP R0, #0 BNE Dccsw - MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way + MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */ B cont Dccsw: CMP R0, #1 BNE Dccisw - MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way + MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */ B cont -Dccisw: MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way -cont: SUBS R9, R9, #1 // Decrement the Way number +Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */ +cont: SUBS R9, R9, #1 /* Decrement the Way number */ BGE Loop3 - SUBS R7, R7, #1 // Decrement the Set number + SUBS R7, R7, #1 /* Decrement the Set number */ BGE Loop2 -Skip: ADD R10, R10, #2 // increment the cache number +Skip: ADD R10, R10, #2 /* increment the cache number */ CMP R3, R10 BGT Loop1 From 2bc9c4299b4121bbe3b603e26c842003a7f10744 Mon Sep 17 00:00:00 2001 From: Toyomasa Watarai Date: Fri, 3 Apr 2015 18:03:31 +0900 Subject: [PATCH 05/13] [LPC824] Add UART channel dupilication check - Add check_duplication() function to detect UART duplication which is reported https://github.com/mbedmicro/mbed/issues/942 - Confirmed to pass MBED_A9 test case (Serial Echo at 115200) - Add a variable initialize code to prevent GCC warning --- .../hal/TARGET_NXP/TARGET_LPC82X/serial_api.c | 31 ++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/serial_api.c index e3dc97e200..a6fa658d04 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/serial_api.c @@ -90,10 +90,39 @@ static uart_irq_handler irq_handler; int stdio_uart_inited = 0; serial_t stdio_uart; +static int check_duplication(serial_t *obj, PinName tx, PinName rx) +{ + if (uart_used == 0) + return 0; + + const SWM_Map *swm; + uint32_t assigned_tx, assigned_rx; + int ch; + for (ch=0; chPINASSIGN[swm->n] & (0xFF << swm->offset); + assigned_tx = assigned_tx >> swm->offset; + // read assigned RX in the UART channel of switch matrix + swm = &SWM_UART_RX[ch]; + assigned_rx = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset); + assigned_rx = assigned_rx >> swm->offset; + if ((assigned_tx == (uint32_t)(tx >> PIN_SHIFT)) && (assigned_rx == (uint32_t)(rx >> PIN_SHIFT))) { + obj->index = ch; + obj->uart = (LPC_USART0_Type *)(LPC_USART0_BASE + (0x4000 * ch)); + return 1; + } + } + return 0; +} + void serial_init(serial_t *obj, PinName tx, PinName rx) { int is_stdio_uart = 0; + if (check_duplication(obj, tx, rx) == 1) + return; + int uart_n = get_available_uart(); if (uart_n == -1) { error("No available UART"); @@ -192,7 +221,7 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b stop_bits -= 1; data_bits -= 7; - int paritysel; + int paritysel = 0; switch (parity) { case ParityNone: paritysel = 0; break; case ParityEven: paritysel = 2; break; From dcd864171de3588952bf08bc7dd03f1b6209bf33 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Fri, 3 Apr 2015 17:17:17 +0200 Subject: [PATCH 06/13] [NUCLEO_F303RE] RTOS singletest adding RTOS tests for NUCLEO_F303RE in singletest.py --- workspace_tools/tests.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index 6cd9dc595c..f73c203e7d 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -612,7 +612,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC"], + "DISCO_F401VC", "NUCLEO_F303RE"], }, { "id": "RTOS_2", "description": "Mutex resource lock", @@ -625,7 +625,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC"], + "DISCO_F401VC", "NUCLEO_F303RE"], }, { "id": "RTOS_3", "description": "Semaphore resource lock", @@ -638,7 +638,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC"], + "DISCO_F401VC", "NUCLEO_F303RE"], }, { "id": "RTOS_4", "description": "Signals messaging", @@ -650,7 +650,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC"], + "DISCO_F401VC", "NUCLEO_F303RE"], }, { "id": "RTOS_5", "description": "Queue messaging", @@ -662,7 +662,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC"], + "DISCO_F401VC", "NUCLEO_F303RE"], }, { "id": "RTOS_6", "description": "Mail messaging", @@ -674,7 +674,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC"], + "DISCO_F401VC", "NUCLEO_F303RE"], }, { "id": "RTOS_7", "description": "Timer", @@ -688,7 +688,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC"], + "DISCO_F401VC", "NUCLEO_F303RE"], }, { "id": "RTOS_8", "description": "ISR (Queue)", @@ -700,7 +700,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC"], + "DISCO_F401VC", "NUCLEO_F303RE"], }, { "id": "RTOS_9", "description": "SD File write-read", From 61ce8ac1321836383ea93f08bcde94a064609751 Mon Sep 17 00:00:00 2001 From: Jurgis Jurksta Date: Sun, 5 Apr 2015 19:01:45 +0300 Subject: [PATCH 07/13] Enable LPC1549 usart when configuring it --- .../hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c index 667c7833e9..237ffa991a 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c @@ -211,8 +211,18 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b default: break; } - - obj->uart->CFG = (data_bits << 2) + + // First disable the the usart as described in documentation and then enable while updating CFG + + // 24.6.1 USART Configuration register + // Remark: If software needs to change configuration values, the following sequence should + // be used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable + // the USART by writing a 0 to the Enable bit (0 may be written to the entire register). 3) + // Write the new configuration value, with the ENABLE bit set to 1. + obj->uart->CFG &= ~(1 << 0); + + obj->uart->CFG = (1 << 0) // this will enable the usart + | (data_bits << 2) | (paritysel << 4) | (stop_bits << 6); } From 93af661dbf8a7e0bb393acee30ce84d110372198 Mon Sep 17 00:00:00 2001 From: Jurgis Jurksta Date: Sun, 5 Apr 2015 22:28:49 +0300 Subject: [PATCH 08/13] Properly disable LPC1549 usart interrupt --- .../mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c index 667c7833e9..462b364874 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c @@ -251,7 +251,7 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { } else { // disable int all_disabled = 0; SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); - obj->uart->INTENSET &= ~(1 << ((irq == RxIrq) ? 0 : 2)); + obj->uart->INTENCLR |= (1 << ((irq == RxIrq) ? 0 : 2)); // disable the interrupt all_disabled = (obj->uart->INTENSET & (1 << ((other_irq == RxIrq) ? 0 : 2))) == 0; if (all_disabled) NVIC_DisableIRQ(irq_n); From 0228696f48258355dcc830daec454e3ca5e81971 Mon Sep 17 00:00:00 2001 From: PaggyCyntec Date: Tue, 7 Apr 2015 14:39:58 +0800 Subject: [PATCH 09/13] Update main.cpp removed "union" because it causes the result of auto-test not stable (sometimes FAIL, sometimes PASS), after removed, the test result is all PASS. --- libraries/tests/mbed/stdio/main.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/libraries/tests/mbed/stdio/main.cpp b/libraries/tests/mbed/stdio/main.cpp index 0b2445de9b..bdfd53c976 100644 --- a/libraries/tests/mbed/stdio/main.cpp +++ b/libraries/tests/mbed/stdio/main.cpp @@ -15,9 +15,8 @@ int main() { DigitalOut led1(LED1); DigitalOut led2(LED2); - union { - int value_int; - }; + int value_int; + notify_start(); // Just to sync with host test supervisor From 1e7fe7474b9df6706bec648c47f5cfe5f7f16b3f Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Tue, 7 Apr 2015 16:46:17 +0900 Subject: [PATCH 10/13] Fix a bug that there is a case that can not be normal communication in I2C. When the following conditions, may not be the normal communication in I2C. 1. A device for I2C address was not found 2. Set "repeated = true". --- .../TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c | 77 ++++++++----------- 1 file changed, 31 insertions(+), 46 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c index 51e89d832a..e3732e62d2 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c @@ -58,7 +58,7 @@ volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; #define SR2_TEND (1 << 6) #define SR2_TDRE (1 << 7) -#define TIMEOUT_1S (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */ +#define WAIT_TIMEOUT (4200) /* Loop counter : Time-out is about 1ms. By 4200 loops, measured value is 1009ms. */ static const PinMap PinMap_I2C_SDA[] = { {P1_1 , I2C_0, 1}, @@ -108,7 +108,7 @@ static inline int i2c_wait_RDRF(i2c_t *obj) { /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ while (!(i2c_status(obj) & SR2_RDRF)) { timeout ++; - if (timeout >= TIMEOUT_1S) { + if (timeout >= WAIT_TIMEOUT) { return -1; } } @@ -122,7 +122,7 @@ static int i2c_wait_TDRE(i2c_t *obj) { /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ while (!(i2c_status(obj) & SR2_TDRE)) { timeout ++; - if (timeout >= TIMEOUT_1S) { + if (timeout >= WAIT_TIMEOUT) { return -1; } } @@ -136,7 +136,7 @@ static int i2c_wait_TEND(i2c_t *obj) { /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ while (!(i2c_status(obj) & SR2_TEND)) { timeout ++; - if (timeout >= TIMEOUT_1S) { + if (timeout >= WAIT_TIMEOUT) { return -1; } } @@ -151,7 +151,7 @@ static int i2c_wait_START(i2c_t *obj) { /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ while (!(i2c_status(obj) & SR2_START)) { timeout ++; - if (timeout >= TIMEOUT_1S) { + if (timeout >= WAIT_TIMEOUT) { return -1; } } @@ -165,7 +165,7 @@ static int i2c_wait_STOP(i2c_t *obj) { /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ while (!(i2c_status(obj) & SR2_STOP)) { timeout ++; - if (timeout >= TIMEOUT_1S) { + if (timeout >= WAIT_TIMEOUT) { return -1; } } @@ -265,17 +265,11 @@ inline int i2c_stop(i2c_t *obj) { return 0; } -static void i2c_set_err_noslave(i2c_t *obj, int stop) { - if (stop) { - (void)i2c_stop(obj); - (void)i2c_wait_STOP(obj); - i2c_set_SR2_NACKF_STOP(obj); - } else { - (void)i2c_restart(obj); - (void)i2c_wait_START(obj); - /* SR2.START = 0 */ - REG(SR2.UINT32) &= ~SR2_START; - } +static void i2c_set_err_noslave(i2c_t *obj) { + (void)i2c_stop(obj); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + obj->last_stop_flag = 1; } static inline int i2c_do_write(i2c_t *obj, int value) { @@ -287,7 +281,7 @@ static inline int i2c_do_write(i2c_t *obj, int value) { while (!(i2c_status(obj) & SR2_TDRE)) { /* RIICnSR2.TDRE=0 */ timeout ++; - if (timeout >= TIMEOUT_1S) { + if (timeout >= WAIT_TIMEOUT) { return -1; } if (i2c_status(obj) & SR2_NACKF) { @@ -432,7 +426,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { if (obj->last_stop_flag != 0) { status = i2c_start(obj); if (status != 0) { - i2c_set_err_noslave(obj, stop); + i2c_set_err_noslave(obj); return I2C_ERROR_BUS_BUSY; } } @@ -440,7 +434,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { /* Send Slave address */ status = i2c_read_address_write(obj, (address | 0x01)); if (status != 0) { - i2c_set_err_noslave(obj, stop); + i2c_set_err_noslave(obj); return I2C_ERROR_NO_SLAVE; } /* wait RDRF */ @@ -448,21 +442,12 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { /* check ACK/NACK */ if ((status != 0) || (REG(SR2.UINT32) & SR2_NACKF == 1)) { /* Slave sends NACK */ - /* If not repeated start, send stop. */ - if (stop) { - i2c_stop(obj); - /* dummy read */ - value = REG(DRR.UINT32); - (void)i2c_wait_STOP(obj); - i2c_set_SR2_NACKF_STOP(obj); - } else { - (void)i2c_restart(obj); - /* dummy read */ - value = REG(DRR.UINT32); - (void)i2c_wait_START(obj); - /* SR2.START = 0 */ - REG(SR2.UINT32) &= ~SR2_START; - } + i2c_stop(obj); + /* dummy read */ + value = REG(DRR.UINT32); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + obj->last_stop_flag = 1; return I2C_ERROR_NO_SLAVE; } /* Read in all except last byte */ @@ -473,7 +458,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { /* wait for it to arrive */ status = i2c_wait_RDRF(obj); if (status != 0) { - i2c_set_err_noslave(obj, stop); + i2c_set_err_noslave(obj); return I2C_ERROR_NO_SLAVE; } /* Recieve the data */ @@ -494,7 +479,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { /* wait for it to arrive */ status = i2c_wait_RDRF(obj); if (status != 0) { - i2c_set_err_noslave(obj, stop); + i2c_set_err_noslave(obj); return I2C_ERROR_NO_SLAVE; } i2c_set_MR3_NACK(obj); @@ -511,7 +496,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { /* wait for it to arrive */ status = i2c_wait_RDRF(obj); if (status != 0) { - i2c_set_err_noslave(obj, stop); + i2c_set_err_noslave(obj); return I2C_ERROR_NO_SLAVE; } @@ -552,7 +537,7 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { if (obj->last_stop_flag != 0) { status = i2c_start(obj); if (status != 0) { - i2c_set_err_noslave(obj, stop); + i2c_set_err_noslave(obj); return I2C_ERROR_BUS_BUSY; } } @@ -560,21 +545,21 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { /* Send Slave address */ status = i2c_do_write(obj, address); if (status != 0) { - i2c_set_err_noslave(obj, stop); + i2c_set_err_noslave(obj); return I2C_ERROR_NO_SLAVE; } /* Send Write data */ for (cnt=0; cnt= TIMEOUT_1S) { + if (timeout >= WAIT_TIMEOUT) { return -1; } } @@ -730,7 +715,7 @@ int i2c_slave_write(i2c_t *obj, const char *data, int length) { /* Wait send end */ status = i2c_wait_TEND(obj); if (status != 0) { - i2c_set_err_noslave(obj, 1); + i2c_set_err_noslave(obj); return 0; } } From 3f7718cec44835c18e9f457e6a28f2b773acda9f Mon Sep 17 00:00:00 2001 From: Jeremy Brodt Date: Thu, 9 Oct 2014 11:54:03 -0500 Subject: [PATCH 11/13] Adding MAXWSNENV platform. --- .../TOOLCHAIN_ARM_STD/MAX32610.sct | 21 + .../TOOLCHAIN_ARM_STD/startup_MAX32610.s | 256 +++++++ .../TARGET_MAX32610/TOOLCHAIN_ARM_STD/sys.cpp | 57 ++ .../TOOLCHAIN_GCC_ARM/max32610.ld | 182 +++++ .../TOOLCHAIN_GCC_ARM/startup_max32610.S | 262 +++++++ .../TOOLCHAIN_IAR/MAX32610.icf | 29 + .../TOOLCHAIN_IAR/startup_MAX32610.s | 383 ++++++++++ .../TARGET_Maxim/TARGET_MAX32610/adc_regs.h | 466 +++++++++++++ .../TARGET_Maxim/TARGET_MAX32610/aes_regs.h | 159 +++++ .../TARGET_Maxim/TARGET_MAX32610/afe_regs.h | 626 +++++++++++++++++ .../TARGET_MAX32610/clkman_regs.h | 493 +++++++++++++ .../TARGET_Maxim/TARGET_MAX32610/cmsis.h | 40 ++ .../TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.c | 65 ++ .../TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.h | 53 ++ .../TARGET_Maxim/TARGET_MAX32610/crc_regs.h | 89 +++ .../TARGET_Maxim/TARGET_MAX32610/dac_regs.h | 180 +++++ .../TARGET_Maxim/TARGET_MAX32610/flc_regs.h | 210 ++++++ .../TARGET_Maxim/TARGET_MAX32610/gpio_regs.h | 477 +++++++++++++ .../TARGET_Maxim/TARGET_MAX32610/i2cm_regs.h | 192 +++++ .../TARGET_Maxim/TARGET_MAX32610/icc_regs.h | 96 +++ .../TARGET_Maxim/TARGET_MAX32610/ioman_regs.h | 508 ++++++++++++++ .../TARGET_Maxim/TARGET_MAX32610/maa_regs.h | 124 ++++ .../TARGET_Maxim/TARGET_MAX32610/max32610.h | 655 ++++++++++++++++++ .../TARGET_Maxim/TARGET_MAX32610/pmu_regs.h | 111 +++ .../TARGET_Maxim/TARGET_MAX32610/pt_regs.h | 175 +++++ .../TARGET_MAX32610/pwrman_regs.h | 386 +++++++++++ .../TARGET_MAX32610/pwrseq_regs.h | 299 ++++++++ .../TARGET_Maxim/TARGET_MAX32610/rtc_regs.h | 246 +++++++ .../TARGET_Maxim/TARGET_MAX32610/spi_regs.h | 215 ++++++ .../TARGET_MAX32610/system_max32610.c | 147 ++++ .../TARGET_MAX32610/system_max32610.h | 53 ++ .../TARGET_Maxim/TARGET_MAX32610/tmr_regs.h | 146 ++++ .../TARGET_Maxim/TARGET_MAX32610/tpu_regs.h | 108 +++ .../TARGET_Maxim/TARGET_MAX32610/trim_regs.h | 92 +++ .../TARGET_Maxim/TARGET_MAX32610/uart_regs.h | 175 +++++ .../TARGET_Maxim/TARGET_MAX32610/usb_regs.h | 453 ++++++++++++ .../TARGET_Maxim/TARGET_MAX32610/wdt_regs.h | 150 ++++ .../TARGET_MAX32610/PeripheralNames.h | 87 +++ .../TARGET_MAX32610/PeripheralPins.c | 186 +++++ .../TARGET_MAX32610/PeripheralPins.h | 65 ++ .../TARGET_Maxim/TARGET_MAX32610/PinNames.h | 136 ++++ .../TARGET_Maxim/TARGET_MAX32610/PortNames.h | 50 ++ .../TARGET_MAXWSNENV/PeripheralAliases.h | 41 ++ .../TARGET_MAXWSNENV/PinAliases.h | 74 ++ .../TARGET_MAXWSNENV/low_level_init.c | 48 ++ .../TARGET_MAX32610/analogin_api.c | 144 ++++ .../TARGET_MAX32610/analogout_api.c | 213 ++++++ .../hal/TARGET_Maxim/TARGET_MAX32610/device.h | 72 ++ .../TARGET_Maxim/TARGET_MAX32610/gpio_api.c | 94 +++ .../TARGET_MAX32610/gpio_irq_api.c | 168 +++++ .../TARGET_MAX32610/gpio_object.h | 71 ++ .../TARGET_Maxim/TARGET_MAX32610/i2c_api.c | 405 +++++++++++ .../TARGET_Maxim/TARGET_MAX32610/objects.h | 118 ++++ .../hal/TARGET_Maxim/TARGET_MAX32610/pinmap.c | 105 +++ .../TARGET_Maxim/TARGET_MAX32610/port_api.c | 97 +++ .../TARGET_Maxim/TARGET_MAX32610/pwmout_api.c | 234 +++++++ .../TARGET_Maxim/TARGET_MAX32610/rtc_api.c | 190 +++++ .../TARGET_Maxim/TARGET_MAX32610/serial_api.c | 355 ++++++++++ .../hal/TARGET_Maxim/TARGET_MAX32610/sleep.c | 169 +++++ .../TARGET_Maxim/TARGET_MAX32610/spi_api.c | 190 +++++ .../TARGET_Maxim/TARGET_MAX32610/us_ticker.c | 261 +++++++ .../rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h | 3 + .../rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c | 7 +- .../tests/mbed/digitalin_digitalout/main.cpp | 4 + libraries/tests/mbed/digitalinout/main.cpp | 4 + libraries/tests/mbed/i2c_TMP102/main.cpp | 3 +- libraries/tests/mbed/i2c_master/main.cpp | 2 +- libraries/tests/mbed/interruptin/main.cpp | 4 + libraries/tests/mbed/portinout/main.cpp | 9 + libraries/tests/mbed/portout/main.cpp | 5 + libraries/tests/mbed/portout_portin/main.cpp | 9 + libraries/tests/mbed/pwm/main.cpp | 9 + libraries/tests/mbed/pwm_led/pwm.cpp | 3 + .../tests/mbed/serial_interrupt_2/main.cpp | 2 + workspace_tools/targets.py | 13 + workspace_tools/tests.py | 19 +- 76 files changed, 12036 insertions(+), 12 deletions(-) create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/MAX32610.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/startup_MAX32610.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/max32610.ld create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/startup_max32610.S create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/MAX32610.icf create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/startup_MAX32610.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/adc_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/aes_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/afe_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/clkman_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/crc_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/dac_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/flc_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/gpio_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/i2cm_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/icc_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/ioman_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/maa_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pmu_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pt_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrman_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrseq_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/rtc_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/spi_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tmr_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tpu_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/trim_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/uart_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/usb_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/wdt_regs.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PortNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PeripheralAliases.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PinAliases.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/low_level_init.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogin_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogout_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/device.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_irq_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_object.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/i2c_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/objects.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/pinmap.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/port_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/pwmout_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/rtc_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/serial_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/sleep.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/spi_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/us_ticker.c diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/MAX32610.sct b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/MAX32610.sct new file mode 100644 index 0000000000..61369d3054 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/MAX32610.sct @@ -0,0 +1,21 @@ + +; MAX32610 +; 256KB FLASH (0x40000) @ 0x000000000 +; 2KB RAM (0x8000) @ 0x20000000 + + +; MAX32610: 256KB FLASH (0x40000) + 32KB RAM (0x8000) + +LR_IROM1 0x00000000 0x40000 { ; load region size_region + ER_IROM1 0x00000000 0x40000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; [RAM] Vector table dynamic copy: 79 vectors * 4 bytes = (0x140) - alignment + RW_IRAM1 (0x20000000+0x140) (0x8000-0x140) { ; RW data + .ANY (+RW +ZI) + } + +} \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/startup_MAX32610.s b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/startup_MAX32610.s new file mode 100644 index 0000000000..933e7871ce --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/startup_MAX32610.s @@ -0,0 +1,256 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp /* Top of Stack */ + DCD Reset_Handler /* Reset Handler */ + DCD NMI_Handler /* NMI Handler */ + DCD HardFault_Handler /* Hard Fault Handler */ + DCD DefaultIRQ_Handler /* MPU Fault Handler */ + DCD DefaultIRQ_Handler /* Bus Fault Handler */ + DCD DefaultIRQ_Handler /* Usage Fault Handler */ + DCD 0 /* Reserved */ + DCD 0 /* Reserved */ + DCD 0 /* Reserved */ + DCD 0 /* Reserved */ + DCD DefaultIRQ_Handler /* SVCall Handler */ + DCD DebugMon_Handler /* Debug Monitor Handler */ + DCD 0 /* Reserved */ + DCD DefaultIRQ_Handler /* PendSV Handler */ + DCD SysTick_IRQHandler /* SysTick Handler */ + + /* Maxim 32610 Externals interrupts */ + DCD UART0_IRQHandler /* 16: 1 UART0 */ + DCD UART1_IRQHandler /* 17: 2 UART1 */ + DCD I2CM0_IRQHandler /* 18: 3 I2C Master 0 */ + DCD I2CS_IRQHandler /* 19: 4 I2C Slave */ + DCD USB_IRQHandler /* 20: 5 USB */ + DCD PMU_IRQHandler /* 21: 6 DMA */ + DCD AFE_IRQHandler /* 22: 7 AFE */ + DCD MAA_IRQHandler /* 23: 8 MAA */ + DCD AES_IRQHandler /* 24: 9 AES */ + DCD SPI0_IRQHandler /* 25:10 SPI0 */ + DCD SPI1_IRQHandler /* 26:11 SPI1 */ + DCD SPI2_IRQHandler /* 27:12 SPI2 */ + DCD TMR0_IRQHandler /* 28:13 Timer32-0 */ + DCD TMR1_IRQHandler /* 29:14 Timer32-1 */ + DCD TMR2_IRQHandler /* 30:15 Timer32-1 */ + DCD TMR3_IRQHandler /* 31:16 Timer32-2 */ + DCD RSVD0_IRQHandler /* 32:17 RSVD */ + DCD RSVD1_IRQHandler /* 33:18 RSVD */ + DCD DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */ + DCD DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */ + DCD DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */ + DCD DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */ + DCD ADC_IRQHandler /* 38:23 ADC */ + DCD FLC_IRQHandler /* 39:24 Flash Controller */ + DCD PWRMAN_IRQHandler /* 40:25 PWRMAN */ + DCD CLKMAN_IRQHandler /* 41:26 CLKMAN */ + DCD RTC0_IRQHandler /* 42:27 RTC INT0 */ + DCD RTC1_IRQHandler /* 43:28 RTC INT1 */ + DCD RTC2_IRQHandler /* 44:29 RTC INT2 */ + DCD RTC3_IRQHandler /* 45:30 RTC INT3 */ + DCD WDT0_IRQHandler /* 46:31 WATCHDOG0 */ + DCD WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */ + DCD WDT1_IRQHandler /* 48:33 WATCHDOG1 */ + DCD WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */ + DCD GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */ + DCD GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */ + DCD GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */ + DCD GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */ + DCD GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */ + DCD GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */ + DCD GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */ + DCD GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */ + DCD TMR16_0_IRQHandler /* 58:43 Timer16-s0 */ + DCD TMR16_1_IRQHandler /* 59:44 Timer16-s1 */ + DCD TMR16_2_IRQHandler /* 60:45 Timer16-s2 */ + DCD TMR16_3_IRQHandler /* 61:46 Timer16-s3 */ + DCD I2CM1_IRQHandler /* 62:47 I2C Master 1 */ +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B NMI_Handler + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Handler + ENDP + +DefaultIRQ_Handler PROC + EXPORT DefaultIRQ_Handler [WEAK] + B DefaultIRQ_Handler + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B DebugMon_Handler + ENDP + +SysTick_IRQHandler PROC + EXPORT SysTick_IRQHandler [WEAK] + B SysTick_IRQHandler + ENDP + +Default_Handler PROC + + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT I2CM0_IRQHandler [WEAK] + EXPORT I2CS_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PMU_IRQHandler [WEAK] + EXPORT AFE_IRQHandler [WEAK] + EXPORT MAA_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT RSVD0_IRQHandler [WEAK] + EXPORT RSVD1_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT DAC1_IRQHandler [WEAK] + EXPORT DAC2_IRQHandler [WEAK] + EXPORT DAC3_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT FLC_IRQHandler [WEAK] + EXPORT PWRMAN_IRQHandler [WEAK] + EXPORT CLKMAN_IRQHandler [WEAK] + EXPORT RTC0_IRQHandler [WEAK] + EXPORT RTC1_IRQHandler [WEAK] + EXPORT RTC2_IRQHandler [WEAK] + EXPORT RTC3_IRQHandler [WEAK] + EXPORT WDT0_IRQHandler [WEAK] + EXPORT WDT0_P_IRQHandler [WEAK] + EXPORT WDT1_IRQHandler [WEAK] + EXPORT WDT1_P_IRQHandler [WEAK] + EXPORT GPIO_P0_IRQHandler [WEAK] + EXPORT GPIO_P1_IRQHandler [WEAK] + EXPORT GPIO_P2_IRQHandler [WEAK] + EXPORT GPIO_P3_IRQHandler [WEAK] + EXPORT GPIO_P4_IRQHandler [WEAK] + EXPORT GPIO_P5_IRQHandler [WEAK] + EXPORT GPIO_P6_IRQHandler [WEAK] + EXPORT GPIO_P7_IRQHandler [WEAK] + EXPORT TMR16_0_IRQHandler [WEAK] + EXPORT TMR16_1_IRQHandler [WEAK] + EXPORT TMR16_2_IRQHandler [WEAK] + EXPORT TMR16_3_IRQHandler [WEAK] + EXPORT I2CM1_IRQHandler [WEAK] + +UART0_IRQHandler +UART1_IRQHandler +I2CM0_IRQHandler +I2CS_IRQHandler +USB_IRQHandler +PMU_IRQHandler +AFE_IRQHandler +MAA_IRQHandler +AES_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +RSVD0_IRQHandler +RSVD1_IRQHandler +DAC0_IRQHandler +DAC1_IRQHandler +DAC2_IRQHandler +DAC3_IRQHandler +ADC_IRQHandler +FLC_IRQHandler +PWRMAN_IRQHandler +CLKMAN_IRQHandler +RTC0_IRQHandler +RTC1_IRQHandler +RTC2_IRQHandler +RTC3_IRQHandler +WDT0_IRQHandler +WDT0_P_IRQHandler +WDT1_IRQHandler +WDT1_P_IRQHandler +GPIO_P0_IRQHandler +GPIO_P1_IRQHandler +GPIO_P2_IRQHandler +GPIO_P3_IRQHandler +GPIO_P4_IRQHandler +GPIO_P5_IRQHandler +GPIO_P6_IRQHandler +GPIO_P7_IRQHandler +TMR16_0_IRQHandler +TMR16_1_IRQHandler +TMR16_2_IRQHandler +TMR16_3_IRQHandler +I2CM1_IRQHandler + + B . + ENDP + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..90d1391ba3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,57 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/max32610.ld b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/max32610.ld new file mode 100644 index 0000000000..be14fd10a7 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/max32610.ld @@ -0,0 +1,182 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +/****************************************************************************** + * + * Linker configuration file, default ARM Cortex M3 produced by Maxim Integrated Inc. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 /* start from 0x0, fullsize flash, 256k */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* full-size SRAM, 32k */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/startup_max32610.S b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/startup_max32610.S new file mode 100644 index 0000000000..cda4da904b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/startup_max32610.S @@ -0,0 +1,262 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + + .syntax unified + .arch armv7-m + +/* Memory Model + The HEAP starts at the end of the DATA section and grows upward. + + The STACK starts at the end of the RAM and grows downward. + + The HEAP and stack STACK are only checked at compile time: + (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE + + This is just a check for the bare minimum for the Heap+Stack area before + aborting compilation, it is not the run time limit: + Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 + */ + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000C00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* Externals interrupts */ + .long UART0_IRQHandler /* 16: 1 UART0 */ + .long UART1_IRQHandler /* 17: 2 UART1 */ + .long I2CM0_IRQHandler /* 18: 3 I2C Master 0 */ + .long I2CS_IRQHandler /* 19: 4 I2C Slave */ + .long USB_IRQHandler /* 20: 5 USB */ + .long PMU_IRQHandler /* 21: 6 DMA */ + .long AFE_IRQHandler /* 22: 7 AFE */ + .long MAA_IRQHandler /* 23: 8 MAA */ + .long AES_IRQHandler /* 24: 9 AES */ + .long SPI0_IRQHandler /* 25:10 SPI0 */ + .long SPI1_IRQHandler /* 26:11 SPI1 */ + .long SPI2_IRQHandler /* 27:12 SPI2 */ + .long TMR0_IRQHandler /* 28:13 Timer32-0 */ + .long TMR1_IRQHandler /* 29:14 Timer32-1 */ + .long TMR2_IRQHandler /* 30:15 Timer32-1 */ + .long TMR3_IRQHandler /* 31:16 Timer32-2 */ + .long RSVD0_IRQHandler /* 32:17 RSVD */ + .long RSVD1_IRQHandler /* 33:18 RSVD */ + .long DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */ + .long DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */ + .long DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */ + .long DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */ + .long ADC_IRQHandler /* 38:23 ADC */ + .long FLC_IRQHandler /* 39:24 Flash Controller */ + .long PWRMAN_IRQHandler /* 40:25 PWRMAN */ + .long CLKMAN_IRQHandler /* 41:26 CLKMAN */ + .long RTC0_IRQHandler /* 42:27 RTC INT0 */ + .long RTC1_IRQHandler /* 43:28 RTC INT1 */ + .long RTC2_IRQHandler /* 44:29 RTC INT2 */ + .long RTC3_IRQHandler /* 45:30 RTC INT3 */ + .long WDT0_IRQHandler /* 46:31 WATCHDOG0 */ + .long WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */ + .long WDT1_IRQHandler /* 48:33 WATCHDOG1 */ + .long WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */ + .long GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */ + .long GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */ + .long GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */ + .long GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */ + .long GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */ + .long GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */ + .long GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */ + .long GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */ + .long TMR16_0_IRQHandler /* 58:43 Timer16-s0 */ + .long TMR16_1_IRQHandler /* 59:44 Timer16-s1 */ + .long TMR16_2_IRQHandler /* 60:45 Timer16-s2 */ + .long TMR16_3_IRQHandler /* 61:46 Timer16-s3 */ + .long I2CM1_IRQHandler /* 62:47 I2C Master 1 */ + + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.Lflash_to_ram_loop: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .Lflash_to_ram_loop + +.Lflash_to_ram_loop_end: + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_default_handler UART0_IRQHandler /* 16: 1 UART0 */ + def_irq_default_handler UART1_IRQHandler /* 17: 2 UART1 */ + def_irq_default_handler I2CM0_IRQHandler /* 18: 3 I2C Master 0 */ + def_irq_default_handler I2CS_IRQHandler /* 19: 4 I2C Slave */ + def_irq_default_handler USB_IRQHandler /* 20: 5 USB */ + def_irq_default_handler PMU_IRQHandler /* 21: 6 DMA */ + def_irq_default_handler AFE_IRQHandler /* 22: 7 AFE */ + def_irq_default_handler MAA_IRQHandler /* 23: 8 MAA */ + def_irq_default_handler AES_IRQHandler /* 24: 9 AES */ + def_irq_default_handler SPI0_IRQHandler /* 25:10 SPI0 */ + def_irq_default_handler SPI1_IRQHandler /* 26:11 SPI1 */ + def_irq_default_handler SPI2_IRQHandler /* 27:12 SPI2 */ + def_irq_default_handler TMR0_IRQHandler /* 28:13 Timer32-0 */ + def_irq_default_handler TMR1_IRQHandler /* 29:14 Timer32-1 */ + def_irq_default_handler TMR2_IRQHandler /* 30:15 Timer32-1 */ + def_irq_default_handler TMR3_IRQHandler /* 31:16 Timer32-2 */ + def_irq_default_handler RSVD0_IRQHandler /* 32:17 RSVD */ + def_irq_default_handler RSVD1_IRQHandler /* 33:18 RSVD */ + def_irq_default_handler DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */ + def_irq_default_handler DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */ + def_irq_default_handler DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */ + def_irq_default_handler DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */ + def_irq_default_handler ADC_IRQHandler /* 38:23 ADC */ + def_irq_default_handler FLC_IRQHandler /* 39:24 Flash Controller */ + def_irq_default_handler PWRMAN_IRQHandler /* 40:25 PWRMAN */ + def_irq_default_handler CLKMAN_IRQHandler /* 41:26 CLKMAN */ + def_irq_default_handler RTC0_IRQHandler /* 42:27 RTC INT0 */ + def_irq_default_handler RTC1_IRQHandler /* 43:28 RTC INT1 */ + def_irq_default_handler RTC2_IRQHandler /* 44:29 RTC INT2 */ + def_irq_default_handler RTC3_IRQHandler /* 45:30 RTC INT3 */ + def_irq_default_handler WDT0_IRQHandler /* 46:31 WATCHDOG0 */ + def_irq_default_handler WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */ + def_irq_default_handler WDT1_IRQHandler /* 48:33 WATCHDOG1 */ + def_irq_default_handler WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */ + def_irq_default_handler GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */ + def_irq_default_handler GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */ + def_irq_default_handler GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */ + def_irq_default_handler GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */ + def_irq_default_handler GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */ + def_irq_default_handler GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */ + def_irq_default_handler GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */ + def_irq_default_handler GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */ + def_irq_default_handler TMR16_0_IRQHandler /* 58:43 Timer16-s0 */ + def_irq_default_handler TMR16_1_IRQHandler /* 59:44 Timer16-s1 */ + def_irq_default_handler TMR16_2_IRQHandler /* 60:45 Timer16-s2 */ + def_irq_default_handler TMR16_3_IRQHandler /* 61:46 Timer16-s3 */ + def_irq_default_handler I2CM1_IRQHandler /* 62:47 I2C Master 1 */ + + .end diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/MAX32610.icf b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/MAX32610.icf new file mode 100644 index 0000000000..2b90dc973d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/MAX32610.icf @@ -0,0 +1,29 @@ +/* [ROM] */ +define symbol __intvec_start__ = 0x0; +define symbol __region_ROM_start__ = 0x0; +define symbol __region_ROM_end__ = 0x0003FFFF; + +/* [RAM] Vector table dynamic copy: 79 vectors * 4 bytes = 316 bytes (0x13C) */ +define symbol __NVIC_start__ = 0x00000000; +define symbol __NVIC_end__ = 0x00000140; /* to be aligned on 8 bytes */ +define symbol __region_RAM_start__ = 0x20000000; +define symbol __region_RAM_end__ = 0x20007FFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; + +/* Stack and Heap */ +define symbol __size_cstack__ = 0x800; +define symbol __size_heap__ = 0x800; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/startup_MAX32610.s b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/startup_MAX32610.s new file mode 100644 index 0000000000..518756c0b4 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/startup_MAX32610.s @@ -0,0 +1,383 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table DCD sfe(CSTACK) /* Top of Stack */ + DCD Reset_Handler /* Reset Handler */ + DCD NMI_Handler /* NMI Handler */ + DCD HardFault_Handler /* Hard Fault Handler */ + DCD DefaultIRQ_Handler /* MPU Fault Handler */ + DCD DefaultIRQ_Handler /* Bus Fault Handler */ + DCD DefaultIRQ_Handler /* Usage Fault Handler */ + DCD 0 /* Reserved */ + DCD 0 /* Reserved */ + DCD 0 /* Reserved */ + DCD 0 /* Reserved */ + DCD DefaultIRQ_Handler /* SVCall Handler */ + DCD DebugMon_Handler /* Debug Monitor Handler */ + DCD 0 /* Reserved */ + DCD DefaultIRQ_Handler /* PendSV Handler */ + DCD SysTick_IRQHandler /* SysTick Handler */ + + /* Maxim 32610 Externals interrupts */ + DCD UART0_IRQHandler /* 16: 1 UART0 */ + DCD UART1_IRQHandler /* 17: 2 UART1 */ + DCD I2CM0_IRQHandler /* 18: 3 I2C Master 0 */ + DCD I2CS_IRQHandler /* 19: 4 I2C Slave */ + DCD USB_IRQHandler /* 20: 5 USB */ + DCD PMU_IRQHandler /* 21: 6 DMA */ + DCD AFE_IRQHandler /* 22: 7 AFE */ + DCD MAA_IRQHandler /* 23: 8 MAA */ + DCD AES_IRQHandler /* 24: 9 AES */ + DCD SPI0_IRQHandler /* 25:10 SPI0 */ + DCD SPI1_IRQHandler /* 26:11 SPI1 */ + DCD SPI2_IRQHandler /* 27:12 SPI2 */ + DCD TMR0_IRQHandler /* 28:13 Timer32-0 */ + DCD TMR1_IRQHandler /* 29:14 Timer32-1 */ + DCD TMR2_IRQHandler /* 30:15 Timer32-1 */ + DCD TMR3_IRQHandler /* 31:16 Timer32-2 */ + DCD RSVD0_IRQHandler /* 32:17 RSVD */ + DCD RSVD1_IRQHandler /* 33:18 RSVD */ + DCD DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */ + DCD DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */ + DCD DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */ + DCD DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */ + DCD ADC_IRQHandler /* 38:23 ADC */ + DCD FLC_IRQHandler /* 39:24 Flash Controller */ + DCD PWRMAN_IRQHandler /* 40:25 PWRMAN */ + DCD CLKMAN_IRQHandler /* 41:26 CLKMAN */ + DCD RTC0_IRQHandler /* 42:27 RTC INT0 */ + DCD RTC1_IRQHandler /* 43:28 RTC INT1 */ + DCD RTC2_IRQHandler /* 44:29 RTC INT2 */ + DCD RTC3_IRQHandler /* 45:30 RTC INT3 */ + DCD WDT0_IRQHandler /* 46:31 WATCHDOG0 */ + DCD WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */ + DCD WDT1_IRQHandler /* 48:33 WATCHDOG1 */ + DCD WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */ + DCD GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */ + DCD GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */ + DCD GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */ + DCD GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */ + DCD GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */ + DCD GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */ + DCD GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */ + DCD GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */ + DCD TMR16_0_IRQHandler /* 58:43 Timer16-s0 */ + DCD TMR16_1_IRQHandler /* 59:44 Timer16-s1 */ + DCD TMR16_2_IRQHandler /* 60:45 Timer16-s2 */ + DCD TMR16_3_IRQHandler /* 61:46 Timer16-s3 */ + DCD I2CM1_IRQHandler /* 62:47 I2C Master 1 */ + + THUMB +; Dummy Exception Handlers (infinite loops which can be modified) + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK DefaultIRQ_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DefaultIRQ_Handler + B DefaultIRQ_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK SysTick_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_IRQHandler + B SysTick_IRQHandler + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_IRQHandler + B UART0_IRQHandler + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_IRQHandler + B UART1_IRQHandler + + PUBWEAK I2CM0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2CM0_IRQHandler + B I2CM0_IRQHandler + + PUBWEAK I2CS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2CS_IRQHandler + B I2CS_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PMU_IRQHandler + B PMU_IRQHandler + + PUBWEAK AFE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AFE_IRQHandler + B AFE_IRQHandler + + PUBWEAK MAA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MAA_IRQHandler + B MAA_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + PUBWEAK RSVD0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RSVD0_IRQHandler + B RSVD0_IRQHandler + + PUBWEAK RSVD1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RSVD1_IRQHandler + B RSVD1_IRQHandler + + PUBWEAK DAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC0_IRQHandler + B DAC0_IRQHandler + + PUBWEAK DAC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC1_IRQHandler + B DAC1_IRQHandler + + PUBWEAK DAC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC2_IRQHandler + B DAC2_IRQHandler + + PUBWEAK DAC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC3_IRQHandler + B DAC3_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK FLC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLC_IRQHandler + B FLC_IRQHandler + + PUBWEAK PWRMAN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWRMAN_IRQHandler + B PWRMAN_IRQHandler + + PUBWEAK CLKMAN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CLKMAN_IRQHandler + B CLKMAN_IRQHandler + + PUBWEAK RTC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC0_IRQHandler + B RTC0_IRQHandler + + PUBWEAK RTC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC1_IRQHandler + B RTC1_IRQHandler + + PUBWEAK RTC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC2_IRQHandler + B RTC2_IRQHandler + + PUBWEAK RTC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC3_IRQHandler + B RTC3_IRQHandler + + PUBWEAK WDT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT0_IRQHandler + B WDT0_IRQHandler + + PUBWEAK WDT0_P_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT0_P_IRQHandler + B WDT0_P_IRQHandler + + PUBWEAK WDT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT1_IRQHandler + B WDT1_IRQHandler + + PUBWEAK WDT1_P_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT1_P_IRQHandler + B WDT1_P_IRQHandler + + PUBWEAK GPIO_P0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P0_IRQHandler + B GPIO_P0_IRQHandler + + PUBWEAK GPIO_P1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P1_IRQHandler + B GPIO_P1_IRQHandler + + PUBWEAK GPIO_P2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P2_IRQHandler + B GPIO_P2_IRQHandler + + PUBWEAK GPIO_P3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P3_IRQHandler + B GPIO_P3_IRQHandler + + PUBWEAK GPIO_P4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P4_IRQHandler + B GPIO_P4_IRQHandler + + PUBWEAK GPIO_P5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P5_IRQHandler + B GPIO_P5_IRQHandler + + PUBWEAK GPIO_P6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P6_IRQHandler + B GPIO_P6_IRQHandler + + PUBWEAK GPIO_P7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P7_IRQHandler + B GPIO_P7_IRQHandler + + PUBWEAK TMR16_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_0_IRQHandler + B TMR16_0_IRQHandler + + PUBWEAK TMR16_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_1_IRQHandler + B TMR16_1_IRQHandler + + PUBWEAK TMR16_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_2_IRQHandler + B TMR16_2_IRQHandler + + PUBWEAK TMR16_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_3_IRQHandler + B TMR16_3_IRQHandler + + PUBWEAK I2CM1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2CM1_IRQHandler + B I2CM1_IRQHandler + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/adc_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/adc_regs.h new file mode 100644 index 0000000000..4e4d5299c2 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/adc_regs.h @@ -0,0 +1,466 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_ADC_REGS_H +#define _MXC_ADC_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file adc_regs.h + * @addtogroup adc ADC + * @{ + */ + +/** + * @brief Defines ADC Modes. + */ +typedef enum { + /** Single Mode Full Rate */ + MXC_E_ADC_MODE_SMPLCNT_FULL_RATE = 0, + /** Single Mode Low Power */ + MXC_E_ADC_MODE_SMPLCNT_LOW_POWER = 1, + /** Continuous Mode Full Rate */ + MXC_E_ADC_MODE_CONTINUOUS_FULL_RATE = 2, + /** Continuous Mode Low Power */ + MXC_E_ADC_MODE_CONTINUOUS_LOW_POWER = 3, + /** Single Mode Full Rate with Scan Enabled */ + MXC_E_ADC_MODE_SMPLCNT_SCAN_FULL_RATE = 8, + /** Single Mode Low Power with Scan Enabled */ + MXC_E_ADC_MODE_SMPLCNT_SCAN_LOW_POWER = 9, + /** Continuous Mode Full Rate with Scan Enabled */ + MXC_E_ADC_MODE_CONTINUOUS_SCAN_FULL_RATE = 10, + /** Continuous Mode Low Power with Scan Enabled */ + MXC_E_ADC_MODE_CONTINUOUS_SCAN_LOW_POWER = 11 +} mxc_adc_mode_t; + +/** + * @brief Defines ADC Range Control. + */ +typedef enum { + /** Bi-polar Operation (-Vref/2 -> Vref/2) */ + MXC_E_ADC_RANGE_HALF = 0, + /** Bi-polar Operation (-Vref -> Vref) */ + MXC_E_ADC_RANGE_FULL +} mxc_adc_range_t; + +/** + * @brief Defines ADC Bipolar operation. + */ +typedef enum { + /** Uni-polar operation (0 -> Vref) */ + MXC_E_ADC_BI_POL_UNIPOLAR = 0, + /** Bi-polar operation see ADC Range Control */ + MXC_E_ADC_BI_POL_BIPOLAR +} mxc_adc_bi_pol_t; + +/** + * @brief Defines Decimation Filter Modes. + */ +typedef enum { + /** Decimation Filter ByPassed */ + MXC_E_ADC_AVG_MODE_FILTER_BYPASS = 0, + /** Output Average Only*/ + MXC_E_ADC_AVG_MODE_FILTER_OUTPUT, + /** Output Average and Raw Data (Test Mode Only) */ + MXC_E_ADC_AVG_MODE_FILTER_OUTPUT_RAW +} mxc_adc_avg_mode_t; + +/** + * @brief Defines ADC StartMode Modes. + */ +typedef enum { + /** StarMode via Software */ + MXC_E_ADC_STRT_MODE_SOFTWARE = 0, + /** StarMode via PulseTrain */ + MXC_E_ADC_STRT_MODE_PULSETRAIN +} mxc_adc_strt_mode_t; + +/** + * @brief Defines Mux Channel Select for the Positive Input to the ADC. + */ +typedef enum { + /** Single Mode Input AIN0+; Diff Mode AIN0+/AIN8- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN0 = 0, + /** Single Mode Input AIN1+; Diff Mode AIN1+/AIN9- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN1 = 1, + /** Single Mode Input AIN2+; Diff Mode AIN2+/AIN10- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN2 = 2, + /** Single Mode Input AIN3+; Diff Mode AIN3+/AIN11- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN3 = 3, + /** Single Mode Input AIN4+; Diff Mode AIN4+/AIN12- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN4 = 4, + /** Single Mode Input AIN5+; Diff Mode AIN5+/AIN13- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN5 = 5, + /** Single Mode Input AIN6+; Diff Mode AIN6+/AIN14- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN6 = 6, + /** Single Mode Input AIN7+; Diff Mode AIN7+/AIN15- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN7 = 7, + /** Single Mode Input AIN8+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN8 = 8, + /** Single Mode Input AIN9+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN9 = 9, + /** Single Mode Input AIN10+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN10 = 10, + /** Single Mode Input AIN11+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN11 = 11, + /** Single Mode Input AIN12+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN12 = 12, + /** Single Mode Input AIN13+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN13 = 13, + /** Single Mode Input AIN14+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN14 = 14, + /** Single Mode Input AIN15+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN15 = 15, + /** Positive Input VSSADC */ + MXC_E_ADC_PGA_MUX_CH_SEL_VSSADC = 16, + /** Positive Input TMON_R */ + MXC_E_ADC_PGA_MUX_CH_SEL_TMON_R = 17, + /** Positive Input VDDA/4 */ + MXC_E_ADC_PGA_MUX_CH_SEL_VDDA4 = 18, + /** Positive Input PWRMAN_TST */ + MXC_E_ADC_PGA_MUX_CH_SEL_PWRMON_TST = 19, + /** Positive Input Ain0Div */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN0DIV = 20, + /** Positive Input OpAmp OUTA */ + MXC_E_ADC_PGA_MUX_CH_SEL_OUTA = 32, + /** Positive Input OpAmp OUTB */ + MXC_E_ADC_PGA_MUX_CH_SEL_OUTB = 33, + /** Positive Input OpAmp OUTC */ + MXC_E_ADC_PGA_MUX_CH_SEL_OUTC = 34, + /** Positive Input OpAmp OUTD */ + MXC_E_ADC_PGA_MUX_CH_SEL_OUTD = 35, + /** Positive INA+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_INAPLUS = 36, + /** Positive SNO_or */ + MXC_E_ADC_PGA_MUX_CH_SEL_SNO_OR = 37, + /** Positive SCM_or */ + MXC_E_ADC_PGA_MUX_CH_SEL_SCM_OR = 38, + /** Positive TPROBE_sense */ + MXC_E_ADC_PGA_MUX_CH_SEL_TPROBE_SENSE = 48, + /** Positive VREFDAC */ + MXC_E_ADC_PGA_MUX_CH_SEL_VREFDAC = 49, + /** Positive VREFADJ */ + MXC_E_ADC_PGA_MUX_CH_SEL_VREFADJ = 50, + /** Positive Vdd3xtal */ + MXC_E_ADC_PGA_MUX_CH_SEL_VDD3XTAL = 51 +} mxc_adc_pga_mux_ch_sel_t; + +/** + * @brief Decoded with the MUX Channel Select to enable Differential Mode Input to the ADC. + */ +typedef enum { + /** Differential Mode Disabled */ + MXC_E_ADC_PGA_MUX_DIFF_DISABLE = 0, + /** Differential Mode Enabled */ + MXC_E_ADC_PGA_MUX_DIFF_ENABLE +} mxc_adc_pga_mux_diff_t; + +/** + * @brief Defines the PGA Gain Options. + */ +typedef enum { + /** PGA Gain = 1 */ + MXC_E_ADC_PGA_GAIN_1 = 0, + /** PGA Gain = 2 */ + MXC_E_ADC_PGA_GAIN_2, + /** PGA Gain = 4 */ + MXC_E_ADC_PGA_GAIN_4, + /** PGA Gain = 8 */ + MXC_E_ADC_PGA_GAIN_8, +} mxc_adc_pga_gain_t; + +/** + * @brief Defines the Switch Control Mode. + */ +typedef enum { + /** Switch Control Mode = Software */ + MXC_E_ADC_SPST_SW_CTRL_SOFTWARE = 0, + /** Switch Control Mode = Pulse Train */ + MXC_E_ADC_SPST_SW_CTRL_PULSETRAIN +} mxc_adc_spst_sw_ctrl_t; + +/** + * @brief Defines the number of channels to scan when Scan Mode is enabled. + */ +typedef enum { + /** Number of Channels to Scan = 1 */ + MXC_E_ADC_SCAN_CNT_1 = 0, + /** Number of Channels to Scan = 2 */ + MXC_E_ADC_SCAN_CNT_2, + /** Number of Channels to Scan = 3 */ + MXC_E_ADC_SCAN_CNT_3, + /** Number of Channels to Scan = 4 */ + MXC_E_ADC_SCAN_CNT_4, + /** Number of Channels to Scan = 5 */ + MXC_E_ADC_SCAN_CNT_5, + /** Number of Channels to Scan = 6 */ + MXC_E_ADC_SCAN_CNT_6, + /** Number of Channels to Scan = 7 */ + MXC_E_ADC_SCAN_CNT_7, + /** Number of Channels to Scan = 8 */ + MXC_E_ADC_SCAN_CNT_8, +} mxc_adc_scan_cnt_t; + +/* Offset Register Description + ====== =================================================== */ +typedef struct { + __IO uint32_t ctrl0; /* 0x0000 ADC Control Register 0 */ + __IO uint32_t pga_ctrl; /* 0x0004 PGA Control Register */ + __IO uint32_t tg_ctrl0; /* 0x0008 ADC Timing Generator Control 0 */ + __IO uint32_t tg_ctrl1; /* 0x000C ADC Timing Generator Control 1 */ + __IO uint32_t limit; /* 0x0010 ADC Limit Settings */ + __IO uint32_t intr; /* 0x0014 ADC Interrupt Flags and Enable/Disable Controls */ + __IO uint32_t out; /* 0x0018 ADC Output Register */ +} mxc_adc_regs_t; + +/* Offset Register Description + ====== =================================================== */ +typedef struct { + __IO uint32_t ctrl1; /* 0x0000 ADC Control Register 1 */ + __IO uint32_t scan1; /* 0x0004 ADC Auto-Scan Settings 1 */ + __IO uint32_t scan2; /* 0x0008 ADC Auto-Scan Settings 2 */ + __IO uint32_t ro_cal0; /* 0x000C ADC Ring Osc Calibration 0 */ + __IO uint32_t ro_cal1; /* 0x0010 ADC Ring Osc Calibration 1 */ +} mxc_adccfg_regs_t; + +typedef struct { + __IO uint16_t data; /* 0x0000 Read to pull sample data from ADC FIFO */ +} mxc_adc_fifo_regs_t; + +/* + Register offsets for module ADC, ADCCFG, ADC_FIFO +*/ +#define MXC_R_ADC_OFFS_CTRL0 ((uint32_t)0x00000000UL) +#define MXC_R_ADC_OFFS_PGA_CTRL ((uint32_t)0x00000004UL) +#define MXC_R_ADC_OFFS_TG_CTRL0 ((uint32_t)0x00000008UL) +#define MXC_R_ADC_OFFS_TG_CTRL1 ((uint32_t)0x0000000CUL) +#define MXC_R_ADC_OFFS_LIMIT ((uint32_t)0x00000010UL) +#define MXC_R_ADC_OFFS_INTR ((uint32_t)0x00000014UL) +#define MXC_R_ADC_OFFS_OUT ((uint32_t)0x00000018UL) + +#define MXC_R_ADCCFG_OFFS_CTRL1 ((uint32_t)0x00000000UL) +#define MXC_R_ADCCFG_OFFS_SCAN1 ((uint32_t)0x00000004UL) +#define MXC_R_ADCCFG_OFFS_SCAN2 ((uint32_t)0x00000008UL) +#define MXC_R_ADCCFG_OFFS_RO_CAL0 ((uint32_t)0x0000000CUL) +#define MXC_R_ADCCFG_OFFS_RO_CAL1 ((uint32_t)0x00000010UL) +#define MXC_R_ADC_FIFO_OFFS_DATA ((uint32_t)0x00000000UL) + +/* + Field positions and masks for module ADC. +*/ +#define MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS 0 +#define MXC_F_ADC_CTRL0_ADC_WAKE_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS)) +#define MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS 5 +#define MXC_F_ADC_CTRL0_ADC_STRT_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS)) +#define MXC_F_ADC_CTRL0_ADC_RANGE_POS 6 +#define MXC_F_ADC_CTRL0_ADC_RANGE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_RANGE_POS)) +#define MXC_F_ADC_CTRL0_ADC_BI_POL_POS 7 +#define MXC_F_ADC_CTRL0_ADC_BI_POL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_BI_POL_POS)) +#define MXC_F_ADC_CTRL0_ADC_DV_REG_POS 8 +#define MXC_F_ADC_CTRL0_ADC_DV_REG ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_REG_POS)) +#define MXC_F_ADC_CTRL0_ADC_DV_POS 9 +#define MXC_F_ADC_CTRL0_ADC_DV ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_POS)) +#define MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS 10 +#define MXC_F_ADC_CTRL0_ADC_LMT_DMODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS)) +#define MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS 11 +#define MXC_F_ADC_CTRL0_ADC_SMP_EXT ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS)) +#define MXC_F_ADC_CTRL0_ADC_CLK_EN_POS 12 +#define MXC_F_ADC_CTRL0_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_CLK_EN_POS)) +#define MXC_F_ADC_CTRL0_CPU_ADC_RST_POS 13 +#define MXC_F_ADC_CTRL0_CPU_ADC_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_RST_POS)) +#define MXC_F_ADC_CTRL0_CPU_ADC_START_POS 14 +#define MXC_F_ADC_CTRL0_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_START_POS)) +#define MXC_F_ADC_CTRL0_CPU_ADC_EN_POS 15 +#define MXC_F_ADC_CTRL0_CPU_ADC_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_EN_POS)) +#define MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS 18 +#define MXC_F_ADC_CTRL0_ADC_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS)) +#define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS 19 +#define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS)) +#define MXC_F_ADC_CTRL0_AVG_MODE_POS 20 +#define MXC_F_ADC_CTRL0_AVG_MODE ((uint32_t)(0x00000003UL << MXC_F_ADC_CTRL0_AVG_MODE_POS)) +#define MXC_F_ADC_CTRL0_CPU_DAC_START_POS 22 +#define MXC_F_ADC_CTRL0_CPU_DAC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_DAC_START_POS)) +#define MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS 24 +#define MXC_F_ADC_CTRL0_ADC_CLK_MODE ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS)) +#define MXC_F_ADC_CTRL0_ADC_MODE_POS 28 +#define MXC_F_ADC_CTRL0_ADC_MODE ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_MODE_POS)) + +#define MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS 0 +#define MXC_F_ADC_PGA_CTRL_PGA_GAIN ((uint32_t)(0x00000003UL << MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS)) +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS 2 +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS)) +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS 3 +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS)) +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS 4 +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS)) +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS 5 +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS)) +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS 6 +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS)) +#define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS 8 +#define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT ((uint32_t)(0x0000001FUL << MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS)) +#define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS 13 +#define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS)) +#define MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS 14 +#define MXC_F_ADC_PGA_CTRL_MUX_DIFF ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS)) +#define MXC_F_ADC_PGA_CTRL_MUX_MODE_POS 15 +#define MXC_F_ADC_PGA_CTRL_MUX_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_MODE_POS)) +#define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS 20 +#define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS)) +#define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS 24 +#define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL ((uint32_t)(0x0000003FUL << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS)) + +#define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS 0 +#define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS)) +#define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS 16 +#define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS)) + +#define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS 0 +#define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS)) +#define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS 4 +#define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS)) +#define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS 8 +#define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS)) +#define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS 12 +#define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS)) +#define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS 16 +#define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS)) + +#define MXC_F_ADC_LIMIT_LO_LIMIT_POS 0 +#define MXC_F_ADC_LIMIT_LO_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_LO_LIMIT_POS)) +#define MXC_F_ADC_LIMIT_HI_LIMIT_POS 16 +#define MXC_F_ADC_LIMIT_HI_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_HI_LIMIT_POS)) + +#define MXC_F_ADC_INTR_FIFO_AF_POS 6 +#define MXC_F_ADC_INTR_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_AF_POS)) +#define MXC_F_ADC_INTR_OUT_RNG_IF_POS 7 +#define MXC_F_ADC_INTR_OUT_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IF_POS)) +#define MXC_F_ADC_INTR_HI_RNG_IF_POS 8 +#define MXC_F_ADC_INTR_HI_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IF_POS)) +#define MXC_F_ADC_INTR_LO_RNG_IF_POS 9 +#define MXC_F_ADC_INTR_LO_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IF_POS)) +#define MXC_F_ADC_INTR_DONE_IF_POS 10 +#define MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IF_POS)) +#define MXC_F_ADC_INTR_FIFO_UF_IF_POS 11 +#define MXC_F_ADC_INTR_FIFO_UF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IF_POS)) +#define MXC_F_ADC_INTR_FIFO_OF_IF_POS 12 +#define MXC_F_ADC_INTR_FIFO_OF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IF_POS)) +#define MXC_F_ADC_INTR_FIFO_3Q_IF_POS 13 +#define MXC_F_ADC_INTR_FIFO_3Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IF_POS)) +#define MXC_F_ADC_INTR_FIFO_2Q_IF_POS 14 +#define MXC_F_ADC_INTR_FIFO_2Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IF_POS)) +#define MXC_F_ADC_INTR_FIFO_1Q_IF_POS 15 +#define MXC_F_ADC_INTR_FIFO_1Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IF_POS)) +#define MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS 16 +#define MXC_F_ADC_INTR_SPST0_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS)) +#define MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS 17 +#define MXC_F_ADC_INTR_SPST1_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS)) +#define MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS 18 +#define MXC_F_ADC_INTR_SPST2_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS)) +#define MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS 19 +#define MXC_F_ADC_INTR_SPST3_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS)) +#define MXC_F_ADC_INTR_OUT_RNG_IE_POS 23 +#define MXC_F_ADC_INTR_OUT_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IE_POS)) +#define MXC_F_ADC_INTR_HI_RNG_IE_POS 24 +#define MXC_F_ADC_INTR_HI_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IE_POS)) +#define MXC_F_ADC_INTR_LO_RNG_IE_POS 25 +#define MXC_F_ADC_INTR_LO_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IE_POS)) +#define MXC_F_ADC_INTR_DONE_IE_POS 26 +#define MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IE_POS)) +#define MXC_F_ADC_INTR_FIFO_UF_IE_POS 27 +#define MXC_F_ADC_INTR_FIFO_UF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IE_POS)) +#define MXC_F_ADC_INTR_FIFO_OF_IE_POS 28 +#define MXC_F_ADC_INTR_FIFO_OF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IE_POS)) +#define MXC_F_ADC_INTR_FIFO_3Q_IE_POS 29 +#define MXC_F_ADC_INTR_FIFO_3Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IE_POS)) +#define MXC_F_ADC_INTR_FIFO_2Q_IE_POS 30 +#define MXC_F_ADC_INTR_FIFO_2Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IE_POS)) +#define MXC_F_ADC_INTR_FIFO_1Q_IE_POS 31 +#define MXC_F_ADC_INTR_FIFO_1Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IE_POS)) + +#define MXC_F_ADC_OUT_DATA_REG_POS 0 +#define MXC_F_ADC_OUT_DATA_REG ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_OUT_DATA_REG_POS)) + +#define MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS 16 +#define MXC_F_ADC_CTRL1_ADC_SCAN_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS)) + +#define MXC_F_ADC_SCAN1_ADC_SCAN0_POS 0 +#define MXC_F_ADC_SCAN1_ADC_SCAN0 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN0_POS)) +#define MXC_F_ADC_SCAN1_ADC_SCAN1_POS 8 +#define MXC_F_ADC_SCAN1_ADC_SCAN1 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN1_POS)) +#define MXC_F_ADC_SCAN1_ADC_SCAN2_POS 16 +#define MXC_F_ADC_SCAN1_ADC_SCAN2 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN2_POS)) +#define MXC_F_ADC_SCAN1_ADC_SCAN3_POS 24 +#define MXC_F_ADC_SCAN1_ADC_SCAN3 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN3_POS)) + +#define MXC_F_ADC_SCAN2_ADC_SCAN4_POS 0 +#define MXC_F_ADC_SCAN2_ADC_SCAN4 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN4_POS)) +#define MXC_F_ADC_SCAN2_ADC_SCAN5_POS 8 +#define MXC_F_ADC_SCAN2_ADC_SCAN5 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN5_POS)) +#define MXC_F_ADC_SCAN2_ADC_SCAN6_POS 16 +#define MXC_F_ADC_SCAN2_ADC_SCAN6 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN6_POS)) +#define MXC_F_ADC_SCAN2_ADC_SCAN7_POS 24 +#define MXC_F_ADC_SCAN2_ADC_SCAN7 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN7_POS)) + +#define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0 +#define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS)) +#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1 +#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS)) +#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2 +#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS)) +#define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8 +#define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS)) +#define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23 +#define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS)) + +#define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0 +#define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS)) +#define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10 +#define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS)) +#define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20 +#define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS)) + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _MXC_ADC_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/aes_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/aes_regs.h new file mode 100644 index 0000000000..cf9995be40 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/aes_regs.h @@ -0,0 +1,159 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_AES_REGS_H_ +#define _MXC_AES_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file aes_regs.h + * @addtogroup aes AES + * @{ + */ + +/** + * @brief Settings for AES_CTRL.CRYPT_MODE + */ +typedef enum { + MXC_E_AES_CTRL_ENCRYPT_MODE = 0, + MXC_E_AES_CTRL_DECRYPT_MODE = 1 +} mxc_aes_ctrl_crypt_mode_t; + +/** + * @brief Settings for AES_CTRL.EXP_KEY_MODE + */ +typedef enum { + MXC_E_AES_CTRL_CALC_NEW_EXP_KEY = 0, + MXC_E_AES_CTRL_USE_LAST_EXP_KEY = 1 +} mxc_aes_ctrl_exp_key_mode_t; + +/** + * @brief Settings for AES_CTRL.KEY_SIZE + */ +typedef enum { + MXC_E_AES_CTRL_KEY_SIZE_128 = 0, + MXC_E_AES_CTRL_KEY_SIZE_192 = 1, + MXC_E_AES_CTRL_KEY_SIZE_256 = 2 +} mxc_aes_ctrl_key_size_t; + +/* Offset Register Description + ====== =========================================================== */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 AES Control and Status */ + __I uint32_t rsv004; /* 0x0004 */ + __IO uint32_t erase_all; /* 0x0008 Write to Trigger AES Memory Erase */ +} mxc_aes_regs_t; + +/* Offset Register Description + ====== =========================================================== */ +typedef struct { + __IO uint32_t inp[4]; /* 0x0000 AES Input 0..3 */ + __IO uint32_t key[8]; /* 0x0010 AES Key 0..7 */ + __IO uint32_t out[4]; /* 0x0030 AES Output 0..3 */ + __IO uint32_t expkey[8]; /* 0x0040 AES Expanded Key Data 0..7 */ +} mxc_aes_mem_regs_t; + +/* + Register offsets for module AES. +*/ +#define MXC_R_AES_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_AES_OFFS_ERASE_ALL ((uint32_t)0x00000008UL) +#define MXC_R_AES_MEM_OFFS_INP0 ((uint32_t)0x00000000UL) +#define MXC_R_AES_MEM_OFFS_INP1 ((uint32_t)0x00000004UL) +#define MXC_R_AES_MEM_OFFS_INP2 ((uint32_t)0x00000008UL) +#define MXC_R_AES_MEM_OFFS_INP3 ((uint32_t)0x0000000CUL) +#define MXC_R_AES_MEM_OFFS_KEY0 ((uint32_t)0x00000010UL) +#define MXC_R_AES_MEM_OFFS_KEY1 ((uint32_t)0x00000014UL) +#define MXC_R_AES_MEM_OFFS_KEY2 ((uint32_t)0x00000018UL) +#define MXC_R_AES_MEM_OFFS_KEY3 ((uint32_t)0x0000001CUL) +#define MXC_R_AES_MEM_OFFS_KEY4 ((uint32_t)0x00000020UL) +#define MXC_R_AES_MEM_OFFS_KEY5 ((uint32_t)0x00000024UL) +#define MXC_R_AES_MEM_OFFS_KEY6 ((uint32_t)0x00000028UL) +#define MXC_R_AES_MEM_OFFS_KEY7 ((uint32_t)0x0000002CUL) +#define MXC_R_AES_MEM_OFFS_OUT0 ((uint32_t)0x00000030UL) +#define MXC_R_AES_MEM_OFFS_OUT1 ((uint32_t)0x00000034UL) +#define MXC_R_AES_MEM_OFFS_OUT2 ((uint32_t)0x00000038UL) +#define MXC_R_AES_MEM_OFFS_OUT3 ((uint32_t)0x0000003CUL) +#define MXC_R_AES_MEM_OFFS_EXPKEY0 ((uint32_t)0x00000040UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY1 ((uint32_t)0x00000044UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY2 ((uint32_t)0x00000048UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY3 ((uint32_t)0x0000004CUL) +#define MXC_R_AES_MEM_OFFS_EXPKEY4 ((uint32_t)0x00000050UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY5 ((uint32_t)0x00000054UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY6 ((uint32_t)0x00000058UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY7 ((uint32_t)0x0000005CUL) + +#define MXC_F_AES_CTRL_START_POS 0 +#define MXC_F_AES_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS)) +#define MXC_F_AES_CTRL_CRYPT_MODE_POS 1 +#define MXC_F_AES_CTRL_CRYPT_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS)) +#define MXC_F_AES_CTRL_EXP_KEY_MODE_POS 2 +#define MXC_F_AES_CTRL_EXP_KEY_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) +#define MXC_F_AES_CTRL_KEY_SIZE_POS 3 +#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) +#define MXC_F_AES_CTRL_INTEN_POS 5 +#define MXC_F_AES_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS)) +#define MXC_F_AES_CTRL_INTFL_POS 6 +#define MXC_F_AES_CTRL_INTFL ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS)) + +#define MXC_V_AES_CTRL_ENCRYPT_MODE 0 +#define MXC_V_AES_CTRL_DECRYPT_MODE 1 +#define MXC_S_AES_CTRL_ENCRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) +#define MXC_S_AES_CTRL_DECRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) + +#define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY 0 +#define MXC_V_AES_CTRL_USE_LAST_EXP_KEY 1 +#define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) +#define MXC_S_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) + +#define MXC_V_AES_CTRL_KEY_SIZE_128 0 +#define MXC_V_AES_CTRL_KEY_SIZE_192 1 +#define MXC_V_AES_CTRL_KEY_SIZE_256 2 +#define MXC_S_AES_CTRL_KEY_SIZE_128 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS)) +#define MXC_S_AES_CTRL_KEY_SIZE_192 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS)) +#define MXC_S_AES_CTRL_KEY_SIZE_256 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_AES_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/afe_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/afe_regs.h new file mode 100644 index 0000000000..31a3f7cb80 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/afe_regs.h @@ -0,0 +1,626 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_AFE_REGS_H +#define _MXC_AFE_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file afe_regs.h + * @addtogroup afe AFE + * @{ + */ + +/** + * @brief Defines Configure Options for the LED Ports. + */ +typedef enum { + /** LED Sink Port 0 with OpAmp A, LED Sink Port 1 with OpAmp C */ + MXC_E_AFE_LED_CFG_PORT_OPAMP_A_C = 0, + /** LED Sink Port 0 with OpAmp B, LED Sink Port 1 with OpAmp D */ + MXC_E_AFE_LED_CFG_PORT_OPAMP_B_D, + /** Disable LED Sink Port 0,Disable LED Sink Port 1 */ + MXC_E_AFE_LED_CFG_PORT_DISABLED, +} mxc_afe_led_cfg_port_t; + +/** + * @brief Setup of Wake Up Detector for LPCs. + */ +typedef enum { + /** IDLE */ + MXC_E_AFE_EN_WUD_COMP_IDLE = 0, + /** Activate WUD for falling edges */ + MXC_E_AFE_EN_WUD_COMP_FALLING_EDGE = 2, + /** Activate WUD for rising edges */ + MXC_E_AFE_EN_WUD_COMP_RISING_EDGE = 3 +} mxc_afe_en_wud_comp_t; + +/** + * @brief LPC InMode. + */ +typedef enum { + /** InMode: both Nch and Pch */ + MXC_E_AFE_IN_MODE_COMP_NCH_PCH = 0, + /** InMode: only Nch */ + MXC_E_AFE_IN_MODE_COMP_NCH, + /** InMode: only Pch */ + MXC_E_AFE_IN_MODE_COMP_PCH, +} mxc_afe_in_mode_comp_t; + +/** + * @brief LPC Bias. + */ +typedef enum { + /** BIAS 0.52uA Delay 4.0us */ + MXC_E_AFE_BIAS_MODE_COMP_0 = 0, + /** BIAS 1.4uA Delay 1.7us */ + MXC_E_AFE_BIAS_MODE_COMP_1, + /** BIAS 2.8uA Delay 1.1us */ + MXC_E_AFE_BIAS_MODE_COMP_2, + /** BIAS 5.1uA Delay 0.7us */ + MXC_E_AFE_BIAS_MODE_COMP_3 +} mxc_afe_bias_mode_comp_t; + +/** + * @brief TMON Current Value. + */ +typedef enum { + /** TMON Current 4uA */ + MXC_E_AFE_TMON_CURRENT_VAL_0 = 0, + /** TMON Current 60uA */ + MXC_E_AFE_TMON_CURRENT_VAL_1, + /** TMON Current 64uA */ + MXC_E_AFE_TMON_CURRENT_VAL_2, + /** TMON Current 120uA */ + MXC_E_AFE_TMON_CURRENT_VAL_3 +} mxc_afe_tmon_current_t; + +/** + * @brief REFADC and REFDAC Voltage Select. + */ +typedef enum { + /** Voltage Reference = 1.024 V */ + MXC_E_AFE_REF_VOLT_SEL_1024 = 0, + /** Voltage Reference = 1.5 V */ + MXC_E_AFE_REF_VOLT_SEL_1500, + /** Voltage Reference = 2.048 V */ + MXC_E_AFE_REF_VOLT_SEL_2048, + /** Voltage Reference = 2.5 V */ + MXC_E_AFE_REF_VOLT_SEL_2500 +} mxc_afe_ref_volt_sel_t; + +/** + * @brief Selection for DAC VOltage Reference, REFADC or REFDAC. + */ +typedef enum { + /** DAC Voltage Reference = REFADC */ + MXC_E_AFE_DAC_REF_REFADC = 0, + /** DAC Voltage Reference = REFDAC */ + MXC_E_AFE_DAC_REF_REFDAC +} mxc_afe_dac_ref_t; + +/** + * @brief Selection for LPC Hysteresis. + */ +typedef enum { + /** LPC Hysteresis = 0 mV */ + MXC_E_AFE_HYST_COMP_0 = 0, + /** LPC Hysteresis = 7.5 mV */ + MXC_E_AFE_HYST_COMP_1, + /** LPC Hysteresis = 15 mV */ + MXC_E_AFE_HYST_COMP_2, + /** LPC Hysteresis = 30 mV */ + MXC_E_AFE_HYST_COMP_3 +} mxc_afe_hyst_comp_t; + +/** + * @brief Selection for MUX for SCM_or_sel. + */ +typedef enum { + /** SCM_or = HIZ */ + MXC_E_AFE_SCM_OR_SEL_HIZ = 0, + /** SCM_or = SCM0 */ + MXC_E_AFE_SCM_OR_SEL_SCM0, + /** SCM_or = SCM1 */ + MXC_E_AFE_SCM_OR_SEL_SCM1, + /** SCM_or = SCM2 */ + MXC_E_AFE_SCM_OR_SEL_SCM2, + /** SCM_or = SCM3 */ + MXC_E_AFE_SCM_OR_SEL_SCM3 +} mxc_afe_scm_or_sel_t; + +/** + * @brief Selection for MUX for SNO_or_sel. + */ +typedef enum { + /** SNO_or = HIZ */ + MXC_E_AFE_SNO_OR_SEL_HIZ = 0, + /** SNO_or = SNO0 */ + MXC_E_AFE_SNO_OR_SEL_SNO0, + /** SNO_or = SNO1 */ + MXC_E_AFE_SNO_OR_SEL_SNO1, + /** SNO_or = SNO2 */ + MXC_E_AFE_SNO_OR_SEL_SNO2, + /** SNO_or = SNO3 */ + MXC_E_AFE_SNO_OR_SEL_SNO3 +} mxc_afe_sno_or_sel_t; + +/** + * @brief Selection for MUX DACx_sel. + */ +typedef enum { + /** dacx = DACOP */ + MXC_E_AFE_DACX_SEL_P = 0, + /** dacx = DACON */ + MXC_E_AFE_DACX_SEL_N +} mxc_afe_dacx_sel_t; + +/** + * @brief Selection for state of Switch. + */ +typedef enum { + /** Switch is OPEN */ + MXC_E_AFE_CLOSE_SPST_SWITCH_OPEN = 0, + /** Switch is CLOSED */ + MXC_E_AFE_CLOSE_SPST_SWITCH_CLOSE +} mxc_afe_close_spst_t; + +/** + * @brief Switch to Connect Positive Pad to GND. + */ +typedef enum { + /** Positive Pad GND Switch OPEN */ + MXC_E_AFE_GND_SEL_OPAMP_SWITCH_OPEN = 0, + /** Positive Pad GND Switch CLOSED */ + MXC_E_AFE_GND_SEL_OPAMP_SWITCH_CLOSED +} mxc_afe_gnd_sel_opamp_t; + +/** + * @brief MUX Selection for OpPsel. + */ +typedef enum { + /** OpPsel = INx+ */ + MXC_E_AFE_P_IN_SEL_OPAMP_INPLUS = 0, + /** OpPsel = DAC_or */ + MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR, + /** OpPsel = SNO_or */ + MXC_E_AFE_P_IN_SEL_OPAMP_SNO_OR, + /** OpPsel = DAC_or also output on INx+ */ + MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR_AND_INPLUS +} mxc_afe_p_in_sel_opamp_t; + +/** + * @brief MUX Selection for OpNsel. + */ +typedef enum { + /** OpNsel = INx- */ + MXC_E_AFE_N_IN_SEL_OPAMP_INMINUS = 0, + /** OpNsel = OUTx */ + MXC_E_AFE_N_IN_SEL_OPAMP_OUT, + /** OpNsel = SCM_or */ + MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR, + /**OpNsel = SCM_or also output on INx- */ + MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR_AND_INMINUS, +} mxc_afe_n_in_sel_opamp_t; + +/** + * @brief MUX Selection for DAC_sel. + */ +typedef enum { + /** DAC_or = DAC0 */ + MXC_E_AFE_DAC_SEL_DAC0 = 0, + /** DAC_or = DAC1 */ + MXC_E_AFE_DAC_SEL_DAC1, + /** DAC_or = DAC2P */ + MXC_E_AFE_DAC_SEL_DAC2P, + /** DAC_or = DAC3P */ + MXC_E_AFE_DAC_SEL_DAC3P +} mxc_afe_dac_sel_t; + +/** + * @brief MUX Selection for NPAD_sel. + */ +typedef enum { + /** NPAD_Sel = HIZ */ + MXC_E_AFE_NPAD_SEL_HIZ = 0, + /** NPAD_Sel = LED Observe Port */ + MXC_E_AFE_NPAD_SEL_LED_OBS_PORT, + /** NPAD_Sel = DAC_or */ + MXC_E_AFE_NPAD_SEL_DAC_OR, + /** NPAD_Sel = DAC_or and LED Observe Port */ + MXC_E_AFE_NPAD_SEL_DAC_OR_AND_LED_OBS_PORT +} mxc_afe_npad_sel_t; + +/** + * @brief MUX Selection for CmpPSel. + */ +typedef enum { + /** CmpPSel = INx+ */ + MXC_E_AFE_POS_IN_SEL_COMP_INPLUS = 0, + /** CmpPSel = SCM */ + MXC_E_AFE_POS_IN_SEL_COMP_SCM, + /** CmpPSel = dac1 */ + MXC_E_AFE_POS_IN_SEL_COMP_DAC1, + /** CmpPSel = DAC3P */ + MXC_E_AFE_POS_IN_SEL_COMP_DAC3P, + /** CmpPSel = LED Observe Port */ + MXC_E_AFE_POS_IN_SEL_COMP_LED_OBS_PORT, + /** CmpPSel = dac1 also output on INx+ */ + MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_INPLUS, + /** CmpPSel = DAC3P also output on INx+ */ + MXC_E_AFE_POS_IN_SEL_COMP_DAC3P_AND_INPLUS, + /** CmpPSel = dac1 also output on SCM */ + MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_SCM +} mxc_afe_pos_in_sel_comp_t; + +/** + * @brief MUX Selection for CmpNSel. + */ +typedef enum { + /** CmpNSel = INx- */ + MXC_E_AFE_NEG_IN_SEL_COMP_INMINUS = 0, + /** CmpNSel = SNO */ + MXC_E_AFE_NEG_IN_SEL_COMP_SNO, + /** CmpNSel = dac0 */ + MXC_E_AFE_NEG_IN_SEL_COMP_DAC0, + /** CmpNSel = DAC2P */ + MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P, + /** CmpNSel = LED Observation Port */ + MXC_E_AFE_NEG_IN_SEL_COMP_LED_OBS_PORT, + /** CmpNSel = dac0 also output on INx- */ + MXC_E_AFE_NEG_IN_SEL_COMP_DAC0_AND_INMINUS, + /** CmpNSel = DAC2 also output on INx- */ + MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_INMINUS, + /** CmpNSel = DAC2 also output on SNO */ + MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_SNO +} mxc_afe_neg_in_sel_comp_t; + +/* Offset Register Description + ====== ==================================================== */ +typedef struct { + __IO uint32_t intr; /* 0x0000 Analog Front End Interrupt Flags and Enable/Disable */ + __IO uint32_t ctrl0; /* 0x0004 Analog Front End Control 0 */ + __IO uint32_t ctrl1; /* 0x0008 Analog Front End Control 1 */ + __IO uint32_t ctrl2; /* 0x000C Analog Front End Control 2 */ + __IO uint32_t ctrl3; /* 0x0010 Analog Front End Control 3 */ + __IO uint32_t ctrl4; /* 0x0014 Analog Front End Control 4 */ + __IO uint32_t ctrl5; /* 0x0018 Analog Front End Control 5 */ +} mxc_afe_regs_t; + +/* + Register offsets for module AFE. +*/ +#define MXC_R_AFE_OFFS_INTR ((uint32_t)0x00000000UL) +#define MXC_R_AFE_OFFS_CTRL0 ((uint32_t)0x00000004UL) +#define MXC_R_AFE_OFFS_CTRL1 ((uint32_t)0x00000008UL) +#define MXC_R_AFE_OFFS_CTRL2 ((uint32_t)0x0000000CUL) +#define MXC_R_AFE_OFFS_CTRL3 ((uint32_t)0x00000010UL) +#define MXC_R_AFE_OFFS_CTRL4 ((uint32_t)0x00000014UL) +#define MXC_R_AFE_OFFS_CTRL5 ((uint32_t)0x00000018UL) + +/* + Field positions and masks for module AFE. +*/ +#define MXC_F_AFE_INTR_OP_COMP0_IF_POS 0 +#define MXC_F_AFE_INTR_OP_COMP0_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IF_POS)) +#define MXC_F_AFE_INTR_OP_COMP1_IF_POS 1 +#define MXC_F_AFE_INTR_OP_COMP1_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IF_POS)) +#define MXC_F_AFE_INTR_OP_COMP2_IF_POS 2 +#define MXC_F_AFE_INTR_OP_COMP2_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IF_POS)) +#define MXC_F_AFE_INTR_OP_COMP3_IF_POS 3 +#define MXC_F_AFE_INTR_OP_COMP3_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IF_POS)) +#define MXC_F_AFE_INTR_LP_COMP0_IF_POS 4 +#define MXC_F_AFE_INTR_LP_COMP0_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IF_POS)) +#define MXC_F_AFE_INTR_LP_COMP1_IF_POS 5 +#define MXC_F_AFE_INTR_LP_COMP1_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IF_POS)) +#define MXC_F_AFE_INTR_LP_COMP2_IF_POS 6 +#define MXC_F_AFE_INTR_LP_COMP2_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IF_POS)) +#define MXC_F_AFE_INTR_LP_COMP3_IF_POS 7 +#define MXC_F_AFE_INTR_LP_COMP3_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IF_POS)) +#define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS 8 +#define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS 9 +#define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS 10 +#define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS 11 +#define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS 12 +#define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS 13 +#define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS 14 +#define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS 15 +#define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_OP_COMP0_POL_POS 16 +#define MXC_F_AFE_INTR_OP_COMP0_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_POL_POS)) +#define MXC_F_AFE_INTR_OP_COMP1_POL_POS 17 +#define MXC_F_AFE_INTR_OP_COMP1_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_POL_POS)) +#define MXC_F_AFE_INTR_OP_COMP2_POL_POS 18 +#define MXC_F_AFE_INTR_OP_COMP2_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_POL_POS)) +#define MXC_F_AFE_INTR_OP_COMP3_POL_POS 19 +#define MXC_F_AFE_INTR_OP_COMP3_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_POL_POS)) +#define MXC_F_AFE_INTR_LP_COMP0_POL_POS 20 +#define MXC_F_AFE_INTR_LP_COMP0_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_POL_POS)) +#define MXC_F_AFE_INTR_LP_COMP1_POL_POS 21 +#define MXC_F_AFE_INTR_LP_COMP1_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_POL_POS)) +#define MXC_F_AFE_INTR_LP_COMP2_POL_POS 22 +#define MXC_F_AFE_INTR_LP_COMP2_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_POL_POS)) +#define MXC_F_AFE_INTR_LP_COMP3_POL_POS 23 +#define MXC_F_AFE_INTR_LP_COMP3_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_POL_POS)) +#define MXC_F_AFE_INTR_OP_COMP0_IE_POS 24 +#define MXC_F_AFE_INTR_OP_COMP0_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IE_POS)) +#define MXC_F_AFE_INTR_OP_COMP1_IE_POS 25 +#define MXC_F_AFE_INTR_OP_COMP1_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IE_POS)) +#define MXC_F_AFE_INTR_OP_COMP2_IE_POS 26 +#define MXC_F_AFE_INTR_OP_COMP2_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IE_POS)) +#define MXC_F_AFE_INTR_OP_COMP3_IE_POS 27 +#define MXC_F_AFE_INTR_OP_COMP3_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IE_POS)) +#define MXC_F_AFE_INTR_LP_COMP0_IE_POS 28 +#define MXC_F_AFE_INTR_LP_COMP0_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IE_POS)) +#define MXC_F_AFE_INTR_LP_COMP1_IE_POS 29 +#define MXC_F_AFE_INTR_LP_COMP1_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IE_POS)) +#define MXC_F_AFE_INTR_LP_COMP2_IE_POS 30 +#define MXC_F_AFE_INTR_LP_COMP2_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IE_POS)) +#define MXC_F_AFE_INTR_LP_COMP3_IE_POS 31 +#define MXC_F_AFE_INTR_LP_COMP3_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IE_POS)) + +#define MXC_F_AFE_CTRL0_LED_CFG_POS 0 +#define MXC_F_AFE_CTRL0_LED_CFG ((uint32_t)(0x0000000FUL << MXC_F_AFE_CTRL0_LED_CFG_POS)) +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS 4 +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS)) +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS 5 +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS)) +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS 6 +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS)) +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS 7 +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS)) +#define MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS 8 +#define MXC_F_AFE_CTRL0_EN_WUD_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS)) +#define MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS 10 +#define MXC_F_AFE_CTRL0_EN_WUD_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS)) +#define MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS 12 +#define MXC_F_AFE_CTRL0_EN_WUD_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS)) +#define MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS 14 +#define MXC_F_AFE_CTRL0_EN_WUD_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS)) +#define MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS 16 +#define MXC_F_AFE_CTRL0_IN_MODE_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS)) +#define MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS 18 +#define MXC_F_AFE_CTRL0_IN_MODE_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS)) +#define MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS 20 +#define MXC_F_AFE_CTRL0_IN_MODE_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS)) +#define MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS 22 +#define MXC_F_AFE_CTRL0_IN_MODE_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS)) +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS 24 +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS)) +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS 26 +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS)) +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS 28 +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS)) +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS 30 +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS)) + +#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS 0 +#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS)) +#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS 1 +#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS)) +#define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS 3 +#define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS)) +#define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS 4 +#define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS)) +#define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS 5 +#define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS)) +#define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS 6 +#define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS)) +#define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS 8 +#define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS)) +#define MXC_F_AFE_CTRL1_REF_SEL_POS 10 +#define MXC_F_AFE_CTRL1_REF_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_SEL_POS)) +#define MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS 11 +#define MXC_F_AFE_CTRL1_REF_ADC_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS)) +#define MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS 12 +#define MXC_F_AFE_CTRL1_REF_DAC_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS)) +#define MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS 13 +#define MXC_F_AFE_CTRL1_REF_BLK_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS)) +#define MXC_F_AFE_CTRL1_REF_ADC_COMP_POS 14 +#define MXC_F_AFE_CTRL1_REF_ADC_COMP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_COMP_POS)) +#define MXC_F_AFE_CTRL1_REF_DAC_COMP_POS 15 +#define MXC_F_AFE_CTRL1_REF_DAC_COMP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_COMP_POS)) +#define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS 16 +#define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS)) +#define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS 18 +#define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS)) +#define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS 20 +#define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS)) +#define MXC_F_AFE_CTRL1_PLL_TST_EN_POS 23 +#define MXC_F_AFE_CTRL1_PLL_TST_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_PLL_TST_EN_POS)) +#define MXC_F_AFE_CTRL1_V1EXTADJ_POS 25 +#define MXC_F_AFE_CTRL1_V1EXTADJ ((uint32_t)(0x0000001FUL << MXC_F_AFE_CTRL1_V1EXTADJ_POS)) +#define MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS 30 +#define MXC_F_AFE_CTRL1_TMON_CUR_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS)) + +#define MXC_F_AFE_CTRL2_HYST_COMP0_POS 0 +#define MXC_F_AFE_CTRL2_HYST_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP0_POS)) +#define MXC_F_AFE_CTRL2_HYST_COMP1_POS 2 +#define MXC_F_AFE_CTRL2_HYST_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP1_POS)) +#define MXC_F_AFE_CTRL2_HYST_COMP2_POS 4 +#define MXC_F_AFE_CTRL2_HYST_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP2_POS)) +#define MXC_F_AFE_CTRL2_HYST_COMP3_POS 6 +#define MXC_F_AFE_CTRL2_HYST_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP3_POS)) +#define MXC_F_AFE_CTRL2_HY_POL_COMP0_POS 8 +#define MXC_F_AFE_CTRL2_HY_POL_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP0_POS)) +#define MXC_F_AFE_CTRL2_HY_POL_COMP1_POS 9 +#define MXC_F_AFE_CTRL2_HY_POL_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP1_POS)) +#define MXC_F_AFE_CTRL2_HY_POL_COMP2_POS 10 +#define MXC_F_AFE_CTRL2_HY_POL_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP2_POS)) +#define MXC_F_AFE_CTRL2_HY_POL_COMP3_POS 11 +#define MXC_F_AFE_CTRL2_HY_POL_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP3_POS)) +#define MXC_F_AFE_CTRL2_POWERUP_COMP0_POS 12 +#define MXC_F_AFE_CTRL2_POWERUP_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP0_POS)) +#define MXC_F_AFE_CTRL2_POWERUP_COMP1_POS 13 +#define MXC_F_AFE_CTRL2_POWERUP_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP1_POS)) +#define MXC_F_AFE_CTRL2_POWERUP_COMP2_POS 14 +#define MXC_F_AFE_CTRL2_POWERUP_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP2_POS)) +#define MXC_F_AFE_CTRL2_POWERUP_COMP3_POS 15 +#define MXC_F_AFE_CTRL2_POWERUP_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP3_POS)) +#define MXC_F_AFE_CTRL2_DACOUT_EN0_POS 16 +#define MXC_F_AFE_CTRL2_DACOUT_EN0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN0_POS)) +#define MXC_F_AFE_CTRL2_DACOUT_EN1_POS 17 +#define MXC_F_AFE_CTRL2_DACOUT_EN1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN1_POS)) +#define MXC_F_AFE_CTRL2_DACOUT_EN2_POS 18 +#define MXC_F_AFE_CTRL2_DACOUT_EN2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN2_POS)) +#define MXC_F_AFE_CTRL2_DACOUT_EN3_POS 19 +#define MXC_F_AFE_CTRL2_DACOUT_EN3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN3_POS)) +#define MXC_F_AFE_CTRL2_SCM_OR_SEL_POS 20 +#define MXC_F_AFE_CTRL2_SCM_OR_SEL ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SCM_OR_SEL_POS)) +#define MXC_F_AFE_CTRL2_SNO_OR_SEL_POS 23 +#define MXC_F_AFE_CTRL2_SNO_OR_SEL ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SNO_OR_SEL_POS)) +#define MXC_F_AFE_CTRL2_DAC0_SEL_POS 26 +#define MXC_F_AFE_CTRL2_DAC0_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC0_SEL_POS)) +#define MXC_F_AFE_CTRL2_DAC1_SEL_POS 27 +#define MXC_F_AFE_CTRL2_DAC1_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC1_SEL_POS)) + +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS 12 +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS)) +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS 13 +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS)) +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS 14 +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS)) +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS 15 +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS)) +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS 16 +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS)) +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS 17 +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS)) +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS 18 +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS)) +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS 19 +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS)) +#define MXC_F_AFE_CTRL3_CLOSE_SPST0_POS 20 +#define MXC_F_AFE_CTRL3_CLOSE_SPST0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST0_POS)) +#define MXC_F_AFE_CTRL3_CLOSE_SPST1_POS 21 +#define MXC_F_AFE_CTRL3_CLOSE_SPST1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST1_POS)) +#define MXC_F_AFE_CTRL3_CLOSE_SPST2_POS 22 +#define MXC_F_AFE_CTRL3_CLOSE_SPST2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST2_POS)) +#define MXC_F_AFE_CTRL3_CLOSE_SPST3_POS 23 +#define MXC_F_AFE_CTRL3_CLOSE_SPST3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST3_POS)) +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS 24 +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS)) +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS 25 +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS)) +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS 26 +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS)) +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS 27 +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS)) +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS 28 +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS)) +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS 29 +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS)) +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS 30 +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS)) +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS 31 +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS)) + +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS 0 +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS)) +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS 2 +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS)) +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS 4 +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS)) +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS 6 +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS)) +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS 8 +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS)) +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS 10 +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS)) +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS 12 +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS)) +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS 14 +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS)) +#define MXC_F_AFE_CTRL4_DAC_SEL_A_POS 16 +#define MXC_F_AFE_CTRL4_DAC_SEL_A ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_A_POS)) +#define MXC_F_AFE_CTRL4_DAC_SEL_B_POS 18 +#define MXC_F_AFE_CTRL4_DAC_SEL_B ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_B_POS)) +#define MXC_F_AFE_CTRL4_DAC_SEL_C_POS 20 +#define MXC_F_AFE_CTRL4_DAC_SEL_C ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_C_POS)) +#define MXC_F_AFE_CTRL4_DAC_SEL_D_POS 22 +#define MXC_F_AFE_CTRL4_DAC_SEL_D ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_D_POS)) +#define MXC_F_AFE_CTRL4_NPAD_SEL_A_POS 24 +#define MXC_F_AFE_CTRL4_NPAD_SEL_A ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_A_POS)) +#define MXC_F_AFE_CTRL4_NPAD_SEL_B_POS 26 +#define MXC_F_AFE_CTRL4_NPAD_SEL_B ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_B_POS)) +#define MXC_F_AFE_CTRL4_NPAD_SEL_C_POS 28 +#define MXC_F_AFE_CTRL4_NPAD_SEL_C ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_C_POS)) +#define MXC_F_AFE_CTRL4_NPAD_SEL_D_POS 30 +#define MXC_F_AFE_CTRL4_NPAD_SEL_D ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_D_POS)) + +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS 0 +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS)) +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS 3 +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS)) +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS 6 +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS)) +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS 9 +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS)) +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS 12 +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS)) +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS 15 +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS)) +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS 18 +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS)) +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS 21 +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS)) +#define MXC_F_AFE_CTRL5_OP_CMP0_POS 24 +#define MXC_F_AFE_CTRL5_OP_CMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP0_POS)) +#define MXC_F_AFE_CTRL5_OP_CMP1_POS 25 +#define MXC_F_AFE_CTRL5_OP_CMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP1_POS)) +#define MXC_F_AFE_CTRL5_OP_CMP2_POS 26 +#define MXC_F_AFE_CTRL5_OP_CMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP2_POS)) +#define MXC_F_AFE_CTRL5_OP_CMP3_POS 27 +#define MXC_F_AFE_CTRL5_OP_CMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP3_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_AFE_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/clkman_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/clkman_regs.h new file mode 100644 index 0000000000..28a258b999 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/clkman_regs.h @@ -0,0 +1,493 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_CLKMAN_REGS_H_ +#define _MXC_CLKMAN_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file clkman_regs.h + * @addtogroup clkman CLKMAN + * @{ + */ + +/** + * @brief Defines clock input selections for the phase locked loop. + */ +typedef enum { + /** Input select for high frequency crystal oscillator */ + MXC_E_CLKMAN_PLL_INPUT_SELECT_HFX = 0, + /** Input select for 24MHz ring oscillator */ + MXC_E_CLKMAN_PLL_INPUT_SELECT_24MHZ_RO, +} mxc_clkman_pll_input_select_t; + +/** + * @brief Defines clock input frequency for the phase locked loop. + */ +typedef enum { + /** Input frequency of 24MHz */ + MXC_E_CLKMAN_PLL_DIVISOR_SELECT_24MHZ = 0, + /** Input frequency of 12MHz */ + MXC_E_CLKMAN_PLL_DIVISOR_SELECT_12MHZ, + /** Input frequency of 8MHz */ + MXC_E_CLKMAN_PLL_DIVISOR_SELECT_8MHZ, +} mxc_clkman_pll_divisor_select_t; + +/** + * @brief Defines terminal count for PLL stable. + */ +typedef enum { + /** Clock stable after 2^8 = 256 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_8_CLKS = 0, + /** Clock stable after 2^9 = 512 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_9_CLKS, + /** Clock stable after 2^10 = 1024 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_10_CLKS, + /** Clock stable after 2^11 = 2048 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_11_CLKS, + /** Clock stable after 2^12 = 4096 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_12_CLKS, + /** Clock stable after 2^13 = 8192 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_13_CLKS, + /** Clock stable after 2^14 = 16384 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_14_CLKS, + /** Clock stable after 2^15 = 32768 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_15_CLKS, + /** Clock stable after 2^16 = 65536 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_16_CLKS, + /** Clock stable after 2^17 = 131072 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_17_CLKS, + /** Clock stable after 2^18 = 262144 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_18_CLKS, + /** Clock stable after 2^19 = 524288 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_19_CLKS, + /** Clock stable after 2^20 = 1048576 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_20_CLKS, + /** Clock stable after 2^21 = 2097152 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_21_CLKS, + /** Clock stable after 2^22 = 4194304 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_22_CLKS, + /** Clock stable after 2^23 = 8388608 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_23_CLKS +} mxc_clkman_stability_count_t; + +/** + * @brief Defines clock source selections for system clock. + */ +typedef enum { + /** Clock select for 24MHz ring oscillator divided by 8 (3MHz) */ + MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8 = 0, + /** Clock select for 24MHz ring oscillator */ + MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO, + /** Clock select for high frequency crystal oscillator */ + MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX, + /** Clock select for 48MHz phase locked loop output divided by 2 (24MHz) */ + MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2 +} mxc_clkman_system_source_select_t; + +/** + * @brief Defines clock source selections for analog to digital converter clock. + */ +typedef enum { + /** Clock select for system clock frequency */ + MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM = 0, + /** Clock select for 8MHz phase locked loop output */ + MXC_E_CLKMAN_ADC_SOURCE_SELECT_PLL_8MHZ, + /** Clock select for high frequency crystal oscillator */ + MXC_E_CLKMAN_ADC_SOURCE_SELECT_HFX, + /** Clock select for 24MHz ring oscillator */ + MXC_E_CLKMAN_ADC_SOURCE_SELECT_24MHZ_RO, +} mxc_clkman_adc_source_select_t; + +/** + * @brief Defines clock source selections for watchdog timer clock. + */ +typedef enum { + /** Clock select for system clock frequency */ + MXC_E_CLKMAN_WDT_SOURCE_SELECT_SYSTEM = 0, + /** Clock select for 8MHz phase locked loop output */ + MXC_E_CLKMAN_WDT_SOURCE_SELECT_RTC, + /** Clock select for high frequency crystal oscillator */ + MXC_E_CLKMAN_WDT_SOURCE_SELECT_24MHZ_RO, + /** Clock select for 24MHz ring oscillator */ + MXC_E_CLKMAN_WDT_SOURCE_SELECT_NANO, +} mxc_clkman_wdt_source_select_t; + +/** + * @brief Defines clock scales for various clocks. + */ +typedef enum { + /** Clock disabled */ + MXC_E_CLKMAN_CLK_SCALE_DISABLED = 0, + /** Clock enabled */ + MXC_E_CLKMAN_CLK_SCALE_ENABLED, + /** Clock scale for dividing by 2 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_2, + /** Clock scale for dividing by 4 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_4, + /** Clock scale for dividing by 8 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_8, + /** Clock scale for dividing by 16 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_16, + /** Clock scale for dividing by 32 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_32, + /** Clock scale for dividing by 64 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_64, + /** Clock scale for dividing by 128 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_128, + /** Clock scale for dividing by 256 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_256 +} mxc_clkman_clk_scale_t; + +/** + * @brief Defines Setting of the Clock Gates . + */ +typedef enum { + /** Clock Gater is Off */ + MXC_E_CLKMAN_CLK_GATE_OFF = 0, + /** Clock Gater is Dynamic */ + MXC_E_CLKMAN_CLK_GATE_DYNAMIC, + /** Clock Gater is On */ + MXC_E_CLKMAN_CLK_GATE_ON +} mxc_clkman_clk_gate_t; + +/* Offset Register Description + ====== ===================================================================== */ +typedef struct { + __IO uint32_t clk_config; /* 0x0000 System Clock Configuration */ + __IO uint32_t clk_ctrl; /* 0x0004 System Clock Controls */ + __IO uint32_t intfl; /* 0x0008 Interrupt Flags */ + __IO uint32_t inten; /* 0x000C Interrupt Enable/Disable Controls */ + __IO uint32_t trim_calc; /* 0x0010 Trim Calculation Controls */ + __I uint32_t rsv0014[4]; /* 0x0014 */ + __IO uint32_t i2c_timer_ctrl; /* 0x0024 I2C Timer Control */ + __I uint32_t rsv0028[6]; /* 0x0028 */ + __IO uint32_t clk_ctrl_0_system; /* 0x0040 Control Settings for CLK0 - System Clock */ + __IO uint32_t clk_ctrl_1_gpio; /* 0x0044 Control Settings for CLK1 - GPIO Module Clock */ + __IO uint32_t clk_ctrl_2_pt; /* 0x0048 Control Settings for CLK2 - Pulse Train Module Clock */ + __IO uint32_t clk_ctrl_3_spi0; /* 0x004C Control Settings for CLK3 - SPI0 Master Clock */ + __IO uint32_t clk_ctrl_4_spi1; /* 0x0050 Control Settings for CLK4 - SPI1 Master Clock */ + __IO uint32_t clk_ctrl_5_spi2; /* 0x0054 Control Settings for CLK5 - SPI2 Master Clock */ + __IO uint32_t clk_ctrl_6_i2cm; /* 0x0058 Control Settings for CLK6 - Clock for all I2C Masters */ + __IO uint32_t clk_ctrl_7_i2cs; /* 0x005C Control Settings for CLK7 - I2C Slave Clock */ + __IO uint32_t clk_ctrl_8_lcd_chpump; /* 0x0060 Control Settings for CLK8 - LCD Charge Pump Clock */ + __IO uint32_t clk_ctrl_9_puf; /* 0x0064 Control Settings for CLK9 - PUF Clock */ + __IO uint32_t clk_ctrl_10_prng; /* 0x0068 Control Settings for CLK10 - PRNG Clock */ + __IO uint32_t clk_ctrl_11_wdt0; /* 0x006C Control Settings for CLK11 - Watchdog Timer 0 ScaledSysClk */ + __IO uint32_t clk_ctrl_12_wdt1; /* 0x0070 Control Settings for CLK12 - Watchdog Timer 1 ScaledSysClk */ + __IO uint32_t clk_ctrl_13_rtc_int_sync; /* 0x0074 Control Settings for CLK13 - RTC Interrupt Sync Clock */ + __IO uint32_t clk_ctrl_14_dac0; /* 0x0078 Control Settings for CLK14 - 12-bit DAC 0 Clock */ + __IO uint32_t clk_ctrl_15_dac1; /* 0x007C Control Settings for CLK15 - 12-bit DAC 1 Clock */ + __IO uint32_t clk_ctrl_16_dac2; /* 0x0080 Control Settings for CLK16 - 8-bit DAC 0 Clock */ + __IO uint32_t clk_ctrl_17_dac3; /* 0x0084 Control Settings for CLK17 - 8-bit DAC 1 Clock */ + __I uint32_t rsv0088[30]; /* 0x0088 */ + __IO uint32_t crypt_clk_ctrl_0_aes; /* 0x0100 Control Settings for Crypto Clock 0 - AES */ + __IO uint32_t crypt_clk_ctrl_1_maa; /* 0x0104 Control Settings for Crypto Clock 1 - MAA */ + __IO uint32_t crypt_clk_ctrl_2_prng; /* 0x0108 Control Settings for Crypto Clock 2 - PRNG */ + __I uint32_t rsv010C[13]; /* 0x010C */ + __IO uint32_t clk_gate_ctrl0; /* 0x0140 Dynamic Clock Gating Control Register 0 */ + __IO uint32_t clk_gate_ctrl1; /* 0x0144 Dynamic Clock Gating Control Register 1 */ + __IO uint32_t clk_gate_ctrl2; /* 0x0148 Dynamic Clock Gating Control Register 2 */ +} mxc_clkman_regs_t; + +/* + Register offsets for module CLKMAN. +*/ +#define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) +#define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL) +#define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL) +#define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL) +#define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000024UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_0_SYSTEM ((uint32_t)0x00000040UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_1_GPIO ((uint32_t)0x00000044UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_2_PT ((uint32_t)0x00000048UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_3_SPI0 ((uint32_t)0x0000004CUL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_4_SPI1 ((uint32_t)0x00000050UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_5_SPI2 ((uint32_t)0x00000054UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_6_I2CM ((uint32_t)0x00000058UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_7_I2CS ((uint32_t)0x0000005CUL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_8_LCD_CHPUMP ((uint32_t)0x00000060UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_9_PUF ((uint32_t)0x00000064UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_10_PRNG ((uint32_t)0x00000068UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_11_WDT0 ((uint32_t)0x0000006CUL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_12_WDT1 ((uint32_t)0x00000070UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_13_RTC_INT_SYNC ((uint32_t)0x00000074UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_14_DAC0 ((uint32_t)0x00000078UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_15_DAC1 ((uint32_t)0x0000007CUL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_16_DAC2 ((uint32_t)0x00000080UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_17_DAC3 ((uint32_t)0x00000084UL) +#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL) +#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL) +#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL) +#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL) +#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL) +#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL) + +/* + Field positions and masks for module CLKMAN. +*/ +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS 0 +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS 1 +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS 2 +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS 4 +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST ((uint32_t)(0x0000001FUL << MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS 9 +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL ((uint32_t)(0x00000007UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS 12 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS 13 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS 14 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS 16 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS 18 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS 19 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS 20 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 24 +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS 25 +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 28 +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 1 +#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS 3 +#define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS 4 +#define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS 8 +#define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS 9 +#define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS 12 +#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS 16 +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS 17 +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS 20 +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS 21 +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 24 +#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS)) + +#define MXC_F_CLKMAN_INTFL_RING_STABLE_POS 0 +#define MXC_F_CLKMAN_INTFL_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_RING_STABLE_POS)) +#define MXC_F_CLKMAN_INTFL_PLL_STABLE_POS 1 +#define MXC_F_CLKMAN_INTFL_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_PLL_STABLE_POS)) +#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 2 +#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS)) + +#define MXC_F_CLKMAN_INTEN_RING_STABLE_POS 0 +#define MXC_F_CLKMAN_INTEN_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_RING_STABLE_POS)) +#define MXC_F_CLKMAN_INTEN_PLL_STABLE_POS 1 +#define MXC_F_CLKMAN_INTEN_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_PLL_STABLE_POS)) +#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 2 +#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS)) + +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0 +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS)) +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1 +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS)) +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2 +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS)) +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3 +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS)) +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16 +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS)) + +#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0 +#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS 0 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS 2 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS 14 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS 16 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS 18 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS 20 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS 22 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS 24 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 26 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS 28 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 30 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS)) + +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS 0 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS 2 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS 4 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS 6 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS 8 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS 10 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS 12 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS 14 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 16 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 18 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS 20 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS 22 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS 24 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS 30 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS)) + +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS 0 +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS 2 +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS 4 +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS 6 +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_CLKMAN_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis.h new file mode 100644 index 0000000000..8ca978a2f3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis.h @@ -0,0 +1,40 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "max32610.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.c new file mode 100644 index 0000000000..3694273047 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.c @@ -0,0 +1,65 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "cmsis_nvic.h" + +#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_ARM_STD) +__attribute__((aligned(256))) +#endif +#if defined(TOOLCHAIN_IAR) +#pragma data_alignment=256 +#endif +static void (*ramVectorTable[MXC_IRQ_COUNT])(void); + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t*)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR != (uint32_t)ramVectorTable) { + uint32_t *old_vectors = (uint32_t*)SCB->VTOR; + vectors = (uint32_t*)ramVectorTable; + for (i = 0; i < NVIC_NUM_VECTORS; i++) { + vectors[i] = old_vectors[i]; + } + SCB->VTOR = (uint32_t)ramVectorTable; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.h new file mode 100644 index 0000000000..d3e5447614 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.h @@ -0,0 +1,53 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +#define NVIC_NUM_VECTORS MXC_IRQ_COUNT +#define NVIC_USER_IRQ_OFFSET 16 + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif /* MBED_CMSIS_NVIC_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/crc_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/crc_regs.h new file mode 100644 index 0000000000..6acec11048 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/crc_regs.h @@ -0,0 +1,89 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_CRC_REGS_H_ +#define _MXC_CRC_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file crc_regs.h + * @addtogroup crc CRC + * @{ + */ + +/* Offset Register Description + ====== ======================================================= */ +typedef struct { + __IO uint32_t reseed; /* 0x0000 CRC-16/CRC-32 Reseed Controls */ + __IO uint32_t seed16; /* 0x0004 Reseed Value for CRC-16 Calculations */ + __IO uint32_t seed32; /* 0x0008 Reseed Value for CRC-32 Calculations */ +} mxc_crc_regs_t; + +/* Offset Register Description + ====== ======================================================= */ +typedef struct { + __IO uint32_t value16[512]; /* 0x0000 Write Next CRC-16 Data Value / Read CRC-16 Result Value */ + __IO uint32_t value32[512]; /* 0x0800 Write Next CRC-32 Data Value / Read CRC-32 Result Value */ +} mxc_crc_data_regs_t; + +/* + Register offsets for module CRC. +*/ +#define MXC_R_CRC_OFFS_RESEED ((uint32_t)0x00000000UL) +#define MXC_R_CRC_OFFS_SEED16 ((uint32_t)0x00000004UL) +#define MXC_R_CRC_OFFS_SEED32 ((uint32_t)0x00000008UL) +#define MXC_R_CRC_DATA_OFFS_VALUE16 ((uint32_t)0x00000000UL) +#define MXC_R_CRC_DATA_OFFS_VALUE32 ((uint32_t)0x00000800UL) + +/* + Field positions and masks for module CRC. +*/ +#define MXC_F_CRC_RESEED_CRC16_POS 0 +#define MXC_F_CRC_RESEED_CRC16 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC16_POS)) +#define MXC_F_CRC_RESEED_CRC32_POS 1 +#define MXC_F_CRC_RESEED_CRC32 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC32_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_CRC_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/dac_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/dac_regs.h new file mode 100644 index 0000000000..2f0f4bd8c5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/dac_regs.h @@ -0,0 +1,180 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_DAC_REGS_H +#define _MXC_DAC_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file dac_regs.h + * @addtogroup dac DAC + * @{ + */ + +/** + * @brief Defines the DAC Operational Modes. + */ +typedef enum { + /** DAC OpMode FIFO */ + MXC_E_DAC_OP_MODE_FIFO = 0, + /** DAC OpMode Sample Count */ + MXC_E_DAC_OP_MODE_DACSMPLCNT, + /** DAC OpMode DAC_REG Control */ + MXC_E_DAC_OP_MODE_DAC_REG, + /** DAC OpMode Continuous */ + MXC_E_DAC_OP_MODE_CONTINUOUS +} mxc_dac_op_mode_t; + +/** + * @brief Defines the DAC Interpolation Options. + */ +typedef enum { + /** DAC Interpolation is Disabled */ + MXC_E_DAC_INTERP_MODE_DISABLED = 0, + /** DAC Interpolation 2:1 */ + MXC_E_DAC_INTERP_MODE_2_TO_1, + /** DAC Interpolation 4:1 */ + MXC_E_DAC_INTERP_MODE_4_TO_1, + /** DAC Interpolation 8:1 */ + MXC_E_DAC_INTERP_MODE_8_TO_1 +} mxc_dac_interp_mode_t; + +/** + * @brief Defines the DAC Start Modes. + */ +typedef enum { + /** Start on FIFO Not Empty */ + MXC_E_DAC_START_MODE_FIFO_NOT_EMPTY = 0, + /** Start on ADC generated Start Strobe */ + MXC_E_DAC_START_MODE_ADC_STROBE, + /** Start on DAC generated Start Strobe */ + MXC_E_DAC_START_MODE_DAC_STROBE +} mxc_dac_start_mode_t; + +/* Offset Register Description + ====== ================================================== */ +typedef struct { + __IO uint32_t ctrl0; /* 0x0000 DAC Control Register 0 */ + __IO uint32_t rate; /* 0x0004 DAC Output Rate Control */ + __IO uint32_t ctrl1_int; /* 0x0008 DAC Control Register 1, Interrupt Flags and Enable */ + __IO uint32_t reg; /* 0x000C DAC Data Register */ + __IO uint32_t trm; /* 0x0010 DAC Trim Register */ +} mxc_dac_regs_t; + +/* Offset Register Description + ====== ================================================== */ +typedef struct { + union { + __IO uint8_t output_8; /* 0x0000 Write to push values to DAC output FIFO */ + __IO uint16_t output_16; /* 0x0000 Write to push values to DAC output FIFO */ + }; +} mxc_dac_fifo_t; + +/* + Register offsets for module DAC12. +*/ +#define MXC_R_DAC_OFFS_CTRL0 ((uint32_t)0x00000000UL) +#define MXC_R_DAC_OFFS_RATE ((uint32_t)0x00000004UL) +#define MXC_R_DAC_OFFS_CTRL1_INT ((uint32_t)0x00000008UL) +#define MXC_R_DAC_FIFO_OFFS_OUTPUT ((uint32_t)0x00000000UL) + +/* + Field positions and masks for module DAC. +*/ +#define MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS 0 +#define MXC_F_DAC_CTRL0_FIFO_AE_CNT ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS)) +#define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS 5 +#define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS)) +#define MXC_F_DAC_CTRL0_FIFO_EMPTY_POS 6 +#define MXC_F_DAC_CTRL0_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_EMPTY_POS)) +#define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS 7 +#define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS)) +#define MXC_F_DAC_CTRL0_INTERP_MODE_POS 8 +#define MXC_F_DAC_CTRL0_INTERP_MODE ((uint32_t)(0x00000007UL << MXC_F_DAC_CTRL0_INTERP_MODE_POS)) +#define MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS 12 +#define MXC_F_DAC_CTRL0_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS)) +#define MXC_F_DAC_CTRL0_START_MODE_POS 16 +#define MXC_F_DAC_CTRL0_START_MODE ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_START_MODE_POS)) +#define MXC_F_DAC_CTRL0_CPU_START_POS 20 +#define MXC_F_DAC_CTRL0_CPU_START ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CPU_START_POS)) +#define MXC_F_DAC_CTRL0_OP_MODE_POS 24 +#define MXC_F_DAC_CTRL0_OP_MODE ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_OP_MODE_POS)) +#define MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS 26 +#define MXC_F_DAC_CTRL0_POWER_MODE_1_0 ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS)) +#define MXC_F_DAC_CTRL0_POWER_ON_POS 28 +#define MXC_F_DAC_CTRL0_POWER_ON ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_ON_POS)) +#define MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS 29 +#define MXC_F_DAC_CTRL0_CLOCK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS)) +#define MXC_F_DAC_CTRL0_POWER_MODE_2_POS 30 +#define MXC_F_DAC_CTRL0_POWER_MODE_2 ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_MODE_2_POS)) +#define MXC_F_DAC_CTRL0_RESET_POS 31 +#define MXC_F_DAC_CTRL0_RESET ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_RESET_POS)) + +#define MXC_F_DAC_RATE_RATE_CNT_POS 0 +#define MXC_F_DAC_RATE_RATE_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_RATE_CNT_POS)) +#define MXC_F_DAC_RATE_SAMPLE_CNT_POS 16 +#define MXC_F_DAC_RATE_SAMPLE_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_SAMPLE_CNT_POS)) + +#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS 0 +#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS)) +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS 1 +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS)) +#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS 2 +#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS)) +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS 3 +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS)) +#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS 16 +#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS)) +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS 17 +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS)) +#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS 18 +#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS)) +#define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS 28 +#define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS)) +#define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS 29 +#define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _DAC12_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/flc_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/flc_regs.h new file mode 100644 index 0000000000..864c8c9b97 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/flc_regs.h @@ -0,0 +1,210 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_FLC_REGS_H +#define _MXC_FLC_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file flc_regs.h + * @addtogroup flc FLC + * @{ + */ +/* Offset Register Description + ====== ======================================================= */ +typedef struct { + __IO uint32_t faddr; /* 0x0000 Flash Operation Address */ + __IO uint32_t fckdiv; /* 0x0004 Flash Clock Rate Divisor */ + __IO uint32_t ctrl; /* 0x0008 Flash Control Register */ + __I uint32_t rsv000C[6]; /* 0x000C */ + __IO uint32_t intr; /* 0x0024 Flash Controller Interrupt Flags and Enable/Disable 0 */ + __I uint32_t rsv0028[2]; /* 0x0028 */ + __IO uint32_t fdata; /* 0x0030 Flash Operation Data Register */ + __I uint32_t rsv0034[7]; /* 0x0034 */ + __IO uint32_t perform; /* 0x0050 Flash Performance Settings */ + __I uint32_t rsv0054[11]; /* 0x0054 */ + __IO uint32_t status; /* 0x0080 Security Status Flags */ + __I uint32_t rsv0084; /* 0x0084 */ + __IO uint32_t security; /* 0x0088 Flash Controller Security Settings */ + __I uint32_t rsv008C[4]; /* 0x008C */ + __IO uint32_t bypass; /* 0x009C Status Flags for DSB Operations */ + __IO uint32_t user_option; /* 0x0100 Used to set DSB Access code and Auto-Lock in info block */ + __I uint32_t rsv0104[15]; /* 0x0104 */ + __IO uint32_t ctrl2; /* 0x0140 Flash Control Register 2 */ + __IO uint32_t intfl1; /* 0x0144 Interrupt Flags Register 1 */ + __IO uint32_t inten1; /* 0x0148 Interrupt Enable/Disable Register 1 */ + __I uint32_t rsv014C; /* 0x014C */ + __IO uint32_t disable_xr0; /* 0x0150 Disable Flash Page Exec/Read Register 0 */ + __IO uint32_t disable_xr1; /* 0x0154 Disable Flash Page Exec/Read Register 1 */ + __IO uint32_t disable_xr2; /* 0x0158 Disable Flash Page Exec/Read Register 2 */ + __IO uint32_t disable_xr3; /* 0x015C Disable Flash Page Exec/Read Register 3 */ + __IO uint32_t disable_we0; /* 0x0160 Disable Flash Page Write/Erase Register 0 */ + __IO uint32_t disable_we1; /* 0x0164 Disable Flash Page Write/Erase Register 1 */ + __IO uint32_t disable_we2; /* 0x0168 Disable Flash Page Write/Erase Register 2 */ + __IO uint32_t disable_we3; /* 0x016C Disable Flash Page Write/Erase Register 3 */ +} mxc_flc_regs_t; + +/* + Register offsets for module FLC. +*/ +#define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL) +#define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL) +#define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL) +#define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL) +#define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL) +#define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL) +#define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL) +#define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL) +#define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL) +#define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL) +#define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL) +#define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL) +#define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL) +#define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000150UL) +#define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000154UL) +#define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000158UL) +#define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000015CUL) +#define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000160UL) +#define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000164UL) +#define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000168UL) +#define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000016CUL) + +#define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55) +#define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA) + +#define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2) + +/* + Field positions and masks for module FLC. +*/ +#define MXC_F_FLC_FADDR_FADDR_POS 0 +#define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x0003FFFFUL << MXC_F_FLC_FADDR_FADDR_POS)) + +#define MXC_F_FLC_FCKDIV_FCKDIV_POS 0 +#define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000001FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS)) + +#define MXC_F_FLC_CTRL_WRITE_POS 0 +#define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS)) +#define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 +#define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) +#define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 +#define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) +#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 +#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) +#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16 +#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS)) +#define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17 +#define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS)) +#define MXC_F_FLC_CTRL_PENDING_POS 24 +#define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS)) +#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25 +#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS)) +#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27 +#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS)) +#define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28 +#define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS)) + +#define MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS 0 +#define MXC_F_FLC_INTR_FLASH_OP_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS)) +#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS 1 +#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS)) +#define MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS 9 +#define MXC_F_FLC_INTR_FLASH_OP_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS)) +#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS 10 +#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS)) + +#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8 +#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS)) +#define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0 +#define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS)) + +#define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS 0 +#define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS)) +#define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS 1 +#define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS)) +#define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3 +#define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS)) + +#define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0 +#define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS)) +#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8 +#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS)) +#define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 31 +#define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS)) + +#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0 +#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS)) +#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1 +#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS)) +#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2 +#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS)) +#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3 +#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS)) + +#define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0 +#define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_FLASH_LVE_POS)) +#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8 +#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS)) + +#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0 +#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS)) +#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1 +#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS)) +#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2 +#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS)) +#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3 +#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS)) + +#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0 +#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS)) +#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1 +#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS)) +#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2 +#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS)) +#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3 +#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_FLC_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/gpio_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/gpio_regs.h new file mode 100644 index 0000000000..8a8122d8cc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/gpio_regs.h @@ -0,0 +1,477 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_GPIO_REGS_H_ +#define _MXC_GPIO_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file gpio_regs.h + * @addtogroup gpio GPIO + * @{ + */ + +/* Offset Register Description + ============= ========================================== */ +typedef struct { + __I uint32_t rsv000[16]; /* 0x0000-0x003C */ + + __IO uint32_t free[8]; /* 0x0040-0x005C Port P[0..7] Free for GPIO Operation Flags */ + __I uint32_t rsv060[8]; /* 0x0060-0x007C */ + + __IO uint32_t out_mode[8]; /* 0x0080-0x009C Port P[0..7] GPIO Output Drive Mode */ + __I uint32_t rsv0A0[8]; /* 0x00A0-0x00BC */ + + __IO uint32_t out_val[8]; /* 0x00C0-0x00DC Port P[0..7] GPIO Output Value */ + __I uint32_t rsv0E0[8]; /* 0x00E0-0x00FC */ + + __IO uint32_t func_sel[8]; /* 0x0100-0x011C Port P[0..7] GPIO Function Select */ + __I uint32_t rsv120[8]; /* 0x0120-0x013C */ + + __IO uint32_t in_mode[8]; /* 0x0140-0x015C Port P[0..7] GPIO Input Monitoring Mode */ + __I uint32_t rsv160[8]; /* 0x0160-0x017C */ + + __IO uint32_t in_val[8]; /* 0x0180-0x019C Port P[0..7] GPIO Input Value */ + __I uint32_t rsv1A0[8]; /* 0x01A0-0x01BC */ + + __IO uint32_t int_mode[8]; /* 0x01C0-0x01DC Port P[0..7] Interrupt Detection Mode */ + __I uint32_t rsv1E0[8]; /* 0x01E0-0x01FC */ + + __IO uint32_t intfl[8]; /* 0x0200-0x021C Port P[0..7] Interrupt Flags */ + __I uint32_t rsv220[8]; /* 0x0220-0x023C */ + + __IO uint32_t inten[8]; /* 0x0240-0x025C Port P[0..7] Interrupt Enables */ +} mxc_gpio_regs_t; + +/* + Register offsets for module GPIO. +*/ +#define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL) +#define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL) +#define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL) +#define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL) +#define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL) +#define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL) +#define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL) +#define MXC_R_GPIO_OFFS_FREE_P7 ((uint32_t)0x0000005CUL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P7 ((uint32_t)0x0000009CUL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P7 ((uint32_t)0x000000DCUL) +#define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL) +#define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL) +#define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL) +#define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL) +#define MXC_R_GPIO_OFFS_FUNC_SEL_P7 ((uint32_t)0x0000011CUL) +#define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL) +#define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P7 ((uint32_t)0x0000015CUL) +#define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL) +#define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P7 ((uint32_t)0x0000019CUL) +#define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL) +#define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P7 ((uint32_t)0x000001DCUL) +#define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL) +#define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL) +#define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL) +#define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL) +#define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL) +#define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL) +#define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL) +#define MXC_R_GPIO_OFFS_INTFL_P7 ((uint32_t)0x0000021CUL) +#define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL) +#define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL) +#define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL) +#define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL) +#define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL) +#define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL) +#define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL) +#define MXC_R_GPIO_OFFS_INTEN_P7 ((uint32_t)0x0000025CUL) + + +/* + Field positions and masks for module GPIO. +*/ +#define MXC_F_GPIO_FREE_PIN0_POS 0 +#define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS)) +#define MXC_F_GPIO_FREE_PIN1_POS 1 +#define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS)) +#define MXC_F_GPIO_FREE_PIN2_POS 2 +#define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS)) +#define MXC_F_GPIO_FREE_PIN3_POS 3 +#define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS)) +#define MXC_F_GPIO_FREE_PIN4_POS 4 +#define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS)) +#define MXC_F_GPIO_FREE_PIN5_POS 5 +#define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS)) +#define MXC_F_GPIO_FREE_PIN6_POS 6 +#define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS)) +#define MXC_F_GPIO_FREE_PIN7_POS 7 +#define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS)) + +#define MXC_F_GPIO_OUT_MODE_PIN0_POS 0 +#define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN1_POS 4 +#define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN2_POS 8 +#define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN3_POS 12 +#define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN4_POS 16 +#define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN5_POS 20 +#define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN6_POS 24 +#define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN7_POS 28 +#define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS)) + +#define MXC_F_GPIO_OUT_VAL_PIN0_POS 0 +#define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN1_POS 1 +#define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN2_POS 2 +#define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN3_POS 3 +#define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN4_POS 4 +#define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN5_POS 5 +#define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN6_POS 6 +#define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN7_POS 7 +#define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS)) + +#define MXC_F_GPIO_FUNC_SEL_PIN0_POS 0 +#define MXC_F_GPIO_FUNC_SEL_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN1_POS 4 +#define MXC_F_GPIO_FUNC_SEL_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN2_POS 8 +#define MXC_F_GPIO_FUNC_SEL_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN3_POS 12 +#define MXC_F_GPIO_FUNC_SEL_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN4_POS 16 +#define MXC_F_GPIO_FUNC_SEL_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN5_POS 20 +#define MXC_F_GPIO_FUNC_SEL_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN6_POS 24 +#define MXC_F_GPIO_FUNC_SEL_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN7_POS 28 +#define MXC_F_GPIO_FUNC_SEL_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS)) + +#define MXC_F_GPIO_IN_MODE_PIN0_POS 0 +#define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS)) +#define MXC_F_GPIO_IN_MODE_PIN1_POS 4 +#define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS)) +#define MXC_F_GPIO_IN_MODE_PIN2_POS 8 +#define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS)) +#define MXC_F_GPIO_IN_MODE_PIN3_POS 12 +#define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS)) +#define MXC_F_GPIO_IN_MODE_PIN4_POS 16 +#define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS)) +#define MXC_F_GPIO_IN_MODE_PIN5_POS 20 +#define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS)) +#define MXC_F_GPIO_IN_MODE_PIN6_POS 24 +#define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS)) +#define MXC_F_GPIO_IN_MODE_PIN7_POS 28 +#define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS)) + +#define MXC_F_GPIO_IN_VAL_PIN0_POS 0 +#define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS)) +#define MXC_F_GPIO_IN_VAL_PIN1_POS 1 +#define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS)) +#define MXC_F_GPIO_IN_VAL_PIN2_POS 2 +#define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS)) +#define MXC_F_GPIO_IN_VAL_PIN3_POS 3 +#define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS)) +#define MXC_F_GPIO_IN_VAL_PIN4_POS 4 +#define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS)) +#define MXC_F_GPIO_IN_VAL_PIN5_POS 5 +#define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS)) +#define MXC_F_GPIO_IN_VAL_PIN6_POS 6 +#define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS)) +#define MXC_F_GPIO_IN_VAL_PIN7_POS 7 +#define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS)) + +#define MXC_F_GPIO_INT_MODE_PIN0_POS 0 +#define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS)) +#define MXC_F_GPIO_INT_MODE_PIN1_POS 4 +#define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS)) +#define MXC_F_GPIO_INT_MODE_PIN2_POS 8 +#define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS)) +#define MXC_F_GPIO_INT_MODE_PIN3_POS 12 +#define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS)) +#define MXC_F_GPIO_INT_MODE_PIN4_POS 16 +#define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS)) +#define MXC_F_GPIO_INT_MODE_PIN5_POS 20 +#define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS)) +#define MXC_F_GPIO_INT_MODE_PIN6_POS 24 +#define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS)) +#define MXC_F_GPIO_INT_MODE_PIN7_POS 28 +#define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS)) + +#define MXC_F_GPIO_INTFL_PIN0_POS 0 +#define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS)) +#define MXC_F_GPIO_INTFL_PIN1_POS 1 +#define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS)) +#define MXC_F_GPIO_INTFL_PIN2_POS 2 +#define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS)) +#define MXC_F_GPIO_INTFL_PIN3_POS 3 +#define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS)) +#define MXC_F_GPIO_INTFL_PIN4_POS 4 +#define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS)) +#define MXC_F_GPIO_INTFL_PIN5_POS 5 +#define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS)) +#define MXC_F_GPIO_INTFL_PIN6_POS 6 +#define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS)) +#define MXC_F_GPIO_INTFL_PIN7_POS 7 +#define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS)) + +#define MXC_F_GPIO_INTEN_PIN0_POS 0 +#define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS)) +#define MXC_F_GPIO_INTEN_PIN1_POS 1 +#define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS)) +#define MXC_F_GPIO_INTEN_PIN2_POS 2 +#define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS)) +#define MXC_F_GPIO_INTEN_PIN3_POS 3 +#define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS)) +#define MXC_F_GPIO_INTEN_PIN4_POS 4 +#define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS)) +#define MXC_F_GPIO_INTEN_PIN5_POS 5 +#define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS)) +#define MXC_F_GPIO_INTEN_PIN6_POS 6 +#define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS)) +#define MXC_F_GPIO_INTEN_PIN7_POS 7 +#define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS)) + + +/* + Field values and shifted values for module GPIO. +*/ +#define MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN0_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN0_POS)) +#define MXC_S_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN0_AVAILABLE << MXC_F_GPIO_FREE_PIN0_POS)) + +#define MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN1_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN1_POS)) +#define MXC_S_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN1_AVAILABLE << MXC_F_GPIO_FREE_PIN1_POS)) + +#define MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN2_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN2_POS)) +#define MXC_S_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN2_AVAILABLE << MXC_F_GPIO_FREE_PIN2_POS)) + +#define MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN3_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN3_POS)) +#define MXC_S_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN3_AVAILABLE << MXC_F_GPIO_FREE_PIN3_POS)) + +#define MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN4_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN4_POS)) +#define MXC_S_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN4_AVAILABLE << MXC_F_GPIO_FREE_PIN4_POS)) + +#define MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN5_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN5_POS)) +#define MXC_S_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN5_AVAILABLE << MXC_F_GPIO_FREE_PIN5_POS)) + +#define MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN6_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN6_POS)) +#define MXC_S_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN6_AVAILABLE << MXC_F_GPIO_FREE_PIN6_POS)) + +#define MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN7_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN7_POS)) +#define MXC_S_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN7_AVAILABLE << MXC_F_GPIO_FREE_PIN7_POS)) + +#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL)) +#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL)) +#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL)) +#define MXC_V_GPIO_OUT_MODE_HIGH_Z ((uint32_t)(0x00000003UL)) +#define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL)) +#define MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE ((uint32_t)(0x00000005UL)) +#define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL)) +#define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL)) +#define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL)) +#define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL)) + +#define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS)) + +#define MXC_V_GPIO_INT_MODE_DISABLED ((uint32_t)(0x00000000UL)) +#define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL)) +#define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL)) +#define MXC_V_GPIO_INT_MODE_BOTH_EDGES ((uint32_t)(0x00000003UL)) +#define MXC_V_GPIO_INT_MODE_LOW_LEVEL ((uint32_t)(0x00000004UL)) +#define MXC_V_GPIO_INT_MODE_HIGH_LEVEL ((uint32_t)(0x00000005UL)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_GPIO_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/i2cm_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/i2cm_regs.h new file mode 100644 index 0000000000..173d3107a3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/i2cm_regs.h @@ -0,0 +1,192 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_I2CM_REGS_H_ +#define _MXC_I2CM_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file i2cm_regs.h + * @addtogroup i2cm I2CM + * @{ + */ + +/* Offset Register Description + ====== ================================================ */ +typedef struct { + __IO uint32_t fs_clk_div; /* 0x0000 Full Speed SCL Clock Settings */ + __IO uint32_t hs_clk_div; /* 0x0004 High Speed SCL Clock Settings */ + __I uint32_t rsv0008; /* 0x0008 */ + __IO uint32_t timeout; /* 0x000C [TO_CNTL] Timeout and Auto-Stop Settings */ + __IO uint32_t ctrl; /* 0x0010 [EN_CNTL] I2C Master Control Register */ + __IO uint32_t trans; /* 0x0014 [MSTR_CNTL] I2C Master Tx Start and Status Flags */ + __IO uint32_t intfl; /* 0x0018 Interrupt Flags */ + __IO uint32_t inten; /* 0x001C Interrupt Enable/Disable Controls */ + __I uint32_t rsv0020[2]; /* 0x0020 */ + __IO uint32_t bb; /* 0x0028 Bit-Bang Control Register */ +} mxc_i2cm_regs_t; + +/* Offset Register Description + ====== ================================================ */ +typedef struct { + __IO uint32_t trans[512]; /* 0x0000 I2C Master Transaction FIFO */ + __IO uint32_t rslts[512]; /* 0x0800 I2C Master Results FIFO */ +} mxc_i2cm_fifo_regs_t; + +/* + Register offsets for module I2CM. +*/ +#define MXC_R_I2CM_OFFS_FS_CLK_DIV ((uint32_t)0x00000000UL) +#define MXC_R_I2CM_OFFS_HS_CLK_DIV ((uint32_t)0x00000004UL) +#define MXC_R_I2CM_OFFS_TIMEOUT ((uint32_t)0x0000000CUL) +#define MXC_R_I2CM_OFFS_CTRL ((uint32_t)0x00000010UL) +#define MXC_R_I2CM_OFFS_TRANS ((uint32_t)0x00000014UL) +#define MXC_R_I2CM_OFFS_INTFL ((uint32_t)0x00000018UL) +#define MXC_R_I2CM_OFFS_INTEN ((uint32_t)0x0000001CUL) +#define MXC_R_I2CM_OFFS_BB ((uint32_t)0x00000028UL) +#define MXC_R_I2CM_OFFS_AHB_RETRY ((uint32_t)0x00000030UL) + +#define MXC_R_I2CM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL) +#define MXC_R_I2CM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL) + +/* + Field positions and masks for module I2CM. +*/ +#define MXC_S_I2CM_TRANS_TAG_START 0x000 +#define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK 0x100 +#define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK 0x200 +#define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT 0x400 +#define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK 0x500 +#define MXC_S_I2CM_TRANS_TAG_STOP 0x700 +#define MXC_S_I2CM_RSTLS_TAG_DATA 0x100 +#define MXC_S_I2CM_RSTLS_TAG_EMPTY 0x200 + +#define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS 0 +#define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS)) +#define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS 8 +#define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)) +#define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS 20 +#define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS)) + +#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS 16 +#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS)) +#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS 24 +#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS)) + +#define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS 2 +#define MXC_F_I2CM_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS)) +#define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS 3 +#define MXC_F_I2CM_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS)) +#define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS 7 +#define MXC_F_I2CM_CTRL_MSTR_RESET_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS)) + +#define MXC_F_I2CM_TRANS_TX_START_POS 0 +#define MXC_F_I2CM_TRANS_TX_START ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS)) +#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS 1 +#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS)) +#define MXC_F_I2CM_TRANS_TX_DONE_POS 2 +#define MXC_F_I2CM_TRANS_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS)) +#define MXC_F_I2CM_TRANS_TX_NACKED_POS 3 +#define MXC_F_I2CM_TRANS_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS)) +#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS 4 +#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS)) +#define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS 5 +#define MXC_F_I2CM_TRANS_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS)) + +#define MXC_F_I2CM_INTFL_TX_DONE_POS 0 +#define MXC_F_I2CM_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS)) +#define MXC_F_I2CM_INTFL_TX_NACKED_POS 1 +#define MXC_F_I2CM_INTFL_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS)) +#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS 2 +#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS)) +#define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS 3 +#define MXC_F_I2CM_INTFL_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS)) +#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS 4 +#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS)) +#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS 5 +#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS)) +#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS 6 +#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS)) +#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS 7 +#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS)) +#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS 8 +#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS)) +#define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS 9 +#define MXC_F_I2CM_INTFL_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS)) + +#define MXC_F_I2CM_INTEN_TX_DONE_POS 0 +#define MXC_F_I2CM_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS)) +#define MXC_F_I2CM_INTEN_TX_NACKED_POS 1 +#define MXC_F_I2CM_INTEN_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS)) +#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS 2 +#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS)) +#define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS 3 +#define MXC_F_I2CM_INTEN_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS)) +#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS 4 +#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS)) +#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS 5 +#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS)) +#define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS 6 +#define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS)) +#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS 7 +#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS)) +#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS 8 +#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS)) +#define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS 9 +#define MXC_F_I2CM_INTEN_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS)) + +#define MXC_F_I2CM_BB_BB_SCL_OUT_POS 0 +#define MXC_F_I2CM_BB_BB_SCL_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS)) +#define MXC_F_I2CM_BB_BB_SDA_OUT_POS 1 +#define MXC_F_I2CM_BB_BB_SDA_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS)) +#define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS 2 +#define MXC_F_I2CM_BB_BB_SCL_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS)) +#define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS 3 +#define MXC_F_I2CM_BB_BB_SDA_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS)) +#define MXC_F_I2CM_BB_RX_FIFO_CNT_POS 16 +#define MXC_F_I2CM_BB_RX_FIFO_CNT ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/icc_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/icc_regs.h new file mode 100644 index 0000000000..c8407a843c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/icc_regs.h @@ -0,0 +1,96 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_ICC_REGS_H_ +#define _MXC_ICC_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file icc_regs.h + * @addtogroup icc ICC + * @{ + */ + +/* Offset Register Description + ====== =================================================== */ +typedef struct { + __IO uint32_t id; /* 0x0000 Device ID Register */ + __IO uint32_t mem_cfg; /* 0x0004 Memory Configuration */ + __I uint32_t rsv0008[62]; /* 0x0008 */ + __IO uint32_t ctrl_stat; /* 0x0100 Control and Status */ + __I uint32_t rsv0104[383]; /* 0x0104 */ + __IO uint32_t invdt_all; /* 0x0700 Invalidate (Clear) Cache Control */ +} mxc_icc_regs_t; + +/* + Register offsets for module ICC. +*/ +#define MXC_R_ICC_OFFS_ID ((uint32_t)0x00000000UL) +#define MXC_R_ICC_OFFS_MEM_CFG ((uint32_t)0x00000004UL) +#define MXC_R_ICC_OFFS_CTRL_STAT ((uint32_t)0x00000100UL) +#define MXC_R_ICC_OFFS_INVDT_ALL ((uint32_t)0x00000700UL) + +/* + Field positions and masks for module ICC. +*/ +#define MXC_F_ICC_ID_RTL_VERSION_POS 0 +#define MXC_F_ICC_ID_RTL_VERSION ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_RTL_VERSION_POS)) +#define MXC_F_ICC_ID_PART_NUM_POS 6 +#define MXC_F_ICC_ID_PART_NUM ((uint32_t)(0x0000000FUL << MXC_F_ICC_ID_PART_NUM_POS)) +#define MXC_F_ICC_ID_CACHE_ID_POS 10 +#define MXC_F_ICC_ID_CACHE_ID ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_CACHE_ID_POS)) + +#define MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS 0 +#define MXC_F_ICC_MEM_CFG_CACHE_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS)) +#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS 16 +#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS)) + +#define MXC_F_ICC_CTRL_STAT_ENABLE_POS 0 +#define MXC_F_ICC_CTRL_STAT_ENABLE ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_ENABLE_POS)) +#define MXC_F_ICC_CTRL_STAT_READY_POS 16 +#define MXC_F_ICC_CTRL_STAT_READY ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_READY_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_ICC_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/ioman_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/ioman_regs.h new file mode 100644 index 0000000000..930a181595 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/ioman_regs.h @@ -0,0 +1,508 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_IOMAN_REGS_H_ +#define _MXC_IOMAN_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file ioman_regs.h + * @addtogroup ioman IO MUX Manager + * @{ + */ + +typedef enum { + /** Pin Mapping 'A' */ + MXC_E_IOMAN_MAPPING_A = 0, + /** Pin Mapping 'B' */ + MXC_E_IOMAN_MAPPING_B, + /** Pin Mapping 'C' */ + MXC_E_IOMAN_MAPPING_C, + /** Pin Mapping 'D' */ + MXC_E_IOMAN_MAPPING_D, + /** Pin Mapping 'E' */ + MXC_E_IOMAN_MAPPING_E, + /** Pin Mapping 'F' */ + MXC_E_IOMAN_MAPPING_F, + /** Pin Mapping 'G' */ + MXC_E_IOMAN_MAPPING_G, + /** Pin Mapping 'H' */ + MXC_E_IOMAN_MAPPING_H, +} ioman_mapping_t; + +/* Offset Register Description + ====== ========================================== */ +typedef struct { + __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 */ + __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 */ + __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 */ + __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 */ + __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 */ + __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 */ + __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 */ + __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 */ + __IO uint32_t spi0_req; /* 0x0020 SPI0 I/O Mode Request */ + __IO uint32_t spi0_ack; /* 0x0024 SPI0 I/O Mode Acknowledge */ + __IO uint32_t spi1_req; /* 0x0028 SPI1 I/O Mode Request */ + __IO uint32_t spi1_ack; /* 0x002C SPI1 I/O Mode Acknowledge */ + __IO uint32_t spi2_req; /* 0x0030 SPI2 I/O Mode Request */ + __IO uint32_t spi2_ack; /* 0x0034 SPI2 I/O Mode Acknowledge */ + __IO uint32_t uart0_req; /* 0x0038 UART0 I/O Mode Request */ + __IO uint32_t uart0_ack; /* 0x003C UART0 I/O Mode Acknowledge */ + __IO uint32_t uart1_req; /* 0x0040 UART1 I/O Mode Request */ + __IO uint32_t uart1_ack; /* 0x0044 UART1 I/O Mode Acknowledge */ + __IO uint32_t i2cm0_req; /* 0x0048 I2C Master 0 I/O Request */ + __IO uint32_t i2cm0_ack; /* 0x004C I2C Master 0 I/O Acknowledge */ + __IO uint32_t i2cs0_req; /* 0x0050 I2C Slave 0 I/O Request */ + __IO uint32_t i2s0_ack; /* 0x0054 I2C Slave 0 I/O Acknowledge */ + __IO uint32_t lcd_com_req; /* 0x0058 LCD COM Driver I/O Request */ + __IO uint32_t lcd_com_ack; /* 0x005C LCD COM Driver I/O Acknowledge */ + __IO uint32_t lcd_seg_req0; /* 0x0060 LCD SEG Driver I/O Request Register 0 */ + __IO uint32_t lcd_seg_req1; /* 0x0064 LCD SEG Driver I/O Request Register 1 */ + __IO uint32_t lcd_seg_ack0; /* 0x0068 LCD SEG Driver I/O Acknowledge Register 0 */ + __IO uint32_t lcd_seg_ack1; /* 0x006C LCD SEG Driver I/O Acknowledge Register 1 */ + __IO uint32_t crnt_req; /* 0x0070 Current Drive I/O Request Register */ + __IO uint32_t io_crnt_ack; /* 0x0074 Current Drive I/O Acknowledge Register */ + __IO uint32_t crnt_mode; /* 0x0078 Current Drive I/O Mode Control */ + __IO uint32_t ali_connect0; /* 0x007C Analog I/O Connection Control Register 0 */ + __IO uint32_t ali_connect1; /* 0x0080 Analog I/O Connection Control Register 1 */ + __IO uint32_t i2cm1_req; /* 0x0084 I2C Master 1 I/O Request */ + __IO uint32_t i2cm1_ack; /* 0x0088 I2C Master 1 I/O Acknowledge */ + __IO uint32_t padx_control; /* 0x008C PADX Control */ +} mxc_ioman_regs_t; + + +/* + Register offsets for module IOMAN. +*/ +#define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL) +#define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL) +#define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL) +#define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL) +#define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL) +#define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL) +#define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL) +#define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL) +#define MXC_R_IOMAN_OFFS_SPI0_REQ ((uint32_t)0x00000020UL) +#define MXC_R_IOMAN_OFFS_SPI0_ACK ((uint32_t)0x00000024UL) +#define MXC_R_IOMAN_OFFS_SPI1_REQ ((uint32_t)0x00000028UL) +#define MXC_R_IOMAN_OFFS_SPI1_ACK ((uint32_t)0x0000002CUL) +#define MXC_R_IOMAN_OFFS_SPI2_REQ ((uint32_t)0x00000030UL) +#define MXC_R_IOMAN_OFFS_SPI2_ACK ((uint32_t)0x00000034UL) +#define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000038UL) +#define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x0000003CUL) +#define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000040UL) +#define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x00000044UL) +#define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000048UL) +#define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x0000004CUL) +#define MXC_R_IOMAN_OFFS_I2CS0_REQ ((uint32_t)0x00000050UL) +#define MXC_R_IOMAN_OFFS_I2SC0_ACK ((uint32_t)0x00000054UL) +#define MXC_R_IOMAN_OFFS_LCD_COM_REQ ((uint32_t)0x00000058UL) +#define MXC_R_IOMAN_OFFS_LCD_COM_ACK ((uint32_t)0x0000005CUL) +#define MXC_R_IOMAN_OFFS_LCD_SEG_REQ0 ((uint32_t)0x00000060UL) +#define MXC_R_IOMAN_OFFS_LCD_SEG_REQ1 ((uint32_t)0x00000064UL) +#define MXC_R_IOMAN_OFFS_LCD_SEG_ACK0 ((uint32_t)0x00000068UL) +#define MXC_R_IOMAN_OFFS_LCD_SEG_ACK1 ((uint32_t)0x0000006CUL) +#define MXC_R_IOMAN_OFFS_IO_CRNT_REQ ((uint32_t)0x00000070UL) +#define MXC_R_IOMAN_OFFS_IO_CRNT_ACK ((uint32_t)0x00000074UL) +#define MXC_R_IOMAN_OFFS_IO_CRNT_MODE ((uint32_t)0x00000078UL) +#define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x0000007CUL) +#define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000080UL) +#define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000084UL) +#define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x00000088UL) +#define MXC_R_IOMAN_OFFS_PADX_CONTROL ((uint32_t)0x0000008CUL) + + +/* + Field positions and masks for module IOMAN. +*/ +#define MXC_F_IOMAN_WUD_REQ0_PORT0_POS 0 +#define MXC_F_IOMAN_WUD_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT0_POS)) +#define MXC_F_IOMAN_WUD_REQ0_PORT1_POS 8 +#define MXC_F_IOMAN_WUD_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT1_POS)) +#define MXC_F_IOMAN_WUD_REQ0_PORT2_POS 16 +#define MXC_F_IOMAN_WUD_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT2_POS)) +#define MXC_F_IOMAN_WUD_REQ0_PORT3_POS 24 +#define MXC_F_IOMAN_WUD_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT3_POS)) + +#define MXC_F_IOMAN_WUD_REQ1_PORT4_POS 0 +#define MXC_F_IOMAN_WUD_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT4_POS)) +#define MXC_F_IOMAN_WUD_REQ1_PORT5_POS 8 +#define MXC_F_IOMAN_WUD_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT5_POS)) +#define MXC_F_IOMAN_WUD_REQ1_PORT6_POS 16 +#define MXC_F_IOMAN_WUD_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT6_POS)) +#define MXC_F_IOMAN_WUD_REQ1_PORT7_POS 24 +#define MXC_F_IOMAN_WUD_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT7_POS)) + +#define MXC_F_IOMAN_WUD_ACK0_PORT0_POS 0 +#define MXC_F_IOMAN_WUD_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT0_POS)) +#define MXC_F_IOMAN_WUD_ACK0_PORT1_POS 8 +#define MXC_F_IOMAN_WUD_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT1_POS)) +#define MXC_F_IOMAN_WUD_ACK0_PORT2_POS 16 +#define MXC_F_IOMAN_WUD_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT2_POS)) +#define MXC_F_IOMAN_WUD_ACK0_PORT3_POS 24 +#define MXC_F_IOMAN_WUD_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT3_POS)) + +#define MXC_F_IOMAN_WUD_ACK1_PORT4_POS 0 +#define MXC_F_IOMAN_WUD_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT4_POS)) +#define MXC_F_IOMAN_WUD_ACK1_PORT5_POS 8 +#define MXC_F_IOMAN_WUD_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT5_POS)) +#define MXC_F_IOMAN_WUD_ACK1_PORT6_POS 16 +#define MXC_F_IOMAN_WUD_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT6_POS)) +#define MXC_F_IOMAN_WUD_ACK1_PORT7_POS 24 +#define MXC_F_IOMAN_WUD_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT7_POS)) + +#define MXC_F_IOMAN_ALI_REQ0_PORT0_POS 0 +#define MXC_F_IOMAN_ALI_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT0_POS)) +#define MXC_F_IOMAN_ALI_REQ0_PORT1_POS 8 +#define MXC_F_IOMAN_ALI_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT1_POS)) +#define MXC_F_IOMAN_ALI_REQ0_PORT2_POS 16 +#define MXC_F_IOMAN_ALI_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT2_POS)) +#define MXC_F_IOMAN_ALI_REQ0_PORT3_POS 24 +#define MXC_F_IOMAN_ALI_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT3_POS)) + +#define MXC_F_IOMAN_ALI_REQ1_PORT4_POS 0 +#define MXC_F_IOMAN_ALI_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT4_POS)) +#define MXC_F_IOMAN_ALI_REQ1_PORT5_POS 8 +#define MXC_F_IOMAN_ALI_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT5_POS)) +#define MXC_F_IOMAN_ALI_REQ1_PORT6_POS 16 +#define MXC_F_IOMAN_ALI_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT6_POS)) +#define MXC_F_IOMAN_ALI_REQ1_PORT7_POS 24 +#define MXC_F_IOMAN_ALI_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT7_POS)) + +#define MXC_F_IOMAN_ALI_ACK0_PORT0_POS 0 +#define MXC_F_IOMAN_ALI_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT0_POS)) +#define MXC_F_IOMAN_ALI_ACK0_PORT1_POS 8 +#define MXC_F_IOMAN_ALI_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT1_POS)) +#define MXC_F_IOMAN_ALI_ACK0_PORT2_POS 16 +#define MXC_F_IOMAN_ALI_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT2_POS)) +#define MXC_F_IOMAN_ALI_ACK0_PORT3_POS 24 +#define MXC_F_IOMAN_ALI_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT3_POS)) + +#define MXC_F_IOMAN_ALI_ACK1_PORT4_POS 0 +#define MXC_F_IOMAN_ALI_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT4_POS)) +#define MXC_F_IOMAN_ALI_ACK1_PORT5_POS 8 +#define MXC_F_IOMAN_ALI_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT5_POS)) +#define MXC_F_IOMAN_ALI_ACK1_PORT6_POS 16 +#define MXC_F_IOMAN_ALI_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT6_POS)) +#define MXC_F_IOMAN_ALI_ACK1_PORT7_POS 24 +#define MXC_F_IOMAN_ALI_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT7_POS)) + +#define MXC_F_IOMAN_SPI_MAPPING_POS 0 +#define MXC_F_IOMAN_SPI_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPI_MAPPING_POS)) +#define MXC_F_IOMAN_SPI_CORE_IO_POS 4 +#define MXC_F_IOMAN_SPI_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_CORE_IO_POS)) +#define MXC_F_IOMAN_SPI_SS0_IO_POS 8 +#define MXC_F_IOMAN_SPI_SS0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS0_IO_POS)) +#define MXC_F_IOMAN_SPI_SS1_IO_POS 9 +#define MXC_F_IOMAN_SPI_SS1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS1_IO_POS)) +#define MXC_F_IOMAN_SPI_SS2_IO_POS 10 +#define MXC_F_IOMAN_SPI_SS2_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS2_IO_POS)) +#define MXC_F_IOMAN_SPI_SS3_IO_POS 11 +#define MXC_F_IOMAN_SPI_SS3_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS3_IO_POS)) +#define MXC_F_IOMAN_SPI_SS4_IO_POS 12 +#define MXC_F_IOMAN_SPI_SS4_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS4_IO_POS)) +#define MXC_F_IOMAN_SPI_SR0_IO_POS 16 +#define MXC_F_IOMAN_SPI_SR0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR0_IO_POS)) +#define MXC_F_IOMAN_SPI_SR1_IO_POS 17 +#define MXC_F_IOMAN_SPI_SR1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR1_IO_POS)) +#define MXC_F_IOMAN_SPI_QUAD_IO_POS 20 +#define MXC_F_IOMAN_SPI_QUAD_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_QUAD_IO_POS)) +#define MXC_F_IOMAN_SPI_FAST_MODE_POS 24 +#define MXC_F_IOMAN_SPI_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_FAST_MODE_POS)) + +#define MXC_F_IOMAN_UART_MAPPING_POS 0 +#define MXC_F_IOMAN_UART_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_UART_MAPPING_POS)) +#define MXC_F_IOMAN_UART_CORE_IO_POS 4 +#define MXC_F_IOMAN_UART_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CORE_IO_POS)) +#define MXC_F_IOMAN_UART_CTS_IO_POS 5 +#define MXC_F_IOMAN_UART_CTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CTS_IO_POS)) +#define MXC_F_IOMAN_UART_RTS_IO_POS 6 +#define MXC_F_IOMAN_UART_RTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_RTS_IO_POS)) + +#define MXC_F_IOMAN_I2CM_MAPPING_POS 0 +#define MXC_F_IOMAN_I2CM_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM_MAPPING_POS)) +#define MXC_F_IOMAN_I2CM_CORE_IO_POS 4 +#define MXC_F_IOMAN_I2CM_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM_CORE_IO_POS)) + +#define MXC_F_IOMAN_I2CS_MAPPING_POS 0 +#define MXC_F_IOMAN_I2CS_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_MAPPING_POS)) +#define MXC_F_IOMAN_I2CS_CORE_IO_POS 4 +#define MXC_F_IOMAN_I2CS_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_CORE_IO_POS)) + +#define MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS 0 +#define MXC_F_IOMAN_LCD_COM_REQ_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS)) + +#define MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS 0 +#define MXC_F_IOMAN_LCD_COM_ACK_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS)) + +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS 0 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS 1 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS 2 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS 3 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS 4 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS 5 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS 6 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS 7 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS 8 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS 9 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS 10 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS 11 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS 12 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS 13 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS 14 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS 15 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS 16 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS 17 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS 18 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS 19 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS 20 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS 21 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS 22 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS 23 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS 24 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS 25 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS 26 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS 27 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS 28 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS 29 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS 30 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS 31 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS)) + +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS 0 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS 1 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS 2 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS 3 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS 4 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS 5 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS 6 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS 7 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS)) + +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS 0 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS 1 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS 2 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS 3 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS 4 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS 5 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS 6 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS 7 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS 8 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS 9 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS 10 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS 11 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS 12 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS 13 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS 14 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS 15 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS 16 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS 17 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS 18 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS 19 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS 20 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS 21 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS 22 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS 23 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS 24 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS 25 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS 26 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS 27 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS 28 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS 29 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS 30 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS 31 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS)) + +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS 0 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS 1 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS 2 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS 3 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS 4 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS 5 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS 6 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS 7 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS)) + +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS 0 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS 1 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS 2 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS 3 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS 4 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS 5 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS 6 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS 7 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS)) + +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS 0 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS 1 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS 2 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS 3 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS 4 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS 5 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS 6 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS 7 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS)) + +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS 0 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS 4 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS 8 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS 12 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS 16 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS 20 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS 24 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS 28 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS)) + +#define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS 0 +#define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS)) +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS 4 +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS)) +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS 6 +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS)) +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS 8 +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS)) +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS 10 +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_IOMAN_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/maa_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/maa_regs.h new file mode 100644 index 0000000000..e8c80c712b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/maa_regs.h @@ -0,0 +1,124 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_MAA_REGS_H_ +#define _MXC_MAA_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file maa_regs.h + * @addtogroup maa MAA + * @{ + */ + +/* Offset Register Description + ====== ========================================================== */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 MAA Control, Configuration and Status */ + __IO uint32_t maws; /* 0x0004 MAA Word (Operand) Size, Big/Little Endian Mode Select */ +} mxc_maa_regs_t; + +/* Offset Register Description + ====== ========================================================== */ +typedef struct { + __IO uint32_t seg0[16]; /* 0x0000 [64 bytes] MAA Memory Segment 0 */ + __IO uint32_t seg1[16]; /* 0x0040 [64 bytes] MAA Memory Segment 1 */ + __IO uint32_t seg2[16]; /* 0x0080 [64 bytes] MAA Memory Segment 2 */ + __IO uint32_t seg3[16]; /* 0x00C0 [64 bytes] MAA Memory Segment 3 */ + __IO uint32_t seg4[16]; /* 0x0100 [64 bytes] MAA Memory Segment 4 */ + __IO uint32_t seg5[16]; /* 0x0140 [64 bytes] MAA Memory Segment 5 */ +} mxc_maa_mem_regs_t; + +/* + Register offsets for module MAA. +*/ +#define MXC_R_MAA_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_MAA_OFFS_MAWS ((uint32_t)0x00000004UL) +#define MXC_R_MAA_MEM_OFFS_SEG0 ((uint32_t)0x00000000UL) +#define MXC_R_MAA_MEM_OFFS_SEG1 ((uint32_t)0x00000040UL) +#define MXC_R_MAA_MEM_OFFS_SEG2 ((uint32_t)0x00000080UL) +#define MXC_R_MAA_MEM_OFFS_SEG3 ((uint32_t)0x000000C0UL) +#define MXC_R_MAA_MEM_OFFS_SEG4 ((uint32_t)0x00000100UL) +#define MXC_R_MAA_MEM_OFFS_SEG5 ((uint32_t)0x00000140UL) + +/* + Field positions and masks for module MAA. +*/ +#define MXC_F_MAA_CTRL_START_POS 0 +#define MXC_F_MAA_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_START_POS)) +#define MXC_F_MAA_CTRL_OPSEL_POS 1 +#define MXC_F_MAA_CTRL_OPSEL ((uint32_t)(0x00000007UL << MXC_F_MAA_CTRL_OPSEL_POS)) +#define MXC_F_MAA_CTRL_OCALC_POS 4 +#define MXC_F_MAA_CTRL_OCALC ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_OCALC_POS)) +#define MXC_F_MAA_CTRL_INTEN_POS 5 +#define MXC_F_MAA_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_INTEN_POS)) +#define MXC_F_MAA_CTRL_IF_DONE_POS 6 +#define MXC_F_MAA_CTRL_IF_DONE ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_DONE_POS)) +#define MXC_F_MAA_CTRL_IF_ERROR_POS 7 +#define MXC_F_MAA_CTRL_IF_ERROR ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_ERROR_POS)) +#define MXC_F_MAA_CTRL_OFS_A_POS 8 +#define MXC_F_MAA_CTRL_OFS_A ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_A_POS)) +#define MXC_F_MAA_CTRL_OFS_B_POS 10 +#define MXC_F_MAA_CTRL_OFS_B ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_B_POS)) +#define MXC_F_MAA_CTRL_OFS_EXP_POS 12 +#define MXC_F_MAA_CTRL_OFS_EXP ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_EXP_POS)) +#define MXC_F_MAA_CTRL_OFS_MOD_POS 14 +#define MXC_F_MAA_CTRL_OFS_MOD ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_MOD_POS)) +#define MXC_F_MAA_CTRL_SEG_A_POS 16 +#define MXC_F_MAA_CTRL_SEG_A ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_A_POS)) +#define MXC_F_MAA_CTRL_SEG_B_POS 20 +#define MXC_F_MAA_CTRL_SEG_B ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_B_POS)) +#define MXC_F_MAA_CTRL_SEG_RES_POS 24 +#define MXC_F_MAA_CTRL_SEG_RES ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_RES_POS)) +#define MXC_F_MAA_CTRL_SEG_TMP_POS 28 +#define MXC_F_MAA_CTRL_SEG_TMP ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_TMP_POS)) + +#define MXC_F_MAA_MAWS_MODLEN_POS 0 +#define MXC_F_MAA_MAWS_MODLEN ((uint32_t)(0x000003FFUL << MXC_F_MAA_MAWS_MODLEN_POS)) +#define MXC_F_MAA_MAWS_BYTESWAP_POS 16 +#define MXC_F_MAA_MAWS_BYTESWAP ((uint32_t)(0x00000001UL << MXC_F_MAA_MAWS_BYTESWAP_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_MAA_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h new file mode 100644 index 0000000000..182a9078fe --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h @@ -0,0 +1,655 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MAX32610_H_ +#define _MAX32610_H_ + +#include + +typedef enum IRQn_Type { + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + /* Externals interrupts */ + UART0_IRQn = 0, /* 16:01 UART0 */ + UART1_IRQn, /* 17: 2 UART1 */ + I2CM0_IRQn, /* 18: 3 I2C Master 0 */ + I2CS_IRQn, /* 19: 4 I2C Slave */ + USB_IRQn, /* 20: 5 USB */ + PMU_IRQn, /* 21: 6 DMA */ + AFE_IRQn, /* 22: 7 AFE */ + MAA_IRQn, /* 23: 8 MAA */ + AES_IRQn, /* 24: 9 AES */ + SPI0_IRQn, /* 25:10 SPI0 */ + SPI1_IRQn, /* 26:11 SPI1 */ + SPI2_IRQn, /* 27:12 SPI2 */ + TMR0_IRQn, /* 28:13 Timer32-0 */ + TMR1_IRQn, /* 29:14 Timer32-1 */ + TMR2_IRQn, /* 30:15 Timer32-1 */ + TMR3_IRQn, /* 31:16 Timer32-2 */ + RSVD0_IRQn, /* 32:17 RSVD */ + RSVD1_IRQn, /* 33:18 RSVD */ + DAC0_IRQn, /* 34:19 DAC0 (12-bit DAC) */ + DAC1_IRQn, /* 35:20 DAC1 (12-bit DAC) */ + DAC2_IRQn, /* 36:21 DAC2 (8-bit DAC) */ + DAC3_IRQn, /* 37:22 DAC3 (8-bit DAC) */ + ADC_IRQn, /* 38:23 ADC */ + FLC_IRQn, /* 39:24 Flash Controller */ + PWRMAN_IRQn, /* 40:25 PWRMAN */ + CLKMAN_IRQn, /* 41:26 CLKMAN */ + RTC0_IRQn, /* 42:27 RTC INT0 */ + RTC1_IRQn, /* 43:28 RTC INT1 */ + RTC2_IRQn, /* 44:29 RTC INT2 */ + RTC3_IRQn, /* 45:30 RTC INT3 */ + WDT0_IRQn, /* 46:31 WATCHDOG0 */ + WDT0_P_IRQn, /* 47:32 WATCHDOG0 PRE-WINDOW */ + WDT1_IRQn, /* 48:33 WATCHDOG1 */ + WDT1_P_IRQn, /* 49:34 WATCHDOG1 PRE-WINDOW */ + GPIO_P0_IRQn, /* 50:35 GPIO Port 0 */ + GPIO_P1_IRQn, /* 51:36 GPIO Port 1 */ + GPIO_P2_IRQn, /* 52:37 GPIO Port 2 */ + GPIO_P3_IRQn, /* 53:38 GPIO Port 3 */ + GPIO_P4_IRQn, /* 54:39 GPIO Port 4 */ + GPIO_P5_IRQn, /* 55:40 GPIO Port 5 */ + GPIO_P6_IRQn, /* 56:41 GPIO Port 6 */ + GPIO_P7_IRQn, /* 57:42 GPIO Port 7 */ + TMR16_0_IRQn, /* 58:43 Timer16-s0 */ + TMR16_1_IRQn, /* 59:44 Timer16-s1 */ + TMR16_2_IRQn, /* 60:45 Timer16-s2 */ + TMR16_3_IRQn, /* 61:46 Timer16-s3 */ + I2CM1_IRQn, /* 62:47 I2C Master 1 */ + MXC_IRQ_EXT_COUNT, +} IRQn_Type; + +#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ + +#include /* Processor and core peripherals */ +#include "system_max32610.h" /* System Header */ + + +/* ================================================================================ */ +/* ================== Device Specific Memory Section ================== */ +/* ================================================================================ */ + +#define MXC_FLASH_MEM_BASE 0x00000000UL +#define MXC_FLASH_PAGE_SIZE 0x1000 // 256 x 128b = 4KB +#define MXC_FLASH_MEM_SIZE 0x00040000UL +#define MXC_SYS_MEM_BASE 0x20000000UL + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/*******************************************************************************/ +/* General Purpose I/O Ports (GPIO) */ + + +#define MXC_BASE_GPIO ((uint32_t)0x40000000UL) +#define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO) +#define MXC_BASE_GPIO_BITBAND ((uint32_t)0x42000000UL) + +#define MXC_GPIO_GET_IRQ(i) (((unsigned int)i) + GPIO_P0_IRQn) + + +/*******************************************************************************/ +/* Pulse Train Generation */ + +#define MXC_CFG_PT_INSTANCES (13) + +#define MXC_BASE_PTG ((uint32_t)0x40001000UL) +#define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG) +#define MXC_BASE_PT ((uint32_t)0x40001008UL) +#define MXC_PT ((mxc_pt_regs_t *)MXC_BASE_PT) +#define MXC_BASE_PT0 ((uint32_t)0x40001008UL) +#define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0) +#define MXC_BASE_PT1 ((uint32_t)0x40001010UL) +#define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1) +#define MXC_BASE_PT2 ((uint32_t)0x40001018UL) +#define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2) +#define MXC_BASE_PT3 ((uint32_t)0x40001020UL) +#define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3) +#define MXC_BASE_PT4 ((uint32_t)0x40001028UL) +#define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4) +#define MXC_BASE_PT5 ((uint32_t)0x40001030UL) +#define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5) +#define MXC_BASE_PT6 ((uint32_t)0x40001038UL) +#define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6) +#define MXC_BASE_PT7 ((uint32_t)0x40001040UL) +#define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7) + +/* PT12, PT13, PT14 are not used */ + +/*******************************************************************************/ +/* CRC-16/CRC-32 Engine */ + +#define MXC_BASE_CRC ((uint32_t)0x40010000UL) +#define MXC_CRC_REGS ((mxc_crc_regs_t *)MXC_BASE_CRC) + +#define MXC_BASE_CRC_DATA ((uint32_t)0x4010B000UL) +#define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA) + +/*******************************************************************************/ +/* Trust Protection Unit (TPU) */ + +#define MXC_BASE_TPU ((uint32_t)0x40011000UL) +#define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU) + +#define MXC_BASE_TPU_TSR ((uint32_t)0x40011C00UL) +#define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR) + +/*******************************************************************************/ +/* AES Cryptographic Engine */ + +#define MXC_BASE_AES ((uint32_t)0x40011400UL) +#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES) + +#define MXC_BASE_AES_MEM ((uint32_t)0x4010A000UL) +#define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM) + + +/*******************************************************************************/ +/* MAA Cryptographic Engine */ + +#define MXC_BASE_MAA ((uint32_t)0x40011800UL) +#define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA) + +#define MXC_BASE_MAA_MEM ((uint32_t)0x4010A800UL) +#define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM) + +/*******************************************************************************/ +/* 32-Bit PWM Timer/Counter */ + +#define MXC_CFG_TMR_INSTANCES (4) + +#define MXC_BASE_TMR0 ((uint32_t)0x40012000UL) +#define MXC_BASE_TMR0_BITBAND ((uint32_t)0x42240000UL) +#define MXC_TMR0 ((mxc_tmr_regs_t *) MXC_BASE_TMR0) + +#define MXC_BASE_TMR1 ((uint32_t)0x40013000UL) +#define MXC_BASE_TMR1_BITBAND ((uint32_t)0x42260000UL) +#define MXC_TMR1 ((mxc_tmr_regs_t *) MXC_BASE_TMR1) + +#define MXC_BASE_TMR2 ((uint32_t)0x40014000UL) +#define MXC_BASE_TMR2_BITBAND ((uint32_t)0x42280000UL) +#define MXC_TMR2 ((mxc_tmr_regs_t *) MXC_BASE_TMR2) + +#define MXC_BASE_TMR3 ((uint32_t)0x40015000UL) +#define MXC_BASE_TMR3_BITBAND ((uint32_t)0x422A0000UL) +#define MXC_TMR3 ((mxc_tmr_regs_t *) MXC_BASE_TMR3) + + +#define MXC_TMR_GET_IRQ_32(i) ((i) == 0 ? TMR0_IRQn : \ + (i) == 1 ? TMR1_IRQn : \ + (i) == 2 ? TMR2_IRQn : \ + (i) == 3 ? TMR3_IRQn : 0) + +#define MXC_TMR_GET_IRQ_16(i) ((i) == 0 ? TMR0_IRQn : \ + (i) == 1 ? TMR1_IRQn : \ + (i) == 2 ? TMR2_IRQn : \ + (i) == 3 ? TMR3_IRQn : \ + (i) == 4 ? TMR16_0_IRQn : \ + (i) == 5 ? TMR16_1_IRQn : \ + (i) == 6 ? TMR16_2_IRQn : \ + (i) == 7 ? TMR16_3_IRQn : 0) + +#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \ + (i) == 1 ? MXC_BASE_TMR1 : \ + (i) == 2 ? MXC_BASE_TMR2 : \ + (i) == 3 ? MXC_BASE_TMR3 : 0) + +#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \ + (i) == 1 ? MXC_TMR1 : \ + (i) == 2 ? MXC_TMR2 : \ + (i) == 3 ? MXC_TMR3 : 0) +/*******************************************************************************/ +/* Watchdog Timer */ + +#define MXC_CFG_WDT_INSTANCES (2) + +#define MXC_BASE_WDT0 ((uint32_t)0x40021000UL) +#define MXC_BASE_WDT0_BITBAND ((uint32_t)0x42420000UL) +#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) + +#define MXC_BASE_WDT1 ((uint32_t)0x40022000UL) +#define MXC_BASE_WDT1_BITBAND ((uint32_t)0x42440000UL) +#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) + +#define MXC_WDT_GET_IRQ(i) ((i) == 0 ? WDT0_IRQn : \ + (i) == 1 ? WDT1_IRQn : 0) + +#define MXC_WDT_GET_IRQ_P(i) ((i) == 0 ? WDT0_P_IRQn : \ + (i) == 1 ? WDT1_P_IRQn : 0) + +#define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \ + (i) == 1 ? MXC_BASE_WDT1 : 0) + +#define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \ + (i) == 1 ? MXC_WDT1 : 0) + +/*******************************************************************************/ +/* SPI Interface */ + +#define MXC_CFG_SPI_INSTANCES (3) +#define MXC_CFG_SPI_FIFO_DEPTH (16) + +#define MXC_BASE_SPI0 ((uint32_t)0x40030000UL) +#define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0) + +#define MXC_BASE_SPI0_TXFIFO ((uint32_t)0x40100000UL) +#define MXC_SPI0_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI0_TXFIFO) +#define MXC_BASE_SPI0_RXFIFO ((uint32_t)0x40100800UL) +#define MXC_SPI0_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI0_RXFIFO) + +#define MXC_BASE_SPI1 ((uint32_t)0x40031000UL) +#define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1) + +#define MXC_BASE_SPI1_TXFIFO ((uint32_t)0x40101000UL) +#define MXC_SPI1_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI1_TXFIFO) +#define MXC_BASE_SPI1_RXFIFO ((uint32_t)0x40101800UL) +#define MXC_SPI1_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI1_RXFIFO) + +#define MXC_BASE_SPI2 ((uint32_t)0x40032000UL) +#define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2) + +#define MXC_BASE_SPI2_TXFIFO ((uint32_t)0x40102000UL) +#define MXC_SPI2_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI2_TXFIFO) +#define MXC_BASE_SPI2_RXFIFO ((uint32_t)0x40102800UL) +#define MXC_SPI2_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI2_RXFIFO) + + +#define MXC_SPI_GET_IRQ(i) ((i) == 0 ? SPI0_IRQn : \ + (i) == 1 ? SPI1_IRQn : \ + (i) == 2 ? SPI2_IRQn : 0) + +#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \ + (i) == 1 ? MXC_BASE_SPI1 : \ + (i) == 2 ? MXC_BASE_SPI2 : 0) + +#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \ + (i) == 1 ? MXC_SPI1 : \ + (i) == 2 ? MXC_SPI2 : 0) + +#define MXC_SPI_GET_RXFIFO(i) ((i) == 0 ? MXC_SPI0_RXFIFO : \ + (i) == 1 ? MXC_SPI1_RXFIFO : \ + (i) == 2 ? MXC_SPI2_RXFIFO : 0) + +#define MXC_SPI_GET_TXFIFO(i) ((i) == 0 ? MXC_SPI0_TXFIFO : \ + (i) == 1 ? MXC_SPI1_TXFIFO : \ + (i) == 2 ? MXC_SPI2_TXFIFO : 0) + +#define MXC_SPI_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_SPI0) +#define MXC_SPI_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00003000) >> 12) + + +/*******************************************************************************/ +/* UART Interface */ + +#define MXC_CFG_UART_INSTANCES (2) + +#define MXC_BASE_UART0 ((uint32_t)0x40038000UL) +#define MXC_BASE_UART0_BITBAND ((uint32_t)0x42700000UL) +#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) + +#define MXC_BASE_UART1 ((uint32_t)0x40039000UL) +#define MXC_BASE_UART1_BITBAND ((uint32_t)0x42720000UL) +#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) + + +#define MXC_UART_GET_IRQ(i) ((i) == 0 ? UART0_IRQn : \ + (i) == 1 ? UART1_IRQn : 0) + +#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \ + (i) == 1 ? MXC_BASE_UART1 : 0) + +#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \ + (i) == 1 ? MXC_UART1 : 0) + +#define MXC_UART_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_UART0) +#define MXC_UART_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00001000) >> 12) + + +/*******************************************************************************/ +/* I2C Master Interface */ + +#define MXC_CFG_I2CM_INSTANCES (2) + +#define MXC_BASE_I2CM0 ((uint32_t)0x40040000UL) +#define MXC_BASE_I2CM0_BITBAND ((uint32_t)0x42800000UL) +#define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0) +#define MXC_BASE_I2CM0_TX_FIFO ((uint32_t)0x40103000UL) +#define MXC_BASE_I2CM0_RX_FIFO ((uint32_t)0x40103800UL) + +#define MXC_BASE_I2CM1 ((uint32_t)0x40042000UL) +#define MXC_BASE_I2CM1_BITBAND ((uint32_t)0x42840000UL) +#define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1) +#define MXC_BASE_I2CM1_TX_FIFO ((uint32_t)0x4010D000UL) +#define MXC_BASE_I2CM1_RX_FIFO ((uint32_t)0x4010D800UL) + +#define MXC_I2CM_GET_IRQ(i) ((i) == 0 ? I2CM0_IRQn : \ + (i) == 1 ? I2CM1_IRQn : 0) + +#define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \ + (i) == 1 ? MXC_BASE_I2CM1 : 0) + +#define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \ + (i) == 1 ? MXC_I2CM1 : 0) + +#define MXC_I2CM_GET_BASE_TX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_TX_FIFO : \ + (i) == 1 ? MXC_BASE_I2CM1_TX_FIFO : 0) + +#define MXC_I2CM_GET_BASE_RX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_RX_FIFO : \ + (i) == 1 ? MXC_BASE_I2CM1_RX_FIFO : 0) + +#define MXC_I2CM_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 13) + MXC_BASE_I2CM0) +#define MXC_I2CM_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00002000) >> 13) + + +/*******************************************************************************/ +/* I2C Slave Interface */ + +#define MXC_CFG_I2CS_INSTANCES (1) + +#define MXC_BASE_I2CS0 ((uint32_t)0x40041000UL) +#define MXC_BASE_I2CS0_BITBAND ((uint32_t)0x42820000UL) +#define MXC_I2CS0 ((mxc_i2cs_regs_t *)MXC_BASE_I2CS0) + +#define MXC_BASE_I2CS0_FIFO ((uint32_t)0x40104000UL) +#define MXC_I2CS0_FIFO ((mxc_i2cs_fifo_regs_t *)MXC_BASE_I2CS0) + + + +/*******************************************************************************/ +/* DACs */ + +#define MXC_CFG_DAC_INSTANCES (4) +#define MXC_CFG_DAC_FIFO_DEPTH (32) + +#define MXC_BASE_DAC0 ((uint32_t)0x40050000UL) +#define MXC_DAC0 ((mxc_dac_regs_t *)MXC_BASE_DAC0) +#define MXC_BASE_DAC0_FIFO ((uint32_t)0x40105000UL) +#define MXC_DAC0_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC0_FIFO) +#define MXC_DAC0_WIDTH ((uint8_t)(2)) + +#define MXC_BASE_DAC1 ((uint32_t)0x40051000UL) +#define MXC_DAC1 ((mxc_dac_regs_t *)MXC_BASE_DAC1) +#define MXC_BASE_DAC1_FIFO ((uint32_t)0x40106000UL) +#define MXC_DAC1_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC1_FIFO) +#define MXC_DAC1_WIDTH ((uint8_t)(2)) + +#define MXC_BASE_DAC2 ((uint32_t)0x40052000UL) +#define MXC_DAC2 ((mxc_dac_regs_t *)MXC_BASE_DAC2) +#define MXC_BASE_DAC2_FIFO ((uint32_t)0x40107000UL) +#define MXC_DAC2_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC2_FIFO) +#define MXC_DAC2_WIDTH ((uint8_t)(1)) + +#define MXC_BASE_DAC3 ((uint32_t)0x40053000UL) +#define MXC_DAC3 ((mxc_dac_regs_t *)MXC_BASE_DAC3) +#define MXC_BASE_DAC3_FIFO ((uint32_t)0x40108000UL) +#define MXC_DAC3_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC3_FIFO) +#define MXC_DAC3_WIDTH ((uint8_t)(1)) + + +#define MXC_DAC_GET_IRQ(i) ((i) == 0 ? DAC0_IRQn : \ + (i) == 1 ? DAC1_IRQn : \ + (i) == 2 ? DAC2_IRQn : \ + (i) == 3 ? DAC3_IRQn : 0) + + +#define MXC_DAC_GET_BASE(i) (i == 0 ? MXC_BASE_DAC0 : \ + i == 1 ? MXC_BASE_DAC1 : \ + i == 2 ? MXC_BASE_DAC2 : \ + i == 3 ? MXC_BASE_DAC3 : 0) + +#define MXC_DAC_GET_FIFO(i) (i == 0 ? MXC_BASE_DAC0_FIFO : \ + i == 1 ? MXC_BASE_DAC1_FIFO : \ + i == 2 ? MXC_BASE_DAC2_FIFO : \ + i == 3 ? MXC_BASE_DAC3_FIFO : 0) + +#define MXC_DAC_GET_PMU_FIFO_IRQ(i) (i == 0 ? PMU_IRQ_DAC0_FIFO_AE : \ + i == 1 ? PMU_IRQ_DAC1_FIFO_AE : \ + i == 2 ? PMU_IRQ_DAC2_FIFO_AE : \ + i == 3 ? PMU_IRQ_DAC3_FIFO_AE : 0) + +#define MXC_DAC_GET_DAC(i) (i == 0 ? MXC_DAC0 : \ + i == 1 ? MXC_DAC1 : \ + i == 2 ? MXC_DAC2 : \ + i == 3 ? MXC_DAC3 : 0) + +#define MXC_DAC_GET_WIDTH(i) (i == 0 ? MXC_DAC0_WIDTH : \ + i == 1 ? MXC_DAC1_WIDTH : \ + i == 2 ? MXC_DAC2_WIDTH : \ + i == 3 ? MXC_DAC3_WIDTH : 0) + + +/*******************************************************************************/ +/* Analog Front End */ + +#define MXC_BASE_AFE ((uint32_t)0x4005401CUL) +#define MXC_AFE ((mxc_afe_regs_t *)MXC_BASE_AFE) + + + +/*******************************************************************************/ +/* ADC */ + +#define MXC_CFG_ADC_FIFO_DEPTH ((uint32_t)(32)) + +#define MXC_BASE_ADC ((uint32_t)0x40054000UL) +#define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC) + +#define MXC_BASE_ADCCFG ((uint32_t)0x40054038UL) +#define MXC_ADCCFG ((mxc_adccfg_regs_t *)MXC_BASE_ADCCFG) + +#define MXC_BASE_ADC_FIFO ((uint32_t)0x40109000UL) +#define MXC_ADC_FIFO ((mxc_adc_fifo_regs_t *)MXC_BASE_ADC_FIFO) + + + +/*******************************************************************************/ +/* Peripheral Management Unit (PMU) - formerly DMA Controller */ + +#define MXC_CFG_PMU_CHANNELS (6) + +#define MXC_BASE_PMU0 ((uint32_t)0x40070000UL) +#define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0) +#define MXC_BASE_PMU1 ((uint32_t)0x40070020UL) +#define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1) +#define MXC_BASE_PMU2 ((uint32_t)0x40070040UL) +#define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2) +#define MXC_BASE_PMU3 ((uint32_t)0x40070060UL) +#define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3) +#define MXC_BASE_PMU4 ((uint32_t)0x40070080UL) +#define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4) +#define MXC_BASE_PMU5 ((uint32_t)0x400700A0UL) +#define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5) + +#define MXC_BASE_PMU_BITBAND ((uint32_t)0x42E00000UL) +#define MXC_BASE_PMU_BITBAND_CHOFFSET ((uint32_t)0x00000400UL) +/*******************************************************************************/ + +typedef enum { + PMU_IRQ_DAC0_FIFO_AE, + PMU_IRQ_DAC1_FIFO_AE, + PMU_IRQ_DAC2_FIFO_AE, + PMU_IRQ_DAC3_FIFO_AE, + PMU_IRQ_DAC0_DONE, + PMU_IRQ_DAC1_DONE, + PMU_IRQ_DAC2_DONE, + PMU_IRQ_DAC3_DONE, + PMU_IRQ_ADC_FIFO_AF, + PMU_IRQ_ADC_DONE, + PMU_IRQ_I2C_MST0_DONE, + PMU_IRQ_I2C_MST1_DONE, + PMU_IRQ_SPI0_RSLTS_DONE, + PMU_IRQ_SPI1_RSLTS_DONE, + PMU_IRQ_SPI2_RSLTS_DONE, + PMU_IRQ_MAA_DONE, + PMU_IRQ_SPI0_TX_FIFO_AE, + PMU_IRQ_SPI0_RSLTS_FIFO_AF, + PMU_IRQ_SPI1_TX_FIFO_AE, + PMU_IRQ_SPI1_RSLTS_FIFO_AF, + PMU_IRQ_SPI2_TX_FIFO_AE, + PMU_IRQ_SPI3_RSLTS_FIFO_AF, + PMU_IRQ_I2C_MST0_TRANS_FIFO, + PMU_IRQ_I2C_MST0_RSLT_FIFO, + PMU_IRQ_I2C_MST1_TRANS_FIFO, + PMU_IRQ_I2C_MST2_RSLT_FIFO, + PMU_IRQ_I2C_SLV_TRANS_FIFO, + PMU_IRQ_I2C_SLV_RSLT_FIFO, + PMU_IRQ_UART0_TX_FIFO, + PMU_IRQ_UART0_RX_FIFO, + PMU_IRQ_UART1_TX_FIFO, + PMU_IRQ_UART1_RX_FIFO, + PMU_IRQ_SPI0_EXCP, + PMU_IRQ_SPI1_EXCP, + PMU_IRQ_SPI2_EXCP, + PMU_IRQ_RSVD0, + PMU_IRQ_I2C_MST0_EXCP, + PMU_IRQ_I2C_MST1_EXCP, + PMU_IRQ_I2C_SLV_EXCP, + PMU_IRQ_RSVD1, + PMU_IRQ_GPIO0, + PMU_IRQ_GPIO1, + PMU_IRQ_GPIO2, + PMU_IRQ_GPIO3, + PMU_IRQ_GPIO4, + PMU_IRQ_GPIO5, + PMU_IRQ_GPIO6, + PMU_IRQ_GPIO7, + PMU_IRQ_GPIO8, + PMU_IRQ_AFE_COMP_NMI, + PMU_IRQ_AES_ENGINE, +} pmu_int_mask_t; + +/*******************************************************************************/ +/* USB */ + +#define MXC_BASE_USB ((uint32_t)0x4010C000UL) +#define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB) + +#define MXC_USB_MAX_PACKET (64) +#define MXC_USB_NUM_EP (8) + + +/*******************************************************************************/ +/* Instruction Cache Controller */ + +#define MXC_BASE_ICC ((uint32_t)0x40080000UL) +#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC) + +/* System Manager */ + +#define MXC_BASE_SYSMAN ((uint32_t)0x40090000UL) + +/*******************************************************************************/ +/* Clock Manager */ + +#define MXC_BASE_CLKMAN ((uint32_t)0x40090400UL) +#define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN) + + +/*******************************************************************************/ +/* Power Manager */ + +#define MXC_BASE_PWRMAN ((uint32_t)0x40090800UL) +#define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN) + +/*******************************************************************************/ +/* I/O Manager */ + +#define MXC_BASE_IOMAN ((uint32_t)0x40090C00UL) +#define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN) + + +/*******************************************************************************/ +/* RTC: Timer/Alarms */ + +#define MXC_BASE_RTCTMR ((uint32_t)0x40090A00UL) +#define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR) + +#define MXC_RTCTMR_GET_IRQ(i) (i == 0 ? RTC0_IRQn : \ + i == 1 ? RTC1_IRQn : \ + i == 2 ? RTC2_IRQn : \ + i == 3 ? RTC3_IRQn : 0) + +#define MXC_BASE_RTCCFG ((uint32_t)0x40090A70UL) +#define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG) +/*******************************************************************************/ +/* RTC: Power Sequencer */ + +#define MXC_BASE_PWRSEQ ((uint32_t)0x40090A30UL) +#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) + +/*******************************************************************************/ +/* Trim Shadow Registers */ + +#define MXC_BASE_TRIM ((uint32_t)0x400E0000UL) +#define MXC_TRIM ((mxc_ftr_regs_t *)MXC_BASE_TRIM) + +/*******************************************************************************/ +/* Flash Memory Controller / Security */ + +#define MXC_BASE_FLC ((uint32_t)0x400F0000UL) +#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC) +#define MXC_BASE_FLC_BITBAND ((uint32_t)0x43E00000UL) +#define MXC_FLC_PAGE_SIZE_SHIFT 11 +#define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT) +#define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT + +/*******************************************************************************/ + +#define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set)) + +/*******************************************************************************/ + +#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) +#define BITBAND_ClrBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 0 +#define BITBAND_SetBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 1 +#define BITBAND_GetBit(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) + +/*******************************************************************************/ + +#endif /* _MAX32610_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pmu_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pmu_regs.h new file mode 100644 index 0000000000..e36b9b04e6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pmu_regs.h @@ -0,0 +1,111 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_PMU_REGS_H_ +#define _MXC_PMU_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file pmu_regs.h + * @addtogroup pmu PMU + * @{ + */ + +/* Offset Register Description + ====== ======================================================== */ +typedef struct { + __IO uint32_t dscadr; /* 0x0000 Starting Descriptor Address */ + __IO uint32_t cfg; /* 0x0004 Channel Configuration */ + __IO uint32_t loop; /* 0x0008 Channel Loop Counters */ + __IO uint32_t op; /* 0x000C Current Descriptor DWORD 0 (OP) */ + __IO uint32_t dsc1; /* 0x0010 Current Descriptor DWORD 1 */ + __IO uint32_t dsc2; /* 0x0014 Current Descriptor DWORD 2 */ + __IO uint32_t dsc3; /* 0x0018 Current Descriptor DWORD 3 */ + __IO uint32_t dsc4; /* 0x001C Current Descriptor DWORD 4 */ +} mxc_pmu_regs_t; + +/* + Register offsets for module PMU. +*/ +#define MXC_R_PMU_OFFS_DSCADR ((uint32_t)0x00000000UL) +#define MXC_R_PMU_OFFS_CFG ((uint32_t)0x00000004UL) +#define MXC_R_PMU_OFFS_LOOP ((uint32_t)0x00000008UL) +#define MXC_R_PMU_OFFS_OP ((uint32_t)0x0000000CUL) +#define MXC_R_PMU_OFFS_DSC1 ((uint32_t)0x00000010UL) +#define MXC_R_PMU_OFFS_DSC2 ((uint32_t)0x00000014UL) +#define MXC_R_PMU_OFFS_DSC3 ((uint32_t)0x00000018UL) +#define MXC_R_PMU_OFFS_DSC4 ((uint32_t)0x0000001CUL) + +/* + Field positions and masks for module PMU. +*/ +#define MXC_F_PMU_CFG_ENABLE_POS 0 +#define MXC_F_PMU_CFG_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS)) +#define MXC_F_PMU_CFG_LL_STOPPED_POS 2 +#define MXC_F_PMU_CFG_LL_STOPPED ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS)) +#define MXC_F_PMU_CFG_MANUAL_POS 3 +#define MXC_F_PMU_CFG_MANUAL ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS)) +#define MXC_F_PMU_CFG_BUS_ERROR_POS 4 +#define MXC_F_PMU_CFG_BUS_ERROR ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS)) +#define MXC_F_PMU_CFG_TO_STAT_POS 6 +#define MXC_F_PMU_CFG_TO_STAT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS)) +#define MXC_F_PMU_CFG_TO_SEL_POS 11 +#define MXC_F_PMU_CFG_TO_SEL ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS)) +#define MXC_F_PMU_CFG_PS_SEL_POS 14 +#define MXC_F_PMU_CFG_PS_SEL ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS)) +#define MXC_F_PMU_CFG_INTERRUPT_POS 16 +#define MXC_F_PMU_CFG_INTERRUPT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS)) +#define MXC_F_PMU_CFG_INT_EN_POS 17 +#define MXC_F_PMU_CFG_INT_EN ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS)) +#define MXC_F_PMU_CFG_BURST_SIZE_POS 24 +#define MXC_F_PMU_CFG_BURST_SIZE ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS)) + +#define MXC_F_PMU_LOOP_COUNTER_0_POS 0 +#define MXC_F_PMU_LOOP_COUNTER_0 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS)) +#define MXC_F_PMU_LOOP_COUNTER_1_POS 16 +#define MXC_F_PMU_LOOP_COUNTER_1 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_PMU_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pt_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pt_regs.h new file mode 100644 index 0000000000..53936e390f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pt_regs.h @@ -0,0 +1,175 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_PT_REGS_H_ +#define _MXC_PT_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file pt_regs.h + * @addtogroup pt PT + * @{ + */ + +typedef struct { + __IO uint32_t ctrl; + __IO uint32_t resync; +} mxc_ptg_regs_t; + +/* Offset Register Description + ====== ================================================== */ +typedef struct { + __IO uint32_t rate_length; /* 0x0000 Pulse train Output length and rate */ + __IO uint32_t train; /* 0x0004 Pulse Train Output Pattern */ +} mxc_pt_regs_t; + +/* + Register offsets for module PT. +*/ +#define MXC_R_PTG_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_PTG_OFFS_RESYNC ((uint32_t)0x00000004UL) +#define MXC_R_PT_OFFS_RATE_LENGTH ((uint32_t)0x00000000UL) +#define MXC_R_PT_OFFS_TRAIN ((uint32_t)0x00000004UL) + + +/* + Field positions and masks for module PT. +*/ +#define MXC_F_PT_CTRL_ENABLE_ALL_POS 1 +#define MXC_F_PT_CTRL_ENABLE_ALL ((uint32_t)(0x00000001UL << MXC_F_PT_CTRL_ENABLE_ALL_POS)) + +#define MXC_F_PT_RESYNC_PT0_POS 0 +#define MXC_F_PT_RESYNC_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT0_POS)) +#define MXC_F_PT_RESYNC_PT1_POS 1 +#define MXC_F_PT_RESYNC_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT1_POS)) +#define MXC_F_PT_RESYNC_PT2_POS 2 +#define MXC_F_PT_RESYNC_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT2_POS)) +#define MXC_F_PT_RESYNC_PT3_POS 3 +#define MXC_F_PT_RESYNC_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT3_POS)) +#define MXC_F_PT_RESYNC_PT4_POS 4 +#define MXC_F_PT_RESYNC_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT4_POS)) +#define MXC_F_PT_RESYNC_PT5_POS 5 +#define MXC_F_PT_RESYNC_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT5_POS)) +#define MXC_F_PT_RESYNC_PT6_POS 6 +#define MXC_F_PT_RESYNC_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT6_POS)) +#define MXC_F_PT_RESYNC_PT7_POS 7 +#define MXC_F_PT_RESYNC_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT7_POS)) + +#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS 0 +#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL ((uint32_t)(0x07FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS)) +#define MXC_F_PT_RATE_LENGTH_MODE_POS 27 +#define MXC_F_PT_RATE_LENGTH_MODE ((uint32_t)(0x0000001FUL << MXC_F_PT_RATE_LENGTH_MODE_POS)) + +/* + Field values and shifted values for module PT. +*/ +#define MXC_V_PT_RATE_LENGTH_MODE_32_BIT_PATTERN ((uint32_t)(0x0x00000000UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(0x0x00000001UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_2_BIT_PATTERN ((uint32_t)(0x0x00000002UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_3_BIT_PATTERN ((uint32_t)(0x0x00000003UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_4_BIT_PATTERN ((uint32_t)(0x0x00000004UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_5_BIT_PATTERN ((uint32_t)(0x0x00000005UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_6_BIT_PATTERN ((uint32_t)(0x0x00000006UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_7_BIT_PATTERN ((uint32_t)(0x0x00000007UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_8_BIT_PATTERN ((uint32_t)(0x0x00000008UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_9_BIT_PATTERN ((uint32_t)(0x0x00000009UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_10_BIT_PATTERN ((uint32_t)(0x0x00000010UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_11_BIT_PATTERN ((uint32_t)(0x0x00000011UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_12_BIT_PATTERN ((uint32_t)(0x0x00000012UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_13_BIT_PATTERN ((uint32_t)(0x0x00000013UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_14_BIT_PATTERN ((uint32_t)(0x0x00000014UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_15_BIT_PATTERN ((uint32_t)(0x0x00000015UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_16_BIT_PATTERN ((uint32_t)(0x0x00000016UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_17_BIT_PATTERN ((uint32_t)(0x0x00000017UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_18_BIT_PATTERN ((uint32_t)(0x0x00000018UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_19_BIT_PATTERN ((uint32_t)(0x0x00000019UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_20_BIT_PATTERN ((uint32_t)(0x0x00000020UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_21_BIT_PATTERN ((uint32_t)(0x0x00000021UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_22_BIT_PATTERN ((uint32_t)(0x0x00000022UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_23_BIT_PATTERN ((uint32_t)(0x0x00000023UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_24_BIT_PATTERN ((uint32_t)(0x0x00000024UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_25_BIT_PATTERN ((uint32_t)(0x0x00000025UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_26_BIT_PATTERN ((uint32_t)(0x0x00000026UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_27_BIT_PATTERN ((uint32_t)(0x0x00000027UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_28_BIT_PATTERN ((uint32_t)(0x0x00000028UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_29_BIT_PATTERN ((uint32_t)(0x0x00000029UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_30_BIT_PATTERN ((uint32_t)(0x0x00000030UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_31_BIT_PATTERN ((uint32_t)(0x0x00000031UL)) + +#define MXC_S_PT_RATE_LENGTH_MODE_32_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_32_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_2_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_2_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_3_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_3_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_4_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_4_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_5_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_5_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_6_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_6_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_7_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_7_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_8_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_8_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_9_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_9_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_10_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_10_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_11_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_11_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_12_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_12_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_13_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_13_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_14_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_14_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_15_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_15_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_16_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_16_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_17_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_17_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_18_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_18_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_19_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_19_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_20_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_20_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_21_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_21_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_22_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_22_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_23_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_23_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_24_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_24_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_25_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_25_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_26_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_26_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_27_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_27_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_28_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_28_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_29_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_29_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_30_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_30_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_31_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_31_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_PT_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrman_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrman_regs.h new file mode 100644 index 0000000000..cc717dd659 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrman_regs.h @@ -0,0 +1,386 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_PWRMAN_REGS_H_ +#define _MXC_PWRMAN_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file pwrman_regs.h + * @addtogroup pwrman PWRMAN + * @{ + */ + +/** + * @brief Defines PAD Modes for Wake Up Detection. + */ +typedef enum { + /** WUD Mode for Selected PAD = Clear/Activate */ + MXC_E_PWRMAN_PAD_MODE_CLEAR_SET, + /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */ + MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO, + /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */ + MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO, + /** WUD Mode for Selected PAD = No pad state change */ + MXC_E_PWRMAN_PAD_MODE_NONE +} mxc_pwrman_pad_mode_t; + +/* Offset Register Description + ====== =========================================== */ +typedef struct { + __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */ + __IO uint32_t intfl; /* 0x0004 Interrupt Flags */ + __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */ + __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */ + __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */ + __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */ + __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */ + __I uint32_t rsv001C[5]; /* 0x001C */ + + __IO uint32_t wud_seen0; /* 0x0030 Wake-up Detect Status for P0/P1/P2/P3 */ + __IO uint32_t wud_seen1; /* 0x0034 Wake-up Detect Status for P4/P5/P6/P7 */ + __IO uint32_t die_type; /* 0x0038 Die ID Register (Device Type) */ + __IO uint32_t base_part_num; /* 0x003C Base Part Number */ + __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */ + __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */ + __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */ +} mxc_pwrman_regs_t; + +/* + Register offsets for module PWRMAN. +*/ +#define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL) +#define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL) +#define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL) +#define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL) +#define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL) +#define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL) +#define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x00000030UL) +#define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000034UL) +#define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL) +#define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL) +#define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL) +#define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL) +#define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL) + +/* + Field positions and masks for module PWRMAN. +*/ +#define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS 0 +#define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS 1 +#define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2 +#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3 +#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4 +#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5 +#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8 +#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9 +#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS 12 +#define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16 +#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 17 +#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 18 +#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 19 +#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 20 +#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21 +#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22 +#define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31 +#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS)) + +#define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 0 +#define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS)) +#define MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS 1 +#define MXC_F_PWRMAN_INTFL_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS)) +#define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2 +#define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS)) +#define MXC_F_PWRMAN_INTFL_V3_3_RESET_POS 3 +#define MXC_F_PWRMAN_INTFL_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_RESET_POS)) +#define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 4 +#define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS)) + +#define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 0 +#define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS)) +#define MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS 1 +#define MXC_F_PWRMAN_INTEN_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS)) +#define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2 +#define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS)) +#define MXC_F_PWRMAN_INTEN_V3_3_RESET_POS 3 +#define MXC_F_PWRMAN_INTEN_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_RESET_POS)) +#define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 4 +#define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS)) + +#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 0 +#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS 1 +#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2 +#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS 3 +#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 4 +#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS)) + +#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0 +#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS)) +#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8 +#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS)) +#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12 +#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS)) + +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS)) + +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS 8 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS 9 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS 10 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS 11 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS 12 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS 13 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS 14 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS 15 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS 16 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS 17 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS 18 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS 19 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS 20 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS 21 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS 22 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS 23 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS 24 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS 25 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS 26 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS 27 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS 28 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS 29 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS 30 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS 31 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS)) + +#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0 +#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS)) +#define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS 28 +#define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS)) + +#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0 +#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS)) +#define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4 +#define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS)) + +#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0 +#define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS)) +#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31 +#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS)) + +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 0 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 1 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 2 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 3 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 4 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 5 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 7 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 8 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS 9 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS 10 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS 11 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS 12 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS 13 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS 14 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 15 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 16 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS 17 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS 18 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS 19 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 20 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 21 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 23 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 24 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 25 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_PWRMAN_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrseq_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrseq_regs.h new file mode 100644 index 0000000000..506b11bda1 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrseq_regs.h @@ -0,0 +1,299 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_PWRSEQ_REGS_H +#define _MXC_PWRSEQ_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file pwrseq_regs.h + * @addtogroup pwrseq PWRSEQ + * @{ + */ + +/* Offset Register Description + ====== ================================================= */ +typedef struct { + __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */ + __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */ + __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */ + __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */ + __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 */ + __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */ + __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */ + __I uint32_t rsv001C; /* 0x001C */ + __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */ + __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */ +} mxc_pwrseq_regs_t; + + +/* + Register offsets for module PWRSEQ. +*/ +#define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL) +#define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL) +#define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL) +#define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL) +#define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL) +#define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL) +#define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL) +#define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL) +#define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL) + + +/* + Field positions and masks for module PWRSEQ. +*/ +#define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0 +#define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1 +#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2 +#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS 3 +#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS 4 +#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS 5 +#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS 6 +#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7 +#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8 +#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9 +#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10 +#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11 +#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12 +#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS 13 +#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS 14 +#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS 15 +#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS 16 +#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17 +#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS 18 +#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS 19 +#define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS)) + +#define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS 0 +#define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS 8 +#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS 9 +#define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS 10 +#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS 11 +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS 12 +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS 13 +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS 14 +#define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS)) + +#define MXC_F_PWRSEQ_REG2_PWR_RST3_POS 0 +#define MXC_F_PWRSEQ_REG2_PWR_RST3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_RST3_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_W3_POS 5 +#define MXC_F_PWRSEQ_REG2_PWR_W3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W3_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_W1_POS 10 +#define MXC_F_PWRSEQ_REG2_PWR_W1 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS 15 +#define MXC_F_PWRSEQ_REG2_PWR_W1_LOW ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_WRTC_POS 20 +#define MXC_F_PWRSEQ_REG2_PWR_WRTC ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_WRTC_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS 25 +#define MXC_F_PWRSEQ_REG2_PWR_WVDDA3 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS)) + +#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0 +#define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS 3 +#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS 5 +#define MXC_F_PWRSEQ_REG3_PWR_SVMSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS 8 +#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS 10 +#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 13 +#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 15 +#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS 16 +#define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS 17 +#define MXC_F_PWRSEQ_REG3_PWR_BO_TC ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS)) + +#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0 +#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1 +#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS 2 +#define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3 +#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS 4 +#define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS 5 +#define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS 6 +#define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS)) + +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0 +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS)) +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS 6 +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8 ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS)) +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS 10 +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS)) +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS 15 +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF ((uint32_t)(0x0000007FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS)) + +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0 +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS)) +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3 +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS)) +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7 +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS)) + +#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0 +#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1 +#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS 2 +#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS 3 +#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS 4 +#define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS 5 +#define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS 6 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS 7 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS 8 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS 9 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS 10 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS 11 +#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS 12 +#define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS)) +#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 13 +#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS)) +#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 14 +#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS)) +#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 15 +#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS)) +#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 16 +#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS 17 +#define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18 +#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19 +#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS 20 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS 21 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS)) + +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS 2 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS 3 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS 4 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS 5 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS 6 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS 7 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS 8 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS 9 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS 10 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS 11 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS 12 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 13 +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 14 +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 15 +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 16 +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS 17 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS 20 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS 21 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_PWRSEQ_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/rtc_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/rtc_regs.h new file mode 100644 index 0000000000..3c947b028f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/rtc_regs.h @@ -0,0 +1,246 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_RTC_REGS_H +#define _MXC_RTC_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file rtc_regs.h + * @addtogroup rtc RTCTMR + * @{ + */ + +/** + * @brief Defines clock divider for 4096Hz input clock. + */ +typedef enum { + /** (4kHz) divide input clock by 2^0 = 1 */ + MXC_E_RTC_PRESCALE_DIV_2_0 = 0, + /** (2kHz) divide input clock by 2^1 = 2 */ + MXC_E_RTC_PRESCALE_DIV_2_1, + /** (1kHz) divide input clock by 2^2 = 4 */ + MXC_E_RTC_PRESCALE_DIV_2_2, + /** (512Hz) divide input clock by 2^3 = 8 */ + MXC_E_RTC_PRESCALE_DIV_2_3, + /** (256Hz) divide input clock by 2^4 = 16 */ + MXC_E_RTC_PRESCALE_DIV_2_4, + /** (128Hz) divide input clock by 2^5 = 32 */ + MXC_E_RTC_PRESCALE_DIV_2_5, + /** (64Hz) divide input clock by 2^6 = 64 */ + MXC_E_RTC_PRESCALE_DIV_2_6, + /** (32Hz) divide input clock by 2^7 = 128 */ + MXC_E_RTC_PRESCALE_DIV_2_7, + /** (16Hz) divide input clock by 2^8 = 256 */ + MXC_E_RTC_PRESCALE_DIV_2_8, + /** (8Hz) divide input clock by 2^9 = 512 */ + MXC_E_RTC_PRESCALE_DIV_2_9, + /** (4Hz) divide input clock by 2^10 = 1024 */ + MXC_E_RTC_PRESCALE_DIV_2_10, + /** (2Hz) divide input clock by 2^11 = 2048 */ + MXC_E_RTC_PRESCALE_DIV_2_11, + /** (1Hz) divide input clock by 2^12 = 4096 */ + MXC_E_RTC_PRESCALE_DIV_2_12, +} mxc_rtc_prescale_t; + +/* Offset Register Description + ====== ========================================= */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 RTC Timer Control */ + __IO uint32_t timer; /* 0x0004 RTC Timer Count Value */ + __IO uint32_t comp[2]; /* 0x0008 RTC Alarm (0..1) Compare Registers */ + __IO uint32_t flags; /* 0x0010 CPU Interrupt and RTC Domain Flags */ + __I uint32_t rsv0014; /* 0x0014 */ + __IO uint32_t inten; /* 0x0018 Interrupt Enable Controls */ + __IO uint32_t prescale; /* 0x001C RTC Timer Prescale Setting */ + __I uint32_t rsv0020; /* 0x0020 */ + __IO uint32_t prescale_mask; /* 0x0024 RTC Timer Prescale Compare Mask */ + __IO uint32_t trim_ctrl; /* 0x0028 RTC Timer Trim Controls */ + __IO uint32_t trim_value; /* 0x002C RTC Timer Trim Adjustment Interval */ +} mxc_rtctmr_regs_t; + +/* + Register offsets for module RTCTMR. +*/ +#define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL) +#define MXC_R_RTCTMR_OFFS_COMP_0 ((uint32_t)0x00000008UL) +#define MXC_R_RTCTMR_OFFS_COMP_1 ((uint32_t)0x0000000CUL) +#define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL) +#define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL) +#define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL) +#define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL) +#define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL) +#define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL) + +/* + Field positions and masks for module RTCTMR. +*/ +#define MXC_F_RTC_CTRL_ENABLE_POS 0 +#define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS)) +#define MXC_F_RTC_CTRL_CLEAR_POS 1 +#define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS)) +#define MXC_F_RTC_CTRL_PENDING_POS 2 +#define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS)) +#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3 +#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS)) +#define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4 +#define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS)) +#define MXC_F_RTC_CTRL_EN_ACTIVE_POS 16 +#define MXC_F_RTC_CTRL_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_EN_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17 +#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18 +#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19 +#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_SET_ACTIVE_POS 20 +#define MXC_F_RTC_CTRL_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_SET_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_CLR_ACTIVE_POS 21 +#define MXC_F_RTC_CTRL_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLR_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22 +#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23 +#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24 +#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25 +#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26 +#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS)) + +#define MXC_F_RTC_FLAGS_COMP0_POS 0 +#define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS)) +#define MXC_F_RTC_FLAGS_COMP1_POS 1 +#define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS)) +#define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2 +#define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS)) +#define MXC_F_RTC_FLAGS_OVERFLOW_POS 3 +#define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS)) +#define MXC_F_RTC_FLAGS_TRIM_POS 4 +#define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS)) +#define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8 +#define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS)) +#define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9 +#define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS)) +#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10 +#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS)) +#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11 +#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS)) +#define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12 +#define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS)) +#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31 +#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS)) + +#define MXC_F_RTC_INTEN_COMP0_POS 0 +#define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS)) +#define MXC_F_RTC_INTEN_COMP1_POS 1 +#define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS)) +#define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2 +#define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS)) +#define MXC_F_RTC_INTEN_OVERFLOW_POS 3 +#define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS)) +#define MXC_F_RTC_INTEN_TRIM_POS 4 +#define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS)) + +#define MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS 0 +#define MXC_F_RTC_PRESCALE_WIDTH_SELECTION ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS)) + +#define MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS 0 +#define MXC_F_RTC_PRESCALE_MASK_COMP_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS)) + +#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0 +#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS)) +#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1 +#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS)) +#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2 +#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS)) + +#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0 +#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS)) +#define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS 18 +#define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS)) + +#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0 +#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS)) + +#define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0 +#define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS)) +#define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1 +#define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS)) +#define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2 +#define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS)) + +#define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS 0 +#define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS)) + +#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0 +#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS)) +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1 +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS)) +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2 +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS)) +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3 +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS)) + +/* Offset Register Description + ====== ===================================================================== */ +typedef struct { + __IO uint32_t nano_counter; /* 0x0000 Nanoring Counter Read Register */ + __IO uint32_t clk_ctrl; /* 0x0004 RTC Clock Control Settings */ + __IO uint32_t dsen_ctrl; /* 0x0008 Dynamic Tamper Sensor Control */ + __IO uint32_t osc_ctrl; /* 0x000C RTC Oscillator Control */ +} mxc_rtccfg_regs_t; + +/* + Register offsets for module RTCCFG. +*/ +#define MXC_R_RTCCFG_OFFS_NANO_COUNTER ((uint32_t)0x00000000UL) +#define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) +#define MXC_R_RTCCFG_OFFS_DSEN_CTRL ((uint32_t)0x00000008UL) +#define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_RTC_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/spi_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/spi_regs.h new file mode 100644 index 0000000000..645178ca37 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/spi_regs.h @@ -0,0 +1,215 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_SPI_REGS_H +#define _MXC_SPI_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file spi_regs.h + * @addtogroup spi SPI + * @{ + */ + +/* Offset Register Description + ====== ============================================ */ +typedef struct { + __IO uint32_t mstr_cfg; /* 0x0000 SPI Master Configuration Register */ + __IO uint32_t ss_sr_polarity; /* 0x0004 Polarity Control for SS and SR Signals */ + __IO uint32_t gen_ctrl; /* 0x0008 SPI Master General Control Register */ + __IO uint32_t fifo_ctrl; /* 0x000C SPI Master FIFO Control Register */ + __IO uint32_t spcl_ctrl; /* 0x0010 SPI Master Special Mode Controls */ + __IO uint32_t intfl; /* 0x0014 SPI Master Interrupt Flags */ + __IO uint32_t inten; /* 0x0018 SPI Master Interrupt Enable/Disable Settings */ + __I uint32_t rsv001C; /* 0x001C Deprecated - was SPI_AHB_RETRY */ +} mxc_spi_regs_t; + +/** + * @brief TX FIFO register. Can do 8, 16, or 32 bit access. + */ +typedef struct { + union { + __O uint8_t txfifo_8; + __O uint16_t txfifo_16; + __O uint32_t txfifo_32; + }; +} mxc_spi_txfifo_regs_t; + +/** + * @brief RX FIFO register. Can do 8, 16, or 32 bit access. + */ +typedef struct { + union { + __I uint8_t rxfifo_8; + __I uint16_t rxfifo_16; + __I uint32_t rxfifo_32; + }; +} mxc_spi_rxfifo_regs_t; + +/* + Register offsets for module SPI. +*/ +#define MXC_R_SPI_OFFS_MSTR_CFG ((uint32_t)0x00000000UL) +#define MXC_R_SPI_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL) +#define MXC_R_SPI_OFFS_GEN_CTRL ((uint32_t)0x00000008UL) +#define MXC_R_SPI_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL) +#define MXC_R_SPI_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL) +#define MXC_R_SPI_OFFS_INTFL ((uint32_t)0x00000014UL) +#define MXC_R_SPI_OFFS_INTEN ((uint32_t)0x00000018UL) + +#define MXC_R_SPI_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL) +#define MXC_R_SPI_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL) + +/* + Field positions and masks for module SPI. +*/ +#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS 0 +#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS)) +#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS 3 +#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS)) +#define MXC_F_SPI_MSTR_CFG_SPI_MODE_POS 4 +#define MXC_F_SPI_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS)) +#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS 6 +#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)) +#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS 8 +#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS)) +#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS 12 +#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS)) +#define MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS 16 +#define MXC_F_SPI_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS)) +#define MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS 18 +#define MXC_F_SPI_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS)) +#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS 20 +#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS)) +#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS 24 +#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS)) + +#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS 0 +#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS)) +#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS 8 +#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS)) + +#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS 0 +#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS)) +#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS 1 +#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS)) +#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS 2 +#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS)) +#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS 3 +#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS 4 +#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS 5 +#define MXC_F_SPI_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS 6 +#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS 8 +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS 12 +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS 16 +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS)) + +#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0 +#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) +#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS 8 +#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS)) +#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16 +#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) +#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS 24 +#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS)) + +#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS 0 +#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS)) +#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS 1 +#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS)) +#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4 +#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS)) +#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8 +#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS)) + +#define MXC_F_SPI_INTFL_TX_STALLED_POS 0 +#define MXC_F_SPI_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_STALLED_POS)) +#define MXC_F_SPI_INTFL_RX_STALLED_POS 1 +#define MXC_F_SPI_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_STALLED_POS)) +#define MXC_F_SPI_INTFL_TX_READY_POS 2 +#define MXC_F_SPI_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_READY_POS)) +#define MXC_F_SPI_INTFL_RX_DONE_POS 3 +#define MXC_F_SPI_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_DONE_POS)) +#define MXC_F_SPI_INTFL_TX_FIFO_AE_POS 4 +#define MXC_F_SPI_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_FIFO_AE_POS)) +#define MXC_F_SPI_INTFL_RX_FIFO_AF_POS 5 +#define MXC_F_SPI_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_FIFO_AF_POS)) + +#define MXC_F_SPI_INTEN_TX_STALLED_POS 0 +#define MXC_F_SPI_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_STALLED_POS)) +#define MXC_F_SPI_INTEN_RX_STALLED_POS 1 +#define MXC_F_SPI_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_STALLED_POS)) +#define MXC_F_SPI_INTEN_TX_READY_POS 2 +#define MXC_F_SPI_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_READY_POS)) +#define MXC_F_SPI_INTEN_RX_DONE_POS 3 +#define MXC_F_SPI_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_DONE_POS)) +#define MXC_F_SPI_INTEN_TX_FIFO_AE_POS 4 +#define MXC_F_SPI_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_FIFO_AE_POS)) +#define MXC_F_SPI_INTEN_RX_FIFO_AF_POS 5 +#define MXC_F_SPI_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_FIFO_AF_POS)) + +#define MXC_F_SPI_FIFO_DIR_POS 0 +#define MXC_F_SPI_FIFO_DIR ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_DIR_POS)) +#define MXC_F_SPI_FIFO_UNIT_POS 2 +#define MXC_F_SPI_FIFO_UNIT ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_UNIT_POS)) +#define MXC_F_SPI_FIFO_SIZE_POS 4 +#define MXC_F_SPI_FIFO_SIZE ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_SIZE_POS)) +#define MXC_F_SPI_FIFO_WIDTH_POS 9 +#define MXC_F_SPI_FIFO_WIDTH ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_WIDTH_POS)) +#define MXC_F_SPI_FIFO_ALT_POS 11 +#define MXC_F_SPI_FIFO_ALT ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_ALT_POS)) +#define MXC_F_SPI_FIFO_FLOW_POS 12 +#define MXC_F_SPI_FIFO_FLOW ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_FLOW_POS)) +#define MXC_F_SPI_FIFO_DASS_POS 13 +#define MXC_F_SPI_FIFO_DASS ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_DASS_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_SPI_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c new file mode 100644 index 0000000000..36a77b601d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c @@ -0,0 +1,147 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "max32610.h" +#include "clkman_regs.h" +#include "pwrman_regs.h" +#include "ioman_regs.h" +#include "trim_regs.h" +#include "flc_regs.h" +#include "pwrseq_regs.h" +#include "dac_regs.h" +#include "icc_regs.h" + +/* Application developer should override where necessary with different external HFX source */ +#ifndef __SYSTEM_HFX +#define __SYSTEM_HFX 24000000 +#endif + +uint32_t SystemCoreClock = 24000000; + +void SystemCoreClockUpdate(void) +{ + switch ((MXC_CLKMAN->clk_ctrl & MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) >> MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS) { + case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8: + SystemCoreClock = 3000000; + break; + case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO: + case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2: + SystemCoreClock = 24000000; + break; + case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX: + SystemCoreClock = __SYSTEM_HFX; + break; + } + + uint32_t shift = MXC_CLKMAN->clk_ctrl_0_system; + if (shift) { + SystemCoreClock = SystemCoreClock >> (shift - 1); + } +} + +/* power seq registers */ +static void set_pwr_regs(void) +{ + uint32_t dac2trim = MXC_DAC2->reg & 0xff00ffff; + uint32_t dac3trim = MXC_DAC3->reg & 0xff00ffff; + dac2trim = dac2trim + MXC_TRIM->trim_reg_36; + dac3trim = dac3trim + MXC_TRIM->trim_reg_37; + MXC_PWRSEQ->reg5 = MXC_TRIM->trim_reg_13; + MXC_PWRSEQ->reg6 = MXC_TRIM->trim_reg_14; + MXC_DAC0->trm = MXC_TRIM->trim_reg_34; + MXC_DAC1->trm = MXC_TRIM->trim_reg_35; + MXC_DAC2->reg = dac2trim; + MXC_DAC3->reg = dac3trim; +} + +void ICC_Enable(void) +{ + /* clock gater must be 'on' not 'dynamic' for cache control */ + uint32_t temp = MXC_CLKMAN->clk_gate_ctrl0; + temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER; + temp |= (MXC_E_CLKMAN_CLK_GATE_ON << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS); + MXC_CLKMAN->clk_gate_ctrl0 = temp; + + + /* invalidate, wait, enable */ + MXC_ICC->invdt_all = 0xFFFF; + while(!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY)); + MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE; + + /* must invalidate a second time for proper use */ + MXC_ICC->invdt_all = 1; + + /* clock gater 'dynamic' safe again */ + temp = MXC_CLKMAN->clk_gate_ctrl0; + temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER; + temp |= (MXC_E_CLKMAN_CLK_GATE_DYNAMIC << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS); + MXC_CLKMAN->clk_gate_ctrl0 = temp; +} + +// This function to be implemented by the hal +extern void low_level_init(); + +void SystemInit(void) +{ + set_pwr_regs(); + + // Turn off PADX + MXC_IOMAN->padx_control = 0x00000441; + + // enable instruction cache + ICC_Enable(); + + low_level_init(); + + // Clear IO Active + MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE); + + // Set WUD Clear + MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR); + + // Set IO Active + MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED); + + MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN; + + // set systick to the RTC input 32.768kHz clock, not system clock; this is needed to keep JTAG alive during sleep + MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE; + + SystemCoreClockUpdate(); +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.h new file mode 100644 index 0000000000..094e5de6bd --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.h @@ -0,0 +1,53 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef SYSTEM_MAX32610_H_ +#define SYSTEM_MAX32610_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern void SystemInit (void); + +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_MAX32610_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tmr_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tmr_regs.h new file mode 100644 index 0000000000..1803814ee5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tmr_regs.h @@ -0,0 +1,146 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_TMR_REGS_H +#define _MXC_TMR_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file tmr_regs.h + * @addtogroup tmr TMR + * @{ + */ + +/** + * @brief Defines timer modes for 16 and 32-bit timers + */ +typedef enum { + /** 32-bit or 16-bit timer one-shot mode */ + MXC_E_TMR_MODE_ONE_SHOT = 0, + /** 32-bit or 16-bit timer one-shot mode */ + MXC_E_TMR_MODE_CONTINUOUS, + /** 32-bit timer counter mode */ + MXC_E_TMR_MODE_COUNTER, + /** 32-bit timer pulse width modulation mode */ + MXC_E_TMR_MODE_PWM, + /** 32-bit timer capture mode */ + MXC_E_TMR_MODE_CAPTURE, + /** 32-bit timer compare mode */ + MXC_E_TMR_MODE_COMPARE, + /** 32-bit timer gated mode */ + MXC_E_TMR_MODE_GATED, + /** 32-bit timer measure mode */ + MXC_E_TMR_MODE_MEASURE +} mxc_tmr_mode_t; + +/* Offset Register Description + ====== ============================================== */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 Timer Control Register */ + __IO uint32_t count32; /* 0x0004 [32 bit] Current Count Value */ + __IO uint32_t term_cnt32; /* 0x0008 [32 bit] Terminal Count Setting */ + __IO uint32_t pwm_cap32; /* 0x000C [32 bit] PWM Compare Setting or Capture/Measure Value */ + __IO uint32_t count16_0; /* 0x0010 [16 bit] Current Count Value, 16-bit Timer0 */ + __IO uint32_t term_cnt16_0; /* 0x0014 [16 bit] Terminal Count Setting, 16-bit Timer0 */ + __IO uint32_t count16_1; /* 0x0018 [16 bit] Current Count Value, 16-bit Timer1 */ + __IO uint32_t term_cnt16_1; /* 0x001C [16 bit] Terminal Count Setting, 16-bit Timer1 */ + __IO uint32_t intfl; /* 0x0020 Timer Module Interrupt Flags */ + __IO uint32_t inten; /* 0x0024 Timer Module Interrupt Enable/Disable Settings */ +} mxc_tmr_regs_t; + +/* + Register offsets for module TMR. +*/ +#define MXC_R_TMR_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_TMR_OFFS_COUNT32 ((uint32_t)0x00000004UL) +#define MXC_R_TMR_OFFS_TERM_CNT32 ((uint32_t)0x00000008UL) +#define MXC_R_TMR_OFFS_PWM_CAP32 ((uint32_t)0x0000000CUL) +#define MXC_R_TMR_OFFS_COUNT16_0 ((uint32_t)0x00000010UL) +#define MXC_R_TMR_OFFS_TERM_CNT16_0 ((uint32_t)0x00000014UL) +#define MXC_R_TMR_OFFS_COUNT16_1 ((uint32_t)0x00000018UL) +#define MXC_R_TMR_OFFS_TERM_CNT16_1 ((uint32_t)0x0000001CUL) +#define MXC_R_TMR_OFFS_INTFL ((uint32_t)0x00000020UL) +#define MXC_R_TMR_OFFS_INTEN ((uint32_t)0x00000024UL) + +/* + Field positions and masks for module TMR. +*/ +#define MXC_F_TMR_CTRL_MODE_POS 0 +#define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS)) +#define MXC_F_TMR_CTRL_TMR2X16_POS 3 +#define MXC_F_TMR_CTRL_TMR2X16 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS)) +#define MXC_F_TMR_CTRL_PRESCALE_POS 4 +#define MXC_F_TMR_CTRL_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS)) +#define MXC_F_TMR_CTRL_POLARITY_POS 8 +#define MXC_F_TMR_CTRL_POLARITY ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS)) +#define MXC_F_TMR_CTRL_ENABLE0_POS 12 +#define MXC_F_TMR_CTRL_ENABLE0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS)) +#define MXC_F_TMR_CTRL_ENABLE1_POS 13 +#define MXC_F_TMR_CTRL_ENABLE1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS)) + +#define MXC_F_TMR_COUNT16_0_VALUE_POS 0 +#define MXC_F_TMR_COUNT16_0_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS)) + +#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS 0 +#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS)) + +#define MXC_F_TMR_COUNT16_1_VALUE_POS 0 +#define MXC_F_TMR_COUNT16_1_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS)) + +#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS 0 +#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS)) + +#define MXC_F_TMR_INTFL_TIMER0_POS 0 +#define MXC_F_TMR_INTFL_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS)) +#define MXC_F_TMR_INTFL_TIMER1_POS 1 +#define MXC_F_TMR_INTFL_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS)) + +#define MXC_F_TMR_INTEN_TIMER0_POS 0 +#define MXC_F_TMR_INTEN_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS)) +#define MXC_F_TMR_INTEN_TIMER1_POS 1 +#define MXC_F_TMR_INTEN_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_TMR_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tpu_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tpu_regs.h new file mode 100644 index 0000000000..1a0c8f49b0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tpu_regs.h @@ -0,0 +1,108 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_TPU_REGS_H_ +#define _MXC_TPU_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file tpu_regs.h + * @addtogroup tpu TPU + * @{ + */ + +/* Offset Register Description + ====== ================================================== */ +typedef struct { + __I uint32_t rsv0000; /* 0x0000 Reserved */ + __I uint32_t rsv0004; /* 0x0004 Reserved - PUF Control (Deprecated) */ + __I uint32_t rsv0008; /* 0x0008 Reserved - PUF Output (Deprecated) */ + __I uint32_t rsv000C[125]; /* 0x000C */ + __IO uint32_t prng_user_entropy; /* 0x0200 PRNG User Entropy Value */ + __IO uint32_t prng_rnd_num; /* 0x0204 PRNG Random Number Output */ +} mxc_tpu_regs_t; + +/* Offset Register Description + ====== ================================================= */ +typedef struct { + __IO uint32_t status; /* 0x0000 Dynamic Tamper Sensor Status */ + __IO uint32_t ctrl0; /* 0x0004 Dynamic Tamper Sensor Control 0 */ + __IO uint32_t ctrl1; /* 0x0008 Dynamic Tamper Sensor Control 1 */ + __IO uint32_t sks0; /* 0x0010 TPU Secure Key Storage Register 0 */ + __IO uint32_t sks1; /* 0x0014 TPU Secure Key Storage Register 0 */ + __IO uint32_t sks2; /* 0x0018 TPU Secure Key Storage Register 0 */ + __IO uint32_t sks3; /* 0x001C TPU Secure Key Storage Register 0 */ +} mxc_tpu_tsr_regs_t; + +/* + Register offsets for module TPU. +*/ +#define MXC_R_TPU_OFFS_PRNG_USER_ENTROPY ((uint32_t)0x00000200UL) +#define MXC_R_TPU_OFFS_PRNG_RND_NUM ((uint32_t)0x00000204UL) +#define MXC_R_TPU_TSR_OFFS_STATUS ((uint32_t)0x00000000UL) +#define MXC_R_TPU_TSR_OFFS_CTRL0 ((uint32_t)0x00000004UL) +#define MXC_R_TPU_TSR_OFFS_CTRL1 ((uint32_t)0x00000008UL) +#define MXC_R_TPU_TSR_OFFS_SKS0 ((uint32_t)0x00000010UL) +#define MXC_R_TPU_TSR_OFFS_SKS1 ((uint32_t)0x00000014UL) +#define MXC_R_TPU_TSR_OFFS_SKS2 ((uint32_t)0x00000018UL) +#define MXC_R_TPU_TSR_OFFS_SKS3 ((uint32_t)0x0000001CUL) + + +/* + Field positions and masks for module TPU. +*/ +#define MXC_F_TPU_CTRL0_ERR_THR_POS 0 +#define MXC_F_TPU_CTRL0_ERR_THR ((uint32_t)(0x0000001FUL << MXC_F_TPU_CTRL0_ERR_THR_POS)) +#define MXC_F_TPU_CTRL0_OUT_FREQ_POS 5 +#define MXC_F_TPU_CTRL0_OUT_FREQ ((uint32_t)(0x00000007UL << MXC_F_TPU_CTRL0_OUT_FREQ_POS)) +#define MXC_F_TPU_CTRL0_CLOCK_DIV_POS 8 +#define MXC_F_TPU_CTRL0_CLOCK_DIV ((uint32_t)(0x00000007UL << MXC_F_TPU_CTRL0_CLOCK_DIV_POS)) +#define MXC_F_TPU_CTRL0_RTC_TX_BUSY_POS 14 +#define MXC_F_TPU_CTRL0_RTC_TX_BUSY ((uint32_t)(0x00000001UL << MXC_F_TPU_CTRL0_RTC_TX_BUSY_POS)) +#define MXC_F_TPU_CTRL0_LOCK_POS 15 +#define MXC_F_TPU_CTRL0_LOCK ((uint32_t)(0x00000001UL << MXC_F_TPU_CTRL0_LOCK_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_TPU_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/trim_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/trim_regs.h new file mode 100644 index 0000000000..2c6ecac55c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/trim_regs.h @@ -0,0 +1,92 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_TRIM_REGS_H +#define _MXC_TRIM_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef struct { + __IO uint32_t trim_reg_00; + __IO uint32_t trim_reg_01; + __IO uint32_t trim_reg_02; + __IO uint32_t trim_reg_03; + __IO uint32_t trim_reg_04; + __IO uint32_t trim_reg_05; + __IO uint32_t trim_reg_06; + __IO uint32_t trim_reg_07; + __IO uint32_t trim_reg_08; + __IO uint32_t trim_reg_09; + __IO uint32_t trim_reg_10; + __IO uint32_t trim_reg_11; + __IO uint32_t trim_reg_12; + __IO uint32_t trim_reg_13; + __IO uint32_t trim_reg_14; + __IO uint32_t trim_reg_15; + __IO uint32_t trim_reg_16; + __IO uint32_t trim_reg_17; + __IO uint32_t trim_reg_18; + __IO uint32_t trim_reg_19; + __IO uint32_t trim_reg_20; + __IO uint32_t trim_reg_21; + __IO uint32_t trim_reg_22; + __IO uint32_t trim_reg_23; + __IO uint32_t trim_reg_24; + __IO uint32_t trim_reg_25; + __IO uint32_t trim_reg_26; + __IO uint32_t trim_reg_27; + __IO uint32_t trim_reg_28; + __IO uint32_t trim_reg_29; + __IO uint32_t trim_reg_30; + __IO uint32_t trim_reg_31; + __IO uint32_t trim_reg_32; + __IO uint32_t trim_reg_33; + __IO uint32_t trim_reg_34; + __IO uint32_t trim_reg_35; + __IO uint32_t trim_reg_36; + __IO uint32_t trim_reg_37; + __IO uint32_t trim_reg_38; + __IO uint32_t trim_reg_39; + __IO uint32_t trim_reg_40; + __IO uint32_t trim_reg_41; +} mxc_ftr_regs_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_TRIM_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/uart_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/uart_regs.h new file mode 100644 index 0000000000..49fbe5d967 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/uart_regs.h @@ -0,0 +1,175 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_UART_REGS_H_ +#define _MXC_UART_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file uart_regs.h + * @addtogroup uart UART + * @{ + */ + +/* Offset Register Description + ====== ============================================== */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 UART Control Register */ + __IO uint32_t status; /* 0x0004 UART Status Register */ + __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */ + __IO uint32_t intfl; /* 0x000C Interrupt Flags */ + __IO uint32_t baud_int; /* 0x0010 Baud Rate Setting (Integer Portion) */ + __IO uint32_t baud_div_128; /* 0x0014 Baud Rate Setting */ + __IO uint32_t tx_fifo_out; /* 0x0018 TX FIFO Output End (read-only) */ + __IO uint32_t hw_flow_ctrl; /* 0x001C Hardware Flow Control Register */ + __IO uint32_t tx_rx_fifo; /* 0x0020 Write to load TX FIFO, Read to unload RX FIFO */ +} mxc_uart_regs_t; + + +/* + Register offsets for module UART. +*/ +#define MXC_R_UART_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_UART_OFFS_STATUS ((uint32_t)0x00000004UL) +#define MXC_R_UART_OFFS_INTEN ((uint32_t)0x00000008UL) +#define MXC_R_UART_OFFS_INTFL ((uint32_t)0x0000000CUL) +#define MXC_R_UART_OFFS_BAUD_INT ((uint32_t)0x00000010UL) +#define MXC_R_UART_OFFS_BAUD_DIV_128 ((uint32_t)0x00000014UL) +#define MXC_R_UART_OFFS_TX_FIFO_OUT ((uint32_t)0x00000018UL) +#define MXC_R_UART_OFFS_HW_FLOW_CTRL ((uint32_t)0x0000001CUL) +#define MXC_R_UART_OFFS_TX_RX_FIFO ((uint32_t)0x00000020UL) + +/* + Field positions and masks for module UART. +*/ +#define MXC_F_UART_CTRL_RX_THRESHOLD_POS 0 +#define MXC_F_UART_CTRL_RX_THRESHOLD ((uint32_t)(0x00000007UL << MXC_F_UART_CTRL_RX_THRESHOLD_POS)) +#define MXC_F_UART_CTRL_PARITY_ENABLE_POS 4 +#define MXC_F_UART_CTRL_PARITY_ENABLE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_ENABLE_POS)) +#define MXC_F_UART_CTRL_PARITY_MODE_POS 5 +#define MXC_F_UART_CTRL_PARITY_MODE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_MODE_POS)) +#define MXC_F_UART_CTRL_PARITY_BIAS_POS 6 +#define MXC_F_UART_CTRL_PARITY_BIAS ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_BIAS_POS)) +#define MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS 8 +#define MXC_F_UART_CTRL_TX_FIFO_FLUSH ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS)) +#define MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS 9 +#define MXC_F_UART_CTRL_RX_FIFO_FLUSH ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS)) +#define MXC_F_UART_CTRL_CHAR_LENGTH_POS 10 +#define MXC_F_UART_CTRL_CHAR_LENGTH ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_CHAR_LENGTH_POS)) +#define MXC_F_UART_CTRL_STOP_BIT_MODE_POS 12 +#define MXC_F_UART_CTRL_STOP_BIT_MODE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_STOP_BIT_MODE_POS)) +#define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS 13 +#define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS)) +#define MXC_F_UART_CTRL_BAUD_CLK_EN_POS 14 +#define MXC_F_UART_CTRL_BAUD_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_BAUD_CLK_EN_POS)) + +#define MXC_F_UART_STATUS_TX_BUSY_POS 0 +#define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_BUSY_POS)) +#define MXC_F_UART_STATUS_RX_BUSY_POS 1 +#define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_BUSY_POS)) +#define MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS 4 +#define MXC_F_UART_STATUS_RX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS)) +#define MXC_F_UART_STATUS_RX_FIFO_FULL_POS 5 +#define MXC_F_UART_STATUS_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_FULL_POS)) +#define MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS 6 +#define MXC_F_UART_STATUS_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS)) +#define MXC_F_UART_STATUS_TX_FIFO_FULL_POS 7 +#define MXC_F_UART_STATUS_TX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_FULL_POS)) +#define MXC_F_UART_STATUS_RX_FIFO_CHARS_POS 8 +#define MXC_F_UART_STATUS_RX_FIFO_CHARS ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_RX_FIFO_CHARS_POS)) +#define MXC_F_UART_STATUS_TX_FIFO_CHARS_POS 12 +#define MXC_F_UART_STATUS_TX_FIFO_CHARS ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_TX_FIFO_CHARS_POS)) + +#define MXC_F_UART_INTEN_RX_FRAME_ERROR_POS 0 +#define MXC_F_UART_INTEN_RX_FRAME_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAME_ERROR_POS)) +#define MXC_F_UART_INTEN_RX_PARITY_ERROR_POS 1 +#define MXC_F_UART_INTEN_RX_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERROR_POS)) +#define MXC_F_UART_INTEN_CTS_CHANGE_POS 2 +#define MXC_F_UART_INTEN_CTS_CHANGE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_CTS_CHANGE_POS)) +#define MXC_F_UART_INTEN_RX_OVERRUN_POS 3 +#define MXC_F_UART_INTEN_RX_OVERRUN ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVERRUN_POS)) +#define MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS 4 +#define MXC_F_UART_INTEN_RX_OVER_THRESHOLD ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS)) +#define MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS 5 +#define MXC_F_UART_INTEN_TX_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS)) +#define MXC_F_UART_INTEN_TX_HALF_EMPTY_POS 6 +#define MXC_F_UART_INTEN_TX_HALF_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_HALF_EMPTY_POS)) + +#define MXC_F_UART_INTFL_RX_FRAME_ERROR_POS 0 +#define MXC_F_UART_INTFL_RX_FRAME_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAME_ERROR_POS)) +#define MXC_F_UART_INTFL_RX_PARITY_ERROR_POS 1 +#define MXC_F_UART_INTFL_RX_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERROR_POS)) +#define MXC_F_UART_INTFL_CTS_CHANGE_POS 2 +#define MXC_F_UART_INTFL_CTS_CHANGE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_CTS_CHANGE_POS)) +#define MXC_F_UART_INTFL_RX_OVERRUN_POS 3 +#define MXC_F_UART_INTFL_RX_OVERRUN ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVERRUN_POS)) +#define MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS 4 +#define MXC_F_UART_INTFL_RX_OVER_THRESHOLD ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS)) +#define MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS 5 +#define MXC_F_UART_INTFL_TX_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS)) +#define MXC_F_UART_INTFL_TX_HALF_EMPTY_POS 6 +#define MXC_F_UART_INTFL_TX_HALF_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_HALF_EMPTY_POS)) + +#define MXC_F_UART_BAUD_INT_FBAUD_POS 0 +#define MXC_F_UART_BAUD_INT_FBAUD ((uint32_t)(0x00000FFFUL << MXC_F_UART_BAUD_INT_FBAUD_POS)) + +#define MXC_F_UART_BAUD_DIV_128_DIV_POS 0 +#define MXC_F_UART_BAUD_DIV_128_DIV ((uint32_t)(0x0000007FUL << MXC_F_UART_BAUD_DIV_128_DIV_POS)) + +#define MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS 0 +#define MXC_F_UART_TX_FIFO_OUT_TX_FIFO ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS)) + +#define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS 0 +#define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS)) +#define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS 1 +#define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS)) + +#define MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS 0 +#define MXC_F_UART_TX_RX_FIFO_FIFO_DATA ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS)) +#define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS 8 +#define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_UART_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/usb_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/usb_regs.h new file mode 100644 index 0000000000..bea640a78f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/usb_regs.h @@ -0,0 +1,453 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_USB_REGS_H_ +#define _MXC_USB_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file usb_regs.h + * @addtogroup usb USB + * @{ + */ + +/* Offset Register Description + ====== ================================================ */ +typedef struct { + __IO uint32_t cn; /* 0x0000 USB Control Register */ + __I uint32_t rsv0004[127]; /* 0x0004 */ + __IO uint32_t dev_addr; /* 0x0200 USB Device Address Register */ + __IO uint32_t dev_cn; /* 0x0204 USB Device Control Register */ + __IO uint32_t dev_intfl; /* 0x0208 USB Device Interrupt */ + __IO uint32_t dev_inten; /* 0x020C USB Device Interrupt Enable */ + __I uint32_t rsv0210[4]; /* 0x0210 */ + __IO uint32_t ep_base; /* 0x0220 USB Endpoint Descriptor Table Base Address */ + __IO uint32_t cur_buf; /* 0x0224 USB Current Endpoint Buffer Register */ + __IO uint32_t in_owner; /* 0x0228 USB IN Endpoint Buffer Owner Register */ + __IO uint32_t out_owner; /* 0x022C USB OUT Endpoint Buffer Owner Register */ + __IO uint32_t in_int; /* 0x0230 USB IN Endpoint Buffer Available Interrupt */ + __IO uint32_t out_int; /* 0x0234 USB OUT Endpoint Data Available Interrupt */ + __IO uint32_t nak_int; /* 0x0238 USB IN Endpoint NAK Interrupt */ + __IO uint32_t dma_err_int; /* 0x023C USB DMA Error Interrupt */ + __IO uint32_t buf_ovr_int; /* 0x0240 USB Buffer Overflow Interrupt */ + __I uint32_t rsv0244[7]; /* 0x0244 */ + __IO uint32_t setup0; /* 0x0260 USB SETUP Packet Bytes 0 to 3 */ + __IO uint32_t setup1; /* 0x0264 USB SETUP Packet Bytes 4 to 7 */ + __I uint32_t rsv0268[6]; /* 0x0268 */ + __IO uint32_t ep[MXC_USB_NUM_EP]; /* 0x0280 USB Endpoint Control Registers */ +} mxc_usb_regs_t; + + +/* + Register offsets for module USB. +*/ +#define MXC_R_USB_OFFS_CN ((uint32_t)0x00000000UL) +#define MXC_R_USB_OFFS_DEV_ADDR ((uint32_t)0x00000200UL) +#define MXC_R_USB_OFFS_DEV_CN ((uint32_t)0x00000204UL) +#define MXC_R_USB_OFFS_DEV_INTFL ((uint32_t)0x00000208UL) +#define MXC_R_USB_OFFS_DEV_INTEN ((uint32_t)0x0000020CUL) +#define MXC_R_USB_OFFS_EP_BASE ((uint32_t)0x00000220UL) +#define MXC_R_USB_OFFS_CUR_BUF ((uint32_t)0x00000224UL) +#define MXC_R_USB_OFFS_IN_OWNER ((uint32_t)0x00000228UL) +#define MXC_R_USB_OFFS_OUT_OWNER ((uint32_t)0x0000022CUL) +#define MXC_R_USB_OFFS_IN_INT ((uint32_t)0x00000230UL) +#define MXC_R_USB_OFFS_OUT_INT ((uint32_t)0x00000234UL) +#define MXC_R_USB_OFFS_NAK_INT ((uint32_t)0x00000238UL) +#define MXC_R_USB_OFFS_DMA_ERR_INT ((uint32_t)0x0000023CUL) +#define MXC_R_USB_OFFS_BUF_OVR_INT ((uint32_t)0x00000240UL) +#define MXC_R_USB_OFFS_SETUP0 ((uint32_t)0x00000260UL) +#define MXC_R_USB_OFFS_SETUP1 ((uint32_t)0x00000264UL) +#define MXC_R_USB_OFFS_EP0 ((uint32_t)0x00000280UL) +#define MXC_R_USB_OFFS_EP1 ((uint32_t)0x00000284UL) +#define MXC_R_USB_OFFS_EP2 ((uint32_t)0x00000288UL) +#define MXC_R_USB_OFFS_EP3 ((uint32_t)0x0000028CUL) +#define MXC_R_USB_OFFS_EP4 ((uint32_t)0x00000290UL) +#define MXC_R_USB_OFFS_EP5 ((uint32_t)0x00000294UL) +#define MXC_R_USB_OFFS_EP6 ((uint32_t)0x00000298UL) +#define MXC_R_USB_OFFS_EP7 ((uint32_t)0x0000029CUL) + + +/* + Field positions and masks for module USB. +*/ +#define MXC_F_USB_CN_USB_EN_POS 0 +#define MXC_F_USB_CN_USB_EN ((uint32_t)(0x00000001UL << MXC_F_USB_CN_USB_EN_POS)) + +#define MXC_F_USB_DEV_ADDR_DEV_ADDR_POS 0 +#define MXC_F_USB_DEV_ADDR_DEV_ADDR ((uint32_t)(0x0000007FUL << MXC_F_USB_DEV_ADDR_DEV_ADDR_POS)) + +#define MXC_F_USB_DEV_CN_SIGRWU_POS 2 +#define MXC_F_USB_DEV_CN_SIGRWU ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_SIGRWU_POS)) +#define MXC_F_USB_DEV_CN_CONNECT_POS 3 +#define MXC_F_USB_DEV_CN_CONNECT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_CONNECT_POS)) +#define MXC_F_USB_DEV_CN_ULPM_POS 4 +#define MXC_F_USB_DEV_CN_ULPM ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_ULPM_POS)) +#define MXC_F_USB_DEV_CN_URST_POS 5 +#define MXC_F_USB_DEV_CN_URST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_URST_POS)) +#define MXC_F_USB_DEV_CN_VBGATE_POS 6 +#define MXC_F_USB_DEV_CN_VBGATE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_VBGATE_POS)) +#define MXC_F_USB_DEV_CN_FIFO_MODE_POS 9 +#define MXC_F_USB_DEV_CN_FIFO_MODE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_FIFO_MODE_POS)) + +#define MXC_F_USB_DEV_INTFL_DPACT_POS 0 +#define MXC_F_USB_DEV_INTFL_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DPACT_POS)) +#define MXC_F_USB_DEV_INTFL_RWU_DN_POS 1 +#define MXC_F_USB_DEV_INTFL_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_RWU_DN_POS)) +#define MXC_F_USB_DEV_INTFL_BACT_POS 2 +#define MXC_F_USB_DEV_INTFL_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BACT_POS)) +#define MXC_F_USB_DEV_INTFL_BRST_POS 3 +#define MXC_F_USB_DEV_INTFL_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_POS)) +#define MXC_F_USB_DEV_INTFL_SUSP_POS 4 +#define MXC_F_USB_DEV_INTFL_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SUSP_POS)) +#define MXC_F_USB_DEV_INTFL_NO_VBUS_POS 5 +#define MXC_F_USB_DEV_INTFL_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_NO_VBUS_POS)) +#define MXC_F_USB_DEV_INTFL_VBUS_POS 6 +#define MXC_F_USB_DEV_INTFL_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_POS)) +#define MXC_F_USB_DEV_INTFL_BRST_DN_POS 7 +#define MXC_F_USB_DEV_INTFL_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_DN_POS)) +#define MXC_F_USB_DEV_INTFL_SETUP_POS 8 +#define MXC_F_USB_DEV_INTFL_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SETUP_POS)) +#define MXC_F_USB_DEV_INTFL_EP_IN_POS 9 +#define MXC_F_USB_DEV_INTFL_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_IN_POS)) +#define MXC_F_USB_DEV_INTFL_EP_OUT_POS 10 +#define MXC_F_USB_DEV_INTFL_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_OUT_POS)) +#define MXC_F_USB_DEV_INTFL_EP_NAK_POS 11 +#define MXC_F_USB_DEV_INTFL_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_NAK_POS)) +#define MXC_F_USB_DEV_INTFL_DMA_ERR_POS 12 +#define MXC_F_USB_DEV_INTFL_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DMA_ERR_POS)) +#define MXC_F_USB_DEV_INTFL_BUF_OVR_POS 13 +#define MXC_F_USB_DEV_INTFL_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BUF_OVR_POS)) +#define MXC_F_USB_DEV_INTFL_VBUS_ST_POS 16 +#define MXC_F_USB_DEV_INTFL_VBUS_ST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_ST_POS)) + +#define MXC_F_USB_DEV_INTEN_DPACT_POS 0 +#define MXC_F_USB_DEV_INTEN_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DPACT_POS)) +#define MXC_F_USB_DEV_INTEN_RWU_DN_POS 1 +#define MXC_F_USB_DEV_INTEN_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_RWU_DN_POS)) +#define MXC_F_USB_DEV_INTEN_BACT_POS 2 +#define MXC_F_USB_DEV_INTEN_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BACT_POS)) +#define MXC_F_USB_DEV_INTEN_BRST_POS 3 +#define MXC_F_USB_DEV_INTEN_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_POS)) +#define MXC_F_USB_DEV_INTEN_SUSP_POS 4 +#define MXC_F_USB_DEV_INTEN_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SUSP_POS)) +#define MXC_F_USB_DEV_INTEN_NO_VBUS_POS 5 +#define MXC_F_USB_DEV_INTEN_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_NO_VBUS_POS)) +#define MXC_F_USB_DEV_INTEN_VBUS_POS 6 +#define MXC_F_USB_DEV_INTEN_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_VBUS_POS)) +#define MXC_F_USB_DEV_INTEN_BRST_DN_POS 7 +#define MXC_F_USB_DEV_INTEN_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_DN_POS)) +#define MXC_F_USB_DEV_INTEN_SETUP_POS 8 +#define MXC_F_USB_DEV_INTEN_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SETUP_POS)) +#define MXC_F_USB_DEV_INTEN_EP_IN_POS 9 +#define MXC_F_USB_DEV_INTEN_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_IN_POS)) +#define MXC_F_USB_DEV_INTEN_EP_OUT_POS 10 +#define MXC_F_USB_DEV_INTEN_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_OUT_POS)) +#define MXC_F_USB_DEV_INTEN_EP_NAK_POS 11 +#define MXC_F_USB_DEV_INTEN_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_NAK_POS)) +#define MXC_F_USB_DEV_INTEN_DMA_ERR_POS 12 +#define MXC_F_USB_DEV_INTEN_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DMA_ERR_POS)) +#define MXC_F_USB_DEV_INTEN_BUF_OVR_POS 13 +#define MXC_F_USB_DEV_INTEN_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BUF_OVR_POS)) + +#define MXC_F_USB_EP_BASE_EP_BASE_POS 9 +#define MXC_F_USB_EP_BASE_EP_BASE ((uint32_t)(0x007FFFFFUL << MXC_F_USB_EP_BASE_EP_BASE_POS)) + +#define MXC_F_USB_CUR_BUF_OUT_BUF_POS 0 +#define MXC_F_USB_CUR_BUF_OUT_BUF ((uint32_t)(0x000000FFUL << MXC_F_USB_CUR_BUF_OUT_BUF_POS)) +#define MXC_F_USB_CUR_BUF_IN_BUF_POS 16 +#define MXC_F_USB_CUR_BUF_IN_BUF ((uint32_t)(0x000000FFUL << MXC_F_USB_CUR_BUF_IN_BUF_POS)) + +#define MXC_F_USB_IN_OWNER_BUF0_OWNER_POS 0 +#define MXC_F_USB_IN_OWNER_BUF0_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_OWNER_BUF0_OWNER_POS)) +#define MXC_F_USB_IN_OWNER_BUF1_OWNER_POS 16 +#define MXC_F_USB_IN_OWNER_BUF1_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_OWNER_BUF1_OWNER_POS)) + +#define MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS 0 +#define MXC_F_USB_OUT_OWNER_BUF0_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS)) +#define MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS 16 +#define MXC_F_USB_OUT_OWNER_BUF1_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS)) + +#define MXC_F_USB_IN_INT_INBAV0_POS 0 +#define MXC_F_USB_IN_INT_INBAV0 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV0_POS)) +#define MXC_F_USB_IN_INT_INBAV1_POS 1 +#define MXC_F_USB_IN_INT_INBAV1 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV1_POS)) +#define MXC_F_USB_IN_INT_INBAV2_POS 2 +#define MXC_F_USB_IN_INT_INBAV2 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV2_POS)) +#define MXC_F_USB_IN_INT_INBAV3_POS 3 +#define MXC_F_USB_IN_INT_INBAV3 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV3_POS)) +#define MXC_F_USB_IN_INT_INBAV4_POS 4 +#define MXC_F_USB_IN_INT_INBAV4 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV4_POS)) +#define MXC_F_USB_IN_INT_INBAV5_POS 5 +#define MXC_F_USB_IN_INT_INBAV5 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV5_POS)) +#define MXC_F_USB_IN_INT_INBAV6_POS 6 +#define MXC_F_USB_IN_INT_INBAV6 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV6_POS)) +#define MXC_F_USB_IN_INT_INBAV7_POS 7 +#define MXC_F_USB_IN_INT_INBAV7 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV7_POS)) + +#define MXC_F_USB_OUT_INT_OUTDAV0_POS 0 +#define MXC_F_USB_OUT_INT_OUTDAV0 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV0_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV1_POS 1 +#define MXC_F_USB_OUT_INT_OUTDAV1 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV1_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV2_POS 2 +#define MXC_F_USB_OUT_INT_OUTDAV2 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV2_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV3_POS 3 +#define MXC_F_USB_OUT_INT_OUTDAV3 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV3_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV4_POS 4 +#define MXC_F_USB_OUT_INT_OUTDAV4 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV4_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV5_POS 5 +#define MXC_F_USB_OUT_INT_OUTDAV5 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV5_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV6_POS 6 +#define MXC_F_USB_OUT_INT_OUTDAV6 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV6_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV7_POS 7 +#define MXC_F_USB_OUT_INT_OUTDAV7 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV7_POS)) + +#define MXC_F_USB_NAK_INT_NAK0_POS 0 +#define MXC_F_USB_NAK_INT_NAK0 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK0_POS)) +#define MXC_F_USB_NAK_INT_NAK1_POS 1 +#define MXC_F_USB_NAK_INT_NAK1 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK1_POS)) +#define MXC_F_USB_NAK_INT_NAK2_POS 2 +#define MXC_F_USB_NAK_INT_NAK2 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK2_POS)) +#define MXC_F_USB_NAK_INT_NAK3_POS 3 +#define MXC_F_USB_NAK_INT_NAK3 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK3_POS)) +#define MXC_F_USB_NAK_INT_NAK4_POS 4 +#define MXC_F_USB_NAK_INT_NAK4 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK4_POS)) +#define MXC_F_USB_NAK_INT_NAK5_POS 5 +#define MXC_F_USB_NAK_INT_NAK5 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK5_POS)) +#define MXC_F_USB_NAK_INT_NAK6_POS 6 +#define MXC_F_USB_NAK_INT_NAK6 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK6_POS)) +#define MXC_F_USB_NAK_INT_NAK7_POS 7 +#define MXC_F_USB_NAK_INT_NAK7 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK7_POS)) + +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR0_POS 0 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR0 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR0_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR1_POS 1 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR1 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR1_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR2_POS 2 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR2 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR2_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR3_POS 3 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR3 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR3_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR4_POS 4 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR4 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR4_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR5_POS 5 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR5 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR5_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR6_POS 6 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR6 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR6_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR7_POS 7 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR7 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR7_POS)) + +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR0_POS 0 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR0 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR0_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR1_POS 1 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR1 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR1_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR2_POS 2 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR2 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR2_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR3_POS 3 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR3 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR3_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR4_POS 4 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR4 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR4_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR5_POS 5 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR5 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR5_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR6_POS 6 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR6 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR6_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR7_POS 7 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR7 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR7_POS)) + +#define MXC_F_USB_SETUP0_BYTE0_POS 0 +#define MXC_F_USB_SETUP0_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE0_POS)) +#define MXC_F_USB_SETUP0_BYTE1_POS 8 +#define MXC_F_USB_SETUP0_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE1_POS)) +#define MXC_F_USB_SETUP0_BYTE2_POS 16 +#define MXC_F_USB_SETUP0_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE2_POS)) +#define MXC_F_USB_SETUP0_BYTE3_POS 24 +#define MXC_F_USB_SETUP0_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE3_POS)) + +#define MXC_F_USB_SETUP1_BYTE4_POS 0 +#define MXC_F_USB_SETUP1_BYTE4 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE4_POS)) +#define MXC_F_USB_SETUP1_BYTE5_POS 8 +#define MXC_F_USB_SETUP1_BYTE5 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE5_POS)) +#define MXC_F_USB_SETUP1_BYTE6_POS 16 +#define MXC_F_USB_SETUP1_BYTE6 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE6_POS)) +#define MXC_F_USB_SETUP1_BYTE7_POS 24 +#define MXC_F_USB_SETUP1_BYTE7 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE7_POS)) + + +#define MXC_F_USB_EP0_EP_DIR_POS 0 +#define MXC_F_USB_EP0_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP0_EP_DIR_POS)) +#define MXC_F_USB_EP0_EP_BUF2_POS 3 +#define MXC_F_USB_EP0_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_BUF2_POS)) +#define MXC_F_USB_EP0_EP_INT_EN_POS 4 +#define MXC_F_USB_EP0_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_INT_EN_POS)) +#define MXC_F_USB_EP0_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP0_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_NAK_EN_POS)) +#define MXC_F_USB_EP0_EP_DT_POS 6 +#define MXC_F_USB_EP0_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_DT_POS)) +#define MXC_F_USB_EP0_EP_STALL_POS 8 +#define MXC_F_USB_EP0_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_STALL_POS)) +#define MXC_F_USB_EP0_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP0_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_ST_STALL_POS)) +#define MXC_F_USB_EP0_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP0_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP1_EP_DIR_POS 0 +#define MXC_F_USB_EP1_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP1_EP_DIR_POS)) +#define MXC_F_USB_EP1_EP_BUF2_POS 3 +#define MXC_F_USB_EP1_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_BUF2_POS)) +#define MXC_F_USB_EP1_EP_INT_EN_POS 4 +#define MXC_F_USB_EP1_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_INT_EN_POS)) +#define MXC_F_USB_EP1_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP1_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_NAK_EN_POS)) +#define MXC_F_USB_EP1_EP_DT_POS 6 +#define MXC_F_USB_EP1_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_DT_POS)) +#define MXC_F_USB_EP1_EP_STALL_POS 8 +#define MXC_F_USB_EP1_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_STALL_POS)) +#define MXC_F_USB_EP1_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP1_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_ST_STALL_POS)) +#define MXC_F_USB_EP1_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP1_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP2_EP_DIR_POS 0 +#define MXC_F_USB_EP2_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP2_EP_DIR_POS)) +#define MXC_F_USB_EP2_EP_BUF2_POS 3 +#define MXC_F_USB_EP2_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_BUF2_POS)) +#define MXC_F_USB_EP2_EP_INT_EN_POS 4 +#define MXC_F_USB_EP2_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_INT_EN_POS)) +#define MXC_F_USB_EP2_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP2_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_NAK_EN_POS)) +#define MXC_F_USB_EP2_EP_DT_POS 6 +#define MXC_F_USB_EP2_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_DT_POS)) +#define MXC_F_USB_EP2_EP_STALL_POS 8 +#define MXC_F_USB_EP2_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_STALL_POS)) +#define MXC_F_USB_EP2_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP2_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_ST_STALL_POS)) +#define MXC_F_USB_EP2_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP2_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP3_EP_DIR_POS 0 +#define MXC_F_USB_EP3_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP3_EP_DIR_POS)) +#define MXC_F_USB_EP3_EP_BUF2_POS 3 +#define MXC_F_USB_EP3_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_BUF2_POS)) +#define MXC_F_USB_EP3_EP_INT_EN_POS 4 +#define MXC_F_USB_EP3_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_INT_EN_POS)) +#define MXC_F_USB_EP3_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP3_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_NAK_EN_POS)) +#define MXC_F_USB_EP3_EP_DT_POS 6 +#define MXC_F_USB_EP3_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_DT_POS)) +#define MXC_F_USB_EP3_EP_STALL_POS 8 +#define MXC_F_USB_EP3_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_STALL_POS)) +#define MXC_F_USB_EP3_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP3_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_ST_STALL_POS)) +#define MXC_F_USB_EP3_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP3_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP4_EP_DIR_POS 0 +#define MXC_F_USB_EP4_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP4_EP_DIR_POS)) +#define MXC_F_USB_EP4_EP_BUF2_POS 3 +#define MXC_F_USB_EP4_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_BUF2_POS)) +#define MXC_F_USB_EP4_EP_INT_EN_POS 4 +#define MXC_F_USB_EP4_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_INT_EN_POS)) +#define MXC_F_USB_EP4_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP4_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_NAK_EN_POS)) +#define MXC_F_USB_EP4_EP_DT_POS 6 +#define MXC_F_USB_EP4_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_DT_POS)) +#define MXC_F_USB_EP4_EP_STALL_POS 8 +#define MXC_F_USB_EP4_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_STALL_POS)) +#define MXC_F_USB_EP4_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP4_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_ST_STALL_POS)) +#define MXC_F_USB_EP4_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP4_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP5_EP_DIR_POS 0 +#define MXC_F_USB_EP5_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP5_EP_DIR_POS)) +#define MXC_F_USB_EP5_EP_BUF2_POS 3 +#define MXC_F_USB_EP5_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_BUF2_POS)) +#define MXC_F_USB_EP5_EP_INT_EN_POS 4 +#define MXC_F_USB_EP5_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_INT_EN_POS)) +#define MXC_F_USB_EP5_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP5_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_NAK_EN_POS)) +#define MXC_F_USB_EP5_EP_DT_POS 6 +#define MXC_F_USB_EP5_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_DT_POS)) +#define MXC_F_USB_EP5_EP_STALL_POS 8 +#define MXC_F_USB_EP5_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_STALL_POS)) +#define MXC_F_USB_EP5_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP5_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_ST_STALL_POS)) +#define MXC_F_USB_EP5_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP5_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP6_EP_DIR_POS 0 +#define MXC_F_USB_EP6_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP6_EP_DIR_POS)) +#define MXC_F_USB_EP6_EP_BUF2_POS 3 +#define MXC_F_USB_EP6_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_BUF2_POS)) +#define MXC_F_USB_EP6_EP_INT_EN_POS 4 +#define MXC_F_USB_EP6_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_INT_EN_POS)) +#define MXC_F_USB_EP6_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP6_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_NAK_EN_POS)) +#define MXC_F_USB_EP6_EP_DT_POS 6 +#define MXC_F_USB_EP6_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_DT_POS)) +#define MXC_F_USB_EP6_EP_STALL_POS 8 +#define MXC_F_USB_EP6_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_STALL_POS)) +#define MXC_F_USB_EP6_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP6_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_ST_STALL_POS)) +#define MXC_F_USB_EP6_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP6_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP7_EP_DIR_POS 0 +#define MXC_F_USB_EP7_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP7_EP_DIR_POS)) +#define MXC_F_USB_EP7_EP_BUF2_POS 3 +#define MXC_F_USB_EP7_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_BUF2_POS)) +#define MXC_F_USB_EP7_EP_INT_EN_POS 4 +#define MXC_F_USB_EP7_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_INT_EN_POS)) +#define MXC_F_USB_EP7_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP7_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_NAK_EN_POS)) +#define MXC_F_USB_EP7_EP_DT_POS 6 +#define MXC_F_USB_EP7_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_DT_POS)) +#define MXC_F_USB_EP7_EP_STALL_POS 8 +#define MXC_F_USB_EP7_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_STALL_POS)) +#define MXC_F_USB_EP7_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP7_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_ST_STALL_POS)) +#define MXC_F_USB_EP7_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP7_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_ST_ACK_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_USB_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/wdt_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/wdt_regs.h new file mode 100644 index 0000000000..906e801460 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/wdt_regs.h @@ -0,0 +1,150 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_WDT_REGS_H_ +#define _MXC_WDT_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file wdt_regs.h + * @addtogroup wdt WDT + * @{ + */ + +/** + * @brief Defines watchdog timer periods + */ +typedef enum { + /** 2^31 cycle period */ + MXC_E_WDT_PERIOD_2_31_CLKS = 0, + /** 2^30 cycle period */ + MXC_E_WDT_PERIOD_2_30_CLKS, + /** 2^29 cycle period */ + MXC_E_WDT_PERIOD_2_29_CLKS, + /** 2^28 cycle period */ + MXC_E_WDT_PERIOD_2_28_CLKS, + /** 2^27 cycle period */ + MXC_E_WDT_PERIOD_2_27_CLKS, + /** 2^26 cycle period */ + MXC_E_WDT_PERIOD_2_26_CLKS, + /** 2^25 cycle period */ + MXC_E_WDT_PERIOD_2_25_CLKS, + /** 2^24 cycle period */ + MXC_E_WDT_PERIOD_2_24_CLKS, + /** 2^23 cycle period */ + MXC_E_WDT_PERIOD_2_23_CLKS, + /** 2^22 cycle period */ + MXC_E_WDT_PERIOD_2_22_CLKS, + /** 2^21 cycle period */ + MXC_E_WDT_PERIOD_2_21_CLKS, + /** 2^20 cycle period */ + MXC_E_WDT_PERIOD_2_20_CLKS, + /** 2^19 cycle period */ + MXC_E_WDT_PERIOD_2_19_CLKS, + /** 2^18 cycle period */ + MXC_E_WDT_PERIOD_2_18_CLKS, + /** 2^17 cycle period */ + MXC_E_WDT_PERIOD_2_17_CLKS, + /** 2^16 cycle period */ + MXC_E_WDT_PERIOD_2_16_CLKS, +} mxc_wdt_period_t; + +/* Offset Register Description + ====== ================================================ */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 Watchdog Timer Control Register */ + __IO uint32_t clear; /* 0x0004 Watchdog Clear Register (Feed Dog) */ + __IO uint32_t int_rst_fl; /* 0x0008 Watchdog Interrupt/Reset Flags */ + __IO uint32_t int_rst_en; /* 0x000C Interrupt/Reset Enable/Disable Controls */ + __I uint32_t rsv0010; /* 0x0010 */ + __IO uint32_t lock_ctrl; /* 0x0014 Lock Register Setting for WDT CTRL */ +} mxc_wdt_regs_t; + +/* + Register offsets for module WDT. +*/ +#define MXC_R_WDT_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_WDT_OFFS_CLEAR ((uint32_t)0x00000004UL) +#define MXC_R_WDT_OFFS_INT_RST_FL ((uint32_t)0x00000008UL) +#define MXC_R_WDT_OFFS_INT_RST_EN ((uint32_t)0x0000000CUL) +#define MXC_R_WDT_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL) + +#define MXC_V_WDT_WDLOCK_LOCK_KEY ((uint8_t)0x24) +#define MXC_V_WDT_WDLOCK_UNLOCK_KEY ((uint8_t)0x42) + + +/* + Field positions and masks for module WDT. +*/ +#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 +#define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) +#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 +#define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) +#define MXC_F_WDT_CTRL_EN_TIMER_POS 8 +#define MXC_F_WDT_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS)) +#define MXC_F_WDT_CTRL_EN_CLOCK_POS 9 +#define MXC_F_WDT_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS)) +#define MXC_F_WDT_CTRL_WAIT_PERIOD_POS 12 +#define MXC_F_WDT_CTRL_WAIT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) + +#define MXC_F_WDT_FLAGS_TIMEOUT_POS 0 +#define MXC_F_WDT_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS)) +#define MXC_F_WDT_FLAGS_PRE_WIN_POS 1 +#define MXC_F_WDT_FLAGS_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS)) +#define MXC_F_WDT_FLAGS_RESET_OUT_POS 2 +#define MXC_F_WDT_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS)) + +#define MXC_F_WDT_ENABLE_TIMEOUT_POS 0 +#define MXC_F_WDT_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS)) +#define MXC_F_WDT_ENABLE_PRE_WIN_POS 1 +#define MXC_F_WDT_ENABLE_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS)) +#define MXC_F_WDT_ENABLE_RESET_OUT_POS 2 +#define MXC_F_WDT_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS)) + +#define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS 0 +#define MXC_F_WDT_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_WDT_REGS_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralNames.h new file mode 100644 index 0000000000..5000bc6451 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralNames.h @@ -0,0 +1,87 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = MXC_BASE_UART0, + UART_1 = MXC_BASE_UART1 +} UARTName; + +typedef enum { + I2C_0 = MXC_BASE_I2CM0, + I2C_1 = MXC_BASE_I2CM1 +} I2CName; + +typedef enum { + SPI_0 = MXC_BASE_SPI0, + SPI_1 = MXC_BASE_SPI1, + SPI_2 = MXC_BASE_SPI2 +} SPIName; + +typedef enum { + PWM_0 = MXC_BASE_PT0, + PWM_1 = MXC_BASE_PT1, + PWM_2 = MXC_BASE_PT2, + PWM_3 = MXC_BASE_PT3, + PWM_4 = MXC_BASE_PT4, + PWM_5 = MXC_BASE_PT5, + PWM_6 = MXC_BASE_PT6, + PWM_7 = MXC_BASE_PT7 +} PWMName; + +typedef enum { + ADC = MXC_BASE_ADC +} ADCName; + +typedef enum { + DAC0 = MXC_BASE_DAC0, + DAC1 = MXC_BASE_DAC1, + DAC2 = MXC_BASE_DAC2, + DAC3 = MXC_BASE_DAC3, +} DACName; + +#include "PeripheralAliases.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c new file mode 100644 index 0000000000..def88c99aa --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c @@ -0,0 +1,186 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "device.h" +#include "PeripheralPins.h" +#include "ioman_regs.h" + +/* + * To select a peripheral function on Maxim microcontrollers, multiple + * configurations must be made. The mbed PinMap structure only includes one + * data member to hold this information. To extend the configuration storage, + * the "function" data member is used as a pointer to a pin_function_t + * structure. This structure is defined in objects.h. The definitions below + * include the creation of the pin_function_t structures and the assignment of + * the pointers to the "function" data members. + */ + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + { P0_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P0_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_H | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_I2C_SCL[] = { + { P0_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P0_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_H | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { NC, NC, 0 } +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + { P1_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P1_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P2_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P2_5, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_UART_RX[] = { + { P1_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P1_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P2_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P2_4, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_UART_CTS[] = { + { P1_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) }, + { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) }, + { P2_4, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) }, + { P2_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) }, + { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_UART_RTS[] = { + { P1_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) }, + { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) }, + { P2_5, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) }, + { P2_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) }, + { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) }, + { NC, NC, 0 } +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + { P0_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { NC, NC, 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + { P0_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + { P0_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + { P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) }, + { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO)}) }, + { NC, NC, 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {P0_0, PWM_0, 1}, {P0_0, PWM_0, 2}, {P0_0, PWM_4, 3}, + {P0_1, PWM_0, 3}, {P0_1, PWM_1, 1}, {P0_1, PWM_4, 2}, + {P0_2, PWM_1, 2}, {P0_2, PWM_2, 1}, {P0_2, PWM_5, 3}, + {P0_3, PWM_1, 3}, {P0_3, PWM_3, 1}, {P0_3, PWM_5, 2}, + {P0_4, PWM_2, 2}, {P0_4, PWM_4, 1}, {P0_4, PWM_6, 3}, + {P0_5, PWM_2, 3}, {P0_5, PWM_5, 1}, {P0_5, PWM_6, 2}, + {P0_6, PWM_3, 2}, {P0_6, PWM_6, 1}, {P0_6, PWM_7, 3}, + {P0_7, PWM_3, 3}, {P0_7, PWM_7, 1}, {P0_7, PWM_7, 2}, + + {P1_0, PWM_0, 1}, {P1_0, PWM_0, 2}, {P1_0, PWM_4, 3}, + {P1_1, PWM_0, 3}, {P1_1, PWM_1, 1}, {P1_1, PWM_4, 2}, + {P1_2, PWM_1, 2}, {P1_2, PWM_2, 1}, {P1_2, PWM_5, 3}, + {P1_3, PWM_1, 3}, {P1_3, PWM_3, 1}, {P1_3, PWM_5, 2}, + {P1_4, PWM_2, 2}, {P1_4, PWM_4, 1}, {P1_4, PWM_6, 3}, + {P1_5, PWM_2, 3}, {P1_5, PWM_5, 1}, {P1_5, PWM_6, 2}, + {P1_6, PWM_3, 2}, {P1_6, PWM_6, 1}, {P1_6, PWM_7, 3}, + {P1_7, PWM_3, 3}, {P1_7, PWM_7, 1}, {P1_7, PWM_7, 2}, + + {P2_0, PWM_0, 1}, {P2_0, PWM_0, 2}, {P2_0, PWM_4, 3}, + {P2_1, PWM_0, 3}, {P2_1, PWM_1, 1}, {P2_1, PWM_4, 2}, + {P2_2, PWM_1, 2}, {P2_2, PWM_2, 1}, {P2_2, PWM_5, 3}, + {P2_3, PWM_1, 3}, {P2_3, PWM_3, 1}, {P2_3, PWM_5, 2}, + {P2_4, PWM_2, 2}, {P2_4, PWM_4, 1}, {P2_4, PWM_6, 3}, + {P2_5, PWM_2, 3}, {P2_5, PWM_5, 1}, {P2_5, PWM_6, 2}, + {P2_6, PWM_3, 2}, {P2_6, PWM_6, 1}, {P2_6, PWM_7, 3}, + {P2_7, PWM_3, 3}, {P2_7, PWM_7, 1}, {P2_7, PWM_7, 2}, + {NC, NC, 0} +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {AIN_0P, ADC, 0}, + {AIN_1P, ADC, 0}, + {AIN_2P, ADC, 0}, + {AIN_3P, ADC, 0}, + {AIN_4P, ADC, 0}, + {AIN_5P, ADC, 0}, + {AIN_0N, ADC, 0}, + {AIN_1N, ADC, 0}, + {AIN_2N, ADC, 0}, + {AIN_3N, ADC, 0}, + {AIN_4N, ADC, 0}, + {AIN_5N, ADC, 0}, + {AIN_0D, ADC, 1}, + {AIN_1D, ADC, 1}, + {AIN_2D, ADC, 1}, + {AIN_3D, ADC, 1}, + {AIN_4D, ADC, 1}, + {AIN_5D, ADC, 1}, + {NC, NC, 0} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {AOUT_AO, DAC0, 0}, + {AOUT_BO, DAC1, 0}, + {AOUT_CO, DAC2, 0}, + {AOUT_DO, DAC3, 0}, + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.h new file mode 100644 index 0000000000..c06ab368b6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.h @@ -0,0 +1,65 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_CTS[]; +extern const PinMap PinMap_UART_RTS[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************DAC***************/ +extern const PinMap PinMap_DAC[]; + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PinNames.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PinNames.h new file mode 100644 index 0000000000..b172fc608b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PinNames.h @@ -0,0 +1,136 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "gpio_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT = MXC_V_GPIO_OUT_MODE_HIGH_Z, + PIN_OUTPUT = MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE +} PinDirection; + +#define PORT_SHIFT 12 +#define PINNAME_TO_PORT(name) ((unsigned int)(name) >> PORT_SHIFT) +#define PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << PORT_SHIFT)) + +typedef enum { + P0_0 = (0 << PORT_SHIFT) | 0, + P0_1 = (0 << PORT_SHIFT) | 1, + P0_2 = (0 << PORT_SHIFT) | 2, + P0_3 = (0 << PORT_SHIFT) | 3, + P0_4 = (0 << PORT_SHIFT) | 4, + P0_5 = (0 << PORT_SHIFT) | 5, + P0_6 = (0 << PORT_SHIFT) | 6, + P0_7 = (0 << PORT_SHIFT) | 7, + P1_0 = (1 << PORT_SHIFT) | 0, + P1_1 = (1 << PORT_SHIFT) | 1, + P1_2 = (1 << PORT_SHIFT) | 2, + P1_3 = (1 << PORT_SHIFT) | 3, + P1_4 = (1 << PORT_SHIFT) | 4, + P1_5 = (1 << PORT_SHIFT) | 5, + P1_6 = (1 << PORT_SHIFT) | 6, + P1_7 = (1 << PORT_SHIFT) | 7, + P2_0 = (2 << PORT_SHIFT) | 0, + P2_1 = (2 << PORT_SHIFT) | 1, + P2_2 = (2 << PORT_SHIFT) | 2, + P2_3 = (2 << PORT_SHIFT) | 3, + P2_4 = (2 << PORT_SHIFT) | 4, + P2_5 = (2 << PORT_SHIFT) | 5, + P2_6 = (2 << PORT_SHIFT) | 6, + P2_7 = (2 << PORT_SHIFT) | 7, + + // Analog ADC pins + AIN_0P = (0xA << PORT_SHIFT) | 0, + AIN_1P = (0xA << PORT_SHIFT) | 1, + AIN_2P = (0xA << PORT_SHIFT) | 2, + AIN_3P = (0xA << PORT_SHIFT) | 3, + AIN_4P = (0xA << PORT_SHIFT) | 4, + AIN_5P = (0xA << PORT_SHIFT) | 5, + AIN_0N = (0xB << PORT_SHIFT) | 0, + AIN_1N = (0xB << PORT_SHIFT) | 1, + AIN_2N = (0xB << PORT_SHIFT) | 2, + AIN_3N = (0xB << PORT_SHIFT) | 3, + AIN_4N = (0xB << PORT_SHIFT) | 4, + AIN_5N = (0xB << PORT_SHIFT) | 5, + + // Analog differential ADC + AIN_0D = (0xC << PORT_SHIFT) | 0, + AIN_1D = (0xC << PORT_SHIFT) | 1, + AIN_2D = (0xC << PORT_SHIFT) | 2, + AIN_3D = (0xC << PORT_SHIFT) | 3, + AIN_4D = (0xC << PORT_SHIFT) | 4, + AIN_5D = (0xC << PORT_SHIFT) | 5, + + // OPAMP Positive supply pins + AOUT_AP = (0xD << PORT_SHIFT) | 0, + AOUT_BP = (0xD << PORT_SHIFT) | 1, + AOUT_CP = (0xD << PORT_SHIFT) | 2, + AOUT_DP = (0xD << PORT_SHIFT) | 3, + + // OPAMP Negative supply pins + AOUT_AN = (0xE << PORT_SHIFT) | 0, + AOUT_BN = (0xE << PORT_SHIFT) | 1, + AOUT_CN = (0xE << PORT_SHIFT) | 2, + AOUT_DN = (0xE << PORT_SHIFT) | 3, + + // DAC Output pins + AOUT_AO = (0xF << PORT_SHIFT) | 0, + AOUT_BO = (0xF << PORT_SHIFT) | 1, + AOUT_CO = (0xF << PORT_SHIFT) | 2, + AOUT_DO = (0xF << PORT_SHIFT) | 3, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullUp, + OpenDrain, + PullNone, + PullDefault = PullUp +} PinMode; + +#include "PinAliases.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PortNames.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PortNames.h new file mode 100644 index 0000000000..9dd2de18f2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PortNames.h @@ -0,0 +1,50 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, + Port1 = 1, + Port2 = 2 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PeripheralAliases.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PeripheralAliases.h new file mode 100644 index 0000000000..0fdf2267e3 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PeripheralAliases.h @@ -0,0 +1,41 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _PERIPHERAL_ALIASES_H +#define _PERIPHERAL_ALIASES_H + +#define STDIO_UART UART_1 +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#endif /* _PERIPHERAL_ALIASES_H */ diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PinAliases.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PinAliases.h new file mode 100644 index 0000000000..95ebfa14d4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PinAliases.h @@ -0,0 +1,74 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _PIN_ALIASES_H +#define _PIN_ALIASES_H + +#define LED_RED P1_7 +#define LED_GREEN P1_6 +#define LED_BLUE P1_4 + +// mbed original LED naming +#define LED1 LED_RED +#define LED2 LED_GREEN +#define LED3 LED_BLUE +#define LED4 LED_BLUE + +#define LED_OFF 1 +#define LED_ON !LED_OFF + +// Push button +#define SW1 P1_5 + +// USB Pins +#define USBTX P1_3 +#define USBRX P1_2 + +#define I2C_SCL P0_5 +#define I2C_SDA P0_4 + +#define HCI_SCK P2_0 +#define HCI_MOSI P2_1 +#define HCI_MISO P2_2 +#define HCI_CSN P2_3 +#define HCI_IRQ P2_4 +#define HCI_RST P2_5 + +#define TP1 P1_1 +#define TP2 P1_0 +#define TP3 P0_1 +#define TP4 P0_0 +#define TP5 P0_5 +#define TP6 P0_4 + +#endif /* _PIN_ALIASES_H */ diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/low_level_init.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/low_level_init.c new file mode 100644 index 0000000000..906fa7d81e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/low_level_init.c @@ -0,0 +1,48 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "cmsis.h" +#include "gpio_regs.h" +#include "clkman_regs.h" + +//****************************************************************************** +// This function will get called early in system initialization +void low_level_init(void) +{ + /* set pins connected to EM9301 to output low */ + MXC_GPIO->out_val[2] = 0x00; + MXC_GPIO->out_mode[2] = 0x00555555; + + /* wait for the RO to stabilize */ + while (!(MXC_CLKMAN->intfl & MXC_F_CLKMAN_INTFL_RING_STABLE)); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogin_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogin_api.c new file mode 100644 index 0000000000..2d64a187e0 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogin_api.c @@ -0,0 +1,144 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "analogin_api.h" +#include "clkman_regs.h" +#include "pwrman_regs.h" +#include "afe_regs.h" +#include "PeripheralPins.h" + +#define PGA_TRK_CNT 0x8 +#define ADC_ACT_CNT 0x1 +#define ADC_PGA_CNT 0x1 +#define ADC_ACQ_CNT 0x1 +#define ADC_SLP_CNT 0x0 + +//****************************************************************************** +void analogin_init(analogin_t *obj, PinName pin) +{ + // Make sure pin is an analog pin we can use for ADC + MBED_ASSERT((ADCName)pinmap_peripheral(pin, PinMap_ADC) != (ADCName)NC); + + // Set the object pointer + obj->adc = MXC_ADC; + obj->adccfg = MXC_ADCCFG; + obj->adc_fifo = MXC_ADC_FIFO; + obj->adc_pin = pin; + + // Set the ADC clock to the system clock frequency + MXC_SET_FIELD(&MXC_CLKMAN->clk_ctrl, MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT, + (MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N | (MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM << + MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS))); + + // Enable AFE power + MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED; + + // Setup and hold window + MXC_SET_FIELD(&obj->adc->tg_ctrl0, MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT, PGA_TRK_CNT); + + // Setup sampling count and timing + MXC_SET_FIELD(&obj->adc->tg_ctrl1, (MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT | + MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT | MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT), + ((ADC_PGA_CNT << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS) | + (ADC_ACQ_CNT << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS) | + (ADC_SLP_CNT << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS) | + (MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT))); +} + +//****************************************************************************** +float analogin_read(analogin_t *obj) +{ + // Convert integer to float + return (((float)analogin_read_u16(obj)/(float)0xFFFF)); +} + +//****************************************************************************** +uint16_t analogin_read_u16(analogin_t *obj) +{ + // Set the pin to take readings from + unsigned mux_pos; + unsigned diff = 0; + if(obj->adc_pin >> PORT_SHIFT == 0xB) { + mux_pos = (obj->adc_pin & 0xF) + 8; + } else { + mux_pos = (obj->adc_pin & 0xF); + } + + if(obj->adc_pin >> PORT_SHIFT == 0xC) { + diff = 1; + mux_pos = (obj->adc_pin & 0xF) + 8; + } + + // Setup the ADC clock + MXC_SET_FIELD(&obj->adc->ctrl0, (MXC_F_ADC_CTRL0_ADC_MODE | MXC_F_ADC_CTRL0_AVG_MODE | + MXC_F_ADC_CTRL0_ADC_CLK_MODE | MXC_F_ADC_CTRL0_ADC_BI_POL), + ((MXC_E_ADC_MODE_SMPLCNT_FULL_RATE << MXC_F_ADC_CTRL0_ADC_MODE_POS) | + (MXC_E_ADC_AVG_MODE_FILTER_OUTPUT << MXC_F_ADC_CTRL0_AVG_MODE_POS) | + (0x2 << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS) | + MXC_F_ADC_CTRL0_ADC_CLK_EN)); + + // Setup the input multiplexor + MXC_SET_FIELD(&obj->adc->pga_ctrl, (MXC_F_ADC_PGA_CTRL_MUX_CH_SEL | + MXC_F_ADC_PGA_CTRL_MUX_DIFF | MXC_F_ADC_PGA_CTRL_PGA_GAIN), + ((mux_pos << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS) | + (diff << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS))); + + // Setup voltage reference + MXC_SET_FIELD(&MXC_AFE->ctrl1, MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL, + (MXC_F_AFE_CTRL1_REF_ADC_POWERUP | MXC_F_AFE_CTRL1_REF_BLK_POWERUP | + (MXC_E_AFE_REF_VOLT_SEL_1500 << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS))); + + // Enable the ADC + obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_EN; + + // Clear the done bit + obj->adc->intr = MXC_F_ADC_INTR_DONE_IF; + + // Take one sample + obj->adc->tg_ctrl0 |= (1 << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS); + + // Set the start bit to take the sample + obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_START; + + // Wait for the conversion to complete + while(!(obj->adc->intr & MXC_F_ADC_INTR_DONE_IF)) {} + + // Get sample from the fifo + uint16_t sample = (uint16_t)(obj->adc->out & 0xFFFF); + + // Disable ADC + obj->adc->ctrl0 &= ~MXC_F_ADC_CTRL0_CPU_ADC_EN; + + return (sample - 1); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogout_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogout_api.c new file mode 100644 index 0000000000..00ca4e9936 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogout_api.c @@ -0,0 +1,213 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "analogout_api.h" +#include "clkman_regs.h" +#include "pwrman_regs.h" +#include "afe_regs.h" +#include "PeripheralPins.h" + +//****************************************************************************** +void analogout_init(dac_t *obj, PinName pin) +{ + // Make sure pin is an analog pin we can use for ADC + DACName dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); + MBED_ASSERT((DACName)dac != (DACName)NC); + + // Set the object pointer + obj->dac = ((mxc_dac_regs_t*)MXC_DAC_GET_DAC((pin & 0x3))); + obj->dac_fifo = ((mxc_dac_fifo_t*)MXC_DAC_GET_FIFO((pin & 0x3))); + obj->index = (pin & 0x3); + + // Set the ADC clock to the system clock frequency + MXC_SET_FIELD(&MXC_CLKMAN->clk_ctrl, MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT, + (MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N | (MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM << + MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS))); + + + // Setup the OPAMP in follower mode + switch(obj->index) { + case 0: + // Enable DAC clock + MXC_CLKMAN->clk_ctrl_14_dac0 = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Enable OPAMP + MXC_AFE->ctrl5 &= ~MXC_F_AFE_CTRL5_OP_CMP0; + + // Set the positive and negative inputs + MXC_SET_FIELD(&MXC_AFE->ctrl4, (MXC_F_AFE_CTRL4_DAC_SEL_A | + MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0 | MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0), + ((0x1 << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS) | + (0x1 << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS) | + (0x0 << MXC_F_AFE_CTRL4_DAC_SEL_A_POS))); + + // Enable N and P channel inputs + MXC_AFE->ctrl3 |= (MXC_F_AFE_CTRL3_EN_PCH_OPAMP0 | + MXC_F_AFE_CTRL3_EN_NCH_OPAMP0); + break; + case 1: + // Enable DAC clock + MXC_CLKMAN->clk_ctrl_15_dac1 = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Enable OPAMP + MXC_AFE->ctrl5 &= ~MXC_F_AFE_CTRL5_OP_CMP1; + + // Set the positive and negative inputs + MXC_SET_FIELD(&MXC_AFE->ctrl4, (MXC_F_AFE_CTRL4_DAC_SEL_B | + MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1 | MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1), + ((0x1 << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS) | + (0x1 << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS) | + (0x1 << MXC_F_AFE_CTRL4_DAC_SEL_B_POS))); + + // Enable N and P channel inputs + MXC_AFE->ctrl3 |= (MXC_F_AFE_CTRL3_EN_PCH_OPAMP1 | + MXC_F_AFE_CTRL3_EN_NCH_OPAMP1); + + break; + case 2: + // Enable DAC clock + MXC_CLKMAN->clk_ctrl_16_dac2 = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Enable OPAMP + MXC_AFE->ctrl5 &= ~MXC_F_AFE_CTRL5_OP_CMP2; + + // Set the positive and negative inputs + MXC_SET_FIELD(&MXC_AFE->ctrl4, (MXC_F_AFE_CTRL4_DAC_SEL_C | + MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2 | MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2), + ((0x1 << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS) | + (0x1 << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS) | + (0x2 << MXC_F_AFE_CTRL4_DAC_SEL_C_POS))); + + // Enable N and P channel inputs + MXC_AFE->ctrl3 |= (MXC_F_AFE_CTRL3_EN_PCH_OPAMP2 | + MXC_F_AFE_CTRL3_EN_NCH_OPAMP2); + break; + case 3: + // Enable DAC clock + MXC_CLKMAN->clk_ctrl_17_dac3 = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Enable OPAMP + MXC_AFE->ctrl5 &= ~MXC_F_AFE_CTRL5_OP_CMP3; + + // Set the positive and negative inputs + MXC_SET_FIELD(&MXC_AFE->ctrl4, (MXC_F_AFE_CTRL4_DAC_SEL_D | + MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3 | MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3), + ((0x1 << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS) | + (0x1 << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS) | + (0x3 << MXC_F_AFE_CTRL4_DAC_SEL_D_POS))); + + // Enable N and P channel inputs + MXC_AFE->ctrl3 |= (MXC_F_AFE_CTRL3_EN_PCH_OPAMP3 | + MXC_F_AFE_CTRL3_EN_NCH_OPAMP3); + break; + } + + // Enable AFE power + MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED; + + // Setup internal voltage references + MXC_SET_FIELD(&MXC_AFE->ctrl1, (MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL | MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL), + (MXC_F_AFE_CTRL1_REF_ADC_POWERUP | MXC_F_AFE_CTRL1_REF_BLK_POWERUP | + (MXC_E_AFE_REF_VOLT_SEL_1500 << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS))); + + // Disable interpolation + obj->dac->ctrl0 &= MXC_F_DAC_CTRL0_INTERP_MODE; +} + +//****************************************************************************** +void analogout_write(dac_t *obj, float value) +{ + analogout_write_u16(obj, (uint16_t)((value/1.0) * 0xFFFF)); +} + +//****************************************************************************** +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + // Enable the OPAMP + // Setup the OPAMP in follower mode + switch(obj->index) { + case 0: + MXC_AFE->ctrl3 |= MXC_F_AFE_CTRL3_POWERUP_OPAMP0; + break; + case 1: + MXC_AFE->ctrl3 |= MXC_F_AFE_CTRL3_POWERUP_OPAMP1; + break; + case 2: + MXC_AFE->ctrl3 |= MXC_F_AFE_CTRL3_POWERUP_OPAMP2; + break; + case 3: + MXC_AFE->ctrl3 |= MXC_F_AFE_CTRL3_POWERUP_OPAMP3; + break; + } + + // Output 1 sample with minimal delay + obj->dac->rate |= 0x1; + + // Set the start mode to output once data is in the FIFO + obj->dac->ctrl0 &= ~(MXC_F_DAC_CTRL0_START_MODE | MXC_F_DAC_CTRL0_OP_MODE); + + // Enable the DAC + obj->dac->ctrl0 |= (MXC_F_DAC_CTRL0_POWER_MODE_2 | + MXC_F_DAC_CTRL0_POWER_MODE_1_0 | MXC_F_DAC_CTRL0_POWER_ON | + MXC_F_DAC_CTRL0_CLOCK_GATE_EN | MXC_F_DAC_CTRL0_CPU_START); + + if(obj->index < 2) { + // Convert 16 bits to 12 bits + obj->out = (value >> 4); + obj->dac_fifo->output_16 = (obj->out); + + } else { + // Convert 16 bits to 8 bits + obj->out = (value >> 8); + obj->dac_fifo->output_8 = (obj->out); + } +} + +//****************************************************************************** +float analogout_read(dac_t *obj) +{ + return (((float)analogout_read_u16(obj) / (float)0xFFFF) * 1.5); +} + +//****************************************************************************** +uint16_t analogout_read_u16(dac_t *obj) +{ + if(obj->index < 2) { + // Convert 12 bits to 16 bits + return (obj->out << 4); + } else { + // Convert 8 bits to 16 bits + return (obj->out << 8); + } +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/device.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/device.h new file mode 100644 index 0000000000..59ff712fe9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/device.h @@ -0,0 +1,72 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_SERIAL_FC 1 + +#define DEVICE_SPI 1 + +#define DEVICE_I2C 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_ANALOGIN 1 + +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_RTC 1 + +#define DEVICE_SLEEP 1 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_PATTERN 1 + +#define DEVICE_CAN 0 +#define DEVICE_ETHERNET 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_api.c new file mode 100644 index 0000000000..2b1c1986ec --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_api.c @@ -0,0 +1,94 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "gpio_api.h" +#include "pinmap.h" +#include "gpio_regs.h" +#include "clkman_regs.h" + +uint32_t gpio_set(PinName name) +{ + MBED_ASSERT(name != (PinName)NC); + pin_function(name, 0); + return 1 << PINNAME_TO_PIN(name); +} + +void gpio_init(gpio_t *obj, PinName name) +{ + obj->name = name; + if (name == (PinName)NC) { + return; + } + + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + + obj->reg_out = (uint32_t*)BITBAND(&MXC_GPIO->out_val[port], pin); + obj->reg_in = (uint32_t*)BITBAND(&MXC_GPIO->in_val[port], pin); + + /* Ensure that the GPIO clock is enabled */ + if (MXC_CLKMAN->clk_ctrl_1_gpio == MXC_E_CLKMAN_CLK_SCALE_DISABLED) { + MXC_CLKMAN->clk_ctrl_1_gpio = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + } +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + pin_mode(obj->name, mode); +} + +void pin_dir(PinName name, PinDirection direction) +{ + MBED_ASSERT(name != (PinName)NC); + + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + + /* Set function */ + MXC_GPIO->func_sel[port] &= ~(0xF << (4 * pin)); + + /* Normal input is always enabled */ + MXC_GPIO->in_mode[port] &= ~(0xF << (4 * pin)); + + /* Set requested output mode */ + uint32_t out_mode = MXC_GPIO->out_mode[port]; + out_mode &= ~(0xF << (4 * pin)); + out_mode |= (direction << (4 * pin)); + MXC_GPIO->out_mode[port] = out_mode; +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + pin_dir(obj->name, direction); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_irq_api.c new file mode 100644 index 0000000000..4e153cd01a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_irq_api.c @@ -0,0 +1,168 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include "cmsis.h" +#include "gpio_irq_api.h" +#include "mbed_error.h" + +#define NUM_PORTS 3 +#define NUM_PINS_PER_PORT 8 + +static uint32_t ids[NUM_PORTS][NUM_PINS_PER_PORT] = {{0}}; +static gpio_irq_handler irq_handler; + +static void handle_irq(unsigned int port) +{ + uint32_t intfl, in_val; + uint32_t mask; + unsigned int pin; + + /* Read pin state */ + in_val = MXC_GPIO->in_val[port]; + + /* Read interrupts */ + intfl = MXC_GPIO->intfl[port] & MXC_GPIO->inten[port]; + + mask = 1; + + for (pin = 0; pin < NUM_PINS_PER_PORT; pin++) { + if (intfl & mask) { + if (ids[port][pin]) { + if (in_val & mask) { + irq_handler(ids[port][pin], IRQ_RISE); + } else { + irq_handler(ids[port][pin], IRQ_FALL); + } + } + MXC_GPIO->intfl[port] = mask; /* clear interrupt */ + } + mask <<= 1; + } +} + +void gpio_irq_0(void) +{ + handle_irq(0); +} + +void gpio_irq_1(void) +{ + handle_irq(1); +} + +void gpio_irq_2(void) +{ + handle_irq(2); +} + +int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id) +{ + if (name == NC) + return -1; + + uint8_t port = PINNAME_TO_PORT(name); + uint8_t pin = PINNAME_TO_PIN(name); + + if ((port > NUM_PORTS) || (pin > NUM_PINS_PER_PORT)) { + return 1; + } + + obj->port = port; + obj->pin = pin; + + irq_handler = handler; + + ids[port][pin] = id; + + /* register handlers */ + NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)gpio_irq_0); + NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)gpio_irq_1); + NVIC_SetVector(GPIO_P2_IRQn, (uint32_t)gpio_irq_2); + + /* disable the interrupt locally */ + MXC_GPIO->int_mode[port] &= ~(0xF << (pin*4)); + + /* clear a pending request */ + MXC_GPIO->intfl[port] = 1 << pin; + + /* enable the requested interrupt */ + MXC_GPIO->inten[port] |= (1 << pin); + NVIC_EnableIRQ(GPIO_P0_IRQn + port); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + /* disable interrupt */ + MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin); + MXC_GPIO->int_mode[obj->port] &= ~(0xF << (obj->pin*4)); + + ids[obj->port][obj->pin] = 0; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + uint32_t int_mode = MXC_GPIO->int_mode[obj->port]; + uint32_t curr_mode = (int_mode >> (obj->pin*4)) & 0x3; /* only supporting edge interrupts */ + + uint32_t new_mode = curr_mode; + if (event == IRQ_FALL) { + if (enable) { + new_mode |= 0x1; + } else { + new_mode &= ~0x1; + } + } else if (event == IRQ_RISE) { + if (enable) { + new_mode |= 0x2; + } else { + new_mode &= ~0x2; + } + } + + int_mode &= ~(0xF << (obj->pin*4)); + int_mode |= (new_mode << (obj->pin*4)); + MXC_GPIO->int_mode[obj->port] = int_mode; +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ + MXC_GPIO->inten[obj->port] |= (1 << obj->pin); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_object.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_object.h new file mode 100644 index 0000000000..0c064f9068 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_object.h @@ -0,0 +1,71 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName name; + __IO uint32_t *reg_out; + __I uint32_t *reg_in; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) +{ + MBED_ASSERT(obj->name != (PinName)NC); + *obj->reg_out = !!value; +} + +static inline int gpio_read(gpio_t *obj) +{ + MBED_ASSERT(obj->name != (PinName)NC); + return *obj->reg_in; +} + +void pin_dir(PinName name, PinDirection direction); + +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->name != (PinName)NC; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/i2c_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/i2c_api.c new file mode 100644 index 0000000000..cb986662db --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/i2c_api.c @@ -0,0 +1,405 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "i2c_api.h" +#include "cmsis.h" +#include "i2cm_regs.h" +#include "clkman_regs.h" +#include "ioman_regs.h" +#include "PeripheralPins.h" + +#define I2C_SLAVE_ADDR_READ_BIT 0x0001 + +#ifndef MXC_I2CM_TX_TIMEOUT +#define MXC_I2CM_TX_TIMEOUT 0x5000 +#endif + +#ifndef MXC_I2CM_RX_TIMEOUT +#define MXC_I2CM_RX_TIMEOUT 0x5000 +#endif + +typedef enum { + /** 100KHz */ + MXC_E_I2CM_SPEED_100KHZ = 0, + /** 400KHz */ + MXC_E_I2CM_SPEED_400KHZ, + /** 1MHz */ + MXC_E_I2CM_SPEED_1MHZ +} i2cm_speed_t; + +/* Clock divider lookup table */ +static const uint32_t clk_div_table[3][8] = { + /* MXC_E_I2CM_SPEED_100KHZ */ + { + /* 0: */ 0, /* not supported */ + /* 1: 6MHz */ (( 3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | ( 7 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 2: 8MHz */ (( 4 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (10 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 48 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 3: 12MHz */ (( 6 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (17 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 72 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 4: 16MHz */ (( 8 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 96 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 5: */ 0, /* not supported */ + /* 6: */ 0, /* not supported */ + /* 7: 24MHz */ ((12 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (38 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (144 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + }, + /* MXC_E_I2CM_SPEED_400KHZ */ + { + /* 0: */ 0, /* not supported */ + /* 1: */ 0, /* not supported */ + /* 2: */ 0, /* not supported */ + /* 3: 12MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (1 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (18 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 4: 16MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (2 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 5: */ 0, /* not supported */ + /* 6: */ 0, /* not supported */ + /* 7: 24MHz */ ((3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (5 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + }, + /* MXC_E_I2CM_SPEED_1MHZ */ + { + /* 0: */ 0, /* not supported */ + /* 1: */ 0, /* not supported */ + /* 2: */ 0, /* not supported */ + /* 3: */ 0, /* not supported */ + /* 4: */ 0, /* not supported */ + /* 5: */ 0, /* not supported */ + /* 6: */ 0, /* not supported */ + /* 7: 24MHz */ ((1 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (0 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (14 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + }, +}; + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + // determine the I2C to use + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + mxc_i2cm_regs_t *i2c = (mxc_i2cm_regs_t*)pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)i2c != NC); + + obj->i2c = i2c; + obj->txfifo = (uint16_t*)MXC_I2CM_GET_BASE_TX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c)); + obj->rxfifo = (uint16_t*)MXC_I2CM_GET_BASE_RX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c)); + obj->start_pending = 0; + obj->stop_pending = 0; + + // configure the pins + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + + // enable the clock + MXC_CLKMAN->clk_ctrl_6_i2cm = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // reset module + i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN; + i2c->ctrl = 0; + + // set default frequency at 100k + i2c_frequency(obj, 100000); + + // set timeout to 255 ms and turn on the auto-stop option + i2c->timeout = (0xFF << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS) | MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN; + + // enable tx_fifo and rx_fifo + i2c->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN); +} + +void i2c_frequency(i2c_t *obj, int hz) +{ + // compute clock array index + int clki = ((SystemCoreClock + 1500000) / 3000000) - 1; + + // get clock divider settings from lookup table + if ((hz < 400000) && (clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki] > 0)) { + obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki]; + } else if ((hz < 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki] > 0)) { + obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki]; + } else if ((hz >= 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki] > 0)) { + obj->i2c->hs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki]; + } +} + +static int write_tx_fifo(i2c_t *obj, const uint16_t data) +{ + int timeout = MXC_I2CM_TX_TIMEOUT; + + while (*obj->txfifo) { + uint32_t intfl = obj->i2c->intfl; + if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) { + return I2C_ERROR_NO_SLAVE; + } + if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) { + return I2C_ERROR_BUS_BUSY; + } + timeout--; + } + *obj->txfifo = data; + + return 0; +} + +static int wait_tx_in_progress(i2c_t *obj) +{ + int timeout = MXC_I2CM_TX_TIMEOUT; + + while ((obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS) && --timeout); + + uint32_t intfl = obj->i2c->intfl; + + if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) { + i2c_reset(obj); + return I2C_ERROR_NO_SLAVE; + } + + if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) { + i2c_reset(obj); + return I2C_ERROR_BUS_BUSY; + } + + return 0; +} + +int i2c_start(i2c_t *obj) +{ + obj->start_pending = 1; + return 0; +} + +int i2c_stop(i2c_t *obj) +{ + obj->start_pending = 0; + write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP); + + return wait_tx_in_progress(obj); +} + +void i2c_reset(i2c_t *obj) +{ + obj->i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN; + obj->i2c->intfl = 0x3FF; // clear all interrupts + obj->i2c->ctrl = MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN; + obj->start_pending = 0; +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + int err; + + // clear all interrupts + obj->i2c->intfl = 0x3FF; + + if (obj->start_pending) { + obj->start_pending = 0; + data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_START; + } else { + data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_TXDATA_ACK; + } + + if ((err = write_tx_fifo(obj, data)) != 0) { + return err; + } + + obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START; + + return 0; +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + uint16_t fifo_value; + int err; + + // clear all interrupts + obj->i2c->intfl = 0x3FF; + + if (last) { + fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_NACK; + } else { + fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT; + } + + if ((err = write_tx_fifo(obj, fifo_value)) != 0) { + return err; + } + + obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START; + + int timeout = MXC_I2CM_RX_TIMEOUT; + while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) && + (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) { + if ((--timeout < 0) || !(obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + break; + } + } + + if (obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) { + obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY; + return *obj->rxfifo; + } + + return -1; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + int err, retval = 0; + int i; + + if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + return 0; + } + + // clear all interrupts + obj->i2c->intfl = 0x3FF; + + // write the address to the fifo + if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address))) != 0) { // start + addr (write) + return err; + } + obj->start_pending = 0; + + // start the transaction + obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START; + + // load as much of the cmd into the FIFO as possible + for (i = 0; i < length; i++) { + if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | data[i]))) != 0) { // cmd (expect ACK) + retval = (retval ? retval : err); + break; + } + } + + if (stop) { + obj->stop_pending = 0; + if ((err = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition + retval = (retval ? retval : err); + } + + if ((err = wait_tx_in_progress(obj)) != 0) { + retval = (retval ? retval : err); + } + } else { + obj->stop_pending = 1; + int timeout = MXC_I2CM_TX_TIMEOUT; + // Wait for TX fifo to be empty + while(!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY) && timeout--) {} + } + + if (retval == 0) { + return length; + } + + return retval; +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + int err, retval = 0; + int i = length; + int timeout; + + if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + return 0; + } + + // clear all interrupts + obj->i2c->intfl = 0x3FF; + + // start + addr (read) + if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address | I2C_SLAVE_ADDR_READ_BIT))) != 0) { + goto read_done; + } + obj->start_pending = 0; + + while (i > 256) { + if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != 0) { + goto read_done; + } + i -= 256; + } + + if (i > 1) { + if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (i - 2)))) != 0) { + goto read_done; + } + } + + // start the transaction + obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START; + + if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK)) != 0) { // NACK last data byte + goto read_done; + } + + if (stop) { + if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition + goto read_done; + } + } + + timeout = MXC_I2CM_RX_TIMEOUT; + i = 0; + while (i < length) { + while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) && + (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) { + if ((--timeout < 0) || !(obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + retval = -3; + goto read_done; + } + } + + timeout = MXC_I2CM_RX_TIMEOUT; + + obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY; + + uint16_t temp = *obj->rxfifo; + + if (temp & MXC_S_I2CM_RSTLS_TAG_EMPTY) { + continue; + } + data[i++] = (uint8_t) temp; + } + +read_done: + + if (stop) { + obj->stop_pending = 0; + if ((err = wait_tx_in_progress(obj)) != 0) { + retval = (retval ? retval : err); + } + } else { + obj->stop_pending = 1; + } + + if (retval == 0) { + return length; + } + + return retval; +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/objects.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/objects.h new file mode 100644 index 0000000000..442ab5e248 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/objects.h @@ -0,0 +1,118 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "gpio_object.h" +#include "gpio_regs.h" +#include "uart_regs.h" +#include "i2cm_regs.h" +#include "spi_regs.h" +#include "pt_regs.h" +#include "adc_regs.h" +#include "dac_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct port_s { + PortName port; + uint32_t mask; + __IO uint32_t *reg_out; + __I uint32_t *reg_in; +}; + +struct gpio_irq_s { + uint8_t port; + uint8_t pin; +}; + +struct serial_s { + int index; + mxc_uart_regs_t *uart; +}; + +struct i2c_s { + int index; + mxc_i2cm_regs_t *i2c; + volatile uint16_t *txfifo; + volatile uint16_t *rxfifo; + int start_pending; + int stop_pending; +}; + +struct spi_s { + int index; + mxc_spi_regs_t *spi; + mxc_spi_rxfifo_regs_t *rxfifo; + mxc_spi_txfifo_regs_t *txfifo; +}; + +struct pwmout_s { + mxc_pt_regs_t *pwm; + int period; + int pulse_width; +}; + +struct analogin_s { + mxc_adc_regs_t *adc; + mxc_adccfg_regs_t *adccfg; + mxc_adc_fifo_regs_t * adc_fifo; + PinName adc_pin; +}; + +struct dac_s { + int index; + uint16_t out; + mxc_dac_regs_t *dac; + mxc_dac_fifo_t * dac_fifo; +}; + +typedef struct { + volatile uint32_t *reg_req; + volatile uint32_t *reg_ack; + uint32_t req_val; + uint32_t ack_mask; +} pin_function_t; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/pinmap.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/pinmap.c new file mode 100644 index 0000000000..099c77a307 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/pinmap.c @@ -0,0 +1,105 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "pinmap.h" +#include "objects.h" +#include "gpio_regs.h" +#include "ioman_regs.h" + +void pin_function(PinName name, int function) +{ + MBED_ASSERT(name != (PinName)NC); + + if ((function >= 0) && (function <= 0xF)) { + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + uint32_t temp = MXC_GPIO->func_sel[port] & ~(0xF << (pin*4)); + MXC_GPIO->func_sel[port] = temp | ((uint32_t)function << (pin*4)); + } else { + /* Assume this is a pointer to a pin function object */ + pin_function_t *obj = (pin_function_t*)function; + + if ((*obj->reg_ack & obj->ack_mask) != obj->req_val) { + /* Request pin mapping */ + *obj->reg_req |= obj->req_val; + + /* Check for acknowledgment */ + MBED_ASSERT((*obj->reg_ack & obj->ack_mask) == obj->req_val); + } + } +} + +void pin_mode(PinName name, PinMode mode) +{ + MBED_ASSERT(name != (PinName)NC); + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + + /* Must set mode while retaining direction */ + + /* Get the current direction */ + uint32_t out_mode = MXC_GPIO->out_mode[port]; + uint32_t curr_mode = (out_mode >> (pin*4)) & 0xF; + PinDirection dir = PIN_OUTPUT; + if ((curr_mode == MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP) || (curr_mode == MXC_V_GPIO_OUT_MODE_HIGH_Z)) { + dir = PIN_INPUT; + } + + /* Set mode based on current direction */ + uint32_t new_mode; + if (dir == PIN_OUTPUT) { + // PullUp = not valid, + // OpenDrain = MXC_V_GPIO_OUT_MODE_OD, + // PullNone = MXC_V_GPIO_OUT_MODE_NORMAL, + if (mode == OpenDrain) { + new_mode = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN; + } else { + new_mode = MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE; + } + } else { + // PullUp = MXC_V_GPIO_OUT_MODE_HIZPU, + // OpenDrain = not valid, + // PullNone = MXC_V_GPIO_OUT_MODE_HIZ, + if (mode == PullUp) { + new_mode = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP; + } else { + new_mode = MXC_V_GPIO_OUT_MODE_HIGH_Z; + } + } + + /* Set new mode */ + out_mode &= ~(0xF << (pin*4)); + out_mode |= (new_mode << (pin*4)); + MXC_GPIO->out_mode[port] = out_mode; +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/port_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/port_api.c new file mode 100644 index 0000000000..f8b7e0884c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/port_api.c @@ -0,0 +1,97 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "port_api.h" +#include "pinmap.h" +#include "gpio_api.h" +#include "gpio_regs.h" +#include "clkman_regs.h" + +PinName port_pin(PortName port, int pin_n) +{ + return (PinName)((port << PORT_SHIFT) | pin_n); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + obj->port = port; + obj->mask = mask; + obj->reg_out = &MXC_GPIO->out_val[port]; + obj->reg_in = &MXC_GPIO->in_val[port]; + + /* Ensure that the GPIO clock is enabled */ + if (MXC_CLKMAN->clk_ctrl_1_gpio == MXC_E_CLKMAN_CLK_SCALE_DISABLED) { + MXC_CLKMAN->clk_ctrl_1_gpio = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + } + + uint32_t i; + // The function is set per pin: reuse gpio logic + for (i=0; i<32; i++) { + if (obj->mask & (1<port, i)); + pin_dir(port_pin(obj->port, i), dir); + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint32_t i; + // The mode is set per pin: reuse pinmap logic + for (i=0; i<32; i++) { + if (obj->mask & (1<port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) +{ + uint32_t i; + // The mode is set per pin: reuse gpio logic + for (i=0; i<32; i++) { + if (obj->mask & (1<port, i), dir); + } + } +} + +void port_write(port_t *obj, int value) +{ + *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); +} + +int port_read(port_t *obj) +{ + return (*obj->reg_in & obj->mask); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/pwmout_api.c new file mode 100644 index 0000000000..1a412248de --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/pwmout_api.c @@ -0,0 +1,234 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "cmsis.h" +#include "pwmout_api.h" +#include "pinmap.h" +#include "ioman_regs.h" +#include "clkman_regs.h" +#include "PeripheralPins.h" + +//****************************************************************************** +void pwmout_init(pwmout_t* obj, PinName pin) +{ + // Make sure the pin is free for GPIO use + unsigned int port = (unsigned int)pin >> PORT_SHIFT; + unsigned int port_pin = (unsigned int)pin & ~(0xFFFFFFFF << PORT_SHIFT); + MBED_ASSERT(MXC_GPIO->free[port] & (0x1 << port_pin)); + + int i = 0; + PinMap pwm = PinMap_PWM[0]; + + // Check if there is a pulse train already active on this port + int pin_func = (MXC_GPIO->func_sel[port] & (0xF << (port_pin*4))) >> (port_pin*4); + if((pin_func > 0) && (pin_func < 4)) { + // Search through PinMap_PWM to find the active PT + while(pwm.pin != (PinName)NC) { + if((pwm.pin == pin) && (pwm.function == pin_func)) { + break; + } + pwm = PinMap_PWM[++i]; + } + + } else { + // Search through PinMap_PWM to find an available PT + int i = 0; + while(pwm.pin != (PinName)NC && (i > -1)) { + pwm = PinMap_PWM[i++]; + if(pwm.pin == pin) { + // Check each instance of PT + while(1) { + // Check to see if this PT instance is already in use + if((((mxc_pt_regs_t*)pwm.peripheral)->rate_length & + MXC_F_PT_RATE_LENGTH_MODE)) { + i = -1; + break; + } + + // If all instances are in use, overwrite the last + pwm = PinMap_PWM[++i]; + if(pwm.pin != pin) { + pwm = PinMap_PWM[--i]; + i = -1; + break; + } + + } + } + } + } + + // Make sure we found an available PWM generator + MBED_ASSERT(pwm.pin != (PinName)NC); + + // Disable all pwm output + MXC_PTG->ctrl = 0; + + // Enable the clock + MXC_CLKMAN->clk_ctrl_2_pt = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Set the drive mode to normal + MXC_SET_FIELD(&MXC_GPIO->out_mode[port], (0x7 << (port_pin*4)), (MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << (port_pin*4))); + + // Set the obj pointer to the propper PWM instance + obj->pwm = (mxc_pt_regs_t*)pwm.peripheral; + + // Initialize object period and pulse width + obj->period = -1; + obj->pulse_width = -1; + + // Disable the output + obj->pwm->train = 0x0; + obj->pwm->rate_length = 0x0; + + // Configure the pin + pin_mode(pin, (PinMode)PullNone); + pin_function(pin, pwm.function); + + // default to 20ms: standard for servos, and fine for e.g. brightness control + pwmout_period_us(obj, 20000); + pwmout_write (obj, 0); + + // Enable the global pwm + MXC_PTG->ctrl = MXC_F_PT_CTRL_ENABLE_ALL; +} + +//****************************************************************************** +void pwmout_free(pwmout_t* obj) +{ + // Set the registers to the reset value + obj->pwm->train = 0; + obj->pwm->rate_length = 0x08000000; +} + +//****************************************************************************** +static void pwmout_update(pwmout_t* obj) +{ + // Calculate and set the divider ratio + int div = (obj->period * (SystemCoreClock/1000000))/32; + if (div < 2){ + div = 2; + } + MXC_SET_FIELD(&obj->pwm->rate_length, MXC_F_PT_RATE_LENGTH_RATE_CONTROL, div); + + // Change the duty cycle to adjust the pulse width + obj->pwm->train = (0xFFFFFFFF << (32-((32*obj->pulse_width)/obj->period))); +} + + +//****************************************************************************** +void pwmout_write(pwmout_t* obj, float percent) +{ + // Saturate percent if outside of range + if(percent < 0.0) { + percent = 0.0; + } else if(percent > 1.0) { + percent = 1.0; + } + + // Resize the pulse width to set the duty cycle + pwmout_pulsewidth_us(obj, (int)(percent*obj->period)); +} + +//****************************************************************************** +float pwmout_read(pwmout_t* obj) +{ + // Check for when pulsewidth or period equals 0 + if((obj->pulse_width == 0) || (obj->period == 0)){ + return 0; + } + + // Return the duty cycle + return ((float)obj->pulse_width / (float)obj->period); +} + +//****************************************************************************** +void pwmout_period(pwmout_t* obj, float seconds) +{ + pwmout_period_us(obj, (int)(seconds * 1000000.0)); +} + +//****************************************************************************** +void pwmout_period_ms(pwmout_t* obj, int ms) +{ + pwmout_period_us(obj, ms*1000); +} + +//****************************************************************************** +void pwmout_period_us(pwmout_t* obj, int us) +{ + // Check the range of the period + MBED_ASSERT((us >= 0) && (us <= (int)(SystemCoreClock/32))); + + // Set pulse width to half the period if uninitialized + if(obj->pulse_width == -1){ + obj->pulse_width = us/2; + } + + // Save the period + obj->period = us; + + // Update the registers + pwmout_update(obj); +} + +//****************************************************************************** +void pwmout_pulsewidth(pwmout_t* obj, float seconds) +{ + pwmout_pulsewidth_us(obj, (int)(seconds * 1000000.0)); +} + +//****************************************************************************** +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) +{ + pwmout_pulsewidth_us(obj, ms*1000); +} + +//****************************************************************************** +void pwmout_pulsewidth_us(pwmout_t* obj, int us) +{ + // Check the range of the pulsewidth + MBED_ASSERT((us >= 0) && (us <= (int)(SystemCoreClock/32))); + + // Initialize period to double the pulsewidth if uninitialized + if(obj->period == -1){ + obj->period = 2*us; + } + + // Save the pulsewidth + obj->pulse_width = us; + + // Update the register + pwmout_update(obj); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/rtc_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/rtc_api.c new file mode 100644 index 0000000000..033420d4ad --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/rtc_api.c @@ -0,0 +1,190 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "rtc_api.h" +#include "cmsis.h" +#include "rtc_regs.h" +#include "pwrseq_regs.h" +#include "clkman_regs.h" + +static int rtc_inited = 0; +static volatile uint32_t overflow_cnt = 0; +static uint32_t overflow_alarm = 0; + +//****************************************************************************** +static void overflow_handler(void) +{ + MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS; + overflow_cnt++; + + if (overflow_cnt == overflow_alarm) { + // Enable the comparator interrupt for the alarm + MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0; + } +} + +//****************************************************************************** +static void alarm_handler(void) +{ + MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0; + MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS; +} + +//****************************************************************************** +void rtc_init(void) +{ + if(rtc_inited) { + return; + } + rtc_inited = 1; + + // Enable the clock to the synchronizer + MXC_CLKMAN->clk_ctrl_13_rtc_int_sync = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Enable the clock to the RTC + MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN; + + // Set the divider from the 4kHz clock + MXC_RTCTMR->prescale = MXC_E_RTC_PRESCALE_DIV_2_0; + + // Enable the overflow interrupt + MXC_RTCTMR->inten |= MXC_F_RTC_FLAGS_OVERFLOW; + + // Prepare interrupt handlers + NVIC_SetVector(RTC0_IRQn, (uint32_t)alarm_handler); + NVIC_EnableIRQ(RTC0_IRQn); + NVIC_SetVector(RTC3_IRQn, (uint32_t)overflow_handler); + NVIC_EnableIRQ(RTC3_IRQn); + + // Enable the RTC + MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE; +} + +//****************************************************************************** +void rtc_free(void) +{ + if (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE) { + // Clear and disable RTC + MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR; + MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; + + // Wait for pending transactions + while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); + } + + // Disable the clock to the RTC + MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP); + + // Disable the clock to the synchronizer + MXC_CLKMAN->clk_ctrl_13_rtc_int_sync = MXC_E_CLKMAN_CLK_SCALE_DISABLED; +} + +//****************************************************************************** +int rtc_isenabled(void) +{ + return (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE); +} + +//****************************************************************************** +time_t rtc_read(void) +{ + unsigned int shift_amt; + uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt; + + // Account for a change in the default prescaler + shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale; + + // Ensure coherency between overflow_cnt and timer + do { + ovf_cnt_1 = overflow_cnt; + timer_cnt = MXC_RTCTMR->timer; + ovf_cnt_2 = overflow_cnt; + } while (ovf_cnt_1 != ovf_cnt_2); + + return (timer_cnt >> shift_amt) + (ovf_cnt_1 << (32 - shift_amt)); +} + +//****************************************************************************** +uint64_t rtc_read_us(void) +{ + unsigned int shift_amt; + uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt; + uint64_t currentUs; + + // Account for a change in the default prescaler + shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale; + + // Ensure coherency between overflow_cnt and timer + do { + ovf_cnt_1 = overflow_cnt; + timer_cnt = MXC_RTCTMR->timer; + ovf_cnt_2 = overflow_cnt; + } while (ovf_cnt_1 != ovf_cnt_2); + + currentUs = (((uint64_t)timer_cnt * 1000000) >> shift_amt) + (((uint64_t)ovf_cnt_1 * 1000000) << (32 - shift_amt)); + + return currentUs; +} + +//****************************************************************************** +void rtc_write(time_t t) +{ + // Account for a change in the default prescaler + unsigned int shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale; + + MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; // disable the timer while updating + MXC_RTCTMR->timer = t << shift_amt; + overflow_cnt = t >> (32 - shift_amt); + MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE; // enable the timer while updating +} + +//****************************************************************************** +void rtc_set_wakeup(uint64_t wakeupUs) +{ + // Account for a change in the default prescaler + unsigned int shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale; + + // Disable the alarm while it is prepared + MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0; + MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_COMP0; // clear interrupt + + overflow_alarm = (wakeupUs >> (32 - shift_amt)) / 1000000; + + if (overflow_alarm == overflow_cnt) { + MXC_RTCTMR->comp[0] = (wakeupUs << shift_amt) / 1000000; + MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0; + } + + // Enable wakeup from RTC + MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER | MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/serial_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/serial_api.c new file mode 100644 index 0000000000..34fc49ce8a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/serial_api.c @@ -0,0 +1,355 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include "mbed_assert.h" +#include "cmsis.h" +#include "serial_api.h" +#include "uart_regs.h" +#include "PeripheralPins.h" + +#define UART_NUM 2 +#define DEFAULT_BAUD 9600 +#define DEFAULT_STOP 1 +#define DEFAULT_PARITY ParityNone + +#define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAME_ERROR | \ + MXC_F_UART_INTFL_RX_PARITY_ERROR | \ + MXC_F_UART_INTFL_RX_OVERRUN) + +// Variables for managing the stdio UART +int stdio_uart_inited; +serial_t stdio_uart; + +// Variables for interrupt driven +static uart_irq_handler irq_handler; +static uint32_t serial_irq_ids[UART_NUM]; + +//****************************************************************************** +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + // Determine which uart is associated with each pin + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + + // Make sure that both pins are pointing to the same uart + MBED_ASSERT(uart != (UARTName)NC); + + // Set the obj pointer to the proper uart + obj->uart = (mxc_uart_regs_t*)uart; + + // Set the uart index + obj->index = MXC_UART_BASE_TO_INSTANCE(obj->uart); + + // Configure the pins + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + // Flush the RX and TX FIFOs, clear the settings + obj->uart->ctrl = ( MXC_F_UART_CTRL_TX_FIFO_FLUSH | MXC_F_UART_CTRL_RX_FIFO_FLUSH); + + // Disable interrupts + obj->uart->inten = 0; + obj->uart->intfl = 0; + + // Configure to default settings + serial_baud(obj, DEFAULT_BAUD); + serial_format(obj, 8, ParityNone, 1); + + // Manage stdio UART + if(uart == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +//****************************************************************************** +void serial_baud(serial_t *obj, int baudrate) +{ + uint32_t idiv = 0, ddiv = 0, div = 0; + + // Calculate the integer and decimal portions + div = SystemCoreClock / ((baudrate / 100) * 128); + idiv = (div / 100); + ddiv = (div - idiv * 100) * 128 / 100; + + obj->uart->baud_int = idiv; + obj->uart->baud_div_128 = ddiv; + + // Enable the baud clock + obj->uart->ctrl |= MXC_F_UART_CTRL_BAUD_CLK_EN; +} + +//****************************************************************************** +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + + // Check the validity of the inputs + MBED_ASSERT((data_bits > 4) && (data_bits < 9)); + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || + (parity == ParityEven) || (parity == ParityForced1) || + (parity == ParityForced0)); + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); + + // Adjust the stop and data bits + stop_bits -= 1; + data_bits -= 5; + + // Adjust the parity setting + int paren = 0, mode = 0; + switch (parity) { + case ParityNone: + paren = 0; + mode = 0; + break; + case ParityOdd : + paren = 1; + mode = 0; + break; + case ParityEven: + paren = 1; + mode = 1; + break; + case ParityForced1: + // Hardware does not support forced parity + MBED_ASSERT(0); + break; + case ParityForced0: + // Hardware does not support forced parity + MBED_ASSERT(0); + break; + default: + paren = 1; + mode = 0; + break; + } + + obj->uart->ctrl |= ((data_bits << MXC_F_UART_CTRL_CHAR_LENGTH_POS) | + (stop_bits << MXC_F_UART_CTRL_STOP_BIT_MODE_POS) | + (paren << MXC_F_UART_CTRL_PARITY_ENABLE_POS) | + (mode << MXC_F_UART_CTRL_PARITY_MODE_POS)); +} + +//****************************************************************************** +void uart_handler(mxc_uart_regs_t* uart, int id) +{ + // Check for errors or RX Threshold + if(uart->intfl & (MXC_F_UART_INTFL_RX_OVER_THRESHOLD | UART_ERRORS)) { + irq_handler(serial_irq_ids[id], RxIrq); + uart->intfl &= ~(MXC_F_UART_INTFL_RX_OVER_THRESHOLD | UART_ERRORS); + } + + // Check for TX Threshold + if(uart->intfl & MXC_F_UART_INTFL_TX_ALMOST_EMPTY) { + irq_handler(serial_irq_ids[id], TxIrq); + uart->intfl &= ~(MXC_F_UART_INTFL_TX_ALMOST_EMPTY); + } +} + +void uart0_handler(void) +{ + uart_handler(MXC_UART0, 0); +} +void uart1_handler(void) +{ + uart_handler(MXC_UART1, 1); +} + +//****************************************************************************** +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +//****************************************************************************** +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + if(obj->index == 0) { + NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler); + NVIC_EnableIRQ(UART0_IRQn); + } else { + NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler); + NVIC_EnableIRQ(UART1_IRQn); + } + + if(irq == RxIrq) { + // Set the RX FIFO Threshold to 1 + obj->uart->ctrl &= ~MXC_F_UART_CTRL_RX_THRESHOLD; + obj->uart->ctrl |= 0x1; + // Enable RX FIFO Threshold Interrupt + if(enable) { + // Clear pending interrupts + obj->uart->intfl = 0; + obj->uart->inten |= (MXC_F_UART_INTFL_RX_OVER_THRESHOLD | + UART_ERRORS); + } else { + // Clear pending interrupts + obj->uart->intfl = 0; + obj->uart->inten &= ~(MXC_F_UART_INTFL_RX_OVER_THRESHOLD | + UART_ERRORS); + } + + } else if (irq == TxIrq) { + // Enable TX Almost empty Interrupt + if(enable) { + // Clear pending interrupts + obj->uart->intfl = 0; + obj->uart->inten |= MXC_F_UART_INTFL_TX_ALMOST_EMPTY; + } else { + // Clear pending interrupts + obj->uart->intfl = 0; + obj->uart->inten &= ~MXC_F_UART_INTFL_TX_ALMOST_EMPTY; + } + + } else { + MBED_ASSERT(0); + } +} + + +//****************************************************************************** +int serial_getc(serial_t *obj) +{ + int c; + + // Wait for data to be available + while(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY) {} + c = obj->uart->tx_rx_fifo & 0xFF; + + // Echo characters for stdio + if (obj->uart == (mxc_uart_regs_t*)STDIO_UART) { + obj->uart->tx_rx_fifo = c; + } + + return c; +} + +//****************************************************************************** +void serial_putc(serial_t *obj, int c) +{ + // Append a carriage return for stdio + if ((c == (int)'\n') && (obj->uart == (mxc_uart_regs_t*)STDIO_UART)) { + while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {} + obj->uart->tx_rx_fifo = '\r'; + } + + // Wait for TXFIFO to not be full + while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {} + obj->uart->tx_rx_fifo = c; + +} + +//****************************************************************************** +int serial_readable(serial_t *obj) +{ + return (!(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY)); +} + +//****************************************************************************** +int serial_writable(serial_t *obj) +{ + return (!(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL)); +} + +//****************************************************************************** +void serial_clear(serial_t *obj) +{ + // Clear the rx and tx fifos + obj->uart->ctrl |= (MXC_F_UART_CTRL_TX_FIFO_FLUSH | MXC_F_UART_CTRL_RX_FIFO_FLUSH ); +} + + +//****************************************************************************** +void serial_break_set(serial_t *obj) +{ + // Make sure that nothing is being sent + while(obj->uart->status & MXC_F_UART_STATUS_RX_BUSY) {} + + // Disable the clock to pause any transmission + obj->uart->ctrl &= ~MXC_F_UART_CTRL_BAUD_CLK_EN ; +} + +//****************************************************************************** +void serial_break_clear(serial_t *obj) +{ + obj->uart->ctrl |= MXC_F_UART_CTRL_BAUD_CLK_EN; +} + + +//****************************************************************************** +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + + +//****************************************************************************** +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + if(FlowControlNone == type) { + // Disable hardware flow control + obj->uart->ctrl &= ~(MXC_F_UART_CTRL_HW_FLOW_CTRL_EN); + return; + } + + // Check to see if we can use HW flow control + UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); + UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS); + UARTName uart = (UARTName)pinmap_merge(uart_cts, uart_rts); + + if((FlowControlCTS == type) || (FlowControlRTSCTS== type)) { + // Make sure pin is in the PinMap + MBED_ASSERT(uart_cts != (UARTName)NC); + + // Enable the pin for CTS function + pinmap_pinout(txflow, PinMap_UART_CTS); + } + + if((FlowControlRTS == type) || (FlowControlRTSCTS== type)) { + // Make sure pin is in the PinMap + MBED_ASSERT(uart_rts != (UARTName)NC); + + // Enable the pin for RTS function + pinmap_pinout(rxflow, PinMap_UART_RTS); + } + + if(FlowControlRTSCTS == type){ + // Make sure that the pins are pointing to the same UART + MBED_ASSERT(uart != (UARTName)NC); + } + + // Enable hardware flow control + obj->uart->ctrl |= MXC_F_UART_CTRL_HW_FLOW_CTRL_EN; +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/sleep.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/sleep.c new file mode 100644 index 0000000000..3eb9154f03 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/sleep.c @@ -0,0 +1,169 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "sleep_api.h" +#include "us_ticker_api.h" +#include "cmsis.h" +#include "pwrman_regs.h" +#include "pwrseq_regs.h" +#include "ioman_regs.h" +#include "rtc_regs.h" + +#define MIN_DEEP_SLEEP_US 500 + +uint64_t rtc_read_us(void); +void rtc_set_wakeup(uint64_t wakeupUs); +void us_ticker_deinit(void); +void us_ticker_set(timestamp_t timestamp); + +static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART; + +// Normal wait mode +void sleep(void) +{ + // Normal sleep mode for ARM core + SCB->SCR = 0; + + __DSB(); + __WFI(); +} + +// Work-around for issue of clearing power sequencer I/O flag +static void clearAllGPIOWUD(void) +{ + uint32_t wud_req0 = MXC_IOMAN->wud_req0; + uint32_t wud_req1 = MXC_IOMAN->wud_req1; + + // I/O must be a wakeup detect to clear + MXC_IOMAN->wud_req0 = 0xffffffff; + MXC_IOMAN->wud_req1 = 0xffffffff; + + // Clear all WUDs + MXC_PWRMAN->wud_ctrl = (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS) | MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL; + MXC_PWRMAN->wud_pulse0 = 1; + + // Restore WUD requests + MXC_IOMAN->wud_req0 = wud_req0; + MXC_IOMAN->wud_req1 = wud_req1; +} + +// Low-power stop mode +void deepsleep(void) +{ + uint64_t sleepStartRtcUs; + uint32_t sleepStartTickerUs; + int32_t sleepDurationUs; + uint64_t sleepEndRtcUs; + uint64_t elapsedUs; + + __disable_irq(); + + // Wait for all STDIO characters to be sent. The UART clock will stop. + while (stdio_uart->status & MXC_F_UART_STATUS_TX_BUSY); + + // Record the current times + sleepStartRtcUs = rtc_read_us(); + sleepStartTickerUs = us_ticker_read(); + + // Get the next mbed timer expiration + timestamp_t next_event = 0; + us_ticker_get_next_timestamp(&next_event); + sleepDurationUs = next_event - sleepStartTickerUs; + + if (sleepDurationUs < MIN_DEEP_SLEEP_US) { + /* The next wakeup is too soon. */ + __enable_irq(); + return; + } + + // Disable the us_ticker. It won't be clocked in DeepSleep + us_ticker_deinit(); + + // Prepare to wakeup from the RTC + rtc_set_wakeup(sleepStartRtcUs + sleepDurationUs); + + // Prepare for LP1 + uint32_t reg0 = MXC_PWRSEQ->reg0; + reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP; // disable VDD3 SVM during sleep mode + reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP; // disable VREG18 SVM during sleep mode + if (reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN) { // if real-time clock enabled during run + reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // enable real-time clock during sleep mode + } else { + reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // disable real-time clock during sleep mode + } + reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP; // enable CHZY regulator during sleep mode + reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1; // go into LP1 + reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT; // clear first boot flag + MXC_PWRSEQ->reg0 = reg0; + + MXC_PWRSEQ->reg3 = (MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK) | (3 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS); + + // Deep sleep for ARM core + SCB->SCR = SCB_SCR_SLEEPDEEP_Msk; + + // clear latches for wakeup detect + MXC_PWRSEQ->flags = MXC_PWRSEQ->flags; + if (MXC_PWRSEQ->flags & MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP) { + // attempt work-around for I/O flag clearing issue + clearAllGPIOWUD(); + MXC_PWRSEQ->flags = MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP; + } + + // Wait for pending RTC transaction + while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); + + // Ensure that the event register is clear + __SEV(); // set event + __WFE(); // clear event + + // Enter LP1 + __WFE(); + // Woke up from LP1 + + // The RTC timer does not update until the next tick + uint64_t tempUs = rtc_read_us(); + do { + sleepEndRtcUs = rtc_read_us(); + } while(sleepEndRtcUs == tempUs); + + // Get the elapsed time from the RTC. Wakeup could have been from some other event. + elapsedUs = sleepEndRtcUs - sleepStartRtcUs; + + // Update the us_ticker. It was not clocked during DeepSleep + us_ticker_init(); + us_ticker_set(sleepStartTickerUs + elapsedUs); + us_ticker_get_next_timestamp(&next_event); + us_ticker_set_interrupt(next_event); + + __enable_irq(); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/spi_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/spi_api.c new file mode 100644 index 0000000000..85e39db333 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/spi_api.c @@ -0,0 +1,190 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include "mbed_assert.h" +#include "cmsis.h" +#include "spi_api.h" +#include "pinmap.h" +#include "ioman_regs.h" +#include "clkman_regs.h" +#include "PeripheralPins.h" + +#define DEFAULT_CHAR 8 +#define DEFAULT_MODE 0 +#define DEFAULT_FREQ 1000000 + +// Formatting settings +static int spi_bits; + +//****************************************************************************** +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + // Make sure pins are pointing to the same SPI instance + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl; + + // Give the application the option to manually control Slave Select + if((SPIName)spi_ssel != (SPIName)NC) { + spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + } else { + spi_cntl = spi_sclk; + } + + SPIName spi = (SPIName)pinmap_merge(spi_data, spi_cntl); + + MBED_ASSERT((SPIName)spi != (SPIName)NC); + + // Set the obj pointer to the proper SPI Instance + obj->spi = (mxc_spi_regs_t*)spi; + + // Set the SPI index and FIFOs + obj->index = MXC_SPI_BASE_TO_INSTANCE(obj->spi); + obj->rxfifo = MXC_SPI_GET_RXFIFO(obj->index); + obj->txfifo = MXC_SPI_GET_TXFIFO(obj->index); + + // Configure the pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + pinmap_pinout(ssel, PinMap_SPI_SSEL); + + // Enable SPI and FIFOs + obj->spi->gen_ctrl = (MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN | + MXC_F_SPI_GEN_CTRL_TX_FIFO_EN | + MXC_F_SPI_GEN_CTRL_RX_FIFO_EN ); + + // Give instance the default settings + spi_format(obj, DEFAULT_CHAR, DEFAULT_MODE, 0); + spi_frequency(obj, DEFAULT_FREQ); +} + +//****************************************************************************** +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + // Check the validity of the inputs + MBED_ASSERT(((bits >= 1) && (bits <= 32)) && ((mode >= 0) && (mode <= 3))); + + // Only supports master mode + MBED_ASSERT(!slave); + + // Save formatting data + spi_bits = bits; + + // Set the mode + obj->spi->mstr_cfg &= ~(MXC_F_SPI_MSTR_CFG_SPI_MODE); + obj->spi->mstr_cfg |= (mode << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS); +} + +//****************************************************************************** +void spi_frequency(spi_t *obj, int hz) +{ + // Maximum frequency is half the system frequency + MBED_ASSERT((unsigned int)hz < (SystemCoreClock / 2)); + unsigned clocks = ((SystemCoreClock/2)/(hz)); + + // Figure out the divider ratio + int clk_div = 1; + while(clk_div < 10) { + if(clocks < 0x10) { + break; + } + clk_div++; + clocks = clocks >> 1; + } + + // Turn on the SPI clock + if(obj->index == 0) { + MXC_CLKMAN->clk_ctrl_3_spi0 = clk_div; + } else if(obj->index == 1) { + MXC_CLKMAN->clk_ctrl_4_spi1 = clk_div; + } else if(obj->index == 2) { + MXC_CLKMAN->clk_ctrl_5_spi2 = clk_div; + } else { + MBED_ASSERT(0); + } + + // Set the number of clocks to hold sclk high and low + MXC_SET_FIELD(&obj->spi->mstr_cfg, (MXC_F_SPI_MSTR_CFG_SCK_HI_CLK | MXC_F_SPI_MSTR_CFG_SCK_LO_CLK), + ((clocks << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS) | (clocks << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS))); +} + +//****************************************************************************** +int spi_master_write(spi_t *obj, int value) +{ + int bits = spi_bits; + if(spi_bits == 32) { + bits = 0; + } + // Create the header + uint16_t header = ((0x3 << MXC_F_SPI_FIFO_DIR_POS ) | // TX and RX + (0x0 << MXC_F_SPI_FIFO_UNIT_POS) | // Send bits + (bits << MXC_F_SPI_FIFO_SIZE_POS) | // Number of units + (0x1 << MXC_F_SPI_FIFO_DASS_POS)); // Deassert SS + + // Send the message header + obj->txfifo->txfifo_16 = header; + + // Send the data + if(spi_bits < 17) { + obj->txfifo->txfifo_16 = (uint16_t)value; + } else { + obj->txfifo->txfifo_32 = (uint32_t)value; + } + + // Get the data + bits = spi_bits; + int result = 0; + int i = 0; + while(bits > 0) { + // Wait for data + while(((obj->spi->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED) + >> MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS) < 1) {} + + result |= (obj->rxfifo->rxfifo_8 << (i++*8)); + bits-=8; + } + + return result; +} + +//****************************************************************************** +int spi_busy(spi_t *obj) +{ + return !(obj->spi->intfl & MXC_F_SPI_INTFL_TX_READY); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/us_ticker.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/us_ticker.c new file mode 100644 index 0000000000..b129ae5b69 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/us_ticker.c @@ -0,0 +1,261 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_error.h" +#include "us_ticker_api.h" +#include "PeripheralNames.h" +#include "tmr_regs.h" + +#define US_TIMER MXC_TMR0 +#define US_TIMER_IRQn TMR0_IRQn + +static int us_ticker_inited = 0; +static uint32_t ticks_per_us; +static uint32_t tick_win; +static volatile uint64_t current_cnt; // Hold the current ticks +static volatile uint64_t event_cnt; // Holds the value of the next event + +#define ticks_to_us(ticks) ((ticks) / ticks_per_us); +#define MAX_TICK_VAL ((uint64_t)0xFFFFFFFF * ticks_per_us) + +//****************************************************************************** +static inline void inc_current_cnt(uint32_t inc) { + + // Overflow the ticker when the us ticker overflows + current_cnt += inc; + if(current_cnt > MAX_TICK_VAL) { + current_cnt -= (MAX_TICK_VAL + 1); + } +} + +//****************************************************************************** +static inline int event_passed(uint64_t current, uint64_t event) { + + // Determine if the event has already happened. + // If the event is behind the current ticker, within a window, + // then the event has already happened. + if(((current < tick_win) && ((event < current) || + (event > (MAX_TICK_VAL - (tick_win - current))))) || + ((event < current) && (event > (current - tick_win)))) { + return 1; + } + + return 0; +} + +//****************************************************************************** +static inline uint64_t event_diff(uint64_t current, uint64_t event) { + + // Check to see if the ticker will overflow before the event + if(current <= event) { + return (event - current); + } + + return ((MAX_TICK_VAL - current) + event); +} + +//****************************************************************************** +static void tmr_handler(void) +{ + uint32_t term_cnt32 = US_TIMER->term_cnt32; + US_TIMER->term_cnt32 = 0xFFFFFFFF; // reset to max value to prevent further interrupts + US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupt + NVIC_ClearPendingIRQ(US_TIMER_IRQn); + + inc_current_cnt(term_cnt32); + + if (event_passed(current_cnt + US_TIMER->count32, event_cnt )) { + // the timestamp has expired + event_cnt = -1; // reset to max value + us_ticker_irq_handler(); + } else { + + uint64_t diff = event_diff(current_cnt, event_cnt); + if (diff < (uint64_t)0xFFFFFFFF) { + // the event occurs before the next overflow + US_TIMER->term_cnt32 = diff; + + // Since the timer keeps counting after the terminal value is reached, it is possible that the new + // terminal value is in the past. + if (US_TIMER->term_cnt32 < US_TIMER->count32) { + // the timestamp has expired + US_TIMER->term_cnt32 = 0xFFFFFFFF; // reset to max value to prevent further interrupts + US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupt + NVIC_ClearPendingIRQ(US_TIMER_IRQn); + event_cnt = -1; // reset to max value + us_ticker_irq_handler(); + } + } + } +} + +//****************************************************************************** +void us_ticker_init(void) +{ + if (us_ticker_inited) + return; + us_ticker_inited = 1; + + current_cnt = 0; + event_cnt = -1; // initialize to max value + + if (SystemCoreClock <= 1000000) { + error("us_ticker cannot operate at this SystemCoreClock"); + return; + } + + // Configure timer for 32-bit continuous mode with /1 prescaler + US_TIMER->ctrl = MXC_E_TMR_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS | (0 << MXC_F_TMR_CTRL_PRESCALE_POS); + ticks_per_us = SystemCoreClock / 1000000; + + // Set the tick window to 10ms + tick_win = SystemCoreClock/100; + + // Set timer overflow to the max + US_TIMER->term_cnt32 = 0xFFFFFFFF; + US_TIMER->pwm_cap32 = 0xFFFFFFFF; + US_TIMER->count32 = 0; + + US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear pending interrupts + + NVIC_SetVector(US_TIMER_IRQn, (uint32_t)tmr_handler); + NVIC_EnableIRQ(US_TIMER_IRQn); + + US_TIMER->inten |= MXC_F_TMR_INTEN_TIMER0; // enable interrupts + US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer +} + +//****************************************************************************** +void us_ticker_deinit(void) +{ + US_TIMER->ctrl = 0; // disable timer + US_TIMER->inten = 0; // disable interrupts + US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupts + us_ticker_inited = 0; +} + +//****************************************************************************** +uint32_t us_ticker_read(void) +{ + uint64_t current_cnt1, current_cnt2; + uint32_t term_cnt, tmr_cnt; + int intfl1, intfl2; + + if (!us_ticker_inited) + us_ticker_init(); + + // Ensure coherency between current_cnt and US_TIMER->count32 + do { + current_cnt1 = current_cnt; + intfl1 = US_TIMER->intfl; + term_cnt = US_TIMER->term_cnt32; + tmr_cnt = US_TIMER->count32; + intfl2 = US_TIMER->intfl; + current_cnt2 = current_cnt; + } while ((current_cnt1 != current_cnt2) || (intfl1 != intfl2)); + + if (intfl1) { + current_cnt1 += term_cnt; + } + + current_cnt1 += tmr_cnt; + + return (current_cnt1 / ticks_per_us); +} + +//****************************************************************************** +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + // Note: interrupts are disabled before this function is called. + US_TIMER->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0; // disable timer + + if (US_TIMER->intfl) { + US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupt + NVIC_ClearPendingIRQ(US_TIMER_IRQn); + inc_current_cnt(US_TIMER->term_cnt32); + } + + // add and reset the current count value + inc_current_cnt(US_TIMER->count32); + US_TIMER->count32 = 0; + + // add the number of cycles that the timer is disabled here for + inc_current_cnt(200); + + event_cnt = (uint64_t)timestamp * ticks_per_us; + + // Check to see if the event has already passed + if (!event_passed(current_cnt, event_cnt)) { + uint64_t diff = event_diff(current_cnt, event_cnt); + if (diff < (uint64_t)0xFFFFFFFF) { + // the event occurs before the next overflow + US_TIMER->term_cnt32 = diff; + } else { + // the event occurs after the next overflow + US_TIMER->term_cnt32 = 0xFFFFFFFF; // set to max + } + } else { + // the requested timestamp occurs in the past + // set the timer up to immediately expire + US_TIMER->term_cnt32 = 1; + } + US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer +} + +//****************************************************************************** +void us_ticker_disable_interrupt(void) +{ + // There are no more events, set timer overflow to the max + US_TIMER->term_cnt32 = 0xFFFFFFFF; +} + +//****************************************************************************** +void us_ticker_clear_interrupt(void) +{ + // cleared in the local handler +} + +//****************************************************************************** +void us_ticker_set(timestamp_t timestamp) +{ + US_TIMER->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0; // disable timer + current_cnt = (uint64_t)timestamp * ticks_per_us; + US_TIMER->count32 = 0; + US_TIMER->term_cnt32 = 0xFFFFFFFF; + US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer + + if (((uint64_t)timestamp * ticks_per_us) >= event_cnt) { + // The next timestamp has elapsed. Trigger the interrupt to handle it. + NVIC_SetPendingIRQ(US_TIMER_IRQn); + } +} diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h index db6c237218..530046c741 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h @@ -301,6 +301,9 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL} #elif defined(TARGET_STM32F303RE) #define INITIAL_SP (0x20010000UL) +#elif defined(TARGET_MAX32610) +#define INITIAL_SP (0x20008000UL) + #else #error "no target defined" diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c index d05145f027..0b836cd419 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c @@ -51,7 +51,7 @@ #ifndef OS_TASKCNT # if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \ - || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) + || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) # define OS_TASKCNT 14 # elif defined(TARGET_LPC11U24) || defined(TARGET_STM32F303RE) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ @@ -67,7 +67,7 @@ #ifndef OS_SCHEDULERSTKSIZE # if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \ - || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) + || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) # define OS_SCHEDULERSTKSIZE 256 # elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ @@ -168,6 +168,9 @@ #elif defined(TARGET_STM32F401VC) # define OS_CLOCK 84000000 +#elif defined(TARGET_MAX32610) +# define OS_CLOCK 24000000 + # else # error "no target defined" # endif diff --git a/libraries/tests/mbed/digitalin_digitalout/main.cpp b/libraries/tests/mbed/digitalin_digitalout/main.cpp index a056db24e6..bd8894ced2 100644 --- a/libraries/tests/mbed/digitalin_digitalout/main.cpp +++ b/libraries/tests/mbed/digitalin_digitalout/main.cpp @@ -36,6 +36,10 @@ DigitalIn in(PD_0); DigitalOut out(D7); DigitalIn in(D0); +#elif defined(TARGET_MAXWSNENV) +DigitalOut out(TP3); +DigitalIn in(TP4); + #else DigitalOut out(p5); DigitalIn in(p25); diff --git a/libraries/tests/mbed/digitalinout/main.cpp b/libraries/tests/mbed/digitalinout/main.cpp index af937041d8..d9d91a7364 100644 --- a/libraries/tests/mbed/digitalinout/main.cpp +++ b/libraries/tests/mbed/digitalinout/main.cpp @@ -36,6 +36,10 @@ DigitalInOut d2(PD_0); DigitalInOut d1(D0); DigitalInOut d2(D7); +#elif defined(TARGET_MAXWSNENV) +DigitalInOut d1(TP3); +DigitalInOut d2(TP4); + #else DigitalInOut d1(p5); DigitalInOut d2(p25); diff --git a/libraries/tests/mbed/i2c_TMP102/main.cpp b/libraries/tests/mbed/i2c_TMP102/main.cpp index 388d38e13f..163ea88d2b 100644 --- a/libraries/tests/mbed/i2c_TMP102/main.cpp +++ b/libraries/tests/mbed/i2c_TMP102/main.cpp @@ -27,7 +27,8 @@ TMP102 temperature(p28, p27, 0x90); defined(TARGET_NUCLEO_L073RZ) || \ defined(TARGET_NUCLEO_L152RE) || \ defined(TARGET_LPC824) || \ - defined(TARGET_FF_ARDUINO) + defined(TARGET_FF_ARDUINO) || \ + defined(TARGET_MAXWSNENV) TMP102 temperature(I2C_SDA, I2C_SCL, 0x90); #else diff --git a/libraries/tests/mbed/i2c_master/main.cpp b/libraries/tests/mbed/i2c_master/main.cpp index ef195192bf..392be3218c 100644 --- a/libraries/tests/mbed/i2c_master/main.cpp +++ b/libraries/tests/mbed/i2c_master/main.cpp @@ -8,7 +8,7 @@ I2C i2c(PTE0, PTE1); #elif defined(TARGET_nRF51822) I2C i2c(p22,p20); -#elif defined(TARGET_FF_ARDUINO) +#elif defined(TARGET_FF_ARDUINO) || defined(TARGET_MAXWSNENV) I2C i2c(I2C_SDA, I2C_SCL); #else I2C i2c(p28, p27); diff --git a/libraries/tests/mbed/interruptin/main.cpp b/libraries/tests/mbed/interruptin/main.cpp index 45779a0970..3a55c00d8d 100644 --- a/libraries/tests/mbed/interruptin/main.cpp +++ b/libraries/tests/mbed/interruptin/main.cpp @@ -66,6 +66,10 @@ void in_handler() { #define PIN_OUT D0 #define PIN_IN D7 +#elif defined(TARGET_MAXWSNENV) +#define PIN_OUT P0_0 +#define PIN_IN P0_1 + #else #define PIN_IN (p5) #define PIN_OUT (p25) diff --git a/libraries/tests/mbed/portinout/main.cpp b/libraries/tests/mbed/portinout/main.cpp index d88ff2d934..1a30f42561 100644 --- a/libraries/tests/mbed/portinout/main.cpp +++ b/libraries/tests/mbed/portinout/main.cpp @@ -63,6 +63,15 @@ #define P2_2 (1 << 25) // p25 #define PORT_2 Port0 +#elif defined(TARGET_MAXWSNENV) +#define P1_1 (1 << 0) +#define P1_2 (1 << 1) +#define PORT_1 Port0 + +#define P2_1 (1 << 0) +#define P2_2 (1 << 1) +#define PORT_2 Port1 + #elif defined(TARGET_NUCLEO_F030R8) || \ defined(TARGET_NUCLEO_F070RB) || \ defined(TARGET_NUCLEO_F072RB) || \ diff --git a/libraries/tests/mbed/portout/main.cpp b/libraries/tests/mbed/portout/main.cpp index b15383bad0..3c30032493 100644 --- a/libraries/tests/mbed/portout/main.cpp +++ b/libraries/tests/mbed/portout/main.cpp @@ -10,6 +10,11 @@ # define LED2 (1 << 9) // P1.9 # define LED3 (1 << 10) // P1.10 # define LED4 (1 << 11) // P1.11 +# elif defined(TARGET_MAXWSNENV) +# define LED1 (1 << 4) // P1.4 +# define LED2 (1 << 6) // P1.6 +# define LED3 (1 << 7) // P1.7 +# define LED4 0 # endif #define LED_MASK (LED1|LED2|LED3|LED4) diff --git a/libraries/tests/mbed/portout_portin/main.cpp b/libraries/tests/mbed/portout_portin/main.cpp index 263595d8f7..222c3c414a 100644 --- a/libraries/tests/mbed/portout_portin/main.cpp +++ b/libraries/tests/mbed/portout_portin/main.cpp @@ -63,6 +63,15 @@ #define P2_2 (1 << 25) // p25 #define PORT_2 Port0 +#elif defined(TARGET_MAXWSNENV) +#define P1_1 (1 << 0) +#define P1_2 (1 << 1) +#define PORT_1 Port0 + +#define P2_1 (1 << 0) +#define P2_2 (1 << 1) +#define PORT_2 Port1 + #elif defined(TARGET_NUCLEO_F030R8) || \ defined(TARGET_NUCLEO_F070RB) || \ defined(TARGET_NUCLEO_F072RB) || \ diff --git a/libraries/tests/mbed/pwm/main.cpp b/libraries/tests/mbed/pwm/main.cpp index fd99c96457..1f0b4bba62 100644 --- a/libraries/tests/mbed/pwm/main.cpp +++ b/libraries/tests/mbed/pwm/main.cpp @@ -85,6 +85,15 @@ int main() { printf("Initialize PWM on pin PA_7 with duty cycle: %.2f\n", pwm_1.read()); printf("Initialize PWM on pin PC_7 with duty cycle: %.2f\n", pwm_2.read()); +#elif defined(TARGET_MAXWSNENV) + PwmOut pwm_1(TP2); + PwmOut pwm_2(TP4); + + pwm_1.write(0.75); + pwm_2.write(0.50); + + printf("Initialize PWM on pin TP2 with duty cycle: %.2f\n", pwm_1.read()); + printf("Initialize PWM on pin TP4 with duty cycle: %.2f\n", pwm_2.read()); #else #error This test is not supported on this target. #endif diff --git a/libraries/tests/mbed/pwm_led/pwm.cpp b/libraries/tests/mbed/pwm_led/pwm.cpp index 78b47c8a79..828a41cb78 100644 --- a/libraries/tests/mbed/pwm_led/pwm.cpp +++ b/libraries/tests/mbed/pwm_led/pwm.cpp @@ -22,6 +22,9 @@ defined (TARGET_LPC824) #define TEST_LED LED_GREEN +#elif defined (TARGET_MAXWSNENV) +#define TEST_LED LED_GREEN + #else #error This test is not supported on this target. #endif diff --git a/libraries/tests/mbed/serial_interrupt_2/main.cpp b/libraries/tests/mbed/serial_interrupt_2/main.cpp index 744116045e..8833c36da7 100644 --- a/libraries/tests/mbed/serial_interrupt_2/main.cpp +++ b/libraries/tests/mbed/serial_interrupt_2/main.cpp @@ -4,6 +4,8 @@ Serial pc(USBTX, USBRX); #if defined(TARGET_LPC4088) Serial uart(P4_22, P4_23); +#elif defined(TARGET_MAXWSNENV) +Serial uart(P0_1, P0_0); #else Serial uart(p9, p10); #endif diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 6f25e0a480..fa26f5da3f 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -1111,6 +1111,16 @@ class RZ_A1H(Target): return 2 +### Maxim Integrated ### + +class MAXWSNENV(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M3" + self.extra_labels = ['Maxim', 'MAX32610'] + self.macros = ['__SYSTEM_HFX=24000000'] + self.supported_toolchains = ["GCC_ARM", "IAR", "ARM"] + self.default_toolchain = "ARM" # Get a single instance for each target TARGETS = [ @@ -1220,6 +1230,9 @@ TARGETS = [ ### Renesas ### RZ_A1H(), + + ### Maxim Integrated ### + MAXWSNENV(), ] # Map each target name to its unique instance diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index f73c203e7d..a2ccf52cb0 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -39,6 +39,7 @@ Wiring: * TMP102 (I2C): * LPC1*: (SDA=p28 , SCL=p27) * KL25Z: (SDA=PTC9, SCL=PTC8) + * MAXWSNENV: (SDA=TP6, SCL=TP5) * digital_loop (Digital(In|Out|InOut), InterruptIn): * Arduino headers: (D0 <-> D7) @@ -46,12 +47,14 @@ Wiring: * LPC1*: (p5 <-> p25 ) * KL25Z: (PTA5<-> PTC6) * NUCLEO_F103RB: (PC_6 <-> PB_8) + * MAXWSNENV: (TP3 <-> TP4) * port_loop (Port(In|Out|InOut)): * Arduino headers: (D0 <-> D7), (D1 <-> D6) * LPC1*: (p5 <-> p25), (p6 <-> p26) * KL25Z: (PTA5 <-> PTC6), (PTA4 <-> PTC5) * NUCLEO_F103RB: (PC_6 <-> PB_8), (PC_5 <-> PB_9) + * MAXWSNENV: (TP1 <-> TP3), (TP2 <-> TP4) * analog_loop (AnalogIn, AnalogOut): * Arduino headers: (A0 <-> A5) @@ -612,7 +615,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], }, { "id": "RTOS_2", "description": "Mutex resource lock", @@ -625,7 +628,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], }, { "id": "RTOS_3", "description": "Semaphore resource lock", @@ -638,7 +641,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], }, { "id": "RTOS_4", "description": "Signals messaging", @@ -650,7 +653,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], }, { "id": "RTOS_5", "description": "Queue messaging", @@ -662,7 +665,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], }, { "id": "RTOS_6", "description": "Mail messaging", @@ -674,7 +677,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], }, { "id": "RTOS_7", "description": "Timer", @@ -688,7 +691,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], }, { "id": "RTOS_8", "description": "ISR (Queue)", @@ -700,7 +703,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], }, { "id": "RTOS_9", "description": "SD File write-read", From 41d37b5f2d4c7f348418965a4f0d5d0480c1d293 Mon Sep 17 00:00:00 2001 From: Toyomasa Watarai Date: Wed, 8 Apr 2015 14:42:17 +0900 Subject: [PATCH 12/13] [RTOS] Add workaround for internal fault * Add #pragma Ospace to prevent internal fault of armcc 5.04 and 5.05 * Reported by http://developer.mbed.org/questions/5003/Compiling-latest-github-with-ARM-DS5-fai/ --- libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c | 7 +++++++ libraries/rtos/rtx/TARGET_CORTEX_M/rt_CMSIS.c | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c index 586eabec94..91a3584a33 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c @@ -2066,6 +2066,10 @@ osStatus osMailPut (osMailQId queue_id, void *mail) { return osMessagePut(*((void **)queue_id), (uint32_t)mail, 0); } +#ifdef __arm__ +#pragma push +#pragma Ospace +#endif // __arm__ /// Get a mail from a queue os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { osEvent ret; @@ -2080,3 +2084,6 @@ os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { return ret; } +#ifdef __arm__ +#pragma pop +#endif // __arm__ diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/rt_CMSIS.c b/libraries/rtos/rtx/TARGET_CORTEX_M/rt_CMSIS.c index 19d48caaa4..13a23458af 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/rt_CMSIS.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/rt_CMSIS.c @@ -1862,6 +1862,10 @@ osStatus osMailPut (osMailQId queue_id, void *mail) { return osMessagePut(*((void **)queue_id), (uint32_t)mail, 0); } +#ifdef __arm__ +#pragma push +#pragma Ospace +#endif // __arm__ /// Get a mail from a queue os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { osEvent ret; @@ -1876,3 +1880,6 @@ os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { return ret; } +#ifdef __arm__ +#pragma pop +#endif // __arm__ From 331dc0725ddd63483e057688dfd2f70d628f7c29 Mon Sep 17 00:00:00 2001 From: 0xc0170 Date: Wed, 8 Apr 2015 08:10:42 +0200 Subject: [PATCH 13/13] Squashed commits from #1002, from Marcomissyou. Delta target - add RTC, bugfixes in mbed_overrides and pinnames --- .../TARGET_DELTA_DFCM_NNN40/PinNames.h | 25 +++--- .../TARGET_DELTA_DFCM_NNN40/device.h | 2 +- .../TARGET_DELTA_DFCM_NNN40/mbed_overrides.c | 88 ++++++++++++++++++- .../TARGET_DELTA_DFCM_NNN40/rtc_api.c | 71 +++++++++++++++ workspace_tools/targets.py | 9 -- 5 files changed, 174 insertions(+), 21 deletions(-) create mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/rtc_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h index c6c288ec62..3db5f772a8 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h @@ -62,7 +62,7 @@ typedef enum { p28 = NC, p29 = 29, p30 = 30, - p31 = 31, + p31 = 31, LED1 = p7, LED2 = p13, @@ -96,19 +96,24 @@ typedef enum { A3 = p3, A4 = p4, A5 = p5, - - SWIO = p19, - VERF0 = p0, + + SWIO = p19, + VERF0 = p0, + + // SPI for controlling internal flash, don't use it. + FLASH_SPIMOSI = 15, + FLASH_SPIMISO = 9, + FLASH_SPICS = 28, + FLASH_SPICLK = 11, // Not connected - - CTS_PIN_NUMBER = NC, - RTS_PIN_NUMBER = NC, - SPI_PSELMOSI1 = NC, + CTS_PIN_NUMBER= NC, + RTS_PIN_NUMBER= NC, + SPI_PSELMOSI1 = NC, SPI_PSELMISO1 = NC, SPI_PSELSS1 = NC, SPI_PSELSCK1 = NC, - LED3 = NC, - LED4 = NC + LED3 = NC, + LED4 = NC } PinName; typedef enum { diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h index 21442bcf3a..2b5a0b6b3f 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h @@ -35,7 +35,7 @@ #define DEVICE_CAN 0 -#define DEVICE_RTC 0 +#define DEVICE_RTC 1 #define DEVICE_ETHERNET 0 diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c index 68809a503b..d3d2fe0d64 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c @@ -13,9 +13,89 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #include "cmsis.h" + +#define SPIM1_SCK_PIN 11u /**< SPI clock GPIO pin number. */ +#define SPIM1_MOSI_PIN 15u /**< SPI Master Out Slave In GPIO pin number. */ +#define SPIM1_MISO_PIN 9u /**< SPI Master In Slave Out GPIO pin number. */ +#define SPIM1_SS_PIN 28u /**< SPI Slave Select GPIO pin number. */ + +#define CMD_POWER_UP (0xAB) +#define CMD_POWER_DOWN (0xB9) + +void spi_flash_init(void) +{ + NRF_GPIO->PIN_CNF[SPIM1_MOSI_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); + NRF_GPIO->PIN_CNF[SPIM1_MISO_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); + NRF_GPIO->PIN_CNF[SPIM1_SCK_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); + + NRF_GPIO->PIN_CNF[SPIM1_SS_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + //cs = 1; + NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos); + + NRF_SPI1->ENABLE = 1; + NRF_SPI1->PSELSCK = SPIM1_SCK_PIN; + NRF_SPI1->PSELMOSI = SPIM1_MISO_PIN; + NRF_SPI1->PSELMISO = SPIM1_MOSI_PIN; + //spi.frequency(1000000); + NRF_SPI1->FREQUENCY = 0x10000000; //1MHz + + //spi.format(8,0); + uint32_t config_mode = 0; + config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos); //mode 0 + NRF_SPI1->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos)); + //cs = 0; + NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos); + //spi.write(CMD_POWER_UP); + while (!NRF_SPI1->EVENTS_READY == 0) { + } + NRF_SPI1->TXD = (uint32_t)CMD_POWER_UP; + while (!NRF_SPI1->EVENTS_READY == 1) { + } + NRF_SPI1->EVENTS_READY = 0; + NRF_SPI1->RXD; + //wait_ms(30); + // Deselect the device + //cs = 1; + NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos); + +} + +void spi_flash_powerDown(void) +{ + NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos); + //spi.write(CMD_POWER_DOWN); + while (!NRF_SPI1->EVENTS_READY == 0) { + } + NRF_SPI1->TXD = (uint32_t)CMD_POWER_DOWN; + while (!NRF_SPI1->EVENTS_READY == 1) { + } + NRF_SPI1->EVENTS_READY = 0; + NRF_SPI1->RXD; + NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos); + + //wait for sleep + //wait_us(3); +} + void mbed_sdk_init() { // Default SWIO setting, pull SWIO(p19) to low for turning antenna switch to BLE radiated path @@ -34,4 +114,10 @@ void mbed_sdk_init() while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0) {// Do nothing. } + + spi_flash_init(); + + //nrf_delay_ms(10); + spi_flash_powerDown(); + } diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/rtc_api.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/rtc_api.c new file mode 100644 index 0000000000..527d308058 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/rtc_api.c @@ -0,0 +1,71 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "rtc_api.h" + + +#define LFCLK_FREQUENCY (32768UL) +#define RTC0_COUNTER_PRESCALER ((LFCLK_FREQUENCY/8) - 1) +#define COMPARE_COUNTERTIME (691200UL) //86400 x 8 + + +time_t initTime; + +void rtc_init(void) { + + NVIC_EnableIRQ(RTC0_IRQn); // Enable Interrupt for the RTC in the core. + //NRF_RTC0->TASKS_STOP =1; + NRF_RTC0->PRESCALER = RTC0_COUNTER_PRESCALER; // Set prescaler to a TICK of RTC_FREQUENCY. + NRF_RTC0->CC[0] = COMPARE_COUNTERTIME; // Compare0 after approx COMPARE_COUNTERTIME seconds. + + // Enable COMPARE0 event and COMPARE0 interrupt: + NRF_RTC0->EVTENSET = RTC_EVTENSET_COMPARE0_Msk; + NRF_RTC0->INTENSET = RTC_INTENSET_COMPARE0_Msk; + NRF_RTC0->TASKS_START = 1; +} + +void rtc_free(void) { + // [TODO] +} + +/* + * Little check routine to see if the RTC has been enabled + * + * Clock Control Register + * RTC_CCR[0] : 0 = Disabled, 1 = Enabled + * + */ +int rtc_isenabled(void) { + // [TODO] return(((NRF_RTC0->TASKS_START) & 0x01) != 0); +} + +time_t rtc_read(void) { + + time_t t = initTime; + t += (86400*NRF_RTC0->EVENTS_COMPARE[0]); + t += (int)((NRF_RTC0->COUNTER)/8); + return(t); +} + +void rtc_write(time_t t) { + // Convert the time in to a tm + + // Pause clock, and clear counter register (clears us count) + NRF_RTC0->TASKS_STOP = 1; + + initTime = t; + // Restart clock + NRF_RTC0->TASKS_START = 1; +} diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 6f25e0a480..b1d85b3659 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -1027,15 +1027,6 @@ class DELTA_DFCM_NNN40_OTA(NRF51822): self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'DELTA_DFCM_NNN40'] self.MERGE_SOFT_DEVICE = False self.macros += self.common_macros - -class DELTA_DFCM_NNN40_OTA(NRF51822): - def __init__(self): - NRF51822.__init__(self) - self.core = "Cortex-M0" - self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'DELTA_DFCM_NNN40'] - self.MERGE_SOFT_DEVICE = False - self.macros += self.common_macros - ### ARM ### class ARM_MPS2_M0(Target):