mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #3312 from NXPmicro/SPI_ASYNCH_API
K64F: SPI Asynch API implementationpull/3360/merge
Martin Kojtal
GitHub
commit
163667165e
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@ -0,0 +1,48 @@
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/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FSL_DMA_REQS_H_
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#define _FSL_DMA_REQS_H_
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#include "fsl_common.h"
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/* Array for DSPI DMA TX requests */
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#define SPI_DMA_TX_REQUEST_NUMBERS \
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{ \
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kDmaRequestMux0SPI0Tx, kDmaRequestMux0SPI1, kDmaRequestMux0SPI2 \
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}
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/* Array for DSPI DMA RX requests */
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#define SPI_DMA_RX_REQUEST_NUMBERS \
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{ \
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kDmaRequestMux0SPI0Rx, kDmaRequestMux0SPI1, kDmaRequestMux0SPI2 \
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}
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#endif /* _FSL_DMA_REQS_H_ */
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@ -162,8 +162,6 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
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handle->txBuffIfNull = ((uint32_t)DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA;
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handle->state = kDSPI_Busy;
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dspi_command_data_config_t commandStruct;
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DSPI_StopTransfer(base);
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DSPI_FlushFifo(base, true, true);
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@ -222,6 +220,8 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
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return kStatus_InvalidArgument;
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}
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handle->state = kDSPI_Busy;
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DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
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EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiMasterCallback,
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@ -706,13 +706,13 @@ static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle,
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DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
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dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
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if (dspiEdmaPrivateHandle->handle->callback)
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{
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dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle,
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kStatus_Success, dspiEdmaPrivateHandle->handle->userData);
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}
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dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
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}
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void DSPI_MasterTransferAbortEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle)
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@ -25,6 +25,7 @@
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#include "mbed_error.h"
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#include "fsl_dspi.h"
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#include "peripheral_clock_defines.h"
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#include "dma_reqs.h"
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#include "PeripheralPins.h"
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/* Array of SPI peripheral base address. */
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@ -42,8 +43,8 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
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uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
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uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
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obj->instance = pinmap_merge(spi_data, spi_cntl);
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MBED_ASSERT((int)obj->instance != NC);
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obj->spi.instance = pinmap_merge(spi_data, spi_cntl);
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MBED_ASSERT((int)obj->spi.instance != NC);
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// pin out the spi pins
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pinmap_pinout(mosi, PinMap_SPI_MOSI);
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@ -52,11 +53,16 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
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if (ssel != NC) {
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pinmap_pinout(ssel, PinMap_SPI_SSEL);
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}
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/* Set the transfer status to idle */
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obj->spi.status = kDSPI_Idle;
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obj->spi.spiDmaMasterRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC;
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}
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void spi_free(spi_t *obj)
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{
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DSPI_Deinit(spi_address[obj->instance]);
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DSPI_Deinit(spi_address[obj->spi.instance]);
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}
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void spi_format(spi_t *obj, int bits, int mode, int slave)
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@ -64,6 +70,10 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
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dspi_master_config_t master_config;
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dspi_slave_config_t slave_config;
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/* Bits: values between 4 and 16 are valid */
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MBED_ASSERT(bits >= 4 && bits <= 16);
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obj->spi.bits = bits;
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if (slave) {
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/* Slave config */
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DSPI_SlaveGetDefaultConfig(&slave_config);
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@ -72,7 +82,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
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slave_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
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slave_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
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DSPI_SlaveInit(spi_address[obj->instance], &slave_config);
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DSPI_SlaveInit(spi_address[obj->spi.instance], &slave_config);
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} else {
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/* Master config */
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DSPI_MasterGetDefaultConfig(&master_config);
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@ -82,21 +92,21 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
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master_config.ctarConfig.direction = kDSPI_MsbFirst;
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master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
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DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));
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DSPI_MasterInit(spi_address[obj->spi.instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->spi.instance]));
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}
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}
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void spi_frequency(spi_t *obj, int hz)
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{
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uint32_t busClock = CLOCK_GetFreq(spi_clocks[obj->instance]);
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DSPI_MasterSetBaudRate(spi_address[obj->instance], kDSPI_Ctar0, (uint32_t)hz, busClock);
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uint32_t busClock = CLOCK_GetFreq(spi_clocks[obj->spi.instance]);
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DSPI_MasterSetBaudRate(spi_address[obj->spi.instance], kDSPI_Ctar0, (uint32_t)hz, busClock);
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//Half clock period delay after SPI transfer
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DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
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DSPI_MasterSetDelayTimes(spi_address[obj->spi.instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
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}
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static inline int spi_readable(spi_t * obj)
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{
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return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
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return (DSPI_GetStatusFlags(spi_address[obj->spi.instance]) & kDSPI_RxFifoDrainRequestFlag);
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}
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int spi_master_write(spi_t *obj, int value)
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@ -106,14 +116,14 @@ int spi_master_write(spi_t *obj, int value)
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DSPI_GetDefaultDataCommandConfig(&command);
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command.isEndOfQueue = true;
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DSPI_MasterWriteDataBlocking(spi_address[obj->instance], &command, (uint16_t)value);
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DSPI_MasterWriteDataBlocking(spi_address[obj->spi.instance], &command, (uint16_t)value);
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DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_TxFifoFillRequestFlag);
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DSPI_ClearStatusFlags(spi_address[obj->spi.instance], kDSPI_TxFifoFillRequestFlag);
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// wait rx buffer full
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while (!spi_readable(obj));
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rx_data = DSPI_ReadData(spi_address[obj->instance]);
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DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag | kDSPI_EndOfQueueFlag);
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rx_data = DSPI_ReadData(spi_address[obj->spi.instance]);
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DSPI_ClearStatusFlags(spi_address[obj->spi.instance], kDSPI_RxFifoDrainRequestFlag | kDSPI_EndOfQueueFlag);
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return rx_data & 0xffff;
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}
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@ -127,14 +137,297 @@ int spi_slave_read(spi_t *obj)
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uint32_t rx_data;
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while (!spi_readable(obj));
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rx_data = DSPI_ReadData(spi_address[obj->instance]);
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DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag);
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rx_data = DSPI_ReadData(spi_address[obj->spi.instance]);
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DSPI_ClearStatusFlags(spi_address[obj->spi.instance], kDSPI_RxFifoDrainRequestFlag);
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return rx_data & 0xffff;
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}
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void spi_slave_write(spi_t *obj, int value)
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{
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DSPI_SlaveWriteDataBlocking(spi_address[obj->instance], (uint32_t)value);
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DSPI_SlaveWriteDataBlocking(spi_address[obj->spi.instance], (uint32_t)value);
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}
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static int32_t spi_master_transfer_asynch(spi_t *obj)
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{
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dspi_transfer_t masterXfer;
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int32_t status;
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uint32_t transferSize;
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/*Start master transfer*/
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masterXfer.txData = obj->tx_buff.buffer;
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masterXfer.rxData = obj->rx_buff.buffer;
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masterXfer.dataSize = obj->tx_buff.length;
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masterXfer.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous;
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/* Busy transferring */
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obj->spi.status = kDSPI_Busy;
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if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_ALLOCATED ||
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obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
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status = DSPI_MasterTransferEDMA(spi_address[obj->spi.instance], &obj->spi.spi_dma_master_handle, &masterXfer);
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if (status == kStatus_DSPI_OutOfRange) {
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if (obj->spi.bits > 8) {
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transferSize = 1022;
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} else {
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transferSize = 511;
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}
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masterXfer.dataSize = transferSize;
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/* Save amount of TX done by DMA */
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obj->tx_buff.pos += transferSize;
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obj->rx_buff.pos += transferSize;
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/* Try again */
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status = DSPI_MasterTransferEDMA(spi_address[obj->spi.instance], &obj->spi.spi_dma_master_handle, &masterXfer);
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}
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} else {
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status = DSPI_MasterTransferNonBlocking(spi_address[obj->spi.instance], &obj->spi.spi_master_handle, &masterXfer);
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}
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return status;
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}
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static bool spi_allocate_dma(spi_t *obj, uint32_t handler)
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{
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dma_request_source_t dma_rx_requests[] = SPI_DMA_RX_REQUEST_NUMBERS;
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dma_request_source_t dma_tx_requests[] = SPI_DMA_TX_REQUEST_NUMBERS;
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edma_config_t userConfig;
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/* Allocate the DMA channels */
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/* Allocate the RX channel */
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obj->spi.spiDmaMasterRx.dmaChannel = dma_channel_allocate(dma_rx_requests[obj->spi.instance]);
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if (obj->spi.spiDmaMasterRx.dmaChannel == DMA_ERROR_OUT_OF_CHANNELS) {
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return false;
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}
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/* Check if we have separate DMA requests for TX & RX */
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if (dma_tx_requests[obj->spi.instance] != dma_rx_requests[obj->spi.instance]) {
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/* Allocate the TX channel with the DMA TX request number set as source */
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obj->spi.spiDmaMasterTx.dmaChannel = dma_channel_allocate(dma_tx_requests[obj->spi.instance]);
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} else {
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/* Allocate the TX channel without setting source */
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obj->spi.spiDmaMasterTx.dmaChannel = dma_channel_allocate(kDmaRequestMux0Disable);
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}
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if (obj->spi.spiDmaMasterTx.dmaChannel == DMA_ERROR_OUT_OF_CHANNELS) {
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dma_channel_free(obj->spi.spiDmaMasterRx.dmaChannel);
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return false;
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}
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/* Allocate an intermediary DMA channel */
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obj->spi.spiDmaMasterIntermediary.dmaChannel = dma_channel_allocate(kDmaRequestMux0Disable);
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if (obj->spi.spiDmaMasterIntermediary.dmaChannel == DMA_ERROR_OUT_OF_CHANNELS) {
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dma_channel_free(obj->spi.spiDmaMasterRx.dmaChannel);
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dma_channel_free(obj->spi.spiDmaMasterTx.dmaChannel);
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return false;
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}
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/* EDMA init*/
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/*
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* userConfig.enableRoundRobinArbitration = false;
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* userConfig.enableHaltOnError = true;
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* userConfig.enableContinuousLinkMode = false;
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* userConfig.enableDebugMode = false;
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*/
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EDMA_GetDefaultConfig(&userConfig);
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EDMA_Init(DMA0, &userConfig);
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/* Set up dspi master */
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memset(&(obj->spi.spiDmaMasterRx.handle), 0, sizeof(obj->spi.spiDmaMasterRx.handle));
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memset(&(obj->spi.spiDmaMasterTx.handle), 0, sizeof(obj->spi.spiDmaMasterTx.handle));
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memset(&(obj->spi.spiDmaMasterIntermediary.handle), 0, sizeof(obj->spi.spiDmaMasterIntermediary.handle));
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EDMA_CreateHandle(&(obj->spi.spiDmaMasterRx.handle), DMA0, obj->spi.spiDmaMasterRx.dmaChannel);
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EDMA_CreateHandle(&(obj->spi.spiDmaMasterIntermediary.handle), DMA0,
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obj->spi.spiDmaMasterIntermediary.dmaChannel);
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EDMA_CreateHandle(&(obj->spi.spiDmaMasterTx.handle), DMA0, obj->spi.spiDmaMasterTx.dmaChannel);
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DSPI_MasterTransferCreateHandleEDMA(spi_address[obj->spi.instance], &obj->spi.spi_dma_master_handle, (dspi_master_edma_transfer_callback_t)handler,
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NULL, &obj->spi.spiDmaMasterRx.handle,
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&obj->spi.spiDmaMasterIntermediary.handle,
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&obj->spi.spiDmaMasterTx.handle);
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return true;
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}
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static void spi_enable_dma(spi_t *obj, uint32_t handler, DMAUsage state)
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{
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dma_init();
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if (state == DMA_USAGE_ALWAYS && obj->spi.spiDmaMasterRx.dmaUsageState != DMA_USAGE_ALLOCATED) {
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/* Try to allocate channels */
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if (spi_allocate_dma(obj, handler)) {
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obj->spi.spiDmaMasterRx.dmaUsageState = DMA_USAGE_ALLOCATED;
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} else {
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obj->spi.spiDmaMasterRx.dmaUsageState = state;
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}
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} else if (state == DMA_USAGE_OPPORTUNISTIC) {
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if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_ALLOCATED) {
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/* Channels have already been allocated previously by an ALWAYS state, so after this transfer, we will release them */
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obj->spi.spiDmaMasterRx.dmaUsageState = DMA_USAGE_TEMPORARY_ALLOCATED;
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} else {
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/* Try to allocate channels */
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if (spi_allocate_dma(obj, handler)) {
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obj->spi.spiDmaMasterRx.dmaUsageState = DMA_USAGE_TEMPORARY_ALLOCATED;
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} else {
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obj->spi.spiDmaMasterRx.dmaUsageState = state;
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}
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}
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} else if (state == DMA_USAGE_NEVER) {
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/* If channels are allocated, get rid of them */
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if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_ALLOCATED) {
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dma_channel_free(obj->spi.spiDmaMasterRx.dmaChannel);
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dma_channel_free(obj->spi.spiDmaMasterTx.dmaChannel);
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dma_channel_free(obj->spi.spiDmaMasterIntermediary.dmaChannel);
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}
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obj->spi.spiDmaMasterRx.dmaUsageState = DMA_USAGE_NEVER;
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}
|
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}
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static void spi_buffer_set(spi_t *obj, const void *tx, uint32_t tx_length, void *rx, uint32_t rx_length, uint8_t bit_width)
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{
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obj->tx_buff.buffer = (void *)tx;
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obj->rx_buff.buffer = rx;
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obj->tx_buff.length = tx_length;
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obj->rx_buff.length = rx_length;
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obj->tx_buff.pos = 0;
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obj->rx_buff.pos = 0;
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obj->tx_buff.width = bit_width;
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obj->rx_buff.width = bit_width;
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}
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void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
|
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{
|
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if(spi_active(obj)) {
|
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return;
|
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}
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/* check corner case */
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if(tx_length == 0) {
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tx_length = rx_length;
|
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tx = (void*) 0;
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}
|
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|
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/* First, set the buffer */
|
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spi_buffer_set(obj, tx, tx_length, rx, rx_length, bit_width);
|
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|
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/* If using DMA, allocate channels only if they have not already been allocated */
|
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if (hint != DMA_USAGE_NEVER) {
|
||||
/* User requested to transfer using DMA */
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spi_enable_dma(obj, handler, hint);
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|
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/* Check if DMA setup was successful */
|
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if (obj->spi.spiDmaMasterRx.dmaUsageState != DMA_USAGE_ALLOCATED && obj->spi.spiDmaMasterRx.dmaUsageState != DMA_USAGE_TEMPORARY_ALLOCATED) {
|
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/* Set up an interrupt transfer as DMA is unavailable */
|
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DSPI_MasterTransferCreateHandle(spi_address[obj->spi.instance], &obj->spi.spi_master_handle, (dspi_master_transfer_callback_t)handler, NULL);
|
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}
|
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} else {
|
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/* User requested to transfer using interrupts */
|
||||
/* Disable the DMA */
|
||||
spi_enable_dma(obj, handler, hint);
|
||||
|
||||
/* Set up the interrupt transfer */
|
||||
DSPI_MasterTransferCreateHandle(spi_address[obj->spi.instance], &obj->spi.spi_master_handle, (dspi_master_transfer_callback_t)handler, NULL);
|
||||
}
|
||||
|
||||
/* Start the transfer */
|
||||
if (spi_master_transfer_asynch(obj) != kStatus_Success) {
|
||||
obj->spi.status = kDSPI_Idle;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t spi_irq_handler_asynch(spi_t *obj)
|
||||
{
|
||||
uint32_t transferSize;
|
||||
dspi_transfer_t masterXfer;
|
||||
|
||||
/* Determine whether the current scenario is DMA or IRQ, and act accordingly */
|
||||
if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_ALLOCATED || obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
|
||||
/* DMA implementation */
|
||||
/* Check If there is still data in the TX buffer */
|
||||
if (obj->tx_buff.pos < obj->tx_buff.length) {
|
||||
/* Setup a new DMA transfer. */
|
||||
if (obj->spi.bits > 8) {
|
||||
transferSize = 1022;
|
||||
} else {
|
||||
transferSize = 511;
|
||||
}
|
||||
|
||||
/* Update the TX buffer only if it is used */
|
||||
if (obj->tx_buff.buffer) {
|
||||
masterXfer.txData = ((uint8_t *)obj->tx_buff.buffer) + obj->tx_buff.pos;
|
||||
} else {
|
||||
masterXfer.txData = 0;
|
||||
}
|
||||
|
||||
/* Update the RX buffer only if it is used */
|
||||
if (obj->rx_buff.buffer) {
|
||||
masterXfer.rxData = ((uint8_t *)obj->rx_buff.buffer) + obj->rx_buff.pos;
|
||||
} else {
|
||||
masterXfer.rxData = 0;
|
||||
}
|
||||
|
||||
/* Check how much data is remaining in the buffer */
|
||||
if ((obj->tx_buff.length - obj->tx_buff.pos) > transferSize) {
|
||||
masterXfer.dataSize = transferSize;
|
||||
} else {
|
||||
masterXfer.dataSize = obj->tx_buff.length - obj->tx_buff.pos;
|
||||
}
|
||||
masterXfer.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous;
|
||||
|
||||
/* Save amount of TX done by DMA */
|
||||
obj->tx_buff.pos += masterXfer.dataSize;
|
||||
obj->rx_buff.pos += masterXfer.dataSize;
|
||||
|
||||
/* Start another transfer */
|
||||
DSPI_MasterTransferEDMA(spi_address[obj->spi.instance], &obj->spi.spi_dma_master_handle, &masterXfer);
|
||||
return 0;
|
||||
} else {
|
||||
/* Release the dma channels if they were opportunistically allocated */
|
||||
if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
|
||||
dma_channel_free(obj->spi.spiDmaMasterRx.dmaChannel);
|
||||
dma_channel_free(obj->spi.spiDmaMasterTx.dmaChannel);
|
||||
dma_channel_free(obj->spi.spiDmaMasterIntermediary.dmaChannel);
|
||||
obj->spi.spiDmaMasterRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC;
|
||||
}
|
||||
obj->spi.status = kDSPI_Idle;
|
||||
|
||||
return SPI_EVENT_COMPLETE;
|
||||
}
|
||||
} else {
|
||||
/* Interrupt implementation */
|
||||
obj->spi.status = kDSPI_Idle;
|
||||
|
||||
return SPI_EVENT_COMPLETE;
|
||||
}
|
||||
}
|
||||
|
||||
void spi_abort_asynch(spi_t *obj)
|
||||
{
|
||||
// If we're not currently transferring, then there's nothing to do here
|
||||
if(spi_active(obj) == 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
// Determine whether we're running DMA or interrupt
|
||||
if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_ALLOCATED ||
|
||||
obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
|
||||
DSPI_MasterTransferAbortEDMA(spi_address[obj->spi.instance], &obj->spi.spi_dma_master_handle);
|
||||
/* Release the dma channels if they were opportunistically allocated */
|
||||
if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
|
||||
dma_channel_free(obj->spi.spiDmaMasterRx.dmaChannel);
|
||||
dma_channel_free(obj->spi.spiDmaMasterTx.dmaChannel);
|
||||
dma_channel_free(obj->spi.spiDmaMasterIntermediary.dmaChannel);
|
||||
obj->spi.spiDmaMasterRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC;
|
||||
}
|
||||
} else {
|
||||
/* Interrupt implementation */
|
||||
DSPI_MasterTransferAbort(spi_address[obj->spi.instance], &obj->spi.spi_master_handle);
|
||||
}
|
||||
|
||||
obj->spi.status = kDSPI_Idle;
|
||||
}
|
||||
|
||||
uint8_t spi_active(spi_t *obj)
|
||||
{
|
||||
return obj->spi.status;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_dmamux.h"
|
||||
#include "dma_api.h"
|
||||
|
||||
uint32_t channels = 0; // Bit vector of taken channels
|
||||
|
||||
void dma_init(void)
|
||||
{
|
||||
/* DMA MUX init */
|
||||
DMAMUX_Init(DMAMUX0);
|
||||
}
|
||||
|
||||
int dma_channel_allocate(uint32_t capabilities)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS; i++) {
|
||||
if ((channels & (1 << i)) == 0) {
|
||||
// Channel available
|
||||
channels |= 1 << i;
|
||||
/* Check if we need to set the source and enable the MUX for this channel */
|
||||
if (capabilities != kDmaRequestMux0Disable) {
|
||||
DMAMUX_SetSource(DMAMUX0, i, capabilities);
|
||||
DMAMUX_EnableChannel(DMAMUX0, i);
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
}
|
||||
|
||||
// Couldn't find a channel.
|
||||
return DMA_ERROR_OUT_OF_CHANNELS;
|
||||
}
|
||||
|
||||
int dma_channel_free(int channelid)
|
||||
{
|
||||
channels &= ~(1 << channelid);
|
||||
DMAMUX_DisableChannel(DMAMUX0, channelid);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef MBED_DMA_API_HAL_H
|
||||
#define MBED_DMA_API_HAL_H
|
||||
|
||||
#include "dma_api.h"
|
||||
#if defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT >= 1U)
|
||||
#include "fsl_edma.h"
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT >= 1U)
|
||||
#include "fsl_dma.h"
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
DMAUsage dmaUsageState;
|
||||
int dmaChannel;
|
||||
#if defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT >= 1U)
|
||||
edma_handle_t handle;
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT >= 1U)
|
||||
dma_handle_t handle;
|
||||
#endif
|
||||
} dma_options_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -20,6 +20,10 @@
|
|||
#include "PortNames.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "PinNames.h"
|
||||
#if DEVICE_SPI_ASYNCH
|
||||
#include "fsl_dspi_edma.h"
|
||||
#endif
|
||||
#include "dma_api_hal.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
|
@ -55,6 +59,15 @@ struct i2c_s {
|
|||
|
||||
struct spi_s {
|
||||
uint32_t instance;
|
||||
uint8_t bits;
|
||||
#if DEVICE_SPI_ASYNCH
|
||||
status_t status;
|
||||
dspi_master_handle_t spi_master_handle;
|
||||
dspi_master_edma_handle_t spi_dma_master_handle;
|
||||
dma_options_t spiDmaMasterRx;
|
||||
dma_options_t spiDmaMasterTx;
|
||||
dma_options_t spiDmaMasterIntermediary;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct dac_s {
|
||||
|
|
|
|||
|
|
@ -576,7 +576,7 @@
|
|||
"macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED"],
|
||||
"inherits": ["Target"],
|
||||
"detect_code": ["0240"],
|
||||
"device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "STORAGE", "TRNG"],
|
||||
"device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "STORAGE", "TRNG"],
|
||||
"features": ["LWIP", "STORAGE"],
|
||||
"release_versions": ["2", "5"],
|
||||
"device_name": "MK64FN1M0xxx12"
|
||||
|
|
@ -588,7 +588,7 @@
|
|||
"extra_labels": ["Freescale", "KSDK2_MCUS", "KPSDK_MCUS", "KPSDK_CODE", "MCU_K64F"],
|
||||
"is_disk_virtual": true,
|
||||
"macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"],
|
||||
"device_has": ["I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
|
||||
"device_has": ["I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES"],
|
||||
"device_name": "MK64FN1M0xxx12"
|
||||
},
|
||||
"HEXIWEAR": {
|
||||
|
|
@ -600,7 +600,7 @@
|
|||
"is_disk_virtual": true,
|
||||
"default_toolchain": "ARM",
|
||||
"detect_code": ["0214"],
|
||||
"device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
|
||||
"device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
|
||||
"default_lib": "std",
|
||||
"release_versions": ["2", "5"],
|
||||
"device_name": "MK64FN1M0xxx12"
|
||||
|
|
|
|||
Loading…
Reference in New Issue