mirror of https://github.com/ARMmbed/mbed-os.git
Add KL25Z support to rtos
Emilio Monti
parent
865ffcb623
commit
15e1cb5bbb
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@ -0,0 +1,301 @@
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/*----------------------------------------------------------------------------
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* RL-ARM - RTX
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*----------------------------------------------------------------------------
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* Name: HAL_CM0.C
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* Purpose: Hardware Abstraction Layer for Cortex-M0
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* Rev.: V4.60
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*----------------------------------------------------------------------------
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*
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* Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
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* All rights reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* - Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*---------------------------------------------------------------------------*/
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#include "rt_TypeDef.h"
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#include "RTX_Config.h"
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#include "rt_System.h"
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#include "rt_HAL_CM.h"
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#include "rt_Task.h"
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#include "rt_MemBox.h"
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/*----------------------------------------------------------------------------
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* Functions
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*---------------------------------------------------------------------------*/
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/*--------------------------- rt_set_PSP ------------------------------------*/
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__asm void rt_set_PSP (U32 stack) {
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MSR PSP,R0
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BX LR
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}
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/*--------------------------- rt_get_PSP ------------------------------------*/
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__asm U32 rt_get_PSP (void) {
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MRS R0,PSP
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BX LR
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}
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/*--------------------------- os_set_env ------------------------------------*/
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__asm void os_set_env (void) {
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/* Switch to Unprivileged/Privileged Thread mode, use PSP. */
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MOV R0,SP ; PSP = MSP
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MSR PSP,R0
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LDR R0,=__cpp(&os_flags)
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LDRB R0,[R0]
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LSLS R0,#31
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BNE PrivilegedE
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MOVS R0,#0x03 ; Unprivileged Thread mode, use PSP
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MSR CONTROL,R0
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BX LR
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PrivilegedE
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MOVS R0,#0x02 ; Privileged Thread mode, use PSP
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MSR CONTROL,R0
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BX LR
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ALIGN
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}
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/*--------------------------- _alloc_box ------------------------------------*/
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__asm void *_alloc_box (void *box_mem) {
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/* Function wrapper for Unprivileged/Privileged mode. */
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LDR R3,=__cpp(rt_alloc_box)
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MOV R12,R3
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MRS R3,IPSR
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LSLS R3,#24
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BNE PrivilegedA
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MRS R3,CONTROL
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LSLS R3,#31
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BEQ PrivilegedA
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SVC 0
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BX LR
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PrivilegedA
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BX R12
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ALIGN
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}
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/*--------------------------- _free_box -------------------------------------*/
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__asm int _free_box (void *box_mem, void *box) {
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/* Function wrapper for Unprivileged/Privileged mode. */
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LDR R3,=__cpp(rt_free_box)
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MOV R12,R3
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MRS R3,IPSR
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LSLS R3,#24
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BNE PrivilegedF
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MRS R3,CONTROL
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LSLS R3,#31
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BEQ PrivilegedF
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SVC 0
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BX LR
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PrivilegedF
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BX R12
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ALIGN
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}
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/*-------------------------- SVC_Handler ------------------------------------*/
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__asm void SVC_Handler (void) {
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PRESERVE8
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IMPORT SVC_Count
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IMPORT SVC_Table
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IMPORT rt_stk_check
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MRS R0,PSP ; Read PSP
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LDR R1,[R0,#24] ; Read Saved PC from Stack
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SUBS R1,R1,#2 ; Point to SVC Instruction
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LDRB R1,[R1] ; Load SVC Number
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CMP R1,#0
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BNE SVC_User ; User SVC Number > 0
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MOV LR,R4
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LDMIA R0,{R0-R3,R4} ; Read R0-R3,R12 from stack
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MOV R12,R4
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MOV R4,LR
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BLX R12 ; Call SVC Function
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MRS R3,PSP ; Read PSP
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STMIA R3!,{R0-R2} ; Store return values
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LDR R3,=__cpp(&os_tsk)
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LDMIA R3!,{R1,R2} ; os_tsk.run, os_tsk.new
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CMP R1,R2
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BEQ SVC_Exit ; no task switch
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SUBS R3,#8
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CMP R1,#0 ; Runtask deleted?
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BEQ SVC_Next
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MRS R0,PSP ; Read PSP
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SUBS R0,R0,#32 ; Adjust Start Address
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STR R0,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack
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STMIA R0!,{R4-R7} ; Save old context (R4-R7)
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MOV R4,R8
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MOV R5,R9
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MOV R6,R10
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MOV R7,R11
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STMIA R0!,{R4-R7} ; Save old context (R8-R11)
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PUSH {R2,R3}
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BL rt_stk_check ; Check for Stack overflow
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POP {R2,R3}
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SVC_Next
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STR R2,[R3] ; os_tsk.run = os_tsk.new
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LDR R0,[R2,#TCB_TSTACK] ; os_tsk.new->tsk_stack
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ADDS R0,R0,#16 ; Adjust Start Address
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LDMIA R0!,{R4-R7} ; Restore new Context (R8-R11)
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MOV R8,R4
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MOV R9,R5
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MOV R10,R6
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MOV R11,R7
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MSR PSP,R0 ; Write PSP
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SUBS R0,R0,#32 ; Adjust Start Address
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LDMIA R0!,{R4-R7} ; Restore new Context (R4-R7)
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SVC_Exit
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MOVS R0,#:NOT:0xFFFFFFFD ; Set EXC_RETURN value
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MVNS R0,R0
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BX R0 ; RETI to Thread Mode, use PSP
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/*------------------- User SVC ------------------------------*/
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SVC_User
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PUSH {R4,LR} ; Save Registers
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LDR R2,=SVC_Count
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LDR R2,[R2]
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CMP R1,R2
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BHI SVC_Done ; Overflow
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LDR R4,=SVC_Table-4
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LSLS R1,R1,#2
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LDR R4,[R4,R1] ; Load SVC Function Address
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MOV LR,R4
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LDMIA R0,{R0-R3,R4} ; Read R0-R3,R12 from stack
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MOV R12,R4
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BLX LR ; Call SVC Function
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MRS R4,PSP ; Read PSP
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STMIA R4!,{R0-R3} ; Function return values
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SVC_Done
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POP {R4,PC} ; RETI
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ALIGN
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}
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/*-------------------------- PendSV_Handler ---------------------------------*/
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__asm void PendSV_Handler (void) {
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PRESERVE8
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BL __cpp(rt_pop_req)
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Sys_Switch
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LDR R3,=__cpp(&os_tsk)
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LDMIA R3!,{R1,R2} ; os_tsk.run, os_tsk.new
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CMP R1,R2
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BEQ Sys_Exit ; no task switch
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SUBS R3,#8
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MRS R0,PSP ; Read PSP
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SUBS R0,R0,#32 ; Adjust Start Address
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STR R0,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack
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STMIA R0!,{R4-R7} ; Save old context (R4-R7)
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MOV R4,R8
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MOV R5,R9
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MOV R6,R10
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MOV R7,R11
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STMIA R0!,{R4-R7} ; Save old context (R8-R11)
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PUSH {R2,R3}
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BL rt_stk_check ; Check for Stack overflow
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POP {R2,R3}
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STR R2,[R3] ; os_tsk.run = os_tsk.new
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LDR R0,[R2,#TCB_TSTACK] ; os_tsk.new->tsk_stack
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ADDS R0,R0,#16 ; Adjust Start Address
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LDMIA R0!,{R4-R7} ; Restore new Context (R8-R11)
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MOV R8,R4
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MOV R9,R5
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MOV R10,R6
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MOV R11,R7
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MSR PSP,R0 ; Write PSP
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SUBS R0,R0,#32 ; Adjust Start Address
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LDMIA R0!,{R4-R7} ; Restore new Context (R4-R7)
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Sys_Exit
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MOVS R0,#:NOT:0xFFFFFFFD ; Set EXC_RETURN value
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MVNS R0,R0
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BX R0 ; RETI to Thread Mode, use PSP
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ALIGN
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}
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/*-------------------------- SysTick_Handler --------------------------------*/
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__asm void SysTick_Handler (void) {
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PRESERVE8
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BL __cpp(rt_systick)
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B Sys_Switch
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ALIGN
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}
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/*-------------------------- OS_Tick_Handler --------------------------------*/
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__asm void OS_Tick_Handler (void) {
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PRESERVE8
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BL __cpp(os_tick_irqack)
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BL __cpp(rt_systick)
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B Sys_Switch
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ALIGN
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}
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/*----------------------------------------------------------------------------
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* end of file
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*---------------------------------------------------------------------------*/
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@ -0,0 +1,57 @@
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;/*----------------------------------------------------------------------------
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; * RL-ARM - RTX
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; *----------------------------------------------------------------------------
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; * Name: SVC_TABLE.S
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; * Purpose: Pre-defined SVC Table for Cortex-M
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; * Rev.: V4.60
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; *----------------------------------------------------------------------------
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; *
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; * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
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; * All rights reserved.
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; * Redistribution and use in source and binary forms, with or without
|
||||||
|
; * modification, are permitted provided that the following conditions are met:
|
||||||
|
; * - Redistributions of source code must retain the above copyright
|
||||||
|
; * notice, this list of conditions and the following disclaimer.
|
||||||
|
; * - Redistributions in binary form must reproduce the above copyright
|
||||||
|
; * notice, this list of conditions and the following disclaimer in the
|
||||||
|
; * documentation and/or other materials provided with the distribution.
|
||||||
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; * - Neither the name of ARM nor the names of its contributors may be used
|
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; * to endorse or promote products derived from this software without
|
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; * specific prior written permission.
|
||||||
|
; *
|
||||||
|
; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
; * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
; * POSSIBILITY OF SUCH DAMAGE.
|
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; *---------------------------------------------------------------------------*/
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AREA SVC_TABLE, CODE, READONLY
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EXPORT SVC_Count
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SVC_Cnt EQU (SVC_End-SVC_Table)/4
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SVC_Count DCD SVC_Cnt
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; Import user SVC functions here.
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; IMPORT __SVC_1
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EXPORT SVC_Table
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SVC_Table
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; Insert user SVC functions here. SVC 0 used by RTL Kernel.
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; DCD __SVC_1 ; user SVC function
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SVC_End
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END
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/*----------------------------------------------------------------------------
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* end of file
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*---------------------------------------------------------------------------*/
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@ -207,6 +207,9 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL}
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#elif TARGET_LPC11U24
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#elif TARGET_LPC11U24
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#define INITIAL_SP (0x10001000UL)
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#define INITIAL_SP (0x10001000UL)
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#elif TARGET_KL25Z
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#define INITIAL_SP (0x20003000UL)
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#endif
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#endif
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extern unsigned char Image$$RW_IRAM1$$ZI$$Limit[];
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extern unsigned char Image$$RW_IRAM1$$ZI$$Limit[];
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@ -51,7 +51,7 @@
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#ifndef OS_TASKCNT
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#ifndef OS_TASKCNT
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# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
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# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
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# define OS_TASKCNT 14
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# define OS_TASKCNT 14
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# elif defined(TARGET_LPC11U24)
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# elif defined(TARGET_LPC11U24) || defined(TARGET_KL25Z)
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# define OS_TASKCNT 6
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# define OS_TASKCNT 6
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# endif
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# endif
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#endif
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#endif
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@ -60,7 +60,7 @@
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#ifndef OS_SCHEDULERSTKSIZE
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#ifndef OS_SCHEDULERSTKSIZE
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# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
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# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
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# define OS_SCHEDULERSTKSIZE 256
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# define OS_SCHEDULERSTKSIZE 256
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# elif defined(TARGET_LPC11U24)
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# elif defined(TARGET_LPC11U24) || defined(TARGET_KL25Z)
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# define OS_SCHEDULERSTKSIZE 128
|
# define OS_SCHEDULERSTKSIZE 128
|
||||||
# endif
|
# endif
|
||||||
#endif
|
#endif
|
||||||
|
|
@ -103,7 +103,8 @@
|
||||||
#ifndef OS_CLOCK
|
#ifndef OS_CLOCK
|
||||||
# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
|
# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
|
||||||
# define OS_CLOCK 96000000
|
# define OS_CLOCK 96000000
|
||||||
# elif defined(TARGET_LPC11U24)
|
|
||||||
|
# elif defined(TARGET_LPC11U24) || defined(TARGET_KL25Z)
|
||||||
# define OS_CLOCK 48000000
|
# define OS_CLOCK 48000000
|
||||||
# endif
|
# endif
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -40,6 +40,8 @@
|
||||||
#include "core_cm3.h"
|
#include "core_cm3.h"
|
||||||
#elif defined (__CORTEX_M0)
|
#elif defined (__CORTEX_M0)
|
||||||
#include "core_cm0.h"
|
#include "core_cm0.h"
|
||||||
|
#elif defined (__CORTEX_M0PLUS)
|
||||||
|
#include "core_cm0plus.h"
|
||||||
#else
|
#else
|
||||||
#error "Missing __CORTEX_Mx definition"
|
#error "Missing __CORTEX_Mx definition"
|
||||||
#endif
|
#endif
|
||||||
|
|
@ -192,7 +194,7 @@ typedef uint32_t __attribute__((vector_size(16))) ret128;
|
||||||
SVC_ArgR(2,t3,a3) \
|
SVC_ArgR(2,t3,a3) \
|
||||||
SVC_ArgR(3,t4,a4)
|
SVC_ArgR(3,t4,a4)
|
||||||
|
|
||||||
#if (defined (__CORTEX_M0))
|
#if (defined (__CORTEX_M0)) || defined (__CORTEX_M0PLUS)
|
||||||
#define SVC_Call(f) \
|
#define SVC_Call(f) \
|
||||||
__asm volatile \
|
__asm volatile \
|
||||||
( \
|
( \
|
||||||
|
|
|
||||||
|
|
@ -50,7 +50,7 @@
|
||||||
|
|
||||||
#undef __USE_EXCLUSIVE_ACCESS
|
#undef __USE_EXCLUSIVE_ACCESS
|
||||||
|
|
||||||
#if defined (__CORTEX_M0)
|
#if defined (__CORTEX_M0) || defined (__CORTEX_M0PLUS)
|
||||||
#define __TARGET_ARCH_6S_M 1
|
#define __TARGET_ARCH_6S_M 1
|
||||||
#else
|
#else
|
||||||
#define __TARGET_ARCH_6S_M 0
|
#define __TARGET_ARCH_6S_M 0
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue