mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #9126 from fluidblue/master
Fix multiple definitions of '__aeabi_atexit'pull/9155/head
Cruz Monrreal
GitHub
commit
15765d6286
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@ -168,6 +168,4 @@ AFTER_VECTORS void DebugMon_Handler (void) {}
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||||||
AFTER_VECTORS void PendSV_Handler (void) {}
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AFTER_VECTORS void PendSV_Handler (void) {}
|
||||||
AFTER_VECTORS void SysTick_Handler (void) {}
|
AFTER_VECTORS void SysTick_Handler (void) {}
|
||||||
AFTER_VECTORS void IntDefaultHandler (void) {}
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AFTER_VECTORS void IntDefaultHandler (void) {}
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||||||
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||||||
int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;}
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}
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}
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||||||
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@ -1,237 +0,0 @@
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/*Based on following file*/
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/*
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* GENERATED FILE - DO NOT EDIT
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|
||||||
* (c) Code Red Technologies Ltd, 2008-13
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||||||
* (c) NXP Semiconductors 2013-2014
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|
||||||
* Generated linker script file for LPC11U68
|
|
||||||
* Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))
|
|
||||||
* By LPCXpresso v7.2.0 [Build 153] [2014-05-19] on Sat Jun 14 15:26:54 JST 2014
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|
||||||
*/
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|
||||||
GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
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||||||
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|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
/* Define each memory region */
|
|
||||||
MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes */
|
|
||||||
Ram0_32 (rwx) : ORIGIN = 0x10000000+0x100, LENGTH = 0x8000-0x100 /* 32K bytes */
|
|
||||||
Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes */
|
|
||||||
Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes */
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|
||||||
|
|
||||||
|
|
||||||
}
|
|
||||||
/* Define a symbol for the top of each memory region */
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|
||||||
__top_MFlash256 = 0x0 + 0x40000;
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|
||||||
__top_Ram0_32 = 0x10000000+0x100 + 0x8000-0x100;
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|
||||||
__top_Ram1_2 = 0x20000000 + 0x800;
|
|
||||||
__top_Ram2USB_2 = 0x20004000 + 0x800;
|
|
||||||
|
|
||||||
ENTRY(ResetISR)
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|
||||||
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
|
|
||||||
/* MAIN TEXT SECTION */
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|
||||||
.text : ALIGN(8)
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|
||||||
{
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|
||||||
FILL(0xff)
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|
||||||
KEEP(*(.isr_vector))
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||||||
*(.text.ResetISR)
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|
||||||
*(.text.SystemInit)
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||||||
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|
||||||
/* Global Section Table */
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|
||||||
. = ALIGN(8) ;
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|
||||||
__section_table_start = .;
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||||||
__data_section_table = .;
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|
||||||
LONG(LOADADDR(.data));
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|
||||||
LONG( ADDR(.data));
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|
||||||
LONG( SIZEOF(.data));
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|
||||||
LONG(LOADADDR(.data_RAM2));
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|
||||||
LONG( ADDR(.data_RAM2));
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|
||||||
LONG( SIZEOF(.data_RAM2));
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|
||||||
LONG(LOADADDR(.data_RAM3));
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|
||||||
LONG( ADDR(.data_RAM3));
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|
||||||
LONG( SIZEOF(.data_RAM3));
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|
||||||
__data_section_table_end = .;
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|
||||||
__bss_section_table = .;
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|
||||||
LONG( ADDR(.bss));
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|
||||||
LONG( SIZEOF(.bss));
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|
||||||
LONG( ADDR(.bss_RAM2));
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|
||||||
LONG( SIZEOF(.bss_RAM2));
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|
||||||
LONG( ADDR(.bss_RAM3));
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|
||||||
LONG( SIZEOF(.bss_RAM3));
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|
||||||
__bss_section_table_end = .;
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|
||||||
__section_table_end = . ;
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|
||||||
/* End of Global Section Table */
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|
||||||
|
|
||||||
|
|
||||||
*(.after_vectors*)
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|
||||||
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||||||
*(.text*)
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|
||||||
*(.rodata .rodata.*)
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||||||
. = ALIGN(8);
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||||||
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||||||
/* C++ constructors etc */
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||||||
. = ALIGN(8);
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||||||
KEEP(*(.init))
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||||||
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|
||||||
. = ALIGN(8);
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|
||||||
__preinit_array_start = .;
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|
||||||
KEEP (*(.preinit_array))
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|
||||||
__preinit_array_end = .;
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|
||||||
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|
||||||
. = ALIGN(8);
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|
||||||
__init_array_start = .;
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|
||||||
KEEP (*(SORT(.init_array.*)))
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|
||||||
KEEP (*(.init_array))
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|
||||||
__init_array_end = .;
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|
||||||
|
|
||||||
KEEP(*(.fini));
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|
||||||
|
|
||||||
. = ALIGN(0x4);
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|
||||||
KEEP (*crtbegin.o(.ctors))
|
|
||||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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|
||||||
KEEP (*(SORT(.ctors.*)))
|
|
||||||
KEEP (*crtend.o(.ctors))
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|
||||||
|
|
||||||
. = ALIGN(0x4);
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|
||||||
KEEP (*crtbegin.o(.dtors))
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|
||||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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|
||||||
KEEP (*(SORT(.dtors.*)))
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|
||||||
KEEP (*crtend.o(.dtors))
|
|
||||||
} > MFlash256
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|
||||||
|
|
||||||
/*
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|
||||||
* for exception handling/unwind - some Newlib functions (in common
|
|
||||||
* with C++ and STDC++) use this.
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|
||||||
*/
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|
||||||
.ARM.extab : ALIGN(8)
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|
||||||
{
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|
||||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
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|
||||||
} > MFlash256
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|
||||||
__exidx_start = .;
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|
||||||
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|
||||||
.ARM.exidx : ALIGN(8)
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|
||||||
{
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|
||||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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|
||||||
} > MFlash256
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|
||||||
__exidx_end = .;
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|
||||||
|
|
||||||
_etext = .;
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|
||||||
|
|
||||||
/* possible MTB section for Ram1_2 */
|
|
||||||
.mtb_buffer_RAM2 (NOLOAD) :
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|
||||||
{
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|
||||||
KEEP(*(.mtb.$RAM2*))
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||||||
KEEP(*(.mtb.$RAM1_2*))
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|
||||||
} > Ram1_2
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||||||
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|
||||||
/* DATA section for Ram1_2 */
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||||||
.data_RAM2 : ALIGN(8)
|
|
||||||
{
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||||||
FILL(0xff)
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|
||||||
*(.ramfunc.$RAM2)
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|
||||||
*(.ramfunc.$Ram1_2)
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|
||||||
*(.data.$RAM2*)
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|
||||||
*(.data.$Ram1_2*)
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|
||||||
. = ALIGN(8) ;
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|
||||||
} > Ram1_2 AT>MFlash256
|
|
||||||
/* possible MTB section for Ram2USB_2 */
|
|
||||||
.mtb_buffer_RAM3 (NOLOAD) :
|
|
||||||
{
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|
||||||
KEEP(*(.mtb.$RAM3*))
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|
||||||
KEEP(*(.mtb.$RAM2USB_2*))
|
|
||||||
} > Ram2USB_2
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|
||||||
|
|
||||||
/* DATA section for Ram2USB_2 */
|
|
||||||
.data_RAM3 : ALIGN(8)
|
|
||||||
{
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|
||||||
FILL(0xff)
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|
||||||
*(.ramfunc.$RAM3)
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|
||||||
*(.ramfunc.$Ram2USB_2)
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|
||||||
*(.data.$RAM3*)
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|
||||||
*(.data.$Ram2USB_2*)
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|
||||||
. = ALIGN(8) ;
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|
||||||
} > Ram2USB_2 AT>MFlash256
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|
||||||
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|
||||||
/* MAIN DATA SECTION */
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|
||||||
|
|
||||||
/* Default MTB section */
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|
||||||
.mtb_buffer_default (NOLOAD) :
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||||||
{
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|
||||||
KEEP(*(.mtb*))
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|
||||||
} > Ram0_32
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|
||||||
|
|
||||||
.uninit_RESERVED : ALIGN(8)
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|
||||||
{
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|
||||||
KEEP(*(.bss.$RESERVED*))
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|
||||||
. = ALIGN(8) ;
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|
||||||
_end_uninit_RESERVED = .;
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|
||||||
} > Ram0_32
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|
||||||
|
|
||||||
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|
||||||
/* Main DATA section (Ram0_32) */
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|
||||||
.data : ALIGN(8)
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|
||||||
{
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|
||||||
FILL(0xff)
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|
||||||
_data = . ;
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|
||||||
*(vtable)
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|
||||||
*(.ramfunc*)
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|
||||||
*(.data*)
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|
||||||
. = ALIGN(8) ;
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|
||||||
_edata = . ;
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|
||||||
} > Ram0_32 AT>MFlash256
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|
||||||
|
|
||||||
/* BSS section for Ram1_2 */
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|
||||||
.bss_RAM2 : ALIGN(8)
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|
||||||
{
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||||||
*(.bss.$RAM2*)
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|
||||||
*(.bss.$Ram1_2*)
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|
||||||
. = ALIGN(8) ;
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|
||||||
} > Ram1_2
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||||||
/* BSS section for Ram2USB_2 */
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||||||
.bss_RAM3 : ALIGN(8)
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|
||||||
{
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|
||||||
*(.bss.$RAM3*)
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||||||
*(.bss.$Ram2USB_2*)
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|
||||||
. = ALIGN(8) ;
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|
||||||
} > Ram2USB_2
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|
||||||
|
|
||||||
/* MAIN BSS SECTION */
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|
||||||
.bss : ALIGN(8)
|
|
||||||
{
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|
||||||
_bss = .;
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|
||||||
*(.bss*)
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|
||||||
*(COMMON)
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|
||||||
. = ALIGN(8) ;
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|
||||||
_ebss = .;
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|
||||||
PROVIDE(end = .);
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|
||||||
__end__ = .;
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|
||||||
} > Ram0_32
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|
||||||
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|
||||||
/* NOINIT section for Ram1_2 */
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|
||||||
.noinit_RAM2 (NOLOAD) : ALIGN(8)
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|
||||||
{
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|
||||||
*(.noinit.$RAM2*)
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|
||||||
*(.noinit.$Ram1_2*)
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|
||||||
. = ALIGN(8) ;
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|
||||||
} > Ram1_2
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|
||||||
/* NOINIT section for Ram2USB_2 */
|
|
||||||
.noinit_RAM3 (NOLOAD) : ALIGN(8)
|
|
||||||
{
|
|
||||||
*(.noinit.$RAM3*)
|
|
||||||
*(.noinit.$Ram2USB_2*)
|
|
||||||
. = ALIGN(8) ;
|
|
||||||
} > Ram2USB_2
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|
||||||
|
|
||||||
/* DEFAULT NOINIT SECTION */
|
|
||||||
.noinit (NOLOAD): ALIGN(8)
|
|
||||||
{
|
|
||||||
_noinit = .;
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|
||||||
*(.noinit*)
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|
||||||
. = ALIGN(8) ;
|
|
||||||
_end_noinit = .;
|
|
||||||
} > Ram0_32
|
|
||||||
|
|
||||||
PROVIDE(_pvHeapStart = .);
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|
||||||
PROVIDE(_vStackTop = __top_Ram0_32 - 0);
|
|
||||||
}
|
|
||||||
|
|
@ -1,93 +0,0 @@
|
||||||
//*****************************************************************************
|
|
||||||
// aeabi_romdiv_patch.s
|
|
||||||
// - Provides "patch" versions of the aeabi integer divide functions to
|
|
||||||
// replace the standard ones pulled in from the C library, which vector
|
|
||||||
// integer divides onto the rom division functions contained in
|
|
||||||
// specific NXP MCUs such as LPC11Uxx and LPC12xx.
|
|
||||||
// - Note that this patching will only occur if "__USE_ROMDIVIDE" is
|
|
||||||
// defined for the project build for both the compiler and assembler.
|
|
||||||
//*****************************************************************************
|
|
||||||
//
|
|
||||||
// Copyright(C) NXP Semiconductors, 2013
|
|
||||||
// All rights reserved.
|
|
||||||
//
|
|
||||||
// Software that is described herein is for illustrative purposes only
|
|
||||||
// which provides customers with programming information regarding the
|
|
||||||
// LPC products. This software is supplied "AS IS" without any warranties of
|
|
||||||
// any kind, and NXP Semiconductors and its licensor disclaim any and
|
|
||||||
// all warranties, express or implied, including all implied warranties of
|
|
||||||
// merchantability, fitness for a particular purpose and non-infringement of
|
|
||||||
// intellectual property rights. NXP Semiconductors assumes no responsibility
|
|
||||||
// or liability for the use of the software, conveys no license or rights under any
|
|
||||||
// patent, copyright, mask work right, or any other intellectual property rights in
|
|
||||||
// or to any products. NXP Semiconductors reserves the right to make changes
|
|
||||||
// in the software without notification. NXP Semiconductors also makes no
|
|
||||||
// representation or warranty that such application will be suitable for the
|
|
||||||
// specified use without further testing or modification.
|
|
||||||
//
|
|
||||||
// Permission to use, copy, modify, and distribute this software and its
|
|
||||||
// documentation is hereby granted, under NXP Semiconductors' and its
|
|
||||||
// licensor's relevant copyrights in the software, without fee, provided that it
|
|
||||||
// is used in conjunction with NXP Semiconductors microcontrollers. This
|
|
||||||
// copyright, permission, and disclaimer notice must appear in all copies of
|
|
||||||
// this code.
|
|
||||||
//*****************************************************************************
|
|
||||||
#if defined(__USE_ROMDIVIDE)
|
|
||||||
|
|
||||||
// Note that the romdivide "divmod" functions are not actually called from
|
|
||||||
// the below code, as these functions are actually just wrappers to the
|
|
||||||
// main romdivide "div" functions which push the quotient and remainder onto
|
|
||||||
// the stack, so as to be compatible with the way that C returns structures.
|
|
||||||
//
|
|
||||||
// This is not needed for the aeabi "divmod" functions, as the compiler
|
|
||||||
// automatically generates code that handles the return values being passed
|
|
||||||
// back in registers when it generates inline calls to __aeabi_idivmod and
|
|
||||||
// __aeabi_uidivmod routines.
|
|
||||||
|
|
||||||
.syntax unified
|
|
||||||
.text
|
|
||||||
|
|
||||||
// ========= __aeabi_idiv & __aeabi_idivmod =========
|
|
||||||
.align 2
|
|
||||||
.section .text.__aeabi_idiv
|
|
||||||
|
|
||||||
.global __aeabi_idiv
|
|
||||||
.set __aeabi_idivmod, __aeabi_idiv // make __aeabi_uidivmod an alias
|
|
||||||
.global __aeabi_idivmod
|
|
||||||
.global pDivRom_idiv // pointer to the romdivide 'idiv' functione
|
|
||||||
.func
|
|
||||||
.thumb_func
|
|
||||||
.type __aeabi_idiv, %function
|
|
||||||
|
|
||||||
__aeabi_idiv:
|
|
||||||
push {r4, lr}
|
|
||||||
ldr r3, =pDivRom_idiv
|
|
||||||
ldr r3, [r3, #0] // Load address of function
|
|
||||||
blx r3 // Call divide function
|
|
||||||
pop {r4, pc}
|
|
||||||
|
|
||||||
.endfunc
|
|
||||||
|
|
||||||
// ======== __aeabi_uidiv & __aeabi_uidivmod ========
|
|
||||||
.align 2
|
|
||||||
|
|
||||||
.section .text.__aeabi_uidiv
|
|
||||||
|
|
||||||
.global __aeabi_uidiv
|
|
||||||
.set __aeabi_uidivmod, __aeabi_uidiv // make __aeabi_uidivmod an alias
|
|
||||||
.global __aeabi_uidivmod
|
|
||||||
.global pDivRom_uidiv // pointer to the romdivide 'uidiv' function
|
|
||||||
.func
|
|
||||||
.thumb_func
|
|
||||||
.type __aeabi_uidiv, %function
|
|
||||||
|
|
||||||
__aeabi_uidiv:
|
|
||||||
push {r4, lr}
|
|
||||||
ldr r3, =pDivRom_uidiv
|
|
||||||
ldr r3, [r3, #0] // Load address of function
|
|
||||||
blx r3 // Call divide function
|
|
||||||
pop {r4, pc}
|
|
||||||
|
|
||||||
.endfunc
|
|
||||||
|
|
||||||
#endif // (__USE_ROMDIVIDE)
|
|
||||||
|
|
@ -1,85 +0,0 @@
|
||||||
//*****************************************************************************
|
|
||||||
// +--+
|
|
||||||
// | ++----+
|
|
||||||
// +-++ |
|
|
||||||
// | |
|
|
||||||
// +-+--+ |
|
|
||||||
// | +--+--+
|
|
||||||
// +----+ Copyright (c) 2013 Code Red Technologies Ltd.
|
|
||||||
//
|
|
||||||
// mtb.c
|
|
||||||
//
|
|
||||||
// Optionally defines an array to be used as a buffer for Micro Trace
|
|
||||||
// Buffer (MTB) instruction trace on Cortex-M0+ parts
|
|
||||||
//
|
|
||||||
// Version : 130502
|
|
||||||
//
|
|
||||||
// Software License Agreement
|
|
||||||
//
|
|
||||||
// The software is owned by Code Red Technologies and/or its suppliers, and is
|
|
||||||
// protected under applicable copyright laws. All rights are reserved. Any
|
|
||||||
// use in violation of the foregoing restrictions may subject the user to criminal
|
|
||||||
// sanctions under applicable laws, as well as to civil liability for the breach
|
|
||||||
// of the terms and conditions of this license.
|
|
||||||
//
|
|
||||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
|
||||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
|
||||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
|
||||||
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
|
|
||||||
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
|
|
||||||
// CODE RED TECHNOLOGIES LTD.
|
|
||||||
//
|
|
||||||
//*****************************************************************************
|
|
||||||
|
|
||||||
/*******************************************************************
|
|
||||||
* Symbols controlling behavior of this code...
|
|
||||||
*
|
|
||||||
* __MTB_DISABLE
|
|
||||||
* If this symbol is defined, then the buffer array for the MTB
|
|
||||||
* will not be created.
|
|
||||||
*
|
|
||||||
* __MTB_BUFFER_SIZE
|
|
||||||
* Symbol specifying the sizer of the buffer array for the MTB.
|
|
||||||
* This must be a power of 2 in size, and fit into the available
|
|
||||||
* RAM. The MTB buffer will also be aligned to its 'size'
|
|
||||||
* boundary and be placed at the start of a RAM bank (which
|
|
||||||
* should ensure minimal or zero padding due to alignment).
|
|
||||||
*
|
|
||||||
* __MTB_RAM_BANK
|
|
||||||
* Allows MTB Buffer to be placed into specific RAM bank. When
|
|
||||||
* this is not defined, the "default" (first if there are
|
|
||||||
* several) RAM bank is used.
|
|
||||||
*******************************************************************/
|
|
||||||
|
|
||||||
// Ignore with none Code Red tools
|
|
||||||
#if defined (__CODE_RED)
|
|
||||||
|
|
||||||
// Allow MTB to be removed by setting a define (via command line)
|
|
||||||
#if !defined (__MTB_DISABLE)
|
|
||||||
|
|
||||||
// Allow for MTB buffer size being set by define set via command line
|
|
||||||
// Otherwise provide small default buffer
|
|
||||||
#if !defined (__MTB_BUFFER_SIZE)
|
|
||||||
#define __MTB_BUFFER_SIZE 128
|
|
||||||
#endif
|
|
||||||
|
|
||||||
// Check that buffer size requested is >0 bytes in size
|
|
||||||
#if (__MTB_BUFFER_SIZE > 0)
|
|
||||||
// Pull in MTB related macros
|
|
||||||
#include <cr_mtb_buffer.h>
|
|
||||||
|
|
||||||
// Check if MYTB buffer is to be placed in specific RAM bank
|
|
||||||
#if defined(__MTB_RAM_BANK)
|
|
||||||
// Place MTB buffer into explicit bank of RAM
|
|
||||||
__CR_MTB_BUFFER_EXT(__MTB_BUFFER_SIZE,__MTB_RAM_BANK);
|
|
||||||
#else
|
|
||||||
// Place MTB buffer into 'default' bank of RAM
|
|
||||||
__CR_MTB_BUFFER(__MTB_BUFFER_SIZE);
|
|
||||||
|
|
||||||
#endif // defined(__MTB_RAM_BANK)
|
|
||||||
|
|
||||||
#endif // (__MTB_BUFFER_SIZE > 0)
|
|
||||||
|
|
||||||
#endif // !defined (__MTB_DISABLE)
|
|
||||||
|
|
||||||
#endif // defined (__CODE_RED)
|
|
||||||
|
|
@ -1,195 +0,0 @@
|
||||||
extern "C" {
|
|
||||||
|
|
||||||
#include "LPC11U6x.h"
|
|
||||||
#define WEAK __attribute__ ((weak))
|
|
||||||
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
|
|
||||||
#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))void ResetISR(void);
|
|
||||||
|
|
||||||
// Patch the AEABI integer divide functions to use MCU's romdivide library
|
|
||||||
#ifdef __USE_ROMDIVIDE
|
|
||||||
// Location in memory that holds the address of the ROM Driver table
|
|
||||||
#define PTR_ROM_DRIVER_TABLE ((unsigned int *)(0x1FFF1FF8))
|
|
||||||
// Variables to store addresses of idiv and udiv functions within MCU ROM
|
|
||||||
unsigned int *pDivRom_idiv;
|
|
||||||
unsigned int *pDivRom_uidiv;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
extern unsigned int __data_section_table;
|
|
||||||
extern unsigned int __data_section_table_end;
|
|
||||||
extern unsigned int __bss_section_table;
|
|
||||||
extern unsigned int __bss_section_table_end;
|
|
||||||
|
|
||||||
|
|
||||||
extern void __libc_init_array(void);
|
|
||||||
extern int main(void);
|
|
||||||
extern void _vStackTop(void);
|
|
||||||
extern void (* const g_pfnVectors[])(void);
|
|
||||||
|
|
||||||
void ResetISR(void);
|
|
||||||
WEAK void NMI_Handler(void);
|
|
||||||
WEAK void HardFault_Handler(void);
|
|
||||||
WEAK void SVC_Handler(void);
|
|
||||||
WEAK void PendSV_Handler(void);
|
|
||||||
WEAK void SysTick_Handler(void);
|
|
||||||
WEAK void IntDefaultHandler(void);
|
|
||||||
|
|
||||||
void PIN_INT0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void PIN_INT1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void PIN_INT2_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void PIN_INT3_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void PIN_INT4_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void PIN_INT5_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void PIN_INT6_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void PIN_INT7_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void GINT0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void GINT1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void I2C1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void USART1_4_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void USART2_3_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void SCT0_1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void I2C0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void TIMER16_0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void TIMER16_1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void TIMER32_0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void TIMER32_1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void USART0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void USB_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void USB_FIQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void ADCA_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void RTC_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void BOD_WDT_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void FMC_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void DMA_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void ADCB_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
void USBWakeup_IRQHandler (void) ALIAS(IntDefaultHandler);
|
|
||||||
|
|
||||||
__attribute__ ((section(".isr_vector")))
|
|
||||||
void (* const g_pfnVectors[])(void) = {
|
|
||||||
// Core Level - CM0
|
|
||||||
&_vStackTop, // The initial stack pointer
|
|
||||||
ResetISR, // The reset handler
|
|
||||||
NMI_Handler, // The NMI handler
|
|
||||||
HardFault_Handler, // The hard fault handler
|
|
||||||
0, // Reserved
|
|
||||||
0, // Reserved
|
|
||||||
0, // Reserved
|
|
||||||
0, // Reserved
|
|
||||||
0, // Reserved
|
|
||||||
0, // Reserved
|
|
||||||
0, // Reserved
|
|
||||||
SVC_Handler, // SVCall handler
|
|
||||||
0, // Reserved
|
|
||||||
0, // Reserved
|
|
||||||
PendSV_Handler, // The PendSV handler
|
|
||||||
SysTick_Handler, // The SysTick handler
|
|
||||||
|
|
||||||
// Chip Level - LPC11U68
|
|
||||||
PIN_INT0_IRQHandler, // 0 - GPIO pin interrupt 0
|
|
||||||
PIN_INT1_IRQHandler, // 1 - GPIO pin interrupt 1
|
|
||||||
PIN_INT2_IRQHandler, // 2 - GPIO pin interrupt 2
|
|
||||||
PIN_INT3_IRQHandler, // 3 - GPIO pin interrupt 3
|
|
||||||
PIN_INT4_IRQHandler, // 4 - GPIO pin interrupt 4
|
|
||||||
PIN_INT5_IRQHandler, // 5 - GPIO pin interrupt 5
|
|
||||||
PIN_INT6_IRQHandler, // 6 - GPIO pin interrupt 6
|
|
||||||
PIN_INT7_IRQHandler, // 7 - GPIO pin interrupt 7
|
|
||||||
GINT0_IRQHandler, // 8 - GPIO GROUP0 interrupt
|
|
||||||
GINT1_IRQHandler, // 9 - GPIO GROUP1 interrupt
|
|
||||||
I2C1_IRQHandler, // 10 - I2C1
|
|
||||||
USART1_4_IRQHandler, // 11 - combined USART1 & 4 interrupt
|
|
||||||
USART2_3_IRQHandler, // 12 - combined USART2 & 3 interrupt
|
|
||||||
SCT0_1_IRQHandler, // 13 - combined SCT0 and 1 interrupt
|
|
||||||
SSP1_IRQHandler, // 14 - SPI/SSP1 Interrupt
|
|
||||||
I2C0_IRQHandler, // 15 - I2C0
|
|
||||||
TIMER16_0_IRQHandler, // 16 - CT16B0 (16-bit Timer 0)
|
|
||||||
TIMER16_1_IRQHandler, // 17 - CT16B1 (16-bit Timer 1)
|
|
||||||
TIMER32_0_IRQHandler, // 18 - CT32B0 (32-bit Timer 0)
|
|
||||||
TIMER32_1_IRQHandler, // 19 - CT32B1 (32-bit Timer 1)
|
|
||||||
SSP0_IRQHandler, // 20 - SPI/SSP0 Interrupt
|
|
||||||
USART0_IRQHandler, // 21 - USART0
|
|
||||||
USB_IRQHandler, // 22 - USB IRQ
|
|
||||||
USB_FIQHandler, // 23 - USB FIQ
|
|
||||||
ADCA_IRQHandler, // 24 - ADC A(A/D Converter)
|
|
||||||
RTC_IRQHandler, // 25 - Real Time CLock interrpt
|
|
||||||
BOD_WDT_IRQHandler, // 25 - Combined Brownout/Watchdog interrupt
|
|
||||||
FMC_IRQHandler, // 27 - IP2111 Flash Memory Controller
|
|
||||||
DMA_IRQHandler, // 28 - DMA interrupt
|
|
||||||
ADCB_IRQHandler, // 24 - ADC B (A/D Converter)
|
|
||||||
USBWakeup_IRQHandler, // 30 - USB wake-up interrupt
|
|
||||||
0, // 31 - Reserved
|
|
||||||
};
|
|
||||||
/* End Vector */
|
|
||||||
|
|
||||||
AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
|
|
||||||
unsigned int *pulDest = (unsigned int*) start;
|
|
||||||
unsigned int *pulSrc = (unsigned int*) romstart;
|
|
||||||
unsigned int loop;
|
|
||||||
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
|
|
||||||
}
|
|
||||||
|
|
||||||
AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
|
|
||||||
unsigned int *pulDest = (unsigned int*) start;
|
|
||||||
unsigned int loop;
|
|
||||||
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/* Reset entry point*/
|
|
||||||
extern "C" void software_init_hook(void);
|
|
||||||
extern "C" void pre_main(void) __attribute__((weak));
|
|
||||||
|
|
||||||
AFTER_VECTORS void ResetISR(void) {
|
|
||||||
unsigned int LoadAddr, ExeAddr, SectionLen;
|
|
||||||
unsigned int *SectionTableAddr;
|
|
||||||
|
|
||||||
SectionTableAddr = &__data_section_table;
|
|
||||||
|
|
||||||
while (SectionTableAddr < &__data_section_table_end) {
|
|
||||||
LoadAddr = *SectionTableAddr++;
|
|
||||||
ExeAddr = *SectionTableAddr++;
|
|
||||||
SectionLen = *SectionTableAddr++;
|
|
||||||
data_init(LoadAddr, ExeAddr, SectionLen);
|
|
||||||
}
|
|
||||||
while (SectionTableAddr < &__bss_section_table_end) {
|
|
||||||
ExeAddr = *SectionTableAddr++;
|
|
||||||
SectionLen = *SectionTableAddr++;
|
|
||||||
bss_init(ExeAddr, SectionLen);
|
|
||||||
}
|
|
||||||
|
|
||||||
// Patch the AEABI integer divide functions to use MCU's romdivide library
|
|
||||||
#ifdef __USE_ROMDIVIDE
|
|
||||||
// Get address of Integer division routines function table in ROM
|
|
||||||
unsigned int *div_ptr = (unsigned int *)((unsigned int *)*(PTR_ROM_DRIVER_TABLE))[4];
|
|
||||||
// Get addresses of integer divide routines in ROM
|
|
||||||
// These address are then used by the code in aeabi_romdiv_patch.s
|
|
||||||
pDivRom_idiv = (unsigned int *)div_ptr[0];
|
|
||||||
pDivRom_uidiv = (unsigned int *)div_ptr[1];
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
SystemInit();
|
|
||||||
if (pre_main) { // give control to the RTOS
|
|
||||||
software_init_hook(); // this will also call __libc_init_array
|
|
||||||
}
|
|
||||||
else { // for BareMetal (non-RTOS) build
|
|
||||||
__libc_init_array();
|
|
||||||
main();
|
|
||||||
}
|
|
||||||
while (1) {;}
|
|
||||||
}
|
|
||||||
|
|
||||||
AFTER_VECTORS void NMI_Handler (void) {}
|
|
||||||
AFTER_VECTORS void HardFault_Handler (void) {}
|
|
||||||
AFTER_VECTORS void MemManage_Handler (void) {}
|
|
||||||
AFTER_VECTORS void BusFault_Handler (void) {}
|
|
||||||
AFTER_VECTORS void UsageFault_Handler(void) {}
|
|
||||||
AFTER_VECTORS void SVC_Handler (void) {}
|
|
||||||
AFTER_VECTORS void DebugMon_Handler (void) {}
|
|
||||||
AFTER_VECTORS void PendSV_Handler (void) {}
|
|
||||||
AFTER_VECTORS void SysTick_Handler (void) {}
|
|
||||||
AFTER_VECTORS void IntDefaultHandler (void) {}
|
|
||||||
|
|
||||||
int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;}
|
|
||||||
}
|
|
||||||
Loading…
Reference in New Issue