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Merge pull request #10619 from jamesbeyond/fm-iap 

Fastmodel: enable flashIAP and kvstore
pull/10948/head
Martin Kojtal 2019-07-02 14:23:00 +01:00 committed by GitHub
parent 3ef8d1bff6 81c96a785d
commit 149d53cc89
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
27 changed files with 139 additions and 167 deletions
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4
components/storage/blockdevice/COMPONENT_FLASHIAP/mbed_lib.json
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@ -14,6 +14,10 @@
"REALTEK_RTL8195AM": { "REALTEK_RTL8195AM": {
"base-address": "0x1C0000", "base-address": "0x1C0000",
"size": "0x40000" "size": "0x40000"
},
"FVP_MPS2": {
"base-address": "0x00200000",
"size": "0x200000"
} }
} }
} }

4
features/storage/TESTS/kvstore/filesystemstore_tests/main.cpp
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@ -27,8 +27,8 @@
#include "utest.h" #include "utest.h"
#include <stdlib.h> #include <stdlib.h>
#if !defined(TARGET_K64F) #if !defined(TARGET_K64F) && !defined(TARGET_ARM_FM)
#error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices #error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices and Fastmodels
#endif #endif
#define FSST_TEST_NUM_OF_THREADS 5 #define FSST_TEST_NUM_OF_THREADS 5

4
features/storage/TESTS/kvstore/general_tests_phase_1/main.cpp
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@ -29,8 +29,8 @@
using namespace utest::v1; using namespace utest::v1;
using namespace mbed; using namespace mbed;
#if !defined(TARGET_K64F) #if !defined(TARGET_K64F) && !defined(TARGET_ARM_FM)
#error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices #error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices and Fastmodels
#endif #endif
static const char data[] = "data"; static const char data[] = "data";

4
features/storage/TESTS/kvstore/general_tests_phase_2/main.cpp
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@ -29,8 +29,8 @@
using namespace utest::v1; using namespace utest::v1;
using namespace mbed; using namespace mbed;
#if !defined(TARGET_K64F) #if !defined(TARGET_K64F) && !defined(TARGET_ARM_FM)
#error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices #error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices and Fastmodels
#endif #endif
static const char data[] = "data"; static const char data[] = "data";

4
features/storage/TESTS/kvstore/securestore_whitebox/main.cpp
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@ -34,8 +34,8 @@
#include <stdio.h> #include <stdio.h>
#include <algorithm> #include <algorithm>
#if !defined(TARGET_K64F) #if !defined(TARGET_K64F) && !defined(TARGET_ARM_FM)
#error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices #error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices and Fastmodels
#endif #endif
#if !SECURESTORE_ENABLED #if !SECURESTORE_ENABLED

4
features/storage/kvstore/conf/tdb_internal/mbed_lib.json
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@ -22,6 +22,10 @@
"ARM_MUSCA_A1_S": { "ARM_MUSCA_A1_S": {
"internal_size": "0x8000", "internal_size": "0x8000",
"internal_base_address": "0x00420000" "internal_base_address": "0x00420000"
},
"FVP_MPS2": {
"internal_size": "0x200000",
"internal_base_address": "0x00200000"
} }
} }
} }

20
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct
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@ -1,8 +1,9 @@
#! armcc -E #! armcc -E
;* MPS2 CMSIS Library ;* MPS2 CMSIS Library
;* ;*
;* Copyright (c) 2006-2018 ARM Limited ;* Copyright (c) 2006-2019 ARM Limited
;* All rights reserved. ;* All rights reserved.
;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Redistribution and use in source and binary forms, with or without ;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions are met: ;* modification, are permitted provided that the following conditions are met:
@ -37,26 +38,25 @@
#include "../memory_zones.h" #include "../memory_zones.h"
#include "../cmsis_nvic.h" #include "../cmsis_nvic.h"
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#if (defined(__stack_size__)) #if (defined(__stack_size__))
#define STACK_SIZE __stack_size__ #define STACK_SIZE __stack_size__
#else #else
#define STACK_SIZE 0x0400 #define STACK_SIZE MBED_BOOT_STACK_SIZE
#endif #endif
; The vector table is loaded at address 0x00000000 in Flash memory region. ; The vector table is loaded at address 0x00000000 in Flash memory region.
LR_IROM1 MAPPABLE_START MAPPABLE_SIZE { LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM1 MAPPABLE_START MAPPABLE_SIZE { ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*.o (RESET, +First) *.o (RESET, +First)
}
}
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*(InRoot$$Sections) *(InRoot$$Sections)
*(+RO) *(+RO)
} }
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE) { ; RW data RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
*(+RW +ZI) *(+RW +ZI)
} }
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down

7
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_GCC_ARM/MPS2.ld
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@ -2,7 +2,7 @@
* MPS2 CMSIS Library * MPS2 CMSIS Library
*/ */
/* /*
* Copyright (c) 2009-2018 ARM Limited. All rights reserved. * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -21,7 +21,7 @@
/* /*
* This file is derivative of CMSIS V5.00 gcc_arm.ld * This file is derivative of CMSIS V5.00 gcc_arm.ld
*/ */
/* Linker script for mbed FVP Cortex-M0 on MPS2 */ /* Linker script for mbed FVP Cortex-M on MPS2 */
/* Linker script to configure memory regions. */ /* Linker script to configure memory regions. */
/* The length of the VECTORS region is a bit larger than /* The length of the VECTORS region is a bit larger than
@ -37,7 +37,6 @@
MEMORY MEMORY
{ {
VECTORS (rx) : ORIGIN = MAPPABLE_START, LENGTH = MAPPABLE_SIZE
FLASH (rx) : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE FLASH (rx) : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE
RAM (rwx) : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE RAM (rwx) : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE
} }
@ -82,7 +81,7 @@ SECTIONS
__vector_table = .; __vector_table = .;
KEEP(*(.vector_table)) KEEP(*(.vector_table))
. = ALIGN(8); . = ALIGN(8);
} > VECTORS } > FLASH
.text : .text :
{ {

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_IAR/MPS2.icf
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@ -2,7 +2,7 @@
* MPS2 CMSIS Library * MPS2 CMSIS Library
*/ */
/* /*
* Copyright (c) 2009-2018 ARM Limited. All rights reserved. * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -24,21 +24,19 @@
* can not be included here. Please make sure that the two definitions match. * can not be included here. Please make sure that the two definitions match.
*/ */
/* Code memory zones */ /* Code memory zones */
define symbol MAPPABLE_START = 0x00000000; define symbol ZBT_SRAM1_START = 0x00000000;
define symbol MAPPABLE_SIZE = 0x00004000; /* 16 KiB */ define symbol ZBT_SRAM1_SIZE = 0x00400000; /* 4 MiB */
define symbol ZBT_SRAM1_START = (0x00000000 + 0x00004000);
define symbol ZBT_SRAM1_SIZE = (0x00400000 - 0x00004000); /* 4 MiB - 16 KiB */
/* Data memory zones */ /* Data memory zones */
define symbol ZBT_SRAM2_START = 0x20000000; define symbol ZBT_SRAM2_START = 0x20000000;
define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MB */ define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MiB */
/* NVIC vector numbers and size. */ /* NVIC vector numbers and size. */
define symbol NVIC_NUM_VECTORS = (16 + 48); define symbol NVIC_NUM_VECTORS = (16 + 48);
define symbol NVIC_VECTORS_SIZE = (NVIC_NUM_VECTORS * 4); define symbol NVIC_VECTORS_SIZE = (NVIC_NUM_VECTORS * 4);
/*-Specials-*/ /*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MAPPABLE_START; define symbol __ICFEDIT_intvec_start__ = ZBT_SRAM1_START;
/*-Memory Regions-*/ /*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = ZBT_SRAM1_START; define symbol __ICFEDIT_region_ROM_start__ = ZBT_SRAM1_START;

9
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/memory_zones.h
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@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2017-2018 ARM Limited * Copyright (c) 2017-2019 ARM Limited
* SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License Version 2.0 (the "License"); * Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License. * you may not use this file except in compliance with the License.
@ -37,10 +38,8 @@
* only to keep the same name than in the CMSDK RTL and Fast Models Reference * only to keep the same name than in the CMSDK RTL and Fast Models Reference
* Guide. * Guide.
*/ */
#define MAPPABLE_START 0x00000000 #define ZBT_SRAM1_START 0x00000000
#define MAPPABLE_SIZE 0x00004000 /* 16 KiB */ #define ZBT_SRAM1_SIZE 0x00400000 /* 4 MiB */
#define ZBT_SRAM1_START (0x00000000 + 0x00004000)
#define ZBT_SRAM1_SIZE (0x00400000 - 0x00004000) /* 4 MiB - 16 KiB*/
/* Data memory zones */ /* Data memory zones */
#define ZBT_SRAM2_START 0x20000000 #define ZBT_SRAM2_START 0x20000000

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct
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@ -1,8 +1,9 @@
#! armcc -E #! armcc -E
;* MPS2 CMSIS Library ;* MPS2 CMSIS Library
;* ;*
;* Copyright (c) 2006-2018 ARM Limited ;* Copyright (c) 2006-2019 ARM Limited
;* All rights reserved. ;* All rights reserved.
;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Redistribution and use in source and binary forms, with or without ;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions are met: ;* modification, are permitted provided that the following conditions are met:
@ -48,14 +49,9 @@
#endif #endif
; The vector table is loaded at address 0x00000000 in Flash memory region. ; The vector table is loaded at address 0x00000000 in Flash memory region.
LR_IROM1 MAPPABLE_START MAPPABLE_SIZE { LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM1 MAPPABLE_START MAPPABLE_SIZE { ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*.o (RESET, +First) *.o (RESET, +First)
}
}
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*(InRoot$$Sections) *(InRoot$$Sections)
*(+RO) *(+RO)
} }

15
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_GCC_ARM/MPS2.ld
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@ -2,7 +2,7 @@
* MPS2 CMSIS Library * MPS2 CMSIS Library
*/ */
/* /*
* Copyright (c) 2009-2018 ARM Limited. All rights reserved. * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -21,7 +21,7 @@
/* /*
* This file is derivative of CMSIS V5.00 gcc_arm.ld * This file is derivative of CMSIS V5.00 gcc_arm.ld
*/ */
/* Linker script for mbed FVP Cortex-M0-Plus on MPS2 */ /* Linker script for mbed FVP Cortex-M on MPS2 */
/* Linker script to configure memory regions. */ /* Linker script to configure memory regions. */
/* The length of the VECTORS region is a bit larger than /* The length of the VECTORS region is a bit larger than
@ -31,9 +31,12 @@
#include "../memory_zones.h" #include "../memory_zones.h"
#include "../cmsis_nvic.h" #include "../cmsis_nvic.h"
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
MEMORY MEMORY
{ {
VECTORS (rx) : ORIGIN = MAPPABLE_START, LENGTH = MAPPABLE_SIZE
FLASH (rx) : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE FLASH (rx) : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE
RAM (rwx) : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE RAM (rwx) : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE
} }
@ -66,10 +69,6 @@ MEMORY
*/ */
ENTRY(Reset_Handler) ENTRY(Reset_Handler)
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE; STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Size of the vector table in SRAM */ /* Size of the vector table in SRAM */
@ -82,7 +81,7 @@ SECTIONS
__vector_table = .; __vector_table = .;
KEEP(*(.vector_table)) KEEP(*(.vector_table))
. = ALIGN(8); . = ALIGN(8);
} > VECTORS } > FLASH
.text : .text :
{ {

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_IAR/MPS2.icf
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@ -2,7 +2,7 @@
* MPS2 CMSIS Library * MPS2 CMSIS Library
*/ */
/* /*
* Copyright (c) 2009-2018 ARM Limited. All rights reserved. * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -24,21 +24,19 @@
* can not be included here. Please make sure that the two definitions match. * can not be included here. Please make sure that the two definitions match.
*/ */
/* Code memory zones */ /* Code memory zones */
define symbol MAPPABLE_START = 0x00000000; define symbol ZBT_SRAM1_START = 0x00000000;
define symbol MAPPABLE_SIZE = 0x00004000; /* 16 KiB */ define symbol ZBT_SRAM1_SIZE = 0x00400000; /* 4 MiB */
define symbol ZBT_SRAM1_START = (0x00000000 + 0x00004000);
define symbol ZBT_SRAM1_SIZE = (0x00400000 - 0x00004000); /* 4 MiB - 16 KiB */
/* Data memory zones */ /* Data memory zones */
define symbol ZBT_SRAM2_START = 0x20000000; define symbol ZBT_SRAM2_START = 0x20000000;
define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MB */ define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MiB */
/* NVIC vector numbers and size. */ /* NVIC vector numbers and size. */
define symbol NVIC_NUM_VECTORS = (16 + 48); define symbol NVIC_NUM_VECTORS = (16 + 48);
define symbol NVIC_VECTORS_SIZE = (NVIC_NUM_VECTORS * 4); define symbol NVIC_VECTORS_SIZE = (NVIC_NUM_VECTORS * 4);
/*-Specials-*/ /*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MAPPABLE_START; define symbol __ICFEDIT_intvec_start__ = ZBT_SRAM1_START;
/*-Memory Regions-*/ /*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = ZBT_SRAM1_START; define symbol __ICFEDIT_region_ROM_start__ = ZBT_SRAM1_START;

9
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/memory_zones.h
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@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2017-2018 ARM Limited * Copyright (c) 2017-2019 ARM Limited
* SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License Version 2.0 (the "License"); * Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License. * you may not use this file except in compliance with the License.
@ -37,10 +38,8 @@
* only to keep the same name than in the CMSDK RTL and Fast Models Reference * only to keep the same name than in the CMSDK RTL and Fast Models Reference
* Guide. * Guide.
*/ */
#define MAPPABLE_START 0x00000000 #define ZBT_SRAM1_START 0x00000000
#define MAPPABLE_SIZE 0x00004000 /* 16 KiB */ #define ZBT_SRAM1_SIZE 0x00400000 /* 4 MiB */
#define ZBT_SRAM1_START (0x00000000 + 0x00004000)
#define ZBT_SRAM1_SIZE (0x00400000 - 0x00004000) /* 4 MiB - 16 KiB*/
/* Data memory zones */ /* Data memory zones */
#define ZBT_SRAM2_START 0x20000000 #define ZBT_SRAM2_START 0x20000000

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct
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@ -1,8 +1,9 @@
#! armcc -E #! armcc -E
;* MPS2 CMSIS Library ;* MPS2 CMSIS Library
;* ;*
;* Copyright (c) 2006-2018 ARM Limited ;* Copyright (c) 2006-2019 ARM Limited
;* All rights reserved. ;* All rights reserved.
;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Redistribution and use in source and binary forms, with or without ;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions are met: ;* modification, are permitted provided that the following conditions are met:
@ -48,14 +49,9 @@
#endif #endif
; The vector table is loaded at address 0x00000000 in Flash memory region. ; The vector table is loaded at address 0x00000000 in Flash memory region.
LR_IROM1 MAPPABLE_START MAPPABLE_SIZE { LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM1 MAPPABLE_START MAPPABLE_SIZE { ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*.o (RESET, +First) *.o (RESET, +First)
}
}
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*(InRoot$$Sections) *(InRoot$$Sections)
*(+RO) *(+RO)
} }

19
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_GCC_ARM/MPS2.ld
View File

@ -2,7 +2,7 @@
* MPS2 CMSIS Library * MPS2 CMSIS Library
*/ */
/* /*
* Copyright (c) 2009-2018 ARM Limited. All rights reserved. * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -21,19 +21,22 @@
/* /*
* This file is derivative of CMSIS V5.00 gcc_arm.ld * This file is derivative of CMSIS V5.00 gcc_arm.ld
*/ */
/* Linker script for mbed FVP Cortex-M3 on MPS2 */ /* Linker script for mbed FVP Cortex-M on MPS2 */
/* Linker script to configure memory regions. */ /* Linker script to configure memory regions. */
/* The length of the VECTORS region is a bit larger than /* The length of the VECTORS region is a bit larger than
* is necessary based on the number of exception handlers. * is necessary based on the number of exception handlers.
*/ */
#include "../memory_zones.h" #include "../memory_zones.h"
#include "../cmsis_nvic.h" #include "../cmsis_nvic.h"
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
MEMORY MEMORY
{ {
VECTORS (rx) : ORIGIN = MAPPABLE_START, LENGTH = MAPPABLE_SIZE
FLASH (rx) : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE FLASH (rx) : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE
RAM (rwx) : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE RAM (rwx) : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE
} }
@ -66,10 +69,6 @@ MEMORY
*/ */
ENTRY(Reset_Handler) ENTRY(Reset_Handler)
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE; STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Size of the vector table in SRAM */ /* Size of the vector table in SRAM */
@ -82,7 +81,7 @@ SECTIONS
__vector_table = .; __vector_table = .;
KEEP(*(.vector_table)) KEEP(*(.vector_table))
. = ALIGN(8); . = ALIGN(8);
} > VECTORS } > FLASH
.text : .text :
{ {

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_IAR/MPS2.icf
View File

@ -2,7 +2,7 @@
* MPS2 CMSIS Library * MPS2 CMSIS Library
*/ */
/* /*
* Copyright (c) 2009-2018 ARM Limited. All rights reserved. * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -24,21 +24,19 @@
* can not be included here. Please make sure that the two definitions match. * can not be included here. Please make sure that the two definitions match.
*/ */
/* Code memory zones */ /* Code memory zones */
define symbol MAPPABLE_START = 0x00000000; define symbol ZBT_SRAM1_START = 0x00000000;
define symbol MAPPABLE_SIZE = 0x00004000; /* 16 KiB */ define symbol ZBT_SRAM1_SIZE = 0x00400000; /* 4 MiB */
define symbol ZBT_SRAM1_START = (0x00000000 + 0x00004000);
define symbol ZBT_SRAM1_SIZE = (0x00400000 - 0x00004000); /* 4 MiB - 16 KiB */
/* Data memory zones */ /* Data memory zones */
define symbol ZBT_SRAM2_START = 0x20000000; define symbol ZBT_SRAM2_START = 0x20000000;
define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MB */ define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MiB */
/* NVIC vector numbers and size. */ /* NVIC vector numbers and size. */
define symbol NVIC_NUM_VECTORS = (16 + 48); define symbol NVIC_NUM_VECTORS = (16 + 48);
define symbol NVIC_VECTORS_SIZE = (NVIC_NUM_VECTORS * 4); define symbol NVIC_VECTORS_SIZE = (NVIC_NUM_VECTORS * 4);
/*-Specials-*/ /*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MAPPABLE_START; define symbol __ICFEDIT_intvec_start__ = ZBT_SRAM1_START;
/*-Memory Regions-*/ /*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = ZBT_SRAM1_START; define symbol __ICFEDIT_region_ROM_start__ = ZBT_SRAM1_START;

9
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/memory_zones.h
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@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2017-2018 ARM Limited * Copyright (c) 2017-2019 ARM Limited
* SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License Version 2.0 (the "License"); * Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License. * you may not use this file except in compliance with the License.
@ -37,10 +38,8 @@
* only to keep the same name than in the CMSDK RTL and Fast Models Reference * only to keep the same name than in the CMSDK RTL and Fast Models Reference
* Guide. * Guide.
*/ */
#define MAPPABLE_START 0x00000000 #define ZBT_SRAM1_START 0x00000000
#define MAPPABLE_SIZE 0x00004000 /* 16 KiB */ #define ZBT_SRAM1_SIZE 0x00400000 /* 4 MiB */
#define ZBT_SRAM1_START (0x00000000 + 0x00004000)
#define ZBT_SRAM1_SIZE (0x00400000 - 0x00004000) /* 4 MiB - 16 KiB*/
/* Data memory zones */ /* Data memory zones */
#define ZBT_SRAM2_START 0x20000000 #define ZBT_SRAM2_START 0x20000000

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct
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@ -1,8 +1,9 @@
#! armcc -E #! armcc -E
;* MPS2 CMSIS Library ;* MPS2 CMSIS Library
;* ;*
;* Copyright (c) 2006-2018 ARM Limited ;* Copyright (c) 2006-2019 ARM Limited
;* All rights reserved. ;* All rights reserved.
;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Redistribution and use in source and binary forms, with or without ;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions are met: ;* modification, are permitted provided that the following conditions are met:
@ -48,14 +49,9 @@
#endif #endif
; The vector table is loaded at address 0x00000000 in Flash memory region. ; The vector table is loaded at address 0x00000000 in Flash memory region.
LR_IROM1 MAPPABLE_START MAPPABLE_SIZE { LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM1 MAPPABLE_START MAPPABLE_SIZE { ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*.o (RESET, +First) *.o (RESET, +First)
}
}
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*(InRoot$$Sections) *(InRoot$$Sections)
*(+RO) *(+RO)
} }

7
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_GCC_ARM/MPS2.ld
View File

@ -2,7 +2,7 @@
* MPS2 CMSIS Library * MPS2 CMSIS Library
*/ */
/* /*
* Copyright (c) 2009-2018 ARM Limited. All rights reserved. * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -21,7 +21,7 @@
/* /*
* This file is derivative of CMSIS V5.00 gcc_arm.ld * This file is derivative of CMSIS V5.00 gcc_arm.ld
*/ */
/* Linker script for mbed FVP Cortex-M4 on MPS2 */ /* Linker script for mbed FVP Cortex-M on MPS2 */
/* Linker script to configure memory regions. */ /* Linker script to configure memory regions. */
/* The length of the VECTORS region is a bit larger than /* The length of the VECTORS region is a bit larger than
@ -37,7 +37,6 @@
MEMORY MEMORY
{ {
VECTORS (rx) : ORIGIN = MAPPABLE_START, LENGTH = MAPPABLE_SIZE
FLASH (rx) : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE FLASH (rx) : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE
RAM (rwx) : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE RAM (rwx) : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE
} }
@ -82,7 +81,7 @@ SECTIONS
__vector_table = .; __vector_table = .;
KEEP(*(.vector_table)) KEEP(*(.vector_table))
. = ALIGN(8); . = ALIGN(8);
} > VECTORS } > FLASH
.text : .text :
{ {

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_IAR/MPS2.icf
View File

@ -2,7 +2,7 @@
* MPS2 CMSIS Library * MPS2 CMSIS Library
*/ */
/* /*
* Copyright (c) 2009-2018 ARM Limited. All rights reserved. * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -24,21 +24,19 @@
* can not be included here. Please make sure that the two definitions match. * can not be included here. Please make sure that the two definitions match.
*/ */
/* Code memory zones */ /* Code memory zones */
define symbol MAPPABLE_START = 0x00000000; define symbol ZBT_SRAM1_START = 0x00000000;
define symbol MAPPABLE_SIZE = 0x00004000; /* 16 KiB */ define symbol ZBT_SRAM1_SIZE = 0x00400000; /* 4 MiB */
define symbol ZBT_SRAM1_START = (0x00000000 + 0x00004000);
define symbol ZBT_SRAM1_SIZE = (0x00400000 - 0x00004000); /* 4 MiB - 16 KiB */
/* Data memory zones */ /* Data memory zones */
define symbol ZBT_SRAM2_START = 0x20000000; define symbol ZBT_SRAM2_START = 0x20000000;
define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MB */ define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MiB */
/* NVIC vector numbers and size. */ /* NVIC vector numbers and size. */
define symbol NVIC_NUM_VECTORS = (16 + 48); define symbol NVIC_NUM_VECTORS = (16 + 48);
define symbol NVIC_VECTORS_SIZE = (NVIC_NUM_VECTORS * 4); define symbol NVIC_VECTORS_SIZE = (NVIC_NUM_VECTORS * 4);
/*-Specials-*/ /*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MAPPABLE_START; define symbol __ICFEDIT_intvec_start__ = ZBT_SRAM1_START;
/*-Memory Regions-*/ /*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = ZBT_SRAM1_START; define symbol __ICFEDIT_region_ROM_start__ = ZBT_SRAM1_START;

9
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/memory_zones.h
View File

@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2017-2018 ARM Limited * Copyright (c) 2017-2019 ARM Limited
* SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License Version 2.0 (the "License"); * Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License. * you may not use this file except in compliance with the License.
@ -37,10 +38,8 @@
* only to keep the same name than in the CMSDK RTL and Fast Models Reference * only to keep the same name than in the CMSDK RTL and Fast Models Reference
* Guide. * Guide.
*/ */
#define MAPPABLE_START 0x00000000 #define ZBT_SRAM1_START 0x00000000
#define MAPPABLE_SIZE 0x00004000 /* 16 KiB */ #define ZBT_SRAM1_SIZE 0x00400000 /* 4 MiB */
#define ZBT_SRAM1_START (0x00000000 + 0x00004000)
#define ZBT_SRAM1_SIZE (0x00400000 - 0x00004000) /* 4 MiB - 16 KiB*/
/* Data memory zones */ /* Data memory zones */
#define ZBT_SRAM2_START 0x20000000 #define ZBT_SRAM2_START 0x20000000

56
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -1,34 +1,35 @@
#! armcc -E #! armcc -E
;* MPS2 CMSIS Library ;* MPS2 CMSIS Library
;* ;*
;* Copyright (c) 2006-2018 ARM Limited ;* Copyright (c) 2006-2019 ARM Limited
;* All rights reserved. ;* All rights reserved.
;* ;* SPDX-License-Identifier: Apache-2.0
;* Redistribution and use in source and binary forms, with or without ;*
;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions are met: ;* modification, are permitted provided that the following conditions are met:
;* ;*
;* 1. Redistributions of source code must retain the above copyright notice, ;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer. ;* this list of conditions and the following disclaimer.
;* ;*
;* 2. Redistributions in binary form must reproduce the above copyright notice, ;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation ;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution. ;* and/or other materials provided with the distribution.
;* ;*
;* 3. Neither the name of the copyright holder nor the names of its contributors ;* 3. Neither the name of the copyright holder nor the names of its contributors
;* may be used to endorse or promote products derived from this software without ;* may be used to endorse or promote products derived from this software without
;* specific prior written permission. ;* specific prior written permission.
;* ;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE ;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;* POSSIBILITY OF SUCH DAMAGE. ;* POSSIBILITY OF SUCH DAMAGE.
;* ;*
; ************************************************************* ; *************************************************************
; *** Scatter-Loading Description File *** ; *** Scatter-Loading Description File ***
@ -48,14 +49,9 @@
#endif #endif
; The vector table is loaded at address 0x00000000 in Flash memory region. ; The vector table is loaded at address 0x00000000 in Flash memory region.
LR_IROM1 MAPPABLE_START MAPPABLE_SIZE { LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM1 MAPPABLE_START MAPPABLE_SIZE { ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*.o (RESET, +First) *.o (RESET, +First)
}
}
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*(InRoot$$Sections) *(InRoot$$Sections)
*(+RO) *(+RO)
} }

15
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_GCC_ARM/MPS2.ld
View File

@ -2,7 +2,7 @@
* MPS2 CMSIS Library * MPS2 CMSIS Library
*/ */
/* /*
* Copyright (c) 2009-2018 ARM Limited. All rights reserved. * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -21,7 +21,7 @@
/* /*
* This file is derivative of CMSIS V5.00 gcc_arm.ld * This file is derivative of CMSIS V5.00 gcc_arm.ld
*/ */
/* Linker script for mbed FVP Cortex-M7 on MPS2 */ /* Linker script for mbed FVP Cortex-M on MPS2 */
/* Linker script to configure memory regions. */ /* Linker script to configure memory regions. */
/* The length of the VECTORS region is a bit larger than /* The length of the VECTORS region is a bit larger than
@ -31,9 +31,12 @@
#include "../memory_zones.h" #include "../memory_zones.h"
#include "../cmsis_nvic.h" #include "../cmsis_nvic.h"
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
MEMORY MEMORY
{ {
VECTORS (rx) : ORIGIN = MAPPABLE_START, LENGTH = MAPPABLE_SIZE
FLASH (rx) : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE FLASH (rx) : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE
RAM (rwx) : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE RAM (rwx) : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE
} }
@ -66,10 +69,6 @@ MEMORY
*/ */
ENTRY(Reset_Handler) ENTRY(Reset_Handler)
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE; STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Size of the vector table in SRAM */ /* Size of the vector table in SRAM */
@ -82,7 +81,7 @@ SECTIONS
__vector_table = .; __vector_table = .;
KEEP(*(.vector_table)) KEEP(*(.vector_table))
. = ALIGN(8); . = ALIGN(8);
} > VECTORS } > FLASH
.text : .text :
{ {

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_IAR/MPS2.icf
View File

@ -2,7 +2,7 @@
* MPS2 CMSIS Library * MPS2 CMSIS Library
*/ */
/* /*
* Copyright (c) 2009-2018 ARM Limited. All rights reserved. * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -24,21 +24,19 @@
* can not be included here. Please make sure that the two definitions match. * can not be included here. Please make sure that the two definitions match.
*/ */
/* Code memory zones */ /* Code memory zones */
define symbol MAPPABLE_START = 0x00000000; define symbol ZBT_SRAM1_START = 0x00000000;
define symbol MAPPABLE_SIZE = 0x00004000; /* 16 KiB */ define symbol ZBT_SRAM1_SIZE = 0x00400000; /* 4 MiB */
define symbol ZBT_SRAM1_START = (0x00000000 + 0x00004000);
define symbol ZBT_SRAM1_SIZE = (0x00400000 - 0x00004000); /* 4 MiB - 16 KiB */
/* Data memory zones */ /* Data memory zones */
define symbol ZBT_SRAM2_START = 0x20000000; define symbol ZBT_SRAM2_START = 0x20000000;
define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MB */ define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MiB */
/* NVIC vector numbers and size. */ /* NVIC vector numbers and size. */
define symbol NVIC_NUM_VECTORS = (16 + 48); define symbol NVIC_NUM_VECTORS = (16 + 48);
define symbol NVIC_VECTORS_SIZE = (NVIC_NUM_VECTORS * 4); define symbol NVIC_VECTORS_SIZE = (NVIC_NUM_VECTORS * 4);
/*-Specials-*/ /*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MAPPABLE_START; define symbol __ICFEDIT_intvec_start__ = ZBT_SRAM1_START;
/*-Memory Regions-*/ /*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = ZBT_SRAM1_START; define symbol __ICFEDIT_region_ROM_start__ = ZBT_SRAM1_START;

9
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/memory_zones.h
View File

@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2017-2018 ARM Limited * Copyright (c) 2017-2019 ARM Limited
* SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License Version 2.0 (the "License"); * Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License. * you may not use this file except in compliance with the License.
@ -37,10 +38,8 @@
* only to keep the same name than in the CMSDK RTL and Fast Models Reference * only to keep the same name than in the CMSDK RTL and Fast Models Reference
* Guide. * Guide.
*/ */
#define MAPPABLE_START 0x00000000 #define ZBT_SRAM1_START 0x00000000
#define MAPPABLE_SIZE 0x00004000 /* 16 KiB */ #define ZBT_SRAM1_SIZE 0x00400000 /* 4 MiB */
#define ZBT_SRAM1_START (0x00000000 + 0x00004000)
#define ZBT_SRAM1_SIZE (0x00400000 - 0x00004000) /* 4 MiB - 16 KiB*/
/* Data memory zones */ /* Data memory zones */
#define ZBT_SRAM2_START 0x20000000 #define ZBT_SRAM2_START 0x20000000

2
targets/targets.json
View File

@ -8101,7 +8101,7 @@
"USTICKER" "USTICKER"
], ],
"release_versions": ["5"], "release_versions": ["5"],
"components_add": ["LAN91C111"], "components_add": ["LAN91C111", "FLASHIAP"],
"overrides": { "overrides": {
"network-default-interface-type": "ETHERNET" "network-default-interface-type": "ETHERNET"
} }