diff --git a/libraries/USBDevice/USBDevice/USBEndpoints.h b/libraries/USBDevice/USBDevice/USBEndpoints.h index 07d16f984a..2e80d9f1a0 100644 --- a/libraries/USBDevice/USBDevice/USBEndpoints.h +++ b/libraries/USBDevice/USBDevice/USBEndpoints.h @@ -41,7 +41,7 @@ typedef enum { #include "USBEndpoints_LPC17_LPC23.h" #elif defined(TARGET_LPC11UXX) || defined(TARGET_LPC1347) || defined (TARGET_LPC11U6X) || defined (TARGET_LPC1549) #include "USBEndpoints_LPC11U.h" -#elif defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F) +#elif defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) #include "USBEndpoints_KL25Z.h" #elif defined (TARGET_STM32F4) #include "USBEndpoints_STM32F4.h" diff --git a/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp b/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp index 64deaee006..f900c5747d 100644 --- a/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp +++ b/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp @@ -16,7 +16,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F) +#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) #include "USBHAL.h" diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_IAR/TARGET_LPC11U68/LPC11U68.icf b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_IAR/TARGET_LPC11U68/LPC11U68.icf new file mode 100644 index 0000000000..e83d57da08 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_IAR/TARGET_LPC11U68/LPC11U68.icf @@ -0,0 +1,44 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x10007FDF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x800; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __CRP_start__ = 0x000002FC; +define symbol __CRP_end__ = 0x000002FF; + +define symbol __RAM1_start__ = 0x20000000; +define symbol __RAM1_end__ = 0x200007FF; + +define symbol __RAM_USB_start__= 0x20004000; +define symbol __RAM_USB_end__ = 0x200047FF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM1_region = mem:[from __RAM1_start__ to __RAM1_end__]; +define region RAM_USB_region = mem:[from __RAM_USB_start__ to __RAM_USB_end__]; +define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in CRP_region { section .crp }; +place in RAM1_region { section .sram1 }; +place in RAM_USB_region { section .sram_usb }; diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_IAR/TARGET_LPC11U68/startup_LPC11U6X.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_IAR/TARGET_LPC11U68/startup_LPC11U6X.s new file mode 100644 index 0000000000..30ade0e718 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_IAR/TARGET_LPC11U68/startup_LPC11U6X.s @@ -0,0 +1,251 @@ +;/***************************************************************************** +; * @file: startup_LPC11u6x.s +; * @purpose: CMSIS Cortex-M0PLUS Core Device Startup File +; * for the NXP LPC11u6x Device Series (manually edited) +; * @version: V1.00 +; * @date: 19. October 2009 +; *---------------------------------------------------------------------------- +; * +; * Copyright (C) 2009 ARM Limited. All rights reserved. +; * +; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + DCD PIN_INT0_IRQHandler ; Pin interrupt 0 + DCD PIN_INT1_IRQHandler ; Pin interrupt 1 + DCD PIN_INT2_IRQHandler ; Pin interrupt 2 + DCD PIN_INT3_IRQHandler ; Pin interrupt 3 + DCD PIN_INT4_IRQHandler ; Pin interrupt 4 + DCD PIN_INT5_IRQHandler ; Pin interrupt 5 + DCD PIN_INT6_IRQHandler ; Pin interrupt 6 + DCD PIN_INT7_IRQHandler ; Pin interrupt 7 + DCD GINT0_IRQHandler ; Port interrupt group 0 + DCD GINT1_IRQHandler ; Port interrupt group 1 + DCD I2C1_IRQHandler ; I2C1 interrupt + DCD USART1_4_IRQHandler ; USARTS 1 and 4 shared interrupt + DCD USART2_3_IRQHandler ; USARTS 2 and 3 shared interrupt + DCD SCT0_1_IRQHandler ; SCT 0 and 1 shared interrupt + DCD SSP1_IRQHandler ; SSP1 interrupt + DCD I2C0_IRQHandler ; I2C0 interrupt + DCD CT16B0_IRQHandler ; CT16B0 (16-bit Timer 0) + DCD CT16B1_IRQHandler ; CT16B1 (16-bit Timer 1) + DCD CT32B0_IRQHandler ; CT32B0 (32-bit Timer 0) + DCD CT32B1_IRQHandler ; CT32B0 (32-bit Timer 1) + DCD SSP0_IRQHandler ; SSP0 interrupt interrupt + DCD USART0_IRQHandler ; USART 0 interrupt interrupt + DCD USB_IRQHandler ; USB IRQ interrupt + DCD USB_FIQ_IRQHandler ; USB FIQ interrupt + DCD ADC_A_IRQHandler ; ADC A sequence (A/D Converter) interrupt + DCD RTC_IRQHandler ; RTC interrupt + DCD BOD_WDT_IRQHandler ; Shared BOD (Brownout Detect) and WDT interrupts + DCD FLASH_IRQHandler ; Flash Memory Controller interrupt + DCD DMA_IRQHandler ; DMA Controller interrupt + DCD ADC_B_IRQHandler ; ADC B sequence interrupt + DCD USBWakeup_IRQHandler ; USB wake-up interrupt + DCD Reserved_IRQHandler + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK Reserved_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Reserved_IRQHandler + B . + + + PUBWEAK PIN_INT0_IRQHandler + PUBWEAK PIN_INT1_IRQHandler + PUBWEAK PIN_INT2_IRQHandler + PUBWEAK PIN_INT3_IRQHandler + PUBWEAK PIN_INT4_IRQHandler + PUBWEAK PIN_INT5_IRQHandler + PUBWEAK PIN_INT6_IRQHandler + PUBWEAK PIN_INT7_IRQHandler + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT1_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK USART1_4_IRQHandler + PUBWEAK USART2_3_IRQHandler + PUBWEAK SCT0_1_IRQHandler + PUBWEAK SSP1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK CT16B0_IRQHandler + PUBWEAK CT16B1_IRQHandler + PUBWEAK CT32B0_IRQHandler + PUBWEAK CT32B1_IRQHandler + PUBWEAK SSP0_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK USB_FIQ_IRQHandler + PUBWEAK ADC_A_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK BOD_WDT_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK DMA_IRQHandler + PUBWEAK ADC_B_IRQHandler + PUBWEAK USBWakeup_IRQHandler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB + +PIN_INT0_IRQHandler +PIN_INT1_IRQHandler +PIN_INT2_IRQHandler +PIN_INT3_IRQHandler +PIN_INT4_IRQHandler +PIN_INT5_IRQHandler +PIN_INT6_IRQHandler +PIN_INT7_IRQHandler +GINT0_IRQHandler +GINT1_IRQHandler +I2C1_IRQHandler +USART1_4_IRQHandler +USART2_3_IRQHandler +SCT0_1_IRQHandler +SSP1_IRQHandler +I2C0_IRQHandler +CT16B0_IRQHandler +CT16B1_IRQHandler +CT32B0_IRQHandler +CT32B1_IRQHandler +SSP0_IRQHandler +USART0_IRQHandler +USB_IRQHandler +USB_FIQ_IRQHandler +ADC_A_IRQHandler +RTC_IRQHandler +BOD_WDT_IRQHandler +FLASH_IRQHandler +DMA_IRQHandler +ADC_B_IRQHandler +USBWakeup_IRQHandler +Default_Handler + B Default_Handler + + SECTION .crp:CODE:ROOT(2) + DATA +/* Code Read Protection +NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode +CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. + - Copy RAM to flash command can not write to Sector 0. + - Erase command can erase Sector 0 only when all sectors + are selected for erase. + - Compare command is disabled. + - Read Memory command is disabled. +CRP2 0x87654321 - Read Memory is disabled. + - Write to RAM is disabled. + - "Go" command is disabled. + - Copy RAM to flash is disabled. + - Compare is disabled. +CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry + by pulling PIO0_1 LOW is disabled if a valid user code is + present in flash sector 0. +Caution: If CRP3 is selected, no future factory testing can be +performed on the device. +*/ + DCD 0xFFFFFFFF + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_301/LPC11U24.icf b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_301/LPC11U24.icf new file mode 100644 index 0000000000..fe812262b4 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_301/LPC11U24.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x100017DF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x800; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __CRP_start__ = 0x000002FC; +define symbol __CRP_end__ = 0x000002FF; + +define symbol __URAM_start__ = 0x20004000; +define symbol __URAM_end__ = 0x200047FF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region URAM_region = mem:[from __URAM_start__ to __URAM_end__]; +define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in CRP_region { section .crp }; +place in URAM_region { section USB_PACKET_MEMORY }; diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_301/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_301/startup_LPC11xx.s new file mode 100644 index 0000000000..0d9b2ef007 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_301/startup_LPC11xx.s @@ -0,0 +1,333 @@ +/************************************************** + * + * Part one of the system initialization code, contains low-level + * initialization, plain thumb variant. + * + * Copyright 2012 IAR Systems. All rights reserved. + * + * $Revision: 28 $ + * + **************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + DATA + + +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx + DCD FLEX_INT1_IRQHandler + DCD FLEX_INT2_IRQHandler + DCD FLEX_INT3_IRQHandler + DCD FLEX_INT4_IRQHandler + DCD FLEX_INT5_IRQHandler + DCD FLEX_INT6_IRQHandler + DCD FLEX_INT7_IRQHandler + DCD GINT0_IRQHandler + DCD GINT1_IRQHandler ; PIO0 (0:7) + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD USB_IRQHandler ; USB IRQ + DCD USB_FIQHandler ; USB FIQ + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD FMC_IRQHandler ; IP2111 Flash Memory Controller + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD USBWakeup_IRQHandler ; USB wake up + DCD Reserved_IRQHandler ; Reserved + + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK MemManage_Handler + PUBWEAK BusFault_Handler + PUBWEAK UsageFault_Handler + PUBWEAK SVC_Handler + PUBWEAK DebugMon_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + PUBWEAK FLEX_INT0_IRQHandler + PUBWEAK FLEX_INT1_IRQHandler + PUBWEAK FLEX_INT2_IRQHandler + PUBWEAK FLEX_INT3_IRQHandler + PUBWEAK FLEX_INT4_IRQHandler + PUBWEAK FLEX_INT5_IRQHandler + PUBWEAK FLEX_INT6_IRQHandler + PUBWEAK FLEX_INT7_IRQHandler + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT1_IRQHandler + PUBWEAK SSP1_IRQHandler + PUBWEAK I2C_IRQHandler + PUBWEAK TIMER16_0_IRQHandler + PUBWEAK TIMER16_1_IRQHandler + PUBWEAK TIMER32_0_IRQHandler + PUBWEAK TIMER32_1_IRQHandler + PUBWEAK SSP0_IRQHandler + PUBWEAK UART_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK USB_FIQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK WDT_IRQHandler + PUBWEAK BOD_IRQHandler + PUBWEAK FMC_IRQHandler + PUBWEAK USBWakeup_IRQHandler + PUBWEAK Reserved_IRQHandler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB +NMI_Handler: + B . +HardFault_Handler: + B . +MemManage_Handler: + B . +BusFault_Handler: + B . +UsageFault_Handler: + B . +SVC_Handler: + B . +DebugMon_Handler: + B . +PendSV_Handler: + B . +SysTick_Handler: + B . +FLEX_INT0_IRQHandler: + B . +FLEX_INT1_IRQHandler: + B . +FLEX_INT2_IRQHandler: + B . +FLEX_INT3_IRQHandler: + B . +FLEX_INT4_IRQHandler: + B . +FLEX_INT5_IRQHandler: + B . +FLEX_INT6_IRQHandler: + B . +FLEX_INT7_IRQHandler: + B . +GINT0_IRQHandler: + B . +GINT1_IRQHandler: + B . +SSP1_IRQHandler: + B . +I2C_IRQHandler: + B . +TIMER16_0_IRQHandler: + B . +TIMER16_1_IRQHandler: + B . +TIMER32_0_IRQHandler: + B . +TIMER32_1_IRQHandler: + B . +SSP0_IRQHandler: + B . +UART_IRQHandler: + B . +USB_IRQHandler: + B . +USB_FIQHandler: + B . +ADC_IRQHandler: + B . +WDT_IRQHandler: + B . +BOD_IRQHandler: + B . +FMC_IRQHandler: + B . +USBWakeup_IRQHandler: + B . +Reserved_IRQHandler: + B . +Default_Handler: + B . + + SECTION .crp:CODE:ROOT(2) + DATA +/* Code Read Protection +NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode +CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. + - Copy RAM to flash command can not write to Sector 0. + - Erase command can erase Sector 0 only when all sectors + are selected for erase. + - Compare command is disabled. + - Read Memory command is disabled. +CRP2 0x87654321 - Read Memory is disabled. + - Write to RAM is disabled. + - "Go" command is disabled. + - Copy RAM to flash is disabled. + - Compare is disabled. +CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry + by pulling PIO0_1 LOW is disabled if a valid user code is + present in flash sector 0. +Caution: If CRP3 is selected, no future factory testing can be +performed on the device. +*/ + DCD 0xFFFFFFFF + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_401/LPC11U24.icf b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_401/LPC11U24.icf new file mode 100644 index 0000000000..efccdfb62c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_401/LPC11U24.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x800; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __CRP_start__ = 0x000002FC; +define symbol __CRP_end__ = 0x000002FF; + +define symbol __URAM_start__ = 0x20004000; +define symbol __URAM_end__ = 0x200047FF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region URAM_region = mem:[from __URAM_start__ to __URAM_end__]; +define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in CRP_region { section .crp }; +place in URAM_region { section USB_PACKET_MEMORY }; diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_401/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_401/startup_LPC11xx.s new file mode 100644 index 0000000000..0d9b2ef007 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_401/startup_LPC11xx.s @@ -0,0 +1,333 @@ +/************************************************** + * + * Part one of the system initialization code, contains low-level + * initialization, plain thumb variant. + * + * Copyright 2012 IAR Systems. All rights reserved. + * + * $Revision: 28 $ + * + **************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + DATA + + +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx + DCD FLEX_INT1_IRQHandler + DCD FLEX_INT2_IRQHandler + DCD FLEX_INT3_IRQHandler + DCD FLEX_INT4_IRQHandler + DCD FLEX_INT5_IRQHandler + DCD FLEX_INT6_IRQHandler + DCD FLEX_INT7_IRQHandler + DCD GINT0_IRQHandler + DCD GINT1_IRQHandler ; PIO0 (0:7) + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD USB_IRQHandler ; USB IRQ + DCD USB_FIQHandler ; USB FIQ + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD FMC_IRQHandler ; IP2111 Flash Memory Controller + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD USBWakeup_IRQHandler ; USB wake up + DCD Reserved_IRQHandler ; Reserved + + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK MemManage_Handler + PUBWEAK BusFault_Handler + PUBWEAK UsageFault_Handler + PUBWEAK SVC_Handler + PUBWEAK DebugMon_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + PUBWEAK FLEX_INT0_IRQHandler + PUBWEAK FLEX_INT1_IRQHandler + PUBWEAK FLEX_INT2_IRQHandler + PUBWEAK FLEX_INT3_IRQHandler + PUBWEAK FLEX_INT4_IRQHandler + PUBWEAK FLEX_INT5_IRQHandler + PUBWEAK FLEX_INT6_IRQHandler + PUBWEAK FLEX_INT7_IRQHandler + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT1_IRQHandler + PUBWEAK SSP1_IRQHandler + PUBWEAK I2C_IRQHandler + PUBWEAK TIMER16_0_IRQHandler + PUBWEAK TIMER16_1_IRQHandler + PUBWEAK TIMER32_0_IRQHandler + PUBWEAK TIMER32_1_IRQHandler + PUBWEAK SSP0_IRQHandler + PUBWEAK UART_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK USB_FIQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK WDT_IRQHandler + PUBWEAK BOD_IRQHandler + PUBWEAK FMC_IRQHandler + PUBWEAK USBWakeup_IRQHandler + PUBWEAK Reserved_IRQHandler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB +NMI_Handler: + B . +HardFault_Handler: + B . +MemManage_Handler: + B . +BusFault_Handler: + B . +UsageFault_Handler: + B . +SVC_Handler: + B . +DebugMon_Handler: + B . +PendSV_Handler: + B . +SysTick_Handler: + B . +FLEX_INT0_IRQHandler: + B . +FLEX_INT1_IRQHandler: + B . +FLEX_INT2_IRQHandler: + B . +FLEX_INT3_IRQHandler: + B . +FLEX_INT4_IRQHandler: + B . +FLEX_INT5_IRQHandler: + B . +FLEX_INT6_IRQHandler: + B . +FLEX_INT7_IRQHandler: + B . +GINT0_IRQHandler: + B . +GINT1_IRQHandler: + B . +SSP1_IRQHandler: + B . +I2C_IRQHandler: + B . +TIMER16_0_IRQHandler: + B . +TIMER16_1_IRQHandler: + B . +TIMER32_0_IRQHandler: + B . +TIMER32_1_IRQHandler: + B . +SSP0_IRQHandler: + B . +UART_IRQHandler: + B . +USB_IRQHandler: + B . +USB_FIQHandler: + B . +ADC_IRQHandler: + B . +WDT_IRQHandler: + B . +BOD_IRQHandler: + B . +FMC_IRQHandler: + B . +USBWakeup_IRQHandler: + B . +Reserved_IRQHandler: + B . +Default_Handler: + B . + + SECTION .crp:CODE:ROOT(2) + DATA +/* Code Read Protection +NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode +CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. + - Copy RAM to flash command can not write to Sector 0. + - Erase command can erase Sector 0 only when all sectors + are selected for erase. + - Compare command is disabled. + - Read Memory command is disabled. +CRP2 0x87654321 - Read Memory is disabled. + - Write to RAM is disabled. + - "Go" command is disabled. + - Copy RAM to flash is disabled. + - Compare is disabled. +CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry + by pulling PIO0_1 LOW is disabled if a valid user code is + present in flash sector 0. +Caution: If CRP3 is selected, no future factory testing can be +performed on the device. +*/ + DCD 0xFFFFFFFF + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_401/LPC11U35.icf b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_401/LPC11U35.icf new file mode 100644 index 0000000000..db7eb638ac --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_401/LPC11U35.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x000000C0; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x800; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __CRP_start__ = 0x000002FC; +define symbol __CRP_end__ = 0x000002FF; + +define symbol __URAM_start__ = 0x20004000; +define symbol __URAM_end__ = 0x200047FF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region URAM_region = mem:[from __URAM_start__ to __URAM_end__]; +define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in CRP_region { section .crp }; +place in URAM_region { section USB_PACKET_MEMORY }; diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_401/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_401/startup_LPC11xx.s new file mode 100644 index 0000000000..0d9b2ef007 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_401/startup_LPC11xx.s @@ -0,0 +1,333 @@ +/************************************************** + * + * Part one of the system initialization code, contains low-level + * initialization, plain thumb variant. + * + * Copyright 2012 IAR Systems. All rights reserved. + * + * $Revision: 28 $ + * + **************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + DATA + + +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx + DCD FLEX_INT1_IRQHandler + DCD FLEX_INT2_IRQHandler + DCD FLEX_INT3_IRQHandler + DCD FLEX_INT4_IRQHandler + DCD FLEX_INT5_IRQHandler + DCD FLEX_INT6_IRQHandler + DCD FLEX_INT7_IRQHandler + DCD GINT0_IRQHandler + DCD GINT1_IRQHandler ; PIO0 (0:7) + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD USB_IRQHandler ; USB IRQ + DCD USB_FIQHandler ; USB FIQ + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD FMC_IRQHandler ; IP2111 Flash Memory Controller + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD USBWakeup_IRQHandler ; USB wake up + DCD Reserved_IRQHandler ; Reserved + + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK MemManage_Handler + PUBWEAK BusFault_Handler + PUBWEAK UsageFault_Handler + PUBWEAK SVC_Handler + PUBWEAK DebugMon_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + PUBWEAK FLEX_INT0_IRQHandler + PUBWEAK FLEX_INT1_IRQHandler + PUBWEAK FLEX_INT2_IRQHandler + PUBWEAK FLEX_INT3_IRQHandler + PUBWEAK FLEX_INT4_IRQHandler + PUBWEAK FLEX_INT5_IRQHandler + PUBWEAK FLEX_INT6_IRQHandler + PUBWEAK FLEX_INT7_IRQHandler + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT1_IRQHandler + PUBWEAK SSP1_IRQHandler + PUBWEAK I2C_IRQHandler + PUBWEAK TIMER16_0_IRQHandler + PUBWEAK TIMER16_1_IRQHandler + PUBWEAK TIMER32_0_IRQHandler + PUBWEAK TIMER32_1_IRQHandler + PUBWEAK SSP0_IRQHandler + PUBWEAK UART_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK USB_FIQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK WDT_IRQHandler + PUBWEAK BOD_IRQHandler + PUBWEAK FMC_IRQHandler + PUBWEAK USBWakeup_IRQHandler + PUBWEAK Reserved_IRQHandler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB +NMI_Handler: + B . +HardFault_Handler: + B . +MemManage_Handler: + B . +BusFault_Handler: + B . +UsageFault_Handler: + B . +SVC_Handler: + B . +DebugMon_Handler: + B . +PendSV_Handler: + B . +SysTick_Handler: + B . +FLEX_INT0_IRQHandler: + B . +FLEX_INT1_IRQHandler: + B . +FLEX_INT2_IRQHandler: + B . +FLEX_INT3_IRQHandler: + B . +FLEX_INT4_IRQHandler: + B . +FLEX_INT5_IRQHandler: + B . +FLEX_INT6_IRQHandler: + B . +FLEX_INT7_IRQHandler: + B . +GINT0_IRQHandler: + B . +GINT1_IRQHandler: + B . +SSP1_IRQHandler: + B . +I2C_IRQHandler: + B . +TIMER16_0_IRQHandler: + B . +TIMER16_1_IRQHandler: + B . +TIMER32_0_IRQHandler: + B . +TIMER32_1_IRQHandler: + B . +SSP0_IRQHandler: + B . +UART_IRQHandler: + B . +USB_IRQHandler: + B . +USB_FIQHandler: + B . +ADC_IRQHandler: + B . +WDT_IRQHandler: + B . +BOD_IRQHandler: + B . +FMC_IRQHandler: + B . +USBWakeup_IRQHandler: + B . +Reserved_IRQHandler: + B . +Default_Handler: + B . + + SECTION .crp:CODE:ROOT(2) + DATA +/* Code Read Protection +NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode +CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. + - Copy RAM to flash command can not write to Sector 0. + - Erase command can erase Sector 0 only when all sectors + are selected for erase. + - Compare command is disabled. + - Read Memory command is disabled. +CRP2 0x87654321 - Read Memory is disabled. + - Write to RAM is disabled. + - "Go" command is disabled. + - Copy RAM to flash is disabled. + - Compare is disabled. +CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry + by pulling PIO0_1 LOW is disabled if a valid user code is + present in flash sector 0. +Caution: If CRP3 is selected, no future factory testing can be +performed on the device. +*/ + DCD 0xFFFFFFFF + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_501/LPC11U35.icf b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_501/LPC11U35.icf new file mode 100644 index 0000000000..7a91e963c1 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_501/LPC11U35.icf @@ -0,0 +1,44 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x000000C0; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x800; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __CRP_start__ = 0x000002FC; +define symbol __CRP_end__ = 0x000002FF; + +define symbol __URAM_start__ = 0x20004000; +define symbol __URAM_end__ = 0x200047FF; + +define symbol __SRAM1_start__ = 0x20000000; +define symbol __SRAM1_end__ = 0x200007FF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region URAM_region = mem:[from __URAM_start__ to __URAM_end__]; +define region SRAM1_region = mem:[from __SRAM1_start__ to __SRAM1_end__]; +define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in CRP_region { section .crp }; +place in URAM_region { section USB_PACKET_MEMORY }; +place in SRAM1_region { section .SRAM1 }; diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_501/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_501/startup_LPC11xx.s new file mode 100644 index 0000000000..0d9b2ef007 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_501/startup_LPC11xx.s @@ -0,0 +1,333 @@ +/************************************************** + * + * Part one of the system initialization code, contains low-level + * initialization, plain thumb variant. + * + * Copyright 2012 IAR Systems. All rights reserved. + * + * $Revision: 28 $ + * + **************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + DATA + + +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx + DCD FLEX_INT1_IRQHandler + DCD FLEX_INT2_IRQHandler + DCD FLEX_INT3_IRQHandler + DCD FLEX_INT4_IRQHandler + DCD FLEX_INT5_IRQHandler + DCD FLEX_INT6_IRQHandler + DCD FLEX_INT7_IRQHandler + DCD GINT0_IRQHandler + DCD GINT1_IRQHandler ; PIO0 (0:7) + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD USB_IRQHandler ; USB IRQ + DCD USB_FIQHandler ; USB FIQ + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD FMC_IRQHandler ; IP2111 Flash Memory Controller + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD USBWakeup_IRQHandler ; USB wake up + DCD Reserved_IRQHandler ; Reserved + + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK MemManage_Handler + PUBWEAK BusFault_Handler + PUBWEAK UsageFault_Handler + PUBWEAK SVC_Handler + PUBWEAK DebugMon_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + PUBWEAK FLEX_INT0_IRQHandler + PUBWEAK FLEX_INT1_IRQHandler + PUBWEAK FLEX_INT2_IRQHandler + PUBWEAK FLEX_INT3_IRQHandler + PUBWEAK FLEX_INT4_IRQHandler + PUBWEAK FLEX_INT5_IRQHandler + PUBWEAK FLEX_INT6_IRQHandler + PUBWEAK FLEX_INT7_IRQHandler + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT1_IRQHandler + PUBWEAK SSP1_IRQHandler + PUBWEAK I2C_IRQHandler + PUBWEAK TIMER16_0_IRQHandler + PUBWEAK TIMER16_1_IRQHandler + PUBWEAK TIMER32_0_IRQHandler + PUBWEAK TIMER32_1_IRQHandler + PUBWEAK SSP0_IRQHandler + PUBWEAK UART_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK USB_FIQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK WDT_IRQHandler + PUBWEAK BOD_IRQHandler + PUBWEAK FMC_IRQHandler + PUBWEAK USBWakeup_IRQHandler + PUBWEAK Reserved_IRQHandler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB +NMI_Handler: + B . +HardFault_Handler: + B . +MemManage_Handler: + B . +BusFault_Handler: + B . +UsageFault_Handler: + B . +SVC_Handler: + B . +DebugMon_Handler: + B . +PendSV_Handler: + B . +SysTick_Handler: + B . +FLEX_INT0_IRQHandler: + B . +FLEX_INT1_IRQHandler: + B . +FLEX_INT2_IRQHandler: + B . +FLEX_INT3_IRQHandler: + B . +FLEX_INT4_IRQHandler: + B . +FLEX_INT5_IRQHandler: + B . +FLEX_INT6_IRQHandler: + B . +FLEX_INT7_IRQHandler: + B . +GINT0_IRQHandler: + B . +GINT1_IRQHandler: + B . +SSP1_IRQHandler: + B . +I2C_IRQHandler: + B . +TIMER16_0_IRQHandler: + B . +TIMER16_1_IRQHandler: + B . +TIMER32_0_IRQHandler: + B . +TIMER32_1_IRQHandler: + B . +SSP0_IRQHandler: + B . +UART_IRQHandler: + B . +USB_IRQHandler: + B . +USB_FIQHandler: + B . +ADC_IRQHandler: + B . +WDT_IRQHandler: + B . +BOD_IRQHandler: + B . +FMC_IRQHandler: + B . +USBWakeup_IRQHandler: + B . +Reserved_IRQHandler: + B . +Default_Handler: + B . + + SECTION .crp:CODE:ROOT(2) + DATA +/* Code Read Protection +NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode +CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. + - Copy RAM to flash command can not write to Sector 0. + - Erase command can erase Sector 0 only when all sectors + are selected for erase. + - Compare command is disabled. + - Read Memory command is disabled. +CRP2 0x87654321 - Read Memory is disabled. + - Write to RAM is disabled. + - "Go" command is disabled. + - Copy RAM to flash is disabled. + - Compare is disabled. +CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry + by pulling PIO0_1 LOW is disabled if a valid user code is + present in flash sector 0. +Caution: If CRP3 is selected, no future factory testing can be +performed on the device. +*/ + DCD 0xFFFFFFFF + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U37_501/LPC11U37.icf b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U37_501/LPC11U37.icf new file mode 100644 index 0000000000..9a37f2c5ae --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U37_501/LPC11U37.icf @@ -0,0 +1,44 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x000000C0; +define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x800; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __CRP_start__ = 0x000002FC; +define symbol __CRP_end__ = 0x000002FF; + +define symbol __URAM_start__ = 0x20004000; +define symbol __URAM_end__ = 0x200047FF; + +define symbol __SRAM1_start__ = 0x20000000; +define symbol __SRAM1_end__ = 0x200007FF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region URAM_region = mem:[from __URAM_start__ to __URAM_end__]; +define region SRAM1_region = mem:[from __SRAM1_start__ to __SRAM1_end__]; +define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in CRP_region { section .crp }; +place in URAM_region { section USB_PACKET_MEMORY }; +place in SRAM1_region { section .SRAM1 }; diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U37_501/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U37_501/startup_LPC11xx.s new file mode 100644 index 0000000000..0d9b2ef007 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U37_501/startup_LPC11xx.s @@ -0,0 +1,333 @@ +/************************************************** + * + * Part one of the system initialization code, contains low-level + * initialization, plain thumb variant. + * + * Copyright 2012 IAR Systems. All rights reserved. + * + * $Revision: 28 $ + * + **************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + DATA + + +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx + DCD FLEX_INT1_IRQHandler + DCD FLEX_INT2_IRQHandler + DCD FLEX_INT3_IRQHandler + DCD FLEX_INT4_IRQHandler + DCD FLEX_INT5_IRQHandler + DCD FLEX_INT6_IRQHandler + DCD FLEX_INT7_IRQHandler + DCD GINT0_IRQHandler + DCD GINT1_IRQHandler ; PIO0 (0:7) + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD USB_IRQHandler ; USB IRQ + DCD USB_FIQHandler ; USB FIQ + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD FMC_IRQHandler ; IP2111 Flash Memory Controller + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD USBWakeup_IRQHandler ; USB wake up + DCD Reserved_IRQHandler ; Reserved + + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK MemManage_Handler + PUBWEAK BusFault_Handler + PUBWEAK UsageFault_Handler + PUBWEAK SVC_Handler + PUBWEAK DebugMon_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + PUBWEAK FLEX_INT0_IRQHandler + PUBWEAK FLEX_INT1_IRQHandler + PUBWEAK FLEX_INT2_IRQHandler + PUBWEAK FLEX_INT3_IRQHandler + PUBWEAK FLEX_INT4_IRQHandler + PUBWEAK FLEX_INT5_IRQHandler + PUBWEAK FLEX_INT6_IRQHandler + PUBWEAK FLEX_INT7_IRQHandler + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT1_IRQHandler + PUBWEAK SSP1_IRQHandler + PUBWEAK I2C_IRQHandler + PUBWEAK TIMER16_0_IRQHandler + PUBWEAK TIMER16_1_IRQHandler + PUBWEAK TIMER32_0_IRQHandler + PUBWEAK TIMER32_1_IRQHandler + PUBWEAK SSP0_IRQHandler + PUBWEAK UART_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK USB_FIQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK WDT_IRQHandler + PUBWEAK BOD_IRQHandler + PUBWEAK FMC_IRQHandler + PUBWEAK USBWakeup_IRQHandler + PUBWEAK Reserved_IRQHandler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB +NMI_Handler: + B . +HardFault_Handler: + B . +MemManage_Handler: + B . +BusFault_Handler: + B . +UsageFault_Handler: + B . +SVC_Handler: + B . +DebugMon_Handler: + B . +PendSV_Handler: + B . +SysTick_Handler: + B . +FLEX_INT0_IRQHandler: + B . +FLEX_INT1_IRQHandler: + B . +FLEX_INT2_IRQHandler: + B . +FLEX_INT3_IRQHandler: + B . +FLEX_INT4_IRQHandler: + B . +FLEX_INT5_IRQHandler: + B . +FLEX_INT6_IRQHandler: + B . +FLEX_INT7_IRQHandler: + B . +GINT0_IRQHandler: + B . +GINT1_IRQHandler: + B . +SSP1_IRQHandler: + B . +I2C_IRQHandler: + B . +TIMER16_0_IRQHandler: + B . +TIMER16_1_IRQHandler: + B . +TIMER32_0_IRQHandler: + B . +TIMER32_1_IRQHandler: + B . +SSP0_IRQHandler: + B . +UART_IRQHandler: + B . +USB_IRQHandler: + B . +USB_FIQHandler: + B . +ADC_IRQHandler: + B . +WDT_IRQHandler: + B . +BOD_IRQHandler: + B . +FMC_IRQHandler: + B . +USBWakeup_IRQHandler: + B . +Reserved_IRQHandler: + B . +Default_Handler: + B . + + SECTION .crp:CODE:ROOT(2) + DATA +/* Code Read Protection +NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode +CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. + - Copy RAM to flash command can not write to Sector 0. + - Erase command can erase Sector 0 only when all sectors + are selected for erase. + - Compare command is disabled. + - Read Memory command is disabled. +CRP2 0x87654321 - Read Memory is disabled. + - Write to RAM is disabled. + - "Go" command is disabled. + - Copy RAM to flash is disabled. + - Compare is disabled. +CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry + by pulling PIO0_1 LOW is disabled if a valid user code is + present in flash sector 0. +Caution: If CRP3 is selected, no future factory testing can be +performed on the device. +*/ + DCD 0xFFFFFFFF + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_OC_MBUINO/LPC11U24.icf b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_OC_MBUINO/LPC11U24.icf new file mode 100644 index 0000000000..efccdfb62c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_OC_MBUINO/LPC11U24.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x800; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __CRP_start__ = 0x000002FC; +define symbol __CRP_end__ = 0x000002FF; + +define symbol __URAM_start__ = 0x20004000; +define symbol __URAM_end__ = 0x200047FF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region URAM_region = mem:[from __URAM_start__ to __URAM_end__]; +define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in CRP_region { section .crp }; +place in URAM_region { section USB_PACKET_MEMORY }; diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_OC_MBUINO/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_OC_MBUINO/startup_LPC11xx.s new file mode 100644 index 0000000000..0d9b2ef007 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_OC_MBUINO/startup_LPC11xx.s @@ -0,0 +1,333 @@ +/************************************************** + * + * Part one of the system initialization code, contains low-level + * initialization, plain thumb variant. + * + * Copyright 2012 IAR Systems. All rights reserved. + * + * $Revision: 28 $ + * + **************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + DATA + + +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx + DCD FLEX_INT1_IRQHandler + DCD FLEX_INT2_IRQHandler + DCD FLEX_INT3_IRQHandler + DCD FLEX_INT4_IRQHandler + DCD FLEX_INT5_IRQHandler + DCD FLEX_INT6_IRQHandler + DCD FLEX_INT7_IRQHandler + DCD GINT0_IRQHandler + DCD GINT1_IRQHandler ; PIO0 (0:7) + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD USB_IRQHandler ; USB IRQ + DCD USB_FIQHandler ; USB FIQ + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD FMC_IRQHandler ; IP2111 Flash Memory Controller + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD USBWakeup_IRQHandler ; USB wake up + DCD Reserved_IRQHandler ; Reserved + + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK MemManage_Handler + PUBWEAK BusFault_Handler + PUBWEAK UsageFault_Handler + PUBWEAK SVC_Handler + PUBWEAK DebugMon_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + PUBWEAK FLEX_INT0_IRQHandler + PUBWEAK FLEX_INT1_IRQHandler + PUBWEAK FLEX_INT2_IRQHandler + PUBWEAK FLEX_INT3_IRQHandler + PUBWEAK FLEX_INT4_IRQHandler + PUBWEAK FLEX_INT5_IRQHandler + PUBWEAK FLEX_INT6_IRQHandler + PUBWEAK FLEX_INT7_IRQHandler + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT1_IRQHandler + PUBWEAK SSP1_IRQHandler + PUBWEAK I2C_IRQHandler + PUBWEAK TIMER16_0_IRQHandler + PUBWEAK TIMER16_1_IRQHandler + PUBWEAK TIMER32_0_IRQHandler + PUBWEAK TIMER32_1_IRQHandler + PUBWEAK SSP0_IRQHandler + PUBWEAK UART_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK USB_FIQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK WDT_IRQHandler + PUBWEAK BOD_IRQHandler + PUBWEAK FMC_IRQHandler + PUBWEAK USBWakeup_IRQHandler + PUBWEAK Reserved_IRQHandler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB +NMI_Handler: + B . +HardFault_Handler: + B . +MemManage_Handler: + B . +BusFault_Handler: + B . +UsageFault_Handler: + B . +SVC_Handler: + B . +DebugMon_Handler: + B . +PendSV_Handler: + B . +SysTick_Handler: + B . +FLEX_INT0_IRQHandler: + B . +FLEX_INT1_IRQHandler: + B . +FLEX_INT2_IRQHandler: + B . +FLEX_INT3_IRQHandler: + B . +FLEX_INT4_IRQHandler: + B . +FLEX_INT5_IRQHandler: + B . +FLEX_INT6_IRQHandler: + B . +FLEX_INT7_IRQHandler: + B . +GINT0_IRQHandler: + B . +GINT1_IRQHandler: + B . +SSP1_IRQHandler: + B . +I2C_IRQHandler: + B . +TIMER16_0_IRQHandler: + B . +TIMER16_1_IRQHandler: + B . +TIMER32_0_IRQHandler: + B . +TIMER32_1_IRQHandler: + B . +SSP0_IRQHandler: + B . +UART_IRQHandler: + B . +USB_IRQHandler: + B . +USB_FIQHandler: + B . +ADC_IRQHandler: + B . +WDT_IRQHandler: + B . +BOD_IRQHandler: + B . +FMC_IRQHandler: + B . +USBWakeup_IRQHandler: + B . +Reserved_IRQHandler: + B . +Default_Handler: + B . + + SECTION .crp:CODE:ROOT(2) + DATA +/* Code Read Protection +NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode +CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. + - Copy RAM to flash command can not write to Sector 0. + - Erase command can erase Sector 0 only when all sectors + are selected for erase. + - Compare command is disabled. + - Read Memory command is disabled. +CRP2 0x87654321 - Read Memory is disabled. + - Write to RAM is disabled. + - "Go" command is disabled. + - Copy RAM to flash is disabled. + - Compare is disabled. +CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry + by pulling PIO0_1 LOW is disabled if a valid user code is + present in flash sector 0. +Caution: If CRP3 is selected, no future factory testing can be +performed on the device. +*/ + DCD 0xFFFFFFFF + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11CXX/LPC11C24.icf b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11CXX/LPC11C24.icf new file mode 100644 index 0000000000..0ce86b6902 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11CXX/LPC11C24.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x800; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __CRP_start__ = 0x000002FC; +define symbol __CRP_end__ = 0x000002FF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in CRP_region { section .crp }; diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11CXX/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11CXX/startup_LPC11xx.s new file mode 100644 index 0000000000..8af59274d8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11CXX/startup_LPC11xx.s @@ -0,0 +1,299 @@ +/************************************************** + * + * Part one of the system initialization code, contains low-level + * initialization, plain thumb variant. + * + * Copyright 2012 IAR Systems. All rights reserved. + * + * $Revision: 28 $ + * + **************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + DATA + + +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD SLWU_INT0_IRQHandler ; Start logic wake-up interrupt 0 + DCD SLWU_INT1_IRQHandler ; Start logic wake-up interrupt 1 + DCD SLWU_INT2_IRQHandler ; Start logic wake-up interrupt 2 + DCD SLWU_INT3_IRQHandler ; Start logic wake-up interrupt 3 + DCD SLWU_INT4_IRQHandler ; Start logic wake-up interrupt 4 + DCD SLWU_INT5_IRQHandler ; Start logic wake-up interrupt 5 + DCD SLWU_INT6_IRQHandler ; Start logic wake-up interrupt 6 + DCD SLWU_INT7_IRQHandler ; Start logic wake-up interrupt 7 + DCD SLWU_INT8_IRQHandler ; Start logic wake-up interrupt 8 + DCD SLWU_INT9_IRQHandler ; Start logic wake-up interrupt 9 + DCD SLWU_INT10_IRQHandler ; Start logic wake-up interrupt 10 + DCD SLWU_INT11_IRQHandler ; Start logic wake-up interrupt 11 + DCD SLWU_INT12_IRQHandler ; Start logic wake-up interrupt 12 + DCD C_CAN_IRQHandler ; C_CAN + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD Reserved_IRQHandler ; Reserved + DCD PIO_3_IRQHandler ; GPIO interrupt status of port 3 + DCD PIO_2_IRQHandler ; GPIO interrupt status of port 2 + DCD PIO_1_IRQHandler ; GPIO interrupt status of port 1 + DCD PIO_0_IRQHandler ; GPIO interrupt status of port 0 + + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK SVC_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + PUBWEAK Reserved_IRQHandler + PUBWEAK SLWU_INT0_IRQHandler + PUBWEAK SLWU_INT1_IRQHandler + PUBWEAK SLWU_INT2_IRQHandler + PUBWEAK SLWU_INT3_IRQHandler + PUBWEAK SLWU_INT4_IRQHandler + PUBWEAK SLWU_INT5_IRQHandler + PUBWEAK SLWU_INT6_IRQHandler + PUBWEAK SLWU_INT7_IRQHandler + PUBWEAK SLWU_INT8_IRQHandler + PUBWEAK SLWU_INT9_IRQHandler + PUBWEAK SLWU_INT10_IRQHandler + PUBWEAK SLWU_INT11_IRQHandler + PUBWEAK SLWU_INT12_IRQHandler + PUBWEAK C_CAN_IRQHandler + PUBWEAK SSP1_IRQHandler + PUBWEAK I2C_IRQHandler + PUBWEAK TIMER16_0_IRQHandler + PUBWEAK TIMER16_1_IRQHandler + PUBWEAK TIMER32_0_IRQHandler + PUBWEAK TIMER32_1_IRQHandler + PUBWEAK SSP0_IRQHandler + PUBWEAK UART_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK WDT_IRQHandler + PUBWEAK BOD_IRQHandler + PUBWEAK PIO_3_IRQHandler + PUBWEAK PIO_2_IRQHandler + PUBWEAK PIO_1_IRQHandler + PUBWEAK PIO_0_IRQHandler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB + +NMI_Handler +HardFault_Handler +SVC_Handler +PendSV_Handler +SysTick_Handler +Reserved_IRQHandler +SLWU_INT0_IRQHandler +SLWU_INT1_IRQHandler +SLWU_INT2_IRQHandler +SLWU_INT3_IRQHandler +SLWU_INT4_IRQHandler +SLWU_INT5_IRQHandler +SLWU_INT6_IRQHandler +SLWU_INT7_IRQHandler +SLWU_INT8_IRQHandler +SLWU_INT9_IRQHandler +SLWU_INT10_IRQHandler +SLWU_INT11_IRQHandler +SLWU_INT12_IRQHandler +C_CAN_IRQHandler +SSP1_IRQHandler +I2C_IRQHandler +TIMER16_0_IRQHandler +TIMER16_1_IRQHandler +TIMER32_0_IRQHandler +TIMER32_1_IRQHandler +SSP0_IRQHandler +UART_IRQHandler +ADC_IRQHandler +WDT_IRQHandler +BOD_IRQHandler +PIO_3_IRQHandler +PIO_2_IRQHandler +PIO_1_IRQHandler +PIO_0_IRQHandler +Default_Handler + B Default_Handler + + SECTION .crp:CODE:ROOT(2) + DATA +/* Code Read Protection +NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode +CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. + - Copy RAM to flash command can not write to Sector 0. + - Erase command can erase Sector 0 only when all sectors + are selected for erase. + - Compare command is disabled. + - Read Memory command is disabled. +CRP2 0x87654321 - Read Memory is disabled. + - Write to RAM is disabled. + - "Go" command is disabled. + - Copy RAM to flash is disabled. + - Compare is disabled. +CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry + by pulling PIO0_1 LOW is disabled if a valid user code is + present in flash sector 0. +Caution: If CRP3 is selected, no future factory testing can be +performed on the device. +*/ + DCD 0xFFFFFFFF + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11XX/LPC1114.icf b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11XX/LPC1114.icf new file mode 100644 index 0000000000..6ebf7a91bb --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11XX/LPC1114.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x10000FDF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __CRP_start__ = 0x000002FC; +define symbol __CRP_end__ = 0x000002FF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in CRP_region { section .crp }; diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11XX/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11XX/startup_LPC11xx.s new file mode 100644 index 0000000000..8af59274d8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11XX/startup_LPC11xx.s @@ -0,0 +1,299 @@ +/************************************************** + * + * Part one of the system initialization code, contains low-level + * initialization, plain thumb variant. + * + * Copyright 2012 IAR Systems. All rights reserved. + * + * $Revision: 28 $ + * + **************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + DATA + + +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD SLWU_INT0_IRQHandler ; Start logic wake-up interrupt 0 + DCD SLWU_INT1_IRQHandler ; Start logic wake-up interrupt 1 + DCD SLWU_INT2_IRQHandler ; Start logic wake-up interrupt 2 + DCD SLWU_INT3_IRQHandler ; Start logic wake-up interrupt 3 + DCD SLWU_INT4_IRQHandler ; Start logic wake-up interrupt 4 + DCD SLWU_INT5_IRQHandler ; Start logic wake-up interrupt 5 + DCD SLWU_INT6_IRQHandler ; Start logic wake-up interrupt 6 + DCD SLWU_INT7_IRQHandler ; Start logic wake-up interrupt 7 + DCD SLWU_INT8_IRQHandler ; Start logic wake-up interrupt 8 + DCD SLWU_INT9_IRQHandler ; Start logic wake-up interrupt 9 + DCD SLWU_INT10_IRQHandler ; Start logic wake-up interrupt 10 + DCD SLWU_INT11_IRQHandler ; Start logic wake-up interrupt 11 + DCD SLWU_INT12_IRQHandler ; Start logic wake-up interrupt 12 + DCD C_CAN_IRQHandler ; C_CAN + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD Reserved_IRQHandler ; Reserved + DCD PIO_3_IRQHandler ; GPIO interrupt status of port 3 + DCD PIO_2_IRQHandler ; GPIO interrupt status of port 2 + DCD PIO_1_IRQHandler ; GPIO interrupt status of port 1 + DCD PIO_0_IRQHandler ; GPIO interrupt status of port 0 + + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK SVC_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + PUBWEAK Reserved_IRQHandler + PUBWEAK SLWU_INT0_IRQHandler + PUBWEAK SLWU_INT1_IRQHandler + PUBWEAK SLWU_INT2_IRQHandler + PUBWEAK SLWU_INT3_IRQHandler + PUBWEAK SLWU_INT4_IRQHandler + PUBWEAK SLWU_INT5_IRQHandler + PUBWEAK SLWU_INT6_IRQHandler + PUBWEAK SLWU_INT7_IRQHandler + PUBWEAK SLWU_INT8_IRQHandler + PUBWEAK SLWU_INT9_IRQHandler + PUBWEAK SLWU_INT10_IRQHandler + PUBWEAK SLWU_INT11_IRQHandler + PUBWEAK SLWU_INT12_IRQHandler + PUBWEAK C_CAN_IRQHandler + PUBWEAK SSP1_IRQHandler + PUBWEAK I2C_IRQHandler + PUBWEAK TIMER16_0_IRQHandler + PUBWEAK TIMER16_1_IRQHandler + PUBWEAK TIMER32_0_IRQHandler + PUBWEAK TIMER32_1_IRQHandler + PUBWEAK SSP0_IRQHandler + PUBWEAK UART_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK WDT_IRQHandler + PUBWEAK BOD_IRQHandler + PUBWEAK PIO_3_IRQHandler + PUBWEAK PIO_2_IRQHandler + PUBWEAK PIO_1_IRQHandler + PUBWEAK PIO_0_IRQHandler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB + +NMI_Handler +HardFault_Handler +SVC_Handler +PendSV_Handler +SysTick_Handler +Reserved_IRQHandler +SLWU_INT0_IRQHandler +SLWU_INT1_IRQHandler +SLWU_INT2_IRQHandler +SLWU_INT3_IRQHandler +SLWU_INT4_IRQHandler +SLWU_INT5_IRQHandler +SLWU_INT6_IRQHandler +SLWU_INT7_IRQHandler +SLWU_INT8_IRQHandler +SLWU_INT9_IRQHandler +SLWU_INT10_IRQHandler +SLWU_INT11_IRQHandler +SLWU_INT12_IRQHandler +C_CAN_IRQHandler +SSP1_IRQHandler +I2C_IRQHandler +TIMER16_0_IRQHandler +TIMER16_1_IRQHandler +TIMER32_0_IRQHandler +TIMER32_1_IRQHandler +SSP0_IRQHandler +UART_IRQHandler +ADC_IRQHandler +WDT_IRQHandler +BOD_IRQHandler +PIO_3_IRQHandler +PIO_2_IRQHandler +PIO_1_IRQHandler +PIO_0_IRQHandler +Default_Handler + B Default_Handler + + SECTION .crp:CODE:ROOT(2) + DATA +/* Code Read Protection +NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode +CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. + - Copy RAM to flash command can not write to Sector 0. + - Erase command can erase Sector 0 only when all sectors + are selected for erase. + - Compare command is disabled. + - Read Memory command is disabled. +CRP2 0x87654321 - Read Memory is disabled. + - Write to RAM is disabled. + - "Go" command is disabled. + - Copy RAM to flash is disabled. + - Compare is disabled. +CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry + by pulling PIO0_1 LOW is disabled if a valid user code is + present in flash sector 0. +Caution: If CRP3 is selected, no future factory testing can be +performed on the device. +*/ + DCD 0xFFFFFFFF + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_IAR/LPC15xx.icf b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_IAR/LPC15xx.icf new file mode 100644 index 0000000000..e57c0e0c81 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_IAR/LPC15xx.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x02000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x02008FDF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __CRP_start__ = 0x000002FC; +define symbol __CRP_end__ = 0x000002FF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in CRP_region { section .crp }; diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_IAR/startup_LPC15xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_IAR/startup_LPC15xx.s new file mode 100644 index 0000000000..c7f63c0b2f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_IAR/startup_LPC15xx.s @@ -0,0 +1,274 @@ +/************************************************** + * + * Part one of the system initialization code, contains low-level + * initialization, plain thumb variant. + * + * Copyright 2009 IAR Systems. All rights reserved. + * + * $Revision: 28 $ + * + **************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + +; External Interrupts + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD FLASH_IRQHandler ; NVMC Flash Controller + DCD EE_IRQHandler ; NVMC EE Controller + DCD DMA_IRQHandler ; DMA Controller + DCD GINT0_IRQHandler + DCD GINT1_IRQHandler ; PIO0 (0:7) + DCD PIN_INT0_IRQHandler ; 16+ 7 Pin interrupt 0 or pattern match engine slice 0 interrupt + DCD PIN_INT1_IRQHandler ; 16+ 8 Pin interrupt 1 or pattern match engine slice 1 interrupt + DCD PIN_INT2_IRQHandler ; 16+ 9 Pin interrupt 2 or pattern match engine slice 2 interrupt + DCD PIN_INT3_IRQHandler ; 16+10 Pin interrupt 3 or pattern match engine slice 3 interrupt + DCD PIN_INT4_IRQHandler ; 16+11 Pin interrupt 4 or pattern match engine slice 4 interrupt + DCD PIN_INT5_IRQHandler ; 16+12 Pin interrupt 5 or pattern match engine slice 5 interrupt + DCD PIN_INT6_IRQHandler ; 16+13 Pin interrupt 6 or pattern match engine slice 6 interrupt + DCD PIN_INT7_IRQHandler ; 16+14 Pin interrupt 7 or pattern match engine slice 7 interrupt + DCD RIT_IRQHandler ; RIT Timer + DCD SCT0_IRQHandler ; SCT Timer0 + DCD SCT1_IRQHandler ; SCT Timer1 + DCD SCT2_IRQHandler ; SCT Timer2 + DCD SCT3_IRQHandler ; SCT Timer3 + DCD MRT_IRQHandler ; MRT timer + DCD UART0_IRQHandler ; MIN UART0 + DCD UART1_IRQHandler ; MIN UART1 + DCD UART2_IRQHandler ; MIN UART2 + DCD I2C0_IRQHandler ; BI2C + DCD SPI0_IRQHandler ; LSPI0 + DCD SPI1_IRQHandler ; LSPI1 + DCD C_CAN0_IRQHandler ; CAN + DCD USB_IRQ_IRQHandler ; USB IRQ + DCD USB_FIQ_IRQHandler ; USB FIQ + DCD USBWakeup_IRQHandler ; USB wake up + DCD ADC0_SEQA_IRQHandler ; ADC0 SEQA + DCD ADC0_SEQB_IRQHandler ; ADC0 SEQB + DCD ADC0_THCMP_IRQHandler ; ADC0 THCMP + DCD ADC0_OVR_IRQHandler ; ADC0 OVR + DCD ADC1_SEQA_IRQHandler ; ADC1 SEQA + DCD ADC1_SEQB_IRQHandler ; ADC1 SEQB + DCD ADC1_THCMP_IRQHandler ; ADC1 THCMP + DCD ADC1_OVR_IRQHandler ; ADC1 OVR + DCD DAC_IRQHandler ; D/A Converter + DCD CMP0_IRQHandler ; Comparator 0 + DCD CMP1_IRQHandler ; Comparator 1 + DCD CMP2_IRQHandler ; Comparator 2 + DCD CMP3_IRQHandler ; Comparator 3 + DCD QEI_IRQHandler ; QEI + DCD RTC_ALARM_IRQHandler ; RTC Alarm + DCD RTC_WAKE_IRQHandler ; RTC Wake + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK MemManage_Handler + PUBWEAK BusFault_Handler + PUBWEAK UsageFault_Handler + PUBWEAK SVC_Handler + PUBWEAK DebugMon_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + PUBWEAK WDT_IRQHandler + PUBWEAK BOD_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EE_IRQHandler + PUBWEAK DMA_IRQHandler + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT1_IRQHandler + PUBWEAK PIN_INT0_IRQHandler + PUBWEAK PIN_INT1_IRQHandler + PUBWEAK PIN_INT2_IRQHandler + PUBWEAK PIN_INT3_IRQHandler + PUBWEAK PIN_INT4_IRQHandler + PUBWEAK PIN_INT5_IRQHandler + PUBWEAK PIN_INT6_IRQHandler + PUBWEAK PIN_INT7_IRQHandler + PUBWEAK RIT_IRQHandler + PUBWEAK SCT0_IRQHandler + PUBWEAK SCT1_IRQHandler + PUBWEAK SCT2_IRQHandler + PUBWEAK SCT3_IRQHandler + PUBWEAK MRT_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK UART2_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK C_CAN0_IRQHandler + PUBWEAK USB_IRQ_IRQHandler + PUBWEAK USB_FIQ_IRQHandler + PUBWEAK USBWakeup_IRQHandler + PUBWEAK ADC0_SEQA_IRQHandler + PUBWEAK ADC0_SEQB_IRQHandler + PUBWEAK ADC0_THCMP_IRQHandler + PUBWEAK ADC0_OVR_IRQHandler + PUBWEAK ADC1_SEQA_IRQHandler + PUBWEAK ADC1_SEQB_IRQHandler + PUBWEAK ADC1_THCMP_IRQHandler + PUBWEAK ADC1_OVR_IRQHandler + PUBWEAK DAC_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK CMP1_IRQHandler + PUBWEAK CMP2_IRQHandler + PUBWEAK CMP3_IRQHandler + PUBWEAK QEI_IRQHandler + PUBWEAK RTC_ALARM_IRQHandler + PUBWEAK RTC_WAKE_IRQHandler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB + +NMI_Handler +HardFault_Handler +MemManage_Handler +BusFault_Handler +UsageFault_Handler +SVC_Handler +DebugMon_Handler +PendSV_Handler +SysTick_Handler +WDT_IRQHandler +BOD_IRQHandler +FLASH_IRQHandler +EE_IRQHandler +DMA_IRQHandler +GINT0_IRQHandler +GINT1_IRQHandler +PIN_INT0_IRQHandler +PIN_INT1_IRQHandler +PIN_INT2_IRQHandler +PIN_INT3_IRQHandler +PIN_INT4_IRQHandler +PIN_INT5_IRQHandler +PIN_INT6_IRQHandler +PIN_INT7_IRQHandler +RIT_IRQHandler +SCT0_IRQHandler +SCT1_IRQHandler +SCT2_IRQHandler +SCT3_IRQHandler +MRT_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +C_CAN0_IRQHandler +USB_IRQ_IRQHandler +USB_FIQ_IRQHandler +USBWakeup_IRQHandler +ADC0_SEQA_IRQHandler +ADC0_SEQB_IRQHandler +ADC0_THCMP_IRQHandler +ADC0_OVR_IRQHandler +ADC1_SEQA_IRQHandler +ADC1_SEQB_IRQHandler +ADC1_THCMP_IRQHandler +ADC1_OVR_IRQHandler +DAC_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +CMP3_IRQHandler +QEI_IRQHandler +RTC_ALARM_IRQHandler +RTC_WAKE_IRQHandler +Default_Handler + B Default_Handler + + + SECTION .crp:CODE:ROOT(2) + DATA +/* Code Read Protection +CRP1 0x12345678 - Write to RAM command can not access RAM below 0x10000200. + - Read Memory command: disabled. + - Copy RAM to Flash command: cannot write to Sector 0. + - "Go" command: disabled. + - Erase sector(s) command: can erase any individual sector except + sector 0 only, or can erase all sectors at once. + - Compare command: disabled +CRP2 0x87654321 - Write to RAM command: disabled. + - Copy RAM to Flash: disabled. + - Erase command: only allows erase of all sectors. +CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry + by pulling PIO0_1 LOW is disabled if a valid user code is + present in flash sector 0. +Caution: If CRP3 is selected, no future factory testing can be +performed on the device. +*/ + DCD 0xFFFFFFFF + + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_IAR/LPC4088.icf b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_IAR/LPC4088.icf new file mode 100644 index 0000000000..d41b60ed85 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_IAR/LPC4088.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x1000FFDF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_heap__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __CRP_start__ = 0x000002FC; +define symbol __CRP_end__ = 0x000002FF; + +define symbol __RAM1_start__ = 0x20000000; +define symbol __RAM1_end__ = 0x20007FFF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; +define region RAM1_region = mem:[from __RAM1_start__ to __RAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in CRP_region { section .crp }; +place in RAM1_region { section .sram }; diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_IAR/startup_LPC408x.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_IAR/startup_LPC408x.s new file mode 100644 index 0000000000..9fc5ec6fb4 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_IAR/startup_LPC408x.s @@ -0,0 +1,256 @@ +/************************************************** + * + * Part one of the system initialization code, contains low-level + * initialization, plain thumb variant. + * + * Copyright 2011 IAR Systems. All rights reserved. + * + * $Revision: 47876 $ + * + **************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0xEFFFF39E ; Reserved- vector sum + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 16: Watchdog Timer + DCD TIMER0_IRQHandler ; 17: Timer0 + DCD TIMER1_IRQHandler ; 18: Timer1 + DCD TIMER2_IRQHandler ; 19: Timer2 + DCD TIMER3_IRQHandler ; 20: Timer3 + DCD UART0_IRQHandler ; 21: UART0 + DCD UART1_IRQHandler ; 22: UART1 + DCD UART2_IRQHandler ; 23: UART2 + DCD UART3_IRQHandler ; 24: UART3 + DCD PWM1_IRQHandler ; 25: PWM1 + DCD I2C0_IRQHandler ; 26: I2C0 + DCD I2C1_IRQHandler ; 27: I2C1 + DCD I2C2_IRQHandler ; 28: I2C2 + DCD 0 ; 29: reserved, not for SPIFI anymore + DCD SSP0_IRQHandler ; 30: SSP0 + DCD SSP1_IRQHandler ; 31: SSP1 + DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) + DCD RTC_IRQHandler ; 33: Real Time Clock + DCD EINT0_IRQHandler ; 34: External Interrupt 0 + DCD EINT1_IRQHandler ; 35: External Interrupt 1 + DCD EINT2_IRQHandler ; 36: External Interrupt 2 + DCD EINT3_IRQHandler ; 37: External Interrupt 3 + DCD ADC_IRQHandler ; 38: A/D Converter + DCD BOD_IRQHandler ; 39: Brown-Out Detect + DCD USB_IRQHandler ; 40: USB + DCD CAN_IRQHandler ; 41: CAN + DCD DMA_IRQHandler ; 42: General Purpose DMA + DCD I2S_IRQHandler ; 43: I2S + DCD ENET_IRQHandler ; 44: Ethernet + DCD MCI_IRQHandler ; 45: SD/MMC card I/F + DCD MCPWM_IRQHandler ; 46: Motor Control PWM + DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface + DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) + DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup + DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup + DCD UART4_IRQHandler ; 51: UART4 + DCD SSP2_IRQHandler ; 52: SSP2 + DCD LCD_IRQHandler ; 53: LCD + DCD GPIO_IRQHandler ; 54: GPIO + DCD PWM0_IRQHandler ; 55: PWM0 + DCD EEPROM_IRQHandler ; 56: EEPROM +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK MemManage_Handler + PUBWEAK BusFault_Handler + PUBWEAK UsageFault_Handler + PUBWEAK SVC_Handler + PUBWEAK DebugMon_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + PUBWEAK WDT_IRQHandler + PUBWEAK TIMER0_IRQHandler + PUBWEAK TIMER1_IRQHandler + PUBWEAK TIMER2_IRQHandler + PUBWEAK TIMER3_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK UART2_IRQHandler + PUBWEAK UART3_IRQHandler + PUBWEAK PWM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK I2C2_IRQHandler +;SPIFI_IRQHandler ;not used + PUBWEAK SSP0_IRQHandler + PUBWEAK SSP1_IRQHandler + PUBWEAK PLL0_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK EINT0_IRQHandler + PUBWEAK EINT1_IRQHandler + PUBWEAK EINT2_IRQHandler + PUBWEAK EINT3_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK BOD_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK CAN_IRQHandler + PUBWEAK DMA_IRQHandler + PUBWEAK I2S_IRQHandler + PUBWEAK ENET_IRQHandler + PUBWEAK MCI_IRQHandler + PUBWEAK MCPWM_IRQHandler + PUBWEAK QEI_IRQHandler + PUBWEAK PLL1_IRQHandler + PUBWEAK USBActivity_IRQHandler + PUBWEAK CANActivity_IRQHandler + PUBWEAK UART4_IRQHandler + PUBWEAK SSP2_IRQHandler + PUBWEAK LCD_IRQHandler + PUBWEAK GPIO_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK EEPROM_IRQHandler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB +NMI_Handler +HardFault_Handler +MemManage_Handler +BusFault_Handler +UsageFault_Handler +SVC_Handler +DebugMon_Handler +PendSV_Handler +SysTick_Handler +WDT_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +PWM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +;SPIFI_IRQHandler ;not used +SSP0_IRQHandler +SSP1_IRQHandler +PLL0_IRQHandler +RTC_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +ADC_IRQHandler +BOD_IRQHandler +USB_IRQHandler +CAN_IRQHandler +DMA_IRQHandler +I2S_IRQHandler +ENET_IRQHandler +MCI_IRQHandler +MCPWM_IRQHandler +QEI_IRQHandler +PLL1_IRQHandler +USBActivity_IRQHandler +CANActivity_IRQHandler +UART4_IRQHandler +SSP2_IRQHandler +LCD_IRQHandler +GPIO_IRQHandler +PWM0_IRQHandler +EEPROM_IRQHandler +Default_IRQHandler + B Default_IRQHandler + + SECTION .crp:CODE:ROOT(2) + DATA +/* Code Read Protection +NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode +CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. + - Copy RAM to flash command can not write to Sector 0. + - Erase command can erase Sector 0 only when all sectors + are selected for erase. + - Compare command is disabled. + - Read Memory command is disabled. +CRP2 0x87654321 - Read Memory is disabled. + - Write to RAM is disabled. + - "Go" command is disabled. + - Copy RAM to flash is disabled. + - Compare is disabled. +CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry + by pulling PIO0_1 LOW is disabled if a valid user code is + present in flash sector 0. +Caution: If CRP3 is selected, no future factory testing can be +performed on the device. +*/ + DCD 0xFFFFFFFF + + END \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_IAR/LPC810.icf b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_IAR/LPC810.icf new file mode 100644 index 0000000000..3018ad16e6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_IAR/LPC810.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00000FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x100003FF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x100; +define symbol __ICFEDIT_size_heap__ = 0x100; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __CRP_start__ = 0x000002FC; +define symbol __CRP_end__ = 0x000002FF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in CRP_region { section .crp }; diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_IAR/startup_LPC8xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_IAR/startup_LPC8xx.s new file mode 100644 index 0000000000..5ab3196850 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_IAR/startup_LPC8xx.s @@ -0,0 +1,197 @@ +/************************************************** + * + * Part one of the system initialization code, contains low-level + * initialization, plain thumb variant. + * + * Copyright 2011 IAR Systems. All rights reserved. + * + * $Revision: 47876 $ + * + **************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD SPI0_IRQHandler ; SPI0 controller + DCD SPI1_IRQHandler ; SPI1 controller + DCD 0 ; Reserved + DCD UART0_IRQHandler ; UART0 + DCD UART1_IRQHandler ; UART1 + DCD UART2_IRQHandler ; UART2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C_IRQHandler ; I2C controller + DCD SCT_IRQHandler ; Smart Counter Timer + DCD MRT_IRQHandler ; Multi-Rate Timer + DCD CMP_IRQHandler ; Comparator + DCD WDT_IRQHandler ; PIO1 (0:11) + DCD BOD_IRQHandler ; Brown Out Detect + DCD 0 ; Reserved + DCD WKT_IRQHandler ; Wakeup timer + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PININT0_IRQHandler ; PIO INT0 + DCD PININT1_IRQHandler ; PIO INT1 + DCD PININT2_IRQHandler ; PIO INT2 + DCD PININT3_IRQHandler ; PIO INT3 + DCD PININT4_IRQHandler ; PIO INT4 + DCD PININT5_IRQHandler ; PIO INT5 + DCD PININT6_IRQHandler ; PIO INT6 + DCD PININT7_IRQHandler ; PIO INT7 +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK SVC_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK UART2_IRQHandler + PUBWEAK I2C_IRQHandler + PUBWEAK SCT_IRQHandler + PUBWEAK MRT_IRQHandler + PUBWEAK CMP_IRQHandler + PUBWEAK WDT_IRQHandler + PUBWEAK BOD_IRQHandler + PUBWEAK WKT_IRQHandler + PUBWEAK PININT0_IRQHandler + PUBWEAK PININT1_IRQHandler + PUBWEAK PININT2_IRQHandler + PUBWEAK PININT3_IRQHandler + PUBWEAK PININT4_IRQHandler + PUBWEAK PININT5_IRQHandler + PUBWEAK PININT6_IRQHandler + PUBWEAK PININT7_IRQHandler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB +NMI_Handler +HardFault_Handler +SVC_Handler +PendSV_Handler +SysTick_Handler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +I2C_IRQHandler +SCT_IRQHandler +MRT_IRQHandler +CMP_IRQHandler +WDT_IRQHandler +BOD_IRQHandler +WKT_IRQHandler +PININT0_IRQHandler +PININT1_IRQHandler +PININT2_IRQHandler +PININT3_IRQHandler +PININT4_IRQHandler +PININT5_IRQHandler +PININT6_IRQHandler +PININT7_IRQHandler +Default_IRQHandler + B Default_IRQHandler + + SECTION .crp:CODE:ROOT(2) + DATA +/* Code Read Protection +NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode +CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. + - Copy RAM to flash command can not write to Sector 0. + - Erase command can erase Sector 0 only when all sectors + are selected for erase. + - Compare command is disabled. + - Read Memory command is disabled. +CRP2 0x87654321 - Read Memory is disabled. + - Write to RAM is disabled. + - "Go" command is disabled. + - Copy RAM to flash is disabled. + - Compare is disabled. +CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry + by pulling PIO0_1 LOW is disabled if a valid user code is + present in flash sector 0. +Caution: If CRP3 is selected, no future factory testing can be +performed on the device. +*/ + DCD 0xFFFFFFFF + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_IAR/LPC812.icf b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_IAR/LPC812.icf new file mode 100644 index 0000000000..8c19582224 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_IAR/LPC812.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00003FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x10000FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __CRP_start__ = 0x000002FC; +define symbol __CRP_end__ = 0x000002FF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in CRP_region { section .crp }; diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_IAR/startup_LPC8xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_IAR/startup_LPC8xx.s new file mode 100644 index 0000000000..48ead87f40 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_IAR/startup_LPC8xx.s @@ -0,0 +1,198 @@ +/************************************************** + * + * Part one of the system initialization code, contains low-level + * initialization, plain thumb variant. + * + * Copyright 2011 IAR Systems. All rights reserved. + * + * $Revision: 47876 $ + * + **************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD SPI0_IRQHandler ; SPI0 controller + DCD SPI1_IRQHandler ; SPI1 controller + DCD 0 ; Reserved + DCD UART0_IRQHandler ; UART0 + DCD UART1_IRQHandler ; UART1 + DCD UART2_IRQHandler ; UART2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C_IRQHandler ; I2C controller + DCD SCT_IRQHandler ; Smart Counter Timer + DCD MRT_IRQHandler ; Multi-Rate Timer + DCD CMP_IRQHandler ; Comparator + DCD WDT_IRQHandler ; PIO1 (0:11) + DCD BOD_IRQHandler ; Brown Out Detect + DCD 0 ; Reserved + DCD WKT_IRQHandler ; Wakeup timer + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PININT0_IRQHandler ; PIO INT0 + DCD PININT1_IRQHandler ; PIO INT1 + DCD PININT2_IRQHandler ; PIO INT2 + DCD PININT3_IRQHandler ; PIO INT3 + DCD PININT4_IRQHandler ; PIO INT4 + DCD PININT5_IRQHandler ; PIO INT5 + DCD PININT6_IRQHandler ; PIO INT6 + DCD PININT7_IRQHandler ; PIO INT7 +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK SVC_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK UART2_IRQHandler + PUBWEAK I2C_IRQHandler + PUBWEAK SCT_IRQHandler + PUBWEAK MRT_IRQHandler + PUBWEAK CMP_IRQHandler + PUBWEAK WDT_IRQHandler + PUBWEAK BOD_IRQHandler + PUBWEAK WKT_IRQHandler + PUBWEAK PININT0_IRQHandler + PUBWEAK PININT1_IRQHandler + PUBWEAK PININT2_IRQHandler + PUBWEAK PININT3_IRQHandler + PUBWEAK PININT4_IRQHandler + PUBWEAK PININT5_IRQHandler + PUBWEAK PININT6_IRQHandler + PUBWEAK PININT7_IRQHandler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB + +NMI_Handler +HardFault_Handler +SVC_Handler +PendSV_Handler +SysTick_Handler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +I2C_IRQHandler +SCT_IRQHandler +MRT_IRQHandler +CMP_IRQHandler +WDT_IRQHandler +BOD_IRQHandler +WKT_IRQHandler +PININT0_IRQHandler +PININT1_IRQHandler +PININT2_IRQHandler +PININT3_IRQHandler +PININT4_IRQHandler +PININT5_IRQHandler +PININT6_IRQHandler +PININT7_IRQHandler +Default_IRQHandler + B Default_IRQHandler + + SECTION .crp:CODE:ROOT(2) + DATA +/* Code Read Protection +NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode +CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. + - Copy RAM to flash command can not write to Sector 0. + - Erase command can erase Sector 0 only when all sectors + are selected for erase. + - Compare command is disabled. + - Read Memory command is disabled. +CRP2 0x87654321 - Read Memory is disabled. + - Write to RAM is disabled. + - "Go" command is disabled. + - Copy RAM to flash is disabled. + - Compare is disabled. +CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry + by pulling PIO0_1 LOW is disabled if a valid user code is + present in flash sector 0. +Caution: If CRP3 is selected, no future factory testing can be +performed on the device. +*/ + DCD 0xFFFFFFFF + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c index 47f7e81ea1..0035c49ea0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c @@ -73,6 +73,16 @@ extern uint32_t Image$$RW_DATA$$Base; extern uint32_t Image$$ZI_DATA$$Base; extern uint32_t Image$$TTB$$ZI$$Base; +extern uint32_t Image$$VECTORS$$Limit; +extern uint32_t Image$$RO_DATA$$Limit; +extern uint32_t Image$$RW_DATA$$Limit; +extern uint32_t Image$$ZI_DATA$$Limit; + +#define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1) +#define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1) +#define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1) +#define ZI_DATA_SIZE (((uint32_t)&Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA$$Base >> 20) + 1) + static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0 static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 @@ -133,11 +143,11 @@ void create_translation_table(void) __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW); //Define Image - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, 1, Sect_Normal_RO); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 1, Sect_Normal_Cod); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO); + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod); + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW); + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC); /* Set location of level 1 page table ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c index 81e69fd88d..d5d40fd3ef 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c @@ -230,6 +230,8 @@ void SystemInit (void) /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ /* Configure the Flash Latency cycles and enable prefetch buffer */ SetSysClock(); + + SystemCoreClockUpdate(); } /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_GCC_ARM/STM32F302X8_FLASH.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_GCC_ARM/STM32F302X8_FLASH.ld new file mode 100644 index 0000000000..227a5ded06 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_GCC_ARM/STM32F302X8_FLASH.ld @@ -0,0 +1,167 @@ +/* +***************************************************************************** +** +** File : STM32F302X8_FLASH.ld +** +** Abstract : Linker script for STM32F302x8 device with +** 64-KByte FLASH, 16-KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Environment : Atollic TrueSTUDIO(R) +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +** (c)Copyright Atollic AB. +** You may use this file as-is or modify it according to the needs of your +** project. This file may only be built (assembled or compiled and linked) +** using the Atollic TrueSTUDIO(R) product. The use of this file together +** with other tools than Atollic TrueSTUDIO(R) is not permitted. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20003FFF; /* end of RAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64K +RAM (xrw) : ORIGIN = 0x20000188, LENGTH = 16K - 0x188 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + PROVIDE ( __end__ = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_GCC_ARM/startup_stm32f302x8.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_GCC_ARM/startup_stm32f302x8.s new file mode 100644 index 0000000000..18c4997a6c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_GCC_ARM/startup_stm32f302x8.s @@ -0,0 +1,423 @@ +/** + ****************************************************************************** + * @file startup_stm32f302x8.s + * @author MCD Application Team + * @version V2.0.1 + * @date 18-June-2014 + * @brief STM32F302x6/STM32F302x8 devices vector table for + * Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Atollic update: set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_TSC_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_CAN_TX_IRQHandler + .word USB_LP_CAN_RX0_IRQHandler + .word CAN_RX1_IRQHandler + .word CAN_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word 0 + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word 0 + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SPI3_IRQHandler + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word COMP2_IRQHandler + .word COMP4_6_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word USBWakeUp_RMP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word FPU_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_TSC_IRQHandler + .thumb_set EXTI2_TSC_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_CAN_TX_IRQHandler + .thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN_RX0_IRQHandler + .thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler + + .weak CAN_RX1_IRQHandler + .thumb_set CAN_RX1_IRQHandler,Default_Handler + + .weak CAN_SCE_IRQHandler + .thumb_set CAN_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak COMP2_IRQHandler + .thumb_set COMP2_IRQHandler,Default_Handler + + .weak COMP4_6_IRQHandler + .thumb_set COMP4_6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak USBWakeUp_RMP_IRQHandler + .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_GCC_ARM/STM32L152XE_FLASH.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_GCC_ARM/STM32L152XE_FLASH.ld new file mode 100644 index 0000000000..db82509d0a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_GCC_ARM/STM32L152XE_FLASH.ld @@ -0,0 +1,167 @@ +/* +***************************************************************************** +** +** File : STM32L152XE_FLASH.ld +** +** Abstract : Linker script for STM32L152XE Device with +** 512KByte FLASH, 80KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Environment : Atollic TrueSTUDIO(R) +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +** (c)Copyright Atollic AB. +** You may use this file as-is or modify it according to the needs of your +** project. This file may only be built (assembled or compiled and linked) +** using the Atollic TrueSTUDIO(R) product. The use of this file together +** with other tools than Atollic TrueSTUDIO(R) is not permitted. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20013FFF; /* end of RAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K +RAM (xrw) : ORIGIN = 0x2000013C, LENGTH = 80K - 0x13C +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + PROVIDE ( __end__ = .); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_GCC_ARM/startup_stm32l152xe.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_GCC_ARM/startup_stm32l152xe.s new file mode 100644 index 0000000000..d37ec08c9c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_GCC_ARM/startup_stm32l152xe.s @@ -0,0 +1,427 @@ +/** + ****************************************************************************** + * @file startup_stm32l152xe.s + * @author MCD Application Team + * @version V2.0.0 + * @date 5-September-2014 + * @brief STM32L152XE Devices vector table for + * Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word DAC_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word LCD_IRQHandler + .word TIM9_IRQHandler + .word TIM10_IRQHandler + .word TIM11_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USB_FS_WKUP_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word COMP_ACQ_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32L152XE devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak TIM10_IRQHandler + .thumb_set TIM10_IRQHandler,Default_Handler + + .weak TIM11_IRQHandler + .thumb_set TIM11_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USB_FS_WKUP_IRQHandler + .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak COMP_ACQ_IRQHandler + .thumb_set COMP_ACQ_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c index f5d9f6e2b6..e88d27d6a9 100755 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c @@ -29,13 +29,14 @@ static uint32_t serial_irq_ids[UART_NUM] = {0}; static uart_irq_handler irq_handler; -static uint32_t acceptedSpeeds[16][2] = {{1200, UART_BAUDRATE_BAUDRATE_Baud1200}, +static uint32_t acceptedSpeeds[17][2] = {{1200, UART_BAUDRATE_BAUDRATE_Baud1200}, {2400, UART_BAUDRATE_BAUDRATE_Baud2400}, {4800, UART_BAUDRATE_BAUDRATE_Baud4800}, {9600, UART_BAUDRATE_BAUDRATE_Baud9600}, {14400, UART_BAUDRATE_BAUDRATE_Baud14400}, {19200, UART_BAUDRATE_BAUDRATE_Baud19200}, {28800, UART_BAUDRATE_BAUDRATE_Baud28800}, + {31250, (0x00800000UL) /* 31250 baud */}, {38400, UART_BAUDRATE_BAUDRATE_Baud38400}, {57600, UART_BAUDRATE_BAUDRATE_Baud57600}, {76800, UART_BAUDRATE_BAUDRATE_Baud76800}, @@ -109,7 +110,7 @@ void serial_baud(serial_t *obj, int baudrate) return; } - for (int i = 1; i<16; i++) { + for (int i = 1; i<17; i++) { if (baudrateuart->BAUDRATE = acceptedSpeeds[i - 1][1]; return; diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c index 8307996f9f..cafb21ed16 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c @@ -31,7 +31,9 @@ static const PinMap PinMap_ADC[] = { {P1_9, AN1, 1}, {P1_10, AN2, 1}, {P1_11, AN3, 1}, + {P1_12, AN3, 1}, {P1_13, AN5, 1}, + {P1_14, AN5, 1}, {P1_15, AN7, 1}, {NC, NC, 0} }; @@ -56,19 +58,25 @@ void analogin_init(analogin_t *obj, PinName pin) { CPGSTBCR3 &= ~(1 << 1); CPGSTBCR6 &= ~(1 << 7); - // 000_0 000_1 11_00 0_xxx + // 000_0 000_1 00_00 0_xxx // 15: ADFlag 14: IntEn 13: start, [12:9] Triger..0 // [8:6] CLK 100 :: 12-bit 1054tclk // [5:3] scanmode 000 :: single mode // [2:0] channel select - ADCADCSR = 0x0100 | (obj->adc&0xf); + ADCADCSR = 0x01c0 ; - pinmap_pinout(pin, PinMap_ADC); + for (int i = 0; i< sizeof(PinMap_ADC)/sizeof(PinMap); i++) { + pinmap_pinout(PinMap_ADC[i].pin, PinMap_ADC); + } + + //pinmap_pinout(pin, PinMap_ADC); } static inline uint32_t adc_read(analogin_t *obj) { // Select the appropriate channel and start conversion - ADCADCSR |= (1 << 13 | (obj->adc&0xf)); + + ADCADCSR &= 0xfff8; + ADCADCSR |= (1 << 13 | (obj->adc&0x7)); // Repeatedly get the sample data until DONE bit #define nothing diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c new file mode 100644 index 0000000000..a07770a297 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c @@ -0,0 +1,158 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "gpio_irq_api.h" +#include "intc_iodefine.h" +#include "pinmap.h" +#include "cmsis.h" + +#define CHANNEL_NUM 8 + +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler irq_handler; +static const int nIRQn_h = 32; +extern PinName gpio_multi_guard; + +enum { + IRQ0,IRQ1, + IRQ2,IRQ3, + IRQ4,IRQ5, + IRQ6,IRQ7, + +} IRQNo; + +static const PinMap PinMap_IRQ[] = { + {P1_0, IRQ0, 4}, {P1_1, IRQ1, 4}, {P1_2, IRQ2, 4}, + {P1_3, IRQ3, 4}, {P1_5, IRQ5, 4}, {P1_7, IRQ7, 4}, + {P1_8, IRQ2, 3}, {P1_9, IRQ3, 3}, {P1_10, IRQ4, 3}, + {P1_11, IRQ5, 3}, // 9 + {P2_0, IRQ5, 6}, {P2_13, IRQ7, 8}, {P2_14, IRQ0, 8}, + {P2_15, IRQ1, 8}, // 13 + {P3_0, IRQ2, 3}, {P3_3, IRQ4, 3}, // 15 + {P4_8, IRQ0, 8}, {P4_9, IRQ1, 8}, {P4_10, IRQ2, 8}, + {P4_11, IRQ3, 8}, {P4_12, IRQ4, 8}, {P4_13, IRQ5, 8}, + {P4_14, IRQ6, 8}, {P4_15, IRQ7, 8}, // 23 + {P5_6, IRQ6, 6}, {P5_8, IRQ0, 2}, {P5_9, IRQ2, 4}, // 26 + {P6_0, IRQ5, 6}, {P6_1, IRQ4, 4}, {P6_2, IRQ7, 4}, + {P6_3, IRQ2, 4}, {P6_4, IRQ3, 4}, {P6_8, IRQ0, 8}, + {P6_9, IRQ1, 8}, {P6_10, IRQ2, 8}, {P6_11, IRQ3, 8}, + {P6_12, IRQ4, 8}, {P6_13, IRQ5, 8}, {P6_14, IRQ6, 8}, + {P6_15, IRQ7, 8}, // 39 + {P7_8, IRQ1, 8}, {P7_9, IRQ0, 8}, {P7_10, IRQ2, 8}, + {P7_11, IRQ3, 8}, {P7_12, IRQ4, 8}, {P7_13, IRQ5, 8}, + {P7_14, IRQ6, 8}, // 46 + {P8_2, IRQ0, 5}, {P8_3, IRQ1, 6}, {P8_7, IRQ5, 4}, + {P9_1, IRQ0, 4}, // 50 + {P11_12,IRQ3, 3}, {P11_15,IRQ1, 3}, // 52 + + {NC, NC, 0} +}; + +static gpio_irq_event irq_event; + +static void handle_interrupt_in(void) { + int i; + uint16_t irqs; + int irq_num; + + irqs = INTCIRQRR; + for(i = 0; i< 8; i++) { + if (channel_ids[i] && (irqs & (1 << i))) { + irq_handler(channel_ids[i], irq_event); + INTCIRQRR &= ~(1 << i); + irq_num = i; + } + } + GIC_EndInterrupt((IRQn_Type)(nIRQn_h + irq_num)); +} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { + int shift; + if (pin == NC) return -1; + + obj->ch = pinmap_peripheral(pin, PinMap_IRQ); + obj->pin = (int)pin ; + obj->port = (int)id ; + + shift = obj->ch*2; + channel_ids[obj->ch] = id; + irq_handler = handler; + + pinmap_pinout(pin, PinMap_IRQ); + gpio_multi_guard = pin; /* Set multi guard */ + + // INTC settings + InterruptHandlerRegister((IRQn_Type)(nIRQn_h+obj->ch), (void (*)(uint32_t))handle_interrupt_in); + INTCICR1 &= ~(0x3 << shift); + INTCICR1 |= (0x3 << shift); + irq_event = IRQ_RISE; + GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5); + GIC_EnableIRQ((IRQn_Type)(nIRQn_h+obj->ch)); + __enable_irq(); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) { + channel_ids[obj->ch] = 0; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { + int shift = obj->ch*2; + uint16_t val = event == IRQ_RISE ? 2 : + event == IRQ_FALL ? 1 : 0; + uint16_t work_icr_val; + uint16_t work_irqrr_val; + + /* check edge interrupt setting */ + work_icr_val = INTCICR1; + if (enable == 1) { + /* Set interrupt serect */ + work_icr_val |= (val << shift); + } else { + /* Clear interrupt serect */ + work_icr_val &= ~(val << shift); + } + + if ((work_icr_val & (3 << shift)) == 0) { + /* No edge interrupt setting */ + GIC_DisableIRQ((IRQn_Type)(nIRQn_h+obj->ch)); + /* Clear Interrupt flags */ + work_irqrr_val = INTCIRQRR; + INTCIRQRR = (work_irqrr_val & ~(1 << obj->ch)); + } else { + /* Edge interrupt setting */ + if ((work_icr_val & (3 << shift)) == 2) { + /* Setting of rising edge */ + irq_event = IRQ_RISE; + } else { + /* Setting of falling edge of both edge */ + irq_event = IRQ_FALL; + } + GIC_EnableIRQ((IRQn_Type)(nIRQn_h+obj->ch)); + } + INTCICR1 = work_icr_val; +} + +void gpio_irq_enable(gpio_irq_t *obj) { + GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch)); +} + +void gpio_irq_disable(gpio_irq_t *obj) { + GIC_DisableIRQ((IRQn_Type)(nIRQn_h + obj->ch)); +} + diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c index 0ec6bc68e2..13fceaa58e 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c @@ -61,17 +61,51 @@ static inline void i2c_wait_RDRF(i2c_t *obj) { while (!(i2c_status(obj) & (1 << 5))) ; } +static void i2c_reg_reset(i2c_t *obj) { + // full reset + REG(CR1.UINT8[0]) &= ~(1 << 7); // CR1.ICE off + REG(CR1.UINT8[0]) |= (1 << 6); // CR1.IICRST on + REG(CR1.UINT8[0]) |= (1 << 7); // CR1.ICE on + + REG(MR1.UINT8[0]) = 0x08; // P_phi /8 9bit (including Ack) + REG(SER.UINT8[0]) = 0x00; // no slave addr enabled + + // set default frequency at 100k + i2c_frequency(obj, 100000); + + REG(MR2.UINT8[0]) = 0x07; + REG(MR3.UINT8[0]) = 0x00; + + REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT + REG(IER.UINT8[0]) = 0x00; // no interrupt + + REG(CR1.UINT32) &= ~(1 << 6); // CR1.IICRST negate reset +} + // Wait until the Trans Data Empty (TDRE) is set static int i2c_wait_TDRE(i2c_t *obj) { int timeout = 0; while (!(i2c_status(obj) & (1 << 7))) { + timeout ++; if (timeout > 100000) return -1; } return 0; } +static inline int i2c_wait_TEND(i2c_t *obj) { + int timeout = 0; + + while (!(i2c_status(obj) & (1 << 6))) { + timeout ++; + if (timeout > 100000) return -1; + } + + return 0; +} + + static inline void i2c_power_enable(i2c_t *obj) { volatile uint8_t dummy; switch ((int)obj->i2c) { @@ -90,29 +124,13 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) { obj->i2c = pinmap_merge(i2c_sda, i2c_scl); obj->dummy = 1; MBED_ASSERT((int)obj->i2c != NC); - + // enable power i2c_power_enable(obj); - + // full reset - REG(CR1.UINT8[0]) &= ~(1 << 7); // CR1.ICE off - REG(CR1.UINT8[0]) |= (1 << 6); // CR1.IICRST on - REG(CR1.UINT8[0]) |= (1 << 7); // CR1.ICE on + i2c_reg_reset(obj); - REG(MR1.UINT8[0]) = 0x08; // P_phi /8 9bit (including Ack) - REG(SER.UINT8[0]) = 0x00; // no slave addr enabled - - // set default frequency at 100k - i2c_frequency(obj, 100000); - - REG(MR2.UINT8[0]) = 0x07; - REG(MR3.UINT8[0]) = 0x00; - - REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT - REG(IER.UINT8[0]) = 0x00; // no interrupt - - REG(CR1.UINT32) &= ~(1 << 6); // CR1.IICRST negate reset - pinmap_pinout(sda, PinMap_I2C_SDA); pinmap_pinout(scl, PinMap_I2C_SCL); } @@ -127,11 +145,11 @@ inline int i2c_start(i2c_t *obj) { } inline int i2c_stop(i2c_t *obj) { - int timeout = 0; + volatile int timeout = 0; // write the stop bit REG(CR2.UINT32) |= (1 << 3); - + // wait for SP bit to reset while(REG(CR2.UINT32) & (1 << 3)) { timeout ++; @@ -159,91 +177,140 @@ static inline int i2c_do_read(i2c_t *obj, int last) { volatile int dummy = REG(DRR.UINT32); obj->dummy = 0; } - if (last) { - // send a NOT ACK - REG(MR2.UINT32) |= (1 <<6); - } else { - // send a ACK - REG(MR2.UINT32) &= ~(1 <<6); - } + // wait for it to arrive i2c_wait_RDRF(obj); - + + if (last == 2) { + /* this time is befor last byte read */ + /* Set MR3 WATI bit is 1 */; + REG(MR3.UINT32) |= (1 << 6); + } else if (last == 1) { + // send a NOT ACK + REG(MR3.UINT32) |= (1 <<3); + } else { + // send a ACK + REG(MR3.UINT32) &= ~(1 <<3); + } + // return the data return (REG(DRR.UINT32) & 0xFF); } void i2c_frequency(i2c_t *obj, int hz) { uint32_t PCLK = 6666666; - + uint32_t pulse = PCLK / (hz * 2); - + // I2C Rate REG(BRL.UINT32) = pulse; REG(BRH.UINT32) = pulse; } int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { - int count, status; - + int count = 0; + int status; + int value; + volatile uint32_t work_reg = 0; + + + // full reset + i2c_reg_reset(obj); + status = i2c_start(obj); - + if (status == 0xff) { i2c_stop(obj); return I2C_ERROR_BUS_BUSY; } - + status = i2c_do_write(obj, (address | 0x01)); if (status & 0x01) { i2c_stop(obj); return I2C_ERROR_NO_SLAVE; } - - // Read in all except last byte - for (count = 0; count < (length - 1); count++) { - int value = i2c_do_read(obj, 0); - status = i2c_status(obj); - if (status & 0x10) { - i2c_stop(obj); - return count; - } - data[count] = (char) value; + + /* wati RDRF */ + i2c_wait_RDRF(obj); + /* check ACK/NACK */ + if ((REG(SR2.UINT32) & (1 << 4) == 1)) { + /* Slave sends NACK */ + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; } + // Read in all except last byte + if (length > 1) { + for (count = 0; count < (length - 1); count++) { + if (count == (length - 2)) { + value = i2c_do_read(obj, 1); + } else if ((length >= 3) && (count == (length - 3))) { + value = i2c_do_read(obj, 2); + } else { + value = i2c_do_read(obj, 0); + } + status = i2c_status(obj); + if (status & 0x10) { + i2c_stop(obj); + return count; + } + data[count] = (char) value; + } + } + // read in last byte - int value = i2c_do_read(obj, 1); + i2c_wait_RDRF(obj); + /* RIICnSR2.STOP = 0 */ + REG(SR2.UINT32) &= ~(1 << 3); + /* RIICnCR2.SP = 1 */ + REG(CR2.UINT32) |= (1 << 3); + /* RIICnDRR read */ + value = REG(DRR.UINT32) & 0xFF; + /* RIICnMR3.WAIT = 0 */ + REG(MR3.UINT32) &= ~(1 << 6); + /* wait SR2.STOP = 1 */ + while ((work_reg & (1 << 3)) == (1 << 3)) { + work_reg = REG(SR2.UINT32); + } + /* SR2.NACKF = 0 */ + REG(SR2.UINT32) &= ~(1 << 4); + /* SR2.STOP = 0 */ + REG(SR2.UINT32) &= ~(1 << 3); status = i2c_status(obj); if (status & 0x10) { i2c_stop(obj); return length - 1; } - + data[count] = (char) value; - + // If not repeated start, send stop. if (stop) { i2c_stop(obj); } - + return length; } int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { int i, status; - + + // full reset + i2c_reg_reset(obj); + status = i2c_start(obj); - + if ((status == 0xff)) { i2c_stop(obj); return I2C_ERROR_BUS_BUSY; } - + status = i2c_do_write(obj, address); if (status & 0x10) { i2c_stop(obj); return I2C_ERROR_NO_SLAVE; } - + for (i=0; idummy = 0; } - + do { i2c_wait_RDRF(obj); status = i2c_status(obj); @@ -320,35 +389,35 @@ int i2c_slave_read(i2c_t *obj, char *data, int length) { } count++; } while ( !(status & 0x10) && (count < length) ); - + if(status & 0x10) { i2c_stop(obj); } - + //i2c_clear_TDRE(obj); - + return count; } int i2c_slave_write(i2c_t *obj, const char *data, int length) { int count = 0; int status; - + if(length <= 0) { return(0); } - + do { status = i2c_do_write(obj, data[count]); count++; } while ((count < length) && !(status & 0x10)); - + if (!(status & 0x10)) { i2c_stop(obj); } - + i2c_clear_TDRE(obj); - + return(count); } diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c index 4480b83a73..8690a203ac 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c @@ -17,28 +17,34 @@ #include "mbed_error.h" #include "gpio_addrdefine.h" +PinName gpio_multi_guard = (PinName)NC; /* If set pin name here, setting of the "pin" is just one time */ + void pin_function(PinName pin, int function) { if (pin == (PinName)NC) return; int n = pin >> 4; int bitmask = 1<<(pin & 0xf); - if (function == 0) { - // means GPIO mode - *PMC(n) &= ~bitmask; - } else { - // alt-function mode - *PMC(n) |= bitmask; - --function; + if (gpio_multi_guard != pin) { + if (function == 0) { + // means GPIO mode + *PMC(n) &= ~bitmask; + } else { + // alt-function mode + *PMC(n) |= bitmask; + --function; - if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else { *PFCAE(n) &= ~bitmask;} - if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else { *PFCE(n) &= ~bitmask;} - if (function & (1 << 0)) { *PFC(n) |= bitmask;}else { *PFC(n) &= ~bitmask;} - *PIPC(n) |= bitmask; + if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else { *PFCAE(n) &= ~bitmask;} + if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else { *PFCE(n) &= ~bitmask;} + if (function & (1 << 0)) { *PFC(n) |= bitmask;}else { *PFC(n) &= ~bitmask;} + *PIPC(n) |= bitmask; - if (P1_0 <= pin && pin <= P1_7 && function == 0) { - *PBDC(n) |= bitmask; + if (P1_0 <= pin && pin <= P1_7 && function == 0) { + *PBDC(n) |= bitmask; + } } + } else { + gpio_multi_guard = (PinName)NC; } } diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c index d738af2c41..4f219ff48c 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c @@ -142,7 +142,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { b0 SPB2DT - Serial port break data : High-level */ //obj->uart->SCSPTR |= 0x0000u; - obj->uart->SCSCR = 0x0030; + obj->uart->SCSCR = 0x00F0; // pinout the chosen uart pinmap_pinout(tx, PinMap_UART_TX); @@ -156,10 +156,11 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { case P_SCIF4: obj->index = 4; break; case P_SCIF5: obj->index = 5; break; case P_SCIF6: obj->index = 6; break; + case P_SCIF7: obj->index = 7; break; } uart_data[obj->index].sw_rts.pin = NC; uart_data[obj->index].sw_cts.pin = NC; - serial_set_flow_control(obj, FlowControlNone, NC, NC); +// serial_set_flow_control(obj, FlowControlNone, NC, NC); is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); @@ -219,11 +220,105 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b * INTERRUPTS HANDLING ******************************************************************************/ -void uart0_irq() {irq_handler(0, RxIrq);//dummy call +static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) { + uint16_t dummy_read; + /* Clear TDFE */ + switch (index) { + case 0: + dummy_read = SCFSR_0; + SCFSR_0 = (dummy_read & ~0x0060); + break; + case 1: + dummy_read = SCFSR_1; + SCFSR_1 = (dummy_read & ~0x0060); + break; + case 2: + dummy_read = SCFSR_2; + SCFSR_2 = (dummy_read & ~0x0060); + break; + case 3: + dummy_read = SCFSR_3; + SCFSR_3 = (dummy_read & ~0x0060); + break; + case 4: + dummy_read = SCFSR_4; + SCFSR_4 = (dummy_read & ~0x0060); + break; + case 5: + dummy_read = SCFSR_5; + SCFSR_5 = (dummy_read & ~0x0060); + break; + case 6: + dummy_read = SCFSR_6; + SCFSR_6 = (dummy_read & ~0x0060); + break; + case 7: + dummy_read = SCFSR_7; + SCFSR_7 = (dummy_read & ~0x0060); + break; } -void uart1_irq() {/*uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1, (LPC_UART_TypeDef*)LPC_UART1);*/} -void uart2_irq() {/*uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2, (LPC_UART_TypeDef*)LPC_UART2);*/} -void uart3_irq() {/*uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3, (LPC_UART_TypeDef*)LPC_UART3);*/} + irq_handler(uart_data[index].serial_irq_id, TxIrq); + GIC_EndInterrupt(irq_num); +} + +static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) { + uint16_t dummy_read; + /* Clear RDF */ + switch (index) { + case 0: + dummy_read = SCFSR_0; + SCFSR_0 = (dummy_read & ~0x0003); + break; + case 1: + dummy_read = SCFSR_1; + SCFSR_1 = (dummy_read & ~0x0003); + break; + case 2: + dummy_read = SCFSR_2; + SCFSR_2 = (dummy_read & ~0x0003); + break; + case 3: + dummy_read = SCFSR_3; + SCFSR_3 = (dummy_read & ~0x0003); + break; + case 4: + dummy_read = SCFSR_4; + SCFSR_4 = (dummy_read & ~0x0003); + break; + case 5: + dummy_read = SCFSR_5; + SCFSR_5 = (dummy_read & ~0x0003); + break; + case 6: + dummy_read = SCFSR_6; + SCFSR_6 = (dummy_read & ~0x0003); + break; + case 7: + dummy_read = SCFSR_7; + SCFSR_7 = (dummy_read & ~0x0003); + break; + } + irq_handler(uart_data[index].serial_irq_id, RxIrq); + GIC_EndInterrupt(irq_num); +} +/* TX handler */ +void uart0_tx_irq() {uart_tx_irq(SCIFTXI0_IRQn, 0);} +void uart1_tx_irq() {uart_tx_irq(SCIFTXI1_IRQn, 1);} +void uart2_tx_irq() {uart_tx_irq(SCIFTXI2_IRQn, 2);} +void uart3_tx_irq() {uart_tx_irq(SCIFTXI3_IRQn, 3);} +void uart4_tx_irq() {uart_tx_irq(SCIFTXI4_IRQn, 4);} +void uart5_tx_irq() {uart_tx_irq(SCIFTXI5_IRQn, 5);} +void uart6_tx_irq() {uart_tx_irq(SCIFTXI6_IRQn, 6);} +void uart7_tx_irq() {uart_tx_irq(SCIFTXI7_IRQn, 7);} +/* RX handler */ +void uart0_rx_irq() {uart_rx_irq(SCIFRXI0_IRQn, 0);} +void uart1_rx_irq() {uart_rx_irq(SCIFRXI1_IRQn, 1);} +void uart2_rx_irq() {uart_rx_irq(SCIFRXI2_IRQn, 2);} +void uart3_rx_irq() {uart_rx_irq(SCIFRXI3_IRQn, 3);} +void uart4_rx_irq() {uart_rx_irq(SCIFRXI4_IRQn, 4);} +void uart5_rx_irq() {uart_rx_irq(SCIFRXI5_IRQn, 5);} +void uart6_rx_irq() {uart_rx_irq(SCIFRXI6_IRQn, 6);} +void uart7_rx_irq() {uart_rx_irq(SCIFRXI7_IRQn, 7);} void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { irq_handler = handler; @@ -231,27 +326,72 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { } static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { -/* IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - switch ((int)obj->uart) { - case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break; - case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break; - case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break; - case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break; + switch (obj->index){ + case 0: + InterruptHandlerRegister(SCIFTXI0_IRQn, (void (*)(uint32_t))uart0_tx_irq); + InterruptHandlerRegister(SCIFRXI0_IRQn, (void (*)(uint32_t))uart0_rx_irq); + GIC_SetPriority(SCIFTXI0_IRQn, 5); + GIC_SetPriority(SCIFRXI0_IRQn, 5); + GIC_EnableIRQ(SCIFTXI0_IRQn); + GIC_EnableIRQ(SCIFRXI0_IRQn); + break; + case 1: + InterruptHandlerRegister(SCIFTXI1_IRQn, (void (*)(uint32_t))uart1_tx_irq); + InterruptHandlerRegister(SCIFRXI1_IRQn, (void (*)(uint32_t))uart1_rx_irq); + GIC_SetPriority(SCIFTXI1_IRQn, 5); + GIC_SetPriority(SCIFRXI1_IRQn, 5); + GIC_EnableIRQ(SCIFTXI1_IRQn); + GIC_EnableIRQ(SCIFRXI1_IRQn); + break; + case 2: + InterruptHandlerRegister(SCIFTXI2_IRQn, (void (*)(uint32_t))uart2_tx_irq); + InterruptHandlerRegister(SCIFRXI2_IRQn, (void (*)(uint32_t))uart2_rx_irq); + GIC_SetPriority(SCIFTXI2_IRQn, 5); + GIC_SetPriority(SCIFRXI2_IRQn, 5); + GIC_EnableIRQ(SCIFTXI2_IRQn); + GIC_EnableIRQ(SCIFRXI2_IRQn); + break; + case 3: + InterruptHandlerRegister(SCIFTXI3_IRQn, (void (*)(uint32_t))uart3_tx_irq); + InterruptHandlerRegister(SCIFRXI3_IRQn, (void (*)(uint32_t))uart3_rx_irq); + GIC_SetPriority(SCIFTXI3_IRQn, 5); + GIC_SetPriority(SCIFRXI3_IRQn, 5); + GIC_EnableIRQ(SCIFTXI3_IRQn); + GIC_EnableIRQ(SCIFRXI3_IRQn); + break; + case 4: + InterruptHandlerRegister(SCIFTXI4_IRQn, (void (*)(uint32_t))uart4_tx_irq); + InterruptHandlerRegister(SCIFRXI4_IRQn, (void (*)(uint32_t))uart4_rx_irq); + GIC_SetPriority(SCIFTXI4_IRQn, 5); + GIC_SetPriority(SCIFRXI4_IRQn, 5); + GIC_EnableIRQ(SCIFTXI4_IRQn); + GIC_EnableIRQ(SCIFRXI4_IRQn); + break; + case 5: + InterruptHandlerRegister(SCIFTXI5_IRQn, (void (*)(uint32_t))uart5_tx_irq); + InterruptHandlerRegister(SCIFRXI5_IRQn, (void (*)(uint32_t))uart5_rx_irq); + GIC_SetPriority(SCIFTXI5_IRQn, 5); + GIC_SetPriority(SCIFRXI5_IRQn, 5); + GIC_EnableIRQ(SCIFTXI5_IRQn); + GIC_EnableIRQ(SCIFRXI5_IRQn); + break; + case 6: + InterruptHandlerRegister(SCIFTXI6_IRQn, (void (*)(uint32_t))uart6_tx_irq); + InterruptHandlerRegister(SCIFRXI6_IRQn, (void (*)(uint32_t))uart6_rx_irq); + GIC_SetPriority(SCIFTXI6_IRQn, 5); + GIC_SetPriority(SCIFRXI6_IRQn, 5); + GIC_EnableIRQ(SCIFTXI6_IRQn); + GIC_EnableIRQ(SCIFRXI6_IRQn); + break; + case 7: + InterruptHandlerRegister(SCIFTXI7_IRQn, (void (*)(uint32_t))uart7_tx_irq); + InterruptHandlerRegister(SCIFRXI7_IRQn, (void (*)(uint32_t))uart7_rx_irq); + GIC_SetPriority(SCIFTXI7_IRQn, 5); + GIC_SetPriority(SCIFRXI7_IRQn, 5); + GIC_EnableIRQ(SCIFTXI7_IRQn); + GIC_EnableIRQ(SCIFRXI7_IRQn); + break; } - - if (enable) { - obj->uart->IER |= 1 << irq; - //NVIC_SetVector(irq_n, vector); - //NVIC_EnableIRQ(irq_n); - } else if ((TxIrq == irq) || (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable - int all_disabled = 0; - SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); - obj->uart->IER &= ~(1 << irq); - all_disabled = (obj->uart->IER & (1 << other_irq)) == 0; - if (all_disabled) ; - //NVIC_DisableIRQ(irq_n); - }*/ } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { diff --git a/libraries/tests/mbed/interruptin/main.cpp b/libraries/tests/mbed/interruptin/main.cpp index dddbd6f9b4..54527db47b 100644 --- a/libraries/tests/mbed/interruptin/main.cpp +++ b/libraries/tests/mbed/interruptin/main.cpp @@ -53,6 +53,11 @@ void in_handler() { #define PIN_OUT PC_12 #define PIN_IN PD_0 +#elif defined(TARGET_RZ_A1H) +#define PIN_OUT D1 +#define PIN_IN D5 + + #elif defined(TARGET_FF_ARDUINO) #define PIN_OUT D0 #define PIN_IN D7 diff --git a/libraries/tests/net/helloworld/tcpclient/main.cpp b/libraries/tests/net/helloworld/tcpclient/main.cpp index 90bc2225b5..02ba6b74fd 100644 --- a/libraries/tests/net/helloworld/tcpclient/main.cpp +++ b/libraries/tests/net/helloworld/tcpclient/main.cpp @@ -4,13 +4,18 @@ #include "test_env.h" namespace { - const char *HTTP_SERVER_NAME = "http://developer.mbed.org"; + // Test connection information + const char *HTTP_SERVER_NAME = "developer.mbed.org"; + const char *HTTP_SERVER_FILE_PATH = "/media/uploads/mbed_official/hello.txt"; const int HTTP_SERVER_PORT = 80; const int RECV_BUFFER_SIZE = 512; // Test related data const char *HTTP_OK_STR = "200 OK"; const char *HTTP_HELLO_STR = "Hello world!"; + + // Test buffers + char buffer[RECV_BUFFER_SIZE] = {0}; } bool find_substring(const char *first, const char *last, const char *s_first, const char *s_last) { @@ -19,39 +24,54 @@ bool find_substring(const char *first, const char *last, const char *s_first, co } int main() { + bool result = false; EthernetInterface eth; eth.init(); //Use DHCP eth.connect(); - printf("TCP client IP Address is %s\n", eth.getIPAddress()); + printf("TCP client IP Address is %s\r\n", eth.getIPAddress()); TCPSocketConnection sock; - sock.connect(HTTP_SERVER_NAME, HTTP_SERVER_PORT); + if (sock.connect(HTTP_SERVER_NAME, HTTP_SERVER_PORT) == 0) { + printf("HTTP: Connected to %s:%d\r\n", HTTP_SERVER_NAME, HTTP_SERVER_PORT); - char http_cmd[] = "GET /media/uploads/mbed_official/hello.txt HTTP/1.0\n\n"; - sock.send_all(http_cmd, sizeof(http_cmd)); + // We are constructing GET command like this: + // GET http://developer.mbed.org/media/uploads/mbed_official/hello.txt HTTP/1.0\n\n + strcpy(buffer, "GET http://"); + strcat(buffer, HTTP_SERVER_NAME); + strcat(buffer, HTTP_SERVER_FILE_PATH); + strcat(buffer, " HTTP/1.0\n\n"); + // Send GET command + sock.send_all(buffer, strlen(buffer)); - char buffer[RECV_BUFFER_SIZE] = {0}; - bool result = true; - while (true) { - const int ret = sock.receive(buffer, sizeof(buffer) - 1); - if (ret <= 0) - break; - buffer[ret] = '\0'; + // Server will respond with HTTP GET's success code + bool found_200_ok = false; + { + const int ret = sock.receive(buffer, sizeof(buffer) - 1); + buffer[ret] = '\0'; + // Find 200 OK HTTP status in reply + found_200_ok = find_substring(buffer, buffer + ret, HTTP_OK_STR, HTTP_OK_STR + strlen(HTTP_OK_STR)); + printf("HTTP: Received %d chars from server\r\n", ret); + printf("HTTP: Received 200 OK status ... %s\r\n", found_200_ok ? "[OK]" : "[FAIL]"); + printf("HTTP: Received massage:\r\n\r\n"); + printf("%s", buffer); + } - // Find 200 OK HTTP status in reply - bool found_200_ok = find_substring(buffer, buffer + ret, HTTP_OK_STR, HTTP_OK_STR + strlen(HTTP_OK_STR)); - result = result && found_200_ok; + // Server will respond with requested file content + bool found_hello = false; + { + const int ret = sock.receive(buffer, sizeof(buffer) - 1); + buffer[ret] = '\0'; + // Find Hello World! in reply + found_hello = find_substring(buffer, buffer + ret, HTTP_HELLO_STR, HTTP_HELLO_STR + strlen(HTTP_HELLO_STR)); + printf("HTTP: Received %d chars from server\r\n", ret); + printf("HTTP: Received '%s' status ... %s\r\n", HTTP_HELLO_STR, found_hello ? "[OK]" : "[FAIL]"); + printf("HTTP: Received massage:\r\n\r\n"); + printf("%s", buffer); + } - // Find Hello World! in reply - bool found_hello = find_substring(buffer, buffer + ret, HTTP_HELLO_STR, HTTP_HELLO_STR + strlen(HTTP_HELLO_STR)); - result = result && found_hello; - - // Print results - printf("HTTP: Received %d chars from server\r\n", ret); - printf("HTTP: Received 200 OK status ... %s\r\n", found_200_ok ? "[OK]" : "[FAIL]"); - printf("HTTP: Received '%s' status ... %s\r\n", HTTP_HELLO_STR, found_hello ? "[OK]" : "[FAIL]"); - printf("HTTP: Received massage:\r\n\r\n"); - printf("%s", buffer); + if (found_200_ok && found_hello) { + result = true; + } } sock.close(); diff --git a/libraries/tests/net/protocols/NTPClient_HelloWorld/NTPClient/NTPClient.h b/libraries/tests/net/protocols/NTPClient_HelloWorld/NTPClient/NTPClient.h index 598bdc31c3..e0373784f3 100644 --- a/libraries/tests/net/protocols/NTPClient_HelloWorld/NTPClient/NTPClient.h +++ b/libraries/tests/net/protocols/NTPClient_HelloWorld/NTPClient/NTPClient.h @@ -24,12 +24,6 @@ NTP Client header file #ifndef NTPCLIENT_H_ #define NTPCLIENT_H_ -#include - -using std::uint8_t; -using std::uint16_t; -using std::uint32_t; - #include "UDPSocket.h" #define NTP_DEFAULT_PORT 123 @@ -95,8 +89,6 @@ private: } __attribute__ ((packed)); UDPSocket m_sock; - }; - #endif /* NTPCLIENT_H_ */ diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index f98599d5b0..038319908a 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -27,22 +27,22 @@ from workspace_tools.build_api import build_mbed_libs from workspace_tools.targets import TARGET_MAP OFFICIAL_MBED_LIBRARY_BUILD = ( - ('LPC11U24', ('ARM', 'uARM', 'GCC_ARM')), + ('LPC11U24', ('ARM', 'uARM', 'GCC_ARM', 'IAR')), ('LPC1768', ('ARM', 'GCC_ARM', 'GCC_CR', 'GCC_CS', 'IAR')), ('UBLOX_C027', ('ARM', 'GCC_ARM', 'GCC_CR', 'GCC_CS', 'IAR')), ('ARCH_PRO', ('ARM', 'GCC_ARM', 'GCC_CR', 'GCC_CS', 'IAR')), ('LPC2368', ('ARM', 'GCC_ARM')), - ('LPC812', ('uARM',)), + ('LPC812', ('uARM','IAR')), ('LPC824', ('uARM',)), ('SSCI824', ('uARM',)), ('LPC1347', ('ARM','IAR')), - ('LPC4088', ('ARM', 'GCC_ARM', 'GCC_CR')), - ('LPC1114', ('uARM','GCC_ARM')), - ('LPC11U35_401', ('ARM', 'uARM','GCC_ARM','GCC_CR')), - ('LPC11U35_501', ('ARM', 'uARM','GCC_ARM','GCC_CR')), - ('LPC1549', ('uARM','GCC_ARM','GCC_CR')), + ('LPC4088', ('ARM', 'GCC_ARM', 'GCC_CR', 'IAR')), + ('LPC1114', ('uARM','GCC_ARM', 'IAR')), + ('LPC11U35_401', ('ARM', 'uARM','GCC_ARM','GCC_CR', 'IAR')), + ('LPC11U35_501', ('ARM', 'uARM','GCC_ARM','GCC_CR', 'IAR')), + ('LPC1549', ('uARM','GCC_ARM','GCC_CR', 'IAR')), ('XADOW_M0', ('ARM', 'uARM','GCC_ARM','GCC_CR')), - ('ARCH_GPRS', ('ARM', 'uARM', 'GCC_ARM', 'GCC_CR')), + ('ARCH_GPRS', ('ARM', 'uARM', 'GCC_ARM', 'GCC_CR', 'IAR')), ('LPC4337', ('ARM',)), ('KL05Z', ('ARM', 'uARM', 'GCC_ARM', 'IAR')), @@ -57,12 +57,12 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('NUCLEO_F072RB', ('ARM', 'uARM', 'IAR')), ('NUCLEO_F091RC', ('ARM', 'uARM', 'IAR')), ('NUCLEO_F103RB', ('ARM', 'uARM', 'IAR')), - ('NUCLEO_F302R8', ('ARM', 'uARM', 'IAR')), + ('NUCLEO_F302R8', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('NUCLEO_F334R8', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('NUCLEO_F401RE', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('NUCLEO_F411RE', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('NUCLEO_L053R8', ('ARM', 'uARM', 'IAR')), - ('NUCLEO_L152RE', ('ARM', 'uARM', 'IAR')), + ('NUCLEO_L152RE', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('MTS_MDOT_F405RG', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('ARCH_MAX', ('ARM', 'GCC_ARM')), @@ -76,8 +76,8 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('RBLAB_BLENANO', ('ARM', 'GCC_ARM')), ('WALLBOT_BLE', ('ARM', 'GCC_ARM')), - ('LPC11U68', ('uARM','GCC_ARM','GCC_CR')), - ('OC_MBUINO', ('ARM', 'uARM', 'GCC_ARM')), + ('LPC11U68', ('uARM','GCC_ARM','GCC_CR', 'IAR')), + ('OC_MBUINO', ('ARM', 'uARM', 'GCC_ARM', 'IAR')), # ('RZ_A1H' , ('ARM',)), ) diff --git a/workspace_tools/build_travis.py b/workspace_tools/build_travis.py index 511842ada0..3f839f2688 100644 --- a/workspace_tools/build_travis.py +++ b/workspace_tools/build_travis.py @@ -36,6 +36,8 @@ build_list = ( { "target": "NUCLEO_F103RB", "toolchains": "GCC_ARM", "libs": ["fat"] }, { "target": "NUCLEO_L053R8", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "NUCLEO_L152RE", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "NUCLEO_F302R8", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, { "target": "NUCLEO_F334R8", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_F401RE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, diff --git a/workspace_tools/export/coide.py b/workspace_tools/export/coide.py index 74499b269d..2dae5f67c8 100644 --- a/workspace_tools/export/coide.py +++ b/workspace_tools/export/coide.py @@ -28,6 +28,8 @@ class CoIDE(Exporter): 'LPC1768', 'ARCH_PRO', 'DISCO_F407VG', + 'NUCLEO_L152RE', + 'NUCLEO_F302R8', 'NUCLEO_F334R8', 'NUCLEO_F401RE', 'NUCLEO_F411RE', diff --git a/workspace_tools/export/coide_nucleo_f302r8.coproj.tmpl b/workspace_tools/export/coide_nucleo_f302r8.coproj.tmpl new file mode 100644 index 0000000000..c2b4f883e5 --- /dev/null +++ b/workspace_tools/export/coide_nucleo_f302r8.coproj.tmpl @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + {% for file in source_files %} + + {% endfor %} + {% for file in header_files %} + + {% endfor %} + + diff --git a/workspace_tools/export/coide_nucleo_l152re.coproj.tmpl b/workspace_tools/export/coide_nucleo_l152re.coproj.tmpl new file mode 100644 index 0000000000..1711c7a624 --- /dev/null +++ b/workspace_tools/export/coide_nucleo_l152re.coproj.tmpl @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + {% for file in source_files %} + + {% endfor %} + {% for file in header_files %} + + {% endfor %} + + diff --git a/workspace_tools/export/gcc_arm_nucleo_f302r8.tmpl b/workspace_tools/export/gcc_arm_nucleo_f302r8.tmpl new file mode 100644 index 0000000000..6cd9497c11 --- /dev/null +++ b/workspace_tools/export/gcc_arm_nucleo_f302r8.tmpl @@ -0,0 +1,77 @@ +# This file was automagically generated by mbed.org. For more information, +# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded + +GCC_BIN = +PROJECT = {{name}} +OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %} +SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %} +INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %} +LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %} +LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %} +LINKER_SCRIPT = {{linker_script}} + +############################################################################### +AS = $(GCC_BIN)arm-none-eabi-as +CC = $(GCC_BIN)arm-none-eabi-gcc +CPP = $(GCC_BIN)arm-none-eabi-g++ +LD = $(GCC_BIN)arm-none-eabi-gcc +OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy +OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump +SIZE = $(GCC_BIN)arm-none-eabi-size + +CPU = -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=$(FLOAT_ABI) +CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti +CC_FLAGS += -MMD -MP +CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %} + +LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -u _printf_float -u _scanf_float -Wl,--wrap,main +LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref +LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +ifeq ($(HARDFP),1) + FLOAT_ABI = hard +else + FLOAT_ABI = softfp +endif + +ifeq ($(DEBUG), 1) + CC_FLAGS += -DDEBUG -O0 +else + CC_FLAGS += -DNDEBUG -Os +endif + +all: $(PROJECT).bin $(PROJECT).hex size + +clean: + rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS) + +.s.o: + $(AS) $(CPU) -o $@ $< + +.c.o: + $(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $< + +.cpp.o: + $(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 $(INCLUDE_PATHS) -o $@ $< + + +$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) + $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS) + +$(PROJECT).bin: $(PROJECT).elf + @$(OBJCOPY) -O binary $< $@ + +$(PROJECT).hex: $(PROJECT).elf + @$(OBJCOPY) -O ihex $< $@ + +$(PROJECT).lst: $(PROJECT).elf + @$(OBJDUMP) -Sdh $< > $@ + +lst: $(PROJECT).lst + +size: + $(SIZE) $(PROJECT).elf + +DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d) +-include $(DEPS) + diff --git a/workspace_tools/export/gcc_arm_nucleo_l152re.tmpl b/workspace_tools/export/gcc_arm_nucleo_l152re.tmpl new file mode 100644 index 0000000000..8a9f703b28 --- /dev/null +++ b/workspace_tools/export/gcc_arm_nucleo_l152re.tmpl @@ -0,0 +1,71 @@ +# This file was automagically generated by mbed.org. For more information, +# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded + +GCC_BIN = +PROJECT = {{name}} +OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %} +SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %} +INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %} +LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %} +LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %} +LINKER_SCRIPT = {{linker_script}} + +############################################################################### +AS = $(GCC_BIN)arm-none-eabi-as +CC = $(GCC_BIN)arm-none-eabi-gcc +CPP = $(GCC_BIN)arm-none-eabi-g++ +LD = $(GCC_BIN)arm-none-eabi-gcc +OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy +OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump +SIZE = $(GCC_BIN)arm-none-eabi-size + +CPU = -mcpu=cortex-m3 -mthumb +CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti +CC_FLAGS += -MMD -MP +CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %} + +LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -u _printf_float -u _scanf_float -Wl,--wrap,main +LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref +LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +ifeq ($(DEBUG), 1) + CC_FLAGS += -DDEBUG -O0 +else + CC_FLAGS += -DNDEBUG -Os +endif + +all: $(PROJECT).bin $(PROJECT).hex size + +clean: + rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS) + +.s.o: + $(AS) $(CPU) -o $@ $< + +.c.o: + $(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $< + +.cpp.o: + $(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 $(INCLUDE_PATHS) -o $@ $< + + +$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) + $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS) + +$(PROJECT).bin: $(PROJECT).elf + @$(OBJCOPY) -O binary $< $@ + +$(PROJECT).hex: $(PROJECT).elf + @$(OBJCOPY) -O ihex $< $@ + +$(PROJECT).lst: $(PROJECT).elf + @$(OBJDUMP) -Sdh $< > $@ + +lst: $(PROJECT).lst + +size: + $(SIZE) $(PROJECT).elf + +DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d) +-include $(DEPS) + diff --git a/workspace_tools/export/gccarm.py b/workspace_tools/export/gccarm.py index 026df99d4f..8993d44190 100644 --- a/workspace_tools/export/gccarm.py +++ b/workspace_tools/export/gccarm.py @@ -56,11 +56,13 @@ class GccArm(Exporter): 'NUCLEO_F411RE', 'ARCH_MAX', 'DISCO_F429ZI', + 'NUCLEO_F302R8', 'NUCLEO_F334R8', 'DISCO_L053C8', 'NUCLEO_L053R8', 'DISCO_F334C8', 'MTS_MDOT_F405RG', + 'NUCLEO_L152RE', ] DOT_IN_RELATIVE_PATH = True diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py index 8d61c32e2e..13164b4ca7 100644 --- a/workspace_tools/export/iar.py +++ b/workspace_tools/export/iar.py @@ -24,6 +24,14 @@ class IAREmbeddedWorkbench(Exporter): TARGETS = [ 'LPC1768', 'LPC1347', + 'LPC11U24', + 'LPC11U35_401', + 'LPC11U35_501', + 'LPCCAPPUCCINO', + 'LPC1114', + 'LPC1549', + 'LPC812', + 'LPC4088', 'UBLOX_C027', 'ARCH_PRO', 'K20D50M', diff --git a/workspace_tools/export/iar_arch_pro.ewp.tmpl b/workspace_tools/export/iar_arch_pro.ewp.tmpl index 41f12edd53..6eb8e14536 100644 --- a/workspace_tools/export/iar_arch_pro.ewp.tmpl +++ b/workspace_tools/export/iar_arch_pro.ewp.tmpl @@ -164,7 +164,9 @@ 1