mirror of https://github.com/ARMmbed/mbed-os.git
Remove LPC810 target
MarceloSalazar
Marcelo Salazar
parent
de01b388e5
commit
143342fcfa
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@ -1,30 +0,0 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_PERIPHERALNAMES_H
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#define MBED_PERIPHERALNAMES_H
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -1,81 +0,0 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_PINNAMES_H
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#define MBED_PINNAMES_H
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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PIN_INPUT,
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PIN_OUTPUT
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} PinDirection;
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typedef enum {
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P0_0 = 0,
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P0_1 = 1,
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P0_2 = 2,
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P0_3 = 3,
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P0_4 = 4,
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P0_5 = 5,
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dp1 = P0_5,
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dp2 = P0_4,
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dp3 = P0_3,
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dp4 = P0_2,
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dp5 = P0_1,
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dp8 = P0_0,
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// mbed original LED naming
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LED1 = P0_2,
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LED2 = P0_2,
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LED3 = P0_2,
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LED4 = P0_2,
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LED_RED = P0_2,
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// Serial to USB pins
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USBTX = P0_4,
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USBRX = P0_0,
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// Not connected
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NC = (int)0xFFFFFFFF,
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} PinName;
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typedef enum {
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PullUp = 2,
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PullDown = 1,
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PullNone = 0,
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Repeater = 3,
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OpenDrain = 4,
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PullDefault = PullDown
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} PinMode;
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#define STDIO_UART_TX USBTX
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#define STDIO_UART_RX USBRX
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typedef struct {
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unsigned char n;
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unsigned char offset;
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} SWM_Map;
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -1,48 +0,0 @@
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#! armcc -E
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#if !defined(MBED_APP_START)
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#define MBED_APP_START 0x00000000
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#endif
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; 4K flash
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#if !defined(MBED_APP_SIZE)
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#define MBED_APP_SIZE 0x1000
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#endif
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; 1KB
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#if !defined(MBED_RAM_START)
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#define MBED_RAM_START 0x10000000
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#endif
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#if !defined(MBED_RAM_SIZE)
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#define MBED_RAM_SIZE 0x400
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#endif
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#if !defined(MBED_BOOT_STACK_SIZE)
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#define MBED_BOOT_STACK_SIZE 0x400
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#endif
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; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
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#define VECTOR_SIZE 0xC0
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#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
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.ANY (+RW +ZI)
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}
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ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
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}
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ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
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}
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}
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@ -1,185 +0,0 @@
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;/*****************************************************************************
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; * @file: startup_LPC8xx.s
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; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
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; * for the NXP LPC8xx Device Series
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; * @version: V1.0
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; * @date: 16. Aug. 2012
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; * Copyright (C) 2012 ARM Limited. All rights reserved.
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; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; *****************************************************************************/
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
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__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD SPI0_IRQHandler ; SPI0 controller
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DCD SPI1_IRQHandler ; SPI1 controller
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DCD 0 ; Reserved
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DCD UART0_IRQHandler ; UART0
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DCD UART1_IRQHandler ; UART1
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DCD UART2_IRQHandler ; UART2
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD I2C_IRQHandler ; I2C controller
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DCD SCT_IRQHandler ; Smart Counter Timer
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DCD MRT_IRQHandler ; Multi-Rate Timer
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DCD CMP_IRQHandler ; Comparator
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DCD WDT_IRQHandler ; PIO1 (0:11)
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DCD BOD_IRQHandler ; Brown Out Detect
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DCD 0 ; Reserved
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DCD WKT_IRQHandler ; Wakeup timer
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PININT0_IRQHandler ; PIO INT0
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DCD PININT1_IRQHandler ; PIO INT1
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DCD PININT2_IRQHandler ; PIO INT2
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DCD PININT3_IRQHandler ; PIO INT3
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DCD PININT4_IRQHandler ; PIO INT4
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DCD PININT5_IRQHandler ; PIO INT5
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DCD PININT6_IRQHandler ; PIO INT6
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DCD PININT7_IRQHandler ; PIO INT7
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IF :LNOT::DEF:NO_CRP
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AREA |.ARM.__at_0x02FC|, CODE, READONLY
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CRP_Key DCD 0xFFFFFFFF
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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; now, under COMMON lpc8xx_nmi.c and lpc8xx_nmi.h, a real NMI handler is created if NMI is enabled
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; for particular peripheral.
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;NMI_Handler PROC
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; EXPORT NMI_Handler [WEAK]
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; B .
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; ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT NMI_Handler [WEAK]
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EXPORT SPI0_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT UART1_IRQHandler [WEAK]
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EXPORT UART2_IRQHandler [WEAK]
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EXPORT I2C_IRQHandler [WEAK]
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EXPORT SCT_IRQHandler [WEAK]
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EXPORT MRT_IRQHandler [WEAK]
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EXPORT CMP_IRQHandler [WEAK]
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EXPORT WDT_IRQHandler [WEAK]
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EXPORT BOD_IRQHandler [WEAK]
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EXPORT WKT_IRQHandler [WEAK]
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EXPORT PININT0_IRQHandler [WEAK]
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EXPORT PININT1_IRQHandler [WEAK]
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EXPORT PININT2_IRQHandler [WEAK]
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EXPORT PININT3_IRQHandler [WEAK]
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EXPORT PININT4_IRQHandler [WEAK]
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EXPORT PININT5_IRQHandler [WEAK]
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EXPORT PININT6_IRQHandler [WEAK]
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EXPORT PININT7_IRQHandler [WEAK]
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NMI_Handler
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SPI0_IRQHandler
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SPI1_IRQHandler
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UART0_IRQHandler
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UART1_IRQHandler
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UART2_IRQHandler
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I2C_IRQHandler
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SCT_IRQHandler
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MRT_IRQHandler
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CMP_IRQHandler
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WDT_IRQHandler
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BOD_IRQHandler
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WKT_IRQHandler
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PININT0_IRQHandler
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PININT1_IRQHandler
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PININT2_IRQHandler
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PININT3_IRQHandler
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PININT4_IRQHandler
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PININT5_IRQHandler
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PININT6_IRQHandler
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PININT7_IRQHandler
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B .
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ENDP
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ALIGN
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END
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@ -1,156 +0,0 @@
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/* Linker script for mbed LPC810-GCC-ARM based on LPC824.ld */
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#if !defined(MBED_BOOT_STACK_SIZE)
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#define MBED_BOOT_STACK_SIZE 0x400
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#endif
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STACK_SIZE = MBED_BOOT_STACK_SIZE;
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/* Linker script to configure memory regions. */
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MEMORY
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{
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/* Define each memory region */
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FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x1000 /* 4K bytes */
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RAM (rwx) : ORIGIN = 0x10000000+0xC0, LENGTH = 0x400-0xC0 /* 1K bytes */
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}
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/* Linker script to place sections and symbol values. Should be used together
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* with other linker script that defines memory regions FLASH and RAM.
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* It references following symbols, which must be defined in code:
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* Reset_Handler : Entry of reset handler
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*
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* It defines following symbols, which code can use without definition:
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* __exidx_start
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* __exidx_end
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* __etext
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* __data_start__
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* __preinit_array_start
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* __preinit_array_end
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* __init_array_start
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* __init_array_end
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* __fini_array_start
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* __fini_array_end
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* __data_end__
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* __bss_start__
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* __bss_end__
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* __end__
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* end
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* __HeapLimit
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* __StackLimit
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* __StackTop
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* __stack
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*/
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ENTRY(Reset_Handler)
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SECTIONS
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{
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.text :
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{
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KEEP(*(.isr_vector))
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*(.text.Reset_Handler)
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*(.text.SystemInit)
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*(.text*)
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KEEP(*(.init))
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KEEP(*(.fini))
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
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*(.rodata*)
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KEEP(*(.eh_frame*))
|
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} > FLASH
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.ARM.extab :
|
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{
|
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > FLASH
|
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|
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__exidx_start = .;
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.ARM.exidx :
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{
|
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > FLASH
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__exidx_end = .;
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__etext = .;
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.data : AT (__etext)
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{
|
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__data_start__ = .;
|
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*(vtable)
|
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*(.data*)
|
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. = ALIGN(8);
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/* preinit data */
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PROVIDE (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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PROVIDE (__preinit_array_end = .);
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. = ALIGN(8);
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/* init data */
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PROVIDE (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
|
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PROVIDE (__init_array_end = .);
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|
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|
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. = ALIGN(8);
|
||||
/* finit data */
|
||||
PROVIDE (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
|
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PROVIDE (__fini_array_end = .);
|
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|
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. = ALIGN(8);
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/* All data end */
|
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__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
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.bss :
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{
|
||||
__bss_start__ = .;
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*(.bss*)
|
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*(COMMON)
|
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__bss_end__ = .;
|
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} > RAM
|
||||
|
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.heap :
|
||||
{
|
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__end__ = .;
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end = __end__;
|
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*(.heap*)
|
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. = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;
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__HeapLimit = .;
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} > RAM
|
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|
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/* .stack_dummy section doesn't contains any symbols. It is only
|
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* used for linker to calculate size of stack sections, and assign
|
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* values to stack symbols later */
|
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.stack_dummy :
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{
|
||||
*(.stack)
|
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} > RAM
|
||||
|
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/* Set stack top to end of RAM, and stack limit move down by
|
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* size of stack_dummy section */
|
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__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
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__StackLimit = __StackTop - STACK_SIZE;
|
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PROVIDE(__stack = __StackTop);
|
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|
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/* Check if data + heap + stack exceeds RAM limit */
|
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ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
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}
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|
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@ -1,39 +0,0 @@
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/*###ICF### Section handled by ICF editor, don't touch! ****/
|
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/*-Editor annotation file-*/
|
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
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define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
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/*-Memory Regions-*/
|
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define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
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define symbol __ICFEDIT_region_ROM_end__ = 0x00000FFF;
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define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
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define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x100003FF;
|
||||
/*-Sizes-*/
|
||||
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
|
||||
define symbol MBED_BOOT_STACK_SIZE = 0x400;
|
||||
}
|
||||
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __CRP_start__ = 0x000002FC;
|
||||
define symbol __CRP_end__ = 0x000002FF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block HEAP, block CSTACK };
|
||||
place in CRP_region { section .crp };
|
||||
|
|
@ -1,197 +0,0 @@
|
|||
/**************************************************
|
||||
*
|
||||
* Part one of the system initialization code, contains low-level
|
||||
* initialization, plain thumb variant.
|
||||
*
|
||||
* Copyright 2011 IAR Systems. All rights reserved.
|
||||
*
|
||||
* $Revision: 47876 $
|
||||
*
|
||||
**************************************************/
|
||||
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __vector_table_0x1c
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
__vector_table_0x1c
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD SVC_Handler
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD SPI0_IRQHandler ; SPI0 controller
|
||||
DCD SPI1_IRQHandler ; SPI1 controller
|
||||
DCD 0 ; Reserved
|
||||
DCD UART0_IRQHandler ; UART0
|
||||
DCD UART1_IRQHandler ; UART1
|
||||
DCD UART2_IRQHandler ; UART2
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C_IRQHandler ; I2C controller
|
||||
DCD SCT_IRQHandler ; Smart Counter Timer
|
||||
DCD MRT_IRQHandler ; Multi-Rate Timer
|
||||
DCD CMP_IRQHandler ; Comparator
|
||||
DCD WDT_IRQHandler ; PIO1 (0:11)
|
||||
DCD BOD_IRQHandler ; Brown Out Detect
|
||||
DCD 0 ; Reserved
|
||||
DCD WKT_IRQHandler ; Wakeup timer
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PININT0_IRQHandler ; PIO INT0
|
||||
DCD PININT1_IRQHandler ; PIO INT1
|
||||
DCD PININT2_IRQHandler ; PIO INT2
|
||||
DCD PININT3_IRQHandler ; PIO INT3
|
||||
DCD PININT4_IRQHandler ; PIO INT4
|
||||
DCD PININT5_IRQHandler ; PIO INT5
|
||||
DCD PININT6_IRQHandler ; PIO INT6
|
||||
DCD PININT7_IRQHandler ; PIO INT7
|
||||
__Vectors_End
|
||||
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
PUBWEAK HardFault_Handler
|
||||
PUBWEAK SVC_Handler
|
||||
PUBWEAK PendSV_Handler
|
||||
PUBWEAK SysTick_Handler
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
PUBWEAK UART0_IRQHandler
|
||||
PUBWEAK UART1_IRQHandler
|
||||
PUBWEAK UART2_IRQHandler
|
||||
PUBWEAK I2C_IRQHandler
|
||||
PUBWEAK SCT_IRQHandler
|
||||
PUBWEAK MRT_IRQHandler
|
||||
PUBWEAK CMP_IRQHandler
|
||||
PUBWEAK WDT_IRQHandler
|
||||
PUBWEAK BOD_IRQHandler
|
||||
PUBWEAK WKT_IRQHandler
|
||||
PUBWEAK PININT0_IRQHandler
|
||||
PUBWEAK PININT1_IRQHandler
|
||||
PUBWEAK PININT2_IRQHandler
|
||||
PUBWEAK PININT3_IRQHandler
|
||||
PUBWEAK PININT4_IRQHandler
|
||||
PUBWEAK PININT5_IRQHandler
|
||||
PUBWEAK PININT6_IRQHandler
|
||||
PUBWEAK PININT7_IRQHandler
|
||||
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
THUMB
|
||||
NMI_Handler
|
||||
HardFault_Handler
|
||||
SVC_Handler
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
I2C_IRQHandler
|
||||
SCT_IRQHandler
|
||||
MRT_IRQHandler
|
||||
CMP_IRQHandler
|
||||
WDT_IRQHandler
|
||||
BOD_IRQHandler
|
||||
WKT_IRQHandler
|
||||
PININT0_IRQHandler
|
||||
PININT1_IRQHandler
|
||||
PININT2_IRQHandler
|
||||
PININT3_IRQHandler
|
||||
PININT4_IRQHandler
|
||||
PININT5_IRQHandler
|
||||
PININT6_IRQHandler
|
||||
PININT7_IRQHandler
|
||||
Default_IRQHandler
|
||||
B Default_IRQHandler
|
||||
|
||||
SECTION .crp:CODE:ROOT(2)
|
||||
DATA
|
||||
/* Code Read Protection
|
||||
NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
|
||||
CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
|
||||
- Copy RAM to flash command can not write to Sector 0.
|
||||
- Erase command can erase Sector 0 only when all sectors
|
||||
are selected for erase.
|
||||
- Compare command is disabled.
|
||||
- Read Memory command is disabled.
|
||||
CRP2 0x87654321 - Read Memory is disabled.
|
||||
- Write to RAM is disabled.
|
||||
- "Go" command is disabled.
|
||||
- Copy RAM to flash is disabled.
|
||||
- Compare is disabled.
|
||||
CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
|
||||
by pulling PIO0_1 LOW is disabled if a valid user code is
|
||||
present in flash sector 0.
|
||||
Caution: If CRP3 is selected, no future factory testing can be
|
||||
performed on the device.
|
||||
*/
|
||||
DCD 0xFFFFFFFF
|
||||
|
||||
END
|
||||
|
|
@ -1,372 +0,0 @@
|
|||
/******************************************************************************
|
||||
* @file: system_LPC8xx.c
|
||||
* @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
|
||||
* for the NXP LPC8xx Device Series
|
||||
* @version: V1.0
|
||||
* @date: 16. Aug. 2012
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Copyright (C) 2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M0+
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include "LPC8xx.h"
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
/*--------------------- Clock Configuration ----------------------------------
|
||||
//
|
||||
// <e> Clock Configuration
|
||||
// <h> System Oscillator Control Register (SYSOSCCTRL)
|
||||
// <o1.0> BYPASS: System Oscillator Bypass Enable
|
||||
// <i> If enabled then PLL input (sys_osc_clk) is fed
|
||||
// <i> directly from XTALIN and XTALOUT pins.
|
||||
// <o1.9> FREQRANGE: System Oscillator Frequency Range
|
||||
// <i> Determines frequency range for Low-power oscillator.
|
||||
// <0=> 1 - 20 MHz
|
||||
// <1=> 15 - 25 MHz
|
||||
// </h>
|
||||
//
|
||||
// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
|
||||
// <o2.0..4> DIVSEL: Select Divider for Fclkana
|
||||
// <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
|
||||
// <0-31>
|
||||
// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
|
||||
// <0=> Undefined
|
||||
// <1=> 0.5 MHz
|
||||
// <2=> 0.8 MHz
|
||||
// <3=> 1.1 MHz
|
||||
// <4=> 1.4 MHz
|
||||
// <5=> 1.6 MHz
|
||||
// <6=> 1.8 MHz
|
||||
// <7=> 2.0 MHz
|
||||
// <8=> 2.2 MHz
|
||||
// <9=> 2.4 MHz
|
||||
// <10=> 2.6 MHz
|
||||
// <11=> 2.7 MHz
|
||||
// <12=> 2.9 MHz
|
||||
// <13=> 3.1 MHz
|
||||
// <14=> 3.2 MHz
|
||||
// <15=> 3.4 MHz
|
||||
// </h>
|
||||
//
|
||||
// <h> System PLL Control Register (SYSPLLCTRL)
|
||||
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
|
||||
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
|
||||
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
|
||||
// <o3.0..4> MSEL: Feedback Divider Selection
|
||||
// <i> M = MSEL + 1
|
||||
// <0-31>
|
||||
// <o3.5..6> PSEL: Post Divider Selection
|
||||
// <0=> P = 1
|
||||
// <1=> P = 2
|
||||
// <2=> P = 4
|
||||
// <3=> P = 8
|
||||
// </h>
|
||||
//
|
||||
// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
|
||||
// <o4.0..1> SEL: System PLL Clock Source
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
// <2=> Reserved
|
||||
// <3=> CLKIN pin
|
||||
// </h>
|
||||
//
|
||||
// <h> Main Clock Source Select Register (MAINCLKSEL)
|
||||
// <o5.0..1> SEL: Clock Source for Main Clock
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> Input Clock to System PLL
|
||||
// <2=> WDT Oscillator
|
||||
// <3=> System PLL Clock Out
|
||||
// </h>
|
||||
//
|
||||
// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
|
||||
// <o6.0..7> DIV: System AHB Clock Divider
|
||||
// <i> Divides main clock to provide system clock to core, memories, and peripherals.
|
||||
// <i> 0 = is disabled
|
||||
// <0-255>
|
||||
// </h>
|
||||
// </e>
|
||||
*/
|
||||
|
||||
// 1 == IRC 12Mhz 2 == System Oscillator 12Mhz Xtal:
|
||||
#define CLOCK_SETUP 1
|
||||
//use PLL for IRC
|
||||
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000 MSEL=1 => M=2; PSEL=2 => 2P=8; PLLCLKOUT = (12x2) = 24MHz
|
||||
//#define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz
|
||||
#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 Select IRC
|
||||
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT
|
||||
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 DIV=1 => SYSTEMCORECLK = 24 / 1 = 24MHz
|
||||
//#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz
|
||||
/*
|
||||
//-------- <<< end of configuration section >>> ------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Check the register settings
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
||||
#define CHECK_RSVD(val, mask) (val & mask)
|
||||
|
||||
/* Clock Configuration -------------------------------------------------------*/
|
||||
#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
|
||||
#error "SYSOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
|
||||
#error "WDTOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
|
||||
#error "SYSPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
|
||||
#error "SYSPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
|
||||
#error "MAINCLKSEL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
|
||||
#error "SYSAHBCLKDIV: Value out of range!"
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __XTAL (12000000UL) /* Oscillator frequency */
|
||||
#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
|
||||
#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
|
||||
#define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */
|
||||
|
||||
|
||||
#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
|
||||
#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
#if (__FREQSEL == 0)
|
||||
#define __WDT_OSC_CLK ( 0) /* undefined */
|
||||
#elif (__FREQSEL == 1)
|
||||
#define __WDT_OSC_CLK ( 500000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 2)
|
||||
#define __WDT_OSC_CLK ( 800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 3)
|
||||
#define __WDT_OSC_CLK (1100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 4)
|
||||
#define __WDT_OSC_CLK (1400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 5)
|
||||
#define __WDT_OSC_CLK (1600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 6)
|
||||
#define __WDT_OSC_CLK (1800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 7)
|
||||
#define __WDT_OSC_CLK (2000000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 8)
|
||||
#define __WDT_OSC_CLK (2200000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 9)
|
||||
#define __WDT_OSC_CLK (2400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 10)
|
||||
#define __WDT_OSC_CLK (2600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 11)
|
||||
#define __WDT_OSC_CLK (2700000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 12)
|
||||
#define __WDT_OSC_CLK (2900000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 13)
|
||||
#define __WDT_OSC_CLK (3100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 14)
|
||||
#define __WDT_OSC_CLK (3200000 / __DIVSEL)
|
||||
#else
|
||||
#define __WDT_OSC_CLK (3400000 / __DIVSEL)
|
||||
#endif
|
||||
|
||||
/* sys_pllclkin calculation */
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
|
||||
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
|
||||
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
|
||||
#elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
|
||||
#define __SYS_PLLCLKIN (__CLKIN_CLK)
|
||||
#else
|
||||
#define __SYS_PLLCLKIN (0)
|
||||
#endif
|
||||
|
||||
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
|
||||
|
||||
/* main clock calculation */
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 0)
|
||||
#define __MAIN_CLOCK (__IRC_OSC_CLK)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 1)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKIN)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 2)
|
||||
#if (__FREQSEL == 0)
|
||||
#error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
|
||||
#else
|
||||
#define __MAIN_CLOCK (__WDT_OSC_CLK)
|
||||
#endif
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 3)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
|
||||
#else
|
||||
#define __MAIN_CLOCK (0)
|
||||
#endif
|
||||
|
||||
#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
|
||||
|
||||
#else
|
||||
#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
|
||||
#endif // CLOCK_SETUP
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
//Replaced SystemCoreClock with MainClock
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
uint32_t wdt_osc = 0;
|
||||
|
||||
/* Determine clock frequency according to clock register values */
|
||||
switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
|
||||
case 0: wdt_osc = 0; break;
|
||||
case 1: wdt_osc = 500000; break;
|
||||
case 2: wdt_osc = 800000; break;
|
||||
case 3: wdt_osc = 1100000; break;
|
||||
case 4: wdt_osc = 1400000; break;
|
||||
case 5: wdt_osc = 1600000; break;
|
||||
case 6: wdt_osc = 1800000; break;
|
||||
case 7: wdt_osc = 2000000; break;
|
||||
case 8: wdt_osc = 2200000; break;
|
||||
case 9: wdt_osc = 2400000; break;
|
||||
case 10: wdt_osc = 2600000; break;
|
||||
case 11: wdt_osc = 2700000; break;
|
||||
case 12: wdt_osc = 2900000; break;
|
||||
case 13: wdt_osc = 3100000; break;
|
||||
case 14: wdt_osc = 3200000; break;
|
||||
case 15: wdt_osc = 3400000; break;
|
||||
}
|
||||
wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
|
||||
|
||||
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
MainClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* Input Clock to System PLL */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
MainClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
MainClock = __SYS_OSC_CLK;
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
MainClock = 0;
|
||||
break;
|
||||
case 3: /* CLKIN pin */
|
||||
MainClock = __CLKIN_CLK;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 2: /* WDT Oscillator */
|
||||
MainClock = wdt_osc;
|
||||
break;
|
||||
case 3: /* System PLL Clock Out */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
MainClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
MainClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
MainClock = 0;
|
||||
break;
|
||||
case 3: /* CLKIN pin */
|
||||
MainClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void) {
|
||||
volatile uint32_t i;
|
||||
|
||||
/* System clock to the IOCON & the SWM need to be enabled or
|
||||
most of the I/O related peripherals won't work. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
|
||||
LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
|
||||
LPC_SWM->PINENABLE0 &= ~(0x3 << 4);
|
||||
LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */
|
||||
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
|
||||
for (i = 0; i < 200; i++) __NOP();
|
||||
#endif
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 3)
|
||||
LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
|
||||
LPC_SWM->PINENABLE0 &= ~(0x1 << 7);
|
||||
for (i = 0; i < 200; i++) __NOP();
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
|
||||
LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
|
||||
while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
|
||||
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */
|
||||
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
#endif
|
||||
|
||||
#if (((MAINCLKSEL_Val & 0x03) == 2) )
|
||||
LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */
|
||||
for (i = 0; i < 200; i++) __NOP();
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
|
||||
LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
|
||||
while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
|
||||
|
||||
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -577,39 +577,6 @@
|
|||
"1235"
|
||||
]
|
||||
},
|
||||
"LPC810": {
|
||||
"inherits": [
|
||||
"LPCTarget"
|
||||
],
|
||||
"core": "Cortex-M0+",
|
||||
"default_toolchain": "uARM",
|
||||
"extra_labels": [
|
||||
"NXP",
|
||||
"LPC81X"
|
||||
],
|
||||
"is_disk_virtual": true,
|
||||
"supported_toolchains": [
|
||||
"uARM",
|
||||
"IAR",
|
||||
"GCC_ARM"
|
||||
],
|
||||
"device_has": [
|
||||
"I2C",
|
||||
"I2CSLAVE",
|
||||
"INTERRUPTIN",
|
||||
"PWMOUT",
|
||||
"SERIAL",
|
||||
"SERIAL_FC",
|
||||
"SLEEP",
|
||||
"SPI",
|
||||
"SPISLAVE"
|
||||
],
|
||||
"default_lib": "small",
|
||||
"device_name": "LPC810M021FN8",
|
||||
"detect_code": [
|
||||
"1020"
|
||||
]
|
||||
},
|
||||
"LPC812": {
|
||||
"supported_form_factors": [
|
||||
"ARDUINO"
|
||||
|
|
|
|||
Loading…
Reference in New Issue