From 13fec628d0dd3c7f2fcf8e1beab1f853ab3bc222 Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Tue, 26 Jun 2018 15:15:27 +0800
Subject: [PATCH] [NANO130] Change PLL clock source to HIRC instead of HXT

This change is to reduce delay of wake-up from power-down to pass Greentea test.
Because HIRC's accuracy is worse than HXT's, we must switch back to HXT for e.g. USBD application.
This can be done through setting NU_CLOCK_PLL to NU_HXT_PLL.
---
 .../mbed_overrides.c                          | 32 +++++++++++++++++--
 targets/targets.json                          |  5 +++
 2 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/mbed_overrides.c b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/mbed_overrides.c
index f3778c22cd..c17d7022b5 100644
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/mbed_overrides.c
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/mbed_overrides.c
@@ -52,8 +52,36 @@ void mbed_sdk_init(void)
     /* Set HCLK source form HXT and HCLK source divide 1  */
     CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT, CLK_HCLK_CLK_DIVIDER(1));
 
-    /*  Set HCLK frequency 42MHz */
-    CLK_SetCoreClock(42000000);
+    /* Select HXT/HIRC to clock PLL
+     *
+     * Comparison between HXT/HIRC-clocked PLL:
+     * 1. Spare HXT on board if only HIRC is used.
+     * 2. HIRC has shorter stable time.
+     * 3. HXT has better accuracy. USBD requires HXT-clocked PLL.
+     * 4. HIRC has shorter wake-up time from power-down mode. 
+     *    Per test, wake-up time from power-down mode would take:
+     *    T1. 1~13 ms (proportional to deep sleep time) with HXT-clocked PLL as HCLK clock source
+     *    T2. <1 ms with HIRC-clocked PLL as HCLK clock source
+     *    T1 will fail Greentea test which requires max 10 ms wake-up time.
+     *
+     *    If we just call CLK_SetCoreClock(FREQ_42MHZ) to configure HCLK to 42 MHz,
+     *    it will go T1 with HXT already enabled in front. So we manually configure
+     *    it to choose HXT/HIRC-clocked PLL.
+     */
+#define NU_HXT_PLL      1
+#define NU_HIRC_PLL     2
+
+#ifndef NU_CLOCK_PLL
+#define NU_CLOCK_PLL    NU_HIRC_PLL
+#endif
+
+#if (NU_CLOCK_PLL == NU_HXT_PLL)
+    CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT, FREQ_42MHZ*2);
+    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(2));
+#elif (NU_CLOCK_PLL == NU_HIRC_PLL)
+    CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HIRC, FREQ_42MHZ*2);
+    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(2));
+#endif
 
     /* Update System Core Clock */
     /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
diff --git a/targets/targets.json b/targets/targets.json
index 7dc1188ab5..2da63164fe 100755
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -3953,6 +3953,11 @@
             "gpio-irq-debounce-sample-rate": {
                 "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCLKSEL_1, GPIO_DBCLKSEL_2, GPIO_DBCLKSEL_4, ..., or GPIO_DBCLKSEL_32768",
                 "value": "GPIO_DBCLKSEL_16"
+            },
+            "clock-pll": {
+                "help": "Choose clock source to clock PLL: NU_HXT_PLL or NU_HIRC_PLL",
+                "macro_name": "NU_CLOCK_PLL",
+                "value": "NU_HIRC_PLL"
             }
         },
         "inherits": ["Target"],