mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #484 from ohagendorf/master
[Nucleo_F4x1]: 2 extensions for a) toolchain ARM_GCC and b) test DigitalIn DigitalOutpull/488/head^2
commit
1393115460
|
@ -0,0 +1,151 @@
|
||||||
|
/* Linker script for STM32F411 */
|
||||||
|
|
||||||
|
/* Linker script to configure memory regions. */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||||
|
/* CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K */
|
||||||
|
RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Linker script to place sections and symbol values. Should be used together
|
||||||
|
* with other linker script that defines memory regions FLASH and RAM.
|
||||||
|
* It references following symbols, which must be defined in code:
|
||||||
|
* Reset_Handler : Entry of reset handler
|
||||||
|
*
|
||||||
|
* It defines following symbols, which code can use without definition:
|
||||||
|
* __exidx_start
|
||||||
|
* __exidx_end
|
||||||
|
* __etext
|
||||||
|
* __data_start__
|
||||||
|
* __preinit_array_start
|
||||||
|
* __preinit_array_end
|
||||||
|
* __init_array_start
|
||||||
|
* __init_array_end
|
||||||
|
* __fini_array_start
|
||||||
|
* __fini_array_end
|
||||||
|
* __data_end__
|
||||||
|
* __bss_start__
|
||||||
|
* __bss_end__
|
||||||
|
* __end__
|
||||||
|
* end
|
||||||
|
* __HeapLimit
|
||||||
|
* __StackLimit
|
||||||
|
* __StackTop
|
||||||
|
* __stack
|
||||||
|
*/
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
KEEP(*(.isr_vector))
|
||||||
|
*(.text*)
|
||||||
|
|
||||||
|
KEEP(*(.init))
|
||||||
|
KEEP(*(.fini))
|
||||||
|
|
||||||
|
/* .ctors */
|
||||||
|
*crtbegin.o(.ctors)
|
||||||
|
*crtbegin?.o(.ctors)
|
||||||
|
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||||
|
*(SORT(.ctors.*))
|
||||||
|
*(.ctors)
|
||||||
|
|
||||||
|
/* .dtors */
|
||||||
|
*crtbegin.o(.dtors)
|
||||||
|
*crtbegin?.o(.dtors)
|
||||||
|
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||||
|
*(SORT(.dtors.*))
|
||||||
|
*(.dtors)
|
||||||
|
|
||||||
|
*(.rodata*)
|
||||||
|
|
||||||
|
KEEP(*(.eh_frame*))
|
||||||
|
} > FLASH
|
||||||
|
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} > FLASH
|
||||||
|
|
||||||
|
__exidx_start = .;
|
||||||
|
.ARM.exidx :
|
||||||
|
{
|
||||||
|
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||||
|
} > FLASH
|
||||||
|
__exidx_end = .;
|
||||||
|
|
||||||
|
__etext = .;
|
||||||
|
|
||||||
|
.data : AT (__etext)
|
||||||
|
{
|
||||||
|
__data_start__ = .;
|
||||||
|
*(vtable)
|
||||||
|
*(.data*)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* preinit data */
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP(*(.preinit_array))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* init data */
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP(*(SORT(.init_array.*)))
|
||||||
|
KEEP(*(.init_array))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* finit data */
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP(*(SORT(.fini_array.*)))
|
||||||
|
KEEP(*(.fini_array))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
|
||||||
|
KEEP(*(.jcr*))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* All data end */
|
||||||
|
__data_end__ = .;
|
||||||
|
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__bss_start__ = .;
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__bss_end__ = .;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
.heap (COPY):
|
||||||
|
{
|
||||||
|
__end__ = .;
|
||||||
|
end = __end__;
|
||||||
|
*(.heap*)
|
||||||
|
__HeapLimit = .;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||||
|
* used for linker to calculate size of stack sections, and assign
|
||||||
|
* values to stack symbols later */
|
||||||
|
.stack_dummy (COPY):
|
||||||
|
{
|
||||||
|
*(.stack*)
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Set stack top to end of RAM, and stack limit move down by
|
||||||
|
* size of stack_dummy section */
|
||||||
|
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||||
|
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||||
|
PROVIDE(__stack = __StackTop);
|
||||||
|
|
||||||
|
/* Check if data + heap + stack exceeds RAM limit */
|
||||||
|
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||||
|
}
|
||||||
|
|
|
@ -0,0 +1,297 @@
|
||||||
|
/* File: startup_STM32F40x.S
|
||||||
|
* Purpose: startup file for Cortex-M4 devices. Should use with
|
||||||
|
* GCC for ARM Embedded Processors
|
||||||
|
* Version: V1.4
|
||||||
|
* Date: 09 July 2012
|
||||||
|
*
|
||||||
|
* Copyright (c) 2011, 2012, ARM Limited
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
* Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
* Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
* Neither the name of the ARM Limited nor the
|
||||||
|
names of its contributors may be used to endorse or promote products
|
||||||
|
derived from this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||||
|
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||||
|
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||||
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
.syntax unified
|
||||||
|
.arch armv7-m
|
||||||
|
|
||||||
|
.section .stack
|
||||||
|
.align 3
|
||||||
|
#ifdef __STACK_SIZE
|
||||||
|
.equ Stack_Size, __STACK_SIZE
|
||||||
|
#else
|
||||||
|
.equ Stack_Size, 0xc00
|
||||||
|
#endif
|
||||||
|
.globl __StackTop
|
||||||
|
.globl __StackLimit
|
||||||
|
__StackLimit:
|
||||||
|
.space Stack_Size
|
||||||
|
.size __StackLimit, . - __StackLimit
|
||||||
|
__StackTop:
|
||||||
|
.size __StackTop, . - __StackTop
|
||||||
|
|
||||||
|
.section .heap
|
||||||
|
.align 3
|
||||||
|
#ifdef __HEAP_SIZE
|
||||||
|
.equ Heap_Size, __HEAP_SIZE
|
||||||
|
#else
|
||||||
|
.equ Heap_Size, 0x400
|
||||||
|
#endif
|
||||||
|
.globl __HeapBase
|
||||||
|
.globl __HeapLimit
|
||||||
|
__HeapBase:
|
||||||
|
.if Heap_Size
|
||||||
|
.space Heap_Size
|
||||||
|
.endif
|
||||||
|
.size __HeapBase, . - __HeapBase
|
||||||
|
__HeapLimit:
|
||||||
|
.size __HeapLimit, . - __HeapLimit
|
||||||
|
|
||||||
|
.section .isr_vector
|
||||||
|
.align 2
|
||||||
|
.globl __isr_vector
|
||||||
|
__isr_vector:
|
||||||
|
.long __StackTop /* Top of Stack */
|
||||||
|
.long Reset_Handler /* Reset Handler */
|
||||||
|
.long NMI_Handler /* NMI Handler */
|
||||||
|
.long HardFault_Handler /* Hard Fault Handler */
|
||||||
|
.long MemManage_Handler /* MPU Fault Handler */
|
||||||
|
.long BusFault_Handler /* Bus Fault Handler */
|
||||||
|
.long UsageFault_Handler /* Usage Fault Handler */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long SVC_Handler /* SVCall Handler */
|
||||||
|
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long PendSV_Handler /* PendSV Handler */
|
||||||
|
.long SysTick_Handler /* SysTick Handler */
|
||||||
|
|
||||||
|
/* External interrupts */
|
||||||
|
.long WWDG_IRQHandler /* Window WatchDog */
|
||||||
|
.long PVD_IRQHandler /* PVD through EXTI Line detection */
|
||||||
|
.long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||||
|
.long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||||
|
.long FLASH_IRQHandler /* FLASH */
|
||||||
|
.long RCC_IRQHandler /* RCC */
|
||||||
|
.long EXTI0_IRQHandler /* EXTI Line0 */
|
||||||
|
.long EXTI1_IRQHandler /* EXTI Line1 */
|
||||||
|
.long EXTI2_IRQHandler /* EXTI Line2 */
|
||||||
|
.long EXTI3_IRQHandler /* EXTI Line3 */
|
||||||
|
.long EXTI4_IRQHandler /* EXTI Line4 */
|
||||||
|
.long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||||
|
.long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||||
|
.long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||||
|
.long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||||
|
.long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||||
|
.long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||||
|
.long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||||
|
.long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||||
|
.long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
|
||||||
|
.long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
|
||||||
|
.long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
|
||||||
|
.long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
|
.long TIM2_IRQHandler /* TIM2 */
|
||||||
|
.long TIM3_IRQHandler /* TIM3 */
|
||||||
|
.long TIM4_IRQHandler /* TIM4 */
|
||||||
|
.long I2C1_EV_IRQHandler /* I2C1 Event */
|
||||||
|
.long I2C1_ER_IRQHandler /* I2C1 Error */
|
||||||
|
.long I2C2_EV_IRQHandler /* I2C2 Event */
|
||||||
|
.long I2C2_ER_IRQHandler /* I2C2 Error */
|
||||||
|
.long SPI1_IRQHandler /* SPI1 */
|
||||||
|
.long SPI2_IRQHandler /* SPI2 */
|
||||||
|
.long USART1_IRQHandler /* USART1 */
|
||||||
|
.long USART2_IRQHandler /* USART2 */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||||
|
.long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||||
|
.long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long SDIO_IRQHandler /* SDIO */
|
||||||
|
.long TIM5_IRQHandler /* TIM5 */
|
||||||
|
.long SPI3_IRQHandler /* SPI3 */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||||
|
.long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||||
|
.long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||||
|
.long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||||
|
.long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long OTG_FS_IRQHandler /* USB OTG FS */
|
||||||
|
.long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||||
|
.long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||||
|
.long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||||
|
.long USART6_IRQHandler /* USART6 */
|
||||||
|
.long I2C3_EV_IRQHandler /* I2C3 event */
|
||||||
|
.long I2C3_ER_IRQHandler /* I2C3 error */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long FPU_IRQHandler /* FPU */
|
||||||
|
.long SPI4_IRQHandler /* SPI4 */
|
||||||
|
.long SPI5_IRQHandler /* SPI5 */
|
||||||
|
|
||||||
|
.size __isr_vector, . - __isr_vector
|
||||||
|
|
||||||
|
.text
|
||||||
|
.thumb
|
||||||
|
.thumb_func
|
||||||
|
.align 2
|
||||||
|
.globl Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
/* Loop to copy data from read only memory to RAM. The ranges
|
||||||
|
* of copy from/to are specified by following symbols evaluated in
|
||||||
|
* linker script.
|
||||||
|
* __etext: End of code section, i.e., begin of data sections to copy from.
|
||||||
|
* __data_start__/__data_end__: RAM address range that data should be
|
||||||
|
* copied to. Both must be aligned to 4 bytes boundary. */
|
||||||
|
|
||||||
|
ldr r1, =__etext
|
||||||
|
ldr r2, =__data_start__
|
||||||
|
ldr r3, =__data_end__
|
||||||
|
|
||||||
|
.LC0:
|
||||||
|
cmp r2, r3
|
||||||
|
ittt lt
|
||||||
|
ldrlt r0, [r1], #4
|
||||||
|
strlt r0, [r2], #4
|
||||||
|
blt .LC0
|
||||||
|
|
||||||
|
ldr r0, =SystemInit
|
||||||
|
blx r0
|
||||||
|
ldr r0, =_start
|
||||||
|
bx r0
|
||||||
|
.pool
|
||||||
|
.size Reset_Handler, . - Reset_Handler
|
||||||
|
|
||||||
|
.text
|
||||||
|
/* Macro to define default handlers. Default handler
|
||||||
|
* will be weak symbol and just dead loops. They can be
|
||||||
|
* overwritten by other handlers */
|
||||||
|
.macro def_default_handler handler_name
|
||||||
|
.align 1
|
||||||
|
.thumb_func
|
||||||
|
.weak \handler_name
|
||||||
|
.type \handler_name, %function
|
||||||
|
\handler_name :
|
||||||
|
b .
|
||||||
|
.size \handler_name, . - \handler_name
|
||||||
|
.endm
|
||||||
|
|
||||||
|
def_default_handler NMI_Handler
|
||||||
|
def_default_handler HardFault_Handler
|
||||||
|
def_default_handler MemManage_Handler
|
||||||
|
def_default_handler BusFault_Handler
|
||||||
|
def_default_handler UsageFault_Handler
|
||||||
|
def_default_handler SVC_Handler
|
||||||
|
def_default_handler DebugMon_Handler
|
||||||
|
def_default_handler PendSV_Handler
|
||||||
|
def_default_handler SysTick_Handler
|
||||||
|
def_default_handler Default_Handler
|
||||||
|
|
||||||
|
.macro def_irq_default_handler handler_name
|
||||||
|
.weak \handler_name
|
||||||
|
.set \handler_name, Default_Handler
|
||||||
|
.endm
|
||||||
|
|
||||||
|
def_irq_default_handler WWDG_IRQHandler
|
||||||
|
def_irq_default_handler PVD_IRQHandler
|
||||||
|
def_irq_default_handler TAMP_STAMP_IRQHandler
|
||||||
|
def_irq_default_handler RTC_WKUP_IRQHandler
|
||||||
|
def_irq_default_handler FLASH_IRQHandler
|
||||||
|
def_irq_default_handler RCC_IRQHandler
|
||||||
|
def_irq_default_handler EXTI0_IRQHandler
|
||||||
|
def_irq_default_handler EXTI1_IRQHandler
|
||||||
|
def_irq_default_handler EXTI2_IRQHandler
|
||||||
|
def_irq_default_handler EXTI3_IRQHandler
|
||||||
|
def_irq_default_handler EXTI4_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream0_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream1_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream2_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream3_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream4_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream5_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream6_IRQHandler
|
||||||
|
def_irq_default_handler ADC_IRQHandler
|
||||||
|
def_irq_default_handler EXTI9_5_IRQHandler
|
||||||
|
def_irq_default_handler TIM1_BRK_TIM9_IRQHandler
|
||||||
|
def_irq_default_handler TIM1_UP_TIM10_IRQHandler
|
||||||
|
def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
|
def_irq_default_handler TIM1_CC_IRQHandler
|
||||||
|
def_irq_default_handler TIM2_IRQHandler
|
||||||
|
def_irq_default_handler TIM3_IRQHandler
|
||||||
|
def_irq_default_handler TIM4_IRQHandler
|
||||||
|
def_irq_default_handler I2C1_EV_IRQHandler
|
||||||
|
def_irq_default_handler I2C1_ER_IRQHandler
|
||||||
|
def_irq_default_handler I2C2_EV_IRQHandler
|
||||||
|
def_irq_default_handler I2C2_ER_IRQHandler
|
||||||
|
def_irq_default_handler SPI1_IRQHandler
|
||||||
|
def_irq_default_handler SPI2_IRQHandler
|
||||||
|
def_irq_default_handler USART1_IRQHandler
|
||||||
|
def_irq_default_handler USART2_IRQHandler
|
||||||
|
def_irq_default_handler EXTI15_10_IRQHandler
|
||||||
|
def_irq_default_handler RTC_Alarm_IRQHandler
|
||||||
|
def_irq_default_handler OTG_FS_WKUP_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream7_IRQHandler
|
||||||
|
def_irq_default_handler SDIO_IRQHandler
|
||||||
|
def_irq_default_handler TIM5_IRQHandler
|
||||||
|
def_irq_default_handler SPI3_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream0_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream1_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream2_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream3_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream4_IRQHandler
|
||||||
|
def_irq_default_handler OTG_FS_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream5_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream6_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream7_IRQHandler
|
||||||
|
def_irq_default_handler USART6_IRQHandler
|
||||||
|
def_irq_default_handler I2C3_EV_IRQHandler
|
||||||
|
def_irq_default_handler I2C3_ER_IRQHandler
|
||||||
|
def_irq_default_handler FPU_IRQHandler
|
||||||
|
def_irq_default_handler SPI4_IRQHandler
|
||||||
|
def_irq_default_handler SPI5_IRQHandler
|
||||||
|
def_irq_default_handler DEF_IRQHandler
|
||||||
|
|
||||||
|
.end
|
|
@ -10,7 +10,7 @@ DigitalIn in(dp2);
|
||||||
DigitalOut out(D7);
|
DigitalOut out(D7);
|
||||||
DigitalIn in(D2);
|
DigitalIn in(D2);
|
||||||
|
|
||||||
#elif defined(TARGET_NUCLEO_F103RB)
|
#elif defined(TARGET_NUCLEO_F103RB) || defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE)
|
||||||
DigitalOut out(PC_6);
|
DigitalOut out(PC_6);
|
||||||
DigitalIn in(PB_8);
|
DigitalIn in(PB_8);
|
||||||
|
|
||||||
|
|
|
@ -321,9 +321,9 @@ class NUCLEO_F401RE(Target):
|
||||||
class NUCLEO_F411RE(Target):
|
class NUCLEO_F411RE(Target):
|
||||||
def __init__(self):
|
def __init__(self):
|
||||||
Target.__init__(self)
|
Target.__init__(self)
|
||||||
self.core = "Cortex-M4"
|
self.core = "Cortex-M4F"
|
||||||
self.extra_labels = ['STM', 'STM32F4', 'STM32F411RE']
|
self.extra_labels = ['STM', 'STM32F4', 'STM32F411RE']
|
||||||
self.supported_toolchains = ["ARM", "uARM"]
|
self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"]
|
||||||
self.default_toolchain = "uARM"
|
self.default_toolchain = "uARM"
|
||||||
self.supported_form_factors = ["ARDUINO", "MORPHO"]
|
self.supported_form_factors = ["ARDUINO", "MORPHO"]
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue