mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #2473 from svastm/ethernet_mbed_5
[STM32] Add ethernet and feature IPV4pull/2495/merge
Martin Kojtal
GitHub
commit
133f16aa5d
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@ -0,0 +1,87 @@
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#include "stm32f2xx_hal.h"
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/**
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* Override HAL Eth Init function
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*/
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void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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if (heth->Instance == ETH) {
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/* Enable GPIOs clocks */
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__HAL_RCC_GPIOA_CLK_ENABLE();
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__HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_GPIOG_CLK_ENABLE();
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/** ETH GPIO Configuration
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RMII_REF_CLK ----------------------> PA1
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RMII_MDIO -------------------------> PA2
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RMII_MDC --------------------------> PC1
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RMII_MII_CRS_DV -------------------> PA7
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RMII_MII_RXD0 ---------------------> PC4
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RMII_MII_RXD1 ---------------------> PC5
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RMII_MII_RXER ---------------------> PG2
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RMII_MII_TX_EN --------------------> PG11
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RMII_MII_TXD0 ---------------------> PG13
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RMII_MII_TXD1 ---------------------> PB13
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*/
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/* Configure PA1, PA2 and PA7 */
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GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
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GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStructure.Pull = GPIO_NOPULL;
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GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
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GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
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/* Configure PB13 */
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GPIO_InitStructure.Pin = GPIO_PIN_13;
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HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
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/* Configure PC1, PC4 and PC5 */
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GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
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HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
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/* Configure PG2, PG11 and PG13 */
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GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13;
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HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
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/* Enable the Ethernet global Interrupt */
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HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
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HAL_NVIC_EnableIRQ(ETH_IRQn);
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/* Enable ETHERNET clock */
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__HAL_RCC_ETH_CLK_ENABLE();
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}
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}
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/**
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* Override HAL Eth DeInit function
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*/
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void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
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{
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if (heth->Instance == ETH) {
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/* Peripheral clock disable */
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__HAL_RCC_ETH_CLK_DISABLE();
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/** ETH GPIO Configuration
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RMII_REF_CLK ----------------------> PA1
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RMII_MDIO -------------------------> PA2
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RMII_MDC --------------------------> PC1
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RMII_MII_CRS_DV -------------------> PA7
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RMII_MII_RXD0 ---------------------> PC4
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RMII_MII_RXD1 ---------------------> PC5
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RMII_MII_RXER ---------------------> PG2
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RMII_MII_TX_EN --------------------> PG11
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RMII_MII_TXD0 ---------------------> PG13
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RMII_MII_TXD1 ---------------------> PB13
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*/
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HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
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HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
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HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
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HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13);
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/* Disable the Ethernet global Interrupt */
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NVIC_DisableIRQ(ETH_IRQn);
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}
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}
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@ -0,0 +1,452 @@
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#include "stm32f2xx_hal.h"
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#include "lwip/opt.h"
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#include "lwip/timers.h"
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#include "netif/etharp.h"
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#include "lwip/tcpip.h"
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#include <string.h>
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#include "cmsis_os.h"
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#include "mbed_interface.h"
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#define RECV_TASK_PRI (osPriorityHigh)
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#define PHY_TASK_PRI (osPriorityLow)
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#define PHY_TASK_WAIT (200)
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#define ETH_ARCH_PHY_ADDRESS (0x00)
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ETH_HandleTypeDef EthHandle;
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#if defined (__ICCARM__) /*!< IAR Compiler */
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#pragma data_alignment=4
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#endif
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__ALIGN_BEGIN ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB] __ALIGN_END; /* Ethernet Rx DMA Descriptor */
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#if defined (__ICCARM__) /*!< IAR Compiler */
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#pragma data_alignment=4
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#endif
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__ALIGN_BEGIN ETH_DMADescTypeDef DMATxDscrTab[ETH_TXBUFNB] __ALIGN_END; /* Ethernet Tx DMA Descriptor */
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#if defined (__ICCARM__) /*!< IAR Compiler */
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#pragma data_alignment=4
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#endif
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__ALIGN_BEGIN uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __ALIGN_END; /* Ethernet Receive Buffer */
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#if defined (__ICCARM__) /*!< IAR Compiler */
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#pragma data_alignment=4
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#endif
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__ALIGN_BEGIN uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __ALIGN_END; /* Ethernet Transmit Buffer */
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static sys_sem_t rx_ready_sem; /* receive ready semaphore */
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static sys_mutex_t tx_lock_mutex;
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/* function */
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static void _eth_arch_rx_task(void *arg);
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static void _eth_arch_phy_task(void *arg);
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static err_t _eth_arch_netif_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr);
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static err_t _eth_arch_low_level_output(struct netif *netif, struct pbuf *p);
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static struct pbuf * _eth_arch_low_level_input(struct netif *netif);
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/**
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* Ethernet Rx Transfer completed callback
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*
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* @param heth: ETH handle
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* @retval None
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*/
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void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
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{
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sys_sem_signal(&rx_ready_sem);
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}
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/**
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* Ethernet IRQ Handler
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*
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* @param None
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* @retval None
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*/
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void ETH_IRQHandler(void)
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{
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HAL_ETH_IRQHandler(&EthHandle);
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}
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/**
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* In this function, the hardware should be initialized.
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* Called from eth_arch_enetif_init().
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*
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* @param netif the already initialized lwip network interface structure
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* for this ethernetif
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*/
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static void _eth_arch_low_level_init(struct netif *netif)
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{
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uint32_t regvalue = 0;
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HAL_StatusTypeDef hal_eth_init_status;
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/* Init ETH */
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uint8_t MACAddr[6];
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EthHandle.Instance = ETH;
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EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
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EthHandle.Init.Speed = ETH_SPEED_100M;
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EthHandle.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
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EthHandle.Init.PhyAddress = ETH_ARCH_PHY_ADDRESS;
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#if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
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MACAddr[0] = MBED_MAC_ADDR_0;
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MACAddr[1] = MBED_MAC_ADDR_1;
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MACAddr[2] = MBED_MAC_ADDR_2;
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MACAddr[3] = MBED_MAC_ADDR_3;
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MACAddr[4] = MBED_MAC_ADDR_4;
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MACAddr[5] = MBED_MAC_ADDR_5;
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#else
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mbed_mac_address((char *)MACAddr);
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#endif
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EthHandle.Init.MACAddr = &MACAddr[0];
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EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE;
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EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
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EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
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hal_eth_init_status = HAL_ETH_Init(&EthHandle);
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/* Initialize Tx Descriptors list: Chain Mode */
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HAL_ETH_DMATxDescListInit(&EthHandle, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
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/* Initialize Rx Descriptors list: Chain Mode */
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HAL_ETH_DMARxDescListInit(&EthHandle, DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
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#if LWIP_ARP || LWIP_ETHERNET
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/* set MAC hardware address length */
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netif->hwaddr_len = ETHARP_HWADDR_LEN;
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/* set MAC hardware address */
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netif->hwaddr[0] = EthHandle.Init.MACAddr[0];
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netif->hwaddr[1] = EthHandle.Init.MACAddr[1];
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netif->hwaddr[2] = EthHandle.Init.MACAddr[2];
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netif->hwaddr[3] = EthHandle.Init.MACAddr[3];
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netif->hwaddr[4] = EthHandle.Init.MACAddr[4];
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netif->hwaddr[5] = EthHandle.Init.MACAddr[5];
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/* maximum transfer unit */
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netif->mtu = 1500;
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/* device capabilities */
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/* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
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netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
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/* Enable MAC and DMA transmission and reception */
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HAL_ETH_Start(&EthHandle);
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/**** Configure PHY to generate an interrupt when Eth Link state changes ****/
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/* Read Register Configuration */
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HAL_ETH_ReadPHYRegister(&EthHandle, PHY_MICR, ®value);
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regvalue |= (PHY_MICR_INT_EN | PHY_MICR_INT_OE);
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/* Enable Interrupts */
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HAL_ETH_WritePHYRegister(&EthHandle, PHY_MICR, regvalue);
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/* Read Register Configuration */
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HAL_ETH_ReadPHYRegister(&EthHandle, PHY_MISR, ®value);
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regvalue |= PHY_MISR_LINK_INT_EN;
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/* Enable Interrupt on change of link status */
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HAL_ETH_WritePHYRegister(&EthHandle, PHY_MISR, regvalue);
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#endif
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}
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/**
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* This function should do the actual transmission of the packet. The packet is
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* contained in the pbuf that is passed to the function. This pbuf
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* might be chained.
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*
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* @param netif the lwip network interface structure for this ethernetif
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* @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
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* @return ERR_OK if the packet could be sent
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* an err_t value if the packet couldn't be sent
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*
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* @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
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* strange results. You might consider waiting for space in the DMA queue
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* to become availale since the stack doesn't retry to send a packet
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* dropped because of memory failure (except for the TCP timers).
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*/
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static err_t _eth_arch_low_level_output(struct netif *netif, struct pbuf *p)
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{
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err_t errval;
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struct pbuf *q;
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uint8_t *buffer = (uint8_t*)(EthHandle.TxDesc->Buffer1Addr);
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__IO ETH_DMADescTypeDef *DmaTxDesc;
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uint32_t framelength = 0;
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uint32_t bufferoffset = 0;
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uint32_t byteslefttocopy = 0;
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uint32_t payloadoffset = 0;
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DmaTxDesc = EthHandle.TxDesc;
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bufferoffset = 0;
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sys_mutex_lock(&tx_lock_mutex);
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/* copy frame from pbufs to driver buffers */
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for (q = p; q != NULL; q = q->next) {
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/* Is this buffer available? If not, goto error */
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if ((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET) {
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errval = ERR_USE;
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goto error;
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}
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/* Get bytes in current lwIP buffer */
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byteslefttocopy = q->len;
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payloadoffset = 0;
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/* Check if the length of data to copy is bigger than Tx buffer size*/
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while ((byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE) {
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/* Copy data to Tx buffer*/
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memcpy((uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset));
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/* Point to next descriptor */
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DmaTxDesc = (ETH_DMADescTypeDef*)(DmaTxDesc->Buffer2NextDescAddr);
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/* Check if the buffer is available */
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if ((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET) {
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errval = ERR_USE;
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goto error;
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}
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buffer = (uint8_t*)(DmaTxDesc->Buffer1Addr);
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byteslefttocopy = byteslefttocopy - (ETH_TX_BUF_SIZE - bufferoffset);
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payloadoffset = payloadoffset + (ETH_TX_BUF_SIZE - bufferoffset);
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framelength = framelength + (ETH_TX_BUF_SIZE - bufferoffset);
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bufferoffset = 0;
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}
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/* Copy the remaining bytes */
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memcpy((uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), byteslefttocopy);
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bufferoffset = bufferoffset + byteslefttocopy;
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framelength = framelength + byteslefttocopy;
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}
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/* Prepare transmit descriptors to give to DMA */
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HAL_ETH_TransmitFrame(&EthHandle, framelength);
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errval = ERR_OK;
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error:
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/* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */
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if ((EthHandle.Instance->DMASR & ETH_DMASR_TUS) != (uint32_t)RESET) {
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/* Clear TUS ETHERNET DMA flag */
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EthHandle.Instance->DMASR = ETH_DMASR_TUS;
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/* Resume DMA transmission*/
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EthHandle.Instance->DMATPDR = 0;
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}
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sys_mutex_unlock(&tx_lock_mutex);
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return errval;
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}
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/**
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* Should allocate a pbuf and transfer the bytes of the incoming
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* packet from the interface into the pbuf.
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*
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* @param netif the lwip network interface structure for this ethernetif
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* @return a pbuf filled with the received packet (including MAC header)
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* NULL on memory error
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*/
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static struct pbuf * _eth_arch_low_level_input(struct netif *netif)
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{
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struct pbuf *p = NULL;
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struct pbuf *q;
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uint16_t len = 0;
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uint8_t *buffer;
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__IO ETH_DMADescTypeDef *dmarxdesc;
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uint32_t bufferoffset = 0;
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uint32_t payloadoffset = 0;
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uint32_t byteslefttocopy = 0;
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uint32_t i = 0;
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/* get received frame */
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if (HAL_ETH_GetReceivedFrame(&EthHandle) != HAL_OK)
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return NULL;
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/* Obtain the size of the packet and put it into the "len" variable. */
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len = EthHandle.RxFrameInfos.length;
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buffer = (uint8_t*)EthHandle.RxFrameInfos.buffer;
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if (len > 0) {
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/* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
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p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
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}
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if (p != NULL) {
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dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc;
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bufferoffset = 0;
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for (q = p; q != NULL; q = q->next) {
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byteslefttocopy = q->len;
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payloadoffset = 0;
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/* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/
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while ((byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE) {
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/* Copy data to pbuf */
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memcpy((uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
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/* Point to next descriptor */
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dmarxdesc = (ETH_DMADescTypeDef*)(dmarxdesc->Buffer2NextDescAddr);
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buffer = (uint8_t*)(dmarxdesc->Buffer1Addr);
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byteslefttocopy = byteslefttocopy - (ETH_RX_BUF_SIZE - bufferoffset);
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payloadoffset = payloadoffset + (ETH_RX_BUF_SIZE - bufferoffset);
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bufferoffset = 0;
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}
|
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/* Copy remaining data in pbuf */
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memcpy((uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), byteslefttocopy);
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bufferoffset = bufferoffset + byteslefttocopy;
|
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}
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/* Release descriptors to DMA */
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/* Point to first descriptor */
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dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc;
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/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
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for (i = 0; i < EthHandle.RxFrameInfos.SegCount; i++) {
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dmarxdesc->Status |= ETH_DMARXDESC_OWN;
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dmarxdesc = (ETH_DMADescTypeDef*)(dmarxdesc->Buffer2NextDescAddr);
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}
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/* Clear Segment_Count */
|
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EthHandle.RxFrameInfos.SegCount = 0;
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}
|
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|
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/* When Rx Buffer unavailable flag is set: clear it and resume reception */
|
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if ((EthHandle.Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) {
|
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/* Clear RBUS ETHERNET DMA flag */
|
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EthHandle.Instance->DMASR = ETH_DMASR_RBUS;
|
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/* Resume DMA reception */
|
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EthHandle.Instance->DMARPDR = 0;
|
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}
|
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return p;
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}
|
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|
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/**
|
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* This task receives input data
|
||||
*
|
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* \param[in] netif the lwip network interface structure
|
||||
*/
|
||||
static void _eth_arch_rx_task(void *arg)
|
||||
{
|
||||
struct netif *netif = (struct netif*)arg;
|
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struct pbuf *p;
|
||||
|
||||
while (1) {
|
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sys_arch_sem_wait(&rx_ready_sem, 0);
|
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p = _eth_arch_low_level_input(netif);
|
||||
if (p != NULL) {
|
||||
if (netif->input(p, netif) != ERR_OK) {
|
||||
pbuf_free(p);
|
||||
p = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
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|
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/**
|
||||
* This task checks phy link status and updates net status
|
||||
*
|
||||
* \param[in] netif the lwip network interface structure
|
||||
*/
|
||||
static void _eth_arch_phy_task(void *arg)
|
||||
{
|
||||
struct netif *netif = (struct netif*)arg;
|
||||
uint32_t phy_status = 0;
|
||||
|
||||
while (1) {
|
||||
uint32_t status;
|
||||
if (HAL_ETH_ReadPHYRegister(&EthHandle, PHY_SR, &status) == HAL_OK) {
|
||||
if ((status & PHY_LINK_STATUS) && !(phy_status & PHY_LINK_STATUS)) {
|
||||
tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_up, (void*) netif, 1);
|
||||
} else if (!(status & PHY_LINK_STATUS) && (phy_status & PHY_LINK_STATUS)) {
|
||||
tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_down, (void*) netif, 1);
|
||||
}
|
||||
phy_status = status;
|
||||
}
|
||||
osDelay(PHY_TASK_WAIT);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* This function is the ethernet packet send function. It calls
|
||||
* etharp_output after checking link status.
|
||||
*
|
||||
* \param[in] netif the lwip network interface structure for this lpc_enetif
|
||||
* \param[in] q Pointer to pbug to send
|
||||
* \param[in] ipaddr IP address
|
||||
* \return ERR_OK or error code
|
||||
*/
|
||||
static err_t _eth_arch_netif_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr)
|
||||
{
|
||||
/* Only send packet is link is up */
|
||||
if (netif->flags & NETIF_FLAG_LINK_UP) {
|
||||
return etharp_output(netif, q, ipaddr);
|
||||
}
|
||||
return ERR_CONN;
|
||||
}
|
||||
|
||||
/**
|
||||
* Should be called at the beginning of the program to set up the
|
||||
* network interface.
|
||||
*
|
||||
* This function should be passed as a parameter to netif_add().
|
||||
*
|
||||
* @param[in] netif the lwip network interface structure for this lpc_enetif
|
||||
* @return ERR_OK if the loopif is initialized
|
||||
* ERR_MEM if private data couldn't be allocated
|
||||
* any other err_t on error
|
||||
*/
|
||||
err_t eth_arch_enetif_init(struct netif *netif)
|
||||
{
|
||||
/* set MAC hardware address */
|
||||
netif->hwaddr_len = ETHARP_HWADDR_LEN;
|
||||
|
||||
/* maximum transfer unit */
|
||||
netif->mtu = 1500;
|
||||
|
||||
/* device capabilities */
|
||||
netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET | NETIF_FLAG_IGMP;
|
||||
|
||||
#if LWIP_NETIF_HOSTNAME
|
||||
/* Initialize interface hostname */
|
||||
netif->hostname = "lwipstm32";
|
||||
#endif /* LWIP_NETIF_HOSTNAME */
|
||||
|
||||
netif->name[0] = 'e';
|
||||
netif->name[1] = 'n';
|
||||
|
||||
netif->output = _eth_arch_netif_output;
|
||||
netif->linkoutput = _eth_arch_low_level_output;
|
||||
|
||||
/* semaphore */
|
||||
sys_sem_new(&rx_ready_sem, 0);
|
||||
|
||||
sys_mutex_new(&tx_lock_mutex);
|
||||
|
||||
/* task */
|
||||
sys_thread_new("_eth_arch_rx_task", _eth_arch_rx_task, netif, DEFAULT_THREAD_STACKSIZE, RECV_TASK_PRI);
|
||||
sys_thread_new("_eth_arch_phy_task", _eth_arch_phy_task, netif, DEFAULT_THREAD_STACKSIZE, PHY_TASK_PRI);
|
||||
|
||||
/* initialize the hardware */
|
||||
_eth_arch_low_level_init(netif);
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
void eth_arch_enable_interrupts(void)
|
||||
{
|
||||
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
|
||||
HAL_NVIC_EnableIRQ(ETH_IRQn);
|
||||
}
|
||||
|
||||
void eth_arch_disable_interrupts(void)
|
||||
{
|
||||
NVIC_DisableIRQ(ETH_IRQn);
|
||||
}
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/**
|
||||
* Override HAL Eth Init function
|
||||
*/
|
||||
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
if (heth->Instance == ETH) {
|
||||
|
||||
/* Enable GPIOs clocks */
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
|
||||
/** ETH GPIO Configuration
|
||||
RMII_REF_CLK ----------------------> PA1
|
||||
RMII_MDIO -------------------------> PA2
|
||||
RMII_MDC --------------------------> PC1
|
||||
RMII_MII_CRS_DV -------------------> PA7
|
||||
RMII_MII_RXD0 ---------------------> PC4
|
||||
RMII_MII_RXD1 ---------------------> PC5
|
||||
RMII_MII_RXER --------------------->
|
||||
RMII_MII_TX_EN --------------------> PB11
|
||||
RMII_MII_TXD0 ---------------------> PB12
|
||||
RMII_MII_TXD1 ---------------------> PB13
|
||||
*/
|
||||
/* Configure PA1, PA2 and PA7 */
|
||||
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
|
||||
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
/* Configure PB11, PB12 and PB13 */
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
|
||||
/* Configure PC1, PC4 and PC5 */
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
|
||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
|
||||
/* Enable the Ethernet global Interrupt */
|
||||
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
|
||||
HAL_NVIC_EnableIRQ(ETH_IRQn);
|
||||
|
||||
/* Enable ETHERNET clock */
|
||||
__HAL_RCC_ETH_CLK_ENABLE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Override HAL Eth DeInit function
|
||||
*/
|
||||
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
|
||||
{
|
||||
if (heth->Instance == ETH) {
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_ETH_CLK_DISABLE();
|
||||
|
||||
/** ETH GPIO Configuration
|
||||
RMII_REF_CLK ----------------------> PA1
|
||||
RMII_MDIO -------------------------> PA2
|
||||
RMII_MDC --------------------------> PC1
|
||||
RMII_MII_CRS_DV -------------------> PA7
|
||||
RMII_MII_RXD0 ---------------------> PC4
|
||||
RMII_MII_RXD1 ---------------------> PC5
|
||||
RMII_MII_RXER --------------------->
|
||||
RMII_MII_TX_EN --------------------> PB11
|
||||
RMII_MII_TXD0 ---------------------> PB12
|
||||
RMII_MII_TXD1 ---------------------> PB13
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
|
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13);
|
||||
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
|
||||
|
||||
/* Disable the Ethernet global Interrupt */
|
||||
NVIC_DisableIRQ(ETH_IRQn);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/**
|
||||
* Override HAL Eth Init function
|
||||
*/
|
||||
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
if (heth->Instance == ETH) {
|
||||
|
||||
/* Enable GPIOs clocks */
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
|
||||
/** ETH GPIO Configuration
|
||||
RMII_REF_CLK ----------------------> PA1
|
||||
RMII_MDIO -------------------------> PA2
|
||||
RMII_MDC --------------------------> PC1
|
||||
RMII_MII_CRS_DV -------------------> PA7
|
||||
RMII_MII_RXD0 ---------------------> PC4
|
||||
RMII_MII_RXD1 ---------------------> PC5
|
||||
RMII_MII_RXER ---------------------> PG2
|
||||
RMII_MII_TX_EN --------------------> PG11
|
||||
RMII_MII_TXD0 ---------------------> PG13
|
||||
RMII_MII_TXD1 ---------------------> PB13
|
||||
*/
|
||||
/* Configure PA1, PA2 and PA7 */
|
||||
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
|
||||
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
/* Configure PB13 */
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_13;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
|
||||
/* Configure PC1, PC4 and PC5 */
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
|
||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
|
||||
/* Configure PG2, PG11 and PG13 */
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13;
|
||||
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
|
||||
|
||||
/* Enable the Ethernet global Interrupt */
|
||||
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
|
||||
HAL_NVIC_EnableIRQ(ETH_IRQn);
|
||||
|
||||
/* Enable ETHERNET clock */
|
||||
__HAL_RCC_ETH_CLK_ENABLE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Override HAL Eth DeInit function
|
||||
*/
|
||||
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
|
||||
{
|
||||
if (heth->Instance == ETH) {
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_ETH_CLK_DISABLE();
|
||||
|
||||
/** ETH GPIO Configuration
|
||||
RMII_REF_CLK ----------------------> PA1
|
||||
RMII_MDIO -------------------------> PA2
|
||||
RMII_MDC --------------------------> PC1
|
||||
RMII_MII_CRS_DV -------------------> PA7
|
||||
RMII_MII_RXD0 ---------------------> PC4
|
||||
RMII_MII_RXD1 ---------------------> PC5
|
||||
RMII_MII_RXER ---------------------> PG2
|
||||
RMII_MII_TX_EN --------------------> PG11
|
||||
RMII_MII_TXD0 ---------------------> PG13
|
||||
RMII_MII_TXD1 ---------------------> PB13
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
|
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
|
||||
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
|
||||
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13);
|
||||
|
||||
/* Disable the Ethernet global Interrupt */
|
||||
NVIC_DisableIRQ(ETH_IRQn);
|
||||
}
|
||||
}
|
||||
|
|
@ -1,4 +1,3 @@
|
|||
#if defined(TARGET_STM32F4)
|
||||
#include "stm32f4xx_hal.h"
|
||||
#include "lwip/opt.h"
|
||||
|
||||
|
|
@ -9,21 +8,17 @@
|
|||
#include "cmsis_os.h"
|
||||
#include "mbed_interface.h"
|
||||
|
||||
/** @defgroup lwipstm32f4xx_emac_DRIVER stm32f4 EMAC driver for LWIP
|
||||
* @ingroup lwip_emac
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RECV_TASK_PRI (osPriorityHigh)
|
||||
#define PHY_TASK_PRI (osPriorityLow)
|
||||
#define PHY_TASK_WAIT (200)
|
||||
#define ETH_ARCH_PHY_ADDRESS (0x00)
|
||||
|
||||
ETH_HandleTypeDef EthHandle;
|
||||
|
||||
#if defined (__ICCARM__) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
__ALIGN_BEGIN ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB] __ALIGN_END; /* Ethernet Rx MA Descriptor */
|
||||
__ALIGN_BEGIN ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB] __ALIGN_END; /* Ethernet Rx DMA Descriptor */
|
||||
|
||||
#if defined (__ICCARM__) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
|
|
@ -31,7 +26,7 @@ __ALIGN_BEGIN ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB] __ALIGN_END; /* Ether
|
|||
__ALIGN_BEGIN ETH_DMADescTypeDef DMATxDscrTab[ETH_TXBUFNB] __ALIGN_END; /* Ethernet Tx DMA Descriptor */
|
||||
|
||||
#if defined (__ICCARM__) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
__ALIGN_BEGIN uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __ALIGN_END; /* Ethernet Receive Buffer */
|
||||
|
||||
|
|
@ -40,102 +35,15 @@ __ALIGN_BEGIN uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __ALIGN_END; /* Ethe
|
|||
#endif
|
||||
__ALIGN_BEGIN uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __ALIGN_END; /* Ethernet Transmit Buffer */
|
||||
|
||||
|
||||
ETH_HandleTypeDef heth;
|
||||
|
||||
static sys_sem_t rx_ready_sem; /* receive ready semaphore */
|
||||
static sys_mutex_t tx_lock_mutex;
|
||||
|
||||
/* function */
|
||||
static void stm32f4_rx_task(void *arg);
|
||||
static void stm32f4_phy_task(void *arg);
|
||||
static err_t stm32f4_etharp_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr);
|
||||
static err_t stm32f4_low_level_output(struct netif *netif, struct pbuf *p);
|
||||
|
||||
/**
|
||||
* Override HAL Eth Init function
|
||||
*/
|
||||
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
if (heth->Instance == ETH) {
|
||||
/* Peripheral clock enable */
|
||||
__ETH_CLK_ENABLE();
|
||||
|
||||
__GPIOA_CLK_ENABLE();
|
||||
__GPIOB_CLK_ENABLE();
|
||||
__GPIOC_CLK_ENABLE();
|
||||
|
||||
/**ETH GPIO Configuration
|
||||
PC1 ------> ETH_MDC
|
||||
PA1 ------> ETH_REF_CLK
|
||||
PA2 ------> ETH_MDIO
|
||||
PA7 ------> ETH_CRS_DV
|
||||
PC4 ------> ETH_RXD0
|
||||
PC5 ------> ETH_RXD1
|
||||
PB11 ------> ETH_TX_EN
|
||||
PB12 ------> ETH_TXD0
|
||||
PB13 ------> ETH_TXD1
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
/* Peripheral interrupt init*/
|
||||
/* Sets the priority grouping field */
|
||||
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
||||
HAL_NVIC_SetPriority(ETH_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(ETH_IRQn);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Override HAL Eth DeInit function
|
||||
*/
|
||||
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
|
||||
{
|
||||
if (heth->Instance == ETH) {
|
||||
/* Peripheral clock disable */
|
||||
__ETH_CLK_DISABLE();
|
||||
|
||||
/**ETH GPIO Configuration
|
||||
PC1 ------> ETH_MDC
|
||||
PA1 ------> ETH_REF_CLK
|
||||
PA2 ------> ETH_MDIO
|
||||
PA7 ------> ETH_CRS_DV
|
||||
PC4 ------> ETH_RXD0
|
||||
PC5 ------> ETH_RXD1
|
||||
PB11 ------> ETH_TX_EN
|
||||
PB12 ------> ETH_TXD0
|
||||
PB13 ------> ETH_TXD1
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13);
|
||||
|
||||
/* Peripheral interrupt Deinit*/
|
||||
HAL_NVIC_DisableIRQ(ETH_IRQn);
|
||||
}
|
||||
}
|
||||
static void _eth_arch_rx_task(void *arg);
|
||||
static void _eth_arch_phy_task(void *arg);
|
||||
static err_t _eth_arch_netif_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr);
|
||||
static err_t _eth_arch_low_level_output(struct netif *netif, struct pbuf *p);
|
||||
static struct pbuf * _eth_arch_low_level_input(struct netif *netif);
|
||||
|
||||
/**
|
||||
* Ethernet Rx Transfer completed callback
|
||||
|
|
@ -145,7 +53,6 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
|
|||
*/
|
||||
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
|
||||
sys_sem_signal(&rx_ready_sem);
|
||||
}
|
||||
|
||||
|
|
@ -158,7 +65,7 @@ void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
|
|||
*/
|
||||
void ETH_IRQHandler(void)
|
||||
{
|
||||
HAL_ETH_IRQHandler(&heth);
|
||||
HAL_ETH_IRQHandler(&EthHandle);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -170,18 +77,18 @@ void ETH_IRQHandler(void)
|
|||
* @param netif the already initialized lwip network interface structure
|
||||
* for this ethernetif
|
||||
*/
|
||||
static void stm32f4_low_level_init(struct netif *netif)
|
||||
static void _eth_arch_low_level_init(struct netif *netif)
|
||||
{
|
||||
uint32_t regvalue = 0;
|
||||
HAL_StatusTypeDef hal_eth_init_status;
|
||||
|
||||
/* Init ETH */
|
||||
uint8_t MACAddr[6];
|
||||
heth.Instance = ETH;
|
||||
heth.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
|
||||
heth.Init.Speed = ETH_SPEED_10M;
|
||||
heth.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
|
||||
heth.Init.PhyAddress = 1;
|
||||
EthHandle.Instance = ETH;
|
||||
EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
|
||||
EthHandle.Init.Speed = ETH_SPEED_100M;
|
||||
EthHandle.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
|
||||
EthHandle.Init.PhyAddress = ETH_ARCH_PHY_ADDRESS;
|
||||
#if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
|
||||
MACAddr[0] = MBED_MAC_ADDR_0;
|
||||
MACAddr[1] = MBED_MAC_ADDR_1;
|
||||
|
|
@ -190,36 +97,31 @@ static void stm32f4_low_level_init(struct netif *netif)
|
|||
MACAddr[4] = MBED_MAC_ADDR_4;
|
||||
MACAddr[5] = MBED_MAC_ADDR_5;
|
||||
#else
|
||||
mbed_mac_address((char *)MACAddr);
|
||||
mbed_mac_address((char *)MACAddr);
|
||||
#endif
|
||||
heth.Init.MACAddr = &MACAddr[0];
|
||||
heth.Init.RxMode = ETH_RXINTERRUPT_MODE;
|
||||
heth.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
|
||||
heth.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
|
||||
hal_eth_init_status = HAL_ETH_Init(&heth);
|
||||
|
||||
if (hal_eth_init_status == HAL_OK) {
|
||||
/* Set netif link flag */
|
||||
netif->flags |= NETIF_FLAG_LINK_UP;
|
||||
}
|
||||
EthHandle.Init.MACAddr = &MACAddr[0];
|
||||
EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE;
|
||||
EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
|
||||
EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
|
||||
hal_eth_init_status = HAL_ETH_Init(&EthHandle);
|
||||
|
||||
/* Initialize Tx Descriptors list: Chain Mode */
|
||||
HAL_ETH_DMATxDescListInit(&heth, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
|
||||
HAL_ETH_DMATxDescListInit(&EthHandle, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
|
||||
|
||||
/* Initialize Rx Descriptors list: Chain Mode */
|
||||
HAL_ETH_DMARxDescListInit(&heth, DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
|
||||
HAL_ETH_DMARxDescListInit(&EthHandle, DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
|
||||
|
||||
#if LWIP_ARP || LWIP_ETHERNET
|
||||
/* set MAC hardware address length */
|
||||
netif->hwaddr_len = ETHARP_HWADDR_LEN;
|
||||
|
||||
/* set MAC hardware address */
|
||||
netif->hwaddr[0] = heth.Init.MACAddr[0];
|
||||
netif->hwaddr[1] = heth.Init.MACAddr[1];
|
||||
netif->hwaddr[2] = heth.Init.MACAddr[2];
|
||||
netif->hwaddr[3] = heth.Init.MACAddr[3];
|
||||
netif->hwaddr[4] = heth.Init.MACAddr[4];
|
||||
netif->hwaddr[5] = heth.Init.MACAddr[5];
|
||||
netif->hwaddr[0] = EthHandle.Init.MACAddr[0];
|
||||
netif->hwaddr[1] = EthHandle.Init.MACAddr[1];
|
||||
netif->hwaddr[2] = EthHandle.Init.MACAddr[2];
|
||||
netif->hwaddr[3] = EthHandle.Init.MACAddr[3];
|
||||
netif->hwaddr[4] = EthHandle.Init.MACAddr[4];
|
||||
netif->hwaddr[5] = EthHandle.Init.MACAddr[5];
|
||||
|
||||
/* maximum transfer unit */
|
||||
netif->mtu = 1500;
|
||||
|
|
@ -229,24 +131,24 @@ static void stm32f4_low_level_init(struct netif *netif)
|
|||
netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
|
||||
|
||||
/* Enable MAC and DMA transmission and reception */
|
||||
HAL_ETH_Start(&heth);
|
||||
HAL_ETH_Start(&EthHandle);
|
||||
|
||||
/**** Configure PHY to generate an interrupt when Eth Link state changes ****/
|
||||
/* Read Register Configuration */
|
||||
HAL_ETH_ReadPHYRegister(&heth, PHY_MICR, ®value);
|
||||
HAL_ETH_ReadPHYRegister(&EthHandle, PHY_MICR, ®value);
|
||||
|
||||
regvalue |= (PHY_MICR_INT_EN | PHY_MICR_INT_OE);
|
||||
|
||||
/* Enable Interrupts */
|
||||
HAL_ETH_WritePHYRegister(&heth, PHY_MICR, regvalue);
|
||||
HAL_ETH_WritePHYRegister(&EthHandle, PHY_MICR, regvalue);
|
||||
|
||||
/* Read Register Configuration */
|
||||
HAL_ETH_ReadPHYRegister(&heth, PHY_MISR, ®value);
|
||||
HAL_ETH_ReadPHYRegister(&EthHandle, PHY_MISR, ®value);
|
||||
|
||||
regvalue |= PHY_MISR_LINK_INT_EN;
|
||||
|
||||
/* Enable Interrupt on change of link status */
|
||||
HAL_ETH_WritePHYRegister(&heth, PHY_MISR, regvalue);
|
||||
HAL_ETH_WritePHYRegister(&EthHandle, PHY_MISR, regvalue);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -266,17 +168,17 @@ static void stm32f4_low_level_init(struct netif *netif)
|
|||
* dropped because of memory failure (except for the TCP timers).
|
||||
*/
|
||||
|
||||
static err_t stm32f4_low_level_output(struct netif *netif, struct pbuf *p)
|
||||
static err_t _eth_arch_low_level_output(struct netif *netif, struct pbuf *p)
|
||||
{
|
||||
err_t errval;
|
||||
struct pbuf *q;
|
||||
uint8_t *buffer = (uint8_t*)(heth.TxDesc->Buffer1Addr);
|
||||
uint8_t *buffer = (uint8_t*)(EthHandle.TxDesc->Buffer1Addr);
|
||||
__IO ETH_DMADescTypeDef *DmaTxDesc;
|
||||
uint32_t framelength = 0;
|
||||
uint32_t bufferoffset = 0;
|
||||
uint32_t byteslefttocopy = 0;
|
||||
uint32_t payloadoffset = 0;
|
||||
DmaTxDesc = heth.TxDesc;
|
||||
DmaTxDesc = EthHandle.TxDesc;
|
||||
bufferoffset = 0;
|
||||
|
||||
|
||||
|
|
@ -323,19 +225,19 @@ static err_t stm32f4_low_level_output(struct netif *netif, struct pbuf *p)
|
|||
}
|
||||
|
||||
/* Prepare transmit descriptors to give to DMA */
|
||||
HAL_ETH_TransmitFrame(&heth, framelength);
|
||||
HAL_ETH_TransmitFrame(&EthHandle, framelength);
|
||||
|
||||
errval = ERR_OK;
|
||||
|
||||
error:
|
||||
|
||||
/* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */
|
||||
if ((heth.Instance->DMASR & ETH_DMASR_TUS) != (uint32_t)RESET) {
|
||||
if ((EthHandle.Instance->DMASR & ETH_DMASR_TUS) != (uint32_t)RESET) {
|
||||
/* Clear TUS ETHERNET DMA flag */
|
||||
heth.Instance->DMASR = ETH_DMASR_TUS;
|
||||
EthHandle.Instance->DMASR = ETH_DMASR_TUS;
|
||||
|
||||
/* Resume DMA transmission*/
|
||||
heth.Instance->DMATPDR = 0;
|
||||
EthHandle.Instance->DMATPDR = 0;
|
||||
}
|
||||
|
||||
sys_mutex_unlock(&tx_lock_mutex);
|
||||
|
|
@ -352,7 +254,7 @@ error:
|
|||
* @return a pbuf filled with the received packet (including MAC header)
|
||||
* NULL on memory error
|
||||
*/
|
||||
static struct pbuf * stm32f4_low_level_input(struct netif *netif)
|
||||
static struct pbuf * _eth_arch_low_level_input(struct netif *netif)
|
||||
{
|
||||
struct pbuf *p = NULL;
|
||||
struct pbuf *q;
|
||||
|
|
@ -366,12 +268,12 @@ static struct pbuf * stm32f4_low_level_input(struct netif *netif)
|
|||
|
||||
|
||||
/* get received frame */
|
||||
if (HAL_ETH_GetReceivedFrame(&heth) != HAL_OK)
|
||||
if (HAL_ETH_GetReceivedFrame(&EthHandle) != HAL_OK)
|
||||
return NULL;
|
||||
|
||||
/* Obtain the size of the packet and put it into the "len" variable. */
|
||||
len = heth.RxFrameInfos.length;
|
||||
buffer = (uint8_t*)heth.RxFrameInfos.buffer;
|
||||
len = EthHandle.RxFrameInfos.length;
|
||||
buffer = (uint8_t*)EthHandle.RxFrameInfos.buffer;
|
||||
|
||||
if (len > 0) {
|
||||
/* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
|
||||
|
|
@ -379,7 +281,7 @@ static struct pbuf * stm32f4_low_level_input(struct netif *netif)
|
|||
}
|
||||
|
||||
if (p != NULL) {
|
||||
dmarxdesc = heth.RxFrameInfos.FSRxDesc;
|
||||
dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc;
|
||||
bufferoffset = 0;
|
||||
for (q = p; q != NULL; q = q->next) {
|
||||
byteslefttocopy = q->len;
|
||||
|
|
@ -405,23 +307,23 @@ static struct pbuf * stm32f4_low_level_input(struct netif *netif)
|
|||
|
||||
/* Release descriptors to DMA */
|
||||
/* Point to first descriptor */
|
||||
dmarxdesc = heth.RxFrameInfos.FSRxDesc;
|
||||
dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc;
|
||||
/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
|
||||
for (i = 0; i < heth.RxFrameInfos.SegCount; i++) {
|
||||
for (i = 0; i < EthHandle.RxFrameInfos.SegCount; i++) {
|
||||
dmarxdesc->Status |= ETH_DMARXDESC_OWN;
|
||||
dmarxdesc = (ETH_DMADescTypeDef*)(dmarxdesc->Buffer2NextDescAddr);
|
||||
}
|
||||
|
||||
/* Clear Segment_Count */
|
||||
heth.RxFrameInfos.SegCount = 0;
|
||||
EthHandle.RxFrameInfos.SegCount = 0;
|
||||
}
|
||||
|
||||
/* When Rx Buffer unavailable flag is set: clear it and resume reception */
|
||||
if ((heth.Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) {
|
||||
if ((EthHandle.Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) {
|
||||
/* Clear RBUS ETHERNET DMA flag */
|
||||
heth.Instance->DMASR = ETH_DMASR_RBUS;
|
||||
EthHandle.Instance->DMASR = ETH_DMASR_RBUS;
|
||||
/* Resume DMA reception */
|
||||
heth.Instance->DMARPDR = 0;
|
||||
EthHandle.Instance->DMARPDR = 0;
|
||||
}
|
||||
return p;
|
||||
}
|
||||
|
|
@ -431,14 +333,14 @@ static struct pbuf * stm32f4_low_level_input(struct netif *netif)
|
|||
*
|
||||
* \param[in] netif the lwip network interface structure
|
||||
*/
|
||||
static void stm32f4_rx_task(void *arg)
|
||||
static void _eth_arch_rx_task(void *arg)
|
||||
{
|
||||
struct netif *netif = (struct netif*)arg;
|
||||
struct pbuf *p;
|
||||
|
||||
while (1) {
|
||||
sys_arch_sem_wait(&rx_ready_sem, 0);
|
||||
p = stm32f4_low_level_input(netif);
|
||||
p = _eth_arch_low_level_input(netif);
|
||||
if (p != NULL) {
|
||||
if (netif->input(p, netif) != ERR_OK) {
|
||||
pbuf_free(p);
|
||||
|
|
@ -453,23 +355,21 @@ static void stm32f4_rx_task(void *arg)
|
|||
*
|
||||
* \param[in] netif the lwip network interface structure
|
||||
*/
|
||||
static void stm32f4_phy_task(void *arg)
|
||||
static void _eth_arch_phy_task(void *arg)
|
||||
{
|
||||
struct netif *netif = (struct netif*)arg;
|
||||
uint32_t phy_status = 0;
|
||||
|
||||
while (1) {
|
||||
uint32_t status;
|
||||
if (HAL_ETH_ReadPHYRegister(&heth, PHY_SR, &status) == HAL_OK) {
|
||||
if (HAL_ETH_ReadPHYRegister(&EthHandle, PHY_SR, &status) == HAL_OK) {
|
||||
if ((status & PHY_LINK_STATUS) && !(phy_status & PHY_LINK_STATUS)) {
|
||||
tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_up, (void*) netif, 1);
|
||||
} else if (!(status & PHY_LINK_STATUS) && (phy_status & PHY_LINK_STATUS)) {
|
||||
tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_down, (void*) netif, 1);
|
||||
}
|
||||
|
||||
phy_status = status;
|
||||
}
|
||||
|
||||
osDelay(PHY_TASK_WAIT);
|
||||
}
|
||||
}
|
||||
|
|
@ -483,13 +383,12 @@ static void stm32f4_phy_task(void *arg)
|
|||
* \param[in] ipaddr IP address
|
||||
* \return ERR_OK or error code
|
||||
*/
|
||||
static err_t stm32f4_etharp_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr)
|
||||
static err_t _eth_arch_netif_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr)
|
||||
{
|
||||
/* Only send packet is link is up */
|
||||
if (netif->flags & NETIF_FLAG_LINK_UP) {
|
||||
return etharp_output(netif, q, ipaddr);
|
||||
}
|
||||
|
||||
return ERR_CONN;
|
||||
}
|
||||
|
||||
|
|
@ -517,14 +416,14 @@ err_t eth_arch_enetif_init(struct netif *netif)
|
|||
|
||||
#if LWIP_NETIF_HOSTNAME
|
||||
/* Initialize interface hostname */
|
||||
netif->hostname = "lwipstm32f4";
|
||||
netif->hostname = "lwipstm32";
|
||||
#endif /* LWIP_NETIF_HOSTNAME */
|
||||
|
||||
netif->name[0] = 'e';
|
||||
netif->name[1] = 'n';
|
||||
|
||||
netif->output = stm32f4_etharp_output;
|
||||
netif->linkoutput = stm32f4_low_level_output;
|
||||
netif->output = _eth_arch_netif_output;
|
||||
netif->linkoutput = _eth_arch_low_level_output;
|
||||
|
||||
/* semaphore */
|
||||
sys_sem_new(&rx_ready_sem, 0);
|
||||
|
|
@ -532,19 +431,18 @@ err_t eth_arch_enetif_init(struct netif *netif)
|
|||
sys_mutex_new(&tx_lock_mutex);
|
||||
|
||||
/* task */
|
||||
sys_thread_new("stm32f4_recv_task", stm32f4_rx_task, netif, DEFAULT_THREAD_STACKSIZE, RECV_TASK_PRI);
|
||||
sys_thread_new("stm32f4_phy_task", stm32f4_phy_task, netif, DEFAULT_THREAD_STACKSIZE, PHY_TASK_PRI);
|
||||
sys_thread_new("_eth_arch_rx_task", _eth_arch_rx_task, netif, DEFAULT_THREAD_STACKSIZE, RECV_TASK_PRI);
|
||||
sys_thread_new("_eth_arch_phy_task", _eth_arch_phy_task, netif, DEFAULT_THREAD_STACKSIZE, PHY_TASK_PRI);
|
||||
|
||||
/* initialize the hardware */
|
||||
stm32f4_low_level_init(netif);
|
||||
_eth_arch_low_level_init(netif);
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
void eth_arch_enable_interrupts(void)
|
||||
{
|
||||
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
||||
HAL_NVIC_SetPriority(ETH_IRQn, 0, 0);
|
||||
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
|
||||
HAL_NVIC_EnableIRQ(ETH_IRQn);
|
||||
}
|
||||
|
||||
|
|
@ -552,9 +450,3 @@ void eth_arch_disable_interrupts(void)
|
|||
{
|
||||
NVIC_DisableIRQ(ETH_IRQn);
|
||||
}
|
||||
#endif // #if defined(TARGET_STM32F4)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
#include "stm32f7xx_hal.h"
|
||||
|
||||
/**
|
||||
* Override HAL Eth Init function
|
||||
*/
|
||||
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
if (heth->Instance == ETH) {
|
||||
|
||||
/* Enable GPIOs clocks */
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
|
||||
/** ETH GPIO Configuration
|
||||
RMII_REF_CLK ----------------------> PA1
|
||||
RMII_MDIO -------------------------> PA2
|
||||
RMII_MDC --------------------------> PC1
|
||||
RMII_MII_CRS_DV -------------------> PA7
|
||||
RMII_MII_RXD0 ---------------------> PC4
|
||||
RMII_MII_RXD1 ---------------------> PC5
|
||||
RMII_MII_RXER ---------------------> PG2
|
||||
RMII_MII_TX_EN --------------------> PG11
|
||||
RMII_MII_TXD0 ---------------------> PG13
|
||||
RMII_MII_TXD1 ---------------------> PG14
|
||||
*/
|
||||
/* Configure PA1, PA2 and PA7 */
|
||||
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
|
||||
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
/* Configure PC1, PC4 and PC5 */
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
|
||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
|
||||
/* Configure PG2, PG11, PG13 and PG14 */
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;
|
||||
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
|
||||
|
||||
/* Enable the Ethernet global Interrupt */
|
||||
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
|
||||
HAL_NVIC_EnableIRQ(ETH_IRQn);
|
||||
|
||||
/* Enable ETHERNET clock */
|
||||
__HAL_RCC_ETH_CLK_ENABLE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Override HAL Eth DeInit function
|
||||
*/
|
||||
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
|
||||
{
|
||||
if (heth->Instance == ETH) {
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_ETH_CLK_DISABLE();
|
||||
|
||||
/** ETH GPIO Configuration
|
||||
RMII_REF_CLK ----------------------> PA1
|
||||
RMII_MDIO -------------------------> PA2
|
||||
RMII_MDC --------------------------> PC1
|
||||
RMII_MII_CRS_DV -------------------> PA7
|
||||
RMII_MII_RXD0 ---------------------> PC4
|
||||
RMII_MII_RXD1 ---------------------> PC5
|
||||
RMII_MII_RXER ---------------------> PG2
|
||||
RMII_MII_TX_EN --------------------> PG11
|
||||
RMII_MII_TXD0 ---------------------> PG13
|
||||
RMII_MII_TXD1 ---------------------> PG14
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
|
||||
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
|
||||
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14);
|
||||
|
||||
/* Disable the Ethernet global Interrupt */
|
||||
NVIC_DisableIRQ(ETH_IRQn);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
#include "stm32f7xx_hal.h"
|
||||
|
||||
/**
|
||||
* Override HAL Eth Init function
|
||||
*/
|
||||
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
if (heth->Instance == ETH) {
|
||||
|
||||
/* Enable GPIOs clocks */
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
|
||||
/** ETH GPIO Configuration
|
||||
RMII_REF_CLK ----------------------> PA1
|
||||
RMII_MDIO -------------------------> PA2
|
||||
RMII_MDC --------------------------> PC1
|
||||
RMII_MII_CRS_DV -------------------> PA7
|
||||
RMII_MII_RXD0 ---------------------> PC4
|
||||
RMII_MII_RXD1 ---------------------> PC5
|
||||
RMII_MII_RXER ---------------------> PG2
|
||||
RMII_MII_TX_EN --------------------> PG11
|
||||
RMII_MII_TXD0 ---------------------> PG13
|
||||
RMII_MII_TXD1 ---------------------> PB13
|
||||
*/
|
||||
/* Configure PA1, PA2 and PA7 */
|
||||
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
|
||||
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
/* Configure PB13 */
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_13;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
|
||||
/* Configure PC1, PC4 and PC5 */
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
|
||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
|
||||
/* Configure PG2, PG11 and PG13 */
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13;
|
||||
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
|
||||
|
||||
/* Enable the Ethernet global Interrupt */
|
||||
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
|
||||
HAL_NVIC_EnableIRQ(ETH_IRQn);
|
||||
|
||||
/* Enable ETHERNET clock */
|
||||
__HAL_RCC_ETH_CLK_ENABLE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Override HAL Eth DeInit function
|
||||
*/
|
||||
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
|
||||
{
|
||||
if (heth->Instance == ETH) {
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_ETH_CLK_DISABLE();
|
||||
|
||||
/** ETH GPIO Configuration
|
||||
RMII_REF_CLK ----------------------> PA1
|
||||
RMII_MDIO -------------------------> PA2
|
||||
RMII_MDC --------------------------> PC1
|
||||
RMII_MII_CRS_DV -------------------> PA7
|
||||
RMII_MII_RXD0 ---------------------> PC4
|
||||
RMII_MII_RXD1 ---------------------> PC5
|
||||
RMII_MII_RXER ---------------------> PG2
|
||||
RMII_MII_TX_EN --------------------> PG11
|
||||
RMII_MII_TXD0 ---------------------> PG13
|
||||
RMII_MII_TXD1 ---------------------> PB13
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
|
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
|
||||
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
|
||||
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13);
|
||||
|
||||
/* Disable the Ethernet global Interrupt */
|
||||
NVIC_DisableIRQ(ETH_IRQn);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
#include "stm32f7xx_hal.h"
|
||||
|
||||
/**
|
||||
* Override HAL Eth Init function
|
||||
*/
|
||||
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
if (heth->Instance == ETH) {
|
||||
|
||||
/* Enable GPIOs clocks */
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
|
||||
/** ETH GPIO Configuration
|
||||
RMII_REF_CLK ----------------------> PA1
|
||||
RMII_MDIO -------------------------> PA2
|
||||
RMII_MDC --------------------------> PC1
|
||||
RMII_MII_CRS_DV -------------------> PA7
|
||||
RMII_MII_RXD0 ---------------------> PC4
|
||||
RMII_MII_RXD1 ---------------------> PC5
|
||||
RMII_MII_RXER ---------------------> PG2
|
||||
RMII_MII_TX_EN --------------------> PG11
|
||||
RMII_MII_TXD0 ---------------------> PG13
|
||||
RMII_MII_TXD1 ---------------------> PB13
|
||||
*/
|
||||
/* Configure PA1, PA2 and PA7 */
|
||||
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
|
||||
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
/* Configure PB13 */
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_13;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
|
||||
/* Configure PC1, PC4 and PC5 */
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
|
||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
|
||||
/* Configure PG2, PG11 and PG13 */
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13;
|
||||
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
|
||||
|
||||
/* Enable the Ethernet global Interrupt */
|
||||
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
|
||||
HAL_NVIC_EnableIRQ(ETH_IRQn);
|
||||
|
||||
/* Enable ETHERNET clock */
|
||||
__HAL_RCC_ETH_CLK_ENABLE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Override HAL Eth DeInit function
|
||||
*/
|
||||
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
|
||||
{
|
||||
if (heth->Instance == ETH) {
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_ETH_CLK_DISABLE();
|
||||
|
||||
/** ETH GPIO Configuration
|
||||
RMII_REF_CLK ----------------------> PA1
|
||||
RMII_MDIO -------------------------> PA2
|
||||
RMII_MDC --------------------------> PC1
|
||||
RMII_MII_CRS_DV -------------------> PA7
|
||||
RMII_MII_RXD0 ---------------------> PC4
|
||||
RMII_MII_RXD1 ---------------------> PC5
|
||||
RMII_MII_RXER ---------------------> PG2
|
||||
RMII_MII_TX_EN --------------------> PG11
|
||||
RMII_MII_TXD0 ---------------------> PG13
|
||||
RMII_MII_TXD1 ---------------------> PB13
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
|
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
|
||||
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
|
||||
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13);
|
||||
|
||||
/* Disable the Ethernet global Interrupt */
|
||||
NVIC_DisableIRQ(ETH_IRQn);
|
||||
}
|
||||
}
|
||||
|
|
@ -1,4 +1,3 @@
|
|||
#if defined(TARGET_NUCLEO_F746ZG)
|
||||
#include "stm32f7xx_hal.h"
|
||||
#include "lwip/opt.h"
|
||||
|
||||
|
|
@ -9,151 +8,42 @@
|
|||
#include "cmsis_os.h"
|
||||
#include "mbed_interface.h"
|
||||
|
||||
/** @defgroup lwipstm32f7xx_emac_DRIVER stm32f7 EMAC driver for LWIP
|
||||
* @ingroup lwip_emac
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RECV_TASK_PRI (osPriorityHigh)
|
||||
#define PHY_TASK_PRI (osPriorityLow)
|
||||
#define PHY_TASK_WAIT (200)
|
||||
/* LAN8742A PHY Address*/
|
||||
#define LAN8742A_PHY_ADDRESS 0x00
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB] __attribute__((at(0x20002000)));/* Ethernet Rx MA Descriptor */
|
||||
|
||||
ETH_DMADescTypeDef DMATxDscrTab[ETH_TXBUFNB] __attribute__((at(0x200020A0)));/* Ethernet Tx DMA Descriptor */
|
||||
|
||||
uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __attribute__((at(0x20002140))); /* Ethernet Receive Buffer */
|
||||
|
||||
uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __attribute__((at(0x20004480))); /* Ethernet Transmit Buffer */
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
|
||||
#pragma location=0x20002000
|
||||
__no_init ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB];/* Ethernet Rx MA Descriptor */
|
||||
|
||||
#pragma location=0x200020A0
|
||||
__no_init ETH_DMADescTypeDef DMATxDscrTab[ETH_TXBUFNB];/* Ethernet Tx DMA Descriptor */
|
||||
|
||||
#pragma location=0x20002140
|
||||
__no_init uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; /* Ethernet Receive Buffer */
|
||||
|
||||
#pragma location=0x20004480
|
||||
__no_init uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; /* Ethernet Transmit Buffer */
|
||||
|
||||
#elif defined ( __GNUC__ ) /*!< GNU Compiler */
|
||||
|
||||
ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB] __attribute__((section(".RxDecripSection")));/* Ethernet Rx MA Descriptor */
|
||||
|
||||
ETH_DMADescTypeDef DMATxDscrTab[ETH_TXBUFNB] __attribute__((section(".TxDescripSection")));/* Ethernet Tx DMA Descriptor */
|
||||
|
||||
uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __attribute__((section(".RxarraySection"))); /* Ethernet Receive Buffer */
|
||||
|
||||
uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __attribute__((section(".TxarraySection"))); /* Ethernet Transmit Buffer */
|
||||
|
||||
#endif
|
||||
#define ETH_ARCH_PHY_ADDRESS (0x00)
|
||||
|
||||
ETH_HandleTypeDef EthHandle;
|
||||
|
||||
#if defined (__ICCARM__) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
__ALIGN_BEGIN ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB] __ALIGN_END; /* Ethernet Rx DMA Descriptor */
|
||||
|
||||
#if defined (__ICCARM__) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
__ALIGN_BEGIN ETH_DMADescTypeDef DMATxDscrTab[ETH_TXBUFNB] __ALIGN_END; /* Ethernet Tx DMA Descriptor */
|
||||
|
||||
#if defined (__ICCARM__) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
__ALIGN_BEGIN uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __ALIGN_END; /* Ethernet Receive Buffer */
|
||||
|
||||
#if defined (__ICCARM__) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
__ALIGN_BEGIN uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __ALIGN_END; /* Ethernet Transmit Buffer */
|
||||
|
||||
static sys_sem_t rx_ready_sem; /* receive ready semaphore */
|
||||
static sys_mutex_t tx_lock_mutex;
|
||||
|
||||
/* function */
|
||||
static void stm32f7_rx_task(void *arg);
|
||||
static void stm32f7_phy_task(void *arg);
|
||||
static err_t stm32f7_etharp_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr);
|
||||
static err_t stm32f7_low_level_output(struct netif *netif, struct pbuf *p);
|
||||
|
||||
/**
|
||||
* Override HAL Eth Init function
|
||||
*/
|
||||
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
if (heth->Instance == ETH) {
|
||||
|
||||
/* Enable GPIOs clocks */
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
|
||||
/** ETH GPIO Configuration
|
||||
RMII_REF_CLK ----------------------> PA1
|
||||
RMII_MDIO -------------------------> PA2
|
||||
RMII_MDC --------------------------> PC1
|
||||
RMII_MII_CRS_DV -------------------> PA7
|
||||
RMII_MII_RXD0 ---------------------> PC4
|
||||
RMII_MII_RXD1 ---------------------> PC5
|
||||
RMII_MII_RXER ---------------------> PG2
|
||||
RMII_MII_TX_EN --------------------> PG11
|
||||
RMII_MII_TXD0 ---------------------> PG13
|
||||
RMII_MII_TXD1 ---------------------> PB13
|
||||
*/
|
||||
/* Configure PA1, PA2 and PA7 */
|
||||
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
|
||||
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
/* Configure PB13 */
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_13;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
|
||||
/* Configure PC1, PC4 and PC5 */
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
|
||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
|
||||
/* Configure PG2, PG11 and PG13 */
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13;
|
||||
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
|
||||
|
||||
/* Enable the Ethernet global Interrupt */
|
||||
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
|
||||
HAL_NVIC_EnableIRQ(ETH_IRQn);
|
||||
|
||||
/* Enable ETHERNET clock */
|
||||
__HAL_RCC_ETH_CLK_ENABLE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Override HAL Eth DeInit function
|
||||
*/
|
||||
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
|
||||
{
|
||||
if (heth->Instance == ETH) {
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_ETH_CLK_DISABLE();
|
||||
|
||||
/** ETH GPIO Configuration
|
||||
RMII_REF_CLK ----------------------> PA1
|
||||
RMII_MDIO -------------------------> PA2
|
||||
RMII_MDC --------------------------> PC1
|
||||
RMII_MII_CRS_DV -------------------> PA7
|
||||
RMII_MII_RXD0 ---------------------> PC4
|
||||
RMII_MII_RXD1 ---------------------> PC5
|
||||
RMII_MII_RXER ---------------------> PG2
|
||||
RMII_MII_TX_EN --------------------> PG11
|
||||
RMII_MII_TXD0 ---------------------> PG13
|
||||
RMII_MII_TXD1 ---------------------> PB13
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
|
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
|
||||
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
|
||||
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13);
|
||||
|
||||
/* Disable the Ethernet global Interrupt */
|
||||
NVIC_DisableIRQ(ETH_IRQn);
|
||||
}
|
||||
}
|
||||
static void _eth_arch_rx_task(void *arg);
|
||||
static void _eth_arch_phy_task(void *arg);
|
||||
static err_t _eth_arch_netif_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr);
|
||||
static err_t _eth_arch_low_level_output(struct netif *netif, struct pbuf *p);
|
||||
static struct pbuf * _eth_arch_low_level_input(struct netif *netif);
|
||||
|
||||
/**
|
||||
* Ethernet Rx Transfer completed callback
|
||||
|
|
@ -187,7 +77,7 @@ void ETH_IRQHandler(void)
|
|||
* @param netif the already initialized lwip network interface structure
|
||||
* for this ethernetif
|
||||
*/
|
||||
static void stm32f7_low_level_init(struct netif *netif)
|
||||
static void _eth_arch_low_level_init(struct netif *netif)
|
||||
{
|
||||
uint32_t regvalue = 0;
|
||||
HAL_StatusTypeDef hal_eth_init_status;
|
||||
|
|
@ -198,7 +88,7 @@ static void stm32f7_low_level_init(struct netif *netif)
|
|||
EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
|
||||
EthHandle.Init.Speed = ETH_SPEED_100M;
|
||||
EthHandle.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
|
||||
EthHandle.Init.PhyAddress = LAN8742A_PHY_ADDRESS;
|
||||
EthHandle.Init.PhyAddress = ETH_ARCH_PHY_ADDRESS;
|
||||
#if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
|
||||
MACAddr[0] = MBED_MAC_ADDR_0;
|
||||
MACAddr[1] = MBED_MAC_ADDR_1;
|
||||
|
|
@ -207,7 +97,7 @@ static void stm32f7_low_level_init(struct netif *netif)
|
|||
MACAddr[4] = MBED_MAC_ADDR_4;
|
||||
MACAddr[5] = MBED_MAC_ADDR_5;
|
||||
#else
|
||||
mbed_mac_address((char *)MACAddr);
|
||||
mbed_mac_address((char *)MACAddr);
|
||||
#endif
|
||||
EthHandle.Init.MACAddr = &MACAddr[0];
|
||||
EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE;
|
||||
|
|
@ -215,7 +105,6 @@ static void stm32f7_low_level_init(struct netif *netif)
|
|||
EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
|
||||
hal_eth_init_status = HAL_ETH_Init(&EthHandle);
|
||||
|
||||
|
||||
/* Initialize Tx Descriptors list: Chain Mode */
|
||||
HAL_ETH_DMATxDescListInit(&EthHandle, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
|
||||
|
||||
|
|
@ -279,7 +168,7 @@ static void stm32f7_low_level_init(struct netif *netif)
|
|||
* dropped because of memory failure (except for the TCP timers).
|
||||
*/
|
||||
|
||||
static err_t stm32f7_low_level_output(struct netif *netif, struct pbuf *p)
|
||||
static err_t _eth_arch_low_level_output(struct netif *netif, struct pbuf *p)
|
||||
{
|
||||
err_t errval;
|
||||
struct pbuf *q;
|
||||
|
|
@ -365,7 +254,7 @@ error:
|
|||
* @return a pbuf filled with the received packet (including MAC header)
|
||||
* NULL on memory error
|
||||
*/
|
||||
static struct pbuf * stm32f7_low_level_input(struct netif *netif)
|
||||
static struct pbuf * _eth_arch_low_level_input(struct netif *netif)
|
||||
{
|
||||
struct pbuf *p = NULL;
|
||||
struct pbuf *q;
|
||||
|
|
@ -444,14 +333,14 @@ static struct pbuf * stm32f7_low_level_input(struct netif *netif)
|
|||
*
|
||||
* \param[in] netif the lwip network interface structure
|
||||
*/
|
||||
static void stm32f7_rx_task(void *arg)
|
||||
static void _eth_arch_rx_task(void *arg)
|
||||
{
|
||||
struct netif *netif = (struct netif*)arg;
|
||||
struct pbuf *p;
|
||||
|
||||
while (1) {
|
||||
sys_arch_sem_wait(&rx_ready_sem, 0);
|
||||
p = stm32f7_low_level_input(netif);
|
||||
p = _eth_arch_low_level_input(netif);
|
||||
if (p != NULL) {
|
||||
if (netif->input(p, netif) != ERR_OK) {
|
||||
pbuf_free(p);
|
||||
|
|
@ -466,7 +355,7 @@ static void stm32f7_rx_task(void *arg)
|
|||
*
|
||||
* \param[in] netif the lwip network interface structure
|
||||
*/
|
||||
static void stm32f7_phy_task(void *arg)
|
||||
static void _eth_arch_phy_task(void *arg)
|
||||
{
|
||||
struct netif *netif = (struct netif*)arg;
|
||||
uint32_t phy_status = 0;
|
||||
|
|
@ -479,10 +368,8 @@ static void stm32f7_phy_task(void *arg)
|
|||
} else if (!(status & PHY_LINK_STATUS) && (phy_status & PHY_LINK_STATUS)) {
|
||||
tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_down, (void*) netif, 1);
|
||||
}
|
||||
|
||||
phy_status = status;
|
||||
}
|
||||
|
||||
osDelay(PHY_TASK_WAIT);
|
||||
}
|
||||
}
|
||||
|
|
@ -496,13 +383,12 @@ static void stm32f7_phy_task(void *arg)
|
|||
* \param[in] ipaddr IP address
|
||||
* \return ERR_OK or error code
|
||||
*/
|
||||
static err_t stm32f7_etharp_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr)
|
||||
static err_t _eth_arch_netif_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr)
|
||||
{
|
||||
/* Only send packet is link is up */
|
||||
if (netif->flags & NETIF_FLAG_LINK_UP) {
|
||||
return etharp_output(netif, q, ipaddr);
|
||||
}
|
||||
|
||||
return ERR_CONN;
|
||||
}
|
||||
|
||||
|
|
@ -530,14 +416,14 @@ err_t eth_arch_enetif_init(struct netif *netif)
|
|||
|
||||
#if LWIP_NETIF_HOSTNAME
|
||||
/* Initialize interface hostname */
|
||||
netif->hostname = "lwipstm32f7";
|
||||
netif->hostname = "lwipstm32";
|
||||
#endif /* LWIP_NETIF_HOSTNAME */
|
||||
|
||||
netif->name[0] = 'e';
|
||||
netif->name[1] = 'n';
|
||||
|
||||
netif->output = stm32f7_etharp_output;
|
||||
netif->linkoutput = stm32f7_low_level_output;
|
||||
netif->output = _eth_arch_netif_output;
|
||||
netif->linkoutput = _eth_arch_low_level_output;
|
||||
|
||||
/* semaphore */
|
||||
sys_sem_new(&rx_ready_sem, 0);
|
||||
|
|
@ -545,11 +431,11 @@ err_t eth_arch_enetif_init(struct netif *netif)
|
|||
sys_mutex_new(&tx_lock_mutex);
|
||||
|
||||
/* task */
|
||||
sys_thread_new("stm32f7_recv_task", stm32f7_rx_task, netif, DEFAULT_THREAD_STACKSIZE, RECV_TASK_PRI);
|
||||
sys_thread_new("stm32f7_phy_task", stm32f7_phy_task, netif, DEFAULT_THREAD_STACKSIZE, PHY_TASK_PRI);
|
||||
sys_thread_new("_eth_arch_rx_task", _eth_arch_rx_task, netif, DEFAULT_THREAD_STACKSIZE, RECV_TASK_PRI);
|
||||
sys_thread_new("_eth_arch_phy_task", _eth_arch_phy_task, netif, DEFAULT_THREAD_STACKSIZE, PHY_TASK_PRI);
|
||||
|
||||
/* initialize the hardware */
|
||||
stm32f7_low_level_init(netif);
|
||||
_eth_arch_low_level_init(netif);
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
|
@ -564,10 +450,3 @@ void eth_arch_disable_interrupts(void)
|
|||
{
|
||||
NVIC_DisableIRQ(ETH_IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif //defined (TARGET_NUCLEO_F746ZG)
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
|
|
@ -702,6 +702,7 @@
|
|||
"progen": {"target": "nucleo-f207zg"},
|
||||
"detect_code": ["0835"],
|
||||
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
|
||||
"features": ["IPV4"],
|
||||
"release_versions": ["2"]
|
||||
},
|
||||
"NUCLEO_F302R8": {
|
||||
|
|
@ -810,6 +811,7 @@
|
|||
"progen": {"target": "nucleo-f429zi"},
|
||||
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "RTC_LSI", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
|
||||
"detect_code": ["0796"],
|
||||
"features": ["IPV4"],
|
||||
"release_versions": ["2", "5"]
|
||||
},
|
||||
"NUCLEO_F446RE": {
|
||||
|
|
@ -875,6 +877,7 @@
|
|||
"progen": {"target": "nucleo-f767zi"},
|
||||
"detect_code": ["0818"],
|
||||
"device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
|
||||
"features": ["IPV4"],
|
||||
"release_versions": ["2", "5"]
|
||||
},
|
||||
"NUCLEO_L011K4": {
|
||||
|
|
@ -1073,6 +1076,7 @@
|
|||
"progen": {"target": "disco-f746ng"},
|
||||
"detect_code": ["0815"],
|
||||
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
|
||||
"features": ["IPV4"],
|
||||
"release_versions": ["2", "5"]
|
||||
},
|
||||
"DISCO_L476VG": {
|
||||
|
|
|
|||
Loading…
Reference in New Issue