From 1321dc8e716af22e4f42b6d2c8f264b3f5aa7f3a Mon Sep 17 00:00:00 2001 From: bcostm Date: Fri, 24 Mar 2017 11:07:24 +0100 Subject: [PATCH] DISCO_L053C8: enable HSI48 clock for USB --- .../TARGET_DISCO_L053C8/device/system_stm32l0xx.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_stm32l0xx.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_stm32l0xx.c index 19e2826025..a8e6abd122 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_stm32l0xx.c +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_stm32l0xx.c @@ -377,10 +377,8 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ } RCC_OscInitStruct.HSIState = RCC_HSI_OFF; -#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \ - !defined (STM32L011xx) && !defined (STM32L021xx) RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */ -#endif + // PLLCLK = (8 MHz * 8)/2 = 32 MHz RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; @@ -391,6 +389,12 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } + /* Select HSI48 as USB clock source */ + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz