ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #4414 from tkaman/master 

Enable CM3DS_MPS2 target
pull/4571/head
Sam Grove 2017-06-15 11:20:09 -05:00 committed by GitHub
parent 74b6e8cc4c 9bf298ecc8
commit 109269da9c
41 changed files with 7519 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_CM3DS_MPS2/lwipopts_conf.h Normal file
View File

@ -0,0 +1,33 @@
/* Copyright (c) 2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef LWIPOPTS_CONF_H
#define LWIPOPTS_CONF_H
#define LWIP_TRANSPORT_ETHERNET 1
/* The IEEE 802.3ac standard says the maximum Ethernet frame */
/* size is 1522 bytes to accommodate the four-byte VLAN tag. */
#define ETH_MAX_FLEN 1522u /* recommended size for a VLAN frame */
/* Maximum Transfer Unit
* The IEEE 802.3 specification limits the data portion of the 802.3 frame
* to a minimum of 46 and a maximum of 1500 bytes, this is on L3 level.
*/
#define ETH_L2_HEADER_LEN 22u
#define ETH_MAX_PAYLOAD_LEN (ETH_MAX_FLEN - ETH_L2_HEADER_LEN)
#endif /* LWIPOPTS_CONF_H */

397
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_CM3DS_MPS2/mps2_emac.c Normal file
View File

@ -0,0 +1,397 @@
/* mbed Microcontroller Library
* Copyright (c) 2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <ctype.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "ethernet_api.h"
#include "eth_arch.h"
#include "lwip/def.h"
#include "lwip/ethip6.h"
#include "lwip/igmp.h"
#include "lwip/mem.h"
#include "lwip/mld6.h"
#include "lwip/opt.h"
#include "lwip/pbuf.h"
#include "lwip/snmp.h"
#include "lwip/stats.h"
#include "lwip/sys.h"
#include "lwip/tcpip.h"
#include "mbed_interface.h"
#include "mbed_wait_api.h"
#include "netif/etharp.h"
#include "netif/ppp/pppoe.h"
#include "smsc9220_eth.h"
#include "sys_arch.h"
/**
* @file mps2_emac.c
*
* @brief Connects the lwIP stack to the SMSC9220 Ethernet controller driver,
* by implementing the low-level Ethernet interface layer of lwIP,
* according to the skeleton file:
* \mbed-os\features\FEATURE_LWIP\lwip-interface\lwip\src\netif\lwip_ethernetif.c
*
*/
#define HOSTNAME_STRING "lwip_mps2"
static sys_sem_t rx_ready_sem;
struct ethernetif {
const struct eth_addr *ethaddr;
int is_enabled;
sys_mutex_t tx_mutex;
};
/**
* Should allocate a pbuf and transfer the bytes of the incoming
* packet from the interface into the pbuf.
*
* @param netif the lwip network interface structure for this ethernetif
* @return a pbuf filled with the received packet (including MAC header)
* NULL on memory error
*/
static struct pbuf *low_level_input(struct netif *netif)
{
struct pbuf *p, *q;
uint16_t len;
int unread_bytes = 0;
len = ETH_MAX_FLEN;
#if ETH_PAD_SIZE
len += ETH_PAD_SIZE; /* allow room for Ethernet padding */
#endif
/* We allocate a pbuf chain of pbufs from the pool. */
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
if (p != NULL) {
#if ETH_PAD_SIZE
pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
#endif
/* It iterates over the pbuf chain until it has read the entire
* packet into the pbuf. */
for (q = p; q != NULL; q = q->next) {
/* Read enough bytes to fill this pbuf in the chain. The
* available data in the pbuf is given by the q->len
* variable.
* This does not necessarily have to be a memcpy, you can also preallocate
* pbufs for a DMA-enabled MAC and after receiving truncate it to the
* actually received size. In this case, ensure the tot_len member of the
* pbuf is the sum of the chained pbuf len members.
*/
unread_bytes = ethernet_read(q->payload, q->len);
if (unread_bytes == 0) {
break;
}
}
/* package has been read */
MIB2_STATS_NETIF_ADD(netif, ifinoctets, p->tot_len);
if (((u8_t*)p->payload)[0] & 1) {
/* broadcast or multicast packet */
MIB2_STATS_NETIF_INC(netif, ifinnucastpkts);
} else {
/* unicast packet */
MIB2_STATS_NETIF_INC(netif, ifinucastpkts);
}
#if ETH_PAD_SIZE
pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
#endif
LINK_STATS_INC(link.recv);
} else {
/* drop packet */
LINK_STATS_INC(link.memerr);
LINK_STATS_INC(link.drop);
MIB2_STATS_NETIF_INC(netif, ifindiscards);
}
return p;
}
/**
* This function should be called when a packet is ready to be read
* from the interface. It uses the function low_level_input() that
* should handle the actual reception of bytes from the network
* interface. Then the type of the received packet is determined and
* the appropriate input function is called.
*
* @param netif the lwip network interface structure for this ethernetif
*/
static void ethernetif_input(struct netif *netif)
{
struct pbuf *p;
/* move received packet into a new pbuf */
p = low_level_input(netif);
/* if no packet could be read, silently ignore this */
if (p != NULL) {
/* pass all packets to ethernet_input, which decides what packets it supports */
if (netif->input(p, netif) != ERR_OK) {
LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n"));
pbuf_free(p);
}
} else {
LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: buffer null pointer error\n"));
}
}
/**
* This task is called when a packet is received. It will
* pass the packet to the LWIP core.
*
* @param pvParameters pointer to the interface data
*/
static void packet_rx(void* pvParameters)
{
struct netif *netif = pvParameters;
while (1) {
sys_arch_sem_wait(&rx_ready_sem, 0);
ethernetif_input(netif);
smsc9220_enable_interrupt(enum_smsc9220_interrupt_rxstatus_fifo_level);
}
}
/**
* This function should do the actual transmission of the packet. The packet is
* contained in the pbuf that is passed to the function. This pbuf
* might be chained.
*
* @param netif the lwip network interface structure for this ethernetif
* @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
* @return ERR_OK if the packet could be sent
* an err_t value if the packet couldn't be sent
*
* @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
* strange results. You might consider waiting for space in the DMA queue
* to become available since the stack doesn't retry to send a packet
* dropped because of memory failure (except for the TCP timers).
*/
static err_t low_level_output(struct netif *netif, struct pbuf *p)
{
struct pbuf *q;
err_t error = ERR_OK;
unsigned int is_new_packet = 1;
const unsigned int packet_length = p->tot_len;
#if ETH_PAD_SIZE
pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
#endif
/* fragmented packet sending should not be used concurrently */
sys_mutex_lock(&(((struct ethernetif*)(netif->state))->tx_mutex));
for (q = p; (q != NULL) && (error == ERR_OK); q = q->next) {
/* Send the data from the pbuf to the interface, one pbuf at a
* time.
* The SMSC9220 driver should be used directly for sending by
* buffer chain, because the SMSC9220 Ethernet API cannot support
* ethernet_send and ethernet_write functions without additional
* SW FIFO, what would increase the memory footprint.
*/
error = smsc9220_send_by_chunks(packet_length, is_new_packet,
q->payload, q->len);
if (error != ERR_OK) {
LWIP_ASSERT("smsc9220_send_by_chunks error", 0);
return error;
}
is_new_packet = 0;
}
sys_mutex_unlock(&(((struct ethernetif*)(netif->state))->tx_mutex));
/* packet should be sent now */
MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p->tot_len);
if (((u8_t*)p->payload)[0] & 1) {
/* broadcast or multicast packet */
MIB2_STATS_NETIF_INC(netif, ifoutnucastpkts);
} else {
/* unicast packet */
MIB2_STATS_NETIF_INC(netif, ifoutucastpkts);
}
/* increase ifoutdiscards or ifouterrors on error */
#if ETH_PAD_SIZE
pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
#endif
LINK_STATS_INC(link.xmit);
return error;
}
/**
* In this function, the hardware should be initialized.
* Called from ethernetif_init().
*
* @param netif the already initialized lwip network interface structure
* for this ethernetif
*/
static err_t low_level_init(struct netif *netif)
{
err_t error = ERR_OK;
int low_level_error = 0;
/* set MAC hardware address length */
netif->hwaddr_len = ETHARP_HWADDR_LEN;
/* set MAC hardware address */
#if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
netif->hwaddr[0] = MBED_MAC_ADDR_0;
netif->hwaddr[1] = MBED_MAC_ADDR_1;
netif->hwaddr[2] = MBED_MAC_ADDR_2;
netif->hwaddr[3] = MBED_MAC_ADDR_3;
netif->hwaddr[4] = MBED_MAC_ADDR_4;
netif->hwaddr[5] = MBED_MAC_ADDR_5;
#else
ethernet_address((char *)netif->hwaddr);
#endif
/* device capabilities */
/* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
#if LWIP_IPV6 && LWIP_IPV6_MLD
/*
* For hardware/netifs that implement MAC filtering.
* All-nodes link-local is handled by default, so it must let the hardware know
* to allow multicast packets in.
* Should set mld_mac_filter previously. */
if (netif->mld_mac_filter != NULL) {
ip6_addr_t ip6_allnodes_ll;
ip6_addr_set_allnodes_linklocal(&ip6_allnodes_ll);
netif->mld_mac_filter(netif, &ip6_allnodes_ll, MLD6_ADD_MAC_FILTER);
}
#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
low_level_error = ethernet_init();
if (low_level_error != 0) {
return ERR_IF;
}
error = sys_mutex_new(&(((struct ethernetif*)(netif->state))->tx_mutex));
/* Maximum Transfer Unit */
netif->mtu = ETH_MAX_PAYLOAD_LEN;
return error;
}
/**
* Should be called at the beginning of the program to set up the
* network interface. It calls the function low_level_init() to do the
* actual setup of the hardware.
*
* This function should be passed as a parameter to netif_add().
*
* @param netif the lwip network interface structure for this ethernetif
* @return ERR_OK if the loopif is initialized
* ERR_MEM if private data couldn't be allocated
* any other err_t on error
*/
err_t eth_arch_enetif_init(struct netif *netif)
{
err_t error = ERR_OK;
struct ethernetif *ethernetif;
ethernetif->is_enabled = 0;
LWIP_ASSERT("netif != NULL", (netif != NULL));
ethernetif = mem_malloc(sizeof(struct ethernetif));
if (ethernetif == NULL) {
LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n"));
return ERR_MEM;
}
#if LWIP_NETIF_HOSTNAME
/* Initialize interface hostname */
netif->hostname = HOSTNAME_STRING;
#endif /* LWIP_NETIF_HOSTNAME */
/*
* Initialize the snmp variables and counters inside the struct netif.
* The last argument should be replaced with your link speed, in units
* of bits per second.
*/
MIB2_INIT_NETIF(netif, snmp_ifType_ethernet_csmacd,
LINK_SPEED_OF_YOUR_NETIF_IN_BPS);
netif->state = ethernetif;
/* Two-character name, "en" for Ethernet.
* This can be used to get a netif by name, via netif_find */
netif->name[0] = 'e';
netif->name[1] = 'n';
/* We directly use etharp_output() here to save a function call.
* You can instead declare your own function an call etharp_output()
* from it if you have to do some checks before sending (e.g. if link
* is available...) */
netif->output = etharp_output;
#if LWIP_IPV6
netif->output_ip6 = ethip6_output;
#endif /* LWIP_IPV6 */
netif->linkoutput = low_level_output;
ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]);
/* initialize the hardware */
error = low_level_init(netif);
if (error == ERR_OK) {
sys_thread_new("receive_thread", packet_rx, netif,
DEFAULT_THREAD_STACKSIZE, osPriorityNormal);
sys_sem_new(&rx_ready_sem, 0);
ethernetif->is_enabled = 1;
}
return error;
}
void eth_arch_enable_interrupts(void)
{
smsc9220_enable_interrupt(enum_smsc9220_interrupt_rxstatus_fifo_level);
NVIC_EnableIRQ(ETHERNET_IRQn);
}
void eth_arch_disable_interrupts(void)
{
NVIC_DisableIRQ(ETHERNET_IRQn);
}
void ETHERNET_IRQHandler(void)
{
if (smsc9220_get_interrupt(enum_smsc9220_interrupt_rxstatus_fifo_level)) {
sys_sem_signal(&rx_ready_sem);
smsc9220_clear_interrupt(enum_smsc9220_interrupt_rxstatus_fifo_level);
smsc9220_disable_interrupt(enum_smsc9220_interrupt_rxstatus_fifo_level);
}
}
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

92
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/PeripheralNames.h Normal file
View File

@ -0,0 +1,92 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)CMSDK_UART0_BASE, /* MCC UART */
UART_1 = (int)CMSDK_UART1_BASE, /* MPS2+ UART */
UART_2 = (int)CMSDK_UART2_BASE, /* Shield 0 UART */
UART_3 = (int)CMSDK_UART3_BASE, /* Shield 1 UART */
UART_4 = (int)CMSDK_UART4_BASE /* Shield BT UART */
} UARTName;
typedef enum {
I2C_0 = (int)MPS2_TSC_I2C_BASE,
I2C_1 = (int)MPS2_AAIC_I2C_BASE,
I2C_2 = (int)MPS2_SHIELD0_I2C_BASE,
I2C_3 = (int)MPS2_SHIELD1_I2C_BASE
} I2CName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3,
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7,
ADC0_8,
ADC0_9,
ADC0_10,
ADC0_11
} ADCName;
typedef enum {
SPI_0 = (int)MPS2_SSP0_BASE,
SPI_1 = (int)MPS2_SSP1_BASE,
SPI_2 = (int)MPS2_SSP2_BASE,
SPI_3 = (int)MPS2_SSP3_BASE,
SPI_4 = (int)MPS2_SSP4_BASE
} SPIName;
typedef enum {
PWM_1 = 0,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
PWM_8,
PWM_9,
PWM_10,
PWM_11
} PWMName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_1
#define MBED_UART0 MCC_TX, MCC_RX
#define MBED_UART1 USBTX, USBRX
#define MBED_UART2 XB_TX, XB_RX
#define MBED_UART3 SH0_TX, SH0_RX
#define MBED_UART4 SH1_TX, SH1_RX
#define MBED_UARTUSB USBTX, USBRX
#ifdef __cplusplus
}
#endif
#endif

242
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/PinNames.h Normal file
View File

@ -0,0 +1,242 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// MPS2 EXP Pin Names
EXP0 = 0 ,
EXP1 = 4 ,
EXP2 = 2 ,
EXP3 = 3 ,
EXP4 = 1 ,
EXP5 = 15,
EXP6 = 5 ,
EXP7 = 6 ,
EXP8 = 7 ,
EXP9 = 8 ,
EXP10 =9 ,
EXP11 =13,
EXP12 =10,
EXP13 =11,
EXP14 =12,
EXP15 =14,
EXP16 =18,
EXP17 =19,
EXP18 =20,
EXP19 =21,
EXP20 =52,
EXP21 =53,
EXP22 =54,
EXP23 =55,
EXP24 =56,
EXP25 =57,
EXP26 =16,
EXP27 =25,
EXP28 =24,
EXP29 =31,
EXP30 =17,
EXP31 =23,
EXP32 =27,
EXP33 =30,
EXP34 =26,
EXP35 =28,
EXP36 =29,
EXP37 =58,
EXP38 =48,
EXP39 =49,
EXP40 =50,
EXP41 =22,
EXP42 =59,
EXP43 =60,
EXP44 =51,
EXP45 =61,
EXP46 =62,
EXP47 =63,
EXP48 =64,
EXP49 =65,
EXP50 =66,
EXP51 =67,
// Other mbed Pin Names
//LEDs on mps2
//user leds
USERLED1 = 100,
USERLED2 = 101,
//user switches
USERSW1 = 110,
USERSW2 = 111,
//mcc leds
LED1 = 200,
LED2 = 201,
LED3 = 202,
LED4 = 203,
LED5 = 204,
LED6 = 205,
LED7 = 206,
LED8 = 207,
//MCC Switches
SW1 = 210,
SW2 = 211,
SW3 = 212,
SW4 = 213,
SW5 = 214,
SW6 = 215,
SW7 = 216,
SW8 = 217,
//MPS2 SPI header pins j21
SPI_MOSI = 300,
SPI_MISO = 301,
SPI_SCLK = 302,
SPI_SSEL = 303,
//MPS2 CLCD SPI
CLCD_MOSI = 304,
CLCD_MISO = 305,
CLCD_SCLK = 306,
CLCD_SSEL = 307,
CLCD_RESET = 308,
CLCD_RS = 309,
CLCD_RD = 310,
CLCD_BL_CTRL = 311,
//MPS2 shield 0 SPI
SHIELD_0_SPI_SCK = 320,
SHIELD_0_SPI_MOSI = 321,
SHIELD_0_SPI_MISO = 322,
SHIELD_0_SPI_nCS = 323,
//MPS2 shield 1 SPI
SHIELD_1_SPI_SCK = 331,
SHIELD_1_SPI_MOSI = 332,
SHIELD_1_SPI_MISO = 333,
SHIELD_1_SPI_nCS = 334,
//MPS2 shield ADC SPI
ADC_MOSI = 650,
ADC_MISO = 651,
ADC_SCLK = 652,
ADC_SSEL = 653,
//MPS2 Uart
USBTX = 400,
USBRX = 401,
XB_TX = 402,
XB_RX = 403,
SH0_TX = 404,
SH0_RX = 405,
SH1_TX = 406,
SH1_RX = 407,
MCC_TX = 408,
MCC_RX = 409,
//MPS2 I2C touchscreen and audio
TSC_SDA = 500,
TSC_SCL = 501,
AUD_SDA = 502,
AUD_SCL = 503,
//MPS2 I2C for shield
SHIELD_0_SDA = 504,
SHIELD_0_SCL = 505,
SHIELD_1_SDA = 506,
SHIELD_1_SCL = 507,
//MPS2 shield Analog pins
A0_0 = 600,
A0_1 = 601,
A0_2 = 602,
A0_3 = 603,
A0_4 = 604,
A0_5 = 605,
A1_0 = 606,
A1_1 = 607,
A1_2 = 608,
A1_3 = 609,
A1_4 = 610,
A1_5 = 611,
//MPS2 Shield Digital pins
D0_0 = EXP0,
D0_1 = EXP4,
D0_2 = EXP2,
D0_3 = EXP3,
D0_4 = EXP1,
D0_5 = EXP6,
D0_6 = EXP7,
D0_7 = EXP8,
D0_8 = EXP9,
D0_9 = EXP10,
D0_10 = EXP12,
D0_11 = EXP13,
D0_12 = EXP14,
D0_13 = EXP11,
D0_14 = EXP15,
D0_15 = EXP5,
D1_0 = EXP26,
D1_1 = EXP30,
D1_2 = EXP28,
D1_3 = EXP29,
D1_4 = EXP27,
D1_5 = EXP32,
D1_6 = EXP33,
D1_7 = EXP34,
D1_8 = EXP35,
D1_9 = EXP36,
D1_10 = EXP38,
D1_11 = EXP39,
D1_12 = EXP40,
D1_13 = EXP44,
D1_14 = EXP41,
D1_15 = EXP31,
// Not connected
NC = (int)0xFFFFFFFF,
} PinName;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

31
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/PortNames.h Normal file
View File

@ -0,0 +1,31 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
Port0 = 0,
Port1 = 1
} PortName;
#ifdef __cplusplus
}
#endif
#endif

90
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/fpga.c Normal file
View File

@ -0,0 +1,90 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* ----------------------------------------------------------------
* File: fpga.c
* Release: Version 1.0
* ----------------------------------------------------------------
*/
/*
* Code implementation file for the fpga functions.
*/
#include "SMM_MPS2.h" // MPS2 common header
// Function to delay n*ticks (25MHz = 40nS per tick)
// Used for I2C drivers
void i2c_delay(unsigned int tick)
{
unsigned int end;
unsigned int start;
start = MPS2_FPGAIO->COUNTER;
end = start + (tick);
if(end >= start)
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
}
else
{
while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end);
}
}
/* Sleep function to delay n*mS
* Uses FPGA counter.
*/
void Sleepms(unsigned int msec)
{
unsigned int end;
unsigned int start;
start = MPS2_FPGAIO->COUNTER;
end = start + (25 * msec * 1000);
if(end >= start)
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
}
else
{
while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end);
}
}
/* Sleep function to delay n*uS
*/
void Sleepus(unsigned int usec)
{
unsigned int end;
unsigned int start;
start = MPS2_FPGAIO->COUNTER;
end = start + (25 * usec);
if(end >= start)
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
}
else
{
while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end);
}
}

34
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/fpga.h Normal file
View File

@ -0,0 +1,34 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Code implementation file for the fpga functions.
*/
#include "SMM_MPS2.h" // MPS2 common header
// Function to delay n*ticks (25MHz = 40nS per tick)
// Used for I2C drivers
void i2c_delay(unsigned int tick);
/* Sleep function to delay n*mS
* Uses FPGA counter.
*/
void Sleepms(unsigned int msec);
/* Sleep function to delay n*uS
*/
void Sleepus(unsigned int usec);

694
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/smsc9220_eth.c Normal file
View File

@ -0,0 +1,694 @@
/* mbed Microcontroller Library
* Copyright (c) 2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Code implementation file for the LAN Ethernet interface.
*
* This file is the based on mps2_ethernet_api and Selftest's ETH_MPS2.
* MPS2 Selftest:https://silver.arm.com/browse/VEI10 ->
* \ISCM-1-0\AN491\software\Selftest\v2m_mps2\
*/
#include <stdio.h>
#include "mbed_retarget.h"
#include "mbed_wait_api.h"
#include "SMM_MPS2.h"
#include "smsc9220_eth.h"
#define REG_WRITE_TIME_OUT 50
#define RESET_TIME_OUT 10
#define PHY_RESET_TIME_OUT_MS 100
/* Forward declarations */
static unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data);
static unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data);
static unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned int *data);
static unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned int data);
static unsigned int smsc9220_read_id(void);
static unsigned int smsc9220_soft_reset(void);
static void smsc9220_set_txfifo(unsigned int val);
static unsigned int smsc9220_wait_eeprom(void);
static void smsc9220_init_irqs(void);
static unsigned int smsc9220_check_phy(void);
static unsigned int smsc9220_reset_phy(void);
static void smsc9220_advertise_cap(void);
static void smsc9220_enable_xmit(void);
static void smsc9220_enable_mac_xmit(void);
static void smsc9220_enable_mac_recv(void);
/* SMSC9220 low-level operations */
/**
* \brief Read MAC register.
*
* \param[in] regoffset Register offset
* \param[out] data Register value is read
*
* \return 0 in case of success, 1 otherwise
*/
static unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data)
{
unsigned int val = 0;
unsigned int maccmd = 0;
int time_out = REG_WRITE_TIME_OUT;
val = SMSC9220->MAC_CSR_CMD;
if(!(val & ((unsigned int)1 << 31))) { /* Make sure there's no pending operation */
maccmd |= regoffset;
maccmd |= ((unsigned int)1 << 30); /* Indicates read */
maccmd |= ((unsigned int)1 << 31); /* Start bit */
SMSC9220->MAC_CSR_CMD = maccmd; /* Start operation */
do {
val = SMSC9220->BYTE_TEST; /* A no-op read. */
wait_ms(1);
time_out--;
} while(time_out && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
if(!time_out) {
return 1;
}
else {
*data = SMSC9220->MAC_CSR_DATA;
}
} else {
*data = 0;
}
return 0;
}
/**
* \brief Write MAC register.
*
* \param[in] regoffset Register offset
* \param[in] data Register value to write
*
* \return 0 in case of success, 1 otherwise
*/
static unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data)
{
unsigned int read = 0;
unsigned int maccmd = 0;
int time_out = REG_WRITE_TIME_OUT;
read = SMSC9220->MAC_CSR_CMD;
if(!(read & ((unsigned int)1 << 31))) { /* Make sure there's no pending operation */
SMSC9220->MAC_CSR_DATA = data; /* Store data. */
maccmd |= regoffset;
maccmd &= ~((unsigned int)1 << 30); /* Clear indicates write */
maccmd |= ((unsigned int)1 << 31); /* Indicate start of operation */
SMSC9220->MAC_CSR_CMD = maccmd;
do {
read = SMSC9220->BYTE_TEST; /* A no-op read. */
wait_ms(1);
time_out--;
} while(time_out && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
if(!time_out) {
return 1;
}
} else {
printf("Error: SMSC9220 MAC CSR is busy. No data written.\n");
}
return 0;
}
/**
* \brief Read PHY register.
*
* \param[in] regoffset Register offset
* \param[out] data Register value is read
*
* \return 0 in case of success, 1 otherwise
*/
static unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned int *data)
{
unsigned int val = 0;
unsigned int phycmd = 0;
int time_out = REG_WRITE_TIME_OUT;
if (smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val)) {
return 1;
}
if(!(val & 1)) { /* Not busy */
phycmd = 0;
phycmd |= (1 << 11); /* 1 to [15:11] */
phycmd |= ((regoffset & 0x1F) << 6); /* Put regoffset to [10:6] */
phycmd &= ~(1 << 1); /* Clear [1] indicates read. */
phycmd |= (1 << 0); /* Set [0] indicates operation start */
if (smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd)) {
return 1;
}
val = 0;
do {
wait_ms(1);
time_out--;
if (smsc9220_mac_regread(SMSC9220_MAC_MII_ACC,&val)) {
return 1;
}
} while(time_out && (val & ((unsigned int)1 << 0)));
if (!time_out) {
return 1;
} else if (smsc9220_mac_regread(SMSC9220_MAC_MII_DATA, data)) {
return 1;
}
} else {
*data = 0;
return 1;
}
return 0;
}
/**
* \brief Write PHY register.
*
* \param[in] regoffset Register offset
* \param[in] data Register value to write
*
* \return 0 in case of success, 1 otherwise
*/
static unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned int data)
{
unsigned int val = 0;
unsigned int phycmd = 0;
int time_out = REG_WRITE_TIME_OUT;
if (smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val)) {
return 1;
}
if(!(val & 1)) { /* Not busy */
/* Load the data */
if (smsc9220_mac_regwrite(SMSC9220_MAC_MII_DATA, (data & 0xFFFF))) {
return 1;
}
phycmd = 0;
phycmd |= (1 << 11); /* 1 to [15:11] */
phycmd |= ((regoffset & 0x1F) << 6); /* Put regoffset to [10:6] */
phycmd |= (1 << 1); /* Set [1] indicates write. */
phycmd |= (1 << 0); /* Set [0] indicates operation start */
/* Start operation */
if (smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd)) {
return 1;
}
phycmd = 0;
do {
wait_ms(1);
time_out--;
if (smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd)){
return 1;
}
} while(time_out && (phycmd & (1 << 0)));
if (!time_out) {
return 1;
}
} else {
printf("Error: SMSC9220 MAC MII is busy. No data written.\n");
}
return 0;
}
/**
* \brief Read SMSC9220 ID.
*
* \return ID number
*/
inline static unsigned int smsc9220_read_id(void)
{
return SMSC9220->ID_REV;
}
/**
* \brief Initiates a soft reset, returns failure or success.
*
* \return 0 in case of success, 1 otherwise
*/
static unsigned int smsc9220_soft_reset(void)
{
int time_out = RESET_TIME_OUT;
/* Soft reset */
SMSC9220->HW_CFG |= 1;
do {
wait_ms(1);
time_out--;
} while(time_out && (SMSC9220->HW_CFG & 1));
if (!time_out) {
return 1;
}
return 0;
}
/**
* \brief Set maximum transition unit by Tx fifo size.
* Note: The MTU will be smaller by 512 bytes,
* because the status uses this fixed space.
*
* \param[in] val Size of the fifo in kbytes, 2-14
*/
static void smsc9220_set_txfifo(unsigned int val)
{
/* 2kb minimum, 14kb maximum */
if(val >= 2 && val <= 14) {
SMSC9220->HW_CFG = val << 16;
}
}
/**
* \brief Wait for EEPROM to be ready to use.
*
* \return 0 if ready, 1 in case of timeout
*/
static unsigned int smsc9220_wait_eeprom(void)
{
int time_out = REG_WRITE_TIME_OUT;
do {
wait_ms(1);
time_out--;
} while(time_out && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31)));
if (!time_out) {
return 1;
}
return 0;
}
/**
* \brief Initialise irqs
*/
static void smsc9220_init_irqs(void)
{
SMSC9220->INT_EN = 0x0;
SMSC9220->INT_STS = 0xFFFFFFFF; /* clear all interrupts */
SMSC9220->IRQ_CFG = 0x22000100; /* irq deassertion at 220 usecs and master IRQ enable. */
}
/**
* \brief Check PHY ID registers.
*
* \return 0 in case of success, 1 otherwise
*/
static unsigned int smsc9220_check_phy(void)
{
unsigned int phyid1, phyid2;
if (smsc9220_phy_regread(SMSC9220_PHY_ID1,&phyid1)) {
return 1;
}
if (smsc9220_phy_regread(SMSC9220_PHY_ID2,&phyid2)) {
return 1;
}
return ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) ||
(phyid1 == 0x0 && phyid2 == 0x0));
}
/**
* \brief Reset PHY
*
* \return 0 in case of success, 1 otherwise
*/
static unsigned int smsc9220_reset_phy(void)
{
unsigned int read;
if(smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) {
return 1;
}
read |= (1 << 15);
if(smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) {
return 1;
}
return 0;
}
/**
* \brief Advertise all speeds and pause capabilities
*
* \return 0 in case of success, 1 otherwise
*/
static void smsc9220_advertise_cap(void)
{
unsigned int aneg_adv = 0;
smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv);
aneg_adv |= 0xDE0;
smsc9220_phy_regwrite(SMSC9220_PHY_ANEG_ADV, aneg_adv);
smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv);
}
/**
* \brief Enable trasmission
*/
inline static void smsc9220_enable_xmit(void)
{
SMSC9220->TX_CFG = 0x2;
}
static void smsc9220_enable_mac_xmit(void)
{
unsigned int mac_cr = 0;
smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr);
mac_cr |= (1 << 3); /* xmit enable */
mac_cr |= (1 << 28); /* Heartbeat disable */
smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr);
}
/**
* \brief Enable receive
*/
static void smsc9220_enable_mac_recv(void)
{
unsigned int mac_cr = 0;
smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr);
mac_cr |= (1 << 2); /* Recv enable */
smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr);
}
/**
* \brief Check device ID.
*
* \return 0 in case of success, 1 otherwise
*/
static int smsc9220_check_id(void)
{
unsigned int id = smsc9220_read_id();
/* If bottom and top halves of the word are the same */
if(((id >> 16) & 0xFFFF) == (id & 0xFFFF)) {
return 1;
}
switch(((id >> 16) & 0xFFFF)) {
case 0x9220:
break;
default:
return 1;
}
return 0;
}
/*----------------------------------------------------------------------------
Public API
*----------------------------------------------------------------------------*/
int smsc9220_init(void)
{
unsigned int phyreset = 0;
if(smsc9220_check_id()) {
return 1;
}
if(smsc9220_soft_reset()) {
return 1;
}
smsc9220_set_txfifo(5);
/* Sets automatic flow control thresholds, and backpressure */
/* threshold to defaults specified. */
SMSC9220->AFC_CFG = 0x006E3740;
if(smsc9220_wait_eeprom()) {
return 1;
}
/* Configure GPIOs as LED outputs. */
SMSC9220->GPIO_CFG = 0x70070000;
smsc9220_init_irqs();
/* Configure MAC addresses here if needed. */
if(smsc9220_check_phy()) {
return 1;
}
if(smsc9220_reset_phy()) {
return 1;
}
wait_ms(PHY_RESET_TIME_OUT_MS);
/* Checking whether phy reset completed successfully.*/
if (smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &phyreset)) {
return 1;
}
if(phyreset & (1 << 15)) {
return 1;
}
smsc9220_advertise_cap();
smsc9220_establish_link(); /* bit [12] of BCONTROL seems self-clearing. */
/* Although it's not so in the manual. */
/* Interrupt threshold */
SMSC9220->FIFO_INT = 0xFF000000;
smsc9220_enable_mac_xmit();
smsc9220_enable_xmit();
SMSC9220->RX_CFG = 0;
smsc9220_enable_mac_recv();
/* Rx status FIFO level irq threshold */
SMSC9220->FIFO_INT &= ~(0xFF); /* Clear 2 bottom nibbles */
/* This sleep is compulsory otherwise txmit/receive will fail. */
wait_ms(2000);
return 0;
}
void smsc9220_enable_interrupt(enum smsc9220_interrupt_source source)
{
SMSC9220->INT_EN |= (1 << source);
}
void smsc9220_disable_interrupt(enum smsc9220_interrupt_source source)
{
SMSC9220->INT_EN &= ~(1 << source);
}
void smsc9220_clear_interrupt(enum smsc9220_interrupt_source source)
{
SMSC9220->INT_STS |= (1 << source);
}
int smsc9220_get_interrupt(enum smsc9220_interrupt_source source)
{
return (SMSC9220->INT_STS & (1 << source));
}
void smsc9220_establish_link(void)
{
unsigned int bcr = 0;
unsigned int hw_cfg = 0;
smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr);
bcr |= (1 << 12) | (1 << 9);
smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, bcr);
smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr);
hw_cfg = SMSC9220->HW_CFG;
hw_cfg &= 0xF0000;
hw_cfg |= (1 << 20);
SMSC9220->HW_CFG = hw_cfg;
}
int smsc9220_read_mac_address(char *mac)
{
unsigned int mac_low = 0;
unsigned int mac_high = 0;
if( !mac ) {
return 1;
}
/* Read current mac address. */
if (smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high)) {
return 1;
}
if (smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low)) {
return 1;
}
mac[0] = mac_low & 0xFF;
mac[1] = (mac_low >> 8) & 0xFF;
mac[2] = (mac_low >> 16) & 0xFF;
mac[3] = (mac_low >> 24) & 0xFF;
mac[4] = mac_high & 0xFF;
mac[5] = (mac_high >> 8) & 0xFF;
return 0;
}
unsigned int smsc9220_get_tx_data_fifo_size(void)
{
const unsigned int tx_status_fifo_size = 512; /* fixed allocation in bytes */
unsigned int tx_fifo_size = SMSC9220->HW_CFG;
tx_fifo_size = (( tx_fifo_size >> 16 ) & 0x0F) * 1024; /* size is set in kbytes */
return (tx_fifo_size - tx_status_fifo_size);
}
int smsc9220_send_by_chunks(unsigned int total_packet_length, int is_new_packet,
const char *data, unsigned int current_size)
{
static unsigned int ongoing_packet_length = 0; /* size in bytes of the packet is sending */
static unsigned int ongoing_packet_length_sent = 0; /* size in bytes of the packet has been sent */
int is_first_segment = 0; /* signing this is the first segment of the packet to be sent */
int is_last_segment = 0; /* signing this is the last segment of the packet to be sent */
unsigned int txcmd_a, txcmd_b = 0;
unsigned int dwords_to_write = 0;
unsigned int *pktptr = 0;
unsigned int xmit_inf = 0;
unsigned int tx_buffer_free_space = 0;
volatile unsigned int xmit_stat = 0;
if (!data) {
return -1; /* Invalid input parameter */
}
if (is_new_packet) {
is_first_segment = 1;
ongoing_packet_length = total_packet_length;
ongoing_packet_length_sent = 0;
} else if (ongoing_packet_length != total_packet_length ||
ongoing_packet_length_sent >= total_packet_length) {
return -1; /* Invalid input parameter */
}
/* Would next chunk fit into buffer? */
xmit_inf = SMSC9220->TX_FIFO_INF;
tx_buffer_free_space = xmit_inf & 0xFFFF;
if (current_size > tx_buffer_free_space) {
return -1; /* Not enough space in FIFO */
}
if ((ongoing_packet_length_sent + current_size) == total_packet_length) {
is_last_segment = 1;
}
pktptr = (unsigned int *) data;
txcmd_a = 0;
txcmd_b = 0;
txcmd_a |= (is_last_segment << 12) | (is_first_segment << 13); /* Last and first segments */
txcmd_a |= current_size & 0x7FF; /* [10:0] contains length */
txcmd_b |= ((current_size & 0xFFFF) << 16); /* [31:16] contains length */
txcmd_b |= current_size & 0x7FF; /* [10:0] also contains length */
SMSC9220->TX_DATA_PORT = txcmd_a;
SMSC9220->TX_DATA_PORT = txcmd_b;
dwords_to_write = (current_size + 3) >> 2;
/* PIO Copy to FIFO. Could replace this with DMA. */
while(dwords_to_write > 0) {
SMSC9220->TX_DATA_PORT = *pktptr;
pktptr++;
dwords_to_write--;
}
if (is_last_segment) {
/* pop status port */
/* for error check it should be checked "at a later time" according to data sheet */
xmit_stat = SMSC9220->TX_STAT_PORT;
}
ongoing_packet_length_sent += current_size;
return 0;
}
unsigned int smsc9220_get_rxfifo_data_used_space(void)
{
unsigned int rxfifo_inf = SMSC9220->RX_FIFO_INF;
return rxfifo_inf & 0xFFFF;
}
unsigned int smsc9220_receive_by_chunks(char *data, unsigned int dlen)
{
static unsigned int current_packet_size_words = 0;
unsigned int rxfifo_inf = 0;
unsigned int rxfifo_stat = 0;
unsigned int dlen_word = 0;
unsigned int read_length_word = 0;
unsigned int i = 0;
if (!data) {
return 0; /* Invalid input parameter */
}
if (current_packet_size_words == 0) {
/* First the packet status word should be read, */
/* which tells the size of the data, */
/* after the data can be read in synchron. */
rxfifo_inf = SMSC9220->RX_FIFO_INF;
if(rxfifo_inf & 0xFFFF) { /* If there's data */
rxfifo_stat = SMSC9220->RX_STAT_PORT;
if(rxfifo_stat != 0) { /* Fetch status of this packet */
if(rxfifo_stat & (1 << 15)) {
current_packet_size_words = 0; /* error */
}
else {
/* Ethernet controller is padding to 32bit aligned data */
current_packet_size_words = (((rxfifo_stat >> 16) & 0x3FFF) + 3) >> 2;
}
}
}
}
dlen_word = dlen / 4;
read_length_word = (dlen_word < current_packet_size_words) ? dlen_word : current_packet_size_words;
for (i = 0; i < read_length_word; i++) {
((unsigned int*)data)[i] = SMSC9220->RX_DATA_PORT;
current_packet_size_words--;
}
return (current_packet_size_words * 4);
}
unsigned int smsc9220_peek_next_packet_size(void)
{
unsigned int packet_size = 0;
unsigned int rx_stat_peek = 0;
if(smsc9220_get_rxfifo_data_used_space()) {
rx_stat_peek = SMSC9220->RX_STAT_PEEK;
packet_size = ((rx_stat_peek >> 16) & 0x3FFF);
}
return (((packet_size + 3) >> 2) << 2);
}

170
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/smsc9220_eth.h Normal file
View File

@ -0,0 +1,170 @@
/* mbed Microcontroller Library
* Copyright (c) 2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* This file is the re-implementation of mps2_ethernet_api and Selftest's ETH_MPS2.
* MPS2 Selftest:https://silver.arm.com/browse/VEI10 ->
* \ISCM-1-0\AN491\software\Selftest\v2m_mps2\
*/
#ifndef _SMSC9220_ETH_H_
#define _SMSC9220_ETH_H_
enum smsc9220_interrupt_source {
enum_smsc9220_interrupt_gpio0 = 0,
enum_smsc9220_interrupt_gpio1 = 1,
enum_smsc9220_interrupt_gpio2 = 2,
enum_smsc9220_interrupt_rxstatus_fifo_level = 3,
enum_smsc9220_interrupt_rxstatus_fifo_full = 4,
/* 5 Reserved according to Datasheet */
enum_smsc9220_interrupt_rx_dropped_frame = 6,
enum_smsc9220_interrupt_txstatus_fifo_level = 7,
enum_smsc9220_interrupt_txstatus_fifo_full = 8,
enum_smsc9220_interrupt_txdata_fifo_available = 9,
enum_smsc9220_interrupt_txdata_fifo_overrun = 10,
/* 11, 12 Reserved according to Datasheet */
enum_smsc9220_interrupt_transmit_error = 13,
enum_smsc9220_interrupt_receive_error = 14,
enum_smsc9220_interrupt_receive_watchdog_timeout = 15,
enum_smsc9220_interrupt_txstatus_overflow = 16,
enum_smsc9220_interrupt_power_management = 17,
enum_smsc9220_interrupt_phy = 18,
enum_smsc9220_interrupt_gp_timer = 19,
enum_smsc9220_interrupt_rx_dma = 20,
enum_smsc9220_interrupt_tx_ioc = 21,
/* 22 Reserved according to Datasheet*/
enum_smsc9220_interrupt_rx_dropped_frame_half = 23,
enum_smsc9220_interrupt_rx_stopped = 24,
enum_smsc9220_interrupt_tx_stopped = 25,
/* 26 - 30 Reserved according to Datasheet*/
enum_smsc9220_interrupt_sw = 31
};
/* Function declarations */
/**
* \brief Initialize SMS9220 Ethernet controller
*
* \return 0 if init is successful, 1 otherwise
*/
int smsc9220_init(void);
/**
* \brief Enable the given interrupt source.
*
* \param[in] source Enum of the interrupt source.
*/
void smsc9220_enable_interrupt(enum smsc9220_interrupt_source source);
/**
* \brief Disable the given interrupt source.
*
* \param[in] source Enum of the interrupt source.
*/
void smsc9220_disable_interrupt(enum smsc9220_interrupt_source source);
/**
* \brief Clear the given interrupt source.
*
* \param[in] source Enum of the interrupt source.
*/
void smsc9220_clear_interrupt(enum smsc9220_interrupt_source source);
/**
* \brief Get the status of the given interrupt source.
*
* \param[in] source Enum of the interrupt source.
*
* \return non-zero if the given interrupt source is triggered, zero otherwise
*/
int smsc9220_get_interrupt(enum smsc9220_interrupt_source source);
/**
* \brief Establish link
*/
void smsc9220_establish_link(void);
/**
* \brief Read MAC address from EEPROM.
*
* \param[in,out] mac array will include the read MAC address in
* 6 bytes hexadecimal format.
* It should be allocated by the caller to 6 bytes.
*
* \return 0 if read is successful, 1 otherwise
*/
int smsc9220_read_mac_address(char *mac);
/**
* \brief Get the data size of the Tx buffer, aka Maximum Transition Unit
*
* \return Fifo data size in bytes
*/
unsigned int smsc9220_get_tx_data_fifo_size(void);
/**
* \brief Send Ethernet packet from buffer chain.
* The full packet length should be known in the beginning
* of a new packet.
*
* \param[in] total_packet_length Length of the packet. Should be equal to
* the sum of passed buffers within a packet.
* \param[in] is_new_packet Should be set to non-zero if the passed buffer
* should be sent as the start of a new packet.
* If the current buffer should be sent as a full packet,
* it should be set to non-zero respectively.
* \param[in] data Pointer to the data should be sent.
* \param[in] current_size Size of the data in bytes.
*
* \return 0 if the send process is successful, standard C error code otherwise
*/
int smsc9220_send_by_chunks(unsigned int total_packet_length, int is_new_packet,
const char *data, unsigned int current_size);
/**
* \brief Receive Ethernet packet from Rx FIFO to the passed buffer.
* Stops reading at packet border.
* If the passed buffer is larger than the current packet,
* the whole packet will be read into the buffer.
* If the current packet is larger than the passed buffer,
* the buffer will be filled with data and the next call
* will continue the read from that point.
*
* \param[in,out] data Pointer where the data will be read to.
* The caller is responsible to allocate it.
* \param[in] dlen Length of the allocated data in bytes.
*
* \return Remaining bytes left in the fifo of the current packet.
*/
unsigned int smsc9220_receive_by_chunks(char *data, unsigned int dlen);
/**
* \brief Get the used space of Rx fifo in bytes.
*
* \return Data received and waiting for read in bytes
*/
unsigned int smsc9220_get_rxfifo_data_used_space(void);
/**
* \brief Get the size of next unread packet in Rx buffer, using the peak
* register, which is not destructive so can be read asynchronously.
* Warning: In case of heavy receiving load, it's possible this register
* is not perfectly in sync.
*
* \return Size in bytes of the next packet can be read from Rx fifo, according
* to the peek register.
*/
unsigned int smsc9220_peek_next_packet_size(void);
#endif

21
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device.h Normal file
View File

@ -0,0 +1,21 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

883
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/CMSDK_CM3DS.h Normal file
View File

@ -0,0 +1,883 @@
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* This file is derivative of CMSIS V5.00 ARMCM3.h
*/
#ifndef CMSDK_CM3DS_H
#define CMSDK_CM3DS_H
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn
{
/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ---------------------- CMSDK_CM3 Specific Interrupt Numbers ------------------ */
UART0_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */
Spare_IRQn = 1, /* Undefined */
UART1_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */
APB_SLAVE_0_IRQ = 3, /* Reserved for APB Slave */
APB_SLAVE_1_IRQ = 4, /* Reserved for APB Slave */
RTC_IRQn = 5, /* RTC Interrupt */
PORT0_ALL_IRQn = 6, /* GPIO Port 0 combined Interrupt */
PORT1_ALL_IRQn = 7, /* GPIO Port 1 combined Interrupt */
TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
APB_SLAVE_2_IRQ = 11, /* Reserved for APB Slave */
UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
APB_SLAVE_3_IRQ = 13, /* Reserved for APB Slave */
RESERVED0_IRQn = 14, /* Reserved */
TSC_IRQn = 15, /* Touch Screen Interrupt */
PORT0_0_IRQn = 16, /* GPIO Port 0 pin 0 Handler */
PORT0_1_IRQn = 17, /* GPIO Port 0 pin 1 Handler */
PORT0_2_IRQn = 18, /* GPIO Port 0 pin 2 Handler */
PORT0_3_IRQn = 19, /* GPIO Port 0 pin 3 Handler */
PORT0_4_IRQn = 20, /* GPIO Port 0 pin 4 Handler */
PORT0_5_IRQn = 21, /* GPIO Port 0 pin 5 Handler */
PORT0_6_IRQn = 22, /* GPIO Port 0 pin 6 Handler */
PORT0_7_IRQn = 23, /* GPIO Port 0 pin 7 Handler */
PORT0_8_IRQn = 24, /* GPIO Port 0 pin 8 Handler */
PORT0_9_IRQn = 25, /* GPIO Port 0 pin 9 Handler */
PORT0_10_IRQn = 26, /* GPIO Port 0 pin 10 Handler */
PORT0_11_IRQn = 27, /* GPIO Port 0 pin 11 Handler */
PORT0_12_IRQn = 28, /* GPIO Port 0 pin 12 Handler */
PORT0_13_IRQn = 29, /* GPIO Port 0 pin 13 Handler */
PORT0_14_IRQn = 30, /* GPIO Port 0 pin 14 Handler */
PORT0_15_IRQn = 31, /* GPIO Port 0 pin 15 Handler */
FLASH0_IRQn = 32, /* Reserved for Flash */
FLASH1_IRQn = 33, /* Reserved for Flash */
RESERVED1_IRQn = 34, /* Reserved for Cordio */
RESERVED2_IRQn = 35, /* Reserved for Cordio */
RESERVED3_IRQn = 36, /* Reserved for Cordio */
RESERVED4_IRQn = 37, /* Reserved for Cordio */
RESERVED5_IRQn = 38, /* Reserved for Cordio */
RESERVED6_IRQn = 39, /* Reserved for Cordio */
RESERVED7_IRQn = 40, /* Reserved for Cordio */
RESERVED8_IRQn = 41, /* Reserved for Cordio */
PORT2_ALL_IRQn = 42, /* GPIO Port 2 combined Interrupt */
PORT3_ALL_IRQn = 43, /* GPIO Port 3 combined Interrupt */
TRNG_IRQn = 44, /* Random number generator Interrupt */
UART2_IRQn = 45, /* UART 2 RX and TX Combined Interrupt */
UART3_IRQn = 46, /* UART 3 RX and TX Combined Interrupt */
ETHERNET_IRQn = 47, /* Ethernet interrupt t.b.a. */
I2S_IRQn = 48, /* I2S Interrupt */
MPS2_SPI0_IRQn = 49, /* SPI Interrupt (spi header) */
MPS2_SPI1_IRQn = 50, /* SPI Interrupt (clcd) */
MPS2_SPI2_IRQn = 51, /* SPI Interrupt (spi 1 ADC replacement) */
MPS2_SPI3_IRQn = 52, /* SPI Interrupt (spi 0 shield 0 replacement) */
MPS2_SPI4_IRQn = 53, /* SPI Interrupt (shield 1) */
PORT4_ALL_IRQn = 54, /* GPIO Port 4 combined Interrupt */
PORT5_ALL_IRQn = 55, /* GPIO Port 5 combined Interrupt */
UART4_IRQn = 56 /* UART 4 RX and TX Combined Interrupt */
} IRQn_Type;
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
#define __CM3DS_REV 0x0201U /* Core revision r2p1 */
#define __MPU_PRESENT 1 /* MPU present or not */
#define __VTOR_PRESENT 1 /* VTOR present or not */
#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
#include <core_cm3.h> /* Processor and core peripherals */
#include "system_CMSDK_CM3DS.h" /* System Header */
/* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */
/* ================================================================================ */
/* ------------------- Start of section using anonymous unions ------------------ */
#if defined ( __CC_ARM )
#pragma push
#pragma anon_unions
#elif defined(__ICCARM__)
#pragma language=extended
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning 586
#else
#warning Not supported compiler type
#endif
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
union {
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
};
__IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
} CMSDK_UART_TypeDef;
/* CMSDK_UART DATA Register Definitions */
#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
#define CMSDK_UART_INTSTATUS_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
#define CMSDK_UART_INTSTATUS_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
#define CMSDK_UART_INTSTATUS_TXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
#define CMSDK_UART_INTSTATUS_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
#define CMSDK_UART_INTSTATUS_RXIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
#define CMSDK_UART_INTSTATUS_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
#define CMSDK_UART_INTSTATUS_TXIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
/*----------------------------- Timer (TIMER) -------------------------------*/
typedef struct
{
__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
union {
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
};
} CMSDK_TIMER_TypeDef;
/* CMSDK_TIMER CTRL Register Definitions */
#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
/*------------- Timer (TIM) --------------------------------------------------*/
typedef struct
{
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
__IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
uint32_t RESERVED0;
__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
__IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
uint32_t RESERVED1[945];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
} CMSDK_DUALTIMER_BOTH_TypeDef;
#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct
{
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
__O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
__I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
__I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
__IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
} CMSDK_DUALTIMER_SINGLE_TypeDef;
#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
/*-------------------- General Purpose Input Output (GPIO) -------------------*/
typedef struct
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
uint32_t RESERVED0[2];
__IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
__IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
__IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
__IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
__IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
__IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
__IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
__IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
__IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
__IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
union {
__I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
__O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
};
uint32_t RESERVED1[241];
__IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
__IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
} CMSDK_GPIO_TypeDef;
#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
/* GPIO Alternate function pin numbers */
#define CMSDK_GPIO_ALTFUNC_SH0_UART2_RX 0 /* Shield 0 UART 2 Rx */
#define CMSDK_GPIO_ALTFUNC_SH0_UART2_RX_SET (CMSDK_GPIO_ALTFUNC_SH0_UART2_RX % 16)
#define CMSDK_GPIO_SH0_UART2_RX_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH0_UART2_RX / 16)
#define CMSDK_GPIO_ALTFUNC_SH0_UART2_TX 4 /* Shield 0 UART 2 Tx */
#define CMSDK_GPIO_ALTFUNC_SH0_UART2_TX_SET (CMSDK_GPIO_ALTFUNC_SH0_UART2_TX % 16)
#define CMSDK_GPIO_SH0_UART2_TX_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH0_UART2_TX / 16)
#define CMSDK_GPIO_ALTFUNC_SH1_UART3_RX 26 /* Shield 1 UART 3 Rx */
#define CMSDK_GPIO_ALTFUNC_SH1_UART3_RX_SET (CMSDK_GPIO_ALTFUNC_SH1_UART3_RX % 16)
#define CMSDK_GPIO_SH1_UART3_RX_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH1_UART3_RX / 16)
#define CMSDK_GPIO_ALTFUNC_SH1_UART3_TX 30 /* Shield 1 UART 3 Tx */
#define CMSDK_GPIO_ALTFUNC_SH1_UART3_TX_SET (CMSDK_GPIO_ALTFUNC_SH1_UART3_TX % 16)
#define CMSDK_GPIO_SH1_UART3_TX_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH1_UART3_TX / 16)
#define CMSDK_GPIO_ALTFUNC_UART4_RX 23 /* UART 4 Rx */
#define CMSDK_GPIO_ALTFUNC_UART4_RX_SET (CMSDK_GPIO_ALTFUNC_UART4_RX % 16)
#define CMSDK_GPIO_UART4_RX_GPIO_NUM (CMSDK_GPIO_ALTFUNC_UART4_RX / 16)
#define CMSDK_GPIO_ALTFUNC_UART4_TX 24 /* UART 4 Tx */
#define CMSDK_GPIO_ALTFUNC_UART4_TX_SET (CMSDK_GPIO_ALTFUNC_UART4_TX % 16)
#define CMSDK_GPIO_UART4_TX_GPIO_NUM (CMSDK_GPIO_ALTFUNC_UART4_TX / 16)
#define CMSDK_GPIO_ALTFUNC_SH0_SCL_I2C 5 /* Shield 0 SCL I2S */
#define CMSDK_GPIO_ALTFUNC_SH0_SCL_I2C_SET (CMSDK_GPIO_ALTFUNC_SH0_SCL_I2C % 16)
#define CMSDK_GPIO_SH0_SCL_I2C_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH0_SCL_I2C / 16)
#define CMSDK_GPIO_ALTFUNC_SH0_SDA_I2C 15 /* Shield 0 SDA I2S */
#define CMSDK_GPIO_ALTFUNC_SH0_SDA_I2C_SET (CMSDK_GPIO_ALTFUNC_SH0_SDA_I2C % 16)
#define CMSDK_GPIO_SH0_SDA_I2C_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH0_SDA_I2C / 16)
#define CMSDK_GPIO_ALTFUNC_SH1_SCL_I2C 31 /* Shield 1 SCL I2S */
#define CMSDK_GPIO_ALTFUNC_SH1_SCL_I2C_SET (CMSDK_GPIO_ALTFUNC_SH1_SCL_I2C % 16)
#define CMSDK_GPIO_SH1_SCL_I2C_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH1_SCL_I2C / 16)
#define CMSDK_GPIO_ALTFUNC_SH1_SDA_I2C 41 /* Shield 1 SDA I2S */
#define CMSDK_GPIO_ALTFUNC_SH1_SDA_I2C_SET (CMSDK_GPIO_ALTFUNC_SH1_SDA_I2C % 16)
#define CMSDK_GPIO_SH1_SDA_I2C_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH1_SDA_I2C / 16)
#define CMSDK_GPIO_ALTFUNC_SH0_SCK_SPI 11 /* Shield 0 SCK SPI */
#define CMSDK_GPIO_ALTFUNC_SH0_SCK_SPI_SET (CMSDK_GPIO_ALTFUNC_SH0_SCK_SPI % 16)
#define CMSDK_GPIO_SH0_SCK_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH0_SCK_SPI / 16)
#define CMSDK_GPIO_ALTFUNC_SH0_CS_SPI 12 /* Shield 0 CS SPI */
#define CMSDK_GPIO_ALTFUNC_SH0_CS_SPI_SET (CMSDK_GPIO_ALTFUNC_SH0_CS_SPI % 16)
#define CMSDK_GPIO_SH0_CS_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH0_CS_SPI / 16)
#define CMSDK_GPIO_ALTFUNC_SH0_MOSI_SPI 13 /* Shield 0 MOSI SPI */
#define CMSDK_GPIO_ALTFUNC_SH0_MOSI_SPI_SET (CMSDK_GPIO_ALTFUNC_SH0_MOSI_SPI % 16)
#define CMSDK_GPIO_SH0_MOSI_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH0_MOSI_SPI / 16)
#define CMSDK_GPIO_ALTFUNC_SH0_MISO_SPI 14 /* Shield 0 MISO SPI */
#define CMSDK_GPIO_ALTFUNC_SH0_MISO_SPI_SET (CMSDK_GPIO_ALTFUNC_SH0_MISO_SPI % 16)
#define CMSDK_GPIO_SH0_MISO_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH0_MISO_SPI / 16)
#define CMSDK_GPIO_ALTFUNC_SH1_SCK_SPI 44 /* Shield 1 SCK SPI */
#define CMSDK_GPIO_ALTFUNC_SH1_SCK_SPI_SET (CMSDK_GPIO_ALTFUNC_SH1_SCK_SPI % 16)
#define CMSDK_GPIO_SH1_SCK_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH1_SCK_SPI / 16)
#define CMSDK_GPIO_ALTFUNC_SH1_CS_SPI 38 /* Shield 1 CS SPI */
#define CMSDK_GPIO_ALTFUNC_SH1_CS_SPI_SET (CMSDK_GPIO_ALTFUNC_SH1_CS_SPI % 16)
#define CMSDK_GPIO_SH1_CS_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH1_CS_SPI / 16)
#define CMSDK_GPIO_ALTFUNC_SH1_MOSI_SPI 39 /* Shield 1 MOSI SPI */
#define CMSDK_GPIO_ALTFUNC_SH1_MOSI_SPI_SET (CMSDK_GPIO_ALTFUNC_SH1_MOSI_SPI % 16)
#define CMSDK_GPIO_SH1_MOSI_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH1_MOSI_SPI / 16)
#define CMSDK_GPIO_ALTFUNC_SH1_MISO_SPI 40 /* Shield 1 MISO SPI */
#define CMSDK_GPIO_ALTFUNC_SH1_MISO_SPI_SET (CMSDK_GPIO_ALTFUNC_SH1_MISO_SPI % 16)
#define CMSDK_GPIO_SH1_MISO_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH1_MISO_SPI / 16)
#define CMSDK_GPIO_ALTFUNC_ADC_SCK_SPI 19 /* Shield ADC SCK SPI */
#define CMSDK_GPIO_ALTFUNC_ADC_SCK_SPI_SET (CMSDK_GPIO_ALTFUNC_ADC_SCK_SPI % 16)
#define CMSDK_GPIO_ADC_SCK_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_ADC_SCK_SPI / 16)
#define CMSDK_GPIO_ALTFUNC_ADC_CS_SPI 16 /* Shield ADC CS SPI */
#define CMSDK_GPIO_ALTFUNC_ADC_CS_SPI_SET (CMSDK_GPIO_ALTFUNC_ADC_CS_SPI % 16)
#define CMSDK_GPIO_ADC_CS_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_ADC_CS_SPI / 16)
#define CMSDK_GPIO_ALTFUNC_ADC_MOSI_SPI 18 /* Shield ADC MOSI SPI */
#define CMSDK_GPIO_ALTFUNC_ADC_MOSI_SPI_SET (CMSDK_GPIO_ALTFUNC_ADC_MOSI_SPI % 16)
#define CMSDK_GPIO_ADC_MOSI_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_ADC_MOSI_SPI / 16)
#define CMSDK_GPIO_ALTFUNC_ADC_MISO_SPI 17 /* Shield ADC MISO SPI */
#define CMSDK_GPIO_ALTFUNC_ADC_MISO_SPI_SET (CMSDK_GPIO_ALTFUNC_ADC_MISO_SPI % 16)
#define CMSDK_GPIO_ADC_MISO_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_ADC_MISO_SPI / 16)
/*------------- System Control (SYSCON) --------------------------------------*/
typedef struct
{
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
__IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
__IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
uint32_t RESERVED0[3];
__IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */
__IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */
uint32_t RESERVED1[2];
__IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */
__IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */
uint32_t RESERVED2[2];
__IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */
__IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */
__IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */
__IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */
__IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */
__IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */
uint32_t RESERVED3[10];
__IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */
__IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */
__IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */
__IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */
__IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */
__IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */
uint32_t RESERVED4[2];
__IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */
__IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */
__IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */
__IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */
__IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */
__IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */
uint32_t RESERVED5[2];
__IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */
__IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */
__IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */
__IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */
__IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */
__IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */
__IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */
__IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */
__O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */
__IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */
uint32_t RESERVED6[2];
__IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */
__IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */
__I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */
uint32_t RESERVED7[1];
__IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */
__IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */
__IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */
} CMSDK_SYSCON_TypeDef;
#define CMSDK_SYSCON_REMAP_Pos 0
#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
/*------------- PL230 uDMA (PL230) --------------------------------------*/
typedef struct
{
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
__I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
__I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
__O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
__IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
__O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
__IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
__O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
__IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
__O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
__IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
__O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
__IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
__O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
uint32_t RESERVED0[3];
__IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
} CMSDK_PL230_TypeDef;
#define PL230_DMA_CHNL_BITS 0
#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
/*------------------- Watchdog ----------------------------------------------*/
typedef struct
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
__O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
__I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
__I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
uint32_t RESERVED0[762];
__IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
uint32_t RESERVED1[191];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
}CMSDK_WATCHDOG_TypeDef;
#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
/*------------------------- Real Time Clock(RTC) ----------------------------------------------*/
typedef struct
{
__I uint32_t RTCDR; /* 0x00 RO RTC Data Register */
__IO uint32_t RTCMR; /* 0x04 RW RTC Match Register */
__IO uint32_t RTCLR; /* 0x08 RW RTC Load Register */
__IO uint32_t RTCCR; /* 0x0C RW RTC Control Register */
__IO uint32_t RTCIMSC; /* 0x10 RW RTC Inerrupt Mask Set and Clear Register */
__I uint32_t RTCRIS; /* 0x14 RO RTC Raw Inerrupt Status Register */
__I uint32_t RTCMIS; /* 0x18 RO RTC Masked Inerrupt Status Register */
__O uint32_t RTCICR; /* 0x1C WO RTC Interrupt Clear Register */
} CMSDK_RTC_TypeDef;
#define CMSDK_RTC_Enable_Pos 0 /* CMSDK_RTC Enable: Real Time Clock Enable Position */
#define CMSDK_RTC_Enable_Msk (0x1ul << CMSDK_RTC_Enable_Pos) /* CMSDK_RTC Enable: Real Time Clock Enable Mask */
/* -------------------- End of section using anonymous unions ------------------- */
#if defined ( __CC_ARM )
#pragma pop
#elif defined(__ICCARM__)
/* leave anonymous unions enabled */
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning restore
#else
#warning Not supported compiler type
#endif
/* ================================================================================ */
/* ================ Peripheral memory map ================ */
/* ================================================================================ */
/* Peripheral and SRAM base address */
#define CMSDK_FLASH_BASE (0x00000000UL)
#define CMSDK_SRAM_BASE (0x20000000UL)
#define CMSDK_PERIPH_BASE (0x40000000UL)
#define CMSDK_RAM_BASE (0x20000000UL)
#define CMSDK_APB_BASE (0x40000000UL)
#define CMSDK_AHB_BASE (0x40010000UL)
/* APB peripherals */
#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
#define CMSDK_UART2_BASE (0x4002C000UL)
#define CMSDK_UART3_BASE (0x4002D000UL)
#define CMSDK_UART4_BASE (0x4002E000UL)
#define CMSDK_RTC_BASE (CMSDK_APB_BASE + 0x6000UL)
#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
/* AHB peripherals */
#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
#define CMSDK_GPIO4_BASE (0x40030000UL)
#define CMSDK_GPIO5_BASE (0x40031000UL)
#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
/* ================================================================================ */
/* ================ Peripheral declaration ================ */
/* ================================================================================ */
#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE )
#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
#define CMSDK_RTC ((CMSDK_RTC_TypeDef *) CMSDK_RTC_BASE )
#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
#define CMSDK_GPIO4 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO4_BASE )
#define CMSDK_GPIO5 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO5_BASE )
#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
#ifdef __cplusplus
}
#endif
#endif /* CMSDK_BEETLE_H */

602
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/SMM_MPS2.h Normal file
View File

@ -0,0 +1,602 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Code implementation file for the LAN Ethernet interface.
*
* This file is derivative from the MPS2 Selftest's ethernet implementation
* MPS2 Selftest: https://silver.arm.com/browse/VEI10 ->
* \ISCM-1-0\AN491\software\Selftest\v2m_mps2\SMM_MPS2.h
*
*******************************************************************************
* File: smm_mps2.h
* Release: Version 1.1
*******************************************************************************/
#ifndef __SMM_MPS2_H
#define __SMM_MPS2_H
#include "peripherallink.h" /* device specific header file */
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************/
/* FPGA System Register declaration */
/******************************************************************************/
typedef struct
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved
// [1:0] : LEDs
uint32_t RESERVED1[1];
__IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
// [31:2] : Reserved
// [1:0] : Buttons
uint32_t RESERVED2[1];
__IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
__IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
__IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
// Increments when 32-bit prescale counter reach zero
__IO uint32_t PRESCALE; // Offset: 0x1C (R/W) Prescaler
// Bit[31:0] : reload value for prescale counter
__IO uint32_t PSCNTR; // Offset: 0x020 (R/W) 32-bit Prescale counter
// current value of the pre-scaler counter
// The Cycle Up Counter increment when the prescale down counter reach 0
// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
uint32_t RESERVED4[10];
__IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
// [31:10] : Reserved
// [9] : SHIELD_1_SPI_nCS
// [8] : SHIELD_0_SPI_nCS
// [7] : ADC_SPI_nCS
// [6] : CLCD_BL_CTRL
// [5] : CLCD_RD
// [4] : CLCD_RS
// [3] : CLCD_RESET
// [2] : RESERVED
// [1] : SPI_nSS
// [0] : CLCD_CS
} MPS2_FPGAIO_TypeDef;
// MISC register bit definitions
#define CLCD_CS_Pos 0
#define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
#define SPI_nSS_Pos 1
#define SPI_nSS_Msk (1UL<<SPI_nSS_Pos)
#define CLCD_RESET_Pos 3
#define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
#define CLCD_RS_Pos 4
#define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
#define CLCD_RD_Pos 5
#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
#define CLCD_BL_Pos 6
#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
#define ADC_nCS_Pos 7
#define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
#define SHIELD_0_nCS_Pos 8
#define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
#define SHIELD_1_nCS_Pos 9
#define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
/******************************************************************************/
/* SCC Register declaration */
/******************************************************************************/
typedef struct //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved
// [0] 1 : REMAP BlockRam to ZBT
__IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
// [31:8] : Reserved
// [7:0] : MCC LEDs
uint32_t RESERVED0[1];
__I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
// [31:8] : Reserved
// [7:0] : These bits indicate state of the MCC switches
__I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
// [31:4] : Reserved
// [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
uint32_t RESERVED1[35];
__IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
// [31:0] : Data
__IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
// [31:0] : Data
__IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
// [31] : Start (generates interrupt on write to this bit)
// [30] : R/W access
// [29:26] : Reserved
// [25:20] : Function value
// [19:12] : Reserved
// [11:0] : Device (value of 0/1/2 for supported clocks)
__IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
// [31:2] : Reserved
// [1] : Error
// [0] : Complete
__IO uint32_t RESERVED2[20];
__IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
// [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
// [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
// [15:1] : Reserved
// [0] : This bit indicates if all enabled DLLs are locked
uint32_t RESERVED3[957];
__I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
// [31:24] : FPGA build number
// [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
// [19:11] : Reserved
// [10] : if “1” SCC_SW register has been implemented
// [9] : if “1” SCC_LED register has been implemented
// [8] : if “1” DLL lock register has been implemented
// [7:0] : number of SCC configuration register
__I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
// [31:24] : Implementer ID: 0x41 = ARM
// [23:20] : Application note IP variant number
// [19:16] : IP Architecture: 0x4 =AHB
// [15:4] : Primary part number: 386 = AN386
// [3:0] : Application note IP revision number
} MPS2_SCC_TypeDef;
/******************************************************************************/
/* SSP Peripheral declaration */
/******************************************************************************/
typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
// [31:16] : Reserved
// [15:8] : Serial clock rate
// [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
// [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
// [5:4] : Frame format
// [3:0] : Data Size Select
__IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
// [31:4] : Reserved
// [3] : Slave-mode output disable
// [2] : Master or slave mode select
// [1] : Synchronous serial port enable
// [0] : Loop back mode
__IO uint32_t DR; // Offset: 0x008 (R/W) Data register
// [31:16] : Reserved
// [15:0] : Transmit/Receive FIFO
__I uint32_t SR; // Offset: 0x00C (R/ ) Status register
// [31:5] : Reserved
// [4] : PrimeCell SSP busy flag
// [3] : Receive FIFO full
// [2] : Receive FIFO not empty
// [1] : Transmit FIFO not full
// [0] : Transmit FIFO empty
__IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
// [31:8] : Reserved
// [8:0] : Clock prescale divisor
__IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
// [31:4] : Reserved
// [3] : Transmit FIFO interrupt mask
// [2] : Receive FIFO interrupt mask
// [1] : Receive timeout interrupt mask
// [0] : Receive overrun interrupt mask
__I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
// [31:4] : Reserved
// [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
// [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
// [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
// [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
__I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
// [31:4] : Reserved
// [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
// [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
// [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
// [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
__O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
// [31:2] : Reserved
// [1] : Clears the SSPRTINTR interrupt
// [0] : Clears the SSPRORINTR interrupt
__IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
// [31:2] : Reserved
// [1] : Transmit DMA Enable
// [0] : Receive DMA Enable
} MPS2_SSP_TypeDef;
// SSP_CR0 Control register 0
#define SSP_CR0_DSS_Pos 0 // Data Size Select
#define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
#define SSP_CR0_FRF_Pos 4 // Frame Format Select
#define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
#define SSP_CR0_SPO_Pos 6 // SSPCLKOUT polarity
#define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
#define SSP_CR0_SPH_Pos 7 // SSPCLKOUT phase
#define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
#define SSP_CR0_SCR_Pos 8 // Serial Clock Rate (divide)
#define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
#define SSP_CR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
#define SSP_CR0_FRF_MOT 0x0000 // Frame format, Motorola
#define SSP_CR0_DSS_8 0x0007 // Data packet size, 8bits
#define SSP_CR0_DSS_16 0x000F // Data packet size, 16bits
// SSP_CR1 Control register 1
#define SSP_CR1_LBM_Pos 0 // Loop Back Mode
#define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
#define SSP_CR1_SSE_Pos 1 // Serial port enable
#define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
#define SSP_CR1_MS_Pos 2 // Master or Slave mode
#define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
#define SSP_CR1_SOD_Pos 3 // Slave Output mode Disable
#define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
// SSP_SR Status register
#define SSP_SR_TFE_Pos 0 // Transmit FIFO empty
#define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
#define SSP_SR_TNF_Pos 1 // Transmit FIFO not full
#define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
#define SSP_SR_RNE_Pos 2 // Receive FIFO not empty
#define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
#define SSP_SR_RFF_Pos 3 // Receive FIFO full
#define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
#define SSP_SR_BSY_Pos 4 // Busy
#define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
// SSP_CPSR Clock prescale register
#define SSP_CPSR_CPD_Pos 0 // Clock prescale divisor
#define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
#define SSP_CPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
// SSPIMSC Interrupt mask set and clear register
#define SSP_IMSC_RORIM_Pos 0 // Receive overrun not Masked
#define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
#define SSP_IMSC_RTIM_Pos 1 // Receive timeout not Masked
#define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
#define SSP_IMSC_RXIM_Pos 2 // Receive FIFO not Masked
#define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
#define SSP_IMSC_TXIM_Pos 3 // Transmit FIFO not Masked
#define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
// SSPRIS Raw interrupt status register
#define SSP_RIS_RORRIS_Pos 0 // Raw Overrun interrupt flag
#define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
#define SSP_RIS_RTRIS_Pos 1 // Raw Timemout interrupt flag
#define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
#define SSP_RIS_RXRIS_Pos 2 // Raw Receive interrupt flag
#define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
#define SSP_RIS_TXRIS_Pos 3 // Raw Transmit interrupt flag
#define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
// SSPMIS Masked interrupt status register
#define SSP_MIS_RORMIS_Pos 0 // Masked Overrun interrupt flag
#define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
#define SSP_MIS_RTMIS_Pos 1 // Masked Timemout interrupt flag
#define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
#define SSP_MIS_RXMIS_Pos 2 // Masked Receive interrupt flag
#define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
#define SSP_MIS_TXMIS_Pos 3 // Masked Transmit interrupt flag
#define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
// SSPICR Interrupt clear register
#define SSP_ICR_RORIC_Pos 0 // Clears Overrun interrupt flag
#define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
#define SSP_ICR_RTIC_Pos 1 // Clears Timemout interrupt flag
#define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
// SSPDMACR DMA control register
#define SSP_DMACR_RXDMAE_Pos 0 // Enable Receive FIFO DMA
#define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
#define SSP_DMACR_TXDMAE_Pos 1 // Enable Transmit FIFO DMA
#define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
/******************************************************************************/
/* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/
typedef struct
{
union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
};
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
} MPS2_I2C_TypeDef;
#define SDA 1 << 1
#define SCL 1 << 0
/******************************************************************************/
/* Audio I2S Peripheral declaration */
/******************************************************************************/
typedef struct
{
/*!< Offset: 0x000 CONTROL Register (R/W) */
__IO uint32_t CONTROL; // <h> CONTROL </h>
// <o.0> TX Enable
// <0=> TX disabled
// <1=> TX enabled
// <o.1> TX IRQ Enable
// <0=> TX IRQ disabled
// <1=> TX IRQ enabled
// <o.2> RX Enable
// <0=> RX disabled
// <1=> RX enabled
// <o.3> RX IRQ Enable
// <0=> RX IRQ disabled
// <1=> RX IRQ enabled
// <o.10..8> TX Buffer Water Level
// <0=> / IRQ triggers when any space available
// <1=> / IRQ triggers when more than 1 space available
// <2=> / IRQ triggers when more than 2 space available
// <3=> / IRQ triggers when more than 3 space available
// <4=> Undefined!
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <o.14..12> RX Buffer Water Level
// <0=> Undefined!
// <1=> / IRQ triggers when less than 1 space available
// <2=> / IRQ triggers when less than 2 space available
// <3=> / IRQ triggers when less than 3 space available
// <4=> / IRQ triggers when less than 4 space available
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <o.16> FIFO reset
// <0=> Normal operation
// <1=> FIFO reset
// <o.17> Audio Codec reset
// <0=> Normal operation
// <1=> Assert audio Codec reset
/*!< Offset: 0x004 STATUS Register (R/ ) */
__I uint32_t STATUS; // <h> STATUS </h>
// <o.0> TX Buffer alert
// <0=> TX buffer don't need service yet
// <1=> TX buffer need service
// <o.1> RX Buffer alert
// <0=> RX buffer don't need service yet
// <1=> RX buffer need service
// <o.2> TX Buffer Empty
// <0=> TX buffer have data
// <1=> TX buffer empty
// <o.3> TX Buffer Full
// <0=> TX buffer not full
// <1=> TX buffer full
// <o.4> RX Buffer Empty
// <0=> RX buffer have data
// <1=> RX buffer empty
// <o.5> RX Buffer Full
// <0=> RX buffer not full
// <1=> RX buffer full
union {
/*!< Offset: 0x008 Error Status Register (R/ ) */
__I uint32_t ERROR; // <h> ERROR </h>
// <o.0> TX error
// <0=> Okay
// <1=> TX overrun/underrun
// <o.1> RX error
// <0=> Okay
// <1=> RX overrun/underrun
/*!< Offset: 0x008 Error Clear Register ( /W) */
__O uint32_t ERRORCLR; // <h> ERRORCLR </h>
// <o.0> TX error
// <0=> Okay
// <1=> Clear TX error
// <o.1> RX error
// <0=> Okay
// <1=> Clear RX error
};
/*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80)
/*!< Offset: 0x010 Transmit Buffer ( /W) */
__O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
/*!< Offset: 0x014 Receive Buffer (R/ ) */
__I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
uint32_t RESERVED1[186];
__IO uint32_t ITCR; // <h> Integration Test Control Register </h>
// <o.0> ITEN
// <0=> Normal operation
// <1=> Integration Test mode enable
__O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
// <o.0> SDIN
__O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
// <o.0> SDOUT
// <o.1> SCLK
// <o.2> LRCK
// <o.3> IRQOUT
} MPS2_I2S_TypeDef;
#define I2S_CONTROL_TXEN_Pos 0
#define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
#define I2S_CONTROL_TXIRQEN_Pos 1
#define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
#define I2S_CONTROL_RXEN_Pos 2
#define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
#define I2S_CONTROL_RXIRQEN_Pos 3
#define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
#define I2S_CONTROL_TXWLVL_Pos 8
#define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
#define I2S_CONTROL_RXWLVL_Pos 12
#define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
/* FIFO reset*/
#define I2S_CONTROL_FIFORST_Pos 16
#define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
/* Codec reset*/
#define I2S_CONTROL_CODECRST_Pos 17
#define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
#define I2S_STATUS_TXIRQ_Pos 0
#define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
#define I2S_STATUS_RXIRQ_Pos 1
#define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
#define I2S_STATUS_TXEmpty_Pos 2
#define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
#define I2S_STATUS_TXFull_Pos 3
#define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
#define I2S_STATUS_RXEmpty_Pos 4
#define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
#define I2S_STATUS_RXFull_Pos 5
#define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
#define I2S_ERROR_TXERR_Pos 0
#define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
#define I2S_ERROR_RXERR_Pos 1
#define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
/******************************************************************************/
/* SMSC9220 Register Definitions */
/******************************************************************************/
typedef struct // SMSC LAN9220
{
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
uint32_t RESERVED1[0x7];
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
uint32_t RESERVED2[0x7];
__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
__IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
uint32_t RESERVED3; // Reserved for future use (offset 0x60)
__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
uint32_t RESERVED4; // Reserved for future use (offset 0x94)
__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
} SMSC9220_TypeDef;
// SMSC9220 MAC Registers Indices
#define SMSC9220_MAC_CR 0x1
#define SMSC9220_MAC_ADDRH 0x2
#define SMSC9220_MAC_ADDRL 0x3
#define SMSC9220_MAC_HASHH 0x4
#define SMSC9220_MAC_HASHL 0x5
#define SMSC9220_MAC_MII_ACC 0x6
#define SMSC9220_MAC_MII_DATA 0x7
#define SMSC9220_MAC_FLOW 0x8
#define SMSC9220_MAC_VLAN1 0x9
#define SMSC9220_MAC_VLAN2 0xA
#define SMSC9220_MAC_WUFF 0xB
#define SMSC9220_MAC_WUCSR 0xC
// SMSC9220 PHY Registers Indices
#define SMSC9220_PHY_BCONTROL 0x0
#define SMSC9220_PHY_BSTATUS 0x1
#define SMSC9220_PHY_ID1 0x2
#define SMSC9220_PHY_ID2 0x3
#define SMSC9220_PHY_ANEG_ADV 0x4
#define SMSC9220_PHY_ANEG_LPA 0x5
#define SMSC9220_PHY_ANEG_EXP 0x6
#define SMSC9220_PHY_MCONTROL 0x17
#define SMSC9220_PHY_MSTATUS 0x18
#define SMSC9220_PHY_CSINDICATE 0x27
#define SMSC9220_PHY_INTSRC 0x29
#define SMSC9220_PHY_INTMASK 0x30
#define SMSC9220_PHY_CS 0x31
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
#define MPS2_SSP0_BASE (0x40020000ul) /* User SSP Base Address */
#define MPS2_SSP1_BASE (0x40021000ul) /* CLCD SSP Base Address */
#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */
#define MPS2_SSP3_BASE (0x40026000ul) /* shield 0 SSP Base Address */
#define MPS2_SSP4_BASE (0x40027000ul) /* shield 1 SSP Base Address */
#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Audio Interface I2C Base Address */
#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Audio Interface I2C Base Address */
#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
#define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE )
#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
/******************************************************************************/
/* General Function Definitions */
/******************************************************************************/
/******************************************************************************/
/* General MACRO Definitions */
/******************************************************************************/
#endif /* __SMM_MPS2_H */

38
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/MPS2.sct Normal file
View File

@ -0,0 +1,38 @@
/*
* MPS2 CMSIS Library
*
* Copyright (c) 2006-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*************************************************************
*** Scatter-Loading Description File ***
*************************************************************
*/
LR_IROM1 0x00000000 0x00040000 { ; load region size_region
ER_IROM1 0x00000000 0x00040000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Total: 80 vectors = 320 bytes (0x140) to be reserved in RAM
; This is a bit more than is necessary based on the number of
; exception handlers.
RW_IRAM1 (0x20000000+0x140) (0x20000-0x140) { ; RW data
.ANY (+RW +ZI)
}
}

308
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/startup_MPS2.s Normal file
View File

@ -0,0 +1,308 @@
/*
* MPS2 CMSIS Library
*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*
* This file is derivative of CMSIS V5.00 startup_ARMCM3.s
*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
__initial_sp EQU 0x20020000 ; Top of RAM
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0_IRQHandler ; 0:UART 0 RX and TX Combined Interrupt
DCD Spare_IRQHandler ; 1:Undefined
DCD UART1_IRQHandler ; 2:UART 1 RX and TX Combined Interrupt
DCD APB_Slave0_IRQHandler ; 3:Reserved for APB Slave
DCD APB_Slave1_IRQHandler ; 4:Reserved for APB Slave
DCD RTC_IRQHandler ; 5:RTC Interrupt
DCD PORT0_IRQHandler ; 6:GPIO Port 0 combined Interrupt
DCD PORT1_ALL_IRQHandler ; 7:GPIO Port 1 combined Interrupt
DCD TIMER0_IRQHandler ; 8:TIMER 0 Interrupt
DCD TIMER1_IRQHandler ; 9:TIMER 1 Interrupt
DCD DUALTIMER_IRQHandler ; 10:Dual Timer Interrupt
DCD APB_Slave2_IRQHandler ; 11:Reserved for APB Slave
DCD UARTOVF_IRQHandler ; 12:UART 0,1,2 Overflow Interrupt
DCD APB_Slave3_IRQHandler ; 13:Reserved for APB Slave
DCD RESERVED0_IRQHandler ; 14:Reserved
DCD TSC_IRQHandler ; 15:Touch Screen Interrupt
DCD PORT0_0_IRQHandler ; 16:GPIO Port 0 pin 0 Handler
DCD PORT0_1_IRQHandler ; 17:GPIO Port 0 pin 1 Handler
DCD PORT0_2_IRQHandler ; 18:GPIO Port 0 pin 2 Handler
DCD PORT0_3_IRQHandler ; 19:GPIO Port 0 pin 3 Handler
DCD PORT0_4_IRQHandler ; 20:GPIO Port 0 pin 4 Handler
DCD PORT0_5_IRQHandler ; 21:GPIO Port 0 pin 5 Handler
DCD PORT0_6_IRQHandler ; 22:GPIO Port 0 pin 6 Handler
DCD PORT0_7_IRQHandler ; 23:GPIO Port 0 pin 7 Handler
DCD PORT0_8_IRQHandler ; 24:GPIO Port 0 pin 8 Handler
DCD PORT0_9_IRQHandler ; 25:GPIO Port 0 pin 9 Handler
DCD PORT0_10_IRQHandler ; 26:GPIO Port 0 pin 10 Handler
DCD PORT0_11_IRQHandler ; 27:GPIO Port 0 pin 11 Handler
DCD PORT0_12_IRQHandler ; 28:GPIO Port 0 pin 12 Handler
DCD PORT0_13_IRQHandler ; 29:GPIO Port 0 pin 13 Handler
DCD PORT0_14_IRQHandler ; 30:GPIO Port 0 pin 14 Handler
DCD PORT0_15_IRQHandler ; 31:GPIO Port 0 pin 15 Handler
DCD FLASH0_IRQHandler ; 32:Reserved for Flash
DCD FLASH1_IRQHandler ; 33:Reserved for Flash
DCD RESERVED1_IRQHandler ; 34:Reserved
DCD RESERVED2_IRQHandler ; 35:Reserved
DCD RESERVED3_IRQHandler ; 36:Reserved
DCD RESERVED4_IRQHandler ; 37:Reserved
DCD RESERVED5_IRQHandler ; 38:Reserved
DCD RESERVED6_IRQHandler ; 39:Reserved
DCD RESERVED7_IRQHandler ; 40:Reserved
DCD RESERVED8_IRQHandler ; 41:Reserved
DCD PORT2_ALL_IRQHandler ; 42:GPIO Port 2 combined Interrupt
DCD PORT3_ALL_IRQHandler ; 43:GPIO Port 3 combined Interrupt
DCD TRNG_IRQHandler ; 44:Random number generator Interrupt
DCD UART2_IRQHandler ; 45:UART 2 RX and TX Combined Interrupt
DCD UART3_IRQHandler ; 46:UART 3 RX and TX Combined Interrupt
DCD ETHERNET_IRQHandler ; 47:Ethernet interrupt t.b.a.
DCD I2S_IRQHandler ; 48:I2S Interrupt
DCD MPS2_SPI0_IRQHandler ; 49:SPI Interrupt (spi header)
DCD MPS2_SPI1_IRQHandler ; 50:SPI Interrupt (clcd)
DCD MPS2_SPI2_IRQHandler ; 51:SPI Interrupt (spi 1 ADC replacement)
DCD MPS2_SPI3_IRQHandler ; 52:SPI Interrupt (spi 0 shield 0 replacement)
DCD MPS2_SPI4_IRQHandler ; 53:SPI Interrupt (shield 1)
DCD PORT4_ALL_IRQHandler ; 54:GPIO Port 4 combined Interrupt
DCD PORT5_ALL_IRQHandler ; 55:GPIO Port 5 combined Interrupt
DCD UART4_IRQHandler ; 56:UART 4 RX and TX Combined Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UART0_IRQHandler [WEAK] ; 0:UART 0 RX and TX Combined Interrupt
EXPORT Spare_IRQHandler [WEAK] ; 1:Undefined
EXPORT UART1_IRQHandler [WEAK] ; 2:UART 1 RX and TX Combined Interrupt
EXPORT APB_Slave0_IRQHandler [WEAK] ; 3:Reserved for APB Slave
EXPORT APB_Slave1_IRQHandler [WEAK] ; 4:Reserved for APB Slave
EXPORT RTC_IRQHandler [WEAK] ; 5:RTC Interrupt
EXPORT PORT0_IRQHandler [WEAK] ; 6:GPIO Port 0 combined Interrupt
EXPORT PORT1_ALL_IRQHandler [WEAK] ; 7:GPIO Port 1 combined Interrupt
EXPORT TIMER0_IRQHandler [WEAK] ; 8:TIMER 0 Interrupt
EXPORT TIMER1_IRQHandler [WEAK] ; 9:TIMER 1 Interrupt
EXPORT DUALTIMER_IRQHandler [WEAK] ; 10:Dual Timer Interrupt
EXPORT APB_Slave2_IRQHandler [WEAK] ; 11:Reserved for APB Slave
EXPORT UARTOVF_IRQHandler [WEAK] ; 12:UART 0,1,2 Overflow Interrupt
EXPORT APB_Slave3_IRQHandler [WEAK] ; 13:Reserved for APB Slave
EXPORT RESERVED0_IRQHandler [WEAK] ; 14:Reserved
EXPORT TSC_IRQHandler [WEAK] ; 15:Touch Screen Interrupt
EXPORT PORT0_0_IRQHandler [WEAK] ; 16:GPIO Port 0 pin 0 Handler
EXPORT PORT0_1_IRQHandler [WEAK] ; 17:GPIO Port 0 pin 1 Handler
EXPORT PORT0_2_IRQHandler [WEAK] ; 18:GPIO Port 0 pin 2 Handler
EXPORT PORT0_3_IRQHandler [WEAK] ; 19:GPIO Port 0 pin 3 Handler
EXPORT PORT0_4_IRQHandler [WEAK] ; 20:GPIO Port 0 pin 4 Handler
EXPORT PORT0_5_IRQHandler [WEAK] ; 21:GPIO Port 0 pin 5 Handler
EXPORT PORT0_6_IRQHandler [WEAK] ; 22:GPIO Port 0 pin 6 Handler
EXPORT PORT0_7_IRQHandler [WEAK] ; 23:GPIO Port 0 pin 7 Handler
EXPORT PORT0_8_IRQHandler [WEAK] ; 24:GPIO Port 0 pin 8 Handler
EXPORT PORT0_9_IRQHandler [WEAK] ; 25:GPIO Port 0 pin 9 Handler
EXPORT PORT0_10_IRQHandler [WEAK] ; 26:GPIO Port 0 pin 10 Handler
EXPORT PORT0_11_IRQHandler [WEAK] ; 27:GPIO Port 0 pin 11 Handler
EXPORT PORT0_12_IRQHandler [WEAK] ; 28:GPIO Port 0 pin 12 Handler
EXPORT PORT0_13_IRQHandler [WEAK] ; 29:GPIO Port 0 pin 13 Handler
EXPORT PORT0_14_IRQHandler [WEAK] ; 30:GPIO Port 0 pin 14 Handler
EXPORT PORT0_15_IRQHandler [WEAK] ; 31:GPIO Port 0 pin 15 Handler
EXPORT FLASH0_IRQHandler [WEAK] ; 32:Reserved for Flash
EXPORT FLASH1_IRQHandler [WEAK] ; 33:Reserved for Flash
EXPORT RESERVED1_IRQHandler [WEAK] ; 34:Reserved
EXPORT RESERVED2_IRQHandler [WEAK] ; 35:Reserved
EXPORT RESERVED3_IRQHandler [WEAK] ; 36:Reserved
EXPORT RESERVED4_IRQHandler [WEAK] ; 37:Reserved
EXPORT RESERVED5_IRQHandler [WEAK] ; 38:Reserved
EXPORT RESERVED6_IRQHandler [WEAK] ; 39:Reserved
EXPORT RESERVED7_IRQHandler [WEAK] ; 40:Reserved
EXPORT RESERVED8_IRQHandler [WEAK] ; 41:Reserved
EXPORT PORT2_ALL_IRQHandler [WEAK] ; 42:GPIO Port 2 combined Interrupt
EXPORT PORT3_ALL_IRQHandler [WEAK] ; 43:GPIO Port 3 combined Interrupt
EXPORT TRNG_IRQHandler [WEAK] ; 44:Random number generator Interrupt
EXPORT UART2_IRQHandler [WEAK] ; 45:UART 2 RX and TX Combined Interrupt
EXPORT UART3_IRQHandler [WEAK] ; 46:UART 3 RX and TX Combined Interrupt
EXPORT ETHERNET_IRQHandler [WEAK] ; 47:Ethernet interrupt t.b.a.
EXPORT I2S_IRQHandler [WEAK] ; 48:I2S Interrupt
EXPORT MPS2_SPI0_IRQHandler [WEAK] ; 49:SPI Interrupt (spi header)
EXPORT MPS2_SPI1_IRQHandler [WEAK] ; 50:SPI Interrupt (clcd)
EXPORT MPS2_SPI2_IRQHandler [WEAK] ; 51:SPI Interrupt (spi 1 ADC replacement)
EXPORT MPS2_SPI3_IRQHandler [WEAK] ; 52:SPI Interrupt (spi 0 shield 0 replacement)
EXPORT MPS2_SPI4_IRQHandler [WEAK] ; 53:SPI Interrupt (shield 1)
EXPORT PORT4_ALL_IRQHandler [WEAK] ; 54:GPIO Port 4 combined Interrupt
EXPORT PORT5_ALL_IRQHandler [WEAK] ; 55:GPIO Port 5 combined Interrupt
EXPORT UART4_IRQHandler [WEAK] ; 56:UART 4 RX and TX Combined Interrupt
UART0_IRQHandler
Spare_IRQHandler
UART1_IRQHandler
APB_Slave0_IRQHandler
APB_Slave1_IRQHandler
RTC_IRQHandler
PORT0_IRQHandler
PORT1_ALL_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
DUALTIMER_IRQHandler
APB_Slave2_IRQHandler
UARTOVF_IRQHandler
APB_Slave3_IRQHandler
RESERVED0_IRQHandler
TSC_IRQHandler
PORT0_0_IRQHandler
PORT0_1_IRQHandler
PORT0_2_IRQHandler
PORT0_3_IRQHandler
PORT0_4_IRQHandler
PORT0_5_IRQHandler
PORT0_6_IRQHandler
PORT0_7_IRQHandler
PORT0_8_IRQHandler
PORT0_9_IRQHandler
PORT0_10_IRQHandler
PORT0_11_IRQHandler
PORT0_12_IRQHandler
PORT0_13_IRQHandler
PORT0_14_IRQHandler
PORT0_15_IRQHandler
FLASH0_IRQHandler
FLASH1_IRQHandler
RESERVED1_IRQHandler
RESERVED2_IRQHandler
RESERVED3_IRQHandler
RESERVED4_IRQHandler
RESERVED5_IRQHandler
RESERVED6_IRQHandler
RESERVED7_IRQHandler
RESERVED8_IRQHandler
PORT2_ALL_IRQHandler
PORT3_ALL_IRQHandler
TRNG_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
ETHERNET_IRQHandler
I2S_IRQHandler
MPS2_SPI0_IRQHandler
MPS2_SPI1_IRQHandler
MPS2_SPI2_IRQHandler
MPS2_SPI3_IRQHandler
MPS2_SPI4_IRQHandler
PORT4_ALL_IRQHandler
PORT5_ALL_IRQHandler
UART4_IRQHandler
B .
ENDP
ALIGN
END

43
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/sys.cpp Normal file
View File

@ -0,0 +1,43 @@
/*
* PackageLicenseDeclared: Apache-2.0
* Copyright (c) 2009-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <rt_misc.h>
#include <stdint.h>
/* Get RW_IRAM1 from scatter definition */
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
/* beetle_zi_limit has to be 8-byte aligned */
zi_limit = (zi_limit + 7) & ~0x7;
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

211
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_GCC_ARM/MPS2.ld Normal file
View File

@ -0,0 +1,211 @@
/*
* MPS2 CMSIS Library
*/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.00 gcc_arm.ld
*/
/* Linker script for mbed CM3DS on MPS2 */
/* Linker script to configure memory regions. */
/* The length of the VECTORS region is a bit larger than
* is necessary based on the number of exception handlers.
*/
MEMORY
{
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
HEAP_SIZE = 0x4000;
STACK_SIZE = 0x1000;
/* Size of the vector table in SRAM */
M_VECTOR_RAM_SIZE = 0x140;
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(4);
} > VECTORS
.text :
{
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
.interrupts_ram :
{
. = ALIGN(4);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
. += M_VECTOR_RAM_SIZE;
. = ALIGN(4);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > RAM
.data :
{
PROVIDE(__etext = LOADADDR(.data));
. = ALIGN(4);
__data_start__ = .;
*(vtable)
*(.data)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM AT > FLASH
.uninitialized (NOLOAD):
{
. = ALIGN(32);
__uninitialized_start = .;
*(.uninitialized)
KEEP(*(.keep.uninitialized))
. = ALIGN(32);
__uninitialized_end = .;
} > RAM
.bss :
{
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > RAM
bss_size = __bss_end__ - __bss_start__;
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
} /* End of sections */

257
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S Normal file
View File

@ -0,0 +1,257 @@
/*
* MPS2 CMSIS Library
*/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.00 startup_ARMCM3.S
*/
.syntax unified
.arch armv7-m
.section .vector_table,"a",%progbits
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long UART0_IRQHandler /* 0: UART 0 RX and TX Combined Interrupt */
.long Spare_IRQHandler /* 1: Undefined */
.long UART1_IRQHandler /* 2: UART 1 RX and TX Combined Interrupt */
.long APB_Slave0_IRQHandler /* 3: Reserved for APB Slave */
.long APB_Slave1_IRQHandler /* 4: Reserved for APB Slave */
.long RTC_IRQHandler /* 5: RTC Interrupt */
.long PORT0_IRQHandler /* 6: GPIO Port 0 combined Interrupt */
.long PORT1_ALL_IRQHandler /* 7: GPIO Port 1 combined Interrupt */
.long TIMER0_IRQHandler /* 8: TIMER 0 Interrupt */
.long TIMER1_IRQHandler /* 9: TIMER 1 Interrupt */
.long DUALTIMER_IRQHandler /* 10: Dual Timer Interrupt */
.long APB_Slave2_IRQHandler /* 11: Reserved for APB Slave */
.long UARTOVF_IRQHandler /* 12: UART 0,1,2 Overflow Interrupt */
.long APB_Slave3_IRQHandler /* 13: Reserved for APB Slave */
.long RESERVED0_IRQHandler /* 14: Reserved */
.long TSC_IRQHandler /* 15: Touch Screen Interrupt */
.long PORT0_0_IRQHandler /* 16: GPIO Port 0 pin 0 Handler */
.long PORT0_1_IRQHandler /* 17: GPIO Port 0 pin 1 Handler */
.long PORT0_2_IRQHandler /* 18: GPIO Port 0 pin 2 Handler */
.long PORT0_3_IRQHandler /* 19: GPIO Port 0 pin 3 Handler */
.long PORT0_4_IRQHandler /* 20: GPIO Port 0 pin 4 Handler */
.long PORT0_5_IRQHandler /* 21: GPIO Port 0 pin 5 Handler */
.long PORT0_6_IRQHandler /* 22: GPIO Port 0 pin 6 Handler */
.long PORT0_7_IRQHandler /* 23: GPIO Port 0 pin 7 Handler */
.long PORT0_8_IRQHandler /* 24: GPIO Port 0 pin 8 Handler */
.long PORT0_9_IRQHandler /* 25: GPIO Port 0 pin 9 Handler */
.long PORT0_10_IRQHandler /* 26: GPIO Port 0 pin 10 Handler */
.long PORT0_11_IRQHandler /* 27: GPIO Port 0 pin 11 Handler */
.long PORT0_12_IRQHandler /* 28: GPIO Port 0 pin 12 Handler */
.long PORT0_13_IRQHandler /* 29: GPIO Port 0 pin 13 Handler */
.long PORT0_14_IRQHandler /* 30: GPIO Port 0 pin 14 Handler */
.long PORT0_15_IRQHandler /* 31: GPIO Port 0 pin 15 Handler */
.long FLASH0_IRQHandler /* 32: Reserved for Flash */
.long FLASH1_IRQHandler /* 33: Reserved for Flash */
.long RESERVED1_IRQHandler /* 34: Reserved */
.long RESERVED2_IRQHandler /* 35: Reserved */
.long RESERVED3_IRQHandler /* 36: Reserved */
.long RESERVED4_IRQHandler /* 37: Reserved */
.long RESERVED5_IRQHandler /* 38: Reserved */
.long RESERVED6_IRQHandler /* 39: Reserved */
.long RESERVED7_IRQHandler /* 40: Reserved */
.long RESERVED8_IRQHandler /* 41: Reserved */
.long PORT2_ALL_IRQHandler /* 42: GPIO Port 2 combined Interrupt */
.long PORT3_ALL_IRQHandler /* 43: GPIO Port 3 combined Interrupt */
.long TRNG_IRQHandler /* 44: Random number generator Interrupt */
.long UART2_IRQHandler /* 45: UART 2 RX and TX Combined Interrupt */
.long UART3_IRQHandler /* 46: UART 3 RX and TX Combined Interrupt */
.long ETHERNET_IRQHandler /* 47: Ethernet interrupt t.b.a. */
.long I2S_IRQHandler /* 48: I2S Interrupt */
.long MPS2_SPI0_IRQHandler /* 49: SPI Interrupt (spi header) */
.long MPS2_SPI1_IRQHandler /* 50: SPI Interrupt (clcd) */
.long MPS2_SPI2_IRQHandler /* 51: SPI Interrupt (spi 1 ADC replacement) */
.long MPS2_SPI3_IRQHandler /* 52: SPI Interrupt (spi 0 shield 0 replacement) */
.long MPS2_SPI4_IRQHandler /* 53: SPI Interrupt (shield 1) */
.long PORT4_ALL_IRQHandler /* 54: GPIO Port 4 combined Interrupt */
.long PORT5_ALL_IRQHandler /* 55: GPIO Port 5 combined Interrupt */
.long UART4_IRQHandler /* 56: UART 4 RX and TX Combined Interrupt */
.size __isr_vector, . - __isr_vector
.section .text.Reset_Handler
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =SystemInit
blx r0
/*
* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* _etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .Lflash_to_ram_loop_end
movs r4, 0
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
/* Initialize .bss */
init_bss:
ldr r1, =__bss_start__
ldr r2, =__bss_end__
ldr r3, =bss_size
cmp r3, #0
beq system_startup
mov r4, #0
zero:
strb r4, [r1], #1
subs r3, r3, #1
bne zero
system_startup:
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/*
* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers
*/
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
def_default_handler BusFault_Handler
def_default_handler UsageFault_Handler
def_default_handler SVC_Handler
def_default_handler DebugMon_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
/* External interrupts */
def_irq_default_handler UART0_IRQHandler /* 0: UART 0 RX and TX Combined Interrupt */
def_irq_default_handler Spare_IRQHandler /* 1: Undefined */
def_irq_default_handler UART1_IRQHandler /* 2: UART 1 RX and TX Combined Interrupt */
def_irq_default_handler APB_Slave0_IRQHandler /* 3: Reserved for APB Slave */
def_irq_default_handler APB_Slave1_IRQHandler /* 4: Reserved for APB Slave */
def_irq_default_handler RTC_IRQHandler /* 5: RTC Interrupt */
def_irq_default_handler PORT0_IRQHandler /* 6: GPIO Port 0 combined Interrupt */
def_irq_default_handler PORT1_ALL_IRQHandler /* 7: GPIO Port 1 combined Interrupt */
def_irq_default_handler TIMER0_IRQHandler /* 8: TIMER 0 Interrupt */
def_irq_default_handler TIMER1_IRQHandler /* 9: TIMER 1 Interrupt */
def_irq_default_handler DUALTIMER_IRQHandler /* 10: Dual Timer Interrupt */
def_irq_default_handler APB_Slave2_IRQHandler /* 11: Reserved for APB Slave */
def_irq_default_handler UARTOVF_IRQHandler /* 12: UART 0,1,2 Overflow Interrupt */
def_irq_default_handler APB_Slave3_IRQHandler /* 13: Reserved for APB Slave */
def_irq_default_handler RESERVED0_IRQHandler /* 14: Reserved */
def_irq_default_handler TSC_IRQHandler /* 15: Touch Screen Interrupt */
def_irq_default_handler PORT0_0_IRQHandler /* 16: GPIO Port 0 pin 0 Handler */
def_irq_default_handler PORT0_1_IRQHandler /* 17: GPIO Port 0 pin 1 Handler */
def_irq_default_handler PORT0_2_IRQHandler /* 18: GPIO Port 0 pin 2 Handler */
def_irq_default_handler PORT0_3_IRQHandler /* 19: GPIO Port 0 pin 3 Handler */
def_irq_default_handler PORT0_4_IRQHandler /* 20: GPIO Port 0 pin 4 Handler */
def_irq_default_handler PORT0_5_IRQHandler /* 21: GPIO Port 0 pin 5 Handler */
def_irq_default_handler PORT0_6_IRQHandler /* 22: GPIO Port 0 pin 6 Handler */
def_irq_default_handler PORT0_7_IRQHandler /* 23: GPIO Port 0 pin 7 Handler */
def_irq_default_handler PORT0_8_IRQHandler /* 24: GPIO Port 0 pin 8 Handler */
def_irq_default_handler PORT0_9_IRQHandler /* 25: GPIO Port 0 pin 9 Handler */
def_irq_default_handler PORT0_10_IRQHandler /* 26: GPIO Port 0 pin 10 Handler */
def_irq_default_handler PORT0_11_IRQHandler /* 27: GPIO Port 0 pin 11 Handler */
def_irq_default_handler PORT0_12_IRQHandler /* 28: GPIO Port 0 pin 12 Handler */
def_irq_default_handler PORT0_13_IRQHandler /* 29: GPIO Port 0 pin 13 Handler */
def_irq_default_handler PORT0_14_IRQHandler /* 30: GPIO Port 0 pin 14 Handler */
def_irq_default_handler PORT0_15_IRQHandler /* 31: GPIO Port 0 pin 15 Handler */
def_irq_default_handler FLASH0_IRQHandler /* 32: Reserved for Flash */
def_irq_default_handler FLASH1_IRQHandler /* 33: Reserved for Flash */
def_irq_default_handler RESERVED1_IRQHandler /* 34: Reserved */
def_irq_default_handler RESERVED2_IRQHandler /* 35: Reserved */
def_irq_default_handler RESERVED3_IRQHandler /* 36: Reserved */
def_irq_default_handler RESERVED4_IRQHandler /* 37: Reserved */
def_irq_default_handler RESERVED5_IRQHandler /* 38: Reserved */
def_irq_default_handler RESERVED6_IRQHandler /* 39: Reserved */
def_irq_default_handler RESERVED7_IRQHandler /* 40: Reserved */
def_irq_default_handler RESERVED8_IRQHandler /* 41: Reserved */
def_irq_default_handler PORT2_ALL_IRQHandler /* 42: GPIO Port 2 combined Interrupt */
def_irq_default_handler PORT3_ALL_IRQHandler /* 43: GPIO Port 3 combined Interrupt */
def_irq_default_handler TRNG_IRQHandler /* 44: Random number generator Interrupt */
def_irq_default_handler UART2_IRQHandler /* 45: UART 2 RX and TX Combined Interrupt */
def_irq_default_handler UART3_IRQHandler /* 46: UART 3 RX and TX Combined Interrupt */
def_irq_default_handler ETHERNET_IRQHandler /* 47: Ethernet interrupt t.b.a. */
def_irq_default_handler I2S_IRQHandler /* 48: I2S Interrupt */
def_irq_default_handler MPS2_SPI0_IRQHandler /* 49: SPI Interrupt (spi header) */
def_irq_default_handler MPS2_SPI1_IRQHandler /* 50: SPI Interrupt (clcd) */
def_irq_default_handler MPS2_SPI2_IRQHandler /* 51: SPI Interrupt (spi 1 ADC replacement) */
def_irq_default_handler MPS2_SPI3_IRQHandler /* 52: SPI Interrupt (spi 0 shield 0 replacement) */
def_irq_default_handler MPS2_SPI4_IRQHandler /* 53: SPI Interrupt (shield 1) */
def_irq_default_handler PORT4_ALL_IRQHandler /* 54: GPIO Port 4 combined Interrupt */
def_irq_default_handler PORT5_ALL_IRQHandler /* 55: GPIO Port 5 combined Interrupt */
def_irq_default_handler UART4_IRQHandler /* 56: UART 4 RX and TX Combined Interrupt */
.end

56
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_IAR/MPS2.icf Normal file
View File

@ -0,0 +1,56 @@
/*
* MPS2 CMSIS Library
*/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License) you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* The RAM region doesn't start at the beginning of the RAM address
* space to create space for the vector table copied over to the RAM by mbed.
* The space left is a bit bigger than is necessary based on the number of
* interrupt handlers.
*/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000140;
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
/*-Sizes-*/
/* Heap and Stack size */
define symbol __ICFEDIT_size_heap__ = 0x4000;
define symbol __ICFEDIT_size_cstack__ = 0x1000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
initialize by copy { readwrite };
do not initialize { section .noinit };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

490
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_IAR/startup_MPS2.s Normal file
View File

@ -0,0 +1,490 @@
;/*
; * MPS2 CMSIS Library
; */
;/*
; * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
; * This file is derivative of CMSIS V5.00 startup_Device.s
; */
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD UART0_IRQHandler ; 0:UART 0 RX and TX Combined Interrupt
DCD Spare_IRQHandler ; 1:Undefined
DCD UART1_IRQHandler ; 2:UART 1 RX and TX Combined Interrupt
DCD APB_Slave0_IRQHandler ; 3:Reserved for APB Slave
DCD APB_Slave1_IRQHandler ; 4:Reserved for APB Slave
DCD RTC_IRQHandler ; 5:RTC Interrupt
DCD PORT0_IRQHandler ; 6:GPIO Port 0 combined Interrupt
DCD PORT1_ALL_IRQHandler ; 7:GPIO Port 1 combined Interrupt
DCD TIMER0_IRQHandler ; 8:TIMER 0 Interrupt
DCD TIMER1_IRQHandler ; 9:TIMER 1 Interrupt
DCD DUALTIMER_IRQHandler ; 10:Dual Timer Interrupt
DCD APB_Slave2_IRQHandler ; 11:Reserved for APB Slave
DCD UARTOVF_IRQHandler ; 12:UART 0,1,2 Overflow Interrupt
DCD APB_Slave3_IRQHandler ; 13:Reserved for APB Slave
DCD RESERVED0_IRQHandler ; 14:Reserved
DCD TSC_IRQHandler ; 15:Touch Screen Interrupt
DCD PORT0_0_IRQHandler ; 16:GPIO Port 0 pin 0 Handler
DCD PORT0_1_IRQHandler ; 17:GPIO Port 0 pin 1 Handler
DCD PORT0_2_IRQHandler ; 18:GPIO Port 0 pin 2 Handler
DCD PORT0_3_IRQHandler ; 19:GPIO Port 0 pin 3 Handler
DCD PORT0_4_IRQHandler ; 20:GPIO Port 0 pin 4 Handler
DCD PORT0_5_IRQHandler ; 21:GPIO Port 0 pin 5 Handler
DCD PORT0_6_IRQHandler ; 22:GPIO Port 0 pin 6 Handler
DCD PORT0_7_IRQHandler ; 23:GPIO Port 0 pin 7 Handler
DCD PORT0_8_IRQHandler ; 24:GPIO Port 0 pin 8 Handler
DCD PORT0_9_IRQHandler ; 25:GPIO Port 0 pin 9 Handler
DCD PORT0_10_IRQHandler ; 26:GPIO Port 0 pin 10 Handler
DCD PORT0_11_IRQHandler ; 27:GPIO Port 0 pin 11 Handler
DCD PORT0_12_IRQHandler ; 28:GPIO Port 0 pin 12 Handler
DCD PORT0_13_IRQHandler ; 29:GPIO Port 0 pin 13 Handler
DCD PORT0_14_IRQHandler ; 30:GPIO Port 0 pin 14 Handler
DCD PORT0_15_IRQHandler ; 31:GPIO Port 0 pin 15 Handler
DCD FLASH0_IRQHandler ; 32:Reserved for Flash
DCD FLASH1_IRQHandler ; 33:Reserved for Flash
DCD RESERVED1_IRQHandler ; 34:Reserved
DCD RESERVED2_IRQHandler ; 35:Reserved
DCD RESERVED3_IRQHandler ; 36:Reserved
DCD RESERVED4_IRQHandler ; 37:Reserved
DCD RESERVED5_IRQHandler ; 38:Reserved
DCD RESERVED6_IRQHandler ; 39:Reserved
DCD RESERVED7_IRQHandler ; 40:Reserved
DCD RESERVED8_IRQHandler ; 41:Reserved
DCD PORT2_ALL_IRQHandler ; 42:GPIO Port 2 combined Interrupt
DCD PORT3_ALL_IRQHandler ; 43:GPIO Port 3 combined Interrupt
DCD TRNG_IRQHandler ; 44:Random number generator Interrupt
DCD UART2_IRQHandler ; 45:UART 2 RX and TX Combined Interrupt
DCD UART3_IRQHandler ; 46:UART 3 RX and TX Combined Interrupt
DCD ETHERNET_IRQHandler ; 47:Ethernet interrupt t.b.a.
DCD I2S_IRQHandler ; 48:I2S Interrupt
DCD MPS2_SPI0_IRQHandler ; 49:SPI Interrupt (spi header)
DCD MPS2_SPI1_IRQHandler ; 50:SPI Interrupt (clcd)
DCD MPS2_SPI2_IRQHandler ; 51:SPI Interrupt (spi 1 ADC replacement)
DCD MPS2_SPI3_IRQHandler ; 52:SPI Interrupt (spi 0 shield 0 replacement)
DCD MPS2_SPI4_IRQHandler ; 53:SPI Interrupt (shield 1)
DCD PORT4_ALL_IRQHandler ; 54:GPIO Port 4 combined Interrupt
DCD PORT5_ALL_IRQHandler ; 55:GPIO Port 5 combined Interrupt
DCD UART4_IRQHandler ; 56:UART 4 RX and TX Combined Interrupt
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK UART0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART0_IRQHandler
B UART0_IRQHandler
PUBWEAK Spare_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
Spare_IRQHandler
B Spare_IRQHandler
PUBWEAK UART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART1_IRQHandler
B UART1_IRQHandler
PUBWEAK APB_Slave0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
APB_Slave0_IRQHandler
B APB_Slave0_IRQHandler
PUBWEAK APB_Slave1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
APB_Slave1_IRQHandler
B APB_Slave1_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK PORT0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_IRQHandler
B PORT0_IRQHandler
PUBWEAK PORT1_ALL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT1_ALL_IRQHandler
B PORT1_ALL_IRQHandler
PUBWEAK TIMER0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER0_IRQHandler
B TIMER0_IRQHandler
PUBWEAK TIMER1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER1_IRQHandler
B TIMER1_IRQHandler
PUBWEAK DUALTIMER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DUALTIMER_IRQHandler
B DUALTIMER_IRQHandler
PUBWEAK APB_Slave2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
APB_Slave2_IRQHandler
B APB_Slave2_IRQHandler
PUBWEAK UARTOVF_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTOVF_IRQHandler
B UARTOVF_IRQHandler
PUBWEAK APB_Slave3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
APB_Slave3_IRQHandler
B APB_Slave3_IRQHandler
PUBWEAK RESERVED0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RESERVED0_IRQHandler
B RESERVED0_IRQHandler
PUBWEAK TSC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TSC_IRQHandler
B TSC_IRQHandler
PUBWEAK PORT0_0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_0_IRQHandler
B PORT0_0_IRQHandler
PUBWEAK PORT0_1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_1_IRQHandler
B PORT0_1_IRQHandler
PUBWEAK PORT0_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_2_IRQHandler
B PORT0_2_IRQHandler
PUBWEAK PORT0_3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_3_IRQHandler
B PORT0_3_IRQHandler
PUBWEAK PORT0_4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_4_IRQHandler
B PORT0_4_IRQHandler
PUBWEAK PORT0_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_5_IRQHandler
B PORT0_5_IRQHandler
PUBWEAK PORT0_6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_6_IRQHandler
B PORT0_6_IRQHandler
PUBWEAK PORT0_7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_7_IRQHandler
B PORT0_7_IRQHandler
PUBWEAK PORT0_8_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_8_IRQHandler
B PORT0_8_IRQHandler
PUBWEAK PORT0_9_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_9_IRQHandler
B PORT0_9_IRQHandler
PUBWEAK PORT0_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_10_IRQHandler
B PORT0_10_IRQHandler
PUBWEAK PORT0_11_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_11_IRQHandler
B PORT0_11_IRQHandler
PUBWEAK PORT0_12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_12_IRQHandler
B PORT0_12_IRQHandler
PUBWEAK PORT0_13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_13_IRQHandler
B PORT0_13_IRQHandler
PUBWEAK PORT0_14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_14_IRQHandler
B PORT0_14_IRQHandler
PUBWEAK PORT0_15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_15_IRQHandler
B PORT0_15_IRQHandler
PUBWEAK FLASH0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH0_IRQHandler
B FLASH0_IRQHandler
PUBWEAK FLASH1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH1_IRQHandler
B FLASH1_IRQHandler
PUBWEAK RESERVED1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RESERVED1_IRQHandler
B RESERVED1_IRQHandler
PUBWEAK RESERVED2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RESERVED2_IRQHandler
B RESERVED2_IRQHandler
PUBWEAK RESERVED3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RESERVED3_IRQHandler
B RESERVED3_IRQHandler
PUBWEAK RESERVED4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RESERVED4_IRQHandler
B RESERVED4_IRQHandler
PUBWEAK RESERVED5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RESERVED5_IRQHandler
B RESERVED5_IRQHandler
PUBWEAK RESERVED6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RESERVED6_IRQHandler
B RESERVED6_IRQHandler
PUBWEAK RESERVED7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RESERVED7_IRQHandler
B RESERVED7_IRQHandler
PUBWEAK RESERVED8_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RESERVED8_IRQHandler
B RESERVED8_IRQHandler
PUBWEAK PORT2_ALL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT2_ALL_IRQHandler
B PORT2_ALL_IRQHandler
PUBWEAK PORT3_ALL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT3_ALL_IRQHandler
B PORT3_ALL_IRQHandler
PUBWEAK TRNG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TRNG_IRQHandler
B TRNG_IRQHandler
PUBWEAK UART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART2_IRQHandler
B UART2_IRQHandler
PUBWEAK UART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART3_IRQHandler
B UART3_IRQHandler
PUBWEAK ETHERNET_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ETHERNET_IRQHandler
B ETHERNET_IRQHandler
PUBWEAK I2S_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2S_IRQHandler
B I2S_IRQHandler
PUBWEAK MPS2_SPI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
MPS2_SPI0_IRQHandler
B MPS2_SPI0_IRQHandler
PUBWEAK MPS2_SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
MPS2_SPI1_IRQHandler
B MPS2_SPI1_IRQHandler
PUBWEAK MPS2_SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
MPS2_SPI2_IRQHandler
B MPS2_SPI2_IRQHandler
PUBWEAK MPS2_SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
MPS2_SPI3_IRQHandler
B MPS2_SPI3_IRQHandler
PUBWEAK MPS2_SPI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
MPS2_SPI4_IRQHandler
B MPS2_SPI4_IRQHandler
PUBWEAK PORT4_ALL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT4_ALL_IRQHandler
B PORT4_ALL_IRQHandler
PUBWEAK PORT5_ALL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT5_ALL_IRQHandler
B PORT5_ALL_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
END

265
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/apb_timer.c Normal file
View File

@ -0,0 +1,265 @@
/* mbed Microcontroller Library
* Copyright (c) 2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "cmsis.h"
#include "apb_timer.h"
/* Timer Private Data */
typedef struct {
/* Timer Definition */
CMSDK_TIMER_TypeDef *timerN;
/* Timer IRQn */
uint32_t timerIRQn;
/* Timer Reload Value */
uint32_t timerReload;
/* Timer state */
uint32_t state;
} apb_timer_t;
/* Timer state definitions */
#define TIMER_INITIALIZED (1)
#define TIMER_ENABLED (1 << 1)
/*
* This Timer is written for MBED OS and keeps count
* of the ticks. All the elaboration logic is demanded
* to the upper layers.
*/
#define TIMER_MAX_VALUE 0xFFFFFFFF
#define TIMER_TICKS_US (SystemCoreClock/1000000)
/* Timers Array */
static apb_timer_t Timers[NUM_TIMERS];
void Timer_Index_Init(uint32_t timer, uint32_t reload,
CMSDK_TIMER_TypeDef *TimerN, uint32_t IRQn)
{
Timers[timer].timerN = TimerN;
Timers[timer].timerIRQn = IRQn;
Timers[timer].timerReload = reload;
Timers[timer].state = TIMER_INITIALIZED;
}
/*
* Timer_Initialize(): Initializes an hardware timer
* timer: timer to be Initialized
* time_us: timer reload value in us - 0 to reload to timer max value
* time_us = tick_value / TIMER_TICKS_US
*/
#define TIMER_INIT(index, reload) Timer_Index_Init(index, reload, CMSDK_TIMER##index, TIMER##index##_IRQn)
void Timer_Initialize(uint32_t timer, uint32_t time_us)
{
uint32_t reload = 0;
if (timer < NUM_TIMERS) {
if (time_us == 0) {
reload = TIMER_MAX_VALUE;
} else {
reload = (time_us) * TIMER_TICKS_US;
}
switch (timer) {
case 0:
TIMER_INIT(0, reload);
break;
case 1:
TIMER_INIT(1, reload);
break;
default:
break;
}
}
}
/*
* Timer_Enable(): Enables a hardware timer
* timer: timer to be enabled
*/
void Timer_Enable(uint32_t timer)
{
/* The timer has to be contained in a valid range */
if (timer < NUM_TIMERS) {
/* Timer has to be already initialized */
if (Timers[timer].state == TIMER_INITIALIZED) {
/* Disable Timer */
(Timers[timer].timerN)->CTRL = 0x0;
/* Reload Value */
(Timers[timer].timerN)->RELOAD = Timers[timer].timerReload;
/* Enable Interrupt */
(Timers[timer].timerN)->CTRL = CMSDK_TIMER_CTRL_IRQEN_Msk;
/* Enable Counter */
(Timers[timer].timerN)->CTRL |= CMSDK_TIMER_CTRL_EN_Msk;
/* Change timer state */
Timers[timer].state |= TIMER_ENABLED;
}
}
}
/*
* Timer_Disable(): Disables a hardware timer
* timer: timer to be disabled
*/
void Timer_Disable(uint32_t timer)
{
/* The timer has to be contained in a valid range */
if (timer < NUM_TIMERS) {
/* Timer has to be already initialized and enabled */
if (Timers[timer].state == (TIMER_INITIALIZED | TIMER_ENABLED)) {
/* Disable Timer */
(Timers[timer].timerN)->CTRL = 0x0;
/* Change timer state */
Timers[timer].state = TIMER_INITIALIZED;
}
}
}
/*
* Timer_isEnabled(): verifies if a timer is enabled
* timer: timer to be verified
* @return: 0 disabled - 1 enabled
*/
uint32_t Timer_isEnabled(uint32_t timer)
{
/* The timer has to be contained in a valid range */
if (timer < NUM_TIMERS) {
/* Timer has to be already initialized and enabled */
if (Timers[timer].state == (TIMER_INITIALIZED | TIMER_ENABLED)) {
return 1;
}
}
return 0;
}
/*
* Timer_Read(): provides timer VALUE
* timer: timer to be read
* @return: timer VALUE us
*/
uint32_t Timer_Read(uint32_t timer)
{
uint32_t return_value = 0;
/* Verify if the Timer is enabled */
if (Timer_isEnabled(timer) == 1) {
return_value = (Timers[timer].timerReload
- (Timers[timer].timerN)->VALUE) / TIMER_TICKS_US;
}
return return_value;
}
/*
* Timer_SetInterrupt(): sets timer Interrupt
* timer: timer on which interrupt is set
* time_us: reloading time in us
*/
void Timer_SetInterrupt(uint32_t timer, uint32_t time_us)
{
uint32_t load_time_us = 0;
/* Verify if the Timer is enabled */
if (Timer_isEnabled(timer) == 1) {
/* Disable Timer */
Timer_Disable(timer);
/* Enable Interrupt */
(Timers[timer].timerN)->CTRL = CMSDK_TIMER_CTRL_IRQEN_Msk;
/* Check time us condition */
if (time_us == TIMER_DEFAULT_RELOAD) {
load_time_us = TIMER_MAX_VALUE;
} else {
load_time_us = time_us * TIMER_TICKS_US;
}
/* Initialize Timer Value */
Timers[timer].timerReload = load_time_us;
(Timers[timer].timerN)->RELOAD = Timers[timer].timerReload;
(Timers[timer].timerN)->VALUE = Timers[timer].timerReload;
/* Enable Counter */
(Timers[timer].timerN)->CTRL |= CMSDK_TIMER_CTRL_EN_Msk;
/* Change timer state */
Timers[timer].state |= TIMER_ENABLED;
}
}
/*
* Timer_DisableInterrupt(): disables timer interrupt
* timer: timer on which interrupt is disabled
*/
void Timer_DisableInterrupt(uint32_t timer)
{
/* Verify if the Timer is enabled */
if (Timer_isEnabled(timer) == 1) {
/* Disable Interrupt */
(Timers[timer].timerN)->CTRL &= CMSDK_TIMER_CTRL_EN_Msk;
}
}
/*
* Timer_ClearInterrupt(): clear timer interrupt
* timer: timer on which interrupt needs to be cleared
*/
void Timer_ClearInterrupt(uint32_t timer)
{
/* Verify if the Timer is enabled */
if (Timer_isEnabled(timer) == 1) {
/* Clear Interrupt */
(Timers[timer].timerN)->INTCLEAR = CMSDK_TIMER_INTCLEAR_Msk;
}
}
/*
* Timer_GetIRQn(): returns IRQn of a Timer
* timer: timer on which IRQn is defined - 0 if it is not defined
*/
uint32_t Timer_GetIRQn(uint32_t timer)
{
/* Verify if the Timer is enabled */
if (Timer_isEnabled(timer) == 1) {
return Timers[timer].timerIRQn;
}
return 0;
}
/*
* Timer_GetTicksUS(): returns the number of Ticks per us
* timer: timer associated with the Ticks per us
* @return: Ticks per us - 0 if the timer is disables
*/
uint32_t Timer_GetTicksUS(uint32_t timer)
{
/* Verify if the Timer is enabled */
if (Timer_isEnabled(timer) == 1) {
return TIMER_TICKS_US;
}
return 0;
}
/*
* Timer_GetReloadValue(): returns the load value of the selected
* timer.
* timer: timer associated with the Ticks per us
* @return: reload value of the selected singletimer
*/
uint32_t Timer_GetReloadValue(uint32_t timer)
{
/* Verify if the Timer is enabled */
if (Timer_isEnabled(timer) == 1) {
if (timer == TIMER1) {
return Timers[timer].timerReload / TIMER_TICKS_US;
} else {
return Timers[timer].timerReload / TIMER_TICKS_US;
}
}
return 0;
}

111
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/apb_timer.h Normal file
View File

@ -0,0 +1,111 @@
/* mbed Microcontroller Library
* Copyright (c) 2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* This file is derivative of apb_timer.h from BEETLE */
#ifndef _APB_TIMER_DRV_H
#define _APB_TIMER_DRV_H
#ifdef __cplusplus
extern "C" {
#endif
/* Supported Number of Timers */
#define NUM_TIMERS 2
#define TIMER0 0
#define TIMER1 1
/* Default reload */
#define TIMER_DEFAULT_RELOAD 0xFFFFFFFF
/*
* Timer_Initialize(): Initializes an hardware timer
* timer: timer to be Initialized
* time_us: timer reload value in us - 0 to reload to timer max value
* time_us = tick_value / TIMER_TICK_US
*/
void Timer_Initialize(uint32_t timer, uint32_t time_us);
/*
* Timer_Enable(): Enables an hardware timer
* timer: timer to be enabled
*/
void Timer_Enable(uint32_t timer);
/*
* Timer_Disable(): Disables an hardware timer
* timer: timer to be disabled
*/
void Timer_Disable(uint32_t timer);
/*
* Timer_isEnabled(): verifies if a timer is enabled
* timer: timer to be verified
* @return: 0 disabled - 1 enabled
*/
uint32_t Timer_isEnabled(uint32_t timer);
/*
* Timer_Read(): provides timer VALUE
* timer: timer to be read
* @return: timer VALUE
*/
uint32_t Timer_Read(uint32_t timer);
/*
* Timer_SetInterrupt(): sets timer Interrupt
* timer: timer on which interrupt is set
* time_us: reloading time in us
*/
void Timer_SetInterrupt(uint32_t timer, uint32_t time_us);
/*
* Timer_DisableInterrupt(): disables timer interrupt
* timer: timer on which interrupt is disabled
*/
void Timer_DisableInterrupt(uint32_t timer);
/*
* Timer_ClearInterrupt(): clear timer interrupt
* timer: timer on which interrupt needs to be cleared
*/
void Timer_ClearInterrupt(uint32_t timer);
/*
* Timer_GetIRQn(): returns IRQn of a Timer
* timer: timer on which IRQn is defined - 0 if it is not defined
*/
uint32_t Timer_GetIRQn(uint32_t timer);
/*
* Timer_GetTicksUS(): returns the number of Ticks per us
* timer: timer associated with the Ticks per us
* @return: Ticks per us - 0 if the timer is disables
*/
uint32_t Timer_GetTicksUS(uint32_t timer);
/*
* Timer_GetReloadValue(): returns the load value of the selected
* timer.
* timer: timer associated with the Ticks per us
* @return: reload value of the selected singletimer
*/
uint32_t Timer_GetReloadValue(uint32_t timer);
#ifdef __cplusplus
}
#endif
#endif /* _APB_TIMER_DRV_H */

31
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/cmsis.h Normal file
View File

@ -0,0 +1,31 @@
/* mbed Microcontroller Library
* Copyright (c) 2015-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* A generic CMSIS include header, pulling in CM3DS and MPS2 specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
/* CM3DS Core */
#include "CMSDK_CM3DS.h"
/* MPS2 CMSIS Library */
#include "SMM_MPS2.h"
/* NVIC Driver */
#include "cmsis_nvic.h"
/* APB Timer */
#include "apb_timer.h"
#endif /* MBED_CMSIS_H */

25
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/cmsis_nvic.h Normal file
View File

@ -0,0 +1,25 @@
/* mbed Microcontroller Library
* Copyright (c) 2015-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* CMSIS-style functionality to support dynamic vectors
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 48)
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 /* Location of vectors in RAM */
#endif /* MBED_CMSIS_NVIC_H */

35
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/peripherallink.h Normal file
View File

@ -0,0 +1,35 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* This file is derivative from the MPS2 Selftest implementation
* MPS2 Selftest: https://silver.arm.com/browse/VEI10 ->
* \ISCM-1-0\AN491\software\Selftest\v2m_mps2\peripherallink.h
*
*******************************************************************************
* Name: peripherallink.h
* Purpose: Include the correct device header file
*******************************************************************************/
#ifndef __DEVICE_H
#define __DEVICE_H
#if defined CMSDK_CM3DS
#include "CMSDK_CM3DS.h" /* device specific header file */
#else
#warning "no appropriate header file found!"
#endif
#endif /* __DEVICE_H */

104
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/system_CMSDK_CM3DS.c Normal file
View File

@ -0,0 +1,104 @@
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* This file is derivative of CMSIS V5.00 system_ARMCM3.c
*/
#include "cmsis.h"
/*----------------------------------------------------------------------------
* Define clocks
*----------------------------------------------------------------------------*/
#define __XTAL (48000000UL) /* Oscillator frequency */
#define __SYSTEM_CLOCK (__XTAL / 2)
/*----------------------------------------------------------------------------
* Clock Variable definitions
*----------------------------------------------------------------------------*/
/* !< System Clock Frequency (Core Clock) */
uint32_t SystemCoreClock = __SYSTEM_CLOCK;
/* APB System Core Clocks */
#define SYSTEM_CORE_TIMER0 (1 << 0)
#define SYSTEM_CORE_TIMER1 (1 << 1)
#define SYSTEM_CORE_DUALTIMER0 (1 << 2)
#define SYSTEM_CORE_UART0 (1 << 4)
#define SYSTEM_CORE_UART1 (1 << 5)
#define SYSTEM_CORE_I2C0 (1 << 7)
#define SYSTEM_CORE_WDOG (1 << 8)
#define SYSTEM_CORE_QSPI (1 << 11)
#define SYSTEM_CORE_SPI0 (1 << 12)
#define SYSTEM_CORE_SPI1 (1 << 13)
#define SYSTEM_CORE_I2C1 (1 << 14)
#define SYSTEM_CORE_TRNG (1 << 15) /* TRNG can not be a wakeup source */
/*----------------------------------------------------------------------------
* Clock functions
*----------------------------------------------------------------------------*/
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = __SYSTEM_CLOCK;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = __SYSTEM_CLOCK;
// Enable AHB and APB clock
/* GPIO */
CMSDK_SYSCON->AHBCLKCFG0SET = 0xF;
/*
* Activate clock for: I2C1, SPI1, SPIO, QUADSPI, WDOG,
* I2C0, UART0, UART1, TIMER0, TIMER1, DUAL TIMER, TRNG
*/
CMSDK_SYSCON->APBCLKCFG0SET = SYSTEM_CORE_TIMER0
| SYSTEM_CORE_TIMER1
| SYSTEM_CORE_DUALTIMER0
| SYSTEM_CORE_UART0
| SYSTEM_CORE_UART1
| SYSTEM_CORE_I2C0
| SYSTEM_CORE_WDOG
| SYSTEM_CORE_QSPI
| SYSTEM_CORE_SPI0
| SYSTEM_CORE_SPI1
| SYSTEM_CORE_I2C1
| SYSTEM_CORE_TRNG;
}

56
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/system_CMSDK_CM3DS.h Normal file
View File

@ -0,0 +1,56 @@
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* This file is derivative of CMSIS V5.00 system_ARMCM3.h
*/
#ifndef SYSTEM_CMSDK_CM3DS_H
#define SYSTEM_CMSDK_CM3DS_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_CMSDK_CM3DS_H */

85
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/ethernet_api.c Normal file
View File

@ -0,0 +1,85 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <string.h>
#include "ethernet_api.h"
#include "cmsis.h"
#include "mbed_interface.h"
#include "mbed_toolchain.h"
#include "mbed_error.h"
#include "mbed_wait_api.h"
#include "smsc9220_eth.h"
/*----------------------------------------------------------------------------
Ethernet Device initialize
*----------------------------------------------------------------------------*/
int ethernet_init()
{
return smsc9220_init();
}
/*----------------------------------------------------------------------------
Ethernet Device Uninitialize
*----------------------------------------------------------------------------*/
void ethernet_free()
{
/* Uninitialize function is not implemented in Ethernet driver. */
}
int ethernet_write(const char *data, int size)
{
/* smsc9220 cannot provide the functionality of writing into the tx buffer */
/* by chunks, without knowing the full size of the packet in the beginning */
return 0;
}
int ethernet_send()
{
/* smsc9220 cannot provide the functionality of writing into the tx buffer */
/* by chunks, without knowing the full size of the packet in the beginning */
return 0;
}
int ethernet_receive()
{
return smsc9220_peek_next_packet_size();
}
/* Read from an recevied ethernet packet.*/
/* After receive returnd a number bigger than 0 it is*/
/* possible to read bytes from this packet.*/
/* Read will write up to size bytes into data.*/
/* It is possible to use read multible times.*/
/* Each time read will start reading after the last read byte before. */
int ethernet_read(char *data, int dlen)
{
return smsc9220_receive_by_chunks(data, dlen);
}
void ethernet_address(char *mac)
{
smsc9220_read_mac_address(mac);
}
int ethernet_link(void)
{
return 0;
}
void ethernet_set_link(int speed, int duplex)
{
smsc9220_establish_link();
}

189
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/gpio_api.c Normal file
View File

@ -0,0 +1,189 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "gpio_api.h"
#include "pinmap.h"
#define GPIO_NUM 4
CMSDK_GPIO_TypeDef* GPIO_MAP[GPIO_NUM] = {
CMSDK_GPIO0,
CMSDK_GPIO1,
CMSDK_GPIO2,
CMSDK_GPIO3
};
#define RESERVED_MISC_PIN 7
/* \brief Gets the FPGA MISC (Miscellaneous control) bit position for the given
* pin name
*
* FPGA MISC bit mapping:
* [31:7] Reserved
* [6] CLCD_BL_CTRL
* [5] CLCD_RD
* [4] CLCD_RS
* [3] CLCD_RESET
* [2] Reserved
* [1] SPI_nSS
* [0] CLCD_CS
*
* \param[in] pin MISC pin name
*
* \return FPGA MISC bit position
*/
static uint8_t get_fpga_misc_pin_pos(PinName pin)
{
uint8_t pin_position = RESERVED_MISC_PIN;
if (pin == SPI_SCLK) {
pin_position = 0;
} else if (pin == CLCD_SSEL) {
pin_position = 1;
} else if (pin == CLCD_RESET) {
pin_position = 3;
} else if (pin == CLCD_RS) {
pin_position = 4;
} else if (pin == CLCD_RD) {
pin_position = 5;
} else if (pin == CLCD_BL_CTRL){
pin_position = 6;
}
return pin_position;
}
uint32_t gpio_set(PinName pin)
{
/* TODO */
return 1;
}
void gpio_init(gpio_t *obj, PinName pin)
{
uint8_t pin_position = 0;
if (pin == NC) {
return;
}
if(pin <= 15){
pin_position = pin;
obj->reg_data = &CMSDK_GPIO0->DATAOUT;
obj->reg_in = &CMSDK_GPIO0->DATA;
obj->reg_dir = &CMSDK_GPIO0->OUTENABLESET;
obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR;
} else if (pin >= 16 && pin <= 31) {
pin_position = (pin - 16);
obj->reg_data = &CMSDK_GPIO1->DATAOUT;
obj->reg_in = &CMSDK_GPIO1->DATA;
obj->reg_dir = &CMSDK_GPIO1->OUTENABLESET;
obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR;
} else if (pin >= 32 && pin <= 47) {
pin_position = (pin - 32);
obj->reg_data = &CMSDK_GPIO2->DATAOUT;
obj->reg_in = &CMSDK_GPIO2->DATA;
obj->reg_dir = &CMSDK_GPIO2->OUTENABLESET;
obj->reg_dirclr = &CMSDK_GPIO2->OUTENABLECLR;
} else if (pin >= 48 && pin <= 51) {
pin_position = (pin - 48 );
obj->reg_data = &CMSDK_GPIO3->DATAOUT;
obj->reg_in = &CMSDK_GPIO3->DATA;
obj->reg_dir = &CMSDK_GPIO3->OUTENABLESET;
obj->reg_dirclr = &CMSDK_GPIO3->OUTENABLECLR;
} else if (pin == 100 || pin == 101) {
/* User LEDs */
pin_position = (pin - 100);
obj->reg_data = &MPS2_FPGAIO->LED;
obj->reg_in = &MPS2_FPGAIO->LED;
obj->reg_dir = NULL;
obj->reg_dirclr = NULL;
} else if (pin == 110 || pin == 111) {
/* User buttons */
pin_position = pin-110;
obj->reg_data = &MPS2_FPGAIO->BUTTON;
obj->reg_in = &MPS2_FPGAIO->BUTTON;
obj->reg_dir = NULL;
obj->reg_dirclr = NULL;
} else if (pin >= 200 && pin <= 207) {
/* MCC LEDs */
pin_position = pin-200;
obj->reg_data = &MPS2_SCC->LEDS;
obj->reg_in = &MPS2_SCC->LEDS;
obj->reg_dir = NULL;
obj->reg_dirclr = NULL;
} else if (pin >= 210 && pin <= 217) {
/* MCC switches */
pin_position = (pin - 210);
obj->reg_in = &MPS2_SCC->SWITCHES;
obj->reg_data = NULL;
obj->reg_dir = NULL;
obj->reg_dirclr = NULL;
} else if (pin == SHIELD_0_SPI_nCS) {
pin_position = 8;
GPIO_MAP[CMSDK_GPIO_SH0_CS_SPI_GPIO_NUM]->ALTFUNCSET |=
(1 << CMSDK_GPIO_ALTFUNC_SH0_CS_SPI_SET);
} else if (pin == SHIELD_1_SPI_nCS) {
pin_position = 9;
GPIO_MAP[CMSDK_GPIO_SH1_CS_SPI_GPIO_NUM]->ALTFUNCSET |=
(1 << CMSDK_GPIO_ALTFUNC_SH1_CS_SPI_SET);
} else if (pin == ADC_SSEL) {
pin_position = 7;
GPIO_MAP[CMSDK_GPIO_ADC_CS_SPI_GPIO_NUM]->ALTFUNCSET |=
(1 << CMSDK_GPIO_ALTFUNC_ADC_CS_SPI_SET);
} else {
pin_position = get_fpga_misc_pin_pos(pin);
if (pin_position != RESERVED_MISC_PIN) {
obj->reg_data = &MPS2_FPGAIO->MISC;
} else {
pin_position = 0;
}
}
obj->pin = pin;
obj->mask = (0x1 << pin_position);
obj->pin_number = pin;
}
void gpio_mode(gpio_t *obj, PinMode mode)
{
pin_mode(obj->pin, mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction)
{
if (obj->pin >= EXP0 && obj->pin <= EXP51) {
switch (direction) {
case PIN_INPUT :
*obj->reg_dirclr = obj->mask;
break;
case PIN_OUTPUT:
*obj->reg_dir |= obj->mask;
break;
}
}
}
int gpio_is_connected(const gpio_t *obj)
{
if (obj->pin != (PinName)NC) {
return 1;
}
return 0;
}

438
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/gpio_irq_api.c Normal file
View File

@ -0,0 +1,438 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "cmsis.h"
#include "gpio_irq_api.h"
#include "mbed_error.h"
#define CHANNEL_NUM 32
#define CMSDK_GPIO_0 CMSDK_GPIO0
#define CMSDK_GPIO_1 CMSDK_GPIO1
#define PININT_IRQ 0
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler irq_handler;
static inline void handle_interrupt_in(uint32_t channel)
{
uint32_t ch_bit = (1 << channel);
// Return immediately if:
// * The interrupt was already served
// * There is no user handler
// * It is a level interrupt, not an edge interrupt
if (ch_bit < 16) {
if (((CMSDK_GPIO_0->INTSTATUS) == 0)
|| (channel_ids[channel] == 0)
|| ((CMSDK_GPIO_0->INTTYPESET) == 0) ) {
return;
}
if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE);
CMSDK_GPIO_0->INTPOLSET = ch_bit;
}
if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_FALL);
}
CMSDK_GPIO_0->INTCLEAR = ch_bit;
} else {
if (((CMSDK_GPIO_1->INTSTATUS) == 0)
|| (channel_ids[channel] == 0)
|| ((CMSDK_GPIO_1->INTTYPESET) == 0)) {
return;
}
if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE);
CMSDK_GPIO_1->INTPOLSET = ch_bit;
}
if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_FALL);
}
CMSDK_GPIO_1->INTCLEAR = ch_bit;
}
}
void gpio0_irq0(void)
{
handle_interrupt_in(0);
}
void gpio0_irq1(void)
{
handle_interrupt_in(1);
}
void gpio0_irq2(void)
{
handle_interrupt_in(2);
}
void gpio0_irq3(void)
{
handle_interrupt_in(3);
}
void gpio0_irq4(void)
{
handle_interrupt_in(4);
}
void gpio0_irq5(void)
{
handle_interrupt_in(5);
}
void gpio0_irq6(void)
{
handle_interrupt_in(6);
}
void gpio0_irq7(void)
{
handle_interrupt_in(7);
}
void gpio0_irq8(void)
{
handle_interrupt_in(8);
}
void gpio0_irq9(void)
{
handle_interrupt_in(9);
}
void gpio0_irq10(void)
{
handle_interrupt_in(10);
}
void gpio0_irq11(void)
{
handle_interrupt_in(11);
}
void gpio0_irq12(void)
{
handle_interrupt_in(12);
}
void gpio0_irq13(void)
{
handle_interrupt_in(13);
}
void gpio0_irq14(void)
{
handle_interrupt_in(14);
}
void gpio0_irq15(void)
{
handle_interrupt_in(15);
}
void gpio1_irq0(void)
{
handle_interrupt_in(16);
}
void gpio1_irq1(void)
{
handle_interrupt_in(17);
}
void gpio1_irq2(void)
{
handle_interrupt_in(18);
}
void gpio1_irq3(void)
{
handle_interrupt_in(19);
}
void gpio1_irq4(void)
{
handle_interrupt_in(20);
}
void gpio1_irq5(void)
{
handle_interrupt_in(21);
}
void gpio1_irq6(void)
{
handle_interrupt_in(22);
}
void gpio1_irq7(void)
{
handle_interrupt_in(23);
}
void gpio1_irq8(void)
{
handle_interrupt_in(24);
}
void gpio1_irq9(void)
{
handle_interrupt_in(25);
}
void gpio1_irq10(void)
{
handle_interrupt_in(26);
}
void gpio1_irq11(void)
{
handle_interrupt_in(27);
}
void gpio1_irq12(void)
{
handle_interrupt_in(28);
}
void gpio1_irq13(void)
{
handle_interrupt_in(29);
}
void gpio1_irq14(void)
{
handle_interrupt_in(30);
}
void gpio1_irq15(void)
{
handle_interrupt_in(31);
}
int gpio_irq_init(gpio_irq_t *obj, PinName pin,
gpio_irq_handler handler, uint32_t id)
{
int found_free_channel = 0;
int i = 0;
if (pin == NC) {
return -1;
}
irq_handler = handler;
for (i=0; i<CHANNEL_NUM; i++) {
if (channel_ids[i] == 0) {
channel_ids[i] = id;
obj->ch = i;
found_free_channel = 1;
break;
}
}
if (!found_free_channel) {
return -1;
}
/* To select a pin for any of the eight pin interrupts, write the pin number
* as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
* @see: mbed_capi/PinNames.h
*/
if (pin <16) {
CMSDK_GPIO_0->INTENSET |= (0x1 << pin);
}
if (pin >= 16) {
CMSDK_GPIO_1->INTENSET |= (0x1 << pin);
}
void (*channels_irq)(void) = NULL;
switch (obj->ch) {
case 0:
channels_irq = &gpio0_irq0;
break;
case 1:
channels_irq = &gpio0_irq1;
break;
case 2:
channels_irq = &gpio0_irq2;
break;
case 3:
channels_irq = &gpio0_irq3;
break;
case 4:
channels_irq = &gpio0_irq4;
break;
case 5:
channels_irq = &gpio0_irq5;
break;
case 6:
channels_irq = &gpio0_irq6;
break;
case 7:
channels_irq = &gpio0_irq7;
break;
case 8:
channels_irq = &gpio0_irq8;
break;
case 9:
channels_irq = &gpio0_irq9;
break;
case 10:
channels_irq = &gpio0_irq10;
break;
case 11:
channels_irq = &gpio0_irq11;
break;
case 12:
channels_irq = &gpio0_irq12;
break;
case 13:
channels_irq = &gpio0_irq13;
break;
case 14:
channels_irq = &gpio0_irq14;
break;
case 15:
channels_irq = &gpio0_irq15;
break;
case 16:
channels_irq = &gpio1_irq0;
break;
case 17:
channels_irq = &gpio1_irq1;
break;
case 18:
channels_irq = &gpio1_irq2;
break;
case 19:
channels_irq = &gpio1_irq3;
break;
case 20:
channels_irq = &gpio1_irq4;
break;
case 21:
channels_irq = &gpio1_irq5;
break;
case 22:
channels_irq = &gpio1_irq6;
break;
case 23:
channels_irq = &gpio1_irq7;
break;
case 24:
channels_irq = &gpio1_irq8;
break;
case 25:
channels_irq = &gpio1_irq9;
break;
case 26:
channels_irq = &gpio1_irq10;
break;
case 27:
channels_irq = &gpio1_irq11;
break;
case 28:
channels_irq = &gpio1_irq12;
break;
case 29:
channels_irq = &gpio1_irq13;
break;
case 30:
channels_irq = &gpio1_irq14;
break;
case 31:
channels_irq = &gpio1_irq15;
break;
}
NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
return 0;
}
void gpio_irq_free(gpio_irq_t *obj)
{
channel_ids[obj->ch] = 0;
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
{
unsigned int ch_bit = (1 << obj->ch);
if (obj->ch <16) {
/* Clear interrupt */
if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit)) {
CMSDK_GPIO_0->INTCLEAR = ch_bit;
}
CMSDK_GPIO_0->INTTYPESET &= ch_bit;
/* Set interrupt */
if (event == IRQ_RISE) {
CMSDK_GPIO_0->INTPOLSET |= ch_bit;
if (enable) {
CMSDK_GPIO_0->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_0->INTENCLR |= ch_bit;
}
} else {
CMSDK_GPIO_0->INTPOLCLR |= ch_bit;
if (enable) {
CMSDK_GPIO_0->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_0->INTENCLR |= ch_bit;
}
}
} else {
/* Clear interrupt */
if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit)) {
CMSDK_GPIO_1->INTCLEAR = ch_bit;
}
CMSDK_GPIO_1->INTTYPESET &= ch_bit;
/* Set interrupt */
if (event == IRQ_RISE) {
CMSDK_GPIO_1->INTPOLSET |= ch_bit;
if (enable) {
CMSDK_GPIO_1->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_1->INTENCLR |= ch_bit;
}
} else {
CMSDK_GPIO_1->INTPOLCLR |= ch_bit;
if (enable) {
CMSDK_GPIO_1->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_1->INTENCLR |= ch_bit;
}
}
}
}
void gpio_irq_enable(gpio_irq_t *obj)
{
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
}
void gpio_irq_disable(gpio_irq_t *obj)
{
NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
}

56
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/gpio_object.h Normal file
View File

@ -0,0 +1,56 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pin;
uint32_t mask;
uint32_t pin_number;
__IO uint32_t *reg_dir;
__IO uint32_t *reg_dirclr;
__IO uint32_t *reg_data;
__I uint32_t *reg_in;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value)
{
if (value) {
*obj->reg_data |= (obj->mask);
} else {
*obj->reg_data &= ~(obj->mask);
}
}
static inline int gpio_read(gpio_t *obj)
{
return ((*obj->reg_in & obj->mask) ? 1 : 0);
}
#ifdef __cplusplus
}
#endif
#endif

24
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/mbed_overrides.c Normal file
View File

@ -0,0 +1,24 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "smsc9220_eth.h"
/* Provide ethernet devices with a semi-unique MAC address from the UUID */
void mbed_mac_address(char *mac)
{
smsc9220_read_mac_address(mac);
}

81
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/objects.h Normal file
View File

@ -0,0 +1,81 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
struct gpio_irq_s {
uint32_t ch;
};
struct port_s {
__IO uint32_t *reg_dir;
__IO uint32_t *reg_dirclr;
__IO uint32_t *reg_out;
__IO uint32_t *reg_in;
PortName port;
uint32_t mask;
};
struct serial_s {
CMSDK_UART_TypeDef *uart;
int index;
};
struct i2c_s {
MPS2_I2C_TypeDef *i2c;
};
struct tsc_s {
MPS2_I2C_TypeDef *tsc;
};
struct audio_s {
MPS2_I2S_TypeDef *audio_I2S;
MPS2_I2C_TypeDef *audio_I2C;
};
struct spi_s {
MPS2_SSP_TypeDef *spi;
};
struct clcd_s {
MPS2_SSP_TypeDef *clcd;
};
struct analogin_s {
ADCName adc;
MPS2_SSP_TypeDef *adc_spi;
PinName pin;
uint32_t pin_number;
__IO uint32_t address;
};
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

33
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/pinmap.c Normal file
View File

@ -0,0 +1,33 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "pinmap.h"
#include "mbed_error.h"
void pin_function(PinName pin, int function)
{
MBED_ASSERT(pin != (PinName)NC);
/* TODO */
}
void pin_mode(PinName pin, PinMode mode)
{
MBED_ASSERT(pin != (PinName)NC);
/* Pin modes configuration is not supported */
}

79
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/port_api.c Normal file
View File

@ -0,0 +1,79 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "port_api.h"
#include "pinmap.h"
#include "gpio_api.h"
PinName port_pin(PortName port, int pin_n)
{
return (PinName)((port << PORT_SHIFT) | pin_n);
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
{
obj->port = port;
obj->mask = mask;
CMSDK_GPIO_TypeDef *port_reg = (CMSDK_GPIO_TypeDef *)(CMSDK_GPIO0_BASE
+ ((int)port * 0x10));
obj->reg_in = &port_reg->DATAOUT;
obj->reg_dir = &port_reg->OUTENABLESET;
obj->reg_dirclr = &port_reg->OUTENABLECLR;
uint32_t i;
// The function is set per pin: reuse gpio logic
for (i=0; i<16; i++) {
if (obj->mask & (1<<i)) {
gpio_set(port_pin(obj->port, i));
}
}
port_dir(obj, dir);
}
void port_mode(port_t *obj, PinMode mode)
{
uint32_t i;
// The mode is set per pin: reuse pinmap logic
for (i=0; i<32; i++) {
if (obj->mask & (1<<i)) {
pin_mode(port_pin(obj->port, i), mode);
}
}
}
void port_dir(port_t *obj, PinDirection dir)
{
switch (dir) {
case PIN_INPUT:
*obj->reg_dir &= ~obj->mask;
break;
case PIN_OUTPUT:
*obj->reg_dir |= obj->mask;
break;
}
}
void port_write(port_t *obj, int value)
{
*obj->reg_in = value;
}
int port_read(port_t *obj)
{
return (*obj->reg_in);
}

78
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/rtc_api.c Normal file
View File

@ -0,0 +1,78 @@
/*
* Copyright (c) 2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "rtc_api.h"
#include "device.h"
#include "cmsis.h"
/**
* \defgroup hal_rtc RTC hal functions
* @{
*/
/**
* \brief Initialize the RTC peripheral.
* The RTC starts counting from 0x0 at reset and increments
* with a frequency of 1hz (clock source: CLK1HZ).
* The current value can be read through the DATA register
*/
void rtc_init(void)
{
CMSDK_RTC->RTCCR |= (1 << CMSDK_RTC_Enable_Pos);
}
/**
* \brief Deinitialize the RTC peripheral
* According to DDI0224B_RTC_PL031_TRM.pdf chapter 3.3.4 there is
* no reason to implement.
*/
void rtc_free(void)
{
/* Not supported */
}
/**
* \brief Get the RTC enable status
*
* \return 0 disabled, 1 enabled
*/
int rtc_isenabled(void)
{
return (CMSDK_RTC->RTCCR & CMSDK_RTC_Enable_Msk);
}
/**
* \brief Get the current time from the RTC peripheral
*
* \return The current time in seconds
*/
time_t rtc_read(void)
{
return (time_t)CMSDK_RTC->RTCDR;
}
/**
* \brief Set the current time to the RTC peripheral, write it to LOAD register
*
* \param[in] t The current time to be set in seconds
*/
void rtc_write(time_t t)
{
CMSDK_RTC->RTCLR = (uint32_t)t;
}
/**@}*/

452
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/serial_api.c Normal file
View File

@ -0,0 +1,452 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// math.h required for floating point operations for baud rate calculation
#include <math.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "serial_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "gpio_api.h"
/******************************************************************************
* INITIALIZATION
******************************************************************************/
static const PinMap PinMap_UART_TX[] = {
{MCC_TX , UART_0, 0},
{USBTX , UART_1, 0},
{XB_TX , UART_2, 0},
{SH0_TX , UART_3, 0},
{SH1_TX , UART_4, 0},
{NC , NC , 0}
};
static const PinMap PinMap_UART_RX[] = {
{MCC_RX , UART_0, 0},
{USBRX , UART_1, 0},
{XB_RX , UART_2, 0},
{SH0_RX , UART_3, 0},
{SH1_RX , UART_4, 0},
{NC , NC , 0}
};
#define UART_NUM 5
extern CMSDK_GPIO_TypeDef* GPIO_MAP[];
static uart_irq_handler irq_handler;
int stdio_uart_inited = 0;
serial_t stdio_uart;
struct serial_global_data_s {
uint32_t serial_irq_id;
gpio_t sw_rts, sw_cts;
uint8_t count, rx_irq_set_flow, rx_irq_set_api;
};
static struct serial_global_data_s uart_data[UART_NUM];
void serial_init(serial_t *obj, PinName tx, PinName rx)
{
/* Determine the UART to use */
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
if ((int)uart == NC) {
error("Serial pinout mapping failed");
return;
}
obj->uart = (CMSDK_UART_TypeDef *)uart;
switch (uart) {
case UART_0:
/* Disable UART when changing configuration */
CMSDK_UART0->CTRL = 0;
if((int)tx != NC) {
CMSDK_UART0->CTRL |= 0x01; /* TX enable */
}
if((int)rx != NC) {
CMSDK_UART0->CTRL |= 0x02; /* RX enable */
}
break;
case UART_1:
/* Disable UART when changing configuration */
CMSDK_UART1->CTRL = 0;
if((int)tx != NC) {
CMSDK_UART1->CTRL |= 0x01; /* TX enable */
}
if((int)rx != NC) {
CMSDK_UART1->CTRL |= 0x02; /* RX enable */
}
break;
case UART_2:
/* Disable UART when changing configuration */
CMSDK_UART2->CTRL = 0x00;
if ((int)tx != NC) {
CMSDK_UART2->CTRL = 0x1; /* TX enable */
GPIO_MAP[CMSDK_GPIO_SH0_UART2_TX_GPIO_NUM]->ALTFUNCSET |=
(1<<CMSDK_GPIO_ALTFUNC_SH0_UART2_TX_SET);
}
if ((int)rx != NC) {
CMSDK_UART2->CTRL |= 0x2; /* RX enable */
GPIO_MAP[CMSDK_GPIO_SH0_UART2_RX_GPIO_NUM]->ALTFUNCSET |=
(1<<CMSDK_GPIO_ALTFUNC_SH0_UART2_RX_SET);
}
break;
case UART_3:
/* Disable UART when changing configuration */
CMSDK_UART3->CTRL = 0;
if ((int)tx != NC) {
CMSDK_UART3->CTRL = 0x1; /* TX enable */
GPIO_MAP[CMSDK_GPIO_SH1_UART3_TX_GPIO_NUM]->ALTFUNCSET |=
(1<<CMSDK_GPIO_ALTFUNC_SH1_UART3_TX_SET);
}
if((int)rx != NC)
{
CMSDK_UART3->CTRL |= 0x2; /* RX enable */
GPIO_MAP[CMSDK_GPIO_SH1_UART3_RX_GPIO_NUM]->ALTFUNCSET |=
(1<<CMSDK_GPIO_ALTFUNC_SH1_UART3_RX_SET);
}
break;
case UART_4:
/* Disable UART when changing configuration */
CMSDK_UART4->CTRL = 0x00;
if ((int)uart_tx != NC) {
CMSDK_UART4->CTRL |= 0x01; /* TX enable */
GPIO_MAP[CMSDK_GPIO_UART4_TX_GPIO_NUM]->ALTFUNCSET |=
(1<<CMSDK_GPIO_ALTFUNC_UART4_TX_SET);
}
if((int)uart_rx != NC) {
CMSDK_UART4->CTRL |= 0x02; /* RX enable */
GPIO_MAP[CMSDK_GPIO_UART4_RX_GPIO_NUM]->ALTFUNCSET |=
(1<<CMSDK_GPIO_ALTFUNC_UART4_RX_SET);
}
break;
}
/* Set default baud rate and format */
serial_baud(obj, 9600);
/* Pinout the chosen uart */
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
switch (uart) {
case UART_0:
obj->index = 0;
break;
case UART_1:
obj->index = 1;
break;
case UART_2:
obj->index = 2;
break;
case UART_3:
obj->index = 3;
break;
case UART_4:
obj->index = 4;
break;
}
/*
* The CMSDK APB UART doesn't have support for flow control.
* Ref. DDI0479C_cortex_m_system_design_kit_r1p0_trm.pdf
*/
uart_data[obj->index].sw_rts.pin = NC;
uart_data[obj->index].sw_cts.pin = NC;
if (uart == STDIO_UART) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj)
{
uart_data[obj->index].serial_irq_id = 0;
}
void serial_baud(serial_t *obj, int baudrate)
{
/*
* The MPS2 has a simple divider to control the baud rate.
* The formula is:
* Baudrate = PCLK / BAUDDIV where PCLK = SystemCoreClock and
* BAUDDIV is the desire baudrate
*
* So, if the desired baud rate is 9600 the calculation will be:
* Baudrate = SystemCoreClock / 9600;
*/
/* Check to see if minimum baud value entered */
int baudrate_div = 0;
if (baudrate == 0) {
error("Invalid baudrate value");
return;
}
baudrate_div = SystemCoreClock / baudrate;
if (baudrate >= 16) {
switch ((int)obj->uart) {
case UART_0:
CMSDK_UART0->BAUDDIV = baudrate_div;
break;
case UART_1:
CMSDK_UART1->BAUDDIV = baudrate_div;
break;
case UART_2:
CMSDK_UART2->BAUDDIV = baudrate_div;
break;
case UART_3:
CMSDK_UART3->BAUDDIV = baudrate_div;
break;
case UART_4:
CMSDK_UART4->BAUDDIV = baudrate_div;
break;
default:
error("Invalid uart object");
break;
}
} else {
error("Invalid baudrate value");
}
}
void serial_format(serial_t *obj, int data_bits,
SerialParity parity, int stop_bits)
{
/*
* The CMSDK APB UART is a simple design that supports 8-bit communication
* without parity, and is fixed at one stop bit per configuration.
* Ref. DDI0479C_cortex_m_system_design_kit_r1p0_trm.pdf
*/
error("serial format function not supported");
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
static inline void uart_irq(uint32_t intstatus, uint32_t index,
CMSDK_UART_TypeDef *puart)
{
SerialIrq irq_type;
switch (intstatus) {
case 1:
irq_type = TxIrq;
break;
case 2:
irq_type = RxIrq;
break;
default:
return;
}
if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) {
gpio_write(&uart_data[index].sw_rts, 1);
/* Disable interrupt if it wasn't enabled by the application */
if (!uart_data[index].rx_irq_set_api) {
/* Disable Rx interrupt */
puart->CTRL &= ~(CMSDK_UART_CTRL_RXIRQEN_Msk);
}
}
if (uart_data[index].serial_irq_id != 0) {
if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) {
irq_handler(uart_data[index].serial_irq_id, irq_type);
}
}
if (irq_type == TxIrq) {
/* Clear the TX interrupt Flag */
puart->INTCLEAR |= 0x01;
} else {
/* Clear the Rx interupt Flag */
puart->INTCLEAR |= 0x02;
}
}
void uart0_irq()
{
uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef*)CMSDK_UART0);
}
void uart1_irq()
{
uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef*)CMSDK_UART1);
}
void uart2_irq()
{
uart_irq(CMSDK_UART2->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef*)CMSDK_UART2);
}
void uart3_irq() {
uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef*)CMSDK_UART3);
}
void uart4_irq() {
uart_irq(CMSDK_UART4->INTSTATUS & 0x3, 4, (CMSDK_UART_TypeDef*)CMSDK_UART4);
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler = handler;
uart_data[obj->index].serial_irq_id = id;
}
static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable)
{
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
switch ((int)obj->uart) {
case UART_0:
irq_n = UART0_IRQn;
vector = (uint32_t)&uart0_irq;
break;
case UART_1:
irq_n = UART1_IRQn;
vector = (uint32_t)&uart1_irq;
break;
case UART_2:
irq_n = UART2_IRQn;
vector = (uint32_t)&uart2_irq;
break;
case UART_3:
irq_n = UART3_IRQn;
vector = (uint32_t)&uart3_irq;
break;
case UART_4:
irq_n = UART4_IRQn;
vector = (uint32_t)&uart4_irq;
break;
}
if (enable) {
if (irq == TxIrq) {
/* Set TX interrupt enable in CTRL REG */
obj->uart->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk;
} else {
/* Set Rx interrupt on in CTRL REG */
obj->uart->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk;
}
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
} else if ((irq == TxIrq) ||
(uart_data[obj->index].rx_irq_set_api
+ uart_data[obj->index].rx_irq_set_flow == 0)) {
/* Disable IRQ */
int all_disabled = 0;
SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
obj->uart->CTRL &= ~(1 << (irq + 2));
all_disabled = (obj->uart->CTRL & (1 << (other_irq + 2))) == 0;
if (all_disabled) {
NVIC_DisableIRQ(irq_n);
}
}
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
if (RxIrq == irq) {
uart_data[obj->index].rx_irq_set_api = enable;
}
serial_irq_set_internal(obj, irq, enable);
}
/******************************************************************************
* READ/WRITE
******************************************************************************/
int serial_getc(serial_t *obj)
{
while (serial_readable(obj) == 0) {
/* NOP */
}
return obj->uart->DATA;
}
void serial_putc(serial_t *obj, int c)
{
while (serial_writable(obj)) {
/* NOP */
}
obj->uart->DATA = c;
}
int serial_readable(serial_t *obj)
{
return obj->uart->STATE & 0x2;
}
int serial_writable(serial_t *obj)
{
return obj->uart->STATE & 0x1;
}
void serial_clear(serial_t *obj)
{
obj->uart->DATA = 0x00;
}
void serial_pinout_tx(PinName tx)
{
pinmap_pinout(tx, PinMap_UART_TX);
}
void serial_break_set(serial_t *obj)
{
/*
* The CMSDK APB UART doesn't support serial break.
* Ref. DDI0479C_cortex_m_system_design_kit_r1p0_trm.pdf
*/
error("serial_break_set function not supported");
}
void serial_break_clear(serial_t *obj)
{
/*
* The CMSDK APB UART doesn't support serial break.
* Ref. DDI0479C_cortex_m_system_design_kit_r1p0_trm.pdf
*/
error("serial_break_clear function not supported");
}
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
{
/*
* The CMSDK APB UART doesn't have support for flow control.
* Ref. DDI0479C_cortex_m_system_design_kit_r1p0_trm.pdf
*/
error("serial_set_flow_control function not supported");
}

363
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/spi_api.c Normal file
View File

@ -0,0 +1,363 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <math.h>
#include "spi_api.h"
#include "spi_def.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "mbed_wait_api.h"
#define SPI_PL022_MIN_SSPCPSR_VALUE 2
#define SPI_PL022_MAX_SSPCPSR_VALUE 254
#define SPI_PL022_MAX_SRC_VALUE 255
#define SPI_PL022_SSPCR0_SCR_POS 8
#define SPI_PL022_SSPCR0_SCR_MSK (0xFFul<<SPI_PL022_SSPCR0_SCR_POS)
static const PinMap PinMap_SPI_SCLK[] = {
{SPI_SCLK , SPI_0, 0},
{CLCD_SCLK , SPI_1, 0},
{ADC_SCLK , SPI_2, 0},
{SHIELD_0_SPI_SCK , SPI_3, 0},
{SHIELD_1_SPI_SCK , SPI_4, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MOSI[] = {
{SPI_MOSI, SPI_0, 0},
{CLCD_MOSI, SPI_1, 0},
{ADC_MOSI, SPI_2, 0},
{SHIELD_0_SPI_MOSI, SPI_3, 0},
{SHIELD_1_SPI_MOSI, SPI_4, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{SPI_MISO, SPI_0, 0},
{CLCD_MISO, SPI_1, 0},
{ADC_MISO, SPI_2, 0},
{SHIELD_0_SPI_MISO, SPI_3, 0},
{SHIELD_1_SPI_MISO, SPI_4, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
{SPI_SSEL, SPI_0, 0},
{CLCD_SSEL, SPI_1, 0},
{ADC_SSEL, SPI_2, 0},
{SHIELD_0_SPI_nCS, SPI_3, 0},
{SHIELD_1_SPI_nCS, SPI_4, 0},
{NC , NC , 0}
};
extern CMSDK_GPIO_TypeDef* GPIO_MAP[];
static inline int ssp_disable(spi_t *obj);
static inline int ssp_enable(spi_t *obj);
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
int altfunction[4];
/* Determine the SPI to use */
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (MPS2_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
if ((int)obj->spi == NC) {
error("SPI pinout mapping failed");
return;
}
/* Enable power and clocking */
switch ((int)obj->spi) {
case (int)SPI_0:
obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT;
obj->spi->IMSC = 0x8;
obj->spi->DMACR = 0;
obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3;
break;
case (int)SPI_1: /* Configure SSP used for LCD */
obj->spi->CR1 = 0; /* Synchronous serial port disable */
obj->spi->DMACR = 0; /* Disable FIFO DMA */
obj->spi->IMSC = 0; /* Mask all FIFO/IRQ interrupts */
obj->spi->ICR = ((1ul << 0) | /* Clear SSPRORINTR interrupt */
(1ul << 1) ); /* Clear SSPRTINTR interrupt */
obj->spi->CR0 = ((7ul << 0) | /* 8 bit data size */
(0ul << 4) | /* Motorola frame format */
(0ul << 6) | /* CPOL = 0 */
(0ul << 7) | /* CPHA = 0 */
(1ul << 8) ); /* Set serial clock rate */
obj->spi->CPSR = (2ul << 0); /* set SSP clk to 6MHz (6.6MHz max) */
obj->spi->CR1 = ((1ul << 1) | /* Synchronous serial port enable */
(0ul << 2) ); /* Device configured as master */
break;
case (int)SPI_2:
obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT;
obj->spi->IMSC = 0x8;
obj->spi->DMACR = 0;
obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3;
break;
case (int)SPI_3:
obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT;
obj->spi->IMSC = 0x8;
obj->spi->DMACR = 0;
obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3;
break;
case (int)SPI_4:
obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT;
obj->spi->IMSC = 0x8;
obj->spi->DMACR = 0;
obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3;
break;
}
if (mosi != NC) {
altfunction[0] = 1;
} else {
altfunction[0] = 0;
}
if (miso != NC) {
altfunction[1] = 1;
} else {
altfunction[1] = 0;
}
if (sclk != NC) {
altfunction[2] = 1;
} else {
altfunction[2] = 0;
}
if (ssel != NC) {
altfunction[3] = 1;
} else {
altfunction[3] = 0;
}
/* Enable alt function */
switch ((int)obj->spi) {
case (int)SPI_2: /* Shield ADC SPI */
GPIO_MAP[CMSDK_GPIO_ADC_MOSI_SPI_GPIO_NUM]->ALTFUNCSET |=
(altfunction[0]<<CMSDK_GPIO_ALTFUNC_ADC_MOSI_SPI_SET);
GPIO_MAP[CMSDK_GPIO_ADC_MISO_SPI_GPIO_NUM]->ALTFUNCSET |=
(altfunction[1]<<CMSDK_GPIO_ALTFUNC_ADC_MISO_SPI_SET);
GPIO_MAP[CMSDK_GPIO_ADC_SCK_SPI_GPIO_NUM]->ALTFUNCSET |=
(altfunction[2]<<CMSDK_GPIO_ALTFUNC_ADC_SCK_SPI_SET);
GPIO_MAP[CMSDK_GPIO_ADC_CS_SPI_GPIO_NUM]->ALTFUNCSET |=
(altfunction[3]<<CMSDK_GPIO_ALTFUNC_ADC_CS_SPI_SET);
break;
case (int)SPI_3: /* Shield 0 SPI */
GPIO_MAP[CMSDK_GPIO_SH0_MOSI_SPI_GPIO_NUM]->ALTFUNCSET |=
(altfunction[0]<<CMSDK_GPIO_ALTFUNC_SH0_MOSI_SPI_SET);
GPIO_MAP[CMSDK_GPIO_SH0_MISO_SPI_GPIO_NUM]->ALTFUNCSET |=
(altfunction[1]<<CMSDK_GPIO_ALTFUNC_SH0_MISO_SPI_SET);
GPIO_MAP[CMSDK_GPIO_SH0_SCK_SPI_GPIO_NUM]->ALTFUNCSET |=
(altfunction[2]<<CMSDK_GPIO_ALTFUNC_SH0_SCK_SPI_SET);
GPIO_MAP[CMSDK_GPIO_SH0_CS_SPI_GPIO_NUM]->ALTFUNCSET |=
(altfunction[3]<<CMSDK_GPIO_ALTFUNC_SH0_CS_SPI_SET);
break;
case (int)SPI_4: /* Shield 1 SPI */
GPIO_MAP[CMSDK_GPIO_SH1_MOSI_SPI_GPIO_NUM]->ALTFUNCSET |=
(altfunction[0]<<CMSDK_GPIO_ALTFUNC_SH1_MOSI_SPI_SET);
GPIO_MAP[CMSDK_GPIO_SH1_MISO_SPI_GPIO_NUM]->ALTFUNCSET |=
(altfunction[1]<<CMSDK_GPIO_ALTFUNC_SH1_MISO_SPI_SET);
GPIO_MAP[CMSDK_GPIO_SH1_SCK_SPI_GPIO_NUM]->ALTFUNCSET |=
(altfunction[2]<<CMSDK_GPIO_ALTFUNC_SH1_SCK_SPI_SET);
GPIO_MAP[CMSDK_GPIO_SH1_CS_SPI_GPIO_NUM]->ALTFUNCSET |=
(altfunction[3]<<CMSDK_GPIO_ALTFUNC_SH1_CS_SPI_SET);
break;
}
/* Set default format and frequency */
if (ssel == NC) {
spi_format(obj, 8, 0, 0); /* 8 bits, mode 0, master */
} else {
spi_format(obj, 8, 0, 1); /* 8 bits, mode 0, slave */
}
/* Default SPI frequency */
spi_frequency(obj, 1000000);
/* Enable the ssp channel */
ssp_enable(obj);
/* pin out the spi pins */
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
}
void spi_free(spi_t *obj)
{
error("SPI free error");
}
void spi_format(spi_t *obj, int bits, int mode, int slave)
{
ssp_disable(obj);
if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
error("SPI format error");
}
int polarity = (mode & 0x2) ? 1 : 0;
int phase = (mode & 0x1) ? 1 : 0;
// set it up
int DSS = bits - 1; /* DSS (data select size) */
int SPO = (polarity) ? 1 : 0; /* SPO - clock out polarity */
int SPH = (phase) ? 1 : 0; /* SPH - clock out phase */
int FRF = 0; /* FRF (frame format) = SPI */
uint32_t tmp = obj->spi->CR0;
tmp &= ~(0xFFFF);
tmp |= DSS << 0
| FRF << 4
| SPO << 6
| SPH << 7;
obj->spi->CR0 = tmp;
tmp = obj->spi->CR1;
tmp &= ~(0xD);
tmp |= 0 << 0 /* LBM - loop back mode - off */
| ((slave) ? 1 : 0) << 2 /* MS - master slave mode, 1 = slave */
| 0 << 3; /* SOD - slave output disable - na */
obj->spi->CR1 = tmp;
ssp_enable(obj);
}
void spi_frequency(spi_t *obj, int hz)
{
uint32_t clkps_dvsr, scr;
for(clkps_dvsr = SPI_PL022_MIN_SSPCPSR_VALUE;
clkps_dvsr <= SPI_PL022_MAX_SSPCPSR_VALUE; clkps_dvsr += 2) {
/* Calculate clock rate based on the new clock prescale divisor */
scr = (SystemCoreClock / (clkps_dvsr * hz)) - 1;
/* Checks if it can be supported by the divider */
if (scr <= SPI_PL022_MAX_SRC_VALUE) {
ssp_disable(obj);
obj->spi->CPSR = clkps_dvsr;
obj->spi->CR0 &= ~SPI_PL022_SSPCR0_SCR_MSK;
obj->spi->CR0 |= (scr << SPI_PL022_SSPCR0_SCR_POS);
ssp_enable(obj);
return;
}
}
error("Couldn't setup requested SPI frequency");
}
static inline int ssp_disable(spi_t *obj)
{
return obj->spi->CR1 &= ~(1 << 1);
}
static inline int ssp_enable(spi_t *obj)
{
return obj->spi->CR1 |= SSP_CR1_SSE_Msk;
}
static inline int ssp_readable(spi_t *obj)
{
return obj->spi->SR & (1 << 2);
}
static inline int ssp_writeable(spi_t *obj)
{
return obj->spi->SR & SSP_SR_BSY_Msk;
}
static inline void ssp_write(spi_t *obj, int value)
{
obj->spi->DR = value;
while (ssp_writeable(obj));
}
static inline int ssp_read(spi_t *obj)
{
int read_DR = obj->spi->DR;
return read_DR;
}
static inline int ssp_busy(spi_t *obj)
{
return (obj->spi->SR & (1 << 4)) ? (1) : (0);
}
int spi_master_write(spi_t *obj, int value)
{
ssp_write(obj, value);
while (obj->spi->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */
return (ssp_read(obj));
}
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
char *rx_buffer, int rx_length)
{
int total = (tx_length > rx_length) ? tx_length : rx_length;
char out, in;
for (int i = 0; i < total; i++) {
out = (i < tx_length) ? tx_buffer[i] : 0xff;
in = spi_master_write(obj, out);
if (i < rx_length) {
rx_buffer[i] = in;
}
}
return total;
}
int spi_slave_receive(spi_t *obj)
{
return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
}
int spi_slave_read(spi_t *obj)
{
return obj->spi->DR;
}
void spi_slave_write(spi_t *obj, int value)
{
while (ssp_writeable(obj) == 0);
obj->spi->DR = value;
}
int spi_busy(spi_t *obj)
{
return ssp_busy(obj);
}

174
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/spi_def.h Normal file
View File

@ -0,0 +1,174 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* ----------------------------------------------------------------
* File: spi_def.h
* Release: Version 2.0
* ----------------------------------------------------------------
*
* SSP interface Support
* =====================
*/
#define SSPCS_BASE (0x4002804C) // SSP chip select register
#define SSP_BASE (0x40020000) // SSP Prime Cell
#define SSPCR0 ((volatile unsigned int *)(SSP_BASE + 0x00))
#define SSPCR1 ((volatile unsigned int *)(SSP_BASE + 0x04))
#define SSPDR ((volatile unsigned int *)(SSP_BASE + 0x08))
#define SSPSR ((volatile unsigned int *)(SSP_BASE + 0x0C))
#define SSPCPSR ((volatile unsigned int *)(SSP_BASE + 0x10))
#define SSPIMSC ((volatile unsigned int *)(SSP_BASE + 0x14))
#define SSPRIS ((volatile unsigned int *)(SSP_BASE + 0x18))
#define SSPMIS ((volatile unsigned int *)(SSP_BASE + 0x1C))
#define SSPICR ((volatile unsigned int *)(SSP_BASE + 0x20))
#define SSPDMACR ((volatile unsigned int *)(SSP_BASE + 0x24))
#define SSPCS ((volatile unsigned int *)(SSPCS_BASE))
// SSPCR0 Control register 0
#define SSPCR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
#define SSPCR0_SPH 0x0080 // SSPCLKOUT phase
#define SSPCR0_SPO 0x0040 // SSPCLKOUT polarity
#define SSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
#define SSPCR0_DSS_8 0x0007 // Data packet size, 8bits
#define SSPCR0_DSS_16 0x000F // Data packet size, 16bits
// SSPCR1 Control register 1
#define SSPCR1_SOD 0x0008 // Slave Output mode Disable
#define SSPCR1_MS 0x0004 // Master or Slave mode
#define SSPCR1_SSE 0x0002 // Serial port enable
#define SSPCR1_LBM 0x0001 // Loop Back Mode
// SSPSR Status register
#define SSPSR_BSY 0x0010 // Busy
#define SSPSR_RFF 0x0008 // Receive FIFO full
#define SSPSR_RNE 0x0004 // Receive FIFO not empty
#define SSPSR_TNF 0x0002 // Transmit FIFO not full
#define SSPSR_TFE 0x0001 // Transmit FIFO empty
// SSPCPSR Clock prescale register
#define SSPCPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
// SSPIMSC Interrupt mask set and clear register
#define SSPIMSC_TXIM 0x0008 // Transmit FIFO not Masked
#define SSPIMSC_RXIM 0x0004 // Receive FIFO not Masked
#define SSPIMSC_RTIM 0x0002 // Receive timeout not Masked
#define SSPIMSC_RORIM 0x0001 // Receive overrun not Masked
// SSPRIS Raw interrupt status register
#define SSPRIS_TXRIS 0x0008 // Raw Transmit interrupt flag
#define SSPRIS_RXRIS 0x0004 // Raw Receive interrupt flag
#define SSPRIS_RTRIS 0x0002 // Raw Timemout interrupt flag
#define SSPRIS_RORRIS 0x0001 // Raw Overrun interrupt flag
// SSPMIS Masked interrupt status register
#define SSPMIS_TXMIS 0x0008 // Masked Transmit interrupt flag
#define SSPMIS_RXMIS 0x0004 // Masked Receive interrupt flag
#define SSPMIS_RTMIS 0x0002 // Masked Timemout interrupt flag
#define SSPMIS_RORMIS 0x0001 // Masked Overrun interrupt flag
// SSPICR Interrupt clear register
#define SSPICR_RTIC 0x0002 // Clears Timeout interrupt flag
#define SSPICR_RORIC 0x0001 // Clears Overrun interrupt flag
// SSPDMACR DMA control register
#define SSPDMACR_TXDMAE 0x0002 // Enable Transmit FIFO DMA
#define SSPDMACR_RXDMAE 0x0001 // Enable Receive FIFO DMA
// SPICS register (0=Chip Select low)
#define SSPCS_nCS1 0x0002 // nCS1 (SPI_nSS)
// SPI defaults
#define SSPMAXTIME 1000 // Maximum time to wait for SSP (10*10uS)
// EEPROM instruction set
#define EEWRSR 0x0001 // Write status
#define EEWRITE 0x0002 // Write data
#define EEREAD 0x0003 // Read data
#define EEWDI 0x0004 // Write disable
#define EEWREN 0x0006 // Write enable
#define EERDSR 0x0005 // Read status
// EEPROM status register flags
#define EERDSR_WIP 0x0001 // Write in process
#define EERDSR_WEL 0x0002 // Write enable latch
#define EERDSR_BP0 0x0004 // Block protect 0
#define EERDSR_BP1 0x0008 // Block protect 1
#define EERDSR_WPEN 0x0080 // Write protect enable
/* ----------------------------------------------------------------
*
* Color LCD Support
* =================
*/
// Color LCD Controller Internal Register addresses
#define LSSPCS_BASE (0x4002804C) // LSSP chip select register
#define LSSP_BASE (0x40021000) // LSSP Prime Cell
#define LSSPCR0 ((volatile unsigned int *)(LSSP_BASE + 0x00))
#define LSSPCR1 ((volatile unsigned int *)(LSSP_BASE + 0x04))
#define LSSPDR ((volatile unsigned int *)(LSSP_BASE + 0x08))
#define LSSPSR ((volatile unsigned int *)(LSSP_BASE + 0x0C))
#define LSSPCPSR ((volatile unsigned int *)(LSSP_BASE + 0x10))
#define LSSPIMSC ((volatile unsigned int *)(LSSP_BASE + 0x14))
#define LSSPRIS ((volatile unsigned int *)(LSSP_BASE + 0x18))
#define LSSPMIS ((volatile unsigned int *)(LSSP_BASE + 0x1C))
#define LSSPICR ((volatile unsigned int *)(LSSP_BASE + 0x20))
#define LSSPDMACR ((volatile unsigned int *)(LSSP_BASE + 0x24))
#define LSSPCS ((volatile unsigned int *)(LSSPCS_BASE))
// LSSPCR0 Control register 0
#define LSSPCR0_SCR_DFLT 0x0100 // Serial Clock Rate (divide), CLK/(CPSR*(1+SCR))
#define LSSPCR0_SPH 0x0080 // LSSPCLKOUT phase
#define LSSPCR0_SPO 0x0040 // LSSPCLKOUT polarity
#define LSSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
#define LSSPCR0_DSS_8 0x0007 // Data packet size, 8bits
#define LSSPCR0_DSS_16 0x000F // Data packet size, 16bits
// LSSPCR1 Control register 1
#define LSSPCR1_SOD 0x0008 // Slave Output mode Disable
#define LSSPCR1_MS 0x0004 // Master or Slave mode
#define LSSPCR1_SSE 0x0002 // Serial port enable
#define LSSPCR1_LBM 0x0001 // Loop Back Mode
// LSSPSR Status register
#define LSSPSR_BSY 0x0010 // Busy
#define LSSPSR_RFF 0x0008 // Receive FIFO full
#define LSSPSR_RNE 0x0004 // Receive FIFO not empty
#define LSSPSR_TNF 0x0002 // Transmit FIFO not full
#define LSSPSR_TFE 0x0001 // Transmit FIFO empty
// LSSPCPSR Clock prescale register
#define LSSPCPSR_DFLT 0x0002 // Clock prescale (use with SCR)
// SPICS register
#define LSSPCS_nCS0 0x0001 // nCS0 (CLCD_CS)
#define LSSPCS_nCS2 0x0004 // nCS2 (CLCD_T_CS)
#define LCD_RESET 0x0008 // RESET (CLCD_RESET)
#define LCD_RS 0x0010 // RS (CLCD_RS)
#define LCD_RD 0x0020 // RD (CLCD_RD)
#define LCD_BL 0x0040 // Backlight (CLCD_BL_CTRL)
// SPI defaults
#define LSSPMAXTIME 10000 // Maximum time to wait for LSSP (10*10uS)
#define LSPI_START (0x70) // Start byte for SPI transfer
#define LSPI_RD (0x01) // WR bit 1 within start
#define LSPI_WR (0x00) // WR bit 0 within start
#define LSPI_DATA (0x02) // RS bit 1 within start byte
#define LSPI_INDEX (0x00) // RS bit 0 within start byte
// Screen size
#define LCD_WIDTH 320 // Screen Width (in pixels)
#define LCD_HEIGHT 240 // Screen Height (in pixels)

137
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/us_ticker.c Normal file
View File

@ -0,0 +1,137 @@
/* mbed Microcontroller Library
* Copyright (c) 2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* This file is derivative of us_ticker.c from BEETLE */
#include <stddef.h>
#include "cmsis.h"
#include "us_ticker_api.h"
#include "PeripheralNames.h"
#define TIMER_MAX_VALUE 0
/* Private data */
struct us_ticker_drv_data_t {
uint32_t inited; /* us ticker initialized */
uint32_t overflow_delta; /* us ticker overflow */
uint32_t overflow_limit; /* us ticker overflow limit */
};
static struct us_ticker_drv_data_t us_ticker_drv_data = {
.inited = 0,
.overflow_delta = 0,
.overflow_limit = 0
};
void __us_ticker_irq_handler(void)
{
Timer_ClearInterrupt(TIMER1);
/*
* For each overflow event adds the timer max represented value to
* the delta. This allows the us_ticker to keep track of the elapsed
* time:
* elapsed_time = (num_overflow * overflow_limit) + current_time
*/
us_ticker_drv_data.overflow_delta += us_ticker_drv_data.overflow_limit;
}
void us_ticker_init(void)
{
uint32_t us_ticker_irqn0 = 0;
uint32_t us_ticker_irqn1 = 0;
if (us_ticker_drv_data.inited) {
return;
}
us_ticker_drv_data.inited = 1;
/* Initialize Timer 0 */
Timer_Initialize(TIMER0, TIMER_MAX_VALUE);
/* Enable Timer 0 */
Timer_Enable(TIMER0);
/* Initialize Timer 1 */
Timer_Initialize(TIMER1, TIMER_MAX_VALUE);
/* Enable Timer 1 */
Timer_Enable(TIMER1);
/* Timer 0 get IRQn */
us_ticker_irqn0 = Timer_GetIRQn(TIMER0);
NVIC_SetVector((IRQn_Type)us_ticker_irqn0, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ((IRQn_Type)us_ticker_irqn0);
/* Timer 1 get IRQn */
us_ticker_irqn1 = Timer_GetIRQn(TIMER1);
NVIC_SetVector((IRQn_Type)us_ticker_irqn1, (uint32_t)__us_ticker_irq_handler);
NVIC_EnableIRQ((IRQn_Type)us_ticker_irqn1);
/* Timer set interrupt on TIMER1 */
Timer_SetInterrupt(TIMER1, TIMER_DEFAULT_RELOAD);
/*
* Set us_ticker Overflow limit. The us_ticker overflow limit is required
* to calculated the return value of the us_ticker read function in us
* on 32bit.
* A 32bit us value cannot be represented directly in the Timer Load
* register if it is greater than (0xFFFFFFFF ticks)/TIMER_DIVIDER_US.
*/
us_ticker_drv_data.overflow_limit = Timer_GetReloadValue(TIMER1);
}
uint32_t us_ticker_read()
{
uint32_t return_value = 0;
if (!us_ticker_drv_data.inited) {
us_ticker_init();
}
return_value = us_ticker_drv_data.overflow_delta + Timer_Read(TIMER1);
return return_value;
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
int32_t delta = 0;
if (!us_ticker_drv_data.inited) {
us_ticker_init();
}
delta = (int32_t)(timestamp - us_ticker_read());
/* Check if the event was in the past */
if (delta <= 0) {
/* This event was in the past */
Timer_SetInterrupt(TIMER0, 0);
} else {
/* If the event was not in the past enable interrupt */
Timer_SetInterrupt(TIMER0, delta);
}
}
void us_ticker_disable_interrupt(void)
{
Timer_DisableInterrupt(TIMER0);
}
void us_ticker_clear_interrupt(void)
{
Timer_ClearInterrupt(TIMER0);
}

4
targets/TARGET_ARM_SSG/mbed_rtx.h
View File

@ -1,5 +1,5 @@
/* mbed Microcontroller Library
* Copyright (c) 2016 ARM Limited
* Copyright (c) 2016-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@ -17,7 +17,7 @@
#ifndef MBED_MBED_RTX_H
#define MBED_MBED_RTX_H
#if defined(TARGET_BEETLE)
#if defined(TARGET_BEETLE) || defined(TARGET_CM3DS_MPS2)
#ifndef INITIAL_SP
#define INITIAL_SP (0x20020000UL)

9
targets/targets.json
View File

@ -1943,6 +1943,15 @@
"macros": ["CMSDK_BEID"],
"device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
"release_versions": ["2"]
},
"ARM_CM3DS_MPS2": {
"inherits": ["ARM_IOTSS_Target"],
"core": "Cortex-M3",
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"extra_labels": ["ARM_SSG", "CM3DS_MPS2"],
"macros": ["CMSDK_CM3DS"],
"device_has": ["ETHERNET","INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI", "RTC"],
"release_versions": ["2", "5"]
},
"ARM_BEETLE_SOC": {
"inherits": ["ARM_IOTSS_Target"],